diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 1d9ecb6c2..6fd736846 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -254,19 +254,22 @@ function legalize_mstatus(o : Mstatus, v : xlenbits) -> Mstatus = {
    * but only if Zfinx isn't enabled.
    * FIXME: This should be made a platform parameter.
    */
-  let dirty = extStatus_of_bits(m[FS]) == Dirty | extStatus_of_bits(m[XS]) == Dirty |
-              extStatus_of_bits(m[VS]) == Dirty;
-
-  /* Legalize MPP */
   let m = [m with
+    /* Legalize MPP */
     MPP = if have_privLevel(m[MPP]) then m[MPP] else privLevel_to_bits(lowest_supported_privLevel()),
     /* We don't have any extension context yet. */
     XS = extStatus_to_bits(Off),
-    SD = bool_to_bits(dirty),
     FS = if sys_enable_zfinx() then extStatus_to_bits(Off) else m[FS],
     MPRV = if extensionEnabled(Ext_U) then m[MPRV] else 0b0,
   ];
 
+  // Set dirty bit to OR of other status bits.
+  let m = [m with
+    SD = bool_to_bits(extStatus_of_bits(m[FS]) == Dirty |
+                      extStatus_of_bits(m[XS]) == Dirty |
+                      extStatus_of_bits(m[VS]) == Dirty),
+  ];
+
   /* We don't support dynamic changes to SXL and UXL. */
   let m = set_mstatus_SXL(m, get_mstatus_SXL(o));
   let m = set_mstatus_UXL(m, get_mstatus_UXL(o));