diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 5a70db00d..661974fc4 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -836,16 +836,24 @@ bitfield SEnvcfg : xlenbits = {
 
 function legalize_menvcfg(o : MEnvcfg, v : bits(64)) -> MEnvcfg = {
   let v = Mk_MEnvcfg(v);
-  let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0];
-  // Other extensions are not implemented yet so all other fields are read only zero.
-  o
+  [o with
+    FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0,
+    CBZE = v[CBZE],
+    CBCFE = v[CBCFE],
+    CBIE = if v[CBIE] != 0b10 then v[CBIE] else 0b00,
+    // Other extensions are not implemented yet so all other fields are read only zero.
+  ]
 }
 
 function legalize_senvcfg(o : SEnvcfg, v : xlenbits) -> SEnvcfg = {
   let v = Mk_SEnvcfg(v);
-  let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0];
-  // Other extensions are not implemented yet so all other fields are read only zero.
-  o
+  [o with
+    FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0,
+    CBZE = v[CBZE],
+    CBCFE = v[CBCFE],
+    CBIE = if v[CBIE] != 0b10 then v[CBIE] else 0b00,
+    // Other extensions are not implemented yet so all other fields are read only zero.
+  ]
 }
 
 register menvcfg : MEnvcfg