-
Notifications
You must be signed in to change notification settings - Fork 0
/
counter-ram.qsf
108 lines (106 loc) · 6.16 KB
/
counter-ram.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 23:53:44 November 20, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# counter-ram_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY counterram
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:53:44 NOVEMBER 20, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_FILE counterram.vhd
set_global_assignment -name VHDL_FILE debounce.vhd
set_global_assignment -name VHDL_FILE segment.vhd
set_global_assignment -name VHDL_FILE multisegment.vhd
set_global_assignment -name VHDL_FILE counter.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH segment_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME segment_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id segment_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME segment_tb -section_id segment_tb
set_global_assignment -name EDA_TEST_BENCH_FILE segment_tb.vhd -section_id segment_tb -hdl_version VHDL_2008
set_location_assignment PIN_R8 -to clk
set_location_assignment PIN_E1 -to next_address
set_location_assignment PIN_J15 -to previous_address
set_location_assignment PIN_A15 -to o_bin_led[0]
set_location_assignment PIN_L3 -to o_bin_led[7]
set_location_assignment PIN_B1 -to o_bin_led[6]
set_location_assignment PIN_F3 -to o_bin_led[5]
set_location_assignment PIN_D1 -to o_bin_led[4]
set_location_assignment PIN_A11 -to o_bin_led[3]
set_location_assignment PIN_B13 -to o_bin_led[2]
set_location_assignment PIN_A13 -to o_bin_led[1]
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VHDL_FILE segment_pkg.vhd
set_global_assignment -name QIP_FILE pll_clk_16mhz.qip
set_location_assignment PIN_T10 -to o_hex_addr_out.o_bcd[6]
set_location_assignment PIN_P11 -to o_hex_addr_out.o_bcd[5]
set_location_assignment PIN_N12 -to o_hex_addr_out.o_bcd[4]
set_location_assignment PIN_N9 -to o_hex_addr_out.o_bcd[3]
set_location_assignment PIN_R16 -to o_hex_addr_out.o_bcd[1]
set_location_assignment PIN_L16 -to o_hex_addr_out.o_bcd[2]
set_location_assignment PIN_P15 -to o_hex_addr_out.o_bcd[0]
set_location_assignment PIN_R14 -to o_hex_addr_out.ds[0]
set_location_assignment PIN_R11 -to o_hex_addr_out.ds[1]
set_location_assignment PIN_R10 -to o_hex_addr_out.ds[2]
set_location_assignment PIN_P9 -to o_hex_addr_out.ds[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.ds[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.ds[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.ds[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.ds[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.o_bcd[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.o_bcd[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.o_bcd[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.o_bcd[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.o_bcd[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.o_bcd[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to o_hex_addr_out.o_bcd[0]
set_global_assignment -name VHDL_FILE sdram.vhd
set_global_assignment -name VHDL_FILE sdram_pkg.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top