From 9d1eb8376dc14fac67e5aeabc13aa7ac3302c55c Mon Sep 17 00:00:00 2001
From: bi262934 <bi262934@gre069627>
Date: Mon, 4 Mar 2024 18:23:32 +0100
Subject: [PATCH] Fix wrong mask for 64 bits IO access

---
 src/main/scala/naxriscv/platform/NaxriscvProbe.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/naxriscv/platform/NaxriscvProbe.scala b/src/main/scala/naxriscv/platform/NaxriscvProbe.scala
index 50dc4fd..440af0a 100644
--- a/src/main/scala/naxriscv/platform/NaxriscvProbe.scala
+++ b/src/main/scala/naxriscv/platform/NaxriscvProbe.scala
@@ -263,8 +263,8 @@ class NaxriscvProbe(nax : NaxRiscv, hartId : Int){
       ioAccess.error = ioBus.rsp.error.toBoolean
       if(!ioAccess.write) {
         val offset = (ioAccess.address) & (ioBus.p.dataWidth/8-1)
-        val mask = (1l << ioAccess.size*8)-1
-        ioAccess.data = (ioBus.rsp.data.toLong >> offset*8) & mask
+        val mask = (BigInt(1) << ioAccess.size*8)-1
+        ioAccess.data = (ioBus.rsp.data.toLong >> offset*8) & mask.toLong
       }
       backends.foreach(_.ioAccess(hartId, ioAccess))
       ioAccess = null