diff --git a/Core/SNES/Spc.Instructions.cpp b/Core/SNES/Spc.Instructions.cpp
index 294b43bd..37aa2598 100644
--- a/Core/SNES/Spc.Instructions.cpp
+++ b/Core/SNES/Spc.Instructions.cpp
@@ -15,7 +15,8 @@ void Spc::Run()
 		return;
 	}
 
-	uint64_t targetCycle = (uint64_t)(_memoryManager->GetMasterClock() * _clockRatio);
+	//Minus 1 because each call to ProcessCycle increments _state.Cycle by 2
+	uint64_t targetCycle = (uint64_t)(_memoryManager->GetMasterClock() * _clockRatio) - 1;
 	while(_state.Cycle < targetCycle) {
 		ProcessCycle();
 	}
diff --git a/Core/SNES/Spc.cpp b/Core/SNES/Spc.cpp
index c1c830a6..efeac453 100644
--- a/Core/SNES/Spc.cpp
+++ b/Core/SNES/Spc.cpp
@@ -357,7 +357,18 @@ void Spc::CpuWriteRegister(uint32_t addr, uint8_t value)
 	Run();
 	if(_state.NewCpuRegs[addr & 0x03] != value) {
 		_state.NewCpuRegs[addr & 0x03] = value;
-		_pendingCpuRegUpdate = true;
+
+		//If the CPU's write lands in the first half of the SPC cycle (each cycle is 2 clocks) then the SPC 
+		//can see the new value immediately, otherwise it only sees the new value on the following cycle.
+		//The delay is needed for Kishin Kishin Douji Zenki to boot.
+		//However, always delaying to the next SPC cycle causes Kawasaki Superbike Challenge to freeze on boot.
+		//Delaying only when the write occurs in the SPC cycle's second half allows both games to work (at the default 32040hz.)
+		//This solution behaves as if the CPU values were latched/updated every 2mhz tick (which matches the SPC's input clock)
+		if(_memoryManager->GetMasterClock() * _clockRatio - _state.Cycle <= 1) {
+			_state.CpuRegs[addr & 0x03] = value;
+		} else {
+			_pendingCpuRegUpdate = true;
+		}
 	}
 }