diff --git a/bin/dap.bat b/bin/dap.bat
new file mode 100644
index 0000000..c72979e
--- /dev/null
+++ b/bin/dap.bat
@@ -0,0 +1,2 @@
+cd /d E:\software\RT-ThreadStudio\repo\Extract\Debugger_Support_Packages\openocd\bin
+pyocd.exe flash --target=cy8c64xA_cm4 --erase=auto --frequency=12000000 E:\workspace_work\rt-thread\bsp\cypress\psoc6-cy8cproto-4343w\dist_ide_project\Debug\rtthread.hex
\ No newline at end of file
diff --git a/bin/libusb-1.0.dll b/bin/libusb-1.0.dll
new file mode 100644
index 0000000..c25ff3d
Binary files /dev/null and b/bin/libusb-1.0.dll differ
diff --git a/bin/libwinpthread-1.dll b/bin/libwinpthread-1.dll
new file mode 100644
index 0000000..d555a2f
Binary files /dev/null and b/bin/libwinpthread-1.dll differ
diff --git a/bin/openocd.exe b/bin/openocd.exe
new file mode 100644
index 0000000..c1560e2
Binary files /dev/null and b/bin/openocd.exe differ
diff --git a/docs/Cypress OpenOCD CLI User Guide.pdf b/docs/Cypress OpenOCD CLI User Guide.pdf
new file mode 100644
index 0000000..9d11df9
Binary files /dev/null and b/docs/Cypress OpenOCD CLI User Guide.pdf differ
diff --git a/docs/third_party_licenses/MinGW-w64-GCC-license.txt b/docs/third_party_licenses/MinGW-w64-GCC-license.txt
new file mode 100644
index 0000000..e1b3c69
--- /dev/null
+++ b/docs/third_party_licenses/MinGW-w64-GCC-license.txt
@@ -0,0 +1,73 @@
+GCC RUNTIME LIBRARY EXCEPTION
+
+Version 3.1, 31 March 2009
+
+Copyright (C) 2009 Free Software Foundation, Inc.
+
+Everyone is permitted to copy and distribute verbatim copies of this
+license document, but changing it is not allowed.
+
+This GCC Runtime Library Exception ("Exception") is an additional
+permission under section 7 of the GNU General Public License, version
+3 ("GPLv3"). It applies to a given file (the "Runtime Library") that
+bears a notice placed by the copyright holder of the file stating that
+the file is governed by GPLv3 along with this Exception.
+
+When you use GCC to compile a program, GCC may combine portions of
+certain GCC header files and runtime libraries with the compiled
+program. The purpose of this Exception is to allow compilation of
+non-GPL (including proprietary) programs to use, in this way, the
+header files and runtime libraries covered by this Exception.
+
+0. Definitions.
+
+A file is an "Independent Module" if it either requires the Runtime
+Library for execution after a Compilation Process, or makes use of an
+interface provided by the Runtime Library, but is not otherwise based
+on the Runtime Library.
+
+"GCC" means a version of the GNU Compiler Collection, with or without
+modifications, governed by version 3 (or a specified later version) of
+the GNU General Public License (GPL) with the option of using any
+subsequent versions published by the FSF.
+
+"GPL-compatible Software" is software whose conditions of propagation,
+modification and use would permit combination with GCC in accord with
+the license of GCC.
+
+"Target Code" refers to output from any compiler for a real or virtual
+target processor architecture, in executable form or suitable for
+input to an assembler, loader, linker and/or execution
+phase. Notwithstanding that, Target Code does not include data in any
+format that is used as a compiler intermediate representation, or used
+for producing a compiler intermediate representation.
+
+The "Compilation Process" transforms code entirely represented in
+non-intermediate languages designed for human-written code, and/or in
+Java Virtual Machine byte code, into Target Code. Thus, for example,
+use of source code generators and preprocessors need not be considered
+part of the Compilation Process, since the Compilation Process can be
+understood as starting with the output of the generators or
+preprocessors.
+
+A Compilation Process is "Eligible" if it is done using GCC, alone or
+with other GPL-compatible software, or if it is done without using any
+work based on GCC. For example, using non-GPL-compatible Software to
+optimize any GCC intermediate representations would not qualify as an
+Eligible Compilation Process.
+
+1. Grant of Additional Permission.
+
+You have permission to propagate a work of Target Code formed by
+combining the Runtime Library with Independent Modules, even if such
+propagation would otherwise violate the terms of GPLv3, provided that
+all Target Code was generated by Eligible Compilation Processes. You
+may then convey such a combination under terms of your choice,
+consistent with the licensing of the Independent Modules.
+
+2. No Weakening of GCC Copyleft.
+
+The availability of this Exception does not imply any general
+presumption that third-party software is unaffected by the copyleft
+requirements of the license of GCC.
+
diff --git a/docs/third_party_licenses/MinGW-w64-winpthread-git-license.txt b/docs/third_party_licenses/MinGW-w64-winpthread-git-license.txt
new file mode 100644
index 0000000..3507701
--- /dev/null
+++ b/docs/third_party_licenses/MinGW-w64-winpthread-git-license.txt
@@ -0,0 +1,57 @@
+Copyright (c) 2011 mingw-w64 project
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+
+
+/*
+ * Parts of this library are derived by:
+ *
+ * Posix Threads library for Microsoft Windows
+ *
+ * Use at own risk, there is no implied warranty to this code.
+ * It uses undocumented features of Microsoft Windows that can change
+ * at any time in the future.
+ *
+ * (C) 2010 Lockless Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * * Neither the name of Lockless Inc. nor the names of its contributors may be
+ * used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AN
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
diff --git a/docs/third_party_licenses/OpenOCD-license.txt b/docs/third_party_licenses/OpenOCD-license.txt
new file mode 100644
index 0000000..d159169
--- /dev/null
+++ b/docs/third_party_licenses/OpenOCD-license.txt
@@ -0,0 +1,339 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Lesser General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+ Finally, any free program is threatened constantly by software
+patents. We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary. To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License. The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language. (Hereinafter, translation is included without limitation in
+the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+ 1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+ 2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
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+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
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+operating system on which the executable runs, unless that component
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+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
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+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) year name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ , 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.
diff --git a/docs/third_party_licenses/hidapi-license-orig.txt b/docs/third_party_licenses/hidapi-license-orig.txt
new file mode 100644
index 0000000..e3f3380
--- /dev/null
+++ b/docs/third_party_licenses/hidapi-license-orig.txt
@@ -0,0 +1,9 @@
+ HIDAPI - Multi-Platform library for
+ communication with HID devices.
+
+ Copyright 2009, Alan Ott, Signal 11 Software.
+ All Rights Reserved.
+
+ This software may be used by anyone for any reason so
+ long as the copyright notice in the source files
+ remains intact.
diff --git a/docs/third_party_licenses/libusb-license.txt b/docs/third_party_licenses/libusb-license.txt
new file mode 100644
index 0000000..f166cc5
--- /dev/null
+++ b/docs/third_party_licenses/libusb-license.txt
@@ -0,0 +1,502 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+ This license, the Lesser General Public License, applies to some
+specially designated software packages--typically libraries--of the
+Free Software Foundation and other authors who decide to use it. You
+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
+strategy to use in any particular case, based on the explanations below.
+
+ When we speak of free software, we are referring to freedom of use,
+not price. Our General Public Licenses are designed to make sure that
+you have the freedom to distribute copies of free software (and charge
+for this service if you wish); that you receive source code or can get
+it if you want it; that you can change the software and use pieces of
+it in new free programs; and that you are informed that you can do
+these things.
+
+ To protect your rights, we need to make restrictions that forbid
+distributors to deny you these rights or to ask you to surrender these
+rights. These restrictions translate to certain responsibilities for
+you if you distribute copies of the library or if you modify it.
+
+ For example, if you distribute copies of the library, whether gratis
+or for a fee, you must give the recipients all the rights that we gave
+you. You must make sure that they, too, receive or can get the source
+code. If you link other code with the library, you must provide
+complete object files to the recipients, so that they can relink them
+with the library after making changes to the library and recompiling
+it. And you must show them these terms so they know their rights.
+
+ We protect your rights with a two-step method: (1) we copyright the
+library, and (2) we offer you this license, which gives you legal
+permission to copy, distribute and/or modify the library.
+
+ To protect each distributor, we want to make it very clear that
+there is no warranty for the free library. Also, if the library is
+modified by someone else and passed on, the recipients should know
+that what they have is not the original version, so that the original
+author's reputation will not be affected by problems that might be
+introduced by others.
+
+ Finally, software patents pose a constant threat to the existence of
+any free program. We wish to make sure that a company cannot
+effectively restrict the users of a free program by obtaining a
+restrictive license from a patent holder. Therefore, we insist that
+any patent license obtained for a version of the library must be
+consistent with the full freedom of use specified in this license.
+
+ Most GNU software, including some libraries, is covered by the
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\ No newline at end of file
diff --git a/flm/cypress/Apache_License.txt b/flm/cypress/Apache_License.txt
new file mode 100644
index 0000000..d0381d6
--- /dev/null
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@@ -0,0 +1,176 @@
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+ License. However, in accepting such obligations, You may act only
+ on Your own behalf and on Your sole responsibility, not on behalf
+ of any other Contributor, and only if You agree to indemnify,
+ defend, and hold each Contributor harmless for any liability
+ incurred by, or claims asserted against, such Contributor by reason
+ of your accepting any such warranty or additional liability.
+
+ END OF TERMS AND CONDITIONS
diff --git a/flm/cypress/cat1a/CY8C6xxA_SMIF.FLM b/flm/cypress/cat1a/CY8C6xxA_SMIF.FLM
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diff --git a/flm/cypress/cat1a/version.txt b/flm/cypress/cat1a/version.txt
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index 0000000..07bd552
--- /dev/null
+++ b/flm/cypress/cat1a/version.txt
@@ -0,0 +1 @@
+4.1.0.507
diff --git a/flm/cypress/cat1b/CYW208xx_SMIF.FLM b/flm/cypress/cat1b/CYW208xx_SMIF.FLM
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diff --git a/flm/cypress/cat1b/version.txt b/flm/cypress/cat1b/version.txt
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index 0000000..61e5569
--- /dev/null
+++ b/flm/cypress/cat1b/version.txt
@@ -0,0 +1 @@
+1.0.0.116
diff --git a/flm/cypress/cat4/sflash_write.tcl b/flm/cypress/cat4/sflash_write.tcl
new file mode 100644
index 0000000..b0fad3f
--- /dev/null
+++ b/flm/cypress/cat4/sflash_write.tcl
@@ -0,0 +1,406 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+
+###############################################################################
+#
+# sflash_write.tcl
+#
+# This TCL OpenOCD script runs on a PC and communicates with the embedded
+# sflash_write app to allow the PC to write data into a serial flash chip
+# attached to the target processor
+#
+# Usage example:
+#
+# source [find mfg_spi_flash/write_sflash.tcl]
+# sflash_init "BCMUSI11-SDIO-debug"
+# sflash_write_file "example.bin" 0x10 "BCMUSI11-SDIO-debug" 1
+# shutdown
+#
+###############################################################################
+
+# CHIP_RAM_START must be supplied by target specific TCL script
+set MemoryStart $CHIP_RAM_START
+
+###############################################################################
+#
+# These variables must match the ones in Apps/waf/sflash_write/sflash_write.c
+#
+# They rely on the linker script placing the data_config_area_t and
+# data_transfer_area_t structures at the start of RAM
+#
+###############################################################################
+
+# This must match data_config_area_t
+set entry_address_loc [expr $MemoryStart + 0x00 ]
+set stack_address_loc [expr $MemoryStart + 0x04 ]
+set buffer_size_loc [expr $MemoryStart + 0x08 ]
+
+# This must match data_transfer_area_t
+set data_size_loc [expr $MemoryStart + 0x0C ]
+set dest_address_loc [expr $MemoryStart + 0x10 ]
+set command_loc [expr $MemoryStart + 0x14 ]
+set result_loc [expr $MemoryStart + 0x18 ]
+set data_loc [expr $MemoryStart + 0x1C ]
+
+
+# These must match the MFG_SPI_FLASH_COMMAND defines
+set COMMAND_INITIAL_VERIFY (0x01)
+set COMMAND_ERASE (0x02)
+set COMMAND_WRITE (0x04)
+set COMMAND_POST_WRITE_VERIFY (0x08)
+set COMMAND_VERIFY_CHIP_ERASURE (0x10)
+set COMMAND_WRITE_DCT (0x20)
+set COMMAND_READ (0x40)
+set COMMAND_WRITE_ERASE_IF_NEEDED (0x80)
+
+# These must match the mfg_spi_flash_result_t enum
+set RESULT(0xffffffff) "In Progress"
+set RESULT(4294967295) "In Progress"
+set RESULT(0) "OK"
+set RESULT(1) "Erase Failed"
+set RESULT(2) "Verify after write failed"
+set RESULT(3) "Size too big for buffer"
+set RESULT(4) "Size too big for chip"
+set RESULT(5) "DCT location not found - has factory reset app been written?"
+set RESULT(6) "Error during Write"
+set RESULT(7) "Error during Read"
+
+# For handling big single file
+set MAX_SINGLE_FILE_SIZE "4194304"
+
+###############################################################################
+# memread32
+#
+# Helper function that reads a 32 bit value from RAM and returns it
+#
+# address - the RAM address to read from
+###############################################################################
+proc memread32 {address resume_required} {
+ if { $resume_required == 1 } {
+ halt
+ }
+ mem2array memar 32 $address 1
+ if { $resume_required == 1} {
+ resume
+ }
+ return $memar(0)
+}
+
+###############################################################################
+# load_image_bin
+#
+# Loads part of a binary file into RAM
+#
+# fname - filename of binary image file
+# foffset - offset from the start of the binary file where data will be read
+# address - the destination RAM address
+# length - number of bytes to transfer
+###############################################################################
+proc load_image_bin {fname foffset address length } {
+ # Load data from fname filename at foffset offset to
+ # target at address. Load at most length bytes.
+ puts "loadimage address $address foffset $foffset $length"
+ load_image $fname [expr $address - $foffset] bin $address $length
+}
+
+
+proc target_not_supported {} {
+ puts stderr "Target is not currently supported by sflash_write.tcl"
+ shutdown
+}
+
+proc post_init_43909_setup { } {
+ reset init
+ cortex_r4 maskisr on
+
+ # Go to Supervisor ARM mode
+ reg cpsr 0xd3
+ reg lr 0x0
+}
+
+proc post_init_psoc6_setup { } {
+ reset init
+ psoc6 reset_halt sysresetreq
+
+ # Switch to cm4 since that is target for sflash_write
+ targets psoc6.cpu.cm4
+}
+
+###############################################################################
+# sflash_init
+#
+# Prepares for writing to serial flashby loading the sflash_write app into
+# memory and setting it running.
+# This function assumes the following target has already been built:
+# waf.sflash_write-NoOS-
+#
+# PlatBusDebug - The platform, bus and debug part of the build target
+# init4390 - run initialisation for the 4390
+###############################################################################
+proc sflash_init { PlatBusDebug init4390 } {
+ global entry_address_loc
+ global stack_address_loc
+ global buffer_size_loc
+ global entry_address
+ global stack_address
+ global buffer_size
+
+ init
+
+ if { $init4390 == 4390 } {
+ target_not_supported
+ } elseif { $init4390 == 43909 } {
+ post_init_43909_setup
+ } elseif { $init4390 == 6 } {
+ post_init_psoc6_setup
+ }
+
+ load_image $PlatBusDebug
+
+ set entry_address [memread32 $entry_address_loc 0]
+ set stack_address [memread32 $stack_address_loc 0]
+ set buffer_size [memread32 $buffer_size_loc 0]
+
+ puts "entry_address= $entry_address"
+ puts "stack_address= $stack_address"
+ puts "buffer_size= $buffer_size"
+ if { $buffer_size == 0 } {
+ puts "Error: Buffer size read from address $buffer_size_loc on target is zero"
+ exit -1;
+ }
+
+
+ # Setup start address
+ resume $entry_address
+}
+
+
+###############################################################################
+# program_sflash
+#
+# Executes a serial command by communicating to the sflash_write app
+#
+# fname - filename of binary image file (if command requires it)
+# foffset - offset from the start of the binary file where data will be read (if command requires it)
+# dataSize - number of bytes to transfer (if command requires it)
+# destaddr - the destination serial flash address (if command requires it)
+# cmd - The commmand to execute (see list above)
+###############################################################################
+proc program_sflash { filename foffset dataSize destaddr cmd } {
+ global PlatBusDebug MemoryStart data_size_loc data_loc dest_address_loc command_loc result_loc entry_address RESULT entry_address_loc
+
+ halt
+ # Load the binary data into the RAM
+ if { ( $dataSize != 0 ) && ( $filename != "" ) } {
+ load_image_bin $filename $foffset $data_loc $dataSize
+ }
+
+ # Write the details of the data
+ mww $data_size_loc $dataSize
+ mww $dest_address_loc $destaddr
+ mww $result_loc 0xffffffff
+
+ # Write the command - This causes the writing to start
+ mww $command_loc $cmd
+ resume
+
+ set resultval 0xffffffff
+ set loops 0
+ while { ($resultval == 0xffffffff) && ( $loops < 1500 ) } {
+ sleep 100
+ set resultval [memread32 $result_loc 1]
+ incr loops
+ }
+
+ puts "****************** Result: $RESULT($resultval)"
+
+ if { $resultval != 0 } {
+ halt
+ reg
+ exit -1;
+ }
+
+}
+
+
+###############################################################################
+# sflash_write_file
+#
+# Writes an entire binary image file to a serial flash address
+# This function assumes the following target has already been built:
+# waf.sflash_write-NoOS-
+#
+# filename - filename of binary image file
+# destAddress - the destination serial flash address
+# PlatBusDebug - The platform, bus and debug part of the build target
+# erasechip - If 1, Erase the chip before writing.
+# init4390 - run initialisation for the 4390
+###############################################################################
+proc sflash_write_file { filename destAddress PlatBusDebug erasechip init4390 } {
+ global COMMAND_ERASE COMMAND_INITIAL_VERIFY COMMAND_WRITE COMMAND_POST_WRITE_VERIFY buffer_size COMMAND_WRITE_ERASE_IF_NEEDED MAX_SINGLE_FILE_SIZE
+
+ sflash_init $PlatBusDebug $init4390
+
+ set binDataSize [file size $filename]
+ # set erase_command_val [expr $COMMAND_ERASE ]
+ set write_command_val [expr $COMMAND_WRITE_ERASE_IF_NEEDED | $COMMAND_POST_WRITE_VERIFY ]
+ set pos 0
+
+ # if { $erasechip } {
+ # puts "Erasing Chip"
+ # program_sflash $filename $pos 0 $destAddress $erase_command_val
+ # puts "Chip Erase Done"
+ # }
+
+ if { $binDataSize < $MAX_SINGLE_FILE_SIZE } {
+ puts "Total write size is $binDataSize."
+ while { $pos < $binDataSize } {
+ if { ($binDataSize - $pos) < $buffer_size } {
+ set writesize [expr ($binDataSize - $pos)]
+ } else {
+ set writesize $buffer_size
+ }
+ puts "writing $writesize bytes at [expr $destAddress + $pos]"
+ program_sflash $filename $pos $writesize [expr $destAddress + $pos] $write_command_val
+ set pos [expr $pos + $writesize]
+ }
+ } else {
+ puts "The file size was too big ($binDataSize), will split it into small size before write to sflash."
+ set fd_pos 0
+ set tmpfilename_count 0
+
+ ###Read FILE in binary###
+ set fd_binDataSize $binDataSize
+ set fd [open $filename rb]
+ fconfigure $fd -translation binary
+
+ while { $fd_pos < $fd_binDataSize } {
+ if { ($fd_binDataSize - $fd_pos) < $MAX_SINGLE_FILE_SIZE } {
+ set fd_writesize [expr ($fd_binDataSize - $fd_pos)]
+ } else {
+ set fd_writesize $MAX_SINGLE_FILE_SIZE
+ }
+ set data [read $fd $fd_writesize]
+
+ ###Write data to temp file in binary###
+ set tmpfilename $filename\_part\_$tmpfilename_count\.txt
+ set tmp_fd [open $tmpfilename wb]
+ puts -nonewline $tmp_fd $data
+ close $tmp_fd
+
+ ###Write temp file into sflash###
+ puts "Partially, write size is $fd_writesize."
+ set pos 0
+ while { $pos < $fd_writesize } {
+ if { ($fd_writesize - $pos) < $buffer_size } {
+ set writesize [expr ($fd_writesize - $pos)]
+ } else {
+ set writesize $buffer_size
+ }
+ puts "writing $writesize bytes at [expr $destAddress + $pos]"
+ program_sflash $tmpfilename $pos $writesize [expr $destAddress + $pos] $write_command_val
+ set pos [expr $pos + $writesize]
+ }
+
+ file delete $tmpfilename
+ set destAddress [ expr $destAddress + $fd_writesize ]
+ set fd_pos [expr $fd_pos + $fd_writesize]
+ seek $fd $fd_pos
+ set tmpfilename_count [expr $tmpfilename_count + 1]
+ }
+ close $fd
+ }
+}
+
+
+
+###############################################################################
+# sflash_read_file
+#
+# Reads data from a serial flash address
+# This function assumes the following target has already been built:
+# waf.sflash_write-NoOS-
+#
+# filename - output filename for binary image file
+# srcAddress - the destination serial flash address
+# PlatBusDebug - The platform, bus and debug part of the build target
+# length - number of bytes to read
+# init4390 - run initialisation for the 4390
+###############################################################################
+proc sflash_read_file { filename srcAddress PlatBusDebug length init4390 } {
+ global COMMAND_ERASE COMMAND_INITIAL_VERIFY COMMAND_WRITE COMMAND_POST_WRITE_VERIFY buffer_size COMMAND_READ data_loc
+
+ puts ""
+ puts "--> save to $filename"
+ puts "--> SFLASH address $srcAddress"
+ puts "--> length $length"
+ puts ""
+
+ sflash_init $PlatBusDebug $init4390
+ set temp_file "temp.bin"
+
+ # open the output file and set into binary mode
+ set fd_out [open $filename "wb"]
+ fconfigure $fd_out -translation binary
+
+ set read_command_val [expr $COMMAND_READ ]
+ set pos 0
+
+ while { $pos < $length } {
+ if { ($length - $pos) < $buffer_size } {
+ set readsize [expr ($length - $pos)]
+ } else {
+ set readsize $buffer_size
+ }
+
+ puts "reading $readsize bytes from [expr $srcAddress + $pos]"
+ program_sflash "" $pos $readsize [expr $srcAddress + $pos] $read_command_val
+ halt
+ dump_image $temp_file $data_loc $readsize
+
+ set fd_in_size [ file size $temp_file ]
+ puts "temp size: $fd_in_size"
+
+ # get the output file position for reporting
+ set curr_pos [ tell $fd_out ]
+
+ # concatenate temp_file to filename
+ # open temp_file in binary mode and read in the data
+ set fd_in [open $temp_file "rb"]
+ fconfigure $fd_in -translation binary
+ set file_data [read $fd_in ]
+ close $fd_in
+
+ puts -nonewline $fd_out $file_data
+ flush $fd_out
+
+ # get current positioin of output for reporting
+ seek $fd_out 0 end
+ set new_pos [ tell $fd_out ]
+ set written_amount [expr $new_pos - $curr_pos]
+ puts " wrote $written_amount from $curr_pos to $new_pos"
+
+ #update the SFLASH read position
+ set pos [expr $pos + $readsize]
+ }
+ close $fd_out
+
+ file delete $temp_file
+}
+
+
+proc sflash_erase { PlatBusDebug init4390 } {
+ global COMMAND_ERASE COMMAND_INITIAL_VERIFY COMMAND_WRITE COMMAND_POST_WRITE_VERIFY buffer_size COMMAND_WRITE_ERASE_IF_NEEDED
+
+ sflash_init $PlatBusDebug $init4390
+
+ set erase_command_val [expr $COMMAND_ERASE ]
+
+ puts "Erasing Chip"
+ set start_milliseconds [clock milliseconds]
+ program_sflash "" 0 0 0 $erase_command_val
+ set end_milliseconds [clock milliseconds]
+ puts [format "Chip Erase Done (in %d ms)" [expr $end_milliseconds - $start_milliseconds]]
+}
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diff --git a/flm/cypress/traveo2/TV2_8M_SI_B0_DualQuadSPI_320p.elf b/flm/cypress/traveo2/TV2_8M_SI_B0_DualQuadSPI_320p.elf
new file mode 100644
index 0000000..e9bb6a7
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diff --git a/flm/cypress/traveo2/TV2_8M_SI_B0_HyperFlash.elf b/flm/cypress/traveo2/TV2_8M_SI_B0_HyperFlash.elf
new file mode 100644
index 0000000..124deb6
Binary files /dev/null and b/flm/cypress/traveo2/TV2_8M_SI_B0_HyperFlash.elf differ
diff --git a/flm/cypress/traveo2/TV2_8M_SI_B0_HyperFlash_320p.elf b/flm/cypress/traveo2/TV2_8M_SI_B0_HyperFlash_320p.elf
new file mode 100644
index 0000000..be803b2
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diff --git a/flm/cypress/traveo2/TV2_8M_SI_B0_HyperRAM.elf b/flm/cypress/traveo2/TV2_8M_SI_B0_HyperRAM.elf
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index 0000000..96640ea
Binary files /dev/null and b/flm/cypress/traveo2/TV2_8M_SI_B0_HyperRAM.elf differ
diff --git a/flm/cypress/traveo2/TV2_8M_SI_B0_HyperRAM_320p.elf b/flm/cypress/traveo2/TV2_8M_SI_B0_HyperRAM_320p.elf
new file mode 100644
index 0000000..59ec2aa
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diff --git a/flm/cypress/traveo2/TV2_C2D_4M_DualQuadSPI.elf b/flm/cypress/traveo2/TV2_C2D_4M_DualQuadSPI.elf
new file mode 100644
index 0000000..cb03d4d
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_DualQuadSPI.elf differ
diff --git a/flm/cypress/traveo2/TV2_C2D_4M_HyperRAM.elf b/flm/cypress/traveo2/TV2_C2D_4M_HyperRAM.elf
new file mode 100644
index 0000000..38d38ca
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_HyperRAM.elf differ
diff --git a/flm/cypress/traveo2/TV2_C2D_4M_PSVP_DualQuadSPI_0.elf b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_DualQuadSPI_0.elf
new file mode 100644
index 0000000..b5974c5
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_DualQuadSPI_0.elf differ
diff --git a/flm/cypress/traveo2/TV2_C2D_4M_PSVP_DualQuadSPI_1.elf b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_DualQuadSPI_1.elf
new file mode 100644
index 0000000..cf467d9
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_DualQuadSPI_1.elf differ
diff --git a/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperFlash_0.elf b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperFlash_0.elf
new file mode 100644
index 0000000..0276796
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperFlash_0.elf differ
diff --git a/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperFlash_1.elf b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperFlash_1.elf
new file mode 100644
index 0000000..de0a4f4
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperFlash_1.elf differ
diff --git a/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperRAM_0.elf b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperRAM_0.elf
new file mode 100644
index 0000000..a8968b8
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diff --git a/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperRAM_1.elf b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperRAM_1.elf
new file mode 100644
index 0000000..d64dbd9
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_PSVP_HyperRAM_1.elf differ
diff --git a/flm/cypress/traveo2/TV2_C2D_4M_SemperFlash_0.elf b/flm/cypress/traveo2/TV2_C2D_4M_SemperFlash_0.elf
new file mode 100644
index 0000000..e89752d
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_SemperFlash_0.elf differ
diff --git a/flm/cypress/traveo2/TV2_C2D_4M_SemperFlash_1.elf b/flm/cypress/traveo2/TV2_C2D_4M_SemperFlash_1.elf
new file mode 100644
index 0000000..3c1e527
Binary files /dev/null and b/flm/cypress/traveo2/TV2_C2D_4M_SemperFlash_1.elf differ
diff --git a/scripts/bitsbytes.tcl b/scripts/bitsbytes.tcl
new file mode 100644
index 0000000..756c725
--- /dev/null
+++ b/scripts/bitsbytes.tcl
@@ -0,0 +1,59 @@
+#----------------------------------------
+# Purpose - Create some $BIT variables
+# Create $K and $M variables
+# and some bit field extraction variables.
+# Create helper variables ...
+# BIT0.. BIT31
+
+for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} {
+ set vn [format "BIT%d" $x]
+ global $vn
+ set $vn [expr {1 << $x}]
+}
+
+# Create K bytes values
+# __1K ... to __2048K
+for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} {
+ set vn [format "__%dK" $x]
+ global $vn
+ set $vn [expr {1024 * $x}]
+}
+
+# Create M bytes values
+# __1M ... to __2048K
+for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} {
+ set vn [format "__%dM" $x]
+ global $vn
+ set $vn [expr {1024 * 1024 * $x}]
+}
+
+proc create_mask { MSB LSB } {
+ return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}]
+}
+
+# Cut Bits $MSB to $LSB out of this value.
+# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16]
+# Result: 0x02340000
+
+proc extract_bitfield { VALUE MSB LSB } {
+ return [expr {[create_mask $MSB $LSB] & $VALUE}]
+}
+
+
+# Cut bits $MSB to $LSB out of this value
+# and shift (normalize) them down to bit 0.
+#
+# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16]
+# Result: 0x00000234
+#
+proc normalize_bitfield { VALUE MSB LSB } {
+ return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}]
+}
+
+proc show_normalize_bitfield { VALUE MSB LSB } {
+ set m [create_mask $MSB $LSB]
+ set mr [expr {$VALUE & $m}]
+ set sr [expr {$mr >> $LSB}]
+ echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
+ return $sr
+}
diff --git a/scripts/interface/kitprog.cfg b/scripts/interface/kitprog.cfg
new file mode 100644
index 0000000..29fce48
--- /dev/null
+++ b/scripts/interface/kitprog.cfg
@@ -0,0 +1,12 @@
+#
+# Cypress Semiconductor KitProg
+#
+# Note: This is the driver for the proprietary KitPtog protocol. If the
+# KitProg is in CMSIS-DAP mode, you should either use the cmsis-dap
+# interface driver or switch the KitProg to KitProg mode.
+#
+
+adapter driver kitprog
+
+# Optionally specify the serial number of the KitProg you want to use.
+#kitprog_serial 1926402735485200
diff --git a/scripts/interface/kitprog3.cfg b/scripts/interface/kitprog3.cfg
new file mode 100644
index 0000000..bb4559d
--- /dev/null
+++ b/scripts/interface/kitprog3.cfg
@@ -0,0 +1,59 @@
+#
+# Cypress Semiconductor KitProg3
+#
+# KitProg3 is CMSIS-DAP compliant adapter. However, it supports additional functionality
+# such as SPI/I2C bridging, Hardware acquire procedure for PSoC 4/5/6 devices, power control.
+# This functionality has been moved to separate driver to avoid pollution of generic CMSIS-DAP
+# with probe-specific code.
+#
+# Interface driver inherits all functionality of CMSIS-DAP including all tcl commands.
+# Additional functionality can be accessed via tcl using 'kitprog3' prefix
+#
+
+adapter driver kitprog3
+
+proc version_compare {s1 s2} {
+ set l1 [split [lindex $s1 1] "."]
+ set l2 [split [lindex $s2 1] "."]
+ foreach v1 $l1 v2 $l2 {
+ if {![string is integer $v1]} { puts stderr "Error: Malformed version: $s1"; return 0 }
+ if {![string is integer $v2]} { puts stderr "Error: Malformed version: $s2"; return 0 }
+ if {$v1 eq ""} {set v1 0}
+ if {$v2 eq ""} {set v2 0}
+ if {$v1 != $v2} {return [expr $v1 >= $v2 ? -1 : +1]}
+ }
+ return 0
+}
+
+proc find_versions {tools_dir dir_mask version_file} {
+ set result [list]
+ set matching_dirs [lsort -unique [glob -nocomplain -directory $tools_dir $dir_mask]]
+ foreach dir ${matching_dirs} {
+ set ver_file ""
+ catch { set ver_file [find "${dir}/${version_file}"] }
+ if { $ver_file != "" } {
+ set fd [open $ver_file "r"]
+ set ver [read -nonewline $fd]
+ close $fd
+ regsub -all {\s} $ver "" ver
+ regsub -all {} $ver "" ver
+ lappend result [list $dir $ver]
+ }
+ }
+ set result [lsort -command {version_compare} $result]
+ return $result
+}
+
+set script_dir [file dirname [file join [pwd] [info script]]]
+set script_dir_list [file split $script_dir]
+
+if {[llength $script_dir_list] > 5} {
+ set tools_dir [file join {*}[lrange [file split $script_dir] 0 end-5]]
+ set latest_fw_loader [lindex [find_versions $tools_dir "fw-loader*" "version.xml"] 0]
+ set latest_kp3_fw [lindex [find_versions $tools_dir "kp-firmware*" "kitprog3.version"] 0]
+ if {[llength $latest_fw_loader] != 0 && [llength $latest_kp3_fw] != 0} {
+ set fw_loader_dir [lindex $latest_fw_loader 0]
+ set kp3_fw [lindex $latest_kp3_fw 1]
+ kitprog3 set_latest_version $fw_loader_dir $kp3_fw
+ }
+}
diff --git a/scripts/mem_helper.tcl b/scripts/mem_helper.tcl
new file mode 100644
index 0000000..9ea285a
--- /dev/null
+++ b/scripts/mem_helper.tcl
@@ -0,0 +1,42 @@
+# Helper for common memory read/modify/write procedures
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+ set value ""
+ mem2array value 32 $reg 1
+ return $value(0)
+}
+
+add_usage_text mrw "address"
+add_help_text mrw "Returns value of word in memory."
+
+# mrh: "memory read halfword", returns value of $reg
+proc mrh {reg} {
+ set value ""
+ mem2array value 16 $reg 1
+ return $value(0)
+}
+
+add_usage_text mrh "address"
+add_help_text mrh "Returns value of halfword in memory."
+
+# mrb: "memory read byte", returns value of $reg
+proc mrb {reg} {
+ set value ""
+ mem2array value 8 $reg 1
+ return $value(0)
+}
+
+add_usage_text mrb "address"
+add_help_text mrb "Returns value of byte in memory."
+
+# mmw: "memory modify word", updates value of $reg
+# $reg <== ((value & ~$clearbits) | $setbits)
+proc mmw {reg setbits clearbits} {
+ set old [mrw $reg]
+ set new [expr {($old & ~$clearbits) | $setbits}]
+ mww $reg $new
+}
+
+add_usage_text mmw "address setbits clearbits"
+add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;"
diff --git a/scripts/memory.tcl b/scripts/memory.tcl
new file mode 100644
index 0000000..8d50ba8
--- /dev/null
+++ b/scripts/memory.tcl
@@ -0,0 +1,187 @@
+# MEMORY
+#
+# All Memory regions have two components.
+# (1) A count of regions, in the form N_NAME
+# (2) An array within info about each region.
+#
+# The ARRAY
+#
+# ( RegionNumber , ATTRIBUTE )
+#
+# Where is one of:
+#
+# N_FLASH & FLASH (internal memory)
+# N_RAM & RAM (internal memory)
+# N_MMREGS & MMREGS (for memory mapped registers)
+# N_XMEM & XMEM (off chip memory, ie: flash on cs0, sdram on cs2)
+# or N_UNKNOWN & UNKNOWN for things that do not exist.
+#
+# We have 1 unknown region.
+set N_UNKNOWN 1
+# All MEMORY regions must have these attributes
+# CS - chip select (if internal, use -1)
+set UNKNOWN(0,CHIPSELECT) -1
+# BASE - base address in memory
+set UNKNOWN(0,BASE) 0
+# LEN - length in bytes
+set UNKNOWN(0,LEN) $CPU_MAX_ADDRESS
+# HUMAN - human name of the region
+set UNKNOWN(0,HUMAN) "unknown"
+# TYPE - one of:
+# flash, ram, mmr, unknown
+# For harvard arch:
+# iflash, dflash, iram, dram
+set UNKNOWN(0,TYPE) "unknown"
+# RWX - access ablity
+# unix style chmod bits
+# 0 - no access
+# 1 - execute
+# 2 - write
+# 4 - read
+# hence: 7 - readwrite execute
+set RWX_NO_ACCESS 0
+set RWX_X_ONLY $BIT0
+set RWX_W_ONLY $BIT1
+set RWX_R_ONLY $BIT2
+set RWX_RW [expr {$RWX_R_ONLY + $RWX_W_ONLY}]
+set RWX_R_X [expr {$RWX_R_ONLY + $RWX_X_ONLY}]
+set RWX_RWX [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}]
+set UNKNOWN(0,RWX) $RWX_NO_ACCESS
+
+# WIDTH - access width
+# 8,16,32 [0 means ANY]
+set ACCESS_WIDTH_NONE 0
+set ACCESS_WIDTH_8 $BIT0
+set ACCESS_WIDTH_16 $BIT1
+set ACCESS_WIDTH_32 $BIT2
+set ACCESS_WIDTH_ANY [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}]
+set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
+
+proc iswithin { ADDRESS BASE LEN } {
+ return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
+}
+
+proc address_info { ADDRESS } {
+
+ foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
+ if { info exists $WHERE } {
+ set lmt [set N_[set WHERE]]
+ for { set region 0 } { $region < $lmt } { incr region } {
+ if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } {
+ return "$WHERE $region";
+ }
+ }
+ }
+ }
+
+ # Return the 'unknown'
+ return "UNKNOWN 0"
+}
+
+proc memread32 {ADDR} {
+ set foo(0) 0
+ if ![ catch { mem2array foo 32 $ADDR 1 } msg ] {
+ return $foo(0)
+ } else {
+ error "memread32: $msg"
+ }
+}
+
+proc memread16 {ADDR} {
+ set foo(0) 0
+ if ![ catch { mem2array foo 16 $ADDR 1 } msg ] {
+ return $foo(0)
+ } else {
+ error "memread16: $msg"
+ }
+}
+
+proc memread8 {ADDR} {
+ set foo(0) 0
+ if ![ catch { mem2array foo 8 $ADDR 1 } msg ] {
+ return $foo(0)
+ } else {
+ error "memread8: $msg"
+ }
+}
+
+proc memwrite32 {ADDR DATA} {
+ set foo(0) $DATA
+ if ![ catch { array2mem foo 32 $ADDR 1 } msg ] {
+ return $foo(0)
+ } else {
+ error "memwrite32: $msg"
+ }
+}
+
+proc memwrite16 {ADDR DATA} {
+ set foo(0) $DATA
+ if ![ catch { array2mem foo 16 $ADDR 1 } msg ] {
+ return $foo(0)
+ } else {
+ error "memwrite16: $msg"
+ }
+}
+
+proc memwrite8 {ADDR DATA} {
+ set foo(0) $DATA
+ if ![ catch { array2mem foo 8 $ADDR 1 } msg ] {
+ return $foo(0)
+ } else {
+ error "memwrite8: $msg"
+ }
+}
+
+proc memread32_phys {ADDR} {
+ set foo(0) 0
+ if ![ catch { mem2array foo 32 $ADDR 1 phys } msg ] {
+ return $foo(0)
+ } else {
+ error "memread32: $msg"
+ }
+}
+
+proc memread16_phys {ADDR} {
+ set foo(0) 0
+ if ![ catch { mem2array foo 16 $ADDR 1 phys } msg ] {
+ return $foo(0)
+ } else {
+ error "memread16: $msg"
+ }
+}
+
+proc memread8_phys {ADDR} {
+ set foo(0) 0
+ if ![ catch { mem2array foo 8 $ADDR 1 phys } msg ] {
+ return $foo(0)
+ } else {
+ error "memread8: $msg"
+ }
+}
+
+proc memwrite32_phys {ADDR DATA} {
+ set foo(0) $DATA
+ if ![ catch { array2mem foo 32 $ADDR 1 phys } msg ] {
+ return $foo(0)
+ } else {
+ error "memwrite32: $msg"
+ }
+}
+
+proc memwrite16_phys {ADDR DATA} {
+ set foo(0) $DATA
+ if ![ catch { array2mem foo 16 $ADDR 1 phys } msg ] {
+ return $foo(0)
+ } else {
+ error "memwrite16: $msg"
+ }
+}
+
+proc memwrite8_phys {ADDR DATA} {
+ set foo(0) $DATA
+ if ![ catch { array2mem foo 8 $ADDR 1 phys } msg ] {
+ return $foo(0)
+ } else {
+ error "memwrite8: $msg"
+ }
+}
diff --git a/scripts/mmr_helpers.tcl b/scripts/mmr_helpers.tcl
new file mode 100644
index 0000000..d9b6e63
--- /dev/null
+++ b/scripts/mmr_helpers.tcl
@@ -0,0 +1,72 @@
+
+proc proc_exists { NAME } {
+ set n [info commands $NAME]
+ set l [string length $n]
+ return [expr {$l != 0}]
+}
+
+# Give: REGISTER name - must be a global variable.
+proc show_mmr32_reg { NAME } {
+
+ global $NAME
+ # we want $($NAME)
+ set a [set [set NAME]]
+
+ if ![catch { set v [memread32 $a] } msg ] {
+ echo [format "%15s: (0x%08x): 0x%08x" $NAME $a $v]
+
+ # Was a helper defined?
+ set fn show_${NAME}_helper
+ if [ proc_exists $fn ] {
+ # Then call it
+ $fn $NAME $a $v
+ }
+ return $v;
+ } else {
+ error [format "%s (%s)" $msg $NAME ]
+ }
+}
+
+
+# Give: NAMES - an array of names accessible
+# in the callers symbol-scope.
+# VAL - the bits to display.
+
+proc show_mmr32_bits { NAMES VAL } {
+
+ upvar $NAMES MYNAMES
+
+ set w 5
+ foreach {IDX N} $MYNAMES {
+ set l [string length $N]
+ if { $l > $w } { set w $l }
+ }
+
+ for { set x 24 } { $x >= 0 } { incr x -8 } {
+ echo -n " "
+ for { set y 7 } { $y >= 0 } { incr y -1 } {
+ set s $MYNAMES([expr {$x + $y}])
+ echo -n [format "%2d: %-*s | " [expr {$x + $y}] $w $s ]
+ }
+ echo ""
+
+ echo -n " "
+ for { set y 7 } { $y >= 0 } { incr y -1 } {
+ echo -n [format " %d%*s | " [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] ""]
+ }
+ echo ""
+ }
+}
+
+
+proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } {
+ set width [expr {(($MSB - $LSB + 1) + 7) / 4}]
+ set nval [show_normalize_bitfield $VAL $MSB $LSB ]
+ set name0 [lindex $FIELDVALUES 0 ]
+ if [ string compare $name0 _NUMBER_ ] {
+ set sval [lindex $FIELDVALUES $nval]
+ } else {
+ set sval ""
+ }
+ echo [format "%-15s: %d (0x%0*x) %s" $FIELDNAME $nval $width $nval $sval ]
+}
diff --git a/scripts/startup_mark.tcl b/scripts/startup_mark.tcl
new file mode 100644
index 0000000..5de16f3
--- /dev/null
+++ b/scripts/startup_mark.tcl
@@ -0,0 +1 @@
+puts stderr "Started by GNU MCU Eclipse"
diff --git a/scripts/target/cympn.cfg b/scripts/target/cympn.cfg
new file mode 100644
index 0000000..56d7fdf
--- /dev/null
+++ b/scripts/target/cympn.cfg
@@ -0,0 +1,884 @@
+set MPN [dict create]
+dict set MPN 1D00 {CYPD3120-40LQXIT CCG3 128 32 CCG3 NA}
+dict set MPN 1D01 {CYPD3105-42FNXIT CCG3 128 32 CCG3 NA}
+dict set MPN 1D02 {CYPD3121-40LQXIT CCG3 128 32 CCG3 NA}
+dict set MPN 1D03 {CYPD3122-40LQXIT CCG3 128 32 CCG3 NA}
+dict set MPN 1D04 {CYPD3125-40LQXIT CCG3 128 32 CCG3 NA}
+dict set MPN 1D05 {CYPD3135-40LQXIT CCG3 128 32 CCG3 NA}
+dict set MPN 1D06 {CYPD3135-16SXQ CCG3 128 32 CCG3 NA}
+dict set MPN 1D07 {CYPD3126-42FNXIT CCG3 128 32 CCG3 NA}
+dict set MPN 1D09 {CYPD3123-40LQXIT CCG3 128 32 CCG3 NA}
+dict set MPN 1D08 {CYPD3135-32LQXQT CCG3 128 32 CCG3 NA}
+dict set MPN 1D0A {CY7C65219-40LQXIT CCG3 128 32 DMC NA}
+dict set MPN 1D20 {CYPM1211-40LQXIT CCG3 128 32 PMG1S2 NA}
+dict set MPN 1D21 {CYPM1211-42FNXIT CCG3 128 32 PMG1S2 NA}
+dict set MPN 2000 {CYPD3174-24LQXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2001 {CYPD3174-16SXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2002 {CYPD3175-24LQXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2003 {CYPD3171-24LQXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2004 {CYPD3177-24LQXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2005 {CYPD3195-24LDXS CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2006 {CYPD3196-24LDXS CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2007 {CYPD3197-24LDXS CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2008 {CYPD3198-24LDXS CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2009 {CYPD3193-24LDXS CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2010 {CYPD3194-24LDXS CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2011 {CYPD3176-24LQXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 20A0 {CYPD3174S-24LQXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 20A1 {CYPD3174S-16SXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 20A2 {CYPD3178-24LQXQ CCG3PA 64 32 CCG3PA NA}
+dict set MPN 2020 {CYPM1011-24LQXI CCG3PA 64 32 PMG1S0 NA}
+dict set MPN 1800 {CYPD4225-40LQXIT CCG4 128 32 CCG4 NA}
+dict set MPN 1801 {CYPD4125-40LQXIT CCG4 128 32 CCG4 NA}
+dict set MPN 1802 {CYPD4235-40LQXIT CCG4 128 32 CCG4 NA}
+dict set MPN 1803 {CYPD4135-40LQXIT CCG4 128 32 CCG4 NA}
+dict set MPN 1810 {CYPD4225A0-33FNXIT CCG4 128 32 CCG4 NA}
+dict set MPN 1F00 {CYPD4226-40LQXIT CCG4PD3 128 32 CCG4 NA}
+dict set MPN 1F01 {CYPD4126-40LQXIT CCG4PD3 128 32 CCG4 NA}
+dict set MPN 1F02 {CYPD4236-40LQXIT CCG4PD3 128 32 CCG4 NA}
+dict set MPN 1F03 {CYPD4136-40LQXIT CCG4PD3 128 32 CCG4 NA}
+dict set MPN 1F04 {CYPD4126-24LQXI CCG4PD3 128 32 CCG4 NA}
+dict set MPN 1F05 {CYPD4136-24LQXI CCG4PD3 128 32 CCG4 NA}
+dict set MPN 1F06 {CYPD4236-40LQXQT CCG4PD3 128 32 CCG4 NA}
+dict set MPN 2A00 {CYPD6125-40LQXIT CCG6 128 32 CCG6 NA}
+dict set MPN 2A01 {CYPD5126-40LQXIT CCG6 128 32 CCG6 NA}
+dict set MPN 2A02 {CYPD5137-40LQXIT CCG6 128 32 CCG6 NA}
+dict set MPN 2A03 {CYPD6137-40LQXIT CCG6 128 32 CCG6 NA}
+dict set MPN 2A10 {CYPD6126-96BZXI CCG6 128 32 CCG6 NA}
+dict set MPN 2A20 {CYPM1111-40LQXIT CCG6 128 32 PMG1S1 NA}
+dict set MPN 3000 {CYPD6227-96BZXI CCG6DF 64 32 CCG6DF NA}
+dict set MPN 3001 {CYPD6127-96BZXI CCG6DF 64 32 CCG6DF NA}
+dict set MPN 30A0 {CYPD6228-96BZXI CCG6DF 64 32 CCG6DF NA}
+dict set MPN 3300 {CYPD6128-96BZXI CCG6SF 64 32 CCG6SF NA}
+dict set MPN 3301 {CYPD6127-48LQXI CCG6SF 64 32 CCG6SF NA}
+dict set MPN 33A0 {CYPD6128-48LQXI CCG6SF 64 32 CCG6SF NA}
+dict set MPN 3100 {CYPD7291-68LDXS CCG7D 128 32 CCG7D NA}
+dict set MPN 3101 {CYPD7299-68LDXS CCG7D 128 32 CCG7D NA}
+dict set MPN 3110 {CYPD7271-68LQXQ CCG7D 128 32 CCG7D NA}
+dict set MPN 3111 {CYPD7272-68LQXQ CCG7D 128 32 CCG7D NA}
+dict set MPN 3112 {CYPD7273-68LQXQ CCG7D 128 32 CCG7D NA}
+dict set MPN 3113 {CYPD7274-68LQXQ CCG7D 128 32 CCG7D NA}
+dict set MPN 3114 {CYPD7275-68LQXQ CCG7D 128 32 CCG7D NA}
+dict set MPN 3A00 {CYPD7191-40LDXS CCG7S 128 32 CCG7S NA}
+dict set MPN EA41 {CYUSB2402A0-32LTXI MACAW 0 32 MACAW CM4}
+dict set MPN EA40 {CYUSB2402A0-24FNXI MACAW 0 32 MACAW CM4}
+dict set MPN 3500 {CYPM1322-97BZXIT PMG1S3 256 32 PMG1S3 NA}
+dict set MPN 3501 {CYPM1311-48LQXI PMG1S3 256 32 PMG1S3 NA}
+dict set MPN 3580 {CYPD8225-97BZXIT PMG1S3 256 32 PMG1S3 NA}
+dict set MPN 2800 {CY8C4546AZI-S473 PSoC4AMC 64 32 PSoC_4500S NA}
+dict set MPN 2801 {CY8C4546AZI-S475 PSoC4AMC 64 32 PSoC_4500S NA}
+dict set MPN 2802 {CY8C4546AXI-S475 PSoC4AMC 64 32 PSoC_4500S NA}
+dict set MPN 2803 {CY8C4547AZI-S453 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 2804 {CY8C4547AZI-S455 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 2805 {CY8C4547AZI-S463 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 2806 {CY8C4547AZI-S465 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 2807 {CY8C4547AZI-S473 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 2808 {CY8C4547AZI-S475 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 2809 {CY8C4547AXI-S475 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 280A {CY8C4548AZI-S475 PSoC4AMC 256 32 PSoC_4500S NA}
+dict set MPN 280B {CY8C4548AXI-S475 PSoC4AMC 256 32 PSoC_4500S NA}
+dict set MPN 280C {CY8C4548AZI-S483 PSoC4AMC 256 32 PSoC_4500S NA}
+dict set MPN 280D {CY8C4548AZI-S485 PSoC4AMC 256 32 PSoC_4500S NA}
+dict set MPN 280E {CY8C4548AXI-S485 PSoC4AMC 256 32 PSoC_4500S NA}
+dict set MPN 2830 {CY8C4128AZI-S443 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2831 {CY8C4128AZI-S445 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2832 {CY8C4128AXI-S445 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2833 {CY8C4128AZI-S453 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2834 {CY8C4128AZI-S455 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2835 {CY8C4128AXI-S455 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2836 {CY8C4148AZI-S443 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2837 {CY8C4148AZI-S445 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2838 {CY8C4148AXI-S445 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 2839 {CY8C4148AZI-S453 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 283A {CY8C4148AZI-S455 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 283B {CY8C4148AXI-S455 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 28A3 {CY8C4547AZQ-S453 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 28A4 {CY8C4547AZQ-S455 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 28A7 {CY8C4547AZQ-S473 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 28A8 {CY8C4547AZQ-S475 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 28A9 {CY8C4547AXQ-S475 PSoC4AMC 128 32 PSoC_4500S NA}
+dict set MPN 28AC {CY8C4548AZQ-S483 PSoC4AMC 256 32 PSoC_4500S NA}
+dict set MPN 28AD {CY8C4548AZQ-S485 PSoC4AMC 256 32 PSoC_4500S NA}
+dict set MPN 28AE {CY8C4548AXQ-S485 PSoC4AMC 256 32 PSoC_4500S NA}
+dict set MPN 28D6 {CY8C4148AZQ-S443 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 28D7 {CY8C4148AZQ-S445 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 28D8 {CY8C4148AXQ-S445 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 28D9 {CY8C4148AZQ-S453 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 28DA {CY8C4148AZQ-S455 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 28DB {CY8C4148AXQ-S455 PSoC4AMC 256 32 PSoC_4100S_Plus NA}
+dict set MPN 1950 {CY8C4724FNI-S402 PSoC4AS1 16 32 PSoC_4700S NA}
+dict set MPN 1951 {CY8C4724LQI-S401 PSoC4AS1 16 32 PSoC_4700S NA}
+dict set MPN 1952 {CY8C4725FNI-S402 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 1953 {CY8C4725LQI-S401 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 1954 {CY8C4744FNI-S402 PSoC4AS1 16 32 PSoC_4700S NA}
+dict set MPN 1955 {CY8C4744LQI-S401 PSoC4AS1 16 32 PSoC_4700S NA}
+dict set MPN 1956 {CY8C4744AZI-S403 PSoC4AS1 16 32 PSoC_4700S NA}
+dict set MPN 1957 {CY8C4745FNI-S402 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 1958 {CY8C4745LQI-S401 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 1959 {CY8C4745AZI-S403 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 195A {CY8C4745FNI-S412 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 195B {CY8C4745LQI-S411 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 195C {CY8C4745AZI-S413 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 1916 {CY8CINDSAZI-343 PSoC4AS1 32 32 PSoC_4700S NA}
+dict set MPN 1910 {CY8C4024FNI-S402 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1903 {CY8C4024LQI-S401 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1908 {CY8C4024LQI-S402 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 190C {CY8C4024AZI-S403 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1911 {CY8C4024FNI-S412 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1904 {CY8C4024LQI-S411 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1909 {CY8C4024LQI-S412 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 190D {CY8C4024AZI-S413 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1912 {CY8C4025FNI-S402 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1905 {CY8C4025LQI-S401 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 190A {CY8C4025LQI-S402 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 190E {CY8C4025AZI-S403 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1913 {CY8C4025FNI-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1906 {CY8C4025LQI-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 190B {CY8C4025LQI-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 190F {CY8C4025AZI-S413 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1902 {CY8C4045FNI-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1907 {CY8C4045LQI-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1900 {CY8C4045LQI-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1901 {CY8C4045AZI-S413 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1914 {CY8C4024LQI-S403 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1915 {CY8C4024LQI-S413 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1986 {CY8C4024LQA-S411 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1989 {CY8C4024PVA-S411 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1980 {CY8C4024PVA-S412 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1987 {CY8C4025LQA-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 198A {CY8C4025PVA-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1982 {CY8C4025PVA-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1988 {CY8C4045LQA-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 198B {CY8C4045PVA-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1984 {CY8C4045PVA-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19C6 {CY8C4024LQS-S411 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 19C9 {CY8C4024PVS-S411 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 19C0 {CY8C4024PVS-S412 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 19C7 {CY8C4025LQS-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19CA {CY8C4025PVS-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19C2 {CY8C4025PVS-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19C8 {CY8C4045LQS-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19CB {CY8C4045PVS-S411 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19C4 {CY8C4045PVS-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1917 {CY8C4024AXI-S402 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1918 {CY8C4024AXI-S412 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 1919 {CY8C4025AXI-S402 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1920 {CY8C4025AXI-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1921 {CY8C4045AXI-S412 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 191A {CY8C4025LQI-S403 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 191B {CY8C4025LQI-S413 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 191C {CY8C4045LQI-S413 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19EE {CY8C4025AZQ-S403 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19ED {CY8C4024AZQ-S413 PSoC4AS1 16 32 PSoC_4000S NA}
+dict set MPN 19EF {CY8C4025AZQ-S413 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 19F0 {CY8C4045AZQ-S413 PSoC4AS1 32 32 PSoC_4000S NA}
+dict set MPN 1B16 {CY8C4124FNI-S403 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B17 {CY8C4124FNI-S413 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B09 {CY8C4124LQI-S412 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B03 {CY8C4124LQI-S413 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B10 {CY8C4124AZI-S413 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B18 {CY8C4124FNI-S433 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B0A {CY8C4124LQI-S432 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B04 {CY8C4124LQI-S433 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B11 {CY8C4124AZI-S433 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1B19 {CY8C4125FNI-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B0B {CY8C4125LQI-S422 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B05 {CY8C4125LQI-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B12 {CY8C4125AZI-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B1A {CY8C4125FNI-S413 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B0C {CY8C4125LQI-S412 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B06 {CY8C4125LQI-S413 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B13 {CY8C4125AZI-S413 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B1B {CY8C4125FNI-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B0D {CY8C4125LQI-S432 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B07 {CY8C4125LQI-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B14 {CY8C4125AZI-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B1C {CY8C4146FNI-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B0E {CY8C4146LQI-S422 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B08 {CY8C4146LQI-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B15 {CY8C4146AZI-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B02 {CY8C4146FNI-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B0F {CY8C4146LQI-S432 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B00 {CY8C4146LQI-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B01 {CY8C4146AZI-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B1D {CY8C4146FNI-S443 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B1E {CY8C4125AXI-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B1F {CY8C4125AXI-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B27 {CY8C4126AZI-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B28 {CY8C4126AZI-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B20 {CY8C4126AXI-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B21 {CY8C4126AXI-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B26 {CY8C4145AZI-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B22 {CY8C4145AXI-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B23 {CY8C4145AXI-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B24 {CY8C4146AXI-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B25 {CY8C4146AXI-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C02 {CY8C4124PVA-S412 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C03 {CY8C4124LQA-S413 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C05 {CY8C4124PVA-S432 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C06 {CY8C4124LQA-S423 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C07 {CY8C4124LQA-S433 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C09 {CY8C4125PVA-S412 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C10 {CY8C4125LQA-S413 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C12 {CY8C4125PVA-S432 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C13 {CY8C4125LQA-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C15 {CY8C4146PVA-S422 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C16 {CY8C4146PVA-S432 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C17 {CY8C4146LQA-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C19 {CY8C4124PVS-S412 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C20 {CY8C4124LQS-S413 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C22 {CY8C4124PVS-S432 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C23 {CY8C4124LQS-S433 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C25 {CY8C4125PVS-S412 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C26 {CY8C4125LQS-S413 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C28 {CY8C4125PVS-S432 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C29 {CY8C4125LQS-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C31 {CY8C4146PVS-S422 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C32 {CY8C4146PVS-S432 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C33 {CY8C4146LQS-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C35 {CY8C4124PVE-S412 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C36 {CY8C4124LQE-S413 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C38 {CY8C4124PVE-S432 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C39 {CY8C4124LQE-S433 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C41 {CY8C4125PVE-S412 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C42 {CY8C4125LQE-S413 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C44 {CY8C4125PVE-S432 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C45 {CY8C4125LQE-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C47 {CY8C4146PVE-S422 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C48 {CY8C4146PVE-S432 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C46 {CY8C4146LQE-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C49 {CY8C4124PVA-S422 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C50 {CY8C4125PVA-S422 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C51 {CY8C4124PVS-S422 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C52 {CY8C4125PVS-S422 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C53 {CY8C4124PVE-S422 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C54 {CY8C4125PVE-S422 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C55 {CY8C4125LQA-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C56 {CY8C4146LQA-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C57 {CY8C4124LQS-S423 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C58 {CY8C4125LQS-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C59 {CY8C4146LQS-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1C60 {CY8C4124LQE-S423 PSoC4AS2 16 32 PSoC_4100S NA}
+dict set MPN 1C61 {CY8C4125LQE-S423 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1C62 {CY8C4146LQE-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B29 {CY8C4126AZQ-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B2A {CY8C4126AZQ-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B2B {CY8C4146AZQ-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B2C {CY8C4146AZQ-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B2D {CY8C4125AZQ-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B2E {CY8C4145AZQ-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B6B {CY8C4145AXQ-S433 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B6C {CY8C4126AXQ-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B6D {CY8C4146AXQ-S423 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B6E {CY8C4146AXQ-S433 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B6F {CY8C4125LQQ-S432 PSoC4AS2 32 32 PSoC_4100S NA}
+dict set MPN 1B70 {CY8C4146LQQ-S422 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 1B71 {CY8C4146LQQ-S432 PSoC4AS2 64 32 PSoC_4100S NA}
+dict set MPN 2518 {CY8C4126AXI-S443 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 251A {CY8C4126AZI-S445 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 251C {CY8C4126AXI-S445 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2520 {CY8C4126AZI-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2522 {CY8C4126AXI-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2530 {CY8C4146AXI-S443 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2532 {CY8C4146AZI-S445 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2534 {CY8C4146AXI-S445 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2536 {CY8C4146AXI-S453 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2538 {CY8C4146AZI-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 253A {CY8C4146AXI-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2548 {CY8C4127AXI-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 254A {CY8C4127AZI-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 254C {CY8C4127AXI-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 254E {CY8C4127AXI-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2550 {CY8C4127AZI-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2552 {CY8C4127AXI-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2568 {CY8C4147AXI-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 256A {CY8C4147AZI-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 256C {CY8C4147AXI-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 256E {CY8C4147AXI-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2570 {CY8C4147AZI-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2572 {CY8C4147AXI-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2576 {CY8C4147AZI-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2578 {CY8C4147AXI-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 257C {CY8C4147AZI-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 257E {CY8C4147AXI-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2589 {CY8C4126AZA-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2593 {CY8C4146AZA-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25A2 {CY8C4127AZA-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25A5 {CY8C4127AZA-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25BA {CY8C4147AZA-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25BD {CY8C4147AZA-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25C0 {CY8C4147AZA-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25C3 {CY8C4147AZA-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25CD {CY8C4126AZS-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25D7 {CY8C4146AZS-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25E6 {CY8C4127AZS-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25E9 {CY8C4127AZS-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25FE {CY8C4147AZS-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2561 {CY8C4147AZS-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2564 {CY8C4147AZS-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2567 {CY8C4147AZS-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 258B {CY8C4146AZA-S245 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 258D {CY8C4146AZA-S255 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 258F {CY8C4146AZA-S265 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2591 {CY8C4146AZA-S275 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25A8 {CY8C4147AZA-S245 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25AB {CY8C4147AZA-S255 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25AE {CY8C4147AZA-S265 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25B1 {CY8C4147AZA-S275 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25B4 {CY8C4147AZA-S285 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25B7 {CY8C4147AZA-S295 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25CF {CY8C4146AZS-S245 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25D1 {CY8C4146AZS-S255 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25D3 {CY8C4146AZS-S265 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25D5 {CY8C4146AZS-S275 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25EC {CY8C4147AZS-S245 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25EF {CY8C4147AZS-S255 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25F2 {CY8C4147AZS-S265 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25F5 {CY8C4147AZS-S275 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25F8 {CY8C4147AZS-S285 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25FB {CY8C4147AZS-S295 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2580 {CY8C4547AZI-445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2590 {CY8C4146AZI-S443 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2598 {CY8C4146AZI-S453 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2592 {CY8C4146AZI-S463 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2599 {CY8C4127AZI-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2594 {CY8C4127AZI-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2595 {CY8C4147AZI-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2596 {CY8C4147AZI-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2597 {CY8C4147AZI-S463 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2581 {CY8C4146AZQ-S445 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2582 {CY8C4146AZQ-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2583 {CY8C4127AZQ-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2584 {CY8C4147AZQ-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2585 {CY8C4127AZQ-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2586 {CY8C4147AZQ-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2587 {CY8C4147AZQ-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2588 {CY8C4147AZQ-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2505 {CY8C4126AZE-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2507 {CY8C4146AZE-S245 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2509 {CY8C4146AZE-S255 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 250B {CY8C4146AZE-S265 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 250D {CY8C4146AZE-S275 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 250F {CY8C4146AZE-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2511 {CY8C4127AZE-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2513 {CY8C4127AZE-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2515 {CY8C4147AZE-S245 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2517 {CY8C4147AZE-S255 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2519 {CY8C4147AZE-S265 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 251B {CY8C4147AZE-S275 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 251D {CY8C4147AZE-S285 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 251F {CY8C4147AZE-S295 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2521 {CY8C4147AZE-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2523 {CY8C4147AZE-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2503 {CY8C4147AZE-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2501 {CY8C4147AZE-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 252D {CY8C4126LQA-S453 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 252F {CY8C4146LQA-S243 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2531 {CY8C4146LQA-S253 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2533 {CY8C4146LQA-S263 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2535 {CY8C4146LQA-S273 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2537 {CY8C4146LQA-S453 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2541 {CY8C4127LQA-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2543 {CY8C4127LQA-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2545 {CY8C4147LQA-S243 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2547 {CY8C4147LQA-S253 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2549 {CY8C4147LQA-S263 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 254B {CY8C4147LQA-S273 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 254D {CY8C4147LQA-S283 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 254F {CY8C4147LQA-S293 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2551 {CY8C4147LQA-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2553 {CY8C4147LQA-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2555 {CY8C4147LQA-S463 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2557 {CY8C4147LQA-S473 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2560 {CY8C4126LQS-S453 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2562 {CY8C4146LQS-S243 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2563 {CY8C4146LQS-S253 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2565 {CY8C4146LQS-S263 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2566 {CY8C4146LQS-S273 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2569 {CY8C4146LQS-S453 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2573 {CY8C4127LQS-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2575 {CY8C4127LQS-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2577 {CY8C4147LQS-S243 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 257B {CY8C4147LQS-S253 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 257D {CY8C4147LQS-S263 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 258A {CY8C4147LQS-S273 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 258C {CY8C4147LQS-S283 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 258E {CY8C4147LQS-S293 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 259A {CY8C4147LQS-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 259B {CY8C4147LQS-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 259C {CY8C4147LQS-S463 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 259D {CY8C4147LQS-S473 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25A3 {CY8C4126LQE-S453 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25A4 {CY8C4146LQE-S243 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25A6 {CY8C4146LQE-S253 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25A7 {CY8C4146LQE-S263 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25A9 {CY8C4146LQE-S273 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25AA {CY8C4146LQE-S453 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25B2 {CY8C4127LQE-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25B3 {CY8C4127LQE-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25B5 {CY8C4147LQE-S243 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25B6 {CY8C4147LQE-S253 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25B8 {CY8C4147LQE-S263 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25B9 {CY8C4147LQE-S273 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25BB {CY8C4147LQE-S283 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25BC {CY8C4147LQE-S293 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25BE {CY8C4147LQE-S443 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25BF {CY8C4147LQE-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25C1 {CY8C4147LQE-S463 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25C2 {CY8C4147LQE-S473 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2689 {CY8C4126LQA-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 268B {CY8C4146LQA-S245 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 268D {CY8C4146LQA-S255 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 268F {CY8C4146LQA-S265 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2691 {CY8C4146LQA-S275 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2693 {CY8C4146LQA-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 26A2 {CY8C4127LQA-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26A5 {CY8C4127LQA-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26A8 {CY8C4147LQA-S245 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26AB {CY8C4147LQA-S255 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26AE {CY8C4147LQA-S265 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26B1 {CY8C4147LQA-S275 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26B4 {CY8C4147LQA-S285 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26B7 {CY8C4147LQA-S295 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26BA {CY8C4147LQA-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26BD {CY8C4147LQA-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26C0 {CY8C4147LQA-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26C3 {CY8C4147LQA-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26CD {CY8C4126LQS-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 26CF {CY8C4146LQS-S245 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 26D1 {CY8C4146LQS-S255 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 26D3 {CY8C4146LQS-S265 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 26D5 {CY8C4146LQS-S275 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 26D7 {CY8C4146LQS-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 26E6 {CY8C4127LQS-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26E9 {CY8C4127LQS-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26EC {CY8C4147LQS-S245 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26EF {CY8C4147LQS-S255 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26F2 {CY8C4147LQS-S265 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26F5 {CY8C4147LQS-S275 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26F8 {CY8C4147LQS-S285 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26FB {CY8C4147LQS-S295 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 26FE {CY8C4147LQS-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2661 {CY8C4147LQS-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2664 {CY8C4147LQS-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2667 {CY8C4147LQS-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2605 {CY8C4126LQE-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2607 {CY8C4146LQE-S245 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2609 {CY8C4146LQE-S255 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 260B {CY8C4146LQE-S265 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 260D {CY8C4146LQE-S275 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 260F {CY8C4146LQE-S455 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 2611 {CY8C4127LQE-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2613 {CY8C4127LQE-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2615 {CY8C4147LQE-S245 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2617 {CY8C4147LQE-S255 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2619 {CY8C4147LQE-S265 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 261B {CY8C4147LQE-S275 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 261D {CY8C4147LQE-S285 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 261F {CY8C4147LQE-S295 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2621 {CY8C4147LQE-S445 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2623 {CY8C4147LQE-S455 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2603 {CY8C4147LQE-S465 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2601 {CY8C4147LQE-S475 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 25F6 {CY8C4746LQS-S263 PSoC4AS3 64 32 PSoC_4100S_Plus NA}
+dict set MPN 25F7 {CY8C4747LQS-S453 PSoC4AS3 128 32 PSoC_4100S_Plus NA}
+dict set MPN 2E00 {CY8C4148AZI-S548 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E01 {CY8C4148AZI-S553 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E02 {CY8C4148AZI-S555 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E03 {CY8C4148AZI-S558 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E04 {CY8C4148AZI-S583 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E05 {CY8C4148AZI-S585 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E06 {CY8C4148AZI-S588 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E07 {CY8C4148AZI-S593 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E08 {CY8C4148AZI-S595 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E09 {CY8C4148AZI-S598 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E20 {CY8C4149AZI-S545 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E21 {CY8C4149AZI-S548 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E22 {CY8C4149AZI-S555 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E23 {CY8C4149AZI-S558 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E24 {CY8C4149AZI-S565 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E25 {CY8C4149AZI-S568 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E26 {CY8C4149AZI-S575 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E27 {CY8C4149AZI-S578 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E28 {CY8C4149AZI-S583 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E29 {CY8C4149AZI-S585 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E2A {CY8C4149AZI-S588 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E2B {CY8C4149AZI-S593 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E2C {CY8C4149AZI-S595 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E2D {CY8C4149AZI-S598 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E30 {CY8C4148AZQ-S558 PSoC4AS4 256 32 PSoC_4100S_Max NA}
+dict set MPN 2E31 {CY8C4149AZQ-S545 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E32 {CY8C4149AZQ-S548 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E33 {CY8C4149AZQ-S555 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E34 {CY8C4149AZQ-S558 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E35 {CY8C4149AZQ-S593 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E36 {CY8C4149AZQ-S595 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E37 {CY8C4149AZQ-S598 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E2E {CY8C4149AZI-S543 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 2E2F {CY8C4149AZI-S553 PSoC4AS4 384 32 PSoC_4100S_Max NA}
+dict set MPN 1C02 {CY8C4A45PVI-481 PSoC4BS0 32 32 PSoC_Analog_Coprocessor NA}
+dict set MPN 1C03 {CY8C4A45FNI-483 PSoC4BS0 32 32 PSoC_Analog_Coprocessor NA}
+dict set MPN 1C00 {CY8C4A45LQI-483 PSoC4BS0 32 32 PSoC_Analog_Coprocessor NA}
+dict set MPN 1C01 {CY8C4A45AZI-483 PSoC4BS0 32 32 PSoC_Analog_Coprocessor NA}
+dict set MPN 1C06 {CY8C4A25LQI-483 PSoC4BS0 32 32 PSoC_Analog_Coprocessor NA}
+dict set MPN 1C41 {CY8C4A45FNQ-483 PSoC4BS0 32 32 PSoC_Analog_Coprocessor NA}
+dict set MPN 1C40 {CY8C4A45LQQ-483 PSoC4BS0 32 32 PSoC_Analog_Coprocessor NA}
+dict set MPN 1C30 {CY8C4125PVI-PS421 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C35 {CY8C4125FNI-PS423 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C26 {CY8C4125LQI-PS423 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C2B {CY8C4125AZI-PS423 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C32 {CY8C4145PVI-PS421 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C37 {CY8C4145FNI-PS423 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C28 {CY8C4145LQI-PS423 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C2D {CY8C4145AZI-PS423 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C22 {CY8C4145PVI-PS431 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C23 {CY8C4145FNI-PS433 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C20 {CY8C4145LQI-PS433 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C21 {CY8C4145AZI-PS433 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C50 {CY8C4145FNQ-PS423 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 1C51 {CY8C4145FNQ-PS433 PSoC4BS0 32 32 PSoC_4100PS NA}
+dict set MPN 3200 {CY8C4126LCE-HV403 PSOC4HV144K 64 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 3201 {CY8C4126LCE-HV413 PSOC4HV144K 64 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 3202 {CY8C4126LCE-HV423 PSOC4HV144K 64 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 3203 {CY8C4127LCE-HV403 PSOC4HV144K 128 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 3204 {CY8C4127LCE-HV413 PSOC4HV144K 128 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 3205 {CY8C4127LCE-HV423 PSOC4HV144K 128 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 3209 {CY8C4147LCE-HV403 PSOC4HV144K 128 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 320A {CY8C4147LCE-HV413 PSOC4HV144K 128 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 320B {CY8C4147LCE-HV423 PSOC4HV144K 128 8 PSoC_4_HV_PA_144k NA}
+dict set MPN 32FF {CY8C4147LCE-HV423A PSoC4HVPA_192k 128 64 PSoC_4_HV_PA NA}
+dict set MPN EAC0 {CY8C6244AZI-S4D92 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC1 {CY8C6244LQI-S4D92 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC2 {CY8C6244AZI-S4D93 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC3 {CY8C6244AZI-S4D82 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC4 {CY8C6244LQI-S4D82 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC5 {CY8C6244AZI-S4D83 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC6 {CY8C6244AZI-S4D62 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC7 {CY8C6244LQI-S4D62 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC8 {CY8C6244AZI-S4D12 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAC9 {CY8C6244LQI-S4D12 PSoC6A256K 256 32 PSoC_62 NA}
+dict set MPN EAFF {CY8C4588AZI-H685 PSoC6A256K 256 32 PSoC_4500H NA}
+dict set MPN EAFE {CY8C4588AZI-H686 PSoC6A256K 256 32 PSoC_4500H NA}
+dict set MPN EAFD {CY8C4588AZI-H675 PSoC6A256K 256 32 PSoC_4500H NA}
+dict set MPN EAFC {CY8C4588AZI-H676 PSoC6A256K 256 32 PSoC_4500H NA}
+dict set MPN EACA {CY8C6144AZI-S4F92 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EACB {CY8C6144LQI-S4F92 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EACC {CY8C6144AZI-S4F93 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EACD {CY8C6144AZI-S4F82 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EACE {CY8C6144LQI-S4F82 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EACF {CY8C6144AZI-S4F83 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EAD0 {CY8C6144AZI-S4F62 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EAD1 {CY8C6144LQI-S4F62 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EAD2 {CY8C6144AZI-S4F12 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN EAD3 {CY8C6144LQI-S4F12 PSoC6A256K 256 32 PSoC_61 CM0p}
+dict set MPN E470 {CYB0644ABZI-S2D44 PSoC6A2M 1856 32 PSoC_64 NA}
+dict set MPN E4A0 {CYS0644ABZI-S2D44 PSoC6A2M 1856 32 PSoC_64 NA}
+dict set MPN E402 {CY8C624ABZI-S2D44A0 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E453 {CY8C624ABZI-S2D44 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E454 {CY8C624AAZI-S2D44 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E455 {CY8C624AFNI-S2D43 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E450 {CY8C624ABZI-S2D04 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E451 {CY8C624ABZI-S2D14 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E452 {CY8C624AAZI-S2D14 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E456 {CY8C6248AZI-S2D14 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E457 {CY8C6248BZI-S2D44 PSoC6A2M 1024 32 PSoC_62 NA}
+dict set MPN E458 {CY8C6248AZI-S2D44 PSoC6A2M 1024 32 PSoC_62 NA}
+dict set MPN E459 {CY8C6248FNI-S2D43 PSoC6A2M 1024 32 PSoC_62 NA}
+dict set MPN E45A {CY8C614ABZI-S2F04 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E45B {CY8C614AAZI-S2F04 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E45C {CY8C614AFNI-S2F03 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E45D {CY8C614AAZI-S2F14 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E45E {CY8C614ABZI-S2F44 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E45F {CY8C614AAZI-S2F44 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E460 {CY8C614AFNI-S2F43 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E461 {CY8C6148BZI-S2F44 PSoC6A2M 1024 32 PSoC_61 CM0p}
+dict set MPN E462 {CY8C6148AZI-S2F44 PSoC6A2M 1024 32 PSoC_61 CM0p}
+dict set MPN E463 {CY8C6148FNI-S2F43 PSoC6A2M 1024 32 PSoC_61 CM0p}
+dict set MPN E402 {CY8C624ABZI-D44 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E40B {CY8C624AAZI-D44 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E414 {CY8C624AFNI-D43 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E400 {CY8C624ABZI-D04 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E401 {CY8C624ABZI-D14 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E40A {CY8C624AAZI-D14 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E40C {CY8C6248AZI-D14 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E403 {CY8C6248BZI-D44 PSoC6A2M 1024 32 PSoC_62 NA}
+dict set MPN E40D {CY8C6248AZI-D44 PSoC6A2M 1024 32 PSoC_62 NA}
+dict set MPN E415 {CY8C6248FNI-D43 PSoC6A2M 1024 32 PSoC_62 NA}
+dict set MPN E419 {CY8C624ALQI-D42 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E4B0 {CY8C624ALQI-S2D42 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E4B1 {CY8C624ALQI-S2D02 PSoC6A2M 2048 32 PSoC_62 NA}
+dict set MPN E4B2 {CY8C6248LQI-S2D42 PSoC6A2M 1024 32 PSoC_62 NA}
+dict set MPN E4B3 {CY8C6248LQI-S2D02 PSoC6A2M 1024 32 PSoC_62 NA}
+dict set MPN E4B4 {CY8C614ALQI-S2F42 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E4B5 {CY8C614ALQI-S2F02 PSoC6A2M 2048 32 PSoC_61 CM0p}
+dict set MPN E4B6 {CY8C6148LQI-S2F42 PSoC6A2M 1024 32 PSoC_61 CM0p}
+dict set MPN E4B7 {CY8C6148LQI-S2F02 PSoC6A2M 1024 32 PSoC_61 CM0p}
+dict set MPN E700 {CY8C6245AZI-S3D72 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E701 {CY8C6245LQI-S3D72 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E702 {CY8C6245FNI-S3D71 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E703 {CY8C6245AZI-S3D62 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E704 {CY8C6245LQI-S3D62 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E705 {CY8C6245AZI-S3D42 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E706 {CY8C6245LQI-S3D42 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E70D {CYB06445LQI-S3D42 PSoC6A512K 448 32 PSoC_64 NA}
+dict set MPN E707 {CY8C6245FNI-S3D41 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E708 {CY8C6245AZI-S3D12 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E709 {CY8C6245LQI-S3D12 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E70A {CY8C6245FNI-S3D11 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E70B {CY8C6245AZI-S3D02 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E70C {CY8C6245LQI-S3D02 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E70E {CY8C6245WI-S3D72 PSoC6A512K 512 32 PSoC_62 NA}
+dict set MPN E70F {CY8C6145AZI-S3F72 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E710 {CY8C6145LQI-S3F72 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E711 {CY8C6145FNI-S3F71 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E712 {CY8C6145AZI-S3F62 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E713 {CY8C6145LQI-S3F62 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E714 {CY8C6145AZI-S3F42 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E715 {CY8C6145LQI-S3F42 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E716 {CY8C6145FNI-S3F41 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E717 {CY8C6145AZI-S3F12 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E718 {CY8C6145LQI-S3F12 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E719 {CY8C6145FNI-S3F11 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E71A {CY8C6145AZI-S3F02 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E71B {CY8C6145LQI-S3F02 PSoC6A512K 512 32 PSoC_61 CM0p}
+dict set MPN E210 {CY8C6036BZI-F04 PSoC6ABLE2 512 32 PSoC_60 CM0p}
+dict set MPN E211 {CY8C6016BZI-F04 PSoC6ABLE2 512 32 PSoC_60 CM0p}
+dict set MPN E212 {CY8C6116BZI-F54 PSoC6ABLE2 512 32 PSoC_61 CM0p}
+dict set MPN E213 {CY8C6136BZI-F14 PSoC6ABLE2 512 32 PSoC_61 CM0p}
+dict set MPN E214 {CY8C6136BZI-F34 PSoC6ABLE2 512 32 PSoC_61 CM0p}
+dict set MPN E215 {CY8C6137BZI-F14 PSoC6ABLE2 1024 32 PSoC_61 CM0p}
+dict set MPN E216 {CY8C6137BZI-F34 PSoC6ABLE2 1024 32 PSoC_61 CM0p}
+dict set MPN E217 {CY8C6137BZI-F54 PSoC6ABLE2 1024 32 PSoC_61 CM0p}
+dict set MPN E218 {CY8C6117BZI-F34 PSoC6ABLE2 1024 32 PSoC_61 CM0p}
+dict set MPN E219 {CY8C6246BZI-D04 PSoC6ABLE2 512 32 PSoC_62 NA}
+dict set MPN E21A {CY8C6247BZI-D44 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E21B {CY8C6247BZI-D34 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E206 {CY8C6247BZI-D54 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E220 {CY8C6336BZI-BLF03 PSoC6ABLE2 512 32 PSoC_63 CM0p}
+dict set MPN E221 {CY8C6316BZI-BLF03 PSoC6ABLE2 512 32 PSoC_63 CM0p}
+dict set MPN E222 {CY8C6316BZI-BLF53 PSoC6ABLE2 512 32 PSoC_63 CM0p}
+dict set MPN E223 {CY8C6336BZI-BLD13 PSoC6ABLE2 512 32 PSoC_63 NA}
+dict set MPN E224 {CY8C6347BZI-BLD43 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E225 {CY8C6347BZI-BLD33 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E207 {CY8C6347BZI-BLD53 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E226 {CY8C6347FMI-BLD13 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E227 {CY8C6347FMI-BLD43 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E228 {CY8C6347FMI-BLD33 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E208 {CY8C6347FMI-BLD53 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E200 {CY8C637BZI-MD76 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E201 {CY8C637BZI-BLD74 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E202 {CY8C637FMI-BLD73 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E205 {CY8C68237BZ-BLE PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E204 {CY8C68237FM-BLE PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E230 {CY8C6137FDI-F02 PSoC6ABLE2 1024 32 PSoC_61 CM0p}
+dict set MPN E231 {CY8C6117FDI-F02 PSoC6ABLE2 1024 32 PSoC_61 CM0p}
+dict set MPN E232 {CY8C6247FDI-D02 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E233 {CY8C6247FDI-D32 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E240 {CY8C6336BZI-BUD13 PSoC6ABLE2 512 32 PSoC_63 NA}
+dict set MPN E241 {CY8C6347BZI-BUD43 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E242 {CY8C6347BZI-BUD33 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E243 {CY8C6347BZI-BUD53 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E229 {CY8C6337BZI-BLF13 PSoC6ABLE2 1024 32 PSoC_63 CM0p}
+dict set MPN E235 {CY8C6136FDI-F42 PSoC6ABLE2 512 32 PSoC_61 CM0p}
+dict set MPN E234 {CY8C6247FDI-D52 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E236 {CY8C6136FTI-F42 PSoC6ABLE2 512 32 PSoC_61 CM0p}
+dict set MPN E237 {CY8C6247FTI-D52 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E2A1 {CY8C6247BZI-AUD54 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E22A {CY8C6336BZI-BLF04 PSoC6ABLE2 512 32 PSoC_63 CM0p}
+dict set MPN E22B {CY8C6316BZI-BLF04 PSoC6ABLE2 512 32 PSoC_63 CM0p}
+dict set MPN E22C {CY8C6316BZI-BLF54 PSoC6ABLE2 512 32 PSoC_63 CM0p}
+dict set MPN E22D {CY8C6336BZI-BLD14 PSoC6ABLE2 512 32 PSoC_63 NA}
+dict set MPN E22E {CY8C6347BZI-BLD44 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E22F {CY8C6347BZI-BLD34 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E20B {CY8C6347BZI-BLD54 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E20A {CY8C6247BFI-D54 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E2F0 {CYBLE-416045-02 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E244 {CY8C6347FMI-BUD53 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E245 {CY8C6347FMI-BUD13 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E246 {CY8C6347FMI-BUD43 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E247 {CY8C6347FMI-BUD33 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E248 {CY8C6137WI-F54 PSoC6ABLE2 1024 32 PSoC_61 CM0p}
+dict set MPN E249 {CY8C6117WI-F34 PSoC6ABLE2 1024 32 PSoC_61 CM0p}
+dict set MPN E250 {CY8C6247WI-D54 PSoC6ABLE2 1024 32 PSoC_62 NA}
+dict set MPN E251 {CY8C6336LQI-BLF02 PSoC6ABLE2 512 32 PSoC_63 CM0p}
+dict set MPN E252 {CY8C6336LQI-BLF42 PSoC6ABLE2 512 32 PSoC_63 CM0p}
+dict set MPN E253 {CY8C6347LQI-BLD52 PSoC6ABLE2 1024 32 PSoC_63 NA}
+dict set MPN E260 {CYB06447BZI-BLD54 PSoC6ABLE2 832 32 PSoC_64 NA}
+dict set MPN E261 {CYB06447BZI-BLD53 PSoC6ABLE2 832 32 PSoC_64 NA}
+dict set MPN E262 {CYB06447BZI-D54 PSoC6ABLE2 832 32 PSoC_64 NA}
+dict set MPN 2700 {CYAT817L-100AA72 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2701 {CYAT817L-100AS72 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2702 {CYAT817LS-100AA72 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2703 {CYAT817LS-100AS72 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2704 {CYAT817L-128AA72 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2705 {CYAT817L-128AS72 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2760 {CYAT817LS-128AA72 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2761 {CYAT817LS-128AS72 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2762 {CYAT817L-100AA61 TSG7_L 128 32 TSG7_L NA}
+dict set MPN 2763 {CYAT817L-100AS61 TSG7_L 128 32 TSG7_L NA}
+dict set MPN E349 {CYT2B63BAS TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E349 {CYT2B63BAE TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E34A {CYT2B63CAS TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E34A {CYT2B63CAE TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E351 {CYT2B64BAS TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E351 {CYT2B64BAE TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E352 {CYT2B64CAS TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E352 {CYT2B64CAE TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E359 {CYT2B65BAS TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E359 {CYT2B65BAE TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E35A {CYT2B65CAS TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E35A {CYT2B65CAE TVIIBE1M 576 64 CYT2B6 NA}
+dict set MPN E3C9 {CYT2B73BAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3C9 {CYT2B73BAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3CA {CYT2B73CAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3CA {CYT2B73CAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3D1 {CYT2B74BAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3D1 {CYT2B74BAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3D2 {CYT2B74CAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3D2 {CYT2B74CAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3D9 {CYT2B75BAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3D9 {CYT2B75BAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3DA {CYT2B75CAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3DA {CYT2B75CAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3E1 {CYT2B77BAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3E1 {CYT2B77BAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3E2 {CYT2B77CAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3E2 {CYT2B77CAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3E9 {CYT2B78BAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3E9 {CYT2B78BAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3EA {CYT2B78CAS TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E3EA {CYT2B78CAE TVIIBE1M 1088 96 CYT2B7 NA}
+dict set MPN E300 {CYT2B7PSVA TVIIBE1M 1088 96 CYT2B7PSVP NA}
+dict set MPN E6C9 {CYT2B93BAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6C9 {CYT2B93BAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6CA {CYT2B93CAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6CA {CYT2B93CAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6D1 {CYT2B94BAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6D1 {CYT2B94BAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6D2 {CYT2B94CAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6D2 {CYT2B94CAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6D9 {CYT2B95BAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6D9 {CYT2B95BAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6DA {CYT2B95CAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6DA {CYT2B95CAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6E1 {CYT2B97BAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6E1 {CYT2B97BAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6E2 {CYT2B97CAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6E2 {CYT2B97CAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6E9 {CYT2B98BAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6E9 {CYT2B98BAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6EA {CYT2B98CAS TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E6EA {CYT2B98CAE TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E601 {CYT2A0100E TVIIBE2M 2112 128 CYT2B9 NA}
+dict set MPN E600 {CYT2B9PSVA TVIIBE2M 2112 128 CYT2B9PSVP NA}
+dict set MPN EA01 {CYT2BL3BAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA01 {CYT2BL3BAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA02 {CYT2BL3CAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA02 {CYT2BL3CAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA03 {CYT2BL4BAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA03 {CYT2BL4BAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA04 {CYT2BL4CAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA04 {CYT2BL4CAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA05 {CYT2BL5BAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA05 {CYT2BL5BAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA06 {CYT2BL5CAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA06 {CYT2BL5CAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA07 {CYT2BL7BAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA07 {CYT2BL7BAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA08 {CYT2BL7CAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA08 {CYT2BL7CAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA09 {CYT2BL8BAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA09 {CYT2BL8BAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA0A {CYT2BL8CAS TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA0A {CYT2BL8CAE TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN EA0B {CYT2A0101E TVIIBE4M 4160 128 CYT2BL NA}
+dict set MPN E919 {CYT3BB5CES TVIIBH4M 4160 256 CYT3BB NA}
+dict set MPN E919 {CYT3BB5CEE TVIIBH4M 4160 256 CYT3BB NA}
+dict set MPN E91A {CYT3BB7CES TVIIBH4M 4160 256 CYT3BB NA}
+dict set MPN E91A {CYT3BB7CEE TVIIBH4M 4160 256 CYT3BB NA}
+dict set MPN E91B {CYT3BB8CES TVIIBH4M 4160 256 CYT3BB NA}
+dict set MPN E91B {CYT3BB8CEE TVIIBH4M 4160 256 CYT3BB NA}
+dict set MPN E91C {CYT3BBBCES TVIIBH4M 4160 256 CYT3BB NA}
+dict set MPN E91C {CYT3BBBCEE TVIIBH4M 4160 256 CYT3BB NA}
+dict set MPN E91D {CYT4BB5CES TVIIBH4M 4160 256 CYT4BB NA}
+dict set MPN E91D {CYT4BB5CEE TVIIBH4M 4160 256 CYT4BB NA}
+dict set MPN E91E {CYT4BB7CES TVIIBH4M 4160 256 CYT4BB NA}
+dict set MPN E91E {CYT4BB7CEE TVIIBH4M 4160 256 CYT4BB NA}
+dict set MPN E91F {CYT4BB8CES TVIIBH4M 4160 256 CYT4BB NA}
+dict set MPN E91F {CYT4BB8CEE TVIIBH4M 4160 256 CYT4BB NA}
+dict set MPN E920 {CYT4BBBCES TVIIBH4M 4160 256 CYT4BB NA}
+dict set MPN E920 {CYT4BBBCEE TVIIBH4M 4160 256 CYT4BB NA}
+dict set MPN E5D3 {CYT4BF8CES TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5D3 {CYT4BF8CEE TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5D7 {CYT4BF8CDS TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5D7 {CYT4BF8CDE TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5EB {CYT4BFBCJS TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5EB {CYT4BFBCJE TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5EF {CYT4BFBCHS TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5EF {CYT4BFBCHE TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5FB {CYT4BFCCJS TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5FB {CYT4BFCCJE TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5FF {CYT4BFCCHS TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E5FF {CYT4BFCCHE TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E501 {CYT4A0100S TVIIBH8M 8384 256 CYT4BF NA}
+dict set MPN E500 {CYT4BFPSVA TVIIBH8M 8384 256 CYT4BFPSVP NA}
+dict set MPN E840 {CYT3DLPSVA TVIIC2D4M 4160 128 CYT3DLPSVP NA}
+dict set MPN E841 {CYT3DLBBAS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E842 {CYT3DLBBBS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E843 {CYT3DLBBCS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E844 {CYT3DLBBDS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E845 {CYT3DLBBES TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E846 {CYT3DLBBFS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E847 {CYT3DLBBGS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E848 {CYT3DLBBHS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E849 {CYT3DLABAS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E84A {CYT3DLABBS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E84B {CYT3DLABCS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E84C {CYT3DLABDS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E84D {CYT3DLABES TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E84E {CYT3DLABFS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E84F {CYT3DLABGS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E850 {CYT3DLABHS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E851 {CYT3DL9BAS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E852 {CYT3DL9BBS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E853 {CYT3DL9BCS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E854 {CYT3DL9BDS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E855 {CYT3DL9BES TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E856 {CYT3DL9BFS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E857 {CYT3DL9BGS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E858 {CYT3DL9BHS TVIIC2D4M 4160 128 CYT3DL NA}
+dict set MPN E800 {CYT4DNPSVB TVIIC2D6M 6336 128 CYT4DNPSVP NA}
+dict set MPN E811 {CYT4DNJBAS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E812 {CYT4DNJBBS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E813 {CYT4DNJBCS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E814 {CYT4DNJBDS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E815 {CYT4DNJBES TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E816 {CYT4DNJBFS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E817 {CYT4DNJBGS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E818 {CYT4DNJBHS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E819 {CYT4DNJBJS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E81A {CYT4DNJBKS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E81B {CYT4DNJBLS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E81C {CYT4DNJBMS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E81D {CYT4DNJBNS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E81E {CYT4DNJBPS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E81F {CYT4DNJBQS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E820 {CYT4DNJBRS TVIIC2D6M 6336 128 CYT4DN NA}
+dict set MPN E821 {CYT3DLJBBS TVIIC2D6M 4160 128 CYT3DL NA}
+dict set MPN E822 {CYT3DLJBDS TVIIC2D6M 4160 128 CYT3DL NA}
+dict set MPN E823 {CYT3DLJBFS TVIIC2D6M 4160 128 CYT3DL NA}
+dict set MPN E824 {CYT3DLJBHS TVIIC2D6M 4160 128 CYT3DL NA}
+dict set MPN EB01 {CYT4ENDBAS TVIIC2D6MDDR 6336 128 CYT4EN NA}
+dict set MPN EB02 {CYT4ENDBCS TVIIC2D6MDDR 6336 128 CYT4EN NA}
+dict set MPN EB03 {CYT4ENDBES TVIIC2D6MDDR 6336 128 CYT4EN NA}
+dict set MPN EB04 {CYT4ENDBGS TVIIC2D6MDDR 6336 128 CYT4EN NA}
+dict set MPN EB05 {CYT4ENDBJS TVIIC2D6MDDR 6336 128 CYT4EN NA}
+dict set MPN EB06 {CYT4ENDBLS TVIIC2D6MDDR 6336 128 CYT4EN NA}
+dict set MPN EB07 {CYT4ENDBNS TVIIC2D6MDDR 6336 128 CYT4EN NA}
+dict set MPN EB08 {CYT4ENDBQS TVIIC2D6MDDR 6336 128 CYT4EN NA}
+dict set MPN EC01 {CYT2CL8BAS TVIICE4M 4160 128 CYT2CL NA}
+dict set MPN EC02 {CYT2C98BAS TVIICE4M 2112 128 CYT2C9 NA}
+dict set MPN EC03 {CYT2CL7BAS TVIICE4M 4160 128 CYT2CL NA}
+dict set MPN EC04 {CYT2C97BAS TVIICE4M 2112 128 CYT2C9 NA}
+dict set MPN EC05 {CYT2CLHBAS TVIICE4M 4160 128 CYT2CL NA}
+dict set MPN EC06 {CYT2C9HBAS TVIICE4M 2112 128 CYT2C9 NA}
diff --git a/scripts/target/infineon/tle987x.cfg b/scripts/target/infineon/tle987x.cfg
new file mode 100644
index 0000000..84cc238
--- /dev/null
+++ b/scripts/target/infineon/tle987x.cfg
@@ -0,0 +1,36 @@
+#
+# Infineon TLE987x family (Arm Cortex-M3 @ up to 40 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME tle987x
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CPU_SWD_TAPID] } {
+ set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+ set _CPU_SWD_TAPID 0x2BA01477
+}
+
+if { [using_jtag] } {
+ # JTAG not supported, only SWD
+ set _CPU_TAPID 0
+} else {
+ set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME dap -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { ![using_hla] } {
+ cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/scripts/target/mxs40/cy_get_set_device_param.cfg b/scripts/target/mxs40/cy_get_set_device_param.cfg
new file mode 100644
index 0000000..882f20a
--- /dev/null
+++ b/scripts/target/mxs40/cy_get_set_device_param.cfg
@@ -0,0 +1,186 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+
+source [find target/mxs40/psoc6_detect_geometry.cfg]
+source [find target/mxs40/traveo2_detect_geometry.cfg]
+
+#
+# shows flash boot version
+#
+# arguments:
+# target_arch - the target architecture - psoc6 or traveo2
+#
+proc show_flash_boot_ver { target_arch } {
+
+ set fb_ver_str ""
+ set fb_ver_hi_addr ""
+ set fb_ver_lo_addr ""
+
+ switch $target_arch {
+ "psoc6" -
+ "psoc6_2m" {
+ set fb_ver_hi_addr 0x16002004
+ set fb_ver_lo_addr 0x16002018
+ set sflash_svn_ver_addr 0x16000028
+ }
+ "traveo21" -
+ "traveo22" {
+ set fb_ver_hi_addr 0x17002004
+ set fb_ver_lo_addr 0x17002018
+ set sflash_svn_ver_addr 0x170000A8
+ }
+ default {
+ puts stderr "Error: Invalid Target passed into 'show_flash_boot_ver'"
+ return
+ }
+ }
+
+ set fb_ver_lo ""
+ set fb_ver_hi ""
+
+ catch { set fb_ver_hi [mrw $fb_ver_hi_addr] }
+
+ if {$fb_ver_hi eq "" || !$fb_ver_hi} {
+ puts stderr "Error: Invalid FlashBoot: High version word of Flash Boot is zero"
+ return
+ }
+
+ catch { set fb_ver_lo [mrw $fb_ver_lo_addr] }
+
+ set b0 [expr { $fb_ver_hi >> 28 } ]
+ set b1 [expr {($fb_ver_hi >> 24) & 0xF } ]
+ set b2 [expr {($fb_ver_hi >> 16) & 0xFF} ]
+ set b3 [expr {$fb_ver_hi & 0x0000FFFF}]
+
+ if {$b0 > 2} {
+ puts stderr "Error: Unsupported Flash Boot Version - Flash Boot Version \[31:28] = $b0"
+ return
+ }
+
+ if {$b3 != 0x8001} {
+ puts stderr "Error: Flash Boot is corrupted or non Flash Boot image programmed"
+ return
+ }
+
+ if { $b0 == 0 } { ; # Versioning scheme #1 or #2, PSoC6A-BLE-2 device family
+ if { $b1 == 1 } { ; # Versioning scheme #1, ** or *A
+ set fb_ver_str [format "1.%02d" $b2]
+ } elseif { $b1 == 2 } {
+ if { $b2 < 20 } {
+ set fb_ver_str [format "1.0.0.%d" $b2]
+ } elseif { $b2 < 29 } {
+ set fb_ver_str [format "1.0.1.%d" $b2]
+ } else {
+ set fb_ver_str [format "1.20.1.%d" $b2]
+ }
+ }
+ } elseif { $b0 == 1 } { ;# TVII-BE-1M **
+ set fb_ver_str [format "2.0.0.%d" $b2]
+ } elseif { $b0 == 2 } { ;# Versioning scheme #3
+ set patch [expr { $fb_ver_lo >> 24} ]
+ set build [expr { $fb_ver_lo & 0xFFFF } ]
+ set fb_ver_str [format "%d.%d.%d.%d" $b1 $b2 $patch $build ]
+ }
+
+ echo "** Flash Boot version: $fb_ver_str"
+
+ set sflash_svn_ver 0
+ catch {
+ set sflash_svn_ver [mrw $sflash_svn_ver_addr]
+ }
+
+ if { $sflash_svn_ver != 0 && $sflash_svn_ver != 0xFFFFFFFF } {
+ echo "** SFlash version: $sflash_svn_ver"
+ }
+
+ return $fb_ver_str
+}
+
+#
+# shows chip protection
+#
+# arguments:
+# target_arch - the target architecture - psoc6 or traveo2
+#
+proc show_chip_protection {target_arch} {
+ switch $target_arch {
+ "psoc6" {
+ set cpuss_prot_reg 0x40210500
+ }
+ "psoc6_2m" -
+ "traveo21" -
+ "traveo22" {
+ set cpuss_prot_reg 0x402020C4
+ }
+ default {
+ puts stderr "Error: Invalid Target passed into 'show_chip_protection'"
+ return
+ }
+ }
+
+ set protection [ mrw $cpuss_prot_reg ]
+ set ret "X"
+
+ switch $protection {
+ 1 { set ret "VIRGIN" }
+ 2 { set ret "NORMAL" }
+ 3 { set ret "SECURE" }
+ 4 { set ret "DEAD" }
+ default { set ret "UNKNOWN" }
+ }
+
+ echo "** Chip Protection: $ret"
+}
+
+#
+# shows and set device specific parameters
+#
+# arguments:
+# target_arch - the target architecture - psoc6, psoc6_2m or traveo2
+# main_reg_name - the name of main region to be set
+# work_reg_name - the name of work region to be set
+#
+proc cy_get_set_device_param {target_arch {main_reg_name ""} {work_reg_name ""}} {
+ set tgt [target current]
+ set CHIPNAME [string range ${tgt} 0 [expr {[string first "." ${tgt}] - 1}]]
+ global ${CHIPNAME}::info_runned
+ global ${CHIPNAME}::wrong_cfg_msg
+
+ if { ![info exist ${CHIPNAME}::info_runned] } {
+ echo "***************************************"
+ switch $target_arch {
+ "psoc6" -
+ "psoc6_2m" {
+ psoc6_detect_geometry $target_arch $main_reg_name
+ }
+ "traveo21" -
+ "traveo22" {
+ traveo2_detect_geometry $target_arch $main_reg_name $work_reg_name
+ }
+ default {
+ puts stderr [format "Error: Invalid target architecture '%s' is passed into 'cy_get_set_device_param' API" $target_arch]
+ return
+ }
+ }
+
+ show_flash_boot_ver $target_arch
+ show_chip_protection $target_arch
+ echo "***************************************"
+
+ if { [info exist ${CHIPNAME}::wrong_cfg_msg] && [set ${CHIPNAME}::wrong_cfg_msg] != "" } {
+ set cfg_file [set ${CHIPNAME}::wrong_cfg_msg]
+ puts stderr "*******************************************************************************"
+ if {[using_jtag]} {
+ puts stderr "* JTAG CHIPNAME: ${CHIPNAME}"
+ }
+ puts stderr "* The detected device does not match the configuration file in use."
+ puts stderr "* Flash programming will not work. Please use the $cfg_file"
+ puts stderr "* configuration file, or attach a kit that matches the configuration file."
+ puts stderr "*******************************************************************************"
+ terminate
+ }
+ set ${CHIPNAME}::info_runned true
+ }
+}
diff --git a/scripts/target/mxs40/cympn_parser.cfg b/scripts/target/mxs40/cympn_parser.cfg
new file mode 100644
index 0000000..9917809
--- /dev/null
+++ b/scripts/target/mxs40/cympn_parser.cfg
@@ -0,0 +1,105 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+
+source [find target/cympn.cfg]
+
+proc check_die_matches_driver { DIE SERIES } {
+ set tgt [target current]
+ set CHIPNAME [string range ${tgt} 0 [expr {[string first "." ${tgt}] - 1}]]
+
+ global MXS40_DIE_CONFIG_DICT
+ global ${CHIPNAME}::wrong_cfg_msg
+ global ${CHIPNAME}::MXS40_TARGET_DIE
+
+ if {![info exists ${CHIPNAME}::MXS40_TARGET_DIE]} return
+ set is_psoc64 [string equal -nocase $SERIES "PSoC_64"]
+
+ if { $DIE != [set ${CHIPNAME}::MXS40_TARGET_DIE] || $is_psoc64 } {
+ if { [info exists MXS40_DIE_CONFIG_DICT($DIE)] } {
+ set ${CHIPNAME}::wrong_cfg_msg \"$MXS40_DIE_CONFIG_DICT($DIE)\"
+ if { $is_psoc64 } {
+ set ${CHIPNAME}::wrong_cfg_msg [regsub {\.} [set ${CHIPNAME}::wrong_cfg_msg] {_secure.}]
+ }
+ } else {
+ set ${CHIPNAME}::wrong_cfg_msg "proper"
+ }
+ }
+}
+
+#
+# returns size of main and work flash of connected MPN
+#
+# Performs following:
+# - reads SiId from sflash
+# - path through UDD and searches for record with the SiId
+# - if the record is found then size of main and work flash is extracted
+# and returned, otherwise empty list is returned
+#
+# arguments:
+# target_arch - used architecture, can be "psoc6" or "traveo2"
+#
+# return
+# list of flash sizes in form {main_size_kb work_size_kb}
+#
+proc cyp_get_mpn_work_main_size { target_arch } {
+ global MPN
+
+ set siid ""
+ set revision ""
+ set family ""
+
+ switch $target_arch {
+ "psoc6" -
+ "psoc6_2m" {
+ set addr_siid 0x16000000
+ set addr_family 0x1600000C
+ }
+ "traveo2" {
+ set addr_siid 0x17000000
+ set addr_family 0x1700000C
+ }
+ }
+
+ catch {
+ set siid [format "%04X" [expr {[mrw $addr_siid] >> 16} ]]
+ set revision [format "%02X" [expr {([mrw $addr_siid] & 0x0000FF00) >> 8}]]
+ set family [format "%03X" [expr {[mrw $addr_family] & 0x00000FFF}]]
+ }
+
+ if {$family != ""} {
+ # as per MTRO-57
+ set rev_major "0x0[string index $revision 0]"
+ if { $rev_major == "0" } {
+ set rev_major_str "*"
+ } else {
+ set rev_major_str [format %c [expr {$rev_major + 0x40}]]
+ }
+
+ set rev_minor "0x0[string index $revision 1]"
+ if { $rev_minor == "0" } {
+ set rev_minor_str "*"
+ } else {
+ set rev_minor_str [expr {$rev_minor - 1} ]
+ }
+
+ set rev_str "[format %c [expr {$rev_major + 0x40}]]$rev_minor"
+ echo "** Silicon: 0x$siid, Family: 0x$family, Rev.: 0x$revision (${rev_major_str}${rev_minor_str})"
+ }
+
+ if { [dict exists $MPN $siid] } {
+ set PN [lindex $MPN($siid) 0]
+ set DIE [lindex $MPN($siid) 1]
+ set SERIES [lindex $MPN($siid) 4]
+ set main_size [lindex $MPN($siid) 2]
+ set work_size [lindex $MPN($siid) 3]
+ echo "** Detected Device: $PN"
+ check_die_matches_driver $DIE $SERIES
+ return [list $main_size $work_size]
+ } else {
+ echo "** Device is not present in the UDD"
+ }
+
+ return {}
+}
diff --git a/scripts/target/mxs40/cyw20829_common.cfg b/scripts/target/mxs40/cyw20829_common.cfg
new file mode 100644
index 0000000..f2eedc8
--- /dev/null
+++ b/scripts/target/mxs40/cyw20829_common.cfg
@@ -0,0 +1,223 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Common configuration for CYW20829 family of microcontrollers.
+#
+
+source [find target/swj-dp.tcl]
+source [find target/mxs40/mxs40v2_common.cfg]
+
+global _CHIPNAME
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME cyw20829
+}
+
+if { [info exists WORKAREAADDR] } {
+ set _WA_ADDR $WORKAREAADDR
+ unset WORKAREAADDR
+} else {
+ # Top of RAM for devices with 64KB of RAM (0x20010000) - _WA_SIZE (0x8000) = 0x20008000)
+ set _WA_ADDR 0x20008000
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WA_SIZE $WORKAREASIZE
+ unset WORKAREASIZE
+} else {
+ # TODO: 32KB is not enought for current loaders
+ #set _WA_SIZE 0x8000
+ set _WA_SIZE 0x10000
+}
+
+global _QSPI_FLASHLOADER
+if { [info exists QSPI_FLASHLOADER] } {
+ set _QSPI_FLASHLOADER $QSPI_FLASHLOADER
+} else {
+ set _QSPI_FLASHLOADER ../flm/cypress/cat1b/CYW208xx_SMIF.FLM
+}
+
+global TARGET
+set TARGET $_CHIPNAME
+
+###############################################################################
+# SWJ settings
+###############################################################################
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+# Turn on hprot[0] bit in SysAP's AP->CSW register to allow data writes via SysAP
+$_CHIPNAME.dap apsel 0
+$_CHIPNAME.dap apcsw [expr {1 << 24}]
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 4
+}
+
+###############################################################################
+# Reset / Acquire
+###############################################################################
+
+target create ${TARGET}.sysap mem_ap -dap $_CHIPNAME.dap -ap-num 0 -coreid 255
+target create ${TARGET}.cm33ap mem_ap -dap $_CHIPNAME.dap -ap-num 1 -coreid 255
+target create ${TARGET}.cm33 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+${TARGET}.cm33 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE
+
+# Only SRST reset works correctly, SYSRESETREQ + VC_CORERESET causes debug pins been
+# left disconnected due to known silicon design limitation
+reset_config srst_only
+${TARGET}.cm33ap configure -event reset-assert {}
+${TARGET}.cm33 configure -event reset-assert {}
+${TARGET}.cm33 configure -event reset-deassert-post "mxs40v2_reset_deassert_post ${TARGET}.cm33"
+
+$_CHIPNAME.dap configure -event init-fail [subst -nocommands {
+ puts stderr "** DAP is not accessible, trying to acquire in Test Mode"
+ if { ![mxs40v2::acquire_xres $_CHIPNAME.dap 0] } {
+ puts stderr "** Target initialization failed (check connection, power, transport, DAP is enabled etc.)"
+ terminate
+ }
+}]
+
+${TARGET}.sysap configure -event examine-end [subst -nocommands {
+ mxs40v2::display_chip_info $_CHIPNAME
+}]
+
+${TARGET}.sysap configure -event reset-assert {
+ # This is the main Reset procedure, built-ins are overridden
+ if { $::RESET_MODE eq "run" } {
+ mxs40v2::toggle_xres
+ return
+ }
+
+ mxs40v2::acquire_xres
+# TODO: Keep it for a while, maybe WFA->TEST_MODE request will be implemented
+# TODO: if { ![mxs40v2::acquire_xres] && ![mxs40v2::acquire_wfa $TEST_MODE_REQ_HERE] } {}
+}
+
+proc send_certificate {} {
+ global DEBUG_CERTIFICATE
+ global DEBUG_CERTIFICATE_ADDR
+
+ if { ![file exists $DEBUG_CERTIFICATE]} {
+ puts stderr "** Could not open certificate file '$DEBUG_CERTIFICATE'"
+ error {}
+ }
+
+ if {![info exists DEBUG_CERTIFICATE_ADDR]} {
+ set DEBUG_CERTIFICATE_ADDR 0x2000FC00
+ }
+
+ set sys_ap [find_core "sysap"]
+ targets $sys_ap
+
+ mxs40v2::acquire_wfa 2
+ load_image $DEBUG_CERTIFICATE $DEBUG_CERTIFICATE_ADDR
+ mww $::mxs40v2::SRSS_TST_DEBUG_CTL_ADDR 0
+ sleep 25
+
+ set cm33_target [find_core "cm33"]
+ targets $cm33_target
+
+ if {[mxs40v2::wait_for_ap_open] == 0} {
+ targets $sys_ap
+ set boot_status [mxs40v2::decode_boot_status [mrw $::mxs40v2::RAM_BOOT_STATUS_ADDR]]
+ puts stderr "** CM33 AP still closed, Boot Status: $boot_status"
+ error {}
+ }
+
+ $cm33_target arp_examine
+ $cm33_target arp_poll
+ $cm33_target arp_poll
+}
+
+proc find_core { suffix } {
+ set t [target current]
+ set sep [string last "." $t]
+ return [string range $t 0 [expr {$sep - 1}]].$suffix
+}
+
+${TARGET}.cm33ap configure -event examine-end {
+ global DEBUG_CERTIFICATE
+
+ set target [target current]
+ set cm33_target [string map {cm33ap cm33} $target]
+ set sysap_target [string map {cm33ap sysap} $target]
+
+ if { ![mxs40v2::is_ap_open] } {
+ if [info exists DEBUG_CERTIFICATE] {
+ echo "** CM33 AP is closed, sending debug certificate"
+ if [catch {send_certificate}] {
+ puts stderr "** Error sending debug certificate, examination skipped"
+ $cm33_target configure -defer-examine
+ targets $sysap_target
+ return
+ }
+ } else {
+ puts stderr "** CM33 AP is closed and no certificate specified, examination skipped"
+ puts stderr "** Use 'DEBUG_CERTIFICATE' variable to specify certificate filename with full path"
+ $cm33_target configure -defer-examine
+ targets $sysap_target
+ return
+ }
+ }
+
+ # make sure CM33 is examined without need for "reset init"
+ if {[$cm33_target cget -defer-examine] == 0} {
+ targets $cm33_target
+ $cm33_target arp_examine
+ $cm33_target arp_poll
+ $cm33_target arp_poll
+ }
+}
+
+
+###############################################################################
+# SMIF (QSPI) flash bank
+###############################################################################
+
+# example of qspi_config.cfg
+#set SMIF_BANKS {
+# 0 {addr 0x60000000 size 0x10000 psize 0x100 esize 0x1000}
+# 1 {addr 0x60010000 size 0x10000 psize 0x100 esize 0x1000}
+# 2 {addr 0x60020000 size 0x10000 psize 0x100 esize 0x1000}
+# 3 {addr 0x60030000 size 0x10000 psize 0x100 esize 0x1000}
+#}
+
+catch {source [find qspi_config.cfg]}
+if { [info exists SMIF_BANKS] } {
+
+ set num_banks [array size SMIF_BANKS]
+ set bank_param ""
+ if { $num_banks > 1 } {
+ set bank_param "prefer_sector_erase"
+ }
+
+ # flash bank [driver_options ...]
+ # cmsis_flash driver options: [prefer_sector_erase]
+ foreach {key value} [array get SMIF_BANKS] {
+ if { $value(addr) < 0x60000000 || [expr {$value(addr) + $value(size)}] > 0x68000000 } {
+ puts stderr "** Flash bank ${_CHIPNAME}_smif${key}_cm33 crosses XIP address region!"
+ continue
+ }
+
+ flash bank ${_CHIPNAME}_smif${key}_cm33 cmsis_flash $value(addr) $value(size) 4 4 ${TARGET}.cm33 $_QSPI_FLASHLOADER 0x800 {*}$bank_param
+ add_verify_range ${TARGET}.cm33 $value(addr) $value(size)
+
+ set virtual_addr [expr {$value(addr) - 0x5C000000}]
+ flash bank ${_CHIPNAME}_smif${key}_cbus virtual $virtual_addr $value(size) 4 4 ${TARGET}.cm33 ${_CHIPNAME}_smif${key}_cm33
+ add_verify_range ${TARGET}.cm33 $virtual_addr $value(size)
+ }
+}
+
+gdb_smart_program enable
+
+###############################################################################
+# Target info
+###############################################################################
+
+proc check_flashboot_version {} {
+# TODO: Implement check_flashboot_version. Check the same function in psoc6_common.cfg
+}
+
diff --git a/scripts/target/mxs40/cyw20829_status_codes.cfg b/scripts/target/mxs40/cyw20829_status_codes.cfg
new file mode 100644
index 0000000..06adec9
--- /dev/null
+++ b/scripts/target/mxs40/cyw20829_status_codes.cfg
@@ -0,0 +1,141 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Definition of CYW20829 ROMBoot and ServiceApps status codes
+#
+
+if [info exist LOADED_[file rootname [file tail [info script]]]] return
+set LOADED_[file rootname [file tail [info script]]] true
+
+set ::mxs40v2::cyw20829_boot_status_codes {
+ { CYBOOT_NEXT_APP_LAUNCHED 0x0D500067 }
+ { CYBOOT_IDLE_BRANCH_REACHED 0x0D500068 }
+ { CYBOOT_WFA_POLLING 0x0D500080 }
+ { CYBOOT_SERVICE_APP_LAUNCHED 0x0D500081 }
+ { CYBOOT_SERVICE_APP_NOT_LAUNCHED 0x0D500082 }
+ { CYBOOT_WFA_REQUEST_INVALID 0x0D500083 }
+ { CYBOOT_DEBUG_CERT_PASSED 0x0D500084 }
+ { CYBOOT_DEBUG_CERT_FAILED 0x0D500085 }
+ { CYBOOT_SUCCESS 0x0D50B002 }
+ { CYBOOT_BAD_PARAM 0xBAF00001 }
+ { CYBOOT_LOCKED 0xBAF00002 }
+ { CYBOOT_STARTED 0xBAF00003 }
+ { CYBOOT_FINISHED 0xBAF00004 }
+ { CYBOOT_CANCELED 0xBAF00005 }
+ { CYBOOT_TIMEOUT 0xBAF00006 }
+ { CYBOOT_NOT_IMPLEMENTED 0xBAF00007 }
+ { CYBOOT_FAILED 0xBAF00008 }
+ { CYBOOT_FI_DETECTED 0xBAF00009 }
+ { CYBOOT_TOC2_OBJ_INVALID 0xBAF00010 }
+ { CYBOOT_L1_APP_DESCR_INVALID 0xBAF00011 }
+ { CYBOOT_TOC2_DEBUG_CERT_ADDR_EMPTY 0xBAF00012 }
+ { CYBOOT_SERV_APP_DESCR_INVALID 0xBAF00013 }
+ { CYBOOT_BOOTROW_READ_FAILED 0xBAF00020 }
+ { CYBOOT_BOOTROW_CORRUPTED 0xBAF00021 }
+ { CYBOOT_OTP_INIT_FAILED 0xBAF00022 }
+ { CYBOOT_OTP_READ_FAILED 0xBAF00023 }
+ { CYBOOT_OTP_WRITE_FAILED 0xBAF00024 }
+ { CYBOOT_OTP_SMIF_CFG_INVALID 0xBAF00025 }
+ { CYBOOT_PUBKEY_REQUEST_FAILED 0xBAF00030 }
+ { CYBOOT_PUBKEY_FORMAT_INVALID 0xBAF00031 }
+ { CYBOOT_PUBKEY_VALIDATION_FAILED 0xBAF00032 }
+ { CYBOOT_PUBKEY_HASH_PTE_INVALID 0xBAF00033 }
+ { CYBOOT_PUBKEY_HASH_ICV_INVALID 0xBAF00034 }
+ { CYBOOT_PUBKEY_HASH_OEM_INVALID 0xBAF00035 }
+ { CYBOOT_APP_VALIDATION_FAILED 0xBAF00036 }
+ { CYBOOT_APP_LAUNCH_ADDR_INVALID 0xBAF00037 }
+ { CYBOOT_SIGNATURE_INVALID 0xBAF00038 }
+ { CYBOOT_MCUBOOT_INTERNAL_ASSERT 0xBAF00039 }
+ { CYBOOT_RAM_APP_FORMAT_INVALID 0xBAF0003A }
+ { CYBOOT_SMIF_INIT_FAILED 0xBAF00040 }
+ { CYBOOT_SMIF_DEINIT_FAILED 0xBAF00041 }
+ { CYBOOT_SMIF_READ_FAILED 0xBAF00042 }
+ { CYBOOT_SMIF_WRITE_FAILED 0xBAF00043 }
+ { CYBOOT_SMIF_ERASE_FAILED 0xBAF00044 }
+ { CYBOOT_SMIF_GET_SECTOR_SIZE_FAILED 0xBAF00045 }
+ { CYBOOT_SMIF_UNUSED 0xBAF00046 }
+ { CYBOOT_SMIF_CONFIG_EMPTY 0xBAF00047 }
+ { CYBOOT_SMIF_APP_DESCR_INVALID 0xBAF00048 }
+ { CYBOOT_FLASH_ADDRESS_INVALID 0xBAF00049 }
+ { CYBOOT_NUM_ZEROS_0_INVALID 0xBAF00050 }
+ { CYBOOT_NUM_ZEROS_1_INVALID 0xBAF00051 }
+ { CYBOOT_NUM_ZEROS_2_INVALID 0xBAF00052 }
+ { CYBOOT_NUM_ZEROS_3_INVALID 0xBAF00053 }
+ { CYBOOT_NUM_ZEROS_KEY_0_HASH_INVALID 0xBAF00054 }
+ { CYBOOT_NUM_ZEROS_KEY_1_HASH_INVALID 0xBAF00055 }
+ { CYBOOT_BIST_FAILED 0xBAF00060 }
+ { CYBOOT_SAFE_MODE_REACHED 0xBAF00061 }
+ { CYBOOT_DFT_EN_REACHED 0xBAF00062 }
+ { CYBOOT_RESOURCES_DEINIT_FAILED 0xBAF00063 }
+ { CYBOOT_DS_ADDR_INVALID 0xBAF00064 }
+ { CYBOOT_RMA_RESTRICT_INVALID 0xBAF00065 }
+ { CYBOOT_BASIC_TRIM_WRITE_FAILED 0xBAF00069 }
+ { CYBOOT_FULL_TRIM_WRITE_FAILED 0xBAF0006A }
+ { CYBOOT_LCS_UNEXPECTED 0xBAF0006B }
+ { CYBOOT_WARM_BOOT_NOT_SUPPORTED 0xBAF0006C }
+ { CYBOOT_PROT_APPLY_PROT_FAILURE 0xBAF00070 }
+ { CYBOOT_PROT_CFG_SKIPPED 0xBAF00071 }
+ { CYBOOT_PROT_ID_DEBUG_INVALID 0xBAF00072 }
+ { CYBOOT_PROT_ID_APPLY_INVALID 0xBAF00073 }
+ { CYBOOT_PROT_ID_FINISH_INVALID 0xBAF00074 }
+ { CYBOOT_CM33_RESTRICT_INVALID 0xBAF00075 }
+ { CYBOOT_SYS_RESTRICT_INVALID 0xBAF00076 }
+ { CYBOOT_PROT_APP_SECT_VERIF_FAILED 0xBAF00077 }
+ { CYBOOT_PROT_MPC_CFG_FAILED 0xBAF00078 }
+ { CYBOOT_PROT_PPC_CFG_FAILED 0xBAF00079 }
+ { CYBOOT_PROT_WOUNDING_CFG_FAILED 0xBAF0007A }
+ { CYBOOT_PROT_MS_CTL_CFG_FAILED 0xBAF0007B }
+ { CYBOOT_DEBUG_CERT_VERIF_FAILED 0xBAF0007C }
+ { CYBOOT_SHA256_INIT_FAILED 0xBAF00090 }
+ { CYBOOT_SHA256_CALC_FAILED 0xBAF00091 }
+ { CYBOOT_IMG_INVALID 0xBAF000A0 }
+ { CYBOOT_FLASH_AREA_INVALID 0xBAF000AD }
+ { CYBOOT_TLV_INVALID 0xBAF000AE }
+ { CYBOOT_TLV_NO_MORE_FOUND 0xBAF000AF }
+}
+
+foreach status_code $::mxs40v2::cyw20829_boot_status_codes {
+ set ::mxs40v2::[lindex $status_code 0] [lindex $status_code 1]
+}
+
+set ::mxs40v2::cyw20829_app_status_codes {
+ { CYAPP_BAD_PARAM 0x45000002 }
+ { CYAPP_LOCKED 0x45000003 }
+ { CYAPP_STARTED 0x45000004 }
+ { CYAPP_FINISHED 0x45000005 }
+ { CYAPP_CANCELED 0x45000006 }
+ { CYAPP_TIMEOUT 0x45000007 }
+ { CYAPP_OTP_INIT_FAILED 0x45000020 }
+ { CYAPP_OTP_BOOTROW_WRITE_FAILED 0x45000021 }
+ { CYAPP_OTP_BOOTROW_READ_FAILED 0x45000022 }
+ { CYAPP_OTP_WRITE_FAILED 0x45000023 }
+ { CYAPP_OTP_READ_FAILED 0x45000024 }
+ { CYAPP_LCS_INVALID 0x45000030 }
+ { CYAPP_OEM_KEY_ALREADY_REVOKED 0x45000031 }
+ { CYAPP_ICV_KEY_ALREADY_REVOKED 0x45000032 }
+ { CYAPP_SIGNATURE_VERIF_FAILED 0x45000033 }
+ { CYAPP_KEY_0_ALREADY_PROGRAMMED 0x45000034 }
+ { CYAPP_KEY_1_ALREADY_PROGRAMMED 0x45000035 }
+ { CYAPP_OEM_ASSETS_ALREADY_PROGRAMMED 0x45000036 }
+ { CYAPP_PARAM_NV_CNT_INVALID 0x45000100 }
+ { CYAPP_PARAM_OEM_KEY_0_HASH_INVALID 0x45000101 }
+ { CYAPP_PARAM_OEM_KEY_1_HASH_INVALID 0x45000102 }
+ { CYAPP_PARAM_PUBKEY_INVALID 0x45000103 }
+ { CYAPP_PARAM_CONTROL_WORD_INVALID 0x45000104 }
+ { CYAPP_PARAM_TARGET_LCS_INVALID 0x45000105 }
+ { CYAPP_RMA_CERT_VERIF_FAILED 0x45000106 }
+ { CYAPP_PARAM_ACCESS_RESTRICT_INVALID 0x45000107 }
+ { CYAPP_SMIF_INIT_FAILED 0x4500FFF0 }
+ { CYAPP_SMIF_WRITE_FAILED 0x4500FFF1 }
+ { CYAPP_SMIF_READ_FAILED 0x4500FFF2 }
+ { CYAPP_SMIF_VERIF_FAILED 0x4500FFF3 }
+ { CYAPP_SMIF_ERASE_FAILED 0x4500FFF4 }
+ { CYAPP_SMIF_GET_SECTOR_SIZE_FAILED 0x4500FFF5 }
+ { CYAPP_SUCCESS 0xF2A00001 }
+ { CYAPP_APP_RUNNING 0xF2A00010 }
+}
+
+foreach status_code $::mxs40v2::cyw20829_app_status_codes {
+ set ::mxs40v2::[lindex $status_code 0] [lindex $status_code 1]
+}
diff --git a/scripts/target/mxs40/migration.cfg b/scripts/target/mxs40/migration.cfg
new file mode 100644
index 0000000..75f9c62
--- /dev/null
+++ b/scripts/target/mxs40/migration.cfg
@@ -0,0 +1,39 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Migration aids for deprecated global variables
+#
+
+if { [info exists WORKAREAADDR_CM0] } {
+ puts stderr "** The 'WORKAREAADDR_CM0' variable is deprecated, please use 'WORKAREAADDR'"
+ set WORKAREAADDR $WORKAREAADDR_CM0
+ unset WORKAREAADDR_CM0
+}
+
+if { [info exists WORKAREASIZE_CM0] } {
+ puts stderr "** The 'WORKAREASIZE_CM0' variable is deprecated, please use 'WORKAREASIZE'"
+ set WORKAREASIZE $WORKAREASIZE_CM0
+ unset WORKAREASIZE_CM0
+}
+
+if { [info exists WORKAREAADDR_CM4] } {
+ puts stderr "** The 'WORKAREAADDR_CM4' variable is deprecated, please use 'WORKAREAADDR'"
+ set WORKAREAADDR $WORKAREAADDR_CM4
+ unset WORKAREAADDR_CM4
+}
+
+if { [info exists WORKAREASIZE_CM4] } {
+ puts stderr "** The 'WORKAREASIZE_CM4' variable is deprecated, please use 'WORKAREASIZE'"
+ set WORKAREASIZE $WORKAREASIZE_CM4
+ unset WORKAREASIZE_CM4
+}
+
+if { [info proc acquire] eq "" } {
+ proc acquire { target } {
+ puts stderr "** The 'acquire' command is deprecated, please use 'mxs40_acquire'"
+ mxs40_acquire $target
+ }
+ add_usage_text acquire "target"
+ add_help_text acquire "Acquires the device in Test Mode"
+}
diff --git a/scripts/target/mxs40/mxs40_common.cfg b/scripts/target/mxs40/mxs40_common.cfg
new file mode 100644
index 0000000..043921b
--- /dev/null
+++ b/scripts/target/mxs40/mxs40_common.cfg
@@ -0,0 +1,278 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Common configuration for MXS40 family of microcontrollers.
+#
+
+source [find target/mxs40/migration.cfg]
+
+global _MXS40_COMMON_LOADED
+if [info exist _MXS40_COMMON_LOADED] return
+
+source [find mem_helper.tcl]
+source [find target/mxs40/cy_get_set_device_param.cfg]
+set _MXS40_COMMON_LOADED true
+
+###############################################################################
+# Mapping between DIEs from the MPN database and their configuration files
+###############################################################################
+set MXS40_DIE_CONFIG_DICT [dict create \
+ PSoC6ABLE2 psoc6.cfg \
+ PSoC6A256K psoc6_256k.cfg \
+ PSoC6A512K psoc6_512k.cfg \
+ PSoC6A2M psoc6_2m.cfg \
+]
+
+###############################################################################
+# Default speed an reset settings
+###############################################################################
+if {[using_jtag]} {
+ adapter speed 1000
+} else {
+ adapter speed 2000
+}
+
+adapter srst delay 25
+adapter srst pulse_width 25
+
+###############################################################################
+# Acquires the device in Test Mode
+###############################################################################
+proc mxs40_acquire { target } {
+ global _ENABLE_ACQUIRE
+ if { $_ENABLE_ACQUIRE == 0 } {
+ echo "*******************************************************************"
+ echo "* Test Mode acquire disabled. Use 'set ENABLE_ACQUIRE 1' to enable"
+ echo "*******************************************************************"
+ return
+ }
+
+ # acquire will leave CPU in running state
+ # openocd does not expect this
+ # ignore possible error e.g. when listen window is disabled
+ catch {kitprog3 acquire_psoc}
+
+ # we need to re-examine and halt target manually
+ ${target} arp_examine
+ ${target} arp_poll
+
+ if { [$target curstate] eq "reset" } {
+ $target arp_poll
+ }
+
+ # Ensure target has stopped on WFI instruction
+ set loops 2000
+ while { $loops } {
+ set sleeping [ expr {[mrw 0xE000EDF0] & 0x00040000} ]
+ if { $sleeping } break
+ set loops [ expr {$loops - 1} ]
+ }
+
+ if { $sleeping } {
+ ${target} arp_halt
+ ${target} arp_waitstate halted 100
+ echo "** Device acquired successfully"
+ return
+ }
+
+ puts stderr "********************************************"
+ puts stderr "* Failed to acquire the device in Test Mode"
+ puts stderr "********************************************"
+}
+add_usage_text mxs40_acquire "target"
+add_help_text mxs40_acquire "Acquires the device in Test Mode"
+
+###############################################################################
+# Erases all non-virtual flash banks (in reverse order)
+###############################################################################
+proc erase_all {} {
+ lset banks [flash list]
+ set banks_count [llength $banks]
+ for {set i [expr {$banks_count - 1}]} { $i >= 0 } { set i [expr {$i - 1}]} {
+ set bank [lindex $banks $i]
+ set bank_name $bank(name)
+ echo [format "Erasing flash bank \"%s\" (%d of %d)..." $bank_name [expr {$banks_count - $i}] $banks_count ]
+ if { $bank_name != "virtual" } {
+ flash erase_sector $i 0 last
+ } else {
+ echo "skipped (virtual)"
+ }
+ }
+}
+add_help_text erase_all "Erases all non-virtual flash banks (in reverse order, for SMIF compatibility)"
+
+###############################################################################
+# Utility to make 'reset halt' work as reset;halt on a target
+# It does not prevent running code after reset
+###############################################################################
+proc mxs40_reset_deassert_post { target_type target } {
+ global _ENABLE_ACQUIRE
+ global RESET_MODE
+
+ # MXS40 cleared AP registers including TAR during reset
+ # Force examine to synchronize OpenOCD target status
+ $target arp_examine
+ $target arp_poll
+
+ # Exit if $target is supposed to be running after Reset
+ if { $RESET_MODE eq "run" } return
+
+ # Check if $target is a primary core (cm0 for TRAVEO™II)
+ set is_primary_core [string match "*cm0" $target]
+
+ if { $is_primary_core } {
+ if { $_ENABLE_ACQUIRE } {
+ mxs40_acquire $target
+ } else {
+ $target_type reset_halt sysresetreq
+ }
+ check_flashboot_version
+ } else {
+ if { [$target curstate] eq "reset" } {
+ $target arp_poll
+ }
+
+ if { [$target curstate] eq "running" } {
+ echo "** $target: Ran after reset and before halt..."
+ $target arp_halt
+ $target arp_waitstate halted 100
+ }
+ }
+}
+
+# Define check_flashboot_version if not already defined
+# It is used on PSoC6 only to detect pre-production chips
+if { [info proc check_flashboot_version] eq "" } {
+ proc check_flashboot_version {} {}
+}
+
+###############################################################################
+# Tries to detect SMIF geometry by parsing TOC2
+###############################################################################
+proc detect_smif {{sflash_base 0x16000000}} {
+
+ set cfg_ptr [mrw [mrw [ expr {$sflash_base + 62 * 512 + 0x0C} ]]]
+ if { $cfg_ptr == 0 || $cfg_ptr == 0xFFFFFFFF || $cfg_ptr < 0x10000000 || $cfg_ptr > 0x10200000 } {
+ echo "** SMIF configuration structure not found or invalid"
+ return
+ }
+ set chip_num [mrw $cfg_ptr]
+ set chip_cfg_arry_p [mrw [expr {$cfg_ptr + 4}]]
+
+ echo ""
+ for {set i 0} {$i < $chip_num} {incr i} {
+ set chip_cfg [mrw [expr {$chip_cfg_arry_p + 4 * $i}]]
+ set region_base [mrw [expr {$chip_cfg + 12}]]
+ set region_size [mrw [expr {$chip_cfg + 16}]]
+ set phys_cfg [mrw [expr {$chip_cfg + 24}]]
+ set erase_size [mrw [expr {$phys_cfg + 24}]]
+ set prgm_size [mrw [expr {$phys_cfg + 36}]]
+
+ echo "### SMIF region #${i} - Erase Size: 0x[format %X $erase_size], Program Size: 0x[format %X $prgm_size]"
+ echo "set SMIF_BANKS {1 {addr 0x[format %08X $region_base] size 0x[format %08X $region_size] psize 0x[format %X $prgm_size] esize 0x[format %X $erase_size]}}"
+ }
+}
+add_usage_text detect_smif "sflash_base (optional, 0x16000000 by default)"
+add_help_text detect_smif "Detects SMIF regions and displays flash bank configuration"
+
+###############################################################################
+# Overrides default init_reset procedure, stores reset mode in global variable
+###############################################################################
+proc init_reset { mode } {
+ global RESET_MODE
+ set RESET_MODE $mode
+}
+
+###############################################################################
+# Handles GDB extended 'restart' command
+###############################################################################
+proc ocd_gdb_restart {target} {
+ if [string match "*cm0" $target ] {
+ reset init
+ psoc6 reset_halt sysresetreq
+ } else {
+ reset run
+ sleep 200
+ psoc6 reset_halt sysresetreq
+ }
+}
+
+###############################################################################
+# Power dropout/restore handlers
+###############################################################################
+proc power_dropout {} {
+ if { [adapter name] eq "kitprog3" } {
+ local_echo off
+ set voltage [regexp -inline -- {[0-9]+\.[0-9]+} [kitprog3 get_power]]
+ local_echo on
+ puts stderr "Power dropout, target voltage: $voltage mV"
+ }
+}
+
+proc power_restore {} {
+ if { [adapter name] eq "kitprog3" } {
+ local_echo off
+ set voltage [regexp -inline -- {[0-9]+\.[0-9]+} [kitprog3 get_power]]
+ local_echo on
+ puts stderr "Power restore, target voltage: $voltage mV"
+ }
+}
+
+###############################################################################
+# KitProg3 acquire/power control stuff
+###############################################################################
+global _ENABLE_ACQUIRE
+global _ENABLE_POWER_SUPPLY
+
+if {[using_jtag]} {
+ set ENABLE_ACQUIRE 0
+ echo "** Test Mode acquire disabled (not supported in JTAG mode)"
+}
+
+if { [adapter name] eq "kitprog3" } {
+ if { [info exists ENABLE_ACQUIRE] } {
+ if { ( $ENABLE_ACQUIRE != 0 ) && ( $ENABLE_ACQUIRE != 1 ) && ( $ENABLE_ACQUIRE != 2 ) } {
+ puts stderr "** Invalid ENABLE_ACQUIRE value ($ENABLE_ACQUIRE). Allowed values are:"
+ puts stderr "** 0 - Test Mode acquisition is disabled"
+ puts stderr "** 1 - Enable acquisition using XRES method"
+ puts stderr "** 2 - Enable acquisition using power-cycle method"
+ terminate
+ }
+
+ if { $ENABLE_ACQUIRE == 2 && ![info exists ENABLE_POWER_SUPPLY] } {
+ set ENABLE_POWER_SUPPLY default
+ }
+
+ set _ENABLE_ACQUIRE $ENABLE_ACQUIRE
+ } else {
+ set _ENABLE_ACQUIRE 1
+ }
+
+ if { [info exists ENABLE_POWER_SUPPLY] } {
+ set _ENABLE_POWER_SUPPLY $ENABLE_POWER_SUPPLY
+ } else {
+ set _ENABLE_POWER_SUPPLY 0
+ }
+} else {
+ set _ENABLE_ACQUIRE 0
+ set _ENABLE_POWER_SUPPLY 0
+ echo "** Test Mode acquire not supported by selected adapter"
+}
+
+if { $_ENABLE_ACQUIRE } {
+ echo "** Auto-acquire enabled, use \"set ENABLE_ACQUIRE 0\" to disable"
+}
+
+if { [string is integer $_ENABLE_POWER_SUPPLY]} {
+ if { $_ENABLE_POWER_SUPPLY } {
+ echo "** Enabling target power ($_ENABLE_POWER_SUPPLY mV) \"set ENABLE_POWER_SUPPLY 0\" to disable"
+ kitprog3 power_config on $_ENABLE_POWER_SUPPLY
+ }
+} elseif { $_ENABLE_POWER_SUPPLY == "default" } {
+ echo "** Enabling target power (default voltage) \"set ENABLE_POWER_SUPPLY 0\" to disable"
+ kitprog3 power_config on
+} else {
+ puts stderr "Invalid ENABLE_POWER_SUPPLY value - '$_ENABLE_POWER_SUPPLY' (integer or 'default' expected)"
+ terminate
+}
diff --git a/scripts/target/mxs40/mxs40v2_acquire_helpers.cfg b/scripts/target/mxs40/mxs40v2_acquire_helpers.cfg
new file mode 100644
index 0000000..01ce4c4
--- /dev/null
+++ b/scripts/target/mxs40/mxs40v2_acquire_helpers.cfg
@@ -0,0 +1,798 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Acquisition helpers for MXS40v2 family of microcontrollers.
+#
+
+if [info exist LOADED_[file rootname [file tail [info script]]]] return
+set LOADED_[file rootname [file tail [info script]]] true
+
+source [find target/cympn.cfg]
+source [find target/mxs40/cyw20829_status_codes.cfg]
+
+namespace eval mxs40v2 {
+
+variable CYBOOT_ID_MASK 0xFFF00000
+variable CYBOOT_ID_FAIL 0xBAF00000
+variable CYBOOT_ID_SUCCESS 0x0D500000
+variable CYAPP_ID_MASK 0xFFF00000
+variable CYAPP_ID_FAIL 0x45000000
+variable CYAPP_ID_SUCCESS 0xF2A00000
+
+variable ACQUIRE_TIMEOUT 2500
+variable EFUSE_BOOTROW_ADDR 0x40810180
+variable EFUSE_CTRL_ADDR 0x40810000
+variable EFUSE_DEVICE_ID_ADDR 0x40810878
+variable EFUSE_SI_REV_ID_ADDR 0x4081087C
+variable NVIC_VTOR_ADDR 0xE000ED08
+variable RAM_BOOT_BUILD_ADDR 0x20000008
+variable RAM_BOOT_STATUS_ADDR 0x20000000
+variable RAM_BOOT_VERSION_ADDR 0x20000004
+variable SRSS_RES_SOFT_CTL_ADDR 0x40200410
+variable SRSS_RES_SOFT_CTL_RESET_MASK 0x00000001
+variable SRSS_TST_DEBUG_CTL_ADDR 0x40200404
+variable SRSS_TST_DEBUG_CTL_WFA_MASK 0x80000000
+variable SRSS_TST_DEBUG_CTL_WFA_REQ 0x00000001
+variable SRSS_TST_DEBUG_STATUS_ADDR 0x40200408
+variable SRSS_TST_MODE_ADDR 0x40200400
+variable SRSS_TST_MODE_MASK 0x80000000
+
+namespace eval priv {
+
+ variable push_count 0
+ variable pushed_log_level 0
+
+ proc push_log_settings {} {
+ variable push_count
+ variable pushed_log_level
+
+ if { $push_count == 0 } {
+ local_echo off
+ scan [debug_level] "debug_level: %d" pushed_log_level
+ debug_level -1
+ }
+ incr push_count
+ }
+
+ proc pop_log_settings {} {
+ variable push_count
+ variable pushed_log_level
+
+ if { $push_count == 0 } {
+ puts stderr "push/pop log settings mismatch"
+ } else {
+ incr push_count -1
+ }
+
+ if { $push_count == 0 } {
+ debug_level $pushed_log_level
+ local_echo on
+ }
+ }
+
+ proc default_dap_ap { dap_name ap_num } {
+ upvar $dap_name dap
+ upvar $ap_num ap
+
+ set target [target current]
+ set dap [expr {$dap ne {} ? $dap : [$target cget -dap]}]
+ set ap [expr {$ap ne {} ? $ap : [$target cget -ap-num]}]
+ }
+
+ proc read32 { dap ap address } {
+ push_log_settings
+ catch {
+ $dap apreg $ap 0x00 0xAB000002
+ $dap apreg $ap 0x04 $address
+ $dap apreg $ap 0x0C
+ } result options
+ pop_log_settings
+ return {*}$options [string trim $result]
+ }
+
+ proc write32 { dap ap address val } {
+ $dap apreg $ap 0x00 0xAB000002
+ $dap apreg $ap 0x04 $address
+ $dap apreg $ap 0x0C $val
+ }
+
+ proc is_idle_loop { dap ap } {
+ variable [namespace parent]::CYBOOT_ID_FAIL
+ variable [namespace parent]::CYBOOT_ID_MASK
+ variable [namespace parent]::CYBOOT_ID_SUCCESS
+ variable [namespace parent]::CYBOOT_NEXT_APP_LAUNCHED
+ variable [namespace parent]::CYBOOT_WFA_POLLING
+ variable [namespace parent]::RAM_BOOT_STATUS_ADDR
+ variable [namespace parent]::SRSS_TST_DEBUG_CTL_ADDR
+ variable [namespace parent]::SRSS_TST_DEBUG_CTL_WFA_MASK
+ variable [namespace parent]::SRSS_TST_DEBUG_STATUS_ADDR
+
+ if [catch {read32 $dap $ap $SRSS_TST_DEBUG_STATUS_ADDR} mmio_status] {
+ return 0
+ }
+
+ if [catch {read32 $dap $ap $SRSS_TST_DEBUG_CTL_ADDR} debug_status] {
+ return 0
+ }
+
+ # CYBOOT_ID_FAIL in SRSS_TST_DEBUG_CTL_ADDR means device is CORRUPTED
+ # Return BREAK status to exit outer polling loop
+ if { [expr {$mmio_status & $CYBOOT_ID_MASK}] == $CYBOOT_ID_FAIL } {
+ return -code break
+ }
+
+ if {$mmio_status == $CYBOOT_WFA_POLLING &&
+ [expr {$debug_status & $SRSS_TST_DEBUG_CTL_WFA_MASK}]} {
+ return 1
+ }
+
+ if [catch {read32 $dap $ap $RAM_BOOT_STATUS_ADDR} ram_status] {
+ return 0
+ }
+
+ if { [expr {$ram_status & $CYBOOT_ID_MASK}] == $CYBOOT_ID_FAIL ||
+ [expr {$ram_status & $CYBOOT_ID_MASK}] == $CYBOOT_ID_SUCCESS &&
+ $ram_status != $CYBOOT_NEXT_APP_LAUNCHED } {
+ return 1
+ }
+
+ # CYBOOT_NEXT_APP_LAUNCHED means we've missed listen window
+ # Return BREAK status to exit outer polling loop
+ if {$ram_status == $CYBOOT_NEXT_APP_LAUNCHED} {
+ return -code break
+ }
+
+ return 0
+ }
+
+ proc do_reset { reset_mode dap ap } {
+ variable [namespace parent]::SRSS_RES_SOFT_CTL_ADDR
+ variable [namespace parent]::SRSS_RES_SOFT_CTL_RESET_MASK
+
+ if { $reset_mode > 2 } {
+ return 0
+ }
+
+ set RESET_METHODS { 0 "XRES pin" 1 "DP.CDBGRSTREQ" 2 "SRSS_RES_SOFT_CTL" }
+ echo "** Reset using $RESET_METHODS($reset_mode)"
+
+ if { $reset_mode == 0 } {
+ adapter assert srst
+ adapter deassert srst
+ } elseif { $reset_mode == 1 } {
+ catch {$dap dpreg 4 0xF4000040}
+ } elseif { $reset_mode == 2 } {
+ catch {write32 $dap $ap $SRSS_RES_SOFT_CTL_ADDR $SRSS_RES_SOFT_CTL_RESET_MASK}
+ }
+
+ return 1
+ }
+
+# namespace eval priv
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc wait_for_idle_loop { {dap {}} {ap {}} } {
+ variable ACQUIRE_TIMEOUT
+
+ priv::default_dap_ap dap ap
+
+ priv::push_log_settings
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+ priv::pop_log_settings
+
+ set ret 0
+ set t_end [expr {[clock milliseconds] + $ACQUIRE_TIMEOUT}]
+ while {[clock milliseconds] < $t_end} {
+ if [priv::is_idle_loop $dap $ap] {
+ set ret 1
+ break
+ }
+ }
+
+ priv::push_log_settings
+ eval poll $poll_status
+ priv::pop_log_settings
+ return $ret
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc is_ap_open { {dap {}} {ap {}} } {
+ priv::default_dap_ap dap ap
+ priv::push_log_settings
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+
+ set ret 0
+ # read location of the ROM Table to check if AP is opened
+ if ![catch {
+ set dbg_base [string trim [$dap apreg $ap 0xF8]]
+ priv::read32 $dap $ap $dbg_base
+ }] {
+ set ret 1
+ }
+
+ eval poll $poll_status
+ priv::pop_log_settings
+
+ return $ret
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc wait_for_ap_open { {dap {}} {ap {}} } {
+ variable ACQUIRE_TIMEOUT
+
+ priv::default_dap_ap dap ap
+
+ set ret 0
+ set t_end [expr {[clock milliseconds] + $ACQUIRE_TIMEOUT}]
+ while {[clock milliseconds] < $t_end} {
+ if {[is_ap_open $dap $ap]} {
+ set ret 1
+ break
+ }
+ }
+
+ return $ret
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc decode_lcs { bootrow } {
+ if { $bootrow == 0x00 } { return "VIRGIN" }
+ if { $bootrow == 0x29 } { return "SORT" }
+ if { [expr {$bootrow & 0x3F}] != 0x29 } { return "CORRUPTED" }
+
+ set tmp $bootrow
+ set tmp [expr {(($tmp >> 1 ) ^ $tmp ) & 0x00005540}]
+ if { $tmp != 0 } { return "CORRUPTED" }
+
+ set bootrow [expr {$bootrow & 0x0000FFC0}]
+
+ set lcs_table {
+ { "PROVISIONED" 0x00C0 }
+ { "NORMAL" 0xC000 }
+ { "NORMAL_NO_SECURE" 0xCC00 }
+ { "NORMAL_PROVISIONED" 0xC0C0 }
+ { "SECURE" 0xC3C0 }
+ { "RMA" 0xF000 }
+ { "RMA" 0xFC00 }
+ { "RMA" 0xF3C0 }
+ }
+
+ foreach lcs $lcs_table {
+ if { $bootrow == [lindex $lcs 1] } { return [lindex $lcs 0] }
+ }
+
+ return "CORRUPTED"
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc decode_boot_status { status } {
+ foreach val $::mxs40v2::cyw20829_boot_status_codes {
+ if { $status == [lindex $val 1] } { return [lindex $val 0] }
+ }
+
+ foreach val $::mxs40v2::cyw20829_app_status_codes {
+ if { $status == [lindex $val 1] } { return [lindex $val 0] }
+ }
+
+ return "None/Unknown ([format 0x%08X $status])"
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc display_chip_info { chipname {force no} {dap {}} {ap {}} } {
+# Run info command inly once for each particular chip, unless forced
+ global ${chipname}::info_runned
+ if { [info exists ${chipname}::info_runned] && $force != "force" } return
+ set ${chipname}::info_runned 1
+
+ variable CYBOOT_ID_FAIL
+ variable CYBOOT_ID_MASK
+ variable CYBOOT_SERVICE_APP_NOT_LAUNCHED
+ variable EFUSE_BOOTROW_ADDR
+ variable EFUSE_CTRL_ADDR
+ variable EFUSE_DEVICE_ID_ADDR
+ variable EFUSE_SI_REV_ID_ADDR
+ variable RAM_BOOT_BUILD_ADDR
+ variable RAM_BOOT_STATUS_ADDR
+ variable RAM_BOOT_VERSION_ADDR
+ variable SRSS_TST_DEBUG_STATUS_ADDR
+
+ priv::default_dap_ap dap ap
+ priv::push_log_settings
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+
+ set efuse_ctl 0
+ catch {priv::read32 $dap $ap $EFUSE_CTRL_ADDR} efuse_ctl
+ catch {priv::write32 $dap $ap $EFUSE_CTRL_ADDR [expr {$efuse_ctl | 0x80000000}]}
+
+ echo "***************************************"
+ set display_str "** "
+
+ if ![catch {priv::read32 $dap $ap $EFUSE_DEVICE_ID_ADDR} dev_id] {
+ set siid [format "%04X" [expr {$dev_id & 0xFFFF}]]
+ set family [format "%03X" [expr {($dev_id >> 16) & 0xFFF}]]
+ append display_str "Silicon: 0x$siid, Family: 0x$family"
+ }
+
+ if ![catch {priv::read32 $dap $ap $EFUSE_SI_REV_ID_ADDR} rev_id] {
+ set revision [format "%02X" [expr {$rev_id & 0xFF}]]
+ set rev_major "0x0[string index $revision 0]"
+ set rev_major_str [expr {$rev_major == 0 ? "?" : [format %c [expr {$rev_major + 0x40}]]}]
+ set rev_minor "0x0[string index $revision 1]"
+ set rev_minor_str [expr {$rev_minor == 0 ? "?" : [expr {$rev_minor - 1} ]}]
+ if {$display_str ne "** "} { append display_str ", " }
+ append display_str "Rev.: 0x$revision (${rev_major_str}${rev_minor_str})"
+ }
+
+ if {$display_str ne "** "} {
+ echo $display_str
+ }
+
+ if { [info exists siid] && [dict exists $::MPN $siid] } {
+ echo "** Detected Device: [lindex $::MPN($siid) 0]"
+ } else {
+ echo "** Device is not present in the UDD"
+ }
+
+ set lcs {}
+ if ![catch {priv::read32 $dap $ap $EFUSE_BOOTROW_ADDR} bootrow] {
+ set lcs [decode_lcs $bootrow]
+ echo "** Life Cycle : $lcs"
+ }
+
+ set is_corrupted 0
+ if ![catch {priv::read32 $dap $ap $SRSS_TST_DEBUG_STATUS_ADDR} mmio_status] {
+ if { [expr {$mmio_status & $CYBOOT_ID_MASK}] == $CYBOOT_ID_FAIL } {
+ echo "** Boot Status : [decode_boot_status $mmio_status]"
+ echo "** Reached CORRUPTED branch"
+ set is_corrupted 1
+ }
+ }
+
+ if { !$is_corrupted } {
+ if { ![catch {priv::read32 $dap $ap $RAM_BOOT_VERSION_ADDR} boot_version] &&
+ ![catch {priv::read32 $dap $ap $RAM_BOOT_BUILD_ADDR} boot_build] } {
+ set major [expr {($boot_version & 0xFF0000) >> 16}]
+ set minor [expr {($boot_version & 0x00FF00) >> 8}]
+ set patch [expr {$boot_version & 0x0000FF}]
+ echo [format "** Boot version: %d.%d.%d.%d" $major $minor $patch $boot_build]
+ }
+
+ if { ![catch {priv::read32 $dap $ap $RAM_BOOT_STATUS_ADDR} boot_status] } {
+ echo "** Boot Status : [decode_boot_status $boot_status]"
+ if { [expr {$boot_status & $CYBOOT_ID_MASK}] == $CYBOOT_ID_FAIL} {
+ echo "** Reached DEAD branch"
+ }
+ }
+ }
+
+ echo "***************************************"
+
+ if { $lcs eq "NORMAL" } {
+ puts stderr "**** WARNING ******************************************************************"
+ puts stderr "* The detected device is in NORMAL Life Cycle. Programmed application"
+ puts stderr "* will not start until the device is moved to NORMAL_SECURE or NORMAL_NO_SECURE"
+ puts stderr "* state. Please refer to the README.md in the device BSP for more information."
+ puts stderr "*******************************************************************************"
+ }
+
+ catch {priv::write32 $dap $ap $EFUSE_CTRL_ADDR $efuse_ctl}
+
+ eval poll $poll_status
+ priv::pop_log_settings
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc acquire_wfa { {request {}} {dap {}} {ap {}} } {
+ variable SRSS_RES_SOFT_CTL_ADDR
+ variable SRSS_RES_SOFT_CTL_RESET_MASK
+ variable SRSS_TST_DEBUG_CTL_ADDR
+ variable SRSS_TST_DEBUG_CTL_WFA_MASK
+ variable SRSS_TST_DEBUG_CTL_WFA_REQ
+
+ priv::default_dap_ap dap ap
+ priv::push_log_settings
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+ priv::pop_log_settings
+
+ set request [expr {$request ne {} ? $request : $SRSS_TST_DEBUG_CTL_WFA_REQ}]
+
+ if [expr {[priv::read32 $dap $ap $SRSS_TST_DEBUG_CTL_ADDR] & $SRSS_TST_DEBUG_CTL_WFA_MASK}] {
+ catch {
+ priv::write32 $dap $ap $SRSS_TST_DEBUG_CTL_ADDR $SRSS_TST_DEBUG_CTL_WFA_MASK
+ priv::write32 $dap $ap $SRSS_RES_SOFT_CTL_ADDR $SRSS_RES_SOFT_CTL_RESET_MASK
+ }
+ }
+
+ if ![wait_for_ap_open $dap $ap] {
+ puts stderr "** Timed out waiting for AP #$ap to open!"
+ }
+
+ catch {
+ priv::write32 $dap $ap $SRSS_TST_DEBUG_CTL_ADDR $request
+ priv::write32 $dap $ap $SRSS_RES_SOFT_CTL_ADDR $SRSS_RES_SOFT_CTL_RESET_MASK
+ }
+
+ set result [wait_for_idle_loop $dap $ap]
+
+ if {$result} {
+ echo "** Target acquired in FWA mode (req: [format 0x%02X $request])"
+ } else {
+ puts stderr "** Acquisition in WFA mode FAILED!"
+ }
+
+ priv::push_log_settings
+ eval poll $poll_status
+ priv::pop_log_settings
+ return $result
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc launch_service_app { {dap {}} {ap {}} } {
+ variable ACQUIRE_TIMEOUT
+ variable CYAPP_APP_RUNNING
+ variable CYAPP_ID_FAIL
+ variable CYAPP_ID_MASK
+ variable CYAPP_SUCCESS
+ variable CYBOOT_SERVICE_APP_LAUNCHED
+ variable CYBOOT_SERVICE_APP_NOT_LAUNCHED
+ variable SRSS_TST_DEBUG_CTL_ADDR
+ variable SRSS_TST_DEBUG_STATUS_ADDR
+
+ priv::default_dap_ap dap ap
+ priv::push_log_settings
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+ priv::pop_log_settings
+
+ catch {priv::write32 $dap $ap $SRSS_TST_DEBUG_CTL_ADDR 0}
+
+ set result 0
+ set t_end [expr {[clock milliseconds] + $ACQUIRE_TIMEOUT}]
+ while {[clock milliseconds] < $t_end} {
+ if [catch {priv::read32 $dap $ap $SRSS_TST_DEBUG_STATUS_ADDR} mmio_status] continue
+
+ if {$mmio_status == $CYAPP_APP_RUNNING} {
+ echo "** Service application launched!"
+ set result 1
+ break
+ }
+
+ if {$mmio_status == $CYBOOT_SERVICE_APP_NOT_LAUNCHED} {
+ puts stderr "** Service application was not launched by the Boot!"
+ set result 0
+ break
+ }
+ }
+
+ if {$result} {
+ echo "** Waiting for service application to complete..."
+
+ set result 0
+ set t_end [expr {[clock milliseconds] + $ACQUIRE_TIMEOUT}]
+ while {[clock milliseconds] < $t_end} {
+ if [catch {priv::read32 $dap $ap $SRSS_TST_DEBUG_STATUS_ADDR} mmio_status] continue
+ if {$mmio_status == $CYAPP_APP_RUNNING} continue
+
+ if {$mmio_status == $CYAPP_SUCCESS} {
+ echo "** Service application completed successfully!"
+ set result 1
+ break
+ }
+
+ if {[expr {$mmio_status & $CYAPP_ID_MASK}] == $CYAPP_ID_FAIL} {
+ puts stderr "** Service application failed! Status: [decode_boot_status $mmio_status]"
+ set result 0
+ break
+ }
+ }
+ }
+
+ priv::push_log_settings
+ eval poll $poll_status
+ priv::pop_log_settings
+
+ return $result
+}
+
+if { [adapter name] eq "kitprog3" && ![using_jtag]} {
+ # Configure KitProg3/MiniProg4 parameters for CYW20829 device acquisition:
+ # target_type == 4 (CY20829); mode == 0 (Reset); attempts == 2
+ kitprog3 acquire_config off 4 0 2
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc toggle_xres { {dap {}} {ap {}} } {
+ variable ACQUIRE_TIMEOUT
+ variable SRSS_TST_MODE_ADDR
+ variable SRSS_TST_MODE_MASK
+
+ priv::default_dap_ap dap ap
+ priv::push_log_settings
+ set reset_cfg [reset_config]
+ reset_config srst_only
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+
+ set reset_mode 0
+ while { 1 } {
+ set t_end [expr {[clock milliseconds] + $ACQUIRE_TIMEOUT}]
+ while {[clock milliseconds] < $t_end} {
+ if ![catch {priv::write32 $dap $ap $SRSS_TST_MODE_ADDR $SRSS_TST_MODE_MASK}] break
+ }
+
+ if { [priv::do_reset $reset_mode $dap $ap] == 0 } {
+ puts stderr "** Failed to reset the device"
+ break
+ }
+
+ set tst_mode 0xDEADBEEF
+ while {[clock milliseconds] < $t_end} {
+ if ![catch {set tst_mode [priv::read32 $dap $ap $SRSS_TST_MODE_ADDR]}] break
+ }
+
+ if { $tst_mode == 0 } break
+
+ incr reset_mode
+ }
+
+ eval poll $poll_status
+ eval [concat reset_config $reset_cfg]
+ priv::pop_log_settings
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc acquire_xres { {dap {}} {ap {}} } {
+ variable ACQUIRE_TIMEOUT
+ variable SRSS_TST_MODE_ADDR
+ variable SRSS_TST_MODE_MASK
+ variable SRSS_RES_SOFT_CTL_ADDR
+ variable SRSS_RES_SOFT_CTL_RESET_MASK
+
+ priv::default_dap_ap dap ap
+ priv::push_log_settings
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+ priv::pop_log_settings
+
+ local_echo off
+ scan [adapter srst delay] "adapter srst delay: %d" srst_delay
+ set reset_cfg [reset_config]
+
+ adapter srst delay 0
+ reset_config srst_only
+
+ set result 0
+ if { [adapter name] eq "kitprog3" && ![using_jtag]} {
+ kitprog3 acquire_psoc
+ set result [wait_for_idle_loop $dap $ap]
+ }
+
+ if {$result == 0} {
+ for {set i 0} {$i < 3} {incr i} {
+ set t_end [expr {[clock milliseconds] + $ACQUIRE_TIMEOUT}]
+ priv::do_reset $i $dap $ap
+ while {[clock milliseconds] < $t_end} {
+ if ![catch {priv::write32 $dap $ap $SRSS_TST_MODE_ADDR $SRSS_TST_MODE_MASK}] break
+ }
+
+ set result [wait_for_idle_loop $dap $ap]
+ if {$result} break
+ }
+ }
+
+ local_echo off
+ adapter srst delay $srst_delay
+ eval [concat reset_config $reset_cfg]
+ local_echo on
+
+ if {$result} {
+ echo "** Target acquired in Test Mode"
+ } else {
+ puts stderr "** Acquisition in Test Mode FAILED!"
+ }
+
+ priv::push_log_settings
+ eval poll $poll_status
+ priv::pop_log_settings
+ return $result
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc reset_wait_halt { target } {
+ variable ACQUIRE_TIMEOUT
+ variable CYBOOT_IDLE_BRANCH_REACHED
+ variable CYBOOT_ID_FAIL
+ variable CYBOOT_ID_MASK
+ variable CYBOOT_NEXT_APP_LAUNCHED
+ variable RAM_BOOT_STATUS_ADDR
+
+ set app_launched 0
+ set t_end [expr {[clock milliseconds] + $ACQUIRE_TIMEOUT}]
+ while {[clock milliseconds] < $t_end} {
+ $target arp_examine
+ $target arp_poll
+ $target arp_poll
+ set boot_status [mrw $RAM_BOOT_STATUS_ADDR]
+ if [expr {($boot_status & $CYBOOT_ID_MASK) == $CYBOOT_ID_FAIL}] break
+ if {$boot_status == $CYBOOT_IDLE_BRANCH_REACHED} break
+ if {$boot_status == $CYBOOT_NEXT_APP_LAUNCHED} {
+ set app_launched 1
+ break
+ }
+ }
+
+ set ret_val 1
+ if {$app_launched} {
+ if [catch {$target arp_waitstate halted 1000}] {
+ set ret_val 0
+ }
+ } else {
+ puts stderr "** Application was not launched, boot status: [decode_boot_status $boot_status]"
+ $target arp_halt
+ $target arp_waitstate halted 1000
+ }
+
+ return $ret_val
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc reset_halt_breakpoint { target use_certificate } {
+ variable NVIC_VTOR_ADDR
+
+ priv::push_log_settings
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+ priv::pop_log_settings
+
+ set vtbl_addr [mrw $NVIC_VTOR_ADDR]
+ if { !($vtbl_addr >= 0x20000000 && $vtbl_addr < 0x20020000) &&
+ !($vtbl_addr >= 0x04000000 && $vtbl_addr < 0x04020000) &&
+ !($vtbl_addr >= 0x60000000 && $vtbl_addr < 0x68000000) &&
+ !($vtbl_addr >= 0x08000000 && $vtbl_addr < 0x10000000) } {
+ puts stderr "** Vector Table address invalid ([format 0x%08X $vtbl_addr]), using predefined address (0x20004000)"
+ set vtbl_addr 0x20004000
+ }
+
+ set entry_addr [mrw [expr {$vtbl_addr + 4}]]
+ if { !($entry_addr >= 0x20000000 && $entry_addr < 0x20020000) &&
+ !($entry_addr >= 0x04000000 && $entry_addr < 0x04020000) &&
+ !($entry_addr >= 0x60000000 && $entry_addr < 0x68000000) &&
+ !($entry_addr >= 0x08000000 && $entry_addr < 0x10000000) } {
+ puts stderr "** Entry Point address invalid ([format 0x%08X $entry_addr])"
+ eval poll $poll_status
+ return
+ }
+
+ echo "** Entry Point found at ([format 0x%08X $entry_addr])"
+
+ priv::push_log_settings
+ bp $entry_addr 2 hw
+
+ if {$use_certificate} {
+ send_certificate
+ } else {
+ catch {mww 0xE000ED0C 0x05FA0004}
+ }
+
+ priv::pop_log_settings
+ wait_for_ap_open
+ set ret_val [reset_wait_halt $target]
+
+ # Remove all breakpoints
+ rbp all
+ eval poll $poll_status
+
+ return $ret_val
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc reset_halt_vector_catch { target use_certificate } {
+ priv::push_log_settings
+ scan [poll status] "background polling: %s" poll_status
+ poll off
+
+ # Setup VectorCatch
+ set prev_demcr [mrw 0xE000EDFC]
+ mww 0xE000EDFC 0x01000001
+
+ if {$use_certificate} {
+ send_certificate
+ } else {
+ catch {mww 0xE000ED0C 0x05FA0004}
+ }
+
+ priv::pop_log_settings
+ wait_for_ap_open
+ set ret_val [reset_wait_halt $target]
+
+ # Clear VectorCatch
+ mww 0xE000EDFC $prev_demcr
+
+ eval poll $poll_status
+ return $ret_val
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc reset_halt { target {use_certificate 0}} {
+ if ![reset_halt_vector_catch $target $use_certificate] {
+ puts stderr "** VectorCatch acquisition failed, falling back to BKPT method"
+ if ![reset_halt_breakpoint $target $use_certificate] {
+ puts stderr "** BKPT acquisition also failed, giving up"
+ }
+ }
+}
+
+# namespace eval mxs40v2
+}
+
+#####################################################################################################################
+#
+#####################################################################################################################
+proc provision_no_secure {service_app params {service_app_addr 0x20004000} {params_addr 0x2000D000}} {
+ if {[command mode] == "exec"} {
+ puts stderr "** The 'provision_no_secure' can only be called before 'init'"
+ return
+ }
+
+ set tgt [target current]
+ set sep [string last "." $tgt]
+ set cm33_target [string range $tgt 0 [expr {$sep - 1}]].cm33
+ set sysap_target [string range $tgt 0 [expr {$sep - 1}]].sysap
+
+ $cm33_target configure -defer-examine
+ targets $sysap_target
+
+ init
+ mxs40v2::acquire_xres
+
+ set lcs [mxs40v2::decode_lcs [mrw $::mxs40v2::EFUSE_BOOTROW_ADDR]]
+ echo "** Current Life Cycle: $lcs"
+
+ if {$lcs ne "NORMAL"} {
+ puts stderr "** Transition to NORMAL_NO_SECURE can only be done when device is in NORMAL Life Cycle"
+ return
+ }
+
+ mxs40v2::acquire_wfa 1
+ load_image $service_app $service_app_addr
+ load_image $params $params_addr
+ mxs40v2::launch_service_app
+ mxs40v2::acquire_xres
+
+ set lcs [mxs40v2::decode_lcs [mrw $::mxs40v2::EFUSE_BOOTROW_ADDR]]
+ echo "** Current Life Cycle: $lcs"
+}
diff --git a/scripts/target/mxs40/mxs40v2_common.cfg b/scripts/target/mxs40/mxs40v2_common.cfg
new file mode 100644
index 0000000..12d6816
--- /dev/null
+++ b/scripts/target/mxs40/mxs40v2_common.cfg
@@ -0,0 +1,130 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Common configuration for MXS40v2 family of microcontrollers.
+#
+
+if [info exist LOADED_[file rootname [file tail [info script]]]] return
+set LOADED_[file rootname [file tail [info script]]] true
+
+source [find mem_helper.tcl]
+source [find target/mxs40/mxs40v2_acquire_helpers.cfg]
+
+###############################################################################
+# Default speed an reset settings
+###############################################################################
+if {[using_jtag]} {
+ adapter speed 1000
+} else {
+ adapter speed 2000
+}
+
+adapter srst delay 25
+adapter srst pulse_width 25
+
+###############################################################################
+# Erases all non-virtual flash banks (in reverse order)
+###############################################################################
+proc erase_all {} {
+ lset banks [flash list]
+ set banks_count [llength $banks]
+ for {set i 0} { $i < $banks_count } { set i [expr {$i + 1}]} {
+ set bank [lindex $banks $i]
+ set bank_name $bank(name)
+ echo [format "Erasing flash bank \"%s\" (%d of %d)..." $bank_name [expr {$i + 1}] $banks_count ]
+ if { $bank_name != "virtual" } {
+ flash erase_sector $i 0 last
+ } else {
+ echo "skipped (virtual)"
+ }
+ }
+}
+add_help_text erase_all "Erases all non-virtual flash banks"
+
+###############################################################################
+# Utility to make 'reset halt' work as reset;halt on a target
+# It does not prevent running code after reset
+###############################################################################
+proc mxs40v2_reset_deassert_post { target } {
+ global DEBUG_CERTIFICATE
+ global RESET_MODE
+
+ set use_certificate 0
+ if { [mxs40v2::is_ap_open] == 0 } {
+ if [info exists DEBUG_CERTIFICATE] {
+ echo "** CM33 AP was closed after reset, sending debug certificate"
+ if [catch {send_certificate}] {
+ puts stderr "** Error sending debug certificate, examination skipped"
+ set sysap_target [string map {cm33 sysap} $target]
+ targets $sysap_target
+ return
+ }
+ set use_certificate 1
+ } else {
+ puts stderr "** CM33 AP was closed after reset and no certificate specified, examination skipped"
+ puts stderr "** Use 'DEBUG_CERTIFICATE' variable to specify certificate filename with full path"
+ set sysap_target [string map {cm33 sysap} $target]
+ targets $sysap_target
+ return
+ }
+ }
+
+ # MXS40V2 cleared AP registers including TAR during reset
+ # Force examine to synchronize OpenOCD target status
+ $target arp_examine
+ $target arp_poll
+
+ # Exit if $target is supposed to be running after Reset
+ if { $RESET_MODE eq "run" } return
+
+ if { [$target curstate] eq "reset" } {
+ $target arp_poll
+ }
+
+ if { [$target curstate] eq "running" } {
+ $target arp_halt
+ $target arp_waitstate halted 100
+ }
+
+ mxs40v2::reset_halt $target $use_certificate
+ check_flashboot_version
+}
+
+# Define check_flashboot_version if not already defined
+if { [info proc check_flashboot_version] eq "" } {
+ proc check_flashboot_version {} {}
+}
+
+###############################################################################
+# Overrides default init_reset procedure, stores reset mode in global variable
+###############################################################################
+proc init_reset { mode } {
+ global RESET_MODE
+ set RESET_MODE $mode
+}
+
+###############################################################################
+# Power dropout/restore handlers
+###############################################################################
+proc power_dropout {} {
+ if { [adapter name] eq "kitprog3" } {
+ local_echo off
+ set voltage [regexp -inline -- {[0-9]+\.[0-9]+} [kitprog3 get_power]]
+ local_echo on
+ puts stderr "Power dropout, target voltage: $voltage mV"
+ }
+}
+
+proc power_restore {} {
+ if { [adapter name] eq "kitprog3" } {
+ local_echo off
+ set voltage [regexp -inline -- {[0-9]+\.[0-9]+} [kitprog3 get_power]]
+ local_echo on
+ puts stderr "Power restore, target voltage: $voltage mV"
+ }
+}
+
+###############################################################################
+# TODO: KitProg3 acquire/power control stuff
+###############################################################################
diff --git a/scripts/target/mxs40/psoc6_common.cfg b/scripts/target/mxs40/psoc6_common.cfg
new file mode 100644
index 0000000..ab7e7fa
--- /dev/null
+++ b/scripts/target/mxs40/psoc6_common.cfg
@@ -0,0 +1,214 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Common configuration for PSoC 64 family of microcontrollers.
+# PSoC 64 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+source [find target/swj-dp.tcl]
+source [find target/mxs40/mxs40_common.cfg]
+
+global _CHIPNAME
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME psoc6
+}
+
+# Make MXS40_TARGET_DIE chip-specific
+if { ![info exists MXS40_TARGET_DIE] || ![dict exists $MXS40_DIE_CONFIG_DICT $MXS40_TARGET_DIE]} {
+ puts stderr "MXS40_TARGET_DIE not defined or invalid!"
+ puts stderr "Known dies: [dict keys $MXS40_DIE_CONFIG_DICT]"
+ shutdown
+}
+
+set ${_CHIPNAME}::MXS40_TARGET_DIE $MXS40_TARGET_DIE
+unset MXS40_TARGET_DIE
+
+#
+# Is CM0 Debugging enabled ?
+#
+global _ENABLE_CM0
+if { [info exists ENABLE_CM0] } {
+ set _ENABLE_CM0 $ENABLE_CM0
+} else {
+ set _ENABLE_CM0 1
+}
+
+#
+# Is CM4 Debugging enabled ?
+#
+global _ENABLE_CM4
+if { [info exists ENABLE_CM4] } {
+ set _ENABLE_CM4 $ENABLE_CM4
+} else {
+ set _ENABLE_CM4 1
+}
+
+# set acquire mode: power cycle = 2, reset otherwise
+if { $_ENABLE_ACQUIRE == 2 } {
+ kitprog3 acquire_config on 2 1 2
+} elseif { $_ENABLE_ACQUIRE } {
+ kitprog3 acquire_config on 2 0 2
+}
+
+if { [info exists WORKAREAADDR] } {
+ set _WA_ADDR $WORKAREAADDR
+ unset WORKAREAADDR
+} else {
+ set _WA_ADDR 0x08000000
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WA_SIZE $WORKAREASIZE
+ unset WORKAREASIZE
+} else {
+ set _WA_SIZE 0x8000
+}
+
+global TARGET
+set TARGET $_CHIPNAME.cpu
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+proc check_flashboot_version {} {
+ global _ENABLE_CM0
+
+ set rev_id ""
+ catch {
+ set si_id [mrw 0x16000000]
+ set fb_ver [mrw 0x16002004]
+ set rev_id [format "%02X" [expr {($si_id & 0xFF00) >> 8}]]
+ }
+
+ # SI revision 0x22 (*B) and
+ # versioning scheme #2 (ALXD-31) with major mersion #0 (PSoC6A-BLE-2 *A/*B/*C) and
+ # FB build number older than #29
+ if { $rev_id == "22" && \
+ [expr {$fb_ver & 0xFF00FFFF}] == 0x02008001 } {
+ set fb_build [expr {($fb_ver & 0x00FF0000) >> 16}]
+
+ if { $fb_build <= 20 || ( $_ENABLE_CM0 == 0 && $fb_build < 29 ) } {
+ puts stderr "********************************************************************************"
+ puts stderr "* Your PSoC 6 kit is out of date. Please contact Cypress to get a replacement. *"
+ puts stderr "********************************************************************************"
+ } elseif { $fb_build < 29 } {
+ puts stderr "*****************************************************"
+ puts stderr "* You are using a pre-production PSoC 6 BLE device. *"
+ puts stderr "*****************************************************"
+ }
+ }
+}
+
+if { $_ENABLE_CM0 } {
+ set _ACQUIRE_TARGET cm0
+} else {
+ set _ACQUIRE_TARGET cm4
+}
+
+global _HAS_WORKFLASH
+if { ![info exists _HAS_WORKFLASH] } {
+ set _HAS_WORKFLASH 1
+}
+
+if { $_ENABLE_CM0 } {
+ target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+ ${TARGET}.cm0 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
+
+ flash bank ${_CHIPNAME}_main_cm0 ${FLASH_DRIVER_NAME} 0x10000000 0 0 0 ${TARGET}.cm0
+ if { $_HAS_WORKFLASH } {
+ flash bank ${_CHIPNAME}_work_cm0 ${FLASH_DRIVER_NAME} 0x14000000 0 0 0 ${TARGET}.cm0
+ }
+ flash bank ${_CHIPNAME}_super_cm0 ${FLASH_DRIVER_NAME} 0x16000000 0 0 0 ${TARGET}.cm0
+ flash bank ${_CHIPNAME}_efuse_cm0 ${FLASH_DRIVER_NAME}_efuse 0x90700000 1024 1 1 ${TARGET}.cm0 external
+
+ add_verify_range ${TARGET}.cm0 0x08000000 0x00200000
+ add_verify_range ${TARGET}.cm0 0x10000000 0x00200000
+ add_verify_range ${TARGET}.cm0 0x14000000 0x00200000
+ add_verify_range ${TARGET}.cm0 0x16000000 0x00200000
+ add_verify_range ${TARGET}.cm0 0x90700000 0x00000400
+
+ ${TARGET}.cm0 cortex_m reset_config sysresetreq
+ ${TARGET}.cm0 configure -event reset-deassert-post "mxs40_reset_deassert_post psoc6 ${TARGET}.cm0"
+ ${TARGET}.cm0 configure -event examine-end "cy_get_set_device_param $FLASH_DRIVER_NAME ${_CHIPNAME}_main_cm0 ${_CHIPNAME}_work_cm0"
+}
+
+if { $_ENABLE_CM4 } {
+ target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
+ ${TARGET}.cm4 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
+
+ if { $_ENABLE_CM0 } {
+ flash bank ${_CHIPNAME}_main_cm4 virtual 0x10000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_main_cm0
+ if { $_HAS_WORKFLASH } {
+ flash bank ${_CHIPNAME}_work_cm4 virtual 0x14000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_work_cm0
+ }
+ flash bank ${_CHIPNAME}_super_cm4 virtual 0x16000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_super_cm0
+ flash bank ${_CHIPNAME}_efuse_cm4 virtual 0x90700000 1024 1 1 ${TARGET}.cm4 ${_CHIPNAME}_efuse_cm0 external
+ # Avoid double-reset on dual-core parts
+ ${TARGET}.cm4 configure -event reset-assert {}
+ targets ${TARGET}.cm0
+ } else {
+ flash bank ${_CHIPNAME}_main_cm4 ${FLASH_DRIVER_NAME} 0x10000000 0 0 0 ${TARGET}.cm4
+ if { $_HAS_WORKFLASH } {
+ flash bank ${_CHIPNAME}_work_cm4 ${FLASH_DRIVER_NAME} 0x14000000 0 0 0 ${TARGET}.cm4
+ }
+ flash bank ${_CHIPNAME}_super_cm4 ${FLASH_DRIVER_NAME} 0x16000000 0 0 0 ${TARGET}.cm4
+ flash bank ${_CHIPNAME}_efuse_cm4 ${FLASH_DRIVER_NAME}_efuse 0x90700000 1024 1 1 ${TARGET}.cm4 external
+ ${TARGET}.cm4 configure -event examine-end "cy_get_set_device_param $FLASH_DRIVER_NAME ${_CHIPNAME}_main_cm4 ${_CHIPNAME}_work_cm4"
+ }
+
+ add_verify_range ${TARGET}.cm4 0x08000000 0x00200000
+ add_verify_range ${TARGET}.cm4 0x10000000 0x00200000
+ add_verify_range ${TARGET}.cm4 0x14000000 0x00200000
+ add_verify_range ${TARGET}.cm4 0x16000000 0x00200000
+ add_verify_range ${TARGET}.cm4 0x90700000 0x00000400
+
+ ${TARGET}.cm4 cortex_m reset_config sysresetreq
+ ${TARGET}.cm4 configure -event reset-deassert-post "mxs40_reset_deassert_post psoc6 ${TARGET}.cm4"
+}
+
+unset _HAS_WORKFLASH
+
+if { ![info exists PSOC6_JTAG_IRLEN] } {
+ set PSOC6_JTAG_IRLEN 18
+}
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen $PSOC6_JTAG_IRLEN -expected-id 0
+}
+
+# example of qspi_config.cfg
+#set SMIF_BANKS {
+# 1 {addr 0x18000000 size 0x10000 psize 0x100 esize 0x1000}
+# 2 {addr 0x18010000 size 0x10000 psize 0x100 esize 0x1000}
+# 3 {addr 0x18020000 size 0x10000 psize 0x100 esize 0x1000}
+# 4 {addr 0x18030000 size 0x10000 psize 0x100 esize 0x1000}
+#}
+
+catch {source [find qspi_config.cfg]}
+if { [info exists SMIF_BANKS] } {
+
+ set num_banks [array size SMIF_BANKS]
+ set bank_param ""
+ if { $num_banks > 1 } {
+ set bank_param "prefer_sector_erase"
+ }
+
+ foreach {key value} [array get SMIF_BANKS] {
+ if { $_ENABLE_CM0 } {
+ flash bank ${_CHIPNAME}_smif${key}_cm0 cmsis_flash $value(addr) $value(size) 4 4 ${TARGET}.cm0 ../flm/cypress/cat1a/${QSPI_FLASHLOADER} 0x800 {*}$bank_param
+ add_verify_range ${TARGET}.cm0 $value(addr) $value(size)
+ if { $_ENABLE_CM4 } {
+ flash bank ${_CHIPNAME}_smif${key}_cm4 virtual $value(addr) $value(size) 0 0 ${TARGET}.cm4 ${_CHIPNAME}_smif${key}_cm0
+ add_verify_range ${TARGET}.cm4 $value(addr) $value(size)
+ }
+ } else {
+ flash bank ${_CHIPNAME}_smif${key}_cm4 cmsis_flash $value(addr) $value(size) 4 4 ${TARGET}.cm4 ../flm/cypress/cat1a/${QSPI_FLASHLOADER} 0x800 {*}$bank_param
+ add_verify_range ${TARGET}.cm4 $value(addr) $value(size)
+ }
+ }
+}
+
+gdb_smart_program enable
diff --git a/scripts/target/mxs40/psoc6_detect_geometry.cfg b/scripts/target/mxs40/psoc6_detect_geometry.cfg
new file mode 100644
index 0000000..8b5ff10
--- /dev/null
+++ b/scripts/target/mxs40/psoc6_detect_geometry.cfg
@@ -0,0 +1,50 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+
+source [find target/mxs40/cympn_parser.cfg]
+
+#
+# detects main flash size of PSoC6 devices
+#
+# tryies to get PSoC6 geometry from the:
+# 1. $MAIN_FLASH_SIZE if defined
+# 2. UDD
+#
+# arguments:
+# target_arch - the target architecture - psoc6 or psoc6_2m
+# main_reg_name - the name of main region to be set
+#
+proc psoc6_detect_geometry { target_arch main_reg_name } {
+ # following priorities are used:
+ # 1. MAIN_FLASH_SIZE define
+ # 2. UDD
+
+ set tgt [target current]
+ set CHIPNAME [string range ${tgt} 0 [expr {[string first "." ${tgt}] - 1}]]
+ global ${CHIPNAME}::MAIN_FLASH_SIZE
+
+
+ set detected_main_size 0
+
+ # 1. Use ${CHIPNAME}::MAIN_FLASH_SIZE if defined
+ if { [info exists ${CHIPNAME}::MAIN_FLASH_SIZE] } {
+ echo "** Use overriden Main Flash size, kb: [expr {${CHIPNAME}::MAIN_FLASH_SIZE >> 10}]"
+ set detected_main_size ${CHIPNAME}::MAIN_FLASH_SIZE
+ }
+
+ # print MPN
+ set main_work_size [cyp_get_mpn_work_main_size $target_arch]
+
+ if {$detected_main_size == 0} {
+ # 2. Use UDD because flash geometry is not read from register
+ if { [llength $main_work_size] == 2} {
+ set main_size [lindex $main_work_size 0]
+ echo "** Detected Main Flash size, kb: $main_size"
+ set detected_main_size [expr {$main_size * 1024}]
+ }
+ }
+
+ if { ${main_reg_name} != "" } { psoc6 set_region_size ${main_reg_name} $detected_main_size }
+}
diff --git a/scripts/target/mxs40/psoc6_secure_common.cfg b/scripts/target/mxs40/psoc6_secure_common.cfg
new file mode 100644
index 0000000..77a4fcb
--- /dev/null
+++ b/scripts/target/mxs40/psoc6_secure_common.cfg
@@ -0,0 +1,370 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Common configuration for PSoC 64 family of microcontrollers.
+# PSoC 64 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+source [find mem_helper.tcl]
+source [find target/mxs40/cympn_parser.cfg]
+source [find target/mxs40/cy_get_set_device_param.cfg]
+
+adapter speed 2000
+adapter srst delay 0
+adapter srst pulse_width 5
+
+if {[using_jtag]} {
+ puts stderr "JTAG transport not supported by selected target, please switch to SWD"
+ shutdown
+}
+
+proc check_die_matches_driver { DIE SERIES } {
+ set MXS40_DIE_CONFIG_DICT [dict create \
+ PSoC6ABLE2 psoc6.cfg \
+ PSoC6A256K psoc6_256k.cfg \
+ PSoC6A512K psoc6_512k.cfg \
+ PSoC6A2M psoc6_2m.cfg \
+ ]
+
+ global MXS40_TARGET_DIE
+ global wrong_cfg_msg
+
+ if {![info exists MXS40_TARGET_DIE]} return
+ set is_psoc64 [string equal -nocase $SERIES "PSoC_64"]
+
+ if { $DIE != $MXS40_TARGET_DIE || !$is_psoc64 } {
+ if { [info exists MXS40_DIE_CONFIG_DICT($DIE)] } {
+ set wrong_cfg_msg \"$MXS40_DIE_CONFIG_DICT($DIE)\"
+ if { $is_psoc64 } {
+ set wrong_cfg_msg [regsub {\.} $wrong_cfg_msg {_secure.}]
+ }
+ } else {
+ set wrong_cfg_msg "proper"
+ }
+ }
+}
+
+global _ENABLE_ACQUIRE
+global _ENABLE_POWER_SUPPLY
+if { [adapter name] eq "kitprog3" } {
+ if { [info exists ENABLE_ACQUIRE] } {
+ set _ENABLE_ACQUIRE $ENABLE_ACQUIRE
+ } else {
+ set _ENABLE_ACQUIRE 1
+ }
+
+ if { [info exists ENABLE_POWER_SUPPLY] } {
+ set _ENABLE_POWER_SUPPLY $ENABLE_POWER_SUPPLY
+ } else {
+ set _ENABLE_POWER_SUPPLY 0
+ }
+} else {
+ set _ENABLE_ACQUIRE 0
+ set _ENABLE_POWER_SUPPLY 0
+ echo "** Test Mode acquire not supported by selected adapter"
+}
+
+if { $_ENABLE_POWER_SUPPLY } {
+ echo "** Enabling target power ($_ENABLE_POWER_SUPPLY mV) \"set ENABLE_POWER_SUPPLY 0\" to disable"
+ kitprog3 power_config on $_ENABLE_POWER_SUPPLY
+}
+
+set show_device_info_runned 0
+proc show_device_info { target main_region_name } {
+ global show_device_info_runned
+ global _FLASH_DRIVER_NAME
+ global _FLASH_RESTRICTION_SIZE
+
+ # Exit if target was not examined
+ if { [$target was_examined] == 0 } { return }
+
+ if {$show_device_info_runned == 0} {
+ echo "***************************************"
+ echo "** Use overriden Main Flash size, kb: [expr {$_FLASH_RESTRICTION_SIZE >> 10}]"
+ cyp_get_mpn_work_main_size "psoc6"
+ set fb_ver [show_flash_boot_ver $_FLASH_DRIVER_NAME]
+ if {[string match "4.0.0.*" $fb_ver]} {
+ puts stderr "Warn: Pre-production version of device is detected which is incompatible with this software"
+ puts stderr "Warn: Please contact Cypress for new production parts"
+ }
+ echo "***************************************"
+ set show_device_info_runned 1
+
+ global wrong_cfg_msg
+ if { [info exist wrong_cfg_msg] && $wrong_cfg_msg != "" } {
+ set cfg_file $wrong_cfg_msg
+ puts stderr "*******************************************************************************"
+ puts stderr "* The detected device does not match the configuration file in use."
+ puts stderr "* Flash programming will not work. Please use the $cfg_file"
+ puts stderr "* configuration file, or attach a kit that matches the configuration file."
+ puts stderr "*******************************************************************************"
+ terminate
+ }
+ }
+}
+
+if { [info exists POWERUP_DELAY] } {
+ set _POWERUP_DELAY $POWERUP_DELAY
+} else {
+ set _POWERUP_DELAY 5000
+}
+echo "** Using POWERUP_DELAY: $_POWERUP_DELAY ms"
+
+proc power_dropout {} {
+ global _POWERUP_DELAY
+ echo "** Waiting for target to boot ($_POWERUP_DELAY ms), use 'set POWERUP_DELAY' to override"
+ sleep $_POWERUP_DELAY
+}
+
+if { [info exists ENABLE_WFLASH] } {
+ set _ENABLE_WFLASH $ENABLE_WFLASH
+} else {
+ set _ENABLE_WFLASH 1
+}
+
+if { [info exists ENABLE_SFLASH] } {
+ set _ENABLE_SFLASH $ENABLE_SFLASH
+} else {
+ set _ENABLE_SFLASH 0
+}
+
+if { [info exists ENABLE_EFUSE] } {
+ set _ENABLE_EFUSE $ENABLE_EFUSE
+} else {
+ set _ENABLE_EFUSE 0
+}
+
+if {$_ENABLE_EFUSE} {
+ echo "** eFuse Flash Bank enabled"
+}
+
+if { ![info exists TARGET_AP] } {
+ set TARGET_AP "sys_ap"
+ echo "** TARGET_AP not defined, using 'sys_ap' by default"
+}
+echo "** Using TARGET_AP: $TARGET_AP"
+
+if { $TARGET_AP eq "sys_ap" } {
+ set _ENABLE_SYSAP 1
+ set _ENABLE_CM0 0
+ set _ENABLE_CM4 0
+} elseif { $TARGET_AP eq "cm0_ap" } {
+ set _ENABLE_SYSAP 1
+ set _ENABLE_CM0 1
+ set _ENABLE_CM4 0
+} elseif { $TARGET_AP eq "cm4_ap" } {
+ set _ENABLE_SYSAP 1
+ set _ENABLE_CM0 0
+ set _ENABLE_CM4 1
+} elseif { $TARGET_AP eq "cm0_cm4_ap" } {
+ set _ENABLE_SYSAP 1
+ set _ENABLE_CM0 1
+ set _ENABLE_CM4 1
+} else {
+ puts stderr "Error: Invalid TARGET_AP: $TARGET_AP, please use one of the following: sys_ap, cm0_ap, cm4_ap, cm0_cm4_ap"
+ shutdown
+}
+
+if { [info exists ACQUIRE_TIMEOUT] } {
+ set _ACQUIRE_TIMEOUT $ACQUIRE_TIMEOUT
+} else {
+ set _ACQUIRE_TIMEOUT 15000
+}
+
+if { $_ACQUIRE_TIMEOUT > 30000 } {
+ set _ACQUIRE_TIMEOUT 30000
+}
+
+echo "** Using ACQUIRE_TIMEOUT: $_ACQUIRE_TIMEOUT ms"
+
+if { $_ENABLE_ACQUIRE } {
+ set acq_ap_dict [dict create]
+ dict set ACQ_AP_DICT sys_ap 0
+ dict set ACQ_AP_DICT cm0_ap 1
+ dict set ACQ_AP_DICT cm4_ap 2
+ dict set ACQ_AP_DICT cm0_cm4_ap 2
+
+ echo "** Auto-acquire enabled, use \"set ENABLE_ACQUIRE 0\" to disable"
+ kitprog3 acquire_config on 2 0 2 [expr {$_ACQUIRE_TIMEOUT / 1000}] $ACQ_AP_DICT($TARGET_AP)
+}
+
+global TARGET
+set TARGET $_CHIPNAME.cpu
+swd newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+proc init_reset { mode } {
+ global _RESET_MODE
+ set _RESET_MODE $mode
+
+ if {[using_jtag]} {
+ jtag arp_init-reset
+ }
+}
+
+proc reset_deassert_post { target } {
+ global _RESET_MODE
+ global _ACQUIRE_TIMEOUT
+ global _MAGIC_NUMBER_ADDR
+ global _ENABLE_ACQUIRE
+ global TARGET_AP
+
+ switch $TARGET_AP {
+ sys_ap { if { $target != "sysap" } return }
+ cm0_ap { if { $target != "cm0" } return }
+ cm4_ap { if { $target != "cm4" } return }
+ cm0_cm4_ap { if { $target != "cm4" } return }
+ default { error "Invalid TARGET_AP: $TARGET_AP" }
+ }
+
+ if {$_RESET_MODE == "run"} {
+ psoc6 secure_acquire $_MAGIC_NUMBER_ADDR run no_handshake $_ACQUIRE_TIMEOUT
+ if { $TARGET_AP == "cm0_cm4_ap" } {
+ set prev_tgt [target current]
+ targets psoc64.cpu.cm0
+ psoc6 secure_acquire $_MAGIC_NUMBER_ADDR run no_handshake $_ACQUIRE_TIMEOUT
+ targets $prev_tgt
+ }
+ } else {
+ if { $_ENABLE_ACQUIRE } {
+ kitprog3 acquire_psoc
+ }
+
+ psoc6 secure_acquire $_MAGIC_NUMBER_ADDR halt handshake $_ACQUIRE_TIMEOUT
+ if { $TARGET_AP == "cm0_cm4_ap" } {
+ set prev_tgt [target current]
+ targets psoc64.cpu.cm0
+ psoc6 secure_acquire $_MAGIC_NUMBER_ADDR halt handshake $_ACQUIRE_TIMEOUT
+ targets $prev_tgt
+ }
+ }
+}
+
+proc gdb_attach { target } {
+ # PSoC64-1m with CyBootloader performs additional Reset of CM4
+ # right after acquisition in TestMode. This cause problems with
+ # VSCode because gdb connects immediately after 'init' so CPU
+ # halting fails. Adding short delay resolves the issue.
+ sleep 250
+
+ $target arp_examine
+ $target arp_poll
+ $target arp_poll
+ $target arp_halt
+ $target arp_waitstate halted 1000
+}
+
+if { $_ENABLE_SYSAP } {
+ target create ${TARGET}.sysap mem_ap -dap $_CHIPNAME.dap -ap-num 0 -coreid 255
+ ${TARGET}.sysap configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 0
+ ${TARGET}.sysap configure -event examine-end "show_device_info ${TARGET}.sysap main_sysap"
+ ${TARGET}.sysap configure -event reset-deassert-post "reset_deassert_post sysap"
+}
+
+if { $_ENABLE_CM0 } {
+ target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -defer-examine
+ ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM -work-area-size $_WORKAREASIZE_CM -work-area-backup 0
+ ${TARGET}.cm0 configure -event examine-end "show_device_info ${TARGET}.sysap main_cm0"
+ ${TARGET}.cm0 configure -event reset-deassert-post "reset_deassert_post cm0"
+ ${TARGET}.cm0 configure -event gdb-start "mww 0x40260100 0"
+ ${TARGET}.cm0 configure -event gdb-attach "gdb_attach ${TARGET}.cm0"
+}
+
+if { $_ENABLE_CM4 } {
+ target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 2 -defer-examine
+ ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM -work-area-size $_WORKAREASIZE_CM -work-area-backup 0
+ ${TARGET}.cm4 configure -event examine-end "show_device_info ${TARGET}.sysap main_cm4"
+ ${TARGET}.cm4 configure -event reset-deassert-post "reset_deassert_post cm4"
+ ${TARGET}.cm4 configure -event gdb-start "mww 0x40260100 0"
+ ${TARGET}.cm4 configure -event gdb-attach "gdb_attach ${TARGET}.cm4"
+}
+
+if { $TARGET_AP eq "sys_ap" } {
+
+ flash bank ${_CHIPNAME}_main_sysap ${_FLASH_DRIVER_NAME} 0x10000000 0 0 0 ${TARGET}.sysap external
+ if {$_ENABLE_WFLASH} { flash bank ${_CHIPNAME}_work_sysap ${_FLASH_DRIVER_NAME} 0x14000000 0 0 0 ${TARGET}.sysap external }
+ if {$_ENABLE_SFLASH} { flash bank ${_CHIPNAME}_sflash_sysap ${_FLASH_DRIVER_NAME} 0x16000000 0 0 0 ${TARGET}.sysap external }
+ if {$_ENABLE_EFUSE} { flash bank ${_CHIPNAME}_efuse_sysap ${_FLASH_DRIVER_NAME}_efuse 0x90700000 1024 1 1 ${TARGET}.sysap external }
+
+ psoc6 set_region_size ${_CHIPNAME}_main_sysap $_FLASH_RESTRICTION_SIZE
+
+} elseif { $TARGET_AP eq "cm0_ap" } {
+
+ flash bank ${_CHIPNAME}_main_cm0 ${_FLASH_DRIVER_NAME} 0x10000000 0 0 0 ${TARGET}.cm0 external
+ flash bank ${_CHIPNAME}_main_sysap virtual 0x10000000 0 0 0 ${TARGET}.sysap ${_CHIPNAME}_main_cm0
+ if {$_ENABLE_WFLASH} { flash bank ${_CHIPNAME}_work_cm0 ${_FLASH_DRIVER_NAME} 0x14000000 0 0 0 ${TARGET}.cm0 external
+ flash bank ${_CHIPNAME}_work_sysap virtual 0x14000000 0 0 0 ${TARGET}.sysap ${_CHIPNAME}_work_cm0 }
+ if {$_ENABLE_SFLASH} { flash bank ${_CHIPNAME}_sflash_sysap ${_FLASH_DRIVER_NAME} 0x16000000 0 0 0 ${TARGET}.sysap external
+ flash bank ${_CHIPNAME}_sflash_cm0 virtual 0x16000000 0 0 0 ${TARGET}.cm0 ${_CHIPNAME}_sflash_sysap }
+ if {$_ENABLE_EFUSE} { flash bank ${_CHIPNAME}_efuse_sysap ${_FLASH_DRIVER_NAME}_efuse 0x90700000 1024 1 1 ${TARGET}.sysap external
+ flash bank ${_CHIPNAME}_efuse_cm0 virtual 0x90700000 1024 1 1 ${TARGET}.cm0 ${_CHIPNAME}_efuse_sysap }
+
+ if { ![info exists DISABLE_SMIF] } {
+ flash bank ${_CHIPNAME}_smif_cm0 cmsis_flash 0x18000000 0 4 4 ${TARGET}.cm0 ../flm/cypress/cat1a/$_QSPI_FLASHLOADER 0x1000 prefer_sector_erase
+ flash bank ${_CHIPNAME}_smif_sysap virtual 0x18000000 0 4 4 ${TARGET}.sysap ${_CHIPNAME}_smif_cm0 }
+
+ psoc6 set_region_size ${_CHIPNAME}_main_cm0 $_FLASH_RESTRICTION_SIZE
+
+} elseif { $TARGET_AP eq "cm4_ap" } {
+
+ flash bank ${_CHIPNAME}_main_cm4 ${_FLASH_DRIVER_NAME} 0x10000000 0 0 0 ${TARGET}.cm4 external
+ flash bank ${_CHIPNAME}_main_sysap virtual 0x10000000 0 0 0 ${TARGET}.sysap ${_CHIPNAME}_main_cm4
+ if {$_ENABLE_WFLASH} { flash bank ${_CHIPNAME}_work_cm4 ${_FLASH_DRIVER_NAME} 0x14000000 0 0 0 ${TARGET}.cm4 external
+ flash bank ${_CHIPNAME}_work_sysap virtual 0x14000000 0 0 0 ${TARGET}.sysap ${_CHIPNAME}_work_cm4 }
+ if {$_ENABLE_SFLASH} { flash bank ${_CHIPNAME}_sflash_sysap ${_FLASH_DRIVER_NAME} 0x16000000 0 0 0 ${TARGET}.sysap external
+ flash bank ${_CHIPNAME}_sflash_cm4 virtual 0x16000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_sflash_sysap }
+ if {$_ENABLE_EFUSE} { flash bank ${_CHIPNAME}_efuse_sysap ${_FLASH_DRIVER_NAME}_efuse 0x90700000 1024 1 1 ${TARGET}.sysap external
+ flash bank ${_CHIPNAME}_efuse_cm4 virtual 0x90700000 1024 1 1 ${TARGET}.cm4 ${_CHIPNAME}_efuse_sysap }
+
+ if { ![info exists DISABLE_SMIF] } {
+ flash bank ${_CHIPNAME}_smif_cm4 cmsis_flash 0x18000000 0 4 4 ${TARGET}.cm4 ../flm/cypress/cat1a/$_QSPI_FLASHLOADER 0x1000 prefer_sector_erase
+ flash bank ${_CHIPNAME}_smif_sysap virtual 0x18000000 0 4 4 ${TARGET}.sysap ${_CHIPNAME}_smif_cm4 }
+
+ psoc6 set_region_size ${_CHIPNAME}_main_cm4 $_FLASH_RESTRICTION_SIZE
+
+} elseif { $TARGET_AP eq "cm0_cm4_ap" } {
+
+ flash bank ${_CHIPNAME}_main_cm0 ${_FLASH_DRIVER_NAME} 0x10000000 0 0 0 ${TARGET}.cm0 external
+ flash bank ${_CHIPNAME}_main_cm4 virtual 0x10000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_main_cm0
+ flash bank ${_CHIPNAME}_main_sysap virtual 0x10000000 0 0 0 ${TARGET}.sysap ${_CHIPNAME}_main_cm0
+ if {$_ENABLE_WFLASH} { flash bank ${_CHIPNAME}_work_cm0 ${_FLASH_DRIVER_NAME} 0x14000000 0 0 0 ${TARGET}.cm0 external
+ flash bank ${_CHIPNAME}_work_cm4 virtual 0x14000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_work_cm0
+ flash bank ${_CHIPNAME}_work_sysap virtual 0x14000000 0 0 0 ${TARGET}.sysap ${_CHIPNAME}_work_cm0 }
+ if {$_ENABLE_SFLASH} { flash bank ${_CHIPNAME}_sflash_sysap ${_FLASH_DRIVER_NAME} 0x16000000 0 0 0 ${TARGET}.sysap external
+ flash bank ${_CHIPNAME}_sflash_cm0 virtual 0x16000000 0 0 0 ${TARGET}.cm0 ${_CHIPNAME}_sflash_sysap
+ flash bank ${_CHIPNAME}_sflash_cm4 virtual 0x16000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_sflash_sysap }
+ if {$_ENABLE_EFUSE} { flash bank ${_CHIPNAME}_efuse_sysap ${_FLASH_DRIVER_NAME}_efuse 0x90700000 1024 1 1 ${TARGET}.sysap external
+ flash bank ${_CHIPNAME}_efuse_cm0 virtual 0x90700000 1024 1 1 ${TARGET}.cm0 ${_CHIPNAME}_efuse_sysap
+ flash bank ${_CHIPNAME}_efuse_cm4 virtual 0x90700000 1024 1 1 ${TARGET}.cm4 ${_CHIPNAME}_efuse_sysap }
+
+ if { ![info exists DISABLE_SMIF] } {
+ flash bank ${_CHIPNAME}_smif_cm0 cmsis_flash 0x18000000 0 4 4 ${TARGET}.cm0 ../flm/cypress/cat1a/$_QSPI_FLASHLOADER 0x1000 prefer_sector_erase
+ flash bank ${_CHIPNAME}_smif_sysap virtual 0x18000000 0 4 4 ${TARGET}.sysap ${_CHIPNAME}_smif_cm0
+ flash bank ${_CHIPNAME}_smif_cm4 virtual 0x18000000 0 4 4 ${TARGET}.cm4 ${_CHIPNAME}_smif_cm0 }
+
+ psoc6 set_region_size ${_CHIPNAME}_main_cm0 $_FLASH_RESTRICTION_SIZE
+
+} else {
+ puts stderr "Error: Invalid TARGET_AP: $TARGET_AP, please use one of the following: sys_ap, cm0_ap, cm4_ap, cm0_cm4_ap"
+ shutdown
+}
+
+targets ${TARGET}.sysap
+reset_config srst_only srst_gates_jtag
+
+proc erase_all {} {
+ lset banks [flash list]
+ for {set i [expr {[llength $banks] - 1}]} { $i >= 0 } { set i [expr {$i - 1}]} {
+ set bank [lindex $banks $i]
+ if { $bank(base) == 0x10000000 || \
+ $bank(base) == 0x14000000 || \
+ $bank(base) == 0x18000000 } {
+ echo "Erasing flash bank @[format 0x%08X $bank(base)]..."
+ catch {flash erase_sector $i 0 last}
+ }
+ }
+}
+
+add_help_text erase_all "Erases all flash banks (in reverse order, for SMIF compatibility)"
diff --git a/scripts/target/mxs40/traveo2_68m_common.cfg b/scripts/target/mxs40/traveo2_68m_common.cfg
new file mode 100644
index 0000000..46a8726
--- /dev/null
+++ b/scripts/target/mxs40/traveo2_68m_common.cfg
@@ -0,0 +1,110 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Common configuration for TRAVEO™II family of microcontrollers.
+#
+
+source [find target/swj-dp.tcl]
+source [find target/mxs40/mxs40_common.cfg]
+
+if { [info exists WORKAREAADDR] } {
+ set _WA_ADDR $WORKAREAADDR
+ unset WORKAREAADDR
+} else {
+ set _WA_ADDR 0x28000800
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WA_SIZE $WORKAREASIZE
+ unset WORKAREASIZE
+} else {
+ set _WA_SIZE 0x8000
+}
+
+# (large_sector_num << 16) | small_sector_num
+set ${_CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE [ expr {($MAIN_LARGE_SECTOR_NUM << 16) | $MAIN_SMALL_SECTOR_NUM} ]
+set ${_CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE [ expr {($WORK_LARGE_SECTOR_NUM << 16) | $WORK_SMALL_SECTOR_NUM} ]
+
+if { $_ENABLE_ACQUIRE } {
+ kitprog3 acquire_config on 3 0 2
+}
+
+global TARGET
+set TARGET $_CHIPNAME.cpu
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+# makes the data access cacheable. This allows reading and writing data in the
+# CPU cache from the debugger, which is far more useful than going straight to
+# RAM when operating on typical variables, and is generally no worse when
+# operating on special memory locations.
+$_CHIPNAME.dap apsel 2
+$_CHIPNAME.dap apcsw [expr {(1 << 24) | (1 << 25) | (1 << 27) | (1 << 29) | (1 << 31)}]
+$_CHIPNAME.dap apsel 3
+$_CHIPNAME.dap apcsw [expr {(1 << 24) | (1 << 25) | (1 << 27) | (1 << 29) | (1 << 31)}]
+
+proc enable_cm7x {} {
+ mww 0x40261244 0x80000000
+ mww 0x40261248 0x80000000
+ mww 0x4020040C 15
+ mww 0x4020000C 15
+ mww 0x40201200 0x05FA0001
+ mww 0x40201200 0x05FA0003
+ mww 0x40201210 0x05FA0001
+ mww 0x40201210 0x05FA0003
+}
+
+global _TRAVEO_VARIANT_C2D_4M
+if { ![info exists _TRAVEO_VARIANT_C2D_4M] } {
+ set _TRAVEO_VARIANT_C2D_4M 0
+}
+
+if { $_TRAVEO_VARIANT_C2D_4M } {
+ set _FLASH_DRIVER_NAME traveo21
+} else {
+ set _FLASH_DRIVER_NAME traveo22
+}
+
+target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+${TARGET}.cm0 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
+${TARGET}.cm0 cortex_m reset_config sysresetreq
+${TARGET}.cm0 configure -event examine-end "cy_get_set_device_param ${_FLASH_DRIVER_NAME} ${_CHIPNAME}_main_cm0 ${_CHIPNAME}_work_cm0; enable_cm7x"
+${TARGET}.cm0 configure -event reset-deassert-post "mxs40_reset_deassert_post traveo2 ${TARGET}.cm0; enable_cm7x"
+
+target create ${TARGET}.cm70 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
+${TARGET}.cm70 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
+${TARGET}.cm70 configure -event reset-assert {}
+${TARGET}.cm70 configure -event reset-deassert-post "mxs40_reset_deassert_post traveo2 ${TARGET}.cm70"
+
+flash bank ${_CHIPNAME}_main_cm0 ${_FLASH_DRIVER_NAME} 0x10000000 0 0 0 ${TARGET}.cm0
+flash bank ${_CHIPNAME}_work_cm0 ${_FLASH_DRIVER_NAME} 0x14000000 0 0 0 ${TARGET}.cm0
+flash bank ${_CHIPNAME}_super_cm0 ${_FLASH_DRIVER_NAME} 0x17000000 0 0 0 ${TARGET}.cm0
+flash bank ${_CHIPNAME}_efuse_cm0 ${_FLASH_DRIVER_NAME}_efuse 0x90700000 1024 1 1 ${TARGET}.cm0 external
+
+flash bank ${_CHIPNAME}_main_cm70 virtual 0x10000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_main_cm0
+flash bank ${_CHIPNAME}_work_cm70 virtual 0x14000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_work_cm0
+flash bank ${_CHIPNAME}_super_cm70 virtual 0x17000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_super_cm0
+flash bank ${_CHIPNAME}_efuse_cm70 virtual 0x90700000 1024 1 1 ${TARGET}.cm70 ${_CHIPNAME}_efuse_cm0 external
+
+if { $_TRAVEO_VARIANT_C2D_4M == 0} {
+ target create ${TARGET}.cm71 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -coreid 2
+ ${TARGET}.cm71 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
+ ${TARGET}.cm71 configure -event reset-assert {}
+ ${TARGET}.cm71 configure -event reset-deassert-post "mxs40_reset_deassert_post traveo2 ${TARGET}.cm71"
+
+ flash bank ${_CHIPNAME}_main_cm71 virtual 0x10000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_main_cm0
+ flash bank ${_CHIPNAME}_work_cm71 virtual 0x14000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_work_cm0
+ flash bank ${_CHIPNAME}_super_cm71 virtual 0x17000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_super_cm0
+ flash bank ${_CHIPNAME}_efuse_cm71 virtual 0x90700000 1024 1 1 ${TARGET}.cm71 ${_CHIPNAME}_efuse_cm0 external
+}
+
+unset _TRAVEO_VARIANT_C2D_4M
+
+targets ${TARGET}.cm0
+
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME bs -irlen 4 -expected-id 0
+}
diff --git a/scripts/target/mxs40/traveo2_common.cfg b/scripts/target/mxs40/traveo2_common.cfg
new file mode 100644
index 0000000..3aa509f
--- /dev/null
+++ b/scripts/target/mxs40/traveo2_common.cfg
@@ -0,0 +1,65 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Common configuration for TRAVEO™II family of microcontrollers.
+#
+
+source [find target/swj-dp.tcl]
+source [find target/mxs40/mxs40_common.cfg]
+
+if { [info exists WORKAREAADDR] } {
+ set _WA_ADDR $WORKAREAADDR
+ unset WORKAREAADDR
+} else {
+ set _WA_ADDR 0x08000800
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WA_SIZE $WORKAREASIZE
+ unset WORKAREASIZE
+} else {
+ set _WA_SIZE 0x8000
+}
+
+# (large_sector_num << 16) | small_sector_num
+set ${_CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE [ expr {($MAIN_LARGE_SECTOR_NUM << 16) | $MAIN_SMALL_SECTOR_NUM} ]
+set ${_CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE [ expr {($WORK_LARGE_SECTOR_NUM << 16) | $WORK_SMALL_SECTOR_NUM} ]
+
+if { $_ENABLE_ACQUIRE } {
+ kitprog3 acquire_config on 3 0 2
+}
+
+global TARGET
+set TARGET $_CHIPNAME.cpu
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+${TARGET}.cm0 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
+
+flash bank ${_CHIPNAME}_main_cm0 traveo21 0x10000000 0 0 0 ${TARGET}.cm0
+flash bank ${_CHIPNAME}_work_cm0 traveo21 0x14000000 0 0 0 ${TARGET}.cm0
+flash bank ${_CHIPNAME}_super_cm0 traveo21 0x17000000 0 0 0 ${TARGET}.cm0
+flash bank ${_CHIPNAME}_efuse_cm0 traveo21_efuse 0x90700000 1024 1 1 ${TARGET}.cm0 external
+
+${TARGET}.cm0 cortex_m reset_config sysresetreq
+${TARGET}.cm0 configure -event reset-deassert-post "mxs40_reset_deassert_post traveo2 ${TARGET}.cm0"
+${TARGET}.cm0 configure -event examine-end "cy_get_set_device_param traveo21 ${_CHIPNAME}_main_cm0 ${_CHIPNAME}_work_cm0"
+
+target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
+${TARGET}.cm4 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
+
+flash bank ${_CHIPNAME}_main_cm4 virtual 0x10000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_main_cm0
+flash bank ${_CHIPNAME}_work_cm4 virtual 0x14000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_work_cm0
+flash bank ${_CHIPNAME}_super_cm4 virtual 0x17000000 0 0 0 ${TARGET}.cm4 ${_CHIPNAME}_super_cm0
+flash bank ${_CHIPNAME}_efuse_cm4 virtual 0x90700000 1024 1 1 ${TARGET}.cm4 ${_CHIPNAME}_efuse_cm0 external
+
+${TARGET}.cm4 configure -event reset-deassert-post "mxs40_reset_deassert_post traveo2 ${TARGET}.cm4"
+${TARGET}.cm4 configure -event reset-assert {}
+
+targets ${TARGET}.cm0
+
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME bs -irlen 4 -expected-id 0
+}
diff --git a/scripts/target/mxs40/traveo2_detect_geometry.cfg b/scripts/target/mxs40/traveo2_detect_geometry.cfg
new file mode 100644
index 0000000..d68b998
--- /dev/null
+++ b/scripts/target/mxs40/traveo2_detect_geometry.cfg
@@ -0,0 +1,214 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+
+source [find target/mxs40/cympn_parser.cfg]
+
+#
+# extracts number of large and small sectors from passed geometry
+#
+# arguments:
+# geometry - the geometry to be parsed
+# large_sect_tbl - the table that represents large sector coding
+# small_sect_tbl - the table that represents small sector coding
+#
+# return:
+# number of large and small sectors in form [Large_sect_count << 16 | Small_sect_count]
+#
+proc get_sectors_from_geom { geometry large_sect_tbl small_sect_tbl } {
+ set geometry_msk [expr {$geometry & 0x07}]
+ set num_sup_comb [llength $large_sect_tbl]
+
+ if { $geometry_msk >= $num_sup_comb } {
+ puts stderr "Error: Cannot get sector count for Flash Geometry = $geometry_msk"
+ return -1
+ }
+
+ set large_sect_num [lindex $large_sect_tbl $geometry_msk]
+ set small_sect_num [lindex $small_sect_tbl $geometry_msk]
+
+ set ret_value [expr {($large_sect_num << 16) | $small_sect_num}]
+
+ return $ret_value
+}
+
+#
+# converts flash size to geometry
+#
+# arguments:
+# size_kb - the flash size in kb
+# size_tbl - the table that represents flash size to geometry coding
+#
+# return:
+# flash geometry that represents passed flash size
+#
+proc get_geom_from_size {size_kb size_tbl} {
+
+ set num_elements [llength $size_tbl]
+ set geometry -1
+
+ for {set i 0} { $i < $num_elements } {incr i} {
+ set size [lindex $size_tbl $i]
+ if {$size_kb == $size} {
+ set geometry $i
+ break
+ }
+ }
+
+ return $geometry
+}
+
+#
+# detects flash geometry of TRAVEO™II devices
+#
+# tryies to get TRAVEO™II geometry from the:
+# 1. $MAIN_FLASH_SIZE_OVERRIDE and $WORK_FLASH_SIZE_OVERRIDE if defined
+# 2. Flash GEOMETRY register
+# 3. UDD
+#
+# arguments:
+# main_reg_name - the name of main region to be set
+# work_reg_name - the name of work region to be set
+#
+proc traveo2_detect_geometry { target_arch main_reg_name work_reg_name} {
+ set tgt [target current]
+ set CHIPNAME [string range ${tgt} 0 [expr {[string first "." ${tgt}] - 1}]]
+ global ${CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE
+ global ${CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE
+
+ set detected_main_sectors -1
+ set detected_work_sectors -1
+
+ # main / work size where index corresponds to flash geometry
+ set main_size_kb_tbl { 576 1088 2112 4160 6336 8384 }
+ set work_size_kb_tbl { 0 64 96 128 256 512 }
+
+ # main flash geometry decoding
+ # main size kb 576 1088 2112 4160 6336 8384
+ set main_large_sect_num_tbl { 14 30 62 126 190 254 }
+ set main_small_sect_num_tbl { 16 16 16 16 32 32 }
+
+ # work flash geometry decoding
+ # work size kb 0 64 96 128 256 512
+ set work_large_sect_num_tbl { 0 24 36 48 96 192 }
+ set work_small_sect_num_tbl { 0 128 192 256 512 1024 }
+
+ # 1. Checking ${CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE / ${CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE
+ if { [info exists ${CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE] } {
+ if { [set ${CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE] } {
+ set detected_main_sectors [set ${CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE]
+ #each large sector conatins 32 KB
+ set m_size_large [expr {([set ${CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE] >> 16) << 5}]
+ #each small sector conatins 8 KB
+ set m_size_small [expr {([set ${CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE] & 0xFFFF) << 3}]
+ echo "** Use overriden Main Flash size, kb: [expr {$m_size_large + $m_size_small}]"
+ }
+ }
+
+ if { [info exists ${CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE] } {
+ if { [set ${CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE] } {
+ set detected_work_sectors [set ${CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE]
+ #each large sector conatins 2 KB
+ set w_size_large [expr {([set ${CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE] >> 16) << 1}]
+ #each small sector conatins 128 B
+ set w_size_small [expr {([set ${CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE] & 0xFFFF) >> 3}]
+ echo "** Use overriden Work Flash size, kb: [expr {$w_size_large + $w_size_small}]"
+ }
+ }
+
+ # print MPN
+ set main_work_size [cyp_get_mpn_work_main_size "traveo2"]
+
+ set flash_geom 0
+ if { $detected_main_sectors == -1 || $detected_work_sectors == -1 } {
+ # 2. Use UDD if flash size is not overriden
+ if { [llength $main_work_size] == 2} {
+
+ if { $detected_main_sectors == -1 } {
+ set main_size [lindex $main_work_size 0]
+ echo "** Detected Main Flash size, kb: $main_size"
+
+ set geom [get_geom_from_size $main_size $main_size_kb_tbl]
+
+ if { $geom == -1 } {
+ puts stderr "Error: Cannot get geometry for main size kb = $main_size"
+ return
+ }
+ set flash_geom [expr {($flash_geom & 0xF8) | $geom} ]
+ }
+
+ if { $detected_work_sectors == -1 } {
+ set work_size [lindex $main_work_size 1]
+ echo "** Detected Work Flash size, kb: $work_size"
+
+ set geom [get_geom_from_size $work_size $work_size_kb_tbl]
+
+ if { $geom == -1 } {
+ puts stderr "Error: Cannot get geometry for work size kb = $work_size"
+ return
+ }
+
+ set flash_geom [expr {($flash_geom & 0xC7) | ($geom << 3)}]
+ }
+ }
+
+ if {!$flash_geom} {
+
+ # 3. Read Flash GEOMETRY register if main/works sectors are not detected yet
+ set MEM_SPCIF3_GEOMETRY 0x4024F00C
+
+ catch { set flash_geom [expr {[mrw $MEM_SPCIF3_GEOMETRY] & 0x3F}] }
+
+ if {$flash_geom} {
+ if { $detected_main_sectors == -1 } {
+ set m_size [lindex $main_size_kb_tbl [expr {$flash_geom & 0x07}]]
+ echo "** Detected Main Flash size from geometry register, kb: $m_size"
+ }
+
+ if { $detected_work_sectors == -1 } {
+ set w_size [lindex $work_size_kb_tbl [expr {$flash_geom >> 3}]]
+ echo "** Detected Work Flash size from geometry register, kb: $w_size"
+ }
+ }
+ }
+
+ if { !$flash_geom} {
+ puts stderr "Error: Flash geometry was not detected"
+ return
+ }
+
+ # get main/works sectors from geometry if they are not detected yet
+ if { $detected_main_sectors == -1 } {
+ set detected_main_sectors [get_sectors_from_geom $flash_geom $main_large_sect_num_tbl $main_small_sect_num_tbl]
+
+ if { $detected_main_sectors == -1 } {
+ puts stderr "Error: Cannot get sectors for main flash from geometry = $flash_geom"
+ return
+ }
+ }
+
+ if { $detected_work_sectors == -1 } {
+ set work_geom [expr {$flash_geom >> 3}]
+ set detected_work_sectors [get_sectors_from_geom $work_geom $work_large_sect_num_tbl $work_small_sect_num_tbl]
+
+ if { $detected_work_sectors == -1 } {
+ puts stderr "Error: Cannot get sectors for work flash from geometry = $work_geom"
+ return
+ }
+ }
+ }
+
+ if { $detected_main_sectors == -1 } {
+ puts stderr "Error: Main Flash geometry was not detected"
+ return
+ }
+
+ if { $detected_work_sectors == -1 } {
+ puts stderr "Error: Work Flash geometry was not detected"
+ return
+ }
+
+ if { ${main_reg_name} != "" } { traveo2 set_region_size ${main_reg_name} $detected_main_sectors }
+ if { ${work_reg_name} != "" } { traveo2 set_region_size ${work_reg_name} $detected_work_sectors }
+}
diff --git a/scripts/target/psoc4.cfg b/scripts/target/psoc4.cfg
new file mode 100644
index 0000000..a14a06f
--- /dev/null
+++ b/scripts/target/psoc4.cfg
@@ -0,0 +1,227 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC4 family of microcontrollers.
+#
+
+#
+# PSoC 4 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+adapter speed 2000
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME psoc4
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x800
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x0bb11477
+}
+
+global _PSOC4_USE_MEM_AP
+if { [info exists PSOC4_USE_MEM_AP] } {
+ set _PSOC4_USE_MEM_AP $PSOC4_USE_MEM_AP
+} else {
+ set _PSOC4_USE_MEM_AP 0
+}
+
+###############################################################################
+# KitProg3 acquire/power control stuff
+###############################################################################
+global _PSOC4_USE_ACQUIRE
+global _ENABLE_POWER_SUPPLY
+if { [adapter name] eq "kitprog3" } {
+ if { [info exists PSOC4_USE_ACQUIRE] } {
+ if { ( $PSOC4_USE_ACQUIRE != 0 ) && ( $PSOC4_USE_ACQUIRE != 1 ) && ( $PSOC4_USE_ACQUIRE != 2 ) } {
+ puts stderr "** Invalid PSOC4_USE_ACQUIRE value ($PSOC4_USE_ACQUIRE). Allowed values are:"
+ puts stderr "** 0 - Test Mode acquisition is disabled"
+ puts stderr "** 1 - Enable acquisition using XRES method"
+ puts stderr "** 2 - Enable acquisition using power-cycle method"
+ terminate
+ }
+
+ if { $PSOC4_USE_ACQUIRE == 2 && ![info exists ENABLE_POWER_SUPPLY] } {
+ set ENABLE_POWER_SUPPLY default
+ }
+
+ set _PSOC4_USE_ACQUIRE $PSOC4_USE_ACQUIRE
+ } else {
+ set _PSOC4_USE_ACQUIRE 1
+ }
+
+ if { [info exists ENABLE_POWER_SUPPLY] } {
+ set _ENABLE_POWER_SUPPLY $ENABLE_POWER_SUPPLY
+ } else {
+ set _ENABLE_POWER_SUPPLY 0
+ }
+} else {
+ set _PSOC4_USE_ACQUIRE 0
+ set _ENABLE_POWER_SUPPLY 0
+ echo "** Test Mode acquire not supported by selected adapter"
+}
+
+if { $_PSOC4_USE_ACQUIRE } {
+ echo "** Auto-acquire enabled, use \"set PSOC4_USE_ACQUIRE 0\" to disable"
+ # set acquire mode: power cycle = 2, reset otherwise
+ if { $_PSOC4_USE_ACQUIRE == 2 } {
+ kitprog3 acquire_config on 0 1 3
+ } else {
+ kitprog3 acquire_config on 0 0 3
+ }
+}
+
+if { [string is integer $_ENABLE_POWER_SUPPLY]} {
+ if { $_ENABLE_POWER_SUPPLY } {
+ echo "** Enabling target power ($_ENABLE_POWER_SUPPLY mV) \"set ENABLE_POWER_SUPPLY 0\" to disable"
+ kitprog3 power_config on $_ENABLE_POWER_SUPPLY
+ }
+} elseif { $_ENABLE_POWER_SUPPLY == "default" } {
+ echo "** Enabling target power (default voltage) \"set ENABLE_POWER_SUPPLY 0\" to disable"
+ kitprog3 power_config on
+} else {
+ puts stderr "Invalid ENABLE_POWER_SUPPLY value - '$_ENABLE_POWER_SUPPLY' (integer or 'default' expected)"
+ terminate
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+if {$_PSOC4_USE_MEM_AP == 1} {
+ target create $_TARGETNAME mem_ap -dap $_CHIPNAME.dap -ap-num 0 -coreid 255
+ reset_config srst_only
+} else {
+ target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+ $_TARGETNAME cortex_m reset_config sysresetreq
+ $_TARGETNAME configure -event examine-end "psoc4 silicon_info"
+}
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+$_TARGETNAME configure -event reset-deassert-post "psoc4_deassert_post $_TARGETNAME"
+
+flash bank $_CHIPNAME.mflash psoc4 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.sflash psoc4 0x0FFFF200 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.flashp psoc4_flash_prot 0x90400000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.chipp psoc4_flash_prot 0x90600000 1 1 1 $_TARGETNAME
+
+add_verify_range $_TARGETNAME 0x00000000 0x00080000
+add_verify_range $_TARGETNAME 0x0FFFF200 0x00000800
+add_verify_range $_TARGETNAME 0x20000000 0x00040000
+add_verify_range $_TARGETNAME 0x90400000 0x00000400
+
+proc init_reset { mode } {
+ global RESET_MODE
+ set RESET_MODE $mode
+}
+
+proc acquire { target } {
+ global _PSOC4_USE_ACQUIRE
+ global _PSOC4_USE_MEM_AP
+
+ if { $_PSOC4_USE_ACQUIRE == 0 } {
+ echo "----------------------------------------------------------------"
+ echo "Test Mode acquire disabled. Use 'set PSOC4_USE_ACQUIRE 1' to enable"
+ echo "----------------------------------------------------------------"
+ error
+ }
+
+ # acquire will leave CPU in running state
+ # openocd does not expect this
+ # ignore possible error e.g. when listen window is disabled
+ catch {[adapter name] acquire_psoc}
+
+ # we need to re-examine and halt target manually
+ ${target} arp_examine
+ ${target} arp_poll
+ ${target} arp_poll
+
+ # In the PROTECTED mode access is locked for everything except System Calls
+ if { $_PSOC4_USE_MEM_AP == 1 } {
+ echo "** Device acquired successfully"
+ return
+ }
+
+ # Ensure target has stopped on WFI instruction
+ set loops 200
+ while { $loops } {
+ set sleeping [ expr {[mrw 0xE000EDF0] & 0x00040000} ]
+ if { $sleeping } break
+ set loops [ expr {$loops - 1} ]
+ sleep 10
+ }
+
+ if { $sleeping } {
+ ${target} arp_halt
+ ${target} arp_waitstate halted 100
+ echo "** Device acquired successfully"
+ return
+ }
+
+ echo "--------------------------------------------"
+ echo "Failed to acquire PSoC 4 device in Test Mode"
+ echo "--------------------------------------------"
+ error
+}
+
+proc mrw { ADDR } {
+ set foo(0) 0
+ if ![ catch { mem2array foo 32 $ADDR 1 } msg ] {
+ return $foo(0)
+ } else {
+ error $msg
+ }
+}
+
+# Utility to make 'reset halt' work as reset;halt on a target
+# It does not prevent running code after reset
+proc psoc4_deassert_post { target } {
+ global _PSOC4_USE_ACQUIRE
+ global _PSOC4_USE_MEM_AP
+ global RESET_MODE
+
+ if { $RESET_MODE ne "run" } {
+ if { $_PSOC4_USE_ACQUIRE } {
+ acquire $target
+ }
+
+ # PSoC 4 cleares AP registers including TAR during reset
+ # Force examine to synchronize OpenOCD target status
+ $target arp_examine
+ catch {$target arp_poll}
+ catch {$target arp_poll}
+ set st [$target curstate]
+
+ if { $st eq "reset" } {
+ # we assume running state follows
+ # if reset accidentally halts, waiting is useless
+ catch { $target arp_waitstate running 100 }
+ set st [$target curstate]
+ }
+
+ if { $st eq "running" } {
+ echo "** $target: Ran after reset and before halt..."
+ if { !$_PSOC4_USE_ACQUIRE && !$_PSOC4_USE_MEM_AP } {
+ sleep 100
+ psoc4 reset_halt
+ } else {
+ $target arp_halt
+ }
+ $target arp_waitstate halted 100
+ }
+ }
+ psoc4 disable_cpu_read_relocations
+}
diff --git a/scripts/target/psoc4500.cfg b/scripts/target/psoc4500.cfg
new file mode 100644
index 0000000..91b764e
--- /dev/null
+++ b/scripts/target/psoc4500.cfg
@@ -0,0 +1,13 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC4500 family of microcontrollers.
+#
+
+if { ![info exists CHIPNAME] } {
+ set CHIPNAME psoc4500
+}
+
+source [find target/psoc6_256k.cfg]
+
diff --git a/scripts/target/psoc4hv_a0.cfg b/scripts/target/psoc4hv_a0.cfg
new file mode 100644
index 0000000..65a9661
--- /dev/null
+++ b/scripts/target/psoc4hv_a0.cfg
@@ -0,0 +1,274 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC4-HV family of microcontrollers.
+#
+
+#
+# PSoC 4 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+adapter speed 2000
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME psoc4hv
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x800
+}
+
+###############################################################################
+# KitProg3 acquire/power control stuff
+###############################################################################
+global ${_CHIPNAME}::use_acquire
+global ${_CHIPNAME}::enable_power_supply
+if { [adapter name] eq "kitprog3" } {
+ if { [info exists PSOC4_USE_ACQUIRE] } {
+ if { ( $PSOC4_USE_ACQUIRE != 0 ) && ( $PSOC4_USE_ACQUIRE != 1 ) && ( $PSOC4_USE_ACQUIRE != 2 ) } {
+ puts stderr "** Invalid PSOC4_USE_ACQUIRE value ($PSOC4_USE_ACQUIRE). Allowed values are:"
+ puts stderr "** 0 - Test Mode acquisition is disabled"
+ puts stderr "** 1 - Enable acquisition using XRES method"
+ puts stderr "** 2 - Enable acquisition using power-cycle method"
+ terminate
+ }
+
+ if { $PSOC4_USE_ACQUIRE == 2 && ![info exists ENABLE_POWER_SUPPLY] } {
+ set ENABLE_POWER_SUPPLY default
+ }
+
+ set ${_CHIPNAME}::use_acquire $PSOC4_USE_ACQUIRE
+ } else {
+ set ${_CHIPNAME}::use_acquire 1
+ }
+
+ if { [info exists ENABLE_POWER_SUPPLY] } {
+ set ${_CHIPNAME}::enable_power_supply $ENABLE_POWER_SUPPLY
+ } else {
+ set ${_CHIPNAME}::enable_power_supply 0
+ }
+} else {
+ set ${_CHIPNAME}::use_acquire 0
+ set ${_CHIPNAME}::enable_power_supply 0
+ echo "** Test Mode acquire not supported by selected adapter"
+}
+
+if { [set ${_CHIPNAME}::use_acquire] } {
+ echo "** Auto-acquire enabled, use \"set PSOC4_USE_ACQUIRE 0\" to disable"
+ # set acquire mode: power cycle = 2, reset otherwise
+ if { [set ${_CHIPNAME}::use_acquire] == 2 } {
+ kitprog3 acquire_config on 0 1 3
+ } else {
+ kitprog3 acquire_config on 0 0 3
+ }
+}
+
+if { [string is integer [set ${_CHIPNAME}::enable_power_supply]]} {
+ if { [set ${_CHIPNAME}::enable_power_supply] } {
+ echo "** Enabling target power ([set ${_CHIPNAME}::enable_power_supply] mV) \"set ENABLE_POWER_SUPPLY 0\" to disable"
+ kitprog3 power_config on [set ${_CHIPNAME}::enable_power_supply]
+ }
+} elseif { [set ${_CHIPNAME}::enable_power_supply]== "default" } {
+ echo "** Enabling target power (default voltage) \"set ENABLE_POWER_SUPPLY 0\" to disable"
+ kitprog3 power_config on
+} else {
+ puts stderr "Invalid ENABLE_POWER_SUPPLY value - '[set ${_CHIPNAME}::enable_power_supply]' (integer or 'default' expected)"
+ terminate
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Order of examination is important
+target create $_CHIPNAME.mem_ap mem_ap -dap $_CHIPNAME.dap -ap-num 0 -coreid 255
+target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap -ap-num 0
+
+$_CHIPNAME.cpu cortex_m reset_config sysresetreq
+$_CHIPNAME.cpu configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+$_CHIPNAME.cpu configure -event reset-deassert-post "psoc4_deassert_post $_CHIPNAME.cpu"
+
+proc check_protection {} {
+ set target [target current]
+ set dap [$target cget -dap]
+
+ for { set i 0 } { $i < 3 } { incr i } {
+ $dap apreg 0 0x04 0xE000ED00
+ if { [catch {$dap apreg 0 0x0C}] == 0 } {
+ return 0
+ }
+ }
+
+ return 1
+}
+
+proc psoc_soft_acquire {} {
+ echo "** Attempting to soft-acquire the chip in Test Mode..."
+
+ local_echo off
+ scan [debug_level] "debug_level: %d" old_level
+ scan [adapter speed] "adapter speed: %d kHz" adapter_speed
+ debug_level -1
+ reset_config srst_only
+ adapter speed 4000
+ adapter assert srst
+ sleep 25
+ adapter deassert srst
+ catch { mww 0x40030014 0x80000000 }
+ catch { mww 0x40030014 0x80000000 }
+ catch { mww 0x40030014 0x80000000 }
+ catch { mww 0x40030014 0x80000000 }
+ catch { mww 0x40030014 0x80000000 }
+ catch { mww 0x40030014 0x80000000 }
+ catch { mww 0x40030014 0x80000000 }
+ catch { mww 0x40030014 0x80000000 }
+ catch { mww 0x40030014 0x80000000 }
+ if { [catch { mww 0x40030014 0x80000000 }] != 0 } {
+ puts stderr "** Unable to write to SRSS.TST_MODE register"
+ }
+
+ reset_config none
+ adapter speed $adapter_speed
+ debug_level $old_level
+ local_echo on
+}
+
+$_CHIPNAME.mem_ap configure -event examine-end {
+ global _CHIPNAME
+ global ${_CHIPNAME}::is_locked
+
+ if { [info exist ${_CHIPNAME}::is_locked] } return
+
+ local_echo off
+ set ${_CHIPNAME}::is_locked [check_protection]
+ local_echo on
+
+ if { [set ${_CHIPNAME}::is_locked] } {
+ puts stderr "Warn: Chip's resources access is locked down."
+ puts stderr " The state can be set back to OPEN but only after completely erasing the flash."
+ puts stderr " To do so, perform mass erase operation using 'psoc4 mass_erase' command."
+ if { [set ${_CHIPNAME}::use_acquire] == 0 } { psoc_soft_acquire }
+ ${_CHIPNAME}.cpu configure -defer-examine
+ ${_CHIPNAME}.cpu configure -event reset-assert {}
+ targets ${_CHIPNAME}.mem_ap
+ catch { psoc4 silicon_info }
+ } else {
+ targets $_CHIPNAME.cpu
+ $_CHIPNAME.cpu arp_examine
+ catch { psoc4 silicon_info }
+ }
+}
+
+flash bank $_CHIPNAME.mflash psoc4hv 0x00000000 0 4 4 $_CHIPNAME.cpu 0
+flash bank $_CHIPNAME.wflash psoc4hv 0x1F000000 0 4 4 $_CHIPNAME.cpu 1
+flash bank $_CHIPNAME.sflash0 psoc4hv 0x0FFFF000 0 4 4 $_CHIPNAME.cpu 0
+flash bank $_CHIPNAME.sflash1 psoc4hv 0x0FFFF000 0 4 4 $_CHIPNAME.cpu 1
+
+proc init_reset { mode } {
+ global RESET_MODE
+ set RESET_MODE $mode
+}
+
+proc acquire { target } {
+ global _CHIPNAME
+ global ${_CHIPNAME}::is_locked
+ global ${_CHIPNAME}::use_acquire
+
+ if { ![set ${_CHIPNAME}::use_acquire] } {
+ echo "----------------------------------------------------------------"
+ echo "Test Mode acquire disabled. Use 'set PSOC4_USE_ACQUIRE 1' to enable"
+ echo "----------------------------------------------------------------"
+ error
+ }
+
+ # acquire will leave CPU in running state
+ # openocd does not expect this
+ # ignore possible error e.g. when listen window is disabled
+ catch {[adapter name] acquire_psoc}
+
+ # In the PROTECTED mode access is locked for everything except System Calls
+ if { [set ${_CHIPNAME}::is_locked] } {
+ echo "** Device acquired successfully"
+ return
+ }
+
+ # we need to re-examine and halt target manually
+ ${target} arp_examine
+ ${target} arp_poll
+ ${target} arp_poll
+
+ # Ensure target has stopped on WFI instruction
+ set loops 200
+ while { $loops } {
+ set sleeping [ expr {[mrw 0xE000EDF0] & 0x00040000} ]
+ if { $sleeping } break
+ set loops [ expr {$loops - 1} ]
+ sleep 10
+ }
+
+ if { $sleeping } {
+ ${target} arp_halt
+ ${target} arp_waitstate halted 100
+ echo "** Device acquired successfully"
+ return
+ }
+
+ echo "--------------------------------------------"
+ echo "Failed to acquire PSoC 4 device in Test Mode"
+ echo "--------------------------------------------"
+ error
+}
+
+# Utility to make 'reset halt' work as reset;halt on a target
+# It does not prevent running code after reset
+proc psoc4_deassert_post { target } {
+ global _CHIPNAME
+ global ${_CHIPNAME}::is_locked
+ global ${_CHIPNAME}::use_acquire
+
+ global RESET_MODE
+
+ if { $RESET_MODE ne "run" } {
+ if { [set ${_CHIPNAME}::use_acquire] } {
+ acquire $target
+ }
+
+ if { [set ${_CHIPNAME}::is_locked] } return
+
+ if { ![set ${_CHIPNAME}::use_acquire] } {
+ psoc_soft_acquire
+ }
+
+ # PSoC 4 cleares AP registers including TAR during reset
+ # Force examine to synchronize OpenOCD target status
+ $target arp_examine
+ catch {$target arp_poll}
+ catch {$target arp_poll}
+ set st [$target curstate]
+
+ if { $st eq "reset" } {
+ # we assume running state follows
+ # if reset accidentally halts, waiting is useless
+ catch { $target arp_waitstate running 100 }
+ set st [$target curstate]
+ }
+
+ if { $st eq "running" } {
+ echo "** $target: Ran after reset and before halt..."
+ if { ![set ${_CHIPNAME}::use_acquire] } {
+ catch { psoc4 reset_halt }
+ } else {
+ $target arp_halt
+ }
+ $target arp_waitstate halted 100
+ }
+ }
+}
diff --git a/scripts/target/psoc5lp.cfg b/scripts/target/psoc5lp.cfg
new file mode 100644
index 0000000..c90fd42
--- /dev/null
+++ b/scripts/target/psoc5lp.cfg
@@ -0,0 +1,65 @@
+#
+# Cypress PSoC 5LP
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME psoc5lp
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPU_TAPID $CPUTAPID
+} else {
+ set _CPU_TAPID 0x4BA00477
+}
+
+if { [using_jtag] } {
+ set _CPU_DAP_ID $_CPU_TAPID
+} else {
+ set _CPU_DAP_ID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x2000
+}
+
+$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \
+ -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+source [find mem_helper.tcl]
+
+$_TARGETNAME configure -event reset-init {
+ # Configure Target Device (PSoC 5LP Device Programming Specification 5.2)
+
+ set PANTHER_DBG_CFG 0x4008000C
+ set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}]
+ mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0
+
+ set PM_ACT_CFG0 0x400043A0
+ mww $PM_ACT_CFG0 0xBF
+
+ set FASTCLK_IMO_CR 0x40004200
+ set FASTCLK_IMO_CR_F_RANGE_2 [expr {2 << 0}]
+ set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}]
+ mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+ cortex_m reset_config sysresetreq
+}
diff --git a/scripts/target/psoc6.cfg b/scripts/target/psoc6.cfg
new file mode 100644
index 0000000..5e4979b
--- /dev/null
+++ b/scripts/target/psoc6.cfg
@@ -0,0 +1,19 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC 6 family of microcontrollers.
+# PSoC 6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+# uncomment next line to use predefined main flash size
+# set MAIN_FLASH_SIZE 0x100000
+
+set CPUSS_PROTECTION_REG 0x40210500
+set QSPI_FLASHLOADER CY8C6xxx_SMIF.FLM
+
+set FLASH_DRIVER_NAME psoc6
+set MXS40_TARGET_DIE PSoC6ABLE2
+
+source [find target/mxs40/psoc6_common.cfg]
diff --git a/scripts/target/psoc6_256k.cfg b/scripts/target/psoc6_256k.cfg
new file mode 100644
index 0000000..8e4efa3
--- /dev/null
+++ b/scripts/target/psoc6_256k.cfg
@@ -0,0 +1,22 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC6A-256k family of microcontrollers.
+# PSoC 6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+# uncomment next line to use predefined main flash size
+# set MAIN_FLASH_SIZE 0x40000
+
+set CPUSS_PROTECTION_REG 0x402020C4
+set QSPI_FLASHLOADER CY8C6xxA_SMIF.FLM
+
+set FLASH_DRIVER_NAME psoc6_2m
+set MXS40_TARGET_DIE PSoC6A256K
+set PSOC6_JTAG_IRLEN 4
+set _HAS_WORKFLASH 0
+
+source [find target/mxs40/psoc6_common.cfg]
+
diff --git a/scripts/target/psoc6_2m.cfg b/scripts/target/psoc6_2m.cfg
new file mode 100644
index 0000000..e473f6a
--- /dev/null
+++ b/scripts/target/psoc6_2m.cfg
@@ -0,0 +1,19 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC6A-2M family of microcontrollers.
+# PSoC 6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+# uncomment next line to use predefined main flash size
+# set MAIN_FLASH_SIZE 0x200000
+
+set CPUSS_PROTECTION_REG 0x402020C4
+set QSPI_FLASHLOADER CY8C6xxA_SMIF.FLM
+
+set FLASH_DRIVER_NAME psoc6_2m
+set MXS40_TARGET_DIE PSoC6A2M
+
+source [find target/mxs40/psoc6_common.cfg]
diff --git a/scripts/target/psoc6_2m_secure.cfg b/scripts/target/psoc6_2m_secure.cfg
new file mode 100644
index 0000000..26859be
--- /dev/null
+++ b/scripts/target/psoc6_2m_secure.cfg
@@ -0,0 +1,31 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC64-2M family of microcontrollers.
+# PSoC 6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+global _FLASH_RESTRICTION_SIZE
+if { [info exists FLASH_RESTRICTION_SIZE] } {
+ set _FLASH_RESTRICTION_SIZE $FLASH_RESTRICTION_SIZE
+} else {
+ set _FLASH_RESTRICTION_SIZE 0x1D0000
+}
+echo "** Main Flash size limited to $_FLASH_RESTRICTION_SIZE bytes"
+
+set _WORKAREASIZE 0x1800
+set _WORKAREAADDR 0x080EE000
+
+set _WORKAREASIZE_CM 0x8000
+set _WORKAREAADDR_CM 0x08000000
+
+set _CHIPNAME psoc64
+set _FLASH_DRIVER_NAME psoc6_2m
+set _MAGIC_NUMBER_ADDR 0x080FE004
+set _QSPI_FLASHLOADER CY8C6xxA_SMIF_S25FL512S.FLM
+
+set MXS40_TARGET_DIE PSoC6A2M
+
+source [find target/mxs40/psoc6_secure_common.cfg]
diff --git a/scripts/target/psoc6_512k.cfg b/scripts/target/psoc6_512k.cfg
new file mode 100644
index 0000000..e129188
--- /dev/null
+++ b/scripts/target/psoc6_512k.cfg
@@ -0,0 +1,20 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC6A-512k family of microcontrollers.
+# PSoC 6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+# uncomment next line to use predefined main flash size
+# set MAIN_FLASH_SIZE 0x80000
+
+set CPUSS_PROTECTION_REG 0x402020C4
+set QSPI_FLASHLOADER CY8C6xxA_SMIF.FLM
+
+set FLASH_DRIVER_NAME psoc6_2m
+set MXS40_TARGET_DIE PSoC6A512K
+set PSOC6_JTAG_IRLEN 4
+
+source [find target/mxs40/psoc6_common.cfg]
diff --git a/scripts/target/psoc6_512k_secure.cfg b/scripts/target/psoc6_512k_secure.cfg
new file mode 100644
index 0000000..ee0ee6d
--- /dev/null
+++ b/scripts/target/psoc6_512k_secure.cfg
@@ -0,0 +1,35 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC64-512k family of microcontrollers.
+# PSoC 6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+global _FLASH_RESTRICTION_SIZE
+if { [info exists FLASH_RESTRICTION_SIZE] } {
+ set _FLASH_RESTRICTION_SIZE $FLASH_RESTRICTION_SIZE
+} else {
+ set _FLASH_RESTRICTION_SIZE 0x60000
+}
+echo "** Main Flash size limited to $_FLASH_RESTRICTION_SIZE bytes"
+
+set _WORKAREASIZE 0x2000
+set _WORKAREAADDR 0x0802E000
+
+set _WORKAREASIZE_CM 0x8000
+set _WORKAREAADDR_CM 0x08000000
+
+set _CHIPNAME psoc64
+set _FLASH_DRIVER_NAME psoc6_2m
+set _MAGIC_NUMBER_ADDR 0x0803E004
+set _QSPI_FLASHLOADER CY8C6xxA_SMIF_S25Hx512T.FLM
+
+set MXS40_TARGET_DIE PSoC6A512K
+
+if { ![info exists ENABLE_WFLASH] } {
+ set ENABLE_WFLASH 0
+}
+
+source [find target/mxs40/psoc6_secure_common.cfg]
diff --git a/scripts/target/psoc6_secure.cfg b/scripts/target/psoc6_secure.cfg
new file mode 100644
index 0000000..ea4c661
--- /dev/null
+++ b/scripts/target/psoc6_secure.cfg
@@ -0,0 +1,31 @@
+#
+# Copyright (C) <2019-2021>
+#
+#
+# Configuration script for Cypress PSoC64 family of microcontrollers.
+# PSoC 6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+global _FLASH_RESTRICTION_SIZE
+if { [info exists FLASH_RESTRICTION_SIZE] } {
+ set _FLASH_RESTRICTION_SIZE $FLASH_RESTRICTION_SIZE
+} else {
+ set _FLASH_RESTRICTION_SIZE 0xD0000
+}
+echo "** Main Flash size limited to $_FLASH_RESTRICTION_SIZE bytes"
+
+set _WORKAREASIZE 0x1800
+set _WORKAREAADDR 0x0802E000
+
+set _WORKAREASIZE_CM 0x8000
+set _WORKAREAADDR_CM 0x08000000
+
+set _CHIPNAME psoc64
+set _FLASH_DRIVER_NAME psoc6
+set _MAGIC_NUMBER_ADDR 0x08044804
+set _QSPI_FLASHLOADER CY8C6xxx_SMIF_S25Hx512T.FLM
+
+set MXS40_TARGET_DIE PSoC6ABLE2
+
+source [find target/mxs40/psoc6_secure_common.cfg]
diff --git a/scripts/target/swj-dp.tcl b/scripts/target/swj-dp.tcl
new file mode 100644
index 0000000..3fb0263
--- /dev/null
+++ b/scripts/target/swj-dp.tcl
@@ -0,0 +1,35 @@
+# ARM Debug Interface V5 (ADI_V5) utility
+# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
+# SW-DP and JTAG-DP targets don't need to switch based
+# on which transport is active.
+#
+# declare a JTAG or SWD Debug Access Point (DAP)
+# based on the transport in use with this session.
+# You can't access JTAG ops when SWD is active, etc.
+
+# params are currently what "jtag newtap" uses
+# because OpenOCD internals are still strongly biased
+# to JTAG .... but for SWD, "irlen" etc are ignored,
+# and the internals work differently
+
+# for now, ignore non-JTAG and non-SWD transports
+# (e.g. initial flash programming via SPI or UART)
+
+# split out "chip" and "tag" so we can someday handle
+# them more uniformly irlen too...)
+
+if [catch {transport select}] {
+ echo "Error: unable to select a session transport. Can't continue."
+ shutdown
+}
+
+proc swj_newdap {chip tag args} {
+ if [using_jtag] {
+ eval jtag newtap $chip $tag $args
+ } elseif [using_swd] {
+ eval swd newdap $chip $tag $args
+ } else {
+ echo "Error: transport '[ transport select ]' not supported by swj_newdap"
+ shutdown
+ }
+}
diff --git a/source/build_all.sh b/source/build_all.sh
new file mode 100644
index 0000000..ac74706
--- /dev/null
+++ b/source/build_all.sh
@@ -0,0 +1,188 @@
+#!/bin/bash
+set -x -e
+
+################################################################################
+# Usage example:
+# ./build_all.sh PKG_LVERSION=4.0.0-123
+################################################################################
+OPENOCD_REPO="${CI_PROJECT_URL:-https://github.com/cypresssemiconductorco/openocd.git}"
+OPENOCD_BRANCH="${CI_COMMIT_BRANCH:-cypress}"
+
+for cmd in "${@}"; do
+ eval "${cmd}"
+done
+
+################################################################################
+STATIC="${STATIC:-0}"
+OPENOCD_BRANCH="${OPENOCD_BRANCH:-develop}"
+PKG_LVERSION="${PKG_LVERSION:-${OPENOCD_BRANCH}-latest}"
+LIBUSB_BRANCH=master
+LIBUSB_COMMIT=96898a25ccfde6e87737991000a41695ed6b3812
+HIDAPI_BRANCH=master
+HIDAPI_COMMIT=ad27b4617007cf2d824482e79193dc9557afeb1c
+
+################################################################################
+HIDAPI_REPO="https://github.com/libusb/hidapi.git"
+LIBUSB_REPO="https://github.com/libusb/libusb.git"
+SOURCE_PREFIX="$(pwd)/build/_src"
+BUILD_PREFIX="$(pwd)/build/_libs"
+INSTALL_PREFIX="$(pwd)/install"
+BIN_PREFIX="${INSTALL_PREFIX}/openocd/bin"
+CONTRIB_PREFIX="${INSTALL_PREFIX}/openocd/contrib"
+#-------------------------------------------------------------------------------
+
+export MAKEFLAGS=${MAKEFLAGS:=-j8}
+XTRA_CFLAGS+=" -O2 -URELSTR -DRELSTR=\\\"-${PKG_LVERSION}\\\""
+
+case "$OSTYPE" in
+ darwin*)
+ if [ ${STATIC} -eq 1 ]; then
+ echo "Static build is not supported on Mac OS"
+ STATIC=0
+ fi
+ export XTRA_CFLAGS+=" -Qunused-arguments"
+ ;;
+ linux*)
+ XTRA_CFLAGS+=" -Wl,-rpath,XORIGIN"
+ ;;
+ msys*)
+ if [ ${STATIC} -eq 1 ]; then
+ XTRA_CFLAGS+=" -Wl,-static"
+ fi
+ ;;
+ *) echo "Unknown operating system: $OSTYPE"
+ exit 1
+ ;;
+esac
+
+if [ ${STATIC} -eq 1 ]; then
+ XTRA_CFLAGS+=" -static -static-libgcc"
+ XTRA_LDFLAGS+=" -static"
+ LIBUSB_BUILD_TYPE="--enable-shared=no"
+else
+ LIBUSB_BUILD_TYPE="--enable-static=no"
+fi
+
+if [ "$CONFIG" == "Coverage" ]; then
+ XTRA_CFLAGS+=" --coverage -finstrument-functions-exclude-file-list=msys64,jimtcl,src/jtag,src/helper,src/pld,src/rtos,src/server,src/svf,src/target,src/transport,src/xsvf,src/flash/hand"
+fi
+
+function maybe_fetch_package {
+ if [ ! -d "${SOURCE_PREFIX}/${1}" ]; then
+ git clone --branch "${3}" "${2}" "${SOURCE_PREFIX}/${1}"
+ fi
+
+ (cd "${SOURCE_PREFIX}/${1}" && {
+ git reset --hard "origin/${3}"
+ git clean -fd
+ [ -z "$4" ] || git checkout --quiet "$4"
+ git show --oneline -s
+ })
+}
+
+function maybe_build_library {
+ (cd "${SOURCE_PREFIX}/${1}" && {
+ if [ ! -f Makefile ]; then
+ ./bootstrap || ./autogen.sh
+ ./configure --prefix="${BUILD_PREFIX}" --enable-silent-rules "${@:2}"
+ fi
+ make
+ make install
+ })
+}
+
+############################
+# change dynamic shared library install names
+#
+function patch_macos_lib_path {
+ local victim=$1
+ local lib_name=$2
+ local rel_lib_path="${3:-@executable_path}"
+
+ local path_regex="^(.*[\/]?)($lib_name.*\.dylib)"
+
+ otool -L "$victim" | grep "$lib_name" | while read -r line ; do
+ if [[ ${line} =~ ${path_regex} ]]; then
+ lib_dir=${BASH_REMATCH[1]}
+ lib=${BASH_REMATCH[2]}
+
+ install_name_tool -change "${lib_dir}${lib}" "$rel_lib_path/${lib}" "$victim"
+ fi
+ done
+}
+
+# fetch and build hidapi
+maybe_fetch_package "hidapi" "${HIDAPI_REPO}" "${HIDAPI_BRANCH}" "${HIDAPI_COMMIT}"
+maybe_build_library "hidapi" "--enable-shared=no" \
+ LD_LIBRARY_PATH=":${BUILD_PREFIX}/lib" \
+ PKG_CONFIG_PATH="${BUILD_PREFIX}/lib/pkgconfig"
+
+# fetch and build libusb
+libusb_exists=$(find "${BUILD_PREFIX}/lib/" -maxdepth 1 -type f -name "libusb-*" -print -quit)
+if [ -z "$libusb_exists" ]; then
+ maybe_fetch_package "libusb" "${LIBUSB_REPO}" "${LIBUSB_BRANCH}" "${LIBUSB_COMMIT}"
+ maybe_build_library "libusb" "${LIBUSB_BUILD_TYPE}"
+fi
+
+# fetch openocd
+maybe_fetch_package "openocd" "${OPENOCD_REPO}" "${OPENOCD_BRANCH}"
+
+rm -rf "${INSTALL_PREFIX}"
+
+(cd "${SOURCE_PREFIX}/openocd" && {
+ if [ -f Makefile ]; then
+ make distclean
+ fi
+
+ ./bootstrap
+ ./configure --enable-silent-rules --disable-werror --enable-remote-bitbang \
+ --disable-ulink --disable-usbprog --disable-rlink --disable-armjtagew \
+ CFLAGS="${CFLAGS} ${XTRA_CFLAGS}" LDFLAGS="${LDFLAGS} ${XTRA_LDFLAGS}" \
+ LD_LIBRARY_PATH=":${BUILD_PREFIX}/lib:${BUILD_PREFIX}/bin:${LD_LIBRARY_PATH}" \
+ PKG_CONFIG_PATH="${BUILD_PREFIX}/lib/pkgconfig" \
+ CC="gcc" \
+ --prefix="${BUILD_PREFIX}" \
+ --mandir="${BUILD_PREFIX}/share/man" \
+ --infodir="${BUILD_PREFIX}/share/info" \
+ --bindir="${BIN_PREFIX}" \
+ --datarootdir="${INSTALL_PREFIX}"
+
+ make
+ make install-strip
+})
+
+mkdir -p "${INSTALL_PREFIX}/openocd/source"
+cp -av "${SOURCE_PREFIX}/openocd/build"/*.sh "${INSTALL_PREFIX}/openocd/source/"
+
+mkdir -p "${INSTALL_PREFIX}/openocd/docs"
+cp -av "${SOURCE_PREFIX}/openocd/doc/third_party_licenses" "${INSTALL_PREFIX}/openocd/docs/"
+cp -av "${SOURCE_PREFIX}/openocd/doc"/*.pdf "${INSTALL_PREFIX}/openocd/docs/"
+
+rm -rf "${CONTRIB_PREFIX}"
+
+case "$OSTYPE" in
+ darwin*)
+ if [ ${STATIC} -eq 0 ]; then
+ cp "${BUILD_PREFIX}/lib/libusb-1.0.0.dylib" "${BIN_PREFIX}/"
+ patch_macos_lib_path "${BIN_PREFIX}/openocd" "libusb-"
+ fi
+ ;;
+ msys*)
+ if [ ${STATIC} -eq 0 ]; then
+# cp /mingw64/bin/libwinpthread-1.dll ${BIN_PREFIX}/
+ cp -a "/c/msys64/mingw32/bin/libwinpthread-1.dll" "${BIN_PREFIX}/"
+ cp -a "${BUILD_PREFIX}/bin/libusb-1.0.dll" "${BIN_PREFIX}/"
+ strip "${BIN_PREFIX}"/*.dll
+ fi
+ ;;
+ linux*)
+ cp -av "${SOURCE_PREFIX}/openocd/udev_rules" "${INSTALL_PREFIX}/openocd/"
+ if [ ${STATIC} -eq 0 ]; then
+ find "${BUILD_PREFIX}/lib/" -maxdepth 1 -type f -name "libusb*.so.*" \
+ -exec cp -av {} "${BIN_PREFIX}/libusb-1.0.so.0" \;
+ strip "${BIN_PREFIX}/libusb-1.0.so.0"
+ chrpath -r '$ORIGIN' "${BIN_PREFIX}/openocd"
+ fi
+ ;;
+esac
+
diff --git a/version.xml b/version.xml
new file mode 100644
index 0000000..6c605f4
--- /dev/null
+++ b/version.xml
@@ -0,0 +1 @@
+4.3.0.1746