From 840399eb9570884d7e718f2e258d5a71b3fdcac5 Mon Sep 17 00:00:00 2001 From: "Xu, Zefan" Date: Sat, 14 Sep 2024 11:41:23 +0800 Subject: [PATCH] revert(csr): htinst/mtinst should follow the origin spike behaviour This reverts commit 347cd0ede891c2362957b9de91491ea12bfc1523 (OpenXiangShan/riscv-isa-sim#33). According to RISC-V priv spec, htinst/mtinst could be zero when traps into HS/M-mode, except the both following conditions are met: * the fault is caused by an implicit memory access for VS-stage address translation * a nonzero value (the faulting guest physical address) is written to mtval2 or htval Actually, XiangShan would write a nonzero value in such trap, so mtinst could not be written 0. Acctually, spike only implements this nonzero situation for htinst/mtinst, so no more warps are needed. --- riscv/processor.cc | 8 -------- 1 file changed, 8 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index a3d8c3e1f..545f0ac32 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -501,11 +501,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) #endif state.nonvirtual_stval->write(t.get_tval()); state.htval->write(t.get_tval2()); -#ifdef CPU_XIANGSHAN - state.htinst->write(0); -#else state.htinst->write(t.get_tinst()); -#endif reg_t s = state.nonvirtual_sstatus->read(); s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); @@ -555,11 +551,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.mcause->write(supv_double_trap ? CAUSE_DOUBLE_TRAP : t.cause()); state.mtval->write(t.get_tval()); state.mtval2->write(supv_double_trap ? t.cause() : t.get_tval2()); -#ifdef CPU_XIANGSHAN - state.mtinst->write(0); -#else state.mtinst->write(t.get_tinst()); -#endif s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s = set_field(s, MSTATUS_MPP, state.prv);