From 2f898df893adde163aed04533f1da2e17d7ed8fe Mon Sep 17 00:00:00 2001
From: lixin <1037997956@qq.com>
Date: Fri, 20 Dec 2024 13:57:09 +0800
Subject: [PATCH] cpu-o3: make store wb stage configurable

store writeback at S4 by default
when using --ideal-kmhv3, store writeback at S2

Change-Id: I6a318ff6c182daca0ab041840d76575a16e45d82
---
 configs/example/xiangshan.py |  1 +
 src/cpu/o3/BaseO3CPU.py      |  2 ++
 src/cpu/o3/lsq.cc            |  2 ++
 src/cpu/o3/lsq.hh            |  3 +++
 src/cpu/o3/lsq_unit.cc       | 26 ++++++++++++++------------
 5 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/configs/example/xiangshan.py b/configs/example/xiangshan.py
index 6d19885413..01269e7ec2 100644
--- a/configs/example/xiangshan.py
+++ b/configs/example/xiangshan.py
@@ -339,6 +339,7 @@ def setKmhV3IdealParams(args, system):
         cpu.BankConflictCheck = False   # real bank conflict 0.2 score
         cpu.EnableLdMissReplay = False
         cpu.EnablePipeNukeCheck = False
+        cpu.StoreWbStage = 2 # store writeback at s2
 
         cpu.scheduler = IdealScheduler()
         # use centralized load/store issue queue, for hmmer
diff --git a/src/cpu/o3/BaseO3CPU.py b/src/cpu/o3/BaseO3CPU.py
index 9f14fc94de..cd6e69aef6 100644
--- a/src/cpu/o3/BaseO3CPU.py
+++ b/src/cpu/o3/BaseO3CPU.py
@@ -175,6 +175,8 @@ def support_take_over(cls):
     SbufferEvictThreshold = Param.Unsigned(7, "store buffer eviction threshold")
     storeBufferInactiveThreshold = Param.Unsigned(800, "store buffer writeback timeout threshold")
 
+    StoreWbStage = Param.Unsigned(4, "Which PipeLine Stage store instruction writeback, 4 means S4")
+
     LSQDepCheckShift = Param.Unsigned(0,
             "Number of places to shift addr before check")
     LSQCheckLoads = Param.Bool(True,
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index f35a63ee93..23fdd4f5e1 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -88,6 +88,7 @@ LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params)
       enableBankConflictCheck(params.BankConflictCheck),
       _enableLdMissReplay(params.EnableLdMissReplay),
       _enablePipeNukeCheck(params.EnablePipeNukeCheck),
+      _storeWbStage(params.StoreWbStage),
       waitingForStaleTranslation(false),
       staleTranslationWaitTxnId(0),
       lsqPolicy(params.smtLSQPolicy),
@@ -104,6 +105,7 @@ LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params)
     if (!_enableLdMissReplay && _enablePipeNukeCheck) {
         panic("LSQ can not support pipeline nuke replay when EnableLdMissReplay is False");
     }
+    assert(_storeWbStage >= 2 && _storeWbStage <= 4);
 
     //**********************************************
     //************ Handle SMT Parameters ***********
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 1a44bea2a7..dd321344ea 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -1015,6 +1015,7 @@ class LSQ
 
     bool enableLdMissReplay() const { return _enableLdMissReplay; }
     bool enablePipeNukeCheck() const { return _enablePipeNukeCheck; }
+    int storeWbStage() const { return _storeWbStage; }
 
   protected:
     /** D-cache is blocked */
@@ -1039,6 +1040,8 @@ class LSQ
     bool _enableLdMissReplay;
     bool _enablePipeNukeCheck;
 
+    int _storeWbStage;
+
     /** If the LSQ is currently waiting for stale translations */
     bool waitingForStaleTranslation;
     /** The ID if the transaction that made translations stale */
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 89907d0c80..6cce3eb492 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -1432,18 +1432,6 @@ LSQUnit::storePipeS4(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag)
     DPRINTF(LSQUnit, "StorePipeS4: Executing store PC %s [sn:%lli] flags: %s\n",
             inst->pcState(), inst->seqNum, getLdStFlagStr(flag));
 
-    // If the store had a fault then it may not have a mem req
-    if (fault != NoFault || !inst->readPredicate() || !inst->isStoreConditional()) {
-        // If the instruction faulted, then we need to send it
-        // along to commit without the instruction completing.
-        // Send this instruction to commit, also make sure iew
-        // stage realizes there is activity.
-        if (!flag[LdStFlags::Replayed]) {
-            inst->setExecuted();
-            iewStage->instToCommit(inst);
-            iewStage->activityThisCycle();
-        }
-    }
     return fault;
 }
 
@@ -1489,6 +1477,20 @@ LSQUnit::executeStorePipeSx()
                     default:
                         panic("unsupported storepipe length");
                 }
+                if (i == (lsq->storeWbStage() - 1)) {
+                    // If the store had a fault then it may not have a mem req
+                    if (fault != NoFault || !inst->readPredicate() || !inst->isStoreConditional()) {
+                        // If the instruction faulted, then we need to send it
+                        // along to commit without the instruction completing.
+                        // Send this instruction to commit, also make sure iew
+                        // stage realizes there is activity.
+                        if (!flag[LdStFlags::Replayed]) {
+                            inst->setExecuted();
+                            iewStage->instToCommit(inst);
+                            iewStage->activityThisCycle();
+                        }
+                    }
+                }
             } else {
                 DPRINTF(LSQUnit, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
                                 " [sn:%llu]\n", inst->pcState(), inst->threadNumber,