Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Convert interfaces to HDL as well (VHDL records, SV interface) #32

Open
Nic30 opened this issue Feb 5, 2020 · 0 comments
Open

Convert interfaces to HDL as well (VHDL records, SV interface) #32

Nic30 opened this issue Feb 5, 2020 · 0 comments
Labels
enhancement

Comments

@Nic30
Copy link
Owner

Nic30 commented Feb 5, 2020

  1. Extract interface as a VHDL records, SV interfaces and not just a separate signals.
  2. Nice methods for connecting rather than assignments.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
enhancement
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@Nic30