From eb5c7665a1b4bc15e41b629f976a2be1651624de Mon Sep 17 00:00:00 2001 From: Andy Ritger Date: Tue, 30 May 2023 10:11:36 -0700 Subject: [PATCH] 535.43.02 --- CHANGELOG.md | 24 + README.md | 31 +- kernel-open/Kbuild | 9 +- kernel-open/common/inc/nv-firmware-registry.h | 83 + kernel-open/common/inc/nv-firmware.h | 6 +- kernel-open/common/inc/nv-hypervisor.h | 2 + kernel-open/common/inc/nv-ioctl-numa.h | 1 + kernel-open/common/inc/nv-kthread-q.h | 7 +- kernel-open/common/inc/nv-linux.h | 64 +- kernel-open/common/inc/nv-lock.h | 22 +- kernel-open/common/inc/nv.h | 31 +- kernel-open/common/inc/nv_uvm_interface.h | 330 +- kernel-open/common/inc/nv_uvm_types.h | 215 +- kernel-open/common/inc/nvkms-kapi.h | 18 +- kernel-open/common/inc/nvlimits.h | 2 +- kernel-open/common/inc/nvstatuscodes.h | 1 + kernel-open/common/inc/nvtypes.h | 14 +- kernel-open/common/inc/os-interface.h | 7 +- kernel-open/common/inc/rm-gpu-ops.h | 19 +- kernel-open/conftest.sh | 429 +- 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src/common/sdk/nvidia/inc/class/clc6b5sw.h | 2 +- src/common/sdk/nvidia/inc/class/clc770.h | 2 +- .../ctrl0080/ctrl0080rc.h => class/clcb33.h} | 35 +- src/common/sdk/nvidia/inc/class/clcba2.h | 140 + .../nvidia/inc/ctrl/ctrl0000/ctrl0000base.h | 2 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000client.h | 2 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h | 2 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000event.h | 2 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h | 5 +- .../inc/ctrl/ctrl0000/ctrl0000gpuacct.h | 2 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h | 2 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h | 2 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h | 2 +- .../inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h | 2 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000system.h | 56 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h | 7 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h | 2 +- src/common/sdk/nvidia/inc/ctrl/ctrl0002.h | 2 +- src/common/sdk/nvidia/inc/ctrl/ctrl0004.h | 2 +- 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src/nvidia/arch/nvalloc/unix/x86emu/sys.c | 663 + src/nvidia/exports_link_command.txt | 13 + .../generated/g_access_cntr_buffer_nvoc.h | 2 + src/nvidia/generated/g_allclasses.h | 25 + src/nvidia/generated/g_bindata.c | 12 + ...a_kgspGetBinArchiveBooterLoadUcode_AD102.c | 7229 +-- ...a_kgspGetBinArchiveBooterLoadUcode_GA100.c | 7767 ++-- ...a_kgspGetBinArchiveBooterLoadUcode_GA102.c | 7964 ++-- ...a_kgspGetBinArchiveBooterLoadUcode_TU102.c | 7587 ++-- ...a_kgspGetBinArchiveBooterLoadUcode_TU116.c | 7590 ++-- ...kgspGetBinArchiveBooterUnloadUcode_AD102.c | 4321 +- ...kgspGetBinArchiveBooterUnloadUcode_GA100.c | 4117 +- ...kgspGetBinArchiveBooterUnloadUcode_GA102.c | 4296 +- ...kgspGetBinArchiveBooterUnloadUcode_TU102.c | 4014 +- ...kgspGetBinArchiveBooterUnloadUcode_TU116.c | 4012 +- ...spGetBinArchiveConcatenatedFMCDesc_GH100.c | 98 + ...a_kgspGetBinArchiveConcatenatedFMC_GH100.c | 20471 +++++++++ ...bindata_kgspGetBinArchiveGspRmBoot_AD102.c | 7324 ++-- ...bindata_kgspGetBinArchiveGspRmBoot_GA102.c | 4257 +- ...bindata_kgspGetBinArchiveGspRmBoot_GH100.c | 36483 +++++++++------- ...tBinArchiveGspRmCcFmcGfwProdSigned_GH100.c | 10637 +++++ ...etBinArchiveGspRmFmcGfwDebugSigned_GH100.c | 18273 ++++---- ...GetBinArchiveGspRmFmcGfwProdSigned_GH100.c | 18321 ++++---- src/nvidia/generated/g_ce_utils_nvoc.c | 165 + src/nvidia/generated/g_ce_utils_nvoc.h | 233 + src/nvidia/generated/g_chips2halspec_nvoc.c | 2 +- src/nvidia/generated/g_chipset_nvoc.h | 29 + src/nvidia/generated/g_client_resource_nvoc.c | 396 +- src/nvidia/generated/g_client_resource_nvoc.h | 96 + .../g_compute_instance_subscription_nvoc.h | 6 +- .../generated/g_conf_compute_api_nvoc.c | 482 + .../generated/g_conf_compute_api_nvoc.h | 297 + src/nvidia/generated/g_conf_compute_nvoc.c | 434 + src/nvidia/generated/g_conf_compute_nvoc.h | 481 + src/nvidia/generated/g_console_mem_nvoc.c | 4 +- src/nvidia/generated/g_console_mem_nvoc.h | 8 +- src/nvidia/generated/g_dce_client_nvoc.h | 2 +- src/nvidia/generated/g_deferred_api_nvoc.c | 24 +- src/nvidia/generated/g_device_nvoc.c | 153 +- src/nvidia/generated/g_device_nvoc.h | 15 +- src/nvidia/generated/g_disp_inst_mem_nvoc.c | 56 +- src/nvidia/generated/g_disp_objs_nvoc.c | 320 +- src/nvidia/generated/g_disp_objs_nvoc.h | 58 +- src/nvidia/generated/g_dispsw_nvoc.c | 5 +- src/nvidia/generated/g_dispsw_nvoc.h | 2 +- src/nvidia/generated/g_egm_mem_nvoc.c | 364 + src/nvidia/generated/g_egm_mem_nvoc.h | 257 + src/nvidia/generated/g_eng_desc_nvoc.h | 13 + src/nvidia/generated/g_event_nvoc.h | 2 +- src/nvidia/generated/g_fabric_nvoc.h | 2 +- src/nvidia/generated/g_fabric_vaspace_nvoc.c | 2 +- src/nvidia/generated/g_fabric_vaspace_nvoc.h | 39 +- src/nvidia/generated/g_fbsr_nvoc.c | 41 +- src/nvidia/generated/g_fbsr_nvoc.h | 13 + src/nvidia/generated/g_fecs_event_list_nvoc.h | 3 +- src/nvidia/generated/g_fla_mem_nvoc.c | 4 +- src/nvidia/generated/g_fla_mem_nvoc.h | 8 +- src/nvidia/generated/g_gpu_access_nvoc.h | 2 + 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src/nvidia/generated/g_kernel_sec2_nvoc.c | 108 +- src/nvidia/generated/g_kernel_sec2_nvoc.h | 4 +- .../g_kernel_sm_debugger_session_nvoc.c | 92 +- .../g_kernel_sm_debugger_session_nvoc.h | 46 +- src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h | 21 +- src/nvidia/generated/g_mem_desc_nvoc.h | 18 +- src/nvidia/generated/g_mem_fabric_nvoc.c | 25 +- src/nvidia/generated/g_mem_fabric_nvoc.h | 18 +- src/nvidia/generated/g_mem_list_nvoc.c | 4 +- src/nvidia/generated/g_mem_list_nvoc.h | 8 +- src/nvidia/generated/g_mem_mgr_nvoc.c | 119 +- src/nvidia/generated/g_mem_mgr_nvoc.h | 131 +- .../generated/g_mem_multicast_fabric_nvoc.c | 4 +- .../generated/g_mem_multicast_fabric_nvoc.h | 14 +- src/nvidia/generated/g_mem_nvoc.h | 12 +- .../generated/g_mig_config_session_nvoc.h | 4 +- .../generated/g_mig_monitor_session_nvoc.h | 4 +- src/nvidia/generated/g_no_device_mem_nvoc.c | 4 +- src/nvidia/generated/g_no_device_mem_nvoc.h | 8 +- src/nvidia/generated/g_nv_debug_dump_nvoc.h | 4 +- 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+ src/nvidia/inc/kernel/mem_mgr/pool_alloc.h | 14 +- src/nvidia/inc/kernel/os/os_stub.h | 9 - .../inc/kernel/platform/nbsi/nbsi_table.h | 6 +- .../inc/kernel/platform/pci_exp_table.h | 4 +- .../platform/platform_request_handler_utils.h | 52 +- src/nvidia/inc/kernel/rmapi/control.h | 17 +- src/nvidia/inc/kernel/rmapi/mapping_list.h | 2 +- src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h | 49 +- src/nvidia/inc/kernel/rmapi/param_copy.h | 12 +- src/nvidia/inc/kernel/rmapi/rmapi.h | 16 +- src/nvidia/inc/kernel/rmapi/rs_utils.h | 13 +- .../kernel/virtualization/common_vgpu_mgr.h | 14 +- src/nvidia/inc/libraries/containers/btree.h | 2 +- src/nvidia/inc/libraries/containers/list.h | 10 +- src/nvidia/inc/libraries/containers/map.h | 4 +- .../inc/libraries/containers/multimap.h | 62 +- src/nvidia/inc/libraries/containers/queue.h | 4 +- src/nvidia/inc/libraries/containers/ringbuf.h | 169 + .../inc/libraries/containers/type_safety.h | 38 +- src/nvidia/inc/libraries/containers/vector.h | 201 + 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| 19 +- ...nel_head_gpu_0400.c => kernel_head_0400.c} | 66 +- .../src/kernel/gpu/disp/head/kernel_head.c | 15 +- src/nvidia/src/kernel/gpu/disp/kern_disp.c | 177 +- .../disp/rg_line_callback/rg_line_callback.c | 3 +- .../kernel/gpu/disp/vblank_callback/vblank.c | 2 +- .../arch/kepler/kern_gsync_p2060.c | 234 +- .../src/kernel/gpu/external_device/gsync.c | 2 +- .../kernel/gpu/external_device/gsync_api.c | 2 +- .../external_device/kern_external_device.c | 4 +- .../falcon/arch/turing/kernel_falcon_tu102.c | 8 +- .../src/kernel/gpu/falcon/kernel_falcon.c | 83 +- .../kernel/gpu/falcon/kernel_falcon_ctrl.c | 243 + .../gpu/fifo/arch/ampere/kernel_fifo_ga100.c | 5 +- .../gpu/fifo/arch/hopper/kernel_fifo_gh100.c | 66 +- .../gpu/fifo/arch/hopper/usermode_api_gh100.c | 121 - .../gpu/fifo/arch/maxwell/kernel_fifo_gm107.c | 2 +- .../arch/volta/kernel_channel_group_gv100.c | 24 +- .../fifo/arch/volta/kernel_channel_gv100.c | 2 +- .../gpu/fifo/arch/volta/kernel_fifo_gv100.c | 34 + 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.../include/internal/libspdm_lib_config.h | 55 + .../include/internal/libspdm_macro_check.h | 44 + .../include/internal/libspdm_requester_lib.h | 555 + .../include/internal/libspdm_responder_lib.h | 870 + .../internal/libspdm_secured_message_lib.h | 79 + .../2.3.1/include/library/spdm_common_lib.h | 795 + .../2.3.1/include/library/spdm_crypt_lib.h | 877 + .../include/library/spdm_device_secret_lib.h | 256 + .../2.3.1/include/library/spdm_lib_config.h | 415 + .../include/library/spdm_requester_lib.h | 804 + .../include/library/spdm_responder_lib.h | 257 + .../include/library/spdm_return_status.h | 185 + .../library/spdm_secured_message_lib.h | 650 + .../libspdm_com_context_data.c | 2420 + .../libspdm_com_context_data_session.c | 266 + .../libspdm_com_crypto_service.c | 1147 + .../libspdm_com_crypto_service_session.c | 686 + .../spdm_common_lib/libspdm_com_msg_log.c | 102 + .../spdm_common_lib/libspdm_com_opaque_data.c | 232 + .../spdm_common_lib/libspdm_com_support.c | 231 + .../spdm_crypt_lib/libspdm_crypt_aead.c | 159 + .../spdm_crypt_lib/libspdm_crypt_asym.c | 1154 + .../spdm_crypt_lib/libspdm_crypt_cert.c | 1325 + .../spdm_crypt_lib/libspdm_crypt_dhe.c | 270 + .../spdm_crypt_lib/libspdm_crypt_hash.c | 477 + .../spdm_crypt_lib/libspdm_crypt_hkdf.c | 127 + .../spdm_crypt_lib/libspdm_crypt_hmac.c | 419 + .../spdm_crypt_lib/libspdm_crypt_rng.c | 15 + .../spdm_requester_lib/libspdm_req_common.c | 174 + .../libspdm_req_communication.c | 368 + .../libspdm_req_end_session.c | 165 + .../spdm_requester_lib/libspdm_req_finish.c | 576 + .../libspdm_req_get_capabilities.c | 337 + .../libspdm_req_get_certificate.c | 511 + .../libspdm_req_get_digests.c | 273 + .../libspdm_req_get_measurements.c | 679 + .../libspdm_req_get_version.c | 222 + .../libspdm_req_handle_error_response.c | 418 + .../libspdm_req_key_exchange.c | 777 + .../libspdm_req_key_update.c | 326 + .../libspdm_req_negotiate_algorithms.c | 531 + .../libspdm_req_send_receive.c | 685 + .../libspdm_secmes_context_data.c | 398 + .../libspdm_secmes_encode_decode.c | 580 + .../libspdm_secmes_key_exchange.c | 108 + .../libspdm_secmes_session.c | 1113 + .../cipher/libspdm_aead_aes_gcm.c | 187 + .../cryptlib_mbedtls/hash/libspdm_sha.c | 623 + .../cryptlib_mbedtls/hmac/libspdm_hmac_sha.c | 709 + .../cryptlib_mbedtls/internal_crypt_lib.h | 28 + .../cryptlib_mbedtls/kdf/libspdm_hkdf_sha.c | 386 + .../os_stub/cryptlib_mbedtls/pk/libspdm_ec.c | 708 + .../cryptlib_mbedtls/pk/libspdm_x509.c | 1845 + .../cryptlib_mbedtls/rand/libspdm_rand.c | 65 + .../2.3.1/os_stub/include/library/malloclib.h | 64 + .../2.3.1/os_stub/include/library/rnglib.h | 27 + .../2.3.1/os_stub/memlib/compare_mem.c | 49 + .../os_stub/platform_lib_null/time_linux.c | 17 + .../os_stub/platform_lib_null/watchdog.c | 45 + .../os_stub/spdm_crypt_ext_lib/cryptlib_ext.h | 668 + .../os_stub/spdm_device_secret_lib_null/lib.c | 105 + .../libspdm/nvidia/nvspdm_crypt_null.c | 54 + .../libspdm/nvidia/nvspdm_debuglib.c | 58 + .../libspdm/nvidia/nvspdm_malloclib.c | 49 + .../libraries/libspdm/nvidia/nvspdm_memlib.c | 147 + .../libspdm/nvidia/nvspdm_rmconfig.h | 129 + .../src/libraries/libspdm/nvidia/nvspdm_rng.c | 48 + .../src/libraries/libspdm/nvidia/openspdm.mk | 110 + src/nvidia/src/libraries/mmu/mmu_walk.c | 52 +- src/nvidia/src/libraries/mmu/mmu_walk_fill.c | 72 +- .../src/libraries/mmu/mmu_walk_private.h | 2 +- .../src/libraries/nvport/cpu/cpu_common.c | 2 +- .../src/libraries/nvport/cpu/cpu_x86_amd64.c | 64 +- .../src/libraries/nvport/cpu/cpu_x86_amd64.h | 60 +- .../nvport/crypto/crypto_random_xorshift.c | 18 +- .../libraries/nvport/memory/memory_tracking.c | 483 +- .../nvport/memory/memory_unix_kernel_os.c | 4 +- .../src/libraries/poolalloc/poolalloc.c | 62 +- .../libraries/prereq_tracker/prereq_tracker.c | 2 +- .../src/libraries/resserv/src/rs_client.c | 116 +- .../src/libraries/resserv/src/rs_resource.c | 26 +- .../src/libraries/resserv/src/rs_server.c | 81 +- src/nvidia/srcs.mk | 114 +- version.mk | 2 +- 1403 files changed, 295182 insertions(+), 86050 deletions(-) create mode 100644 kernel-open/common/inc/nv-firmware-registry.h create mode 100644 kernel-open/nvidia-uvm/clcba2.h create mode 100644 kernel-open/nvidia-uvm/uvm_ats_sva.c create mode 100644 kernel-open/nvidia-uvm/uvm_ats_sva.h create mode 100644 kernel-open/nvidia-uvm/uvm_conf_computing.c create mode 100644 kernel-open/nvidia-uvm/uvm_conf_computing.h create mode 100644 kernel-open/nvidia-uvm/uvm_hopper_sec2.c create mode 100644 kernel-open/nvidia-uvm/uvm_maxwell_sec2.c create mode 100644 kernel-open/nvidia-uvm/uvm_sec2_test.c create mode 100755 nouveau/extract-firmware-nouveau.py create mode 100644 nouveau/nouveau_firmware_layout.ods create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h create mode 100644 src/common/inc/swref/published/hopper/gh100/dev_fuse.h create mode 100644 src/common/mbedtls/gpl-2.0.txt create mode 100644 src/common/mbedtls/include/mbedtls/aes.h create mode 100644 src/common/mbedtls/include/mbedtls/asn1.h create mode 100644 src/common/mbedtls/include/mbedtls/asn1write.h create mode 100644 src/common/mbedtls/include/mbedtls/base64.h create mode 100644 src/common/mbedtls/include/mbedtls/bignum.h create mode 100644 src/common/mbedtls/include/mbedtls/bn_mul.h create mode 100644 src/common/mbedtls/include/mbedtls/certs.h create mode 100644 src/common/mbedtls/include/mbedtls/check_config.h create mode 100644 src/common/mbedtls/include/mbedtls/cipher.h create mode 100644 src/common/mbedtls/include/mbedtls/cipher_internal.h create mode 100644 src/common/mbedtls/include/mbedtls/config.h create mode 100644 src/common/mbedtls/include/mbedtls/ctr_drbg.h create mode 100644 src/common/mbedtls/include/mbedtls/des.h create mode 100644 src/common/mbedtls/include/mbedtls/ecdh.h create mode 100644 src/common/mbedtls/include/mbedtls/ecdsa.h create mode 100644 src/common/mbedtls/include/mbedtls/ecp.h create mode 100644 src/common/mbedtls/include/mbedtls/ecp_internal.h create mode 100644 src/common/mbedtls/include/mbedtls/entropy.h create mode 100644 src/common/mbedtls/include/mbedtls/error.h create mode 100644 src/common/mbedtls/include/mbedtls/gcm.h create mode 100644 src/common/mbedtls/include/mbedtls/hkdf.h create mode 100644 src/common/mbedtls/include/mbedtls/md.h create mode 100644 src/common/mbedtls/include/mbedtls/md5.h create mode 100644 src/common/mbedtls/include/mbedtls/md_internal.h create mode 100644 src/common/mbedtls/include/mbedtls/nist_kw.h create mode 100644 src/common/mbedtls/include/mbedtls/oid.h create mode 100644 src/common/mbedtls/include/mbedtls/pem.h create mode 100644 src/common/mbedtls/include/mbedtls/pk.h create mode 100644 src/common/mbedtls/include/mbedtls/pk_internal.h create mode 100644 src/common/mbedtls/include/mbedtls/platform.h create mode 100644 src/common/mbedtls/include/mbedtls/platform_util.h create mode 100644 src/common/mbedtls/include/mbedtls/rsa.h create mode 100644 src/common/mbedtls/include/mbedtls/sha256.h create mode 100644 src/common/mbedtls/include/mbedtls/sha512.h create mode 100644 src/common/mbedtls/include/mbedtls/version.h create mode 100644 src/common/mbedtls/include/mbedtls/x509.h create mode 100644 src/common/mbedtls/include/mbedtls/x509_crl.h create mode 100644 src/common/mbedtls/include/mbedtls/x509_crt.h create mode 100644 src/common/mbedtls/include/mbedtls/x509_csr.h create mode 100644 src/common/mbedtls/library/mbedtls_aes.c create mode 100644 src/common/mbedtls/library/mbedtls_asn1parse.c create mode 100644 src/common/mbedtls/library/mbedtls_asn1write.c create mode 100644 src/common/mbedtls/library/mbedtls_base64.c create mode 100644 src/common/mbedtls/library/mbedtls_bignum.c create mode 100644 src/common/mbedtls/library/mbedtls_cipher.c create mode 100644 src/common/mbedtls/library/mbedtls_cipher_wrap.c create mode 100644 src/common/mbedtls/library/mbedtls_ecdh.c create mode 100644 src/common/mbedtls/library/mbedtls_ecdsa.c create mode 100644 src/common/mbedtls/library/mbedtls_ecp.c create mode 100644 src/common/mbedtls/library/mbedtls_ecp_curves.c create mode 100644 src/common/mbedtls/library/mbedtls_gcm.c create mode 100644 src/common/mbedtls/library/mbedtls_hkdf.c create mode 100644 src/common/mbedtls/library/mbedtls_md.c create mode 100644 src/common/mbedtls/library/mbedtls_md_wrap.c create mode 100644 src/common/mbedtls/library/mbedtls_oid.c create mode 100644 src/common/mbedtls/library/mbedtls_pem.c create mode 100644 src/common/mbedtls/library/mbedtls_pk.c create mode 100644 src/common/mbedtls/library/mbedtls_pk_wrap.c create mode 100644 src/common/mbedtls/library/mbedtls_pkparse.c create mode 100644 src/common/mbedtls/library/mbedtls_sha256.c create mode 100644 src/common/mbedtls/library/mbedtls_sha512.c create mode 100644 src/common/mbedtls/library/mbedtls_x509.c create mode 100644 src/common/mbedtls/library/mbedtls_x509_crt.c create mode 100644 src/common/mbedtls/nvidia/nvrm_mbedtls_config.h create mode 100644 src/common/mbedtls/nvidia/nvrm_platform.c create mode 100644 src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h create mode 100644 src/common/sdk/nvidia/inc/cc_drv.h rename src/{nvidia/interface/nv_firmware_types.h => common/sdk/nvidia/inc/class/cl0042.h} (75%) create mode 100644 src/common/sdk/nvidia/inc/class/cl0050.h create mode 100644 src/common/sdk/nvidia/inc/class/cl00da.h rename src/common/sdk/nvidia/inc/{ctrl/ctrl0080/ctrl0080rc.h => class/clcb33.h} (56%) create mode 100644 src/common/sdk/nvidia/inc/class/clcba2.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrl0050.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrl00da.h rename kernel-open/common/inc/nv_firmware_types.h => src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h (78%) create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h create mode 100644 src/nvidia/arch/nvalloc/common/inc/conf_compute/cc_keystore.h create mode 100644 src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h create mode 100644 src/nvidia/arch/nvalloc/common/inc/spdm/rmspdmtransport.h create mode 100644 src/nvidia/arch/nvalloc/common/inc/spdm/rmspdmvendordef.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/types.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h create mode 100644 src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h create mode 100644 src/nvidia/arch/nvalloc/unix/src/vbioscall.c create mode 100644 src/nvidia/arch/nvalloc/unix/x86emu/debug.c create mode 100644 src/nvidia/arch/nvalloc/unix/x86emu/decode.c create mode 100644 src/nvidia/arch/nvalloc/unix/x86emu/fpu.c create mode 100644 src/nvidia/arch/nvalloc/unix/x86emu/ops.c create mode 100644 src/nvidia/arch/nvalloc/unix/x86emu/ops2.c create mode 100644 src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c create mode 100644 src/nvidia/arch/nvalloc/unix/x86emu/sys.c create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c create mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c create mode 100644 src/nvidia/generated/g_ce_utils_nvoc.c create mode 100644 src/nvidia/generated/g_ce_utils_nvoc.h create mode 100644 src/nvidia/generated/g_conf_compute_api_nvoc.c create mode 100644 src/nvidia/generated/g_conf_compute_api_nvoc.h create mode 100644 src/nvidia/generated/g_conf_compute_nvoc.c create mode 100644 src/nvidia/generated/g_conf_compute_nvoc.h create mode 100644 src/nvidia/generated/g_egm_mem_nvoc.c create mode 100644 src/nvidia/generated/g_egm_mem_nvoc.h create mode 100644 src/nvidia/generated/g_platform_request_handler_nvoc.c create mode 100644 src/nvidia/generated/g_sec2_context_nvoc.c create mode 100644 src/nvidia/generated/g_sec2_context_nvoc.h create mode 100644 src/nvidia/generated/g_sem_surf_nvoc.c create mode 100644 src/nvidia/generated/g_sem_surf_nvoc.h create mode 100644 src/nvidia/generated/g_spdm_nvoc.c create mode 100644 src/nvidia/generated/g_spdm_nvoc.h create mode 100644 src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h create mode 100644 src/nvidia/inc/kernel/gpu/conf_compute/conf_compute.h create mode 100644 src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_api.h create mode 100644 src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h create mode 100644 src/nvidia/inc/kernel/gpu/gpu_child_class_defs.h create mode 100644 src/nvidia/inc/kernel/gpu/intr/intr_common.h create mode 100644 src/nvidia/inc/kernel/gpu/kern_gpu_power.h create mode 100644 src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h create mode 100644 src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h create mode 100644 src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h create mode 100644 src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h create mode 100644 src/nvidia/inc/kernel/gpu/mem_mgr/sem_surf.h create mode 100644 src/nvidia/inc/kernel/gpu/sec2/sec2_context.h create mode 100644 src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h create mode 100644 src/nvidia/inc/kernel/gpu/spdm/spdm.h create mode 100644 src/nvidia/inc/kernel/mem_mgr/egm_mem.h create mode 100644 src/nvidia/inc/libraries/containers/ringbuf.h create mode 100644 src/nvidia/inc/libraries/containers/vector.h create mode 100644 src/nvidia/interface/nv-firmware-registry.h create mode 100644 src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/conf_compute/ccsl.c create mode 100644 src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c create mode 100644 src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c create mode 100644 src/nvidia/src/kernel/gpu/conf_compute/conf_compute_keystore.c rename src/nvidia/src/kernel/gpu/disp/head/arch/v04/{kernel_head_gpu_0400.c => kernel_head_0400.c} (53%) create mode 100644 src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c delete mode 100644 src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c delete mode 100644 src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c create mode 100644 src/nvidia/src/kernel/gpu/kern_gpu_power.c create mode 100644 src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c create mode 100644 src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c create mode 100644 src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c create mode 100644 src/nvidia/src/kernel/gpu/sec2/sec2_context.c create mode 100644 src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c create mode 100644 src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c create mode 100644 src/nvidia/src/kernel/gpu/spdm/spdm.c create mode 100644 src/nvidia/src/kernel/mem_mgr/egm_mem.c create mode 100644 src/nvidia/src/kernel/platform/platform_request_handler.c create mode 100644 src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c create mode 100644 src/nvidia/src/libraries/containers/ringbuf.c create mode 100644 src/nvidia/src/libraries/containers/vector.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/cipher/libspdm_aead_aes_gcm.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hash/libspdm_sha.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hmac/libspdm_hmac_sha.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/internal_crypt_lib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/kdf/libspdm_hkdf_sha.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_ec.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_x509.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/rand/libspdm_rand.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h create mode 100644 src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c create mode 100644 src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c create mode 100644 src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c create mode 100644 src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c create mode 100644 src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c create mode 100644 src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h create mode 100644 src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c create mode 100644 src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk diff --git a/CHANGELOG.md b/CHANGELOG.md index 4a18bf8c33..e6263b6a18 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,11 +1,29 @@ # Changelog +## Release 535 Entries + +### [535.43.02] 2023-05-30 + +#### Fixed + +- Fixed console restore with traditional VGA consoles. + +#### Added + +- Added support for Run Time D3 (RTD3) on Ampere and later GPUs. +- Added support for G-Sync on desktop GPUs. + ## Release 530 Entries ### [530.41.03] 2023-03-23 ### [530.30.02] 2023-02-28 +#### Changed + +- GSP firmware is now distributed as `gsp_tu10x.bin` and `gsp_ga10x.bin` to better reflect the GPU architectures supported by each firmware file in this release. + - The .run installer will continue to install firmware to /lib/firmware/nvidia/ and the nvidia.ko kernel module will load the appropriate firmware for each GPU at runtime. + #### Fixed - Add support for resizable BAR on Linux when NVreg_EnableResizableBar=1 module param is set. [#3](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/3) by @sjkelly @@ -16,6 +34,12 @@ ## Release 525 Entries +### [525.116.04] 2023-05-09 + +### [525.116.03] 2023-04-25 + +### [525.105.17] 2023-03-30 + ### [525.89.02] 2023-02-08 ### [525.85.12] 2023-01-30 diff --git a/README.md b/README.md index 4f033ffd91..d8363706d8 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 530.41.03. +version 535.43.02. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -530.41.03 driver release. This can be achieved by installing +535.43.02 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -162,12 +162,25 @@ for the target kernel. - `src/nvidia/` The OS-agnostic code for nvidia.ko - `src/nvidia-modeset/` The OS-agnostic code for nvidia-modeset.ko - `src/common/` Utility code used by one or more of nvidia.ko and nvidia-modeset.ko +- `nouveau/` Tools for integration with the Nouveau device driver + + +## Nouveau device driver integration + +The Python script in the 'nouveau' directory is used to extract some of the +firmware binary images (and related data) encoded in the source code and +store them as distinct files. These files are used by the Nouveau device +driver to load and communicate with the GSP firmware. + +The layout of the binary files is described in nouveau_firmware_layout.ods, +which is an OpenDocument Spreadsheet file, compatible with most spreadsheet +software applications. ## Compatible GPUs The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 530.41.03 release, +(see the table below). However, in the 535.43.02 release, GeForce and Workstation support is still considered alpha-quality. To enable use of the open kernel modules on GeForce and Workstation GPUs, @@ -175,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module parameter to 1. For more details, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/530.41.03/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/535.43.02/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI @@ -754,6 +767,7 @@ Subsystem Device ID. | NVIDIA RTX A3000 12GB Laptop GPU | 24B9 | | NVIDIA RTX A4500 Laptop GPU | 24BA | | NVIDIA RTX A3000 12GB Laptop GPU | 24BB | +| NVIDIA GeForce RTX 3060 | 24C7 | | NVIDIA GeForce RTX 3060 Ti | 24C9 | | NVIDIA GeForce RTX 3080 Laptop GPU | 24DC | | NVIDIA GeForce RTX 3070 Laptop GPU | 24DD | @@ -799,6 +813,8 @@ Subsystem Device ID. | NVIDIA RTX A1000 Laptop GPU | 25B9 | | NVIDIA RTX A2000 8GB Laptop GPU | 25BA | | NVIDIA RTX A500 Laptop GPU | 25BB | +| NVIDIA RTX A1000 6GB Laptop GPU | 25BC | +| NVIDIA RTX A500 Laptop GPU | 25BD | | NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25E0 | | NVIDIA GeForce RTX 3050 Laptop GPU | 25E2 | | NVIDIA GeForce RTX 3050 Laptop GPU | 25E5 | @@ -816,8 +832,10 @@ Subsystem Device ID. | NVIDIA L40 | 26B5 10DE 17DA | | NVIDIA GeForce RTX 4080 | 2704 | | NVIDIA GeForce RTX 4090 Laptop GPU | 2717 | +| NVIDIA RTX 5000 Ada Generation Laptop GPU | 2730 | | NVIDIA GeForce RTX 4090 Laptop GPU | 2757 | | NVIDIA GeForce RTX 4070 Ti | 2782 | +| NVIDIA GeForce RTX 4070 | 2786 | | NVIDIA GeForce RTX 4080 Laptop GPU | 27A0 | | NVIDIA RTX 4000 SFF Ada Generation | 27B0 1028 16FA | | NVIDIA RTX 4000 SFF Ada Generation | 27B0 103C 16FA | @@ -825,10 +843,15 @@ Subsystem Device ID. | NVIDIA RTX 4000 SFF Ada Generation | 27B0 17AA 16FA | | NVIDIA L4 | 27B8 10DE 16CA | | NVIDIA L4 | 27B8 10DE 16EE | +| NVIDIA RTX 4000 Ada Generation Laptop GPU | 27BA | +| NVIDIA RTX 3500 Ada Generation Laptop GPU | 27BB | | NVIDIA GeForce RTX 4080 Laptop GPU | 27E0 | +| NVIDIA GeForce RTX 4060 Ti | 2803 | | NVIDIA GeForce RTX 4070 Laptop GPU | 2820 | +| NVIDIA RTX 3000 Ada Generation Laptop GPU | 2838 | | NVIDIA GeForce RTX 4070 Laptop GPU | 2860 | | NVIDIA GeForce RTX 4060 Laptop GPU | 28A0 | | NVIDIA GeForce RTX 4050 Laptop GPU | 28A1 | +| NVIDIA RTX 2000 Ada Generation Laptop GPU | 28B8 | | NVIDIA GeForce RTX 4060 Laptop GPU | 28E0 | | NVIDIA GeForce RTX 4050 Laptop GPU | 28E1 | diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index de8e19d7c0..9bf03fc844 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"530.41.03\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.43.02\" ifneq ($(SYSSRCHOST1X),) EXTRA_CFLAGS += -I$(SYSSRCHOST1X) @@ -91,7 +91,8 @@ ifeq ($(ARCH),arm64) endif ifeq ($(NV_BUILD_TYPE),debug) - EXTRA_CFLAGS += -g -gsplit-dwarf + EXTRA_CFLAGS += -g + EXTRA_CFLAGS += $(call cc-option,-gsplit-dwarf,) endif EXTRA_CFLAGS += -ffreestanding @@ -216,8 +217,10 @@ NV_HEADER_PRESENCE_TESTS = \ drm/drm_auth.h \ drm/drm_gem.h \ drm/drm_crtc.h \ + drm/drm_color_mgmt.h \ drm/drm_atomic.h \ drm/drm_atomic_helper.h \ + drm/drm_atomic_state_helper.h \ drm/drm_encoder.h \ drm/drm_atomic_uapi.h \ drm/drm_drv.h \ @@ -241,7 +244,6 @@ NV_HEADER_PRESENCE_TESTS = \ linux/efi.h \ linux/kconfig.h \ linux/platform/tegra/mc_utils.h \ - linux/semaphore.h \ linux/printk.h \ linux/ratelimit.h \ linux/prio_tree.h \ @@ -296,6 +298,7 @@ NV_HEADER_PRESENCE_TESTS = \ linux/iosys-map.h \ asm/coco.h \ linux/vfio_pci_core.h \ + linux/mdev.h \ soc/tegra/bpmp-abi.h \ soc/tegra/bpmp.h diff --git a/kernel-open/common/inc/nv-firmware-registry.h b/kernel-open/common/inc/nv-firmware-registry.h new file mode 100644 index 0000000000..ab8b405031 --- /dev/null +++ b/kernel-open/common/inc/nv-firmware-registry.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +// +// This file holds GPU firmware related registry key definitions that are +// shared between Windows and Unix +// + +#ifndef NV_FIRMWARE_REGISTRY_H +#define NV_FIRMWARE_REGISTRY_H + +// +// Registry key that when enabled, will enable use of GPU firmware. +// +// Possible mode values: +// 0 - Do not enable GPU firmware +// 1 - Enable GPU firmware +// 2 - (Default) Use the default enablement policy for GPU firmware +// +// Setting this to anything other than 2 will alter driver firmware- +// enablement policies, possibly disabling GPU firmware where it would +// have otherwise been enabled by default. +// +// Policy bits: +// +// POLICY_ALLOW_FALLBACK: +// As the normal behavior is to fail GPU initialization if this registry +// entry is set in such a way that results in an invalid configuration, if +// instead the user would like the driver to automatically try to fallback +// to initializing the failing GPU with firmware disabled, then this bit can +// be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). +// Note that this can result in a mixed mode configuration (ex: GPU0 has +// firmware enabled, but GPU1 does not). +// +#define NV_REG_STR_ENABLE_GPU_FIRMWARE "EnableGpuFirmware" + +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 + +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 + +#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 + +// +// Registry key that when enabled, will send GPU firmware logs +// to the system log, when possible. +// +// Possible values: +// 0 - Do not send GPU firmware logs to the system log +// 1 - Enable sending of GPU firmware logs to the system log +// 2 - (Default) Enable sending of GPU firmware logs to the system log for +// the debug kernel driver build only +// +#define NV_REG_STR_ENABLE_GPU_FIRMWARE_LOGS "EnableGpuFirmwareLogs" + +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 + +#endif // NV_FIRMWARE_REGISTRY_H diff --git a/kernel-open/common/inc/nv-firmware.h b/kernel-open/common/inc/nv-firmware.h index d5f161bc32..47d84fd06d 100644 --- a/kernel-open/common/inc/nv-firmware.h +++ b/kernel-open/common/inc/nv-firmware.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,11 +81,11 @@ static inline const char *nv_firmware_path( { switch (fw_chip_family) { + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ga10x.bin"); - case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: @@ -100,11 +100,11 @@ static inline const char *nv_firmware_path( { switch (fw_chip_family) { + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ga10x.bin"); - case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: diff --git a/kernel-open/common/inc/nv-hypervisor.h b/kernel-open/common/inc/nv-hypervisor.h index 422f258b2c..93bcdd6e67 100644 --- a/kernel-open/common/inc/nv-hypervisor.h +++ b/kernel-open/common/inc/nv-hypervisor.h @@ -41,6 +41,7 @@ typedef enum _HYPERVISOR_TYPE #define CMD_VGPU_VFIO_INJECT_INTERRUPT 1 #define CMD_VGPU_VFIO_REGISTER_MDEV 2 #define CMD_VGPU_VFIO_PRESENT 3 +#define CMD_VFIO_PCI_CORE_PRESENT 4 #define MAX_VF_COUNT_PER_GPU 64 @@ -57,6 +58,7 @@ typedef struct void *waitQueue; void *nv; NvU32 *vgpuTypeIds; + NvU8 **vgpuNames; NvU32 numVgpuTypes; NvU32 domain; NvU8 bus; diff --git a/kernel-open/common/inc/nv-ioctl-numa.h b/kernel-open/common/inc/nv-ioctl-numa.h index 3fad82092d..1d456ec953 100644 --- a/kernel-open/common/inc/nv-ioctl-numa.h +++ b/kernel-open/common/inc/nv-ioctl-numa.h @@ -62,6 +62,7 @@ typedef struct nv_ioctl_numa_info uint64_t memblock_size __aligned(8); uint64_t numa_mem_addr __aligned(8); uint64_t numa_mem_size __aligned(8); + uint8_t use_auto_online; nv_offline_addresses_t offline_addresses __aligned(8); } nv_ioctl_numa_info_t; diff --git a/kernel-open/common/inc/nv-kthread-q.h b/kernel-open/common/inc/nv-kthread-q.h index 991a1d9578..0b364d7cc9 100644 --- a/kernel-open/common/inc/nv-kthread-q.h +++ b/kernel-open/common/inc/nv-kthread-q.h @@ -28,15 +28,10 @@ #include // list #include // task_struct #include // NUMA_NO_NODE +#include #include "conftest.h" -#if defined(NV_LINUX_SEMAPHORE_H_PRESENT) - #include -#else - #include -#endif - //////////////////////////////////////////////////////////////////////////////// // nv_kthread_q: // diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h index 90df696e4d..a359421781 100644 --- a/kernel-open/common/inc/nv-linux.h +++ b/kernel-open/common/inc/nv-linux.h @@ -633,6 +633,8 @@ static NvBool nv_numa_node_has_memory(int node_id) free_pages(ptr, order); \ } +extern NvU64 nv_shared_gpa_boundary; + static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra) { pgprot_t prot = __pgprot(pgprot_val(vm_prot) | extra); @@ -644,7 +646,18 @@ static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra) * If cc_mkdec() is present, then pgprot_decrypted() can't be used. */ #if defined(NV_CC_MKDEC_PRESENT) - prot = __pgprot(__sme_clr(pgprot_val(vm_prot))); + if (nv_shared_gpa_boundary != 0) + { + /* + * By design, a VM using vTOM doesn't see the SEV setting and + * for AMD with vTOM, *set* means decrypted. + */ + prot = __pgprot(nv_shared_gpa_boundary | (pgprot_val(vm_prot))); + } + else + { + prot = __pgprot(__sme_clr(pgprot_val(vm_prot))); + } #else prot = pgprot_decrypted(prot); #endif @@ -1438,6 +1451,17 @@ struct nv_dma_device { NvBool nvlink; }; +/* Properties of the coherent link */ +typedef struct coherent_link_info_s { + /* Physical Address of the GPU memory in SOC AMAP. In the case of + * baremetal OS environment it is System Physical Address(SPA) and in the case + * of virutalized OS environment it is Intermediate Physical Address(IPA) */ + NvU64 gpu_mem_pa; + /* Bitmap of NUMA node ids, corresponding to the reserved PXMs, + * available for adding GPU memory to the kernel as system RAM */ + DECLARE_BITMAP(free_node_bitmap, MAX_NUMNODES); +} coherent_link_info_t; + #if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) /* * acpi data storage structure @@ -1471,6 +1495,13 @@ typedef struct nv_linux_state_s { /* IBM-NPU info associated with this GPU */ nv_ibmnpu_info_t *npu; + /* coherent link information */ + coherent_link_info_t coherent_link_info; + + /* Dedicated queue to be used for removing FB memory which is onlined + * to kernel as a NUMA node. Refer Bug : 3879845*/ + nv_kthread_q_t remove_numa_memory_q; + /* NUMA node information for the platforms where GPU memory is presented * as a NUMA node to the kernel */ struct { @@ -1481,6 +1512,7 @@ typedef struct nv_linux_state_s { /* NUMA online/offline status for platforms that support GPU memory as * NUMA node */ atomic_t status; + NvBool use_auto_online; } numa_info; nvidia_stack_t *sp[NV_DEV_STACK_COUNT]; @@ -1946,6 +1978,36 @@ static inline int nv_set_numa_status(nv_linux_state_t *nvl, int status) return 0; } +static inline NvBool nv_platform_use_auto_online(nv_linux_state_t *nvl) +{ + return nvl->numa_info.use_auto_online; +} + +typedef struct { + NvU64 base; + NvU64 size; + NvU32 nodeId; + int ret; +} remove_numa_memory_info_t; + +static void offline_numa_memory_callback +( + void *args +) +{ +#ifdef NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT + remove_numa_memory_info_t *pNumaInfo = (remove_numa_memory_info_t *)args; +#ifdef NV_REMOVE_MEMORY_HAS_NID_ARG + pNumaInfo->ret = offline_and_remove_memory(pNumaInfo->nodeId, + pNumaInfo->base, + pNumaInfo->size); +#else + pNumaInfo->ret = offline_and_remove_memory(pNumaInfo->base, + pNumaInfo->size); +#endif +#endif +} + typedef enum { NV_NUMA_STATUS_DISABLED = 0, diff --git a/kernel-open/common/inc/nv-lock.h b/kernel-open/common/inc/nv-lock.h index 34f593d0a1..030422948a 100644 --- a/kernel-open/common/inc/nv-lock.h +++ b/kernel-open/common/inc/nv-lock.h @@ -29,17 +29,12 @@ #include #include #include /* signal_pending, cond_resched */ +#include #if defined(NV_LINUX_SCHED_SIGNAL_H_PRESENT) #include /* signal_pending for kernels >= 4.11 */ #endif -#if defined(NV_LINUX_SEMAPHORE_H_PRESENT) -#include -#else -#include -#endif - #if defined(CONFIG_PREEMPT_RT) || defined(CONFIG_PREEMPT_RT_FULL) typedef raw_spinlock_t nv_spinlock_t; #define NV_SPIN_LOCK_INIT(lock) raw_spin_lock_init(lock) @@ -62,20 +57,7 @@ typedef spinlock_t nv_spinlock_t; #define NV_SPIN_UNLOCK_WAIT(lock) spin_unlock_wait(lock) #endif -#if defined(NV_CONFIG_PREEMPT_RT) -#define NV_INIT_SEMA(sema, val) sema_init(sema,val) -#else -#if !defined(__SEMAPHORE_INITIALIZER) && defined(__COMPAT_SEMAPHORE_INITIALIZER) -#define __SEMAPHORE_INITIALIZER __COMPAT_SEMAPHORE_INITIALIZER -#endif -#define NV_INIT_SEMA(sema, val) \ - { \ - struct semaphore __sema = \ - __SEMAPHORE_INITIALIZER(*(sema), val); \ - *(sema) = __sema; \ - } -#endif -#define NV_INIT_MUTEX(mutex) NV_INIT_SEMA(mutex, 1) +#define NV_INIT_MUTEX(mutex) sema_init(mutex, 1) static inline int nv_down_read_interruptible(struct rw_semaphore *lock) { diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index 48f46e309a..c6389bd73d 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -347,6 +347,12 @@ typedef struct nv_soc_irq_info_s { /* DMA-capable device data, defined by kernel interface layer */ typedef struct nv_dma_device nv_dma_device_t; +typedef struct nv_phys_addr_range +{ + NvU64 addr; + NvU64 len; +} nv_phys_addr_range_t; + typedef struct nv_state_t { void *priv; /* private data */ @@ -466,6 +472,9 @@ typedef struct nv_state_t /* Bool to check if ISO iommu enabled */ NvBool iso_iommu_present; + /* Bool to check if NISO iommu enabled */ + NvBool niso_iommu_present; + /* Bool to check if dma-buf is supported */ NvBool dma_buf_supported; @@ -477,6 +486,8 @@ typedef struct nv_state_t /* Bool to check if the device received a shutdown notification */ NvBool is_shutdown; + /* Bool to check if the GPU has a coherent sysmem link */ + NvBool coherent; } nv_state_t; // These define need to be in sync with defines in system.h @@ -505,6 +516,8 @@ struct nv_file_private_t typedef struct gpuSession *nvgpuSessionHandle_t; typedef struct gpuDevice *nvgpuDeviceHandle_t; typedef struct gpuAddressSpace *nvgpuAddressSpaceHandle_t; +typedef struct gpuTsg *nvgpuTsgHandle_t; +typedef struct UvmGpuTsgAllocParams_tag nvgpuTsgAllocParams_t; typedef struct gpuChannel *nvgpuChannelHandle_t; typedef struct UvmGpuChannelInfo_tag *nvgpuChannelInfo_t; typedef struct UvmGpuChannelAllocParams_tag nvgpuChannelAllocParams_t; @@ -531,7 +544,7 @@ typedef struct UvmGpuPagingChannelAllocParams_tag nvgpuPagingChannelAllocPara typedef struct UvmGpuPagingChannel_tag *nvgpuPagingChannelHandle_t; typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t; typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t; -typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU64, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t); /* @@ -599,6 +612,8 @@ typedef enum #define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ ((nv)->iso_iommu_present) +#define NV_SOC_IS_NISO_IOMMU_PRESENT(nv) \ + ((nv)->niso_iommu_present) /* * GPU add/remove events */ @@ -813,6 +828,7 @@ nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); void NV_API_CALL nv_put_file_private(void *); NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode); @@ -920,6 +936,7 @@ NV_STATUS NV_API_CALL rm_write_registry_string (nvidia_stack_t *, nv_state_t * void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char *); char* NV_API_CALL rm_remove_spaces (const char *); char* NV_API_CALL rm_string_token (char **, const char); +void NV_API_CALL rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool); NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *); @@ -951,12 +968,12 @@ NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent (nvidia_stack_t *, NvU64, N NV_STATUS NV_API_CALL rm_p2p_register_callback (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *); NV_STATUS NV_API_CALL rm_p2p_put_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, void *); NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *); -NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU32, NvU32, NvU64 *, void **); -NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *); +NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **); void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle); -NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, NvU64 *); -NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64); -NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, void *, nv_phys_addr_range_t **, NvU32 *); +void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, nv_phys_addr_range_t **, NvU32); +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *); void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *); NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); @@ -994,7 +1011,7 @@ void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *); NvBool NV_API_CALL rm_is_altstack_in_use(void); /* vGPU VFIO specific functions */ -NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); +NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32); NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); diff --git a/kernel-open/common/inc/nv_uvm_interface.h b/kernel-open/common/inc/nv_uvm_interface.h index 0641620492..9316984971 100644 --- a/kernel-open/common/inc/nv_uvm_interface.h +++ b/kernel-open/common/inc/nv_uvm_interface.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -327,7 +327,7 @@ NV_STATUS nvUvmInterfaceGetPmaObject(uvmGpuDeviceHandle device, // Mirrors pmaEvictPagesCb_t, see its documentation in pma.h. typedef NV_STATUS (*uvmPmaEvictPagesCallback)(void *callbackData, - NvU32 pageSize, + NvU64 pageSize, NvU64 *pPages, NvU32 count, NvU64 physBegin, @@ -390,7 +390,7 @@ void nvUvmInterfacePmaUnregisterEvictionCallbacks(void *pPma); */ NV_STATUS nvUvmInterfacePmaAllocPages(void *pPma, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, UvmPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages); @@ -419,7 +419,7 @@ NV_STATUS nvUvmInterfacePmaAllocPages(void *pPma, NV_STATUS nvUvmInterfacePmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); /******************************************************************************* @@ -447,7 +447,7 @@ NV_STATUS nvUvmInterfacePmaPinPages(void *pPma, NV_STATUS nvUvmInterfacePmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize); + NvU64 pageSize); /******************************************************************************* nvUvmInterfaceMemoryFree @@ -488,7 +488,7 @@ void nvUvmInterfaceMemoryFree(uvmGpuAddressSpaceHandle vaSpace, void nvUvmInterfacePmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); /******************************************************************************* @@ -507,7 +507,7 @@ void nvUvmInterfacePmaFreePages(void *pPma, NV_STATUS nvUvmInterfaceMemoryCpuMap(uvmGpuAddressSpaceHandle vaSpace, UvmGpuPointer gpuPointer, NvLength length, void **cpuPtr, - NvU32 pageSize); + NvU64 pageSize); /******************************************************************************* uvmGpuMemoryCpuUnmap @@ -518,15 +518,58 @@ void nvUvmInterfaceMemoryCpuUnMap(uvmGpuAddressSpaceHandle vaSpace, void *cpuPtr); /******************************************************************************* - nvUvmInterfaceChannelAllocate + nvUvmInterfaceTsgAllocate - This function will allocate a channel bound to a copy engine + This function allocates a Time-Slice Group (TSG). - allocParams must contain an engineIndex as channels need to be bound to an + allocParams must contain an engineIndex as TSGs need to be bound to an engine type at allocation time. The possible values are [0, - UVM_COPY_ENGINE_COUNT_MAX), but notably only the copy engines that have - UvmGpuCopyEngineCaps::supported set to true can be allocated. This struct - also contains information relative to GPFIFO and GPPut. + UVM_COPY_ENGINE_COUNT_MAX) for CE engine type. Notably only the copy engines + that have UvmGpuCopyEngineCaps::supported set to true can be allocated. + + Note that TSG is not supported on all GPU architectures for all engine + types, e.g., pre-Volta GPUs only support TSG for the GR/Compute engine type. + On devices that do not support HW TSGs on the requested engine, this API is + still required, i.e., a TSG handle is required in + nvUvmInterfaceChannelAllocate(), due to information stored in it necessary + for channel allocation. However, when HW TSGs aren't supported, a TSG handle + is essentially a "fake" TSG with no HW scheduling impact. + + tsg is filled with the address of the corresponding TSG handle. + + Arguments: + vaSpace[IN] - VA space linked to a client and a device under which + the TSG is allocated. + allocParams[IN] - structure with allocation settings. + tsg[OUT] - pointer to the new TSG handle. + + Error codes: + NV_ERR_GENERIC + NV_ERR_INVALID_ARGUMENT + NV_ERR_NO_MEMORY + NV_ERR_NOT_SUPPORTED +*/ +NV_STATUS nvUvmInterfaceTsgAllocate(uvmGpuAddressSpaceHandle vaSpace, + const UvmGpuTsgAllocParams *allocParams, + uvmGpuTsgHandle *tsg); + +/******************************************************************************* + nvUvmInterfaceTsgDestroy + + This function destroys a given TSG. + + Arguments: + tsg[IN] - Tsg handle +*/ +void nvUvmInterfaceTsgDestroy(uvmGpuTsgHandle tsg); + +/******************************************************************************* + nvUvmInterfaceChannelAllocate + + This function will allocate a channel bound to a copy engine(CE) or a SEC2 + engine. + + allocParams contains information relative to GPFIFO and GPPut. channel is filled with the address of the corresponding channel handle. @@ -536,17 +579,18 @@ void nvUvmInterfaceMemoryCpuUnMap(uvmGpuAddressSpaceHandle vaSpace, Host channel submission doorbell. Arguments: - vaSpace[IN] - VA space linked to a client and a device under which - the channel will be allocated + tsg[IN] - Time-Slice Group that the channel will be a member. allocParams[IN] - structure with allocation settings channel[OUT] - pointer to the new channel handle channelInfo[OUT] - structure filled with channel information Error codes: NV_ERR_GENERIC + NV_ERR_INVALID_ARGUMENT NV_ERR_NO_MEMORY + NV_ERR_NOT_SUPPORTED */ -NV_STATUS nvUvmInterfaceChannelAllocate(uvmGpuAddressSpaceHandle vaSpace, +NV_STATUS nvUvmInterfaceChannelAllocate(const uvmGpuTsgHandle tsg, const UvmGpuChannelAllocParams *allocParams, uvmGpuChannelHandle *channel, UvmGpuChannelInfo *channelInfo); @@ -554,7 +598,7 @@ NV_STATUS nvUvmInterfaceChannelAllocate(uvmGpuAddressSpaceHandle vaSpace, /******************************************************************************* nvUvmInterfaceChannelDestroy - This function destroys a given channel + This function destroys a given channel. Arguments: channel[IN] - channel handle @@ -575,7 +619,7 @@ void nvUvmInterfaceChannelDestroy(uvmGpuChannelHandle channel); NV_ERR_NO_MEMORY */ NV_STATUS nvUvmInterfaceQueryCaps(uvmGpuDeviceHandle device, - UvmGpuCaps * caps); + UvmGpuCaps *caps); /******************************************************************************* nvUvmInterfaceQueryCopyEnginesCaps @@ -946,13 +990,15 @@ NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(uvmGpuDeviceHandle device); Arguments: device[IN] - Device handle associated with the gpu pAccessCntrInfo[OUT] - Information provided by RM for access counter handling + accessCntrIndex[IN] - Access counter index Error codes: NV_ERR_GENERIC NV_ERR_INVALID_ARGUMENT */ NV_STATUS nvUvmInterfaceInitAccessCntrInfo(uvmGpuDeviceHandle device, - UvmGpuAccessCntrInfo *pAccessCntrInfo); + UvmGpuAccessCntrInfo *pAccessCntrInfo, + NvU32 accessCntrIndex); /******************************************************************************* nvUvmInterfaceDestroyAccessCntrInfo @@ -1402,4 +1448,250 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe char *methodStream, NvU32 methodStreamSize); +/******************************************************************************* + CSL Interface and Locking + + The following functions do not acquire the RM API or GPU locks and must not be called + concurrently with the same UvmCslContext parameter in different threads. The caller must + guarantee this exclusion. + + * nvUvmInterfaceCslLogDeviceEncryption + * nvUvmInterfaceCslRotateIv + * nvUvmInterfaceCslEncrypt + * nvUvmInterfaceCslDecrypt + * nvUvmInterfaceCslSign + * nvUvmInterfaceCslQueryMessagePool +*/ + +/******************************************************************************* + nvUvmInterfaceCslInitContext + + Allocates and initializes a CSL context for a given secure channel. + + The lifetime of the context is the same as the lifetime of the secure channel + it is paired with. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + channel[IN] - Handle to a secure channel. + + Error codes: + NV_ERR_INVALID_STATE - The system is not operating in Confidential Compute mode. + NV_ERR_INVALID_CHANNEL - The associated channel is not a secure channel. + NV_ERR_IN_USE - The context has already been initialized. +*/ +NV_STATUS nvUvmInterfaceCslInitContext(UvmCslContext *uvmCslContext, + uvmGpuChannelHandle channel); + +/******************************************************************************* + nvUvmInterfaceDeinitCslContext + + Securely deinitializes and clears the contents of a context. + + If context is already deinitialized then function returns immediately. + + Arguments: + uvmCslContext[IN] - The CSL context. +*/ +void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext); + + +/******************************************************************************* + nvUvmInterfaceCslLogDeviceEncryption + + Returns an IV that can be later used in the nvUvmInterfaceCslEncrypt + method. The IV contains a "freshness bit" which value is set by this method + and subsequently dirtied by nvUvmInterfaceCslEncrypt to prevent + non-malicious reuse of the IV. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + encryptIv[OUT] - Parameter that is stored before a successful + device encryption. It is used as an input to + nvUvmInterfaceCslEncrypt. + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - New IV would cause a counter to overflow. +*/ +NV_STATUS nvUvmInterfaceCslAcquireEncryptionIv(UvmCslContext *uvmCslContext, + UvmCslIv *encryptIv); + +/******************************************************************************* + nvUvmInterfaceCslLogDeviceEncryption + + Logs and checks information about device encryption. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + decryptIv[OUT] - Parameter that is stored before a successful + device encryption. It is used as an input to + nvUvmInterfaceCslDecrypt. + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - The device encryption would cause a counter + to overflow. +*/ +NV_STATUS nvUvmInterfaceCslLogDeviceEncryption(UvmCslContext *uvmCslContext, + UvmCslIv *decryptIv); + +/******************************************************************************* + nvUvmInterfaceCslRotateIv + + Rotates the IV for a given channel and direction. + + This function will rotate the IV on both the CPU and the GPU. + Outstanding messages that have been encrypted by the GPU should first be + decrypted before calling this function with direction equal to + UVM_CSL_DIR_GPU_TO_CPU. Similiarly, outstanding messages that have been + encrypted by the CPU should first be decrypted before calling this function + with direction equal to UVM_CSL_DIR_CPU_TO_GPU. For a given direction + the channel must be idle before calling this function. This function can be + called regardless of the value of the IV's message counter. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + +Arguments: + uvmCslContext[IN/OUT] - The CSL context. + direction[IN] - Either + - UVM_CSL_DIR_CPU_TO_GPU + - UVM_CSL_DIR_GPU_TO_CPU + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - The rotate operation would cause a counter + to overflow. + NV_ERR_INVALID_ARGUMENT - Invalid value for direction. +*/ +NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext, + UvmCslDirection direction); + +/******************************************************************************* + nvUvmInterfaceCslEncrypt + + Encrypts data and produces an authentication tag. + + Auth, input, and output buffers must not overlap. If they do then calling + this function produces undefined behavior. Performance is typically + maximized when the input and output buffers are 16-byte aligned. This is + natural alignment for AES block. + The encryptIV can be obtained from nvUvmInterfaceCslAcquireEncryptionIv. + However, it is optional. If it is NULL, the next IV in line will be used. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + +Arguments: + uvmCslContext[IN/OUT] - The CSL context. + bufferSize[IN] - Size of the input and output buffers in + units of bytes. Value can range from 1 byte + to (2^32) - 1 bytes. + inputBuffer[IN] - Address of plaintext input buffer. + encryptIv[IN/OUT] - IV to use for encryption. Can be NULL. + outputBuffer[OUT] - Address of ciphertext output buffer. + authTagBuffer[OUT] - Address of authentication tag buffer. + Its size is UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES. + + Error codes: + NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes. + - The encryptIv has already been used. +*/ +NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + UvmCslIv *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); + +/******************************************************************************* + nvUvmInterfaceCslDecrypt + + Verifies the authentication tag and decrypts data. + + Auth, input, and output buffers must not overlap. If they do then calling + this function produces undefined behavior. Performance is typically + maximized when the input and output buffers are 16-byte aligned. This is + natural alignment for AES block. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + bufferSize[IN] - Size of the input and output buffers in + units of bytes. Value can range from 1 byte + to (2^32) - 1 bytes. + decryptIv[IN] - Parameter given by nvUvmInterfaceCslLogDeviceEncryption. + inputBuffer[IN] - Address of ciphertext input buffer. + outputBuffer[OUT] - Address of plaintext output buffer. + authTagBuffer[IN] - Address of authentication tag buffer. + Its size is UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES. + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - The decryption operation would cause a + counter overflow to occur. + NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes. + NV_ERR_INVALID_DATA - Verification of the authentication tag fails. +*/ +NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + UvmCslIv const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *authTagBuffer); + +/******************************************************************************* + nvUvmInterfaceCslSign + + Generates an authentication tag for secure work launch. + + Auth and input buffers must not overlap. If they do then calling this function produces + undefined behavior. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + bufferSize[IN] - Size of the input buffer in units of bytes. + Value can range from 1 byte to (2^32) - 1 bytes. + inputBuffer[IN] - Address of plaintext input buffer. + authTagBuffer[OUT] - Address of authentication tag buffer. + Its size is UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES. + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - The signing operation would cause a counter overflow to occur. + NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes. +*/ +NV_STATUS nvUvmInterfaceCslSign(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer); + + +/******************************************************************************* + nvUvmInterfaceCslQueryMessagePool + + Returns the number of messages that can be encrypted before the message counter will overflow. + + See "CSL Interface and Locking" for locking requirements. + This function does not perform dynamic memory allocation. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + direction[IN] - Either UVM_CSL_DIR_CPU_TO_GPU or UVM_CSL_DIR_GPU_TO_CPU. + messageNum[OUT] - Number of messages left before overflow. + + Error codes: + NV_ERR_INVALID_ARGUMENT - The value of the direction parameter is illegal. +*/ +NV_STATUS nvUvmInterfaceCslQueryMessagePool(UvmCslContext *uvmCslContext, + UvmCslDirection direction, + NvU64 *messageNum); + #endif // _NV_UVM_INTERFACE_H_ diff --git a/kernel-open/common/inc/nv_uvm_types.h b/kernel-open/common/inc/nv_uvm_types.h index 0b9895bf8d..4eb8cc6b1f 100644 --- a/kernel-open/common/inc/nv_uvm_types.h +++ b/kernel-open/common/inc/nv_uvm_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -92,6 +92,7 @@ typedef unsigned long long UvmGpuPointer; typedef struct uvmGpuSession_tag *uvmGpuSessionHandle; // gpuSessionHandle typedef struct uvmGpuDevice_tag *uvmGpuDeviceHandle; // gpuDeviceHandle typedef struct uvmGpuAddressSpace_tag *uvmGpuAddressSpaceHandle; // gpuAddressSpaceHandle +typedef struct uvmGpuTsg_tag *uvmGpuTsgHandle; // gpuTsgHandle typedef struct uvmGpuChannel_tag *uvmGpuChannelHandle; // gpuChannelHandle typedef struct uvmGpuCopyEngine_tag *uvmGpuCopyEngineHandle; // gpuObjectHandle @@ -280,6 +281,15 @@ typedef struct UvmGpuChannelInfo_tag // to kick off the new work. // volatile NvU32 *pWorkSubmissionToken; + + // GPU VAs of both GPFIFO and GPPUT are needed in Confidential Computing + // so a channel can be controlled via another channel (SEC2 or WLC/LCIC) + NvU64 gpFifoGpuVa; + NvU64 gpPutGpuVa; + // GPU VA of work submission offset is needed in Confidential Computing + // so CE channels can ring doorbell of other channels as required for + // WLC/LCIC work submission + NvU64 workSubmissionOffsetGpuVa; } UvmGpuChannelInfo; typedef enum @@ -292,6 +302,17 @@ typedef enum UVM_BUFFER_LOCATION_VID = 2, } UVM_BUFFER_LOCATION; +typedef struct UvmGpuTsgAllocParams_tag +{ + // Interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE + NvU32 engineType; + + // Index of the engine the TSG is bound to. + // Ignored if engineType is anything other than + // UVM_GPU_CHANNEL_ENGINE_TYPE_CE. + NvU32 engineIndex; +} UvmGpuTsgAllocParams; + typedef struct UvmGpuChannelAllocParams_tag { NvU32 numGpFifoEntries; @@ -300,13 +321,9 @@ typedef struct UvmGpuChannelAllocParams_tag NvU32 gpFifoLoc; NvU32 gpPutLoc; - // Index of the engine the channel will be bound to - // ignored if engineType is anything other than UVM_GPU_CHANNEL_ENGINE_TYPE_CE - NvU32 engineIndex; - - // interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE - NvU32 engineType; - + // Allocate the channel as secure. This flag should only be set when + // Confidential Compute is enabled. + NvBool secure; } UvmGpuChannelAllocParams; typedef struct UvmGpuPagingChannelAllocParams_tag @@ -350,6 +367,9 @@ typedef struct // True if the CE can be used for P2P transactions NvBool p2p:1; + // True if the CE supports encryption + NvBool secure:1; + // Mask of physical CEs assigned to this LCE // // The value returned by RM for this field may change when a GPU is @@ -372,39 +392,16 @@ typedef enum UVM_LINK_TYPE_NVLINK_2, UVM_LINK_TYPE_NVLINK_3, UVM_LINK_TYPE_NVLINK_4, + UVM_LINK_TYPE_C2C, } UVM_LINK_TYPE; typedef struct UvmGpuCaps_tag { - NvU32 sysmemLink; // UVM_LINK_TYPE - NvU32 sysmemLinkRateMBps; // See UvmGpuP2PCapsParams::totalLinkLineRateMBps + // If numaEnabled is NV_TRUE, then the system address of allocated GPU + // memory can be converted to struct pages. See + // UvmGpuInfo::systemMemoryWindowStart. NvBool numaEnabled; NvU32 numaNodeId; - - // On ATS systems, GPUs connected to different CPU sockets can have peer - // traffic. They are called indirect peers. However, indirect peers are - // mapped using sysmem aperture. In order to disambiguate the location of a - // specific memory address, each GPU maps its memory to a different window - // in the System Physical Address (SPA) space. The following fields contain - // the base + size of such window for the GPU. systemMemoryWindowSize - // different than 0 indicates that the window is valid. - // - // - If the window is valid, then we can map GPU memory to the CPU as - // cache-coherent by adding the GPU address to the window start. - // - If numaEnabled is NV_TRUE, then we can also convert the system - // addresses of allocated GPU memory to struct pages. - // - // TODO: Bug 1986868: fix window start computation for SIMICS - NvU64 systemMemoryWindowStart; - NvU64 systemMemoryWindowSize; - - // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch - // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, - // nvswitchMemoryWindowStart tells the base address for the GPU in the - // NVSwitch address space. It is used when creating PTEs of memory mappings - // to NVSwitch peers. - NvBool connectedToSwitch; - NvU64 nvswitchMemoryWindowStart; } UvmGpuCaps; typedef struct UvmGpuAddressSpaceInfo_tag @@ -436,6 +433,8 @@ typedef struct UvmGpuAllocInfo_tag NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved + NvBool bUnprotected; // Allocation to be made in unprotected memory whenever + // SEV or GPU CC modes are enabled. Ignored otherwise } UvmGpuAllocInfo; typedef enum @@ -584,6 +583,20 @@ typedef struct UvmGpuClientInfo_tag NvHandle hSmcPartRef; } UvmGpuClientInfo; +typedef enum +{ + UVM_GPU_CONF_COMPUTE_MODE_NONE, + UVM_GPU_CONF_COMPUTE_MODE_APM, + UVM_GPU_CONF_COMPUTE_MODE_HCC, + UVM_GPU_CONF_COMPUTE_MODE_COUNT +} UvmGpuConfComputeMode; + +typedef struct UvmGpuConfComputeCaps_tag +{ + // Out: GPU's confidential compute mode + UvmGpuConfComputeMode mode; +} UvmGpuConfComputeCaps; + #define UVM_GPU_NAME_LENGTH 0x40 typedef struct UvmGpuInfo_tag @@ -648,6 +661,31 @@ typedef struct UvmGpuInfo_tag UvmGpuClientInfo smcUserClientInfo; + // Confidential Compute capabilities of this GPU + UvmGpuConfComputeCaps gpuConfComputeCaps; + + // UVM_LINK_TYPE + NvU32 sysmemLink; + + // See UvmGpuP2PCapsParams::totalLinkLineRateMBps + NvU32 sysmemLinkRateMBps; + + // On coherent systems each GPU maps its memory to a window in the System + // Physical Address (SPA) space. The following fields describe that window. + // + // systemMemoryWindowSize > 0 indicates that the window is valid. meaning + // that GPU memory can be mapped by the CPU as cache-coherent by adding the + // GPU address to the window start. + NvU64 systemMemoryWindowStart; + NvU64 systemMemoryWindowSize; + + // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch + // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, + // nvswitchMemoryWindowStart tells the base address for the GPU in the + // NVSwitch address space. It is used when creating PTEs of memory mappings + // to NVSwitch peers. + NvBool connectedToSwitch; + NvU64 nvswitchMemoryWindowStart; } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag @@ -690,6 +728,9 @@ typedef struct UvmPmaStatistics_tag volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions + volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory + volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory + volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory } UvmPmaStatistics; /******************************************************************************* @@ -797,24 +838,80 @@ struct UvmOpsUvmEvents #endif }; +#define UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES 32 +#define UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES 16 + +typedef union UvmFaultMetadataPacket_tag +{ + struct { + NvU8 authTag[UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES]; + NvBool valid; + }; + // padding to 32Bytes + NvU8 _padding[32]; +} UvmFaultMetadataPacket; + typedef struct UvmGpuFaultInfo_tag { struct { - // Register mappings obtained from RM + // Fault buffer GET register mapping. + // + // When Confidential Computing is enabled, GET refers to the shadow + // buffer (see bufferAddress below), and not to the actual HW buffer. + // In this setup, writes of GET (by UVM) do not result on re-evaluation + // of any interrupt condition. volatile NvU32* pFaultBufferGet; + + // Fault buffer PUT register mapping. + // + // When Confidential Computing is enabled, PUT refers to the shadow + // buffer (see bufferAddress below), and not to the actual HW buffer. + // In this setup, writes of PUT (by GSP-RM) do not result on + // re-evaluation of any interrupt condition. volatile NvU32* pFaultBufferPut; - // Note: this variable is deprecated since buffer overflow is not a separate - // register from future chips. + + // Note: this variable is deprecated since buffer overflow is not a + // separate register from future chips. volatile NvU32* pFaultBufferInfo; + + // Register mapping used to clear a replayable fault interrupt in + // Turing+ GPUs. volatile NvU32* pPmcIntr; + + // Register mapping used to enable replayable fault interrupts. volatile NvU32* pPmcIntrEnSet; + + // Register mapping used to disable replayable fault interrupts. volatile NvU32* pPmcIntrEnClear; + + // Register used to enable, or disable, faults on prefetches. volatile NvU32* pPrefetchCtrl; + + // Replayable fault interrupt mask identifier. NvU32 replayableFaultMask; - // fault buffer cpu mapping and size - void* bufferAddress; + + // Fault buffer CPU mapping + void* bufferAddress; + // + // When Confidential Computing is disabled, the mapping points to the + // actual HW fault buffer. + // + // When Confidential Computing is enabled, the mapping points to a + // copy of the HW fault buffer. This "shadow buffer" is maintained + // by GSP-RM. + + // Size, in bytes, of the fault buffer pointed by bufferAddress. NvU32 bufferSize; + // Mapping pointing to the start of the fault buffer metadata containing + // a 16Byte authentication tag and a valid byte. Always NULL when + // Confidential Computing is disabled. + UvmFaultMetadataPacket *bufferMetadata; + + // Indicates whether UVM owns the replayable fault buffer. + // The value of this field is always NV_TRUE When Confidential Computing + // is disabled. + NvBool bUvmOwnsHwFaultBuffer; } replayable; struct { @@ -834,8 +931,19 @@ typedef struct UvmGpuFaultInfo_tag // Preallocated stack for functions called from the UVM isr bottom half void *isr_bh_sp; + // Used only when Hopper Confidential Compute is enabled + // Register mappings obtained from RM + volatile NvU32* pFaultBufferPut; + + // Used only when Hopper Confidential Compute is enabled + // Cached get index of the non-replayable shadow buffer + NvU32 shadowBufferGet; + + // See replayable.bufferMetadata + UvmFaultMetadataPacket *shadowBufferMetadata; } nonReplayable; NvHandle faultBufferHandle; + struct Device *pDevice; } UvmGpuFaultInfo; struct Device; @@ -871,12 +979,6 @@ typedef struct UvmGpuAccessCntrInfo_tag void* bufferAddress; NvU32 bufferSize; NvHandle accessCntrBufferHandle; - - // The Notification address in the access counter notification msg does not - // contain the correct upper bits 63-47 for GPA-based notifications. RM - // provides us with the correct offset to be added. - // See Bug 1803015 - NvU64 baseDmaSysmemAddr; } UvmGpuAccessCntrInfo; typedef enum @@ -919,6 +1021,7 @@ typedef enum UvmPmaGpuMemoryType_tag } UVM_PMA_GPU_MEMORY_TYPE; typedef UvmGpuChannelInfo gpuChannelInfo; +typedef UvmGpuTsgAllocParams gpuTsgAllocParams; typedef UvmGpuChannelAllocParams gpuChannelAllocParams; typedef UvmGpuCaps gpuCaps; typedef UvmGpuCopyEngineCaps gpuCeCaps; @@ -943,4 +1046,24 @@ typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo; typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams; typedef UvmPmaAllocationOptions gpuPmaAllocationOptions; +// This struct shall not be accessed nor modified directly by UVM as it is +// entirely managed by the RM layer +typedef struct UvmCslContext_tag +{ + struct ccslContext_t *ctx; + void *nvidia_stack; +} UvmCslContext; + +typedef struct UvmCslIv +{ + NvU8 iv[12]; + NvU8 fresh; +} UvmCslIv; + +typedef enum UvmCslDirection +{ + UVM_CSL_DIR_CPU_TO_GPU, + UVM_CSL_DIR_GPU_TO_CPU +} UvmCslDirection; + #endif // _NV_UVM_TYPES_H_ diff --git a/kernel-open/common/inc/nvkms-kapi.h b/kernel-open/common/inc/nvkms-kapi.h index c76493d748..cf0c2a5902 100644 --- a/kernel-open/common/inc/nvkms-kapi.h +++ b/kernel-open/common/inc/nvkms-kapi.h @@ -165,8 +165,6 @@ struct NvKmsKapiConnectorInfo { NvU32 physicalIndex; - NvU32 headMask; - NvKmsConnectorSignalFormat signalFormat; NvKmsConnectorType type; @@ -194,6 +192,7 @@ struct NvKmsKapiStaticDisplayInfo { NvU32 numPossibleClones; NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS]; + NvU32 headMask; }; struct NvKmsKapiSyncpt { @@ -1074,6 +1073,21 @@ struct NvKmsKapiFunctionsTable { NvU64 *pPages ); + /*! + * Check if this memory object can be scanned out for display. + * + * \param [in] device A device allocated using allocateDevice(). + * + * \param [in] memory The memory object to check for display support. + * + * \return NV_TRUE if this memory can be displayed, NV_FALSE if not. + */ + NvBool (*isMemoryValidForDisplay) + ( + const struct NvKmsKapiDevice *device, + const struct NvKmsKapiMemory *memory + ); + /* * Import SGT as a memory handle. * diff --git a/kernel-open/common/inc/nvlimits.h b/kernel-open/common/inc/nvlimits.h index a896adf009..619c749c7e 100644 --- a/kernel-open/common/inc/nvlimits.h +++ b/kernel-open/common/inc/nvlimits.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nvlimits.finn +// Source file: nvlimits.finn // diff --git a/kernel-open/common/inc/nvstatuscodes.h b/kernel-open/common/inc/nvstatuscodes.h index 517a8cef89..3b11ee9eeb 100644 --- a/kernel-open/common/inc/nvstatuscodes.h +++ b/kernel-open/common/inc/nvstatuscodes.h @@ -149,6 +149,7 @@ NV_STATUS_CODE(NV_ERR_NVLINK_TRAINING_ERROR, 0x00000077, "Nvlink Train NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error") NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") +NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value") // Warnings: NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") diff --git a/kernel-open/common/inc/nvtypes.h b/kernel-open/common/inc/nvtypes.h index c349199cf6..84d72a0079 100644 --- a/kernel-open/common/inc/nvtypes.h +++ b/kernel-open/common/inc/nvtypes.h @@ -513,6 +513,12 @@ typedef struct // place to re-locate these from nvos.h which cannot be included by a number // of builds that need them +#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) +#else + #define NV_ATTRIBUTE_UNUSED +#endif + #if defined(_MSC_VER) #if _MSC_VER >= 1310 @@ -536,8 +542,6 @@ typedef struct #define NV_FORCERESULTCHECK - #define NV_ATTRIBUTE_UNUSED - #define NV_FORMAT_PRINTF(_f, _a) #else // ! defined(_MSC_VER) @@ -635,12 +639,6 @@ typedef struct #define NV_FORCERESULTCHECK #endif - #if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) - #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) - #else - #define NV_ATTRIBUTE_UNUSED - #endif - /* * Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at * parameter number 'f' and variadic arguments start at parameter number 'a'. diff --git a/kernel-open/common/inc/os-interface.h b/kernel-open/common/inc/os-interface.h index 588092f618..32ccc0adc2 100644 --- a/kernel-open/common/inc/os-interface.h +++ b/kernel-open/common/inc/os-interface.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -188,7 +188,7 @@ NV_STATUS NV_API_CALL os_read_file (void *, NvU8 *, NvU64, NvU NV_STATUS NV_API_CALL os_open_readonly_file (const char *, void **); NV_STATUS NV_API_CALL os_open_and_read_file (const char *, NvU8 *, NvU64); NvBool NV_API_CALL os_is_nvswitch_present (void); -void NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); +NV_STATUS NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); NV_STATUS NV_API_CALL os_alloc_wait_queue (os_wait_queue **); void NV_API_CALL os_free_wait_queue (os_wait_queue *); void NV_API_CALL os_wait_uninterruptible (os_wait_queue *); @@ -207,6 +207,9 @@ enum os_pci_req_atomics_type { OS_INTF_PCIE_REQ_ATOMICS_128BIT }; NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); +NV_STATUS NV_API_CALL os_numa_add_gpu_memory (void *, NvU64, NvU64, NvU32 *); +NV_STATUS NV_API_CALL os_numa_remove_gpu_memory (void *, NvU64, NvU64, NvU32); +NV_STATUS NV_API_CALL os_offline_page_at_address(NvU64 address); extern NvU32 os_page_size; extern NvU64 os_page_mask; diff --git a/kernel-open/common/inc/rm-gpu-ops.h b/kernel-open/common/inc/rm-gpu-ops.h index cdf26af8b4..7cafc26668 100644 --- a/kernel-open/common/inc/rm-gpu-ops.h +++ b/kernel-open/common/inc/rm-gpu-ops.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -56,7 +56,9 @@ NV_STATUS NV_API_CALL rm_gpu_ops_get_p2p_caps(nvidia_stack_t *, nvgpuDeviceHan NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_map(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, NvLength, void **, NvU32); NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_ummap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, void*); -NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, const nvgpuChannelAllocParams_t *, nvgpuChannelHandle_t *, nvgpuChannelInfo_t); +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_allocate(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, const nvgpuTsgAllocParams_t *, nvgpuTsgHandle_t *); +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_destroy(nvidia_stack_t *, nvgpuTsgHandle_t); +NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *, const nvgpuTsgHandle_t, const nvgpuChannelAllocParams_t *, nvgpuChannelHandle_t *, nvgpuChannelInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_channel_destroy(nvidia_stack_t *, nvgpuChannelHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_memory_free(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64); NV_STATUS NV_API_CALL rm_gpu_ops_query_caps(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuCaps_t); @@ -76,7 +78,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_destroy_fault_info(nvidia_stack_t *, nvgpuDevi NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, void *, NvU32 *); NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *, nvgpuDeviceHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_has_pending_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool *); -NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t); +NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, NvU32); NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_own_access_cntr_intr(nvidia_stack_t *, nvgpuSessionHandle_t, nvgpuAccessCntrInfo_t, NvBool); NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, nvgpuAccessCntrConfig_t); @@ -99,4 +101,15 @@ NV_STATUS NV_API_CALL rm_gpu_ops_paging_channels_map(nvidia_stack_t *, nvgpuAdd void NV_API_CALL rm_gpu_ops_paging_channels_unmap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuDeviceHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *, nvgpuPagingChannelHandle_t, char *, NvU32); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *, struct ccslContext_t **, nvgpuChannelHandle_t); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *, struct ccslContext_t *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_log_device_encryption(nvidia_stack_t *, struct ccslContext_t *, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_acquire_encryption_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt_with_iv(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8*, NvU8 *, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 const *, NvU8 *, NvU8 const *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_sign(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_query_message_pool(nvidia_stack_t *, struct ccslContext_t *, NvU8, NvU64 *); + #endif diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index d6c0790226..538b0b27e7 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -919,9 +919,42 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_MIGRATION_OPS_PRESENT" "" "types" ;; - mdev_parent) + vfio_log_ops) # - # Determine if the struct mdev_parent type is present. + # Determine if vfio_log_ops struct is present or not + # + # Added by commit 80c4b92a2dc48 ("vfio: Introduce the DMA + # logging feature support") in v6.1 + # + CODE=" + #include + #include + struct vfio_log_ops log_ops; + " + + compile_check_conftest "$CODE" "NV_VFIO_LOG_OPS_PRESENT" "" "types" + ;; + + vfio_migration_ops_has_migration_get_data_size) + # + # Determine if vfio_migration_ops struct has .migration_get_data_size field. + # + # Added by commit in 4e016f969529f ("vfio: Add an option to get migration + # data size") in v6.2 kernel. + # + CODE=" + #include + #include + int conftest_mdev_vfio_migration_ops_has_migration_get_data_size(void) { + return offsetof(struct vfio_migration_ops, migration_get_data_size); + }" + + compile_check_conftest "$CODE" "NV_VFIO_MIGRATION_OPS_HAS_MIGRATION_GET_DATA_SIZE" "" "types" + ;; + + mdev_parent_ops) + # + # Determine if the struct mdev_parent_ops type is present. # # Added by commit 42930553a7c1 ("vfio-mdev: de-polute the # namespace, rename parent_device & parent_ops") in v4.10 @@ -929,12 +962,28 @@ compile_test() { CODE=" #include #include - struct mdev_parent_ops conftest_mdev_parent; + struct mdev_parent_ops conftest_mdev_parent_ops; " compile_check_conftest "$CODE" "NV_MDEV_PARENT_OPS_STRUCT_PRESENT" "" "types" ;; + mdev_parent) + # + # Determine if the struct mdev_parent type is present. + # + # Added by commit 89345d5177aa ("vfio/mdev: embedd struct mdev_parent in + # the parent data structure") in v6.1 + # + CODE=" + #include + #include + struct mdev_parent conftest_mdev_parent; + " + + compile_check_conftest "$CODE" "NV_MDEV_PARENT_STRUCT_PRESENT" "" "types" + ;; + mdev_parent_dev) # # Determine if mdev_parent_dev() function is present or not @@ -952,6 +1001,23 @@ compile_test() { compile_check_conftest "$CODE" "NV_MDEV_PARENT_DEV_PRESENT" "" "functions" ;; + vfio_free_device) + # + # Determine if vfio_free_device() function is present or not + # + # Removed by commit 913447d06f03 ("vfio: Remove vfio_free_device") + # in v6.2 + # + CODE=" + #include + #include + void conftest_vfio_free_device() { + vfio_free_device(); + }" + + compile_check_conftest "$CODE" "NV_VFIO_FREE_DEVICE_PRESENT" "" "functions" + ;; + mdev_from_dev) # # Determine if mdev_from_dev() function is present or not. @@ -1124,7 +1190,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_UNINIT_GROUP_DEV_PRESENT" "" "functions" ;; - vfio_pci_core_available) # Determine if VFIO_PCI_CORE is available # @@ -1147,6 +1212,44 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_PCI_CORE_PRESENT" "" "generic" ;; + mdev_available) + # Determine if MDEV is available + # + # Added by commit 7b96953bc640 ("vfio: Mediated device Core driver") + # in v4.10 + # + CODE=" + #if defined(NV_LINUX_MDEV_H_PRESENT) + #include + #include + #endif + + #if !defined(CONFIG_VFIO_MDEV) && !defined(CONFIG_VFIO_MDEV_MODULE) + #error MDEV not enabled + #endif + void conftest_mdev_available(void) { + struct mdev_device *mdev; + }" + + compile_check_conftest "$CODE" "NV_MDEV_PRESENT" "" "generic" + ;; + + vfio_alloc_device) + # + # Determine if vfio_alloc_device() function is present or not. + # + # Added by commit cb9ff3f3b84c (vfio: Add helpers for unifying vfio_device + # life cycle) in v6.1 + # + CODE=" + #include + void conftest_vfio_alloc_device() { + vfio_alloc_device(); + }" + + compile_check_conftest "$CODE" "NV_VFIO_ALLOC_DEVICE_PRESENT" "" "functions" + ;; + vfio_register_emulated_iommu_dev) # # Determine if vfio_register_emulated_iommu_dev() function is present or not. @@ -2039,6 +2142,84 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_REINIT_PRIMARY_MODE_GROUP_PRESENT" "" "functions" ;; + drm_helper_crtc_enable_color_mgmt) + # + # Determine if the function drm_helper_crtc_enable_color_mgmt() is + # present. + # + # Added by commit 5488dc16fde7 ("drm: introduce pipe color + # correction properties") in v4.6 (2016-03-08). + # + # Removed by commit f8ed34ac7b45 ("drm: drm_helper_crtc_enable_color_mgmt() + # => drm_crtc_enable_color_mgmt()") in v4.8-rc1 (2016-06-07). + # + CODE=" + #include + void conftest_drm_helper_crtc_enable_color_mgmt(void) { + drm_helper_crtc_enable_color_mgmt(); + }" + + compile_check_conftest "$CODE" "NV_DRM_HELPER_CRTC_ENABLE_COLOR_MGMT_PRESENT" "" "functions" + + ;; + + drm_crtc_enable_color_mgmt) + # + # Determine if the function drm_crtc_enable_color_mgmt() is + # present. + # + # Added by commit f8ed34ac7b45 ("drm: drm_helper_crtc_enable_color_mgmt() + # => drm_crtc_enable_color_mgmt()") in v4.8-rc1 (2016-06-07), replacing + # drm_helper_crtc_enable_color_mgmt(). + # + # Moved to drm_color_mgmt.[ch] by commit f1e2f66ce2d9 ("drm: Extract + # drm_color_mgmt.[hc]") in v4.9-rc1 (2016-09-22) + # + CODE=" + #if defined(NV_DRM_DRM_CRTC_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_COLOR_MGMT_H_PRESENT) + #include + #endif + void conftest_drm_crtc_enable_color_mgmt(void) { + drm_crtc_enable_color_mgmt(); + }" + + compile_check_conftest "$CODE" "NV_DRM_CRTC_ENABLE_COLOR_MGMT_PRESENT" "" "functions" + ;; + + drm_atomic_helper_legacy_gamma_set) + # + # Determine if the function drm_atomic_helper_legacy_gamma_set() is + # present. + # + # Added by commit 5488dc16fde7 ("drm: introduce pipe color + # correction properties") in v4.6 (2016-03-08) + # + # Accidentally moved to drm_atomic_state_helper.[ch] by commit + # 9ef8a9dc4b21 ("drm: Extract drm_atomic_state_helper.[ch]") + # and moved back to drm_atomic_helper.[ch] by commit 1d8224e790c7 + # ("drm: Fix up drm_atomic_state_helper.[hc] extraction") in + # v5.0-rc1 + # + # Removed by commit 6ca2ab8086af ("drm: automatic legacy gamma + # support") in v5.12 (2020-12-15) + # + CODE=" + #if defined(NV_DRM_DRM_ATOMIC_HELPER_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_ATOMIC_STATE_HELPER_H_PRESENT) + #include + #endif + void conftest_drm_atomic_helper_legacy_gamma_set(void) { + drm_atomic_helper_legacy_gamma_set(); + }" + + compile_check_conftest "$CODE" "NV_DRM_ATOMIC_HELPER_LEGACY_GAMMA_SET_PRESENT" "" "functions" + ;; + wait_on_bit_lock_argument_count) # # Determine how many arguments wait_on_bit_lock takes. @@ -5501,6 +5682,28 @@ compile_test() { compile_check_conftest "$CODE" "NV_MMGET_NOT_ZERO_PRESENT" "" "functions" ;; + mmgrab) + # + # Determine if mmgrab() function is present + # + # mmgrab() function was added by commit + # f1f1007644ffc8051a4c11427d58b1967ae7b75a ("mm: add new + # mmgrab() helper") in v4.11 (2017-02-01). See comment for + # mmget_not_zero for a description of how the headers have + # changed. + CODE=" + #if defined(NV_LINUX_SCHED_MM_H_PRESENT) + #include + #elif defined(NV_LINUX_SCHED_H_PRESENT) + #include + #endif + void conftest_mmgrab(void) { + mmgrab(); + }" + + compile_check_conftest "$CODE" "NV_MMGRAB_PRESENT" "" "functions" + ;; + dma_resv_add_fence) # # Determine if the dma_resv_add_fence() function is present. @@ -5621,6 +5824,80 @@ compile_test() { compile_check_conftest "$CODE" "NV_ACPI_VIDEO_BACKLIGHT_USE_NATIVE" "" "functions" ;; + vm_fault_to_errno) + # + # Determine if the vm_fault_to_errno() function is present. + # + # vm_fault_to_errno() was added by commit 9a291a7c94281 (mm/hugetlb: + # report -EHWPOISON not -EFAULT when FOLL_HWPOISON is specified) in + # v4.12 (2017-06-02). + # + CODE=" + #include + void conftest_vm_fault_to_errno(void) { + vm_fault_to_errno(); + }" + + compile_check_conftest "$CODE" "NV_VM_FAULT_TO_ERRNO_PRESENT" "" "functions" + ;; + + handle_mm_fault_has_mm_arg) + # + # Determine if handle_mm_fault() has mm argument. + # + # mm argument was removed from handle_mm_fault() by commit + # dcddffd41d3f1d3bdcc1dce3f1cd142779b6d4c1 (07/26/2016) ("mm: do not + # pass mm_struct into handle_mm_fault") in v4.8. + # + # To test if handle_mm_fault() has mm argument, define a function + # with the expected signature and then define the corresponding + # function implementation with the expected signature. Successful + # compilation indicates that handle_mm_fault has the mm argument. + # + CODE=" + #include + #include + + typeof(handle_mm_fault) conftest_handle_mm_fault_has_mm_arg; + int conftest_handle_mm_fault_has_mm_arg(struct mm_struct *mm, + struct vm_area_struct *vma, + unsigned long address, + unsigned int flags) { + return 0; + }" + + compile_check_conftest "$CODE" "NV_HANDLE_MM_FAULT_HAS_MM_ARG" "" "types" + ;; + + handle_mm_fault_has_pt_regs_arg) + # + # Determine if handle_mm_fault() has pt_regs argument. + # + # pt_regs argument was added to handle_mm_fault by commit + # bce617edecada007aee8610fbe2c14d10b8de2f6 (08/12/2020) ("mm: do + # page fault accounting in handle_mm_fault") in v5.9. + # + # To test if handle_mm_fault() has pt_regs argument, define a + # function with the expected signature and then define the + # corresponding function implementation with the expected signature. + # Successful compilation indicates that handle_mm_fault has the + # pt_regs argument. + # + CODE=" + #include + #include + + typeof(handle_mm_fault) conftest_handle_mm_fault_has_pt_regs_arg; + vm_fault_t conftest_handle_mm_fault_has_pt_regs_arg(struct vm_area_struct *vma, + unsigned long address, + unsigned int flags, + struct pt_regs *regs) { + return 0; + }" + + compile_check_conftest "$CODE" "NV_HANDLE_MM_FAULT_HAS_PT_REGS_ARG" "" "types" + ;; + pci_rebar_get_possible_sizes) # # Determine if the pci_rebar_get_possible_sizes() function is present. @@ -5637,6 +5914,22 @@ compile_test() { compile_check_conftest "$CODE" "NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT" "" "functions" ;; + wait_for_random_bytes) + # + # Determine if the wait_for_random_bytes() function is present. + # + # Added by commit e297a783e4156 ("random: add wait_for_random_bytes + # API") in v4.13 + # + CODE=" + #include + int conftest_wait_for_random_bytes(void) { + return wait_for_random_bytes(0); + }" + + compile_check_conftest "$CODE" "NV_WAIT_FOR_RANDOM_BYTES_PRESENT" "" "functions" + ;; + drm_connector_has_override_edid) # # Determine if 'struct drm_connector' has an 'override_edid' member. @@ -5663,9 +5956,9 @@ compile_test() { # # Check if iommu_sva_bind_device() has drvdata parameter. # - # Removed by commit be51b1d6bbff48c7d1943a8ff1e5a55777807f6e - # ("iommu/sva: Refactoring iommu_sva_bind/unbind_device()") - # in v6.2 (2022-10-31) + # drvdata argument was removed by commit + # 942fd5435dccb273f90176b046ae6bbba60cfbd8 ("iommu: Remove + # SVM_FLAG_SUPERVISOR_MODE support") in v6.2 (2022-10-31) # CODE=" #include @@ -5699,6 +5992,66 @@ compile_test() { compile_check_conftest "$CODE" "NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS" "" "types" ;; + drm_driver_has_dumb_destroy) + # + # Determine if the 'drm_driver' structure has a 'dumb_destroy' + # function pointer. + # + # Removed by commit 96a7b60f6ddb2 ("drm: remove dumb_destroy + # callback") in v6.3 linux-next (2023-02-10). + # + CODE=" + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + + #if defined(NV_DRM_DRM_DRV_H_PRESENT) + #include + #endif + + int conftest_drm_driver_has_dumb_destroy(void) { + return offsetof(struct drm_driver, dumb_destroy); + }" + + compile_check_conftest "$CODE" "NV_DRM_DRIVER_HAS_DUMB_DESTROY" "" "types" + ;; + + memory_failure_has_trapno_arg) + # + # Check if memory_failure() has trapno parameter. + # + # trapno argument was removed by commit + # 83b57531c58f4173d1c0d0b2c0bc88c853c32ea5 ("mm/memory_failure: + # Remove unused trapno from memory_failure") in v4.15.0 (2017-7-9) + # + CODE=" + #include + void conftest_memory_failure_has_trapno_arg(unsigned long pfn, + int trapno, + int flags) { + (void) memory_failure(pfn, trapno, flags); + }" + + compile_check_conftest "$CODE" "NV_MEMORY_FAILURE_HAS_TRAPNO_ARG" "" "types" + ;; + + memory_failure_mf_sw_simulated_defined) + # + # Check if memory_failure() flag MF_SW_SIMULATED is defined. + # + # MF_SW_SIMULATED was added by commit + # 67f22ba7750f940bcd7e1b12720896c505c2d63f ("mm/hwpoison: + # fix unpoison_memory()") in v5.19.0-rc2 (2022-6-16) + # + CODE=" + #include + int conftest_memory_failure_mf_sw_simulated_defined(void) { + return MF_SW_SIMULATED; + }" + + compile_check_conftest "$CODE" "NV_MEMORY_FAILURE_MF_SW_SIMULATED_DEFINED" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. # @@ -6000,9 +6353,11 @@ case "$5" in iommu=CONFIG_VFIO_IOMMU_TYPE1 mdev=CONFIG_VFIO_MDEV kvm=CONFIG_KVM_VFIO + vfio_pci_core=CONFIG_VFIO_PCI_CORE VFIO_IOMMU_PRESENT=0 VFIO_MDEV_PRESENT=0 KVM_PRESENT=0 + VFIO_PCI_CORE_PRESENT=0 if [ -n "$VGX_KVM_BUILD" ]; then if (test_configuration_option ${iommu} || test_configuration_option ${iommu}_MODULE); then @@ -6017,32 +6372,50 @@ case "$5" in KVM_PRESENT=1 fi - if [ "$VFIO_IOMMU_PRESENT" != "0" ] && - [ "$VFIO_MDEV_PRESENT" != "0" ] && - [ "$KVM_PRESENT" != "0" ] ; then + if (test_configuration_option ${vfio_pci_core} || test_configuration_option ${vfio_pci_core}_MODULE); then + VFIO_PCI_CORE_PRESENT=1 + fi + + # When this sanity check is run via nvidia-installer, it sets ARCH as aarch64. + # But, when it is run via Kbuild, ARCH is set as arm64 + if [ "$ARCH" = "aarch64" ]; then + ARCH="arm64" + fi + + if [ "$VFIO_IOMMU_PRESENT" != "0" ] && [ "$KVM_PRESENT" != "0" ] ; then + + # On x86_64, vGPU requires MDEV framework to be present. + # On aarch64, vGPU requires vfio-pci-core framework to be present. + if ([ "$ARCH" = "arm64" ] && [ "$VFIO_PCI_CORE_PRESENT" != "0" ]) || + ([ "$ARCH" = "x86_64" ] && [ "$VFIO_MDEV_PRESENT" != "0" ];) then exit 0 - else - echo "Below CONFIG options are missing on the kernel for installing"; - echo "NVIDIA vGPU driver on KVM host"; - if [ "$VFIO_IOMMU_PRESENT" = "0" ]; then - echo "CONFIG_VFIO_IOMMU_TYPE1"; fi + fi - if [ "$VFIO_MDEV_PRESENT" = "0" ]; then - echo "CONFIG_VFIO_MDEV"; - fi + echo "Below CONFIG options are missing on the kernel for installing"; + echo "NVIDIA vGPU driver on KVM host"; + if [ "$VFIO_IOMMU_PRESENT" = "0" ]; then + echo "CONFIG_VFIO_IOMMU_TYPE1"; + fi - if [ "$KVM_PRESENT" = "0" ]; then - echo "CONFIG_KVM"; - fi - echo "Please install the kernel with above CONFIG options set, then"; - echo "try installing again"; - echo ""; + if [ "$ARCH" = "arm64" ] && [ "$VFIO_PCI_CORE_PRESENT" = "0" ]; then + echo "CONFIG_VFIO_PCI_CORE"; + fi - if [ "$VERBOSE" = "full_output" ]; then - echo "*** Failed vGPU on KVM sanity check. Bailing out! ***"; - echo ""; - fi + if [ "$ARCH" = "x86_64" ] && [ "$VFIO_MDEV_PRESENT" = "0" ]; then + echo "CONFIG_VFIO_MDEV"; + fi + + if [ "$KVM_PRESENT" = "0" ]; then + echo "CONFIG_KVM"; + fi + echo "Please install the kernel with above CONFIG options set, then"; + echo "try installing again"; + echo ""; + + if [ "$VERBOSE" = "full_output" ]; then + echo "*** Failed vGPU on KVM sanity check. Bailing out! ***"; + echo ""; fi exit 1 else diff --git a/kernel-open/nvidia-drm/nvidia-drm-crtc.c b/kernel-open/nvidia-drm/nvidia-drm-crtc.c index e9fc3fd818..333387a155 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-crtc.c +++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.c @@ -44,6 +44,8 @@ #if defined(NV_LINUX_NVHOST_H_PRESENT) && defined(CONFIG_TEGRA_GRHOST) #include +#elif defined(NV_LINUX_HOST1X_NEXT_H_PRESENT) +#include #endif #if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) @@ -361,6 +363,21 @@ plane_req_config_update(struct drm_plane *plane, if (nv_drm_plane_state->fd_user_ptr) { req_config->config.syncptParams.postSyncptRequested = true; + } +#elif defined(NV_LINUX_HOST1X_NEXT_H_PRESENT) + if (plane_state->fence != NULL) { + int ret = host1x_fence_extract( + plane_state->fence, + &req_config->config.syncptParams.preSyncptId, + &req_config->config.syncptParams.preSyncptValue); + if (ret != 0) { + return ret; + } + req_config->config.syncptParams.preSyncptSpecified = true; + } + + if (nv_drm_plane_state->fd_user_ptr) { + req_config->config.syncptParams.postSyncptRequested = true; } #else return -1; diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index e48378faa5..1a3542a860 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -1436,7 +1436,9 @@ static void nv_drm_update_drm_driver_features(void) nv_drm_driver.dumb_create = nv_drm_dumb_create; nv_drm_driver.dumb_map_offset = nv_drm_dumb_map_offset; +#if defined(NV_DRM_DRIVER_HAS_DUMB_DESTROY) nv_drm_driver.dumb_destroy = nv_drm_dumb_destroy; +#endif /* NV_DRM_DRIVER_HAS_DUMB_DESTROY */ #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ } diff --git a/kernel-open/nvidia-drm/nvidia-drm-encoder.c b/kernel-open/nvidia-drm/nvidia-drm-encoder.c index 653b432543..b5ef5a2829 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-encoder.c +++ b/kernel-open/nvidia-drm/nvidia-drm-encoder.c @@ -205,7 +205,7 @@ nv_drm_add_encoder(struct drm_device *dev, NvKmsKapiDisplay hDisplay) encoder = nv_drm_encoder_new(dev, displayInfo->handle, connectorInfo->signalFormat, - get_crtc_mask(dev, connectorInfo->headMask)); + get_crtc_mask(dev, displayInfo->headMask)); if (IS_ERR(encoder)) { ret = PTR_ERR(encoder); diff --git a/kernel-open/nvidia-drm/nvidia-drm-fb.c b/kernel-open/nvidia-drm/nvidia-drm-fb.c index d119e7c92d..2747123ff5 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-fb.c +++ b/kernel-open/nvidia-drm/nvidia-drm-fb.c @@ -150,6 +150,14 @@ static int nv_drm_framebuffer_init(struct drm_device *dev, for (i = 0; i < ARRAY_SIZE(nv_fb->nv_gem); i++) { if (nv_fb->nv_gem[i] != NULL) { + if (!nvKms->isMemoryValidForDisplay(nv_dev->pDevice, + nv_fb->nv_gem[i]->pMemory)) { + NV_DRM_DEV_LOG_INFO( + nv_dev, + "Framebuffer memory not appropriate for scanout"); + goto fail; + } + params.planes[i].memory = nv_fb->nv_gem[i]->pMemory; params.planes[i].offset = nv_fb->base.offsets[i]; params.planes[i].pitch = nv_fb->base.pitches[i]; @@ -164,6 +172,17 @@ static int nv_drm_framebuffer_init(struct drm_device *dev, params.layout = (modifier & 0x10) ? NvKmsSurfaceMemoryLayoutBlockLinear : NvKmsSurfaceMemoryLayoutPitch; + + // See definition of DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D, we are testing + // 'c', the lossless compression field of the modifier + if (params.layout == NvKmsSurfaceMemoryLayoutBlockLinear && + (modifier >> 23) & 0x7) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Cannot create FB from compressible surface allocation"); + goto fail; + } + params.log2GobsPerBlockY = modifier & 0xf; } else { params.explicit_layout = false; @@ -174,11 +193,14 @@ static int nv_drm_framebuffer_init(struct drm_device *dev, nv_fb->pSurface = nvKms->createSurface(nv_dev->pDevice, ¶ms); if (nv_fb->pSurface == NULL) { NV_DRM_DEV_DEBUG_DRIVER(nv_dev, "Failed to create NvKmsKapiSurface"); - drm_framebuffer_cleanup(&nv_fb->base); - return -EINVAL; + goto fail; } return 0; + +fail: + drm_framebuffer_cleanup(&nv_fb->base); + return -EINVAL; } struct drm_framebuffer *nv_drm_internal_framebuffer_create( diff --git a/kernel-open/nvidia-drm/nvidia-drm-fence.c b/kernel-open/nvidia-drm/nvidia-drm-fence.c index 71d7275a2a..97dfff8d74 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-fence.c +++ b/kernel-open/nvidia-drm/nvidia-drm-fence.c @@ -516,6 +516,7 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, struct nv_drm_gem_fence_context *nv_gem_fence_context; nv_dma_fence_t *fence; + nv_dma_resv_t *resv; nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle); @@ -566,18 +567,20 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, goto fence_context_create_fence_failed; } - nv_dma_resv_lock(&nv_gem->resv, NULL); + resv = nv_drm_gem_res_obj(nv_gem); - ret = nv_dma_resv_reserve_fences(&nv_gem->resv, 1, false); + nv_dma_resv_lock(resv, NULL); + + ret = nv_dma_resv_reserve_fences(resv, 1, false); if (ret == 0) { - nv_dma_resv_add_excl_fence(&nv_gem->resv, fence); + nv_dma_resv_add_excl_fence(resv, fence); } else { NV_DRM_DEV_LOG_ERR( nv_dev, "Failed to reserve fence. Error code: %d", ret); } - nv_dma_resv_unlock(&nv_gem->resv); + nv_dma_resv_unlock(resv); /* dma_resv_add_excl_fence takes its own reference to the fence. */ nv_dma_fence_put(fence); diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c index fdc6de69b5..5d04713ce7 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c @@ -131,11 +131,11 @@ static struct drm_gem_object *__nv_drm_gem_nvkms_prime_dup( const struct nv_drm_gem_object *nv_gem_src); static int __nv_drm_gem_nvkms_map( - struct nv_drm_device *nv_dev, - struct NvKmsKapiMemory *pMemory, - struct nv_drm_gem_nvkms_memory *nv_nvkms_memory, - uint64_t size) + struct nv_drm_gem_nvkms_memory *nv_nvkms_memory) { + struct nv_drm_device *nv_dev = nv_nvkms_memory->base.nv_dev; + struct NvKmsKapiMemory *pMemory = nv_nvkms_memory->base.pMemory; + if (!nv_dev->hasVideoMemory) { return 0; } @@ -153,7 +153,7 @@ static int __nv_drm_gem_nvkms_map( nv_nvkms_memory->pWriteCombinedIORemapAddress = ioremap_wc( (uintptr_t)nv_nvkms_memory->pPhysicalAddress, - size); + nv_nvkms_memory->base.base.size); if (!nv_nvkms_memory->pWriteCombinedIORemapAddress) { NV_DRM_DEV_LOG_INFO( @@ -167,6 +167,22 @@ static int __nv_drm_gem_nvkms_map( return 0; } +static void *__nv_drm_gem_nvkms_prime_vmap( + struct nv_drm_gem_object *nv_gem) +{ + struct nv_drm_gem_nvkms_memory *nv_nvkms_memory = + to_nv_nvkms_memory(nv_gem); + + if (!nv_nvkms_memory->physically_mapped) { + int ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory); + if (ret) { + return ERR_PTR(ret); + } + } + + return nv_nvkms_memory->pWriteCombinedIORemapAddress; +} + static int __nv_drm_gem_map_nvkms_memory_offset( struct nv_drm_device *nv_dev, struct nv_drm_gem_object *nv_gem, @@ -176,10 +192,7 @@ static int __nv_drm_gem_map_nvkms_memory_offset( to_nv_nvkms_memory(nv_gem); if (!nv_nvkms_memory->physically_mapped) { - int ret = __nv_drm_gem_nvkms_map(nv_dev, - nv_nvkms_memory->base.pMemory, - nv_nvkms_memory, - nv_nvkms_memory->base.base.size); + int ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory); if (ret) { return ret; } @@ -214,6 +227,7 @@ static struct sg_table *__nv_drm_gem_nvkms_memory_prime_get_sg_table( const struct nv_drm_gem_object_funcs nv_gem_nvkms_memory_ops = { .free = __nv_drm_gem_nvkms_memory_free, .prime_dup = __nv_drm_gem_nvkms_prime_dup, + .prime_vmap = __nv_drm_gem_nvkms_prime_vmap, .mmap = __nv_drm_gem_nvkms_mmap, .handle_vma_fault = __nv_drm_gem_nvkms_handle_vma_fault, .create_mmap_offset = __nv_drm_gem_map_nvkms_memory_offset, @@ -314,7 +328,7 @@ int nv_drm_dumb_create( * to use dumb buffers for software rendering, so they're not much use * without a CPU mapping. */ - ret = __nv_drm_gem_nvkms_map(nv_dev, pMemory, nv_nvkms_memory, args->size); + ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory); if (ret) { nv_drm_gem_object_unreference_unlocked(&nv_nvkms_memory->base); goto fail; @@ -583,11 +597,13 @@ int nv_drm_dumb_map_offset(struct drm_file *file, return ret; } +#if defined(NV_DRM_DRIVER_HAS_DUMB_DESTROY) int nv_drm_dumb_destroy(struct drm_file *file, struct drm_device *dev, uint32_t handle) { return drm_gem_handle_delete(file, handle); } +#endif /* NV_DRM_DRIVER_HAS_DUMB_DESTROY */ #endif diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h index 7ecbb94d68..ea218a058d 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h @@ -97,9 +97,11 @@ int nv_drm_dumb_map_offset(struct drm_file *file, struct drm_device *dev, uint32_t handle, uint64_t *offset); +#if defined(NV_DRM_DRIVER_HAS_DUMB_DESTROY) int nv_drm_dumb_destroy(struct drm_file *file, struct drm_device *dev, uint32_t handle); +#endif /* NV_DRM_DRIVER_HAS_DUMB_DESTROY */ struct drm_gem_object *nv_drm_gem_nvkms_prime_import( struct drm_device *dev, diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem.c b/kernel-open/nvidia-drm/nvidia-drm-gem.c index d15653c12d..36d2675c01 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem.c @@ -81,10 +81,13 @@ typedef struct dma_buf_map nv_sysio_map_t; static int nv_drm_gem_vmap(struct drm_gem_object *gem, nv_sysio_map_t *map) { - map->vaddr = nv_drm_gem_prime_vmap(gem); - if (map->vaddr == NULL) { + void *vaddr = nv_drm_gem_prime_vmap(gem); + if (vaddr == NULL) { return -ENOMEM; + } else if (IS_ERR(vaddr)) { + return PTR_ERR(vaddr); } + map->vaddr = vaddr; map->is_iomem = true; return 0; } @@ -132,13 +135,8 @@ void nv_drm_gem_object_init(struct nv_drm_device *nv_dev, /* Initialize the gem object */ -#if defined(NV_DRM_FENCE_AVAILABLE) +#if defined(NV_DRM_FENCE_AVAILABLE) && !defined(NV_DRM_GEM_OBJECT_HAS_RESV) nv_dma_resv_init(&nv_gem->resv); - -#if defined(NV_DRM_GEM_OBJECT_HAS_RESV) - nv_gem->base.resv = &nv_gem->resv; -#endif - #endif #if !defined(NV_DRM_DRIVER_HAS_GEM_FREE_OBJECT) @@ -212,8 +210,7 @@ void nv_drm_gem_prime_vunmap(struct drm_gem_object *gem, void *address) nv_dma_resv_t* nv_drm_gem_prime_res_obj(struct drm_gem_object *obj) { struct nv_drm_gem_object *nv_gem = to_nv_gem_object(obj); - - return &nv_gem->resv; + return nv_drm_gem_res_obj(nv_gem); } #endif diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem.h b/kernel-open/nvidia-drm/nvidia-drm-gem.h index a27c2e996a..873ff3234a 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem.h +++ b/kernel-open/nvidia-drm/nvidia-drm-gem.h @@ -45,6 +45,8 @@ #include "nvidia-dma-resv-helper.h" #endif +#include "linux/dma-buf.h" + struct nv_drm_gem_object; struct nv_drm_gem_object_funcs { @@ -71,7 +73,7 @@ struct nv_drm_gem_object { struct NvKmsKapiMemory *pMemory; -#if defined(NV_DRM_FENCE_AVAILABLE) +#if defined(NV_DRM_FENCE_AVAILABLE) && !defined(NV_DRM_GEM_OBJECT_HAS_RESV) nv_dma_resv_t resv; #endif }; @@ -177,6 +179,15 @@ static inline int nv_drm_gem_handle_create(struct drm_file *filp, return drm_gem_handle_create(filp, &nv_gem->base, handle); } +static inline nv_dma_resv_t *nv_drm_gem_res_obj(struct nv_drm_gem_object *nv_gem) +{ +#if defined(NV_DRM_GEM_OBJECT_HAS_RESV) + return nv_gem->base.resv; +#else + return nv_gem->base.dma_buf ? nv_gem->base.dma_buf->resv : &nv_gem->resv; +#endif +} + void nv_drm_gem_object_init(struct nv_drm_device *nv_dev, struct nv_drm_gem_object *nv_gem, const struct nv_drm_gem_object_funcs * const ops, diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index d386793a60..1ef7e7b8b6 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -130,3 +130,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_modeset_lock_all_end NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy diff --git a/kernel-open/nvidia-modeset/nv-kthread-q.c b/kernel-open/nvidia-modeset/nv-kthread-q.c index 31a54cc05b..2098f27a70 100644 --- a/kernel-open/nvidia-modeset/nv-kthread-q.c +++ b/kernel-open/nvidia-modeset/nv-kthread-q.c @@ -301,7 +301,7 @@ static void _q_flush_function(void *args) static void _raw_q_flush(nv_kthread_q_t *q) { nv_kthread_q_item_t q_item; - DECLARE_COMPLETION(completion); + DECLARE_COMPLETION_ONSTACK(completion); nv_kthread_q_item_init(&q_item, _q_flush_function, &completion); diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index 5744a167a4..7f876432b2 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -86,15 +86,6 @@ module_param_named(config_file, nvkms_conf, charp, 0400); static atomic_t nvkms_alloc_called_count; -static bool force_api_to_hw_head_identity_mapping = false; -module_param_named(force_api_to_hw_head_identity_mapping, - force_api_to_hw_head_identity_mapping, bool, 0400); - -NvBool nvkms_force_api_to_hw_head_identity_mappings(void) -{ - return force_api_to_hw_head_identity_mapping; -} - NvBool nvkms_output_rounding_fix(void) { return output_rounding_fix; diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h index bedb7e0751..9e519779a1 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h +++ b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h @@ -40,11 +40,30 @@ #include "nv_stdarg.h" enum NvKmsSyncPtOp { + /* + * Call into Tegra's kernel nvhost driver, and allocate a syncpoint that can + * be exclusively used by the caller. Internally, this operation will call + * get() to set the initial refcount of the syncpoint to 1. + */ NVKMS_SYNCPT_OP_ALLOC, - NVKMS_SYNCPT_OP_GET, + /* + * Decrease the refcount of an already allocated syncpoint. Once the + * refcount drops to 0, the syncpoint will be returned to the free pool that + * nvhost manages, so PUT can also be used to balance out an ALLOC. + */ NVKMS_SYNCPT_OP_PUT, + /* + * Extract syncpt id and thresh from the sync-file file descriptor + */ NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, + /* + * Create dma-fence from syncpt id and thresh value and create sync_file + * file descriptor for the dma-fence handle created. + */ NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, + /* + * read syncpt minimum value of given syncpt + */ NVKMS_SYNCPT_OP_READ_MINVAL, }; @@ -77,7 +96,6 @@ typedef struct { } read_minval; } NvKmsSyncPtOpParams; -NvBool nvkms_force_api_to_hw_head_identity_mappings(void); NvBool nvkms_output_rounding_fix(void); void nvkms_call_rm (void *ops); diff --git a/kernel-open/nvidia-peermem/nv-p2p.h b/kernel-open/nvidia-peermem/nv-p2p.h index a9469bdbb2..e19b38a8f7 100644 --- a/kernel-open/nvidia-peermem/nv-p2p.h +++ b/kernel-open/nvidia-peermem/nv-p2p.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -94,11 +94,10 @@ struct nvidia_p2p_params { } nvidia_p2p_params_t; /* - * Capability flag for users to detect + * Macro for users to detect * driver support for persistent pages. */ -extern int nvidia_p2p_cap_persistent_pages; -#define NVIDIA_P2P_CAP_PERSISTENT_PAGES +#define NVIDIA_P2P_CAP_GET_PAGES_PERSISTENT_API /* * This API is not supported. @@ -173,11 +172,6 @@ struct nvidia_p2p_page_table { * A pointer to the function to be invoked when the pages * underlying the virtual address range are freed * implicitly. - * If NULL, persistent pages will be returned. - * This means the pages underlying the range of GPU virtual memory - * will persist until explicitly freed by nvidia_p2p_put_pages(). - * Persistent GPU memory mappings are not supported on PowerPC, - * MIG-enabled devices and vGPU. * @param[in] data * A non-NULL opaque pointer to private data to be passed to the * callback function. @@ -190,12 +184,48 @@ struct nvidia_p2p_page_table { * insufficient resources were available to complete the operation. * -EIO if an unknown error occurred. */ -int nvidia_p2p_get_pages(uint64_t p2p_token, uint32_t va_space, - uint64_t virtual_address, +int nvidia_p2p_get_pages( uint64_t p2p_token, uint32_t va_space, + uint64_t virtual_address, uint64_t length, + struct nvidia_p2p_page_table **page_table, + void (*free_callback)(void *data), void *data); + +/* + * @brief + * Pin and make the pages underlying a range of GPU virtual memory + * accessible to a third-party device. The pages will persist until + * explicitly freed by nvidia_p2p_put_pages_persistent(). + * + * Persistent GPU memory mappings are not supported on PowerPC, + * MIG-enabled devices and vGPU. + * + * This API only supports pinned, GPU-resident memory, such as that provided + * by cudaMalloc(). + * + * This API may sleep. + * + * @param[in] virtual_address + * The start address in the specified virtual address space. + * Address must be aligned to the 64KB boundary. + * @param[in] length + * The length of the requested P2P mapping. + * Length must be a multiple of 64KB. + * @param[out] page_table + * A pointer to an array of structures with P2P PTEs. + * @param[in] flags + * Must be set to zero for now. + * + * @return + * 0 upon successful completion. + * -EINVAL if an invalid argument was supplied. + * -ENOTSUPP if the requested operation is not supported. + * -ENOMEM if the driver failed to allocate memory or if + * insufficient resources were available to complete the operation. + * -EIO if an unknown error occurred. + */ +int nvidia_p2p_get_pages_persistent(uint64_t virtual_address, uint64_t length, struct nvidia_p2p_page_table **page_table, - void (*free_callback)(void *data), - void *data); + uint32_t flags); #define NVIDIA_P2P_DMA_MAPPING_VERSION 0x00020003 @@ -268,6 +298,8 @@ int nvidia_p2p_dma_unmap_pages(struct pci_dev *peer, * Release a set of pages previously made accessible to * a third-party device. * + * This API may sleep. + * * @param[in] p2p_token * A token that uniquely identifies the P2P mapping. * @param[in] va_space @@ -282,10 +314,33 @@ int nvidia_p2p_dma_unmap_pages(struct pci_dev *peer, * -EINVAL if an invalid argument was supplied. * -EIO if an unknown error occurred. */ -int nvidia_p2p_put_pages(uint64_t p2p_token, uint32_t va_space, - uint64_t virtual_address, +int nvidia_p2p_put_pages(uint64_t p2p_token, + uint32_t va_space, uint64_t virtual_address, struct nvidia_p2p_page_table *page_table); +/* + * @brief + * Release a set of persistent pages previously made accessible to + * a third-party device. + * + * This API may sleep. + * + * @param[in] virtual_address + * The start address in the specified virtual address space. + * @param[in] page_table + * A pointer to the array of structures with P2P PTEs. + * @param[in] flags + * Must be set to zero for now. + * + * @return + * 0 upon successful completion. + * -EINVAL if an invalid argument was supplied. + * -EIO if an unknown error occurred. + */ +int nvidia_p2p_put_pages_persistent(uint64_t virtual_address, + struct nvidia_p2p_page_table *page_table, + uint32_t flags); + /* * @brief * Free a third-party P2P page table. (This function is a no-op.) diff --git a/kernel-open/nvidia-peermem/nvidia-peermem.c b/kernel-open/nvidia-peermem/nvidia-peermem.c index 699d1cf176..a20f7d1dd8 100644 --- a/kernel-open/nvidia-peermem/nvidia-peermem.c +++ b/kernel-open/nvidia-peermem/nvidia-peermem.c @@ -284,8 +284,9 @@ static int nv_dma_unmap(struct sg_table *sg_head, void *context, return 0; } - -static void nv_mem_put_pages(struct sg_table *sg_head, void *context) +static void nv_mem_put_pages_common(int nc, + struct sg_table *sg_head, + void *context) { int ret = 0; struct nv_mem_context *nv_mem_context = @@ -302,8 +303,13 @@ static void nv_mem_put_pages(struct sg_table *sg_head, void *context) if (nv_mem_context->callback_task == current) return; - ret = nvidia_p2p_put_pages(0, 0, nv_mem_context->page_virt_start, - nv_mem_context->page_table); + if (nc) { + ret = nvidia_p2p_put_pages_persistent(nv_mem_context->page_virt_start, + nv_mem_context->page_table, 0); + } else { + ret = nvidia_p2p_put_pages(0, 0, nv_mem_context->page_virt_start, + nv_mem_context->page_table); + } #ifdef _DEBUG_ONLY_ /* Here we expect an error in real life cases that should be ignored - not printed. @@ -318,6 +324,16 @@ static void nv_mem_put_pages(struct sg_table *sg_head, void *context) return; } +static void nv_mem_put_pages(struct sg_table *sg_head, void *context) +{ + nv_mem_put_pages_common(0, sg_head, context); +} + +static void nv_mem_put_pages_nc(struct sg_table *sg_head, void *context) +{ + nv_mem_put_pages_common(1, sg_head, context); +} + static void nv_mem_release(void *context) { struct nv_mem_context *nv_mem_context = @@ -396,8 +412,9 @@ static int nv_mem_get_pages_nc(unsigned long addr, nv_mem_context->core_context = core_context; nv_mem_context->page_size = GPU_PAGE_SIZE; - ret = nvidia_p2p_get_pages(0, 0, nv_mem_context->page_virt_start, nv_mem_context->mapped_size, - &nv_mem_context->page_table, NULL, NULL); + ret = nvidia_p2p_get_pages_persistent(nv_mem_context->page_virt_start, + nv_mem_context->mapped_size, + &nv_mem_context->page_table, 0); if (ret < 0) { peer_err("error %d while calling nvidia_p2p_get_pages() with NULL callback\n", ret); return ret; @@ -407,13 +424,13 @@ static int nv_mem_get_pages_nc(unsigned long addr, } static struct peer_memory_client nv_mem_client_nc = { - .acquire = nv_mem_acquire, - .get_pages = nv_mem_get_pages_nc, - .dma_map = nv_dma_map, - .dma_unmap = nv_dma_unmap, - .put_pages = nv_mem_put_pages, - .get_page_size = nv_mem_get_page_size, - .release = nv_mem_release, + .acquire = nv_mem_acquire, + .get_pages = nv_mem_get_pages_nc, + .dma_map = nv_dma_map, + .dma_unmap = nv_dma_unmap, + .put_pages = nv_mem_put_pages_nc, + .get_page_size = nv_mem_get_page_size, + .release = nv_mem_release, }; #endif /* NV_MLNX_IB_PEER_MEM_SYMBOLS_PRESENT */ @@ -477,9 +494,6 @@ static int __init nv_mem_client_init(void) } // The nc client enables support for persistent pages. - // Thanks to this check, nvidia-peermem requires the new symbol from nvidia.ko, which - // prevents users to unintentionally load this module with unsupported nvidia.ko. - BUG_ON(!nvidia_p2p_cap_persistent_pages); strcpy(nv_mem_client_nc.name, DRV_NAME "_nc"); strcpy(nv_mem_client_nc.version, DRV_VERSION); reg_handle_nc = ib_register_peer_memory_client(&nv_mem_client_nc, NULL); diff --git a/kernel-open/nvidia-uvm/cla06fsubch.h b/kernel-open/nvidia-uvm/cla06fsubch.h index 930a0d3436..330a681740 100644 --- a/kernel-open/nvidia-uvm/cla06fsubch.h +++ b/kernel-open/nvidia-uvm/cla06fsubch.h @@ -1,29 +1,33 @@ -/******************************************************************************* - Copyright (c) 2013 NVIDIA Corporation +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -#ifndef __cla06fsubch_h__ -#define __cla06fsubch_h__ +#ifndef _cla06fsubch_h_ +#define _cla06fsubch_h_ +#define NVA06F_SUBCHANNEL_2D 3 +#define NVA06F_SUBCHANNEL_3D 0 +#define NVA06F_SUBCHANNEL_COMPUTE 1 #define NVA06F_SUBCHANNEL_COPY_ENGINE 4 +#define NVA06F_SUBCHANNEL_I2M 2 -#endif // {__cla06fsubch_h__} +#endif // _cla06fsubch_h_ diff --git a/kernel-open/nvidia-uvm/cla16f.h b/kernel-open/nvidia-uvm/cla16f.h index 742baa96a1..66e7594b56 100644 --- a/kernel-open/nvidia-uvm/cla16f.h +++ b/kernel-open/nvidia-uvm/cla16f.h @@ -1,25 +1,25 @@ -/******************************************************************************* - Copyright (c) 2021-2022 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _cla16f_h_ #define _cla16f_h_ @@ -30,9 +30,48 @@ extern "C" { #include "nvtypes.h" -#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F) - +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F) + +/* pio method data structure */ +typedef volatile struct _cla16f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA16FTypedef, KEPLER_ChannelGPFifoB; +#define NVA16F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla16f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA16FControl, KeplerBControlGPFifo; +/* fields and values */ +#define NVA16F_NUMBER_OF_SUBCHANNELS (8) #define NVA16F_SET_OBJECT (0x00000000) +#define NVA16F_SET_OBJECT_NVCLASS 15:0 +#define NVA16F_SET_OBJECT_ENGINE 20:16 +#define NVA16F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA16F_ILLEGAL (0x00000004) +#define NVA16F_ILLEGAL_HANDLE 31:0 #define NVA16F_NOP (0x00000008) #define NVA16F_NOP_HANDLE 31:0 #define NVA16F_SEMAPHOREA (0x00000010) @@ -100,6 +139,12 @@ extern "C" { #define NVA16F_SET_REFERENCE_COUNT 31:0 #define NVA16F_WFI (0x00000078) #define NVA16F_WFI_HANDLE 31:0 +#define NVA16F_CRC_CHECK (0x0000007c) +#define NVA16F_CRC_CHECK_VALUE 31:0 +#define NVA16F_YIELD (0x00000080) +#define NVA16F_YIELD_OP 1:0 +#define NVA16F_YIELD_OP_NOP 0x00000000 + /* GPFIFO entry format */ #define NVA16F_GP_ENTRY__SIZE 8 @@ -126,13 +171,28 @@ extern "C" { #define NVA16F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 /* dma method formats */ +#define NVA16F_DMA_METHOD_ADDRESS_OLD 12:2 #define NVA16F_DMA_METHOD_ADDRESS 11:0 +#define NVA16F_DMA_SUBDEVICE_MASK 15:4 #define NVA16F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA16F_DMA_TERT_OP 17:16 +#define NVA16F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA16F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA16F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA16F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA16F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA16F_DMA_METHOD_COUNT_OLD 28:18 #define NVA16F_DMA_METHOD_COUNT 28:16 +#define NVA16F_DMA_IMMD_DATA 28:16 #define NVA16F_DMA_SEC_OP 31:29 +#define NVA16F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) #define NVA16F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA16F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) #define NVA16F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) - +#define NVA16F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA16F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA16F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA16F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) /* dma incrementing method format */ #define NVA16F_DMA_INCR_ADDRESS 11:0 #define NVA16F_DMA_INCR_SUBCHANNEL 15:13 @@ -140,7 +200,6 @@ extern "C" { #define NVA16F_DMA_INCR_OPCODE 31:29 #define NVA16F_DMA_INCR_OPCODE_VALUE (0x00000001) #define NVA16F_DMA_INCR_DATA 31:0 - /* dma non-incrementing method format */ #define NVA16F_DMA_NONINCR_ADDRESS 11:0 #define NVA16F_DMA_NONINCR_SUBCHANNEL 15:13 @@ -148,13 +207,45 @@ extern "C" { #define NVA16F_DMA_NONINCR_OPCODE 31:29 #define NVA16F_DMA_NONINCR_OPCODE_VALUE (0x00000003) #define NVA16F_DMA_NONINCR_DATA 31:0 - +/* dma increment-once method format */ +#define NVA16F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA16F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA16F_DMA_ONEINCR_COUNT 28:16 +#define NVA16F_DMA_ONEINCR_OPCODE 31:29 +#define NVA16F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA16F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA16F_DMA_NOP (0x00000000) /* dma immediate-data format */ #define NVA16F_DMA_IMMD_ADDRESS 11:0 #define NVA16F_DMA_IMMD_SUBCHANNEL 15:13 #define NVA16F_DMA_IMMD_DATA 28:16 #define NVA16F_DMA_IMMD_OPCODE 31:29 #define NVA16F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA16F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA16F_DMA_ENDSEG_OPCODE 31:29 +#define NVA16F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA16F_DMA_ADDRESS 12:2 +#define NVA16F_DMA_SUBCH 15:13 +#define NVA16F_DMA_OPCODE3 17:16 +#define NVA16F_DMA_OPCODE3_NONE (0x00000000) +#define NVA16F_DMA_COUNT 28:18 +#define NVA16F_DMA_OPCODE 31:29 +#define NVA16F_DMA_OPCODE_METHOD (0x00000000) +#define NVA16F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA16F_DMA_DATA 31:0 #ifdef __cplusplus }; /* extern "C" */ diff --git a/kernel-open/nvidia-uvm/clb069.h b/kernel-open/nvidia-uvm/clb069.h index 9e1f3a2675..94140dd24d 100644 --- a/kernel-open/nvidia-uvm/clb069.h +++ b/kernel-open/nvidia-uvm/clb069.h @@ -1,24 +1,26 @@ -/******************************************************************************* - Copyright (c) 2014 NVidia Corporation +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ #ifndef _clb069_h_ #define _clb069_h_ diff --git a/kernel-open/nvidia-uvm/clb06f.h b/kernel-open/nvidia-uvm/clb06f.h index 67f521bb53..b2b51e0459 100644 --- a/kernel-open/nvidia-uvm/clb06f.h +++ b/kernel-open/nvidia-uvm/clb06f.h @@ -1,28 +1,28 @@ -/******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -#ifndef _clB06f_h_ -#define _clB06f_h_ +#ifndef _clb06f_h_ +#define _clb06f_h_ #ifdef __cplusplus extern "C" { @@ -30,10 +30,46 @@ extern "C" { #include "nvtypes.h" +/* class MAXWELL_CHANNEL_GPFIFO */ +/* + * Documentation for MAXWELL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ #define MAXWELL_CHANNEL_GPFIFO_A (0x0000B06F) -/* class MAXWELL_CHANNEL_GPFIFO */ +#define NVB06F_TYPEDEF MAXWELL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct _clb06f_tag0 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvb06FControl, MaxwellAControlGPFifo; + +/* fields and values */ +#define NVB06F_NUMBER_OF_SUBCHANNELS (8) #define NVB06F_SET_OBJECT (0x00000000) +#define NVB06F_SET_OBJECT_NVCLASS 15:0 +#define NVB06F_SET_OBJECT_ENGINE 20:16 +#define NVB06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVB06F_ILLEGAL (0x00000004) +#define NVB06F_ILLEGAL_HANDLE 31:0 #define NVB06F_NOP (0x00000008) #define NVB06F_NOP_HANDLE 31:0 #define NVB06F_SEMAPHOREA (0x00000010) @@ -47,6 +83,8 @@ extern "C" { #define NVB06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 #define NVB06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 #define NVB06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVB06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVB06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 @@ -56,8 +94,22 @@ extern "C" { #define NVB06F_SEMAPHORED_RELEASE_SIZE 24:24 #define NVB06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 #define NVB06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 - +#define NVB06F_SEMAPHORED_REDUCTION 30:27 +#define NVB06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVB06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVB06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVB06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVB06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVB06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVB06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVB06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVB06F_SEMAPHORED_FORMAT 31:31 +#define NVB06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVB06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 #define NVB06F_NON_STALL_INTERRUPT (0x00000020) +#define NVB06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVB06F_FB_FLUSH (0x00000024) +#define NVB06F_FB_FLUSH_HANDLE 31:0 // NOTE - MEM_OP_A and MEM_OP_B have been removed for gm20x to make room for // possible future MEM_OP features. MEM_OP_C/D have identical functionality // to the previous MEM_OP_A/B methods. @@ -84,10 +136,27 @@ extern "C" { #define NVB06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f #define NVB06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 #define NVB06F_MEM_OP_D_TLB_INVALIDATE_ADDR_HI 7:0 +#define NVB06F_SET_REFERENCE (0x00000050) +#define NVB06F_SET_REFERENCE_COUNT 31:0 #define NVB06F_WFI (0x00000078) +#define NVB06F_WFI_SCOPE 0:0 +#define NVB06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 +#define NVB06F_WFI_SCOPE_ALL 0x00000001 +#define NVB06F_CRC_CHECK (0x0000007c) +#define NVB06F_CRC_CHECK_VALUE 31:0 +#define NVB06F_YIELD (0x00000080) +#define NVB06F_YIELD_OP 1:0 +#define NVB06F_YIELD_OP_NOP 0x00000000 +#define NVB06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVB06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVB06F_YIELD_OP_TSG 0x00000003 + /* GPFIFO entry format */ #define NVB06F_GP_ENTRY__SIZE 8 +#define NVB06F_GP_ENTRY0_FETCH 0:0 +#define NVB06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVB06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 #define NVB06F_GP_ENTRY0_GET 31:2 #define NVB06F_GP_ENTRY0_OPERAND 31:0 #define NVB06F_GP_ENTRY1_GET_HI 7:0 @@ -98,11 +167,38 @@ extern "C" { #define NVB06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 #define NVB06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 #define NVB06F_GP_ENTRY1_LENGTH 30:10 +#define NVB06F_GP_ENTRY1_SYNC 31:31 +#define NVB06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVB06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE 7:0 +#define NVB06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVB06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVB06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVB06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 /* dma method formats */ +#define NVB06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVB06F_DMA_METHOD_ADDRESS 11:0 +#define NVB06F_DMA_SUBDEVICE_MASK 15:4 +#define NVB06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVB06F_DMA_TERT_OP 17:16 +#define NVB06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVB06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVB06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVB06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVB06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVB06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVB06F_DMA_METHOD_COUNT 28:16 +#define NVB06F_DMA_IMMD_DATA 28:16 #define NVB06F_DMA_SEC_OP 31:29 +#define NVB06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) #define NVB06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVB06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) #define NVB06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVB06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVB06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVB06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVB06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) /* dma incrementing method format */ #define NVB06F_DMA_INCR_ADDRESS 11:0 #define NVB06F_DMA_INCR_SUBCHANNEL 15:13 @@ -132,9 +228,33 @@ extern "C" { #define NVB06F_DMA_IMMD_DATA 28:16 #define NVB06F_DMA_IMMD_OPCODE 31:29 #define NVB06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVB06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVB06F_DMA_ENDSEG_OPCODE 31:29 +#define NVB06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVB06F_DMA_ADDRESS 12:2 +#define NVB06F_DMA_SUBCH 15:13 +#define NVB06F_DMA_OPCODE3 17:16 +#define NVB06F_DMA_OPCODE3_NONE (0x00000000) +#define NVB06F_DMA_COUNT 28:18 +#define NVB06F_DMA_OPCODE 31:29 +#define NVB06F_DMA_OPCODE_METHOD (0x00000000) +#define NVB06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVB06F_DMA_DATA 31:0 #ifdef __cplusplus }; /* extern "C" */ #endif -#endif /* _clB06F_h_ */ +#endif /* _clb06f_h_ */ diff --git a/kernel-open/nvidia-uvm/clb0b5.h b/kernel-open/nvidia-uvm/clb0b5.h index 26ba851036..63fe69577b 100644 --- a/kernel-open/nvidia-uvm/clb0b5.h +++ b/kernel-open/nvidia-uvm/clb0b5.h @@ -1,19 +1,19 @@ /******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER @@ -32,6 +32,10 @@ extern "C" { #define MAXWELL_DMA_COPY_A (0x0000B0B5) +#define NVB0B5_NOP (0x00000100) +#define NVB0B5_NOP_PARAMETER 31:0 +#define NVB0B5_PM_TRIGGER (0x00000140) +#define NVB0B5_PM_TRIGGER_V 31:0 #define NVB0B5_SET_SEMAPHORE_A (0x00000240) #define NVB0B5_SET_SEMAPHORE_A_UPPER 7:0 #define NVB0B5_SET_SEMAPHORE_B (0x00000244) @@ -183,9 +187,75 @@ extern "C" { #define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) #define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) #define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) - +#define NVB0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_DST_WIDTH (0x00000710) +#define NVB0B5_SET_DST_WIDTH_V 31:0 +#define NVB0B5_SET_DST_HEIGHT (0x00000714) +#define NVB0B5_SET_DST_HEIGHT_V 31:0 +#define NVB0B5_SET_DST_DEPTH (0x00000718) +#define NVB0B5_SET_DST_DEPTH_V 31:0 +#define NVB0B5_SET_DST_LAYER (0x0000071C) +#define NVB0B5_SET_DST_LAYER_V 31:0 +#define NVB0B5_SET_DST_ORIGIN (0x00000720) +#define NVB0B5_SET_DST_ORIGIN_X 15:0 +#define NVB0B5_SET_DST_ORIGIN_Y 31:16 +#define NVB0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_SRC_WIDTH (0x0000072C) +#define NVB0B5_SET_SRC_WIDTH_V 31:0 +#define NVB0B5_SET_SRC_HEIGHT (0x00000730) +#define NVB0B5_SET_SRC_HEIGHT_V 31:0 +#define NVB0B5_SET_SRC_DEPTH (0x00000734) +#define NVB0B5_SET_SRC_DEPTH_V 31:0 +#define NVB0B5_SET_SRC_LAYER (0x00000738) +#define NVB0B5_SET_SRC_LAYER_V 31:0 +#define NVB0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVB0B5_SET_SRC_ORIGIN_X 15:0 +#define NVB0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVB0B5_PM_TRIGGER_END (0x00001114) +#define NVB0B5_PM_TRIGGER_END_V 31:0 #ifdef __cplusplus }; /* extern "C" */ #endif #endif // _clb0b5_h + diff --git a/kernel-open/nvidia-uvm/clc06f.h b/kernel-open/nvidia-uvm/clc06f.h index 285d041b50..d8b86072b9 100644 --- a/kernel-open/nvidia-uvm/clc06f.h +++ b/kernel-open/nvidia-uvm/clc06f.h @@ -1,25 +1,25 @@ -/******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _clc06f_h_ #define _clc06f_h_ @@ -30,10 +30,47 @@ extern "C" { #include "nvtypes.h" +/* class PASCAL_CHANNEL_GPFIFO */ +/* + * Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + * Note there is no .mfs file for this class. + */ #define PASCAL_CHANNEL_GPFIFO_A (0x0000C06F) -/* class PASCAL_CHANNEL_GPFIFO_A */ +#define NVC06F_TYPEDEF PASCAL_CHANNELChannelGPFifoA + +/* dma flow control data structure */ +typedef volatile struct Nvc06fControl_struct { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} Nvc06fControl, PascalAControlGPFifo; + +/* fields and values */ +#define NVC06F_NUMBER_OF_SUBCHANNELS (8) #define NVC06F_SET_OBJECT (0x00000000) +#define NVC06F_SET_OBJECT_NVCLASS 15:0 +#define NVC06F_SET_OBJECT_ENGINE 20:16 +#define NVC06F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVC06F_ILLEGAL (0x00000004) +#define NVC06F_ILLEGAL_HANDLE 31:0 #define NVC06F_NOP (0x00000008) #define NVC06F_NOP_HANDLE 31:0 #define NVC06F_SEMAPHOREA (0x00000010) @@ -47,54 +84,33 @@ extern "C" { #define NVC06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 #define NVC06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 #define NVC06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVC06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVC06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 - - -/* GPFIFO entry format */ -#define NVC06F_GP_ENTRY__SIZE 8 -#define NVC06F_GP_ENTRY0_GET 31:2 -#define NVC06F_GP_ENTRY0_OPERAND 31:0 -#define NVC06F_GP_ENTRY1_GET_HI 7:0 -#define NVC06F_GP_ENTRY1_PRIV 8:8 -#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000 -#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 -#define NVC06F_GP_ENTRY1_LEVEL 9:9 -#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 -#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 -#define NVC06F_GP_ENTRY1_LENGTH 30:10 - -/* dma incrementing method format */ -#define NVC06F_DMA_INCR_ADDRESS 11:0 -#define NVC06F_DMA_INCR_SUBCHANNEL 15:13 -#define NVC06F_DMA_INCR_COUNT 28:16 -#define NVC06F_DMA_INCR_OPCODE 31:29 -#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001) -#define NVC06F_DMA_INCR_DATA 31:0 -/* dma non-incrementing method format */ -#define NVC06F_DMA_NONINCR_ADDRESS 11:0 -#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13 -#define NVC06F_DMA_NONINCR_COUNT 28:16 -#define NVC06F_DMA_NONINCR_OPCODE 31:29 -#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) -#define NVC06F_DMA_NONINCR_DATA 31:0 -/* dma increment-once method format */ -#define NVC06F_DMA_ONEINCR_ADDRESS 11:0 -#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13 -#define NVC06F_DMA_ONEINCR_COUNT 28:16 -#define NVC06F_DMA_ONEINCR_OPCODE 31:29 -#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) -#define NVC06F_DMA_ONEINCR_DATA 31:0 -/* dma no-operation format */ -#define NVC06F_DMA_NOP (0x00000000) -/* dma immediate-data format */ -#define NVC06F_DMA_IMMD_ADDRESS 11:0 -#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13 -#define NVC06F_DMA_IMMD_DATA 28:16 -#define NVC06F_DMA_IMMD_OPCODE 31:29 -#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004) - +#define NVC06F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVC06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVC06F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVC06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION 30:27 +#define NVC06F_SEMAPHORED_REDUCTION_MIN 0x00000000 +#define NVC06F_SEMAPHORED_REDUCTION_MAX 0x00000001 +#define NVC06F_SEMAPHORED_REDUCTION_XOR 0x00000002 +#define NVC06F_SEMAPHORED_REDUCTION_AND 0x00000003 +#define NVC06F_SEMAPHORED_REDUCTION_OR 0x00000004 +#define NVC06F_SEMAPHORED_REDUCTION_ADD 0x00000005 +#define NVC06F_SEMAPHORED_REDUCTION_INC 0x00000006 +#define NVC06F_SEMAPHORED_REDUCTION_DEC 0x00000007 +#define NVC06F_SEMAPHORED_FORMAT 31:31 +#define NVC06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 +#define NVC06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 +#define NVC06F_NON_STALL_INTERRUPT (0x00000020) +#define NVC06F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVC06F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR +#define NVC06F_FB_FLUSH_HANDLE 31:0 // NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for // specifying the page address for a targeted TLB invalidate and the uTLB for // a targeted REPLAY_CANCEL for UVM. @@ -153,18 +169,141 @@ extern "C" { #define NVC06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d #define NVC06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e // CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC06F_MEM_OP_D_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +// This B alias is confusing but it was missed as part of the update. Left here +// for compatibility. #define NVC06F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e #define NVC06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f #define NVC06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 #define NVC06F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 #define NVC06F_SET_REFERENCE (0x00000050) #define NVC06F_SET_REFERENCE_COUNT 31:0 - +// Syncpoint methods are only available on Tegra parts. Attempting to use +// them on discrete GPUs will result in Host raising NV_PPBDMA_INTR_0_METHOD. +#define NVC06F_SYNCPOINTA (0x00000070) +#define NVC06F_SYNCPOINTA_PAYLOAD 31:0 +#define NVC06F_SYNCPOINTB (0x00000074) +#define NVC06F_SYNCPOINTB_OPERATION 0:0 +#define NVC06F_SYNCPOINTB_OPERATION_WAIT 0x00000000 +#define NVC06F_SYNCPOINTB_OPERATION_INCR 0x00000001 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 +#define NVC06F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 +#define NVC06F_SYNCPOINTB_SYNCPT_INDEX 19:8 #define NVC06F_WFI (0x00000078) #define NVC06F_WFI_SCOPE 0:0 #define NVC06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 #define NVC06F_WFI_SCOPE_ALL 0x00000001 +#define NVC06F_CRC_CHECK (0x0000007c) +#define NVC06F_CRC_CHECK_VALUE 31:0 +#define NVC06F_YIELD (0x00000080) +#define NVC06F_YIELD_OP 1:0 +#define NVC06F_YIELD_OP_NOP 0x00000000 +#define NVC06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 +#define NVC06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 +#define NVC06F_YIELD_OP_TSG 0x00000003 + + +/* GPFIFO entry format */ +#define NVC06F_GP_ENTRY__SIZE 8 +#define NVC06F_GP_ENTRY0_FETCH 0:0 +#define NVC06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC06F_GP_ENTRY0_GET 31:2 +#define NVC06F_GP_ENTRY0_OPERAND 31:0 +#define NVC06F_GP_ENTRY1_GET_HI 7:0 +#define NVC06F_GP_ENTRY1_PRIV 8:8 +#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVC06F_GP_ENTRY1_LEVEL 9:9 +#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC06F_GP_ENTRY1_LENGTH 30:10 +#define NVC06F_GP_ENTRY1_SYNC 31:31 +#define NVC06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC06F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE 7:0 +#define NVC06F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 +/* dma method formats */ +#define NVC06F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVC06F_DMA_METHOD_ADDRESS 11:0 +#define NVC06F_DMA_SUBDEVICE_MASK 15:4 +#define NVC06F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVC06F_DMA_TERT_OP 17:16 +#define NVC06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVC06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVC06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVC06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVC06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVC06F_DMA_METHOD_COUNT_OLD 28:18 +#define NVC06F_DMA_METHOD_COUNT 28:16 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_SEC_OP 31:29 +#define NVC06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVC06F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVC06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVC06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVC06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVC06F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVC06F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVC06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVC06F_DMA_INCR_ADDRESS 11:0 +#define NVC06F_DMA_INCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_INCR_COUNT 28:16 +#define NVC06F_DMA_INCR_OPCODE 31:29 +#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVC06F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVC06F_DMA_NONINCR_ADDRESS 11:0 +#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_NONINCR_COUNT 28:16 +#define NVC06F_DMA_NONINCR_OPCODE 31:29 +#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVC06F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVC06F_DMA_ONEINCR_ADDRESS 11:0 +#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVC06F_DMA_ONEINCR_COUNT 28:16 +#define NVC06F_DMA_ONEINCR_OPCODE 31:29 +#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVC06F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVC06F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVC06F_DMA_IMMD_ADDRESS 11:0 +#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVC06F_DMA_IMMD_DATA 28:16 +#define NVC06F_DMA_IMMD_OPCODE 31:29 +#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVC06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVC06F_DMA_ENDSEG_OPCODE 31:29 +#define NVC06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVC06F_DMA_ADDRESS 12:2 +#define NVC06F_DMA_SUBCH 15:13 +#define NVC06F_DMA_OPCODE3 17:16 +#define NVC06F_DMA_OPCODE3_NONE (0x00000000) +#define NVC06F_DMA_COUNT 28:18 +#define NVC06F_DMA_OPCODE 31:29 +#define NVC06F_DMA_OPCODE_METHOD (0x00000000) +#define NVC06F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVC06F_DMA_DATA 31:0 #ifdef __cplusplus }; /* extern "C" */ diff --git a/kernel-open/nvidia-uvm/clc0b5.h b/kernel-open/nvidia-uvm/clc0b5.h index 3059a980c2..d1fa85ad8c 100644 --- a/kernel-open/nvidia-uvm/clc0b5.h +++ b/kernel-open/nvidia-uvm/clc0b5.h @@ -1,19 +1,19 @@ /******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER @@ -32,6 +32,10 @@ extern "C" { #define PASCAL_DMA_COPY_A (0x0000C0B5) +#define NVC0B5_NOP (0x00000100) +#define NVC0B5_NOP_PARAMETER 31:0 +#define NVC0B5_PM_TRIGGER (0x00000140) +#define NVC0B5_PM_TRIGGER_V 31:0 #define NVC0B5_SET_SEMAPHORE_A (0x00000240) #define NVC0B5_SET_SEMAPHORE_A_UPPER 16:0 #define NVC0B5_SET_SEMAPHORE_B (0x00000244) @@ -115,6 +119,10 @@ extern "C" { #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_RESERVED 31:28 #define NVC0B5_OFFSET_IN_UPPER (0x00000400) #define NVC0B5_OFFSET_IN_UPPER_UPPER 16:0 #define NVC0B5_OFFSET_IN_LOWER (0x00000404) @@ -183,6 +191,68 @@ extern "C" { #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_DST_WIDTH (0x00000710) +#define NVC0B5_SET_DST_WIDTH_V 31:0 +#define NVC0B5_SET_DST_HEIGHT (0x00000714) +#define NVC0B5_SET_DST_HEIGHT_V 31:0 +#define NVC0B5_SET_DST_DEPTH (0x00000718) +#define NVC0B5_SET_DST_DEPTH_V 31:0 +#define NVC0B5_SET_DST_LAYER (0x0000071C) +#define NVC0B5_SET_DST_LAYER_V 31:0 +#define NVC0B5_SET_DST_ORIGIN (0x00000720) +#define NVC0B5_SET_DST_ORIGIN_X 15:0 +#define NVC0B5_SET_DST_ORIGIN_Y 31:16 +#define NVC0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_SRC_WIDTH (0x0000072C) +#define NVC0B5_SET_SRC_WIDTH_V 31:0 +#define NVC0B5_SET_SRC_HEIGHT (0x00000730) +#define NVC0B5_SET_SRC_HEIGHT_V 31:0 +#define NVC0B5_SET_SRC_DEPTH (0x00000734) +#define NVC0B5_SET_SRC_DEPTH_V 31:0 +#define NVC0B5_SET_SRC_LAYER (0x00000738) +#define NVC0B5_SET_SRC_LAYER_V 31:0 +#define NVC0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC0B5_SET_SRC_ORIGIN_X 15:0 +#define NVC0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC0B5_PM_TRIGGER_END (0x00001114) +#define NVC0B5_PM_TRIGGER_END_V 31:0 #ifdef __cplusplus }; /* extern "C" */ diff --git a/kernel-open/nvidia-uvm/clc1b5.h b/kernel-open/nvidia-uvm/clc1b5.h index e95f14ac97..fff8467fbb 100644 --- a/kernel-open/nvidia-uvm/clc1b5.h +++ b/kernel-open/nvidia-uvm/clc1b5.h @@ -1,19 +1,19 @@ /******************************************************************************* - Copyright (c) 2014 NVIDIA Corporation + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER @@ -32,6 +32,10 @@ extern "C" { #define PASCAL_DMA_COPY_B (0x0000C1B5) +#define NVC1B5_NOP (0x00000100) +#define NVC1B5_NOP_PARAMETER 31:0 +#define NVC1B5_PM_TRIGGER (0x00000140) +#define NVC1B5_PM_TRIGGER_V 31:0 #define NVC1B5_SET_SEMAPHORE_A (0x00000240) #define NVC1B5_SET_SEMAPHORE_A_UPPER 16:0 #define NVC1B5_SET_SEMAPHORE_B (0x00000244) @@ -115,6 +119,14 @@ extern "C" { #define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 #define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) #define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC1B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC1B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 #define NVC1B5_OFFSET_IN_UPPER (0x00000400) #define NVC1B5_OFFSET_IN_UPPER_UPPER 16:0 #define NVC1B5_OFFSET_IN_LOWER (0x00000404) @@ -183,6 +195,76 @@ extern "C" { #define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) #define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) #define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_DST_WIDTH (0x00000710) +#define NVC1B5_SET_DST_WIDTH_V 31:0 +#define NVC1B5_SET_DST_HEIGHT (0x00000714) +#define NVC1B5_SET_DST_HEIGHT_V 31:0 +#define NVC1B5_SET_DST_DEPTH (0x00000718) +#define NVC1B5_SET_DST_DEPTH_V 31:0 +#define NVC1B5_SET_DST_LAYER (0x0000071C) +#define NVC1B5_SET_DST_LAYER_V 31:0 +#define NVC1B5_SET_DST_ORIGIN (0x00000720) +#define NVC1B5_SET_DST_ORIGIN_X 15:0 +#define NVC1B5_SET_DST_ORIGIN_Y 31:16 +#define NVC1B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_SRC_WIDTH (0x0000072C) +#define NVC1B5_SET_SRC_WIDTH_V 31:0 +#define NVC1B5_SET_SRC_HEIGHT (0x00000730) +#define NVC1B5_SET_SRC_HEIGHT_V 31:0 +#define NVC1B5_SET_SRC_DEPTH (0x00000734) +#define NVC1B5_SET_SRC_DEPTH_V 31:0 +#define NVC1B5_SET_SRC_LAYER (0x00000738) +#define NVC1B5_SET_SRC_LAYER_V 31:0 +#define NVC1B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC1B5_SET_SRC_ORIGIN_X 15:0 +#define NVC1B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC1B5_SRC_ORIGIN_X (0x00000744) +#define NVC1B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC1B5_SRC_ORIGIN_Y (0x00000748) +#define NVC1B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_X (0x0000074C) +#define NVC1B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_Y (0x00000750) +#define NVC1B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_PM_TRIGGER_END (0x00001114) +#define NVC1B5_PM_TRIGGER_END_V 31:0 #ifdef __cplusplus }; /* extern "C" */ diff --git a/kernel-open/nvidia-uvm/clc3b5.h b/kernel-open/nvidia-uvm/clc3b5.h index 04d4ba29c8..74ee1b74f6 100644 --- a/kernel-open/nvidia-uvm/clc3b5.h +++ b/kernel-open/nvidia-uvm/clc3b5.h @@ -1,19 +1,19 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER @@ -32,6 +32,10 @@ extern "C" { #define VOLTA_DMA_COPY_A (0x0000C3B5) +#define NVC3B5_NOP (0x00000100) +#define NVC3B5_NOP_PARAMETER 31:0 +#define NVC3B5_PM_TRIGGER (0x00000140) +#define NVC3B5_PM_TRIGGER_V 31:0 #define NVC3B5_SET_SEMAPHORE_A (0x00000240) #define NVC3B5_SET_SEMAPHORE_A_UPPER 16:0 #define NVC3B5_SET_SEMAPHORE_B (0x00000244) @@ -126,8 +130,6 @@ extern "C" { #define NVC3B5_LAUNCH_DMA_VPRMODE 23:22 #define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) #define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) -#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_VID2SYS (0x00000002) -#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_SYS2VID (0x00000003) #define NVC3B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 #define NVC3B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 #define NVC3B5_OFFSET_IN_UPPER (0x00000400) @@ -198,6 +200,76 @@ extern "C" { #define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) #define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) #define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_DST_WIDTH (0x00000710) +#define NVC3B5_SET_DST_WIDTH_V 31:0 +#define NVC3B5_SET_DST_HEIGHT (0x00000714) +#define NVC3B5_SET_DST_HEIGHT_V 31:0 +#define NVC3B5_SET_DST_DEPTH (0x00000718) +#define NVC3B5_SET_DST_DEPTH_V 31:0 +#define NVC3B5_SET_DST_LAYER (0x0000071C) +#define NVC3B5_SET_DST_LAYER_V 31:0 +#define NVC3B5_SET_DST_ORIGIN (0x00000720) +#define NVC3B5_SET_DST_ORIGIN_X 15:0 +#define NVC3B5_SET_DST_ORIGIN_Y 31:16 +#define NVC3B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_SRC_WIDTH (0x0000072C) +#define NVC3B5_SET_SRC_WIDTH_V 31:0 +#define NVC3B5_SET_SRC_HEIGHT (0x00000730) +#define NVC3B5_SET_SRC_HEIGHT_V 31:0 +#define NVC3B5_SET_SRC_DEPTH (0x00000734) +#define NVC3B5_SET_SRC_DEPTH_V 31:0 +#define NVC3B5_SET_SRC_LAYER (0x00000738) +#define NVC3B5_SET_SRC_LAYER_V 31:0 +#define NVC3B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC3B5_SET_SRC_ORIGIN_X 15:0 +#define NVC3B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC3B5_SRC_ORIGIN_X (0x00000744) +#define NVC3B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC3B5_SRC_ORIGIN_Y (0x00000748) +#define NVC3B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_X (0x0000074C) +#define NVC3B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_Y (0x00000750) +#define NVC3B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_PM_TRIGGER_END (0x00001114) +#define NVC3B5_PM_TRIGGER_END_V 31:0 #ifdef __cplusplus }; /* extern "C" */ diff --git a/kernel-open/nvidia-uvm/clcba2.h b/kernel-open/nvidia-uvm/clcba2.h new file mode 100644 index 0000000000..7ede90d673 --- /dev/null +++ b/kernel-open/nvidia-uvm/clcba2.h @@ -0,0 +1,97 @@ +/******************************************************************************* + Copyright (c) 2021-2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clcba2_h_ +#define _clcba2_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HOPPER_SEC2_WORK_LAUNCH_A (0x0000CBA2) + +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI (0x00000400) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO (0x00000404) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI (0x00000408) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO (0x0000040c) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_SIZE (0x00000410) +#define NVCBA2_DECRYPT_COPY_SIZE_DATA 31:2 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI (0x00000414) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO (0x00000418) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI (0x0000041C) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO (0x00000420) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_SEMAPHORE_A (0x00000440) +#define NVCBA2_SEMAPHORE_A_UPPER 24:0 +#define NVCBA2_SEMAPHORE_B (0x00000444) +#define NVCBA2_SEMAPHORE_B_LOWER 31:2 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER (0x00000448) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER_DATA 31:0 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000044C) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER_DATA 31:0 +#define NVCBA2_SEMAPHORE_D (0x00000450) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR 0:0 +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE 1:1 +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP 2:2 +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE 3:3 +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE (0x00000470) +#define NVCBA2_EXECUTE_NOTIFY 0:0 +#define NVCBA2_EXECUTE_NOTIFY_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_ON 1:1 +#define NVCBA2_EXECUTE_NOTIFY_ON_END (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ON_BEGIN (0x00000001) +#define NVCBA2_EXECUTE_FLUSH_DISABLE 2:2 +#define NVCBA2_EXECUTE_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_EXECUTE_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_INTR 3:3 +#define NVCBA2_EXECUTE_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE 4:4 +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_EXECUTE_TIMESTAMP 5:5 +#define NVCBA2_EXECUTE_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_TIMESTAMP_ENABLE (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcba2_h diff --git a/kernel-open/nvidia-uvm/nv-kthread-q.c b/kernel-open/nvidia-uvm/nv-kthread-q.c index 31a54cc05b..2098f27a70 100644 --- a/kernel-open/nvidia-uvm/nv-kthread-q.c +++ b/kernel-open/nvidia-uvm/nv-kthread-q.c @@ -301,7 +301,7 @@ static void _q_flush_function(void *args) static void _raw_q_flush(nv_kthread_q_t *q) { nv_kthread_q_item_t q_item; - DECLARE_COMPLETION(completion); + DECLARE_COMPLETION_ONSTACK(completion); nv_kthread_q_item_init(&q_item, _q_flush_function, &completion); diff --git a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild index 12fc09ff82..b051989267 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild @@ -1,6 +1,11 @@ NVIDIA_UVM_SOURCES ?= NVIDIA_UVM_SOURCES_CXX ?= +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ats_sva.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_conf_computing.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_sec2_test.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_maxwell_sec2.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_sec2.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_common.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_linux.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_debug_optimized.c diff --git a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild index ea71293886..17194445d6 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild @@ -84,7 +84,9 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_set NV_CONFTEST_FUNCTION_COMPILE_TESTS += migrate_vma_setup NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero +NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmgrab NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_sva_bind_device_has_drvdata_arg +NV_CONFTEST_FUNCTION_COMPILE_TESTS += vm_fault_to_errno NV_CONFTEST_TYPE_COMPILE_TESTS += backing_dev_info NV_CONFTEST_TYPE_COMPILE_TESTS += mm_context_t @@ -104,5 +106,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_vma_added_flags NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_device_range NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += handle_mm_fault_has_mm_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += handle_mm_fault_has_pt_regs_arg NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg diff --git a/kernel-open/nvidia-uvm/uvm.c b/kernel-open/nvidia-uvm/uvm.c index 1e10a381ee..a74ad154b3 100644 --- a/kernel-open/nvidia-uvm/uvm.c +++ b/kernel-open/nvidia-uvm/uvm.c @@ -28,6 +28,7 @@ #include "uvm_lock.h" #include "uvm_test.h" #include "uvm_va_space.h" +#include "uvm_va_space_mm.h" #include "uvm_va_range.h" #include "uvm_va_block.h" #include "uvm_tools.h" @@ -72,6 +73,11 @@ uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val) BUILD_BUG_ON(__alignof__(uvm_va_space_t) < (1UL << UVM_FD_TYPE_BITS)); break; + case UVM_FD_MM: + UVM_ASSERT(ptr); + BUILD_BUG_ON(__alignof__(struct file) < (1UL << UVM_FD_TYPE_BITS)); + break; + default: UVM_ASSERT(0); } @@ -82,6 +88,106 @@ uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val) return type; } +void *uvm_fd_get_type(struct file *filp, uvm_fd_type_t type) +{ + void *ptr; + + UVM_ASSERT(uvm_file_is_nvidia_uvm(filp)); + + if (uvm_fd_type(filp, &ptr) == type) + return ptr; + else + return NULL; +} + +static NV_STATUS uvm_api_mm_initialize(UVM_MM_INITIALIZE_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space; + uvm_va_space_mm_t *va_space_mm; + struct file *uvm_file; + uvm_fd_type_t old_fd_type; + struct mm_struct *mm; + NV_STATUS status; + + uvm_file = fget(params->uvmFd); + if (!uvm_file_is_nvidia_uvm(uvm_file)) { + status = NV_ERR_INVALID_ARGUMENT; + goto err; + } + + if (uvm_fd_type(uvm_file, (void **)&va_space) != UVM_FD_VA_SPACE) { + status = NV_ERR_INVALID_ARGUMENT; + goto err; + } + + // Tell userspace the MM FD is not required and it may be released + // with no loss of functionality. + if (!uvm_va_space_mm_enabled(va_space)) { + status = NV_WARN_NOTHING_TO_DO; + goto err; + } + + old_fd_type = nv_atomic_long_cmpxchg((atomic_long_t *)&filp->private_data, + UVM_FD_UNINITIALIZED, + UVM_FD_INITIALIZING); + old_fd_type &= UVM_FD_TYPE_MASK; + if (old_fd_type != UVM_FD_UNINITIALIZED) { + status = NV_ERR_IN_USE; + goto err; + } + + va_space_mm = &va_space->va_space_mm; + uvm_spin_lock(&va_space_mm->lock); + switch (va_space->va_space_mm.state) { + // We only allow the va_space_mm to be initialised once. If + // userspace passed the UVM FD to another process it is up to + // userspace to ensure it also passes the UVM MM FD that + // initialised the va_space_mm or arranges some other way to keep + // a reference on the FD. + case UVM_VA_SPACE_MM_STATE_ALIVE: + status = NV_ERR_INVALID_STATE; + goto err_release_unlock; + break; + + // Once userspace has released the va_space_mm the GPU is + // effectively dead and no new work can be started. We don't + // support re-initializing once userspace has closed the FD. + case UVM_VA_SPACE_MM_STATE_RELEASED: + status = NV_ERR_PAGE_TABLE_NOT_AVAIL; + goto err_release_unlock; + break; + + // Keep the warnings at bay + case UVM_VA_SPACE_MM_STATE_UNINITIALIZED: + mm = va_space->va_space_mm.mm; + if (!mm || !mmget_not_zero(mm)) { + status = NV_ERR_PAGE_TABLE_NOT_AVAIL; + goto err_release_unlock; + } + + va_space_mm->state = UVM_VA_SPACE_MM_STATE_ALIVE; + break; + + default: + UVM_ASSERT(0); + break; + } + uvm_spin_unlock(&va_space_mm->lock); + atomic_long_set_release((atomic_long_t *)&filp->private_data, (long)uvm_file | UVM_FD_MM); + + return NV_OK; + +err_release_unlock: + uvm_spin_unlock(&va_space_mm->lock); + atomic_long_set_release((atomic_long_t *)&filp->private_data, UVM_FD_UNINITIALIZED); + +err: + if (uvm_file) + fput(uvm_file); + + return status; +} + // Called when opening /dev/nvidia-uvm. This code doesn't take any UVM locks, so // there's no need to acquire g_uvm_global.pm.lock, but if that changes the PM // lock will need to be taken. @@ -147,20 +253,44 @@ static void uvm_release_deferred(void *data) uvm_up_read(&g_uvm_global.pm.lock); } +static void uvm_mm_release(struct file *filp, struct file *uvm_file) +{ + uvm_va_space_t *va_space = uvm_va_space_get(uvm_file); + uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; + struct mm_struct *mm = va_space_mm->mm; + + if (uvm_va_space_mm_enabled(va_space)) { + uvm_va_space_mm_unregister(va_space); + + if (uvm_va_space_mm_enabled(va_space)) + uvm_mmput(mm); + + va_space_mm->mm = NULL; + fput(uvm_file); + } +} + static int uvm_release(struct inode *inode, struct file *filp) { + void *ptr; uvm_va_space_t *va_space; uvm_fd_type_t fd_type; int ret; - fd_type = uvm_fd_type(filp, (void **)&va_space); + fd_type = uvm_fd_type(filp, &ptr); UVM_ASSERT(fd_type != UVM_FD_INITIALIZING); if (fd_type == UVM_FD_UNINITIALIZED) { uvm_kvfree(filp->f_mapping); return 0; } + else if (fd_type == UVM_FD_MM) { + uvm_kvfree(filp->f_mapping); + uvm_mm_release(filp, (struct file *)ptr); + return 0; + } UVM_ASSERT(fd_type == UVM_FD_VA_SPACE); + va_space = (uvm_va_space_t *)ptr; filp->private_data = NULL; filp->f_mapping = NULL; @@ -756,6 +886,13 @@ static int uvm_mmap(struct file *filp, struct vm_area_struct *vma) return ret; } +bool uvm_vma_is_managed(struct vm_area_struct *vma) +{ + return vma->vm_ops == &uvm_vm_ops_disabled || + vma->vm_ops == &uvm_vm_ops_managed || + vma->vm_ops == &uvm_vm_ops_semaphore_pool; +} + static int uvm_mmap_entry(struct file *filp, struct vm_area_struct *vma) { UVM_ENTRY_RET(uvm_mmap(filp, vma)); @@ -804,6 +941,9 @@ static NV_STATUS uvm_api_initialize(UVM_INITIALIZE_PARAMS *params, struct file * else status = NV_OK; } + else if (old_fd_type == UVM_FD_MM) { + status = NV_ERR_INVALID_ARGUMENT; + } else { UVM_ASSERT(old_fd_type == UVM_FD_INITIALIZING); status = NV_ERR_BUSY_RETRY; @@ -827,6 +967,7 @@ static long uvm_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return 0; UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_INITIALIZE, uvm_api_initialize); + UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_MM_INITIALIZE, uvm_api_mm_initialize); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_PAGEABLE_MEM_ACCESS, uvm_api_pageable_mem_access); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_PAGEABLE_MEM_ACCESS_ON_GPU, uvm_api_pageable_mem_access_on_gpu); diff --git a/kernel-open/nvidia-uvm/uvm.h b/kernel-open/nvidia-uvm/uvm.h index db13a30f01..8177b9797d 100644 --- a/kernel-open/nvidia-uvm/uvm.h +++ b/kernel-open/nvidia-uvm/uvm.h @@ -54,7 +54,7 @@ #ifndef _UVM_H_ #define _UVM_H_ -#define UVM_API_LATEST_REVISION 7 +#define UVM_API_LATEST_REVISION 8 #if !defined(UVM_API_REVISION) #error "please define UVM_API_REVISION macro to a desired version number or UVM_API_LATEST_REVISION macro" @@ -410,6 +410,12 @@ NV_STATUS UvmRegisterGpuSmc(const NvProcessorUuid *gpuUuid, // location will have their range group association changed to // UVM_RANGE_GROUP_ID_NONE. // +// If the Confidential Computing feature is enabled in the system, any VA +// ranges allocated using UvmAllocSemaphorePool and owned by this GPU will be +// unmapped from all GPUs and the CPU. UvmFree must still be called on those +// ranges to reclaim the VA. See UvmAllocSemaphorePool to determine which GPU +// is considered the owner. +// // Arguments: // gpuUuid: (INPUT) // UUID of the GPU to unregister. @@ -1094,10 +1100,12 @@ NV_STATUS UvmAllowMigrationRangeGroups(const NvU64 *rangeGroupIds, // Creates a new mapping in the virtual address space of the process, populates // it at the specified preferred location, maps it on the provided list of // processors if feasible and associates the range with the given range group. +// If the preferredLocationUuid is the UUID of the CPU, preferred location is +// set to all CPU nodes allowed by the global and thread memory policies. // // This API is equivalent to the following code sequence: // UvmMemMap(base, length); -// UvmSetPreferredLocation(base, length, preferredLocationUuid); +// UvmSetPreferredLocation(base, length, preferredLocationUuid, -1); // for (i = 0; i < accessedByCount; i++) { // UvmSetAccessedBy(base, length, &accessedByUuids[i]); // } @@ -1262,6 +1270,12 @@ NV_STATUS UvmCleanUpZombieResources(void); // // The VA range can be unmapped and freed via a call to UvmFree. // +// If the Confidential Computing feature is enabled in the system, at least one +// GPU must be provided in the perGpuAttribs array. The first GPU in the array +// is considered the owning GPU. If the owning GPU is unregistered via +// UvmUnregisterGpu, this allocation will no longer be usable. +// See UvmUnregisterGpu. +// // Arguments: // base: (INPUT) // Base address of the virtual address range. @@ -1298,6 +1312,8 @@ NV_STATUS UvmCleanUpZombieResources(void); // NV_ERR_INVALID_ARGUMENT: // perGpuAttribs is NULL but gpuAttribsCount is non-zero or vice-versa, // or caching is requested on more than one GPU. +// The Confidential Computing feature is enabled and the perGpuAttribs +// list is empty. // // NV_ERR_NOT_SUPPORTED: // The current process is not the one which called UvmInitialize, and @@ -1444,7 +1460,7 @@ NV_STATUS UvmMigrate(void *base, NV_STATUS UvmMigrate(void *base, NvLength length, const NvProcessorUuid *destinationUuid, - NvU32 preferredCpuMemoryNode); + NvS32 preferredCpuMemoryNode); #endif //------------------------------------------------------------------------------ @@ -1537,7 +1553,7 @@ NV_STATUS UvmMigrateAsync(void *base, NV_STATUS UvmMigrateAsync(void *base, NvLength length, const NvProcessorUuid *destinationUuid, - NvU32 preferredCpuMemoryNode, + NvS32 preferredCpuMemoryNode, void *semaphoreAddress, NvU32 semaphorePayload); #endif @@ -2217,11 +2233,10 @@ NV_STATUS UvmDisableReadDuplication(void *base, // supported by the specified processor. // // The virtual address range specified by (base, length) must have been -// allocated via a call to either UvmAlloc or UvmMemMap, or be supported -// system-allocated pageable memory. If the input range is pageable memory and -// at least one GPU in the system supports transparent access to pageable -// memory, the behavior described below does not take effect and the preferred -// location of the pages in the given range does not change. +// allocated via a call to either UvmAlloc or UvmMemMap (managed memory), or be +// supported system-allocated pageable memory. If the input range corresponds to +// a file backed shared mapping and least one GPU in the system supports +// transparent access to pageable memory, the behavior below is not guaranteed. // // If any pages in the VA range are associated with a range group that was made // non-migratable via UvmPreventMigrationRangeGroups, then those pages are @@ -2240,17 +2255,17 @@ NV_STATUS UvmDisableReadDuplication(void *base, // not cause a migration if a mapping for that page from that processor can be // established without migrating the page. // -// When a page migrates away from its preferred location, the mapping on the -// preferred location's processor is cleared so that the next access from that -// processor will cause a fault and migrate the page back to its preferred -// location. In other words, a page is mapped on the preferred location's -// processor only if the page is in its preferred location. Thus, when the -// preferred location changes, mappings to pages in the given range are removed -// from the new preferred location if the pages are resident in a different -// processor. Note that if the preferred location's processor is a GPU, then a -// mapping from that GPU to a page in the VA range is only created if a GPU VA -// space has been registered for that GPU and the page is in its preferred -// location. +// When a page that was allocated via either UvmAlloc or UvmMemMap migrates away +// from its preferred location, the mapping on the preferred location's +// processor is cleared so that the next access from that processor will cause a +// fault and migrate the page back to its preferred location. In other words, a +// page is mapped on the preferred location's processor only if the page is in +// its preferred location. Thus, when the preferred location changes, mappings +// to pages in the given range are removed from the new preferred location if +// the pages are resident in a different processor. Note that if the preferred +// location's processor is a GPU, then a mapping from that GPU to a page in the +// VA range is only created if a GPU VA space has been registered for that GPU +// and the page is in its preferred location. // // If read duplication has been enabled for any pages in this VA range and // UvmPreventMigrationRangeGroups has not been called on the range group that @@ -2263,7 +2278,7 @@ NV_STATUS UvmDisableReadDuplication(void *base, // // If the preferred location processor is present in the accessed-by list of any // of the pages in this VA range, then the migration and mapping policies -// associated with associated with the accessed-by list. +// associated with this API override those associated with the accessed-by list. // // The state set by this API can be cleared either by calling // UvmUnsetPreferredLocation for the same VA range or by calling @@ -2284,35 +2299,66 @@ NV_STATUS UvmDisableReadDuplication(void *base, // preferredLocationUuid: (INPUT) // UUID of the preferred location. // +// preferredCpuNumaNode: (INPUT) +// Preferred CPU NUMA memory node used if preferredLocationUuid is the +// UUID of the CPU. -1 is a special value which indicates all CPU nodes +// allowed by the global and thread memory policies. This argument is +// ignored if preferredLocationUuid refers to a GPU or the given virtual +// address range corresponds to managed memory. If NUMA is not enabled, +// only 0 or -1 is allowed. +// // Errors: // NV_ERR_INVALID_ADDRESS: -// base and length are not properly aligned, or the range does not -// represent a valid UVM allocation, or the range is pageable memory and -// the system does not support accessing pageable memory, or the range -// does not represent a supported Operating System allocation. +// One of the following occurred: +// - base and length are not properly aligned. +// - The range does not represent a valid UVM allocation. +// - The range is pageable memory and the system does not support +// accessing pageable memory. +// - The range does not represent a supported Operating System +// allocation. // // NV_ERR_OUT_OF_RANGE: // The VA range exceeds the largest virtual address supported by the // specified processor. // // NV_ERR_INVALID_DEVICE: -// preferredLocationUuid is neither the UUID of the CPU nor the UUID of -// a GPU that was registered by this process. Or at least one page in -// VA range belongs to a non-migratable range group and the specified -// UUID represents a fault-capable GPU. Or preferredLocationUuid is the -// UUID of a non-fault-capable GPU and at least one page in the VA range -// belongs to a non-migratable range group and another non-fault-capable -// GPU is in the accessed-by list of the same page but P2P support -// between both GPUs has not been enabled. +// One of the following occurred: +// - preferredLocationUuid is neither the UUID of the CPU nor the UUID +// of a GPU that was registered by this process. +// - At least one page in VA range belongs to a non-migratable range +// group and the specified UUID represents a fault-capable GPU. +// - preferredLocationUuid is the UUID of a non-fault-capable GPU and at +// least one page in the VA range belongs to a non-migratable range +// group and another non-fault-capable GPU is in the accessed-by list +// of the same page but P2P support between both GPUs has not been +// enabled. +// +// NV_ERR_INVALID_ARGUMENT: +// One of the following occured: +// - preferredLocationUuid is the UUID of a CPU and preferredCpuNumaNode +// refers to a registered GPU. +// - preferredCpuNumaNode is invalid and preferredLocationUuid is the +// UUID of the CPU. +// +// NV_ERR_NOT_SUPPORTED: +// The UVM file descriptor is associated with another process and the +// input virtual range corresponds to system-allocated pageable memory. // // NV_ERR_GENERIC: // Unexpected error. We try hard to avoid returning this error code, // because it is not very informative. // //------------------------------------------------------------------------------ +#if UVM_API_REV_IS_AT_MOST(7) NV_STATUS UvmSetPreferredLocation(void *base, NvLength length, const NvProcessorUuid *preferredLocationUuid); +#else +NV_STATUS UvmSetPreferredLocation(void *base, + NvLength length, + const NvProcessorUuid *preferredLocationUuid, + NvS32 preferredCpuNumaNode); +#endif //------------------------------------------------------------------------------ // UvmUnsetPreferredLocation @@ -2326,10 +2372,9 @@ NV_STATUS UvmSetPreferredLocation(void *base, // // The virtual address range specified by (base, length) must have been // allocated via a call to either UvmAlloc or UvmMemMap, or be supported -// system-allocated pageable memory. If the input range is pageable memory and -// at least one GPU in the system supports transparent access to pageable -// memory, the behavior described below does not take effect and the preferred -// location of the pages in the given range does not change. +// system-allocated pageable memory. If the input range corresponds to a file +// backed shared mapping and least one GPU in the system supports transparent +// access to pageable memory, the behavior below is not guaranteed. // // If the VA range is associated with a non-migratable range group, then that // association is cleared. i.e. the pages in this VA range have their range @@ -2348,10 +2393,18 @@ NV_STATUS UvmSetPreferredLocation(void *base, // // Errors: // NV_ERR_INVALID_ADDRESS: -// base and length are not properly aligned or the range does not -// represent a valid UVM allocation, or the range is pageable memory and -// the system does not support accessing pageable memory, or the range -// does not represent a supported Operating System allocation. +// One of the following occured: +// - base and length are not properly aligned or the range does not +// represent a valid UVM allocation. +// - The range is pageable memory and the system does not support +// accessing pageable memory. +// - The range does not represent a supported Operating System +// allocation. +// - The range contains both managed and pageable memory allocations. +// +// NV_ERR_NOT_SUPPORTED: +// The UVM file descriptor is associated with another process and the +// input virtual range corresponds to system-allocated pageable memory. // // NV_ERR_GENERIC: // Unexpected error. We try hard to avoid returning this error code, @@ -2632,13 +2685,34 @@ NV_STATUS UvmDisableSystemWideAtomics(const NvProcessorUuid *gpuUuid); // NV_ERR_INVALID_STATE: // UVM was not initialized before calling this function. // -// NV_ERR_GENERIC: -// Unexpected error. We try hard to avoid returning this error code, -// because it is not very informative. -// //------------------------------------------------------------------------------ NV_STATUS UvmGetFileDescriptor(UvmFileDescriptor *returnedFd); +//------------------------------------------------------------------------------ +// UvmGetMmFileDescriptor +// +// Returns the UVM file descriptor currently being used to keep the +// memory management context valid. The data type of the returned file +// descriptor is platform specific. +// +// If UvmInitialize has not yet been called, an error is returned. +// +// Arguments: +// returnedFd: (OUTPUT) +// A platform specific file descriptor. +// +// Error codes: +// NV_ERR_INVALID_ARGUMENT: +// returnedFd is NULL. +// +// NV_ERR_INVALID_STATE: +// UVM was not initialized before calling this function. +// +// NV_ERR_NOT_SUPPORTED: +// This file descriptor is not required on this platform. +//------------------------------------------------------------------------------ +NV_STATUS UvmGetMmFileDescriptor(UvmFileDescriptor *returnedFd); + //------------------------------------------------------------------------------ // UvmIs8Supported // @@ -3761,7 +3835,6 @@ NV_STATUS UvmToolsDisableCounters(UvmToolsCountersHandle counters, // NV_ERR_INVALID_ARGUMENT: // Read spans more than a single target process allocation. // -// //------------------------------------------------------------------------------ NV_STATUS UvmToolsReadProcessMemory(UvmToolsSessionHandle session, void *buffer, diff --git a/kernel-open/nvidia-uvm/uvm_ada.c b/kernel-open/nvidia-uvm/uvm_ada.c index 820ac0e142..8852c44abf 100644 --- a/kernel-open/nvidia-uvm/uvm_ada.c +++ b/kernel-open/nvidia-uvm/uvm_ada.c @@ -49,11 +49,13 @@ void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu) // A single top level PDE on Ada covers 128 TB and that's the minimum size // that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; // Not all units on Ada support 49-bit addressing, including those which diff --git a/kernel-open/nvidia-uvm/uvm_ampere.c b/kernel-open/nvidia-uvm/uvm_ampere.c index e949c80f10..d4af699e42 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere.c +++ b/kernel-open/nvidia-uvm/uvm_ampere.c @@ -47,14 +47,16 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu) // A single top level PDE on Ampere covers 128 TB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; // See uvm_mmu.h for mapping placement - parent_gpu->flat_vidmem_va_base = 136ull * 1024 * 1024 * 1024 * 1024; - parent_gpu->flat_sysmem_va_base = 256ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->flat_vidmem_va_base = 136 * UVM_SIZE_1TB; + parent_gpu->flat_sysmem_va_base = 256 * UVM_SIZE_1TB; + + parent_gpu->ce_phys_vidmem_write_supported = true; parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; diff --git a/kernel-open/nvidia-uvm/uvm_ampere_ce.c b/kernel-open/nvidia-uvm/uvm_ampere_ce.c index f7037cab44..69eb84c7ca 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere_ce.c +++ b/kernel-open/nvidia-uvm/uvm_ampere_ce.c @@ -183,7 +183,10 @@ void uvm_hal_ampere_ce_memcopy_patch_src_c6b5(uvm_push_t *push, uvm_gpu_address_ src->address -= uvm_pushbuffer_get_gpu_va_for_push(push->channel->pool->manager->pushbuffer, push); } -bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) +bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); diff --git a/kernel-open/nvidia-uvm/uvm_api.h b/kernel-open/nvidia-uvm/uvm_api.h index 66ddeaa9aa..a63d163bb7 100644 --- a/kernel-open/nvidia-uvm/uvm_api.h +++ b/kernel-open/nvidia-uvm/uvm_api.h @@ -201,21 +201,20 @@ static bool uvm_api_range_invalid_64k(NvU64 base, NvU64 length) return uvm_api_range_invalid_aligned(base, length, UVM_PAGE_SIZE_64K); } -// Returns true if the interval [start, start + length -1] is entirely covered -// by vmas. -// -// LOCKING: mm->mmap_lock must be held in at least read mode. -bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length); +typedef enum +{ + UVM_API_RANGE_TYPE_MANAGED, + UVM_API_RANGE_TYPE_HMM, + UVM_API_RANGE_TYPE_ATS, + UVM_API_RANGE_TYPE_INVALID +} uvm_api_range_type_t; -// Check that the interval [base, base + length) is fully covered by UVM -// managed ranges (NV_OK is returned), or (if ATS is enabled and mm != NULL) -// fully covered by valid vmas (NV_WARN_NOTHING_TO_DO is returned), or (if HMM -// is enabled and mm != NULL) fully covered by valid vmas (NV_OK is returned). -// Any other input results in a return status of NV_ERR_INVALID_ADDRESS. +// If the interval [base, base + length) is fully covered by VMAs which all have +// the same uvm_api_range_type_t, that range type is returned. // // LOCKING: va_space->lock must be held in at least read mode. If mm != NULL, // mm->mmap_lock must also be held in at least read mode. -NV_STATUS uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length); +uvm_api_range_type_t uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length); NV_STATUS uvm_api_pageable_mem_access_on_gpu(UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS *params, struct file *filp); NV_STATUS uvm_api_register_gpu(UVM_REGISTER_GPU_PARAMS *params, struct file *filp); diff --git a/kernel-open/nvidia-uvm/uvm_ats.c b/kernel-open/nvidia-uvm/uvm_ats.c index 0dcd5e6dd7..d55dc61676 100644 --- a/kernel-open/nvidia-uvm/uvm_ats.c +++ b/kernel-open/nvidia-uvm/uvm_ats.c @@ -57,6 +57,10 @@ NV_STATUS uvm_ats_add_gpu(uvm_parent_gpu_t *parent_gpu) return uvm_ats_ibm_add_gpu(parent_gpu); } + else if (UVM_ATS_SVA_SUPPORTED()) { + if (g_uvm_global.ats.enabled) + return uvm_ats_sva_add_gpu(parent_gpu); + } return NV_OK; } @@ -71,6 +75,10 @@ void uvm_ats_remove_gpu(uvm_parent_gpu_t *parent_gpu) uvm_ats_ibm_remove_gpu(parent_gpu); } + else if (UVM_ATS_SVA_SUPPORTED()) { + if (g_uvm_global.ats.enabled) + uvm_ats_sva_remove_gpu(parent_gpu); + } } NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) @@ -87,6 +95,8 @@ NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) if (UVM_ATS_IBM_SUPPORTED()) status = uvm_ats_ibm_bind_gpu(gpu_va_space); + else if (UVM_ATS_SVA_SUPPORTED()) + status = uvm_ats_sva_bind_gpu(gpu_va_space); return status; } @@ -100,6 +110,8 @@ void uvm_ats_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space) if (UVM_ATS_IBM_SUPPORTED()) uvm_ats_ibm_unbind_gpu(gpu_va_space); + else if (UVM_ATS_SVA_SUPPORTED()) + uvm_ats_sva_unbind_gpu(gpu_va_space); } NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) @@ -126,6 +138,8 @@ NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) if (UVM_ATS_IBM_SUPPORTED()) status = uvm_ats_ibm_register_gpu_va_space(gpu_va_space); + else if (UVM_ATS_SVA_SUPPORTED()) + status = uvm_ats_sva_register_gpu_va_space(gpu_va_space); if (status == NV_OK) uvm_processor_mask_set(&va_space->ats.registered_gpu_va_spaces, gpu_id); @@ -148,6 +162,8 @@ void uvm_ats_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) if (UVM_ATS_IBM_SUPPORTED()) uvm_ats_ibm_unregister_gpu_va_space(gpu_va_space); + else if (UVM_ATS_SVA_SUPPORTED()) + uvm_ats_sva_unregister_gpu_va_space(gpu_va_space); uvm_va_space_down_write(va_space); uvm_processor_mask_clear(&va_space->ats.registered_gpu_va_spaces, gpu_id); diff --git a/kernel-open/nvidia-uvm/uvm_ats.h b/kernel-open/nvidia-uvm/uvm_ats.h index 2d4d8f336a..78da10f144 100644 --- a/kernel-open/nvidia-uvm/uvm_ats.h +++ b/kernel-open/nvidia-uvm/uvm_ats.h @@ -29,7 +29,9 @@ #include "uvm_ats_ibm.h" #include "nv_uvm_types.h" - #define UVM_ATS_SUPPORTED() (UVM_ATS_IBM_SUPPORTED()) + #include "uvm_ats_sva.h" + + #define UVM_ATS_SUPPORTED() (UVM_ATS_IBM_SUPPORTED() || UVM_ATS_SVA_SUPPORTED()) typedef struct { @@ -41,6 +43,7 @@ typedef struct { uvm_ibm_va_space_t ibm; + uvm_sva_va_space_t sva; }; } uvm_ats_va_space_t; @@ -58,6 +61,7 @@ typedef struct { uvm_ibm_gpu_va_space_t ibm; + uvm_sva_gpu_va_space_t sva; }; } uvm_ats_gpu_va_space_t; @@ -90,6 +94,8 @@ void uvm_ats_remove_gpu(uvm_parent_gpu_t *parent_gpu); // LOCKING: mmap_lock must be lockable. // VA space lock must be lockable. // gpu_va_space->gpu must be retained. +// mm must be retained with uvm_va_space_mm_retain() iff +// UVM_ATS_SVA_SUPPORTED() is 1 NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space); // Decrements the refcount on the {gpu, mm} pair. Removes the binding from the diff --git a/kernel-open/nvidia-uvm/uvm_ats_faults.c b/kernel-open/nvidia-uvm/uvm_ats_faults.c index cf10231034..10840b6811 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_faults.c +++ b/kernel-open/nvidia-uvm/uvm_ats_faults.c @@ -41,18 +41,18 @@ MODULE_PARM_DESC(uvm_exp_perf_prefetch_ats_order_non_replayable, // the module parameters, clamped to the vma containing fault_addr (if any). // Note that this means the region contains fault_addr but may not begin at // fault_addr. -static void expand_fault_region(struct mm_struct *mm, - NvU64 fault_addr, +static void expand_fault_region(struct vm_area_struct *vma, + NvU64 start, + size_t length, uvm_fault_client_type_t client_type, - unsigned long *start, - unsigned long *size) + unsigned long *migrate_start, + unsigned long *migrate_length) { - struct vm_area_struct *vma; unsigned int order; unsigned long outer, aligned_start, aligned_size; - *start = fault_addr; - *size = PAGE_SIZE; + *migrate_start = start; + *migrate_length = length; if (client_type == UVM_FAULT_CLIENT_TYPE_HUB) order = uvm_exp_perf_prefetch_ats_order_non_replayable; @@ -62,32 +62,31 @@ static void expand_fault_region(struct mm_struct *mm, if (order == 0) return; - vma = find_vma_intersection(mm, fault_addr, fault_addr + 1); - if (!vma) - return; - + UVM_ASSERT(vma); UVM_ASSERT(order < BITS_PER_LONG - PAGE_SHIFT); aligned_size = (1UL << order) * PAGE_SIZE; - aligned_start = fault_addr & ~(aligned_size - 1); + aligned_start = start & ~(aligned_size - 1); - *start = max(vma->vm_start, aligned_start); + *migrate_start = max(vma->vm_start, aligned_start); outer = min(vma->vm_end, aligned_start + aligned_size); - *size = outer - *start; + *migrate_length = outer - *migrate_start; } -static NV_STATUS uvm_ats_service_fault(uvm_gpu_va_space_t *gpu_va_space, - NvU64 fault_addr, - uvm_fault_access_type_t access_type, - uvm_fault_client_type_t client_type) +static NV_STATUS service_ats_faults(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 start, + size_t length, + uvm_fault_access_type_t access_type, + uvm_fault_client_type_t client_type) { uvm_va_space_t *va_space = gpu_va_space->va_space; struct mm_struct *mm = va_space->va_space_mm.mm; bool write = (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE); NV_STATUS status; - NvU64 start; - NvU64 length; + NvU64 user_space_start; + NvU64 user_space_length; // Request uvm_migrate_pageable() to touch the corresponding page after // population. @@ -124,16 +123,14 @@ static NV_STATUS uvm_ats_service_fault(uvm_gpu_va_space_t *gpu_va_space, .populate_permissions = write ? UVM_POPULATE_PERMISSIONS_WRITE : UVM_POPULATE_PERMISSIONS_ANY, .touch = true, .skip_mapped = true, - .user_space_start = &start, - .user_space_length = &length, + .user_space_start = &user_space_start, + .user_space_length = &user_space_length, }; UVM_ASSERT(uvm_ats_can_service_faults(gpu_va_space, mm)); - expand_fault_region(mm, fault_addr, client_type, &uvm_migrate_args.start, &uvm_migrate_args.length); + expand_fault_region(vma, start, length, client_type, &uvm_migrate_args.start, &uvm_migrate_args.length); - // TODO: Bug 2103669: Service more than a single fault at a time - // // We are trying to use migrate_vma API in the kernel (if it exists) to // populate and map the faulting region on the GPU. We want to do this only // on the first touch. That is, pages which are not already mapped. So, we @@ -148,114 +145,141 @@ static NV_STATUS uvm_ats_service_fault(uvm_gpu_va_space_t *gpu_va_space, return status; } -NV_STATUS uvm_ats_service_fault_entry(uvm_gpu_va_space_t *gpu_va_space, - uvm_fault_buffer_entry_t *current_entry, - uvm_ats_fault_invalidate_t *ats_invalidate) +static void flush_tlb_write_faults(uvm_gpu_va_space_t *gpu_va_space, + NvU64 addr, + size_t size, + uvm_fault_client_type_t client_type) { - NvU64 gmmu_region_base; - bool in_gmmu_region; - NV_STATUS status = NV_OK; - uvm_fault_access_type_t service_access_type; + uvm_ats_fault_invalidate_t *ats_invalidate; + + if (client_type == UVM_FAULT_CLIENT_TYPE_GPC) + ats_invalidate = &gpu_va_space->gpu->parent->fault_buffer_info.replayable.ats_invalidate; + else + ats_invalidate = &gpu_va_space->gpu->parent->fault_buffer_info.non_replayable.ats_invalidate; + + if (!ats_invalidate->write_faults_in_batch) { + uvm_tlb_batch_begin(&gpu_va_space->page_tables, &ats_invalidate->write_faults_tlb_batch); + ats_invalidate->write_faults_in_batch = true; + } + + uvm_tlb_batch_invalidate(&ats_invalidate->write_faults_tlb_batch, addr, size, PAGE_SIZE, UVM_MEMBAR_NONE); +} +NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_fault_context_t *ats_context) +{ + NV_STATUS status = NV_OK; + uvm_va_block_region_t subregion; + uvm_va_block_region_t region = uvm_va_block_region(0, PAGES_PER_UVM_VA_BLOCK); + uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + uvm_page_mask_t *faults_serviced_mask = &ats_context->faults_serviced_mask; + uvm_page_mask_t *reads_serviced_mask = &ats_context->reads_serviced_mask; + uvm_fault_client_type_t client_type = ats_context->client_type; + + UVM_ASSERT(vma); + UVM_ASSERT(IS_ALIGNED(base, UVM_VA_BLOCK_SIZE)); UVM_ASSERT(g_uvm_global.ats.enabled); + UVM_ASSERT(gpu_va_space); UVM_ASSERT(gpu_va_space->ats.enabled); UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); - UVM_ASSERT(current_entry->fault_access_type == - uvm_fault_access_type_mask_highest(current_entry->access_type_mask)); - - service_access_type = current_entry->fault_access_type; - - // ATS lookups are disabled on all addresses within the same - // UVM_GMMU_ATS_GRANULARITY as existing GMMU mappings (see documentation in - // uvm_mmu.h). User mode is supposed to reserve VAs as appropriate to - // prevent any system memory allocations from falling within the NO_ATS - // range of other GMMU mappings, so this shouldn't happen during normal - // operation. However, since this scenario may lead to infinite fault loops, - // we handle it by canceling the fault. - // - // TODO: Bug 2103669: Remove redundant VA range lookups - gmmu_region_base = UVM_ALIGN_DOWN(current_entry->fault_address, UVM_GMMU_ATS_GRANULARITY); - in_gmmu_region = !uvm_va_space_range_empty(current_entry->va_space, - gmmu_region_base, - gmmu_region_base + UVM_GMMU_ATS_GRANULARITY - 1); - if (in_gmmu_region) { - status = NV_ERR_INVALID_ADDRESS; - } - else { - // TODO: Bug 2103669: Service more than a single fault at a time - status = uvm_ats_service_fault(gpu_va_space, - current_entry->fault_address, - service_access_type, - current_entry->fault_source.client_type); + uvm_page_mask_zero(faults_serviced_mask); + uvm_page_mask_zero(reads_serviced_mask); + + if (!(vma->vm_flags & VM_READ)) + return status; + + if (!(vma->vm_flags & VM_WRITE)) { + // If VMA doesn't have write permissions, all write faults are fatal. + // Try servicing such faults for read iff they are also present in + // read_fault_mask. This is because for replayable faults, if there are + // pending read accesses on the same page, we have to service them + // before we can cancel the write/atomic faults. So we try with read + // fault access type even though these write faults are fatal. + if (ats_context->client_type == UVM_FAULT_CLIENT_TYPE_GPC) + uvm_page_mask_and(write_fault_mask, write_fault_mask, read_fault_mask); + else + uvm_page_mask_zero(write_fault_mask); } - // Do not flag prefetch faults as fatal unless something fatal happened - if (status == NV_ERR_INVALID_ADDRESS) { - if (current_entry->fault_access_type != UVM_FAULT_ACCESS_TYPE_PREFETCH) { - current_entry->is_fatal = true; - current_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); - - // Compute cancel mode for replayable faults - if (current_entry->is_replayable) { - if (service_access_type == UVM_FAULT_ACCESS_TYPE_READ || in_gmmu_region) - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; - else - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC; - - // If there are pending read accesses on the same page, we have to - // service them before we can cancel the write/atomic faults. So we - // retry with read fault access type. - if (!in_gmmu_region && - current_entry->fault_access_type > UVM_FAULT_ACCESS_TYPE_READ && - uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ)) { - status = uvm_ats_service_fault(gpu_va_space, - current_entry->fault_address, - UVM_FAULT_ACCESS_TYPE_READ, - current_entry->fault_source.client_type); - - // If read accesses are also invalid, cancel the fault. If a - // different error code is returned, exit - if (status == NV_ERR_INVALID_ADDRESS) - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; - else if (status != NV_OK) - return status; - } - } + for_each_va_block_subregion_in_mask(subregion, write_fault_mask, region) { + NvU64 start = base + (subregion.first * PAGE_SIZE); + size_t length = uvm_va_block_region_num_pages(subregion) * PAGE_SIZE; + uvm_fault_access_type_t access_type = (vma->vm_flags & VM_WRITE) ? + UVM_FAULT_ACCESS_TYPE_WRITE : + UVM_FAULT_ACCESS_TYPE_READ; + + UVM_ASSERT(start >= vma->vm_start); + UVM_ASSERT((start + length) <= vma->vm_end); + + status = service_ats_faults(gpu_va_space, vma, start, length, access_type, client_type); + if (status != NV_OK) + return status; + + if (vma->vm_flags & VM_WRITE) { + uvm_page_mask_region_fill(faults_serviced_mask, subregion); + + // The Linux kernel never invalidates TLB entries on mapping + // permission upgrade. This is a problem if the GPU has cached + // entries with the old permission. The GPU will re-fetch the entry + // if the PTE is invalid and page size is not 4K (this is the case + // on P9). However, if a page gets upgraded from R/O to R/W and GPU + // has the PTEs cached with R/O permissions we will enter an + // infinite loop because we just forward the fault to the Linux + // kernel and it will see that the permissions in the page table are + // correct. Therefore, we flush TLB entries on ATS write faults. + flush_tlb_write_faults(gpu_va_space, start, length, client_type); } else { - current_entry->is_invalid_prefetch = true; + uvm_page_mask_region_fill(reads_serviced_mask, subregion); } - - // Do not fail overall fault servicing due to logical errors - status = NV_OK; } - // The Linux kernel never invalidates TLB entries on mapping permission - // upgrade. This is a problem if the GPU has cached entries with the old - // permission. The GPU will re-fetch the entry if the PTE is invalid and - // page size is not 4K (this is the case on P9). However, if a page gets - // upgraded from R/O to R/W and GPU has the PTEs cached with R/O - // permissions we will enter an infinite loop because we just forward the - // fault to the Linux kernel and it will see that the permissions in the - // page table are correct. Therefore, we flush TLB entries on ATS write - // faults. - if (!current_entry->is_fatal && current_entry->fault_access_type > UVM_FAULT_ACCESS_TYPE_READ) { - if (!ats_invalidate->write_faults_in_batch) { - uvm_tlb_batch_begin(&gpu_va_space->page_tables, &ats_invalidate->write_faults_tlb_batch); - ats_invalidate->write_faults_in_batch = true; - } + // Remove write faults from read_fault_mask + uvm_page_mask_andnot(read_fault_mask, read_fault_mask, write_fault_mask); + + for_each_va_block_subregion_in_mask(subregion, read_fault_mask, region) { + NvU64 start = base + (subregion.first * PAGE_SIZE); + size_t length = uvm_va_block_region_num_pages(subregion) * PAGE_SIZE; + + UVM_ASSERT(start >= vma->vm_start); + UVM_ASSERT((start + length) <= vma->vm_end); - uvm_tlb_batch_invalidate(&ats_invalidate->write_faults_tlb_batch, - current_entry->fault_address, - PAGE_SIZE, - PAGE_SIZE, - UVM_MEMBAR_NONE); + status = service_ats_faults(gpu_va_space, vma, start, length, UVM_FAULT_ACCESS_TYPE_READ, client_type); + if (status != NV_OK) + return status; + + uvm_page_mask_region_fill(faults_serviced_mask, subregion); } return status; } +bool uvm_ats_check_in_gmmu_region(uvm_va_space_t *va_space, NvU64 address, uvm_va_range_t *next) +{ + uvm_va_range_t *prev; + NvU64 gmmu_region_base = UVM_ALIGN_DOWN(address, UVM_GMMU_ATS_GRANULARITY); + + UVM_ASSERT(va_space); + + if (next) { + if (next->node.start <= gmmu_region_base + UVM_GMMU_ATS_GRANULARITY - 1) + return true; + + prev = uvm_va_range_container(uvm_range_tree_prev(&va_space->va_range_tree, &next->node)); + } + else { + // No VA range exists after address, so check the last VA range in the + // tree. + prev = uvm_va_range_container(uvm_range_tree_last(&va_space->va_range_tree)); + } + + return prev && (prev->node.end >= gmmu_region_base); +} + NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, uvm_ats_fault_invalidate_t *ats_invalidate, uvm_tracker_t *out_tracker) @@ -287,3 +311,4 @@ NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, return status; } + diff --git a/kernel-open/nvidia-uvm/uvm_ats_faults.h b/kernel-open/nvidia-uvm/uvm_ats_faults.h index db8784d6ca..ca67387e74 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_faults.h +++ b/kernel-open/nvidia-uvm/uvm_ats_faults.h @@ -25,10 +25,31 @@ #include "uvm_lock.h" #include "uvm_global.h" #include "uvm_va_space.h" +#include "uvm_gpu.h" -NV_STATUS uvm_ats_service_fault_entry(uvm_gpu_va_space_t *gpu_va_space, - uvm_fault_buffer_entry_t *current_entry, - uvm_ats_fault_invalidate_t *ats_invalidate); +// Service ATS faults in the range (base, base + UVM_VA_BLOCK_SIZE) with service +// type for individual pages in the range requested by page masks set in +// ats_context->read_fault_mask/write_fault_mask. base must be aligned to +// UVM_VA_BLOCK_SIZE. The caller is responsible for ensuring that faulting +// addresses fall completely within the VMA. The caller is also responsible for +// ensuring that the faulting addresses don't overlap a GMMU region. (See +// uvm_ats_check_in_gmmu_region). The caller is also responsible for handling +// any errors returned by this function (fault cancellations etc.). +// +// Returns the fault service status in ats_context->faults_serviced_mask. In +// addition, ats_context->reads_serviced_mask returns whether read servicing +// worked on write faults iff the read service was also requested in the +// corresponding bit in read_fault_mask. These returned masks are only valid if +// the return status is NV_OK. Status other than NV_OK indicate system global +// fault servicing failures. +NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_fault_context_t *ats_context); + +// Return whether there are any VA ranges (and thus GMMU mappings) within the +// UVM_GMMU_ATS_GRANULARITY-aligned region containing address. +bool uvm_ats_check_in_gmmu_region(uvm_va_space_t *va_space, NvU64 address, uvm_va_range_t *next); // This function performs pending TLB invalidations for ATS and clears the // ats_invalidate->write_faults_in_batch flag diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.c b/kernel-open/nvidia-uvm/uvm_ats_sva.c new file mode 100644 index 0000000000..f9753d2c1a --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.c @@ -0,0 +1,156 @@ +/******************************************************************************* + Copyright (c) 2018-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_ats_sva.h" + +#if UVM_ATS_SVA_SUPPORTED() + +#include "uvm_gpu.h" +#include "uvm_va_space.h" +#include "uvm_va_space_mm.h" + +#include +#include + +// linux/sched/mm.h is needed for mmget_not_zero and mmput to get the mm +// reference required for the iommu_sva_bind_device() call. This header is not +// present in all the supported versions. Instead of adding a conftest just for +// this header file, use UVM_ATS_SVA_SUPPORTED(). +#include + +// iommu_sva_bind_device() removed drvdata paramter with commit +// 942fd5435dccb273f90176b046ae6bbba60cfbd8 (10/31/2022). +#if defined(NV_IOMMU_SVA_BIND_DEVICE_HAS_DRVDATA_ARG) +#define UVM_IOMMU_SVA_BIND_DEVICE(dev, mm) iommu_sva_bind_device(dev, mm, NULL) +#else +#define UVM_IOMMU_SVA_BIND_DEVICE(dev, mm) iommu_sva_bind_device(dev, mm) +#endif + +NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) +{ + int ret; + + ret = iommu_dev_enable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); + + return errno_to_nv_status(ret); +} + +void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu) +{ + iommu_dev_disable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); +} + +NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) +{ + NV_STATUS status = NV_OK; + struct iommu_sva *iommu_handle; + struct pci_dev *pci_dev = gpu_va_space->gpu->parent->pci_dev; + uvm_sva_gpu_va_space_t *sva_gpu_va_space = &gpu_va_space->ats.sva; + struct mm_struct *mm = gpu_va_space->va_space->va_space_mm.mm; + + UVM_ASSERT(gpu_va_space->ats.enabled); + UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_INIT); + UVM_ASSERT(mm); + + // The mmput() below may trigger the kernel's mm teardown with exit_mmap() + // and uvm_va_space_mm_shutdown() and uvm_vm_close_managed() in that path + // will try to grab the va_space lock and deadlock if va_space was already + // locked. + uvm_assert_unlocked_order(UVM_LOCK_ORDER_VA_SPACE); + + // iommu_sva_bind_device() requires the mm reference to be acquired. Since + // the mm is already retained, mm is still valid but may be inactive since + // mm_users can still be zero since UVM doesn't use mm_users and maintains a + // separate refcount (retained_count) for the mm in va_space_mm. See the + // block comment in va_space_mm.c for more details. So, return an error if + // mm_users is zero. + if (!mmget_not_zero(mm)) + return NV_ERR_PAGE_TABLE_NOT_AVAIL; + + // Multiple calls for the {same pci_dev, mm} pair are refcounted by the ARM + // SMMU Layer. + iommu_handle = UVM_IOMMU_SVA_BIND_DEVICE(&pci_dev->dev, mm); + if (IS_ERR(iommu_handle)) { + status = errno_to_nv_status(PTR_ERR(iommu_handle)); + goto out; + } + + // If this is not the first bind of the gpu in the mm, then the previously + // stored iommu_handle in the gpu_va_space must match the handle returned by + // iommu_sva_bind_device(). + if (sva_gpu_va_space->iommu_handle) { + UVM_ASSERT(sva_gpu_va_space->iommu_handle == iommu_handle); + nv_kref_get(&sva_gpu_va_space->kref); + } + else { + sva_gpu_va_space->iommu_handle = iommu_handle; + nv_kref_init(&sva_gpu_va_space->kref); + } + +out: + mmput(mm); + return status; +} + +static void uvm_sva_reset_iommu_handle(nv_kref_t *nv_kref) +{ + uvm_sva_gpu_va_space_t *sva_gpu_va_space = container_of(nv_kref, uvm_sva_gpu_va_space_t, kref); + sva_gpu_va_space->iommu_handle = NULL; +} + +void uvm_ats_sva_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space) +{ + uvm_sva_gpu_va_space_t *sva_gpu_va_space = &gpu_va_space->ats.sva; + + // ARM SMMU layer decrements the refcount for the {pci_dev, mm} pair. + // The actual unbind happens only when the refcount reaches zero. + if (sva_gpu_va_space->iommu_handle) { + iommu_sva_unbind_device(sva_gpu_va_space->iommu_handle); + nv_kref_put(&sva_gpu_va_space->kref, uvm_sva_reset_iommu_handle); + } +} + +NV_STATUS uvm_ats_sva_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) +{ + NvU32 pasid; + NV_STATUS status = NV_OK; + uvm_sva_gpu_va_space_t *sva_gpu_va_space = &gpu_va_space->ats.sva; + + // A successful iommu_sva_bind_device() should have preceded this call. + UVM_ASSERT(sva_gpu_va_space->iommu_handle); + + pasid = iommu_sva_get_pasid(sva_gpu_va_space->iommu_handle); + if (pasid == IOMMU_PASID_INVALID) + status = errno_to_nv_status(ENODEV); + else + gpu_va_space->ats.pasid = pasid; + + return status; +} + +void uvm_ats_sva_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) +{ + gpu_va_space->ats.pasid = -1U; +} + +#endif // UVM_ATS_SVA_SUPPORTED() diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.h b/kernel-open/nvidia-uvm/uvm_ats_sva.h new file mode 100644 index 0000000000..120ecfbf51 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.h @@ -0,0 +1,112 @@ +/******************************************************************************* + Copyright (c) 2018-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef __UVM_ATS_SVA_H__ +#define __UVM_ATS_SVA_H__ + +#include "uvm_gpu.h" +#include "uvm_forward_decl.h" + +#include + +// For ATS support on aarch64, arm_smmu_sva_bind() is needed for +// iommu_sva_bind_device() calls. Unfortunately, arm_smmu_sva_bind() is not +// conftest-able. We instead look for the presence of ioasid_get() or +// mm_pasid_set(). ioasid_get() was added in the same patch series as +// arm_smmu_sva_bind() and removed in v6.0. mm_pasid_set() was added in the +// same patch as the removal of ioasid_get(). We assume the presence of +// arm_smmu_sva_bind() if ioasid_get(v5.11 - v5.17) or mm_pasid_set(v5.18+) is +// present. +// +// arm_smmu_sva_bind() was added with commit +// 32784a9562fb0518b12e9797ee2aec52214adf6f and ioasid_get() was added with +// commit cb4789b0d19ff231ce9f73376a023341300aed96 (11/23/2020). Commit +// 701fac40384f07197b106136012804c3cae0b3de (02/15/2022) removed ioasid_get() +// and added mm_pasid_set(). + #if UVM_CAN_USE_MMU_NOTIFIERS() && (defined(NV_IOASID_GET_PRESENT) || defined(NV_MM_PASID_SET_PRESENT)) + #define UVM_ATS_SVA_SUPPORTED() 1 + #else + #define UVM_ATS_SVA_SUPPORTED() 0 + #endif + +typedef struct +{ + int placeholder; +} uvm_sva_va_space_t; + +typedef struct +{ + // Reference count for the iommu_handle + nv_kref_t kref; + struct iommu_sva *iommu_handle; +} uvm_sva_gpu_va_space_t; + +#if UVM_ATS_SVA_SUPPORTED() + NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu); + void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu); + + // LOCKING: mmap_lock must be lockable + // VA space lock must not be held. + NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space); + + // LOCKING: VA space lock must not be held. + void uvm_ats_sva_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space); + + // LOCKING: None + NV_STATUS uvm_ats_sva_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space); + + // LOCKING: None + void uvm_ats_sva_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space); +#else + static NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) + { + return NV_OK; + } + + static void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu) + { + + } + + static NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space) + { + return NV_OK; + } + + static void uvm_ats_sva_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space) + { + + } + + static NV_STATUS uvm_ats_sva_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) + { + return NV_OK; + } + + static void uvm_ats_sva_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) + { + + } +#endif // UVM_ATS_SVA_SUPPORTED + +#endif // __UVM_ATS_SVA_H__ diff --git a/kernel-open/nvidia-uvm/uvm_ce_test.c b/kernel-open/nvidia-uvm/uvm_ce_test.c index 5bb1c106da..eb7ef249c2 100644 --- a/kernel-open/nvidia-uvm/uvm_ce_test.c +++ b/kernel-open/nvidia-uvm/uvm_ce_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -31,6 +31,7 @@ #include "uvm_va_space.h" #include "uvm_rm_mem.h" #include "uvm_mem.h" +#include "uvm_gpu.h" #define CE_TEST_MEM_SIZE (2 * 1024 * 1024) #define CE_TEST_MEM_END_SIZE 32 @@ -53,6 +54,11 @@ static NV_STATUS test_non_pipelined(uvm_gpu_t *gpu) uvm_push_t push; bool is_proxy; + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, CE_TEST_MEM_SIZE, 0, &host_mem); TEST_CHECK_GOTO(status == NV_OK, done); host_ptr = (NvU32 *)uvm_rm_mem_get_cpu_va(host_mem); @@ -67,7 +73,7 @@ static NV_STATUS test_non_pipelined(uvm_gpu_t *gpu) TEST_CHECK_GOTO(status == NV_OK, done); is_proxy = uvm_channel_is_proxy(push.channel); - host_mem_gpu_va = uvm_rm_mem_get_gpu_va(host_mem, gpu, is_proxy); + host_mem_gpu_va = uvm_rm_mem_get_gpu_va(host_mem, gpu, is_proxy).address; // All of the following CE transfers are done from a single (L)CE and // disabling pipelining is enough to order them when needed. Only push_end @@ -75,7 +81,7 @@ static NV_STATUS test_non_pipelined(uvm_gpu_t *gpu) // Initialize to a bad value for (i = 0; i < CE_TEST_MEM_COUNT; ++i) { - mem_gpu_va = uvm_rm_mem_get_gpu_va(mem[i], gpu, is_proxy); + mem_gpu_va = uvm_rm_mem_get_gpu_va(mem[i], gpu, is_proxy).address; uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); @@ -84,7 +90,7 @@ static NV_STATUS test_non_pipelined(uvm_gpu_t *gpu) // Set the first buffer to 1 uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - mem_gpu_va = uvm_rm_mem_get_gpu_va(mem[0], gpu, is_proxy); + mem_gpu_va = uvm_rm_mem_get_gpu_va(mem[0], gpu, is_proxy).address; gpu->parent->ce_hal->memset_v_4(&push, mem_gpu_va, 1, CE_TEST_MEM_SIZE); for (i = 0; i < CE_TEST_MEM_COUNT; ++i) { @@ -92,9 +98,9 @@ static NV_STATUS test_non_pipelined(uvm_gpu_t *gpu) if (dst == CE_TEST_MEM_COUNT) dst_va = host_mem_gpu_va; else - dst_va = uvm_rm_mem_get_gpu_va(mem[dst], gpu, is_proxy); + dst_va = uvm_rm_mem_get_gpu_va(mem[dst], gpu, is_proxy).address; - src_va = uvm_rm_mem_get_gpu_va(mem[i], gpu, is_proxy); + src_va = uvm_rm_mem_get_gpu_va(mem[i], gpu, is_proxy).address; // The first memcpy needs to be non-pipelined as otherwise the previous // memset/memcpy to the source may not be done yet. @@ -168,6 +174,11 @@ static NV_STATUS test_membar(uvm_gpu_t *gpu) uvm_push_t push; NvU32 value; + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, sizeof(NvU32), 0, &host_mem); TEST_CHECK_GOTO(status == NV_OK, done); host_ptr = (NvU32 *)uvm_rm_mem_get_cpu_va(host_mem); @@ -176,7 +187,7 @@ static NV_STATUS test_membar(uvm_gpu_t *gpu) status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, &push, "Membar test"); TEST_CHECK_GOTO(status == NV_OK, done); - host_mem_gpu_va = uvm_rm_mem_get_gpu_va(host_mem, gpu, uvm_channel_is_proxy(push.channel)); + host_mem_gpu_va = uvm_rm_mem_get_gpu_va(host_mem, gpu, uvm_channel_is_proxy(push.channel)).address; for (i = 0; i < REDUCTIONS; ++i) { uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); @@ -327,6 +338,11 @@ static NV_STATUS test_memcpy_and_memset_inner(uvm_gpu_t *gpu, return NV_OK; } + if (!gpu->parent->ce_hal->memcopy_is_valid(&push, dst, src)) { + TEST_NV_CHECK_RET(uvm_push_end_and_wait(&push)); + return NV_OK; + } + // The input virtual addresses exist in UVM's internal address space, not // the proxy address space if (uvm_channel_is_proxy(push.channel)) { @@ -334,6 +350,16 @@ static NV_STATUS test_memcpy_and_memset_inner(uvm_gpu_t *gpu, return NV_ERR_INVALID_STATE; } + // If physical accesses aren't supported, silently convert to virtual to + // test the flat mapping. + TEST_CHECK_RET(gpu_verif_addr.is_virtual); + + if (!src.is_virtual) + src = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(src.aperture, src.address)); + + if (!dst.is_virtual) + dst = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(dst.aperture, dst.address)); + // Memset src with the appropriate element size, then memcpy to dst and from // dst to the verif location (physical sysmem). @@ -383,17 +409,17 @@ static NV_STATUS test_memcpy_and_memset(uvm_gpu_t *gpu) uvm_mem_t *gpu_uvm_mem = NULL; uvm_rm_mem_t *sys_rm_mem = NULL; uvm_rm_mem_t *gpu_rm_mem = NULL; - uvm_gpu_address_t gpu_addresses[4]; - NvU64 gpu_va; - size_t size; + uvm_gpu_address_t gpu_addresses[4] = {0}; + size_t size = gpu->big_page.internal_size; static const size_t element_sizes[] = {1, 4, 8}; const size_t iterations = 4; size_t i, j, k, s; uvm_mem_alloc_params_t mem_params = {0}; - size = gpu->big_page.internal_size; - - TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, &verif_mem), done); + if (uvm_conf_computing_mode_enabled(gpu)) + TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(size, gpu, current->mm, &verif_mem), done); + else + TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, &verif_mem), done); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, gpu), done); gpu_verif_addr = uvm_mem_gpu_address_virtual_kernel(verif_mem, gpu); @@ -432,18 +458,27 @@ static NV_STATUS test_memcpy_and_memset(uvm_gpu_t *gpu) // Virtual address (in UVM's internal address space) backed by vidmem TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_GPU, size, 0, &gpu_rm_mem), done); is_proxy_va_space = false; - gpu_va = uvm_rm_mem_get_gpu_va(gpu_rm_mem, gpu, is_proxy_va_space); - gpu_addresses[2] = uvm_gpu_address_virtual(gpu_va); + gpu_addresses[2] = uvm_rm_mem_get_gpu_va(gpu_rm_mem, gpu, is_proxy_va_space); // Virtual address (in UVM's internal address space) backed by sysmem TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &sys_rm_mem), done); - gpu_va = uvm_rm_mem_get_gpu_va(sys_rm_mem, gpu, is_proxy_va_space); - gpu_addresses[3] = uvm_gpu_address_virtual(gpu_va); + gpu_addresses[3] = uvm_rm_mem_get_gpu_va(sys_rm_mem, gpu, is_proxy_va_space); for (i = 0; i < iterations; ++i) { for (j = 0; j < ARRAY_SIZE(gpu_addresses); ++j) { for (k = 0; k < ARRAY_SIZE(gpu_addresses); ++k) { for (s = 0; s < ARRAY_SIZE(element_sizes); s++) { + // Because gpu_verif_addr is in sysmem, when the Confidential + // Computing feature is enabled, only the following cases are + // valid. + // + // TODO: Bug 3839176: the test partially waived on + // Confidential Computing because it assumes that GPU can + // access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu) && + !(gpu_addresses[k].is_unprotected && gpu_addresses[j].is_unprotected)) { + continue; + } TEST_NV_CHECK_GOTO(test_memcpy_and_memset_inner(gpu, gpu_addresses[k], gpu_addresses[j], @@ -514,6 +549,11 @@ static NV_STATUS test_semaphore_reduction_inc(uvm_gpu_t *gpu) // Semaphore reduction needs 1 word (4 bytes). const size_t size = sizeof(NvU32); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = test_semaphore_alloc_sem(gpu, size, &mem); TEST_CHECK_RET(status == NV_OK); @@ -561,6 +601,11 @@ static NV_STATUS test_semaphore_release(uvm_gpu_t *gpu) // Semaphore release needs 1 word (4 bytes). const size_t size = sizeof(NvU32); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = test_semaphore_alloc_sem(gpu, size, &mem); TEST_CHECK_RET(status == NV_OK); @@ -610,6 +655,11 @@ static NV_STATUS test_semaphore_timestamp(uvm_gpu_t *gpu) // The semaphore is 4 words long (16 bytes). const size_t size = 16; + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = test_semaphore_alloc_sem(gpu, size, &mem); TEST_CHECK_RET(status == NV_OK); @@ -646,6 +696,517 @@ static NV_STATUS test_semaphore_timestamp(uvm_gpu_t *gpu) return status; } +static bool mem_match(uvm_mem_t *mem1, uvm_mem_t *mem2, size_t size) +{ + void *mem1_addr; + void *mem2_addr; + + UVM_ASSERT(uvm_mem_is_sysmem(mem1)); + UVM_ASSERT(uvm_mem_is_sysmem(mem2)); + UVM_ASSERT(mem1->size >= size); + UVM_ASSERT(mem2->size >= size); + + mem1_addr = uvm_mem_get_cpu_addr_kernel(mem1); + mem2_addr = uvm_mem_get_cpu_addr_kernel(mem2); + + return !memcmp(mem1_addr, mem2_addr, size); +} + +static NV_STATUS zero_vidmem(uvm_mem_t *mem) +{ + uvm_push_t push; + uvm_gpu_address_t gpu_address; + uvm_gpu_t *gpu = mem->backing_gpu; + + UVM_ASSERT(uvm_mem_is_vidmem(mem)); + + TEST_NV_CHECK_RET(uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_INTERNAL, &push, "zero vidmem")); + + gpu_address = uvm_mem_gpu_address_virtual_kernel(mem, gpu); + gpu->parent->ce_hal->memset_1(&push, gpu_address, 0, mem->size); + + TEST_NV_CHECK_RET(uvm_push_end_and_wait(&push)); + + return NV_OK; +} + +static void write_range_cpu(uvm_mem_t *mem, NvU64 base_val) +{ + NvU64 *mem_cpu_va; + unsigned i; + + UVM_ASSERT(uvm_mem_is_sysmem(mem)); + UVM_ASSERT(IS_ALIGNED(mem->size, sizeof(*mem_cpu_va))); + + mem_cpu_va = (NvU64 *) uvm_mem_get_cpu_addr_kernel(mem); + + for (i = 0; i < (mem->size / sizeof(*mem_cpu_va)); i++) + mem_cpu_va[i] = base_val++; +} + +static NV_STATUS alloc_vidmem_protected(uvm_gpu_t *gpu, uvm_mem_t **mem, size_t size) +{ + NV_STATUS status; + + UVM_ASSERT(mem); + + *mem = NULL; + + TEST_NV_CHECK_RET(uvm_mem_alloc_vidmem_protected(size, gpu, mem)); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(*mem, gpu), err); + TEST_NV_CHECK_GOTO(zero_vidmem(*mem), err); + + return NV_OK; + +err: + uvm_mem_free(*mem); + return status; +} + +static NV_STATUS alloc_sysmem_unprotected(uvm_gpu_t *gpu, uvm_mem_t **mem, size_t size) +{ + NV_STATUS status; + + UVM_ASSERT(mem); + + *mem = NULL; + + TEST_NV_CHECK_RET(uvm_mem_alloc_sysmem_dma(size, gpu, NULL, mem)); + TEST_NV_CHECK_GOTO(uvm_mem_map_cpu_kernel(*mem), err); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(*mem, gpu), err); + + memset(uvm_mem_get_cpu_addr_kernel(*mem), 0, (*mem)->size); + + return NV_OK; + +err: + uvm_mem_free(*mem); + return status; +} + +static void cpu_encrypt(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size) +{ + size_t offset = 0; + char *src_plain = (char *) uvm_mem_get_cpu_addr_kernel(src_mem); + char *dst_cipher = (char *) uvm_mem_get_cpu_addr_kernel(dst_mem); + char *auth_tag_buffer = (char *) uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + while (offset < size) { + uvm_conf_computing_cpu_encrypt(channel, dst_cipher, src_plain, NULL, copy_size, auth_tag_buffer); + + offset += copy_size; + dst_cipher += copy_size; + src_plain += copy_size; + auth_tag_buffer += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } +} + +static void cpu_acquire_encryption_ivs(uvm_channel_t *channel, + size_t size, + NvU32 copy_size, + UvmCslIv *ivs) +{ + size_t offset = 0; + int i = 0; + + for (; offset < size; offset += copy_size) + uvm_conf_computing_acquire_encryption_iv(channel, &ivs[i++]); +} + +static void cpu_encrypt_rev(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size, + UvmCslIv *encrypt_iv) +{ + char *src_plain = (char *) uvm_mem_get_cpu_addr_kernel(src_mem); + char *dst_cipher = (char *) uvm_mem_get_cpu_addr_kernel(dst_mem); + char *auth_tag_buffer = (char *) uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + int i; + + // CPU encrypt order is the opposite of the GPU decrypt order + for (i = (size / copy_size) - 1; i >= 0; i--) { + uvm_conf_computing_cpu_encrypt(channel, + dst_cipher + i * copy_size, + src_plain + i * copy_size, + encrypt_iv + i, + copy_size, + auth_tag_buffer + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); + } +} + +static NV_STATUS cpu_decrypt_in_order(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + const UvmCslIv *decrypt_iv, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size) +{ + size_t i; + char *dst_plain = (char *) uvm_mem_get_cpu_addr_kernel(dst_mem); + char *src_cipher = (char *) uvm_mem_get_cpu_addr_kernel(src_mem); + char *auth_tag_buffer = (char *) uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + for (i = 0; i < size / copy_size; i++) { + TEST_NV_CHECK_RET(uvm_conf_computing_cpu_decrypt(channel, + dst_plain + i * copy_size, + src_cipher + i * copy_size, + decrypt_iv + i, + copy_size, + auth_tag_buffer + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE)); + } + + return NV_OK; +} +static NV_STATUS cpu_decrypt_out_of_order(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + const UvmCslIv *decrypt_iv, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size) +{ + int i; + char *dst_plain = (char *) uvm_mem_get_cpu_addr_kernel(dst_mem); + char *src_cipher = (char *) uvm_mem_get_cpu_addr_kernel(src_mem); + char *auth_tag_buffer = (char *) uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + UVM_ASSERT((size / copy_size) <= INT_MAX); + + // CPU decrypt order is the opposite of the GPU decrypt order + for (i = (size / copy_size) - 1; i >= 0; i--) { + TEST_NV_CHECK_RET(uvm_conf_computing_cpu_decrypt(channel, + dst_plain + i * copy_size, + src_cipher + i * copy_size, + decrypt_iv + i, + copy_size, + auth_tag_buffer + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE)); + } + + return NV_OK; +} + +// GPU address to use as source or destination in CE decrypt/encrypt operations. +// If the uvm_mem backing storage is contiguous in the [offset, offset + size) +// interval, the physical address gets priority over the virtual counterpart. +static uvm_gpu_address_t gpu_address(uvm_mem_t *mem, uvm_gpu_t *gpu, NvU64 offset, NvU32 size) +{ + uvm_gpu_address_t gpu_virtual_address; + + if (uvm_mem_is_physically_contiguous(mem, offset, size)) + return uvm_mem_gpu_address_physical(mem, gpu, offset, size); + + gpu_virtual_address = uvm_mem_gpu_address_virtual_kernel(mem, gpu); + gpu_virtual_address.address += offset; + + return gpu_virtual_address; +} + +// Automatically get the correct address for the authentication tag. The +// addressing mode of the tag should match that of the reference address +// (destination pointer for GPU encrypt, source pointer for GPU encrypt) +static uvm_gpu_address_t auth_tag_gpu_address(uvm_mem_t *auth_tag_mem, + uvm_gpu_t *gpu, + size_t offset, + uvm_gpu_address_t reference) +{ + uvm_gpu_address_t auth_tag_gpu_address; + + if (!reference.is_virtual) + return uvm_mem_gpu_address_physical(auth_tag_mem, gpu, offset, UVM_CONF_COMPUTING_AUTH_TAG_SIZE); + + auth_tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(auth_tag_mem, gpu); + auth_tag_gpu_address.address += offset; + + return auth_tag_gpu_address; +} + +// Note: no membar is issued in any of the GPU transfers (encryptions) +static void gpu_encrypt(uvm_push_t *push, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + UvmCslIv *decrypt_iv, + size_t size, + NvU32 copy_size) +{ + size_t i; + size_t num_iterations = size / copy_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + for (i = 0; i < num_iterations; i++) { + uvm_gpu_address_t dst_cipher = gpu_address(dst_mem, gpu, i * copy_size, copy_size); + uvm_gpu_address_t src_plain = gpu_address(src_mem, gpu, i * copy_size, copy_size); + uvm_gpu_address_t auth_tag = auth_tag_gpu_address(auth_tag_mem, + gpu, + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + dst_cipher); + + uvm_conf_computing_log_gpu_encryption(push->channel, decrypt_iv); + + if (i > 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + gpu->parent->ce_hal->encrypt(push, dst_cipher, src_plain, copy_size, auth_tag); + decrypt_iv++; + } +} + +// Note: no membar is issued in any of the GPU transfers (decryptions) +static void gpu_decrypt(uvm_push_t *push, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + NvU32 copy_size) +{ + size_t i; + size_t num_iterations = size / copy_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + for (i = 0; i < num_iterations; i++) { + uvm_gpu_address_t dst_plain = gpu_address(dst_mem, gpu, i * copy_size, copy_size); + uvm_gpu_address_t src_cipher = gpu_address(src_mem, gpu, i * copy_size, copy_size); + uvm_gpu_address_t auth_tag = auth_tag_gpu_address(auth_tag_mem, + gpu, + i * UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + src_cipher); + + if (i > 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + gpu->parent->ce_hal->decrypt(push, dst_plain, src_cipher, copy_size, auth_tag); + } +} + +static NV_STATUS test_cpu_to_gpu_roundtrip(uvm_gpu_t *gpu, + uvm_channel_type_t decrypt_channel_type, + uvm_channel_type_t encrypt_channel_type, + size_t size, + NvU32 copy_size, + bool decrypt_in_order, + bool encrypt_in_order) +{ + uvm_push_t push; + NvU64 init_value; + NV_STATUS status = NV_OK; + uvm_mem_t *src_plain = NULL; + uvm_mem_t *src_cipher = NULL; + uvm_mem_t *dst_cipher = NULL; + uvm_mem_t *dst_plain_gpu = NULL; + uvm_mem_t *dst_plain = NULL; + uvm_mem_t *auth_tag_mem = NULL; + size_t auth_tag_buffer_size = (size / copy_size) * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + UvmCslIv *decrypt_iv = NULL; + UvmCslIv *encrypt_iv = NULL; + uvm_tracker_t tracker; + size_t src_plain_size; + + TEST_CHECK_RET(copy_size <= size); + TEST_CHECK_RET(IS_ALIGNED(size, copy_size)); + + uvm_tracker_init(&tracker); + + decrypt_iv = uvm_kvmalloc_zero((size / copy_size) * sizeof(UvmCslIv)); + if (!decrypt_iv) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + encrypt_iv = uvm_kvmalloc_zero((size / copy_size) * sizeof(UvmCslIv)); + if (!encrypt_iv) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &src_cipher, size), out); + TEST_NV_CHECK_GOTO(alloc_vidmem_protected(gpu, &dst_plain_gpu, size), out); + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &dst_cipher, size), out); + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &dst_plain, size), out); + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &auth_tag_mem, auth_tag_buffer_size), out); + + // The plaintext CPU buffer size should fit the initialization value + src_plain_size = UVM_ALIGN_UP(size, sizeof(init_value)); + TEST_NV_CHECK_GOTO(alloc_sysmem_unprotected(gpu, &src_plain, src_plain_size), out); + + // Initialize the plaintext CPU buffer using a value that uniquely + // identifies the given inputs + TEST_CHECK_GOTO((((NvU64) size) < (1ULL << 63)), out); + init_value = ((NvU64) decrypt_in_order << 63) | ((NvU64) size) | ((NvU64) copy_size); + write_range_cpu(src_plain, init_value); + + TEST_NV_CHECK_GOTO(uvm_push_begin(gpu->channel_manager, + decrypt_channel_type, + &push, + "CPU > GPU decrypt"), + out); + + // CPU (decrypted) > CPU (encrypted), using CPU, if in-order + // acquire IVs if not in-order + if (encrypt_in_order) + cpu_encrypt(push.channel, src_cipher, src_plain, auth_tag_mem, size, copy_size); + else + cpu_acquire_encryption_ivs(push.channel, size, copy_size, encrypt_iv); + + // CPU (encrypted) > GPU (decrypted), using GPU + gpu_decrypt(&push, dst_plain_gpu, src_cipher, auth_tag_mem, size, copy_size); + + // Use acquired IVs to encrypt in reverse order + if (!encrypt_in_order) + cpu_encrypt_rev(push.channel, src_cipher, src_plain, auth_tag_mem, size, copy_size, encrypt_iv); + + uvm_push_end(&push); + TEST_NV_CHECK_GOTO(uvm_tracker_add_push(&tracker, &push), out); + + // GPU (decrypted) > CPU (encrypted), using GPU + TEST_NV_CHECK_GOTO(uvm_push_begin_acquire(gpu->channel_manager, + encrypt_channel_type, + &tracker, + &push, + "GPU > CPU encrypt"), + out); + + gpu_encrypt(&push, dst_cipher, dst_plain_gpu, auth_tag_mem, decrypt_iv, size, copy_size); + + TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), out); + + TEST_CHECK_GOTO(!mem_match(src_plain, src_cipher, size), out); + + TEST_CHECK_GOTO(!mem_match(dst_cipher, src_plain, size), out); + + // CPU (encrypted) > CPU (decrypted), using CPU + if (decrypt_in_order) { + TEST_NV_CHECK_GOTO(cpu_decrypt_in_order(push.channel, + dst_plain, + dst_cipher, + decrypt_iv, + auth_tag_mem, + size, + copy_size), + out); + } + else { + TEST_NV_CHECK_GOTO(cpu_decrypt_out_of_order(push.channel, + dst_plain, + dst_cipher, + decrypt_iv, + auth_tag_mem, + size, + copy_size), + out); + } + + TEST_CHECK_GOTO(mem_match(src_plain, dst_plain, size), out); + +out: + uvm_mem_free(auth_tag_mem); + uvm_mem_free(dst_plain); + uvm_mem_free(dst_plain_gpu); + uvm_mem_free(dst_cipher); + uvm_mem_free(src_cipher); + uvm_mem_free(src_plain); + uvm_tracker_deinit(&tracker); + uvm_kvfree(decrypt_iv); + uvm_kvfree(encrypt_iv); + + return status; +} + +static NV_STATUS test_encryption_decryption(uvm_gpu_t *gpu, + uvm_channel_type_t decrypt_channel_type, + uvm_channel_type_t encrypt_channel_type) +{ + bool cpu_decrypt_in_order = true; + bool cpu_encrypt_in_order = true; + size_t size[] = {UVM_PAGE_SIZE_4K, UVM_PAGE_SIZE_4K * 2, UVM_PAGE_SIZE_2M}; + size_t copy_size[] = {UVM_PAGE_SIZE_4K, UVM_PAGE_SIZE_64K, UVM_PAGE_SIZE_2M}; + unsigned i; + + struct { + bool encrypt_in_order; + bool decrypt_in_order; + } orders[] = {{true, true}, {true, false}, {false, true}, {false, false}}; + + struct { + size_t size; + NvU32 copy_size; + } small_sizes[] = {{1, 1}, {3, 1}, {8, 1}, {2, 2}, {8, 4}, {UVM_PAGE_SIZE_4K - 8, 8}, {UVM_PAGE_SIZE_4K + 8, 8}}; + + // Only Confidential Computing uses CE encryption/decryption + if (!uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + // Use a size, and copy size, that are not a multiple of common page sizes. + for (i = 0; i < ARRAY_SIZE(small_sizes); ++i) { + // Skip tests that need large pushbuffer on WLC. Secure work launch + // needs to do at least one decrypt operation so tests that only need + // one operation work ok. Tests using more operations might overflow + // UVM_MAX_WLC_PUSH_SIZE. + if (encrypt_channel_type == UVM_CHANNEL_TYPE_WLC && (small_sizes[i].size / small_sizes[i].copy_size > 1)) + continue; + + TEST_NV_CHECK_RET(test_cpu_to_gpu_roundtrip(gpu, + decrypt_channel_type, + encrypt_channel_type, + small_sizes[i].size, + small_sizes[i].copy_size, + cpu_decrypt_in_order, + cpu_encrypt_in_order)); + } + + // Use sizes, and copy sizes, that are a multiple of common page sizes. + // This is the most typical usage of encrypt/decrypt in the UVM driver. + for (i = 0; i < ARRAY_SIZE(orders); ++i) { + unsigned j; + + cpu_encrypt_in_order = orders[i].encrypt_in_order; + cpu_decrypt_in_order = orders[i].decrypt_in_order; + + for (j = 0; j < ARRAY_SIZE(size); ++j) { + unsigned k; + + for (k = 0; k < ARRAY_SIZE(copy_size); ++k) { + if (copy_size[k] > size[j]) + continue; + + // Skip tests that need large pushbuffer on WLC. Secure work + // launch needs to do at least one decrypt operation so tests + // that only need one operation work ok. Tests using more + // operations might overflow UVM_MAX_WLC_PUSH_SIZE. + if (encrypt_channel_type == UVM_CHANNEL_TYPE_WLC && (size[j] / copy_size[k] > 1)) + continue; + + // There is no difference between in-order and out-of-order + // decryption when encrypting once. + if ((copy_size[k] == size[j]) && !cpu_decrypt_in_order) + continue; + + TEST_NV_CHECK_RET(test_cpu_to_gpu_roundtrip(gpu, + decrypt_channel_type, + encrypt_channel_type, + size[j], + copy_size[k], + cpu_decrypt_in_order, + cpu_encrypt_in_order)); + } + } + } + + return NV_OK; +} + static NV_STATUS test_ce(uvm_va_space_t *va_space, bool skipTimestampTest) { uvm_gpu_t *gpu; @@ -660,6 +1221,8 @@ static NV_STATUS test_ce(uvm_va_space_t *va_space, bool skipTimestampTest) if (!skipTimestampTest) TEST_NV_CHECK_RET(test_semaphore_timestamp(gpu)); + TEST_NV_CHECK_RET(test_encryption_decryption(gpu, UVM_CHANNEL_TYPE_CPU_TO_GPU, UVM_CHANNEL_TYPE_GPU_TO_CPU)); + TEST_NV_CHECK_RET(test_encryption_decryption(gpu, UVM_CHANNEL_TYPE_WLC, UVM_CHANNEL_TYPE_WLC)); } return NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_channel.c b/kernel-open/nvidia-uvm/uvm_channel.c index 895fd846f3..ab23e26c6f 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.c +++ b/kernel-open/nvidia-uvm/uvm_channel.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,8 +33,10 @@ #include "uvm_lock.h" #include "uvm_kvmalloc.h" +#include "nv_uvm_types.h" #include "nv_uvm_interface.h" #include "clb06f.h" +#include "uvm_conf_computing.h" static unsigned uvm_channel_num_gpfifo_entries = UVM_CHANNEL_NUM_GPFIFO_ENTRIES_DEFAULT; @@ -69,17 +71,42 @@ typedef enum UVM_CHANNEL_UPDATE_MODE_FORCE_ALL } uvm_channel_update_mode_t; -static void channel_pool_lock_init(uvm_channel_pool_t *pool) +bool uvm_channel_pool_uses_mutex(uvm_channel_pool_t *pool) { + // Work submission to proxy channels in SR-IOV heavy entails calling RM API + // that acquires a mutex, so the proxy channel pool must use a mutex. if (uvm_channel_pool_is_proxy(pool)) - uvm_mutex_init(&pool->mutex, UVM_LOCK_ORDER_CHANNEL); + return true; + + // When Confidential Computing is enabled push submission requires call to + // CSL routines which acquire the CSL context mutex lock. Moreover, WLC + // submission uses UVM_SPIN_LOOP, which can call 'schedule', to wait for + // LCIC completion. Indirect submission is synchronous, calling + // uvm_push_wait which again uses UVM_SPIN_LOOP. + if (uvm_conf_computing_mode_enabled(pool->manager->gpu)) + return true; + + // Unless the mutex is required, the spinlock is preferred when work + // submission is expected to take little time. + return false; +} + +static void channel_pool_lock_init(uvm_channel_pool_t *pool) +{ + uvm_lock_order_t order = UVM_LOCK_ORDER_CHANNEL; + + if (uvm_conf_computing_mode_enabled(pool->manager->gpu) && uvm_channel_pool_is_wlc(pool)) + order = UVM_LOCK_ORDER_WLC_CHANNEL; + + if (uvm_channel_pool_uses_mutex(pool)) + uvm_mutex_init(&pool->mutex, order); else - uvm_spin_lock_init(&pool->spinlock, UVM_LOCK_ORDER_CHANNEL); + uvm_spin_lock_init(&pool->spinlock, order); } static void channel_pool_lock(uvm_channel_pool_t *pool) { - if (uvm_channel_pool_is_proxy(pool)) + if (uvm_channel_pool_uses_mutex(pool)) uvm_mutex_lock(&pool->mutex); else uvm_spin_lock(&pool->spinlock); @@ -87,7 +114,7 @@ static void channel_pool_lock(uvm_channel_pool_t *pool) static void channel_pool_unlock(uvm_channel_pool_t *pool) { - if (uvm_channel_pool_is_proxy(pool)) + if (uvm_channel_pool_uses_mutex(pool)) uvm_mutex_unlock(&pool->mutex); else uvm_spin_unlock(&pool->spinlock); @@ -245,10 +272,20 @@ static bool try_claim_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) static void unlock_channel_for_push(uvm_channel_t *channel) { + if (uvm_channel_is_secure(channel)) { + NvU32 index = uvm_channel_index_in_pool(channel); + + uvm_channel_pool_assert_locked(channel->pool); + UVM_ASSERT(test_bit(index, channel->pool->push_locks)); + __clear_bit(index, channel->pool->push_locks); + uvm_up_out_of_order(&channel->pool->push_sem); + } } static bool is_channel_locked_for_push(uvm_channel_t *channel) { + if (uvm_channel_is_secure(channel)) + return test_bit(uvm_channel_index_in_pool(channel), channel->pool->push_locks); // For CE and proxy channels, we always return that the channel is locked, // which has no functional impact in the UVM channel code-flow, this is only @@ -256,6 +293,34 @@ static bool is_channel_locked_for_push(uvm_channel_t *channel) return true; } +static void lock_channel_for_push(uvm_channel_t *channel) +{ + if (uvm_channel_is_secure(channel)) { + NvU32 index = uvm_channel_index_in_pool(channel); + + uvm_channel_pool_assert_locked(channel->pool); + + UVM_ASSERT(!test_bit(index, channel->pool->push_locks)); + __set_bit(index, channel->pool->push_locks); + } +} + +static bool test_claim_and_lock_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +{ + NvU32 index = uvm_channel_index_in_pool(channel); + + uvm_channel_pool_assert_locked(channel->pool); + + if (uvm_channel_is_secure(channel) && + !test_bit(index, channel->pool->push_locks) && + try_claim_channel_locked(channel, num_gpfifo_entries)) { + lock_channel_for_push(channel); + return true; + } + + return false; +} + // Reserve a channel in the specified CE pool static NV_STATUS channel_reserve_in_ce_pool(uvm_channel_pool_t *pool, uvm_channel_t **channel_out) { @@ -298,6 +363,69 @@ static NV_STATUS channel_reserve_in_ce_pool(uvm_channel_pool_t *pool, uvm_channe return NV_ERR_GENERIC; } +// Reserve a channel in the specified secure pool +static NV_STATUS channel_reserve_in_secure_pool(uvm_channel_pool_t *pool, uvm_channel_t **channel_out) +{ + uvm_channel_t *channel; + uvm_spin_loop_t spin; + NvU32 index; + + UVM_ASSERT(pool); + UVM_ASSERT(pool->secure); + UVM_ASSERT(uvm_conf_computing_mode_enabled(pool->manager->gpu)); + + // This semaphore is uvm_up() in unlock_channel_for_push() as part of the + // uvm_channel_end_push() routine. + uvm_down(&pool->push_sem); + + // At least one channel is unlocked. We check if any unlocked channel is + // available, i.e., if it has free GPFIFO entries. + + channel_pool_lock(pool); + + for_each_clear_bit(index, pool->push_locks, pool->num_channels) { + channel = &pool->channels[index]; + if (try_claim_channel_locked(channel, 1)) { + lock_channel_for_push(channel); + goto done; + } + } + + channel_pool_unlock(pool); + + // No channels are available. Update and check errors on all channels until + // one becomes available. + uvm_spin_loop_init(&spin); + while (1) { + uvm_for_each_channel_in_pool(channel, pool) { + NV_STATUS status; + + uvm_channel_update_progress(channel); + index = uvm_channel_index_in_pool(channel); + + channel_pool_lock(pool); + + if (test_claim_and_lock_channel(channel, 1)) + goto done; + + channel_pool_unlock(pool); + + status = uvm_channel_check_errors(channel); + if (status != NV_OK) { + uvm_up(&pool->push_sem); + return status; + } + + UVM_SPIN_LOOP(&spin); + } + } + +done: + channel_pool_unlock(pool); + *channel_out = channel; + return NV_OK; +} + NV_STATUS uvm_channel_reserve_type(uvm_channel_manager_t *manager, uvm_channel_type_t type, uvm_channel_t **channel_out) { uvm_channel_pool_t *pool = manager->pool_to_use.default_for_type[type]; @@ -305,6 +433,9 @@ NV_STATUS uvm_channel_reserve_type(uvm_channel_manager_t *manager, uvm_channel_t UVM_ASSERT(pool != NULL); UVM_ASSERT(type < UVM_CHANNEL_TYPE_COUNT); + if (pool->secure) + return channel_reserve_in_secure_pool(pool, channel_out); + return channel_reserve_in_ce_pool(pool, channel_out); } @@ -321,6 +452,9 @@ NV_STATUS uvm_channel_reserve_gpu_to_gpu(uvm_channel_manager_t *manager, UVM_ASSERT(pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE); + if (pool->secure) + return channel_reserve_in_secure_pool(pool, channel_out); + return channel_reserve_in_ce_pool(pool, channel_out); } @@ -357,6 +491,49 @@ static NvU32 channel_get_available_push_info_index(uvm_channel_t *channel) return push_info - channel->push_infos; } +static void channel_semaphore_gpu_encrypt_payload(uvm_push_t *push, uvm_channel_t *channel, NvU64 semaphore_va) +{ + NvU32 iv_index; + uvm_gpu_address_t notifier_gpu_va; + uvm_gpu_address_t auth_tag_gpu_va; + uvm_gpu_address_t semaphore_gpu_va; + uvm_gpu_address_t encrypted_payload_gpu_va; + uvm_gpu_t *gpu = push->gpu; + uvm_gpu_semaphore_t *semaphore = &channel->tracking_sem.semaphore; + UvmCslIv *iv_cpu_addr = semaphore->conf_computing.ivs; + NvU32 payload_size = sizeof(*semaphore->payload); + NvU32 *last_pushed_notifier = &semaphore->conf_computing.last_pushed_notifier; + + UVM_ASSERT(uvm_channel_is_secure_ce(channel)); + + encrypted_payload_gpu_va = uvm_rm_mem_get_gpu_va(semaphore->conf_computing.encrypted_payload, gpu, false); + notifier_gpu_va = uvm_rm_mem_get_gpu_va(semaphore->conf_computing.notifier, gpu, false); + auth_tag_gpu_va = uvm_rm_mem_get_gpu_va(semaphore->conf_computing.auth_tag, gpu, false); + semaphore_gpu_va = uvm_gpu_address_virtual(semaphore_va); + + iv_index = ((*last_pushed_notifier + 2) / 2) % channel->num_gpfifo_entries; + + uvm_conf_computing_log_gpu_encryption(channel, &iv_cpu_addr[iv_index]); + + gpu->parent->ce_hal->memset_4(push, notifier_gpu_va, ++(*last_pushed_notifier), sizeof(*last_pushed_notifier)); + gpu->parent->ce_hal->encrypt(push, encrypted_payload_gpu_va, semaphore_gpu_va, payload_size, auth_tag_gpu_va); + gpu->parent->ce_hal->memset_4(push, notifier_gpu_va, ++(*last_pushed_notifier), sizeof(*last_pushed_notifier)); +} + +// Auxiliary buffer only used by SEC2 channels for CPU computation of the method +// stream signature. Note that it is required that this inline pushbuffer buffer +// is reserved at push->begin. +static void push_reserve_csl_sign_buf(uvm_push_t *push) +{ + uvm_gpu_address_t dummy; + NvU32 *buf; + + buf = uvm_push_get_single_inline_buffer(push, UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE, UVM_METHOD_SIZE, &dummy); + + // Offset UVM_METHOD_SIZE from buf due to the NOP method. + UVM_ASSERT((buf - UVM_METHOD_SIZE / sizeof(*buf)) == push->begin); +} + NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push) { NV_STATUS status; @@ -367,16 +544,40 @@ NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push) manager = channel->pool->manager; + // Only SEC2 and WLC with set up fixed schedule can use direct push + // submission. All other cases (including WLC pre-schedule) need to + // reserve a launch channel that will be used to submit this push + // indirectly. + if (uvm_conf_computing_mode_enabled(uvm_channel_get_gpu(channel)) && + !(uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(manager)) && + !uvm_channel_is_sec2(channel)) { + uvm_channel_type_t indirect_channel_type = uvm_channel_manager_is_wlc_ready(manager) ? + UVM_CHANNEL_TYPE_WLC : + UVM_CHANNEL_TYPE_SEC2; + status = uvm_channel_reserve_type(manager, indirect_channel_type, &push->launch_channel); + if (status != NV_OK) + return status; + } + + // For secure channels, channel's lock should have been acquired in + // uvm_channel_reserve() or channel_reserve_in_secure_pool() before + // reaching here. UVM_ASSERT(is_channel_locked_for_push(channel)); + push->channel = channel; + push->channel_tracking_value = 0; + status = uvm_pushbuffer_begin_push(manager->pushbuffer, push); if (status != NV_OK) return status; - push->channel = channel; - push->channel_tracking_value = 0; push->push_info_index = channel_get_available_push_info_index(channel); + if (uvm_channel_is_sec2(push->channel)) + push_reserve_csl_sign_buf(push); + else if (uvm_channel_is_wlc(push->channel) && uvm_channel_manager_is_wlc_ready(manager)) + uvm_conf_computing_acquire_encryption_iv(push->channel, &push->launch_iv); + return NV_OK; } @@ -395,7 +596,15 @@ static void internal_channel_submit_work(uvm_push_t *push, NvU32 push_size, NvU3 gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + channel->cpu_put; pushbuffer_va = uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push); - gpu->parent->host_hal->set_gpfifo_entry(gpfifo_entry, pushbuffer_va, push_size); + if (uvm_conf_computing_mode_enabled(gpu)) { + void *unprotected_pb = uvm_pushbuffer_get_unprotected_cpu_va_for_push(pushbuffer, push); + UVM_ASSERT(uvm_channel_is_sec2(channel)); + + // Copy push data to unprotected sysmem, it has already been signed. + memcpy(unprotected_pb, push->begin, push_size); + } + + gpu->parent->host_hal->set_gpfifo_entry(gpfifo_entry, pushbuffer_va, push_size, UVM_GPFIFO_SYNC_PROCEED); // Need to make sure all the pushbuffer and the GPFIFO entries writes // complete before updating GPPUT. We also don't want any reads to be moved @@ -432,22 +641,221 @@ static void proxy_channel_submit_work(uvm_push_t *push, NvU32 push_size) } } -static void uvm_channel_semaphore_release(uvm_push_t *push, NvU64 semaphore_va, NvU32 new_payload) +static void do_semaphore_release(uvm_push_t *push, NvU64 semaphore_va, NvU32 new_payload) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); + if (uvm_channel_is_ce(push->channel)) + gpu->parent->ce_hal->semaphore_release(push, semaphore_va, new_payload); + else if (uvm_channel_is_sec2(push->channel)) + gpu->parent->sec2_hal->semaphore_release(push, semaphore_va, new_payload); + else + UVM_ASSERT_MSG(0, "Semaphore release on an unsupported channel.\n"); +} +static void uvm_channel_tracking_semaphore_release(uvm_push_t *push, NvU64 semaphore_va, NvU32 new_payload) +{ // We used to skip the membar or use membar GPU for the semaphore release // for a few pushes, but that doesn't provide sufficient ordering guarantees // in some cases (e.g. ga100 with an LCE with PCEs from both HSHUBs) for the // semaphore writes. To be safe, just always uses a membar sys for now. - // TODO bug 3770539: Optimize membars used by end of push semaphore releases + // TODO: Bug 3770539: Optimize membars used by end of push semaphore releases (void)uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); (void)uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - if (uvm_channel_is_ce(push->channel)) - gpu->parent->ce_hal->semaphore_release(push, semaphore_va, new_payload); - else - UVM_ASSERT_MSG(0, "Semaphore release on an unsupported channel.\n"); + do_semaphore_release(push, semaphore_va, new_payload); + + // When the Confidential Computing feature is enabled, additional work + // needs to be scheduled to get an encrypted shadow copy in unprotected + // sysmem. This allows UVM to later decrypt it and observe the new + // semaphore value. + if (uvm_channel_is_secure_ce(push->channel)) + channel_semaphore_gpu_encrypt_payload(push, push->channel, semaphore_va); +} + +static uvm_channel_t *get_paired_channel(uvm_channel_t *channel) +{ + unsigned index; + uvm_channel_pool_t *paired_pool; + uvm_channel_type_t paired_channel_type; + + UVM_ASSERT(channel); + UVM_ASSERT(uvm_channel_is_wlc(channel) || uvm_channel_is_lcic(channel)); + + index = uvm_channel_index_in_pool(channel); + paired_channel_type = uvm_channel_is_wlc(channel) ? UVM_CHANNEL_TYPE_LCIC : UVM_CHANNEL_TYPE_WLC; + paired_pool = channel->pool->manager->pool_to_use.default_for_type[paired_channel_type]; + return paired_pool->channels + index; +} + +static uvm_channel_t *wlc_get_paired_lcic(uvm_channel_t *wlc_channel) +{ + UVM_ASSERT(wlc_channel); + UVM_ASSERT(uvm_channel_is_wlc(wlc_channel)); + + return get_paired_channel(wlc_channel); +} + +static uvm_channel_t *lcic_get_paired_wlc(uvm_channel_t *lcic_channel) +{ + UVM_ASSERT(lcic_channel); + UVM_ASSERT(uvm_channel_is_lcic(lcic_channel)); + + return get_paired_channel(lcic_channel); +} + +static void internal_channel_submit_work_wlc(uvm_push_t *push) +{ + uvm_channel_t *wlc_channel = push->channel; + uvm_channel_t *lcic_channel = wlc_get_paired_lcic(wlc_channel); + UvmCslIv *iv_cpu_addr = lcic_channel->tracking_sem.semaphore.conf_computing.ivs; + NvU32 *last_pushed_notifier; + NvU32 iv_index; + uvm_spin_loop_t spin; + + UVM_ASSERT(lcic_channel); + + // Wait for the WLC/LCIC to be primed. This means that PUT == GET + 2 + // and a WLC doorbell ring is enough to start work. + UVM_SPIN_WHILE(!uvm_gpu_tracking_semaphore_is_completed(&lcic_channel->tracking_sem), &spin); + + // Executing WLC adds an extra job to LCIC + ++lcic_channel->tracking_sem.queued_value; + + UVM_ASSERT_MSG(uvm_push_get_size(push) == UVM_MAX_WLC_PUSH_SIZE, + "WLC push submission size mismatch, expected: %u, got: %u", + UVM_MAX_WLC_PUSH_SIZE, + uvm_push_get_size(push)); + + // Handles the CPU part of the setup for the LCIC to be able to do GPU + // encryption of its tracking semaphore value. See setup_lcic_schedule(). + last_pushed_notifier = &lcic_channel->tracking_sem.semaphore.conf_computing.last_pushed_notifier; + *lcic_channel->conf_computing.static_notifier_entry_unprotected_sysmem_cpu = ++(*last_pushed_notifier); + *lcic_channel->conf_computing.static_notifier_exit_unprotected_sysmem_cpu = ++(*last_pushed_notifier); + iv_index = (*last_pushed_notifier / 2) % lcic_channel->num_gpfifo_entries; + uvm_conf_computing_log_gpu_encryption(lcic_channel, &iv_cpu_addr[iv_index]); + + // Move push data + uvm_conf_computing_cpu_encrypt(wlc_channel, + wlc_channel->conf_computing.static_pb_unprotected_sysmem_cpu, + push->begin, + &push->launch_iv, + UVM_MAX_WLC_PUSH_SIZE, + wlc_channel->conf_computing.static_pb_unprotected_sysmem_auth_tag_cpu); + + // Make sure all encrypted data is observable before ringing the doorbell. + wmb(); + + // Ring the WLC doorbell to start processing the above push + UVM_GPU_WRITE_ONCE(*wlc_channel->channel_info.workSubmissionOffset, + wlc_channel->channel_info.workSubmissionToken); +} + +static NV_STATUS internal_channel_submit_work_indirect(uvm_push_t *push, + NvU32 old_cpu_put, + NvU32 new_gpu_put) +{ + uvm_pushbuffer_t *pushbuffer = push->channel->pool->manager->pushbuffer; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + uvm_push_t indirect_push; + NV_STATUS status; + NvU64 gpfifo_entry; + + void *push_enc_cpu = uvm_pushbuffer_get_unprotected_cpu_va_for_push(pushbuffer, push); + NvU64 push_enc_gpu = uvm_pushbuffer_get_unprotected_gpu_va_for_push(pushbuffer, push); + void *push_enc_auth_tag; + uvm_gpu_address_t push_enc_auth_tag_gpu; + NvU64 gpfifo_gpu = push->channel->channel_info.gpFifoGpuVa + old_cpu_put * sizeof(gpfifo_entry); + uvm_spin_loop_t spin; + + UVM_ASSERT(!uvm_channel_is_sec2(push->channel)); + + // If the old_cpu_put is not equal to the last gpu put, other pushes are + // pending that need to be submitted. That push/es' submission will update + // the gpu_put pointer to expected value. + UVM_SPIN_WHILE(push->channel->conf_computing.gpu_put != old_cpu_put, &spin); + + // This can never stall or return error. SEC2 launch used during init has + // plenty of PB space available before it needs to check for push + // completion/channel status. WLC launch after WLC channels are initialized + // uses private static pb space and needs neither general PB space, nor it + // counts towards max concurrent pushes. + status = uvm_push_begin_on_reserved_channel(push->launch_channel, + &indirect_push, + "Worklaunch to '%s' via '%s'", + push->channel->name, + push->launch_channel->name); + if (status != NV_OK) + return status; + + + // Move over the pushbuffer data + if (uvm_channel_is_sec2(indirect_push.channel)) { + push_enc_auth_tag = uvm_push_get_single_inline_buffer(&indirect_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &push_enc_auth_tag_gpu); + } + else { + // Auth tags cannot be in protected vidmem. + // WLC channels use a static preallocated space for launch auth tags + push_enc_auth_tag = indirect_push.channel->conf_computing.launch_auth_tag_cpu; + push_enc_auth_tag_gpu = uvm_gpu_address_virtual(indirect_push.channel->conf_computing.launch_auth_tag_gpu_va); + } + + uvm_conf_computing_cpu_encrypt(indirect_push.channel, + push_enc_cpu, + push->begin, + NULL, + uvm_push_get_size(push), + push_enc_auth_tag); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + if (uvm_channel_is_sec2(indirect_push.channel)) { + gpu->parent->sec2_hal->decrypt(&indirect_push, + uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push), + push_enc_gpu, + uvm_push_get_size(push), + push_enc_auth_tag_gpu.address); + } + else { + gpu->parent->ce_hal->decrypt(&indirect_push, + uvm_gpu_address_virtual(uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push)), + uvm_gpu_address_virtual(push_enc_gpu), + uvm_push_get_size(push), + push_enc_auth_tag_gpu); + } + + gpu->parent->host_hal->set_gpfifo_entry(&gpfifo_entry, + uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push), + uvm_push_get_size(push), + UVM_GPFIFO_SYNC_PROCEED); + + // TODO: Bug 2649842: RFE - Investigate using 64-bit semaphore + // SEC2 needs encrypt decrypt to be 16B aligned GPFIFO entries are only 8B + // Use 2x semaphore release to set the values directly. + // We could use a single 64 bit release if it were available + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + do_semaphore_release(&indirect_push, gpfifo_gpu, NvU64_LO32(gpfifo_entry)); + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + do_semaphore_release(&indirect_push, gpfifo_gpu + 4, NvU64_HI32(gpfifo_entry)); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(&indirect_push, push->channel->channel_info.gpPutGpuVa, new_gpu_put); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(&indirect_push, + push->channel->channel_info.workSubmissionOffsetGpuVa, + push->channel->channel_info.workSubmissionToken); + + status = uvm_push_end_and_wait(&indirect_push); + if (status != NV_OK) + return status; + + push->channel->conf_computing.gpu_put = new_gpu_put; + + return status; } void uvm_channel_end_push(uvm_push_t *push) @@ -462,6 +870,7 @@ void uvm_channel_end_push(uvm_push_t *push) NvU32 push_size; NvU32 cpu_put; NvU32 new_cpu_put; + bool needs_sec2_work_submit = false; channel_pool_lock(channel->pool); @@ -469,7 +878,27 @@ void uvm_channel_end_push(uvm_push_t *push) new_payload = (NvU32)new_tracking_value; semaphore_va = uvm_channel_tracking_semaphore_get_gpu_va(channel); - uvm_channel_semaphore_release(push, semaphore_va, new_payload); + uvm_channel_tracking_semaphore_release(push, semaphore_va, new_payload); + + if (uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(channel_manager)) { + uvm_channel_t *paired_lcic = wlc_get_paired_lcic(channel); + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + gpu->parent->ce_hal->semaphore_reduction_inc(push, + paired_lcic->channel_info.gpPutGpuVa, + paired_lcic->num_gpfifo_entries - 1); + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(push, + paired_lcic->channel_info.workSubmissionOffsetGpuVa, + paired_lcic->channel_info.workSubmissionToken); + + if (uvm_push_get_size(push) < UVM_MAX_WLC_PUSH_SIZE) { + // The UVM_MAX_WLC_PUSH_SIZE is set to fit indirect work launch + // pushes. However, direct pushes to WLC can be smaller than this + // size. This is used e.g. by indirect submission of control + // gpfifo entries. + channel_manager->gpu->parent->host_hal->noop(push, UVM_MAX_WLC_PUSH_SIZE - uvm_push_get_size(push)); + } + } push_size = uvm_push_get_size(push); UVM_ASSERT_MSG(push_size <= UVM_MAX_PUSH_SIZE, "push size %u\n", push_size); @@ -481,16 +910,40 @@ void uvm_channel_end_push(uvm_push_t *push) entry->tracking_semaphore_value = new_tracking_value; entry->pushbuffer_offset = uvm_pushbuffer_get_offset_for_push(pushbuffer, push); entry->pushbuffer_size = push_size; + + // Indirect submission via SEC2/WLC needs pushes to be aligned for + // encryption/decryption. The pushbuffer_size of this push + // influences starting address of the next push. + if (uvm_conf_computing_mode_enabled(uvm_channel_get_gpu(channel))) + entry->pushbuffer_size = UVM_ALIGN_UP(push_size, UVM_CONF_COMPUTING_BUF_ALIGNMENT); entry->push_info = &channel->push_infos[push->push_info_index]; entry->type = UVM_GPFIFO_ENTRY_TYPE_NORMAL; UVM_ASSERT(channel->current_gpfifo_count > 0); --channel->current_gpfifo_count; - if (uvm_channel_is_proxy(channel)) + if (uvm_channel_is_proxy(channel)) { proxy_channel_submit_work(push, push_size); - else + } + else if (uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(channel_manager)) { + internal_channel_submit_work_wlc(push); + } + else if (uvm_conf_computing_mode_enabled(channel_manager->gpu) && !uvm_channel_is_sec2(channel)) { + if (uvm_channel_manager_is_wlc_ready(channel_manager)) { + NV_STATUS status = internal_channel_submit_work_indirect(push, cpu_put, new_cpu_put); + + // This codepath should only be used during initialization and thus + // NEVER return an error. + UVM_ASSERT(status == NV_OK); + } + else { + // submitting via SEC2 starts a push, postpone until this push is ended + needs_sec2_work_submit = true; + } + } + else { internal_channel_submit_work(push, push_size, new_cpu_put); + } channel->cpu_put = new_cpu_put; @@ -509,20 +962,103 @@ void uvm_channel_end_push(uvm_push_t *push) // bug 124888, which GL works around by doing a clflush" wmb(); + if (needs_sec2_work_submit) { + NV_STATUS status = internal_channel_submit_work_indirect(push, cpu_put, new_cpu_put); + + // This codepath should only be used during initialization and thus + // NEVER return an error. + UVM_ASSERT(status == NV_OK); + } + push->push_info_index = channel->num_gpfifo_entries; push->channel_tracking_value = new_tracking_value; } +static void submit_ctrl_gpfifo(uvm_channel_t *channel, uvm_gpfifo_entry_t *entry, NvU32 new_cpu_put) +{ + uvm_gpu_t *gpu = channel->pool->manager->gpu; + NvU32 cpu_put = channel->cpu_put; + NvU64 *gpfifo_entry; + + UVM_ASSERT(entry == &channel->gpfifo_entries[cpu_put]); + if (uvm_conf_computing_mode_enabled(gpu) && !uvm_channel_is_sec2(channel)) + return; + + gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + cpu_put; + *gpfifo_entry = entry->control_value; + + // Need to make sure all the GPFIFO entries writes complete before updating + // GPPUT. We also don't want any reads to be moved after the GPPut write as + // the GPU might modify the data they read as soon as the GPPut write + // happens. + mb(); + + gpu->parent->host_hal->write_gpu_put(channel, new_cpu_put); +} + +static NV_STATUS submit_ctrl_gpfifo_indirect(uvm_channel_t *channel, + uvm_gpfifo_entry_t *entry, + NvU32 old_cpu_put, + NvU32 new_gpu_put) +{ + uvm_push_t indirect_push; + NV_STATUS status = NV_OK; + uvm_spin_loop_t spin; + uvm_channel_type_t indirect_channel_type = uvm_channel_manager_is_wlc_ready(channel->pool->manager) ? + UVM_CHANNEL_TYPE_WLC : + UVM_CHANNEL_TYPE_SEC2; + NvU64 gpfifo_gpu = channel->channel_info.gpFifoGpuVa + (old_cpu_put * sizeof(entry->control_value)); + + UVM_ASSERT(!uvm_channel_is_sec2(channel)); + + // If the old_cpu_put is not equal to the last gpu put, + // Another push(es) is pending that needs to be submitted. + // That push/es' submission will update the gpu_put pointer + // to expected value. + UVM_SPIN_WHILE(channel->conf_computing.gpu_put != old_cpu_put, &spin); + + status = uvm_push_begin(channel->pool->manager, + indirect_channel_type, + &indirect_push, + "GPFIFO submit to '%s' via '%s'", + channel->name, + uvm_channel_type_to_string(indirect_channel_type)); + if (status != NV_OK) + return status; + + // TODO: Bug 2649842: RFE - Investigate using 64-bit semaphore + // SEC2 needs encrypt decrypt to be 16B aligned GPFIFO entries are only 8B + // Use 2x semaphore release to set the values directly. + // One 64bit semahore release can be used instead once implemented. + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + do_semaphore_release(&indirect_push, gpfifo_gpu, NvU64_LO32(entry->control_value)); + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + do_semaphore_release(&indirect_push, gpfifo_gpu + 4, NvU64_HI32(entry->control_value)); + + uvm_push_set_flag(&indirect_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + do_semaphore_release(&indirect_push, channel->channel_info.gpPutGpuVa, new_gpu_put); + + status = uvm_push_end_and_wait(&indirect_push); + if (status != NV_OK) + return status; + + channel->conf_computing.gpu_put = new_gpu_put; + + // The above SEC2 work transferred everything + // Ring the doorbell + UVM_GPU_WRITE_ONCE(*channel->channel_info.workSubmissionOffset, channel->channel_info.workSubmissionToken); + return NV_OK; +} + // The caller must submit a normal GPFIFO entry with a semaphore release // following the control GPFIFO, refer to uvm_channel_write_ctrl_gpfifo() for an // example. static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_value) { uvm_gpfifo_entry_t *entry; - NvU64 *gpfifo_entry; NvU32 cpu_put; NvU32 new_cpu_put; - uvm_gpu_t *gpu = channel->pool->manager->gpu; + bool needs_indirect_submit = false; channel_pool_lock(channel->pool); @@ -532,6 +1068,7 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu entry = &channel->gpfifo_entries[cpu_put]; memset(entry, 0, sizeof(*entry)); entry->type = UVM_GPFIFO_ENTRY_TYPE_CONTROL; + entry->control_value = ctrl_fifo_entry_value; // Control GPFIFO entries are followed by a semaphore_release push in UVM. // We add the tracking semaphore value of the next GPFIFO entry, @@ -543,16 +1080,9 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu UVM_ASSERT(channel->current_gpfifo_count > 1); --channel->current_gpfifo_count; - gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + cpu_put; - *gpfifo_entry = ctrl_fifo_entry_value; - - // Need to make sure all the GPFIFO entries writes complete before updating - // GPPUT. We also don't want any reads to be moved after the GPPut write as - // the GPU might modify the data they read as soon as the GPPut write - // happens. - mb(); - - gpu->parent->host_hal->write_gpu_put(channel, new_cpu_put); + submit_ctrl_gpfifo(channel, entry, new_cpu_put); + if (uvm_conf_computing_mode_enabled(channel->pool->manager->gpu) && !uvm_channel_is_sec2(channel)) + needs_indirect_submit = true; channel->cpu_put = new_cpu_put; @@ -563,6 +1093,13 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu // semaphore release, where the channel is unlocked. channel_pool_unlock(channel->pool); + if (needs_indirect_submit) { + NV_STATUS status = submit_ctrl_gpfifo_indirect(channel, entry, cpu_put, new_cpu_put); + + // All failures are globally fatal. There's nothing we do to recover. + UVM_ASSERT_RELEASE(status == NV_OK); + } + // This memory barrier is borrowed from CUDA, as it supposedly fixes perf // issues on some systems. Comment from CUDA: "fixes throughput-related // performance problems, e.g. bugs 626179, 593841. This may be related to @@ -578,6 +1115,11 @@ NV_STATUS uvm_channel_write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_ UVM_ASSERT(!uvm_channel_is_proxy(channel)); + // WLC/LCIC channels can only process custom gpfifo entries before + // their schedule is set up. + UVM_ASSERT(!uvm_channel_is_lcic(channel) || !uvm_channel_manager_is_wlc_ready(channel->pool->manager)); + UVM_ASSERT(!uvm_channel_is_wlc(channel) || !uvm_channel_manager_is_wlc_ready(channel->pool->manager)); + // We reserve two GPFIFO entries, i.e., the control GPFIFO entry and the // subsequent semaphore_release push. There is, however, a potential case // for GPFIFO control submission starvation. This may happen because a @@ -612,11 +1154,61 @@ NV_STATUS uvm_channel_write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_ return NV_OK; } +static NV_STATUS uvm_channel_reserve_secure(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +{ + uvm_spin_loop_t spin; + NV_STATUS status = NV_OK; + uvm_channel_pool_t *pool = channel->pool; + + // This semaphore is uvm_up() in unlock_channel_for_push() as part of the + // uvm_channel_end_push() routine. Note that different than in + // channel_reserve_in_secure_pool, we cannot pick an unlocked channel from + // the secure pool, even when there is one available and *channel is locked. + // Not a concern given that uvm_channel_reserve() is not the common-case for + // channel reservation, and only used for channel initialization, GPFIFO + // control work submission, and testing. + uvm_down(&pool->push_sem); + + channel_pool_lock(pool); + + if (test_claim_and_lock_channel(channel, num_gpfifo_entries)) + goto out; + + channel_pool_unlock(pool); + + uvm_spin_loop_init(&spin); + while (1) { + uvm_channel_update_progress(channel); + + channel_pool_lock(pool); + + if (test_claim_and_lock_channel(channel, num_gpfifo_entries)) + goto out; + + channel_pool_unlock(pool); + + status = uvm_channel_check_errors(channel); + if (status != NV_OK) { + uvm_up(&pool->push_sem); + return status; + } + + UVM_SPIN_LOOP(&spin); + } + +out: + channel_pool_unlock(pool); + return NV_OK; +} + NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { NV_STATUS status = NV_OK; uvm_spin_loop_t spin; + if (uvm_channel_is_secure(channel)) + return uvm_channel_reserve_secure(channel, num_gpfifo_entries); + if (try_claim_channel(channel, num_gpfifo_entries)) return NV_OK; @@ -708,13 +1300,10 @@ NV_STATUS uvm_channel_check_errors(uvm_channel_t *channel) push_info->function); } else { - NvU64 *gpfifo_entry; - UVM_ASSERT(!uvm_channel_is_proxy(channel)); - gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + (fatal_entry - channel->gpfifo_entries); UVM_ERR_PRINT("Channel error likely caused by GPFIFO control entry, data: 0x%llx, gpu_get: %d\n", - *gpfifo_entry, + fatal_entry->control_value, channel->gpu_get); } } @@ -750,9 +1339,197 @@ bool uvm_channel_is_value_completed(uvm_channel_t *channel, NvU64 value) return uvm_gpu_tracking_semaphore_is_value_completed(&channel->tracking_sem, value); } -NvU64 uvm_channel_update_completed_value(uvm_channel_t *channel) -{ - return uvm_gpu_tracking_semaphore_update_completed_value(&channel->tracking_sem); +NvU64 uvm_channel_update_completed_value(uvm_channel_t *channel) +{ + return uvm_gpu_tracking_semaphore_update_completed_value(&channel->tracking_sem); +} + +static NV_STATUS csl_init(uvm_channel_t *channel) +{ + NV_STATUS status; + + UVM_ASSERT(uvm_channel_is_secure(channel)); + uvm_mutex_init(&channel->csl.ctx_lock, UVM_LOCK_ORDER_LEAF); + + status = uvm_rm_locked_call(nvUvmInterfaceCslInitContext(&channel->csl.ctx, channel->handle)); + if (status == NV_OK) { + channel->csl.is_ctx_initialized = true; + } + else { + UVM_DBG_PRINT("nvUvmInterfaceCslInitContext() failed: %s, GPU %s\n", + nvstatusToString(status), + uvm_gpu_name(channel->pool->manager->gpu)); + } + + return status; +} + +static void csl_destroy(uvm_channel_t *channel) +{ + if (!channel->csl.is_ctx_initialized) + return; + + uvm_assert_mutex_unlocked(&channel->csl.ctx_lock); + UVM_ASSERT(!is_channel_locked_for_push(channel)); + + uvm_rm_locked_call_void(nvUvmInterfaceDeinitCslContext(&channel->csl.ctx)); + channel->csl.is_ctx_initialized = false; +} + +static void free_conf_computing_buffers(uvm_channel_t *channel) +{ + UVM_ASSERT(uvm_channel_is_secure_ce(channel)); + + uvm_rm_mem_free(channel->conf_computing.static_pb_protected_vidmem); + uvm_rm_mem_free(channel->conf_computing.static_pb_unprotected_sysmem); + uvm_rm_mem_free(channel->conf_computing.static_notifier_unprotected_sysmem); + uvm_kvfree(channel->conf_computing.static_pb_protected_sysmem); + channel->conf_computing.static_pb_protected_vidmem = NULL; + channel->conf_computing.static_pb_unprotected_sysmem = NULL; + channel->conf_computing.static_notifier_unprotected_sysmem = NULL; + channel->conf_computing.static_pb_protected_sysmem = NULL; + + uvm_rm_mem_free(channel->tracking_sem.semaphore.conf_computing.encrypted_payload); + uvm_rm_mem_free(channel->tracking_sem.semaphore.conf_computing.notifier); + uvm_rm_mem_free(channel->tracking_sem.semaphore.conf_computing.auth_tag); + uvm_kvfree(channel->tracking_sem.semaphore.conf_computing.ivs); + channel->tracking_sem.semaphore.conf_computing.encrypted_payload = NULL; + channel->tracking_sem.semaphore.conf_computing.notifier = NULL; + channel->tracking_sem.semaphore.conf_computing.auth_tag = NULL; + channel->tracking_sem.semaphore.conf_computing.ivs = NULL; +} + +static NV_STATUS alloc_conf_computing_buffers_semaphore(uvm_channel_t *channel) +{ + uvm_gpu_semaphore_t *semaphore = &channel->tracking_sem.semaphore; + uvm_gpu_t *gpu = channel->pool->manager->gpu; + NV_STATUS status; + + UVM_ASSERT(uvm_channel_is_secure_ce(channel)); + status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + sizeof(semaphore->conf_computing.last_pushed_notifier), + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &semaphore->conf_computing.notifier); + + if (status != NV_OK) + return status; + + status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + sizeof(*channel->tracking_sem.semaphore.payload), + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &semaphore->conf_computing.encrypted_payload); + + if (status != NV_OK) + return status; + + status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &semaphore->conf_computing.auth_tag); + + if (status != NV_OK) + return status; + + semaphore->conf_computing.ivs = uvm_kvmalloc_zero(sizeof(*semaphore->conf_computing.ivs) + * channel->num_gpfifo_entries); + + if (!semaphore->conf_computing.ivs) + return NV_ERR_NO_MEMORY; + + return status; +} + +static NV_STATUS alloc_conf_computing_buffers_wlc(uvm_channel_t *channel) +{ + uvm_gpu_t *gpu = channel->pool->manager->gpu; + NV_STATUS status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + UVM_MAX_WLC_PUSH_SIZE + UVM_CONF_COMPUTING_AUTH_TAG_SIZE * 2, + PAGE_SIZE, + &channel->conf_computing.static_pb_unprotected_sysmem); + if (status != NV_OK) + return status; + + status = uvm_rm_mem_alloc(gpu, + UVM_RM_MEM_TYPE_GPU, + UVM_MAX_WLC_PUSH_SIZE * 2, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &channel->conf_computing.static_pb_protected_vidmem); + if (status != NV_OK) + return status; + + channel->conf_computing.static_pb_unprotected_sysmem_cpu = + uvm_rm_mem_get_cpu_va(channel->conf_computing.static_pb_unprotected_sysmem); + channel->conf_computing.static_pb_unprotected_sysmem_auth_tag_cpu = + (char*)channel->conf_computing.static_pb_unprotected_sysmem_cpu + UVM_MAX_WLC_PUSH_SIZE; + + // The location below is only used for launch pushes but reuses + // the same sysmem allocation + channel->conf_computing.launch_auth_tag_cpu = + (char*)channel->conf_computing.static_pb_unprotected_sysmem_cpu + + UVM_MAX_WLC_PUSH_SIZE + UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + channel->conf_computing.launch_auth_tag_gpu_va = + uvm_rm_mem_get_gpu_uvm_va(channel->conf_computing.static_pb_unprotected_sysmem, gpu) + + UVM_MAX_WLC_PUSH_SIZE + UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + + channel->conf_computing.static_pb_protected_sysmem = uvm_kvmalloc(UVM_MAX_WLC_PUSH_SIZE + UVM_PAGE_SIZE_4K); + if (!channel->conf_computing.static_pb_protected_sysmem) + return NV_ERR_NO_MEMORY; + + return status; +} + +static NV_STATUS alloc_conf_computing_buffers_lcic(uvm_channel_t *channel) +{ + uvm_gpu_t *gpu = channel->pool->manager->gpu; + const size_t notifier_size = sizeof(*channel->conf_computing.static_notifier_entry_unprotected_sysmem_cpu); + NV_STATUS status = uvm_rm_mem_alloc_and_map_cpu(gpu, + UVM_RM_MEM_TYPE_SYS, + notifier_size * 2, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &channel->conf_computing.static_notifier_unprotected_sysmem); + if (status != NV_OK) + return status; + + status = uvm_rm_mem_alloc(gpu, + UVM_RM_MEM_TYPE_GPU, + UVM_LCIC_PUSH_SIZE, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &channel->conf_computing.static_pb_protected_vidmem); + if (status != NV_OK) + return status; + + channel->conf_computing.static_notifier_entry_unprotected_sysmem_cpu = + uvm_rm_mem_get_cpu_va(channel->conf_computing.static_notifier_unprotected_sysmem); + channel->conf_computing.static_notifier_exit_unprotected_sysmem_cpu = + channel->conf_computing.static_notifier_entry_unprotected_sysmem_cpu + 1; + + channel->conf_computing.static_notifier_entry_unprotected_sysmem_gpu_va = + uvm_rm_mem_get_gpu_va(channel->conf_computing.static_notifier_unprotected_sysmem, gpu, false); + channel->conf_computing.static_notifier_exit_unprotected_sysmem_gpu_va = + channel->conf_computing.static_notifier_entry_unprotected_sysmem_gpu_va; + channel->conf_computing.static_notifier_exit_unprotected_sysmem_gpu_va.address += notifier_size; + + return status; +} + +static NV_STATUS alloc_conf_computing_buffers(uvm_channel_t *channel) +{ + NV_STATUS status; + + status = alloc_conf_computing_buffers_semaphore(channel); + if (status != NV_OK) + return status; + + if (uvm_channel_is_wlc(channel)) + status = alloc_conf_computing_buffers_wlc(channel); + else if (uvm_channel_is_lcic(channel)) + status = alloc_conf_computing_buffers_lcic(channel); + + return status; } static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) @@ -780,6 +1557,12 @@ static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) uvm_kvfree(channel->gpfifo_entries); + if (uvm_channel_is_secure(channel)) { + csl_destroy(channel); + if (uvm_channel_is_secure_ce(channel)) + free_conf_computing_buffers(channel); + } + if (uvm_channel_is_proxy(channel)) uvm_rm_locked_call_void(nvUvmInterfacePagingChannelDestroy(channel->proxy.handle)); else @@ -793,7 +1576,56 @@ static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) pool->num_channels--; } -static NV_STATUS internal_channel_create(uvm_channel_t *channel, unsigned engine_index) +static unsigned channel_pool_type_num_gpfifo_entries(uvm_channel_manager_t *manager, uvm_channel_pool_type_t pool_type) +{ + switch (pool_type) { + case UVM_CHANNEL_POOL_TYPE_CE: + case UVM_CHANNEL_POOL_TYPE_CE_PROXY: + return manager->conf.num_gpfifo_entries; + case UVM_CHANNEL_POOL_TYPE_SEC2: + return manager->conf.num_gpfifo_entries; + case UVM_CHANNEL_POOL_TYPE_WLC: { + // WLC benefits from larger number of entries since more available + // entries result in less frequent calls to + // uvm_channel_update_progress 16 is the maximum size that can + // re-use static pb preallocated memory when uploading the WLC + // schedule. + return 16; + } + case UVM_CHANNEL_POOL_TYPE_LCIC: { + // Every channel needs at least 3 entries; 1 for sentinel and 2 more + // for submitting GPFIFO control entries. The number also has to be + // power of 2, as the HW stores the size as log2 value. + // LCIC does not accept external pushes, uvm_channel_update_progress + // is not a concern. + return 4; + } + default: + UVM_ASSERT_MSG(0, "Unhandled pool type: %d", pool_type); + return 0; + } +} + +// Returns the TSG for a given channel. +static uvmGpuTsgHandle channel_get_tsg(uvm_channel_t *channel) +{ + unsigned tsg_index = 0; + uvm_channel_pool_t *pool = channel->pool; + + if (uvm_channel_pool_is_wlc(pool) || uvm_channel_pool_is_lcic(pool)) { + if (uvm_channel_pool_is_lcic(pool)) { + channel = lcic_get_paired_wlc(channel); + pool = channel->pool; + } + + tsg_index = uvm_channel_index_in_pool(channel); + } + UVM_ASSERT(tsg_index < pool->num_tsgs); + + return pool->tsg_handles[tsg_index]; +} + +static NV_STATUS internal_channel_create(uvm_channel_t *channel) { NV_STATUS status; UvmGpuChannelAllocParams channel_alloc_params; @@ -802,25 +1634,29 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel, unsigned engine uvm_gpu_t *gpu = manager->gpu; memset(&channel_alloc_params, 0, sizeof(channel_alloc_params)); - channel_alloc_params.numGpFifoEntries = manager->conf.num_gpfifo_entries; + channel_alloc_params.numGpFifoEntries = channel_pool_type_num_gpfifo_entries(manager, channel->pool->pool_type); channel_alloc_params.gpFifoLoc = manager->conf.gpfifo_loc; channel_alloc_params.gpPutLoc = manager->conf.gpput_loc; - channel_alloc_params.engineIndex = engine_index; - if (uvm_channel_is_ce(channel)) { - UVM_ASSERT(channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE); + if (uvm_channel_is_sec2(channel)) { + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); - channel_alloc_params.engineType = UVM_GPU_CHANNEL_ENGINE_TYPE_CE; + // SEC2 channels' GPPUT and GPFIFO must be allocated in sysmem. + channel_alloc_params.gpFifoLoc = UVM_BUFFER_LOCATION_SYS; + channel_alloc_params.gpPutLoc = UVM_BUFFER_LOCATION_SYS; } - status = uvm_rm_locked_call(nvUvmInterfaceChannelAllocate(gpu->rm_address_space, + channel_alloc_params.secure = channel->pool->secure; + + status = uvm_rm_locked_call(nvUvmInterfaceChannelAllocate(channel_get_tsg(channel), &channel_alloc_params, &channel->handle, channel_info)); if (status != NV_OK) { - UVM_ERR_PRINT("nvUvmInterfaceChannelAllocate() failed: %s, GPU %s\n", + UVM_ERR_PRINT("nvUvmInterfaceChannelAllocate() failed: %s, GPU %s, type %s\n", nvstatusToString(status), - uvm_gpu_name(gpu)); + uvm_gpu_name(gpu), + uvm_channel_pool_type_to_string(channel->pool->pool_type)); return status; } @@ -831,8 +1667,11 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel, unsigned engine channel_info->hwChannelId, channel_info->hwRunlistId, channel_info->hwChannelId, - "CE", - engine_index); + uvm_channel_is_sec2(channel) ? "SEC2" : + uvm_channel_is_wlc(channel) ? "WLC" : + uvm_channel_is_lcic(channel) ? "LCIC" : + uvm_channel_is_secure(channel) ? "CE (secure)" : "CE", + channel->pool->engine_index); return NV_OK; } @@ -872,6 +1711,7 @@ static NV_STATUS channel_create(uvm_channel_pool_t *pool, uvm_channel_t *channel NV_STATUS status; uvm_channel_manager_t *manager = pool->manager; uvm_gpu_t *gpu = manager->gpu; + uvm_gpu_semaphore_pool_t *semaphore_pool = gpu->semaphore_pool; unsigned int i; UVM_ASSERT(channel != NULL); @@ -882,7 +1722,10 @@ static NV_STATUS channel_create(uvm_channel_pool_t *pool, uvm_channel_t *channel channel->tools.pending_event_count = 0; INIT_LIST_HEAD(&channel->tools.channel_list_node); - status = uvm_gpu_tracking_semaphore_alloc(gpu->semaphore_pool, &channel->tracking_sem); + if (uvm_conf_computing_mode_enabled(gpu) && !uvm_channel_is_sec2(channel)) + semaphore_pool = gpu->secure_semaphore_pool; + + status = uvm_gpu_tracking_semaphore_alloc(semaphore_pool, &channel->tracking_sem); if (status != NV_OK) { UVM_ERR_PRINT("uvm_gpu_tracking_semaphore_alloc() failed: %s, GPU %s\n", nvstatusToString(status), @@ -893,18 +1736,32 @@ static NV_STATUS channel_create(uvm_channel_pool_t *pool, uvm_channel_t *channel if (uvm_channel_is_proxy(channel)) status = proxy_channel_create(channel, pool->engine_index); else - status = internal_channel_create(channel, pool->engine_index); + status = internal_channel_create(channel); if (status != NV_OK) goto error; - channel->num_gpfifo_entries = manager->conf.num_gpfifo_entries; + channel->num_gpfifo_entries = channel_pool_type_num_gpfifo_entries(manager, pool->pool_type); channel->gpfifo_entries = uvm_kvmalloc_zero(sizeof(*channel->gpfifo_entries) * channel->num_gpfifo_entries); if (channel->gpfifo_entries == NULL) { status = NV_ERR_NO_MEMORY; goto error; } + if (uvm_channel_is_secure(channel)) { + status = csl_init(channel); + if (status != NV_OK) + goto error; + + if (uvm_channel_is_ce(channel)) { + // Must happen after the channel's num_gpfifo_entries is known, as + // UVM needs one IV slot per GPFIFO entry. + status = alloc_conf_computing_buffers(channel); + if (status != NV_OK) + goto error; + } + } + channel->push_infos = uvm_kvmalloc_zero(sizeof(*channel->push_infos) * channel->num_gpfifo_entries); if (channel->push_infos == NULL) { status = NV_ERR_NO_MEMORY; @@ -960,8 +1817,14 @@ static NV_STATUS channel_init(uvm_channel_t *channel) if (uvm_gpu_has_pushbuffer_segments(gpu)) { NvU64 gpfifo_entry; uvm_pushbuffer_t *pushbuffer = channel->pool->manager->pushbuffer; - gpu->parent->host_hal->set_gpfifo_pushbuffer_segment_base(&gpfifo_entry, - uvm_pushbuffer_get_gpu_va_base(pushbuffer)); + NvU64 pb_base = uvm_pushbuffer_get_gpu_va_base(pushbuffer); + + if (uvm_channel_is_sec2(channel)) + pb_base = uvm_pushbuffer_get_sec2_gpu_va_base(pushbuffer); + else if (channel->conf_computing.static_pb_protected_vidmem) + pb_base = uvm_rm_mem_get_gpu_uvm_va(channel->conf_computing.static_pb_protected_vidmem, gpu); + + gpu->parent->host_hal->set_gpfifo_pushbuffer_segment_base(&gpfifo_entry, pb_base); write_ctrl_gpfifo(channel, gpfifo_entry); } @@ -973,12 +1836,20 @@ static NV_STATUS channel_init(uvm_channel_t *channel) if (uvm_channel_is_ce(channel)) gpu->parent->ce_hal->init(&push); + else if (uvm_channel_is_sec2(channel)) + gpu->parent->sec2_hal->init(&push); + else + UVM_ASSERT_MSG(0, "Unknown channel type!"); gpu->parent->host_hal->init(&push); status = uvm_push_end_and_wait(&push); - if (status != NV_OK) - UVM_ERR_PRINT("Channel init failed: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); + if (status != NV_OK) { + UVM_ERR_PRINT("Channel '%s' init failed: %s, GPU %s\n", + channel->name, + nvstatusToString(status), + uvm_gpu_name(gpu)); + } return status; } @@ -998,17 +1869,93 @@ static unsigned channel_pool_type_num_channels(uvm_channel_pool_type_t pool_type if (pool_type == UVM_CHANNEL_POOL_TYPE_CE_PROXY) return 1; + // Not all GPU architectures support more than 1 channel per TSG. Since SEC2 + // is not in UVM critical path for performance, we conservatively create a + // pool/TSG with a single channel. + if (pool_type == UVM_CHANNEL_POOL_TYPE_SEC2) + return 1; + + if (pool_type == UVM_CHANNEL_POOL_TYPE_WLC || pool_type == UVM_CHANNEL_POOL_TYPE_LCIC) + return UVM_PUSH_MAX_CONCURRENT_PUSHES; + return 2; } +// Number of TSGs to create in a pool of a given type. +static unsigned channel_pool_type_num_tsgs(uvm_channel_pool_type_t pool_type) +{ + // For WLC and LCIC channels, we create one TSG per WLC/LCIC channel pair. + // The TSG is stored in the WLC pool. + if (pool_type == UVM_CHANNEL_POOL_TYPE_WLC) + return channel_pool_type_num_channels(pool_type); + else if (pool_type == UVM_CHANNEL_POOL_TYPE_LCIC) + return 0; + + return 1; +} + +static bool pool_type_is_valid(uvm_channel_pool_type_t pool_type) +{ + return(is_power_of_2(pool_type) && (pool_type < UVM_CHANNEL_POOL_TYPE_MASK)); +} + +static UVM_GPU_CHANNEL_ENGINE_TYPE pool_type_to_engine_type(uvm_channel_pool_type_t pool_type) +{ + if (pool_type == UVM_CHANNEL_POOL_TYPE_SEC2) + return UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2; + return UVM_GPU_CHANNEL_ENGINE_TYPE_CE; +} + +static void tsg_destroy(uvm_channel_pool_t *pool, uvmGpuTsgHandle tsg_handle) +{ + UVM_ASSERT(pool->num_tsgs > 0); + + uvm_rm_locked_call_void(nvUvmInterfaceTsgDestroy(tsg_handle)); + pool->num_tsgs--; +} + +static NV_STATUS tsg_create(uvm_channel_pool_t *pool, uvmGpuTsgHandle *tsg_handle) +{ + NV_STATUS status; + UvmGpuTsgAllocParams tsg_alloc_params; + uvm_gpu_t *gpu = pool->manager->gpu; + + pool->num_tsgs++; + + tsg_alloc_params.engineType = pool_type_to_engine_type(pool->pool_type); + tsg_alloc_params.engineIndex = pool->engine_index; + + status = uvm_rm_locked_call(nvUvmInterfaceTsgAllocate(gpu->rm_address_space, &tsg_alloc_params, tsg_handle)); + if (status != NV_OK) { + UVM_ERR_PRINT("nvUvmInterfaceTsgAllocate() failed: %s, GPU %s, type %s\n", + nvstatusToString(status), + uvm_gpu_name(gpu), + uvm_channel_pool_type_to_string(pool->pool_type)); + goto error; + } + + return NV_OK; + +error: + tsg_destroy(pool, *tsg_handle); + + return status; +} + static void channel_pool_destroy(uvm_channel_pool_t *pool) { UVM_ASSERT(pool->manager->num_channel_pools > 0); while (pool->num_channels > 0) channel_destroy(pool, pool->channels + pool->num_channels - 1); - uvm_kvfree(pool->channels); + pool->channels = NULL; + + while (pool->num_tsgs > 0) + tsg_destroy(pool, *(pool->tsg_handles + pool->num_tsgs - 1)); + uvm_kvfree(pool->tsg_handles); + pool->tsg_handles = NULL; + pool->manager->num_channel_pools--; } @@ -1020,23 +1967,56 @@ static NV_STATUS channel_pool_add(uvm_channel_manager_t *channel_manager, NV_STATUS status; unsigned i; unsigned num_channels; + unsigned num_tsgs; uvm_channel_pool_t *pool; + UVM_ASSERT(pool_type_is_valid(pool_type)); + pool = channel_manager->channel_pools + channel_manager->num_channel_pools; + channel_manager->num_channel_pools++; + pool->manager = channel_manager; pool->engine_index = engine_index; pool->pool_type = pool_type; + num_tsgs = channel_pool_type_num_tsgs(pool_type); + if (num_tsgs != 0) { + pool->tsg_handles = uvm_kvmalloc_zero(sizeof(*pool->tsg_handles) * num_tsgs); + if (!pool->tsg_handles) { + status = NV_ERR_NO_MEMORY; + goto error; + } + + for (i = 0; i < num_tsgs; i++) { + uvmGpuTsgHandle *tsg_handle = pool->tsg_handles + i; + + status = tsg_create(pool, tsg_handle); + if (status != NV_OK) + goto error; + } + } + channel_pool_lock_init(pool); num_channels = channel_pool_type_num_channels(pool_type); UVM_ASSERT(num_channels <= UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL); - pool->channels = uvm_kvmalloc_zero(sizeof(*pool->channels) * num_channels); - if (!pool->channels) - return NV_ERR_NO_MEMORY; + if (pool->secure) { + // Use different order lock for SEC2 and WLC channels. + // This allows reserving a SEC2 or WLC channel for indirect work + // submission while holding a reservation for a secure channel. + uvm_lock_order_t order = uvm_channel_pool_is_sec2(pool) ? UVM_LOCK_ORDER_CSL_SEC2_PUSH : + (uvm_channel_pool_is_wlc(pool) ? UVM_LOCK_ORDER_CSL_WLC_PUSH : + UVM_LOCK_ORDER_CSL_PUSH); - channel_manager->num_channel_pools++; + uvm_sema_init(&pool->push_sem, num_channels, order); + } + + pool->channels = uvm_kvmalloc_zero(sizeof(*pool->channels) * num_channels); + if (!pool->channels) { + status = NV_ERR_NO_MEMORY; + goto error; + } for (i = 0; i < num_channels; i++) { uvm_channel_t *channel = pool->channels + i; @@ -1058,6 +2038,23 @@ static NV_STATUS channel_pool_add(uvm_channel_manager_t *channel_manager, return status; } +static NV_STATUS channel_pool_add_secure(uvm_channel_manager_t *channel_manager, + uvm_channel_pool_type_t pool_type, + unsigned engine_index, + uvm_channel_pool_t **pool_out) +{ + uvm_channel_pool_t *pool = channel_manager->channel_pools + channel_manager->num_channel_pools; + + pool->secure = true; + return channel_pool_add(channel_manager, pool_type, engine_index, pool_out); +} + +bool uvm_channel_type_requires_secure_pool(uvm_gpu_t *gpu, uvm_channel_type_t channel_type) +{ + // For now, all channels are secure channels + return true; +} + static bool ce_usable_for_channel_type(uvm_channel_type_t type, const UvmGpuCopyEngineCaps *cap) { if (!cap->supported || cap->grce) @@ -1205,6 +2202,13 @@ static NV_STATUS pick_ce_for_channel_type(uvm_channel_manager_t *manager, if (!ce_usable_for_channel_type(type, cap)) continue; + if (uvm_conf_computing_mode_is_hcc(manager->gpu)) { + // All usable CEs are secure + UVM_ASSERT(cap->secure); + + // Multi-PCE LCEs are disallowed + UVM_ASSERT(hweight32(cap->cePceMask) == 1); + } __set_bit(i, manager->ce_mask); if (best_ce == UVM_COPY_ENGINE_COUNT_MAX) { @@ -1229,32 +2233,38 @@ static NV_STATUS channel_manager_pick_copy_engines(uvm_channel_manager_t *manage { NV_STATUS status; unsigned i; - UvmGpuCopyEnginesCaps ces_caps; + UvmGpuCopyEnginesCaps *ces_caps; uvm_channel_type_t types[] = {UVM_CHANNEL_TYPE_CPU_TO_GPU, UVM_CHANNEL_TYPE_GPU_TO_CPU, UVM_CHANNEL_TYPE_GPU_INTERNAL, UVM_CHANNEL_TYPE_GPU_TO_GPU, UVM_CHANNEL_TYPE_MEMOPS}; - memset(&ces_caps, 0, sizeof(ces_caps)); - status = uvm_rm_locked_call(nvUvmInterfaceQueryCopyEnginesCaps(uvm_gpu_device_handle(manager->gpu), &ces_caps)); + ces_caps = uvm_kvmalloc_zero(sizeof(*ces_caps)); + if (!ces_caps) + return NV_ERR_NO_MEMORY; + + status = uvm_rm_locked_call(nvUvmInterfaceQueryCopyEnginesCaps(uvm_gpu_device_handle(manager->gpu), ces_caps)); if (status != NV_OK) - return status; + goto out; // The order of picking CEs for each type matters as it's affected by the // usage count of each CE and it increases every time a CE is selected. // MEMOPS has the least priority as it only cares about low usage of the // CE to improve latency for (i = 0; i < ARRAY_SIZE(types); ++i) { - status = pick_ce_for_channel_type(manager, ces_caps.copyEngineCaps, types[i], preferred_ce); + status = pick_ce_for_channel_type(manager, ces_caps->copyEngineCaps, types[i], preferred_ce); if (status != NV_OK) - return status; + goto out; } - return NV_OK; +out: + uvm_kvfree(ces_caps); + + return status; } -// Return the pool corresponding to the given CE index +// Return the non-secure pool corresponding to the given CE index // // This function cannot be used to access the proxy pool in SR-IOV heavy. static uvm_channel_pool_t *channel_manager_ce_pool(uvm_channel_manager_t *manager, NvU32 ce) @@ -1342,6 +2352,28 @@ static void init_channel_manager_conf(uvm_channel_manager_t *manager) // 2- Allocation locations + if (uvm_conf_computing_mode_is_hcc(gpu)) { + UVM_ASSERT(gpu->mem_info.size > 0); + + // When the Confidential Computing feature is enabled, the GPU is + // guaranteed to have a frame buffer and the hardware enforces the + // following apertures for all channel types but SEC2. We create SEC2 + // channels by overriding their GPPUT and GPFIFO locations and ignoring + // the location from the channel manager. SEC2 channels are used to + // bootstrap secure work submission. To setup secure work launch, data + // transfers from unprotected main memory to protected vidmem are + // performed by the SEC2 engine and the driver must push work to SEC2 + // channels using unprotected locations. + manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_VID; + manager->conf.gpput_loc = UVM_BUFFER_LOCATION_VID; + + // Pushbuffer is located in unprotected sysmem. This is the location + // that gets mapped to both CPU and GPU. It is populated either by + // signed pushes (SEC2 channels), or encrypted pushes (CE channels). + manager->conf.pushbuffer_loc = UVM_BUFFER_LOCATION_SYS; + return; + } + // Override if the GPU doesn't have memory if (gpu->mem_info.size == 0) { manager->conf.pushbuffer_loc = UVM_BUFFER_LOCATION_SYS; @@ -1406,16 +2438,20 @@ static void init_channel_manager_conf(uvm_channel_manager_t *manager) gpput_loc_value); } - // By default we place GPFIFO and GPPUT on vidmem as it potentially has - // lower latency. - manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_VID; - manager->conf.gpput_loc = UVM_BUFFER_LOCATION_VID; - - // TODO: Bug 1766129: However, this will likely be different on P9 systems. - // Leaving GPFIFO on sysmem for now. GPPut on sysmem is not supported in - // production, so we keep it on vidmem, too. - if (gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_2) + // On coherent platforms where the GPU does not cache sysmem but the CPU + // caches vidmem (and sysmem), we place GPFIFO and GPPUT on sysmem to avoid + // cache thrash. The memory access latency is reduced, despite the required + // access through the bus, because no cache coherence message is exchanged. + if (uvm_gpu_is_coherent(gpu->parent)) { manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_SYS; + manager->conf.gpput_loc = UVM_BUFFER_LOCATION_SYS; + } + else { + // By default we place GPFIFO and GPPUT on vidmem as it potentially has + // lower latency. + manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_VID; + manager->conf.gpput_loc = UVM_BUFFER_LOCATION_VID; + } // Override defaults if (string_to_buffer_location(gpfifo_loc_value) != UVM_BUFFER_LOCATION_DEFAULT) @@ -1440,6 +2476,16 @@ static unsigned channel_manager_get_max_pools(uvm_channel_manager_t *manager) if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) num_channel_pools++; + if (uvm_conf_computing_mode_enabled(manager->gpu)) { + + // Create one CE secure channel pool per usable CE + if (uvm_conf_computing_mode_is_hcc(manager->gpu)) + num_channel_pools += num_used_ce; + + // SEC2 pool, WLC pool, LCIC pool + num_channel_pools += 3; + } + return num_channel_pools; } @@ -1461,11 +2507,373 @@ static NV_STATUS channel_manager_create_ce_pools(uvm_channel_manager_t *manager, return status; for (type = 0; type < UVM_CHANNEL_TYPE_CE_COUNT; type++) { - if (preferred_ce[type] == ce) + // Set pool type if it hasn't been set before. + if (preferred_ce[type] == ce && manager->pool_to_use.default_for_type[type] == NULL) + manager->pool_to_use.default_for_type[type] = pool; + } + } + + return NV_OK; +} + +static NV_STATUS channel_manager_create_ce_secure_pools(uvm_channel_manager_t *manager, unsigned *preferred_ce) +{ + unsigned ce; + + if (!uvm_conf_computing_mode_is_hcc(manager->gpu)) + return NV_OK; + + for_each_set_bit(ce, manager->ce_mask, UVM_COPY_ENGINE_COUNT_MAX) { + NV_STATUS status; + unsigned type; + uvm_channel_pool_t *pool = NULL; + + status = channel_pool_add_secure(manager, UVM_CHANNEL_POOL_TYPE_CE, ce, &pool); + if (status != NV_OK) + return status; + + for (type = 0; type < UVM_CHANNEL_TYPE_CE_COUNT; type++) { + unsigned preferred = preferred_ce[type]; + + if (preferred != ce) + continue; + + if (uvm_channel_type_requires_secure_pool(manager->gpu, type)) { + UVM_ASSERT(manager->pool_to_use.default_for_type[type] == NULL); manager->pool_to_use.default_for_type[type] = pool; + } + } + } + + return NV_OK; +} + +static NV_STATUS setup_wlc_schedule(uvm_channel_t *wlc) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(wlc); + NvU64 protected_vidmem = uvm_rm_mem_get_gpu_uvm_va(wlc->conf_computing.static_pb_protected_vidmem, gpu); + NvU64 unprotected_sysmem_gpu = uvm_rm_mem_get_gpu_uvm_va(wlc->conf_computing.static_pb_unprotected_sysmem, gpu); + void *unprotected_sysmem_cpu = wlc->conf_computing.static_pb_unprotected_sysmem_cpu; + NvU64 tag_offset = (uintptr_t)wlc->conf_computing.static_pb_unprotected_sysmem_auth_tag_cpu - + (uintptr_t)wlc->conf_computing.static_pb_unprotected_sysmem_cpu; + + NvU64 *wlc_gpfifo_entries; + uvm_push_t wlc_decrypt_push, sec2_push; + NvU32 decrypt_push_size; + int i; + NV_STATUS status = NV_OK; + + // "gpfifo" is the representation of GPFIFO copied to gpFifoGpu + const size_t gpfifo_size = wlc->num_gpfifo_entries * sizeof(*wlc_gpfifo_entries); + void *gpfifo_unprotected_cpu = unprotected_sysmem_cpu; + NvU64 gpfifo_unprotected_gpu = unprotected_sysmem_gpu; + + // "run_push" represents mutable push location used by WLC + uvm_gpu_address_t run_push_protected_gpu = uvm_gpu_address_virtual(protected_vidmem); + uvm_gpu_address_t run_push_unprotected_gpu = uvm_gpu_address_virtual(unprotected_sysmem_gpu); + uvm_gpu_address_t run_push_unprotected_auth_tag_gpu = uvm_gpu_address_virtual(unprotected_sysmem_gpu + tag_offset); + + // "decrypt_push" represents WLC decrypt push, constructed using fake_push. + // Copied to wlc_pb_base + UVM_MAX_WLC_PUSH_SIZE, as the second of the two + // pushes that make the WLC fixed schedule. + NvU64 decrypt_push_protected_gpu = protected_vidmem + UVM_MAX_WLC_PUSH_SIZE; + NvU64 decrypt_push_unprotected_gpu = unprotected_sysmem_gpu + gpfifo_size; + void *decrypt_push_unprotected_cpu = (char*)gpfifo_unprotected_cpu + gpfifo_size; + + // Tags for upload via SEC2 + void *decrypt_push_auth_tag, *gpfifo_auth_tag; + uvm_gpu_address_t decrypt_push_auth_tag_gpu, gpfifo_auth_tag_gpu; + + BUILD_BUG_ON(sizeof(*wlc_gpfifo_entries) != sizeof(*wlc->channel_info.gpFifoEntries)); + + UVM_ASSERT(uvm_channel_is_wlc(wlc)); + UVM_ASSERT(tag_offset == UVM_MAX_WLC_PUSH_SIZE); + + // WLC schedule consists of two parts, the number of entries needs to be even. + // This also guarantees that the size is 16B aligned + UVM_ASSERT(IS_ALIGNED(wlc->num_gpfifo_entries, 2)); + + wlc_gpfifo_entries = uvm_kvmalloc(gpfifo_size); + if (!wlc_gpfifo_entries) + return NV_ERR_NO_MEMORY; + + // WLC can only process one job at a time. + // Prune any initialization entries and block all but one (+1 for sentinel) + uvm_channel_update_progress(wlc); + if (!try_claim_channel(wlc, wlc->num_gpfifo_entries - 2)) { + status = NV_ERR_INVALID_STATE; + goto free_gpfifo_entries; + } + + // WLC schedule has two steps: + // 1.) Decrypt from gpu_unprotected_base to wlc_pb_base + // Increment LCIC PUT + // 2.) Execute push at wlc_pb_base + // The first one is a push, the second one is just a GPFIFO entry + status = uvm_push_begin_fake(gpu, &wlc_decrypt_push); + if (status != NV_OK) + goto free_gpfifo_entries; + + // Begin WLC DECRYPT push + uvm_push_set_flag(&wlc_decrypt_push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + gpu->parent->ce_hal->decrypt(&wlc_decrypt_push, + run_push_protected_gpu, + run_push_unprotected_gpu, + UVM_MAX_WLC_PUSH_SIZE, + run_push_unprotected_auth_tag_gpu); + uvm_hal_wfi_membar(&wlc_decrypt_push, UVM_MEMBAR_NONE); + decrypt_push_size = uvm_push_get_size(&wlc_decrypt_push); + + // The code below reuses static unprotected sysmem buffer as a temporary + // storage for uploading the schedule. Check that everything fits. + UVM_ASSERT(gpfifo_size + decrypt_push_size <= UVM_MAX_WLC_PUSH_SIZE); + + // GPFIFO schedule should alternate between the decrypt routine + // we don't know if initialization used even or odd number of + // GPFIFO entries so the exact pattern depends on the value of "PUT" + for (i = 0; i < wlc->num_gpfifo_entries; ++i) { + if (i % 2 == wlc->cpu_put % 2) { + gpu->parent->host_hal->set_gpfifo_entry(wlc_gpfifo_entries + i, + decrypt_push_protected_gpu, + decrypt_push_size, + UVM_GPFIFO_SYNC_PROCEED); + } + else { + gpu->parent->host_hal->set_gpfifo_entry(wlc_gpfifo_entries + i, + run_push_protected_gpu.address, + UVM_MAX_WLC_PUSH_SIZE, + UVM_GPFIFO_SYNC_WAIT); } } + // The schedule is prepared. Upload to vidmem + status = uvm_push_begin(wlc->pool->manager, + UVM_CHANNEL_TYPE_SEC2, + &sec2_push, + "Upload WLC schedule for: %s", wlc->name); + if (status != NV_OK) + goto end_wlc_dec_push; + + decrypt_push_auth_tag = uvm_push_get_single_inline_buffer(&sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &decrypt_push_auth_tag_gpu); + + gpfifo_auth_tag = uvm_push_get_single_inline_buffer(&sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &gpfifo_auth_tag_gpu); + + // Upload WLC pushbuffer + uvm_conf_computing_cpu_encrypt(sec2_push.channel, + decrypt_push_unprotected_cpu, + wlc_decrypt_push.begin, + NULL, + decrypt_push_size, + decrypt_push_auth_tag); + gpu->parent->sec2_hal->decrypt(&sec2_push, + decrypt_push_protected_gpu, + decrypt_push_unprotected_gpu, + decrypt_push_size, + decrypt_push_auth_tag_gpu.address); + + // Upload WLC GPFIFO + uvm_conf_computing_cpu_encrypt(sec2_push.channel, + gpfifo_unprotected_cpu, + wlc_gpfifo_entries, + NULL, + gpfifo_size, + gpfifo_auth_tag); + gpu->parent->sec2_hal->decrypt(&sec2_push, + wlc->channel_info.gpFifoGpuVa, + gpfifo_unprotected_gpu, + gpfifo_size, + gpfifo_auth_tag_gpu.address); + + // Prime the WLC by setting "PUT" two steps ahead. Reuse the current + // cpu_put value that was used during channel initialization. + // Don't update wlc->cpu_put, it will be used to track + // submitted pushes as any other channel. + do_semaphore_release(&sec2_push, + wlc->channel_info.gpPutGpuVa, + (wlc->cpu_put + 2) % wlc->num_gpfifo_entries); + + status = uvm_push_end_and_wait(&sec2_push); + +end_wlc_dec_push: + uvm_push_end_fake(&wlc_decrypt_push); +free_gpfifo_entries: + uvm_kvfree(wlc_gpfifo_entries); + return status; +} + +static NV_STATUS setup_lcic_schedule(uvm_channel_t *paired_wlc, uvm_channel_t *lcic) +{ + uvm_gpu_t *gpu = uvm_channel_get_gpu(lcic); + NvU64 lcic_pb_base = uvm_rm_mem_get_gpu_uvm_va(lcic->conf_computing.static_pb_protected_vidmem, gpu); + + // Reuse WLC sysmem allocation + NvU64 gpu_unprotected = uvm_rm_mem_get_gpu_uvm_va(paired_wlc->conf_computing.static_pb_unprotected_sysmem, gpu); + char *cpu_unprotected = paired_wlc->conf_computing.static_pb_unprotected_sysmem_cpu; + uvm_gpu_semaphore_t *lcic_gpu_semaphore = &lcic->tracking_sem.semaphore; + uvm_gpu_address_t notifier_src_entry_addr = lcic->conf_computing.static_notifier_entry_unprotected_sysmem_gpu_va; + uvm_gpu_address_t notifier_src_exit_addr = lcic->conf_computing.static_notifier_exit_unprotected_sysmem_gpu_va; + uvm_gpu_address_t notifier_dst_addr = uvm_rm_mem_get_gpu_va(lcic_gpu_semaphore->conf_computing.notifier, + gpu, + false); + uvm_gpu_address_t encrypted_payload_gpu_va = + uvm_rm_mem_get_gpu_va(lcic_gpu_semaphore->conf_computing.encrypted_payload, gpu, false); + uvm_gpu_address_t semaphore_gpu_va = uvm_gpu_address_virtual(uvm_channel_tracking_semaphore_get_gpu_va(lcic)); + uvm_gpu_address_t auth_tag_gpu_va = uvm_rm_mem_get_gpu_va(lcic_gpu_semaphore->conf_computing.auth_tag, gpu, false); + NvU32 payload_size = sizeof(*lcic->tracking_sem.semaphore.payload); + NvU32 notifier_size = sizeof(*lcic->conf_computing.static_notifier_entry_unprotected_sysmem_cpu); + + NvU64 *lcic_gpfifo_entries; + uvm_push_t lcic_push, sec2_push; + NvU32 lcic_push_size; + int i; + NV_STATUS status; + + const size_t gpfifo_size = lcic->num_gpfifo_entries * sizeof(*lcic_gpfifo_entries); + char *gpfifo_unprotected_cpu = cpu_unprotected; + NvU64 gpfifo_unprotected_gpu = gpu_unprotected; + char *lcic_push_unprotected_cpu = gpfifo_unprotected_cpu + gpfifo_size; + NvU64 lcic_push_unprotected_gpu = gpfifo_unprotected_gpu + gpfifo_size; + NvU64 lcic_push_protected_gpu = lcic_pb_base; + + char *lcic_push_enc_tag, *gpfifo_enc_tag; + uvm_gpu_address_t lcic_push_enc_tag_gpu, gpfifo_enc_tag_gpu; + + BUILD_BUG_ON(sizeof(*lcic_gpfifo_entries) != sizeof(*lcic->channel_info.gpFifoEntries)); + + UVM_ASSERT(uvm_channel_is_wlc(paired_wlc)); + UVM_ASSERT(uvm_channel_is_lcic(lcic)); + + lcic_gpfifo_entries = uvm_kvmalloc(gpfifo_size); + if (!lcic_gpfifo_entries) + return NV_ERR_NO_MEMORY; + + // LCIC can not process outside jobs. + // Prune any initialization entries and + // block all gpfifo entries (-1 for sentinel) + uvm_channel_update_progress(lcic); + if (!try_claim_channel(lcic, lcic->num_gpfifo_entries - 1)) { + status = NV_ERR_INVALID_STATE; + goto free_gpfifo_entries; + } + + status = uvm_push_begin_fake(gpu, &lcic_push); + if (status != NV_OK) + goto free_gpfifo_entries; + + // LCIC schedule is simple: + // 1.) wait for engine idle + // 2.) advance the WLC PUT by 2 + // 3.) release driver semaphore + uvm_hal_wfi_membar(&lcic_push, UVM_MEMBAR_NONE); + gpu->parent->ce_hal->semaphore_reduction_inc(&lcic_push, + paired_wlc->channel_info.gpPutGpuVa, + paired_wlc->num_gpfifo_entries - 1); + gpu->parent->ce_hal->semaphore_reduction_inc(&lcic_push, + paired_wlc->channel_info.gpPutGpuVa, + paired_wlc->num_gpfifo_entries - 1); + gpu->parent->ce_hal->semaphore_reduction_inc(&lcic_push, + semaphore_gpu_va.address, + 0xffffffff); + + gpu->parent->ce_hal->memcopy(&lcic_push, notifier_dst_addr, notifier_src_entry_addr, notifier_size); + gpu->parent->ce_hal->encrypt(&lcic_push, encrypted_payload_gpu_va, semaphore_gpu_va, payload_size, auth_tag_gpu_va); + gpu->parent->ce_hal->memcopy(&lcic_push, notifier_dst_addr, notifier_src_exit_addr, notifier_size); + + // End LCIC push + lcic_push_size = uvm_push_get_size(&lcic_push); + + // We're reusing pre-allocated structures from WLC, make sure we fit. + UVM_ASSERT(lcic_push_size == UVM_LCIC_PUSH_SIZE); + UVM_ASSERT(lcic_push_size + gpfifo_size <= UVM_MAX_WLC_PUSH_SIZE); + + // Set all entries to execute the above push + for (i = 0; i < lcic->num_gpfifo_entries; ++i) + gpu->parent->host_hal->set_gpfifo_entry(lcic_gpfifo_entries + i, + lcic_push_protected_gpu, + lcic_push_size, + UVM_GPFIFO_SYNC_PROCEED); + + // Upload the prepared schedule using SEC2 + status = uvm_push_begin(lcic->pool->manager, + UVM_CHANNEL_TYPE_SEC2, + &sec2_push, + "Upload LCIC schedule for: %s", lcic->name); + if (status != NV_OK) + goto end_lcic_push; + + lcic_push_enc_tag = uvm_push_get_single_inline_buffer(&sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &lcic_push_enc_tag_gpu); + + gpfifo_enc_tag = uvm_push_get_single_inline_buffer(&sec2_push, + UVM_CONF_COMPUTING_AUTH_TAG_SIZE, + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT, + &gpfifo_enc_tag_gpu); + + // Upload LCIC pushbuffer + uvm_conf_computing_cpu_encrypt(sec2_push.channel, + lcic_push_unprotected_cpu, + lcic_push.begin, + NULL, + lcic_push_size, + lcic_push_enc_tag); + gpu->parent->sec2_hal->decrypt(&sec2_push, + lcic_push_protected_gpu, + lcic_push_unprotected_gpu, + lcic_push_size, + lcic_push_enc_tag_gpu.address); + + // Upload LCIC GPFIFO + uvm_conf_computing_cpu_encrypt(sec2_push.channel, + gpfifo_unprotected_cpu, + lcic_gpfifo_entries, + NULL, + gpfifo_size, + gpfifo_enc_tag); + gpu->parent->sec2_hal->decrypt(&sec2_push, + lcic->channel_info.gpFifoGpuVa, + gpfifo_unprotected_gpu, + gpfifo_size, + gpfifo_enc_tag_gpu.address); + status = uvm_push_end_and_wait(&sec2_push); + +end_lcic_push: + uvm_push_end_fake(&lcic_push); +free_gpfifo_entries: + uvm_kvfree(lcic_gpfifo_entries); + return status; +} + +static NV_STATUS channel_manager_setup_wlc_lcic(uvm_channel_pool_t *wlc_pool, uvm_channel_pool_t *lcic_pool) +{ + NvU32 i; + + UVM_ASSERT(wlc_pool->manager == lcic_pool->manager); + UVM_ASSERT(wlc_pool->manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC] != NULL); + UVM_ASSERT(lcic_pool->manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC] == NULL); + UVM_ASSERT(wlc_pool->num_channels == lcic_pool->num_channels); + + for (i = 0; i < wlc_pool->num_channels; ++i) { + uvm_channel_t *wlc = wlc_pool->channels + i; + uvm_channel_t *lcic = lcic_pool->channels + i; + NV_STATUS status; + + status = setup_wlc_schedule(wlc); + if (status != NV_OK) + return status; + + status = setup_lcic_schedule(wlc, lcic); + if (status != NV_OK) + return status; + } + return NV_OK; } @@ -1475,7 +2883,6 @@ static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) uvm_channel_type_t type; unsigned max_channel_pools; unsigned preferred_ce[UVM_CHANNEL_TYPE_CE_COUNT]; - uvm_channel_pool_t *pool = NULL; for (type = 0; type < ARRAY_SIZE(preferred_ce); type++) preferred_ce[type] = UVM_COPY_ENGINE_COUNT_MAX; @@ -1490,20 +2897,76 @@ static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) if (!manager->channel_pools) return NV_ERR_NO_MEMORY; - status = channel_manager_create_ce_pools(manager, preferred_ce); + if (uvm_conf_computing_mode_enabled(manager->gpu)) { + uvm_channel_pool_t *sec2_pool = NULL; + uvm_channel_pool_t *wlc_pool = NULL; + uvm_channel_pool_t *lcic_pool = NULL; + unsigned wlc_lcic_ce_index; + + status = uvm_rm_mem_alloc(manager->gpu, + UVM_RM_MEM_TYPE_SYS, + sizeof(UvmCslIv), + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &manager->gpu->conf_computing.iv_rm_mem); + + if (status != NV_OK) + return status; + + // Create SEC2 pool. This needs to be done first, initialization of + // other channels needs SEC2. + status = channel_pool_add_secure(manager, UVM_CHANNEL_POOL_TYPE_SEC2, 0, &sec2_pool); + if (status != NV_OK) + return status; + + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_SEC2] = sec2_pool; + + // Use the same CE as CPU TO GPU channels for WLC/LCIC + // Both need to use the same engine for the fixed schedule to work. + // TODO: Bug 3981928: [hcc][uvm] Optimize parameters of WLC/LCIC secure + // work launch + // Find a metric to select the best CE to use + wlc_lcic_ce_index = preferred_ce[UVM_CHANNEL_TYPE_CPU_TO_GPU]; + + // Create WLC/LCIC pools. This should be done early, CE channels use + // them for secure launch. The WLC pool must be created before the LCIC. + status = channel_pool_add_secure(manager, UVM_CHANNEL_POOL_TYPE_WLC, wlc_lcic_ce_index, &wlc_pool); + if (status != NV_OK) + return status; + + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC] = wlc_pool; + + status = channel_pool_add_secure(manager, UVM_CHANNEL_POOL_TYPE_LCIC, wlc_lcic_ce_index, &lcic_pool); + if (status != NV_OK) + return status; + + status = channel_manager_setup_wlc_lcic(wlc_pool, lcic_pool); + if (status != NV_OK) + return status; + + // The LCIC pool must be assigned after the call to + // channel_manager_setup_wlc_lcic(). It determines WLC and LCIC channels + // are ready to be used for secure work submission. + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC] = lcic_pool; + status = channel_manager_create_ce_secure_pools(manager, preferred_ce); + } + else { + status = channel_manager_create_ce_pools(manager, preferred_ce); + } + if (status != NV_OK) return status; // In SR-IOV heavy, add an additional, single-channel, pool that is // dedicated to the MEMOPS type. if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) { + uvm_channel_pool_t *proxy_pool = NULL; uvm_channel_type_t channel_type = uvm_channel_proxy_channel_type(); - status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_CE_PROXY, preferred_ce[channel_type], &pool); + status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_CE_PROXY, preferred_ce[channel_type], &proxy_pool); if (status != NV_OK) return status; - manager->pool_to_use.default_for_type[channel_type] = pool; + manager->pool_to_use.default_for_type[channel_type] = proxy_pool; } return NV_OK; @@ -1547,12 +3010,57 @@ NV_STATUS uvm_channel_manager_create(uvm_gpu_t *gpu, uvm_channel_manager_t **cha static void channel_manager_destroy_pools(uvm_channel_manager_t *manager) { + uvm_rm_mem_free(manager->gpu->conf_computing.iv_rm_mem); + manager->gpu->conf_computing.iv_rm_mem = NULL; while (manager->num_channel_pools > 0) channel_pool_destroy(manager->channel_pools + manager->num_channel_pools - 1); uvm_kvfree(manager->channel_pools); } +// Because the WLC at rest state has PUT = GET + 2, there's always pending work +// This is what enables the driver to submit work just by ringing a doorbell. +// However, this also means that the pending work has to be removed before +// the channel is passed to RM for deallocation. +static void channel_manager_stop_wlc(uvm_channel_manager_t *manager) +{ + uvm_channel_pool_t *wlc_pool = manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC]; + uvm_channel_pool_t *lcic_pool = manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC]; + uvm_channel_t *channel; + uvm_push_t push; + NV_STATUS status; + + uvm_for_each_channel_in_pool(channel, lcic_pool) { + uvm_spin_loop_t spin; + + // Wait for the WLC/LCIC to be primed. This means that PUT == GET + 2 + // and a WLC doorbell ring is enough to start work. + UVM_SPIN_WHILE(!uvm_gpu_tracking_semaphore_is_completed(&channel->tracking_sem), &spin); + } + + status = uvm_push_begin(manager, UVM_CHANNEL_TYPE_SEC2, &push, "Stop WLC channels"); + if (status != NV_OK) { + UVM_ERR_PRINT_NV_STATUS("Failed to begin stop push for WLC", status); + return; + } + + uvm_for_each_channel_in_pool(channel, wlc_pool) { + // Every gpfifo entry advances the gpu put of WLC by two so the current + // value is: (cpu_put * 2) % num_gpfifo_entries and it's ahead of the + // get pointer by 2. + do_semaphore_release(&push, + channel->channel_info.gpPutGpuVa, + (channel->cpu_put * 2 - 2) % channel->num_gpfifo_entries); + } + + status = uvm_push_end_and_wait(&push); + if (status != NV_OK) + UVM_ERR_PRINT_NV_STATUS("Failed to end stop push for WLC", status); + + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC] = NULL; + manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC] = NULL; +} + void uvm_channel_manager_destroy(uvm_channel_manager_t *channel_manager) { if (channel_manager == NULL) @@ -1560,6 +3068,9 @@ void uvm_channel_manager_destroy(uvm_channel_manager_t *channel_manager) proc_remove(channel_manager->procfs.pending_pushes); + if (uvm_channel_manager_is_wlc_ready(channel_manager)) + channel_manager_stop_wlc(channel_manager); + channel_manager_destroy_pools(channel_manager); proc_remove(channel_manager->procfs.channels_dir); @@ -1631,7 +3142,7 @@ uvm_channel_t *uvm_channel_any_of_type(uvm_channel_manager_t *manager, NvU32 poo const char *uvm_channel_type_to_string(uvm_channel_type_t channel_type) { - BUILD_BUG_ON(UVM_CHANNEL_TYPE_COUNT != 5); + BUILD_BUG_ON(UVM_CHANNEL_TYPE_COUNT != 8); switch (channel_type) { UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_CPU_TO_GPU); @@ -1639,24 +3150,45 @@ const char *uvm_channel_type_to_string(uvm_channel_type_t channel_type) UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_GPU_INTERNAL); UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_MEMOPS); UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_GPU_TO_GPU); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_SEC2); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_WLC); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_TYPE_LCIC); UVM_ENUM_STRING_DEFAULT(); } } const char *uvm_channel_pool_type_to_string(uvm_channel_pool_type_t channel_pool_type) { - BUILD_BUG_ON(UVM_CHANNEL_POOL_TYPE_COUNT != 2); + BUILD_BUG_ON(UVM_CHANNEL_POOL_TYPE_COUNT != 5); switch (channel_pool_type) { UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_CE); UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_CE_PROXY); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_SEC2); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_WLC); + UVM_ENUM_STRING_CASE(UVM_CHANNEL_POOL_TYPE_LCIC); UVM_ENUM_STRING_DEFAULT(); } } +static const char *get_gpfifo_location_string(uvm_channel_t *channel) +{ + // SEC2 channels override the channel manager location for GPFIFO. + if (uvm_channel_is_sec2(channel)) + return buffer_location_to_string(UVM_BUFFER_LOCATION_SYS); + return buffer_location_to_string(channel->pool->manager->conf.gpfifo_loc); +} + +static const char *get_gpput_location_string(uvm_channel_t *channel) +{ + // SEC2 channels override the channel manager location for GPPUT. + if (uvm_channel_is_sec2(channel)) + return buffer_location_to_string(UVM_BUFFER_LOCATION_SYS); + return buffer_location_to_string(channel->pool->manager->conf.gpput_loc); +} + static void uvm_channel_print_info(uvm_channel_t *channel, struct seq_file *s) { - uvm_channel_manager_t *manager = channel->pool->manager; UVM_SEQ_OR_DBG_PRINT(s, "Channel %s\n", channel->name); channel_pool_lock(channel->pool); @@ -1664,8 +3196,8 @@ static void uvm_channel_print_info(uvm_channel_t *channel, struct seq_file *s) UVM_SEQ_OR_DBG_PRINT(s, "completed %llu\n", uvm_channel_update_completed_value(channel)); UVM_SEQ_OR_DBG_PRINT(s, "queued %llu\n", channel->tracking_sem.queued_value); UVM_SEQ_OR_DBG_PRINT(s, "GPFIFO count %u\n", channel->num_gpfifo_entries); - UVM_SEQ_OR_DBG_PRINT(s, "GPFIFO location %s\n", buffer_location_to_string(manager->conf.gpfifo_loc)); - UVM_SEQ_OR_DBG_PRINT(s, "GPPUT location %s\n", buffer_location_to_string(manager->conf.gpput_loc)); + UVM_SEQ_OR_DBG_PRINT(s, "GPFIFO location %s\n", get_gpfifo_location_string(channel)); + UVM_SEQ_OR_DBG_PRINT(s, "GPPUT location %s\n", get_gpput_location_string(channel)); UVM_SEQ_OR_DBG_PRINT(s, "get %u\n", channel->gpu_get); UVM_SEQ_OR_DBG_PRINT(s, "put %u\n", channel->cpu_put); UVM_SEQ_OR_DBG_PRINT(s, "Semaphore GPU VA 0x%llx\n", uvm_channel_tracking_semaphore_get_gpu_va(channel)); @@ -1728,14 +3260,11 @@ static void channel_print_pushes(uvm_channel_t *channel, NvU32 finished_pushes_c continue; if (entry->type == UVM_GPFIFO_ENTRY_TYPE_CONTROL) { - NvU64 *gpfifo_entry; - UVM_ASSERT(!uvm_channel_is_proxy(channel)); - gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + gpu_get; UVM_SEQ_OR_DBG_PRINT(seq, " control GPFIFO entry - data: 0x%llx, gpu_get: %d\n", - *gpfifo_entry, + entry->control_value, gpu_get); } else { diff --git a/kernel-open/nvidia-uvm/uvm_channel.h b/kernel-open/nvidia-uvm/uvm_channel.h index 2ccb7beeb2..4b8a35afa1 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.h +++ b/kernel-open/nvidia-uvm/uvm_channel.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -51,7 +51,7 @@ #define UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MAX (1024 * 1024) // Maximum number of channels per pool. -#define UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL 8 +#define UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL UVM_PUSH_MAX_CONCURRENT_PUSHES // Semaphore payloads cannot advance too much between calls to // uvm_gpu_tracking_semaphore_update_completed_value(). In practice the jumps @@ -66,7 +66,7 @@ #define uvm_channel_pool_assert_locked(pool) ( \ { \ - if (uvm_channel_pool_is_proxy(pool)) \ + if (uvm_channel_pool_uses_mutex(pool)) \ uvm_assert_mutex_locked(&(pool)->mutex); \ else \ uvm_assert_spinlock_locked(&(pool)->spinlock); \ @@ -94,7 +94,29 @@ typedef enum // ^^^^^^ // Channel types backed by a CE. - UVM_CHANNEL_TYPE_COUNT = UVM_CHANNEL_TYPE_CE_COUNT, + // ---------------------------------- + // Channel types not backed by a CE. + // vvvvvv + + // SEC2 channels + UVM_CHANNEL_TYPE_SEC2 = UVM_CHANNEL_TYPE_CE_COUNT, + + // ---------------------------------- + // Channel type with fixed schedules + + // Work Launch Channel (WLC) is a specialized channel + // for launching work on other channels when + // Confidential Computing is enabled. + // It is paired with LCIC (below) + UVM_CHANNEL_TYPE_WLC, + + // Launch Confirmation Indicator Channel (LCIC) is a + // specialized channel with fixed schedule. It gets + // triggered by executing WLC work, and makes sure that + // WLC get/put pointers are up-to-date. + UVM_CHANNEL_TYPE_LCIC, + + UVM_CHANNEL_TYPE_COUNT, } uvm_channel_type_t; typedef enum @@ -112,7 +134,15 @@ typedef enum // There is a single proxy pool and channel per GPU. UVM_CHANNEL_POOL_TYPE_CE_PROXY = (1 << 1), - UVM_CHANNEL_POOL_TYPE_COUNT = 2, + // A pool of SEC2 channels owned by UVM. These channels are backed by a SEC2 + // engine. + UVM_CHANNEL_POOL_TYPE_SEC2 = (1 << 2), + + UVM_CHANNEL_POOL_TYPE_WLC = (1 << 3), + + UVM_CHANNEL_POOL_TYPE_LCIC = (1 << 4), + + UVM_CHANNEL_POOL_TYPE_COUNT = 5, // A mask used to select pools of any type. UVM_CHANNEL_POOL_TYPE_MASK = ((1U << UVM_CHANNEL_POOL_TYPE_COUNT) - 1) @@ -136,15 +166,23 @@ struct uvm_gpfifo_entry_struct // this entry. NvU64 tracking_semaphore_value; - // The following fields are only valid when type is - // UVM_GPFIFO_ENTRY_TYPE_NORMAL. + union { + struct { + // Offset of the pushbuffer in the pushbuffer allocation used by + // this entry. + NvU32 pushbuffer_offset; - // Offset of the pushbuffer in the pushbuffer allocation used by - // this entry. - NvU32 pushbuffer_offset; + // Size of the pushbuffer used for this entry. + NvU32 pushbuffer_size; + }; - // Size of the pushbuffer used for this entry. - NvU32 pushbuffer_size; + // Value of control entry + // Exact value of GPFIFO entry copied directly to GPFIFO[PUT] location. + NvU64 control_value; + }; + + // The following fields are only valid when type is + // UVM_GPFIFO_ENTRY_TYPE_NORMAL. // List node used by the pushbuffer tracking struct list_head pending_list_node; @@ -160,6 +198,19 @@ typedef struct // Owning channel manager uvm_channel_manager_t *manager; + // On Volta+ GPUs, all channels in a pool are members of the same TSG, i.e., + // num_tsgs is 1. Pre-Volta GPUs also have a single TSG object, but since HW + // does not support TSG for CE engines, a HW TSG is not created, but a TSG + // object is required to allocate channels. + // When Confidential Computing mode is enabled, the WLC and LCIC channel + // types require one TSG for each WLC/LCIC pair of channels. In this case, + // we do not use a TSG per channel pool, but instead a TSG per WLC/LCIC + // channel pair, num_tsgs equals to the number of channel pairs. + uvmGpuTsgHandle *tsg_handles; + + // Number TSG handles owned by this pool. + NvU32 num_tsgs; + // Channels in this pool uvm_channel_t *channels; @@ -176,22 +227,26 @@ typedef struct // Lock protecting the state of channels in the pool. // // There are two pool lock types available: spinlock and mutex. The mutex - // variant is required when the thread holding the pool lock must - // sleep (ex: acquire another mutex) deeper in the call stack, either in UVM - // or RM. For example, work submission to proxy channels in SR-IOV heavy - // entails calling an RM API that acquires a mutex, so the proxy channel - // pool must use the mutex variant. - // - // Unless the mutex is required, the spinlock is preferred. This is because, - // other than for proxy channels, work submission takes little time and does - // not involve any RM calls, so UVM can avoid any invocation that may result - // on a sleep. All non-proxy channel pools use the spinlock variant, even in - // SR-IOV heavy. + // variant is required when the thread holding the pool lock must sleep + // (ex: acquire another mutex) deeper in the call stack, either in UVM or + // RM. union { uvm_spinlock_t spinlock; uvm_mutex_t mutex; }; + // Secure operations require that uvm_push_begin order matches + // uvm_push_end order, because the engine's state is used in its internal + // operation and each push may modify this state. push_locks is protected by + // the channel pool lock. + DECLARE_BITMAP(push_locks, UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL); + + // Counting semaphore for available and unlocked channels, it must be + // acquired before submitting work to a secure channel. + uvm_semaphore_t push_sem; + + // See uvm_channel_is_secure() documentation. + bool secure; } uvm_channel_pool_t; struct uvm_channel_struct @@ -242,6 +297,66 @@ struct uvm_channel_struct // uvm_channel_end_push(). uvm_gpu_tracking_semaphore_t tracking_sem; + struct + { + // Secure operations require that uvm_push_begin order matches + // uvm_push_end order, because the engine's state is used in + // its internal operation and each push may modify this state. + uvm_mutex_t push_lock; + + // Every secure channel has cryptographic state in HW, which is + // mirrored here for CPU-side operations. + UvmCslContext ctx; + bool is_ctx_initialized; + + // CPU-side CSL crypto operations which operate on the same CSL state + // are not thread-safe, so they must be wrapped in locks at the UVM + // level. Encryption, decryption and logging operations must be + // protected with the ctx_lock. + uvm_mutex_t ctx_lock; + } csl; + + struct + { + // The value of GPU side PUT index. + // Indirect work submission introduces delay between updating the CPU + // put when ending a push, and updating the GPU visible value via + // indirect work launch. It is used to order multiple pending indirect + // work launches to match the order of push end-s that triggered them. + volatile NvU32 gpu_put; + + // Static pushbuffer for channels with static schedule (WLC/LCIC) + uvm_rm_mem_t *static_pb_protected_vidmem; + + // Static pushbuffer staging buffer for WLC + uvm_rm_mem_t *static_pb_unprotected_sysmem; + void *static_pb_unprotected_sysmem_cpu; + void *static_pb_unprotected_sysmem_auth_tag_cpu; + + // The above static locations are required by the WLC (and LCIC) + // schedule. Protected sysmem location completes WLC's independence + // from the pushbuffer allocator. + void *static_pb_protected_sysmem; + + // Static tracking semaphore notifier values + // Because of LCIC's fixed schedule, the secure semaphore release + // mechanism uses two additional static locations for incrementing the + // notifier values. See: + // . channel_semaphore_secure_release() + // . setup_lcic_schedule() + // . internal_channel_submit_work_wlc() + uvm_rm_mem_t *static_notifier_unprotected_sysmem; + NvU32 *static_notifier_entry_unprotected_sysmem_cpu; + NvU32 *static_notifier_exit_unprotected_sysmem_cpu; + uvm_gpu_address_t static_notifier_entry_unprotected_sysmem_gpu_va; + uvm_gpu_address_t static_notifier_exit_unprotected_sysmem_gpu_va; + + // Explicit location for push launch tag used by WLC. + // Encryption auth tags have to be located in unprotected sysmem. + void *launch_auth_tag_cpu; + NvU64 launch_auth_tag_gpu_va; + } conf_computing; + // RM channel information union { @@ -337,6 +452,73 @@ struct uvm_channel_manager_struct // Create a channel manager for the GPU NV_STATUS uvm_channel_manager_create(uvm_gpu_t *gpu, uvm_channel_manager_t **manager_out); +static bool uvm_channel_pool_is_ce(uvm_channel_pool_t *pool); + +// A channel is secure if it has HW encryption capabilities. +// +// Secure channels are treated differently in the UVM driver. Each secure +// channel has a unique CSL context associated with it, has relatively +// restrictive reservation policies (in comparison with non-secure channels), +// it is requested to be allocated differently by RM, etc. +static bool uvm_channel_pool_is_secure(uvm_channel_pool_t *pool) +{ + return pool->secure; +} + +static bool uvm_channel_is_secure(uvm_channel_t *channel) +{ + return uvm_channel_pool_is_secure(channel->pool); +} + +static bool uvm_channel_pool_is_sec2(uvm_channel_pool_t *pool) +{ + UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); + + return (pool->pool_type == UVM_CHANNEL_POOL_TYPE_SEC2); +} + +static bool uvm_channel_pool_is_secure_ce(uvm_channel_pool_t *pool) +{ + return uvm_channel_pool_is_secure(pool) && uvm_channel_pool_is_ce(pool); +} + +static bool uvm_channel_pool_is_wlc(uvm_channel_pool_t *pool) +{ + UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); + + return (pool->pool_type == UVM_CHANNEL_POOL_TYPE_WLC); +} + +static bool uvm_channel_pool_is_lcic(uvm_channel_pool_t *pool) +{ + UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); + + return (pool->pool_type == UVM_CHANNEL_POOL_TYPE_LCIC); +} + +static bool uvm_channel_is_sec2(uvm_channel_t *channel) +{ + return uvm_channel_pool_is_sec2(channel->pool); +} + +static bool uvm_channel_is_secure_ce(uvm_channel_t *channel) +{ + return uvm_channel_pool_is_secure_ce(channel->pool); +} + +static bool uvm_channel_is_wlc(uvm_channel_t *channel) +{ + return uvm_channel_pool_is_wlc(channel->pool); +} + +static bool uvm_channel_is_lcic(uvm_channel_t *channel) +{ + return uvm_channel_pool_is_lcic(channel->pool); +} + +bool uvm_channel_type_requires_secure_pool(uvm_gpu_t *gpu, uvm_channel_type_t channel_type); +NV_STATUS uvm_channel_secure_init(uvm_gpu_t *gpu, uvm_channel_t *channel); + static bool uvm_channel_pool_is_proxy(uvm_channel_pool_t *pool) { UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); @@ -352,6 +534,8 @@ static bool uvm_channel_is_proxy(uvm_channel_t *channel) static bool uvm_channel_pool_is_ce(uvm_channel_pool_t *pool) { UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); + if (uvm_channel_pool_is_wlc(pool) || uvm_channel_pool_is_lcic(pool)) + return true; return (pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE) || uvm_channel_pool_is_proxy(pool); } @@ -361,6 +545,8 @@ static bool uvm_channel_is_ce(uvm_channel_t *channel) return uvm_channel_pool_is_ce(channel->pool); } +bool uvm_channel_pool_uses_mutex(uvm_channel_pool_t *pool); + // Proxy channels are used to push page tree related methods, so their channel // type is UVM_CHANNEL_TYPE_MEMOPS. static uvm_channel_type_t uvm_channel_proxy_channel_type(void) @@ -415,6 +601,13 @@ NvU32 uvm_channel_manager_update_progress(uvm_channel_manager_t *channel_manager // beginning. NV_STATUS uvm_channel_manager_wait(uvm_channel_manager_t *manager); +// Check if WLC/LCIC mechanism is ready/setup +// Should only return false during initialization +static bool uvm_channel_manager_is_wlc_ready(uvm_channel_manager_t *manager) +{ + return (manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_WLC] != NULL) && + (manager->pool_to_use.default_for_type[UVM_CHANNEL_TYPE_LCIC] != NULL); +} // Get the GPU VA of semaphore_channel's tracking semaphore within the VA space // associated with access_channel. // diff --git a/kernel-open/nvidia-uvm/uvm_channel_test.c b/kernel-open/nvidia-uvm/uvm_channel_test.c index 1b7a81c4bc..24805897e4 100644 --- a/kernel-open/nvidia-uvm/uvm_channel_test.c +++ b/kernel-open/nvidia-uvm/uvm_channel_test.c @@ -60,6 +60,11 @@ static NV_STATUS test_ordering(uvm_va_space_t *va_space) gpu = uvm_va_space_find_first_gpu(va_space); TEST_CHECK_RET(gpu != NULL); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_rm_mem_alloc_and_map_all(gpu, UVM_RM_MEM_TYPE_SYS, buffer_size, 0, &mem); TEST_CHECK_GOTO(status == NV_OK, done); @@ -69,7 +74,7 @@ static NV_STATUS test_ordering(uvm_va_space_t *va_space) status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, &push, "Initial memset"); TEST_CHECK_GOTO(status == NV_OK, done); - gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(push.channel)); + gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(push.channel)).address; // Semaphore release as part of uvm_push_end() will do the membar uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); @@ -104,7 +109,7 @@ static NV_STATUS test_ordering(uvm_va_space_t *va_space) value + 1); TEST_CHECK_GOTO(status == NV_OK, done); - gpu_va_base = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(push.channel)); + gpu_va_base = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(push.channel)).address; gpu_va_src = gpu_va_base + (value % values_count) * sizeof(NvU32); gpu_va_dst = gpu_va_base + ((value + 1) % values_count) * sizeof(NvU32); @@ -200,6 +205,9 @@ static NV_STATUS uvm_test_rc_for_gpu(uvm_gpu_t *gpu) uvm_for_each_pool(pool, manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { NvU32 i; for (i = 0; i < 512; ++i) { @@ -341,8 +349,8 @@ static void snapshot_counter(uvm_push_t *push, return; is_proxy_channel = uvm_channel_is_proxy(push->channel); - counter_gpu_va = uvm_rm_mem_get_gpu_va(counter_mem, gpu, is_proxy_channel); - snapshot_gpu_va = uvm_rm_mem_get_gpu_va(snapshot_mem, gpu, is_proxy_channel) + index * 2 * sizeof(NvU32); + counter_gpu_va = uvm_rm_mem_get_gpu_va(counter_mem, gpu, is_proxy_channel).address; + snapshot_gpu_va = uvm_rm_mem_get_gpu_va(snapshot_mem, gpu, is_proxy_channel).address + index * 2 * sizeof(NvU32); // Copy the last and first counter to a snapshot for later verification. @@ -367,7 +375,7 @@ static void set_counter(uvm_push_t *push, uvm_rm_mem_t *counter_mem, NvU32 value bool is_proxy_channel; is_proxy_channel = uvm_channel_is_proxy(push->channel); - counter_gpu_va = uvm_rm_mem_get_gpu_va(counter_mem, gpu, is_proxy_channel); + counter_gpu_va = uvm_rm_mem_get_gpu_va(counter_mem, gpu, is_proxy_channel).address; gpu->parent->ce_hal->memset_v_4(push, counter_gpu_va, value, count * sizeof(NvU32)); } @@ -427,7 +435,7 @@ static void test_memset_rm_mem(uvm_push_t *push, uvm_rm_mem_t *rm_mem, NvU32 val UVM_ASSERT(rm_mem->size % 4 == 0); gpu = uvm_push_get_gpu(push); - gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, uvm_channel_is_proxy(push->channel)); + gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, uvm_channel_is_proxy(push->channel)).address; gpu->parent->ce_hal->memset_v_4(push, gpu_va, value, rm_mem->size); } @@ -672,6 +680,74 @@ static NV_STATUS stress_test_all_gpus_in_va(uvm_va_space_t *va_space, return status; } +// The following test is inspired by uvm_push_test.c:test_concurrent_pushes. +// This test verifies that concurrent pushes using the same secure channel pool +// select different channels. +NV_STATUS test_secure_channel_selection(uvm_va_space_t *va_space) +{ + NV_STATUS status = NV_OK; + uvm_channel_pool_t *pool; + uvm_push_t *pushes; + uvm_gpu_t *gpu; + NvU32 i; + NvU32 num_pushes; + + gpu = uvm_va_space_find_first_gpu(va_space); + + if (!uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + uvm_thread_context_lock_disable_tracking(); + + for_each_va_space_gpu(gpu, va_space) { + uvm_channel_type_t channel_type; + + for (channel_type = 0; channel_type < UVM_CHANNEL_TYPE_COUNT; channel_type++) { + if (!uvm_channel_type_requires_secure_pool(gpu, channel_type)) + continue; + + pool = gpu->channel_manager->pool_to_use.default_for_type[channel_type]; + TEST_CHECK_RET(pool != NULL); + + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; + + if (pool->num_channels < 2) + continue; + + num_pushes = min(pool->num_channels, (NvU32)UVM_PUSH_MAX_CONCURRENT_PUSHES); + + pushes = uvm_kvmalloc_zero(sizeof(*pushes) * num_pushes); + TEST_CHECK_RET(pushes != NULL); + + for (i = 0; i < num_pushes; i++) { + uvm_push_t *push = &pushes[i]; + status = uvm_push_begin(gpu->channel_manager, channel_type, push, "concurrent push %u", i); + TEST_NV_CHECK_GOTO(status, error); + if (i > 0) + TEST_CHECK_GOTO(pushes[i-1].channel != push->channel, error); + } + for (i = 0; i < num_pushes; i++) { + uvm_push_t *push = &pushes[i]; + status = uvm_push_end_and_wait(push); + TEST_NV_CHECK_GOTO(status, error); + } + + uvm_kvfree(pushes); + } + } + + uvm_thread_context_lock_enable_tracking(); + + return status; +error: + uvm_thread_context_lock_enable_tracking(); + uvm_kvfree(pushes); + + return status; +} + NV_STATUS test_write_ctrl_gpfifo_noop(uvm_va_space_t *va_space) { uvm_gpu_t *gpu; @@ -683,6 +759,14 @@ NV_STATUS test_write_ctrl_gpfifo_noop(uvm_va_space_t *va_space) uvm_for_each_pool(pool, manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; + + // Skip WLC channels as those can't accept ctrl gpfifos + // after their schedule is set up + if (uvm_channel_pool_is_wlc(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { NvU32 i; @@ -714,6 +798,14 @@ NV_STATUS test_write_ctrl_gpfifo_and_pushes(uvm_va_space_t *va_space) uvm_for_each_pool(pool, manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; + + // Skip WLC channels as those can't accept ctrl gpfifos + // after their schedule is set up + if (uvm_channel_pool_is_wlc(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { NvU32 i; uvm_push_t push; @@ -757,6 +849,11 @@ NV_STATUS test_write_ctrl_gpfifo_tight(uvm_va_space_t *va_space) gpu = uvm_va_space_find_first_gpu(va_space); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + for_each_va_space_gpu(gpu, va_space) { uvm_channel_manager_t *manager = gpu->channel_manager; @@ -850,6 +947,9 @@ static NV_STATUS test_channel_pushbuffer_extension_base(uvm_va_space_t *va_space uvm_for_each_pool(pool, manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept any pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { NvU32 i; uvm_push_t push; @@ -897,6 +997,10 @@ NV_STATUS uvm_test_channel_sanity(UVM_TEST_CHANNEL_SANITY_PARAMS *params, struct if (status != NV_OK) goto done; + status = test_secure_channel_selection(va_space); + if (status != NV_OK) + goto done; + // The following tests have side effects, they reset the GPU's // channel_manager. status = test_channel_pushbuffer_extension_base(va_space); @@ -937,12 +1041,18 @@ static NV_STATUS uvm_test_channel_stress_stream(uvm_va_space_t *va_space, uvm_mutex_lock(&g_uvm_global.global_lock); uvm_va_space_down_read_rm(va_space); + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(uvm_va_space_find_first_gpu(va_space))) + goto done; + status = stress_test_all_gpus_in_va(va_space, params->num_streams, params->iterations, params->seed, params->verbose); +done: uvm_va_space_up_read_rm(va_space); uvm_mutex_unlock(&g_uvm_global.global_lock); diff --git a/kernel-open/nvidia-uvm/uvm_common.h b/kernel-open/nvidia-uvm/uvm_common.h index c890ee81cc..7631c2610c 100644 --- a/kernel-open/nvidia-uvm/uvm_common.h +++ b/kernel-open/nvidia-uvm/uvm_common.h @@ -211,6 +211,11 @@ static inline NvBool uvm_uuid_is_cpu(const NvProcessorUuid *uuid) { return memcmp(uuid, &NV_PROCESSOR_UUID_CPU_DEFAULT, sizeof(*uuid)) == 0; } +#define UVM_SIZE_1KB (1024ULL) +#define UVM_SIZE_1MB (1024 * UVM_SIZE_1KB) +#define UVM_SIZE_1GB (1024 * UVM_SIZE_1MB) +#define UVM_SIZE_1TB (1024 * UVM_SIZE_1GB) +#define UVM_SIZE_1PB (1024 * UVM_SIZE_1TB) #define UVM_ALIGN_DOWN(x, a) ({ \ typeof(x) _a = a; \ @@ -352,6 +357,7 @@ typedef enum UVM_FD_UNINITIALIZED, UVM_FD_INITIALIZING, UVM_FD_VA_SPACE, + UVM_FD_MM, UVM_FD_COUNT } uvm_fd_type_t; @@ -388,6 +394,10 @@ bool uvm_file_is_nvidia_uvm(struct file *filp); // NULL returns the value of the pointer. uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val); +// Returns the pointer stored in filp->private_data if the type +// matches, otherwise returns NULL. +void *uvm_fd_get_type(struct file *filp, uvm_fd_type_t type); + // Reads the first word in the supplied struct page. static inline void uvm_touch_page(struct page *page) { @@ -400,4 +410,7 @@ static inline void uvm_touch_page(struct page *page) kunmap(page); } +// Return true if the VMA is one used by UVM managed allocations. +bool uvm_vma_is_managed(struct vm_area_struct *vma); + #endif /* _UVM_COMMON_H */ diff --git a/kernel-open/nvidia-uvm/uvm_conf_computing.c b/kernel-open/nvidia-uvm/uvm_conf_computing.c new file mode 100644 index 0000000000..9dcb8f2c1f --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_conf_computing.c @@ -0,0 +1,446 @@ +/******************************************************************************* + Copyright (c) 2021 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_common.h" +#include "uvm_global.h" +#include "uvm_conf_computing.h" +#include "uvm_kvmalloc.h" +#include "uvm_gpu.h" +#include "uvm_mem.h" +#include "uvm_processors.h" +#include "uvm_tracker.h" +#include "nv_uvm_interface.h" +#include "uvm_va_block.h" + + +static UvmGpuConfComputeMode uvm_conf_computing_get_mode(const uvm_parent_gpu_t *parent) +{ + return parent->rm_info.gpuConfComputeCaps.mode; +} + +bool uvm_conf_computing_mode_enabled_parent(const uvm_parent_gpu_t *parent) +{ + return uvm_conf_computing_get_mode(parent) != UVM_GPU_CONF_COMPUTE_MODE_NONE; +} + +bool uvm_conf_computing_mode_enabled(const uvm_gpu_t *gpu) +{ + return uvm_conf_computing_mode_enabled_parent(gpu->parent); +} + +bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu) +{ + return uvm_conf_computing_get_mode(gpu->parent) == UVM_GPU_CONF_COMPUTE_MODE_HCC; +} + +NV_STATUS uvm_conf_computing_init_parent_gpu(const uvm_parent_gpu_t *parent) +{ + UvmGpuConfComputeMode cc, sys_cc; + uvm_gpu_t *first; + + uvm_assert_mutex_locked(&g_uvm_global.global_lock); + + // TODO: Bug 2844714. + // Since we have no routine to traverse parent gpus, + // find first child GPU and get its parent. + first = uvm_global_processor_mask_find_first_gpu(&g_uvm_global.retained_gpus); + if (!first) + return NV_OK; + + sys_cc = uvm_conf_computing_get_mode(first->parent); + cc = uvm_conf_computing_get_mode(parent); + + return cc == sys_cc ? NV_OK : NV_ERR_NOT_SUPPORTED; +} + +static void dma_buffer_destroy_locked(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t *dma_buffer) +{ + uvm_assert_mutex_locked(&dma_buffer_pool->lock); + + list_del(&dma_buffer->node); + uvm_tracker_wait_deinit(&dma_buffer->tracker); + + uvm_mem_free(dma_buffer->alloc); + uvm_mem_free(dma_buffer->auth_tag); + uvm_kvfree(dma_buffer); +} + +static uvm_gpu_t *dma_buffer_pool_to_gpu(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + return container_of(dma_buffer_pool, uvm_gpu_t, conf_computing.dma_buffer_pool); +} + +// Allocate and map a new DMA stage buffer to CPU and GPU (VA) +static NV_STATUS dma_buffer_create(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t **dma_buffer_out) +{ + uvm_gpu_t *dma_owner; + uvm_conf_computing_dma_buffer_t *dma_buffer; + uvm_mem_t *alloc = NULL; + NV_STATUS status = NV_OK; + size_t auth_tags_size = (UVM_CONF_COMPUTING_DMA_BUFFER_SIZE / PAGE_SIZE) * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + + dma_buffer = uvm_kvmalloc_zero(sizeof(*dma_buffer)); + if (!dma_buffer) + return NV_ERR_NO_MEMORY; + + dma_owner = dma_buffer_pool_to_gpu(dma_buffer_pool); + uvm_tracker_init(&dma_buffer->tracker); + INIT_LIST_HEAD(&dma_buffer->node); + + status = uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(UVM_CONF_COMPUTING_DMA_BUFFER_SIZE, dma_owner, NULL, &alloc); + if (status != NV_OK) + goto err; + + dma_buffer->alloc = alloc; + + status = uvm_mem_map_gpu_kernel(alloc, dma_owner); + if (status != NV_OK) + goto err; + + status = uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(auth_tags_size, dma_owner, NULL, &alloc); + if (status != NV_OK) + goto err; + + dma_buffer->auth_tag = alloc; + + status = uvm_mem_map_gpu_kernel(alloc, dma_owner); + if (status != NV_OK) + goto err; + + *dma_buffer_out = dma_buffer; + + return status; + +err: + dma_buffer_destroy_locked(dma_buffer_pool, dma_buffer); + return status; +} + +void uvm_conf_computing_dma_buffer_pool_sync(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + uvm_conf_computing_dma_buffer_t *dma_buffer; + + if (dma_buffer_pool->num_dma_buffers == 0) + return; + + uvm_mutex_lock(&dma_buffer_pool->lock); + list_for_each_entry(dma_buffer, &dma_buffer_pool->free_dma_buffers, node) + uvm_tracker_wait(&dma_buffer->tracker); + uvm_mutex_unlock(&dma_buffer_pool->lock); +} + +static void conf_computing_dma_buffer_pool_deinit(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + uvm_conf_computing_dma_buffer_t *dma_buffer; + uvm_conf_computing_dma_buffer_t *next_buff; + + if (dma_buffer_pool->num_dma_buffers == 0) + return; + + // Because the pool is teared down at the same time the GPU is unregistered + // the lock is required only to quiet assertions not for functional reasons + // see dma_buffer_destroy_locked()). + uvm_mutex_lock(&dma_buffer_pool->lock); + + list_for_each_entry_safe(dma_buffer, next_buff, &dma_buffer_pool->free_dma_buffers, node) { + dma_buffer_destroy_locked(dma_buffer_pool, dma_buffer); + dma_buffer_pool->num_dma_buffers--; + } + + UVM_ASSERT(dma_buffer_pool->num_dma_buffers == 0); + UVM_ASSERT(list_empty(&dma_buffer_pool->free_dma_buffers)); + uvm_mutex_unlock(&dma_buffer_pool->lock); +} + +static void dma_buffer_pool_add(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t *dma_buffer) +{ + uvm_assert_mutex_locked(&dma_buffer_pool->lock); + list_add_tail(&dma_buffer->node, &dma_buffer_pool->free_dma_buffers); +} + +static NV_STATUS conf_computing_dma_buffer_pool_init(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + size_t i; + uvm_gpu_t *gpu; + size_t num_dma_buffers = 32; + NV_STATUS status = NV_OK; + + UVM_ASSERT(dma_buffer_pool->num_dma_buffers == 0); + + gpu = dma_buffer_pool_to_gpu(dma_buffer_pool); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + INIT_LIST_HEAD(&dma_buffer_pool->free_dma_buffers); + uvm_mutex_init(&dma_buffer_pool->lock, UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL); + dma_buffer_pool->num_dma_buffers = num_dma_buffers; + + uvm_mutex_lock(&dma_buffer_pool->lock); + for (i = 0; i < num_dma_buffers; i++) { + uvm_conf_computing_dma_buffer_t *dma_buffer; + + status = dma_buffer_create(dma_buffer_pool, &dma_buffer); + if (status != NV_OK) + break; + + dma_buffer_pool_add(dma_buffer_pool, dma_buffer); + } + uvm_mutex_unlock(&dma_buffer_pool->lock); + + if (i < num_dma_buffers) + conf_computing_dma_buffer_pool_deinit(dma_buffer_pool); + + return status; +} + +static NV_STATUS dma_buffer_pool_expand_locked(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) +{ + size_t i; + uvm_gpu_t *gpu; + size_t nb_to_alloc; + NV_STATUS status = NV_OK; + UVM_ASSERT(dma_buffer_pool->num_dma_buffers > 0); + + gpu = dma_buffer_pool_to_gpu(dma_buffer_pool); + nb_to_alloc = dma_buffer_pool->num_dma_buffers; + for (i = 0; i < nb_to_alloc; ++i) { + uvm_conf_computing_dma_buffer_t *dma_buffer; + + status = dma_buffer_create(dma_buffer_pool, &dma_buffer); + if (status != NV_OK) + break; + + dma_buffer_pool_add(dma_buffer_pool, dma_buffer); + } + + dma_buffer_pool->num_dma_buffers += i; + + if (i == 0) + return status; + + return NV_OK; +} + +NV_STATUS uvm_conf_computing_dma_buffer_alloc(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t **dma_buffer_out, + uvm_tracker_t *out_tracker) +{ + uvm_conf_computing_dma_buffer_t *dma_buffer = NULL; + NV_STATUS status; + + UVM_ASSERT(dma_buffer_pool->num_dma_buffers > 0); + + // TODO: Bug 3385623: Heuristically expand DMA memory pool + uvm_mutex_lock(&dma_buffer_pool->lock); + if (list_empty(&dma_buffer_pool->free_dma_buffers)) { + status = dma_buffer_pool_expand_locked(dma_buffer_pool); + + if (status != NV_OK) { + uvm_mutex_unlock(&dma_buffer_pool->lock); + return status; + } + } + + // We're guaranteed that at least one DMA stage buffer is available at this + // point. + dma_buffer = list_first_entry(&dma_buffer_pool->free_dma_buffers, uvm_conf_computing_dma_buffer_t, node); + list_del_init(&dma_buffer->node); + uvm_mutex_unlock(&dma_buffer_pool->lock); + + status = uvm_tracker_wait_for_other_gpus(&dma_buffer->tracker, dma_buffer->alloc->dma_owner); + if (status != NV_OK) + goto error; + + if (out_tracker) + status = uvm_tracker_add_tracker_safe(out_tracker, &dma_buffer->tracker); + else + status = uvm_tracker_wait(&dma_buffer->tracker); + + if (status != NV_OK) + goto error; + + uvm_page_mask_zero(&dma_buffer->encrypted_page_mask); + *dma_buffer_out = dma_buffer; + + return status; + +error: + uvm_tracker_deinit(&dma_buffer->tracker); + uvm_conf_computing_dma_buffer_free(dma_buffer_pool, dma_buffer, NULL); + return status; +} + +void uvm_conf_computing_dma_buffer_free(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t *dma_buffer, + uvm_tracker_t *tracker) +{ + + NV_STATUS status; + + if (!dma_buffer) + return; + + UVM_ASSERT(dma_buffer_pool->num_dma_buffers > 0); + + uvm_tracker_remove_completed(&dma_buffer->tracker); + if (tracker) { + uvm_tracker_remove_completed(tracker); + status = uvm_tracker_add_tracker_safe(&dma_buffer->tracker, tracker); + if (status != NV_OK) + UVM_ASSERT(status == uvm_global_get_status()); + } + + uvm_mutex_lock(&dma_buffer_pool->lock); + dma_buffer_pool_add(dma_buffer_pool, dma_buffer); + uvm_mutex_unlock(&dma_buffer_pool->lock); +} + +static void dummy_iv_mem_deinit(uvm_gpu_t *gpu) +{ + uvm_mem_free(gpu->conf_computing.iv_mem); +} + +static NV_STATUS dummy_iv_mem_init(uvm_gpu_t *gpu) +{ + NV_STATUS status; + + if (!uvm_conf_computing_mode_is_hcc(gpu)) + return NV_OK; + + status = uvm_mem_alloc_sysmem_dma(sizeof(UvmCslIv), gpu, NULL, &gpu->conf_computing.iv_mem); + if (status != NV_OK) + return status; + + status = uvm_mem_map_gpu_kernel(gpu->conf_computing.iv_mem, gpu); + if (status != NV_OK) + goto error; + + return NV_OK; + +error: + dummy_iv_mem_deinit(gpu); + return status; +} + +NV_STATUS uvm_conf_computing_gpu_init(uvm_gpu_t *gpu) +{ + NV_STATUS status; + + if (!uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + status = conf_computing_dma_buffer_pool_init(&gpu->conf_computing.dma_buffer_pool); + if (status != NV_OK) + return status; + + status = dummy_iv_mem_init(gpu); + if (status != NV_OK) + goto error; + + return NV_OK; + +error: + uvm_conf_computing_gpu_deinit(gpu); + return status; +} + +void uvm_conf_computing_gpu_deinit(uvm_gpu_t *gpu) +{ + dummy_iv_mem_deinit(gpu); + conf_computing_dma_buffer_pool_deinit(&gpu->conf_computing.dma_buffer_pool); +} + +void uvm_conf_computing_log_gpu_encryption(uvm_channel_t *channel, UvmCslIv *iv) +{ + NV_STATUS status; + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslLogDeviceEncryption(&channel->csl.ctx, iv); + uvm_mutex_unlock(&channel->csl.ctx_lock); + + // nvUvmInterfaceLogDeviceEncryption fails when a 64-bit encryption counter + // overflows. This is not supposed to happen on CC. + UVM_ASSERT(status == NV_OK); +} + +void uvm_conf_computing_acquire_encryption_iv(uvm_channel_t *channel, UvmCslIv *iv) +{ + NV_STATUS status; + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslAcquireEncryptionIv(&channel->csl.ctx, iv); + uvm_mutex_unlock(&channel->csl.ctx_lock); + + // nvUvmInterfaceLogDeviceEncryption fails when a 64-bit encryption counter + // overflows. This is not supposed to happen on CC. + UVM_ASSERT(status == NV_OK); +} + +void uvm_conf_computing_cpu_encrypt(uvm_channel_t *channel, + void *dst_cipher, + const void *src_plain, + UvmCslIv *encrypt_iv, + size_t size, + void *auth_tag_buffer) +{ + NV_STATUS status; + + UVM_ASSERT(size); + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslEncrypt(&channel->csl.ctx, + size, + (NvU8 const *) src_plain, + encrypt_iv, + (NvU8 *) dst_cipher, + (NvU8 *) auth_tag_buffer); + uvm_mutex_unlock(&channel->csl.ctx_lock); + + // nvUvmInterfaceCslEncrypt fails when a 64-bit encryption counter + // overflows. This is not supposed to happen on CC. + UVM_ASSERT(status == NV_OK); +} + +NV_STATUS uvm_conf_computing_cpu_decrypt(uvm_channel_t *channel, + void *dst_plain, + const void *src_cipher, + const UvmCslIv *src_iv, + size_t size, + const void *auth_tag_buffer) +{ + NV_STATUS status; + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslDecrypt(&channel->csl.ctx, + size, + (const NvU8 *) src_cipher, + src_iv, + (NvU8 *) dst_plain, + (const NvU8 *) auth_tag_buffer); + uvm_mutex_unlock(&channel->csl.ctx_lock); + + return status; +} diff --git a/kernel-open/nvidia-uvm/uvm_conf_computing.h b/kernel-open/nvidia-uvm/uvm_conf_computing.h new file mode 100644 index 0000000000..1e916c4736 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_conf_computing.h @@ -0,0 +1,178 @@ +/******************************************************************************* + Copyright (c) 2021-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef __UVM_CONF_COMPUTING_H__ +#define __UVM_CONF_COMPUTING_H__ + +#include "nv_uvm_types.h" +#include "uvm_forward_decl.h" +#include "uvm_lock.h" +#include "uvm_tracker.h" +#include "uvm_va_block_types.h" + +#include "linux/list.h" + +#define UVM_CONF_COMPUTING_AUTH_TAG_SIZE (UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES) + +// An authentication tag pointer is required by HW to be 16-bytes aligned. +#define UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT 16 + +// An IV pointer is required by HW to be 16-bytes aligned. +// +// Use sizeof(UvmCslIv) to refer to the IV size. +#define UVM_CONF_COMPUTING_IV_ALIGNMENT 16 + +// SEC2 decrypt operation buffers are required to be 16-bytes aligned. CE +// encrypt/decrypt can be unaligned if the buffer lies in a single 32B segment. +// Otherwise, they need to be 32B aligned. +#define UVM_CONF_COMPUTING_BUF_ALIGNMENT 32 + +#define UVM_CONF_COMPUTING_DMA_BUFFER_SIZE UVM_VA_BLOCK_SIZE + +// SEC2 supports at most a stream of 64 entries in the method stream for +// signing. Each entry is made of the method address and method data, therefore +// the maximum buffer size is: UVM_METHOD_SIZE * 2 * 64 = 512. +// UVM, however, won't use this amount of entries, in the worst case scenario, +// we push a semaphore_releases or a decrypt. A SEC2 semaphore_release uses 6 1U +// entries, whereas a SEC2 decrypt uses 10 1U entries. For 10 entries, +// UVM_METHOD_SIZE * 2 * 10 = 80. +#define UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE 80 + +// All GPUs derive confidential computing status from their parent. +// By current policy all parent GPUs have identical confidential +// computing status. +NV_STATUS uvm_conf_computing_init_parent_gpu(const uvm_parent_gpu_t *parent); +bool uvm_conf_computing_mode_enabled_parent(const uvm_parent_gpu_t *parent); +bool uvm_conf_computing_mode_enabled(const uvm_gpu_t *gpu); +bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu); + +typedef struct +{ + // List of free DMA buffers (uvm_conf_computing_dma_buffer_t). + // A free DMA buffer can be grabbed anytime, though the tracker + // inside it may still have pending work. + struct list_head free_dma_buffers; + + // Used to grow the pool when full. + size_t num_dma_buffers; + + // Lock protecting the dma_buffer_pool + uvm_mutex_t lock; +} uvm_conf_computing_dma_buffer_pool_t; + +typedef struct +{ + // Backing DMA allocation + uvm_mem_t *alloc; + + // Used internally by the pool management code to track the state of + // a free buffer. + uvm_tracker_t tracker; + + // When the DMA buffer is used as the destination of a GPU encryption, SEC2 + // writes the authentication tag here. Later when the buffer is decrypted + // on the CPU the authentication tag is used again (read) for CSL to verify + // the authenticity. The allocation is big enough for one authentication + // tag per PAGE_SIZE page in the alloc buffer. + uvm_mem_t *auth_tag; + + // CSL supports out-of-order decryption, the decrypt IV is used similarly + // to the authentication tag. The allocation is big enough for one IV per + // PAGE_SIZE page in the alloc buffer. The granularity between the decrypt + // IV and authentication tag must match. + UvmCslIv decrypt_iv[(UVM_CONF_COMPUTING_DMA_BUFFER_SIZE / PAGE_SIZE)]; + + // Bitmap of the encrypted pages in the backing allocation + uvm_page_mask_t encrypted_page_mask; + + // See uvm_conf_computing_dma_pool lists + struct list_head node; +} uvm_conf_computing_dma_buffer_t; + +// Retrieve a DMA buffer from the given DMA allocation pool. +// NV_OK Stage buffer successfully retrieved +// NV_ERR_NO_MEMORY No free DMA buffers are available for grab, and +// expanding the memory pool to get new ones failed. +// +// out_dma_buffer is only valid if NV_OK is returned. The caller is responsible +// for calling uvm_conf_computing_dma_buffer_free once the operations on this +// buffer are done. +// When out_tracker is passed to the function, the buffer's dependencies are +// added to the tracker. The caller is guaranteed that all pending tracker +// entries come from the same GPU as the pool's owner. Before being able to use +// the DMA buffer, the caller is responsible for either acquiring or waiting +// on out_tracker. If out_tracker is NULL, the wait happens in the allocation +// itself. +// Upon success the encrypted_page_mask is cleared as part of the allocation. +NV_STATUS uvm_conf_computing_dma_buffer_alloc(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t **out_dma_buffer, + uvm_tracker_t *out_tracker); + +// Free a DMA buffer to the DMA allocation pool. All DMA buffers must be freed +// prior to GPU deinit. +// +// The tracker is optional and a NULL tracker indicates that no new operation +// has been pushed for the buffer. A non-NULL tracker indicates any additional +// pending operations on the buffer pushed by the caller that need to be +// synchronized before freeing or re-using the buffer. +void uvm_conf_computing_dma_buffer_free(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, + uvm_conf_computing_dma_buffer_t *dma_buffer, + uvm_tracker_t *tracker); + +// Synchronize trackers in all entries in the GPU's DMA pool +void uvm_conf_computing_dma_buffer_pool_sync(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool); + + +// Initialization and deinitialization of Confidential Computing data structures +// for the given GPU. +NV_STATUS uvm_conf_computing_gpu_init(uvm_gpu_t *gpu); +void uvm_conf_computing_gpu_deinit(uvm_gpu_t *gpu); + +// Logs encryption information from the GPU and returns the IV. +void uvm_conf_computing_log_gpu_encryption(uvm_channel_t *channel, UvmCslIv *iv); + +// Acquires next CPU encryption IV and returns it. +void uvm_conf_computing_acquire_encryption_iv(uvm_channel_t *channel, UvmCslIv *iv); + +// CPU side encryption helper with explicit IV, which is obtained from +// uvm_conf_computing_acquire_encryption_iv. Without an explicit IV +// the function uses the next IV in order. Encrypts data in src_plain and +// write the cipher text in dst_cipher. src_plain and dst_cipher can't overlap. +// The IV is invalidated and can't be used again after this operation. +void uvm_conf_computing_cpu_encrypt(uvm_channel_t *channel, + void *dst_cipher, + const void *src_plain, + UvmCslIv *encrypt_iv, + size_t size, + void *auth_tag_buffer); + +// CPU side decryption helper. Decrypts data from src_cipher and writes the +// plain text in dst_plain. src_cipher and dst_plain can't overlap. IV obtained +// from uvm_conf_computing_log_gpu_encryption() needs to be be passed to src_iv. +NV_STATUS uvm_conf_computing_cpu_decrypt(uvm_channel_t *channel, + void *dst_plain, + const void *src_cipher, + const UvmCslIv *src_iv, + size_t size, + const void *auth_tag_buffer); +#endif // __UVM_CONF_COMPUTING_H__ diff --git a/kernel-open/nvidia-uvm/uvm_forward_decl.h b/kernel-open/nvidia-uvm/uvm_forward_decl.h index bb5fb72915..a69234223b 100644 --- a/kernel-open/nvidia-uvm/uvm_forward_decl.h +++ b/kernel-open/nvidia-uvm/uvm_forward_decl.h @@ -37,6 +37,7 @@ typedef struct uvm_ce_hal_struct uvm_ce_hal_t; typedef struct uvm_arch_hal_struct uvm_arch_hal_t; typedef struct uvm_fault_buffer_hal_struct uvm_fault_buffer_hal_t; typedef struct uvm_access_counter_buffer_hal_struct uvm_access_counter_buffer_hal_t; +typedef struct uvm_sec2_hal_struct uvm_sec2_hal_t; typedef struct uvm_gpu_semaphore_struct uvm_gpu_semaphore_t; typedef struct uvm_gpu_tracking_semaphore_struct uvm_gpu_tracking_semaphore_t; typedef struct uvm_gpu_semaphore_pool_struct uvm_gpu_semaphore_pool_t; diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c index 3f233fac2d..d04ecf8dbc 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_gpu.c @@ -41,6 +41,7 @@ #include "uvm_gpu_access_counters.h" #include "uvm_ats.h" #include "uvm_test.h" +#include "uvm_conf_computing.h" #include "uvm_linux.h" @@ -66,21 +67,6 @@ static uvm_user_channel_t *get_user_channel(uvm_rb_tree_node_t *node) return container_of(node, uvm_user_channel_t, instance_ptr.node); } -static void fill_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo *gpu_info) -{ - char uuid_buffer[UVM_GPU_UUID_TEXT_BUFFER_LENGTH]; - - parent_gpu->rm_info = *gpu_info; - - format_uuid_to_buffer(uuid_buffer, sizeof(uuid_buffer), &parent_gpu->uuid); - snprintf(parent_gpu->name, - sizeof(parent_gpu->name), - "ID %u: %s: %s", - uvm_id_value(parent_gpu->id), - parent_gpu->rm_info.name, - uuid_buffer); -} - static uvm_gpu_link_type_t get_gpu_link_type(UVM_LINK_TYPE link_type) { switch (link_type) { @@ -94,44 +80,68 @@ static uvm_gpu_link_type_t get_gpu_link_type(UVM_LINK_TYPE link_type) return UVM_GPU_LINK_NVLINK_3; case UVM_LINK_TYPE_NVLINK_4: return UVM_GPU_LINK_NVLINK_4; + case UVM_LINK_TYPE_C2C: + return UVM_GPU_LINK_C2C; default: return UVM_GPU_LINK_INVALID; } } -static NV_STATUS get_gpu_caps(uvm_parent_gpu_t *parent_gpu) +static void fill_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo *gpu_info) { - NV_STATUS status; - UvmGpuCaps gpu_caps; + char uuid_buffer[UVM_GPU_UUID_TEXT_BUFFER_LENGTH]; - memset(&gpu_caps, 0, sizeof(gpu_caps)); + parent_gpu->rm_info = *gpu_info; - status = uvm_rm_locked_call(nvUvmInterfaceQueryCaps(parent_gpu->rm_device, &gpu_caps)); - if (status != NV_OK) - return status; + parent_gpu->system_bus.link = get_gpu_link_type(gpu_info->sysmemLink); + UVM_ASSERT(parent_gpu->system_bus.link != UVM_GPU_LINK_INVALID); + + parent_gpu->system_bus.link_rate_mbyte_per_s = gpu_info->sysmemLinkRateMBps; - parent_gpu->sysmem_link = get_gpu_link_type(gpu_caps.sysmemLink); - UVM_ASSERT(parent_gpu->sysmem_link != UVM_GPU_LINK_INVALID); + if (gpu_info->systemMemoryWindowSize > 0) { + // memory_window_end is inclusive but uvm_gpu_is_coherent() checks + // memory_window_end > memory_window_start as its condition. + UVM_ASSERT(gpu_info->systemMemoryWindowSize > 1); + parent_gpu->system_bus.memory_window_start = gpu_info->systemMemoryWindowStart; + parent_gpu->system_bus.memory_window_end = gpu_info->systemMemoryWindowStart + + gpu_info->systemMemoryWindowSize - 1; + } - parent_gpu->sysmem_link_rate_mbyte_per_s = gpu_caps.sysmemLinkRateMBps; - parent_gpu->nvswitch_info.is_nvswitch_connected = gpu_caps.connectedToSwitch; + parent_gpu->nvswitch_info.is_nvswitch_connected = gpu_info->connectedToSwitch; // nvswitch is routed via physical pages, where the upper 13-bits of the // 47-bit address space holds the routing information for each peer. // Currently, this is limited to a 16GB framebuffer window size. if (parent_gpu->nvswitch_info.is_nvswitch_connected) - parent_gpu->nvswitch_info.fabric_memory_window_start = gpu_caps.nvswitchMemoryWindowStart; + parent_gpu->nvswitch_info.fabric_memory_window_start = gpu_info->nvswitchMemoryWindowStart; + + format_uuid_to_buffer(uuid_buffer, sizeof(uuid_buffer), &parent_gpu->uuid); + snprintf(parent_gpu->name, + sizeof(parent_gpu->name), + "ID %u: %s: %s", + uvm_id_value(parent_gpu->id), + parent_gpu->rm_info.name, + uuid_buffer); +} + +static NV_STATUS get_gpu_caps(uvm_gpu_t *gpu) +{ + NV_STATUS status; + UvmGpuCaps gpu_caps; + + memset(&gpu_caps, 0, sizeof(gpu_caps)); + + status = uvm_rm_locked_call(nvUvmInterfaceQueryCaps(uvm_gpu_device_handle(gpu), &gpu_caps)); + if (status != NV_OK) + return status; if (gpu_caps.numaEnabled) { - parent_gpu->numa_info.enabled = true; - parent_gpu->numa_info.node_id = gpu_caps.numaNodeId; - parent_gpu->numa_info.system_memory_window_start = gpu_caps.systemMemoryWindowStart; - parent_gpu->numa_info.system_memory_window_end = gpu_caps.systemMemoryWindowStart + - gpu_caps.systemMemoryWindowSize - - 1; + UVM_ASSERT(uvm_gpu_is_coherent(gpu->parent)); + gpu->mem_info.numa.enabled = true; + gpu->mem_info.numa.node_id = gpu_caps.numaNodeId; } else { - UVM_ASSERT(!g_uvm_global.ats.enabled); + UVM_ASSERT(!uvm_gpu_is_coherent(gpu->parent)); } return NV_OK; @@ -347,26 +357,30 @@ NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr) static void gpu_info_print_ce_caps(uvm_gpu_t *gpu, struct seq_file *s) { NvU32 i; - UvmGpuCopyEnginesCaps ces_caps; + UvmGpuCopyEnginesCaps *ces_caps; NV_STATUS status; - memset(&ces_caps, 0, sizeof(ces_caps)); - status = uvm_rm_locked_call(nvUvmInterfaceQueryCopyEnginesCaps(uvm_gpu_device_handle(gpu), &ces_caps)); + ces_caps = uvm_kvmalloc_zero(sizeof(*ces_caps)); + if (!ces_caps) { + UVM_SEQ_OR_DBG_PRINT(s, "supported_ces: unavailable (no memory)\n"); + return; + } + status = uvm_rm_locked_call(nvUvmInterfaceQueryCopyEnginesCaps(uvm_gpu_device_handle(gpu), ces_caps)); if (status != NV_OK) { UVM_SEQ_OR_DBG_PRINT(s, "supported_ces: unavailable (query failed)\n"); - return; + goto out; } UVM_SEQ_OR_DBG_PRINT(s, "supported_ces:\n"); for (i = 0; i < UVM_COPY_ENGINE_COUNT_MAX; ++i) { - UvmGpuCopyEngineCaps *ce_caps = ces_caps.copyEngineCaps + i; + UvmGpuCopyEngineCaps *ce_caps = ces_caps->copyEngineCaps + i; if (!ce_caps->supported) continue; - UVM_SEQ_OR_DBG_PRINT(s, " ce %u pce mask 0x%08x grce %u shared %u sysmem read %u sysmem write %u sysmem %u nvlink p2p %u " - "p2p %u\n", + UVM_SEQ_OR_DBG_PRINT(s, " ce %u pce mask 0x%08x grce %u shared %u sysmem read %u sysmem write %u sysmem %u " + "nvlink p2p %u p2p %u\n", i, ce_caps->cePceMask, ce_caps->grce, @@ -377,6 +391,9 @@ static void gpu_info_print_ce_caps(uvm_gpu_t *gpu, struct seq_file *s) ce_caps->nvlinkP2p, ce_caps->p2p); } + +out: + uvm_kvfree(ces_caps); } static const char *uvm_gpu_virt_type_string(UVM_VIRT_MODE virtMode) @@ -394,7 +411,7 @@ static const char *uvm_gpu_virt_type_string(UVM_VIRT_MODE virtMode) static const char *uvm_gpu_link_type_string(uvm_gpu_link_type_t link_type) { - BUILD_BUG_ON(UVM_GPU_LINK_MAX != 6); + BUILD_BUG_ON(UVM_GPU_LINK_MAX != 7); switch (link_type) { UVM_ENUM_STRING_CASE(UVM_GPU_LINK_INVALID); @@ -403,6 +420,7 @@ static const char *uvm_gpu_link_type_string(uvm_gpu_link_type_t link_type) UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_2); UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_3); UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_4); + UVM_ENUM_STRING_CASE(UVM_GPU_LINK_C2C); UVM_ENUM_STRING_DEFAULT(); } } @@ -410,7 +428,6 @@ static const char *uvm_gpu_link_type_string(uvm_gpu_link_type_t link_type) static void gpu_info_print_common(uvm_gpu_t *gpu, struct seq_file *s) { const UvmGpuInfo *gpu_info = &gpu->parent->rm_info; - uvm_numa_info_t *numa_info = &gpu->parent->numa_info; NvU64 num_pages_in; NvU64 num_pages_out; NvU64 mapped_cpu_pages_size; @@ -429,9 +446,9 @@ static void gpu_info_print_common(uvm_gpu_t *gpu, struct seq_file *s) return; UVM_SEQ_OR_DBG_PRINT(s, "CPU link type %s\n", - uvm_gpu_link_type_string(gpu->parent->sysmem_link)); + uvm_gpu_link_type_string(gpu->parent->system_bus.link)); UVM_SEQ_OR_DBG_PRINT(s, "CPU link bandwidth %uMBps\n", - gpu->parent->sysmem_link_rate_mbyte_per_s); + gpu->parent->system_bus.link_rate_mbyte_per_s); UVM_SEQ_OR_DBG_PRINT(s, "architecture 0x%X\n", gpu_info->gpuArch); UVM_SEQ_OR_DBG_PRINT(s, "implementation 0x%X\n", gpu_info->gpuImplementation); @@ -453,13 +470,13 @@ static void gpu_info_print_common(uvm_gpu_t *gpu, struct seq_file *s) gpu->mem_info.max_allocatable_address, gpu->mem_info.max_allocatable_address / (1024 * 1024)); - if (numa_info->enabled) { - NvU64 window_size = numa_info->system_memory_window_end - numa_info->system_memory_window_start + 1; - UVM_SEQ_OR_DBG_PRINT(s, "numa_node_id %u\n", numa_info->node_id); - UVM_SEQ_OR_DBG_PRINT(s, "system_memory_window_start 0x%llx\n", - numa_info->system_memory_window_start); - UVM_SEQ_OR_DBG_PRINT(s, "system_memory_window_end 0x%llx\n", - numa_info->system_memory_window_end); + if (gpu->mem_info.numa.enabled) { + NvU64 window_size = gpu->parent->system_bus.memory_window_end - gpu->parent->system_bus.memory_window_start + 1; + UVM_SEQ_OR_DBG_PRINT(s, "numa_node_id %u\n", uvm_gpu_numa_node(gpu)); + UVM_SEQ_OR_DBG_PRINT(s, "memory_window_start 0x%llx\n", + gpu->parent->system_bus.memory_window_start); + UVM_SEQ_OR_DBG_PRINT(s, "memory_window_end 0x%llx\n", + gpu->parent->system_bus.memory_window_end); UVM_SEQ_OR_DBG_PRINT(s, "system_memory_window_size 0x%llx (%llu MBs)\n", window_size, window_size / (1024 * 1024)); @@ -550,6 +567,10 @@ static void gpu_info_print_common(uvm_gpu_t *gpu, struct seq_file *s) gpu_info_print_ce_caps(gpu, s); + if (uvm_conf_computing_mode_enabled(gpu)) { + UVM_SEQ_OR_DBG_PRINT(s, "dma_buffer_pool_num_buffers %lu\n", + gpu->conf_computing.dma_buffer_pool.num_dma_buffers); + } } static void @@ -843,7 +864,7 @@ static void deinit_procfs_peer_cap_files(uvm_gpu_peer_t *peer_caps) proc_remove(peer_caps->procfs.peer_file[1]); } -static NV_STATUS init_semaphore_pool(uvm_gpu_t *gpu) +static NV_STATUS init_semaphore_pools(uvm_gpu_t *gpu) { NV_STATUS status; uvm_gpu_t *other_gpu; @@ -852,7 +873,17 @@ static NV_STATUS init_semaphore_pool(uvm_gpu_t *gpu) if (status != NV_OK) return status; + // When the Confidential Computing feature is enabled, a separate secure + // pool is created that holds page allocated in the CPR of vidmem. + if (uvm_conf_computing_mode_enabled(gpu)) { + status = uvm_gpu_semaphore_secure_pool_create(gpu, &gpu->secure_semaphore_pool); + if (status != NV_OK) + return status; + } + for_each_global_gpu(other_gpu) { + if (uvm_conf_computing_mode_enabled(gpu)) + break; if (other_gpu == gpu) continue; status = uvm_gpu_semaphore_pool_map_gpu(other_gpu->semaphore_pool, gpu); @@ -863,7 +894,7 @@ static NV_STATUS init_semaphore_pool(uvm_gpu_t *gpu) return NV_OK; } -static void deinit_semaphore_pool(uvm_gpu_t *gpu) +static void deinit_semaphore_pools(uvm_gpu_t *gpu) { uvm_gpu_t *other_gpu; @@ -874,6 +905,7 @@ static void deinit_semaphore_pool(uvm_gpu_t *gpu) } uvm_gpu_semaphore_pool_destroy(gpu->semaphore_pool); + uvm_gpu_semaphore_pool_destroy(gpu->secure_semaphore_pool); } static NV_STATUS find_unused_global_gpu_id(uvm_parent_gpu_t *parent_gpu, uvm_global_gpu_id_t *out_id) @@ -1067,6 +1099,13 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, return status; } + status = uvm_conf_computing_init_parent_gpu(parent_gpu); + if (status != NV_OK) { + UVM_ERR_PRINT("Confidential computing: %s, GPU %s\n", + nvstatusToString(status), parent_gpu->name); + return status; + } + parent_gpu->pci_dev = gpu_platform_info->pci_dev; parent_gpu->closest_cpu_numa_node = dev_to_node(&parent_gpu->pci_dev->dev); parent_gpu->dma_addressable_start = gpu_platform_info->dma_addressable_start; @@ -1102,12 +1141,6 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, uvm_mmu_init_gpu_chunk_sizes(parent_gpu); - status = get_gpu_caps(parent_gpu); - if (status != NV_OK) { - UVM_ERR_PRINT("Failed to get GPU caps: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); - return status; - } - status = uvm_ats_add_gpu(parent_gpu); if (status != NV_OK) { UVM_ERR_PRINT("uvm_ats_add_gpu failed: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); @@ -1166,6 +1199,12 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info) return status; } + status = get_gpu_caps(gpu); + if (status != NV_OK) { + UVM_ERR_PRINT("Failed to get GPU caps: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); + return status; + } + uvm_mmu_init_gpu_peer_addresses(gpu); status = alloc_and_init_address_space(gpu); @@ -1198,7 +1237,7 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info) return status; } - status = init_semaphore_pool(gpu); + status = init_semaphore_pools(gpu); if (status != NV_OK) { UVM_ERR_PRINT("Failed to initialize the semaphore pool: %s, GPU %s\n", nvstatusToString(status), @@ -1228,6 +1267,14 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info) return status; } + status = uvm_conf_computing_gpu_init(gpu); + if (status != NV_OK) { + UVM_ERR_PRINT("Failed to initialize Confidential Compute: %s for GPU %s\n", + nvstatusToString(status), + uvm_gpu_name(gpu)); + return status; + } + status = init_procfs_files(gpu); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init procfs files: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); @@ -1403,6 +1450,8 @@ static void remove_gpus_from_gpu(uvm_gpu_t *gpu) // Sync all trackers in PMM uvm_pmm_gpu_sync(&gpu->pmm); + // Sync all trackers in the GPU's DMA allocation pool + uvm_conf_computing_dma_buffer_pool_sync(&gpu->conf_computing.dma_buffer_pool); } // Remove all references to the given GPU from its parent, since it is being @@ -1485,7 +1534,7 @@ static void deinit_gpu(uvm_gpu_t *gpu) // pain during development. deconfigure_address_space(gpu); - deinit_semaphore_pool(gpu); + deinit_semaphore_pools(gpu); uvm_pmm_sysmem_mappings_deinit(&gpu->pmm_reverse_sysmem_mappings); @@ -1536,6 +1585,13 @@ static void remove_gpu(uvm_gpu_t *gpu) if (free_parent) destroy_nvlink_peers(gpu); + // uvm_mem_free and other uvm_mem APIs invoked by the Confidential Compute + // deinitialization must be called before the GPU is removed from the global + // table. + // + // TODO: Bug 2008200: Add and remove the GPU in a more reasonable spot. + uvm_conf_computing_gpu_deinit(gpu); + // TODO: Bug 2844714: If the parent is not being freed, the following // gpu_table_lock is only needed to protect concurrent // find_first_valid_gpu() in BH from the __clear_bit here. After @@ -2213,9 +2269,12 @@ static NV_STATUS init_peer_access(uvm_gpu_t *gpu0, { NV_STATUS status; + UVM_ASSERT(p2p_caps_params->p2pLink != UVM_LINK_TYPE_C2C); + // check for peer-to-peer compatibility (PCI-E or NvLink). peer_caps->link_type = get_gpu_link_type(p2p_caps_params->p2pLink); if (peer_caps->link_type == UVM_GPU_LINK_INVALID + || peer_caps->link_type == UVM_GPU_LINK_C2C ) return NV_ERR_NOT_SUPPORTED; @@ -2225,8 +2284,8 @@ static NV_STATUS init_peer_access(uvm_gpu_t *gpu0, peer_caps->is_indirect_peer = (p2p_caps_params->indirectAccess == NV_TRUE); if (peer_caps->is_indirect_peer) { - UVM_ASSERT(gpu0->parent->numa_info.enabled); - UVM_ASSERT(gpu1->parent->numa_info.enabled); + UVM_ASSERT(gpu0->mem_info.numa.enabled); + UVM_ASSERT(gpu1->mem_info.numa.enabled); status = uvm_pmm_gpu_indirect_peer_init(&gpu0->pmm, gpu1); if (status != NV_OK) @@ -2415,8 +2474,7 @@ static NV_STATUS discover_nvlink_peers(uvm_gpu_t *gpu) // Indirect peers are only supported when onlined as NUMA nodes, because // we want to use vm_insert_page and dma_map_page. - if (p2p_caps_params.indirectAccess && - (!gpu->parent->numa_info.enabled || !other_gpu->parent->numa_info.enabled)) + if (p2p_caps_params.indirectAccess && (!gpu->mem_info.numa.enabled || !other_gpu->mem_info.numa.enabled)) continue; status = enable_nvlink_peer_access(gpu, other_gpu, &p2p_caps_params); @@ -2601,6 +2659,9 @@ uvm_aperture_t uvm_gpu_page_tree_init_location(const uvm_gpu_t *gpu) if (uvm_gpu_is_virt_mode_sriov_heavy(gpu)) return UVM_APERTURE_VID; + if (uvm_conf_computing_mode_enabled(gpu)) + return UVM_APERTURE_VID; + return UVM_APERTURE_DEFAULT; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu.h b/kernel-open/nvidia-uvm/uvm_gpu.h index ca68a256c4..a596abc663 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_gpu.h @@ -46,6 +46,7 @@ #include "uvm_rb_tree.h" #include "uvm_perf_prefetch.h" #include "nv-kthread-q.h" +#include "uvm_conf_computing.h" // Buffer length to store uvm gpu id, RM device name and gpu uuid. #define UVM_GPU_NICE_NAME_BUFFER_LENGTH (sizeof("ID 999: : ") + \ @@ -133,6 +134,12 @@ struct uvm_service_block_context_struct // This is set if the page migrated to/from the GPU and CPU. bool did_migrate; + + // Sequence number used to start a mmu notifier read side critical + // section. + unsigned long notifier_seq; + + struct vm_fault *vmf; } cpu_fault; // @@ -168,6 +175,31 @@ struct uvm_service_block_context_struct uvm_perf_prefetch_bitmap_tree_t prefetch_bitmap_tree; }; +typedef struct +{ + // Mask of read faulted pages in a UVM_VA_BLOCK_SIZE aligned region of a SAM + // VMA. Used for batching ATS faults in a vma. + uvm_page_mask_t read_fault_mask; + + // Mask of write faulted pages in a UVM_VA_BLOCK_SIZE aligned region of a + // SAM VMA. Used for batching ATS faults in a vma. + uvm_page_mask_t write_fault_mask; + + // Mask of successfully serviced pages in a UVM_VA_BLOCK_SIZE aligned region + // of a SAM VMA. Used to return ATS fault status. + uvm_page_mask_t faults_serviced_mask; + + // Mask of successfully serviced read faults on pages in write_fault_mask. + uvm_page_mask_t reads_serviced_mask; + + // Temporary mask used for uvm_page_mask_or_equal. This is used since + // bitmap_or_equal() isn't present in all linux kernel versions. + uvm_page_mask_t tmp_mask; + + // Client type of the service requestor. + uvm_fault_client_type_t client_type; +} uvm_ats_fault_context_t; + struct uvm_fault_service_batch_context_struct { // Array of elements fetched from the GPU fault buffer. The number of @@ -200,6 +232,8 @@ struct uvm_fault_service_batch_context_struct NvU32 num_replays; + uvm_ats_fault_context_t ats_context; + // Unique id (per-GPU) generated for tools events recording NvU32 batch_id; @@ -338,6 +372,9 @@ typedef struct // Unique id (per-GPU) generated for tools events recording NvU32 batch_id; + // Information required to service ATS faults. + uvm_ats_fault_context_t ats_context; + // Information required to invalidate stale ATS PTEs from the GPU TLBs uvm_ats_fault_invalidate_t ats_invalidate; } non_replayable; @@ -349,22 +386,6 @@ typedef struct NvU64 disable_prefetch_faults_timestamp; } uvm_fault_buffer_info_t; -typedef struct -{ - // True if the platform supports HW coherence (P9) and RM has exposed the - // GPU's memory as a NUMA node to the kernel. - bool enabled; - - // Range in the system physical address space where the memory of this GPU - // is mapped - NvU64 system_memory_window_start; - NvU64 system_memory_window_end; - - NvU64 memblock_size; - - unsigned node_id; -} uvm_numa_info_t; - struct uvm_access_counter_service_batch_context_struct { uvm_access_counter_buffer_entry_t *notification_cache; @@ -502,6 +523,10 @@ typedef struct // Page tables with the mapping. uvm_page_table_range_vec_t *range_vec; + + // Used during init to indicate whether the mapping has been fully + // initialized. + bool ready; } uvm_gpu_identity_mapping_t; // Root chunk mapping @@ -524,6 +549,7 @@ typedef enum UVM_GPU_LINK_NVLINK_2, UVM_GPU_LINK_NVLINK_3, UVM_GPU_LINK_NVLINK_4, + UVM_GPU_LINK_C2C, UVM_GPU_LINK_MAX } uvm_gpu_link_type_t; @@ -581,6 +607,14 @@ struct uvm_gpu_struct // Max (inclusive) physical address of this GPU's memory that the driver // can allocate through PMM (PMA). NvU64 max_allocatable_address; + + struct + { + // True if the platform supports HW coherence and the GPU's memory + // is exposed as a NUMA node to the kernel. + bool enabled; + unsigned int node_id; + } numa; } mem_info; struct @@ -637,6 +671,8 @@ struct uvm_gpu_struct uvm_gpu_semaphore_pool_t *semaphore_pool; + uvm_gpu_semaphore_pool_t *secure_semaphore_pool; + uvm_channel_manager_t *channel_manager; uvm_pmm_gpu_t pmm; @@ -696,6 +732,25 @@ struct uvm_gpu_struct // mappings (instead of kernel), and it is used in most configurations. uvm_pmm_sysmem_mappings_t pmm_reverse_sysmem_mappings; + struct + { + uvm_conf_computing_dma_buffer_pool_t dma_buffer_pool; + + // Dummy memory used to store the IV contents during CE encryption. + // This memory location is also only available after CE channels + // because we use them to write PTEs for allocations such as this one. + // This location is used when a physical addressing for the IV buffer + // is required. See uvm_hal_hopper_ce_encrypt(). + uvm_mem_t *iv_mem; + + // Dummy memory used to store the IV contents during CE encryption. + // Because of the limitations of `iv_mem', and the need to have such + // buffer at channel initialization, we use an RM allocation. + // This location is used when a virtual addressing for the IV buffer + // is required. See uvm_hal_hopper_ce_encrypt(). + uvm_rm_mem_t *iv_rm_mem; + } conf_computing; + // ECC handling // In order to trap ECC errors as soon as possible the driver has the hw // interrupt register mapped directly. If an ECC interrupt is ever noticed @@ -833,6 +888,10 @@ struct uvm_parent_gpu_struct uvm_arch_hal_t *arch_hal; uvm_fault_buffer_hal_t *fault_buffer_hal; uvm_access_counter_buffer_hal_t *access_counter_buffer_hal; + uvm_sec2_hal_t *sec2_hal; + + // Whether CE supports physical addressing mode for writes to vidmem + bool ce_phys_vidmem_write_supported; uvm_gpu_peer_copy_mode_t peer_copy_mode; @@ -954,9 +1013,6 @@ struct uvm_parent_gpu_struct // Fault buffer info. This is only valid if supports_replayable_faults is set to true uvm_fault_buffer_info_t fault_buffer_info; - // NUMA info, mainly for ATS - uvm_numa_info_t numa_info; - // PMM lazy free processing queue. // TODO: Bug 3881835: revisit whether to use nv_kthread_q_t or workqueue. nv_kthread_q_t lazy_free_q; @@ -1049,8 +1105,22 @@ struct uvm_parent_gpu_struct NvU64 fabric_memory_window_start; } nvswitch_info; - uvm_gpu_link_type_t sysmem_link; - NvU32 sysmem_link_rate_mbyte_per_s; + struct + { + // Note that this represents the link to system memory, not the link the + // system used to discover the GPU. There are some cases such as NVLINK2 + // where the GPU is still on the PCIe bus, but it accesses memory over + // this link rather than PCIe. + uvm_gpu_link_type_t link; + NvU32 link_rate_mbyte_per_s; + + // Range in the system physical address space where the memory of this + // GPU is exposed as coherent. memory_window_end is inclusive. + // memory_window_start == memory_window_end indicates that no window is + // present (coherence is not supported). + NvU64 memory_window_start; + NvU64 memory_window_end; + } system_bus; }; static const char *uvm_gpu_name(uvm_gpu_t *gpu) @@ -1146,23 +1216,20 @@ NV_STATUS uvm_gpu_init_va_space(uvm_va_space_t *va_space); void uvm_gpu_exit_va_space(uvm_va_space_t *va_space); -static uvm_numa_info_t *uvm_gpu_numa_info(uvm_gpu_t *gpu) +static unsigned int uvm_gpu_numa_node(uvm_gpu_t *gpu) { - UVM_ASSERT(gpu->parent->numa_info.enabled); - - return &gpu->parent->numa_info; + UVM_ASSERT(gpu->mem_info.numa.enabled); + return gpu->mem_info.numa.node_id; } static uvm_gpu_phys_address_t uvm_gpu_page_to_phys_address(uvm_gpu_t *gpu, struct page *page) { - uvm_numa_info_t *numa_info = uvm_gpu_numa_info(gpu); - unsigned long sys_addr = page_to_pfn(page) << PAGE_SHIFT; - unsigned long gpu_offset = sys_addr - numa_info->system_memory_window_start; + unsigned long gpu_offset = sys_addr - gpu->parent->system_bus.memory_window_start; - UVM_ASSERT(page_to_nid(page) == numa_info->node_id); - UVM_ASSERT(sys_addr >= numa_info->system_memory_window_start); - UVM_ASSERT(sys_addr + PAGE_SIZE - 1 <= numa_info->system_memory_window_end); + UVM_ASSERT(page_to_nid(page) == uvm_gpu_numa_node(gpu)); + UVM_ASSERT(sys_addr >= gpu->parent->system_bus.memory_window_start); + UVM_ASSERT(sys_addr + PAGE_SIZE - 1 <= gpu->parent->system_bus.memory_window_end); return uvm_gpu_phys_address(UVM_APERTURE_VID, gpu_offset); } @@ -1270,8 +1337,8 @@ static bool uvm_gpus_are_indirect_peers(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1) uvm_gpu_peer_t *peer_caps = uvm_gpu_peer_caps(gpu0, gpu1); if (peer_caps->link_type != UVM_GPU_LINK_INVALID && peer_caps->is_indirect_peer) { - UVM_ASSERT(gpu0->parent->numa_info.enabled); - UVM_ASSERT(gpu1->parent->numa_info.enabled); + UVM_ASSERT(gpu0->mem_info.numa.enabled); + UVM_ASSERT(gpu1->mem_info.numa.enabled); UVM_ASSERT(peer_caps->link_type != UVM_GPU_LINK_PCIE); UVM_ASSERT(!uvm_gpus_are_nvswitch_connected(gpu0, gpu1)); return true; @@ -1291,6 +1358,9 @@ static uvm_gpu_address_t uvm_gpu_address_virtual_from_vidmem_phys(uvm_gpu_t *gpu UVM_ASSERT(uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)); UVM_ASSERT(pa <= gpu->mem_info.max_allocatable_address); + if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu)) + UVM_ASSERT(gpu->static_flat_mapping.ready); + return uvm_gpu_address_virtual(gpu->parent->flat_vidmem_va_base + pa); } @@ -1308,6 +1378,23 @@ static uvm_gpu_address_t uvm_gpu_address_virtual_from_sysmem_phys(uvm_gpu_t *gpu return uvm_gpu_address_virtual(gpu->parent->flat_sysmem_va_base + pa); } +// Given a GPU or CPU physical address (not peer), retrieve an address suitable +// for CE access. +static uvm_gpu_address_t uvm_gpu_address_copy(uvm_gpu_t *gpu, uvm_gpu_phys_address_t phys_addr) +{ + UVM_ASSERT(phys_addr.aperture == UVM_APERTURE_VID || phys_addr.aperture == UVM_APERTURE_SYS); + + if (phys_addr.aperture == UVM_APERTURE_VID) { + if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) + return uvm_gpu_address_virtual_from_vidmem_phys(gpu, phys_addr.address); + } + else if (uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) { + return uvm_gpu_address_virtual_from_sysmem_phys(gpu, phys_addr.address); + } + + return uvm_gpu_address_from_phys(phys_addr); +} + static uvm_gpu_identity_mapping_t *uvm_gpu_get_peer_mapping(uvm_gpu_t *gpu, uvm_gpu_id_t peer_id) { return &gpu->peer_mappings[uvm_id_gpu_index(peer_id)]; @@ -1383,6 +1470,11 @@ bool uvm_gpu_can_address_kernel(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); // addresses. NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr); +static bool uvm_gpu_is_coherent(const uvm_parent_gpu_t *parent_gpu) +{ + return parent_gpu->system_bus.memory_window_end > parent_gpu->system_bus.memory_window_start; +} + static bool uvm_gpu_has_pushbuffer_segments(uvm_gpu_t *gpu) { return gpu->parent->max_host_va > (1ull << 40); @@ -1446,6 +1538,7 @@ typedef enum { UVM_GPU_BUFFER_FLUSH_MODE_CACHED_PUT, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, + UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, } uvm_gpu_buffer_flush_mode_t; #endif // __UVM_GPU_H__ diff --git a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c index e09fcb9759..05262e7a2b 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c @@ -210,13 +210,13 @@ static NV_STATUS config_granularity_to_bytes(UVM_ACCESS_COUNTER_GRANULARITY gran *bytes = 64 * 1024ULL; break; case UVM_ACCESS_COUNTER_GRANULARITY_2M: - *bytes = 2 * 1024 * 1024ULL; + *bytes = 2 * UVM_SIZE_1MB; break; case UVM_ACCESS_COUNTER_GRANULARITY_16M: - *bytes = 16 * 1024 * 1024ULL; + *bytes = 16 * UVM_SIZE_1MB; break; case UVM_ACCESS_COUNTER_GRANULARITY_16G: - *bytes = 16 * 1024 * 1024 * 1024ULL; + *bytes = 16 * UVM_SIZE_1GB; break; default: return NV_ERR_INVALID_ARGUMENT; @@ -404,7 +404,8 @@ NV_STATUS uvm_gpu_init_access_counters(uvm_parent_gpu_t *parent_gpu) UVM_ASSERT(parent_gpu->access_counter_buffer_hal != NULL); status = uvm_rm_locked_call(nvUvmInterfaceInitAccessCntrInfo(parent_gpu->rm_device, - &access_counters->rm_info)); + &access_counters->rm_info, + 0)); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init notify buffer info from RM: %s, GPU %s\n", nvstatusToString(status), @@ -707,6 +708,7 @@ static void access_counter_buffer_flush_locked(uvm_gpu_t *gpu, uvm_gpu_buffer_fl UVM_ASSERT(gpu->parent->access_counters_supported); // Read PUT pointer from the GPU if requested + UVM_ASSERT(flush_mode != UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT); if (flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT) access_counters->cached_put = UVM_GPU_READ_ONCE(*access_counters->rm_info.pAccessCntrBufferPut); @@ -1198,6 +1200,11 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, service_context->num_retries = 0; service_context->block_context.mm = mm; + if (uvm_va_block_is_hmm(va_block)) { + uvm_hmm_service_context_init(service_context); + uvm_hmm_migrate_begin_wait(va_block); + } + uvm_mutex_lock(&va_block->lock); reverse_mappings_to_va_block_page_mask(va_block, reverse_mappings, num_reverse_mappings, accessed_pages); @@ -1211,6 +1218,9 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, uvm_mutex_unlock(&va_block->lock); + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_finish(va_block); + if (status == NV_OK) *out_flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu_isr.c b/kernel-open/nvidia-uvm/uvm_gpu_isr.c index 2a5cdac822..1b3770ada0 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_isr.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_isr.c @@ -85,76 +85,86 @@ static void uvm_gpu_replayable_faults_intr_enable(uvm_parent_gpu_t *parent_gpu); static unsigned schedule_replayable_faults_handler(uvm_parent_gpu_t *parent_gpu) { + uvm_assert_spinlock_locked(&parent_gpu->isr.interrupts_lock); + + if (parent_gpu->isr.is_suspended) + return 0; + // handling gets set to false for all handlers during removal, so quit if // the GPU is in the process of being removed. - if (parent_gpu->isr.replayable_faults.handling) { + if (!parent_gpu->isr.replayable_faults.handling) + return 0; - // Use raw call instead of UVM helper. Ownership will be recorded in the - // bottom half. See comment replayable_faults_isr_bottom_half(). - if (down_trylock(&parent_gpu->isr.replayable_faults.service_lock.sem) == 0) { - if (uvm_gpu_replayable_faults_pending(parent_gpu)) { - nv_kref_get(&parent_gpu->gpu_kref); - - // Interrupts need to be disabled here to avoid an interrupt - // storm - uvm_gpu_replayable_faults_intr_disable(parent_gpu); - - // Schedule a bottom half, but do *not* release the GPU ISR - // lock. The bottom half releases the GPU ISR lock as part of - // its cleanup. - nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, - &parent_gpu->isr.replayable_faults.bottom_half_q_item); - return 1; - } - else { - up(&parent_gpu->isr.replayable_faults.service_lock.sem); - } - } + // Use raw call instead of UVM helper. Ownership will be recorded in the + // bottom half. See comment replayable_faults_isr_bottom_half(). + if (down_trylock(&parent_gpu->isr.replayable_faults.service_lock.sem) != 0) + return 0; + + if (!uvm_gpu_replayable_faults_pending(parent_gpu)) { + up(&parent_gpu->isr.replayable_faults.service_lock.sem); + return 0; } - return 0; + nv_kref_get(&parent_gpu->gpu_kref); + + // Interrupts need to be disabled here to avoid an interrupt storm + uvm_gpu_replayable_faults_intr_disable(parent_gpu); + + // Schedule a bottom half, but do *not* release the GPU ISR lock. The bottom + // half releases the GPU ISR lock as part of its cleanup. + nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, + &parent_gpu->isr.replayable_faults.bottom_half_q_item); + + return 1; } static unsigned schedule_non_replayable_faults_handler(uvm_parent_gpu_t *parent_gpu) { + bool scheduled; + + if (parent_gpu->isr.is_suspended) + return 0; + // handling gets set to false for all handlers during removal, so quit if // the GPU is in the process of being removed. - if (parent_gpu->isr.non_replayable_faults.handling) { - // Non-replayable_faults are stored in a synchronized circular queue - // shared by RM/UVM. Therefore, we can query the number of pending - // faults. This type of faults are not replayed and since RM advances - // GET to PUT when copying the fault packets to the queue, no further - // interrupts will be triggered by the gpu and faults may stay - // unserviced. Therefore, if there is a fault in the queue, we schedule - // a bottom half unconditionally. - if (uvm_gpu_non_replayable_faults_pending(parent_gpu)) { - bool scheduled; - nv_kref_get(&parent_gpu->gpu_kref); - - scheduled = nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, - &parent_gpu->isr.non_replayable_faults.bottom_half_q_item) != 0; - - // If the q_item did not get scheduled because it was already - // queued, that instance will handle the pending faults. Just - // drop the GPU kref. - if (!scheduled) - uvm_parent_gpu_kref_put(parent_gpu); - - return 1; - } - } + if (!parent_gpu->isr.non_replayable_faults.handling) + return 0; - return 0; + // Non-replayable_faults are stored in a synchronized circular queue + // shared by RM/UVM. Therefore, we can query the number of pending + // faults. This type of faults are not replayed and since RM advances + // GET to PUT when copying the fault packets to the queue, no further + // interrupts will be triggered by the gpu and faults may stay + // unserviced. Therefore, if there is a fault in the queue, we schedule + // a bottom half unconditionally. + if (!uvm_gpu_non_replayable_faults_pending(parent_gpu)) + return 0; + + nv_kref_get(&parent_gpu->gpu_kref); + + scheduled = nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, + &parent_gpu->isr.non_replayable_faults.bottom_half_q_item) != 0; + + // If the q_item did not get scheduled because it was already + // queued, that instance will handle the pending faults. Just + // drop the GPU kref. + if (!scheduled) + uvm_parent_gpu_kref_put(parent_gpu); + + return 1; } static unsigned schedule_access_counters_handler(uvm_parent_gpu_t *parent_gpu) { uvm_assert_spinlock_locked(&parent_gpu->isr.interrupts_lock); + if (parent_gpu->isr.is_suspended) + return 0; + if (!parent_gpu->isr.access_counters.handling_ref_count) return 0; - if (down_trylock(&parent_gpu->isr.access_counters.service_lock.sem)) + if (down_trylock(&parent_gpu->isr.access_counters.service_lock.sem) != 0) return 0; if (!uvm_gpu_access_counters_pending(parent_gpu)) { @@ -199,7 +209,7 @@ static NV_STATUS uvm_isr_top_half(const NvProcessorUuid *gpu_uuid) { uvm_parent_gpu_t *parent_gpu; unsigned num_handlers_scheduled = 0; - NV_STATUS status; + NV_STATUS status = NV_OK; if (!in_interrupt() && in_atomic()) { // Early-out if we're not in interrupt context, but memory allocations @@ -238,18 +248,15 @@ static NV_STATUS uvm_isr_top_half(const NvProcessorUuid *gpu_uuid) ++parent_gpu->isr.interrupt_count; - if (parent_gpu->isr.is_suspended) { - status = NV_ERR_NO_INTR_PENDING; - } - else { - num_handlers_scheduled += schedule_replayable_faults_handler(parent_gpu); - num_handlers_scheduled += schedule_non_replayable_faults_handler(parent_gpu); - num_handlers_scheduled += schedule_access_counters_handler(parent_gpu); + num_handlers_scheduled += schedule_replayable_faults_handler(parent_gpu); + num_handlers_scheduled += schedule_non_replayable_faults_handler(parent_gpu); + num_handlers_scheduled += schedule_access_counters_handler(parent_gpu); - if (num_handlers_scheduled == 0) - status = NV_WARN_MORE_PROCESSING_REQUIRED; + if (num_handlers_scheduled == 0) { + if (parent_gpu->isr.is_suspended) + status = NV_ERR_NO_INTR_PENDING; else - status = NV_OK; + status = NV_WARN_MORE_PROCESSING_REQUIRED; } uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); @@ -511,6 +518,9 @@ static void replayable_faults_isr_bottom_half(void *args) uvm_gpu_replayable_faults_isr_unlock(parent_gpu); put_kref: + // It is OK to drop a reference on the parent GPU if a bottom half has + // been retriggered within uvm_gpu_replayable_faults_isr_unlock, because the + // rescheduling added an additional reference. uvm_parent_gpu_kref_put(parent_gpu); } @@ -591,6 +601,51 @@ static void access_counters_isr_bottom_half_entry(void *args) UVM_ENTRY_VOID(access_counters_isr_bottom_half(args)); } +static void replayable_faults_retrigger_bottom_half(uvm_parent_gpu_t *parent_gpu) +{ + bool retrigger = false; + + // When Confidential Computing is enabled, UVM does not (indirectly) trigger + // the replayable fault interrupt by updating GET. This is because, in this + // configuration, GET is a dummy register used to inform GSP-RM (the owner + // of the HW replayable fault buffer) of the latest entry consumed by the + // UVM driver. The real GET register is owned by GSP-RM. + // + // The retriggering of a replayable faults bottom half happens then + // manually, by scheduling a bottom half for later if there is any pending + // work in the fault buffer accessible by UVM. The retriggering adddresses + // two problematic scenarios caused by GET updates not setting any + // interrupt: + // + // (1) UVM didn't process all the entries up to cached PUT + // + // (2) UVM did process all the entries up to cached PUT, but GPS-RM + // added new entries such that cached PUT is out-of-date + // + // In both cases, re-enablement of interrupts would have caused the + // replayable fault to be triggered in a non-CC setup, because the updated + // value of GET is different from PUT. But this not the case in Confidential + // Computing, so a bottom half needs to be manually scheduled in order to + // ensure that all faults are serviced. + // + // While in the typical case the retriggering happens within a replayable + // fault bottom half, it can also happen within a non-interrupt path such as + // uvm_gpu_fault_buffer_flush. + if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + retrigger = true; + + if (!retrigger) + return; + + uvm_spin_lock_irqsave(&parent_gpu->isr.interrupts_lock); + + // If there is pending work, schedule a replayable faults bottom + // half. It is valid for a bottom half (q_item) to reschedule itself. + (void) schedule_replayable_faults_handler(parent_gpu); + + uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); +} + void uvm_gpu_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) { UVM_ASSERT(nv_kref_read(&parent_gpu->gpu_kref) > 0); @@ -632,9 +687,9 @@ void uvm_gpu_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu) // service_lock mutex is released. if (parent_gpu->isr.replayable_faults.handling) { - // Turn page fault interrupts back on, unless remove_gpu() has already removed this GPU - // from the GPU table. remove_gpu() indicates that situation by setting - // gpu->replayable_faults.handling to false. + // Turn page fault interrupts back on, unless remove_gpu() has already + // removed this GPU from the GPU table. remove_gpu() indicates that + // situation by setting gpu->replayable_faults.handling to false. // // This path can only be taken from the bottom half. User threads // calling this function must have previously retained the GPU, so they @@ -671,6 +726,8 @@ void uvm_gpu_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu) uvm_up_out_of_order(&parent_gpu->isr.replayable_faults.service_lock); uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); + + replayable_faults_retrigger_bottom_half(parent_gpu); } void uvm_gpu_non_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) diff --git a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c index 2373511a8c..6c33d670db 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c @@ -435,6 +435,11 @@ static NV_STATUS service_managed_fault_in_block(uvm_gpu_t *gpu, service_context->operation = UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS; service_context->num_retries = 0; + if (uvm_va_block_is_hmm(va_block)) { + uvm_hmm_service_context_init(service_context); + uvm_hmm_migrate_begin_wait(va_block); + } + uvm_mutex_lock(&va_block->lock); status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, &va_block_retry, @@ -449,6 +454,9 @@ static NV_STATUS service_managed_fault_in_block(uvm_gpu_t *gpu, uvm_mutex_unlock(&va_block->lock); + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_finish(va_block); + return status == NV_OK? tracker_status: status; } @@ -512,6 +520,14 @@ static void schedule_kill_channel(uvm_gpu_t *gpu, &user_channel->kill_channel.kill_channel_q_item); } +static void service_fault_fatal(uvm_fault_buffer_entry_t *fault_entry, NV_STATUS status) +{ + UVM_ASSERT(fault_entry->fault_access_type != UVM_FAULT_ACCESS_TYPE_PREFETCH); + + fault_entry->is_fatal = true; + fault_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); +} + static NV_STATUS service_non_managed_fault(uvm_gpu_va_space_t *gpu_va_space, struct mm_struct *mm, uvm_fault_buffer_entry_t *fault_entry, @@ -521,6 +537,7 @@ static NV_STATUS service_non_managed_fault(uvm_gpu_va_space_t *gpu_va_space, uvm_non_replayable_fault_buffer_info_t *non_replayable_faults = &gpu->parent->fault_buffer_info.non_replayable; uvm_ats_fault_invalidate_t *ats_invalidate = &non_replayable_faults->ats_invalidate; NV_STATUS status = lookup_status; + NV_STATUS fatal_fault_status = NV_ERR_INVALID_ADDRESS; UVM_ASSERT(!fault_entry->is_fatal); @@ -537,27 +554,63 @@ static NV_STATUS service_non_managed_fault(uvm_gpu_va_space_t *gpu_va_space, return status; if (uvm_ats_can_service_faults(gpu_va_space, mm)) { + struct vm_area_struct *vma; + uvm_va_range_t *va_range_next; + NvU64 fault_address = fault_entry->fault_address; + uvm_fault_access_type_t fault_access_type = fault_entry->fault_access_type; + uvm_ats_fault_context_t *ats_context = &non_replayable_faults->ats_context; + + uvm_page_mask_zero(&ats_context->read_fault_mask); + uvm_page_mask_zero(&ats_context->write_fault_mask); + + ats_context->client_type = UVM_FAULT_CLIENT_TYPE_HUB; + ats_invalidate->write_faults_in_batch = false; + va_range_next = uvm_va_space_iter_first(gpu_va_space->va_space, fault_entry->fault_address, ~0ULL); + // The VA isn't managed. See if ATS knows about it. - status = uvm_ats_service_fault_entry(gpu_va_space, fault_entry, ats_invalidate); + vma = find_vma_intersection(mm, fault_address, fault_address + 1); + if (!vma || uvm_ats_check_in_gmmu_region(gpu_va_space->va_space, fault_address, va_range_next)) { - // Invalidate ATS TLB entries if needed - if (status == NV_OK) { - status = uvm_ats_invalidate_tlbs(gpu_va_space, - ats_invalidate, - &non_replayable_faults->fault_service_tracker); + // Do not return error due to logical errors in the application + status = NV_OK; + } + else { + NvU64 base = UVM_VA_BLOCK_ALIGN_DOWN(fault_address); + uvm_page_mask_t *faults_serviced_mask = &ats_context->faults_serviced_mask; + uvm_page_index_t page_index = (fault_address - base) / PAGE_SIZE; + uvm_page_mask_t *fault_mask = (fault_access_type >= UVM_FAULT_ACCESS_TYPE_WRITE) ? + &ats_context->write_fault_mask : + &ats_context->read_fault_mask; + + uvm_page_mask_set(fault_mask, page_index); + + status = uvm_ats_service_faults(gpu_va_space, vma, base, ats_context); + if (status == NV_OK) { + // Invalidate ATS TLB entries if needed + if (uvm_page_mask_test(faults_serviced_mask, page_index)) { + status = uvm_ats_invalidate_tlbs(gpu_va_space, + ats_invalidate, + &non_replayable_faults->fault_service_tracker); + fatal_fault_status = NV_OK; + } + } + else { + fatal_fault_status = status; + } } } else { - UVM_ASSERT(fault_entry->fault_access_type != UVM_FAULT_ACCESS_TYPE_PREFETCH); - fault_entry->is_fatal = true; - fault_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); + fatal_fault_status = status; // Do not return error due to logical errors in the application status = NV_OK; } + if (fatal_fault_status != NV_OK) + service_fault_fatal(fault_entry, fatal_fault_status); + return status; } @@ -670,6 +723,8 @@ void uvm_gpu_service_non_replayable_fault_buffer(uvm_gpu_t *gpu) // Differently to replayable faults, we do not batch up and preprocess // non-replayable faults since getting multiple faults on the same // memory region is not very likely + // + // TODO: Bug 2103669: [UVM/ATS] Optimize ATS fault servicing for (i = 0; i < cached_faults; ++i) { status = service_fault(gpu, &gpu->parent->fault_buffer_info.non_replayable.fault_cache[i]); if (status != NV_OK) diff --git a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c index 8160fa7915..62b17ee3ac 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c @@ -23,6 +23,7 @@ #include "linux/sort.h" #include "nv_uvm_interface.h" +#include "uvm_common.h" #include "uvm_linux.h" #include "uvm_global.h" #include "uvm_gpu_replayable_faults.h" @@ -296,6 +297,19 @@ void uvm_gpu_fault_buffer_deinit(uvm_parent_gpu_t *parent_gpu) } } +// TODO: Bug 4098289: this function can be removed, and the calls to it replaced +// with calls to uvm_conf_computing_mode_enabled_parent, once UVM ownership is +// dictated by Confidential Computing enablement. Currently we support a +// non-production scenario in which Confidential Computing is enabled, but +// UVM still owns the replayable fault buffer. +bool uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(uvm_parent_gpu_t *parent_gpu) +{ + if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + return parent_gpu->fault_buffer_info.rm_info.replayable.bUvmOwnsHwFaultBuffer; + + return true; +} + bool uvm_gpu_replayable_faults_pending(uvm_parent_gpu_t *parent_gpu) { uvm_replayable_fault_buffer_info_t *replayable_faults = &parent_gpu->fault_buffer_info.replayable; @@ -529,6 +543,35 @@ static void write_get(uvm_parent_gpu_t *parent_gpu, NvU32 get) parent_gpu->fault_buffer_hal->write_get(parent_gpu, get); } +static NV_STATUS hw_fault_buffer_flush_locked(uvm_parent_gpu_t *parent_gpu) +{ + NV_STATUS status = NV_OK; + + // When Confidential Computing is enabled, GSP-RM owns the HW replayable + // fault buffer. Flushing the fault buffer implies flushing both the HW + // buffer (using a RM API), and the SW buffer accessible by UVM ("shadow" + // buffer). + // + // The HW buffer needs to be flushed first. This is because, once that + // flush completes, any faults that were present in the HW buffer when + // fault_buffer_flush_locked is called, are now either flushed from the HW + // buffer, or are present in the shadow buffer and are about to be discarded + // too. + if (!uvm_conf_computing_mode_enabled_parent(parent_gpu)) + return NV_OK; + + // nvUvmInterfaceFlushReplayableFaultBuffer relies on the caller to ensure + // serialization for a given GPU. + UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); + + // Flush the HW replayable buffer owned by GSP-RM. + status = nvUvmInterfaceFlushReplayableFaultBuffer(parent_gpu->rm_device); + + UVM_ASSERT(status == NV_OK); + + return status; +} + static NV_STATUS fault_buffer_flush_locked(uvm_gpu_t *gpu, uvm_gpu_buffer_flush_mode_t flush_mode, uvm_fault_replay_type_t fault_replay, @@ -537,23 +580,37 @@ static NV_STATUS fault_buffer_flush_locked(uvm_gpu_t *gpu, NvU32 get; NvU32 put; uvm_spin_loop_t spin; - uvm_replayable_fault_buffer_info_t *replayable_faults = &gpu->parent->fault_buffer_info.replayable; + uvm_parent_gpu_t *parent_gpu = gpu->parent; + uvm_replayable_fault_buffer_info_t *replayable_faults = &parent_gpu->fault_buffer_info.replayable; + NV_STATUS status; - UVM_ASSERT(uvm_sem_is_locked(&gpu->parent->isr.replayable_faults.service_lock)); - UVM_ASSERT(gpu->parent->replayable_faults_supported); + UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); + UVM_ASSERT(parent_gpu->replayable_faults_supported); + + // Wait for the prior replay to flush out old fault messages + if (flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT) { + status = uvm_tracker_wait(&replayable_faults->replay_tracker); + if (status != NV_OK) + return status; + } // Read PUT pointer from the GPU if requested - if (flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT) - replayable_faults->cached_put = gpu->parent->fault_buffer_hal->read_put(gpu->parent); + if (flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT || flush_mode == UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT) { + status = hw_fault_buffer_flush_locked(parent_gpu); + if (status != NV_OK) + return status; + + replayable_faults->cached_put = parent_gpu->fault_buffer_hal->read_put(parent_gpu); + } get = replayable_faults->cached_get; put = replayable_faults->cached_put; while (get != put) { // Wait until valid bit is set - UVM_SPIN_WHILE(!gpu->parent->fault_buffer_hal->entry_is_valid(gpu->parent, get), &spin); + UVM_SPIN_WHILE(!parent_gpu->fault_buffer_hal->entry_is_valid(parent_gpu, get), &spin); - gpu->parent->fault_buffer_hal->entry_clear_valid(gpu->parent, get); + parent_gpu->fault_buffer_hal->entry_clear_valid(parent_gpu, get); ++get; if (get == replayable_faults->max_faults) get = 0; @@ -575,7 +632,7 @@ NV_STATUS uvm_gpu_fault_buffer_flush(uvm_gpu_t *gpu) uvm_gpu_replayable_faults_isr_lock(gpu->parent); status = fault_buffer_flush_locked(gpu, - UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, + UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START, NULL); @@ -956,6 +1013,10 @@ static NV_STATUS translate_instance_ptrs(uvm_gpu_t *gpu, // If the channel is gone then we're looking at a stale fault entry. // The fault must have been resolved already (serviced or // cancelled), so we can just flush the fault buffer. + // + // No need to use UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT since + // there was a context preemption for the entries we want to flush, + // meaning PUT must reflect them. status = fault_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START, @@ -1047,46 +1108,80 @@ static bool check_fault_entry_duplicate(const uvm_fault_buffer_entry_t *current_ return is_duplicate; } -static void fault_entry_duplicate_flags(uvm_fault_buffer_entry_t *current_entry, - const uvm_fault_buffer_entry_t *previous_entry) +static void update_batch_and_notify_fault(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + uvm_va_block_t *va_block, + uvm_processor_id_t preferred_location, + uvm_fault_buffer_entry_t *current_entry, + bool is_duplicate) { - UVM_ASSERT(previous_entry); - UVM_ASSERT(check_fault_entry_duplicate(current_entry, previous_entry)); + if (is_duplicate) + batch_context->num_duplicate_faults += current_entry->num_instances; + else + batch_context->num_duplicate_faults += current_entry->num_instances - 1; - // Propagate the is_invalid_prefetch flag across all prefetch faults - // on the page - if (previous_entry->is_invalid_prefetch) - current_entry->is_invalid_prefetch = true; + uvm_perf_event_notify_gpu_fault(¤t_entry->va_space->perf_events, + va_block, + gpu->id, + preferred_location, + current_entry, + batch_context->batch_id, + is_duplicate); +} - // If a page is throttled, all faults on the page must be skipped - if (previous_entry->is_throttled) - current_entry->is_throttled = true; +static void mark_fault_invalid_prefetch(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *fault_entry) +{ + fault_entry->is_invalid_prefetch = true; + + // For block faults, the following counter might be updated more than once + // for the same fault if block_context->num_retries > 0. As a result, this + // counter might be higher than the actual count. In order for this counter + // to be always accurate, block_context needs to passed down the stack from + // all callers. But since num_retries > 0 case is uncommon and imprecise + // invalid_prefetch counter doesn't affect functionality (other than + // disabling prefetching if the counter indicates lots of invalid prefetch + // faults), this is ok. + batch_context->num_invalid_prefetch_faults += fault_entry->num_instances; } -static void update_batch_context(uvm_fault_service_batch_context_t *batch_context, - uvm_fault_buffer_entry_t *current_entry, - const uvm_fault_buffer_entry_t *previous_entry) +static void mark_fault_throttled(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *fault_entry) { - bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); - uvm_fault_utlb_info_t *utlb = &batch_context->utlbs[current_entry->fault_source.utlb_id]; + fault_entry->is_throttled = true; + batch_context->has_throttled_faults = true; +} - UVM_ASSERT(utlb->num_pending_faults > 0); +static void mark_fault_fatal(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *fault_entry, + UvmEventFatalReason fatal_reason, + uvm_fault_cancel_va_mode_t cancel_va_mode) +{ + uvm_fault_utlb_info_t *utlb = &batch_context->utlbs[fault_entry->fault_source.utlb_id]; - if (is_duplicate) - batch_context->num_duplicate_faults += current_entry->num_instances; - else - batch_context->num_duplicate_faults += current_entry->num_instances - 1; + fault_entry->is_fatal = true; + fault_entry->fatal_reason = fatal_reason; + fault_entry->replayable.cancel_va_mode = cancel_va_mode; - if (current_entry->is_invalid_prefetch) - batch_context->num_invalid_prefetch_faults += current_entry->num_instances; + utlb->has_fatal_faults = true; + batch_context->has_fatal_faults = true; +} - if (current_entry->is_fatal) { - utlb->has_fatal_faults = true; - batch_context->has_fatal_faults = true; - } +static void fault_entry_duplicate_flags(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *current_entry, + const uvm_fault_buffer_entry_t *previous_entry) +{ + UVM_ASSERT(previous_entry); + UVM_ASSERT(check_fault_entry_duplicate(current_entry, previous_entry)); + + // Propagate the is_invalid_prefetch flag across all prefetch faults + // on the page + if (previous_entry->is_invalid_prefetch) + mark_fault_invalid_prefetch(batch_context, current_entry); - if (current_entry->is_throttled) - batch_context->has_throttled_faults = true; + // If a page is throttled, all faults on the page must be skipped + if (previous_entry->is_throttled) + mark_fault_throttled(batch_context, current_entry); } // This function computes the maximum access type that can be serviced for the @@ -1109,12 +1204,17 @@ static void update_batch_context(uvm_fault_service_batch_context_t *batch_contex // Return values: // - service_access_type: highest access type that can be serviced. static uvm_fault_access_type_t check_fault_access_permissions(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, + uvm_service_block_context_t *service_block_context, uvm_fault_buffer_entry_t *fault_entry, bool allow_migration) { NV_STATUS perm_status; + UvmEventFatalReason fatal_reason; + uvm_fault_cancel_va_mode_t cancel_va_mode; + uvm_fault_access_type_t ret = UVM_FAULT_ACCESS_TYPE_COUNT; + uvm_va_block_context_t *va_block_context = &service_block_context->block_context; perm_status = uvm_va_block_check_logical_permissions(va_block, va_block_context, @@ -1127,16 +1227,20 @@ static uvm_fault_access_type_t check_fault_access_permissions(uvm_gpu_t *gpu, return fault_entry->fault_access_type; if (fault_entry->fault_access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH) { - fault_entry->is_invalid_prefetch = true; - return UVM_FAULT_ACCESS_TYPE_COUNT; + // Only update the count the first time since logical permissions cannot + // change while we hold the VA space lock + // TODO: Bug 1750144: That might not be true with HMM. + if (service_block_context->num_retries == 0) + mark_fault_invalid_prefetch(batch_context, fault_entry); + + return ret; } // At this point we know that some fault instances cannot be serviced - fault_entry->is_fatal = true; - fault_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(perm_status); + fatal_reason = uvm_tools_status_to_fatal_fault_reason(perm_status); if (fault_entry->fault_access_type > UVM_FAULT_ACCESS_TYPE_READ) { - fault_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC; + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC; // If there are pending read accesses on the same page, we have to // service them before we can cancel the write/atomic faults. So we @@ -1149,19 +1253,23 @@ static uvm_fault_access_type_t check_fault_access_permissions(uvm_gpu_t *gpu, fault_entry->fault_address), UVM_FAULT_ACCESS_TYPE_READ, allow_migration); - if (perm_status == NV_OK) - return UVM_FAULT_ACCESS_TYPE_READ; - - // If that didn't succeed, cancel all faults - fault_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; - fault_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(perm_status); + if (perm_status == NV_OK) { + ret = UVM_FAULT_ACCESS_TYPE_READ; + } + else { + // Read accesses didn't succeed, cancel all faults + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + fatal_reason = uvm_tools_status_to_fatal_fault_reason(perm_status); + } } } else { - fault_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; } - return UVM_FAULT_ACCESS_TYPE_COUNT; + mark_fault_fatal(batch_context, fault_entry, fatal_reason, cancel_va_mode); + + return ret; } // We notify the fault event for all faults within the block so that the @@ -1258,24 +1366,26 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); } + // Only update counters the first time since logical permissions cannot + // change while we hold the VA space lock. + // TODO: Bug 1750144: That might not be true with HMM. if (block_context->num_retries == 0) { - uvm_perf_event_notify_gpu_fault(&va_space->perf_events, - va_block, - gpu->id, - block_context->block_context.policy->preferred_location, - current_entry, - batch_context->batch_id, - is_duplicate); + update_batch_and_notify_fault(gpu, + batch_context, + va_block, + block_context->block_context.policy->preferred_location, + current_entry, + is_duplicate); } // Service the most intrusive fault per page, only. Waive the rest if (is_duplicate) { - fault_entry_duplicate_flags(current_entry, previous_entry); + fault_entry_duplicate_flags(batch_context, current_entry, previous_entry); // The previous fault was non-fatal so the page has been already // serviced if (!previous_entry->is_fatal) - goto next; + continue; } // Ensure that the migratability iterator covers the current fault @@ -1286,15 +1396,16 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, UVM_ASSERT(iter.start <= current_entry->fault_address && iter.end >= current_entry->fault_address); service_access_type = check_fault_access_permissions(gpu, + batch_context, va_block, - &block_context->block_context, + block_context, current_entry, iter.migratable); // Do not exit early due to logical errors such as access permission // violation. if (service_access_type == UVM_FAULT_ACCESS_TYPE_COUNT) - goto next; + continue; if (service_access_type != current_entry->fault_access_type) { // Some of the fault instances cannot be serviced due to invalid @@ -1313,15 +1424,21 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, page_index, gpu->id, uvm_fault_access_type_to_prot(service_access_type))) - goto next; + continue; thrashing_hint = uvm_perf_thrashing_get_hint(va_block, current_entry->fault_address, gpu->id); if (thrashing_hint.type == UVM_PERF_THRASHING_HINT_TYPE_THROTTLE) { // Throttling is implemented by sleeping in the fault handler on // the CPU and by continuing to process faults on other pages on // the GPU - current_entry->is_throttled = true; - goto next; + // + // Only update the flag the first time since logical permissions + // cannot change while we hold the VA space lock. + // TODO: Bug 1750144: That might not be true with HMM. + if (block_context->num_retries == 0) + mark_fault_throttled(batch_context, current_entry); + + continue; } else if (thrashing_hint.type == UVM_PERF_THRASHING_HINT_TYPE_PIN) { if (block_context->thrashing_pin_count++ == 0) @@ -1361,13 +1478,6 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, first_page_index = page_index; if (page_index > last_page_index) last_page_index = page_index; - - next: - // Only update counters the first time since logical permissions cannot - // change while we hold the VA space lock - // TODO: Bug 1750144: That might not be true with HMM. - if (block_context->num_retries == 0) - update_batch_context(batch_context, current_entry, previous_entry); } // Apply the changes computed in the fault service block context, if there @@ -1408,6 +1518,9 @@ static NV_STATUS service_fault_batch_block(uvm_gpu_t *gpu, fault_block_context->operation = UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS; fault_block_context->num_retries = 0; + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_begin_wait(va_block); + uvm_mutex_lock(&va_block->lock); status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, &va_block_retry, @@ -1422,6 +1535,9 @@ static NV_STATUS service_fault_batch_block(uvm_gpu_t *gpu, uvm_mutex_unlock(&va_block->lock); + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_finish(va_block); + return status == NV_OK? tracker_status: status; } @@ -1435,116 +1551,350 @@ typedef enum FAULT_SERVICE_MODE_CANCEL, } fault_service_mode_t; -static NV_STATUS service_fault_batch_ats(uvm_gpu_va_space_t *gpu_va_space, - struct mm_struct *mm, - uvm_fault_service_batch_context_t *batch_context, - NvU32 first_fault_index, - NvU32 *block_faults) +static void service_fault_batch_fatal(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NV_STATUS status, + uvm_fault_cancel_va_mode_t cancel_va_mode, + NvU32 *block_faults) { - NV_STATUS status; - uvm_gpu_t *gpu = gpu_va_space->gpu; - uvm_ats_fault_invalidate_t *ats_invalidate = &gpu->parent->fault_buffer_info.replayable.ats_invalidate; uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[first_fault_index]; const uvm_fault_buffer_entry_t *previous_entry = first_fault_index > 0 ? batch_context->ordered_fault_cache[first_fault_index - 1] : NULL; bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); if (is_duplicate) - fault_entry_duplicate_flags(current_entry, previous_entry); + fault_entry_duplicate_flags(batch_context, current_entry, previous_entry); - // Generate fault events for all fault packets - uvm_perf_event_notify_gpu_fault(¤t_entry->va_space->perf_events, - NULL, - gpu->id, - UVM_ID_INVALID, - current_entry, - batch_context->batch_id, - is_duplicate); - - // The VA isn't managed. See if ATS knows about it, unless it is a - // duplicate and the previous fault was non-fatal so the page has - // already been serviced - // - // TODO: Bug 2103669: Service more than one ATS fault at a time so we - // don't do an unconditional VA range lookup for every ATS fault. - if (!is_duplicate || previous_entry->is_fatal) - status = uvm_ats_service_fault_entry(gpu_va_space, current_entry, ats_invalidate); + if (current_entry->fault_access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH) + mark_fault_invalid_prefetch(batch_context, current_entry); else - status = NV_OK; + mark_fault_fatal(batch_context, current_entry, uvm_tools_status_to_fatal_fault_reason(status), cancel_va_mode); (*block_faults)++; - - update_batch_context(batch_context, current_entry, previous_entry); - - return status; } -static void service_fault_batch_fatal(uvm_gpu_t *gpu, - uvm_fault_service_batch_context_t *batch_context, - NvU32 first_fault_index, - NV_STATUS status, - NvU32 *block_faults) +static void service_fault_batch_fatal_notify(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NV_STATUS status, + uvm_fault_cancel_va_mode_t cancel_va_mode, + NvU32 *block_faults) { uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[first_fault_index]; const uvm_fault_buffer_entry_t *previous_entry = first_fault_index > 0 ? batch_context->ordered_fault_cache[first_fault_index - 1] : NULL; bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); - if (is_duplicate) - fault_entry_duplicate_flags(current_entry, previous_entry); + service_fault_batch_fatal(gpu, batch_context, first_fault_index, status, cancel_va_mode, block_faults); - // The VA block cannot be found, set the fatal fault flag, - // unless it is a prefetch fault - if (current_entry->fault_access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH) { - current_entry->is_invalid_prefetch = true; + update_batch_and_notify_fault(gpu, batch_context, NULL, UVM_ID_INVALID, current_entry, is_duplicate); +} + +static NV_STATUS service_fault_batch_ats_sub_vma(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_fault_service_batch_context_t *batch_context, + NvU32 fault_index_start, + NvU32 fault_index_end, + NvU32 *block_faults) +{ + NvU32 i; + NV_STATUS status = NV_OK; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_ats_fault_context_t *ats_context = &batch_context->ats_context; + const uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + const uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + const uvm_page_mask_t *faults_serviced_mask = &ats_context->faults_serviced_mask; + const uvm_page_mask_t *reads_serviced_mask = &ats_context->reads_serviced_mask; + uvm_page_mask_t *tmp_mask = &ats_context->tmp_mask; + + UVM_ASSERT(vma); + + ats_context->client_type = UVM_FAULT_CLIENT_TYPE_GPC; + + uvm_page_mask_or(tmp_mask, write_fault_mask, read_fault_mask); + + status = uvm_ats_service_faults(gpu_va_space, vma, base, &batch_context->ats_context); + + UVM_ASSERT(uvm_page_mask_subset(faults_serviced_mask, tmp_mask)); + + if ((status != NV_OK) || uvm_page_mask_equal(faults_serviced_mask, tmp_mask)) { + (*block_faults) += (fault_index_end - fault_index_start); + return status; } - else { - current_entry->is_fatal = true; - current_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + + // Check faults_serviced_mask and reads_serviced_mask for precise fault + // attribution after calling the ATS servicing routine. The + // errors returned from ATS servicing routine should only be + // global errors such as OOM or ECC. uvm_gpu_service_replayable_faults() + // handles global errors by calling cancel_fault_batch(). Precise + // attribution isn't currently supported in such cases. + // + // Precise fault attribution for global errors can be handled by + // servicing one fault at a time until fault servicing encounters an + // error. + // TODO: Bug 3989244: Precise ATS fault attribution for global errors. + for (i = fault_index_start; i < fault_index_end; i++) { + uvm_page_index_t page_index; + uvm_fault_cancel_va_mode_t cancel_va_mode; + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + uvm_fault_access_type_t access_type = current_entry->fault_access_type; + + page_index = (current_entry->fault_address - base) / PAGE_SIZE; + + if (uvm_page_mask_test(faults_serviced_mask, page_index)) { + (*block_faults)++; + continue; + } + + if (access_type <= UVM_FAULT_ACCESS_TYPE_READ) { + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + } + else if (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE) { + if (uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ) && + !uvm_page_mask_test(reads_serviced_mask, page_index)) + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + else + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC; + } + + service_fault_batch_fatal(gpu, batch_context, i, NV_ERR_INVALID_ADDRESS, cancel_va_mode, block_faults); } - update_batch_context(batch_context, current_entry, previous_entry); + return status; +} - uvm_perf_event_notify_gpu_fault(¤t_entry->va_space->perf_events, - NULL, - gpu->id, - UVM_ID_INVALID, - current_entry, - batch_context->batch_id, - is_duplicate); +static void start_new_sub_batch(NvU64 *sub_batch_base, + NvU64 address, + NvU32 *sub_batch_fault_index, + NvU32 fault_index, + uvm_ats_fault_context_t *ats_context) +{ + uvm_page_mask_zero(&ats_context->read_fault_mask); + uvm_page_mask_zero(&ats_context->write_fault_mask); - (*block_faults)++; + *sub_batch_fault_index = fault_index; + *sub_batch_base = UVM_VA_BLOCK_ALIGN_DOWN(address); +} + +static NV_STATUS service_fault_batch_ats_sub(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + uvm_fault_service_batch_context_t *batch_context, + NvU32 fault_index, + NvU64 outer, + NvU32 *block_faults) +{ + NV_STATUS status = NV_OK; + NvU32 i = fault_index; + NvU32 sub_batch_fault_index; + NvU64 sub_batch_base; + uvm_fault_buffer_entry_t *previous_entry = NULL; + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + uvm_ats_fault_context_t *ats_context = &batch_context->ats_context; + uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + uvm_gpu_t *gpu = gpu_va_space->gpu; + bool replay_per_va_block = + (gpu->parent->fault_buffer_info.replayable.replay_policy == UVM_PERF_FAULT_REPLAY_POLICY_BLOCK); + + UVM_ASSERT(vma); + + outer = min(outer, (NvU64) vma->vm_end); + + start_new_sub_batch(&sub_batch_base, current_entry->fault_address, &sub_batch_fault_index, i, ats_context); + + do { + uvm_page_index_t page_index; + NvU64 fault_address = current_entry->fault_address; + uvm_fault_access_type_t access_type = current_entry->fault_access_type; + bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); + + i++; + + update_batch_and_notify_fault(gpu_va_space->gpu, + batch_context, + NULL, + UVM_ID_INVALID, + current_entry, + is_duplicate); + + // End of sub-batch. Service faults gathered so far. + if (fault_address >= (sub_batch_base + UVM_VA_BLOCK_SIZE)) { + UVM_ASSERT(!uvm_page_mask_empty(read_fault_mask) || !uvm_page_mask_empty(write_fault_mask)); + + status = service_fault_batch_ats_sub_vma(gpu_va_space, + vma, + sub_batch_base, + batch_context, + sub_batch_fault_index, + i - 1, + block_faults); + if (status != NV_OK || replay_per_va_block) + break; + + start_new_sub_batch(&sub_batch_base, fault_address, &sub_batch_fault_index, i - 1, ats_context); + } + + page_index = (fault_address - sub_batch_base) / PAGE_SIZE; + + if ((access_type <= UVM_FAULT_ACCESS_TYPE_READ) || + uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ)) + uvm_page_mask_set(read_fault_mask, page_index); + + if (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE) + uvm_page_mask_set(write_fault_mask, page_index); + + previous_entry = current_entry; + current_entry = i < batch_context->num_coalesced_faults ? batch_context->ordered_fault_cache[i] : NULL; + + } while (current_entry && + (current_entry->fault_address < outer) && + (previous_entry->va_space == current_entry->va_space)); + + // Service the last sub-batch. + if ((status == NV_OK) && (!uvm_page_mask_empty(read_fault_mask) || !uvm_page_mask_empty(write_fault_mask))) { + status = service_fault_batch_ats_sub_vma(gpu_va_space, + vma, + sub_batch_base, + batch_context, + sub_batch_fault_index, + i, + block_faults); + } + + return status; +} + +static NV_STATUS service_fault_batch_ats(uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NvU64 outer, + NvU32 *block_faults) +{ + NvU32 i; + NV_STATUS status = NV_OK; + + for (i = first_fault_index; i < batch_context->num_coalesced_faults;) { + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + const uvm_fault_buffer_entry_t *previous_entry = i > first_fault_index ? + batch_context->ordered_fault_cache[i - 1] : NULL; + NvU64 fault_address = current_entry->fault_address; + struct vm_area_struct *vma; + NvU32 num_faults_before = (*block_faults); + + if (previous_entry && (previous_entry->va_space != current_entry->va_space)) + break; + + if (fault_address >= outer) + break; + + vma = find_vma_intersection(mm, fault_address, fault_address + 1); + if (!vma) { + // Since a vma wasn't found, cancel all accesses on the page since + // cancelling write and atomic accesses will not cancel pending read + // faults and this can lead to a deadlock since read faults need to + // be serviced first before cancelling write faults. + service_fault_batch_fatal_notify(gpu_va_space->gpu, + batch_context, + i, + NV_ERR_INVALID_ADDRESS, + UVM_FAULT_CANCEL_VA_MODE_ALL, + block_faults); + + // Do not fail due to logical errors. + status = NV_OK; + + break; + } + + status = service_fault_batch_ats_sub(gpu_va_space, vma, batch_context, i, outer, block_faults); + if (status != NV_OK) + break; + + i += ((*block_faults) - num_faults_before); + } + + return status; } static NV_STATUS service_fault_batch_dispatch(uvm_va_space_t *va_space, uvm_gpu_va_space_t *gpu_va_space, uvm_fault_service_batch_context_t *batch_context, - NvU32 first_fault_index, - NvU32 *block_faults) + NvU32 fault_index, + NvU32 *block_faults, + bool replay_per_va_block) { NV_STATUS status; - uvm_va_range_t *va_range; + uvm_va_range_t *va_range = NULL; + uvm_va_range_t *va_range_next = NULL; uvm_va_block_t *va_block; uvm_gpu_t *gpu = gpu_va_space->gpu; uvm_va_block_context_t *va_block_context = &gpu->parent->fault_buffer_info.replayable.block_service_context.block_context; - uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[first_fault_index]; + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[fault_index]; struct mm_struct *mm = va_block_context->mm; NvU64 fault_address = current_entry->fault_address; (*block_faults) = 0; - va_range = uvm_va_range_find(va_space, fault_address); + va_range_next = uvm_va_space_iter_first(va_space, fault_address, ~0ULL); + if (va_range_next && (fault_address >= va_range_next->node.start)) { + UVM_ASSERT(fault_address < va_range_next->node.end); + + va_range = va_range_next; + va_range_next = uvm_va_space_iter_next(va_range_next, ~0ULL); + } + status = uvm_va_block_find_create_in_range(va_space, va_range, fault_address, va_block_context, &va_block); if (status == NV_OK) { - status = service_fault_batch_block(gpu, va_block, batch_context, first_fault_index, block_faults); + status = service_fault_batch_block(gpu, va_block, batch_context, fault_index, block_faults); } else if ((status == NV_ERR_INVALID_ADDRESS) && uvm_ats_can_service_faults(gpu_va_space, mm)) { - status = service_fault_batch_ats(gpu_va_space, mm, batch_context, first_fault_index, block_faults); + NvU64 outer = ~0ULL; + + UVM_ASSERT(replay_per_va_block == + (gpu->parent->fault_buffer_info.replayable.replay_policy == UVM_PERF_FAULT_REPLAY_POLICY_BLOCK)); + + // Limit outer to the minimum of next va_range.start and first + // fault_address' next UVM_GMMU_ATS_GRANULARITY alignment so that it's + // enough to check whether the first fault in this dispatch belongs to a + // GMMU region. + if (va_range_next) { + outer = min(va_range_next->node.start, + UVM_ALIGN_DOWN(fault_address + UVM_GMMU_ATS_GRANULARITY, UVM_GMMU_ATS_GRANULARITY)); + } + + // ATS lookups are disabled on all addresses within the same + // UVM_GMMU_ATS_GRANULARITY as existing GMMU mappings (see documentation + // in uvm_mmu.h). User mode is supposed to reserve VAs as appropriate to + // prevent any system memory allocations from falling within the NO_ATS + // range of other GMMU mappings, so this shouldn't happen during normal + // operation. However, since this scenario may lead to infinite fault + // loops, we handle it by canceling the fault. + if (uvm_ats_check_in_gmmu_region(va_space, fault_address, va_range_next)) { + service_fault_batch_fatal_notify(gpu, + batch_context, + fault_index, + NV_ERR_INVALID_ADDRESS, + UVM_FAULT_CANCEL_VA_MODE_ALL, + block_faults); + + // Do not fail due to logical errors + status = NV_OK; + } + else { + status = service_fault_batch_ats(gpu_va_space, mm, batch_context, fault_index, outer, block_faults); + } } else { - service_fault_batch_fatal(gpu_va_space->gpu, batch_context, first_fault_index, status, block_faults); + service_fault_batch_fatal_notify(gpu, + batch_context, + fault_index, + status, + UVM_FAULT_CANCEL_VA_MODE_ALL, + block_faults); // Do not fail due to logical errors status = NV_OK; @@ -1573,12 +1923,14 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, struct mm_struct *mm = NULL; const bool replay_per_va_block = service_mode != FAULT_SERVICE_MODE_CANCEL && gpu->parent->fault_buffer_info.replayable.replay_policy == UVM_PERF_FAULT_REPLAY_POLICY_BLOCK; - uvm_va_block_context_t *va_block_context = - &gpu->parent->fault_buffer_info.replayable.block_service_context.block_context; + uvm_service_block_context_t *service_context = + &gpu->parent->fault_buffer_info.replayable.block_service_context; + uvm_va_block_context_t *va_block_context = &service_context->block_context; UVM_ASSERT(gpu->parent->replayable_faults_supported); ats_invalidate->write_faults_in_batch = false; + uvm_hmm_service_context_init(service_context); for (i = 0; i < batch_context->num_coalesced_faults;) { NvU32 block_faults; @@ -1616,7 +1968,7 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); if (uvm_processor_mask_test_and_clear_atomic(&va_space->needs_fault_buffer_flush, gpu->id)) { status = fault_buffer_flush_locked(gpu, - UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, + UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START, batch_context); if (status == NV_OK) @@ -1649,7 +2001,12 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, continue; } - status = service_fault_batch_dispatch(va_space, gpu_va_space, batch_context, i, &block_faults); + status = service_fault_batch_dispatch(va_space, + gpu_va_space, + batch_context, + i, + &block_faults, + replay_per_va_block); // TODO: Bug 3900733: clean up locking in service_fault_batch(). if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { uvm_va_space_up_read(va_space); @@ -2095,7 +2452,11 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat // arriving. Therefore, in each iteration we just try to cancel faults // from uTLBs that contained fatal faults in the previous iterations // and will cause the TLB to stop generating new page faults after the - // following replay with type UVM_FAULT_REPLAY_TYPE_START_ACK_ALL + // following replay with type UVM_FAULT_REPLAY_TYPE_START_ACK_ALL. + // + // No need to use UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT since we + // don't care too much about old faults, just new faults from uTLBs + // which faulted before the replay. status = fault_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START_ACK_ALL, @@ -2204,6 +2565,8 @@ static void enable_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu, uvm_fau // If more than 66% of faults are invalid prefetch accesses, disable // prefetch faults for a while. + // num_invalid_prefetch_faults may be higher than the actual count. See the + // comment in mark_fault_invalid_prefetch(..). // Some tests rely on this logic (and ratio) to correctly disable prefetch // fault reporting. If the logic changes, the tests will have to be changed. if (parent_gpu->fault_buffer_info.prefetch_faults_enabled && diff --git a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h index 2e10f6ebc7..a052e1195c 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h +++ b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h @@ -75,4 +75,7 @@ void uvm_gpu_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu); // only called from the ISR bottom half void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu); +// Returns true if UVM owns the hardware replayable fault buffer +bool uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(uvm_parent_gpu_t *parent_gpu); + #endif // __UVM_GPU_PAGE_FAULT_H__ diff --git a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c index 8b455715b3..3887ad8047 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c @@ -26,6 +26,7 @@ #include "uvm_global.h" #include "uvm_kvmalloc.h" #include "uvm_channel.h" // For UVM_GPU_SEMAPHORE_MAX_JUMP +#include "uvm_conf_computing.h" #define UVM_SEMAPHORE_SIZE 4 #define UVM_SEMAPHORE_PAGE_SIZE PAGE_SIZE @@ -44,6 +45,9 @@ struct uvm_gpu_semaphore_pool_struct // List of all the semaphore pages belonging to the pool struct list_head pages; + // Pages aperture. + uvm_aperture_t aperture; + // Count of free semaphores among all the pages NvU32 free_semaphores_count; @@ -66,11 +70,24 @@ struct uvm_gpu_semaphore_pool_page_struct DECLARE_BITMAP(free_semaphores, UVM_SEMAPHORE_COUNT_PER_PAGE); }; +static bool gpu_semaphore_pool_is_secure(uvm_gpu_semaphore_pool_t *pool) +{ + return uvm_conf_computing_mode_enabled(pool->gpu) && (pool->aperture == UVM_APERTURE_VID); +} + +static bool gpu_semaphore_is_secure(uvm_gpu_semaphore_t *semaphore) +{ + return gpu_semaphore_pool_is_secure(semaphore->page->pool); +} + static NvU32 get_index(uvm_gpu_semaphore_t *semaphore) { NvU32 offset; NvU32 index; + if (gpu_semaphore_is_secure(semaphore)) + return semaphore->conf_computing.index; + UVM_ASSERT(semaphore->payload != NULL); UVM_ASSERT(semaphore->page != NULL); @@ -118,6 +135,14 @@ static bool is_canary(NvU32 val) return (val & ~UVM_SEMAPHORE_CANARY_MASK) == UVM_SEMAPHORE_CANARY_BASE; } +static bool semaphore_uses_canary(uvm_gpu_semaphore_pool_t *pool) +{ + // A pool allocated in the CPR of vidmem cannot be read/written from the + // CPU. + return !gpu_semaphore_pool_is_secure(pool) && UVM_IS_DEBUG(); + return UVM_IS_DEBUG(); +} + // Can the GPU access the semaphore, i.e., can Host/Esched address the semaphore // pool? static bool gpu_can_access_semaphore_pool(uvm_gpu_t *gpu, uvm_rm_mem_t *rm_mem) @@ -125,13 +150,34 @@ static bool gpu_can_access_semaphore_pool(uvm_gpu_t *gpu, uvm_rm_mem_t *rm_mem) return ((uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu) + rm_mem->size - 1) < gpu->parent->max_host_va); } +// Secure semaphore pools are allocated in the CPR of vidmem and only mapped to +// the owning GPU as no other processor have access to it. +static NV_STATUS pool_alloc_secure_page(uvm_gpu_semaphore_pool_t *pool, + uvm_gpu_semaphore_pool_page_t *pool_page, + uvm_rm_mem_type_t memory_type) +{ + NV_STATUS status; + + UVM_ASSERT(gpu_semaphore_pool_is_secure(pool)); + status = uvm_rm_mem_alloc(pool->gpu, + memory_type, + UVM_SEMAPHORE_PAGE_SIZE, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &pool_page->memory); + + if (status != NV_OK) + return status; + + return NV_OK; +} + static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) { NV_STATUS status; uvm_gpu_semaphore_pool_page_t *pool_page; NvU32 *payloads; size_t i; - uvm_rm_mem_type_t rm_mem_type = UVM_RM_MEM_TYPE_SYS; + uvm_rm_mem_type_t memory_type = (pool->aperture == UVM_APERTURE_SYS) ? UVM_RM_MEM_TYPE_SYS : UVM_RM_MEM_TYPE_GPU; uvm_assert_mutex_locked(&pool->mutex); @@ -142,13 +188,24 @@ static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) pool_page->pool = pool; + // Whenever the Confidential Computing feature is enabled, engines can + // access semaphores only in the CPR of vidmem. Mapping to other GPUs is + // also disabled. + if (gpu_semaphore_pool_is_secure(pool)) { + status = pool_alloc_secure_page(pool, pool_page, memory_type); + + if (status != NV_OK) + goto error; + } + else { status = uvm_rm_mem_alloc_and_map_all(pool->gpu, - rm_mem_type, + memory_type, UVM_SEMAPHORE_PAGE_SIZE, 0, &pool_page->memory); if (status != NV_OK) goto error; + } // Verify the GPU can access the semaphore pool. UVM_ASSERT(gpu_can_access_semaphore_pool(pool->gpu, pool_page->memory)); @@ -159,8 +216,7 @@ static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) list_add(&pool_page->all_pages_node, &pool->pages); pool->free_semaphores_count += UVM_SEMAPHORE_COUNT_PER_PAGE; - // Initialize the semaphore payloads to known values - if (UVM_IS_DEBUG()) { + if (semaphore_uses_canary(pool)) { payloads = uvm_rm_mem_get_cpu_va(pool_page->memory); for (i = 0; i < UVM_SEMAPHORE_COUNT_PER_PAGE; i++) payloads[i] = make_canary(0); @@ -176,8 +232,6 @@ static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) static void pool_free_page(uvm_gpu_semaphore_pool_page_t *page) { uvm_gpu_semaphore_pool_t *pool; - NvU32 *payloads; - size_t i; UVM_ASSERT(page); pool = page->pool; @@ -190,9 +244,9 @@ static void pool_free_page(uvm_gpu_semaphore_pool_page_t *page) "count: %u\n", pool->free_semaphores_count); - // Check for semaphore release-after-free - if (UVM_IS_DEBUG()) { - payloads = uvm_rm_mem_get_cpu_va(page->memory); + if (semaphore_uses_canary(pool)) { + size_t i; + NvU32 *payloads = uvm_rm_mem_get_cpu_va(page->memory); for (i = 0; i < UVM_SEMAPHORE_COUNT_PER_PAGE; i++) UVM_ASSERT(is_canary(payloads[i])); } @@ -223,11 +277,18 @@ NV_STATUS uvm_gpu_semaphore_alloc(uvm_gpu_semaphore_pool_t *pool, uvm_gpu_semaph if (semaphore_index == UVM_SEMAPHORE_COUNT_PER_PAGE) continue; - semaphore->payload = (NvU32*)((char*)uvm_rm_mem_get_cpu_va(page->memory) + semaphore_index * UVM_SEMAPHORE_SIZE); + if (gpu_semaphore_pool_is_secure(pool)) { + semaphore->conf_computing.index = semaphore_index; + } + else { + semaphore->payload = (NvU32*)((char*)uvm_rm_mem_get_cpu_va(page->memory) + + semaphore_index * UVM_SEMAPHORE_SIZE); + } + semaphore->page = page; - // Check for semaphore release-after-free - UVM_ASSERT(is_canary(uvm_gpu_semaphore_get_payload(semaphore))); + if (semaphore_uses_canary(pool)) + UVM_ASSERT(is_canary(uvm_gpu_semaphore_get_payload(semaphore))); uvm_gpu_semaphore_set_payload(semaphore, 0); @@ -266,7 +327,7 @@ void uvm_gpu_semaphore_free(uvm_gpu_semaphore_t *semaphore) // Write a known value lower than the current payload in an attempt to catch // release-after-free and acquire-after-free. - if (UVM_IS_DEBUG()) + if (semaphore_uses_canary(pool)) uvm_gpu_semaphore_set_payload(semaphore, make_canary(uvm_gpu_semaphore_get_payload(semaphore))); uvm_mutex_lock(&pool->mutex); @@ -294,12 +355,26 @@ NV_STATUS uvm_gpu_semaphore_pool_create(uvm_gpu_t *gpu, uvm_gpu_semaphore_pool_t pool->free_semaphores_count = 0; pool->gpu = gpu; + pool->aperture = UVM_APERTURE_SYS; *pool_out = pool; return NV_OK; } +NV_STATUS uvm_gpu_semaphore_secure_pool_create(uvm_gpu_t *gpu, uvm_gpu_semaphore_pool_t **pool_out) +{ + NV_STATUS status; + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + status = uvm_gpu_semaphore_pool_create(gpu, pool_out); + if (status == NV_OK) + (*pool_out)->aperture = UVM_APERTURE_VID; + + return status; +} + void uvm_gpu_semaphore_pool_destroy(uvm_gpu_semaphore_pool_t *pool) { uvm_gpu_semaphore_pool_page_t *page; @@ -375,13 +450,16 @@ NvU64 uvm_gpu_semaphore_get_gpu_proxy_va(uvm_gpu_semaphore_t *semaphore, uvm_gpu NvU64 uvm_gpu_semaphore_get_gpu_va(uvm_gpu_semaphore_t *semaphore, uvm_gpu_t *gpu, bool is_proxy_va_space) { NvU32 index = get_index(semaphore); - NvU64 base_va = uvm_rm_mem_get_gpu_va(semaphore->page->memory, gpu, is_proxy_va_space); + NvU64 base_va = uvm_rm_mem_get_gpu_va(semaphore->page->memory, gpu, is_proxy_va_space).address; return base_va + UVM_SEMAPHORE_SIZE * index; } NvU32 uvm_gpu_semaphore_get_payload(uvm_gpu_semaphore_t *semaphore) { + if (gpu_semaphore_is_secure(semaphore)) + return UVM_GPU_READ_ONCE(semaphore->conf_computing.cached_payload); + return UVM_GPU_READ_ONCE(*semaphore->payload); } @@ -398,6 +476,10 @@ void uvm_gpu_semaphore_set_payload(uvm_gpu_semaphore_t *semaphore, NvU32 payload // being optimized out on non-SMP configs (we need them for interacting with // the GPU correctly even on non-SMP). mb(); + + if (gpu_semaphore_is_secure(semaphore)) + UVM_GPU_WRITE_ONCE(semaphore->conf_computing.cached_payload, payload); + else UVM_GPU_WRITE_ONCE(*semaphore->payload, payload); } @@ -425,9 +507,22 @@ static bool tracking_semaphore_check_gpu(uvm_gpu_tracking_semaphore_t *tracking_ return true; } +bool tracking_semaphore_uses_mutex(uvm_gpu_tracking_semaphore_t *tracking_semaphore) +{ + uvm_gpu_t *gpu = tracking_semaphore->semaphore.page->pool->gpu; + + UVM_ASSERT(tracking_semaphore_check_gpu(tracking_semaphore)); + if (uvm_conf_computing_mode_enabled(gpu)) + return true; + + return false; +} + + NV_STATUS uvm_gpu_tracking_semaphore_alloc(uvm_gpu_semaphore_pool_t *pool, uvm_gpu_tracking_semaphore_t *tracking_sem) { NV_STATUS status; + uvm_lock_order_t order = UVM_LOCK_ORDER_LEAF; memset(tracking_sem, 0, sizeof(*tracking_sem)); @@ -437,7 +532,14 @@ NV_STATUS uvm_gpu_tracking_semaphore_alloc(uvm_gpu_semaphore_pool_t *pool, uvm_g UVM_ASSERT(uvm_gpu_semaphore_get_payload(&tracking_sem->semaphore) == 0); - uvm_spin_lock_init(&tracking_sem->lock, UVM_LOCK_ORDER_LEAF); + if (uvm_conf_computing_mode_enabled(pool->gpu)) + order = UVM_LOCK_ORDER_SECURE_SEMAPHORE; + + if (tracking_semaphore_uses_mutex(tracking_sem)) + uvm_mutex_init(&tracking_sem->m_lock, order); + else + uvm_spin_lock_init(&tracking_sem->s_lock, order); + atomic64_set(&tracking_sem->completed_value, 0); tracking_sem->queued_value = 0; @@ -449,15 +551,117 @@ void uvm_gpu_tracking_semaphore_free(uvm_gpu_tracking_semaphore_t *tracking_sem) uvm_gpu_semaphore_free(&tracking_sem->semaphore); } +static bool should_skip_secure_semaphore_update(NvU32 last_observed_notifier, NvU32 gpu_notifier) +{ + // No new value, or the GPU is currently writing the new encrypted material + // and no change in value would still result in corrupted data. + return (last_observed_notifier == gpu_notifier) || (gpu_notifier % 2); +} + +static void uvm_gpu_semaphore_encrypted_payload_update(uvm_channel_t *channel, uvm_gpu_semaphore_t *semaphore) +{ + UvmCslIv local_iv; + NvU32 local_payload; + NvU32 new_sem_value; + NvU32 gpu_notifier; + NvU32 last_observed_notifier; + NvU32 new_gpu_notifier = 0; + NvU32 iv_index = 0; + + // A channel can have multiple entries pending and the tracking semaphore + // update of each entry can race with this function. Since the semaphore + // needs to be updated to release a used entry, we never need more + // than 'num_gpfifo_entries' re-tries. + unsigned tries_left = channel->num_gpfifo_entries; + NV_STATUS status = NV_OK; + NvU8 local_auth_tag[UVM_CONF_COMPUTING_AUTH_TAG_SIZE]; + UvmCslIv *ivs_cpu_addr = semaphore->conf_computing.ivs; + void *auth_tag_cpu_addr = uvm_rm_mem_get_cpu_va(semaphore->conf_computing.auth_tag); + NvU32 *gpu_notifier_cpu_addr = (NvU32 *)uvm_rm_mem_get_cpu_va(semaphore->conf_computing.notifier); + NvU32 *payload_cpu_addr = (NvU32 *)uvm_rm_mem_get_cpu_va(semaphore->conf_computing.encrypted_payload); + + UVM_ASSERT(uvm_channel_is_secure_ce(channel)); + + last_observed_notifier = semaphore->conf_computing.last_observed_notifier; + gpu_notifier = UVM_READ_ONCE(*gpu_notifier_cpu_addr); + UVM_ASSERT(last_observed_notifier <= gpu_notifier); + + if (should_skip_secure_semaphore_update(last_observed_notifier, gpu_notifier)) + return; + + do { + gpu_notifier = UVM_READ_ONCE(*gpu_notifier_cpu_addr); + + // Odd notifier value means there's an update in progress. + if (gpu_notifier % 2) + continue; + + // Make sure no memory accesses happen before we read the notifier + smp_mb__after_atomic(); + + iv_index = (gpu_notifier / 2) % channel->num_gpfifo_entries; + memcpy(local_auth_tag, auth_tag_cpu_addr, sizeof(local_auth_tag)); + local_payload = UVM_READ_ONCE(*payload_cpu_addr); + memcpy(&local_iv, &ivs_cpu_addr[iv_index], sizeof(local_iv)); + + // Make sure the second read of notifier happens after + // all memory accesses. + smp_mb__before_atomic(); + new_gpu_notifier = UVM_READ_ONCE(*gpu_notifier_cpu_addr); + tries_left--; + } while ((tries_left > 0) && ((gpu_notifier != new_gpu_notifier) || (gpu_notifier % 2))); + + if (!tries_left) { + status = NV_ERR_INVALID_STATE; + goto error; + } + + if (gpu_notifier == new_gpu_notifier) { + status = uvm_conf_computing_cpu_decrypt(channel, + &new_sem_value, + &local_payload, + &local_iv, + sizeof(new_sem_value), + &local_auth_tag); + + if (status != NV_OK) + goto error; + + uvm_gpu_semaphore_set_payload(semaphore, new_sem_value); + UVM_WRITE_ONCE(semaphore->conf_computing.last_observed_notifier, new_gpu_notifier); + } + + return; + +error: + // Decryption failure is a fatal error as well as running out of try left. + // Upon testing, all decryption happened within one try, anything that + // would require ten retry would be considered active tampering with the + // data structures. + uvm_global_set_fatal_error(status); +} + static NvU64 update_completed_value_locked(uvm_gpu_tracking_semaphore_t *tracking_semaphore) { NvU64 old_value = atomic64_read(&tracking_semaphore->completed_value); // The semaphore value is the bottom 32 bits of completed_value NvU32 old_sem_value = (NvU32)old_value; - NvU32 new_sem_value = uvm_gpu_semaphore_get_payload(&tracking_semaphore->semaphore); + NvU32 new_sem_value; NvU64 new_value; - uvm_assert_spinlock_locked(&tracking_semaphore->lock); + if (tracking_semaphore_uses_mutex(tracking_semaphore)) + uvm_assert_mutex_locked(&tracking_semaphore->m_lock); + else + uvm_assert_spinlock_locked(&tracking_semaphore->s_lock); + + if (tracking_semaphore->semaphore.conf_computing.encrypted_payload) { + // TODO: Bug 4008734: [UVM][HCC] Extend secure tracking semaphore + // mechanism to all semaphore + uvm_channel_t *channel = container_of(tracking_semaphore, uvm_channel_t, tracking_sem); + uvm_gpu_semaphore_encrypted_payload_update(channel, &tracking_semaphore->semaphore); + } + + new_sem_value = uvm_gpu_semaphore_get_payload(&tracking_semaphore->semaphore); // The following logic to update the completed value is very subtle, it // helps to read https://www.kernel.org/doc/Documentation/memory-barriers.txt @@ -466,7 +670,7 @@ static NvU64 update_completed_value_locked(uvm_gpu_tracking_semaphore_t *trackin if (old_sem_value == new_sem_value) { // No progress since the last update. // No additional memory barrier required in this case as completed_value - // is always updated under the spinlock that this thread just acquired. + // is always updated under the lock that this thread just acquired. // That guarantees full ordering with all the accesses the thread that // updated completed_value did under the lock including the GPU // semaphore read. @@ -493,7 +697,7 @@ static NvU64 update_completed_value_locked(uvm_gpu_tracking_semaphore_t *trackin (NvU64)(uintptr_t)tracking_semaphore->semaphore.payload, old_value, new_value); - // Use an atomic write even though the spinlock is held so that the value can + // Use an atomic write even though the lock is held so that the value can // be (carefully) read atomically outside of the lock. // // atomic64_set() on its own doesn't imply any memory barriers and we need @@ -521,9 +725,9 @@ static NvU64 update_completed_value_locked(uvm_gpu_tracking_semaphore_t *trackin // guarantees that no accesses will be ordered above the atomic (and hence // the GPU semaphore read). // - // Notably the soon following uvm_spin_unlock() is a release barrier that - // allows later memory accesses to be reordered above it and hence doesn't - // provide the necessary ordering with the GPU semaphore read. + // Notably the soon following unlock is a release barrier that allows later + // memory accesses to be reordered above it and hence doesn't provide the + // necessary ordering with the GPU semaphore read. // // Also notably this would still need to be handled if we ever switch to // atomic64_set_release() and atomic64_read_acquire() for accessing @@ -540,11 +744,17 @@ NvU64 uvm_gpu_tracking_semaphore_update_completed_value(uvm_gpu_tracking_semapho // Check that the GPU which owns the semaphore is still present UVM_ASSERT(tracking_semaphore_check_gpu(tracking_semaphore)); - uvm_spin_lock(&tracking_semaphore->lock); + if (tracking_semaphore_uses_mutex(tracking_semaphore)) + uvm_mutex_lock(&tracking_semaphore->m_lock); + else + uvm_spin_lock(&tracking_semaphore->s_lock); completed = update_completed_value_locked(tracking_semaphore); - uvm_spin_unlock(&tracking_semaphore->lock); + if (tracking_semaphore_uses_mutex(tracking_semaphore)) + uvm_mutex_unlock(&tracking_semaphore->m_lock); + else + uvm_spin_unlock(&tracking_semaphore->s_lock); return completed; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.h b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.h index 50931f840e..1ba892ae29 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.h +++ b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.h @@ -47,6 +47,16 @@ struct uvm_gpu_semaphore_struct // Pointer to the memory location NvU32 *payload; + struct { + NvU16 index; + NvU32 cached_payload; + uvm_rm_mem_t *encrypted_payload; + uvm_rm_mem_t *notifier; + uvm_rm_mem_t *auth_tag; + UvmCslIv *ivs; + NvU32 last_pushed_notifier; + NvU32 last_observed_notifier; + } conf_computing; }; // A primitive used for tracking progress of the GPU @@ -67,7 +77,10 @@ struct uvm_gpu_tracking_semaphore_struct atomic64_t completed_value; // Lock protecting updates to the completed_value - uvm_spinlock_t lock; + union { + uvm_spinlock_t s_lock; + uvm_mutex_t m_lock; + }; // Last queued value // All accesses to the queued value should be handled by the user of the GPU @@ -78,6 +91,12 @@ struct uvm_gpu_tracking_semaphore_struct // Create a semaphore pool for a GPU. NV_STATUS uvm_gpu_semaphore_pool_create(uvm_gpu_t *gpu, uvm_gpu_semaphore_pool_t **pool_out); +// When the Confidential Computing feature is enabled, pools associated with +// secure CE channels are allocated in the CPR of vidmem and as such have +// all the associated access restrictions. Because of this, they're called +// secure pools and secure semaphores are allocated out of said secure pools. +NV_STATUS uvm_gpu_semaphore_secure_pool_create(uvm_gpu_t *gpu, uvm_gpu_semaphore_pool_t **pool_out); + // Destroy a semaphore pool // Locking: // - Global lock needs to be held in read mode (for unmapping from all GPUs) @@ -90,6 +109,9 @@ void uvm_gpu_semaphore_pool_destroy(uvm_gpu_semaphore_pool_t *pool); // Allocate a semaphore from the pool. // The semaphore will be mapped on all GPUs currently registered with the UVM // driver, and on all new GPUs which will be registered in the future. +// Unless the Confidential Computing feature is enabled and the pool is a +// secure pool. In this case, it is only mapped to the GPU that holds the +// allocation. // The mappings are added to UVM's internal address space, and (in SR-IOV heavy) // to the proxy address space. // diff --git a/kernel-open/nvidia-uvm/uvm_hal.c b/kernel-open/nvidia-uvm/uvm_hal.c index 7ef0e84974..20ace7e24a 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.c +++ b/kernel-open/nvidia-uvm/uvm_hal.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -53,6 +53,7 @@ MODULE_PARM_DESC(uvm_downgrade_force_membar_sys, "Force all TLB invalidation dow #define ARCH_OP_COUNT (sizeof(uvm_arch_hal_t) / sizeof(void *)) #define FAULT_BUFFER_OP_COUNT (sizeof(uvm_fault_buffer_hal_t) / sizeof(void *)) #define ACCESS_COUNTER_BUFFER_OP_COUNT (sizeof(uvm_access_counter_buffer_hal_t) / sizeof(void *)) +#define SEC2_OP_COUNT (sizeof(uvm_sec2_hal_t) / sizeof(void *)) // Table for copy engine functions. // Each entry is associated with a copy engine class through the 'class' field. @@ -73,6 +74,7 @@ static uvm_hal_class_ops_t ce_table[] = .offset_in_out = uvm_hal_maxwell_ce_offset_in_out, .phys_mode = uvm_hal_maxwell_ce_phys_mode, .plc_mode = uvm_hal_maxwell_ce_plc_mode, + .memcopy_copy_type = uvm_hal_maxwell_ce_memcopy_copy_type, .memcopy_is_valid = uvm_hal_ce_memcopy_is_valid_stub, .memcopy_patch_src = uvm_hal_ce_memcopy_patch_src_stub, .memcopy = uvm_hal_maxwell_ce_memcopy, @@ -82,6 +84,8 @@ static uvm_hal_class_ops_t ce_table[] = .memset_4 = uvm_hal_maxwell_ce_memset_4, .memset_8 = uvm_hal_maxwell_ce_memset_8, .memset_v_4 = uvm_hal_maxwell_ce_memset_v_4, + .encrypt = uvm_hal_maxwell_ce_encrypt_unsupported, + .decrypt = uvm_hal_maxwell_ce_decrypt_unsupported, } }, { @@ -149,11 +153,14 @@ static uvm_hal_class_ops_t ce_table[] = .semaphore_reduction_inc = uvm_hal_hopper_ce_semaphore_reduction_inc, .offset_out = uvm_hal_hopper_ce_offset_out, .offset_in_out = uvm_hal_hopper_ce_offset_in_out, + .memcopy_copy_type = uvm_hal_hopper_ce_memcopy_copy_type, .memset_1 = uvm_hal_hopper_ce_memset_1, .memset_4 = uvm_hal_hopper_ce_memset_4, .memset_8 = uvm_hal_hopper_ce_memset_8, .memcopy_is_valid = uvm_hal_hopper_ce_memcopy_is_valid, .memset_is_valid = uvm_hal_hopper_ce_memset_is_valid, + .encrypt = uvm_hal_hopper_ce_encrypt, + .decrypt = uvm_hal_hopper_ce_decrypt, }, }, }; @@ -371,6 +378,7 @@ static uvm_hal_class_ops_t fault_buffer_table[] = .entry_clear_valid = uvm_hal_maxwell_fault_buffer_entry_clear_valid_unsupported, .entry_size = uvm_hal_maxwell_fault_buffer_entry_size_unsupported, .parse_non_replayable_entry = uvm_hal_maxwell_fault_buffer_parse_non_replayable_entry_unsupported, + .get_fault_type = uvm_hal_maxwell_fault_buffer_get_fault_type_unsupported, } }, { @@ -392,6 +400,7 @@ static uvm_hal_class_ops_t fault_buffer_table[] = .entry_is_valid = uvm_hal_pascal_fault_buffer_entry_is_valid, .entry_clear_valid = uvm_hal_pascal_fault_buffer_entry_clear_valid, .entry_size = uvm_hal_pascal_fault_buffer_entry_size, + .get_fault_type = uvm_hal_pascal_fault_buffer_get_fault_type, } }, { @@ -404,6 +413,7 @@ static uvm_hal_class_ops_t fault_buffer_table[] = .get_ve_id = uvm_hal_volta_fault_buffer_get_ve_id, .parse_entry = uvm_hal_volta_fault_buffer_parse_entry, .parse_non_replayable_entry = uvm_hal_volta_fault_buffer_parse_non_replayable_entry, + .get_fault_type = uvm_hal_volta_fault_buffer_get_fault_type, } }, { @@ -495,6 +505,59 @@ static uvm_hal_class_ops_t access_counter_buffer_table[] = }, }; +static uvm_hal_class_ops_t sec2_table[] = +{ + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GM000, + .u.sec2_ops = { + .init = uvm_hal_maxwell_sec2_init_noop, + .decrypt = uvm_hal_maxwell_sec2_decrypt_unsupported, + .semaphore_release = uvm_hal_maxwell_sec2_semaphore_release_unsupported, + .semaphore_timestamp = uvm_hal_maxwell_sec2_semaphore_timestamp_unsupported, + } + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GM200, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GM000, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GP100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GM200, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GV100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GP100, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GV100, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100, + .u.sec2_ops = {} + }, + { + .id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100, + .parent_id = NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100, + .u.sec2_ops = { + .init = uvm_hal_hopper_sec2_init, + .semaphore_release = uvm_hal_hopper_sec2_semaphore_release, + .semaphore_timestamp = uvm_hal_hopper_sec2_semaphore_timestamp_unsupported, + .decrypt = uvm_hal_hopper_sec2_decrypt, + } + }, +}; + static inline uvm_hal_class_ops_t *ops_find_by_id(uvm_hal_class_ops_t *table, NvU32 row_count, NvU32 id) { NvLength i; @@ -598,6 +661,15 @@ NV_STATUS uvm_hal_init_table(void) return status; } + status = ops_init_from_parent(sec2_table, + ARRAY_SIZE(sec2_table), + SEC2_OP_COUNT, + offsetof(uvm_hal_class_ops_t, u.sec2_ops)); + if (status != NV_OK) { + UVM_ERR_PRINT("ops_init_from_parent(sec2_table) failed: %s\n", nvstatusToString(status)); + return status; + } + return NV_OK; } @@ -648,6 +720,14 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counter_buffer_hal = &class_ops->u.access_counter_buffer_ops; + class_ops = ops_find_by_id(sec2_table, ARRAY_SIZE(sec2_table), gpu_info->gpuArch); + if (class_ops == NULL) { + UVM_ERR_PRINT("SEC2 HAL not found, GPU %s, arch: 0x%X\n", parent_gpu->name, gpu_info->gpuArch); + return NV_ERR_INVALID_CLASS; + } + + parent_gpu->sec2_hal = &class_ops->u.sec2_ops; + return NV_OK; } @@ -658,6 +738,9 @@ static void hal_override_properties(uvm_parent_gpu_t *parent_gpu) // TODO: Bug 200692962: Add support for access counters in vGPU if (parent_gpu->virt_mode != UVM_VIRT_MODE_NONE) parent_gpu->access_counters_supported = false; + // Access counters are not supported in CC. + else if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + parent_gpu->access_counters_supported = false; } void uvm_hal_init_properties(uvm_parent_gpu_t *parent_gpu) @@ -711,7 +794,7 @@ uvm_membar_t uvm_hal_downgrade_membar_type(uvm_gpu_t *gpu, bool is_local_vidmem) // memory, including those from other processors like the CPU or peer GPUs, // must come through this GPU's L2. In all current architectures, MEMBAR_GPU // is sufficient to resolve ordering at the L2 level. - if (is_local_vidmem && !gpu->parent->numa_info.enabled && !uvm_downgrade_force_membar_sys) + if (is_local_vidmem && !uvm_gpu_is_coherent(gpu->parent) && !uvm_downgrade_force_membar_sys) return UVM_MEMBAR_GPU; // If the mapped memory was remote, or if a coherence protocol can cache @@ -895,7 +978,7 @@ void uvm_hal_ce_memcopy_patch_src_stub(uvm_push_t *push, uvm_gpu_address_t *src) { } -bool uvm_hal_ce_memset_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) +bool uvm_hal_ce_memset_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t num_elements, size_t element_size) { return true; } diff --git a/kernel-open/nvidia-uvm/uvm_hal.h b/kernel-open/nvidia-uvm/uvm_hal.h index 75cbb38d5c..3ad4fb736f 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.h +++ b/kernel-open/nvidia-uvm/uvm_hal.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -40,6 +40,8 @@ typedef void (*uvm_hal_init_t)(uvm_push_t *push); void uvm_hal_maxwell_ce_init(uvm_push_t *push); void uvm_hal_maxwell_host_init_noop(uvm_push_t *push); void uvm_hal_pascal_host_init(uvm_push_t *push); +void uvm_hal_maxwell_sec2_init_noop(uvm_push_t *push); +void uvm_hal_hopper_sec2_init(uvm_push_t *push); // Host method validation typedef bool (*uvm_hal_host_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); @@ -207,9 +209,11 @@ void uvm_hal_hopper_host_tlb_invalidate_test(uvm_push_t *push, typedef void (*uvm_hal_semaphore_release_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_maxwell_sec2_semaphore_release_unsupported(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_volta_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_turing_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_hopper_sec2_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); @@ -228,15 +232,30 @@ void uvm_hal_maxwell_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_volta_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_hopper_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); +void uvm_hal_maxwell_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va); +void uvm_hal_hopper_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va); + typedef void (*uvm_hal_semaphore_acquire_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_turing_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); -typedef void (*uvm_hal_host_set_gpfifo_entry_t)(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); -void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); -void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); -void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length); +typedef void (*uvm_hal_host_set_gpfifo_entry_t)(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag); +void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag); +void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag); +void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag); typedef void (*uvm_hal_host_set_gpfifo_noop_t)(NvU64 *fifo_entry); void uvm_hal_maxwell_host_set_gpfifo_noop(NvU64 *fifo_entry); @@ -273,6 +292,10 @@ typedef NvU32 (*uvm_hal_ce_plc_mode_t)(void); NvU32 uvm_hal_maxwell_ce_plc_mode(void); NvU32 uvm_hal_ampere_ce_plc_mode_c7b5(void); +typedef NvU32 (*uvm_hal_ce_memcopy_type_t)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +NvU32 uvm_hal_maxwell_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +NvU32 uvm_hal_hopper_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); + // CE method validation typedef bool (*uvm_hal_ce_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); bool uvm_hal_ampere_ce_method_is_valid_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data); @@ -309,10 +332,19 @@ void uvm_hal_maxwell_ce_memcopy_v_to_v(uvm_push_t *push, NvU64 dst, NvU64 src, s // The validation happens at the start of the memset (uvm_hal_memset_*_t) // execution. Use uvm_hal_ce_memset_is_valid_stub to skip the validation for // a given architecture. -typedef bool (*uvm_hal_ce_memset_is_valid)(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); -bool uvm_hal_ce_memset_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); -bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); -bool uvm_hal_hopper_ce_memset_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); +typedef bool (*uvm_hal_ce_memset_is_valid)(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size); +bool uvm_hal_ce_memset_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t num_elements, size_t element_size); +bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size); +bool uvm_hal_hopper_ce_memset_is_valid(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size); // Memset size bytes at dst to a given N-byte input value. // @@ -342,6 +374,54 @@ void uvm_hal_hopper_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 va void uvm_hal_hopper_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size); void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); +// Encrypts the contents of the source buffer into the destination buffer, up to +// the given size. The authentication tag of the encrypted contents is written +// to auth_tag, so it can be verified later on by a decrypt operation. +// +// The addressing modes of the destination and authentication tag addresses +// should match. If the addressing mode is physical, then the address apertures +// should also match. +typedef void (*uvm_hal_ce_encrypt_t)(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); + +// Decrypts the contents of the source buffer into the destination buffer, up to +// the given size. The method also verifies the integrity of the encrypted +// buffer by calculating its authentication tag, and comparing it with the one +// provided as argument. +// +// The addressing modes of the source and authentication tag addresses should +// match. If the addressing mode is physical, then the address apertures should +// also match. +typedef void (*uvm_hal_ce_decrypt_t)(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); + +void uvm_hal_maxwell_ce_encrypt_unsupported(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); +void uvm_hal_maxwell_ce_decrypt_unsupported(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); +void uvm_hal_hopper_ce_encrypt(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); +void uvm_hal_hopper_ce_decrypt(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag); + // Increments the semaphore by 1, or resets to 0 if the incremented value would // exceed the payload. // @@ -414,6 +494,7 @@ typedef bool (*uvm_hal_fault_buffer_entry_is_valid_t)(uvm_parent_gpu_t *parent_g typedef void (*uvm_hal_fault_buffer_entry_clear_valid_t)(uvm_parent_gpu_t *parent_gpu, NvU32 index); typedef NvU32 (*uvm_hal_fault_buffer_entry_size_t)(uvm_parent_gpu_t *parent_gpu); typedef void (*uvm_hal_fault_buffer_replay_t)(uvm_push_t *push, uvm_fault_replay_type_t type); +typedef uvm_fault_type_t (*uvm_hal_fault_buffer_get_fault_type_t)(const NvU32 *fault_entry); typedef void (*uvm_hal_fault_cancel_global_t)(uvm_push_t *push, uvm_gpu_phys_address_t instance_ptr); typedef void (*uvm_hal_fault_cancel_targeted_t)(uvm_push_t *push, uvm_gpu_phys_address_t instance_ptr, @@ -430,6 +511,8 @@ NvU8 uvm_hal_maxwell_fault_buffer_get_ve_id_unsupported(NvU16 mmu_engine_id, uvm void uvm_hal_maxwell_fault_buffer_parse_entry_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index, uvm_fault_buffer_entry_t *buffer_entry); +uvm_fault_type_t uvm_hal_maxwell_fault_buffer_get_fault_type_unsupported(const NvU32 *fault_entry); + void uvm_hal_pascal_enable_replayable_faults(uvm_parent_gpu_t *parent_gpu); void uvm_hal_pascal_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu); void uvm_hal_pascal_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get); @@ -439,6 +522,8 @@ void uvm_hal_pascal_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 i void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, NvU32 index, uvm_fault_buffer_entry_t *buffer_entry); +uvm_fault_type_t uvm_hal_pascal_fault_buffer_get_fault_type(const NvU32 *fault_entry); + NvU32 uvm_hal_volta_fault_buffer_read_put(uvm_parent_gpu_t *parent_gpu); NvU32 uvm_hal_volta_fault_buffer_read_get(uvm_parent_gpu_t *parent_gpu); void uvm_hal_volta_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index); @@ -446,6 +531,8 @@ NvU8 uvm_hal_volta_fault_buffer_get_ve_id(NvU16 mmu_engine_id, uvm_mmu_engine_ty void uvm_hal_volta_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, NvU32 index, uvm_fault_buffer_entry_t *buffer_entry); +uvm_fault_type_t uvm_hal_volta_fault_buffer_get_fault_type(const NvU32 *fault_entry); + void uvm_hal_turing_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu); void uvm_hal_turing_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get); NvU8 uvm_hal_hopper_fault_buffer_get_ve_id(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type); @@ -586,6 +673,28 @@ void uvm_hal_volta_access_counter_clear_targeted(uvm_push_t *push, void uvm_hal_turing_disable_access_counter_notifications(uvm_parent_gpu_t *parent_gpu); void uvm_hal_turing_clear_access_counter_notifications(uvm_parent_gpu_t *parent_gpu, NvU32 get); +// The source and destination addresses must be 16-byte aligned. Note that the +// best performance is achieved with 256-byte alignment. The decrypt size must +// be larger than 0, and a multiple of 4 bytes. +// +// The authentication tag address must also be 16-byte aligned. +// The authentication tag buffer size is UVM_CONF_COMPUTING_AUTH_TAG_SIZE bytes +// defined in uvm_conf_computing.h. +// +// Decrypts the src buffer into the dst buffer of the given size. +// The method also verifies integrity of the src buffer by calculating its +// authentication tag and comparing it with the provided one. +// +// Note: SEC2 does not support encryption. +typedef void (*uvm_hal_sec2_decrypt_t)(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, NvU32 size, NvU64 auth_tag_va); + +void uvm_hal_maxwell_sec2_decrypt_unsupported(uvm_push_t *push, + NvU64 dst_va, + NvU64 src_va, + NvU32 size, + NvU64 auth_tag_va); +void uvm_hal_hopper_sec2_decrypt(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, NvU32 size, NvU64 auth_tag_va); + struct uvm_host_hal_struct { uvm_hal_init_t init; @@ -629,6 +738,7 @@ struct uvm_ce_hal_struct uvm_hal_ce_offset_in_out_t offset_in_out; uvm_hal_ce_phys_mode_t phys_mode; uvm_hal_ce_plc_mode_t plc_mode; + uvm_hal_ce_memcopy_type_t memcopy_copy_type; uvm_hal_ce_memcopy_is_valid memcopy_is_valid; uvm_hal_ce_memcopy_patch_src memcopy_patch_src; uvm_hal_memcopy_t memcopy; @@ -639,6 +749,8 @@ struct uvm_ce_hal_struct uvm_hal_memset_8_t memset_8; uvm_hal_memset_v_4_t memset_v_4; uvm_hal_semaphore_reduction_inc_t semaphore_reduction_inc; + uvm_hal_ce_encrypt_t encrypt; + uvm_hal_ce_decrypt_t decrypt; }; struct uvm_arch_hal_struct @@ -665,6 +777,7 @@ struct uvm_fault_buffer_hal_struct uvm_hal_fault_buffer_entry_clear_valid_t entry_clear_valid; uvm_hal_fault_buffer_entry_size_t entry_size; uvm_hal_fault_buffer_parse_non_replayable_entry_t parse_non_replayable_entry; + uvm_hal_fault_buffer_get_fault_type_t get_fault_type; }; struct uvm_access_counter_buffer_hal_struct @@ -678,6 +791,14 @@ struct uvm_access_counter_buffer_hal_struct uvm_hal_access_counter_buffer_entry_size_t entry_size; }; +struct uvm_sec2_hal_struct +{ + uvm_hal_init_t init; + uvm_hal_sec2_decrypt_t decrypt; + uvm_hal_semaphore_release_t semaphore_release; + uvm_hal_semaphore_timestamp_t semaphore_timestamp; +}; + typedef struct { // id is either a hardware class or GPU architecture @@ -700,6 +821,8 @@ typedef struct // access_counter_buffer_ops: id is an architecture uvm_access_counter_buffer_hal_t access_counter_buffer_ops; + // sec2_ops: id is an architecture + uvm_sec2_hal_t sec2_ops; } u; } uvm_hal_class_ops_t; diff --git a/kernel-open/nvidia-uvm/uvm_hal_types.h b/kernel-open/nvidia-uvm/uvm_hal_types.h index 25497cf250..eace5e7c5b 100644 --- a/kernel-open/nvidia-uvm/uvm_hal_types.h +++ b/kernel-open/nvidia-uvm/uvm_hal_types.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -111,6 +111,11 @@ typedef struct // Whether the address is virtual bool is_virtual; + + // Whether the address resides in a non-protected memory region when the + // Confidential Computing feature is enabled. Default is protected. + // Ignored if the feature is disabled and should not be used. + bool is_unprotected; } uvm_gpu_address_t; // Create a virtual GPU address @@ -258,8 +263,8 @@ typedef enum UVM_FAULT_CANCEL_VA_MODE_COUNT, } uvm_fault_cancel_va_mode_t; -// Types of faults that can show up in the fault buffer. Non-UVM related faults are grouped in FATAL category -// since we don't care about the specific type +// Types of faults that can show up in the fault buffer. Non-UVM related faults +// are grouped in FATAL category since we don't care about the specific type. typedef enum { UVM_FAULT_TYPE_INVALID_PDE = 0, @@ -272,7 +277,8 @@ typedef enum // READ to WRITE-ONLY (ATS) UVM_FAULT_TYPE_READ, - // The next values are considered fatal and are not handled by the UVM driver + // The next values are considered fatal and are not handled by the UVM + // driver UVM_FAULT_TYPE_FATAL, // Values required for tools @@ -311,10 +317,24 @@ typedef enum UVM_MMU_ENGINE_TYPE_COUNT, } uvm_mmu_engine_type_t; +typedef enum +{ + // Allow entry to be fetched before the previous entry finishes ESCHED + // execution. + UVM_GPFIFO_SYNC_PROCEED = 0, + + // Fetch of this entry has to wait until the previous entry has finished + // executing by ESCHED. + // For a complete engine sync the previous entry needs to include + // WAIT_FOR_IDLE command or other engine synchronization. + UVM_GPFIFO_SYNC_WAIT, +} uvm_gpfifo_sync_t; + const char *uvm_mmu_engine_type_string(uvm_mmu_engine_type_t mmu_engine_type); -// HW unit that triggered the fault. We include the fields required for fault cancelling. Including more information -// might be useful for performance heuristics in the future +// HW unit that triggered the fault. We include the fields required for fault +// cancelling. Including more information might be useful for performance +// heuristics in the future. typedef struct { uvm_fault_client_type_t client_type : order_base_2(UVM_FAULT_CLIENT_TYPE_COUNT) + 1; @@ -429,7 +449,8 @@ typedef enum // Completes when all fault replays are in-flight UVM_FAULT_REPLAY_TYPE_START = 0, - // Completes when all faulting accesses have been correctly translated or faulted again + // Completes when all faulting accesses have been correctly translated or + // faulted again UVM_FAULT_REPLAY_TYPE_START_ACK_ALL, UVM_FAULT_REPLAY_TYPE_MAX @@ -467,18 +488,18 @@ struct uvm_access_counter_buffer_entry_struct { struct { - // Instance pointer of one of the channels in the TSG that triggered the - // notification + // Instance pointer of one of the channels in the TSG that triggered + // the notification. uvm_gpu_phys_address_t instance_ptr; uvm_mmu_engine_type_t mmu_engine_type; NvU32 mmu_engine_id; - // Identifier of the subcontext that performed the memory accesses that - // triggered the notification. This value, combined with the instance_ptr, - // is needed to obtain the GPU VA space of the process that triggered the - // notification. + // Identifier of the subcontext that performed the memory accesses + // that triggered the notification. This value, combined with the + // instance_ptr, is needed to obtain the GPU VA space of the process + // that triggered the notification. NvU32 ve_id; // VA space for the address that triggered the notification @@ -524,8 +545,8 @@ static uvm_prot_t uvm_fault_access_type_to_prot(uvm_fault_access_type_t access_t return UVM_PROT_READ_WRITE; default: - // Prefetch faults, if not ignored, are handled like read faults and require - // a mapping with, at least, READ_ONLY access permission + // Prefetch faults, if not ignored, are handled like read faults and + // requirea mapping with, at least, READ_ONLY access permission. return UVM_PROT_READ_ONLY; } } diff --git a/kernel-open/nvidia-uvm/uvm_hmm.c b/kernel-open/nvidia-uvm/uvm_hmm.c index 05fd2d47a8..8b094b5100 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.c +++ b/kernel-open/nvidia-uvm/uvm_hmm.c @@ -23,31 +23,29 @@ #include "uvm_hmm.h" -// TODO: Bug 1750144: Enable HMM by default once the feature is formally -// enabled for production use. - -// Support for HMM ( https://docs.kernel.org/mm/hmm.html ). HMM features are -// disabled in this driver because they are still in development. In order to -// experiment with the early, "alpha" version of HMM features in this driver, -// set "uvm_disable_hmm=0" on the kernel or module loading command line. -// However, again: -// -// HMM FEATURES IN THIS DRIVER ARE UNSUPPORTED BECAUSE THEY ARE NOT READY. -// -// ENABLING HMM IN THIS DRIVER MAY CAUSE YOUR KERNEL TO CRASH, CORRUPT DATA, -// OR OTHERWISE MISBEHAVE. DO NOT ENABLE HMM HERE UNLESS YOU ARE FULLY -// PREPARED TO DEAL WITH THE INEVITABLE BUGS AND LIMITATIONS IN THIS ALPHA -// FEATURE. -// +// Support for HMM ( https://docs.kernel.org/mm/hmm.html ): + +#ifdef NVCPU_X86_64 +static bool uvm_disable_hmm = false; +MODULE_PARM_DESC(uvm_disable_hmm, + "Force-disable HMM functionality in the UVM driver. " + "Default: false (HMM is enabled if possible). " + "However, even with uvm_disable_hmm=false, HMM will not be " + "enabled if is not supported in this driver build " + "configuration, or if ATS settings conflict with HMM."); +#else +// So far, we've only tested HMM on x86_64, so disable it by default everywhere +// else. static bool uvm_disable_hmm = true; -module_param(uvm_disable_hmm, bool, 0444); MODULE_PARM_DESC(uvm_disable_hmm, "Force-disable HMM functionality in the UVM driver. " - "Default: true. Setting to false potentially enables HMM. USE " - "AT YOUR OWN RISK: HMM FEATURES ARE NOT READY IN THIS DRIVER. " - "Also, even with uvm_disable_hmm=false, HMM will not be " + "Default: true (HMM is not enabled on this CPU architecture). " + "However, even with uvm_disable_hmm=false, HMM will not be " "enabled if is not supported in this driver build " "configuration, or if ATS settings conflict with HMM."); +#endif + +module_param(uvm_disable_hmm, bool, 0444); #if UVM_IS_CONFIG_HMM() @@ -73,12 +71,9 @@ MODULE_PARM_DESC(uvm_disable_hmm, #include "uvm_va_policy.h" #include "uvm_tools.h" -static NV_STATUS hmm_va_block_migrate_locked(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - uvm_make_resident_cause_t cause); +static NV_STATUS gpu_chunk_add(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page); typedef struct { @@ -138,15 +133,15 @@ NV_STATUS uvm_hmm_va_space_initialize(uvm_va_space_t *va_space) struct mm_struct *mm = va_space->va_space_mm.mm; int ret; - if (!uvm_hmm_is_enabled(va_space) || !mm) + if (!uvm_hmm_is_enabled(va_space)) return NV_OK; - if (va_space->initialization_flags & UVM_INIT_FLAGS_DISABLE_HMM) - return NV_ERR_INVALID_STATE; - uvm_assert_mmap_lock_locked_write(mm); uvm_assert_rwsem_locked_write(&va_space->lock); + uvm_range_tree_init(&hmm_va_space->blocks); + uvm_mutex_init(&hmm_va_space->blocks_lock, UVM_LOCK_ORDER_LEAF); + // Initialize MMU interval notifiers for this process. // This allows mmu_interval_notifier_insert() to be called without holding // the mmap_lock for write. @@ -157,9 +152,6 @@ NV_STATUS uvm_hmm_va_space_initialize(uvm_va_space_t *va_space) if (ret) return errno_to_nv_status(ret); - uvm_range_tree_init(&hmm_va_space->blocks); - uvm_mutex_init(&hmm_va_space->blocks_lock, UVM_LOCK_ORDER_LEAF); - return NV_OK; } @@ -222,11 +214,6 @@ void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_ hmm_va_block_unregister_gpu(va_block, gpu, mm); } - - // By now, all GPU VA spaces are removed and all HMM pages local to the - // GPU have been migrated to the CPU. Check for any orphaned pages that - // Linux might still have a reference to. - uvm_pmm_gpu_free_orphan_pages(&gpu->pmm); } static void hmm_va_block_remove_gpu_va_space(uvm_va_block_t *va_block, @@ -293,9 +280,14 @@ static bool hmm_invalidate(uvm_va_block_t *va_block, if (!mmu_notifier_range_blockable(range)) return false; - // Ignore invalidation callbacks when migrating pages since unmapping the - // source pages is handled as part of the migration process. - if (uvm_context->ignore_hmm_invalidate_va_block == va_block) + // We only ignore invalidations in this context whilst holding the + // va_block lock. This prevents deadlock when try_to_migrate() + // calls the notifier, but holding the lock prevents other threads + // invalidating PTEs so we can safely assume the results of + // migrate_vma_setup() are correct. + if (uvm_context->ignore_hmm_invalidate_va_block == va_block || + ((range->event == MMU_NOTIFY_MIGRATE || range->event == MMU_NOTIFY_EXCLUSIVE) && + range->owner == &g_uvm_global)) return true; va_block_context = uvm_va_block_context_alloc(mm); @@ -304,9 +296,9 @@ static bool hmm_invalidate(uvm_va_block_t *va_block, uvm_mutex_lock(&va_block->lock); - // Ignore this invalidation callback if the block is dead. - if (uvm_va_block_is_dead(va_block)) - goto unlock; + // mmu_interval_notifier_remove() is always called before marking a + // va_block as dead so this va_block has to be alive. + UVM_ASSERT(!uvm_va_block_is_dead(va_block)); // Note: unmap_vmas() does MMU_NOTIFY_UNMAP [0, 0xffffffffffffffff] // Also note that hmm_invalidate() can be called when a new va_block is not @@ -323,6 +315,11 @@ static bool hmm_invalidate(uvm_va_block_t *va_block, if (start > end) goto unlock; + // These will be equal if no other thread causes an invalidation + // whilst the va_block lock was dropped. + uvm_context->hmm_invalidate_seqnum++; + va_block->hmm.changed++; + mmu_interval_set_seq(mni, cur_seq); region = uvm_va_block_region_from_start_end(va_block, start, end); @@ -399,82 +396,20 @@ NV_STATUS uvm_hmm_va_block_find(uvm_va_space_t *va_space, return NV_OK; } -NV_STATUS uvm_hmm_va_block_cpu_find(uvm_va_space_t *va_space, - uvm_service_block_context_t *service_context, - struct vm_fault *vmf, - uvm_va_block_t **va_block_ptr) +static int migrate_vma_setup_locked(struct migrate_vma *args, uvm_va_block_t *va_block) { uvm_thread_context_t *uvm_context = uvm_thread_context(); - uvm_range_tree_node_t *node; - NvU64 fault_addr = vmf->address; - struct vm_area_struct *vma = vmf->vma; - uvm_va_block_t *va_block; - uvm_page_index_t page_index; - struct migrate_vma *args; int ret; - UVM_ASSERT(uvm_hmm_is_enabled(va_space)); - uvm_assert_rwsem_locked(&va_space->lock); - UVM_ASSERT(fault_addr >= vma->vm_start && fault_addr < vma->vm_end); - - // Note that we must find a va_block for the faulting address because - // the block had to be migrated to the GPU and a device private PTE - // inserted into the CPU page tables in order for migrate_to_ram() to be - // called. Not finding it means the va_block was destroyed while the - // Linux kernel still has a reference to the device private page which - // can only be an error. - uvm_mutex_lock(&va_space->hmm.blocks_lock); - node = uvm_range_tree_find(&va_space->hmm.blocks, fault_addr); - uvm_mutex_unlock(&va_space->hmm.blocks_lock); - - if (!node) - return NV_ERR_INVALID_ADDRESS; - - va_block = hmm_va_block_from_node(node); - page_index = uvm_va_block_cpu_page_index(va_block, fault_addr); - - // In order to reduce live locks when multiple CPU threads fault on the - // same device private PTE, call migrate_vma_setup() now before acquiring - // the va_block lock. Otherwise, each thread locks the block, sees the - // wrong reference count, unlocks the va_block, and then the next thread - // does the same thing. Winning the race here means the migration PTE is - // inserted and the other threads are more likely to wait for the migration - // PTE to be removed. TODO: Bug 3949334: migrate_vma_setup() is called - // without the va_block lock. - args = &service_context->block_context.hmm.migrate_vma_args; - args->vma = vma; - args->src = service_context->block_context.hmm.src_pfns + page_index; - args->dst = service_context->block_context.hmm.dst_pfns + page_index; - args->start = fault_addr; - args->end = fault_addr + PAGE_SIZE; - args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; - args->pgmap_owner = &g_uvm_global; - args->fault_page = vmf->page; - - // Prevent MMU invalidation callbacks from deadlocking in this thread. + // It's only safe to ignore invalidations whilst doing a migration + // and holding the va_block lock. + uvm_assert_mutex_locked(&va_block->lock); uvm_context->ignore_hmm_invalidate_va_block = va_block; - ret = migrate_vma_setup(args); - UVM_ASSERT(!ret); + // We shouldn't be generating any more invalidations now. uvm_context->ignore_hmm_invalidate_va_block = NULL; - - if (!(args->src[0] & MIGRATE_PFN_MIGRATE)) - return NV_ERR_BUSY_RETRY; - - service_context->block_context.hmm.vma = vma; - - *va_block_ptr = va_block; - - return NV_OK; -} - -void uvm_hmm_cpu_fault_finish(uvm_service_block_context_t *service_context) -{ - // This is here to catch retries before uvm_hmm_service_locked() is called. - // If migrate_vma_finalize() has already been called, don't call it again. - if (service_context->block_context.hmm.migrate_vma_args.vma) - migrate_vma_finalize(&service_context->block_context.hmm.migrate_vma_args); + return ret; } static bool uvm_hmm_vma_is_valid(struct vm_area_struct *vma, @@ -482,16 +417,30 @@ static bool uvm_hmm_vma_is_valid(struct vm_area_struct *vma, bool allow_unreadable_vma) { // UVM doesn't support userfaultfd. hmm_range_fault() doesn't support - // VM_IO, VM_PFNMAP, or VM_MIXEDMAP VMAs. It also doesn't support - // VMAs without VM_READ but we allow those VMAs to have policy set on - // them. + // VM_IO or VM_PFNMAP VMAs. It also doesn't support VMAs without VM_READ + // but we allow those VMAs to have policy set on them. + // migrate_vma_setup() doesn't support VM_SPECIAL VMAs but that is handled + // by uvm_hmm_must_use_sysmem() forcing residency to the CPU. return vma && addr >= vma->vm_start && !userfaultfd_armed(vma) && - !(vma->vm_flags & (VM_IO | VM_PFNMAP | VM_MIXEDMAP)) && + !(vma->vm_flags & (VM_IO | VM_PFNMAP)) && + !uvm_vma_is_managed(vma) && (allow_unreadable_vma || (vma->vm_flags & VM_READ)); } +static void hmm_va_block_init(uvm_va_block_t *va_block, + uvm_va_space_t *va_space, + NvU64 start, + NvU64 end) +{ + va_block->hmm.va_space = va_space; + va_block->hmm.node.start = start; + va_block->hmm.node.end = end; + uvm_range_tree_init(&va_block->hmm.va_policy_tree); + uvm_mutex_init(&va_block->hmm.migrate_lock, UVM_LOCK_ORDER_VA_BLOCK_MIGRATE); +} + static NV_STATUS hmm_va_block_find_create(uvm_va_space_t *va_space, NvU64 addr, bool allow_unreadable_vma, @@ -551,12 +500,7 @@ static NV_STATUS hmm_va_block_find_create(uvm_va_space_t *va_space, if (status != NV_OK) goto err_unlock; - va_block->hmm.node.start = start; - va_block->hmm.node.end = end; - va_block->hmm.va_space = va_space; - uvm_range_tree_init(&va_block->hmm.va_policy_tree); - init_waitqueue_head(&va_block->hmm.atomic_waitq); - uvm_page_mask_zero(&va_block->hmm.atomic_busy); + hmm_va_block_init(va_block, va_space, start, end); ret = mmu_interval_notifier_insert(&va_block->hmm.notifier, mm, @@ -632,6 +576,30 @@ bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, return true; } +void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context) +{ + // TODO: Bug 4050579: Remove this when swap cached pages can be migrated. + service_context->block_context.hmm.swap_cached = false; +} + +NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block) +{ + if (uvm_mutex_trylock(&va_block->hmm.migrate_lock)) + return NV_OK; + + return NV_ERR_BUSY_RETRY; +} + +void uvm_hmm_migrate_begin_wait(uvm_va_block_t *va_block) +{ + uvm_mutex_lock(&va_block->hmm.migrate_lock); +} + +void uvm_hmm_migrate_finish(uvm_va_block_t *va_block) +{ + uvm_mutex_unlock(&va_block->hmm.migrate_lock); +} + // Migrate the given range [start end] within a va_block to dest_id. static NV_STATUS hmm_migrate_range(uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, @@ -647,6 +615,7 @@ static NV_STATUS hmm_migrate_range(uvm_va_block_t *va_block, const uvm_va_policy_t *policy; NV_STATUS status = NV_OK; + uvm_hmm_migrate_begin_wait(va_block); uvm_mutex_lock(&va_block->lock); uvm_for_each_va_policy_in(policy, va_block, start, end, node, region) { @@ -670,10 +639,53 @@ static NV_STATUS hmm_migrate_range(uvm_va_block_t *va_block, } uvm_mutex_unlock(&va_block->lock); + uvm_hmm_migrate_finish(va_block); return status; } +void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space) +{ + // We can't use uvm_va_space_mm_retain(), because the va_space_mm + // should already be dead by now. + struct mm_struct *mm = va_space->va_space_mm.mm; + uvm_hmm_va_space_t *hmm_va_space = &va_space->hmm; + uvm_range_tree_node_t *node, *next; + uvm_va_block_t *va_block; + uvm_va_block_context_t *block_context; + + uvm_down_read_mmap_lock(mm); + uvm_va_space_down_write(va_space); + + uvm_range_tree_for_each_safe(node, next, &hmm_va_space->blocks) { + uvm_va_block_region_t region; + struct vm_area_struct *vma; + + va_block = hmm_va_block_from_node(node); + block_context = uvm_va_space_block_context(va_space, mm); + uvm_hmm_migrate_begin_wait(va_block); + uvm_mutex_lock(&va_block->lock); + for_each_va_block_vma_region(va_block, mm, vma, ®ion) { + if (!uvm_hmm_vma_is_valid(vma, vma->vm_start, false)) + continue; + + block_context->hmm.vma = vma; + block_context->policy = &uvm_va_policy_default; + uvm_hmm_va_block_migrate_locked(va_block, + NULL, + block_context, + UVM_ID_CPU, + region, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + } + uvm_mutex_unlock(&va_block->lock); + uvm_hmm_migrate_finish(va_block); + } + + uvm_va_space_up_write(va_space); + uvm_up_read_mmap_lock(mm); +} + NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr) { uvm_va_block_test_t *block_test; @@ -756,12 +768,7 @@ static NV_STATUS hmm_split_block(uvm_va_block_t *va_block, return status; // Initialize the newly created HMM va_block. - new_va_block->hmm.node.start = new_va_block->start; - new_va_block->hmm.node.end = new_va_block->end; - new_va_block->hmm.va_space = va_space; - uvm_range_tree_init(&new_va_block->hmm.va_policy_tree); - init_waitqueue_head(&new_va_block->hmm.atomic_waitq); - uvm_page_mask_zero(&new_va_block->hmm.atomic_busy); + hmm_va_block_init(new_va_block, va_space, new_va_block->start, new_va_block->end); ret = mmu_interval_notifier_insert(&new_va_block->hmm.notifier, mm, @@ -1509,7 +1516,6 @@ static void hmm_va_block_cpu_page_unpopulate(uvm_va_block_t *va_block, if (!chunk) return; - UVM_ASSERT(uvm_cpu_chunk_is_hmm(chunk)); UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || !uvm_page_mask_test(&va_block->cpu.resident, page_index)); @@ -1533,10 +1539,12 @@ static bool hmm_va_block_cpu_page_is_same(uvm_va_block_t *va_block, // that was expected to be processed isn't migrating, we have to clear the // masks to make service_context consistent with what is actually being // handled. -static NV_STATUS clear_service_context_masks(uvm_service_block_context_t *service_context, - uvm_processor_id_t new_residency, - uvm_page_index_t page_index) +static void clear_service_context_masks(uvm_service_block_context_t *service_context, + uvm_processor_id_t new_residency, + uvm_page_index_t page_index) { + uvm_page_mask_clear(&service_context->block_context.caller_page_mask, page_index); + uvm_page_mask_clear(&service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency, page_index); @@ -1555,11 +1563,6 @@ static NV_STATUS clear_service_context_masks(uvm_service_block_context_t *servic uvm_page_mask_test_and_clear(&service_context->read_duplicate_mask, page_index)) { service_context->read_duplicate_count--; } - - if (service_context->access_type[page_index] != UVM_FAULT_ACCESS_TYPE_PREFETCH) - return NV_WARN_MORE_PROCESSING_REQUIRED; - - return NV_OK; } static void cpu_mapping_set(uvm_va_block_t *va_block, @@ -1596,11 +1599,16 @@ static void gpu_chunk_remove(uvm_va_block_t *va_block, UVM_ASSERT(gpu_state); gpu_chunk = gpu_state->chunks[page_index]; - UVM_ASSERT(gpu_chunk); + if (!gpu_chunk) { + // If we didn't find a chunk it's because the page was unmapped for + // mremap and no fault has established a new mapping. + UVM_ASSERT(!uvm_page_mask_test(&gpu_state->resident, page_index)); + return; + } // TODO: Bug 3898467: unmap indirect peers when freeing GPU chunks - uvm_mmu_chunk_unmap(gpu_chunk, NULL); + uvm_mmu_chunk_unmap(gpu_chunk, &va_block->tracker); gpu_state->chunks[page_index] = NULL; } @@ -1615,6 +1623,17 @@ static NV_STATUS gpu_chunk_add(uvm_va_block_t *va_block, id = uvm_pmm_devmem_page_to_gpu_id(page); gpu_state = uvm_va_block_gpu_state_get(va_block, id); + + // It's possible that this is a fresh va_block we're trying to add an + // existing gpu_chunk to. This occurs for example when a GPU faults on a + // virtual address that has been remapped with mremap(). + if (!gpu_state) { + status = uvm_va_block_gpu_state_alloc(va_block); + if (status != NV_OK) + return status; + gpu_state = uvm_va_block_gpu_state_get(va_block, id); + } + UVM_ASSERT(gpu_state); // Note that a mremap() might be to a CPU virtual address that is nolonger @@ -1653,31 +1672,48 @@ static NV_STATUS gpu_chunk_add(uvm_va_block_t *va_block, return NV_OK; } -static void clean_up(uvm_va_block_t *va_block, - const unsigned long *src_pfns, - uvm_va_block_region_t region, - uvm_page_mask_t *page_mask, - uvm_page_mask_t *same_devmem_page_mask) +// This is called just before calling migrate_vma_finalize() in order to wait +// for GPU operations to complete and update the va_block state to match which +// pages migrated (or not) and therefore which pages will be released by +// migrate_vma_finalize(). +// 'migrated_pages' is the mask of pages that migrated, +// 'same_devmem_page_mask' is the mask of pages that are the same in src_pfns +// and dst_pfns and therefore appear to migrate_vma_*() to be not migrating. +// 'region' is the page index region of all migrated, non-migrated, and +// same_devmem_page_mask pages. +static NV_STATUS sync_page_and_chunk_state(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + const unsigned long *dst_pfns, + uvm_va_block_region_t region, + const uvm_page_mask_t *migrated_pages, + const uvm_page_mask_t *same_devmem_page_mask) { uvm_page_index_t page_index; + NV_STATUS status; - va_block->hmm.changed++; + // Wait for the GPU to finish. migrate_vma_finalize() will release the + // migrated source pages (or non migrating destination pages), so GPU + // opererations must be finished by then. + status = uvm_tracker_wait(&va_block->tracker); - for_each_va_block_page_in_region_mask(page_index, page_mask, region) { - struct page *src_page; + for_each_va_block_page_in_region(page_index, region) { + struct page *page; if (uvm_page_mask_test(same_devmem_page_mask, page_index)) continue; - UVM_ASSERT(src_pfns[page_index] & MIGRATE_PFN_MIGRATE); + // If a page migrated, clean up the source page. + // Otherwise, clean up the destination page. + if (uvm_page_mask_test(migrated_pages, page_index)) + page = migrate_pfn_to_page(src_pfns[page_index]); + else + page = migrate_pfn_to_page(dst_pfns[page_index]); - // A zero source page (pte_none) needs no clean up. - src_page = migrate_pfn_to_page(src_pfns[page_index]); - if (!src_page) + if (!page) continue; - if (is_device_private_page(src_page)) { - gpu_chunk_remove(va_block, page_index, src_page); + if (is_device_private_page(page)) { + gpu_chunk_remove(va_block, page_index, page); } else { // If the source page is a system memory page, @@ -1687,6 +1723,8 @@ static void clean_up(uvm_va_block_t *va_block, hmm_va_block_cpu_page_unpopulate(va_block, page_index); } } + + return status; } // Update va_block state to reflect that the page isn't migrating. @@ -1695,19 +1733,8 @@ static void clean_up_non_migrating_page(uvm_va_block_t *va_block, unsigned long *dst_pfns, uvm_page_index_t page_index) { - struct page *src_page = migrate_pfn_to_page(src_pfns[page_index]); struct page *dst_page = migrate_pfn_to_page(dst_pfns[page_index]); - // If the source page is a normal page that is not migrating, then - // migrate_vma_finalize() will restore the CPU page table with the page PTE. - // Note that the va_block lock has to be held across the migrate_vma_setup, - // migrate_vma_finalize for this to be true so invalidate callbacks don't - // clear the residency and mapping state. - // TODO: Bug 3949334: migrate_vma_setup() is called without the va_block - // lock. - if (src_page && !is_device_private_page(src_page)) - cpu_mapping_set(va_block, src_pfns[page_index] & MIGRATE_PFN_WRITE, page_index); - if (!dst_page) return; @@ -1717,7 +1744,6 @@ static void clean_up_non_migrating_page(uvm_va_block_t *va_block, gpu_chunk_remove(va_block, page_index, dst_page); } else { - UVM_ASSERT(uvm_cpu_chunk_is_hmm(uvm_cpu_chunk_get_chunk_for_page(va_block, page_index))); UVM_ASSERT(page_ref_count(dst_page) == 1); hmm_va_block_cpu_page_unpopulate(va_block, page_index); @@ -1735,6 +1761,10 @@ static void clean_up_non_migrating_pages(uvm_va_block_t *va_block, uvm_page_mask_t *page_mask) { uvm_page_index_t page_index; + NV_STATUS status; + + status = uvm_tracker_wait(&va_block->tracker); + UVM_ASSERT(status == NV_OK); for_each_va_block_page_in_region_mask(page_index, page_mask, region) { clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); @@ -1786,6 +1816,10 @@ static void lock_block_cpu_page(uvm_va_block_t *va_block, UVM_ASSERT(same_devmem_page_mask); UVM_ASSERT(src_page == dst_page); uvm_page_mask_set(same_devmem_page_mask, page_index); + + // The call to migrate_vma_setup() will have inserted a migration PTE + // so the CPU has no access. + cpu_mapping_clear(va_block, page_index); return; } @@ -1882,18 +1916,6 @@ static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, uvm_page_index_t page_index; NV_STATUS status = NV_OK; - // Normally the source page will be a device private page that is being - // migrated to system memory. However, when it is a GPU fault, the source - // page can be a system memory page that the GPU will remote map. If the - // GPU needs atomic access, the destination PTE be a device exclusive PTE - // which migrate_vma_setup() won't select. We check for that and set - // same_devmem_page_mask to record that it should be processed. Also, - // if the source and destination page are the same, the page reference - // count won't be the "expected" count and migrate_vma_pages() won't migrate - // it. This mask tracks that too. - if (same_devmem_page_mask) - uvm_page_mask_zero(same_devmem_page_mask); - for_each_va_block_page_in_region_mask(page_index, page_mask, region) { struct page *src_page; struct page *dst_page; @@ -1907,6 +1929,13 @@ static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, uvm_page_mask_set(same_devmem_page_mask, page_index); continue; } + + // We have previously found a page that is CPU resident which can't + // be migrated (probably a shared mapping) so make sure we establish + // a remote mapping for it. + if (uvm_page_mask_test(same_devmem_page_mask, page_index)) + continue; + goto clr_mask; } @@ -1914,9 +1943,10 @@ static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, src_page = migrate_pfn_to_page(src_pfns[page_index]); if (src_page) { - // The call to migrate_vma_setup() will have inserted a migration - // PTE so the CPU has no access. - cpu_mapping_clear(va_block, page_index); + // mremap may have caused us to loose the gpu_chunk associated with + // this va_block/page_index so make sure we have the correct chunk. + if (is_device_private_page(src_page)) + gpu_chunk_add(va_block, page_index, src_page); if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { lock_block_cpu_page(va_block, page_index, src_page, dst_pfns, same_devmem_page_mask); @@ -1975,18 +2005,14 @@ static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, clr_mask: // TODO: Bug 3900774: clean up murky mess of mask clearing. uvm_page_mask_clear(page_mask, page_index); - if (service_context) { - status = clear_service_context_masks(service_context, UVM_ID_CPU, page_index); - if (status != NV_OK) - break; - } - - if (uvm_page_mask_empty(page_mask)) - return NV_WARN_NOTHING_TO_DO; + if (service_context) + clear_service_context_masks(service_context, UVM_ID_CPU, page_index); } if (status != NV_OK) clean_up_non_migrating_pages(va_block, src_pfns, dst_pfns, region, page_mask); + else if (uvm_page_mask_empty(page_mask)) + return NV_WARN_MORE_PROCESSING_REQUIRED; return status; } @@ -2069,40 +2095,30 @@ static NV_STATUS uvm_hmm_devmem_fault_finalize_and_map(uvm_hmm_devmem_fault_cont if (uvm_page_mask_test(&devmem_fault_context->same_devmem_page_mask, page_index)) continue; - clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); - // TODO: Bug 3900774: clean up murky mess of mask clearing. uvm_page_mask_clear(page_mask, page_index); - status = clear_service_context_masks(service_context, UVM_ID_CPU, page_index); - if (status != NV_OK) - return status; - - // Return if nothing is actually migrating. - if (uvm_page_mask_empty(page_mask)) - return NV_WARN_MORE_PROCESSING_REQUIRED; + clear_service_context_masks(service_context, UVM_ID_CPU, page_index); } - status = uvm_va_block_service_finish(processor_id, va_block, service_context); - - // Wait for the GPU CE to finish. - // After this callback returns, the kernel will unmap all migrated - // pages, so the copy must be finished by then. - tracker_status = uvm_tracker_wait(&va_block->tracker); - if (status == NV_OK) - status = tracker_status; + if (uvm_page_mask_empty(page_mask)) + status = NV_WARN_MORE_PROCESSING_REQUIRED; + else + status = uvm_va_block_service_finish(processor_id, va_block, service_context); - clean_up(va_block, - src_pfns, - region, - page_mask, - &devmem_fault_context->same_devmem_page_mask); + tracker_status = sync_page_and_chunk_state(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &devmem_fault_context->same_devmem_page_mask); - return status; + return status == NV_OK ? tracker_status : status; } static NV_STATUS populate_region(uvm_va_block_t *va_block, unsigned long *pfns, - uvm_va_block_region_t region) + uvm_va_block_region_t region, + uvm_page_mask_t *populated_page_mask) { uvm_page_index_t page_index; NV_STATUS status; @@ -2161,6 +2177,11 @@ static NV_STATUS populate_region(uvm_va_block_t *va_block, status = hmm_va_block_cpu_page_populate(va_block, page_index, page); if (status != NV_OK) return status; + + // Record that we populated this page. hmm_block_cpu_fault_locked() + // uses this to ensure pages that don't migrate get remote mapped. + if (populated_page_mask) + uvm_page_mask_set(populated_page_mask, page_index); } // Since we have a stable snapshot of the CPU pages, we can @@ -2174,16 +2195,32 @@ static NV_STATUS populate_region(uvm_va_block_t *va_block, return NV_OK; } -// Make the service_context->region be resident on the CPU by calling -// hmm_range_fault() to fault in CPU pages. -static NV_STATUS hmm_va_block_make_resident_cpu(uvm_va_block_t *va_block, - uvm_service_block_context_t *service_context) +static void hmm_range_fault_begin(uvm_va_block_t *va_block) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + + uvm_assert_mutex_locked(&va_block->lock); + uvm_context->hmm_invalidate_seqnum = va_block->hmm.changed; +} + +static bool hmm_range_fault_retry(uvm_va_block_t *va_block) { uvm_thread_context_t *uvm_context = uvm_thread_context(); + + uvm_assert_mutex_locked(&va_block->lock); + return uvm_context->hmm_invalidate_seqnum != va_block->hmm.changed; +} + +// Make the region be resident on the CPU by calling hmm_range_fault() to fault +// in CPU pages. +static NV_STATUS hmm_make_resident_cpu(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + unsigned long *hmm_pfns, + uvm_va_block_region_t region, + NvU8 *access_type, + uvm_page_mask_t *populated_page_mask) +{ uvm_page_index_t page_index; - uvm_va_block_region_t region = service_context->region; - unsigned long *hmm_pfns = service_context->block_context.hmm.src_pfns; - unsigned long seqnum; int ret; struct hmm_range range = { .notifier = &va_block->hmm.notifier, @@ -2195,16 +2232,14 @@ static NV_STATUS hmm_va_block_make_resident_cpu(uvm_va_block_t *va_block, }; for_each_va_block_page_in_region(page_index, region) { - if (service_context->access_type[page_index] >= UVM_FAULT_ACCESS_TYPE_WRITE || - (service_context->block_context.hmm.vma->vm_flags & VM_WRITE)) + if ((access_type && access_type[page_index] >= UVM_FAULT_ACCESS_TYPE_WRITE) || + (vma->vm_flags & VM_WRITE)) hmm_pfns[page_index] = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE; else hmm_pfns[page_index] = HMM_PFN_REQ_FAULT; } - // Save the current sequence number so we can detect residency and mapping - // changes while not holding the va_block lock. - seqnum = va_block->hmm.changed; + hmm_range_fault_begin(va_block); // Mirror the VA block to the HMM address range. // Note that we request HMM to handle page faults, which means that it will @@ -2214,66 +2249,21 @@ static NV_STATUS hmm_va_block_make_resident_cpu(uvm_va_block_t *va_block, // the invalidation callback acquires. uvm_mutex_unlock(&va_block->lock); - // Prevent MMU invalidation callbacks in this thread from invalidating - // the hmm_range_fault() results. - uvm_context->ignore_hmm_invalidate_va_block = va_block; - range.notifier_seq = mmu_interval_read_begin(range.notifier); ret = hmm_range_fault(&range); - uvm_context->ignore_hmm_invalidate_va_block = NULL; - uvm_mutex_lock(&va_block->lock); if (ret) return (ret == -EBUSY) ? NV_WARN_MORE_PROCESSING_REQUIRED : errno_to_nv_status(ret); - if (mmu_interval_read_retry(range.notifier, range.notifier_seq)) - return NV_WARN_MORE_PROCESSING_REQUIRED; - - // We unlocked and relocked the block lock so the va_block state might have - // changed. We know there were no invalidation callbacks due to the above - // check. The mmap lock and va_space lock are stil being held so pages - // could be evicted or migrated but not destroyed. The VMAs will be - // unchanged since we hold the mmap lock. The policies will still be - // unchanged since no invalidate() callback was seen and holding the - // va_space lock prevents API policy changes. - if (seqnum != va_block->hmm.changed) + if (hmm_range_fault_retry(va_block)) return NV_WARN_MORE_PROCESSING_REQUIRED; return populate_region(va_block, - service_context->block_context.hmm.src_pfns, - region); -} - -static void hmm_handle_prefetch_setup(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region, - struct migrate_vma *args) -{ - uvm_page_index_t fault_index = args->src - va_block_context->hmm.src_pfns; - unsigned long src_pfn; - int ret; - - // Save the src_pfn. The migrate_vma_setup() will see a migration PTE and - // mark the faulting address entry as not migrating. Then restore the - // original entry. - src_pfn = args->src[0]; - UVM_ASSERT(src_pfn & MIGRATE_PFN_MIGRATE); - UVM_ASSERT(!args->dst[0]); - - args->src = va_block_context->hmm.src_pfns + region.first; - args->dst = va_block_context->hmm.dst_pfns + region.first; - args->start = uvm_va_block_region_start(va_block, region); - args->end = uvm_va_block_region_end(va_block, region) + 1; - fault_index -= region.first; - - ret = migrate_vma_setup(args); - UVM_ASSERT(!ret); - - UVM_ASSERT(!args->src[fault_index]); - args->src[fault_index] = src_pfn; - UVM_ASSERT(!args->dst[fault_index]); + hmm_pfns, + region, + populated_page_mask); } // Release the reference count on any pages that were made device exclusive. @@ -2294,41 +2284,18 @@ static void hmm_release_atomic_pages(uvm_va_block_t *va_block, } } -// Wait for any atomic migrations to finish before doing further migrations. -// This function drops the va_block lock and reacquires it so callers need to -// validate any cached va_block state after this function returns. -static void hmm_wait_for_atomic(uvm_va_block_t *va_block, - uvm_va_block_region_t region) -{ - uvm_assert_mutex_locked(&va_block->lock); - - while (!uvm_page_mask_region_empty(&va_block->hmm.atomic_busy, region)) { - uvm_mutex_unlock(&va_block->lock); - - wait_event(va_block->hmm.atomic_waitq, uvm_page_mask_region_empty(&va_block->hmm.atomic_busy, region)); - - uvm_mutex_lock(&va_block->lock); - } -} - static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_service_block_context_t *service_context) { - uvm_thread_context_t *uvm_context = uvm_thread_context(); uvm_va_block_region_t region = service_context->region; struct page **pages = service_context->block_context.hmm.pages; - unsigned long notifier_seq; int npages; uvm_page_index_t page_index; uvm_make_resident_cause_t cause; NV_STATUS status; - hmm_wait_for_atomic(va_block, region); - - uvm_page_mask_region_fill(&va_block->hmm.atomic_busy, region); - if (!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || !uvm_page_mask_region_full(&va_block->cpu.resident, region)) { // There is an atomic GPU fault. We need to make sure no pages are @@ -2341,30 +2308,36 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, else cause = UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER; - status = hmm_va_block_migrate_locked(va_block, - va_block_retry, - &service_context->block_context, - UVM_ID_CPU, - region, - cause); + status = uvm_hmm_va_block_migrate_locked(va_block, + va_block_retry, + &service_context->block_context, + UVM_ID_CPU, + region, + cause); if (status != NV_OK) - goto clear; + goto done; // make_device_exclusive_range() will try to call migrate_to_ram() // and deadlock with ourself if the data isn't CPU resident. if (!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || !uvm_page_mask_region_full(&va_block->cpu.resident, region)) { status = NV_WARN_MORE_PROCESSING_REQUIRED; - goto clear; + goto done; } } - uvm_mutex_unlock(&va_block->lock); + // TODO: Bug 4014681: atomic GPU operations are not supported on MAP_SHARED + // mmap() files so we check for that here and report a fatal fault. + // Otherwise with the current Linux 6.1 make_device_exclusive_range(), + // it doesn't make the page exclusive and we end up in an endless loop. + if (service_context->block_context.hmm.vma->vm_flags & VM_SHARED) { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } - // Prevent MMU invalidation callbacks from deadlocking in this thread. - uvm_context->ignore_hmm_invalidate_va_block = va_block; + hmm_range_fault_begin(va_block); - notifier_seq = mmu_interval_read_begin(&va_block->hmm.notifier); + uvm_mutex_unlock(&va_block->lock); npages = make_device_exclusive_range(service_context->block_context.mm, uvm_va_block_cpu_page_address(va_block, region.first), @@ -2372,19 +2345,17 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, pages + region.first, &g_uvm_global); - uvm_context->ignore_hmm_invalidate_va_block = NULL; - uvm_mutex_lock(&va_block->lock); if (npages < 0) { status = (npages == -EBUSY) ? NV_WARN_MORE_PROCESSING_REQUIRED : errno_to_nv_status(npages); - goto clear; + goto done; } while ((size_t)npages < uvm_va_block_region_num_pages(region)) pages[region.first + npages++] = NULL; - if (mmu_interval_read_retry(&va_block->hmm.notifier, notifier_seq)) { + if (hmm_range_fault_retry(va_block)) { status = NV_WARN_MORE_PROCESSING_REQUIRED; goto release; } @@ -2432,10 +2403,7 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, release: hmm_release_atomic_pages(va_block, service_context); -clear: - uvm_page_mask_region_clear(&va_block->hmm.atomic_busy, region); - wake_up_all(&va_block->hmm.atomic_waitq); - +done: return status; } @@ -2451,12 +2419,26 @@ static bool is_atomic_fault(NvU8 *access_type, uvm_va_block_region_t region) return false; } +static bool is_gpu_resident(uvm_va_block_t *va_block, uvm_va_block_region_t region) +{ + uvm_processor_id_t gpu_id; + + for_each_gpu_id_in_mask(gpu_id, &va_block->resident) { + uvm_va_block_gpu_state_t *gpu_state; + + gpu_state = uvm_va_block_gpu_state_get(va_block, gpu_id); + if (!uvm_page_mask_region_empty(&gpu_state->resident, region)) + return true; + } + + return false; +} + static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_service_block_context_t *service_context) { - uvm_thread_context_t *uvm_context = uvm_thread_context(); uvm_va_block_region_t region = service_context->region; struct migrate_vma *args = &service_context->block_context.hmm.migrate_vma_args; NV_STATUS status; @@ -2468,12 +2450,20 @@ static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, .service_context = service_context, }; - // uvm_va_block_select_residency() should select the CPU for the - // new_residency. This might not be true if GPU memory is accessible - // from the CPU and the preferred location is the GPU, but then HMM - // wouldn't be needed. - UVM_ASSERT(uvm_processor_mask_get_count(&service_context->resident_processors) == 1); - UVM_ASSERT(UVM_ID_IS_CPU(uvm_processor_mask_find_first_id(&service_context->resident_processors))); + // Normally the source page will be a device private page that is being + // migrated to system memory. However, when it is a GPU fault, the source + // page can be a system memory page that the GPU needs to remote map + // instead. However migrate_vma_setup() won't select these types of + // mappings/pages: + // - device exclusive PTEs + // - shared mappings + // - file backed mappings + // Also, if the source and destination page are the same, the page reference + // count won't be the "expected" count and migrate_vma_pages() won't migrate + // it. This mask records that uvm_hmm_devmem_fault_alloc_and_copy() and + // uvm_hmm_devmem_fault_finalize_and_map() still needs to process these + // pages even if src_pfn indicates they are not migrating. + uvm_page_mask_zero(&fault_context.same_devmem_page_mask); if (!UVM_ID_IS_CPU(processor_id)) { if (is_atomic_fault(service_context->access_type, region)) { @@ -2483,40 +2473,49 @@ static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, service_context); } - hmm_wait_for_atomic(va_block, region); - - status = hmm_va_block_make_resident_cpu(va_block, service_context); + status = hmm_make_resident_cpu(va_block, + service_context->block_context.hmm.vma, + service_context->block_context.hmm.src_pfns, + region, + service_context->access_type, + &fault_context.same_devmem_page_mask); if (status != NV_OK) return status; + + // If no GPU has a resident copy, we can skip the migrate_vma_*(). + // This is necessary if uvm_hmm_must_use_sysmem() returned true. + if (!is_gpu_resident(va_block, region)) { + status = uvm_va_block_service_copy(processor_id, + UVM_ID_CPU, + va_block, + va_block_retry, + service_context); + if (status != NV_OK) + return status; + + return uvm_va_block_service_finish(processor_id, va_block, service_context); + } } - // Prevent MMU invalidation callbacks from deadlocking in this thread. - uvm_context->ignore_hmm_invalidate_va_block = va_block; + args->vma = service_context->block_context.hmm.vma; + args->src = service_context->block_context.hmm.src_pfns + region.first; + args->dst = service_context->block_context.hmm.dst_pfns + region.first; + args->start = uvm_va_block_region_start(va_block, region); + args->end = uvm_va_block_region_end(va_block, region) + 1; + args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; + args->pgmap_owner = &g_uvm_global; if (UVM_ID_IS_CPU(processor_id)) { - // args were set by uvm_hmm_va_block_cpu_find() but the prefetch - // calculation might have expanded the region. - if (uvm_va_block_region_num_pages(region) > 1) { - hmm_handle_prefetch_setup(va_block, - &service_context->block_context, - region, - args); - } + args->fault_page = service_context->cpu_fault.vmf->page; } else { - args->vma = service_context->block_context.hmm.vma; - args->src = service_context->block_context.hmm.src_pfns + region.first; - args->dst = service_context->block_context.hmm.dst_pfns + region.first; - args->start = uvm_va_block_region_start(va_block, region); - args->end = uvm_va_block_region_end(va_block, region) + 1; - args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE | MIGRATE_VMA_SELECT_SYSTEM; - args->pgmap_owner = &g_uvm_global; + args->flags |= MIGRATE_VMA_SELECT_SYSTEM; args->fault_page = NULL; - - ret = migrate_vma_setup(args); - UVM_ASSERT(!ret); } + ret = migrate_vma_setup_locked(args, va_block); + UVM_ASSERT(!ret); + // The overall process here is to migrate pages from the GPU to the CPU // and possibly remote map the GPU to sysmem if accessed_by is set. // This is safe because we hold the va_block lock across the calls to @@ -2536,14 +2535,8 @@ static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, status = uvm_hmm_devmem_fault_finalize_and_map(&fault_context); } - uvm_context->ignore_hmm_invalidate_va_block = NULL; - migrate_vma_finalize(args); - // Notify uvm_hmm_cpu_fault_finish() that migrate_vma_finalize() has been - // called. - service_context->block_context.hmm.migrate_vma_args.vma = NULL; - if (status == NV_WARN_NOTHING_TO_DO) status = NV_OK; @@ -2582,6 +2575,17 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, continue; } + if (folio_test_swapcache(page_folio(src_page))) { + // TODO: Bug 4050579: Remove this when swap cached pages can be + // migrated. + if (service_context) { + service_context->block_context.hmm.swap_cached = true; + break; + } + + goto clr_mask; + } + // If the page is already allocated, it is most likely a mirrored // page. Check to be sure it matches what we have recorded. The // page shouldn't be a staging page from a GPU to GPU migration @@ -2630,18 +2634,14 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, clr_mask: // TODO: Bug 3900774: clean up murky mess of mask clearing. uvm_page_mask_clear(page_mask, page_index); - if (service_context) { - status = clear_service_context_masks(service_context, dest_id, page_index); - if (status != NV_OK) - break; - } - - // Return if nothing is actually migrating. - // TODO: Bug 3900021: investigate thrashing improvements. - if (uvm_page_mask_empty(page_mask)) - return NV_WARN_NOTHING_TO_DO; + if (service_context) + clear_service_context_masks(service_context, dest_id, page_index); } + if (uvm_page_mask_empty(page_mask) || + (service_context && service_context->block_context.hmm.swap_cached)) + status = NV_WARN_MORE_PROCESSING_REQUIRED; + if (status != NV_OK) clean_up_non_migrating_pages(va_block, src_pfns, dst_pfns, region, page_mask); @@ -2722,7 +2722,7 @@ static NV_STATUS uvm_hmm_gpu_fault_finalize_and_map(uvm_hmm_gpu_fault_event_t *u uvm_va_block_region_t region; uvm_page_index_t page_index; uvm_page_mask_t *page_mask; - NV_STATUS status; + NV_STATUS status, tracker_status; processor_id = uvm_hmm_gpu_fault_event->processor_id; new_residency = uvm_hmm_gpu_fault_event->new_residency; @@ -2747,35 +2747,24 @@ static NV_STATUS uvm_hmm_gpu_fault_finalize_and_map(uvm_hmm_gpu_fault_event_t *u if (uvm_page_mask_test(&uvm_hmm_gpu_fault_event->same_devmem_page_mask, page_index)) continue; - clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); - // TODO: Bug 3900774: clean up murky mess of mask clearing. uvm_page_mask_clear(page_mask, page_index); - status = clear_service_context_masks(service_context, new_residency, page_index); - if (status != NV_OK) - return status; - - // Return if nothing is actually migrating. - if (uvm_page_mask_empty(page_mask)) - return NV_WARN_NOTHING_TO_DO; + clear_service_context_masks(service_context, new_residency, page_index); } - // Update the va_block state and GPU mappings. - status = uvm_va_block_service_finish(processor_id, va_block, service_context); - if (status == NV_OK) { - // Wait for the GPU to finish. - // After this callback returns, the kernel will free all migrated - // system memory pages, so the copy must be finished by then. - status = uvm_tracker_wait(&va_block->tracker); - } + if (uvm_page_mask_empty(page_mask)) + status = NV_WARN_MORE_PROCESSING_REQUIRED; + else + status = uvm_va_block_service_finish(processor_id, va_block, service_context); - clean_up(va_block, - src_pfns, - region, - page_mask, - &uvm_hmm_gpu_fault_event->same_devmem_page_mask); + tracker_status = sync_page_and_chunk_state(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_gpu_fault_event->same_devmem_page_mask); - return status; + return status == NV_OK ? tracker_status : status; } NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, @@ -2784,7 +2773,6 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, uvm_va_block_retry_t *va_block_retry, uvm_service_block_context_t *service_context) { - uvm_thread_context_t *uvm_context = uvm_thread_context(); struct mm_struct *mm = service_context->block_context.mm; struct vm_area_struct *vma = service_context->block_context.hmm.vma; uvm_va_block_region_t region = service_context->region; @@ -2797,6 +2785,8 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, return status; uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_block->hmm.va_space->lock); + uvm_assert_mutex_locked(&va_block->hmm.migrate_lock); uvm_assert_mutex_locked(&va_block->lock); UVM_ASSERT(vma); @@ -2804,8 +2794,6 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, if (UVM_ID_IS_CPU(new_residency)) return hmm_block_cpu_fault_locked(processor_id, va_block, va_block_retry, service_context); - hmm_wait_for_atomic(va_block, region); - uvm_hmm_gpu_fault_event.processor_id = processor_id; uvm_hmm_gpu_fault_event.new_residency = new_residency; uvm_hmm_gpu_fault_event.va_block = va_block; @@ -2821,10 +2809,7 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, args->pgmap_owner = &g_uvm_global; args->fault_page = NULL; - // Prevent MMU invalidation callbacks from deadlocking in this thread. - uvm_context->ignore_hmm_invalidate_va_block = va_block; - - ret = migrate_vma_setup(args); + ret = migrate_vma_setup_locked(args, va_block); UVM_ASSERT(!ret); // The overall process here is to migrate pages from the CPU or GPUs to the @@ -2843,7 +2828,6 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, // page being migrated. status = uvm_hmm_gpu_fault_alloc_and_copy(vma, &uvm_hmm_gpu_fault_event); if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { - uvm_context->ignore_hmm_invalidate_va_block = NULL; migrate_vma_finalize(args); // migrate_vma_setup() might have not been able to lock/isolate any @@ -2851,7 +2835,12 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, // We do know that none of the pages in the region are zero pages // since migrate_vma_setup() would have reported that information. // Try to make it resident in system memory and retry the migration. - status = hmm_va_block_make_resident_cpu(va_block, service_context); + status = hmm_make_resident_cpu(va_block, + service_context->block_context.hmm.vma, + service_context->block_context.hmm.src_pfns, + region, + service_context->access_type, + NULL); return NV_WARN_MORE_PROCESSING_REQUIRED; } @@ -2860,7 +2849,6 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, status = uvm_hmm_gpu_fault_finalize_and_map(&uvm_hmm_gpu_fault_event); } - uvm_context->ignore_hmm_invalidate_va_block = NULL; migrate_vma_finalize(args); if (status == NV_WARN_NOTHING_TO_DO) @@ -2891,6 +2879,7 @@ static NV_STATUS uvm_hmm_migrate_alloc_and_copy(struct vm_area_struct *vma, dest_id = uvm_hmm_migrate_event->dest_id; page_mask = &uvm_hmm_migrate_event->page_mask; uvm_page_mask_init_from_region(page_mask, region, NULL); + uvm_page_mask_zero(&uvm_hmm_migrate_event->same_devmem_page_mask); uvm_assert_mutex_locked(&va_block->lock); @@ -2958,7 +2947,6 @@ static NV_STATUS uvm_hmm_migrate_finalize(uvm_hmm_migrate_event_t *uvm_hmm_migra uvm_page_mask_t *page_mask; const unsigned long *src_pfns; unsigned long *dst_pfns; - NV_STATUS status; va_block = uvm_hmm_migrate_event->va_block; va_block_retry = uvm_hmm_migrate_event->va_block_retry; @@ -2984,107 +2972,39 @@ static NV_STATUS uvm_hmm_migrate_finalize(uvm_hmm_migrate_event_t *uvm_hmm_migra if (uvm_page_mask_test(&uvm_hmm_migrate_event->same_devmem_page_mask, page_index)) continue; - clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); - uvm_page_mask_clear(page_mask, page_index); } uvm_va_block_make_resident_finish(va_block, va_block_context, region, page_mask); - // Wait for the GPU CE to finish. - // After this callback returns, the kernel will unmap all migrated - // pages, so the copy must be finished by then. - status = uvm_tracker_wait(&va_block->tracker); - if (status != NV_OK) - UVM_ERR_PRINT("uvm_tracker_wait failed, error %s\n", nvstatusToString(status)); - - clean_up(va_block, - src_pfns, - region, - page_mask, - &uvm_hmm_migrate_event->same_devmem_page_mask); - - return status; + return sync_page_and_chunk_state(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_migrate_event->same_devmem_page_mask); } -static NV_STATUS hmm_va_block_migrate_make_resident_cpu(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_page_mask_t *page_mask) +static bool is_resident(uvm_va_block_t *va_block, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region) { - uvm_thread_context_t *uvm_context = uvm_thread_context(); - struct vm_area_struct *vma = va_block_context->hmm.vma; - uvm_page_index_t page_index; - uvm_va_block_region_t region = uvm_va_block_region_from_mask(va_block, page_mask); - unsigned long *hmm_pfns = va_block_context->hmm.src_pfns; - unsigned long seqnum; - int ret; - struct hmm_range range = { - .notifier = &va_block->hmm.notifier, - .start = uvm_va_block_region_start(va_block, region), - .end = uvm_va_block_region_end(va_block, region) + 1, - .hmm_pfns = hmm_pfns + region.first, - .pfn_flags_mask = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE, - .dev_private_owner = &g_uvm_global, - }; - - for_each_va_block_page_in_region(page_index, region) { - if (vma->vm_flags & VM_WRITE) - hmm_pfns[page_index] = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE; - else - hmm_pfns[page_index] = HMM_PFN_REQ_FAULT; - } - - // Save the current sequence number so we can detect residency and mapping - // changes while not holding the va_block lock. - seqnum = va_block->hmm.changed; - - // Mirror the VA block to the HMM address range. - // Note that we request HMM to handle page faults, which means that it will - // populate and map potentially not-yet-existing pages to the VMA. - // Also note that mmu_interval_read_begin() calls wait_event() for any - // parallel invalidation callbacks to finish so we can't hold locks that - // the invalidation callback acquires. - uvm_mutex_unlock(&va_block->lock); - - // Prevent MMU invalidation callbacks in this thread from invalidating - // the hmm_range_fault() results. - uvm_context->ignore_hmm_invalidate_va_block = va_block; - - range.notifier_seq = mmu_interval_read_begin(range.notifier); - ret = hmm_range_fault(&range); - - uvm_context->ignore_hmm_invalidate_va_block = NULL; - - uvm_mutex_lock(&va_block->lock); - - if (ret) - return (ret == -EBUSY) ? NV_WARN_MORE_PROCESSING_REQUIRED : errno_to_nv_status(ret); - - if (mmu_interval_read_retry(range.notifier, range.notifier_seq)) - return NV_WARN_MORE_PROCESSING_REQUIRED; - - // We unlocked and relocked the block lock but held the mmap lock and - // va_space lock so pages could only be migrated, not destroyed. The VMAs - // will be unchanged since we hold the mmap lock. The policies will still - // be unchanged since no invalidate() callback was seen and holding the - // va_space lock prevents API policy changes. - if (seqnum != va_block->hmm.changed) - return NV_WARN_MORE_PROCESSING_REQUIRED; + if (!uvm_processor_mask_test(&va_block->resident, dest_id)) + return false; - return populate_region(va_block, hmm_pfns, region); + return uvm_page_mask_region_full(uvm_va_block_resident_mask_get(va_block, dest_id), region); } // Note that migrate_vma_*() doesn't handle asynchronous migrations so the // migration flag UVM_MIGRATE_FLAG_SKIP_CPU_MAP doesn't have an effect. // TODO: Bug 3900785: investigate ways to implement async migration. -static NV_STATUS hmm_va_block_migrate_locked(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - uvm_make_resident_cause_t cause) +NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause) { - uvm_thread_context_t *uvm_context = uvm_thread_context(); uvm_hmm_migrate_event_t uvm_hmm_migrate_event; struct vm_area_struct *vma = va_block_context->hmm.vma; NvU64 start; @@ -3096,6 +3016,8 @@ static NV_STATUS hmm_va_block_migrate_locked(uvm_va_block_t *va_block, UVM_ASSERT(vma); UVM_ASSERT(va_block_context->mm == vma->vm_mm); uvm_assert_mmap_lock_locked(va_block_context->mm); + uvm_assert_rwsem_locked(&va_block->hmm.va_space->lock); + uvm_assert_mutex_locked(&va_block->hmm.migrate_lock); uvm_assert_mutex_locked(&va_block->lock); start = uvm_va_block_region_start(va_block, region); @@ -3119,17 +3041,38 @@ static NV_STATUS hmm_va_block_migrate_locked(uvm_va_block_t *va_block, args->pgmap_owner = &g_uvm_global; args->fault_page = NULL; - // Prevent MMU invalidation callbacks from deadlocking in this thread. - uvm_context->ignore_hmm_invalidate_va_block = va_block; - - ret = migrate_vma_setup(args); - UVM_ASSERT(!ret); + // Note that migrate_vma_setup() doesn't handle file backed or VM_SPECIAL + // VMAs so if UvmMigrate() tries to migrate such a region, -EINVAL will + // be returned and we will only try to make the pages be CPU resident. + ret = migrate_vma_setup_locked(args, va_block); + if (ret) + return hmm_make_resident_cpu(va_block, + vma, + va_block_context->hmm.src_pfns, + region, + NULL, + NULL); - if (!args->cpages) { + // The overall process here is to migrate pages from the CPU or GPUs to the + // destination processor. Note that block_migrate_add_mappings() handles + // updating GPU mappings after the migration. + // This is safe because we hold the va_block lock across the calls to + // uvm_hmm_migrate_alloc_and_copy(), migrate_vma_pages(), + // uvm_hmm_migrate_finalize(), migrate_vma_finalize() and + // block_migrate_add_mappings(). + // If uvm_hmm_migrate_alloc_and_copy() needs to drop the va_block + // lock, a sequence number is used to tell if an invalidate() callback + // occurred while not holding the lock. If the sequence number changes, + // all the locks need to be dropped (mm, va_space, va_block) and the whole + // uvm_hmm_va_block_migrate_locked() called again. Otherwise, there were no + // conflicting invalidate callbacks and our snapshots of the CPU page + // tables are accurate and can be used to DMA pages and update GPU page + // tables. + status = uvm_hmm_migrate_alloc_and_copy(vma, &uvm_hmm_migrate_event); + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { uvm_processor_id_t id; uvm_page_mask_t *page_mask; - uvm_context->ignore_hmm_invalidate_va_block = NULL; migrate_vma_finalize(args); // The CPU pages tables might contain only device private pages or @@ -3149,31 +3092,19 @@ static NV_STATUS hmm_va_block_migrate_locked(uvm_va_block_t *va_block, return NV_OK; } - return hmm_va_block_migrate_make_resident_cpu(va_block, va_block_context, page_mask); + return hmm_make_resident_cpu(va_block, + vma, + va_block_context->hmm.src_pfns, + region, + NULL, + NULL); } - // The overall process here is to migrate pages from the CPU or GPUs to the - // destination processor. Note that block_migrate_add_mappings() handles - // updating GPU mappings after the migration. - // This is safe because we hold the va_block lock across the calls to - // uvm_hmm_migrate_alloc_and_copy(), migrate_vma_pages(), - // uvm_hmm_migrate_finalize(), migrate_vma_finalize() and - // block_migrate_add_mappings(). - // If uvm_hmm_migrate_alloc_and_copy() needs to drop the va_block - // lock, a sequence number is used to tell if an invalidate() callback - // occurred while not holding the lock. If the sequence number changes, - // all the locks need to be dropped (mm, va_space, va_block) and the whole - // uvm_hmm_va_block_migrate_locked() called again. Otherwise, there were no - // conflicting invalidate callbacks and our snapshots of the CPU page - // tables are accurate and can be used to DMA pages and update GPU page - // tables. - status = uvm_hmm_migrate_alloc_and_copy(vma, &uvm_hmm_migrate_event); if (status == NV_OK) { migrate_vma_pages(args); status = uvm_hmm_migrate_finalize(&uvm_hmm_migrate_event); } - uvm_context->ignore_hmm_invalidate_va_block = NULL; migrate_vma_finalize(args); if (status == NV_WARN_NOTHING_TO_DO) @@ -3182,23 +3113,6 @@ static NV_STATUS hmm_va_block_migrate_locked(uvm_va_block_t *va_block, return status; } -NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - uvm_make_resident_cause_t cause) -{ - hmm_wait_for_atomic(va_block, region); - - return hmm_va_block_migrate_locked(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - cause); -} - NV_STATUS uvm_hmm_migrate_ranges(uvm_va_space_t *va_space, uvm_va_block_context_t *va_block_context, NvU64 base, @@ -3424,32 +3338,34 @@ NV_STATUS uvm_hmm_va_block_evict_pages_from_gpu(uvm_va_block_t *va_block, NULL); } -NV_STATUS uvm_hmm_pmm_gpu_evict_chunk(uvm_gpu_t *gpu, - uvm_gpu_chunk_t *gpu_chunk) +NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) { - uvm_thread_context_t *uvm_context = uvm_thread_context(); - unsigned long pfn = uvm_pmm_gpu_devmem_get_pfn(&gpu->pmm, gpu_chunk); unsigned long src_pfn = 0; unsigned long dst_pfn = 0; struct page *dst_page; NV_STATUS status = NV_OK; int ret; - // TODO: Bug 3368756: add support for large GPU pages. - UVM_ASSERT(uvm_gpu_chunk_get_size(gpu_chunk) == PAGE_SIZE); - - uvm_context->ignore_hmm_invalidate_va_block = gpu_chunk->va_block; ret = migrate_device_range(&src_pfn, pfn, 1); - uvm_context->ignore_hmm_invalidate_va_block = NULL; if (ret) return errno_to_nv_status(ret); if (src_pfn & MIGRATE_PFN_MIGRATE) { - // All the code for copying a vidmem page to sysmem relies on having - // a va_block. This case is only to support fork() and the child isn't - // guaranteed to get valid data. + // All the code for copying a vidmem page to sysmem relies on + // having a va_block. However certain combinations of mremap() + // and fork() can result in device-private pages being mapped + // in a child process without a va_block. + // + // We don't expect the above to be a common occurance so for + // now we allocate a fresh zero page when evicting without a + // va_block. However this results in child processes losing + // data so make sure we warn about it. Ideally we would just + // not migrate and SIGBUS the child if it tries to access the + // page. However that would prevent unloading of the driver so + // we're stuck with this until we fix the problem. // TODO: Bug 3902536: add code to migrate GPU memory without having a // va_block. + WARN_ON(1); dst_page = alloc_page(GFP_HIGHUSER_MOVABLE | __GFP_ZERO); if (!dst_page) { status = NV_ERR_NO_MEMORY; @@ -3531,7 +3447,6 @@ NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, struct vm_area_struct *vma; struct hmm_range range; uvm_va_block_region_t region; - unsigned long seqnum; unsigned long pfn; NvU64 end; int ret; @@ -3558,7 +3473,6 @@ NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, range.default_flags = 0; range.pfn_flags_mask = 0; range.dev_private_owner = &g_uvm_global; - range.notifier_seq = mmu_interval_read_begin(range.notifier); if (populate) { range.default_flags = HMM_PFN_REQ_FAULT; @@ -3566,36 +3480,33 @@ NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, range.default_flags |= HMM_PFN_REQ_WRITE; } - // Save the current sequence number so we can detect residency and mapping - // changes while not holding the va_block lock. - uvm_mutex_lock(&va_block->lock); - seqnum = va_block->hmm.changed; - uvm_mutex_unlock(&va_block->lock); + uvm_hmm_migrate_begin_wait(va_block); while (true) { + range.notifier_seq = mmu_interval_read_begin(range.notifier); ret = hmm_range_fault(&range); if (ret == -EBUSY) continue; - if (ret) + if (ret) { + uvm_hmm_migrate_finish(va_block); return errno_to_nv_status(ret); + } uvm_mutex_lock(&va_block->lock); - if (!mmu_interval_read_retry(range.notifier, range.notifier_seq) && - seqnum == va_block->hmm.changed) + if (!mmu_interval_read_retry(range.notifier, range.notifier_seq)) break; - seqnum = va_block->hmm.changed; - uvm_mutex_unlock(&va_block->lock); } // Update the va_block CPU state based on the snapshot. // Note that we have to adjust the pfns address since it will be indexed // by region.first. - status = populate_region(va_block, &pfn - region.first, region); + status = populate_region(va_block, &pfn - region.first, region, NULL); uvm_mutex_unlock(&va_block->lock); + uvm_hmm_migrate_finish(va_block); return NV_OK; } @@ -3704,7 +3615,18 @@ bool uvm_hmm_must_use_sysmem(uvm_va_block_t *va_block, UVM_ASSERT(va_block_context->mm == vma->vm_mm); uvm_assert_mmap_lock_locked(va_block_context->mm); - return !vma_is_anonymous(vma); + // TODO: Bug 4050579: Remove this when swap cached pages can be migrated. + if (va_block_context->hmm.swap_cached) + return true; + + // migrate_vma_setup() can't migrate VM_SPECIAL so we have to force GPU + // remote mapping. + // TODO: Bug 3660968: add support for file-backed migrations. + // TODO: Bug 3368756: add support for transparent huge page migrations. + return !vma_is_anonymous(vma) || + (vma->vm_flags & VM_SPECIAL) || + vma_is_dax(vma) || + is_vm_hugetlb_page(vma); } #endif // UVM_IS_CONFIG_HMM() diff --git a/kernel-open/nvidia-uvm/uvm_hmm.h b/kernel-open/nvidia-uvm/uvm_hmm.h index b6ecdae6d5..cd30ac3bfd 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.h +++ b/kernel-open/nvidia-uvm/uvm_hmm.h @@ -84,25 +84,6 @@ typedef struct NvU64 addr, uvm_va_block_t **va_block_ptr); - // Find an existing HMM va_block when processing a CPU fault and try to - // isolate and lock the faulting page. - // Return NV_ERR_INVALID_ADDRESS if the block is not found, - // NV_ERR_BUSY_RETRY if the page could not be locked, and - // NV_OK if the block is found and the page is locked. Also, - // uvm_hmm_cpu_fault_finish() must be called if NV_OK is returned. - // Locking: This must be called with the vma->vm_mm locked and the va_space - // read locked. - NV_STATUS uvm_hmm_va_block_cpu_find(uvm_va_space_t *va_space, - uvm_service_block_context_t *service_context, - struct vm_fault *vmf, - uvm_va_block_t **va_block_ptr); - - // This must be called after uvm_va_block_cpu_fault() if - // uvm_hmm_va_block_cpu_find() returns NV_OK. - // Locking: This must be called with the vma->vm_mm locked and the va_space - // read locked. - void uvm_hmm_cpu_fault_finish(uvm_service_block_context_t *service_context); - // Find or create a new HMM va_block. // // Return NV_ERR_INVALID_ADDRESS if there is no VMA associated with the @@ -136,6 +117,26 @@ typedef struct uvm_va_block_context_t *va_block_context, uvm_va_block_region_t region); + // Initialize the HMM portion of the service_context. + // This should be called one time before any retry loops calling + // uvm_va_block_service_locked(). + void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context); + + // Begin a migration critical section. When calling into the kernel it is + // sometimes necessary to drop the va_block lock. This function returns + // NV_OK when no other thread has started a migration critical section. + // Otherwise, it returns NV_ERR_BUSY_RETRY and threads should then retry + // this function to begin a critical section. + // Locking: va_block lock must not be held. + NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block); + + // Same as uvm_hmm_migrate_begin() but waits if required before beginning a + // critical section. + void uvm_hmm_migrate_begin_wait(uvm_va_block_t *va_block); + + // Finish a migration critical section. + void uvm_hmm_migrate_finish(uvm_va_block_t *va_block); + // Find or create a HMM va_block and mark it so the next va_block split // will fail for testing purposes. // Locking: This function must be called with mm retained and locked for @@ -314,6 +315,11 @@ typedef struct uvm_migrate_mode_t mode, uvm_tracker_t *out_tracker); + // Evicts all va_blocks in the va_space to the CPU. Unlike the + // other va_block eviction functions this is based on virtual + // address and therefore takes mmap_lock for read. + void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space); + // This sets the va_block_context->hmm.src_pfns[] to the ZONE_DEVICE private // PFN for the GPU chunk memory. NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, @@ -345,13 +351,13 @@ typedef struct const uvm_page_mask_t *pages_to_evict, uvm_va_block_region_t region); - // Migrate a GPU chunk to system memory. This called to remove CPU page - // table references to device private struct pages for the given GPU after - // all other references in va_blocks have been released and the GPU is - // in the process of being removed/torn down. Note that there is no mm, - // VMA, va_block or any user channel activity on this GPU. - NV_STATUS uvm_hmm_pmm_gpu_evict_chunk(uvm_gpu_t *gpu, - uvm_gpu_chunk_t *gpu_chunk); + // Migrate a GPU device-private page to system memory. This is + // called to remove CPU page table references to device private + // struct pages for the given GPU after all other references in + // va_blocks have been released and the GPU is in the process of + // being removed/torn down. Note that there is no mm, VMA, + // va_block or any user channel activity on this GPU. + NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn); // This returns what would be the intersection of va_block start/end and // VMA start/end-1 for the given 'lookup_address' if @@ -432,18 +438,6 @@ typedef struct return NV_ERR_INVALID_ADDRESS; } - static NV_STATUS uvm_hmm_va_block_cpu_find(uvm_va_space_t *va_space, - uvm_service_block_context_t *service_context, - struct vm_fault *vmf, - uvm_va_block_t **va_block_ptr) - { - return NV_ERR_INVALID_ADDRESS; - } - - static void uvm_hmm_cpu_fault_finish(uvm_service_block_context_t *service_context) - { - } - static NV_STATUS uvm_hmm_va_block_find_create(uvm_va_space_t *va_space, NvU64 addr, uvm_va_block_context_t *va_block_context, @@ -464,6 +458,23 @@ typedef struct return true; } + static void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context) + { + } + + static NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block) + { + return NV_OK; + } + + static void uvm_hmm_migrate_begin_wait(uvm_va_block_t *va_block) + { + } + + static void uvm_hmm_migrate_finish(uvm_va_block_t *va_block) + { + } + static NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr) { return NV_ERR_INVALID_ADDRESS; @@ -586,6 +597,10 @@ typedef struct return NV_ERR_INVALID_ADDRESS; } + static void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space) + { + } + static NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_gpu_chunk_t *gpu_chunk, @@ -612,8 +627,7 @@ typedef struct return NV_OK; } - static NV_STATUS uvm_hmm_pmm_gpu_evict_chunk(uvm_gpu_t *gpu, - uvm_gpu_chunk_t *gpu_chunk) + static NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) { return NV_OK; } diff --git a/kernel-open/nvidia-uvm/uvm_hopper.c b/kernel-open/nvidia-uvm/uvm_hopper.c index 5aa7e9b516..588d79aa9b 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper.c +++ b/kernel-open/nvidia-uvm/uvm_hopper.c @@ -49,11 +49,17 @@ void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu) // A single top level PDE on Hopper covers 64 PB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 64ull * 1024 * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 64 * UVM_SIZE_1PB; - parent_gpu->uvm_mem_va_base = parent_gpu->rm_va_size + 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = parent_gpu->rm_va_size + 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + // See uvm_mmu.h for mapping placement + parent_gpu->flat_vidmem_va_base = (64 * UVM_SIZE_1PB) + (8 * UVM_SIZE_1TB); + + // Physical CE writes to vidmem are non-coherent with respect to the CPU on + // GH180. + parent_gpu->ce_phys_vidmem_write_supported = !uvm_gpu_is_coherent(parent_gpu); parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; diff --git a/kernel-open/nvidia-uvm/uvm_hopper_ce.c b/kernel-open/nvidia-uvm/uvm_hopper_ce.c index f1b81a608b..cdc3499a5f 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper_ce.c +++ b/kernel-open/nvidia-uvm/uvm_hopper_ce.c @@ -24,6 +24,7 @@ #include "uvm_hal.h" #include "uvm_push.h" #include "uvm_mem.h" +#include "uvm_conf_computing.h" #include "clc8b5.h" static NvU32 ce_aperture(uvm_aperture_t aperture) @@ -97,7 +98,8 @@ void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 p NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | - HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_PAYLOAD_SIZE, ONE_WORD) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_SEMAPHORE_NO_TIMESTAMP) | launch_dma_plc_mode); } @@ -114,7 +116,8 @@ void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, N NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | - HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_PAYLOAD_SIZE, ONE_WORD) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_SEMAPHORE_NO_TIMESTAMP) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION, INC) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_SIGN, UNSIGNED) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_ENABLE, TRUE) | @@ -135,7 +138,8 @@ void uvm_hal_hopper_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | - HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_FOUR_WORD_SEMAPHORE) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_PAYLOAD_SIZE, ONE_WORD) | + HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_SEMAPHORE_WITH_TIMESTAMP) | launch_dma_plc_mode); } @@ -148,12 +152,46 @@ static NvU32 hopper_memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t ds return HWCONST(C8B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); } -static bool hopper_scrub_enable(uvm_gpu_address_t dst, size_t size) +static bool va_is_flat_vidmem(uvm_gpu_t *gpu, NvU64 va) { - return !dst.is_virtual && - dst.aperture == UVM_APERTURE_VID && - IS_ALIGNED(dst.address, UVM_PAGE_SIZE_4K) && - IS_ALIGNED(size, UVM_PAGE_SIZE_4K); + return (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) && + va >= gpu->parent->flat_vidmem_va_base && + va < gpu->parent->flat_vidmem_va_base + UVM_GPU_MAX_PHYS_MEM; +} + +// Return whether a memset should use the fast scrubber. If so, convert dst to +// the address needed by the fast scrubber. +static bool hopper_scrub_enable(uvm_gpu_t *gpu, uvm_gpu_address_t *dst, size_t size) +{ + if (!IS_ALIGNED(dst->address, UVM_PAGE_SIZE_4K) || !IS_ALIGNED(size, UVM_PAGE_SIZE_4K)) + return false; + + // When CE physical writes are disallowed, higher layers will convert + // physical memsets to virtual using the flat mapping. Those layers are + // unaware of the fast scrubber, which is safe to use specifically when CE + // physical access is disallowed. Detect such memsets within the flat vidmem + // region and convert them back to physical, since the fast scrubber only + // works with physical addressing. + if (dst->is_virtual && !gpu->parent->ce_phys_vidmem_write_supported && va_is_flat_vidmem(gpu, dst->address)) { + *dst = uvm_gpu_address_physical(UVM_APERTURE_VID, dst->address - gpu->parent->flat_vidmem_va_base); + return true; + } + + return !dst->is_virtual && dst->aperture == UVM_APERTURE_VID; +} + +static NvU32 hopper_memset_copy_type(uvm_push_t *push, uvm_gpu_address_t dst) +{ + if (uvm_conf_computing_mode_enabled(uvm_push_get_gpu(push)) && dst.is_unprotected) + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, NONPROT2NONPROT); + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, DEFAULT); +} + +NvU32 uvm_hal_hopper_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +{ + if (uvm_conf_computing_mode_enabled(uvm_push_get_gpu(push)) && dst.is_unprotected && src.is_unprotected) + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, NONPROT2NONPROT); + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, DEFAULT); } static void hopper_memset_common(uvm_push_t *push, @@ -172,8 +210,10 @@ static void hopper_memset_common(uvm_push_t *push, NvU32 launch_dma_remap_enable; NvU32 launch_dma_scrub_enable; NvU32 flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + NvU32 copy_type_value = hopper_memset_copy_type(push, dst); + bool is_scrub = hopper_scrub_enable(gpu, &dst, num_elements * memset_element_size); - UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, memset_element_size), + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, num_elements, memset_element_size), "Memset validation failed in channel %s, GPU %s", push->channel->name, uvm_gpu_name(gpu)); @@ -186,7 +226,7 @@ static void hopper_memset_common(uvm_push_t *push, else pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); - if (memset_element_size == 8 && hopper_scrub_enable(dst, num_elements * memset_element_size)) { + if (memset_element_size == 8 && is_scrub) { launch_dma_remap_enable = HWCONST(C8B5, LAUNCH_DMA, REMAP_ENABLE, FALSE); launch_dma_scrub_enable = HWCONST(C8B5, LAUNCH_DMA, MEMORY_SCRUB_ENABLE, TRUE); @@ -223,6 +263,7 @@ static void hopper_memset_common(uvm_push_t *push, launch_dma_scrub_enable | launch_dma_dst_type | launch_dma_plc_mode | + copy_type_value | pipelined_value); dst.address += memset_this_time * memset_element_size; @@ -250,7 +291,7 @@ void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 v void uvm_hal_hopper_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size) { - if (hopper_scrub_enable(dst, size)) { + if (hopper_scrub_enable(uvm_push_get_gpu(push), &dst, size)) { NvU64 value64 = value; value64 |= value64 << 8; @@ -274,7 +315,7 @@ void uvm_hal_hopper_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 v { UVM_ASSERT_MSG(size % 4 == 0, "size: %zd\n", size); - if (hopper_scrub_enable(dst, size)) { + if (hopper_scrub_enable(uvm_push_get_gpu(push), &dst, size)) { NvU64 value64 = value; value64 |= value64 << 32; @@ -294,15 +335,235 @@ void uvm_hal_hopper_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 v hopper_memset_common(push, dst, size, 4); } -bool uvm_hal_hopper_ce_memset_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) +bool uvm_hal_hopper_ce_memset_is_valid(uvm_push_t *push, + uvm_gpu_address_t dst, + size_t num_elements, + size_t element_size) { + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + // In HCC, if a memset uses physical addressing for the destination, then + // it must write to (protected) vidmem. If the memset uses virtual + // addressing, and the backing storage is not vidmem, the access is only + // legal if the copy type is NONPROT2NONPROT, and the destination is + // unprotected sysmem, but the validation does not detect it. + if (uvm_conf_computing_mode_is_hcc(gpu) && !dst.is_virtual && dst.aperture != UVM_APERTURE_VID) + return false; + + if (!gpu->parent->ce_phys_vidmem_write_supported) { + size_t size = num_elements * element_size; + uvm_gpu_address_t temp = dst; + + // Physical vidmem writes are disallowed, unless using the scrubber + if (!dst.is_virtual && dst.aperture == UVM_APERTURE_VID && !hopper_scrub_enable(gpu, &temp, size)) { + UVM_ERR_PRINT("Destination address of vidmem memset must be virtual, not physical: {%s, 0x%llx} size %zu\n", + uvm_gpu_address_aperture_string(dst), + dst.address, + size); + return false; + } + } return true; } bool uvm_hal_hopper_ce_memcopy_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) { + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + if (uvm_conf_computing_mode_is_hcc(gpu)) { + // In HCC, if a memcopy uses physical addressing for either the + // destination or the source, then the corresponding aperture must be + // vidmem. If virtual addressing is used, and the backing storage is + // sysmem the access is only legal if the copy type is NONPROT2NONPROT, + // but the validation does not detect it. In other words the copy + // source and destination is unprotected sysmem. + if (!src.is_virtual && (src.aperture != UVM_APERTURE_VID)) + return false; + + if (!dst.is_virtual && (dst.aperture != UVM_APERTURE_VID)) + return false; + + if (dst.is_unprotected != src.is_unprotected) + return false; + } + + if (!gpu->parent->ce_phys_vidmem_write_supported && !dst.is_virtual && dst.aperture == UVM_APERTURE_VID) { + UVM_ERR_PRINT("Destination address of vidmem memcopy must be virtual, not physical: {%s, 0x%llx}\n", + uvm_gpu_address_aperture_string(dst), + dst.address); + return false; + } return true; } +// Specialized version of uvm_hal_volta_ce_memcopy used for encryption and +// decryption. Pre-Hopper functionality, such as validation or address patching, +// has been removed. +static void encrypt_or_decrypt(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, NvU32 size) +{ + NvU32 pipelined_value; + NvU32 launch_dma_src_dst_type; + NvU32 launch_dma_plc_mode; + NvU32 flush_value; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + // HW allows unaligned operations only if the entire buffer is in one 32B + // sector. Operations on buffers larger than 32B have to be aligned. + if (size > UVM_CONF_COMPUTING_BUF_ALIGNMENT) { + UVM_ASSERT(IS_ALIGNED(src.address, UVM_CONF_COMPUTING_BUF_ALIGNMENT)); + UVM_ASSERT(IS_ALIGNED(dst.address, UVM_CONF_COMPUTING_BUF_ALIGNMENT)); + } + else { + UVM_ASSERT((dst.address >> UVM_CONF_COMPUTING_BUF_ALIGNMENT) == + ((dst.address + size - 1) >> UVM_CONF_COMPUTING_BUF_ALIGNMENT)); + UVM_ASSERT((src.address >> UVM_CONF_COMPUTING_BUF_ALIGNMENT) == + ((src.address + size - 1) >> UVM_CONF_COMPUTING_BUF_ALIGNMENT)); + } + + launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + + flush_value = hopper_get_flush_value(push); + + gpu->parent->ce_hal->offset_in_out(push, src.address, dst.address); + + NV_PUSH_1U(C8B5, LINE_LENGTH_IN, size); + + NV_PUSH_1U(C8B5, LAUNCH_DMA, HWCONST(C8B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + HWCONST(C8B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + HWCONST(C8B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + HWCONST(C8B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) | + HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, SECURE) | + flush_value | + launch_dma_src_dst_type | + launch_dma_plc_mode | + pipelined_value); +} + +// The GPU CE encrypt operation requires clients to pass a valid +// address where the used IV will be written. But this requirement is +// unnecessary, because UVM should instead rely on the CSL +// nvUvmInterfaceCslLogDeviceEncryption API to independently track +// the expected IV. +// +// To satisfy the HW requirement the same unprotected sysmem address is +// passed to all GPU-side encryptions. This dummy buffer is allocated at +// GPU initialization time. +static NvU64 encrypt_iv_address(uvm_push_t *push, uvm_gpu_address_t dst) +{ + NvU64 iv_address; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + // Match addressing mode of destination and IV + if (dst.is_virtual) { + iv_address = uvm_rm_mem_get_gpu_va(gpu->conf_computing.iv_rm_mem, gpu, false).address; + } + else { + iv_address = uvm_mem_gpu_physical(gpu->conf_computing.iv_mem, + gpu, + 0, + gpu->conf_computing.iv_mem->size).address; + } + + UVM_ASSERT(IS_ALIGNED(iv_address, UVM_CONF_COMPUTING_IV_ALIGNMENT)); + + return iv_address; +} + +// TODO: Bug 3842953: adapt CE encrypt/decrypt for p2p encrypted transfers +void uvm_hal_hopper_ce_encrypt(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag) +{ + + NvU32 auth_tag_address_hi32, auth_tag_address_lo32; + NvU64 iv_address; + NvU32 iv_address_hi32, iv_address_lo32; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT(uvm_conf_computing_mode_is_hcc(gpu)); + UVM_ASSERT(uvm_push_is_fake(push) || uvm_channel_is_secure(push->channel)); + UVM_ASSERT(IS_ALIGNED(auth_tag.address, UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT)); + + if (!src.is_virtual) + UVM_ASSERT(src.aperture == UVM_APERTURE_VID); + + // The addressing mode (and aperture, if applicable) of the destination + // pointer determines the addressing mode and aperture used by the + // encryption to reference the other two addresses written by it: + // authentication tag, and IV. If the client passes a sysmem physical + // address as destination, then the authentication tag must also be a sysmem + // physical address. + UVM_ASSERT(dst.is_virtual == auth_tag.is_virtual); + + if (!dst.is_virtual) { + UVM_ASSERT(dst.aperture == UVM_APERTURE_SYS); + UVM_ASSERT(auth_tag.aperture == UVM_APERTURE_SYS); + } + + NV_PUSH_1U(C8B5, SET_SECURE_COPY_MODE, HWCONST(C8B5, SET_SECURE_COPY_MODE, MODE, ENCRYPT)); + + auth_tag_address_hi32 = HWVALUE(C8B5, SET_ENCRYPT_AUTH_TAG_ADDR_UPPER, UPPER, NvU64_HI32(auth_tag.address)); + auth_tag_address_lo32 = HWVALUE(C8B5, SET_ENCRYPT_AUTH_TAG_ADDR_LOWER, LOWER, NvU64_LO32(auth_tag.address)); + + iv_address = encrypt_iv_address(push, dst); + + iv_address_hi32 = HWVALUE(C8B5, SET_ENCRYPT_IV_ADDR_UPPER, UPPER, NvU64_HI32(iv_address)); + iv_address_lo32 = HWVALUE(C8B5, SET_ENCRYPT_IV_ADDR_LOWER, LOWER, NvU64_LO32(iv_address)); + + NV_PUSH_4U(C8B5, SET_ENCRYPT_AUTH_TAG_ADDR_UPPER, auth_tag_address_hi32, + SET_ENCRYPT_AUTH_TAG_ADDR_LOWER, auth_tag_address_lo32, + SET_ENCRYPT_IV_ADDR_UPPER, iv_address_hi32, + SET_ENCRYPT_IV_ADDR_LOWER, iv_address_lo32); + + encrypt_or_decrypt(push, dst, src, size); +} + +// TODO: Bug 3842953: adapt CE encrypt/decrypt for p2p encrypted transfers +void uvm_hal_hopper_ce_decrypt(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag) +{ + + NvU32 auth_tag_address_hi32, auth_tag_address_lo32; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT(uvm_conf_computing_mode_is_hcc(gpu)); + UVM_ASSERT(!push->channel || uvm_channel_is_secure(push->channel)); + UVM_ASSERT(IS_ALIGNED(auth_tag.address, UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT)); + + // The addressing mode (and aperture, if applicable) of the source and + // authentication pointers should match. But unlike in the encryption case, + // clients are not forced to pass a valid IV address. + UVM_ASSERT(src.is_virtual == auth_tag.is_virtual); + + if (!src.is_virtual) { + UVM_ASSERT(src.aperture == UVM_APERTURE_SYS); + UVM_ASSERT(auth_tag.aperture == UVM_APERTURE_SYS); + } + + if (!dst.is_virtual) + UVM_ASSERT(dst.aperture == UVM_APERTURE_VID); + + NV_PUSH_1U(C8B5, SET_SECURE_COPY_MODE, HWCONST(C8B5, SET_SECURE_COPY_MODE, MODE, DECRYPT)); + + auth_tag_address_hi32 = HWVALUE(C8B5, SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER, UPPER, NvU64_HI32(auth_tag.address)); + auth_tag_address_lo32 = HWVALUE(C8B5, SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER, LOWER, NvU64_LO32(auth_tag.address)); + + NV_PUSH_2U(C8B5, SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER, auth_tag_address_hi32, + SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER, auth_tag_address_lo32); + + encrypt_or_decrypt(push, dst, src, size); +} + diff --git a/kernel-open/nvidia-uvm/uvm_hopper_host.c b/kernel-open/nvidia-uvm/uvm_hopper_host.c index d24a236511..7fd2e4ca02 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper_host.c +++ b/kernel-open/nvidia-uvm/uvm_hopper_host.c @@ -391,10 +391,15 @@ void uvm_hal_hopper_host_set_gpfifo_pushbuffer_segment_base(NvU64 *fifo_entry, N *fifo_entry |= (NvU64)(HWCONST(C86F, GP_ENTRY1, OPCODE, SET_PB_SEGMENT_EXTENDED_BASE)) << 32; } -void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length) +void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag) { NvU64 fifo_entry_value; NvU64 pb_low_bits_mask = (1ull << 40) - 1; + const NvU32 sync_value = (sync_flag == UVM_GPFIFO_SYNC_WAIT) ? HWCONST(C86F, GP_ENTRY1, SYNC, WAIT) : + HWCONST(C86F, GP_ENTRY1, SYNC, PROCEED); UVM_ASSERT(!uvm_global_is_suspended()); UVM_ASSERT_MSG(IS_ALIGNED(pushbuffer_va, 4), "pushbuffer va unaligned: %llu\n", pushbuffer_va); @@ -406,7 +411,8 @@ void uvm_hal_hopper_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va pushbuffer_va &= pb_low_bits_mask; fifo_entry_value = HWVALUE(C86F, GP_ENTRY0, GET, NvU64_LO32(pushbuffer_va) >> 2); fifo_entry_value |= (NvU64)(HWVALUE(C86F, GP_ENTRY1, GET_HI, NvU64_HI32(pushbuffer_va)) | - HWVALUE(C86F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2)) << 32; + HWVALUE(C86F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2) | + sync_value) << 32; *fifo_entry = fifo_entry_value; } diff --git a/kernel-open/nvidia-uvm/uvm_hopper_sec2.c b/kernel-open/nvidia-uvm/uvm_hopper_sec2.c new file mode 100644 index 0000000000..2184c8a780 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_hopper_sec2.c @@ -0,0 +1,212 @@ +/******************************************************************************* + Copyright (c) 2022-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_hal.h" +#include "uvm_hal_types.h" +#include "uvm_push.h" +#include "uvm_push_macros.h" +#include "nv_uvm_types.h" +#include "nv_uvm_interface.h" +#include "clcba2.h" +#include "clc86f.h" +#include "clb06f.h" + +#define UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES (1 << HWSHIFT(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA)) + +static void sign_push(uvm_push_t *push, NvU32 *init_method, NvU8 *auth_tag) +{ + NvU32 *sign_input_buf = push->begin + UVM_METHOD_SIZE / sizeof(*push->begin); + NvU32 sign_size = 0; + NV_STATUS status; + + UVM_ASSERT(init_method < push->next); + + while (init_method < push->next) { + NvU8 subch = READ_HWVALUE(*init_method, B06F, DMA, METHOD_SUBCHANNEL); + NvU32 count = READ_HWVALUE(*init_method, B06F, DMA, METHOD_COUNT); + + if (subch == UVM_SUBCHANNEL_CBA2) { + NvU32 method_addr = READ_HWVALUE(*init_method, B06F, DMA, METHOD_ADDRESS) << 2; + + UVM_ASSERT(count == 1); + UVM_ASSERT((sign_size + 2) * UVM_METHOD_SIZE <= UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE); + + sign_input_buf[sign_size] = method_addr; + sign_input_buf[sign_size + 1] = init_method[1]; + + // We consume the method address and the method data from the input, + // we advance the sign_input_buf by 2. + sign_size += 2; + } + + init_method += (count + 1); + } + + UVM_ASSERT(sign_size > 0); + + status = nvUvmInterfaceCslSign(&push->channel->csl.ctx, + sign_size * UVM_METHOD_SIZE, + (NvU8 *)sign_input_buf, + auth_tag); + + UVM_ASSERT_MSG(status == NV_OK, + "Failure to sign method stream auth tag, err: %s, GPU: %s.\n", + nvstatusToString(status), + uvm_gpu_name(uvm_push_get_gpu(push))); +} + +void uvm_hal_hopper_sec2_init(uvm_push_t *push) +{ + // Commonly, we would push a SET_OBJECT HOPPER_SEC2_WORK_LAUNCH_A in the + // init function. During channel initialization, this method would be sent + // to ESCHED to notify the expected SEC2 class ID. ESCHED forwards this + // method to the SEC2 engine. SEC2 is not guaranteed to support the + // SET_OBJECT method, so we shouldn't submit it. +} + +void uvm_hal_hopper_sec2_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + NvU32 sem_lo; + NvU32 flush_value; + NvU8 *sign_auth_tag_ptr; + NvU32 sign_auth_tag_addr_lo; + uvm_gpu_address_t sign_auth_tag_gpu_va; + NvU32 *csl_sign_init = push->next; + + UVM_ASSERT(IS_ALIGNED(NvU64_LO32(gpu_va), 1 << HWSHIFT(CBA2, SEMAPHORE_B, LOWER))); + + sem_lo = READ_HWVALUE(NvU64_LO32(gpu_va), CBA2, SEMAPHORE_B, LOWER); + + flush_value = uvm_hal_membar_before_semaphore(push) ? HWCONST(CBA2, SEMAPHORE_D, FLUSH_DISABLE, FALSE) : + HWCONST(CBA2, SEMAPHORE_D, FLUSH_DISABLE, TRUE); + + // The push and the method stream signature have the same lifetime, we + // reserve space in the pushbuffer to store the signature. After the push is + // processed by the GPU, the pushbuffer is recycled entirely, including the + // signature buffer. + sign_auth_tag_ptr = uvm_push_get_single_inline_buffer(push, + UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES, + UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES, + &sign_auth_tag_gpu_va); + + NV_PUSH_1U(CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_HI, + HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_HI, DATA, NvU64_HI32(sign_auth_tag_gpu_va.address))); + + sign_auth_tag_addr_lo = READ_HWVALUE(NvU64_LO32(sign_auth_tag_gpu_va.address), + CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_LO, + DATA); + NV_PUSH_1U(CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_LO, + HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA, sign_auth_tag_addr_lo)); + + NV_PUSH_1U(CBA2, SEMAPHORE_A, HWVALUE(CBA2, SEMAPHORE_A, UPPER, NvU64_HI32(gpu_va))); + NV_PUSH_1U(CBA2, SEMAPHORE_B, HWVALUE(CBA2, SEMAPHORE_B, LOWER, sem_lo)); + NV_PUSH_1U(CBA2, SET_SEMAPHORE_PAYLOAD_LOWER, payload); + + NV_PUSH_1U(CBA2, SEMAPHORE_D, HWCONST(CBA2, SEMAPHORE_D, TIMESTAMP, DISABLE) | + HWCONST(CBA2, SEMAPHORE_D, PAYLOAD_SIZE, 32_BIT) | + flush_value); + + sign_push(push, csl_sign_init, sign_auth_tag_ptr); +} + +void uvm_hal_hopper_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va) +{ + // TODO: Bug 3804752: [uvm][HCC] Add support for Hopper SEC2 HAL in UVM. + // Semaphore_timestamp is not implemented in the SEC2 engine yet. We will + // add support in UVM when they become available. + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + UVM_ASSERT_MSG(false, "SEC2 semaphore_timestamp is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} + +static void execute_with_membar(uvm_push_t *push) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push); + + NvU32 flush_value = (membar == UVM_MEMBAR_SYS) ? HWCONST(CBA2, EXECUTE, FLUSH_DISABLE, FALSE) : + HWCONST(CBA2, EXECUTE, FLUSH_DISABLE, TRUE); + + NV_PUSH_1U(CBA2, EXECUTE, flush_value | + HWCONST(CBA2, EXECUTE, NOTIFY, DISABLE)); + + if (membar == UVM_MEMBAR_GPU) { + gpu->parent->host_hal->wait_for_idle(push); + gpu->parent->host_hal->membar_gpu(push); + } +} + +void uvm_hal_hopper_sec2_decrypt(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, NvU32 size, NvU64 auth_tag_va) +{ + NvU8 *sign_auth_tag_ptr; + NvU32 sign_auth_tag_addr_lo; + uvm_gpu_address_t sign_auth_tag_gpu_va; + NvU32 *csl_sign_init = push->next; + + // Check that the provided alignment matches HW + BUILD_BUG_ON(UVM_CONF_COMPUTING_BUF_ALIGNMENT < (1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA))); + BUILD_BUG_ON(UVM_CONF_COMPUTING_BUF_ALIGNMENT % (1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA)) != 0); + + // No overlapping. + UVM_ASSERT(!uvm_ranges_overlap(src_va, src_va + size - 1, dst_va, dst_va + size - 1)); + + // Alignment requirements. + UVM_ASSERT(IS_ALIGNED(NvU64_LO32(src_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_SRC_ADDR_LO, DATA))); + UVM_ASSERT(IS_ALIGNED(NvU64_LO32(dst_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA))); + UVM_ASSERT(IS_ALIGNED(NvU64_LO32(auth_tag_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_LO, DATA))); + UVM_ASSERT(IS_ALIGNED(size, 1 << HWSHIFT(CBA2, DECRYPT_COPY_SIZE, DATA))); + + // See comments in SEC2 semaphore_release. + sign_auth_tag_ptr = uvm_push_get_single_inline_buffer(push, + UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES, + UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES, + &sign_auth_tag_gpu_va); + + NV_PUSH_1U(CBA2, DECRYPT_COPY_SRC_ADDR_HI, NvU64_HI32(src_va)); + NV_PUSH_1U(CBA2, DECRYPT_COPY_SRC_ADDR_LO, NvU64_LO32(src_va)); + + NV_PUSH_1U(CBA2, DECRYPT_COPY_DST_ADDR_HI, NvU64_HI32(dst_va)); + NV_PUSH_1U(CBA2, DECRYPT_COPY_DST_ADDR_LO, NvU64_LO32(dst_va)); + + NV_PUSH_1U(CBA2, DECRYPT_COPY_SIZE, size); + NV_PUSH_1U(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_HI, NvU64_HI32(auth_tag_va)); + NV_PUSH_1U(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_LO, NvU64_LO32(auth_tag_va)); + + NV_PUSH_1U(CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_HI, + HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_HI, DATA, NvU64_HI32(sign_auth_tag_gpu_va.address))); + + sign_auth_tag_addr_lo = READ_HWVALUE(NvU64_LO32(sign_auth_tag_gpu_va.address), + CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_LO, + DATA); + NV_PUSH_1U(CBA2, + METHOD_STREAM_AUTH_TAG_ADDR_LO, + HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA, sign_auth_tag_addr_lo)); + + execute_with_membar(push); + + sign_push(push, csl_sign_init, sign_auth_tag_ptr); +} diff --git a/kernel-open/nvidia-uvm/uvm_ioctl.h b/kernel-open/nvidia-uvm/uvm_ioctl.h index 9459759a42..b0f291b421 100644 --- a/kernel-open/nvidia-uvm/uvm_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_ioctl.h @@ -1048,6 +1048,41 @@ typedef struct NV_STATUS rmStatus; // OUT } UVM_MAP_EXTERNAL_SPARSE_PARAMS; +// +// Used to initialise a secondary UVM file-descriptor which holds a +// reference on the memory map to prevent it being torn down without +// first notifying UVM. This is achieved by preventing mmap() calls on +// the secondary file-descriptor so that on process exit +// uvm_mm_release() will be called while the memory map is present +// such that UVM can cleanly shutdown the GPU by handling faults +// instead of cancelling them. +// +// This ioctl must be called after the primary file-descriptor has +// been initialised with the UVM_INITIALIZE ioctl. The primary FD +// should be passed in the uvmFd field and the UVM_MM_INITIALIZE ioctl +// will hold a reference on the primary FD. Therefore uvm_release() is +// guaranteed to be called after uvm_mm_release(). +// +// Once this file-descriptor has been closed the UVM context is +// effectively dead and subsequent operations requiring a memory map +// will fail. Calling UVM_MM_INITIALIZE on a context that has already +// been initialized via any FD will return NV_ERR_INVALID_STATE. +// +// Calling this with a non-UVM file-descriptor in uvmFd will return +// NV_ERR_INVALID_ARGUMENT. Calling this on the same file-descriptor +// as UVM_INITIALIZE or more than once on the same FD will return +// NV_ERR_IN_USE. +// +// Not all platforms require this secondary file-descriptor. On those +// platforms NV_WARN_NOTHING_TO_DO will be returned and users may +// close the file-descriptor at anytime. +#define UVM_MM_INITIALIZE UVM_IOCTL_BASE(75) +typedef struct +{ + NvS32 uvmFd; // IN + NV_STATUS rmStatus; // OUT +} UVM_MM_INITIALIZE_PARAMS; + // // Temporary ioctls which should be removed before UVM 8 release // Number backwards from 2047 - highest custom ioctl function number diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index 561af31fa4..96e20195d3 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -540,6 +540,7 @@ typedef struct #endif // NV_IS_EXPORT_SYMBOL_PRESENT_int_active_memcg #if defined(NVCPU_X86) || defined(NVCPU_X86_64) + #include #include #endif @@ -547,6 +548,27 @@ typedef struct #define PAGE_KERNEL_NOENC PAGE_KERNEL #endif +// uvm_pgprot_decrypted is a GPL-aware version of pgprot_decrypted that returns +// the given input when UVM cannot use GPL symbols, or pgprot_decrypted is not +// defined. Otherwise, the function is equivalent to pgprot_decrypted. UVM only +// depends on pgprot_decrypted when the driver is allowed to use GPL symbols: +// both AMD's SEV and Intel's TDX are only supported in conjunction with OpenRM. +// +// It is safe to invoke uvm_pgprot_decrypted in KVM + AMD SEV-SNP guests, even +// if the call is not required, because pgprot_decrypted(PAGE_KERNEL_NOENC) == +// PAGE_KERNEL_NOENC. +// +// pgprot_decrypted was added by commit 21729f81ce8a ("x86/mm: Provide general +// kernel support for memory encryption") in v4.14 (2017-07-18) +static inline pgprot_t uvm_pgprot_decrypted(pgprot_t prot) +{ +#if defined(pgprot_decrypted) + return pgprot_decrypted(prot); +#endif + + return prot; +} + // Commit 1dff8083a024650c75a9c961c38082473ceae8cf (v4.7). // // Archs with CONFIG_MMU should have their own page.h, and can't include diff --git a/kernel-open/nvidia-uvm/uvm_lock.c b/kernel-open/nvidia-uvm/uvm_lock.c index b4b101baab..4b6c846d56 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.c +++ b/kernel-open/nvidia-uvm/uvm_lock.c @@ -27,7 +27,7 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) { - BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 26); + BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 33); switch (lock_order) { UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_INVALID); @@ -43,18 +43,25 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_GPU_SEMAPHORE_POOL); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_RM_API); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_RM_GPUS); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_BLOCK_MIGRATE); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_BLOCK); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CHUNK_MAPPING); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PAGE_TREE); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CSL_PUSH); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CSL_WLC_PUSH); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CSL_SEC2_PUSH); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PUSH); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM_PMA); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_PMM_ROOT_CHUNK); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CHANNEL); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_WLC_CHANNEL); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_SPACE_EVENTS); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_SPACE_TOOLS); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_SEMA_POOL_TRACKER); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_SECURE_SEMAPHORE); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_LEAF); UVM_ENUM_STRING_DEFAULT(); } diff --git a/kernel-open/nvidia-uvm/uvm_lock.h b/kernel-open/nvidia-uvm/uvm_lock.h index 570a4ec465..55af421387 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.h +++ b/kernel-open/nvidia-uvm/uvm_lock.h @@ -279,6 +279,14 @@ // Operations not allowed while holding the lock: // - GPU memory allocation which can evict memory (would require nesting // block locks) +// - GPU DMA Allocation pool lock (gpu->conf_computing.dma_buffer_pool.lock) +// Order: UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL +// Exclusive lock (mutex) +// +// Protects: +// - Protect the state of the uvm_conf_computing_dma_buffer_pool_t +// when the Confidential Computing feature is enabled on the system. +// // - Chunk mapping lock (gpu->root_chunk_mappings.bitlocks and // gpu->sysmem_mappings.bitlock) // Order: UVM_LOCK_ORDER_CHUNK_MAPPING @@ -313,6 +321,58 @@ // Operations not allowed while holding this lock // - GPU memory allocation which can evict // +// - Secure channel CSL channel pool semaphore +// Order: UVM_LOCK_ORDER_CSL_PUSH +// Semaphore per SEC2 channel pool +// +// The semaphore controls concurrent pushes to secure channels. Secure work +// submission depends on channel availability in GPFIFO entries (as in any +// other channel type) but also on channel locking. Each secure channel has a +// lock to enforce ordering of pushes. The channel's CSL lock is taken on +// channel reservation until uvm_push_end. Secure channels are stateful +// channels and the CSL lock protects their CSL state/context. +// +// Operations allowed while holding this lock +// - Pushing work to CE secure channels +// +// - WLC CSL channel pool semaphore +// Order: UVM_LOCK_ORDER_CSL_WLC_PUSH +// Semaphore per WLC channel pool +// +// The semaphore controls concurrent pushes to WLC channels. WLC work +// submission depends on channel availability in GPFIFO entries (as in any +// other channel type) but also on channel locking. Each WLC channel has a +// lock to enforce ordering of pushes. The channel's CSL lock is taken on +// channel reservation until uvm_push_end. SEC2 channels are stateful +// channels and the CSL lock protects their CSL state/context. +// +// This lock ORDER is different and sits below generic secure channel CSL +// lock and above SEC2 CSL lock. This reflects the dual nature of WLC +// channels; they use SEC2 indirect work launch during initialization, +// and after their schedule is initialized they provide indirect launch +// functionality to other CE channels. +// +// Operations allowed while holding this lock +// - Pushing work to WLC channels +// +// - SEC2 CSL channel pool semaphore +// Order: UVM_LOCK_ORDER_SEC2_CSL_PUSH +// Semaphore per SEC2 channel pool +// +// The semaphore controls concurrent pushes to SEC2 channels. SEC2 work +// submission depends on channel availability in GPFIFO entries (as in any +// other channel type) but also on channel locking. Each SEC2 channel has a +// lock to enforce ordering of pushes. The channel's CSL lock is taken on +// channel reservation until uvm_push_end. SEC2 channels are stateful +// channels and the CSL lock protects their CSL state/context. +// +// This lock ORDER is different and lower than the generic secure channel +// lock to allow secure work submission to use a SEC2 channel to submit +// work before releasing the CSL lock of the originating secure channel. +// +// Operations allowed while holding this lock +// - Pushing work to SEC2 channels +// // - Concurrent push semaphore // Order: UVM_LOCK_ORDER_PUSH // Semaphore (uvm_semaphore_t) @@ -346,6 +406,15 @@ // channel pool lock documentation contains the guidelines about which lock // type (mutex or spinlock) to use. // +// - WLC Channel lock +// Order: UVM_LOCK_ORDER_WLC_CHANNEL +// Spinlock (uvm_spinlock_t) +// +// Lock protecting the state of WLC channels in a channel pool. This lock +// is separate from the above generic channel lock to allow for indirect +// worklaunch pushes while holding the main channel lock. +// (WLC pushes don't need any of the pushbuffer locks described above) +// // - Tools global VA space list lock (g_tools_va_space_list_lock) // Order: UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST // Reader/writer lock (rw_sempahore) @@ -366,6 +435,12 @@ // events come from perf events, both VA_SPACE_EVENTS and VA_SPACE_TOOLS // must be taken to register/report some tools events. // +// - Tracking semaphores +// Order: UVM_LOCK_ORDER_SECURE_SEMAPHORE +// When the Confidential Computing feature is enabled, CE semaphores are +// encrypted, and require to take the CSL lock (UVM_LOCK_ORDER_LEAF) to +// decrypt the payload. +// // - Leaf locks // Order: UVM_LOCK_ORDER_LEAF // @@ -390,18 +465,25 @@ typedef enum UVM_LOCK_ORDER_GPU_SEMAPHORE_POOL, UVM_LOCK_ORDER_RM_API, UVM_LOCK_ORDER_RM_GPUS, + UVM_LOCK_ORDER_VA_BLOCK_MIGRATE, UVM_LOCK_ORDER_VA_BLOCK, + UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL, UVM_LOCK_ORDER_CHUNK_MAPPING, UVM_LOCK_ORDER_PAGE_TREE, + UVM_LOCK_ORDER_CSL_PUSH, + UVM_LOCK_ORDER_CSL_WLC_PUSH, + UVM_LOCK_ORDER_CSL_SEC2_PUSH, UVM_LOCK_ORDER_PUSH, UVM_LOCK_ORDER_PMM, UVM_LOCK_ORDER_PMM_PMA, UVM_LOCK_ORDER_PMM_ROOT_CHUNK, UVM_LOCK_ORDER_CHANNEL, + UVM_LOCK_ORDER_WLC_CHANNEL, UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST, UVM_LOCK_ORDER_VA_SPACE_EVENTS, UVM_LOCK_ORDER_VA_SPACE_TOOLS, UVM_LOCK_ORDER_SEMA_POOL_TRACKER, + UVM_LOCK_ORDER_SECURE_SEMAPHORE, UVM_LOCK_ORDER_LEAF, UVM_LOCK_ORDER_COUNT, } uvm_lock_order_t; @@ -914,9 +996,10 @@ typedef struct // be the same as the string passed to "spinlock". // See uvm_spin_lock() and uvm_spin_unlock() below as examples. // -#define uvm_assert_spinlock_locked(spinlock) ({ \ - typeof(spinlock) _lock_ = (spinlock); \ - UVM_ASSERT(spin_is_locked(&_lock_->lock) && uvm_check_locked(_lock_, UVM_LOCK_FLAGS_MODE_EXCLUSIVE)); \ +#define uvm_assert_spinlock_locked(spinlock) ({ \ + typeof(spinlock) _lock_ = (spinlock); \ + UVM_ASSERT(spin_is_locked(&_lock_->lock)); \ + UVM_ASSERT(uvm_check_locked(_lock_, UVM_LOCK_FLAGS_MODE_EXCLUSIVE)); \ }) #define uvm_assert_spinlock_unlocked(spinlock) UVM_ASSERT(!spin_is_locked(&(spinlock)->lock)) diff --git a/kernel-open/nvidia-uvm/uvm_maxwell.c b/kernel-open/nvidia-uvm/uvm_maxwell.c index 6f80a6a652..b6ccf39626 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell.c @@ -33,11 +33,13 @@ void uvm_hal_maxwell_arch_init_properties(uvm_parent_gpu_t *parent_gpu) // space for UVM internal mappings. // A single top level PDE covers 64 or 128 MB on Maxwell so 128 GB is fine to use. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1GB; - parent_gpu->uvm_mem_va_base = 768ull * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 768 * UVM_SIZE_1GB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + // We don't have a compelling use case in UVM-Lite for direct peer // migrations between GPUs, so don't bother setting them up. parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_UNSUPPORTED; diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_ce.c b/kernel-open/nvidia-uvm/uvm_maxwell_ce.c index 6144bb46b6..6e052b8235 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_ce.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_ce.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021-2022 NVIDIA Corporation + Copyright (c) 2021-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -29,10 +29,10 @@ void uvm_hal_maxwell_ce_init(uvm_push_t *push) { // Notably this sends SET_OBJECT with the CE class on subchannel 0 instead - // of the recommended by HW subchannel 4 (subchannel 4 is recommended to + // of the recommended by HW subchannel 4 (subchannel 4 is required to // match CE usage on GRCE). For the UVM driver using subchannel 0 has the - // benefit of also verifying that we ended up on the right PBDMA though as - // SET_OBJECT with CE class on subchannel 0 would fail on GRCE. + // benefit of also verifying that we ended up on the right CE engine type + // though as SET_OBJECT with CE class on subchannel 0 would fail on GRCE. NV_PUSH_1U(B06F, SET_OBJECT, uvm_push_get_gpu(push)->parent->rm_info.ceClass); } @@ -185,6 +185,12 @@ NvU32 uvm_hal_maxwell_ce_plc_mode(void) return 0; } +// Noop, since COPY_TYPE doesn't exist in Maxwell. +NvU32 uvm_hal_maxwell_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +{ + return 0; +} + void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size) { // If >4GB copies ever become an important use case, this function should @@ -195,6 +201,7 @@ void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu NvU32 pipelined_value; NvU32 launch_dma_src_dst_type; NvU32 launch_dma_plc_mode; + NvU32 copy_type_value; UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_is_valid(push, dst, src), "Memcopy validation failed in channel %s, GPU %s.\n", @@ -205,6 +212,7 @@ void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src); launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(push, dst, src); if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); @@ -226,6 +234,7 @@ void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu HWCONST(B0B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE) | launch_dma_src_dst_type | launch_dma_plc_mode | + copy_type_value | pipelined_value); pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); @@ -266,7 +275,7 @@ static void memset_common(uvm_push_t *push, uvm_gpu_address_t dst, size_t size, NvU32 launch_dma_dst_type; NvU32 launch_dma_plc_mode; - UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, memset_element_size), + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, size, memset_element_size), "Memset validation failed in channel %s, GPU %s.\n", push->channel->name, uvm_gpu_name(gpu)); @@ -352,3 +361,24 @@ void uvm_hal_maxwell_ce_memset_v_4(uvm_push_t *push, NvU64 dst_va, NvU32 value, uvm_push_get_gpu(push)->parent->ce_hal->memset_4(push, uvm_gpu_address_virtual(dst_va), value, size); } +void uvm_hal_maxwell_ce_encrypt_unsupported(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT_MSG(false, "CE encrypt is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} + +void uvm_hal_maxwell_ce_decrypt_unsupported(uvm_push_t *push, + uvm_gpu_address_t dst, + uvm_gpu_address_t src, + NvU32 size, + uvm_gpu_address_t auth_tag) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + UVM_ASSERT_MSG(false, "CE decrypt is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c b/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c index f5c9af6ce9..903fcfe0aa 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -62,6 +62,12 @@ NvU8 uvm_hal_maxwell_fault_buffer_get_ve_id_unsupported(NvU16 mmu_engine_id, uvm return 0; } +uvm_fault_type_t uvm_hal_maxwell_fault_buffer_get_fault_type_unsupported(const NvU32 *fault_entry) +{ + UVM_ASSERT_MSG(false, "fault_buffer_get_fault_type is not supported.\n"); + return UVM_FAULT_TYPE_COUNT; +} + void uvm_hal_maxwell_fault_buffer_parse_entry_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index, uvm_fault_buffer_entry_t *buffer_entry) diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_host.c b/kernel-open/nvidia-uvm/uvm_maxwell_host.c index 56d4b9e818..e8f47ec311 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_host.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_host.c @@ -217,9 +217,14 @@ void uvm_hal_maxwell_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) HWCONST(A16F, SEMAPHORED, RELEASE_WFI, DIS)); } -void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length) +void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag) { NvU64 fifo_entry_value; + const NvU32 sync_value = (sync_flag == UVM_GPFIFO_SYNC_WAIT) ? HWCONST(A16F, GP_ENTRY1, SYNC, WAIT) : + HWCONST(A16F, GP_ENTRY1, SYNC, PROCEED); UVM_ASSERT(!uvm_global_is_suspended()); UVM_ASSERT_MSG(pushbuffer_va % 4 == 0, "pushbuffer va unaligned: %llu\n", pushbuffer_va); @@ -228,7 +233,8 @@ void uvm_hal_maxwell_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_v fifo_entry_value = HWVALUE(A16F, GP_ENTRY0, GET, NvU64_LO32(pushbuffer_va) >> 2); fifo_entry_value |= (NvU64)(HWVALUE(A16F, GP_ENTRY1, GET_HI, NvU64_HI32(pushbuffer_va)) | HWVALUE(A16F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2) | - HWCONST(A16F, GP_ENTRY1, PRIV, KERNEL)) << 32; + HWCONST(A16F, GP_ENTRY1, PRIV, KERNEL) | + sync_value) << 32; *fifo_entry = fifo_entry_value; } diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_sec2.c b/kernel-open/nvidia-uvm/uvm_maxwell_sec2.c new file mode 100644 index 0000000000..5cc538b419 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_maxwell_sec2.c @@ -0,0 +1,53 @@ +/******************************************************************************* + Copyright (c) 2021-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_gpu.h" +#include "uvm_hal.h" +#include "uvm_push.h" +#include "uvm_common.h" + +void uvm_hal_maxwell_sec2_init_noop(uvm_push_t *push) +{ +} + +void uvm_hal_maxwell_sec2_semaphore_release_unsupported(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + UVM_ASSERT_MSG(false, "SEC2 semaphore_release is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} + +void uvm_hal_maxwell_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + UVM_ASSERT_MSG(false, "SEC2 semaphore_timestamp is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} + +void uvm_hal_maxwell_sec2_decrypt_unsupported(uvm_push_t *push, + NvU64 dst_va, + NvU64 src_va, + NvU32 size, + NvU64 auth_tag_va) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + UVM_ASSERT_MSG(false, "SEC2 decrypt is not supported on GPU: %s.\n", uvm_gpu_name(gpu)); +} diff --git a/kernel-open/nvidia-uvm/uvm_mem.c b/kernel-open/nvidia-uvm/uvm_mem.c index 4370af9443..5ba285c4b6 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_mem.c @@ -22,6 +22,7 @@ *******************************************************************************/ #include "uvm_mem.h" +#include "uvm_hal_types.h" #include "uvm_mmu.h" #include "uvm_processors.h" #include "uvm_va_space.h" @@ -67,26 +68,15 @@ static bool vidmem_can_be_mapped(uvm_mem_t *vidmem, bool is_user_space) return true; } -static bool sysmem_can_be_mapped(uvm_mem_t *sysmem) -{ - UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); - - // If SEV is enabled, only unprotected memory can be mapped - if (g_uvm_global.sev_enabled) - return uvm_mem_is_sysmem_dma(sysmem); - - return true; -} - static bool mem_can_be_mapped_on_cpu(uvm_mem_t *mem, bool is_user_space) { if (uvm_mem_is_sysmem(mem)) - return sysmem_can_be_mapped(mem); + return true; if (!vidmem_can_be_mapped(mem, is_user_space)) return false; - return mem->backing_gpu->parent->numa_info.enabled && PAGE_ALIGNED(mem->chunk_size); + return mem->backing_gpu->mem_info.numa.enabled && PAGE_ALIGNED(mem->chunk_size); } static bool mem_can_be_mapped_on_cpu_kernel(uvm_mem_t *mem) @@ -99,10 +89,21 @@ static bool mem_can_be_mapped_on_cpu_user(uvm_mem_t *mem) return mem_can_be_mapped_on_cpu(mem, true); } +static bool sysmem_can_be_mapped_on_gpu(uvm_mem_t *sysmem) +{ + UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); + + // If SEV is enabled, only unprotected memory can be mapped + if (g_uvm_global.sev_enabled) + return uvm_mem_is_sysmem_dma(sysmem); + + return true; +} + static bool mem_can_be_mapped_on_gpu(uvm_mem_t *mem, uvm_gpu_t *gpu, bool is_user_space) { if (uvm_mem_is_sysmem(mem)) - return sysmem_can_be_mapped(mem); + return sysmem_can_be_mapped_on_gpu(mem); if (!vidmem_can_be_mapped(mem, is_user_space)) return false; @@ -312,7 +313,7 @@ static NvU32 mem_pick_chunk_size(uvm_mem_t *mem) // When UVM_PAGE_SIZE_DEFAULT is used on NUMA-enabled GPUs, we force // chunk_size to be PAGE_SIZE at least, to allow CPU mappings. - if (mem->backing_gpu->parent->numa_info.enabled) + if (mem->backing_gpu->mem_info.numa.enabled) chunk_size = max(chunk_size, (NvU32)PAGE_SIZE); return chunk_size; @@ -449,6 +450,9 @@ static gfp_t sysmem_allocation_gfp_flags(int order, bool zero) return gfp_flags; } +// This allocation is a non-protected memory allocation under Confidential +// Computing. +// // There is a tighter coupling between allocation and mapping because of the // allocator UVM must use. Hence, this function does the equivalent of // uvm_mem_map_gpu_phys(). @@ -523,9 +527,10 @@ static NV_STATUS mem_alloc_sysmem_chunks(uvm_mem_t *mem, gfp_t gfp_flags) // In case of failure, the caller is required to handle cleanup by calling // uvm_mem_free -static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero, bool is_protected) +static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero, bool is_unprotected) { NV_STATUS status; + uvm_pmm_gpu_memory_type_t mem_type; UVM_ASSERT(uvm_mem_is_vidmem(mem)); @@ -542,14 +547,23 @@ static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero, bool is_prot if (!mem->vidmem.chunks) return NV_ERR_NO_MEMORY; - status = uvm_pmm_gpu_alloc_kernel(&mem->backing_gpu->pmm, - mem->chunks_count, - mem->chunk_size, - UVM_PMM_ALLOC_FLAGS_NONE, - mem->vidmem.chunks, - NULL); + // When CC is disabled the behavior is identical to that of PMM, and the + // protection flag is ignored (squashed by PMM internally). + if (is_unprotected) + mem_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED; + else + mem_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED; + + status = uvm_pmm_gpu_alloc(&mem->backing_gpu->pmm, + mem->chunks_count, + mem->chunk_size, + mem_type, + UVM_PMM_ALLOC_FLAGS_NONE, + mem->vidmem.chunks, + NULL); + if (status != NV_OK) { - UVM_ERR_PRINT("pmm_gpu_alloc(count=%zd, size=0x%x) failed: %s\n", + UVM_ERR_PRINT("uvm_pmm_gpu_alloc (count=%zd, size=0x%x) failed: %s\n", mem->chunks_count, mem->chunk_size, nvstatusToString(status)); @@ -559,7 +573,7 @@ static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero, bool is_prot return NV_OK; } -static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zero, bool is_protected) +static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zero, bool is_unprotected) { if (uvm_mem_is_sysmem(mem)) { gfp_t gfp_flags; @@ -581,7 +595,7 @@ static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zer return status; } - return mem_alloc_vidmem_chunks(mem, zero, is_protected); + return mem_alloc_vidmem_chunks(mem, zero, is_unprotected); } NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_global_processor_mask_t *mask) @@ -611,7 +625,7 @@ NV_STATUS uvm_mem_alloc(const uvm_mem_alloc_params_t *params, uvm_mem_t **mem_ou NV_STATUS status; NvU64 physical_size; uvm_mem_t *mem = NULL; - bool is_protected = false; + bool is_unprotected = false; UVM_ASSERT(params->size > 0); @@ -633,7 +647,12 @@ NV_STATUS uvm_mem_alloc(const uvm_mem_alloc_params_t *params, uvm_mem_t **mem_ou physical_size = UVM_ALIGN_UP(mem->size, mem->chunk_size); mem->chunks_count = physical_size / mem->chunk_size; - status = mem_alloc_chunks(mem, params->mm, params->zero, is_protected); + if (params->is_unprotected) + UVM_ASSERT(uvm_mem_is_vidmem(mem)); + + is_unprotected = params->is_unprotected; + + status = mem_alloc_chunks(mem, params->mm, params->zero, is_unprotected); if (status != NV_OK) goto error; @@ -718,8 +737,8 @@ static NV_STATUS mem_map_cpu_to_sysmem_kernel(uvm_mem_t *mem) pages[page_index] = mem_cpu_page(mem, page_index * PAGE_SIZE); } - if (g_uvm_global.sev_enabled) - prot = PAGE_KERNEL_NOENC; + if (g_uvm_global.sev_enabled && uvm_mem_is_sysmem_dma(mem)) + prot = uvm_pgprot_decrypted(PAGE_KERNEL_NOENC); mem->kernel.cpu_addr = vmap(pages, num_pages, VM_MAP, prot); @@ -982,7 +1001,7 @@ uvm_gpu_address_t uvm_mem_gpu_address_copy(uvm_mem_t *mem, uvm_gpu_t *accessing_ UVM_ASSERT(uvm_mem_is_physically_contiguous(mem, offset, size)); if (uvm_mem_is_sysmem(mem) || uvm_mem_is_local_vidmem(mem, accessing_gpu)) - return uvm_mem_gpu_address_physical(mem, accessing_gpu, offset, size); + return uvm_gpu_address_copy(accessing_gpu, uvm_mem_gpu_physical(mem, accessing_gpu, offset, size)); // Peer GPUs may need to use some form of translation (identity mappings, // indirect peers) to copy. @@ -1041,6 +1060,16 @@ static NV_STATUS mem_map_gpu(uvm_mem_t *mem, page_size = mem_pick_gpu_page_size(mem, gpu, tree); UVM_ASSERT_MSG(uvm_mmu_page_size_supported(tree, page_size), "page_size 0x%x\n", page_size); + // When the Confidential Computing feature is enabled, DMA allocations are + // majoritarily allocated and managed by a per-GPU DMA buffer pool + // (uvm_conf_computing_dma_buffer_pool_t). Because we would typically + // already hold the DMA_BUFFER_POOL lock at this time, we cannot hold + // the block lock. Allocate PTEs without eviction in this context. + // + // See uvm_pmm_gpu_alloc() + if (uvm_mem_is_sysmem_dma(mem)) + pmm_flags = UVM_PMM_ALLOC_FLAGS_NONE; + status = uvm_page_table_range_vec_create(tree, gpu_va, uvm_mem_physical_size(mem), @@ -1205,7 +1234,7 @@ void uvm_mem_unmap_gpu_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) static bool mem_can_be_phys_mapped_on_gpu(uvm_mem_t *mem, uvm_gpu_t *gpu) { if (uvm_mem_is_sysmem(mem)) - return sysmem_can_be_mapped(mem); + return sysmem_can_be_mapped_on_gpu(mem); else return uvm_mem_is_local_vidmem(mem, gpu); } @@ -1306,10 +1335,16 @@ NvU64 uvm_mem_get_gpu_va_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) uvm_gpu_address_t uvm_mem_gpu_address_virtual_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) { - return uvm_gpu_address_virtual(uvm_mem_get_gpu_va_kernel(mem, gpu)); + uvm_gpu_address_t addr = uvm_gpu_address_virtual(uvm_mem_get_gpu_va_kernel(mem, gpu)); + if (uvm_conf_computing_mode_enabled(gpu) && mem->dma_owner) + addr.is_unprotected = true; + return addr; } uvm_gpu_address_t uvm_mem_gpu_address_physical(uvm_mem_t *mem, uvm_gpu_t *gpu, NvU64 offset, NvU64 size) { - return uvm_gpu_address_from_phys(uvm_mem_gpu_physical(mem, gpu, offset, size)); + uvm_gpu_address_t addr = uvm_gpu_address_from_phys(uvm_mem_gpu_physical(mem, gpu, offset, size)); + if (uvm_conf_computing_mode_enabled(gpu) && mem->dma_owner) + addr.is_unprotected = true; + return addr; } diff --git a/kernel-open/nvidia-uvm/uvm_mem.h b/kernel-open/nvidia-uvm/uvm_mem.h index 7dba2f1216..74bd80a42e 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_mem.h @@ -86,7 +86,7 @@ // The size of the VA used for mapping uvm_mem_t allocations // 128 GBs should be plenty for internal allocations and fits easily on all // supported architectures. -#define UVM_MEM_VA_SIZE (128ull * 1024 * 1024 * 1024) +#define UVM_MEM_VA_SIZE (128 * UVM_SIZE_1GB) typedef struct { @@ -128,6 +128,11 @@ typedef struct // has to be aligned to PAGE_SIZE. NvU32 page_size; + // The protection flag is only observed for vidmem allocations when CC is + // enabled. If set to true, the allocation returns unprotected vidmem; + // otherwise, the allocation returns protected vidmem. + bool is_unprotected; + // If true, the allocation is zeroed (scrubbed). bool zero; } uvm_mem_alloc_params_t; @@ -161,6 +166,8 @@ struct uvm_mem_struct // lifetime of the GPU. For CPU allocations there is no lifetime limitation. uvm_gpu_t *backing_gpu; + // For Confidential Computing, the accessing GPU needs to be known at alloc + // time for sysmem allocations. uvm_gpu_t *dma_owner; union @@ -385,6 +392,12 @@ static NV_STATUS uvm_mem_alloc_vidmem(NvU64 size, uvm_gpu_t *gpu, uvm_mem_t **me return uvm_mem_alloc(¶ms, mem_out); } +// Helper for allocating protected vidmem with the default page size +static NV_STATUS uvm_mem_alloc_vidmem_protected(NvU64 size, uvm_gpu_t *gpu, uvm_mem_t **mem_out) +{ + return uvm_mem_alloc_vidmem(size, gpu, mem_out); +} + // Helper for allocating sysmem and mapping it on the CPU static NV_STATUS uvm_mem_alloc_sysmem_and_map_cpu_kernel(NvU64 size, struct mm_struct *mm, uvm_mem_t **mem_out) { diff --git a/kernel-open/nvidia-uvm/uvm_mem_test.c b/kernel-open/nvidia-uvm/uvm_mem_test.c index 787063cf57..0c7fd7a1eb 100644 --- a/kernel-open/nvidia-uvm/uvm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_mem_test.c @@ -25,6 +25,7 @@ #include "uvm_kvmalloc.h" #include "uvm_mem.h" #include "uvm_push.h" +#include "uvm_conf_computing.h" #include "uvm_test.h" #include "uvm_test_ioctl.h" #include "uvm_va_space.h" @@ -80,17 +81,14 @@ static NV_STATUS check_accessible_from_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem) for (offset = 0; offset < verif_size; offset += mem->chunk_size) { uvm_gpu_address_t sys_mem_gpu_address, mem_gpu_address; size_t size_this_time = min((NvU64)mem->chunk_size, verif_size - offset); - bool should_use_pa; TEST_NV_CHECK_GOTO(uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_CPU_TO_GPU, &push, " "), done); sys_mem_gpu_address = uvm_mem_gpu_address_virtual_kernel(sys_mem, gpu); sys_mem_gpu_address.address += offset; - should_use_pa = uvm_channel_is_privileged(push.channel); - - if (should_use_pa) { - mem_gpu_address = uvm_mem_gpu_address_physical(mem, gpu, offset, size_this_time); + if (uvm_channel_is_privileged(push.channel)) { + mem_gpu_address = uvm_mem_gpu_address_copy(mem, gpu, offset, size_this_time); } else { mem_gpu_address = uvm_mem_gpu_address_virtual_kernel(mem, gpu); @@ -130,7 +128,7 @@ static NV_STATUS check_accessible_from_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem) mem_gpu_address.address += offset; if (uvm_channel_is_privileged(push.channel)) { - sys_mem_gpu_address = uvm_mem_gpu_address_physical(sys_mem, gpu, offset, size_this_time); + sys_mem_gpu_address = uvm_mem_gpu_address_copy(sys_mem, gpu, offset, size_this_time); } else { sys_mem_gpu_address = uvm_mem_gpu_address_virtual_kernel(sys_mem, gpu); @@ -212,7 +210,7 @@ static NV_STATUS test_map_cpu(uvm_mem_t *mem) char *cpu_addr; if (uvm_mem_is_vidmem(mem)) - UVM_ASSERT(mem->backing_gpu->parent->numa_info.enabled); + UVM_ASSERT(mem->backing_gpu->mem_info.numa.enabled); // Map TEST_NV_CHECK_RET(uvm_mem_map_cpu_kernel(mem)); @@ -315,7 +313,7 @@ static NV_STATUS test_alloc_vidmem(uvm_gpu_t *gpu, NvU32 page_size, size_t size, TEST_CHECK_GOTO(status == NV_OK, error); if (page_size == UVM_PAGE_SIZE_DEFAULT) { - if (gpu->parent->numa_info.enabled) + if (gpu->mem_info.numa.enabled) TEST_CHECK_GOTO(mem->chunk_size >= PAGE_SIZE && mem->chunk_size <= max(size, (size_t)PAGE_SIZE), error); else TEST_CHECK_GOTO(mem->chunk_size == UVM_PAGE_SIZE_4K || mem->chunk_size <= size, error); @@ -323,7 +321,7 @@ static NV_STATUS test_alloc_vidmem(uvm_gpu_t *gpu, NvU32 page_size, size_t size, TEST_NV_CHECK_GOTO(test_map_gpu(mem, gpu), error); - if (gpu->parent->numa_info.enabled && (page_size == UVM_PAGE_SIZE_DEFAULT || page_size >= PAGE_SIZE)) + if (gpu->mem_info.numa.enabled && (page_size == UVM_PAGE_SIZE_DEFAULT || page_size >= PAGE_SIZE)) TEST_CHECK_GOTO(test_map_cpu(mem) == NV_OK, error); *mem_out = mem; @@ -371,6 +369,11 @@ static NV_STATUS test_all(uvm_va_space_t *va_space) int i; + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(uvm_va_space_find_first_gpu(va_space))) + return NV_OK; + gpu_count = uvm_processor_mask_get_gpu_count(&va_space->registered_gpus); // +1 for the CPU @@ -469,7 +472,7 @@ static NV_STATUS test_basic_vidmem(uvm_gpu_t *gpu) page_sizes &= UVM_CHUNK_SIZES_MASK; for_each_page_size(page_size, page_sizes) { TEST_CHECK_GOTO(uvm_mem_alloc_vidmem(page_size - 1, gpu, &mem) == NV_OK, done); - if (gpu->parent->numa_info.enabled) + if (gpu->mem_info.numa.enabled) TEST_CHECK_GOTO(mem->chunk_size >= PAGE_SIZE && mem->chunk_size <= max(page_size, (NvU32)PAGE_SIZE), done); else TEST_CHECK_GOTO(mem->chunk_size < page_size || page_size == smallest_page_size, done); @@ -477,7 +480,7 @@ static NV_STATUS test_basic_vidmem(uvm_gpu_t *gpu) mem = NULL; TEST_CHECK_GOTO(uvm_mem_alloc_vidmem(page_size, gpu, &mem) == NV_OK, done); - if (gpu->parent->numa_info.enabled) + if (gpu->mem_info.numa.enabled) TEST_CHECK_GOTO(mem->chunk_size == max(page_size, (NvU32)PAGE_SIZE), done); else TEST_CHECK_GOTO(mem->chunk_size == page_size, done); @@ -493,6 +496,41 @@ static NV_STATUS test_basic_vidmem(uvm_gpu_t *gpu) return status; } +static NV_STATUS test_basic_vidmem_unprotected(uvm_gpu_t *gpu) +{ + NV_STATUS status = NV_OK; + uvm_mem_t *mem = NULL; + + uvm_mem_alloc_params_t params = { 0 }; + params.size = UVM_PAGE_SIZE_4K; + params.backing_gpu = gpu; + params.page_size = UVM_PAGE_SIZE_4K; + + // If CC is enabled, the protection flag is observed. Because currently all + // vidmem is in the protected region, the allocation should succeed. + // + // If CC is disabled, the protection flag is ignored. + params.is_unprotected = false; + TEST_NV_CHECK_RET(uvm_mem_alloc(¶ms, &mem)); + + uvm_mem_free(mem); + mem = NULL; + + // If CC is enabled, the allocation should fail because currently the + // unprotected region is empty. + // + // If CC is disabled, the behavior should be identical to that of a + // protected allocation. + params.is_unprotected = true; + if (uvm_conf_computing_mode_enabled(gpu)) + TEST_CHECK_RET(uvm_mem_alloc(¶ms, &mem) == NV_ERR_NO_MEMORY); + else + TEST_NV_CHECK_RET(uvm_mem_alloc(¶ms, &mem)); + + uvm_mem_free(mem); + return status; +} + static NV_STATUS test_basic_sysmem(void) { NV_STATUS status = NV_OK; @@ -531,15 +569,54 @@ static NV_STATUS test_basic_sysmem_dma(uvm_gpu_t *gpu) return status; } +static NV_STATUS test_basic_dma_pool(uvm_gpu_t *gpu) +{ + size_t i, j; + size_t num_buffers; + size_t status = NV_OK; + uvm_conf_computing_dma_buffer_t **dma_buffers; + + // If the Confidential Computing feature is disabled, the DMA buffers + // pool is not initialized. + if (!uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + + // We're going to reclaim one more chunks that the pool have. Triggerring + // one expansion. + num_buffers = gpu->conf_computing.dma_buffer_pool.num_dma_buffers + 1; + dma_buffers = uvm_kvmalloc_zero(sizeof(*dma_buffers) * num_buffers); + if (dma_buffers == NULL) + return NV_ERR_NO_MEMORY; + + for (i = 0; i < num_buffers; ++i) { + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &dma_buffers[i], NULL); + if (status != NV_OK) + break; + } + + TEST_CHECK_GOTO(gpu->conf_computing.dma_buffer_pool.num_dma_buffers >= num_buffers, done); + TEST_CHECK_GOTO(i == num_buffers, done); + +done: + j = i; + for (i = 0; i < j; ++i) + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, dma_buffers[i], NULL); + + uvm_kvfree(dma_buffers); + return status; +} + static NV_STATUS test_basic(uvm_va_space_t *va_space) { uvm_gpu_t *gpu; - TEST_CHECK_RET(test_basic_sysmem() == NV_OK); + TEST_NV_CHECK_RET(test_basic_sysmem()); for_each_va_space_gpu(gpu, va_space) { - TEST_CHECK_RET(test_basic_vidmem(gpu) == NV_OK); - TEST_CHECK_RET(test_basic_sysmem_dma(gpu) == NV_OK); + TEST_NV_CHECK_RET(test_basic_vidmem(gpu)); + TEST_NV_CHECK_RET(test_basic_sysmem_dma(gpu)); + TEST_NV_CHECK_RET(test_basic_vidmem_unprotected(gpu)); + TEST_NV_CHECK_RET(test_basic_dma_pool(gpu)); } return NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_migrate.c b/kernel-open/nvidia-uvm/uvm_migrate.c index 1fb125df15..026058a3df 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate.c +++ b/kernel-open/nvidia-uvm/uvm_migrate.c @@ -933,20 +933,15 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) tracker_ptr = &tracker; if (params->length > 0) { - status = uvm_api_range_type_check(va_space, mm, params->base, params->length); - if (status == NV_OK) { - status = uvm_migrate(va_space, - mm, - params->base, - params->length, - (dest_gpu ? dest_gpu->id : UVM_ID_CPU), - params->flags, - uvm_va_space_iter_first(va_space, - params->base, - params->base), - tracker_ptr); + uvm_api_range_type_t type; + + type = uvm_api_range_type_check(va_space, mm, params->base, params->length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; } - else if (status == NV_WARN_NOTHING_TO_DO) { + + if (type == UVM_API_RANGE_TYPE_ATS) { uvm_migrate_args_t uvm_migrate_args = { .va_space = va_space, @@ -964,6 +959,18 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) status = uvm_migrate_pageable(&uvm_migrate_args); } + else { + status = uvm_migrate(va_space, + mm, + params->base, + params->length, + (dest_gpu ? dest_gpu->id : UVM_ID_CPU), + params->flags, + uvm_va_space_iter_first(va_space, + params->base, + params->base), + tracker_ptr); + } } done: diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c index 08150f73b0..a7effb9081 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c @@ -63,7 +63,7 @@ static NV_STATUS migrate_vma_page_copy_address(struct page *page, if (owning_gpu == copying_gpu) { // Local vidmem address - *gpu_addr = uvm_gpu_address_from_phys(uvm_gpu_page_to_phys_address(owning_gpu, page)); + *gpu_addr = uvm_gpu_address_copy(owning_gpu, uvm_gpu_page_to_phys_address(owning_gpu, page)); } else if (direct_peer) { // Direct GPU peer @@ -88,25 +88,13 @@ static NV_STATUS migrate_vma_page_copy_address(struct page *page, __set_bit(page_index, state->dma.page_mask); - *gpu_addr = uvm_gpu_address_physical(UVM_APERTURE_SYS, state->dma.addrs[page_index]); + *gpu_addr = uvm_gpu_address_copy(copying_gpu, + uvm_gpu_phys_address(UVM_APERTURE_SYS, state->dma.addrs[page_index])); } return NV_OK; } -// Return the GPU identified with the given NUMA node id -static uvm_gpu_t *get_gpu_from_node_id(uvm_va_space_t *va_space, int node_id) -{ - uvm_gpu_t *gpu; - - for_each_va_space_gpu(gpu, va_space) { - if (uvm_gpu_numa_info(gpu)->node_id == node_id) - return gpu; - } - - return NULL; -} - // Create a new push to zero pages on dst_id static NV_STATUS migrate_vma_zero_begin_push(uvm_va_space_t *va_space, uvm_processor_id_t dst_id, @@ -169,7 +157,7 @@ static NV_STATUS migrate_vma_copy_begin_push(uvm_va_space_t *va_space, // NUMA-enabled GPUs can copy to any other NUMA node in the system even if // P2P access has not been explicitly enabled (ie va_space->can_copy_from // is not set). - if (!gpu->parent->numa_info.enabled) { + if (!gpu->mem_info.numa.enabled) { UVM_ASSERT_MSG(uvm_processor_mask_test(&va_space->can_copy_from[uvm_id_value(gpu->id)], dst_id), "GPU %s dst %s src %s\n", uvm_va_space_processor_name(va_space, gpu->id), @@ -281,7 +269,7 @@ static void migrate_vma_compute_masks(struct vm_area_struct *vma, const unsigned continue; } - src_gpu = get_gpu_from_node_id(uvm_migrate_args->va_space, src_nid); + src_gpu = uvm_va_space_find_gpu_with_memory_node_id(uvm_migrate_args->va_space, src_nid); // Already resident on a node with no CPUs that doesn't belong to a // GPU, don't move @@ -980,13 +968,14 @@ NV_STATUS uvm_migrate_pageable(uvm_migrate_args_t *uvm_migrate_args) // wanted to call this function from a bottom half with CPU dst_id. UVM_ASSERT(!(current->flags & PF_KTHREAD)); - if (!nv_numa_node_has_memory(dst_node_id) || get_gpu_from_node_id(va_space, dst_node_id) != NULL) + if (!nv_numa_node_has_memory(dst_node_id) || + uvm_va_space_find_gpu_with_memory_node_id(va_space, dst_node_id) != NULL) return NV_ERR_INVALID_ARGUMENT; } else { // Incoming dst_node_id is only valid if dst_id belongs to the CPU. Use // dst_node_id as the GPU node id if dst_id doesn't belong to the CPU. - uvm_migrate_args->dst_node_id = uvm_gpu_numa_info(uvm_va_space_get_gpu(va_space, dst_id))->node_id; + uvm_migrate_args->dst_node_id = uvm_gpu_numa_node(uvm_va_space_get_gpu(va_space, dst_id)); } state = kmem_cache_alloc(g_uvm_migrate_vma_state_cache, NV_UVM_GFP_FLAGS); diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h index 3afedafd8d..9ee36ec9e5 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h @@ -58,11 +58,13 @@ typedef struct #ifdef UVM_MIGRATE_VMA_SUPPORTED #include -// The calls to migrate_vma are capped at 32MB to set an upper bound on the +// The calls to migrate_vma are capped at 512 pages to set an upper bound on the // amount of metadata that needs to be allocated for the operation. This number -// was chosen because performance seems to plateau at this size. -#define UVM_MIGRATE_VMA_MAX_SIZE (32UL * 1024 * 1024) -#define UVM_MIGRATE_VMA_MAX_PAGES (UVM_MIGRATE_VMA_MAX_SIZE >> PAGE_SHIFT) +// was chosen because performance seems to plateau at this size on 64K-pages +// kernels. On kernels with PAGE_SIZE == 4K, 512 pages correspond to 2M VA block, +// which is also a standard size for batch operations. +#define UVM_MIGRATE_VMA_MAX_PAGES (512UL) +#define UVM_MIGRATE_VMA_MAX_SIZE (UVM_MIGRATE_VMA_MAX_PAGES * PAGE_SIZE) typedef struct { diff --git a/kernel-open/nvidia-uvm/uvm_mmu.c b/kernel-open/nvidia-uvm/uvm_mmu.c index 50b8b627cd..03ccda18cc 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -34,6 +34,7 @@ #include "uvm_mem.h" #include "uvm_va_space.h" +#include // The page tree has 6 levels on Hopper+ GPUs, and the root is never freed by a // normal 'put' operation which leaves a maximum of 5 levels. @@ -102,7 +103,7 @@ static NV_STATUS phys_mem_allocate_sysmem(uvm_page_tree_t *tree, NvLength size, NvU64 dma_addr; unsigned long flags = __GFP_ZERO; uvm_memcg_context_t memcg_context; - uvm_va_space_t *va_space; + uvm_va_space_t *va_space = NULL; struct mm_struct *mm = NULL; if (tree->type == UVM_PAGE_TREE_TYPE_USER && tree->gpu_va_space && UVM_CGROUP_ACCOUNTING_SUPPORTED()) { @@ -244,6 +245,84 @@ static void page_table_range_init(uvm_page_table_range_t *range, dir->ref_count += range->entry_count; } +static bool uvm_mmu_use_cpu(uvm_page_tree_t *tree) +{ + // When physical CE writes can't be used for vidmem we use a flat virtual + // mapping instead. The GPU PTEs for that flat mapping have to be + // bootstrapped using the CPU. + return tree->location != UVM_APERTURE_SYS && + !tree->gpu->parent->ce_phys_vidmem_write_supported && + !tree->gpu->static_flat_mapping.ready; +} + +// uvm_mmu_page_table_page() and the uvm_mmu_page_table_cpu_* family of +// functions can only be used when uvm_mmu_use_cpu() returns true, which implies +// a coherent system. + +static struct page *uvm_mmu_page_table_page(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc_t *phys_alloc) +{ + // All platforms that require CPU PTE writes for bootstrapping can fit + // tables within a page. + UVM_ASSERT(phys_alloc->size <= PAGE_SIZE); + + if (phys_alloc->addr.aperture == UVM_APERTURE_SYS) + return phys_alloc->handle.page; + + return uvm_gpu_chunk_to_page(&gpu->pmm, phys_alloc->handle.chunk); +} + +static void *uvm_mmu_page_table_cpu_map(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc_t *phys_alloc) +{ + struct page *page = uvm_mmu_page_table_page(gpu, phys_alloc); + NvU64 page_offset = offset_in_page(phys_alloc->addr.address); + return (char *)kmap(page) + page_offset; +} + +static void uvm_mmu_page_table_cpu_unmap(uvm_gpu_t *gpu, uvm_mmu_page_table_alloc_t *phys_alloc) +{ + kunmap(uvm_mmu_page_table_page(gpu, phys_alloc)); +} + +static void uvm_mmu_page_table_cpu_memset_8(uvm_gpu_t *gpu, + uvm_mmu_page_table_alloc_t *phys_alloc, + NvU32 start_index, + NvU64 pattern, + NvU32 num_entries) +{ + NvU64 *ptr = uvm_mmu_page_table_cpu_map(gpu, phys_alloc); + size_t i; + + UVM_ASSERT(IS_ALIGNED((uintptr_t)ptr, sizeof(*ptr))); + UVM_ASSERT((start_index + num_entries) * sizeof(*ptr) <= phys_alloc->size); + + for (i = 0; i < num_entries; i++) + ptr[start_index + i] = pattern; + + uvm_mmu_page_table_cpu_unmap(gpu, phys_alloc); +} + +static void uvm_mmu_page_table_cpu_memset_16(uvm_gpu_t *gpu, + uvm_mmu_page_table_alloc_t *phys_alloc, + NvU32 start_index, + NvU64 *pattern, + NvU32 num_entries) +{ + struct + { + NvU64 u0, u1; + } *ptr; + size_t i; + + ptr = uvm_mmu_page_table_cpu_map(gpu, phys_alloc); + UVM_ASSERT(IS_ALIGNED((uintptr_t)ptr, sizeof(*ptr))); + UVM_ASSERT((start_index + num_entries) * sizeof(*ptr) <= phys_alloc->size); + + for (i = 0; i < num_entries; i++) + memcpy(&ptr[start_index + i], pattern, sizeof(*ptr)); + + uvm_mmu_page_table_cpu_unmap(gpu, phys_alloc); +} + static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_directory_t *dir, uvm_push_t *push) { NvU64 clear_bits[2]; @@ -262,10 +341,19 @@ static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_direc } // initialize the memory to a reasonable value - tree->gpu->parent->ce_hal->memset_8(push, - uvm_gpu_address_from_phys(dir->phys_alloc.addr), + if (push) { + tree->gpu->parent->ce_hal->memset_8(push, + uvm_mmu_gpu_address(tree->gpu, dir->phys_alloc.addr), + *clear_bits, + dir->phys_alloc.size); + } + else { + uvm_mmu_page_table_cpu_memset_8(tree->gpu, + &dir->phys_alloc, + 0, *clear_bits, - dir->phys_alloc.size); + dir->phys_alloc.size / sizeof(*clear_bits)); + } } static uvm_page_directory_t *allocate_directory(uvm_page_tree_t *tree, @@ -321,25 +409,44 @@ static inline NvU32 index_to_entry(uvm_mmu_mode_hal_t *hal, NvU32 entry_index, N return hal->entries_per_index(depth) * entry_index + hal->entry_offset(depth, page_size); } -// pde_fill() populates pde_count PDE entries (starting at start_index) with -// the same mapping, i.e., with the same physical address (phys_addr). -static void pde_fill(uvm_page_tree_t *tree, - NvU32 depth, - uvm_mmu_page_table_alloc_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr, - uvm_push_t *push) +static void pde_fill_cpu(uvm_page_tree_t *tree, + NvU32 depth, + uvm_mmu_page_table_alloc_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr) { NvU64 pde_data[2], entry_size; - uvm_gpu_address_t pde_entry_addr; - UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, depth, UVM_PAGE_SIZE_AGNOSTIC)); + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + entry_size = tree->hal->entry_size(depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + tree->hal->make_pde(pde_data, phys_addr, depth); + + if (entry_size == sizeof(pde_data[0])) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, directory, start_index, pde_data[0], pde_count); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, directory, start_index, pde_data, pde_count); +} + +static void pde_fill_gpu(uvm_page_tree_t *tree, + NvU32 depth, + uvm_mmu_page_table_alloc_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + NvU64 pde_data[2], entry_size; + uvm_gpu_address_t pde_entry_addr = uvm_mmu_gpu_address(tree->gpu, directory->addr); + + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + entry_size = tree->hal->entry_size(depth); UVM_ASSERT(sizeof(pde_data) >= entry_size); tree->hal->make_pde(pde_data, phys_addr, depth); - pde_entry_addr = uvm_gpu_address_from_phys(directory->addr); pde_entry_addr.address += start_index * entry_size; if (entry_size == sizeof(pde_data[0])) { @@ -386,6 +493,24 @@ static void pde_fill(uvm_page_tree_t *tree, } } +// pde_fill() populates pde_count PDE entries (starting at start_index) with +// the same mapping, i.e., with the same physical address (phys_addr). +static void pde_fill(uvm_page_tree_t *tree, + NvU32 depth, + uvm_mmu_page_table_alloc_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, depth, UVM_PAGE_SIZE_AGNOSTIC)); + + if (push) + pde_fill_gpu(tree, depth, directory, start_index, pde_count, phys_addr, push); + else + pde_fill_cpu(tree, depth, directory, start_index, pde_count, phys_addr); +} + static uvm_page_directory_t *host_pde_write(uvm_page_directory_t *dir, uvm_page_directory_t *parent, NvU32 index_in_parent) @@ -426,7 +551,11 @@ static void host_pde_clear(uvm_page_tree_t *tree, uvm_page_directory_t *dir, NvU dir->ref_count--; } -static void pde_clear(uvm_page_tree_t *tree, uvm_page_directory_t *dir, NvU32 entry_index, NvU32 page_size, void *push) +static void pde_clear(uvm_page_tree_t *tree, + uvm_page_directory_t *dir, + NvU32 entry_index, + NvU32 page_size, + uvm_push_t *push) { host_pde_clear(tree, dir, entry_index, page_size); pde_write(tree, dir, entry_index, false, push); @@ -492,12 +621,62 @@ static NV_STATUS page_tree_end_and_wait(uvm_page_tree_t *tree, uvm_push_t *push) return NV_OK; } -// initialize new page tables and insert them into the tree -static NV_STATUS write_gpu_state(uvm_page_tree_t *tree, - NvU32 page_size, - NvS32 invalidate_depth, - NvU32 used_count, - uvm_page_directory_t **dirs_used) +static NV_STATUS write_gpu_state_cpu(uvm_page_tree_t *tree, + NvU32 page_size, + NvS32 invalidate_depth, + NvU32 used_count, + uvm_page_directory_t **dirs_used) +{ + NvS32 i; + uvm_push_t push; + NV_STATUS status; + + uvm_assert_mutex_locked(&tree->lock); + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + if (used_count == 0) + return NV_OK; + + status = uvm_tracker_wait(&tree->tracker); + if (status != NV_OK) + return status; + + for (i = 0; i < used_count; i++) + phys_mem_init(tree, page_size, dirs_used[i], NULL); + + // Only a single membar is needed between the memsets of the page tables + // and the writes of the PDEs pointing to those page tables. + mb(); + + // write entries bottom up, so that they are valid once they're inserted + // into the tree + for (i = used_count - 1; i >= 0; i--) + pde_write(tree, dirs_used[i]->host_parent, dirs_used[i]->index_in_parent, false, NULL); + + // A CPU membar is needed between the PDE writes and the subsequent TLB + // invalidate. Work submission guarantees such a membar. + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "%u dirs", used_count); + if (status != NV_OK) + return status; + + UVM_ASSERT(invalidate_depth >= 0); + + // See the comments in write_gpu_state_gpu() + tree->gpu->parent->host_hal->tlb_invalidate_all(&push, + uvm_page_tree_pdb(tree)->addr, + invalidate_depth, + UVM_MEMBAR_NONE); + page_tree_end(tree, &push); + page_tree_tracker_overwrite_with_push(tree, &push); + + return NV_OK; +} + +static NV_STATUS write_gpu_state_gpu(uvm_page_tree_t *tree, + NvU32 page_size, + NvS32 invalidate_depth, + NvU32 used_count, + uvm_page_directory_t **dirs_used) { NvS32 i; uvm_push_t push; @@ -508,11 +687,12 @@ static NV_STATUS write_gpu_state(uvm_page_tree_t *tree, uvm_membar_t membar_after_writes = UVM_MEMBAR_GPU; uvm_assert_mutex_locked(&tree->lock); + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); if (used_count == 0) return NV_OK; - status = page_tree_begin_acquire(tree, &tree->tracker, &push, "write_gpu_state: %u dirs", used_count); + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "%u dirs", used_count); if (status != NV_OK) return status; @@ -533,15 +713,15 @@ static NV_STATUS write_gpu_state(uvm_page_tree_t *tree, // Only a single membar is needed between the memsets of the page tables // and the writes of the PDEs pointing to those page tables. - // The membar can be local if all of the page tables and PDEs are in GPU memory, - // but must be a sysmembar if any of them are in sysmem. - tree->gpu->parent->host_hal->wait_for_idle(&push); - uvm_hal_membar(tree->gpu, &push, membar_after_writes); + // The membar can be local if all of the page tables and PDEs are in GPU + // memory, but must be a sysmembar if any of them are in sysmem. + uvm_hal_wfi_membar(&push, membar_after_writes); // Reset back to a local membar by default membar_after_writes = UVM_MEMBAR_GPU; - // write entries bottom up, so that they are valid once they're inserted into the tree + // write entries bottom up, so that they are valid once they're inserted + // into the tree for (i = used_count - 1; i >= 0; i--) { uvm_page_directory_t *dir = dirs_used[i]; @@ -553,18 +733,19 @@ static NV_STATUS write_gpu_state(uvm_page_tree_t *tree, // If any of the written PDEs is in sysmem, a sysmembar is needed before // the TLB invalidate. - // Notably sysmembar is needed even though the writer (CE) and reader (MMU) are - // on the same GPU, because CE physical writes take the L2 bypass path. + // Notably sysmembar is needed even though the writer (CE) and reader + // (MMU) are on the same GPU, because CE physical writes take the L2 + // bypass path. if (dir->host_parent->phys_alloc.addr.aperture == UVM_APERTURE_SYS) membar_after_writes = UVM_MEMBAR_SYS; } - tree->gpu->parent->host_hal->wait_for_idle(&push); - uvm_hal_membar(tree->gpu, &push, membar_after_writes); + uvm_hal_wfi_membar(&push, membar_after_writes); UVM_ASSERT(invalidate_depth >= 0); - // Upgrades don't have to flush out accesses, so no membar is needed on the TLB invalidate. + // Upgrades don't have to flush out accesses, so no membar is needed on the + // TLB invalidate. tree->gpu->parent->host_hal->tlb_invalidate_all(&push, uvm_page_tree_pdb(tree)->addr, invalidate_depth, @@ -582,6 +763,19 @@ static NV_STATUS write_gpu_state(uvm_page_tree_t *tree, return NV_OK; } +// initialize new page tables and insert them into the tree +static NV_STATUS write_gpu_state(uvm_page_tree_t *tree, + NvU32 page_size, + NvS32 invalidate_depth, + NvU32 used_count, + uvm_page_directory_t **dirs_used) +{ + if (uvm_mmu_use_cpu(tree)) + return write_gpu_state_cpu(tree, page_size, invalidate_depth, used_count, dirs_used); + else + return write_gpu_state_gpu(tree, page_size, invalidate_depth, used_count, dirs_used); +} + static void free_unused_directories(uvm_page_tree_t *tree, NvU32 used_count, uvm_page_directory_t **dirs_used, @@ -633,6 +827,8 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) uvm_pte_batch_t batch; NvU32 entry_size; + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + // Allocate the ptes_invalid_4k. status = allocate_page_table(tree, UVM_PAGE_SIZE_4K, &tree->map_remap.ptes_invalid_4k); if (status != NV_OK) @@ -718,6 +914,9 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // // In SR-IOV heavy the the page tree must be in vidmem, to prevent guest drivers // from updating GPU page tables without hypervisor knowledge. +// When the Confidential Computing feature is enabled, all kernel +// allocations must be made in the CPR of vidmem. This is a hardware security +// constraint. // Inputs Outputs // init location | uvm_page_table_location || tree->location | tree->location_sys_fallback // -------------|-------------------------||----------------|---------------- @@ -734,7 +933,8 @@ static void page_tree_set_location(uvm_page_tree_t *tree, uvm_aperture_t locatio (location == UVM_APERTURE_DEFAULT), "Invalid location %s (%d)\n", uvm_aperture_string(location), (int)location); - should_location_be_vidmem = uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu); + should_location_be_vidmem = uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu) + || uvm_conf_computing_mode_enabled(tree->gpu); // The page tree of a "fake" GPU used during page tree testing can be in // sysmem even if should_location_be_vidmem is true. A fake GPU can be @@ -798,6 +998,11 @@ NV_STATUS uvm_page_tree_init(uvm_gpu_t *gpu, return status; } + if (uvm_mmu_use_cpu(tree)) { + phys_mem_init(tree, UVM_PAGE_SIZE_AGNOSTIC, tree->root, NULL); + return NV_OK; + } + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "init page tree"); if (status != NV_OK) return status; @@ -858,7 +1063,7 @@ void uvm_page_tree_put_ptes_async(uvm_page_tree_t *tree, uvm_page_table_range_t uvm_page_directory_t *free_queue[MAX_OPERATION_DEPTH]; uvm_page_directory_t *dir = range->table; uvm_push_t push; - NV_STATUS status; + NV_STATUS status = NV_OK; NvU32 invalidate_depth = 0; // The logic of what membar is needed when is pretty subtle, please refer to @@ -880,34 +1085,58 @@ void uvm_page_tree_put_ptes_async(uvm_page_tree_t *tree, uvm_page_table_range_t uvm_membar_t this_membar; if (free_count == 0) { + if (uvm_mmu_use_cpu(tree)) + status = uvm_tracker_wait(&tree->tracker); + + if (status == NV_OK) { + // Begin a push which will be submitted before the memory gets + // freed. + // + // When writing with the CPU we don't strictly need to begin + // this push until after the writes are done, but doing it here + // doesn't hurt and makes the function's logic simpler. + status = page_tree_begin_acquire(tree, + &tree->tracker, + &push, + "put ptes: start: %u, count: %u", + range->start_index, + range->entry_count); + } - // begin a push which will be submitted before the memory gets freed - status = page_tree_begin_acquire(tree, &tree->tracker, &push, "put ptes: start: %u, count: %u", - range->start_index, range->entry_count); - // Failure to get a push can only happen if we've hit a fatal UVM - // channel error. We can't perform the unmap, so just leave things - // in place for debug. + // Failure to wait for a tracker or get a push can only happen if + // we've hit a fatal UVM channel error. We can't perform the unmap, + // so just leave things in place for debug. if (status != NV_OK) { UVM_ASSERT(status == uvm_global_get_status()); dir->ref_count += range->entry_count; - uvm_mutex_unlock(&tree->lock); - return; + goto done; } } - // All writes can be pipelined as put_ptes() cannot be called with any - // operations pending on the affected PTEs and PDEs. - uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); - - // Don't issue any membars as part of the clear, a single membar will be - // done below before the invalidate. - uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - pde_clear(tree, dir->host_parent, dir->index_in_parent, range->page_size, &push); + if (uvm_mmu_use_cpu(tree)) { + pde_clear(tree, dir->host_parent, dir->index_in_parent, range->page_size, NULL); + } + else { + // All writes can be pipelined as put_ptes() cannot be called with + // any operations pending on the affected PTEs and PDEs. + uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + // Don't issue any membars as part of the clear, a single membar + // will be done below before the invalidate. + uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + pde_clear(tree, dir->host_parent, dir->index_in_parent, range->page_size, &push); + } invalidate_depth = dir->host_parent->depth; - // Take the membar with the widest scope of any of the pointed-to PDEs - this_membar = uvm_hal_downgrade_membar_type(tree->gpu, dir->phys_alloc.addr.aperture == UVM_APERTURE_VID); + // If we're using the CPU to do the write a SYS membar is required. + // Otherwise, take the membar with the widest scope of any of the + // pointed-to PDEs. + if (uvm_mmu_use_cpu(tree)) + this_membar = UVM_MEMBAR_SYS; + else + this_membar = uvm_hal_downgrade_membar_type(tree->gpu, dir->phys_alloc.addr.aperture == UVM_APERTURE_VID); + membar_after_invalidate = max(membar_after_invalidate, this_membar); // If any of the cleared PDEs were in sysmem then a SYS membar is @@ -923,23 +1152,28 @@ void uvm_page_tree_put_ptes_async(uvm_page_tree_t *tree, uvm_page_table_range_t dir = parent; } - if (free_count == 0) { - uvm_mutex_unlock(&tree->lock); - return; - } + if (free_count == 0) + goto done; + + if (uvm_mmu_use_cpu(tree)) + mb(); + else + uvm_hal_wfi_membar(&push, membar_after_pde_clears); - tree->gpu->parent->host_hal->wait_for_idle(&push); - uvm_hal_membar(tree->gpu, &push, membar_after_pde_clears); tree->gpu->parent->host_hal->tlb_invalidate_all(&push, uvm_page_tree_pdb(tree)->addr, invalidate_depth, membar_after_invalidate); - // We just did the appropriate membar above, no need for another one in push_end(). - // At least currently as if the L2 bypass path changes to only require a GPU - // membar between PDE write and TLB invalidate, we'll need to push a - // sysmembar so the end-of-push semaphore is ordered behind the PDE writes. - uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + if (!uvm_mmu_use_cpu(tree)) { + // We just did the appropriate membar above, no need for another one in + // push_end(). If the L2 bypass path changes to only require a GPU + // membar between PDE write and TLB invalidate, we'll need to push a + // sysmembar so the end-of-push semaphore is ordered behind the PDE + // writes. + uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + } + page_tree_end(tree, &push); page_tree_tracker_overwrite_with_push(tree, &push); @@ -949,6 +1183,7 @@ void uvm_page_tree_put_ptes_async(uvm_page_tree_t *tree, uvm_page_table_range_t uvm_kvfree(free_queue[i]); } +done: uvm_mutex_unlock(&tree->lock); } @@ -1255,19 +1490,22 @@ static NV_STATUS poison_ptes(uvm_page_tree_t *tree, UVM_ASSERT(pte_dir->depth == tree->hal->page_table_depth(page_size)); + // The flat mappings should always be set up when executing this path + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "Poisoning child table of page size %u", page_size); if (status != NV_OK) return status; tree->gpu->parent->ce_hal->memset_8(&push, - uvm_gpu_address_from_phys(pte_dir->phys_alloc.addr), + uvm_mmu_gpu_address(tree->gpu, pte_dir->phys_alloc.addr), tree->hal->poisoned_pte(), pte_dir->phys_alloc.size); // If both the new PTEs and the parent PDE are in vidmem, then a GPU- // local membar is enough to keep the memset of the PTEs ordered with // any later write of the PDE. Otherwise we need a sysmembar. See the - // comments in write_gpu_state. + // comments in write_gpu_state_gpu. if (pte_dir->phys_alloc.addr.aperture == UVM_APERTURE_VID && parent->phys_alloc.addr.aperture == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); @@ -1527,7 +1765,43 @@ NV_STATUS uvm_page_table_range_vec_split_upper(uvm_page_table_range_vec_t *range return NV_OK; } -NV_STATUS uvm_page_table_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar) +static NV_STATUS uvm_page_table_range_vec_clear_ptes_cpu(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar) +{ + uvm_page_tree_t *tree = range_vec->tree; + NvU32 entry_size = uvm_mmu_pte_size(tree, range_vec->page_size); + NvU64 invalid_ptes[2] = {0, 0}; + uvm_push_t push; + NV_STATUS status; + size_t i; + + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + for (i = 0; i < range_vec->range_count; ++i) { + uvm_page_table_range_t *range = &range_vec->ranges[i]; + uvm_mmu_page_table_alloc_t *dir = &range->table->phys_alloc; + + if (entry_size == 8) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, dir, range->start_index, invalid_ptes[0], range->entry_count); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, dir, range->start_index, invalid_ptes, range->entry_count); + } + + // A CPU membar is needed between the PTE writes and the subsequent TLB + // invalidate. Work submission guarantees such a membar. + status = page_tree_begin_acquire(tree, + NULL, + &push, + "Invalidating [0x%llx, 0x%llx)", + range_vec->start, + range_vec->start + range_vec->size); + if (status != NV_OK) + return status; + + uvm_tlb_batch_single_invalidate(tree, &push, range_vec->start, range_vec->size, range_vec->page_size, tlb_membar); + return page_tree_end_and_wait(tree, &push); +} + +static NV_STATUS uvm_page_table_range_vec_clear_ptes_gpu(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar) { NV_STATUS status = NV_OK; NV_STATUS tracker_status; @@ -1545,6 +1819,7 @@ NV_STATUS uvm_page_table_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_ UVM_ASSERT(range_vec); UVM_ASSERT(tree); UVM_ASSERT(gpu); + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); i = 0; while (i < range_vec->range_count) { @@ -1595,6 +1870,14 @@ NV_STATUS uvm_page_table_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_ return status; } +NV_STATUS uvm_page_table_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar) +{ + if (uvm_mmu_use_cpu(range_vec->tree)) + return uvm_page_table_range_vec_clear_ptes_cpu(range_vec, tlb_membar); + else + return uvm_page_table_range_vec_clear_ptes_gpu(range_vec, tlb_membar); +} + void uvm_page_table_range_vec_deinit(uvm_page_table_range_vec_t *range_vec) { size_t i; @@ -1626,10 +1909,58 @@ void uvm_page_table_range_vec_destroy(uvm_page_table_range_vec_t *range_vec) uvm_kvfree(range_vec); } -NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, - uvm_membar_t tlb_membar, - uvm_page_table_range_pte_maker_t pte_maker, - void *caller_data) +static NV_STATUS uvm_page_table_range_vec_write_ptes_cpu(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data) +{ + NV_STATUS status; + size_t i; + uvm_page_tree_t *tree = range_vec->tree; + NvU32 entry_size = uvm_mmu_pte_size(tree, range_vec->page_size); + uvm_push_t push; + NvU64 offset = 0; + + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + // Enforce ordering with prior accesses to the pages being mapped before the + // mappings are activated. + mb(); + + for (i = 0; i < range_vec->range_count; ++i) { + uvm_page_table_range_t *range = &range_vec->ranges[i]; + uvm_mmu_page_table_alloc_t *dir = &range->table->phys_alloc; + NvU32 entry; + + for (entry = range->start_index; entry < range->entry_count; ++entry) { + NvU64 pte_bits[2] = {pte_maker(range_vec, offset, caller_data), 0}; + + if (entry_size == 8) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, dir, entry, pte_bits[0], 1); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, dir, entry, pte_bits, 1); + + offset += range_vec->page_size; + } + } + + status = page_tree_begin_acquire(tree, + NULL, + &push, + "Invalidating [0x%llx, 0x%llx)", + range_vec->start, + range_vec->start + range_vec->size); + if (status != NV_OK) + return status; + + uvm_tlb_batch_single_invalidate(tree, &push, range_vec->start, range_vec->size, range_vec->page_size, tlb_membar); + return page_tree_end_and_wait(tree, &push); +} + +static NV_STATUS uvm_page_table_range_vec_write_ptes_gpu(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data) { NV_STATUS status = NV_OK; NV_STATUS tracker_status; @@ -1650,6 +1981,8 @@ NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_ NvU32 max_entries_per_push = max_total_entry_size_per_push / entry_size; + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + for (i = 0; i < range_vec->range_count; ++i) { uvm_page_table_range_t *range = &range_vec->ranges[i]; NvU64 range_start = range_vec_calc_range_start(range_vec, i); @@ -1728,6 +2061,17 @@ NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_ return status; } +NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data) +{ + if (uvm_mmu_use_cpu(range_vec->tree)) + return uvm_page_table_range_vec_write_ptes_cpu(range_vec, tlb_membar, pte_maker, caller_data); + else + return uvm_page_table_range_vec_write_ptes_gpu(range_vec, tlb_membar, pte_maker, caller_data); +} + typedef struct identity_mapping_pte_maker_data_struct { NvU64 phys_offset; @@ -1745,13 +2089,12 @@ static NvU64 identity_mapping_pte_maker(uvm_page_table_range_vec_t *range_vec, N } static NV_STATUS create_identity_mapping(uvm_gpu_t *gpu, - NvU64 base, + uvm_gpu_identity_mapping_t *mapping, NvU64 size, uvm_aperture_t aperture, NvU64 phys_offset, NvU32 page_size, - uvm_pmm_alloc_flags_t pmm_flags, - uvm_page_table_range_vec_t **range_vec) + uvm_pmm_alloc_flags_t pmm_flags) { NV_STATUS status; identity_mapping_pte_maker_data_t data = @@ -1761,32 +2104,36 @@ static NV_STATUS create_identity_mapping(uvm_gpu_t *gpu, }; status = uvm_page_table_range_vec_create(&gpu->address_space_tree, - base, + mapping->base, size, page_size, pmm_flags, - range_vec); + &mapping->range_vec); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init range vec for aperture %d identity mapping at [0x%llx, 0x%llx): %s, GPU %s\n", aperture, - base, - base + size, + mapping->base, + mapping->base + size, nvstatusToString(status), uvm_gpu_name(gpu)); return status; } - status = uvm_page_table_range_vec_write_ptes(*range_vec, UVM_MEMBAR_NONE, identity_mapping_pte_maker, &data); + status = uvm_page_table_range_vec_write_ptes(mapping->range_vec, + UVM_MEMBAR_NONE, + identity_mapping_pte_maker, + &data); if (status != NV_OK) { UVM_ERR_PRINT("Failed to write PTEs for aperture %d identity mapping at [0x%llx, 0x%llx): %s, GPU %s\n", aperture, - base, - base + size, + mapping->base, + mapping->base + size, nvstatusToString(status), uvm_gpu_name(gpu)); return status; } + mapping->ready = true; return NV_OK; } @@ -1795,6 +2142,10 @@ static void destroy_identity_mapping(uvm_gpu_identity_mapping_t *mapping) if (mapping->range_vec == NULL) return; + // Tell the teardown routines they can't use this mapping as part of their + // teardown. + mapping->ready = false; + (void)uvm_page_table_range_vec_clear_ptes(mapping->range_vec, UVM_MEMBAR_SYS); uvm_page_table_range_vec_destroy(mapping->range_vec); mapping->range_vec = NULL; @@ -1802,7 +2153,7 @@ static void destroy_identity_mapping(uvm_gpu_identity_mapping_t *mapping) bool uvm_mmu_gpu_needs_static_vidmem_mapping(uvm_gpu_t *gpu) { - return false; + return !gpu->parent->ce_phys_vidmem_write_supported; } bool uvm_mmu_gpu_needs_dynamic_vidmem_mapping(uvm_gpu_t *gpu) @@ -1838,13 +2189,12 @@ NV_STATUS create_static_vidmem_mapping(uvm_gpu_t *gpu) flat_mapping->base = gpu->parent->flat_vidmem_va_base; return create_identity_mapping(gpu, - flat_mapping->base, + flat_mapping, size, aperture, phys_offset, page_size, - UVM_PMM_ALLOC_FLAGS_EVICT, - &flat_mapping->range_vec); + UVM_PMM_ALLOC_FLAGS_EVICT); } static void destroy_static_vidmem_mapping(uvm_gpu_t *gpu) @@ -1884,13 +2234,12 @@ NV_STATUS uvm_mmu_create_peer_identity_mappings(uvm_gpu_t *gpu, uvm_gpu_t *peer) UVM_ASSERT(peer_mapping->base); return create_identity_mapping(gpu, - peer_mapping->base, + peer_mapping, size, aperture, phys_offset, page_size, - UVM_PMM_ALLOC_FLAGS_EVICT, - &peer_mapping->range_vec); + UVM_PMM_ALLOC_FLAGS_EVICT); } void uvm_mmu_destroy_peer_identity_mappings(uvm_gpu_t *gpu, uvm_gpu_t *peer) @@ -2304,14 +2653,14 @@ static NV_STATUS create_dynamic_sysmem_mapping(uvm_gpu_t *gpu) // SR-IOV each mapping addition adds a lot of overhead due to vGPU plugin // involvement), metadata memory footprint (inversely proportional to the // mapping size), etc. - mapping_size = 4ULL * 1024 * 1024 * 1024; + mapping_size = 4 * UVM_SIZE_1GB; // The mapping size should be at least 1GB, due to bitlock limitations. This // shouldn't be a problem because the expectation is to use 512MB PTEs, and // using a granularity of 1GB already results in allocating a large array of // sysmem mappings with 128K entries. UVM_ASSERT(is_power_of_2(mapping_size)); - UVM_ASSERT(mapping_size >= 1ULL * 1024 * 1024 * 1024); + UVM_ASSERT(mapping_size >= UVM_SIZE_1GB); UVM_ASSERT(mapping_size >= uvm_mmu_biggest_page_size(&gpu->address_space_tree)); UVM_ASSERT(mapping_size <= flat_sysmem_va_size); @@ -2367,13 +2716,12 @@ NV_STATUS uvm_mmu_sysmem_map(uvm_gpu_t *gpu, NvU64 pa, NvU64 size) sysmem_mapping->base = virtual_address.address; status = create_identity_mapping(gpu, - sysmem_mapping->base, + sysmem_mapping, gpu->sysmem_mappings.mapping_size, UVM_APERTURE_SYS, phys_offset, page_size, - pmm_flags, - &sysmem_mapping->range_vec); + pmm_flags); } sysmem_mapping_unlock(gpu, sysmem_mapping); @@ -2394,14 +2742,14 @@ NV_STATUS uvm_mmu_create_flat_mappings(uvm_gpu_t *gpu) { NV_STATUS status; - status = create_dynamic_sysmem_mapping(gpu); - if (status != NV_OK) - return status; - status = create_static_vidmem_mapping(gpu); if (status != NV_OK) goto error; + status = create_dynamic_sysmem_mapping(gpu); + if (status != NV_OK) + return status; + status = create_dynamic_vidmem_mapping(gpu); if (status != NV_OK) goto error; @@ -2416,8 +2764,16 @@ NV_STATUS uvm_mmu_create_flat_mappings(uvm_gpu_t *gpu) void uvm_mmu_destroy_flat_mappings(uvm_gpu_t *gpu) { destroy_dynamic_vidmem_mapping(gpu); - destroy_static_vidmem_mapping(gpu); destroy_dynamic_sysmem_mapping(gpu); + destroy_static_vidmem_mapping(gpu); +} + +uvm_gpu_address_t uvm_mmu_gpu_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t phys_addr) +{ + if (phys_addr.aperture == UVM_APERTURE_VID && !gpu->parent->ce_phys_vidmem_write_supported) + return uvm_gpu_address_virtual_from_vidmem_phys(gpu, phys_addr.address); + + return uvm_gpu_address_from_phys(phys_addr); } NV_STATUS uvm_test_invalidate_tlb(UVM_TEST_INVALIDATE_TLB_PARAMS *params, struct file *filp) diff --git a/kernel-open/nvidia-uvm/uvm_mmu.h b/kernel-open/nvidia-uvm/uvm_mmu.h index 1935b4cc5b..2f21b6ee78 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.h +++ b/kernel-open/nvidia-uvm/uvm_mmu.h @@ -50,7 +50,11 @@ // | | // | (not used) | // | | -// ------------------ 64PB + 8TB +// ------------------ 64PB + 8TB + 256GB (UVM_GPU_MAX_PHYS_MEM) +// | vidmem | +// | flat mapping | ==> UVM_GPU_MAX_PHYS_MEM +// | (256GB) | +// ------------------ 64PB + 8TB (flat_vidmem_va_base) // |peer ident. maps| // |32 * 256GB = 8TB| ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE // ------------------ 64PB @@ -105,7 +109,7 @@ // +----------------+ 0 (rm_va_base) // Maximum memory of any GPU. -#define UVM_GPU_MAX_PHYS_MEM (256ull * 1024 * 1024 * 1024) +#define UVM_GPU_MAX_PHYS_MEM (256 * UVM_SIZE_1GB) // The size of VA that should be reserved per peer identity mapping. // This should be at least the maximum amount of memory of any GPU. @@ -649,6 +653,14 @@ static uvm_aperture_t uvm_page_table_range_aperture(uvm_page_table_range_t *rang return range->table->phys_alloc.addr.aperture; } +// Given a GPU or CPU physical address that refers to pages tables, retrieve an +// address suitable for CE writes to those page tables. This should be used +// instead of uvm_gpu_address_copy because PTE writes are used to bootstrap the +// various flat virtual mappings, so we usually ensure that PTE writes work even +// if virtual mappings are required for other accesses. This is only needed when +// CE has system-wide physical addressing restrictions. +uvm_gpu_address_t uvm_mmu_gpu_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t phys_addr); + NV_STATUS uvm_test_invalidate_tlb(UVM_TEST_INVALIDATE_TLB_PARAMS *params, struct file *filp); #endif diff --git a/kernel-open/nvidia-uvm/uvm_page_tree_test.c b/kernel-open/nvidia-uvm/uvm_page_tree_test.c index 5b5dedf5d0..a5710e582f 100644 --- a/kernel-open/nvidia-uvm/uvm_page_tree_test.c +++ b/kernel-open/nvidia-uvm/uvm_page_tree_test.c @@ -541,7 +541,7 @@ static NV_STATUS allocate_then_free_8_8_64k(uvm_gpu_t *gpu) NvLength size = 64 * 1024; NvLength stride = 32 * size; - NvLength start = stride * 248 + 256LL * 1024 * 1024 * 1024 + (1LL << 47); + NvLength start = (248 * stride) + (256 * UVM_SIZE_1GB) + (128 * UVM_SIZE_1TB); int i; MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); @@ -662,7 +662,7 @@ static NV_STATUS get_entire_table_4k(uvm_gpu_t *gpu) NvU64 start = 1UL << 47; - NvLength size = 1 << 21; + NvLength size = 2 * UVM_SIZE_1MB; MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_4K, start, size, &range), NV_OK); @@ -685,7 +685,7 @@ static NV_STATUS get_entire_table_512m(uvm_gpu_t *gpu) uvm_page_table_range_t range; NvU64 start = 1UL << 48; - NvLength size = 512UL * 512 * 1024 * 1024; + NvLength size = 512UL * UVM_PAGE_SIZE_512M; MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_512M, start, size, &range), NV_OK); @@ -711,7 +711,7 @@ static NV_STATUS split_4k_from_2m(uvm_gpu_t *gpu) uvm_page_table_range_t range_64k; NvU64 start = 1UL << 48; - NvLength size = 1 << 21; + NvLength size = 2 * UVM_SIZE_1MB; MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_2M, start, size, &range_2m), NV_OK); @@ -759,7 +759,7 @@ static NV_STATUS split_2m_from_512m(uvm_gpu_t *gpu) uvm_page_table_range_t range_2m; NvU64 start = 1UL << 48; - NvLength size = 512UL * 1024 * 1024; + NvLength size = UVM_PAGE_SIZE_512M; MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_512M, start, size, &range_512m), NV_OK); @@ -812,7 +812,7 @@ static NV_STATUS get_2gb_range(uvm_gpu_t *gpu) uvm_page_tree_t tree; uvm_page_table_range_t range; - NvU64 start = 2UL * (1 << 30); + NvU64 start = 2 * UVM_SIZE_1GB; NvU64 size = start; MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); diff --git a/kernel-open/nvidia-uvm/uvm_pascal.c b/kernel-open/nvidia-uvm/uvm_pascal.c index a2dd460b52..83c675a273 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal.c +++ b/kernel-open/nvidia-uvm/uvm_pascal.c @@ -49,11 +49,13 @@ void uvm_hal_pascal_arch_init_properties(uvm_parent_gpu_t *parent_gpu) // A single top level PDE on Pascal covers 128 TB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_VIRTUAL; // Not all units on Pascal support 49-bit addressing, including those which diff --git a/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c b/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c index 020f5ce182..ca50f5bfbf 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c +++ b/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -105,7 +105,7 @@ static uvm_fault_access_type_t get_fault_access_type(const NvU32 *fault_entry) return UVM_FAULT_ACCESS_TYPE_COUNT; } -static uvm_fault_type_t get_fault_type(const NvU32 *fault_entry) +uvm_fault_type_t uvm_hal_pascal_fault_buffer_get_fault_type(const NvU32 *fault_entry) { NvU32 hw_fault_type_value = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, FAULT_TYPE); @@ -197,11 +197,27 @@ static NvU32 *get_fault_buffer_entry(uvm_parent_gpu_t *parent_gpu, NvU32 index) return fault_entry; } +// When Confidential Computing is enabled, fault entries are encrypted. Each +// fault has (unencrypted) metadata containing the authentication tag, and a +// valid bit that allows UVM to check if an encrypted fault is valid, without +// having to decrypt it first. +static UvmFaultMetadataPacket *get_fault_buffer_entry_metadata(uvm_parent_gpu_t *parent_gpu, NvU32 index) +{ + UvmFaultMetadataPacket *fault_entry_metadata; + + UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults); + UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + + fault_entry_metadata = parent_gpu->fault_buffer_info.rm_info.replayable.bufferMetadata; + UVM_ASSERT(fault_entry_metadata != NULL); + + return fault_entry_metadata + index; +} + void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, NvU32 index, uvm_fault_buffer_entry_t *buffer_entry) { - NV_STATUS status; NvU32 *fault_entry; NvU64 addr_hi, addr_lo; NvU64 timestamp_hi, timestamp_lo; @@ -209,13 +225,12 @@ void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, NvU32 utlb_id; BUILD_BUG_ON(NVB069_FAULT_BUF_SIZE > UVM_GPU_MMU_MAX_FAULT_PACKET_SIZE); - status = NV_OK; - - fault_entry = get_fault_buffer_entry(parent_gpu, index); // Valid bit must be set before this function is called UVM_ASSERT(parent_gpu->fault_buffer_hal->entry_is_valid(parent_gpu, index)); + fault_entry = get_fault_buffer_entry(parent_gpu, index); + addr_hi = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, INST_HI); addr_lo = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, INST_LO); buffer_entry->instance_ptr.address = addr_lo + (addr_hi << HWSIZE_MW(B069, FAULT_BUF_ENTRY, INST_LO)); @@ -233,7 +248,7 @@ void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, timestamp_lo = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, TIMESTAMP_LO); buffer_entry->timestamp = timestamp_lo + (timestamp_hi << HWSIZE_MW(B069, FAULT_BUF_ENTRY, TIMESTAMP_LO)); - buffer_entry->fault_type = get_fault_type(fault_entry); + buffer_entry->fault_type = parent_gpu->fault_buffer_hal->get_fault_type(fault_entry); buffer_entry->fault_access_type = get_fault_access_type(fault_entry); @@ -269,23 +284,39 @@ void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, bool uvm_hal_pascal_fault_buffer_entry_is_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - NvU32 *fault_entry; - bool is_valid; + if (uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) { + NvU32 *fault_entry = get_fault_buffer_entry(parent_gpu, index); - fault_entry = get_fault_buffer_entry(parent_gpu, index); + return READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID); + } + else { + // Use the valid bit present in the encryption metadata, which is + // unencrypted, instead of the valid bit present in the (encrypted) + // fault itself. + UvmFaultMetadataPacket *fault_entry_metadata = get_fault_buffer_entry_metadata(parent_gpu, index); - is_valid = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID); + return fault_entry_metadata->valid; + } - return is_valid; + UVM_ASSERT_MSG(false, "Invalid path"); + return false; } void uvm_hal_pascal_fault_buffer_entry_clear_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - NvU32 *fault_entry; + if (uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) { + NvU32 *fault_entry = get_fault_buffer_entry(parent_gpu, index); - fault_entry = get_fault_buffer_entry(parent_gpu, index); + WRITE_HWCONST_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID, FALSE); + } + else { + // Use the valid bit present in the encryption metadata, which is + // unencrypted, instead of the valid bit present in the (encrypted) + // fault itself. + UvmFaultMetadataPacket *fault_entry_metadata = get_fault_buffer_entry_metadata(parent_gpu, index); - WRITE_HWCONST_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID, FALSE); + fault_entry_metadata->valid = false; + } } NvU32 uvm_hal_pascal_fault_buffer_entry_size(uvm_parent_gpu_t *parent_gpu) diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c index 0aae1817c6..a81d0fc644 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c @@ -22,6 +22,7 @@ *******************************************************************************/ #include "uvm_api.h" +#include "uvm_conf_computing.h" #include "uvm_perf_events.h" #include "uvm_perf_module.h" #include "uvm_perf_thrashing.h" @@ -262,6 +263,7 @@ static unsigned uvm_perf_thrashing_pin_threshold = UVM_PERF_THRASHING_PIN_THRESH // detection/prevention parameters #define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT 500 #define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_EMULATION (UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT * 800) +#define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_HCC (UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT * 10) // Lapse of time in microseconds that determines if two consecutive events on // the same page can be considered thrashing @@ -532,18 +534,20 @@ static void gpu_thrashing_stats_destroy(uvm_gpu_t *gpu) // Get the thrashing detection struct for the given VA space if it exists // -// VA space lock needs to be held +// The caller must ensure that the va_space cannot be deleted, for the +// duration of this call. Holding either the va_block or va_space lock will do +// that. static va_space_thrashing_info_t *va_space_thrashing_info_get_or_null(uvm_va_space_t *va_space) { - // TODO: Bug 3898454: check locking requirement for UVM-HMM. - return uvm_perf_module_type_data(va_space->perf_modules_data, UVM_PERF_MODULE_TYPE_THRASHING); } // Get the thrashing detection struct for the given VA space. It asserts that // the information has been previously created. // -// VA space lock needs to be held +// The caller must ensure that the va_space cannot be deleted, for the +// duration of this call. Holding either the va_block or va_space lock will do +// that. static va_space_thrashing_info_t *va_space_thrashing_info_get(uvm_va_space_t *va_space) { va_space_thrashing_info_t *va_space_thrashing = va_space_thrashing_info_get_or_null(va_space); @@ -1783,22 +1787,6 @@ const uvm_page_mask_t *uvm_perf_thrashing_get_thrashing_pages(uvm_va_block_t *va return &block_thrashing->thrashing_pages; } -bool uvm_perf_thrashing_is_block_thrashing(uvm_va_block_t *va_block) -{ - uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - va_space_thrashing_info_t *va_space_thrashing = va_space_thrashing_info_get(va_space); - block_thrashing_info_t *block_thrashing = NULL; - - if (!va_space_thrashing->params.enable) - return false; - - block_thrashing = thrashing_info_get(va_block); - if (!block_thrashing) - return false; - - return block_thrashing->num_thrashing_pages > 0; -} - #define TIMER_GRANULARITY_NS 20000ULL static void thrashing_unpin_pages(struct work_struct *work) { @@ -1854,6 +1842,8 @@ static void thrashing_unpin_pages(struct work_struct *work) break; va_block = pinned_page->va_block; + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_begin_wait(va_block); uvm_mutex_lock(&va_block->lock); // Only operate if the pinned page's tracking state isn't already @@ -1876,6 +1866,8 @@ static void thrashing_unpin_pages(struct work_struct *work) } uvm_mutex_unlock(&va_block->lock); + if (uvm_va_block_is_hmm(va_block)) + uvm_hmm_migrate_finish(va_block); kmem_cache_free(g_pinned_page_cache, pinned_page); } @@ -1947,12 +1939,24 @@ void uvm_perf_thrashing_unload(uvm_va_space_t *va_space) NV_STATUS uvm_perf_thrashing_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu) { // If a simulated GPU is registered, re-initialize thrashing parameters in - // case they need to be adjusted - if (g_uvm_global.num_simulated_devices > 0) { + // case they need to be adjusted. + bool params_need_readjusting = g_uvm_global.num_simulated_devices > 0; + + // Likewise, when the Confidential Computing feature is enabled, the DMA + // path is slower due to cryptographic operations & other associated + // overhead. Enforce a larger window to allow the thrashing mitigation + // mechanisms to work properly. + params_need_readjusting = params_need_readjusting || uvm_conf_computing_mode_enabled(gpu); + + if (params_need_readjusting) { va_space_thrashing_info_t *va_space_thrashing = va_space_thrashing_info_get(va_space); - if (!va_space_thrashing->params.test_overrides) + if (!va_space_thrashing->params.test_overrides) { + if (uvm_conf_computing_mode_enabled(gpu)) + g_uvm_perf_thrashing_lapse_usec = UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_HCC; + va_space_thrashing_info_init_params(va_space_thrashing); + } } return NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.h b/kernel-open/nvidia-uvm/uvm_perf_thrashing.h index eeac8e1a59..d219718c9b 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.h +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.h @@ -84,9 +84,6 @@ uvm_processor_mask_t *uvm_perf_thrashing_get_thrashing_processors(uvm_va_block_t const uvm_page_mask_t *uvm_perf_thrashing_get_thrashing_pages(uvm_va_block_t *va_block); -// Returns true if any page in the block is thrashing, or false otherwise -bool uvm_perf_thrashing_is_block_thrashing(uvm_va_block_t *va_block); - // Global initialization/cleanup functions NV_STATUS uvm_perf_thrashing_init(void); void uvm_perf_thrashing_exit(void); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c index 511430256d..1acbc8a8d3 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c @@ -172,6 +172,7 @@ #include "uvm_va_block.h" #include "uvm_test.h" #include "uvm_linux.h" +#include "uvm_conf_computing.h" static int uvm_global_oversubscription = 1; module_param(uvm_global_oversubscription, int, S_IRUGO); @@ -242,11 +243,13 @@ const char *uvm_pmm_gpu_memory_type_string(uvm_pmm_gpu_memory_type_t type) { switch (type) { UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_USER); + UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED); UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_KERNEL); + UVM_ENUM_STRING_CASE(UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED); UVM_ENUM_STRING_DEFAULT(); } - BUILD_BUG_ON(UVM_PMM_GPU_MEMORY_TYPE_COUNT != 2); + BUILD_BUG_ON(UVM_PMM_GPU_MEMORY_TYPE_COUNT != 4); } const char *uvm_pmm_gpu_chunk_state_string(uvm_pmm_gpu_chunk_state_t state) @@ -454,7 +457,19 @@ bool uvm_pmm_gpu_memory_type_is_user(uvm_pmm_gpu_memory_type_t type) UVM_ASSERT(type < UVM_PMM_GPU_MEMORY_TYPE_COUNT); switch (type) { - case UVM_PMM_GPU_MEMORY_TYPE_USER: + case UVM_PMM_GPU_MEMORY_TYPE_USER: // Alias UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED + case UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED: + return true; + default: + return false; + } +} + +static bool memory_type_is_protected(uvm_pmm_gpu_memory_type_t type) +{ + switch (type) { + case UVM_PMM_GPU_MEMORY_TYPE_USER: // Alias UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED + case UVM_PMM_GPU_MEMORY_TYPE_KERNEL: // Alias UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED: return true; default: return false; @@ -486,11 +501,11 @@ uvm_gpu_t *uvm_gpu_chunk_get_gpu(const uvm_gpu_chunk_t *chunk) struct page *uvm_gpu_chunk_to_page(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) { uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); - NvU64 sys_addr = chunk->address + uvm_gpu_numa_info(gpu)->system_memory_window_start; + NvU64 sys_addr = chunk->address + gpu->parent->system_bus.memory_window_start; unsigned long pfn = sys_addr >> PAGE_SHIFT; - UVM_ASSERT(sys_addr + uvm_gpu_chunk_get_size(chunk) <= uvm_gpu_numa_info(gpu)->system_memory_window_end + 1); - UVM_ASSERT(gpu->parent->numa_info.enabled); + UVM_ASSERT(sys_addr + uvm_gpu_chunk_get_size(chunk) <= gpu->parent->system_bus.memory_window_end + 1); + UVM_ASSERT(gpu->mem_info.numa.enabled); return pfn_to_page(pfn); } @@ -520,7 +535,16 @@ void uvm_pmm_gpu_sync(uvm_pmm_gpu_t *pmm) static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_parent_gpu_t *parent_gpu, uvm_pmm_gpu_memory_type_t type) { - return type; + if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + return type; + + // Enforce the contract that when the Confidential Computing feature is + // disabled, all user types are alike, as well as all kernel types, + // respectively. See uvm_pmm_gpu_memory_type_t. + if (uvm_pmm_gpu_memory_type_is_user(type)) + return UVM_PMM_GPU_MEMORY_TYPE_USER; + + return UVM_PMM_GPU_MEMORY_TYPE_KERNEL; } NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, @@ -622,18 +646,6 @@ static NV_STATUS pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, return NV_OK; } -NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, - size_t num_chunks, - uvm_chunk_size_t chunk_size, - uvm_pmm_alloc_flags_t flags, - uvm_gpu_chunk_t **chunks, - uvm_tracker_t *out_tracker) -{ - uvm_pmm_gpu_memory_type_t memory_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL; - - return pmm_gpu_alloc_kernel(pmm, num_chunks, chunk_size, memory_type, flags, chunks, out_tracker); -} - static void chunk_update_lists_locked(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) { uvm_gpu_root_chunk_t *root_chunk = root_chunk_from_chunk(pmm, chunk); @@ -1535,7 +1547,7 @@ static bool root_chunk_has_elevated_page(uvm_pmm_gpu_t *pmm, uvm_gpu_root_chunk_ uvm_gpu_chunk_t *chunk = &root_chunk->chunk; struct page *page; - if (!gpu->parent->numa_info.enabled) + if (!gpu->mem_info.numa.enabled) return false; page = uvm_gpu_chunk_to_page(pmm, chunk); @@ -2155,7 +2167,7 @@ NV_STATUS alloc_root_chunk(uvm_pmm_gpu_t *pmm, // Also, user pages that are about to be overwritten, don't need to be // zeroed, either. Add an interface to uvm_pmm_gpu_alloc for callers to // specify when they don't need zeroed pages. - const bool skip_pma_scrubbing = gpu->parent->numa_info.enabled; + const bool skip_pma_scrubbing = gpu->mem_info.numa.enabled; UVM_ASSERT(uvm_pmm_gpu_memory_type_is_user(type) || uvm_pmm_gpu_memory_type_is_kernel(type)); options.flags = UVM_PMA_ALLOCATE_DONT_EVICT; @@ -2168,9 +2180,14 @@ NV_STATUS alloc_root_chunk(uvm_pmm_gpu_t *pmm, // TODO: Bug 200480500: Batching is currently disabled on P9. Re-enable // when the performance of best-effort allocations is verified. - if (gpu->parent->numa_info.enabled) + if (gpu->mem_info.numa.enabled) flags |= UVM_PMM_ALLOC_FLAGS_DONT_BATCH; + // When the confidential computing feature is enabled, allocate GPU memory + // in the protected region, unless specified otherwise. + if (uvm_conf_computing_mode_enabled(gpu) && memory_type_is_protected(type)) + options.flags |= UVM_PMA_ALLOCATE_PROTECTED_REGION; + if (!gpu->parent->rm_info.isSimulated && !(options.flags & UVM_PMA_ALLOCATE_PINNED) && !(flags & UVM_PMM_ALLOC_FLAGS_DONT_BATCH)) { @@ -2424,6 +2441,12 @@ static bool check_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) UVM_ASSERT(uvm_global_id_equal(uvm_global_gpu_id_from_index(chunk->gpu_global_index), gpu->global_id)); + // See pmm_squash_memory_type(). + if (!uvm_conf_computing_mode_enabled(gpu)) { + UVM_ASSERT(chunk->type == UVM_PMM_GPU_MEMORY_TYPE_USER || + chunk->type == UVM_PMM_GPU_MEMORY_TYPE_KERNEL); + } + if (chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) UVM_ASSERT(chunk_size > uvm_chunk_find_first_size(chunk_sizes)); @@ -2756,6 +2779,11 @@ static NV_STATUS uvm_pmm_gpu_pma_evict_pages(void *void_pmm, UVM_ASSERT(IS_ALIGNED(UVM_CHUNK_SIZE_MAX, page_size)); UVM_ASSERT(UVM_CHUNK_SIZE_MAX >= page_size); + // Currently, when the Confidential Computing feature is enabled, the + // entirety of vidmem is protected. + if (uvm_conf_computing_mode_enabled(uvm_pmm_to_gpu(pmm)) && (mem_type != UVM_PMA_GPU_MEMORY_TYPE_PROTECTED)) + return NV_ERR_INVALID_ARGUMENT; + while (num_pages_left_to_evict > 0) { uvm_gpu_root_chunk_t *root_chunk; uvm_page_index_t page_index; @@ -2856,7 +2884,7 @@ static NV_STATUS uvm_pmm_gpu_pma_evict_pages_wrapper(void *void_pmm, } static NV_STATUS uvm_pmm_gpu_pma_evict_pages_wrapper_entry(void *void_pmm, - NvU32 page_size, + NvU64 page_size, NvU64 *pages, NvU32 num_pages_to_evict, NvU64 phys_start, @@ -3369,9 +3397,20 @@ static void evict_orphan_pages(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) } if (subchunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED && subchunk->is_referenced) { + unsigned long pfn = uvm_pmm_gpu_devmem_get_pfn(pmm, subchunk); + + // TODO: Bug 3368756: add support for large GPU pages. + UVM_ASSERT(uvm_gpu_chunk_get_size(subchunk) == PAGE_SIZE); uvm_spin_unlock(&pmm->list_lock); - uvm_hmm_pmm_gpu_evict_chunk(uvm_pmm_to_gpu(pmm), subchunk); + // The above check for subchunk state is racy because the + // chunk may be freed after the lock is dropped. It is + // still safe to proceed in that case because the struct + // page reference will have dropped to zero and cannot + // have been re-allocated as this is only called during + // GPU teardown. Therefore migrate_device_range() will + // simply fail. + uvm_hmm_pmm_gpu_evict_pfn(pfn); continue; } @@ -3379,13 +3418,24 @@ static void evict_orphan_pages(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) } } -void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm) +// Free any orphan pages. +// This should be called as part of removing a GPU: after all work is stopped +// and all va_blocks have been destroyed. There normally won't be any +// device private struct page references left but there can be cases after +// fork() where a child process still holds a reference. This function searches +// for pages that still have a reference and migrates the page to the GPU in +// order to release the reference in the CPU page table. +static void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm) { size_t i; if (!pmm->initialized) return; + // This is only safe to call during GPU teardown where chunks + // cannot be re-allocated. + UVM_ASSERT(uvm_gpu_retained_count(uvm_pmm_to_gpu(pmm)) == 0); + // Scan all the root chunks looking for subchunks which are still // referenced. This is slow, but we only do this when unregistering a GPU // and is not critical for performance. @@ -3429,7 +3479,7 @@ static vm_fault_t devmem_fault(struct vm_fault *vmf) { uvm_va_space_t *va_space = vmf->page->zone_device_data; - if (!va_space) + if (!va_space || va_space->va_space_mm.mm != vmf->vma->vm_mm) return VM_FAULT_SIGBUS; return uvm_va_space_cpu_fault_hmm(va_space, vmf->vma, vmf); @@ -3517,6 +3567,10 @@ static NV_STATUS devmem_init(uvm_pmm_gpu_t *pmm) static void devmem_deinit(uvm_pmm_gpu_t *pmm) { } + +static void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm) +{ +} #endif // UVM_IS_CONFIG_HMM() static void process_lazy_free(uvm_pmm_gpu_t *pmm) @@ -3551,8 +3605,11 @@ NV_STATUS uvm_pmm_gpu_init(uvm_pmm_gpu_t *pmm) uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); const uvm_chunk_sizes_mask_t chunk_size_init[][UVM_PMM_GPU_MEMORY_TYPE_COUNT] = { - { gpu->parent->mmu_user_chunk_sizes, gpu->parent->mmu_kernel_chunk_sizes }, - { 0, uvm_mem_kernel_chunk_sizes(gpu)}, + { gpu->parent->mmu_user_chunk_sizes, + gpu->parent->mmu_user_chunk_sizes, + gpu->parent->mmu_kernel_chunk_sizes, + gpu->parent->mmu_kernel_chunk_sizes }, + { 0, 0, uvm_mem_kernel_chunk_sizes(gpu), uvm_mem_kernel_chunk_sizes(gpu)}, }; NV_STATUS status = NV_OK; size_t i, j, k; @@ -3597,13 +3654,13 @@ NV_STATUS uvm_pmm_gpu_init(uvm_pmm_gpu_t *pmm) goto cleanup; // Assert that max physical address of the GPU is not unreasonably big for - // creating the flat array of root chunks. Currently the worst case is a - // Maxwell GPU that has 0.5 GB of its physical memory mapped at the 64GB - // physical address. 256GB should provide reasonable amount of - // future-proofing and results in 128K chunks which is still manageable. - UVM_ASSERT_MSG(gpu->mem_info.max_allocatable_address < 256ull * 1024 * 1024 * 1024, - "Max physical address over 256GB: %llu\n", - gpu->mem_info.max_allocatable_address); + // creating the flat array of root chunks. 256GB should provide a reasonable + // amount of future-proofing and results in 128K chunks which is still + // manageable. + UVM_ASSERT_MSG(gpu->mem_info.max_allocatable_address < UVM_GPU_MAX_PHYS_MEM, + "Max physical address 0x%llx exceeds limit of 0x%llx\n", + gpu->mem_info.max_allocatable_address, + UVM_GPU_MAX_PHYS_MEM); // Align up the size to have a root chunk for the last part of the FB. PMM // won't be able to allocate it, if it doesn't fit a whole root chunk, but @@ -3686,6 +3743,8 @@ void uvm_pmm_gpu_deinit(uvm_pmm_gpu_t *pmm) return; gpu = uvm_pmm_to_gpu(pmm); + + uvm_pmm_gpu_free_orphan_pages(pmm); nv_kthread_q_flush(&gpu->parent->lazy_free_q); UVM_ASSERT(list_empty(&pmm->root_chunks.va_block_lazy_free)); release_free_root_chunks(pmm); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.h b/kernel-open/nvidia-uvm/uvm_pmm_gpu.h index 71f04da798..6337f8575c 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.h @@ -97,9 +97,18 @@ typedef enum { // Memory type for backing user pages. On Pascal+ it can be evicted. UVM_PMM_GPU_MEMORY_TYPE_USER, + // When the Confidential Computing feature is enabled, the protected flavor + // allocates memory out of the VPR region. When it's disabled, all flavors + // have no effects and are equivalent to the base type. + UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED = UVM_PMM_GPU_MEMORY_TYPE_USER, + UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED, // Memory type for internal UVM allocations. It cannot be evicted. UVM_PMM_GPU_MEMORY_TYPE_KERNEL, + // See user types for the behavior description when the Confidential + // Computing feature is ON or OFF. + UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED = UVM_PMM_GPU_MEMORY_TYPE_KERNEL, + UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED, // Number of types - MUST BE LAST. UVM_PMM_GPU_MEMORY_TYPE_COUNT @@ -216,15 +225,6 @@ uvm_gpu_id_t uvm_pmm_devmem_page_to_gpu_id(struct page *page); // Return the PFN of the device private struct page for the given GPU chunk. unsigned long uvm_pmm_gpu_devmem_get_pfn(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk); -// Free any orphan pages. -// This should be called as part of removing a GPU: after all work is stopped -// and all va_blocks have been destroyed. There normally won't be any -// device private struct page references left but there can be cases after -// fork() where a child process still holds a reference. This function searches -// for pages that still have a reference and migrates the page to the GPU in -// order to release the reference in the CPU page table. -void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm); - #endif struct uvm_gpu_chunk_struct @@ -468,6 +468,10 @@ struct page *uvm_gpu_chunk_to_page(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk); // node has to be returned to a valid state before calling either of the APIs. // // In case of an error, the chunks array is guaranteed to be cleared. +// +// If the memory returned by the PMM allocator cannot be physically addressed, +// the MMU interface provides user chunk mapping and unmapping functions +// (uvm_mmu_chunk_map/unmap) that enable virtual addressing. NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, size_t num_chunks, uvm_chunk_size_t chunk_size, @@ -480,21 +484,26 @@ NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, // // Internally calls uvm_pmm_gpu_alloc() and sets the state of all chunks to // allocated on success. -NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, - size_t num_chunks, - uvm_chunk_size_t chunk_size, - uvm_pmm_alloc_flags_t flags, - uvm_gpu_chunk_t **chunks, - uvm_tracker_t *out_tracker); +// +// If Confidential Computing is enabled, this helper allocates protected kernel +// memory. +static NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, + size_t num_chunks, + uvm_chunk_size_t chunk_size, + uvm_pmm_alloc_flags_t flags, + uvm_gpu_chunk_t **chunks, + uvm_tracker_t *out_tracker) +{ + return uvm_pmm_gpu_alloc(pmm, num_chunks, chunk_size, UVM_PMM_GPU_MEMORY_TYPE_KERNEL, flags, chunks, out_tracker); +} // Helper for allocating user memory // // Simple wrapper that just uses UVM_PMM_GPU_MEMORY_TYPE_USER for the memory // type. // -// If the memory returned by the PMM allocator cannot be physically addressed, -// the MMU interface provides user chunk mapping and unmapping functions -// (uvm_mmu_chunk_map/unmap) that enable virtual addressing. +// If Confidential Computing is enabled, this helper allocates protected user +// memory. static NV_STATUS uvm_pmm_gpu_alloc_user(uvm_pmm_gpu_t *pmm, size_t num_chunks, uvm_chunk_size_t chunk_size, diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c b/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c index d9f84ed521..ec4a630dc3 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c @@ -618,7 +618,6 @@ static NV_STATUS cpu_chunk_map_on_cpu(uvm_cpu_chunk_t *chunk, void **cpu_addr) static NV_STATUS test_cpu_chunk_mapping_access(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) { NvU64 dma_addr; - uvm_gpu_phys_address_t gpu_phys_addr; uvm_gpu_address_t gpu_addr; uvm_push_t push; NvU32 *cpu_addr; @@ -630,12 +629,7 @@ static NV_STATUS test_cpu_chunk_mapping_access(uvm_cpu_chunk_t *chunk, uvm_gpu_t memset(cpu_addr, 0, chunk_size); dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); - gpu_phys_addr = uvm_gpu_phys_address(UVM_APERTURE_SYS, dma_addr); - - if (uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) - gpu_addr = uvm_gpu_address_virtual_from_sysmem_phys(gpu, gpu_phys_addr.address); - else - gpu_addr = uvm_gpu_address_from_phys(gpu_phys_addr); + gpu_addr = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(UVM_APERTURE_SYS, dma_addr)); TEST_NV_CHECK_GOTO(uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, diff --git a/kernel-open/nvidia-uvm/uvm_pmm_test.c b/kernel-open/nvidia-uvm/uvm_pmm_test.c index 4f3bb2e4f7..342e62c4b0 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_test.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_test.c @@ -100,6 +100,22 @@ typedef enum // It is duplicated because we do not want to expose it as an API. static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_parent_gpu_t *parent_gpu, uvm_pmm_gpu_memory_type_t type) { + if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + return type; + + // Enforce the contract that when the Confidential Computing feature is + // disabled, all user types are alike, as well as all kernel types, + // respectively. See uvm_pmm_gpu_memory_type_t. + switch (type) { + case UVM_PMM_GPU_MEMORY_TYPE_USER: // Alias UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED + case UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED: + return UVM_PMM_GPU_MEMORY_TYPE_USER; + case UVM_PMM_GPU_MEMORY_TYPE_KERNEL: // Alias UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED + case UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED: + return UVM_PMM_GPU_MEMORY_TYPE_KERNEL; + default: + UVM_ASSERT(0); + } return type; } @@ -306,6 +322,13 @@ static NV_STATUS gpu_mem_check(uvm_gpu_t *gpu, NvU32 *verif_cpu_addr = uvm_mem_get_cpu_addr_kernel(verif_mem); size_t i; + // TODO: Bug 3839176: [UVM][HCC][uvm_test] Update tests that assume GPU + // engines can directly access sysmem + // Skip this test for now. To enable this test under SEV, + // The GPU->CPU CE copy needs to be updated so it uses encryption when + // CC is enabled. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; UVM_ASSERT(verif_mem->size >= size); memset(verif_cpu_addr, 0, size); @@ -341,6 +364,11 @@ static NV_STATUS gpu_mem_check(uvm_gpu_t *gpu, return NV_OK; } +static uvm_gpu_address_t chunk_copy_addr(uvm_gpu_t *gpu, uvm_gpu_chunk_t *chunk) +{ + return uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(UVM_APERTURE_VID, chunk->address)); +} + static NV_STATUS init_test_chunk(uvm_va_space_t *va_space, uvm_pmm_gpu_t *pmm, test_chunk_t *test_chunk, @@ -362,10 +390,7 @@ static NV_STATUS init_test_chunk(uvm_va_space_t *va_space, TEST_NV_CHECK_GOTO(uvm_mmu_chunk_map(test_chunk->chunk), chunk_free); - if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) - chunk_addr = uvm_gpu_address_virtual_from_vidmem_phys(gpu, test_chunk->chunk->address); - else - chunk_addr = uvm_gpu_address_physical(UVM_APERTURE_VID, test_chunk->chunk->address); + chunk_addr = chunk_copy_addr(gpu, test_chunk->chunk); // Fill the chunk TEST_NV_CHECK_GOTO(do_memset_4(gpu, chunk_addr, pattern, size, &test_chunk->tracker), chunk_unmap); @@ -407,15 +432,10 @@ static NV_STATUS destroy_test_chunk(uvm_pmm_gpu_t *pmm, test_chunk_t *test_chunk { uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); NV_STATUS status; - uvm_gpu_address_t chunk_addr; uvm_gpu_chunk_t *chunk = test_chunk->chunk; + uvm_gpu_address_t chunk_addr = chunk_copy_addr(gpu, chunk); uvm_chunk_size_t size = uvm_gpu_chunk_get_size(chunk); - if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) - chunk_addr = uvm_gpu_address_virtual_from_vidmem_phys(gpu, chunk->address); - else - chunk_addr = uvm_gpu_address_physical(UVM_APERTURE_VID, chunk->address); - status = gpu_mem_check(gpu, verif_mem, chunk_addr, size, test_chunk->pattern, &test_chunk->tracker); list_del(&test_chunk->node); @@ -511,7 +531,7 @@ static NV_STATUS basic_test(uvm_va_space_t *va_space, uvm_gpu_t *gpu, if (mode == UvmTestPmmSanityModeBasic) { first_memory_type = UVM_PMM_GPU_MEMORY_TYPE_USER; - last_memory_type = UVM_PMM_GPU_MEMORY_TYPE_USER; + last_memory_type = UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED; first_free_pattern = BASIC_TEST_FREE_PATTERN_EVERY_N; last_free_pattern = BASIC_TEST_FREE_PATTERN_EVERY_N; } @@ -867,6 +887,8 @@ NV_STATUS uvm_test_pmm_check_leak(UVM_TEST_PMM_CHECK_LEAK_PARAMS *params, struct uvm_pmm_gpu_memory_type_t last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER; uvm_pmm_gpu_memory_type_t current_user_mode = first_user_mode; + last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED; + if (params->alloc_limit < -1) return NV_ERR_INVALID_ARGUMENT; @@ -1002,6 +1024,8 @@ NV_STATUS uvm_test_pmm_async_alloc(UVM_TEST_PMM_ASYNC_ALLOC_PARAMS *params, stru uvm_pmm_gpu_memory_type_t last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER; uvm_pmm_gpu_memory_type_t current_user_mode = first_user_mode; + last_user_mode = UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED; + uvm_va_space_down_read(va_space); gpu = uvm_va_space_get_gpu_by_uuid(va_space, ¶ms->gpu_uuid); if (!gpu) { @@ -1226,7 +1250,7 @@ static NV_STATUS test_indirect_peers(uvm_gpu_t *owning_gpu, uvm_gpu_t *accessing } // Check that accessing_gpu can read and write - local_addr = uvm_gpu_address_physical(UVM_APERTURE_VID, chunks[0]->address); + local_addr = chunk_copy_addr(owning_gpu, chunks[0]); peer_addr = uvm_pmm_gpu_peer_copy_address(&owning_gpu->pmm, chunks[0], accessing_gpu); // Init on local GPU @@ -1391,7 +1415,7 @@ NV_STATUS uvm_test_pmm_chunk_with_elevated_page(UVM_TEST_PMM_CHUNK_WITH_ELEVATED uvm_va_space_down_read(va_space); for_each_va_space_gpu(gpu, va_space) { - if (!gpu->parent->numa_info.enabled) + if (!gpu->mem_info.numa.enabled) continue; ran_test = true; diff --git a/kernel-open/nvidia-uvm/uvm_policy.c b/kernel-open/nvidia-uvm/uvm_policy.c index 66f5033df3..5220b96b2d 100644 --- a/kernel-open/nvidia-uvm/uvm_policy.c +++ b/kernel-open/nvidia-uvm/uvm_policy.c @@ -30,7 +30,7 @@ #include "uvm_gpu.h" #include "uvm_va_space_mm.h" -bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length) +static bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length) { const NvU64 end = start + length; struct vm_area_struct *vma; @@ -50,7 +50,7 @@ bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length) return false; } -NV_STATUS uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length) +uvm_api_range_type_t uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length) { uvm_va_range_t *va_range, *va_range_last; const NvU64 last_address = base + length - 1; @@ -61,21 +61,23 @@ NV_STATUS uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *m uvm_assert_rwsem_locked(&va_space->lock); if (uvm_api_range_invalid(base, length)) - return NV_ERR_INVALID_ADDRESS; + return UVM_API_RANGE_TYPE_INVALID; // Check if passed interval overlaps with any VA range. if (uvm_va_space_range_empty(va_space, base, last_address)) { if (g_uvm_global.ats.enabled && uvm_va_space_pageable_mem_access_supported(va_space) && mm && - uvm_is_valid_vma_range(mm, base, length)) - return NV_WARN_NOTHING_TO_DO; - else if (uvm_hmm_is_enabled(va_space) && - mm && - uvm_is_valid_vma_range(mm, base, length)) - return NV_OK; - else - return NV_ERR_INVALID_ADDRESS; + uvm_is_valid_vma_range(mm, base, length)) { + + return UVM_API_RANGE_TYPE_ATS; + } + else if (uvm_hmm_is_enabled(va_space) && mm && uvm_is_valid_vma_range(mm, base, length)) { + return UVM_API_RANGE_TYPE_HMM; + } + else { + return UVM_API_RANGE_TYPE_INVALID; + } } va_range_last = NULL; @@ -86,10 +88,10 @@ NV_STATUS uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *m // Check if passed interval overlaps with an unmanaged VA range, or a // sub-interval not tracked by a VA range if (!va_range_last || va_range_last->node.end < last_address) - return NV_ERR_INVALID_ADDRESS; + return UVM_API_RANGE_TYPE_INVALID; // Passed interval is fully covered by managed VA ranges - return NV_OK; + return UVM_API_RANGE_TYPE_MANAGED; } static NV_STATUS split_as_needed(uvm_va_space_t *va_space, @@ -282,7 +284,7 @@ static NV_STATUS preferred_location_set(uvm_va_space_t *va_space, NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS *params, struct file *filp) { - NV_STATUS status; + NV_STATUS status = NV_OK; NV_STATUS tracker_status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); uvm_va_space_t *va_space = uvm_va_space_get(filp); @@ -294,7 +296,7 @@ NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS const NvU64 start = params->requestedBase; const NvU64 length = params->length; const NvU64 end = start + length - 1; - bool range_is_ats = false; + uvm_api_range_type_t type; UVM_ASSERT(va_space); @@ -302,13 +304,10 @@ NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS uvm_va_space_down_write(va_space); has_va_space_write_lock = true; - status = uvm_api_range_type_check(va_space, mm, start, length); - if (status != NV_OK) { - if (status != NV_WARN_NOTHING_TO_DO) - goto done; - - status = NV_OK; - range_is_ats = true; + type = uvm_api_range_type_check(va_space, mm, start, length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; } // If the CPU is the preferred location, we don't have to find the associated uvm_gpu_t @@ -333,10 +332,23 @@ NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS UVM_ASSERT(status == NV_OK); - // TODO: Bug 2098544: On ATS systems, honor the preferred location policy - // for system memory ranges instead of ignoring it. - if (range_is_ats) + // UvmSetPreferredLocation on non-ATS regions targets the VA range of the + // associated file descriptor, not the calling process. Since + // UvmSetPreferredLocation on ATS regions are handled in userspace, + // implementing the non-ATS behavior is not possible. So, return an error + // instead. Although the out of process case can be supported for HMM, + // return an error to make the API behavior consistent for all SAM regions. + if ((type != UVM_API_RANGE_TYPE_MANAGED) && (current->mm != mm)) { + status = NV_ERR_NOT_SUPPORTED; goto done; + } + + // For ATS regions, let userspace handle it. + if (type == UVM_API_RANGE_TYPE_ATS) { + UVM_ASSERT(g_uvm_global.ats.enabled); + status = NV_WARN_NOTHING_TO_DO; + goto done; + } status = preferred_location_set(va_space, mm, start, length, preferred_location_id, &first_va_range_to_migrate, &local_tracker); if (status != NV_OK) @@ -384,19 +396,38 @@ NV_STATUS uvm_api_unset_preferred_location(const UVM_UNSET_PREFERRED_LOCATION_PA uvm_va_space_t *va_space = uvm_va_space_get(filp); struct mm_struct *mm; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); + uvm_api_range_type_t type; UVM_ASSERT(va_space); mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); - status = uvm_api_range_type_check(va_space, mm, params->requestedBase, params->length); + type = uvm_api_range_type_check(va_space, mm, params->requestedBase, params->length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; + } - if (status == NV_OK) - status = preferred_location_set(va_space, mm, params->requestedBase, params->length, UVM_ID_INVALID, NULL, &local_tracker); - else if (status == NV_WARN_NOTHING_TO_DO) - status = NV_OK; + if ((type != UVM_API_RANGE_TYPE_MANAGED) && (current->mm != mm)) { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + if (type == UVM_API_RANGE_TYPE_ATS) { + status = NV_WARN_NOTHING_TO_DO; + goto done; + } + + status = preferred_location_set(va_space, + mm, + params->requestedBase, + params->length, + UVM_ID_INVALID, + NULL, + &local_tracker); + +done: tracker_status = uvm_tracker_wait_deinit(&local_tracker); uvm_va_space_up_write(va_space); @@ -483,26 +514,23 @@ static NV_STATUS accessed_by_set(uvm_va_space_t *va_space, bool set_bit) { uvm_processor_id_t processor_id = UVM_ID_INVALID; - uvm_va_range_t *va_range, *va_range_last; struct mm_struct *mm; const NvU64 last_address = base + length - 1; - bool range_is_sysmem = false; accessed_by_split_params_t split_params; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); - NV_STATUS status; + NV_STATUS status = NV_OK; NV_STATUS tracker_status; + uvm_api_range_type_t type; UVM_ASSERT(va_space); mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); - status = uvm_api_range_type_check(va_space, mm, base, length); - if (status != NV_OK) { - if (status != NV_WARN_NOTHING_TO_DO) - goto done; - status = NV_OK; - range_is_sysmem = true; + type = uvm_api_range_type_check(va_space, mm, base, length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; } if (uvm_uuid_is_cpu(processor_uuid)) { @@ -523,8 +551,10 @@ static NV_STATUS accessed_by_set(uvm_va_space_t *va_space, processor_id = gpu->id; } - if (range_is_sysmem) + if (type == UVM_API_RANGE_TYPE_ATS) { + status = NV_OK; goto done; + } split_params.processor_id = processor_id; split_params.set_bit = set_bit; @@ -536,36 +566,35 @@ static NV_STATUS accessed_by_set(uvm_va_space_t *va_space, if (status != NV_OK) goto done; - va_range_last = NULL; - uvm_for_each_managed_va_range_in_contig(va_range, va_space, base, last_address) { - va_range_last = va_range; + if (type == UVM_API_RANGE_TYPE_MANAGED) { + uvm_va_range_t *va_range; + uvm_va_range_t *va_range_last = NULL; - // If we didn't split the ends, check that they match - if (va_range->node.start < base || va_range->node.end > last_address) - UVM_ASSERT(uvm_processor_mask_test(&uvm_va_range_get_policy(va_range)->accessed_by, - processor_id) == set_bit); + uvm_for_each_managed_va_range_in_contig(va_range, va_space, base, last_address) { + va_range_last = va_range; - if (set_bit) { - status = uvm_va_range_set_accessed_by(va_range, processor_id, mm, &local_tracker); - if (status != NV_OK) - goto done; - } - else { - uvm_va_range_unset_accessed_by(va_range, processor_id, &local_tracker); + // If we didn't split the ends, check that they match + if (va_range->node.start < base || va_range->node.end > last_address) + UVM_ASSERT(uvm_processor_mask_test(&uvm_va_range_get_policy(va_range)->accessed_by, + processor_id) == set_bit); + + if (set_bit) { + status = uvm_va_range_set_accessed_by(va_range, processor_id, mm, &local_tracker); + if (status != NV_OK) + goto done; + } + else { + uvm_va_range_unset_accessed_by(va_range, processor_id, &local_tracker); + } } - } - if (va_range_last) { + UVM_ASSERT(va_range_last); UVM_ASSERT(va_range_last->node.end >= last_address); - goto done; } - - status = uvm_hmm_set_accessed_by(va_space, - processor_id, - set_bit, - base, - last_address, - &local_tracker); + else { + UVM_ASSERT(type == UVM_API_RANGE_TYPE_HMM); + status = uvm_hmm_set_accessed_by(va_space, processor_id, set_bit, base, last_address, &local_tracker); + } done: tracker_status = uvm_tracker_wait_deinit(&local_tracker); @@ -756,11 +785,11 @@ static bool read_duplication_is_split_needed(const uvm_va_policy_t *policy, void static NV_STATUS read_duplication_set(uvm_va_space_t *va_space, NvU64 base, NvU64 length, bool enable) { - uvm_va_range_t *va_range, *va_range_last; struct mm_struct *mm; const NvU64 last_address = base + length - 1; NV_STATUS status; uvm_read_duplication_policy_t new_policy; + uvm_api_range_type_t type; UVM_ASSERT(va_space); @@ -768,11 +797,13 @@ static NV_STATUS read_duplication_set(uvm_va_space_t *va_space, NvU64 base, NvU6 mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); - status = uvm_api_range_type_check(va_space, mm, base, length); - if (status != NV_OK) { - if (status == NV_WARN_NOTHING_TO_DO) - status = NV_OK; - + type = uvm_api_range_type_check(va_space, mm, base, length); + if (type == UVM_API_RANGE_TYPE_INVALID) { + status = NV_ERR_INVALID_ADDRESS; + goto done; + } + else if (type == UVM_API_RANGE_TYPE_ATS) { + status = NV_OK; goto done; } @@ -787,43 +818,44 @@ static NV_STATUS read_duplication_set(uvm_va_space_t *va_space, NvU64 base, NvU6 if (status != NV_OK) goto done; - va_range_last = NULL; - uvm_for_each_managed_va_range_in_contig(va_range, va_space, base, last_address) { - va_range_last = va_range; + if (type == UVM_API_RANGE_TYPE_MANAGED) { + uvm_va_range_t *va_range; + uvm_va_range_t *va_range_last = NULL; - // If we didn't split the ends, check that they match - if (va_range->node.start < base || va_range->node.end > last_address) - UVM_ASSERT(uvm_va_range_get_policy(va_range)->read_duplication == new_policy); + uvm_for_each_managed_va_range_in_contig(va_range, va_space, base, last_address) { + va_range_last = va_range; - // If the va_space cannot currently read duplicate, only change the user - // state. All memory should already have read duplication unset. - if (uvm_va_space_can_read_duplicate(va_space, NULL)) { + // If we didn't split the ends, check that they match + if (va_range->node.start < base || va_range->node.end > last_address) + UVM_ASSERT(uvm_va_range_get_policy(va_range)->read_duplication == new_policy); - // Handle SetAccessedBy mappings - if (new_policy == UVM_READ_DUPLICATION_ENABLED) { - status = uvm_va_range_set_read_duplication(va_range, mm); - if (status != NV_OK) - goto done; - } - else { - // If unsetting read duplication fails, the return status is - // not propagated back to the caller - (void)uvm_va_range_unset_read_duplication(va_range, mm); + // If the va_space cannot currently read duplicate, only change the user + // state. All memory should already have read duplication unset. + if (uvm_va_space_can_read_duplicate(va_space, NULL)) { + + // Handle SetAccessedBy mappings + if (new_policy == UVM_READ_DUPLICATION_ENABLED) { + status = uvm_va_range_set_read_duplication(va_range, mm); + if (status != NV_OK) + goto done; + } + else { + // If unsetting read duplication fails, the return status is + // not propagated back to the caller + (void)uvm_va_range_unset_read_duplication(va_range, mm); + } } - } - uvm_va_range_get_policy(va_range)->read_duplication = new_policy; - } + uvm_va_range_get_policy(va_range)->read_duplication = new_policy; + } - if (va_range_last) { + UVM_ASSERT(va_range_last); UVM_ASSERT(va_range_last->node.end >= last_address); - goto done; } - - status = uvm_hmm_set_read_duplication(va_space, - new_policy, - base, - last_address); + else { + UVM_ASSERT(type == UVM_API_RANGE_TYPE_HMM); + status = uvm_hmm_set_read_duplication(va_space, new_policy, base, last_address); + } done: uvm_va_space_up_write(va_space); diff --git a/kernel-open/nvidia-uvm/uvm_populate_pageable.c b/kernel-open/nvidia-uvm/uvm_populate_pageable.c index 17a54234a4..1967e1bdf8 100644 --- a/kernel-open/nvidia-uvm/uvm_populate_pageable.c +++ b/kernel-open/nvidia-uvm/uvm_populate_pageable.c @@ -30,6 +30,14 @@ #include "uvm_va_space.h" #include "uvm_populate_pageable.h" +#if defined(NV_HANDLE_MM_FAULT_HAS_MM_ARG) +#define UVM_HANDLE_MM_FAULT(vma, addr, flags) handle_mm_fault(vma->vm_mm, vma, addr, flags) +#elif defined(NV_HANDLE_MM_FAULT_HAS_PT_REGS_ARG) +#define UVM_HANDLE_MM_FAULT(vma, addr, flags) handle_mm_fault(vma, addr, flags, NULL) +#else +#define UVM_HANDLE_MM_FAULT(vma, addr, flags) handle_mm_fault(vma, addr, flags) +#endif + static bool is_write_populate(struct vm_area_struct *vma, uvm_populate_permissions_t populate_permissions) { switch (populate_permissions) { @@ -45,6 +53,34 @@ static bool is_write_populate(struct vm_area_struct *vma, uvm_populate_permissio } } +NV_STATUS uvm_handle_fault(struct vm_area_struct *vma, unsigned long start, unsigned long vma_num_pages, bool write) +{ + NV_STATUS status = NV_OK; + + unsigned long i; + unsigned int ret = 0; + unsigned int fault_flags = write ? FAULT_FLAG_WRITE : 0; + +#ifdef FAULT_FLAG_REMOTE + fault_flags |= (FAULT_FLAG_REMOTE); +#endif + + for (i = 0; i < vma_num_pages; i++) { + ret = UVM_HANDLE_MM_FAULT(vma, start + (i * PAGE_SIZE), fault_flags); + if (ret & VM_FAULT_ERROR) { +#if defined(NV_VM_FAULT_TO_ERRNO_PRESENT) + int err = vm_fault_to_errno(ret, fault_flags); + status = errno_to_nv_status(err); +#else + status = errno_to_nv_status(-EFAULT); +#endif + break; + } + } + + return status; +} + NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma, unsigned long start, unsigned long length, @@ -97,6 +133,10 @@ NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma, if (uvm_managed_vma) uvm_record_unlock_mmap_lock_read(mm); + status = uvm_handle_fault(vma, start, vma_num_pages, !!(gup_flags & FOLL_WRITE)); + if (status != NV_OK) + goto out; + if (touch) ret = NV_PIN_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL, NULL); else diff --git a/kernel-open/nvidia-uvm/uvm_pte_batch.c b/kernel-open/nvidia-uvm/uvm_pte_batch.c index 64fdb54963..e8360e34c3 100644 --- a/kernel-open/nvidia-uvm/uvm_pte_batch.c +++ b/kernel-open/nvidia-uvm/uvm_pte_batch.c @@ -54,7 +54,7 @@ static void uvm_pte_batch_flush_ptes_inline(uvm_pte_batch_t *batch) uvm_push_set_flag(batch->push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); uvm_push_set_flag(batch->push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); gpu->parent->ce_hal->memcopy(batch->push, - uvm_gpu_address_from_phys(batch->pte_first_address), + uvm_mmu_gpu_address(gpu, batch->pte_first_address), inline_data_addr, ptes_size); } @@ -62,7 +62,7 @@ static void uvm_pte_batch_flush_ptes_inline(uvm_pte_batch_t *batch) static void uvm_pte_batch_flush_ptes_memset(uvm_pte_batch_t *batch) { uvm_gpu_t *gpu = uvm_push_get_gpu(batch->push); - uvm_gpu_address_t addr = uvm_gpu_address_from_phys(batch->pte_first_address); + uvm_gpu_address_t addr = uvm_mmu_gpu_address(gpu, batch->pte_first_address); NvU32 i; UVM_ASSERT(batch->pte_count != 0); @@ -201,7 +201,7 @@ void uvm_pte_batch_clear_ptes(uvm_pte_batch_t *batch, uvm_gpu_phys_address_t fir uvm_push_set_flag(batch->push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); uvm_push_set_flag(batch->push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); gpu->parent->ce_hal->memset_8(batch->push, - uvm_gpu_address_from_phys(first_pte), + uvm_mmu_gpu_address(gpu, first_pte), empty_pte_bits, entry_size * entry_count); diff --git a/kernel-open/nvidia-uvm/uvm_push.c b/kernel-open/nvidia-uvm/uvm_push.c index 07fd4828be..58c643e20a 100644 --- a/kernel-open/nvidia-uvm/uvm_push.c +++ b/kernel-open/nvidia-uvm/uvm_push.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -351,11 +351,11 @@ void *uvm_push_inline_data_get(uvm_push_inline_data_t *data, size_t size) UVM_ASSERT(!uvm_global_is_suspended()); UVM_ASSERT_MSG(uvm_push_get_size(data->push) + uvm_push_inline_data_size(data) + UVM_METHOD_SIZE + size <= UVM_MAX_PUSH_SIZE, - "push size %u inline data size %zu new data size %zu max push %u\n", - uvm_push_get_size(data->push), uvm_push_inline_data_size(data), size, UVM_MAX_PUSH_SIZE); + "push size %u inline data size %zu new data size %zu max push %u\n", + uvm_push_get_size(data->push), uvm_push_inline_data_size(data), size, UVM_MAX_PUSH_SIZE); UVM_ASSERT_MSG(uvm_push_inline_data_size(data) + size <= UVM_PUSH_INLINE_DATA_MAX_SIZE, - "inline data size %zu new data size %zu max %u\n", - uvm_push_inline_data_size(data), size, UVM_PUSH_INLINE_DATA_MAX_SIZE); + "inline data size %zu new data size %zu max %u\n", + uvm_push_inline_data_size(data), size, UVM_PUSH_INLINE_DATA_MAX_SIZE); data->next_data += size; @@ -368,6 +368,7 @@ void *uvm_push_inline_data_get_aligned(uvm_push_inline_data_t *data, size_t size size_t offset = 0; char *buffer; + UVM_ASSERT(alignment <= UVM_PAGE_SIZE_4K); UVM_ASSERT_MSG(IS_ALIGNED(alignment, UVM_METHOD_SIZE), "alignment %zu\n", alignment); offset = UVM_ALIGN_UP(next_ptr, alignment) - next_ptr; @@ -404,16 +405,16 @@ uvm_gpu_address_t uvm_push_inline_data_end(uvm_push_inline_data_t *data) return uvm_gpu_address_virtual(inline_data_address); } -// Same as uvm_push_get_single_inline_buffer() but provides the specified -// alignment. -static void *push_get_single_inline_buffer_aligned(uvm_push_t *push, - size_t size, - size_t alignment, - uvm_gpu_address_t *gpu_address) +void *uvm_push_get_single_inline_buffer(uvm_push_t *push, + size_t size, + size_t alignment, + uvm_gpu_address_t *gpu_address) { uvm_push_inline_data_t data; void *buffer; + UVM_ASSERT(IS_ALIGNED(alignment, UVM_METHOD_SIZE)); + uvm_push_inline_data_begin(push, &data); buffer = uvm_push_inline_data_get_aligned(&data, size, alignment); *gpu_address = uvm_push_inline_data_end(&data); @@ -423,11 +424,6 @@ static void *push_get_single_inline_buffer_aligned(uvm_push_t *push, return buffer; } -void *uvm_push_get_single_inline_buffer(uvm_push_t *push, size_t size, uvm_gpu_address_t *gpu_address) -{ - return push_get_single_inline_buffer_aligned(push, size, UVM_METHOD_SIZE, gpu_address); -} - NvU64 *uvm_push_timestamp(uvm_push_t *push) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); @@ -435,12 +431,15 @@ NvU64 *uvm_push_timestamp(uvm_push_t *push) NvU64 *timestamp; uvm_gpu_address_t address; - timestamp = (NvU64 *)push_get_single_inline_buffer_aligned(push, timestamp_size, timestamp_size, &address); + timestamp = (NvU64 *)uvm_push_get_single_inline_buffer(push, timestamp_size, timestamp_size, &address); + // Timestamp is in the second half of the 16 byte semaphore release timestamp += 1; if (uvm_channel_is_ce(push->channel)) gpu->parent->ce_hal->semaphore_timestamp(push, address.address); + else if (uvm_channel_is_sec2(push->channel)) + gpu->parent->sec2_hal->semaphore_timestamp(push, address.address); else UVM_ASSERT_MSG(0, "Semaphore release timestamp on an unsupported channel.\n"); @@ -457,6 +456,8 @@ bool uvm_push_method_is_valid(uvm_push_t *push, NvU8 subch, NvU32 method_address return gpu->parent->host_hal->method_is_valid(push, method_address, method_data); else if (subch == UVM_SW_OBJ_SUBCHANNEL) return gpu->parent->host_hal->sw_method_is_valid(push, method_address, method_data); + else if (subch == UVM_SUBCHANNEL_SEC2) + return true; UVM_ERR_PRINT("Unsupported subchannel 0x%x\n", subch); return false; diff --git a/kernel-open/nvidia-uvm/uvm_push.h b/kernel-open/nvidia-uvm/uvm_push.h index 8c29156615..c4b5a54240 100644 --- a/kernel-open/nvidia-uvm/uvm_push.h +++ b/kernel-open/nvidia-uvm/uvm_push.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -31,10 +31,6 @@ #include "uvm_tracker.h" #include "nvtypes.h" -// Space (in bytes) used by uvm_push_end() on a CE channel. -// This is the storage required by a semaphore release. -#define UVM_PUSH_CE_END_SIZE 24 - // The max amount of inline push data is limited by how much space can be jumped // over with a single NOOP method. #define UVM_PUSH_INLINE_DATA_MAX_SIZE (UVM_METHOD_COUNT_MAX * UVM_METHOD_SIZE) @@ -93,6 +89,12 @@ struct uvm_push_struct // A bitmap of flags from uvm_push_flag_t DECLARE_BITMAP(flags, UVM_PUSH_FLAG_COUNT); + + // IV to use when launching WLC push + UvmCslIv launch_iv; + + // Channel to use for indirect submission + uvm_channel_t *launch_channel; }; #define UVM_PUSH_ACQUIRE_INFO_MAX_ENTRIES 16 @@ -127,7 +129,7 @@ struct uvm_push_acquire_info_struct }; } values[UVM_PUSH_ACQUIRE_INFO_MAX_ENTRIES]; - NvU32 num_values; + NvU32 num_values; }; struct uvm_push_info_struct @@ -361,9 +363,17 @@ static bool uvm_push_has_space(uvm_push_t *push, NvU32 free_space) // These do just enough for inline push data and uvm_push_get_gpu() to work. // Used by tests that run on fake GPUs without a channel manager (see // uvm_page_tree_test.c for an example). +// When the Confidential Computing feature is enabled, LCIC channels also use +// fake push for other things, like encrypting semaphore values to unprotected +// sysmem. NV_STATUS uvm_push_begin_fake(uvm_gpu_t *gpu, uvm_push_t *push); void uvm_push_end_fake(uvm_push_t *push); +static bool uvm_push_is_fake(uvm_push_t *push) +{ + return !push->channel; +} + // Begin an inline data fragment in the push // // The inline data will be ignored by the GPU, but can be referenced from @@ -380,6 +390,7 @@ void uvm_push_end_fake(uvm_push_t *push); static void uvm_push_inline_data_begin(uvm_push_t *push, uvm_push_inline_data_t *data) { data->push = push; + // +1 for the NOOP method inserted at inline_data_end() data->next_data = (char*)(push->next + 1); } @@ -407,7 +418,8 @@ void *uvm_push_inline_data_get(uvm_push_inline_data_t *data, size_t size); // Same as uvm_push_inline_data_get() but provides the specified alignment. void *uvm_push_inline_data_get_aligned(uvm_push_inline_data_t *data, size_t size, size_t alignment); -// Get a single buffer of size bytes of inline data in the push +// Get a single buffer of size bytes of inline data in the push, alignment must +// be positive and a multiple of UVM_METHOD_SIZE. // // Returns the CPU pointer to the beginning of the buffer. The buffer can be // accessed as long as the push is on-going. Also returns the GPU address of the @@ -415,7 +427,10 @@ void *uvm_push_inline_data_get_aligned(uvm_push_inline_data_t *data, size_t size // // This is a wrapper around uvm_push_inline_data_begin() and // uvm_push_inline_data_end() so see their comments for more details. -void *uvm_push_get_single_inline_buffer(uvm_push_t *push, size_t size, uvm_gpu_address_t *gpu_address); +void *uvm_push_get_single_inline_buffer(uvm_push_t *push, + size_t size, + size_t alignment, + uvm_gpu_address_t *gpu_address); // Helper that copies size bytes of data from src into the inline data fragment static void uvm_push_inline_data_add(uvm_push_inline_data_t *data, const void *src, size_t size) diff --git a/kernel-open/nvidia-uvm/uvm_push_macros.h b/kernel-open/nvidia-uvm/uvm_push_macros.h index 4b50638ac0..0e6359af58 100644 --- a/kernel-open/nvidia-uvm/uvm_push_macros.h +++ b/kernel-open/nvidia-uvm/uvm_push_macros.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -108,6 +108,14 @@ // value. For example, Kepler reserves subchannels 5-7 for software objects. #define UVM_SUBCHANNEL_C076 UVM_SW_OBJ_SUBCHANNEL +// NVA06F_SUBCHANNEL_COMPUTE is a semi-arbitrary value for UVM_SUBCHANNEL_SEC2. +// We need a "unique" subchannel across all subchannels UVM submits work. This +// is used when we are post-processing a pushbuffer and we need to extract SEC2 +// methods from a it, having a unique subchannel facilitates the SEC2 method +// identification. +#define UVM_SUBCHANNEL_SEC2 NVA06F_SUBCHANNEL_COMPUTE +#define UVM_SUBCHANNEL_CBA2 UVM_SUBCHANNEL_SEC2 + #define UVM_METHOD_SIZE 4 #define UVM_METHOD_COUNT_MAX HWMASK(B06F, DMA, INCR_COUNT) #if HWMASK(B06F, DMA, INCR_COUNT) != HWMASK(B06F, DMA, NONINCR_COUNT) @@ -126,29 +134,29 @@ HWVALUE(B06F, DMA, NONINCR_SUBCHANNEL, (subch)) | \ HWVALUE(B06F, DMA, NONINCR_COUNT, (count))) -#define __UVM_ASSERT_CONTIGUOUS_METHODS(a1, a2) BUILD_BUG_ON((a2) - (a1) != 4) +#define __UVM_ASSERT_CONTIGUOUS_METHODS(a1, a2) BUILD_BUG_ON((a2) - (a1) != UVM_METHOD_SIZE) // __NV_PUSH_*U support being called recursively from the N+1 sized method with // the _0U doing all the common things. // Notably all the push macros assume that symbol "push" of type uvm_push_t * is // in scope. -#define __NV_PUSH_0U(subch, count, a1) \ - do { \ - UVM_ASSERT(!uvm_global_is_suspended()); \ - UVM_ASSERT(uvm_push_get_size(push) + (count + 1) * 4 <= UVM_MAX_PUSH_SIZE); \ - UVM_ASSERT_MSG(a1 % 4 == 0, "Address %u\n", a1); \ - \ - push->next[0] = UVM_METHOD_INC(subch, a1, count); \ - ++push->next; \ +#define __NV_PUSH_0U(subch, count, a1) \ + do { \ + UVM_ASSERT(!uvm_global_is_suspended()); \ + UVM_ASSERT(uvm_push_get_size(push) + (count + 1) * UVM_METHOD_SIZE <= UVM_MAX_PUSH_SIZE); \ + UVM_ASSERT_MSG(IS_ALIGNED(a1, UVM_METHOD_SIZE), "Address %u\n", a1); \ + \ + push->next[0] = UVM_METHOD_INC(subch, a1, count); \ + ++push->next; \ } while (0) #define __NV_PUSH_1U(subch, count, a1,d1) \ do { \ __NV_PUSH_0U(subch, count, a1); \ - push->next[0] = d1; \ UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a1, d1), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ + push->next[0] = d1; \ ++push->next; \ } while (0) @@ -157,8 +165,8 @@ __UVM_ASSERT_CONTIGUOUS_METHODS(a1, a2); \ __NV_PUSH_1U(subch, count, a1,d1); \ UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a2, d2), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d2; \ ++push->next; \ } while (0) @@ -168,8 +176,8 @@ __UVM_ASSERT_CONTIGUOUS_METHODS(a2, a3); \ __NV_PUSH_2U(subch, count, a1,d1, a2,d2); \ UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a3, d3), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d3; \ ++push->next; \ } while (0) @@ -179,8 +187,8 @@ __UVM_ASSERT_CONTIGUOUS_METHODS(a3, a4); \ __NV_PUSH_3U(subch, count, a1,d1, a2,d2, a3,d3); \ UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a4, d4), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d4; \ ++push->next; \ } while (0) @@ -190,8 +198,8 @@ __UVM_ASSERT_CONTIGUOUS_METHODS(a4, a5); \ __NV_PUSH_4U(subch, count, a1,d1, a2,d2, a3,d3, a4,d4); \ UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a5, d5), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d5; \ ++push->next; \ } while (0) @@ -201,8 +209,8 @@ __UVM_ASSERT_CONTIGUOUS_METHODS(a5, a6); \ __NV_PUSH_5U(subch, count, a1,d1, a2,d2, a3,d3, a4,d4, a5,d5); \ UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a6, d6), \ - "Method validation failed in channel %s\n", \ - push->channel->name); \ + "Method validation failed in channel %s\n", \ + push->channel->name); \ push->next[0] = d6; \ ++push->next; \ } while (0) @@ -248,13 +256,13 @@ // Non-incrementing method with count data fields following it. The data is left // untouched and hence it's primarily useful for a NOP method. -#define __NV_PUSH_NU_NONINC(subch, count, address) \ - do { \ - UVM_ASSERT(!uvm_global_is_suspended()); \ - UVM_ASSERT(uvm_push_get_size(push) + (count + 1) * 4 <= UVM_MAX_PUSH_SIZE); \ - UVM_ASSERT_MSG(address % 4 == 0, "Address %u\n", address); \ - push->next[0] = UVM_METHOD_NONINC(subch, address, count); \ - push->next += count + 1; \ +#define __NV_PUSH_NU_NONINC(subch, count, address) \ + do { \ + UVM_ASSERT(!uvm_global_is_suspended()); \ + UVM_ASSERT(uvm_push_get_size(push) + (count + 1) * UVM_METHOD_SIZE <= UVM_MAX_PUSH_SIZE); \ + UVM_ASSERT_MSG(IS_ALIGNED(address, UVM_METHOD_SIZE), "Address %u\n", address); \ + push->next[0] = UVM_METHOD_NONINC(subch, address, count); \ + push->next += count + 1; \ } while (0) #define NV_PUSH_NU_NONINC(class, a1, count) \ diff --git a/kernel-open/nvidia-uvm/uvm_push_test.c b/kernel-open/nvidia-uvm/uvm_push_test.c index fba9880363..148bdbe730 100644 --- a/kernel-open/nvidia-uvm/uvm_push_test.c +++ b/kernel-open/nvidia-uvm/uvm_push_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -38,10 +38,78 @@ #define TEST_PUSH_INTERLEAVING_NUM_PAUSED_PUSHES 2 -static NvU32 get_push_end_size(uvm_channel_t *channel) +static NvU32 get_push_begin_size(uvm_channel_t *channel) { - if (uvm_channel_is_ce(channel)) - return UVM_PUSH_CE_END_SIZE; + if (uvm_channel_is_sec2(channel)) { + // SEC2 channels allocate CSL signature buffer at the beginning. + return UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE + UVM_METHOD_SIZE; + } + + return 0; +} + +// This is the storage required by a semaphore release. +static NvU32 get_push_end_min_size(uvm_channel_t *channel) +{ + if (uvm_channel_is_ce(channel)) { + if (uvm_channel_is_wlc(channel)) { + // Space (in bytes) used by uvm_push_end() on a Secure CE channel. + // Note that Secure CE semaphore release pushes two memset and one + // encryption method on top of the regular release. + // Memset size + // ------------- + // PUSH_2U (SET_REMAP) : 3 Words + // PUSH_2U (OFFSET_OUT) : 3 Words + // PUSH_1U (LINE_LENGTH_IN) : 2 Words + // PUSH_1U (LAUNCH_DMA) : 2 Words + // Total 10 * UVM_METHOD_SIZE : 40 Bytes + // + // Encrypt size + // ------------- + // PUSH_1U (SET_SECURE_COPY_MODE) : 2 Words + // PUSH_4U (ENCRYPT_AUTH_TAG + IV) : 5 Words + // PUSH_4U (OFFSET_IN_OUT) : 5 Words + // PUSH_2U (LINE_LENGTH_IN) : 2 Words + // PUSH_2U (LAUNCH_DMA) : 2 Words + // Total 16 * UVM_METHOD_SIZE : 64 Bytes + // + // TOTAL : 144 Bytes + + // Same as CE + LCIC GPPut update + LCIC doorbell + return 24 + 144 + 24 + 24; + } + else if (uvm_channel_is_secure_ce(channel)) { + return 24 + 144; + } + // Space (in bytes) used by uvm_push_end() on a CE channel. + return 24; + } + else if (uvm_channel_is_sec2(channel)) { + // A perfectly aligned inline buffer in SEC2 semaphore release. + // We add UVM_METHOD_SIZE because of the NOP method to reserve + // UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES (the inline buffer.) + return 48 + UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES + UVM_METHOD_SIZE; + } + + return 0; +} + +static NvU32 get_push_end_max_size(uvm_channel_t *channel) +{ + if (uvm_channel_is_ce(channel)) { + if (uvm_channel_is_wlc(channel)) { + // WLC pushes are always padded to UVM_MAX_WLC_PUSH_SIZE + return UVM_MAX_WLC_PUSH_SIZE; + } + // Space (in bytes) used by uvm_push_end() on a CE channel. + return get_push_end_min_size(channel); + } + else if (uvm_channel_is_sec2(channel)) { + // Space (in bytes) used by uvm_push_end() on a SEC2 channel. + // Note that SEC2 semaphore release uses an inline buffer with alignment + // requirements. This is the "worst" case semaphore_release storage. + return 48 + UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES + UVM_CONF_COMPUTING_AUTH_TAG_ALIGNMENT; + } return 0; } @@ -56,27 +124,41 @@ static NV_STATUS test_push_end_size(uvm_va_space_t *va_space) for (type = 0; type < UVM_CHANNEL_TYPE_COUNT; ++type) { uvm_push_t push; NvU32 push_size_before; - NvU32 push_end_size_observed, push_end_size_expected; + NvU32 push_end_size_observed; + NvU32 push_end_size_expected[2]; + // SEC2 is only available when Confidential Computing is enabled + if ((type == UVM_CHANNEL_TYPE_SEC2) && !uvm_conf_computing_mode_enabled(gpu)) + continue; + + // WLC is only available when Confidential Computing is enabled + if ((type == UVM_CHANNEL_TYPE_WLC) && !uvm_conf_computing_mode_enabled(gpu)) + continue; + + // LCIC doesn't accept pushes + if (type == UVM_CHANNEL_TYPE_LCIC) + continue; TEST_NV_CHECK_RET(uvm_push_begin(gpu->channel_manager, type, &push, - "type %s\n", + "type %s", uvm_channel_type_to_string(type))); push_size_before = uvm_push_get_size(&push); uvm_push_end(&push); - - push_end_size_expected = get_push_end_size(push.channel); push_end_size_observed = uvm_push_get_size(&push) - push_size_before; - if (push_end_size_observed != push_end_size_expected) { - UVM_TEST_PRINT("push_end_size incorrect, %u instead of %u on channel type %s for GPU %s\n", + push_end_size_expected[0] = get_push_end_min_size(push.channel); + push_end_size_expected[1] = get_push_end_max_size(push.channel); + + if (push_end_size_observed < push_end_size_expected[0] || + push_end_size_observed > push_end_size_expected[1]) { + UVM_TEST_PRINT("push_end_size incorrect, %u instead of [%u:%u] on channel type %s for GPU %s\n", push_end_size_observed, - push_end_size_expected, + push_end_size_expected[0], + push_end_size_expected[1], uvm_channel_type_to_string(type), uvm_gpu_name(gpu)); - // The size mismatch error gets precedence over a wait error (void) uvm_push_wait(&push); @@ -107,6 +189,11 @@ static NV_STATUS test_push_inline_data_gpu(uvm_gpu_t *gpu) uvm_mem_t *mem = NULL; char *verif; + // TODO: Bug 3839176: test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_mem_alloc_sysmem_and_map_cpu_kernel(UVM_PUSH_INLINE_DATA_MAX_SIZE, current->mm, &mem); TEST_CHECK_GOTO(status == NV_OK, done); @@ -152,7 +239,10 @@ static NV_STATUS test_push_inline_data_gpu(uvm_gpu_t *gpu) inline_buf[j] = 1 + i + j; break; case TEST_INLINE_SINGLE_BUFFER: - inline_buf = (char*)uvm_push_get_single_inline_buffer(&push, test_size, &data_gpu_address); + inline_buf = (char*)uvm_push_get_single_inline_buffer(&push, + test_size, + UVM_METHOD_SIZE, + &data_gpu_address); inline_data_size = test_size; for (j = 0; j < test_size; ++j) inline_buf[j] = 1 + i + j; @@ -221,6 +311,12 @@ static NV_STATUS test_concurrent_pushes(uvm_va_space_t *va_space) for_each_va_space_gpu(gpu, va_space) { + // A secure channels reserved at the start of a push cannot be reserved + // again until that push ends. The test would block indefinitely + // if secure pools are not skipped, because the number of pushes started + // per pool exceeds the number of channels in the pool. + if (uvm_channel_type_requires_secure_pool(gpu, channel_type)) + goto done; for (i = 0; i < UVM_PUSH_MAX_CONCURRENT_PUSHES; ++i) { uvm_push_t *push = &pushes[i]; status = uvm_push_begin(gpu->channel_manager, channel_type, push, "concurrent push %u", i); @@ -278,6 +374,11 @@ static NV_STATUS test_push_interleaving_on_gpu(uvm_gpu_t* gpu) uvm_rm_mem_t *mem = NULL; atomic_t on_complete_counter = ATOMIC_INIT(0); + // TODO: Bug 3839176: test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + // This test issues virtual memcopies/memsets, which in SR-IOV heavy cannot // be pushed to a proxy channel. Pushing to a UVM internal CE channel works // in all scenarios. @@ -294,7 +395,7 @@ static NV_STATUS test_push_interleaving_on_gpu(uvm_gpu_t* gpu) num_non_paused_pushes = channel->num_gpfifo_entries; // The UVM driver only allows push interleaving across separate threads, but - // it is hard to consistenly replicate the interleaving. Instead, we + // it is hard to consistently replicate the interleaving. Instead, we // temporarily disable lock tracking, so we can interleave pushes from a // single thread. uvm_thread_context_lock_disable_tracking(); @@ -302,7 +403,7 @@ static NV_STATUS test_push_interleaving_on_gpu(uvm_gpu_t* gpu) status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &mem); TEST_CHECK_GOTO(status == NV_OK, done); host_va = (NvU32*)uvm_rm_mem_get_cpu_va(mem); - gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(channel)); + gpu_va = uvm_rm_mem_get_gpu_va(mem, gpu, uvm_channel_is_proxy(channel)).address; memset(host_va, 0, size); // Begin a few pushes on the channel, but do not end them yet. @@ -434,14 +535,14 @@ static NV_STATUS test_push_exactly_max_push(uvm_gpu_t *gpu, if (status != NV_OK) return status; - TEST_CHECK_RET(uvm_push_has_space(push, UVM_MAX_PUSH_SIZE)); - TEST_CHECK_RET(!uvm_push_has_space(push, UVM_MAX_PUSH_SIZE + 1)); + TEST_CHECK_RET(uvm_push_has_space(push, UVM_MAX_PUSH_SIZE - get_push_begin_size(push->channel))); + TEST_CHECK_RET(!uvm_push_has_space(push, UVM_MAX_PUSH_SIZE - get_push_begin_size(push->channel) + 1)); semaphore_gpu_va = uvm_gpu_semaphore_get_gpu_va(sema_to_acquire, gpu, uvm_channel_is_proxy(push->channel)); gpu->parent->host_hal->semaphore_acquire(push, semaphore_gpu_va, value); // Push a noop leaving just push_end_size in the pushbuffer. - push_end_size = get_push_end_size(push->channel); + push_end_size = get_push_end_max_size(push->channel); gpu->parent->host_hal->noop(push, UVM_MAX_PUSH_SIZE - uvm_push_get_size(push) - push_end_size); TEST_CHECK_RET(uvm_push_has_space(push, push_end_size)); @@ -476,7 +577,7 @@ static NvU32 test_count_available_chunks(uvm_pushbuffer_t *pushbuffer) // Test doing pushes of exactly UVM_MAX_PUSH_SIZE size and only allowing them to // complete one by one. -static NV_STATUS test_max_pushes_on_gpu_and_channel_type(uvm_gpu_t *gpu, uvm_channel_type_t channel_type) +static NV_STATUS test_max_pushes_on_gpu(uvm_gpu_t *gpu) { NV_STATUS status; @@ -485,6 +586,7 @@ static NV_STATUS test_max_pushes_on_gpu_and_channel_type(uvm_gpu_t *gpu, uvm_cha NvU32 total_push_size = 0; NvU32 push_count = 0; NvU32 i; + uvm_channel_type_t channel_type = UVM_CHANNEL_TYPE_GPU_INTERNAL; uvm_tracker_init(&tracker); @@ -492,6 +594,13 @@ static NV_STATUS test_max_pushes_on_gpu_and_channel_type(uvm_gpu_t *gpu, uvm_cha TEST_CHECK_GOTO(status == NV_OK, done); uvm_gpu_semaphore_set_payload(&sema, 0); + if (uvm_conf_computing_mode_enabled(gpu)) { + // Use SEC2 channel when Confidential Compute is enabled + // since all other channel types need extra space for + // work launch, and the channel type really doesn't + // matter for this test. + channel_type = UVM_CHANNEL_TYPE_SEC2; + } // Need to wait for all channels to completely idle so that the pushbuffer // is in completely idle state when we begin. @@ -553,14 +662,6 @@ static NV_STATUS test_max_pushes_on_gpu_and_channel_type(uvm_gpu_t *gpu, uvm_cha return status; } -static NV_STATUS test_max_pushes_on_gpu(uvm_gpu_t *gpu) -{ - - TEST_NV_CHECK_RET(test_max_pushes_on_gpu_and_channel_type(gpu, UVM_CHANNEL_TYPE_GPU_INTERNAL)); - - return NV_OK; -} - // Test doing UVM_PUSHBUFFER_CHUNKS independent pushes expecting each one to use // a different chunk in the pushbuffer. static NV_STATUS test_idle_chunks_on_gpu(uvm_gpu_t *gpu) @@ -570,6 +671,15 @@ static NV_STATUS test_idle_chunks_on_gpu(uvm_gpu_t *gpu) uvm_gpu_semaphore_t sema; uvm_tracker_t tracker = UVM_TRACKER_INIT(); NvU32 i; + uvm_channel_type_t channel_type = UVM_CHANNEL_TYPE_GPU_INTERNAL; + + if (uvm_conf_computing_mode_enabled(gpu)) { + // Use SEC2 channel when Confidential Compute is enabled + // since all other channel types need extra space for + // work launch, and the channel type really doesn't + // matter for this test. + channel_type = UVM_CHANNEL_TYPE_SEC2; + } uvm_tracker_init(&tracker); @@ -587,7 +697,7 @@ static NV_STATUS test_idle_chunks_on_gpu(uvm_gpu_t *gpu) NvU64 semaphore_gpu_va; uvm_push_t push; - status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_INTERNAL, &push, "Push using chunk %u", i); + status = uvm_push_begin(gpu->channel_manager, channel_type, &push, "Push using chunk %u", i); TEST_CHECK_GOTO(status == NV_OK, done); semaphore_gpu_va = uvm_gpu_semaphore_get_gpu_va(&sema, gpu, uvm_channel_is_proxy(push.channel)); @@ -666,6 +776,15 @@ static NV_STATUS test_timestamp_on_gpu(uvm_gpu_t *gpu) NvU32 i; NvU64 last_stamp = 0; + // TODO: Bug 3988992: [UVM][HCC] RFE - Support encrypted semaphore for secure CE channels + // This test is waived when Confidential Computing is enabled because it + // assumes that CPU can directly read the result of a semaphore timestamp + // operation. Instead the operation needs to be follower up by an encrypt + // -decrypt trip to be accessible to CPU. This will be cleaner and simpler + // once encrypted semaphores are available. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + for (i = 0; i < 10; ++i) { status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_INTERNAL, &push, "Releasing a timestamp"); if (status != NV_OK) @@ -769,6 +888,10 @@ static NV_STATUS test_push_gpu_to_gpu(uvm_va_space_t *va_space) for_each_va_space_gpu(gpu_a, va_space) { + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (uvm_conf_computing_mode_enabled(gpu_a)) + return NV_OK; for_each_va_space_gpu(gpu_b, va_space) { if (can_do_peer_copies(va_space, gpu_a, gpu_b)) { waive = false; diff --git a/kernel-open/nvidia-uvm/uvm_pushbuffer.c b/kernel-open/nvidia-uvm/uvm_pushbuffer.c index 94685cfe0c..3500dad64d 100644 --- a/kernel-open/nvidia-uvm/uvm_pushbuffer.c +++ b/kernel-open/nvidia-uvm/uvm_pushbuffer.c @@ -32,6 +32,7 @@ #include "uvm_gpu.h" #include "uvm_common.h" #include "uvm_linux.h" +#include "uvm_conf_computing.h" // Print pushbuffer state into a seq_file if provided or with UVM_DBG_PRINT() if not. static void uvm_pushbuffer_print_common(uvm_pushbuffer_t *pushbuffer, struct seq_file *s); @@ -120,6 +121,36 @@ NV_STATUS uvm_pushbuffer_create(uvm_channel_manager_t *channel_manager, uvm_push if (status != NV_OK) goto error; + if (uvm_conf_computing_mode_enabled(gpu)) { + UVM_ASSERT(channel_manager->conf.pushbuffer_loc == UVM_BUFFER_LOCATION_SYS); + + // Move the above allocation to unprotected_sysmem + pushbuffer->memory_unprotected_sysmem = pushbuffer->memory; + pushbuffer->memory = NULL; + + // Make sure the base can be least 4KB aligned. Pushes can include inline buffers + // with specific alignment requirement. Different base between backing memory + // locations would change that. + pushbuffer->memory_protected_sysmem = uvm_kvmalloc_zero(UVM_PUSHBUFFER_SIZE + UVM_PAGE_SIZE_4K); + if (!pushbuffer->memory_protected_sysmem) { + status = NV_ERR_NO_MEMORY; + goto error; + } + + + status = uvm_rm_mem_alloc(gpu, + UVM_RM_MEM_TYPE_GPU, + UVM_PUSHBUFFER_SIZE, + pushbuffer_alignment, + &pushbuffer->memory); + if (status != NV_OK) + goto error; + + status = uvm_rm_mem_map_gpu(pushbuffer->memory_unprotected_sysmem, gpu, pushbuffer_alignment); + if (status != NV_OK) + goto error; + } + // Verify the GPU can access the pushbuffer. UVM_ASSERT((uvm_pushbuffer_get_gpu_va_base(pushbuffer) + UVM_PUSHBUFFER_SIZE - 1) < gpu->parent->max_host_va); @@ -227,9 +258,24 @@ static bool try_claim_chunk(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push, uvm_ return chunk != NULL; } +static char *get_base_cpu_va(uvm_pushbuffer_t *pushbuffer) +{ + // Confidential Computing pushes are assembled in protected sysmem + // and safely (through encrypt/decrypt) moved to protected vidmem. + // Or signed and moved to unprotected sysmem. + if (uvm_conf_computing_mode_enabled(pushbuffer->channel_manager->gpu)) { + // Align protected sysmem base to 4kB. This should be enough to give + // the same alignment behaviour for inline buffers as the other two + // backing memory locations. + return (char*)(UVM_ALIGN_UP((uintptr_t)pushbuffer->memory_protected_sysmem, UVM_PAGE_SIZE_4K)); + } + + return (char *)uvm_rm_mem_get_cpu_va(pushbuffer->memory); +} + static NvU32 *chunk_get_next_push_start_addr(uvm_pushbuffer_t *pushbuffer, uvm_pushbuffer_chunk_t *chunk) { - char *push_start = (char *)uvm_rm_mem_get_cpu_va(pushbuffer->memory); + char *push_start = get_base_cpu_va(pushbuffer); push_start += chunk_get_offset(pushbuffer, chunk); push_start += chunk->next_push_start; @@ -266,6 +312,16 @@ NV_STATUS uvm_pushbuffer_begin_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *pu UVM_ASSERT(pushbuffer); UVM_ASSERT(push); + UVM_ASSERT(push->channel); + + if (uvm_channel_is_wlc(push->channel)) { + // WLC pushes use static PB and don't count against max concurrent + // pushes. + push->begin = (void*)UVM_ALIGN_UP((uintptr_t)push->channel->conf_computing.static_pb_protected_sysmem, + UVM_PAGE_SIZE_4K); + push->next = push->begin; + return NV_OK; + } // Note that this semaphore is uvm_up()ed in end_push(). uvm_down(&pushbuffer->concurrent_pushes_sema); @@ -374,6 +430,8 @@ void uvm_pushbuffer_destroy(uvm_pushbuffer_t *pushbuffer) proc_remove(pushbuffer->procfs.info_file); + uvm_rm_mem_free(pushbuffer->memory_unprotected_sysmem); + uvm_kvfree(pushbuffer->memory_protected_sysmem); uvm_rm_mem_free(pushbuffer->memory); uvm_kvfree(pushbuffer); } @@ -426,7 +484,17 @@ void uvm_pushbuffer_mark_completed(uvm_pushbuffer_t *pushbuffer, uvm_gpfifo_entr NvU32 uvm_pushbuffer_get_offset_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push) { - NvU32 offset = (char*)push->begin - (char *)uvm_rm_mem_get_cpu_va(pushbuffer->memory); + NvU32 offset; + + if (uvm_channel_is_wlc(push->channel)) { + // WLC channels use private static PB and their gpfifo entries are not + // added to any chunk's list. This only needs to return legal offset. + // Completion cleanup will not find WLC gpfifo entries as either first + // or last entry of any chunk. + return 0; + } + + offset = (char*)push->begin - get_base_cpu_va(pushbuffer); UVM_ASSERT(((NvU64)offset) % sizeof(NvU32) == 0); @@ -439,14 +507,65 @@ NvU64 uvm_pushbuffer_get_gpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_ uvm_gpu_t *gpu = uvm_push_get_gpu(push); bool is_proxy_channel = uvm_channel_is_proxy(push->channel); - pushbuffer_base = uvm_rm_mem_get_gpu_va(pushbuffer->memory, gpu, is_proxy_channel); + pushbuffer_base = uvm_rm_mem_get_gpu_va(pushbuffer->memory, gpu, is_proxy_channel).address; + + if (uvm_channel_is_wlc(push->channel) || uvm_channel_is_lcic(push->channel)) { + // We need to use the same static locations for PB as the fixed + // schedule because that's what the channels are initialized to use. + return uvm_rm_mem_get_gpu_uvm_va(push->channel->conf_computing.static_pb_protected_vidmem, gpu); + } + else if (uvm_channel_is_sec2(push->channel)) { + // SEC2 PBs are in unprotected sysmem + pushbuffer_base = uvm_pushbuffer_get_sec2_gpu_va_base(pushbuffer); + } + + return pushbuffer_base + uvm_pushbuffer_get_offset_for_push(pushbuffer, push); +} + +void *uvm_pushbuffer_get_unprotected_cpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push) +{ + char *pushbuffer_base; + + if (uvm_channel_is_wlc(push->channel)) { + // Reuse existing WLC static pb for initialization + UVM_ASSERT(!uvm_channel_manager_is_wlc_ready(push->channel->pool->manager)); + return push->channel->conf_computing.static_pb_unprotected_sysmem_cpu; + } + + pushbuffer_base = uvm_rm_mem_get_cpu_va(pushbuffer->memory_unprotected_sysmem); + + return pushbuffer_base + uvm_pushbuffer_get_offset_for_push(pushbuffer, push); +} + +NvU64 uvm_pushbuffer_get_unprotected_gpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push) +{ + NvU64 pushbuffer_base; + + if (uvm_channel_is_wlc(push->channel)) { + // Reuse existing WLC static pb for initialization + UVM_ASSERT(!uvm_channel_manager_is_wlc_ready(push->channel->pool->manager)); + return uvm_rm_mem_get_gpu_uvm_va(push->channel->conf_computing.static_pb_unprotected_sysmem, + uvm_push_get_gpu(push)); + } + + pushbuffer_base = uvm_rm_mem_get_gpu_uvm_va(pushbuffer->memory_unprotected_sysmem, uvm_push_get_gpu(push)); return pushbuffer_base + uvm_pushbuffer_get_offset_for_push(pushbuffer, push); } void uvm_pushbuffer_end_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push, uvm_gpfifo_entry_t *gpfifo) { - uvm_pushbuffer_chunk_t *chunk = gpfifo_to_chunk(pushbuffer, gpfifo); + uvm_pushbuffer_chunk_t *chunk; + + if (uvm_channel_is_wlc(push->channel)) { + // WLC channels use static pushbuffer and don't count towards max + // concurrent pushes. Initializing the list as head makes sure the + // deletion in "uvm_pushbuffer_mark_completed" doesn't crash. + INIT_LIST_HEAD(&gpfifo->pending_list_node); + return; + } + + chunk = gpfifo_to_chunk(pushbuffer, gpfifo); uvm_channel_pool_assert_locked(push->channel->pool); @@ -513,3 +632,10 @@ NvU64 uvm_pushbuffer_get_gpu_va_base(uvm_pushbuffer_t *pushbuffer) { return uvm_rm_mem_get_gpu_uvm_va(pushbuffer->memory, pushbuffer->channel_manager->gpu); } + +NvU64 uvm_pushbuffer_get_sec2_gpu_va_base(uvm_pushbuffer_t *pushbuffer) +{ + UVM_ASSERT(uvm_conf_computing_mode_enabled(pushbuffer->channel_manager->gpu)); + + return uvm_rm_mem_get_gpu_uvm_va(pushbuffer->memory_unprotected_sysmem, pushbuffer->channel_manager->gpu); +} diff --git a/kernel-open/nvidia-uvm/uvm_pushbuffer.h b/kernel-open/nvidia-uvm/uvm_pushbuffer.h index 9b43fb672d..3a4ce1dbfa 100644 --- a/kernel-open/nvidia-uvm/uvm_pushbuffer.h +++ b/kernel-open/nvidia-uvm/uvm_pushbuffer.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -155,6 +155,42 @@ // uvm_push_end(). #define UVM_PUSH_MAX_CONCURRENT_PUSHES UVM_PUSHBUFFER_CHUNKS +// Push space needed for static part for the WLC schedule, as initialized in +// 'setup_wlc_schedule': +// * CE decrypt (of WLC PB): 56B +// * WFI: 8B +// Total: 64B +// +// Push space needed for secure work launch is 224B. The push is constructed +// in 'internal_channel_submit_work_indirect' and 'uvm_channel_end_push' +// * CE decrypt (of indirect PB): 56B +// * 2*semaphore release (indirect GPFIFO entry): 2*24B +// * semaphore release (indirect GPPUT): 24B +// * semaphore release (indirect doorbell): 24B +// Appendix added in 'uvm_channel_end_push': +// * semaphore release (WLC tracking): 168B +// * semaphore increment (memcopy): 24B +// * notifier memset: 40B +// * payload encryption: 64B +// * notifier memset: 40B +// * semaphore increment (LCIC GPPUT): 24B +// * semaphore release (LCIC doorbell): 24B +// Total: 368B +#define UVM_MAX_WLC_PUSH_SIZE (368) + +// Push space needed for static LCIC schedule, as initialized in +// 'setup_lcic_schedule': +// * WFI: 8B +// * semaphore increment (WLC GPPUT): 24B +// * semaphore increment (WLC GPPUT): 24B +// * semaphore increment (LCIC tracking): 160B +// * semaphore increment (memcopy): 24B +// * notifier memcopy: 36B +// * payload encryption: 64B +// * notifier memcopy: 36B +// Total: 216B +#define UVM_LCIC_PUSH_SIZE (216) + typedef struct { // Offset within the chunk of where a next push should begin if there is @@ -176,6 +212,12 @@ struct uvm_pushbuffer_struct // Memory allocation backing the pushbuffer uvm_rm_mem_t *memory; + // Mirror image of memory in dma sysmem + uvm_rm_mem_t *memory_unprotected_sysmem; + + // Secure sysmem backing memory + void *memory_protected_sysmem; + // Array of the pushbuffer chunks uvm_pushbuffer_chunk_t chunks[UVM_PUSHBUFFER_CHUNKS]; @@ -221,6 +263,12 @@ void uvm_pushbuffer_mark_completed(uvm_pushbuffer_t *pushbuffer, uvm_gpfifo_entr // Get the GPU VA for an ongoing push NvU64 uvm_pushbuffer_get_gpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push); +// Get the CPU VA for encrypted sysmem mirror +void *uvm_pushbuffer_get_unprotected_cpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push); + +// Get the GPU VA for encrypted sysmem mirror +NvU64 uvm_pushbuffer_get_unprotected_gpu_va_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push); + // Get the offset of the beginning of the push from the base of the pushbuffer allocation NvU32 uvm_pushbuffer_get_offset_for_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push); @@ -239,4 +287,8 @@ void uvm_pushbuffer_print(uvm_pushbuffer_t *pushbuffer); // Helper to retrieve the pushbuffer->memory GPU VA. NvU64 uvm_pushbuffer_get_gpu_va_base(uvm_pushbuffer_t *pushbuffer); +// SEC2 variant to retrieve GPU VA for push location. +// Unlike other channels, SEC2 uses signed pushes in unprotected sysmem. +NvU64 uvm_pushbuffer_get_sec2_gpu_va_base(uvm_pushbuffer_t *pushbuffer); + #endif // __UVM_PUSHBUFFER_H__ diff --git a/kernel-open/nvidia-uvm/uvm_range_allocator_test.c b/kernel-open/nvidia-uvm/uvm_range_allocator_test.c index fe1366e583..d808d8c88c 100644 --- a/kernel-open/nvidia-uvm/uvm_range_allocator_test.c +++ b/kernel-open/nvidia-uvm/uvm_range_allocator_test.c @@ -78,7 +78,7 @@ static NvU64 test_free_range(uvm_range_allocator_t *range_allocator, uvm_range_a return size; } -#define BASIC_TEST_SIZE (1024ull * 1024 * 1024) +#define BASIC_TEST_SIZE UVM_SIZE_1GB #define BASIC_TEST_MAX_ALLOCS (128) // Check that a specific range is free in the allocator diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem.c b/kernel-open/nvidia-uvm/uvm_rm_mem.c index 255c70bcb8..a88dcff484 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem.c @@ -102,12 +102,21 @@ NvU64 uvm_rm_mem_get_gpu_proxy_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) return rm_mem->proxy_vas[uvm_global_id_value(gpu->global_id)]; } -NvU64 uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bool is_proxy_va_space) +uvm_gpu_address_t uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bool is_proxy_va_space) { + uvm_gpu_address_t gpu_va = {0}; + + gpu_va.aperture = UVM_APERTURE_MAX; + gpu_va.is_virtual = true; + if (uvm_conf_computing_mode_enabled(gpu) && (rm_mem->type == UVM_RM_MEM_TYPE_SYS)) + gpu_va.is_unprotected = true; + if (is_proxy_va_space) - return uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu); + gpu_va.address = uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu); else - return uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); + gpu_va.address = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); + + return gpu_va; } void *uvm_rm_mem_get_cpu_va(uvm_rm_mem_t *rm_mem) @@ -199,6 +208,9 @@ NV_STATUS uvm_rm_mem_alloc(uvm_gpu_t *gpu, if (rm_mem == NULL) return NV_ERR_NO_MEMORY; + if (!uvm_conf_computing_mode_enabled(gpu) || type == UVM_RM_MEM_TYPE_SYS) + alloc_info.bUnprotected = NV_TRUE; + alloc_info.alignment = gpu_alignment; if (type == UVM_RM_MEM_TYPE_SYS) @@ -245,6 +257,8 @@ NV_STATUS uvm_rm_mem_map_cpu(uvm_rm_mem_t *rm_mem) gpu = rm_mem->gpu_owner; gpu_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); + if (uvm_conf_computing_mode_enabled(gpu)) + UVM_ASSERT(rm_mem->type == UVM_RM_MEM_TYPE_SYS); status = uvm_rm_locked_call(nvUvmInterfaceMemoryCpuMap(gpu->rm_address_space, gpu_va, diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem.h b/kernel-open/nvidia-uvm/uvm_rm_mem.h index ec087cc2ff..736c0c59d2 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_rm_mem.h @@ -27,6 +27,7 @@ #include "uvm_forward_decl.h" #include "uvm_processors.h" #include "uvm_test_ioctl.h" +#include "uvm_hal_types.h" typedef enum { @@ -143,9 +144,7 @@ NvU64 uvm_rm_mem_get_gpu_proxy_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu); // Get the GPU VA of the given memory in UVM's internal address space (if the // flag is false), or proxy address space (if flag is true). -NvU64 uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, - uvm_gpu_t *gpu, - bool is_proxy_va_space); +uvm_gpu_address_t uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bool is_proxy_va_space); // Query if the memory is mapped on the CPU, GPU (UVM internal/kernel address // space), or GPU (proxy address space) diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c index ba1e56c2d6..306cecf6b8 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c @@ -195,12 +195,16 @@ static NV_STATUS test_all_gpus_in_va(uvm_va_space_t *va_space) for (i = 0; i < ARRAY_SIZE(sizes); ++i) { for (j = 0; j < ARRAY_SIZE(mem_types); ++j) { for (k = 0; k < ARRAY_SIZE(alignments); ++k) { + bool test_cpu_mappings = true; // Create an allocation in the GPU's address space TEST_NV_CHECK_RET(uvm_rm_mem_alloc(gpu, mem_types[j], sizes[i], alignments[k], &rm_mem)); + test_cpu_mappings = mem_types[j] == UVM_RM_MEM_TYPE_SYS || + !uvm_conf_computing_mode_enabled(gpu); // Test CPU mappings - TEST_NV_CHECK_GOTO(map_cpu(rm_mem), error); + if (test_cpu_mappings) + TEST_NV_CHECK_GOTO(map_cpu(rm_mem), error); // Test mappings in the GPU owning the allocation TEST_NV_CHECK_GOTO(map_gpu_owner(rm_mem, alignments[k]), error); diff --git a/kernel-open/nvidia-uvm/uvm_sec2_test.c b/kernel-open/nvidia-uvm/uvm_sec2_test.c new file mode 100644 index 0000000000..c0df72cd65 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_sec2_test.c @@ -0,0 +1,614 @@ +/******************************************************************************* + Copyright (c) 2021-2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "nv_uvm_interface.h" + +typedef struct test_sem_mem_t { + void *cpu_va; + NvU64 gpu_va; + + union { + uvm_mem_t *uvm_mem; + uvm_rm_mem_t *rm_mem; + }; +} test_sem_mem; + +static NV_STATUS test_semaphore_alloc_uvm_rm_mem(uvm_gpu_t *gpu, const size_t size, test_sem_mem *mem_out) +{ + NV_STATUS status; + uvm_rm_mem_t *mem = NULL; + NvU64 gpu_va; + + status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &mem); + TEST_NV_CHECK_RET(status); + + gpu_va = uvm_rm_mem_get_gpu_uvm_va(mem, gpu); + TEST_CHECK_GOTO(gpu_va < gpu->parent->max_host_va, error); + + mem_out->cpu_va = uvm_rm_mem_get_cpu_va(mem); + mem_out->gpu_va = gpu_va; + mem_out->rm_mem = mem; + + return NV_OK; + +error: + uvm_rm_mem_free(mem); + return status; +} + +static NV_STATUS test_semaphore_alloc_sem(uvm_gpu_t *gpu, const size_t size, test_sem_mem *mem_out) +{ + NV_STATUS status = NV_OK; + uvm_mem_t *mem = NULL; + NvU64 gpu_va; + + TEST_NV_CHECK_RET(uvm_mem_alloc_sysmem_dma(size, gpu, current->mm, &mem)); + + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(mem, gpu), error); + gpu_va = uvm_mem_get_gpu_va_kernel(mem, gpu); + + // Use an RM allocation when SEC2 cannot address the semaphore. + // SEC2 VA width is similar to Host's. + if (gpu_va >= gpu->parent->max_host_va) { + uvm_mem_free(mem); + return test_semaphore_alloc_uvm_rm_mem(gpu, size, mem_out); + } + + // This semaphore resides in the uvm_mem region, i.e., it has the GPU VA + // MSbit set. The intent is to validate semaphore operations when the + // semaphore's VA is in the high-end of the GPU effective virtual address + // space spectrum, i.e., its VA upper-bit is set. + TEST_CHECK_GOTO(gpu_va & (1ULL << (gpu->address_space_tree.hal->num_va_bits() - 1)), error); + + TEST_NV_CHECK_GOTO(uvm_mem_map_cpu_kernel(mem), error); + + mem_out->cpu_va = uvm_mem_get_cpu_addr_kernel(mem); + mem_out->gpu_va = gpu_va; + mem_out->uvm_mem = mem; + + return NV_OK; + +error: + uvm_mem_free(mem); + return status; +} + +static void test_semaphore_free_sem(uvm_gpu_t *gpu, test_sem_mem *mem) +{ + if (mem->gpu_va >= gpu->parent->uvm_mem_va_base) + uvm_mem_free(mem->uvm_mem); + else + uvm_rm_mem_free(mem->rm_mem); +} + +// This test is similar to the test_semaphore_release() test in +// uvm_host_test.c, except that this one uses sec2_hal->semaphore_release(); +static NV_STATUS test_semaphore_release(uvm_gpu_t *gpu) +{ + NV_STATUS status; + test_sem_mem mem = { 0 }; + uvm_push_t push; + NvU32 value; + NvU32 payload = 0xA5A55A5A; + NvU32 *cpu_ptr; + + // Semaphore release needs 1 word (4 bytes). + const size_t size = sizeof(NvU32); + + status = test_semaphore_alloc_sem(gpu, size, &mem); + TEST_NV_CHECK_RET(status); + + // Initialize the payload. + cpu_ptr = (NvU32 *)mem.cpu_va; + *cpu_ptr = 0; + + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_SEC2, &push, "semaphore_release test"); + TEST_NV_CHECK_GOTO(status, done); + + gpu->parent->sec2_hal->semaphore_release(&push, mem.gpu_va, payload); + + status = uvm_push_end_and_wait(&push); + TEST_NV_CHECK_GOTO(status, done); + + value = *cpu_ptr; + if (value != payload) { + UVM_TEST_PRINT("Semaphore payload = %u instead of %u, GPU %s\n", value, payload, uvm_gpu_name(gpu)); + status = NV_ERR_INVALID_STATE; + goto done; + } + +done: + test_semaphore_free_sem(gpu, &mem); + + return status; +} + +// This test is similiar to the test_semaphore_timestamp() test in +// uvm_ce_test.c, except that this one uses sec2_hal->semaphore_timestamp(); +static NV_STATUS test_semaphore_timestamp(uvm_gpu_t *gpu) +{ + NV_STATUS status; + test_sem_mem mem = { 0 }; + uvm_push_t push; + NvU32 i; + NvU64 *timestamp; + NvU64 last_timestamp = 0; + + // 2 iterations: + // 1: compare retrieved timestamp with 0; + // 2: compare retrieved timestamp with previous timestamp (obtained in 1). + const NvU32 iterations = 2; + + // The semaphore is 4 words long (16 bytes). + const size_t size = 16; + + // TODO: Bug 3804752: SEC2 semaphore timestamp is not implemented for + // Hopper + if (uvm_conf_computing_mode_is_hcc(gpu)) + return NV_OK; + + status = test_semaphore_alloc_sem(gpu, size, &mem); + TEST_NV_CHECK_RET(status); + + timestamp = (NvU64 *)mem.cpu_va; + TEST_CHECK_GOTO(timestamp != NULL, done); + memset(timestamp, 0, size); + + // Shift the timestamp pointer to where the semaphore timestamp info is. + timestamp += 1; + + for (i = 0; i < iterations; i++) { + status = uvm_push_begin(gpu->channel_manager, + UVM_CHANNEL_TYPE_SEC2, + &push, + "semaphore_timestamp test, iter: %u", + i); + TEST_NV_CHECK_GOTO(status, done); + + gpu->parent->sec2_hal->semaphore_timestamp(&push, mem.gpu_va); + + status = uvm_push_end_and_wait(&push); + TEST_NV_CHECK_GOTO(status, done); + + TEST_CHECK_GOTO(*timestamp != 0, done); + TEST_CHECK_GOTO(*timestamp >= last_timestamp, done); + last_timestamp = *timestamp; + } + +done: + test_semaphore_free_sem(gpu, &mem); + + return status; +} + +typedef enum +{ + MEM_ALLOC_TYPE_SYSMEM_DMA, + MEM_ALLOC_TYPE_VIDMEM_PROTECTED +} mem_alloc_type_t; + +static bool mem_match(uvm_mem_t *mem1, uvm_mem_t *mem2) +{ + void *mem1_addr; + void *mem2_addr; + + UVM_ASSERT(uvm_mem_is_sysmem(mem1)); + UVM_ASSERT(uvm_mem_is_sysmem(mem2)); + UVM_ASSERT(mem1->size == mem2->size); + + mem1_addr = uvm_mem_get_cpu_addr_kernel(mem1); + mem2_addr = uvm_mem_get_cpu_addr_kernel(mem2); + + return !memcmp(mem1_addr, mem2_addr, mem1->size); +} + +static NV_STATUS ce_memset_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem, size_t size, NvU32 val) +{ + uvm_push_t push; + + TEST_NV_CHECK_RET(uvm_push_begin(gpu->channel_manager, + UVM_CHANNEL_TYPE_GPU_INTERNAL, + &push, + "VPR memset")); + + gpu->parent->ce_hal->memset_4(&push, uvm_mem_gpu_address_virtual_kernel(mem, gpu), val, size); + + TEST_NV_CHECK_RET(uvm_push_end_and_wait(&push)); + + return NV_OK; +} + +static void write_range_cpu(uvm_mem_t *mem, size_t size, NvU64 base_val) +{ + char *start, *end; + + UVM_ASSERT(uvm_mem_is_sysmem(mem)); + + start = uvm_mem_get_cpu_addr_kernel(mem); + end = start + size; + + for (; start < end; start += sizeof(NvU64)) + *(NvU64 *) start = base_val++; +} + +static NV_STATUS alloc_and_init_mem(uvm_gpu_t *gpu, uvm_mem_t **mem, size_t size, mem_alloc_type_t type) +{ + NV_STATUS status = NV_OK; + + UVM_ASSERT(mem); + + *mem = NULL; + + if (type == MEM_ALLOC_TYPE_VIDMEM_PROTECTED) { + TEST_NV_CHECK_RET(uvm_mem_alloc_vidmem_protected(size, gpu, mem)); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(*mem, gpu), err); + TEST_NV_CHECK_GOTO(ce_memset_gpu(gpu, *mem, size, 0xdead), err); + } + else { + TEST_NV_CHECK_RET(uvm_mem_alloc_sysmem_dma(size, gpu, NULL, mem)); + TEST_NV_CHECK_GOTO(uvm_mem_map_cpu_kernel(*mem), err); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(*mem, gpu), err); + write_range_cpu(*mem, size, 0xdeaddead); + } + + return NV_OK; + +err: + uvm_mem_free(*mem); + return status; +} + +static void cpu_encrypt(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + size_t copy_size) +{ + size_t i; + void *src_plain = uvm_mem_get_cpu_addr_kernel(src_mem); + void *dst_cipher = uvm_mem_get_cpu_addr_kernel(dst_mem); + void *auth_tag_buffer = uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + UVM_ASSERT(IS_ALIGNED(size, copy_size)); + + for (i = 0; i < size / copy_size; i++) { + uvm_conf_computing_cpu_encrypt(channel, dst_cipher, src_plain, NULL, copy_size, auth_tag_buffer); + + src_plain = (char *) src_plain + copy_size; + dst_cipher = (char *) dst_cipher + copy_size; + auth_tag_buffer = (char *) auth_tag_buffer + UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } +} + +static NV_STATUS cpu_decrypt(uvm_channel_t *channel, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + UvmCslIv *decrypt_iv, + uvm_mem_t *auth_tag_mem, + size_t size, + size_t copy_size) +{ + size_t i; + void *src_cipher = uvm_mem_get_cpu_addr_kernel(src_mem); + void *dst_plain = uvm_mem_get_cpu_addr_kernel(dst_mem); + void *auth_tag_buffer = uvm_mem_get_cpu_addr_kernel(auth_tag_mem); + + UVM_ASSERT(IS_ALIGNED(size, copy_size)); + + for (i = 0; i < size / copy_size; i++) { + TEST_NV_CHECK_RET(uvm_conf_computing_cpu_decrypt(channel, + dst_plain, + src_cipher, + &decrypt_iv[i], + copy_size, + auth_tag_buffer)); + + dst_plain = (char *) dst_plain + copy_size; + src_cipher = (char *) src_cipher + copy_size; + auth_tag_buffer = (char *) auth_tag_buffer + UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } + + return NV_OK; +} + +// gpu_encrypt uses a secure CE for encryption (instead of SEC2). SEC2 does not +// support encryption. The following function is copied from uvm_ce_test.c and +// adapted to SEC2 tests. +static void gpu_encrypt(uvm_push_t *push, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + UvmCslIv *decrypt_iv, + uvm_mem_t *auth_tag_mem, + size_t size, + size_t copy_size) +{ + size_t i; + size_t num_iterations = size / copy_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_gpu_address_t dst_cipher_address = uvm_mem_gpu_address_virtual_kernel(dst_mem, gpu); + uvm_gpu_address_t src_plain_address = uvm_mem_gpu_address_virtual_kernel(src_mem, gpu); + uvm_gpu_address_t auth_tag_address = uvm_mem_gpu_address_virtual_kernel(auth_tag_mem, gpu); + + for (i = 0; i < num_iterations; i++) { + uvm_conf_computing_log_gpu_encryption(push->channel, decrypt_iv); + + if (i > 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + + gpu->parent->ce_hal->encrypt(push, dst_cipher_address, src_plain_address, copy_size, auth_tag_address); + dst_cipher_address.address += copy_size; + src_plain_address.address += copy_size; + auth_tag_address.address += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + decrypt_iv++; + } +} + +static void gpu_decrypt(uvm_push_t *push, + uvm_mem_t *dst_mem, + uvm_mem_t *src_mem, + uvm_mem_t *auth_tag_mem, + size_t size, + size_t copy_size) +{ + size_t i; + size_t num_iterations = size / copy_size; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_gpu_address_t src_cipher_address = uvm_mem_gpu_address_virtual_kernel(src_mem, gpu); + uvm_gpu_address_t dst_plain_address = uvm_mem_gpu_address_virtual_kernel(dst_mem, gpu); + uvm_gpu_address_t auth_tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(auth_tag_mem, gpu); + + UVM_ASSERT(IS_ALIGNED(size, copy_size)); + + for (i = 0; i < num_iterations; i++) { + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + gpu->parent->sec2_hal->decrypt(push, + dst_plain_address.address, + src_cipher_address.address, + copy_size, + auth_tag_gpu_address.address); + + dst_plain_address.address += copy_size; + src_cipher_address.address += copy_size; + auth_tag_gpu_address.address += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } +} + +// This test only uses sysmem so that we can use the CPU for encryption and SEC2 +// for decryption, i.e., the test doesn't depend on any other GPU engine for +// the encryption operation (refer to test_cpu_to_gpu_roundtrip()). This is not +// how SEC2 is used in the driver. The intended SEC2 usage is to decrypt from +// unprotected sysmem to protected vidmem, which is tested in +// test_cpu_to_gpu_roundtrip(). +static NV_STATUS test_cpu_to_gpu_sysmem(uvm_gpu_t *gpu, size_t copy_size, size_t size) +{ + NV_STATUS status = NV_OK; + uvm_mem_t *src_plain = NULL; + uvm_mem_t *cipher = NULL; + uvm_mem_t *dst_plain = NULL; + uvm_mem_t *auth_tag_mem = NULL; + size_t auth_tag_buffer_size = (size / copy_size) * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + uvm_push_t push; + + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &src_plain, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &dst_plain, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &cipher, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &auth_tag_mem, auth_tag_buffer_size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + + write_range_cpu(src_plain, size, uvm_get_stale_thread_id()); + write_range_cpu(dst_plain, size, 0xA5A5A5A5); + + TEST_NV_CHECK_GOTO(uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_SEC2, &push, "enc(cpu)_dec(gpu)"), out); + + cpu_encrypt(push.channel, cipher, src_plain, auth_tag_mem, size, copy_size); + gpu_decrypt(&push, dst_plain, cipher, auth_tag_mem, size, copy_size); + + uvm_push_end_and_wait(&push); + + TEST_CHECK_GOTO(mem_match(src_plain, dst_plain), out); + +out: + uvm_mem_free(auth_tag_mem); + uvm_mem_free(cipher); + uvm_mem_free(dst_plain); + uvm_mem_free(src_plain); + + return status; +} + +// This test depends on the CE for the encryption, so we assume tests from +// uvm_ce_test.c have successfully passed. +static NV_STATUS test_cpu_to_gpu_roundtrip(uvm_gpu_t *gpu, size_t copy_size, size_t size) +{ + NV_STATUS status = NV_OK; + uvm_mem_t *src_plain = NULL; + uvm_mem_t *src_cipher = NULL; + uvm_mem_t *dst_cipher = NULL; + uvm_mem_t *dst_plain = NULL; + uvm_mem_t *dst_plain_cpu = NULL; + uvm_mem_t *auth_tag_mem = NULL; + size_t auth_tag_buffer_size = (size / copy_size) * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + uvm_push_t push; + UvmCslIv *decrypt_iv; + uvm_tracker_t tracker; + + decrypt_iv = uvm_kvmalloc_zero((size / copy_size) * sizeof(UvmCslIv)); + if (!decrypt_iv) + return NV_ERR_NO_MEMORY; + + uvm_tracker_init(&tracker); + + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &src_plain, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &src_cipher, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &dst_cipher, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &dst_plain, size, MEM_ALLOC_TYPE_VIDMEM_PROTECTED), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &dst_plain_cpu, size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + TEST_NV_CHECK_GOTO(alloc_and_init_mem(gpu, &auth_tag_mem, auth_tag_buffer_size, MEM_ALLOC_TYPE_SYSMEM_DMA), out); + + write_range_cpu(src_plain, size, uvm_get_stale_thread_id()); + + TEST_NV_CHECK_GOTO(uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_SEC2, &push, "enc(cpu)_dec(gpu)"), out); + + cpu_encrypt(push.channel, src_cipher, src_plain, auth_tag_mem, size, copy_size); + gpu_decrypt(&push, dst_plain, src_cipher, auth_tag_mem, size, copy_size); + + uvm_push_end(&push); + TEST_NV_CHECK_GOTO(uvm_tracker_add_push(&tracker, &push), out); + + TEST_NV_CHECK_GOTO(uvm_push_begin_acquire(gpu->channel_manager, + UVM_CHANNEL_TYPE_GPU_TO_CPU, + &tracker, + &push, + "enc(gpu)_dec(cpu)"), + out); + + gpu_encrypt(&push, dst_cipher, dst_plain, decrypt_iv, auth_tag_mem, size, copy_size); + + TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), out); + + TEST_CHECK_GOTO(!mem_match(src_plain, src_cipher), out); + TEST_CHECK_GOTO(!mem_match(dst_cipher, src_plain), out); + + TEST_NV_CHECK_GOTO(cpu_decrypt(push.channel, + dst_plain_cpu, + dst_cipher, + decrypt_iv, + auth_tag_mem, + size, + copy_size), + out); + + TEST_CHECK_GOTO(mem_match(src_plain, dst_plain_cpu), out); + +out: + uvm_mem_free(auth_tag_mem); + uvm_mem_free(dst_plain_cpu); + uvm_mem_free(dst_plain); + uvm_mem_free(dst_cipher); + uvm_mem_free(src_cipher); + uvm_mem_free(src_plain); + + uvm_kvfree(decrypt_iv); + + uvm_tracker_deinit(&tracker); + + return status; +} + +static NV_STATUS test_encryption_decryption(uvm_gpu_t *gpu) +{ + size_t copy_sizes[] = { 4, 16, 512, 2 * UVM_SIZE_1KB, 4 * UVM_SIZE_1KB, 64 * UVM_SIZE_1KB, 2 * UVM_SIZE_1MB }; + int i; + + for (i = 0; i < ARRAY_SIZE(copy_sizes); i++) { + // Limit the number of methods in the gpu_encrypt()/gpu_decrypt() work + // submission. + size_t size = min(UVM_VA_BLOCK_SIZE, 256ull * copy_sizes[i]); + + // gpu_encrypt() and gpu_decrypt() iterate over a 'size' buffer. If + // copy_sizes[i] < 16 (SEC2 src and dst alignment requirement is + // 16-byte), SEC2 and our HAL implementation assert/fail. When + // copy_sizes[i] < 16, we only perform a single copy_sizes[i] copy. + if (copy_sizes[i] < 16) + size = copy_sizes[i]; + + UVM_ASSERT(size % copy_sizes[i] == 0); + + TEST_NV_CHECK_RET(test_cpu_to_gpu_sysmem(gpu, copy_sizes[i], size)); + TEST_NV_CHECK_RET(test_cpu_to_gpu_roundtrip(gpu, copy_sizes[i], size)); + } + + return NV_OK; +} + +static NV_STATUS test_sec2(uvm_va_space_t *va_space) +{ + uvm_gpu_t *gpu; + + for_each_va_space_gpu(gpu, va_space) { + TEST_CHECK_RET(uvm_conf_computing_mode_enabled(gpu)); + + TEST_NV_CHECK_RET(test_semaphore_release(gpu)); + TEST_NV_CHECK_RET(test_semaphore_timestamp(gpu)); + TEST_NV_CHECK_RET(test_encryption_decryption(gpu)); + } + + return NV_OK; +} + +NV_STATUS uvm_test_sec2_sanity(UVM_TEST_SEC2_SANITY_PARAMS *params, struct file *filp) +{ + NV_STATUS status; + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + uvm_va_space_down_read_rm(va_space); + + status = test_sec2(va_space); + if (status != NV_OK) + goto done; + +done: + uvm_va_space_up_read_rm(va_space); + + return status; +} + +NV_STATUS uvm_test_sec2_cpu_gpu_roundtrip(UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP_PARAMS *params, struct file *filp) +{ + NV_STATUS status = NV_OK; + uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_gpu_t *gpu; + + uvm_va_space_down_read(va_space); + + for_each_va_space_gpu(gpu, va_space) { + TEST_CHECK_RET(uvm_conf_computing_mode_enabled(gpu)); + + // To exercise certain SEC2 context save/restore races, do a looped + // decrypt with smaller copy sizes instead of larger copy sizes since we + // need SEC2 to context switch with pending work in different channels + // and smaller copies decrypt increases the probability of exercising + // SEC2 context switching. A single push of the entire size may not be + // enough to re-create this scenario since SEC2 doesn't preempt in the + // middle of the decrypt. + status = test_cpu_to_gpu_roundtrip(gpu, UVM_PAGE_SIZE_4K, UVM_VA_BLOCK_SIZE); + if (status != NV_OK) + goto done; + } + +done: + uvm_va_space_up_read(va_space); + + return status; +} diff --git a/kernel-open/nvidia-uvm/uvm_test.c b/kernel-open/nvidia-uvm/uvm_test.c index a8434d0503..f9f5744c0a 100644 --- a/kernel-open/nvidia-uvm/uvm_test.c +++ b/kernel-open/nvidia-uvm/uvm_test.c @@ -300,7 +300,6 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PMM_REVERSE_MAP, uvm_test_pmm_reverse_map); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PMM_INDIRECT_PEERS, uvm_test_pmm_indirect_peers); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_MM_RETAIN, uvm_test_va_space_mm_retain); - UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN, uvm_test_va_space_mm_delay_shutdown); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PMM_CHUNK_WITH_ELEVATED_PAGE, uvm_test_pmm_chunk_with_elevated_page); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_INJECT_ERROR, uvm_test_va_space_inject_error); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_GET_GPU_TIME, uvm_test_get_gpu_time); @@ -327,6 +326,8 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_RANGE_INJECT_ADD_GPU_VA_SPACE_ERROR, uvm_test_va_range_inject_add_gpu_va_space_error); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY, uvm_test_destroy_gpu_va_space_delay); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SEC2_SANITY, uvm_test_sec2_sanity); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP, uvm_test_sec2_cpu_gpu_roundtrip); UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED, uvm_test_cgroup_accounting_supported); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SPLIT_INVALIDATE_DELAY, uvm_test_split_invalidate_delay); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_CPU_CHUNK_API, uvm_test_cpu_chunk_api); diff --git a/kernel-open/nvidia-uvm/uvm_test.h b/kernel-open/nvidia-uvm/uvm_test.h index 8c7b7cbe19..80606f9a53 100644 --- a/kernel-open/nvidia-uvm/uvm_test.h +++ b/kernel-open/nvidia-uvm/uvm_test.h @@ -187,5 +187,7 @@ NV_STATUS uvm_test_tools_flush_replay_events(UVM_TEST_TOOLS_FLUSH_REPLAY_EVENTS_ NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_BUFFER_PARAMS *params, struct file *filp); NV_STATUS uvm_test_rb_tree_directed(UVM_TEST_RB_TREE_DIRECTED_PARAMS *params, struct file *filp); NV_STATUS uvm_test_rb_tree_random(UVM_TEST_RB_TREE_RANDOM_PARAMS *params, struct file *filp); +NV_STATUS uvm_test_sec2_sanity(UVM_TEST_SEC2_SANITY_PARAMS *params, struct file *filp); +NV_STATUS uvm_test_sec2_cpu_gpu_roundtrip(UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP_PARAMS *params, struct file *filp); NV_STATUS uvm_test_cpu_chunk_api(UVM_TEST_CPU_CHUNK_API_PARAMS *params, struct file *filp); #endif diff --git a/kernel-open/nvidia-uvm/uvm_test_ioctl.h b/kernel-open/nvidia-uvm/uvm_test_ioctl.h index eaae4ce115..ef73be0c0f 100644 --- a/kernel-open/nvidia-uvm/uvm_test_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_test_ioctl.h @@ -1081,20 +1081,6 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_VA_SPACE_MM_RETAIN_PARAMS; -// Forces the VA space mm_shutdown callback to delay until more than one thread -// has entered the callback. This provides a high probability of exercising code -// to handle this race condition between exit_mmap and file close. -// -// The delay has an upper bound to prevent an infinite stall. -#define UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN UVM_TEST_IOCTL_BASE(68) -typedef struct -{ - NvBool verbose; - - // NV_ERR_PAGE_TABLE_NOT_AVAIL if no va_space_mm is present - NV_STATUS rmStatus; -} UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN_PARAMS; - #define UVM_TEST_PMM_CHUNK_WITH_ELEVATED_PAGE UVM_TEST_IOCTL_BASE(69) typedef struct { @@ -1371,10 +1357,6 @@ typedef struct // Approximate duration for which to sleep with the va_space_mm retained. NvU64 sleep_us NV_ALIGN_BYTES(8); // In - // On success, this contains the value of mm->mm_users before mmput() is - // called. - NvU64 mm_users NV_ALIGN_BYTES(8); // Out - // NV_ERR_PAGE_TABLE_NOT_AVAIL Could not retain va_space_mm // (uvm_va_space_mm_or_current_retain returned // NULL) @@ -1420,6 +1402,12 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY_PARAMS; +#define UVM_TEST_SEC2_SANITY UVM_TEST_IOCTL_BASE(95) +typedef struct +{ + NV_STATUS rmStatus; // Out +} UVM_TEST_SEC2_SANITY_PARAMS; + #define UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED UVM_TEST_IOCTL_BASE(96) typedef struct { @@ -1433,6 +1421,14 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS; +// Tests the CSL/SEC2 encryption/decryption methods by doing a secure transfer +// of memory from CPU->GPU and a subsequent GPU->CPU transfer. +#define UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP UVM_TEST_IOCTL_BASE(99) +typedef struct +{ + NV_STATUS rmStatus; // Out +} UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP_PARAMS; + #define UVM_TEST_CPU_CHUNK_API UVM_TEST_IOCTL_BASE(100) typedef struct { diff --git a/kernel-open/nvidia-uvm/uvm_thread_context.h b/kernel-open/nvidia-uvm/uvm_thread_context.h index 6be2e41f50..ea3d0dd9f7 100644 --- a/kernel-open/nvidia-uvm/uvm_thread_context.h +++ b/kernel-open/nvidia-uvm/uvm_thread_context.h @@ -76,6 +76,9 @@ struct uvm_thread_context_struct // calls try_to_migrate() doesn't pass the pgmap_owner. uvm_va_block_t *ignore_hmm_invalidate_va_block; + // Used to filter out invalidations we don't care about. + unsigned long hmm_invalidate_seqnum; + // Pointer to enclosing node (if any) in red-black tree // // This field is ignored in interrupt paths diff --git a/kernel-open/nvidia-uvm/uvm_tools.c b/kernel-open/nvidia-uvm/uvm_tools.c index 09edb220b8..3f7d831bbb 100644 --- a/kernel-open/nvidia-uvm/uvm_tools.c +++ b/kernel-open/nvidia-uvm/uvm_tools.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -1613,7 +1613,9 @@ NV_STATUS uvm_api_tools_init_event_tracker(UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS * goto fail; } - if (!uvm_fd_va_space(event_tracker->uvm_file)) { + // We don't use uvm_fd_va_space() here because tools can work + // without an associated va_space_mm. + if (!uvm_fd_get_type(event_tracker->uvm_file, UVM_FD_VA_SPACE)) { fput(event_tracker->uvm_file); event_tracker->uvm_file = NULL; status = NV_ERR_ILLEGAL_ACTION; @@ -2045,17 +2047,23 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, // The RM flavor of the lock is needed to perform ECC checks. uvm_va_space_down_read_rm(va_space); - status = uvm_va_block_find_create(va_space, UVM_ALIGN_DOWN(target_va_start, PAGE_SIZE), block_context, &block); - if (status != NV_OK) { - uvm_va_space_up_read_rm(va_space); - if (mm) - uvm_up_read_mmap_lock(mm); - goto exit; - } + status = uvm_va_block_find_create(va_space, UVM_PAGE_ALIGN_DOWN(target_va_start), block_context, &block); + if (status != NV_OK) + goto unlock_and_exit; uvm_va_space_global_gpus(va_space, global_gpus); for_each_global_gpu_in_mask(gpu, global_gpus) { + + // When CC is enabled, the staging memory cannot be mapped on the + // GPU (it is protected sysmem), but it is still used to store the + // unencrypted version of the page contents when the page is + // resident on vidmem. + if (uvm_conf_computing_mode_enabled(gpu)) { + UVM_ASSERT(uvm_global_processor_mask_empty(retained_global_gpus)); + + break; + } if (uvm_global_processor_mask_test_and_set(retained_global_gpus, gpu->global_id)) continue; @@ -2069,26 +2077,15 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, // (even if those mappings may never be used) as tools read/write is // not on a performance critical path. status = uvm_mem_map_gpu_kernel(stage_mem, gpu); - if (status != NV_OK) { - uvm_va_space_up_read_rm(va_space); - if (mm) - uvm_up_read_mmap_lock(mm); - goto exit; - } + if (status != NV_OK) + goto unlock_and_exit; } // Make sure a CPU resident page has an up to date struct page pointer. if (uvm_va_block_is_hmm(block)) { - status = uvm_hmm_va_block_update_residency_info(block, - mm, - UVM_ALIGN_DOWN(target_va_start, PAGE_SIZE), - true); - if (status != NV_OK) { - uvm_va_space_up_read_rm(va_space); - if (mm) - uvm_up_read_mmap_lock(mm); - goto exit; - } + status = uvm_hmm_va_block_update_residency_info(block, mm, UVM_PAGE_ALIGN_DOWN(target_va_start), true); + if (status != NV_OK) + goto unlock_and_exit; } status = tools_access_va_block(block, block_context, target_va_start, bytes_now, is_write, stage_mem); @@ -2127,6 +2124,13 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, *bytes += bytes_now; } +unlock_and_exit: + if (status != NV_OK) { + uvm_va_space_up_read_rm(va_space); + if (mm) + uvm_up_read_mmap_lock(mm); + } + exit: uvm_va_block_context_free(block_context); diff --git a/kernel-open/nvidia-uvm/uvm_tracker_test.c b/kernel-open/nvidia-uvm/uvm_tracker_test.c index 40576be3c8..9f89163e55 100644 --- a/kernel-open/nvidia-uvm/uvm_tracker_test.c +++ b/kernel-open/nvidia-uvm/uvm_tracker_test.c @@ -83,6 +83,13 @@ static NV_STATUS test_tracker_completion(uvm_va_space_t *va_space) uvm_for_each_pool(pool, gpu->channel_manager) { uvm_channel_t *channel; + // Skip WLC channels as they are used for secure work launch + if (uvm_channel_pool_is_wlc(pool)) + continue; + + // Skip LCIC channels as those can't accept pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { uvm_push_t push; NvU64 semaphore_gpu_va; @@ -214,6 +221,9 @@ static NV_STATUS test_tracker_basic(uvm_va_space_t *va_space) uvm_for_each_pool(pool, gpu->channel_manager) { uvm_channel_t *channel; + // Skip LCIC channels as those can't accept pushes + if (uvm_channel_pool_is_lcic(pool)) + continue; uvm_for_each_channel_in_pool(channel, pool) { uvm_push_t push; status = uvm_push_begin_on_channel(channel, &push, "Test push"); diff --git a/kernel-open/nvidia-uvm/uvm_turing.c b/kernel-open/nvidia-uvm/uvm_turing.c index c7e3c16182..29a1fa68df 100644 --- a/kernel-open/nvidia-uvm/uvm_turing.c +++ b/kernel-open/nvidia-uvm/uvm_turing.c @@ -46,11 +46,13 @@ void uvm_hal_turing_arch_init_properties(uvm_parent_gpu_t *parent_gpu) // A single top level PDE on Turing covers 128 TB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_VIRTUAL; // Not all units on Turing support 49-bit addressing, including those which diff --git a/kernel-open/nvidia-uvm/uvm_turing_host.c b/kernel-open/nvidia-uvm/uvm_turing_host.c index 295cabcf1a..403af652a8 100644 --- a/kernel-open/nvidia-uvm/uvm_turing_host.c +++ b/kernel-open/nvidia-uvm/uvm_turing_host.c @@ -83,9 +83,14 @@ void uvm_hal_turing_host_clear_faulted_channel_method(uvm_push_t *push, // Direct copy of uvm_hal_maxwell_host_set_gpfifo_entry(). It removes // GP_ENTRY1_PRIV_KERNEL, which has been deprecated in Turing+. -void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va, NvU32 pushbuffer_length) +void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, + NvU64 pushbuffer_va, + NvU32 pushbuffer_length, + uvm_gpfifo_sync_t sync_flag) { NvU64 fifo_entry_value; + const NvU32 sync_value = (sync_flag == UVM_GPFIFO_SYNC_WAIT) ? HWCONST(C46F, GP_ENTRY1, SYNC, WAIT) : + HWCONST(C46F, GP_ENTRY1, SYNC, PROCEED); UVM_ASSERT(!uvm_global_is_suspended()); UVM_ASSERT_MSG(pushbuffer_va % 4 == 0, "pushbuffer va unaligned: %llu\n", pushbuffer_va); @@ -93,7 +98,8 @@ void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry, NvU64 pushbuffer_va fifo_entry_value = HWVALUE(C46F, GP_ENTRY0, GET, NvU64_LO32(pushbuffer_va) >> 2); fifo_entry_value |= (NvU64)(HWVALUE(C46F, GP_ENTRY1, GET_HI, NvU64_HI32(pushbuffer_va)) | - HWVALUE(C46F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2)) << 32; + HWVALUE(C46F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2) | + sync_value) << 32; *fifo_entry = fifo_entry_value; } diff --git a/kernel-open/nvidia-uvm/uvm_types.h b/kernel-open/nvidia-uvm/uvm_types.h index 60d3d934ce..da3e6da7a1 100644 --- a/kernel-open/nvidia-uvm/uvm_types.h +++ b/kernel-open/nvidia-uvm/uvm_types.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2013-2020 NVidia Corporation + Copyright (c) 2013-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -493,7 +493,8 @@ typedef enum UvmEventFatalReasonInternalError = 5, // This value is reported when a fault is triggered in an invalid context - // Example: CPU fault on a managed allocation while a kernel is running on a pre-Pascal GPU + // Example: CPU fault on a managed allocation while a kernel is running on a + // pre-Pascal GPU UvmEventFatalReasonInvalidOperation = 6, // ---- Add new values above this line UvmEventNumFatalReasons @@ -659,8 +660,8 @@ typedef struct // or malign-double will have no effect on the field offsets // NvU8 padding8bits; - NvU32 batchId; // Per-GPU unique id to identify the faults that have - // been serviced in batch + NvU32 batchId; // Per-GPU unique id to identify the faults that + // have been serviced in batch NvU64 timeStamp; // cpu time when the replay of the faulting memory // accesses is queued on the gpu NvU64 timeStampGpu; // gpu time stamp when the replay operation finished @@ -674,15 +675,16 @@ typedef struct { // // eventType has to be the 1st argument of this structure. - // Setting eventType = UvmEventTypeFatalFault helps to identify event data in - // a queue. + // Setting eventType = UvmEventTypeFatalFault helps to identify event data + // in a queue. // NvU8 eventType; - NvU8 faultType; // type of gpu fault, refer UvmEventFaultType. Only valid - // if processorIndex is a GPU + NvU8 faultType; // type of gpu fault, refer UvmEventFaultType. Only + // valid if processorIndex is a GPU NvU8 accessType; // memory access type, refer UvmEventMemoryAccessType NvU8 processorIndex; // processor that experienced the fault - NvU8 reason; // reason why the fault is fatal, refer UvmEventFatalReason + NvU8 reason; // reason why the fault is fatal, refer + // UvmEventFatalReason NvU8 padding8bits; NvU16 padding16bits; NvU64 address; // virtual address at which the processor faulted @@ -798,8 +800,8 @@ typedef struct { // // eventType has to be the 1st argument of this structure. - // Setting eventType = UvmEventTypeThrottlingStart helps to identify event data - // in a queue. + // Setting eventType = UvmEventTypeThrottlingStart helps to identify event + // data in a queue. // NvU8 eventType; NvU8 processorIndex; // index of the cpu/gpu that was throttled @@ -819,8 +821,8 @@ typedef struct { // // eventType has to be the 1st argument of this structure. - // Setting eventType = UvmEventTypeThrottlingEnd helps to identify event data - // in a queue. + // Setting eventType = UvmEventTypeThrottlingEnd helps to identify event + // data in a queue. // NvU8 eventType; NvU8 processorIndex; // index of the cpu/gpu that was throttled @@ -946,8 +948,8 @@ typedef struct { // // eventType has to be the 1st argument of this structure. - // Setting eventType = UvmEventTypeAccessCounter helps to identify event data - // in a queue. + // Setting eventType = UvmEventTypeAccessCounter helps to identify event + // data in a queue. // NvU8 eventType; NvU8 srcIndex; // index of the gpu that received the access counter diff --git a/kernel-open/nvidia-uvm/uvm_va_block.c b/kernel-open/nvidia-uvm/uvm_va_block.c index ef37013edb..b476d93a69 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.c +++ b/kernel-open/nvidia-uvm/uvm_va_block.c @@ -39,6 +39,7 @@ #include "uvm_gpu_access_counters.h" #include "uvm_va_space_mm.h" #include "uvm_test_ioctl.h" +#include "uvm_conf_computing.h" typedef enum { @@ -515,6 +516,33 @@ static uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_region(uvm_va_block_t *va_block, (va_block), \ uvm_va_block_region_from_block((va_block))) +struct vm_area_struct *uvm_va_block_find_vma_region(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 start, + uvm_va_block_region_t *region) +{ + struct vm_area_struct *vma; + NvU64 end; + + if (start > va_block->end) + return NULL; + + vma = find_vma_intersection(mm, start, va_block->end + 1); + if (!vma) + return NULL; + + if (start < vma->vm_start) + start = vma->vm_start; + + end = vma->vm_end - 1; + if (end > va_block->end) + end = va_block->end; + + *region = uvm_va_block_region_from_start_end(va_block, start, end); + + return vma; +} + static bool block_check_cpu_chunks(uvm_va_block_t *block) { uvm_cpu_chunk_t *chunk; @@ -955,6 +983,12 @@ static NV_STATUS cpu_chunk_add_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, NV_STATUS status; uvm_chunk_size_t chunk_size; + // When the Confidential Computing feature is enabled the transfers don't + // use the DMA mapping of CPU chunks (since it's protected memory), but + // the DMA address of the unprotected dma buffer. + if (uvm_conf_computing_mode_enabled(gpu)) + return NV_OK; + status = uvm_cpu_chunk_map_gpu(chunk, gpu); if (status != NV_OK) return status; @@ -1334,6 +1368,7 @@ static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, // // Also maps the page for physical access by all GPUs used by the block, which // is required for IOMMU support. Skipped on GPUs without access to CPU memory. +// e.g., this happens when the Confidential Computing Feature is enabled. static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, uvm_page_mask_t *populate_page_mask, uvm_va_block_region_t populate_region, @@ -2259,11 +2294,7 @@ static NV_STATUS block_zero_new_gpu_chunk(uvm_va_block_t *block, // are the pages which must be zeroed. uvm_page_mask_complement(zero_mask, zero_mask); - if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) - memset_addr_base = uvm_gpu_address_virtual_from_vidmem_phys(gpu, chunk->address); - else - memset_addr_base = uvm_gpu_address_physical(UVM_APERTURE_VID, chunk->address); - + memset_addr_base = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(UVM_APERTURE_VID, chunk->address)); memset_addr = memset_addr_base; status = uvm_push_begin_acquire(gpu->channel_manager, @@ -2563,29 +2594,16 @@ static uvm_gpu_address_t block_phys_page_copy_address(uvm_va_block_t *block, uvm_gpu_chunk_t *chunk; uvm_gpu_address_t copy_addr; uvm_va_space_t *va_space; - bool page_in_cpu, page_in_local_gpu; UVM_ASSERT_MSG(block_can_copy_from(block, gpu->id, block_page.processor), "from %s to %s\n", block_processor_name(block, gpu->id), block_processor_name(block, block_page.processor)); - page_in_cpu = UVM_ID_IS_CPU(block_page.processor); - page_in_local_gpu = uvm_id_equal(block_page.processor, gpu->id); - // CPU and local GPU accesses can rely on block_phys_page_address, but the // resulting physical address may need to be converted into virtual. - if (page_in_cpu || page_in_local_gpu) { - uvm_gpu_phys_address_t gpu_phys_address = block_phys_page_address(block, block_page, gpu); - - if (page_in_cpu && uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) - return uvm_gpu_address_virtual_from_sysmem_phys(gpu, gpu_phys_address.address); - - if (page_in_local_gpu && uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) - return uvm_gpu_address_virtual_from_vidmem_phys(gpu, gpu_phys_address.address); - - return uvm_gpu_address_from_phys(gpu_phys_address); - } + if (UVM_ID_IS_CPU(block_page.processor) || uvm_id_equal(block_page.processor, gpu->id)) + return uvm_gpu_address_copy(gpu, block_phys_page_address(block, block_page, gpu)); va_space = uvm_va_block_get_va_space(block); @@ -2636,6 +2654,7 @@ typedef struct { block_copy_addr_t src; block_copy_addr_t dst; + uvm_conf_computing_dma_buffer_t *dma_buffer; } block_copy_state_t; // Begin a push appropriate for copying data from src_id processor to dst_id processor. @@ -2697,6 +2716,36 @@ static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, va_block->end); } + if (uvm_conf_computing_mode_enabled(gpu)) { + // When the Confidential Feature is enabled, additional dependencies + // apply to the input tracker as well as the dma_buffer tracker. + // * In the CPU to GPU case, because UVM performs CPU side + // crypto-operations first before the GPU copy, we both need to + // ensure that the dma_buffer and the input tracker are completed. + // * In the GPU to CPU case, the GPU copy happens first, but the same + // principles apply. Hence, UVM acquires the input tracker and the + // dma buffer. + status = uvm_tracker_overwrite_safe(&local_tracker, tracker); + if (status != NV_OK) + goto error; + + UVM_ASSERT(copy_state->dma_buffer == NULL); + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, + ©_state->dma_buffer, + &local_tracker); + + if (status != NV_OK) + goto error; + + if (channel_type == UVM_CHANNEL_TYPE_CPU_TO_GPU) { + status = uvm_tracker_wait(&local_tracker); + if (status != NV_OK) + goto error; + } + + tracker_ptr = &local_tracker; + } + status = uvm_push_begin_acquire(gpu->channel_manager, channel_type, tracker_ptr, @@ -2707,6 +2756,8 @@ static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, va_block->start, va_block->end); +error: + // Caller is responsible for freeing the DMA buffer on error uvm_tracker_deinit(&local_tracker); return status; } @@ -2863,13 +2914,191 @@ static uvm_gpu_address_t block_copy_get_address(uvm_va_block_t *block, return block_phys_page_copy_address(block, block_phys_page(bca->id, page_index), copying_gpu); } -static uvm_gpu_address_t block_copy_addr_get_virt(uvm_va_block_t *block, - block_copy_addr_t *bca, - uvm_page_index_t page_index, - uvm_gpu_t *copying_gpu) +// When the Confidential Computing feature is enabled, the function performs +// CPU side page encryption and GPU side decryption to the CPR. +// GPU operations respect the caller's membar previously set in the push. +static void conf_computing_block_copy_push_cpu_to_gpu(uvm_va_block_t *block, + block_copy_state_t *copy_state, + uvm_va_block_region_t region, + uvm_push_t *push) +{ + uvm_push_flag_t membar_flag = 0; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_page_index_t page_index = region.first; + uvm_conf_computing_dma_buffer_t *dma_buffer = copy_state->dma_buffer; + struct page *src_page = uvm_cpu_chunk_get_cpu_page(block, page_index); + uvm_gpu_address_t staging_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); + uvm_gpu_address_t auth_tag_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); + char *cpu_auth_tag_buffer = (char *)uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag) + + (page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); + uvm_gpu_address_t dst_address = block_copy_get_address(block, ©_state->dst, page_index, gpu); + char *cpu_va_staging_buffer = (char *)uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc) + (page_index * PAGE_SIZE); + + UVM_ASSERT(UVM_ID_IS_CPU(copy_state->src.id)); + UVM_ASSERT(UVM_ID_IS_GPU(copy_state->dst.id)); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + // See comment in block_copy_begin_push. + UVM_ASSERT(uvm_tracker_is_completed(&block->tracker)); + + staging_buffer.address += page_index * PAGE_SIZE; + auth_tag_buffer.address += page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + + // kmap() only guarantees PAGE_SIZE contiguity, all encryption and + // decryption must happen on a PAGE_SIZE basis. + for_each_va_block_page_in_region(page_index, region) { + void *src_cpu_virt_addr; + + // The caller guarantees that all pages in region are contiguous, + // meaning they're guaranteed to be part of the same compound page. + UVM_ASSERT(src_page == uvm_cpu_chunk_get_cpu_page(block, page_index)); + + src_cpu_virt_addr = kmap(src_page); + uvm_conf_computing_cpu_encrypt(push->channel, + cpu_va_staging_buffer, + src_cpu_virt_addr, + NULL, + PAGE_SIZE, + cpu_auth_tag_buffer); + kunmap(src_page); + + // First LCE operation should be non-pipelined to guarantee ordering as + // we do not know when was the last non-pipelined copy. + // Last one applies the membar originally planned for the push if any + // TODO: 3857691: Inherit policy instead of forcing first invocation to + // be non pipelined. + if (page_index > region.first) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + if (page_index < (region.outer - 1)) + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + else if (membar_flag) + uvm_push_set_flag(push, membar_flag); + + gpu->parent->ce_hal->decrypt(push, dst_address, staging_buffer, PAGE_SIZE, auth_tag_buffer); + + src_page++; + dst_address.address += PAGE_SIZE; + cpu_va_staging_buffer += PAGE_SIZE; + staging_buffer.address += PAGE_SIZE; + cpu_auth_tag_buffer += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + auth_tag_buffer.address += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } +} + +// When the Confidential Computing feature is enabled, the function performs +// GPU side page encryption. GPU operations respect the caller's membar +// previously set in the push. +static void conf_computing_block_copy_push_gpu_to_cpu(uvm_va_block_t *block, + block_copy_state_t *copy_state, + uvm_va_block_region_t region, + uvm_push_t *push) +{ + uvm_push_flag_t membar_flag = 0; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_page_index_t page_index = region.first; + uvm_conf_computing_dma_buffer_t *dma_buffer = copy_state->dma_buffer; + uvm_gpu_address_t staging_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); + uvm_gpu_address_t auth_tag_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); + uvm_gpu_address_t src_address = block_copy_get_address(block, ©_state->src, page_index, gpu); + + UVM_ASSERT(UVM_ID_IS_GPU(copy_state->src.id)); + UVM_ASSERT(UVM_ID_IS_CPU(copy_state->dst.id)); + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + + staging_buffer.address += page_index * PAGE_SIZE; + auth_tag_buffer.address += page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + + // Because we use kmap() for mapping pages for CPU side + // crypto-operations and it only guarantees PAGE_SIZE contiguity, all + // encryptions and decryptions must happen on a PAGE_SIZE basis. + for_each_va_block_page_in_region(page_index, region) { + uvm_conf_computing_log_gpu_encryption(push->channel, &dma_buffer->decrypt_iv[page_index]); + + // First LCE operation should be non-pipelined to guarantee ordering as + // we do not know when was the last non-pipelined copy. + // Last one applies the membar originally planned for the push if any + // TODO: 3857691: Inherit policy instead of forcing first invocation to + // be non pipelined. + if (page_index > region.first) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + if (page_index < (region.outer - 1)) + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + else if (membar_flag) + uvm_push_set_flag(push, membar_flag); + + gpu->parent->ce_hal->encrypt(push, staging_buffer, src_address, PAGE_SIZE, auth_tag_buffer); + + src_address.address += PAGE_SIZE; + staging_buffer.address += PAGE_SIZE; + auth_tag_buffer.address += UVM_CONF_COMPUTING_AUTH_TAG_SIZE; + } + + uvm_page_mask_region_fill(&dma_buffer->encrypted_page_mask, region); +} + +static NV_STATUS conf_computing_copy_pages_finish(uvm_va_block_t *block, + block_copy_state_t *copy_state, + uvm_push_t *push) { - uvm_gpu_address_t gpu_address = block_copy_get_address(block, bca, page_index, copying_gpu); - return uvm_gpu_address_virtual_from_vidmem_phys(copying_gpu, gpu_address.address); + NV_STATUS status; + uvm_page_index_t page_index; + uvm_conf_computing_dma_buffer_t *dma_buffer = copy_state->dma_buffer; + uvm_page_mask_t *encrypted_page_mask = &dma_buffer->encrypted_page_mask; + void *auth_tag_buffer_base = uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag); + void *staging_buffer_base = uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc); + + UVM_ASSERT(uvm_channel_is_secure(push->channel)); + + if (UVM_ID_IS_GPU(copy_state->dst.id)) + return NV_OK; + + UVM_ASSERT(UVM_ID_IS_GPU(copy_state->src.id)); + + status = uvm_push_wait(push); + if (status != NV_OK) + return status; + + // kmap() only guarantees PAGE_SIZE contiguity, all encryption and + // decryption must happen on a PAGE_SIZE basis. + for_each_va_block_page_in_mask(page_index, encrypted_page_mask, block) { + struct page *dst_page = uvm_cpu_chunk_get_cpu_page(block, page_index); + void *staging_buffer = (char *)staging_buffer_base + (page_index * PAGE_SIZE); + void *auth_tag_buffer = (char *)auth_tag_buffer_base + (page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); + void *cpu_page_address = kmap(dst_page); + + status = uvm_conf_computing_cpu_decrypt(push->channel, + cpu_page_address, + staging_buffer, + &dma_buffer->decrypt_iv[page_index], + PAGE_SIZE, + auth_tag_buffer); + kunmap(dst_page); + if (status != NV_OK) { + // TODO: Bug 3814087: [UVM][HCC] Handle CSL auth_tag verification + // failures & other failures gracefully. + // uvm_conf_computing_cpu_decrypt() can fail if the authentication + // tag verification fails. May this happen, it is considered a + // critical failure and cannot be recovered. + uvm_global_set_fatal_error(status); + return status; + } + } + + return NV_OK; } static void block_copy_push(uvm_va_block_t *block, @@ -2883,6 +3112,15 @@ static void block_copy_push(uvm_va_block_t *block, uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + if (uvm_channel_is_secure(push->channel)) { + if (UVM_ID_IS_CPU(copy_state->src.id)) + conf_computing_block_copy_push_cpu_to_gpu(block, copy_state, region, push); + else + conf_computing_block_copy_push_gpu_to_cpu(block, copy_state, region, push); + + return; + } + gpu_dst_address = block_copy_get_address(block, ©_state->dst, region.first, gpu); gpu_src_address = block_copy_get_address(block, ©_state->src, region.first, gpu); gpu->parent->ce_hal->memcopy(push, gpu_dst_address, gpu_src_address, uvm_va_block_region_size(region)); @@ -2902,10 +3140,25 @@ static NV_STATUS block_copy_end_push(uvm_va_block_t *block, // at that point. uvm_push_end(push); + if ((push_status == NV_OK) && uvm_channel_is_secure(push->channel)) + push_status = conf_computing_copy_pages_finish(block, copy_state, push); + tracker_status = uvm_tracker_add_push_safe(copy_tracker, push); if (push_status == NV_OK) push_status = tracker_status; + if (uvm_channel_is_secure(push->channel)) { + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); + + uvm_tracker_overwrite_with_push(&local_tracker, push); + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, + copy_state->dma_buffer, + &local_tracker); + copy_state->dma_buffer = NULL; + uvm_tracker_deinit(&local_tracker); + } + return push_status; } @@ -3062,6 +3315,12 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, contig_start_index = page_index; contig_cause = page_cause; + // When CC is enabled, transfers between GPU and CPU don't rely on + // any GPU mapping of CPU chunks, physical or virtual. + if (UVM_ID_IS_CPU(src_id) && uvm_conf_computing_mode_enabled(copying_gpu)) + can_cache_src_phys_addr = false; + if (UVM_ID_IS_CPU(dst_id) && uvm_conf_computing_mode_enabled(copying_gpu)) + can_cache_dst_phys_addr = false; // Computing the physical address is a non-trivial operation and // seems to be a performance limiter on systems with 2 or more // NVLINK links. Therefore, for physically-contiguous block @@ -6118,7 +6377,6 @@ static NV_STATUS block_alloc_pt_range_with_retry(uvm_va_block_t *va_block, // to allocate the lower levels. bool use_alloc_table = block_gpu_supports_2m(va_block, gpu) && page_size < UVM_PAGE_SIZE_2M; - // TODO: Bug 3898454: check locking requirement for UVM-HMM. UVM_ASSERT(page_table_range->table == NULL); if (va_block_test && va_block_test->page_table_allocation_retry_force_count > 0) { @@ -6310,26 +6568,31 @@ static NV_STATUS block_pre_populate_pde1_gpu(uvm_va_block_t *block, uvm_gpu_va_space_t *gpu_va_space, uvm_tracker_t *pending_tracker) { - NvU32 page_sizes = 0; - uvm_gpu_t *gpu = gpu_va_space->gpu; - uvm_va_block_gpu_state_t *gpu_state = block_gpu_state_get_alloc(block, gpu); + NvU32 page_sizes; + NvU32 big_page_size; + uvm_gpu_t *gpu; + uvm_va_block_gpu_state_t *gpu_state; - UVM_ASSERT(gpu_state); + UVM_ASSERT(block); UVM_ASSERT(gpu_va_space); - UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); UVM_ASSERT(gpu_va_space->ats.enabled); + UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); + + gpu = gpu_va_space->gpu; + big_page_size = gpu_va_space->page_tables.big_page_size; + + gpu_state = block_gpu_state_get_alloc(block, gpu); + if (!gpu_state) + return NV_ERR_NO_MEMORY; // If the VA Block supports 2M pages, allocate the 2M PTE only, as it // requires less memory - if (block_gpu_supports_2m(block, gpu)) { + if (block_gpu_supports_2m(block, gpu)) page_sizes = UVM_PAGE_SIZE_2M; - } - else { - // ATS is only enabled on P9 + Volta, therefore, PAGE_SIZE should - // be 64K and should match Volta big page size - UVM_ASSERT(uvm_va_block_gpu_big_page_size(block, gpu) == PAGE_SIZE); - page_sizes = UVM_PAGE_SIZE_64K; - } + else if (uvm_va_block_num_big_pages(block, big_page_size) > 0) + page_sizes = big_page_size; + else + page_sizes = UVM_PAGE_SIZE_4K; return block_alloc_ptes_with_retry(block, gpu, page_sizes, pending_tracker); } @@ -6586,7 +6849,7 @@ static struct page *block_page_get(uvm_va_block_t *block, block_phys_page_t bloc size_t chunk_offset; uvm_gpu_chunk_t *chunk = block_phys_page_chunk(block, block_page, &chunk_offset); - UVM_ASSERT(gpu->parent->numa_info.enabled); + UVM_ASSERT(gpu->mem_info.numa.enabled); page = uvm_gpu_chunk_to_page(&gpu->pmm, chunk) + chunk_offset / PAGE_SIZE; } @@ -10806,6 +11069,162 @@ NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, return uvm_va_block_find_create_in_range(va_space, va_range, addr, va_block_context, out_block); } +// Launch a synchronous, encrypted copy between GPU and CPU. +// +// The copy entails a GPU-side encryption (relying on the Copy Engine), and a +// CPU-side decryption step, such that the destination CPU buffer pointed by +// dst_plain will contain the unencrypted (plain text) contents. The destination +// buffer can be in protected or unprotected sysmem, while the source buffer +// must be in protected vidmem. +// +// The maximum copy size allowed is UVM_CONF_COMPUTING_DMA_BUFFER_SIZE. +// +// The input tracker, if not NULL, is internally acquired by the push +// responsible for the encrypted copy. +__attribute__ ((format(printf, 6, 7))) +static NV_STATUS encrypted_memcopy_gpu_to_cpu(uvm_gpu_t *gpu, + void *dst_plain, + uvm_gpu_address_t src_gpu_address, + size_t size, + uvm_tracker_t *tracker, + const char *format, + ...) +{ + NV_STATUS status; + UvmCslIv decrypt_iv; + uvm_push_t push; + uvm_conf_computing_dma_buffer_t *dma_buffer; + uvm_gpu_address_t dst_gpu_address, auth_tag_gpu_address; + void *src_cipher, *auth_tag; + va_list args; + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(size <= UVM_CONF_COMPUTING_DMA_BUFFER_SIZE); + + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &dma_buffer, NULL); + if (status != NV_OK) + return status; + + va_start(args, format); + status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, tracker, &push, format, args); + va_end(args); + + if (status != NV_OK) + goto out; + + uvm_conf_computing_log_gpu_encryption(push.channel, &decrypt_iv); + + dst_gpu_address = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); + auth_tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); + gpu->parent->ce_hal->encrypt(&push, dst_gpu_address, src_gpu_address, size, auth_tag_gpu_address); + + status = uvm_push_end_and_wait(&push); + if (status != NV_OK) + goto out; + + src_cipher = uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc); + auth_tag = uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag); + status = uvm_conf_computing_cpu_decrypt(push.channel, dst_plain, src_cipher, &decrypt_iv, size, auth_tag); + + out: + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, dma_buffer, NULL); + return status; +} + +// Launch a synchronous, encrypted copy between CPU and GPU. +// +// The source CPU buffer pointed by src_plain contains the unencrypted (plain +// text) contents; the function internally performs a CPU-side encryption step +// before launching the GPU-side CE decryption. The source buffer can be in +// protected or unprotected sysmem, while the destination buffer must be in +// protected vidmem. +// +// The maximum copy size allowed is UVM_CONF_COMPUTING_DMA_BUFFER_SIZE. +// +// The input tracker, if not NULL, is internally acquired by the push +// responsible for the encrypted copy. +__attribute__ ((format(printf, 6, 7))) +static NV_STATUS encrypted_memcopy_cpu_to_gpu(uvm_gpu_t *gpu, + uvm_gpu_address_t dst_gpu_address, + void *src_plain, + size_t size, + uvm_tracker_t *tracker, + const char *format, + ...) +{ + NV_STATUS status; + uvm_push_t push; + uvm_conf_computing_dma_buffer_t *dma_buffer; + uvm_gpu_address_t src_gpu_address, auth_tag_gpu_address; + void *dst_cipher, *auth_tag; + va_list args; + + UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(size <= UVM_CONF_COMPUTING_DMA_BUFFER_SIZE); + + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &dma_buffer, NULL); + if (status != NV_OK) + return status; + + va_start(args, format); + status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_CPU_TO_GPU, tracker, &push, format, args); + va_end(args); + + if (status != NV_OK) + goto out; + + dst_cipher = uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc); + auth_tag = uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag); + uvm_conf_computing_cpu_encrypt(push.channel, dst_cipher, src_plain, NULL, size, auth_tag); + + src_gpu_address = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); + auth_tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); + gpu->parent->ce_hal->decrypt(&push, dst_gpu_address, src_gpu_address, size, auth_tag_gpu_address); + + status = uvm_push_end_and_wait(&push); + +out: + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, dma_buffer, NULL); + return status; +} + +static NV_STATUS va_block_write_cpu_to_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_gpu_address_t dst_gpu_address, + NvU64 dst, + uvm_mem_t *src_mem, + size_t size) +{ + NV_STATUS status; + uvm_push_t push; + uvm_gpu_address_t src_gpu_address; + + if (uvm_conf_computing_mode_enabled(gpu)) { + return encrypted_memcopy_cpu_to_gpu(gpu, + dst_gpu_address, + uvm_mem_get_cpu_addr_kernel(src_mem), + size, + &va_block->tracker, + "Encrypted write to [0x%llx, 0x%llx)", + dst, + dst + size); + } + + status = uvm_push_begin_acquire(gpu->channel_manager, + UVM_CHANNEL_TYPE_CPU_TO_GPU, + &va_block->tracker, + &push, + "Direct write to [0x%llx, 0x%llx)", + dst, + dst + size); + if (status != NV_OK) + return status; + + src_gpu_address = uvm_mem_gpu_address_virtual_kernel(src_mem, gpu); + gpu->parent->ce_hal->memcopy(&push, dst_gpu_address, src_gpu_address, size); + return uvm_push_end_and_wait(&push); +} + NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, uvm_va_block_context_t *block_context, NvU64 dst, @@ -10817,15 +11236,9 @@ NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, NvU64 page_offset = dst & (PAGE_SIZE - 1); uvm_processor_id_t proc = uvm_va_block_page_get_closest_resident(va_block, page_index, UVM_ID_CPU); uvm_va_block_region_t region = uvm_va_block_region_for_page(page_index); - void *src = uvm_mem_get_cpu_addr_kernel(src_mem); - uvm_gpu_t *gpu; - uvm_gpu_address_t src_gpu_address; - uvm_gpu_address_t dst_gpu_address; - uvm_push_t push; uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT_MSG(UVM_ALIGN_DOWN(dst, PAGE_SIZE) == UVM_ALIGN_DOWN(dst + size - 1, PAGE_SIZE), - "dst 0x%llx size 0x%zx\n", dst, size); + UVM_ASSERT_MSG(page_offset + size <= PAGE_SIZE, "Write spans multiple pages: dst 0x%llx, size 0x%zx\n", dst, size); if (UVM_ID_IS_INVALID(proc)) proc = UVM_ID_CPU; @@ -10852,6 +11265,7 @@ NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, if (UVM_ID_IS_CPU(proc)) { char *mapped_page; struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); + void *src = uvm_mem_get_cpu_addr_kernel(src_mem); status = uvm_tracker_wait(&va_block->tracker); if (status != NV_OK) @@ -10863,50 +11277,74 @@ NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, return NV_OK; } + else { + uvm_gpu_t *dst_gpu; + uvm_gpu_address_t dst_gpu_address; - gpu = block_get_gpu(va_block, proc); + UVM_ASSERT(UVM_ID_IS_GPU(proc)); - dst_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), gpu); - dst_gpu_address.address += page_offset; + dst_gpu = block_get_gpu(va_block, proc); - src_gpu_address = uvm_mem_gpu_address_virtual_kernel(src_mem, gpu); + dst_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), dst_gpu); + dst_gpu_address.address += page_offset; + + return va_block_write_cpu_to_gpu(va_block, dst_gpu, dst_gpu_address, dst, src_mem, size); + } +} + +static NV_STATUS va_block_read_gpu_to_cpu(uvm_va_block_t *va_block, + uvm_mem_t *dst_mem, + uvm_gpu_t *gpu, + uvm_gpu_address_t src_gpu_address, + NvU64 src, + size_t size) +{ + NV_STATUS status; + uvm_push_t push; + uvm_gpu_address_t dst_gpu_address; + + if (uvm_conf_computing_mode_enabled(gpu)) { + return encrypted_memcopy_gpu_to_cpu(gpu, + uvm_mem_get_cpu_addr_kernel(dst_mem), + src_gpu_address, + size, + &va_block->tracker, + "Encrypted read from [0x%llx, 0x%llx)", + src, + src + size); + } status = uvm_push_begin_acquire(gpu->channel_manager, - UVM_CHANNEL_TYPE_CPU_TO_GPU, + UVM_CHANNEL_TYPE_GPU_TO_CPU, &va_block->tracker, &push, - "Direct write to [0x%llx, 0x%llx)", - dst, - dst + size); + "Direct read from [0x%llx, 0x%llx)", + src, + src + size); if (status != NV_OK) return status; + dst_gpu_address = uvm_mem_gpu_address_virtual_kernel(dst_mem, gpu); gpu->parent->ce_hal->memcopy(&push, dst_gpu_address, src_gpu_address, size); return uvm_push_end_and_wait(&push); } NV_STATUS uvm_va_block_read_to_cpu(uvm_va_block_t *va_block, uvm_mem_t *dst_mem, NvU64 src, size_t size) { - NV_STATUS status; uvm_page_index_t page_index = uvm_va_block_cpu_page_index(va_block, src); NvU64 page_offset = src & (PAGE_SIZE - 1); uvm_processor_id_t proc = uvm_va_block_page_get_closest_resident(va_block, page_index, UVM_ID_CPU); void *dst = uvm_mem_get_cpu_addr_kernel(dst_mem); - uvm_gpu_t *gpu; - uvm_gpu_address_t src_gpu_address; - uvm_gpu_address_t dst_gpu_address; - uvm_push_t push; uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT_MSG(UVM_ALIGN_DOWN(src, PAGE_SIZE) == UVM_ALIGN_DOWN(src + size - 1, PAGE_SIZE), - "src 0x%llx size 0x%zx\n", src, size); + UVM_ASSERT_MSG(page_offset + size <= PAGE_SIZE, "Read spans multiple pages: src 0x%llx, size 0x%zx\n", src, size); if (UVM_ID_IS_INVALID(proc)) { memset(dst, 0, size); return NV_OK; } - - if (UVM_ID_IS_CPU(proc)) { + else if (UVM_ID_IS_CPU(proc)) { + NV_STATUS status; char *mapped_page; struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); @@ -10920,27 +11358,15 @@ NV_STATUS uvm_va_block_read_to_cpu(uvm_va_block_t *va_block, uvm_mem_t *dst_mem, return NV_OK; } + else { + uvm_gpu_address_t src_gpu_address; + uvm_gpu_t *gpu = block_get_gpu(va_block, proc); - gpu = block_get_gpu(va_block, proc); - - dst_gpu_address = uvm_mem_gpu_address_virtual_kernel(dst_mem, gpu); - - src_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), gpu); - src_gpu_address.address += page_offset; - - status = uvm_push_begin_acquire(gpu->channel_manager, - UVM_CHANNEL_TYPE_GPU_TO_CPU, - &va_block->tracker, - &push, - "Direct read from [0x%llx, 0x%llx)", - src, - src + size); - if (status != NV_OK) - return status; - - gpu->parent->ce_hal->memcopy(&push, dst_gpu_address, src_gpu_address, size); + src_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), gpu); + src_gpu_address.address += page_offset; - return uvm_push_end_and_wait(&push); + return va_block_read_gpu_to_cpu(va_block, dst_mem, gpu, src_gpu_address, src, size); + } } // Deferred work item reestablishing accessed by mappings after eviction. On diff --git a/kernel-open/nvidia-uvm/uvm_va_block.h b/kernel-open/nvidia-uvm/uvm_va_block.h index a7d5730f87..a13a4151be 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.h +++ b/kernel-open/nvidia-uvm/uvm_va_block.h @@ -459,14 +459,12 @@ struct uvm_va_block_struct // The MMU notifier is registered per va_block. struct mmu_interval_notifier notifier; - // Wait queue for GPU atomic operations to system memory. - struct wait_queue_head atomic_waitq; - - // Mask of pages being migrated to system memory for GPU atomic access. - // It is used so other threads don't try to migrate those pages while - // make_device_exclusive_range() is called without holding the va_block - // lock. - uvm_page_mask_t atomic_busy; + // This is used to serialize migrations between CPU and GPU while + // allowing the va_block lock to be dropped. + // This must be acquired before locking the va_block lock if the + // critical section can change the residency state. + // Do not access directly, use the uvm_hmm_migrate_*() routines. + uvm_mutex_t migrate_lock; // Sequence number to tell if any changes were made to the va_block // while not holding the block lock and calling hmm_range_fault(). @@ -1805,6 +1803,11 @@ static bool uvm_page_mask_subset(const uvm_page_mask_t *subset, const uvm_page_m return bitmap_subset(subset->bitmap, mask->bitmap, PAGES_PER_UVM_VA_BLOCK); } +static bool uvm_page_mask_equal(const uvm_page_mask_t *mask_in1, const uvm_page_mask_t *mask_in2) +{ + return bitmap_equal(mask_in1->bitmap, mask_in2->bitmap, PAGES_PER_UVM_VA_BLOCK); +} + static bool uvm_page_mask_init_from_region(uvm_page_mask_t *mask_out, uvm_va_block_region_t region, const uvm_page_mask_t *mask_in) @@ -1991,6 +1994,23 @@ static NvU64 uvm_reverse_map_end(const uvm_reverse_map_t *reverse_map) #define for_each_va_block_page(page_index, va_block) \ for_each_va_block_page_in_region((page_index), uvm_va_block_region_from_block(va_block)) +// Return the first vma intersecting the region [start, va_block->end] +// or NULL if no such vma exists. Also returns the region covered by +// the vma within the va_block. +struct vm_area_struct *uvm_va_block_find_vma_region(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 start, + uvm_va_block_region_t *region); + +// Iterate over all vma regions covered by a va_block +#define for_each_va_block_vma_region(va_block, mm, vma, region) \ + for (vma = uvm_va_block_find_vma_region((va_block), (mm), (va_block)->start, (region)); \ + (vma); \ + vma = uvm_va_block_find_vma_region((va_block), \ + (mm), \ + uvm_va_block_region_end((va_block), *(region)) + 1, \ + (region))) + // Return the block region covered by the given chunk size. page_index must be // any page within the block known to be covered by the chunk. static uvm_va_block_region_t uvm_va_block_chunk_region(uvm_va_block_t *block, diff --git a/kernel-open/nvidia-uvm/uvm_va_block_types.h b/kernel-open/nvidia-uvm/uvm_va_block_types.h index 29bdda4afd..4014df809a 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block_types.h +++ b/kernel-open/nvidia-uvm/uvm_va_block_types.h @@ -247,6 +247,13 @@ typedef struct struct page *pages[PAGES_PER_UVM_VA_BLOCK]; }; + // This flag indicates that at least one page in range being migrated + // or process for a GPU fault (i.e, faulted or prefetched), then + // the whole range will be migrated or remote mapped to system memory. + // TODO: Bug 4050579: Remove this when swap cached pages can be + // migrated. + bool swap_cached; + // Cached VMA pointer. This is only valid while holding the mmap_lock. struct vm_area_struct *vma; diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.h b/kernel-open/nvidia-uvm/uvm_va_policy.h index ab72a75e4b..9fac2f71d0 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.h +++ b/kernel-open/nvidia-uvm/uvm_va_policy.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2022 NVIDIA Corporation + Copyright (c) 2022-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -53,7 +53,7 @@ typedef enum // The VA range is determined from either the uvm_va_range_t for managed // allocations or the uvm_va_policy_node_t for HMM allocations. // -typedef struct uvm_va_policy_struct +struct uvm_va_policy_struct { // Read duplication policy for this VA range (unset, enabled, or disabled). uvm_read_duplication_policy_t read_duplication; @@ -66,7 +66,7 @@ typedef struct uvm_va_policy_struct // their page tables updated to access the (possibly remote) pages. uvm_processor_mask_t accessed_by; -} uvm_va_policy_t; +}; // Policy nodes are used for storing policies in HMM va_blocks. // The va_block lock protects the tree so that invalidation callbacks can diff --git a/kernel-open/nvidia-uvm/uvm_va_range.c b/kernel-open/nvidia-uvm/uvm_va_range.c index 0f3435745f..9378d5ac6e 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.c +++ b/kernel-open/nvidia-uvm/uvm_va_range.c @@ -31,6 +31,7 @@ #include "uvm_kvmalloc.h" #include "uvm_map_external.h" #include "uvm_perf_thrashing.h" +#include "uvm_conf_computing.h" #include "nv_uvm_interface.h" static struct kmem_cache *g_uvm_va_range_cache __read_mostly; @@ -723,7 +724,10 @@ static void va_range_remove_gpu_va_space_semaphore_pool(uvm_va_range_t *va_range { UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_SEMAPHORE_POOL); - uvm_mem_unmap_gpu_user(va_range->semaphore_pool.mem, gpu); + if (uvm_conf_computing_mode_enabled(gpu) && (va_range->semaphore_pool.mem->dma_owner == gpu)) + uvm_va_range_destroy(va_range, NULL); + else + uvm_mem_unmap_gpu_user(va_range->semaphore_pool.mem, gpu); } void uvm_va_range_remove_gpu_va_space(uvm_va_range_t *va_range, @@ -1192,13 +1196,6 @@ NV_STATUS uvm_va_range_split(uvm_va_range_t *existing_va_range, } -static inline uvm_va_range_t *uvm_va_range_container(uvm_range_tree_node_t *node) -{ - if (!node) - return NULL; - return container_of(node, uvm_va_range_t, node); -} - uvm_va_range_t *uvm_va_range_find(uvm_va_space_t *va_space, NvU64 addr) { uvm_assert_rwsem_locked(&va_space->lock); diff --git a/kernel-open/nvidia-uvm/uvm_va_range.h b/kernel-open/nvidia-uvm/uvm_va_range.h index 3c4088454c..d76f9eef44 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.h +++ b/kernel-open/nvidia-uvm/uvm_va_range.h @@ -537,6 +537,13 @@ NV_STATUS uvm_va_range_split(uvm_va_range_t *existing_va_range, // TODO: Bug 1707562: Merge va ranges +static uvm_va_range_t *uvm_va_range_container(uvm_range_tree_node_t *node) +{ + if (!node) + return NULL; + return container_of(node, uvm_va_range_t, node); +} + // Returns the va_range containing addr, if any uvm_va_range_t *uvm_va_range_find(uvm_va_space_t *va_space, NvU64 addr); diff --git a/kernel-open/nvidia-uvm/uvm_va_space.c b/kernel-open/nvidia-uvm/uvm_va_space.c index c9a43056ef..4fd6b56f64 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.c +++ b/kernel-open/nvidia-uvm/uvm_va_space.c @@ -171,8 +171,8 @@ NV_STATUS uvm_va_space_create(struct address_space *mapping, uvm_va_space_t **va return NV_ERR_NO_MEMORY; if (flags & ~UVM_INIT_FLAGS_MASK) { - uvm_kvfree(va_space); - return NV_ERR_INVALID_ARGUMENT; + uvm_kvfree(va_space); + return NV_ERR_INVALID_ARGUMENT; } uvm_init_rwsem(&va_space->lock, UVM_LOCK_ORDER_VA_SPACE); @@ -262,6 +262,7 @@ NV_STATUS uvm_va_space_create(struct address_space *mapping, uvm_va_space_t **va uvm_perf_destroy_va_space_events(&va_space->perf_events); uvm_va_space_up_write(va_space); uvm_up_write_mmap_lock(current->mm); + // See the comment in uvm_va_space_mm_unregister() for why this has to be // called after releasing the locks. uvm_va_space_mm_unregister(va_space); @@ -366,6 +367,11 @@ static void unregister_gpu(uvm_va_space_t *va_space, } } + if (va_space->gpu_unregister_dma_buffer[uvm_id_gpu_index(gpu->id)]) { + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, + va_space->gpu_unregister_dma_buffer[uvm_id_gpu_index(gpu->id)], + &va_space->gpu_unregister_dma_buffer[uvm_id_gpu_index(gpu->id)]->tracker); + } va_space_check_processors_masks(va_space); } @@ -412,6 +418,15 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) uvm_global_processor_mask_t retained_gpus; LIST_HEAD(deferred_free_list); + // Normally we'd expect this to happen as part of uvm_mm_release() + // but if userspace never initialized uvm_mm_fd that won't happen. + // We don't have to take the va_space_mm spinlock and update state + // here because we know no other thread can be in or subsequently + // call uvm_api_mm_initialize successfully because the UVM + // file-descriptor has been released. + if (va_space->va_space_mm.state == UVM_VA_SPACE_MM_STATE_UNINITIALIZED) + uvm_va_space_mm_unregister(va_space); + // Remove the VA space from the global list before we start tearing things // down so other threads can't see the VA space in a partially-valid state. uvm_mutex_lock(&g_uvm_global.va_spaces.lock); @@ -517,17 +532,8 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) uvm_deferred_free_object_list(&deferred_free_list); - // Remove the mm_struct association on this VA space, if any. This may - // invoke uvm_va_space_mm_shutdown(), which in turn will disable all - // channels and wait for any retainers to finish, so it has to be done - // outside of the VA space lock. - // - // Since we must already handle mm shutdown being called at any point prior - // to this call, this call can be made at any point in - // uvm_va_space_destroy(). It's beneficial to do it late after doing all - // deferred frees for GPU VA spaces and channels, because then - // uvm_va_space_mm_shutdown() will have minimal work to do. - uvm_va_space_mm_unregister(va_space); + // MM FD teardown should already have destroyed va_space_mm + UVM_ASSERT(!uvm_va_space_mm_alive(&va_space->va_space_mm)); uvm_mutex_lock(&g_uvm_global.global_lock); @@ -684,12 +690,9 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, goto done; } - // Mixing Volta and Pascal GPUs is not supported on P9 systems. + // Mixing coherent and non-coherent GPUs is not supported for_each_va_space_gpu(other_gpu, va_space) { - if ((gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_2 && - other_gpu->parent->sysmem_link < UVM_GPU_LINK_NVLINK_2) || - (gpu->parent->sysmem_link < UVM_GPU_LINK_NVLINK_2 && - other_gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_2)) { + if (uvm_gpu_is_coherent(gpu->parent) != uvm_gpu_is_coherent(other_gpu->parent)) { status = NV_ERR_INVALID_DEVICE; goto done; } @@ -701,6 +704,17 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, goto done; } + if (uvm_conf_computing_mode_enabled(gpu)) { + NvU32 gpu_index = uvm_id_gpu_index(gpu->id); + status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, + &va_space->gpu_unregister_dma_buffer[gpu_index], + NULL); + if (status != NV_OK) + goto done; + + gpu_can_access_sysmem = false; + } + uvm_processor_mask_set(&va_space->registered_gpus, gpu->id); va_space->registered_gpus_table[uvm_id_gpu_index(gpu->id)] = gpu; @@ -713,15 +727,16 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, // All GPUs have native atomics on their own memory processor_mask_array_set(va_space->has_native_atomics, gpu->id, gpu->id); - if (gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_1) { + // TODO: Bug 3252572: Support the new link type UVM_GPU_LINK_C2C + if (gpu->parent->system_bus.link >= UVM_GPU_LINK_NVLINK_1) { processor_mask_array_set(va_space->has_nvlink, gpu->id, UVM_ID_CPU); processor_mask_array_set(va_space->has_nvlink, UVM_ID_CPU, gpu->id); } - if (gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_2) { + if (uvm_gpu_is_coherent(gpu->parent)) { processor_mask_array_set(va_space->has_native_atomics, gpu->id, UVM_ID_CPU); - if (gpu->parent->numa_info.enabled) { + if (gpu->mem_info.numa.enabled) { processor_mask_array_set(va_space->can_access, UVM_ID_CPU, gpu->id); processor_mask_array_set(va_space->accessible_from, gpu->id, UVM_ID_CPU); processor_mask_array_set(va_space->has_native_atomics, UVM_ID_CPU, gpu->id); @@ -777,9 +792,9 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, goto cleanup; } - if (gpu->parent->numa_info.enabled) { + if (gpu->mem_info.numa.enabled) { *numa_enabled = NV_TRUE; - *numa_node_id = (NvS32)uvm_gpu_numa_info(gpu)->node_id; + *numa_node_id = (NvS32)uvm_gpu_numa_node(gpu); } else { *numa_enabled = NV_FALSE; @@ -987,6 +1002,7 @@ static NV_STATUS enable_peers(uvm_va_space_t *va_space, uvm_gpu_t *gpu0, uvm_gpu return NV_ERR_NOT_COMPATIBLE; } + // TODO: Bug 3848497: Disable GPU Peer Mapping when HCC is enabled processor_mask_array_set(va_space->can_access, gpu0->id, gpu1->id); processor_mask_array_set(va_space->can_access, gpu1->id, gpu0->id); processor_mask_array_set(va_space->accessible_from, gpu0->id, gpu1->id); @@ -1012,8 +1028,8 @@ static NV_STATUS enable_peers(uvm_va_space_t *va_space, uvm_gpu_t *gpu0, uvm_gpu if (peer_caps->is_indirect_peer) { UVM_ASSERT(peer_caps->link_type >= UVM_GPU_LINK_NVLINK_2); - UVM_ASSERT(gpu0->parent->numa_info.enabled); - UVM_ASSERT(gpu1->parent->numa_info.enabled); + UVM_ASSERT(gpu0->mem_info.numa.enabled); + UVM_ASSERT(gpu1->mem_info.numa.enabled); processor_mask_array_set(va_space->indirect_peers, gpu0->id, gpu1->id); processor_mask_array_set(va_space->indirect_peers, gpu1->id, gpu0->id); @@ -1411,6 +1427,10 @@ NV_STATUS uvm_va_space_register_gpu_va_space(uvm_va_space_t *va_space, return NV_ERR_INVALID_DEVICE; mm = uvm_va_space_mm_or_current_retain(va_space); + if (!mm) { + status = NV_ERR_PAGE_TABLE_NOT_AVAIL; + goto error_gpu_release; + } status = create_gpu_va_space(gpu, va_space, user_rm_va_space, &gpu_va_space); if (status != NV_OK) @@ -2200,9 +2220,24 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, uvm_tools_record_throttling_end(va_space, fault_addr, UVM_ID_CPU); if (is_hmm) { - status = uvm_hmm_va_block_cpu_find(va_space, service_context, vmf, &va_block); + // Note that normally we should find a va_block for the faulting + // address because the block had to be created when migrating a + // page to the GPU and a device private PTE inserted into the CPU + // page tables in order for migrate_to_ram() to be called. Not + // finding it means the PTE was remapped to a different virtual + // address with mremap() so create a new va_block if needed. + status = uvm_hmm_va_block_find_create(va_space, + fault_addr, + &service_context->block_context, + &va_block); if (status != NV_OK) break; + + status = uvm_hmm_migrate_begin(va_block); + if (status != NV_OK) + break; + + service_context->cpu_fault.vmf = vmf; } else { status = uvm_va_block_find_create_managed(va_space, fault_addr, &va_block); @@ -2219,10 +2254,10 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, status = uvm_va_block_cpu_fault(va_block, fault_addr, is_write, service_context); if (is_hmm) - uvm_hmm_cpu_fault_finish(service_context); + uvm_hmm_migrate_finish(va_block); } while (status == NV_WARN_MORE_PROCESSING_REQUIRED); - if (status != NV_OK) { + if (status != NV_OK && !(is_hmm && status == NV_ERR_BUSY_RETRY)) { UvmEventFatalReason reason; reason = uvm_tools_status_to_fatal_fault_reason(status); diff --git a/kernel-open/nvidia-uvm/uvm_va_space.h b/kernel-open/nvidia-uvm/uvm_va_space.h index fe39dbeb59..1962ada985 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.h +++ b/kernel-open/nvidia-uvm/uvm_va_space.h @@ -43,6 +43,7 @@ #include "uvm_test_ioctl.h" #include "uvm_ats.h" #include "uvm_va_space_mm.h" +#include "uvm_conf_computing.h" // uvm_deferred_free_object provides a mechanism for building and later freeing // a list of objects which are owned by a VA space, but can't be freed while the @@ -278,6 +279,11 @@ struct uvm_va_space_struct // stored in the VA space to avoid taking the global lock. uvm_cpu_gpu_affinity_t gpu_cpu_numa_affinity[UVM_ID_MAX_GPUS]; + // Unregistering a GPU may trigger memory eviction from the GPU to the CPU. + // This must happen without allocation, thus, a buffer is preallocated + // at GPU register and freed at GPU unregister. + uvm_conf_computing_dma_buffer_t *gpu_unregister_dma_buffer[UVM_ID_MAX_GPUS]; + // Array of GPU VA spaces uvm_gpu_va_space_t *gpu_va_spaces[UVM_ID_MAX_GPUS]; @@ -772,9 +778,7 @@ static uvm_gpu_t *uvm_va_space_find_gpu_with_memory_node_id(uvm_va_space_t *va_s return NULL; for_each_va_space_gpu(gpu, va_space) { - UVM_ASSERT(gpu->parent->numa_info.enabled); - - if (uvm_gpu_numa_info(gpu)->node_id == node_id) + if (uvm_gpu_numa_node(gpu) == node_id) return gpu; } diff --git a/kernel-open/nvidia-uvm/uvm_va_space_mm.c b/kernel-open/nvidia-uvm/uvm_va_space_mm.c index 5d038d55c5..35e92df5ec 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space_mm.c +++ b/kernel-open/nvidia-uvm/uvm_va_space_mm.c @@ -30,78 +30,62 @@ #include "uvm_test.h" #include "uvm_test_ioctl.h" -#if defined(NV_LINUX_SCHED_MM_H_PRESENT) -#include -#elif defined(NV_LINUX_SCHED_H_PRESENT) -#include -#endif - // // This comment block describes some implementation rationale. See the header // for the API descriptions. // // ========================= Retain count vs mm_users ========================== // -// We use two methods to guarantee the mm is available and won't be destroyed. +// To guarantee the mm is available and won't be destroyed we require +// userspace to open a second file descriptor (uvm_mm_fd) and +// initialize it with uvm_api_mm_initialize(). During initialization +// we take a mm_users reference to ensure the mm remains valid until +// the file descriptor is closed. // -// On the call paths where mmput() can be called, we call -// uvm_va_space_mm_or_current_retain() which calls mmget_not_zero(). This -// prevents mm teardown and avoids races with uvm_va_space_mm_shutdown() since -// it prevents mmput() -> __mmput() -> exit_mmap() -> mmu_notifier_release() -> -// uvm_va_space_mm_shutdown() until uvm_va_space_mm_or_current_release(), and -// we guarantee that we can't call uvm_va_space_mm_unregister() -> -// mmu_notifier_unregister() -> uvm_va_space_mm_shutdown() path when someone is -// about to call uvm_va_space_mm_or_current_retain(). -// Kernel calls like mmu_interval_notifier_insert() require mm_users to be -// greater than 0. In general, these are the ioctl paths. +// To ensure userspace can't close the file descriptor and drop the +// mm_users refcount while it is in use threads must call either +// uvm_va_space_mm_retain() or uvm_va_space_mm_or_current_retain() to +// increment the retained count. This also checks that userspace has +// initialized the uvm_mm_fd and therefore holds a valid pagetable +// pin. // -// On the replayable GPU fault handling path, we need the mm to be able to -// service faults in the window when mm_users == 0 but mmu_notifier_release() -// hasn't yet been called. We can't call mmput() because it may result in -// exit_mmap(), which could result in RM calls and VA space destroy. Those need -// to wait for the GPU fault handler to finish, so on that path we use an -// internal retained reference count and wait queue. When the mm is disabled -// via mmu_notifier_release(), we use the wait queue to wait for the reference -// count to go to 0. -// We also use this path for older Linux kernels where mm_users > 0 isn't -// required. +// Closing uvm_mm_fd will call uvm_va_space_mm_shutdown() prior to +// mmput() which ensures there are no active users of the mm. This +// indirection is required because not all threads can call mmput() +// directly. In particular the replayable GPU fault handling path +// can't call mmput() because it may result in exit_mmap() which could +// result in RM calls and VA space destroy and those need to wait for +// the GPU fault handler to finish. // // ============================ Handling mm teardown =========================== // -// mmu_notifiers call the mm release callback both when the mm is really getting -// shut down, and whenever mmu_notifier_unregister is called. This has several -// consequences, including that these two paths can race. If they do race, they -// wait for each other to finish (real teardown of the mm won't start until the -// mmu_notifier_unregister's callback has returned, and mmu_notifier_unregister -// won't return until the mm release callback has returned). +// When the process is exiting we will get notified either via an +// explict close of uvm_mm_fd or implicitly as part of +// exit_files(). We are guaranteed to get this call because we don't +// allow mmap on uvm_mm_fd, and the userspace pagetables (mm_users) +// are guaranteed to exist because we hold a mm_users refcount +// which is released as part of file close. +// +// This allows any outstanding GPU faults to be processed. To prevent +// new faults occurring uvm_va_space_mm_shutdown() is called to stop +// all GPU memory accesses to the mm. Once all GPU memory has been +// stopped no new retainers of the va_space will be allowed and the +// mm_users reference will be dropped, potentially tearing down the mm +// and associated pagetables. // -// When the mm is really getting torn down, uvm_va_space_mm_shutdown is expected -// to stop all GPU memory accesses to that mm and stop servicing faults in that -// mm. This essentially shuts down the VA space for new work. The VA space -// object remains valid for most teardown ioctls until the file is closed, -// because it's legal for the associated process to die then for another process -// with a reference on the file to perform the unregisters or associated ioctls. -// This is particularly true for tools users. +// This essentially shuts down the VA space for new work. The VA space +// object remains valid for most teardown ioctls until the file is +// closed, because it's legal for the associated process to die then +// for another process with a reference on the file to perform the +// unregisters or associated ioctls. This is particularly true for +// tools users. // // An exception to the above is UvmUnregisterChannel. Since channels are // completely removed from the VA space on mm teardown, later channel // unregisters will fail to find the handles and will return an error. // -// The UVM driver will only call mmu_notifier_unregister during VA space destroy -// (file close). -// -// Here is a table of the various teardown scenarios: -// -// Can race with -// Scenario mm teardown -// ----------------------------------------------------------------------------- -// 1) Process exit (mm teardown, file open) - -// 2) Explicit file close in original mm No -// 3) Explicit file close in different mm Yes -// 4) Implicit file close (exit) in original mm No -// 5) Implicit file close (exit) in different mm Yes -// -// At a high level, the sequence of operations to perform during mm teardown is: +// At a high level, the sequence of operations to perform prior to mm +// teardown is: // // 1) Stop all channels // - Prevents new faults and accesses on non-MPS @@ -121,7 +105,7 @@ // the case of MPS, cancel real faults after. // 4) UnsetPageDir // - Prevents new accesses on MPS -// 5) Mark the va_space_mm as dead +// 5) Mark the va_space_mm as released // - Prevents new retainers from using the mm. There won't be any more on // the fault handling paths, but there could be others in worker threads. // @@ -170,7 +154,7 @@ // // ============================================================================= -#define UVM_VA_SPACE_MM_SHUTDOWN_DELAY_MAX_MS 100 +static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space); static int uvm_enable_va_space_mm = 1; module_param(uvm_enable_va_space_mm, int, S_IRUGO); @@ -195,22 +179,7 @@ bool uvm_va_space_mm_enabled(uvm_va_space_t *va_space) return uvm_va_space_mm_enabled_system(); } -static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space); - -#if !defined(NV_MMGET_NOT_ZERO_PRESENT) -static bool mmget_not_zero(struct mm_struct *mm) -{ - return atomic_inc_not_zero(&mm->mm_users); -} -#endif - #if UVM_CAN_USE_MMU_NOTIFIERS() - - static void uvm_mmput(struct mm_struct *mm) - { - mmput(mm); - } - static uvm_va_space_t *get_va_space(struct mmu_notifier *mn) { // This may be called without a thread context present, so be careful @@ -218,11 +187,6 @@ static bool mmget_not_zero(struct mm_struct *mm) return container_of(mn, uvm_va_space_t, va_space_mm.mmu_notifier); } - static void uvm_mmu_notifier_release(struct mmu_notifier *mn, struct mm_struct *mm) - { - UVM_ENTRY_VOID(uvm_va_space_mm_shutdown(get_va_space(mn))); - } - static void uvm_mmu_notifier_invalidate_range_ats(struct mmu_notifier *mn, struct mm_struct *mm, unsigned long start, @@ -249,14 +213,8 @@ static bool mmget_not_zero(struct mm_struct *mm) UVM_ENTRY_VOID(uvm_ats_invalidate(get_va_space(mn), start, end)); } - static struct mmu_notifier_ops uvm_mmu_notifier_ops_release = - { - .release = uvm_mmu_notifier_release, - }; - static struct mmu_notifier_ops uvm_mmu_notifier_ops_ats = { - .release = uvm_mmu_notifier_release, .invalidate_range = uvm_mmu_notifier_invalidate_range_ats, }; @@ -265,11 +223,7 @@ static bool mmget_not_zero(struct mm_struct *mm) UVM_ASSERT(va_space_mm->mm); uvm_assert_mmap_lock_locked_write(va_space_mm->mm); - if (UVM_ATS_IBM_SUPPORTED_IN_DRIVER() && g_uvm_global.ats.enabled) - va_space_mm->mmu_notifier.ops = &uvm_mmu_notifier_ops_ats; - else - va_space_mm->mmu_notifier.ops = &uvm_mmu_notifier_ops_release; - + va_space_mm->mmu_notifier.ops = &uvm_mmu_notifier_ops_ats; return __mmu_notifier_register(&va_space_mm->mmu_notifier, va_space_mm->mm); } @@ -278,11 +232,6 @@ static bool mmget_not_zero(struct mm_struct *mm) mmu_notifier_unregister(&va_space_mm->mmu_notifier, va_space_mm->mm); } #else - static void uvm_mmput(struct mm_struct *mm) - { - UVM_ASSERT(0); - } - static int uvm_mmu_notifier_register(uvm_va_space_mm_t *va_space_mm) { UVM_ASSERT(0); @@ -303,26 +252,28 @@ NV_STATUS uvm_va_space_mm_register(uvm_va_space_t *va_space) uvm_assert_mmap_lock_locked_write(current->mm); uvm_assert_rwsem_locked_write(&va_space->lock); + va_space_mm->state = UVM_VA_SPACE_MM_STATE_UNINITIALIZED; + if (!uvm_va_space_mm_enabled(va_space)) return NV_OK; UVM_ASSERT(!va_space_mm->mm); va_space_mm->mm = current->mm; + uvm_mmgrab(va_space_mm->mm); // We must be prepared to handle callbacks as soon as we make this call, // except for ->release() which can't be called since the mm belongs to // current. - ret = uvm_mmu_notifier_register(va_space_mm); - if (ret) { - // Inform uvm_va_space_mm_unregister() that it has nothing to do. - va_space_mm->mm = NULL; - return errno_to_nv_status(ret); + if (UVM_ATS_IBM_SUPPORTED_IN_DRIVER() && g_uvm_global.ats.enabled) { + ret = uvm_mmu_notifier_register(va_space_mm); + if (ret) { + // Inform uvm_va_space_mm_unregister() that it has nothing to do. + uvm_mmdrop(va_space_mm->mm); + va_space_mm->mm = NULL; + return errno_to_nv_status(ret); + } } - uvm_spin_lock(&va_space_mm->lock); - va_space_mm->alive = true; - uvm_spin_unlock(&va_space_mm->lock); - return NV_OK; } @@ -330,25 +281,35 @@ void uvm_va_space_mm_unregister(uvm_va_space_t *va_space) { uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - // We can't hold the VA space lock or mmap_lock across this function since - // mmu_notifier_unregister() may trigger uvm_va_space_mm_shutdown(), which - // takes those locks and also waits for other threads which may take those - // locks. + // We can't hold the VA space lock or mmap_lock because + // uvm_va_space_mm_shutdown() waits for retainers which may take + // these locks. uvm_assert_unlocked_order(UVM_LOCK_ORDER_MMAP_LOCK); uvm_assert_unlocked_order(UVM_LOCK_ORDER_VA_SPACE); + uvm_va_space_mm_shutdown(va_space); + UVM_ASSERT(va_space_mm->retained_count == 0); + + // Only happens if uvm_va_space_mm_register() fails if (!va_space_mm->mm) return; - UVM_ASSERT(uvm_va_space_mm_enabled(va_space)); - uvm_mmu_notifier_unregister(va_space_mm); - - // We're guaranteed that upon return from mmu_notifier_unregister(), - // uvm_va_space_mm_shutdown() will have been called (though perhaps not by - // this thread). Therefore all retainers have been flushed. - UVM_ASSERT(!va_space_mm->alive); - UVM_ASSERT(va_space_mm->retained_count == 0); - va_space_mm->mm = NULL; + // At this point the mm is still valid because uvm_mm_release() + // hasn't yet called mmput(). uvm_hmm_va_space_destroy() will kill + // all the va_blocks along with any associated gpu_chunks, so we + // need to make sure these chunks are free. However freeing them + // requires a valid mm so we can call migrate_vma_setup(), so we + // do that here. + // TODO: Bug 3902536: [UVM-HMM] add code to migrate GPU memory + // without having a va_block + if (uvm_hmm_is_enabled(va_space)) + uvm_hmm_evict_va_blocks(va_space); + + if (uvm_va_space_mm_enabled(va_space)) { + if (UVM_ATS_IBM_SUPPORTED_IN_DRIVER() && g_uvm_global.ats.enabled) + uvm_mmu_notifier_unregister(va_space_mm); + uvm_mmdrop(va_space_mm->mm); + } } struct mm_struct *uvm_va_space_mm_retain(uvm_va_space_t *va_space) @@ -361,11 +322,19 @@ struct mm_struct *uvm_va_space_mm_retain(uvm_va_space_t *va_space) uvm_spin_lock(&va_space_mm->lock); - if (va_space_mm->alive) { - ++va_space_mm->retained_count; - mm = va_space_mm->mm; - UVM_ASSERT(mm); - } + if (!uvm_va_space_mm_alive(va_space_mm)) + goto out; + + ++va_space_mm->retained_count; + + mm = va_space_mm->mm; + UVM_ASSERT(mm); + +out: + + // uvm_api_mm_init() holds a reference + if (mm) + UVM_ASSERT(atomic_read(&mm->mm_users) > 0); uvm_spin_unlock(&va_space_mm->lock); @@ -374,8 +343,6 @@ struct mm_struct *uvm_va_space_mm_retain(uvm_va_space_t *va_space) struct mm_struct *uvm_va_space_mm_or_current_retain(uvm_va_space_t *va_space) { - uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - // We should only attempt to use current->mm from a user thread UVM_ASSERT(!(current->flags & PF_KTHREAD)); @@ -384,19 +351,22 @@ struct mm_struct *uvm_va_space_mm_or_current_retain(uvm_va_space_t *va_space) if (!current->mm) return NULL; - // If the va_space_mm matches current->mm then it would be safe but sub- - // optimal to call mmget_not_zero(). current->mm is always valid to - // use when non-NULL so there is no need to retain it. - if (!uvm_va_space_mm_enabled(va_space) || va_space_mm->mm == current->mm) + // If !uvm_va_space_mm_enabled() we use current->mm on the ioctl + // paths. In that case we don't need to mmget(current->mm) because + // the current thread mm is always valid. On + // uvm_va_space_mm_enabled() systems we skip trying to retain the + // mm if it is current->mm because userspace may not have + // initialised the mm fd but UVM callers on the ioctl path still + // assume retaining current->mm will succeed. + if (!uvm_va_space_mm_enabled(va_space)) return current->mm; - return mmget_not_zero(va_space_mm->mm) ? va_space_mm->mm : NULL; + return uvm_va_space_mm_retain(va_space); } void uvm_va_space_mm_release(uvm_va_space_t *va_space) { uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - bool do_wake = false; UVM_ASSERT(uvm_va_space_mm_enabled(va_space)); @@ -409,84 +379,26 @@ void uvm_va_space_mm_release(uvm_va_space_t *va_space) --va_space_mm->retained_count; // If we're the last retainer on a dead mm, signal any potential waiters - if (va_space_mm->retained_count == 0 && !va_space_mm->alive) - do_wake = true; - - uvm_spin_unlock(&va_space_mm->lock); + if (va_space_mm->retained_count == 0 && !uvm_va_space_mm_alive(va_space_mm)) { + uvm_spin_unlock(&va_space_mm->lock); - // There could be multiple threads in uvm_va_space_mm_shutdown() waiting on - // us, so we have to wake up all waiters. - if (do_wake) - wake_up_all(&va_space_mm->last_retainer_wait_queue); + // There could be a thread in uvm_va_space_mm_shutdown() + // waiting on us, so wake it up. + wake_up(&va_space_mm->last_retainer_wait_queue); + } + else { + uvm_spin_unlock(&va_space_mm->lock); + } } void uvm_va_space_mm_or_current_release(uvm_va_space_t *va_space, struct mm_struct *mm) { - // We can't hold the VA space lock or mmap_lock across this function since - // mmput() may trigger uvm_va_space_mm_shutdown(), which takes those locks - // and also waits for other threads which may take those locks. - uvm_assert_unlocked_order(UVM_LOCK_ORDER_MMAP_LOCK); - uvm_assert_unlocked_order(UVM_LOCK_ORDER_VA_SPACE); - - if (mm && mm != current->mm) - uvm_mmput(mm); -} - -static void uvm_va_space_mm_shutdown_delay(uvm_va_space_t *va_space) -{ - uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - NvU64 start_time; - int num_threads; - bool timed_out = false; - - if (!va_space_mm->test.delay_shutdown) + if (!uvm_va_space_mm_enabled(va_space) || !mm) return; - start_time = NV_GETTIME(); - - num_threads = atomic_inc_return(&va_space_mm->test.num_mm_shutdown_threads); - UVM_ASSERT(num_threads > 0); - - if (num_threads == 1) { - // Wait for another thread to arrive unless we time out - while (atomic_read(&va_space_mm->test.num_mm_shutdown_threads) == 1) { - if (NV_GETTIME() - start_time >= 1000*1000*UVM_VA_SPACE_MM_SHUTDOWN_DELAY_MAX_MS) { - timed_out = true; - break; - } - } - - if (va_space_mm->test.verbose) - UVM_TEST_PRINT("Multiple threads: %d\n", !timed_out); - } - - // No need to decrement num_mm_shutdown_threads since this va_space_mm is - // being shut down. + uvm_va_space_mm_release(va_space); } -// Handles the va_space's mm being torn down while the VA space still exists. -// This function won't return until all in-flight retainers have called -// uvm_va_space_mm_release(). Subsequent calls to uvm_va_space_mm_retain() will -// return NULL. -// -// uvm_va_space_mm_unregister() must still be called. It is guaranteed that -// uvm_va_space_mm_shutdown() will not be called after -// uvm_va_space_mm_unregister() returns, though they may execute concurrently. -// If so, uvm_va_space_mm_unregister() will not return until -// uvm_va_space_mm_shutdown() is done. -// -// After this call returns the VA space is essentially dead. GPUs cannot make -// any new memory accesses in registered GPU VA spaces, and no more GPU faults -// which are attributed to this VA space will arrive. Additionally, no more -// registration within the VA space is allowed (GPU, GPU VA space, or channel). -// -// The requirements for this callback are that, once we return, the GPU and -// driver are completely done using the associated mm_struct. This includes: -// -// 1) GPUs will not issue any more memory accesses under this mm -// 2) [ATS only] GPUs will not issue any more ATRs under this mm -// 3) The driver will not ask the kernel to service faults on this mm -// static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space) { uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; @@ -495,29 +407,6 @@ static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space) uvm_global_processor_mask_t gpus_to_flush; LIST_HEAD(deferred_free_list); - // The mm must not have been torn down completely yet, but it may have been - // marked as dead by a concurrent thread. - UVM_ASSERT(uvm_va_space_mm_enabled(va_space)); - UVM_ASSERT(va_space_mm->mm); - - // Inject a delay for testing if requested - uvm_va_space_mm_shutdown_delay(va_space); - - // There can be at most two threads here concurrently: - // - // 1) Thread A in process teardown of the original process - // - // 2) Thread B must be in the file close path of another process (either - // implicit or explicit), having already stopped all GPU accesses and - // having called uvm_va_space_mm_unregister. - // - // This corresponds to scenario #5 in the mm teardown block comment at the - // top of the file. We serialize between these threads with the VA space - // lock, but otherwise don't have any special handling: both threads will - // execute the full teardown sequence below. Also, remember that the threads - // won't return to their callers until both threads have returned from this - // function (following the rules for mmu_notifier_unregister). - uvm_va_space_down_write(va_space); // Prevent future registrations of any kind. We'll be iterating over all @@ -545,9 +434,9 @@ static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space) uvm_global_mask_retain(&gpus_to_flush); uvm_va_space_up_write(va_space); - // Flush the fault buffer on all GPUs. This will avoid spurious cancels - // of stale pending translated faults after we clear va_space_mm->alive - // later. + // Flush the fault buffer on all GPUs. This will avoid spurious + // cancels of stale pending translated faults after we set + // UVM_VA_SPACE_MM_STATE_RELEASED later. for_each_global_gpu_in_mask(gpu, &gpus_to_flush) uvm_gpu_fault_buffer_flush(gpu); @@ -593,7 +482,7 @@ static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space) // Now that there won't be any new GPU faults, prevent subsequent retainers // from accessing this mm. uvm_spin_lock(&va_space_mm->lock); - va_space_mm->alive = false; + va_space_mm->state = UVM_VA_SPACE_MM_STATE_RELEASED; uvm_spin_unlock(&va_space_mm->lock); // Finish channel destroy. This can be done at any point after detach as @@ -666,26 +555,6 @@ NV_STATUS uvm_test_va_space_mm_retain(UVM_TEST_VA_SPACE_MM_RETAIN_PARAMS *params return status; } -NV_STATUS uvm_test_va_space_mm_delay_shutdown(UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN_PARAMS *params, struct file *filp) -{ - uvm_va_space_t *va_space = uvm_va_space_get(filp); - uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; - NV_STATUS status = NV_ERR_PAGE_TABLE_NOT_AVAIL; - - uvm_va_space_down_write(va_space); - - if (uvm_va_space_mm_retain(va_space)) { - va_space_mm->test.delay_shutdown = true; - va_space_mm->test.verbose = params->verbose; - uvm_va_space_mm_release(va_space); - status = NV_OK; - } - - uvm_va_space_up_write(va_space); - - return status; -} - NV_STATUS uvm_test_va_space_mm_or_current_retain(UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN_PARAMS *params, struct file *filp) { @@ -704,13 +573,9 @@ NV_STATUS uvm_test_va_space_mm_or_current_retain(UVM_TEST_VA_SPACE_MM_OR_CURRENT status = NV_ERR_INVALID_ARGUMENT; } - if (status == NV_OK) { - if (params->sleep_us) + if (status == NV_OK && params->sleep_us) usleep_range(params->sleep_us, params->sleep_us + 1000); - params->mm_users = atomic_read(&mm->mm_users); - } - uvm_va_space_mm_or_current_release(va_space, mm); return status; diff --git a/kernel-open/nvidia-uvm/uvm_va_space_mm.h b/kernel-open/nvidia-uvm/uvm_va_space_mm.h index c0a4dc7bb2..9186f83138 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space_mm.h +++ b/kernel-open/nvidia-uvm/uvm_va_space_mm.h @@ -32,27 +32,50 @@ #include +#if defined(NV_LINUX_SCHED_MM_H_PRESENT) +#include +#elif defined(NV_LINUX_SCHED_H_PRESENT) +#include +#endif + +typedef enum +{ + // The va_space_mm has not yet been initialized by + // uvm_api_mm_initialize(). Only current->mm can be retained for + // !uvm_va_space_mm_enabled() VA spaces. + UVM_VA_SPACE_MM_STATE_UNINITIALIZED, + + // The va_space_mm has been initialized and if this is a + // uvm_va_space_mm_enabled() space CPU user space page tables are + // valid due to holding a mm_struct reference. However the GPU VA + // space may be in the process of being torn down. + UVM_VA_SPACE_MM_STATE_ALIVE, + + // The va_space_mm has been released. There is no longer any + // mm_struct associated with this va_space_mm and CPU page tables + // may have been released. GPU VA state has been destroyed. + UVM_VA_SPACE_MM_STATE_RELEASED, +} uvm_va_space_mm_state_t; + struct uvm_va_space_mm_struct { - // The mm currently associated with this VA space. Most callers shouldn't - // access this directly, but should instead use uvm_va_space_mm_retain()/ - // uvm_va_space_mm_release(). - // - // The pointer itself is valid between uvm_va_space_mm_register() and - // uvm_va_space_mm_unregister(), but should only be considered usable when - // retained or current. - struct mm_struct *mm; + // The mm currently associated with this VA space. Most callers shouldn't + // access this directly, but should instead use uvm_va_space_mm_retain()/ + // uvm_va_space_mm_release(). + // + // The pointer itself is valid when the va_space_mm state is + // UVM_VA_SPACE_MM_STATE_ALIVE, but should only be considered usable + // when retained or current. + struct mm_struct *mm; #if UVM_CAN_USE_MMU_NOTIFIERS() struct mmu_notifier mmu_notifier; #endif - // Lock protecting the alive and retained_count fields. + // Lock protecting the state and retained_count fields. uvm_spinlock_t lock; - // Whether the mm is usable. uvm_va_space_mm_register() marks the mm as - // alive and uvm_va_space_mm_shutdown() marks it as dead. - bool alive; + uvm_va_space_mm_state_t state; // Refcount for uvm_va_space_mm_retain()/uvm_va_space_mm_release() NvU32 retained_count; @@ -60,22 +83,13 @@ struct uvm_va_space_mm_struct // Wait queue for threads waiting for retainers to finish (retained_count // going to 0 when not alive). wait_queue_head_t last_retainer_wait_queue; - - // State which is only injected by test ioctls - struct - { - // Whether uvm_va_space_mm_shutdown() should do a timed wait for other - // threads to arrive. - bool delay_shutdown; - - bool verbose; - - // Number of threads which have called uvm_va_space_mm_shutdown(). Only - // used when delay_shutdown is true. - atomic_t num_mm_shutdown_threads; - } test; }; +static bool uvm_va_space_mm_alive(struct uvm_va_space_mm_struct *va_space_mm) +{ + return va_space_mm->state == UVM_VA_SPACE_MM_STATE_ALIVE; +} + // Whether the system can support creating an association between a VA space and // an mm. bool uvm_va_space_mm_enabled_system(void); @@ -94,18 +108,24 @@ bool uvm_va_space_mm_enabled(uvm_va_space_t *va_space); // Locking: mmap_lock and the VA space lock must both be held for write. NV_STATUS uvm_va_space_mm_register(uvm_va_space_t *va_space); -// De-associate the mm from the va_space. This function won't return until all -// in-flight retainers have called uvm_va_space_mm_release(). -// uvm_va_space_mm_retain() and friends must not be called after this returns. +// Handles the va_space's mm being torn down while the VA space still exists. +// This function won't return until all in-flight retainers have called +// uvm_va_space_mm_release(). Subsequent calls to uvm_va_space_mm_retain() will +// return NULL. +// +// After this call returns the VA space is essentially dead. GPUs cannot make +// any new memory accesses in registered GPU VA spaces, and no more GPU faults +// which are attributed to this VA space will arrive. Additionally, no more +// registration within the VA space is allowed (GPU, GPU VA space, or channel). +// +// The requirements for this call are that, once we return, the GPU and +// driver are completely done using the associated mm_struct. This includes: // -// This function may invoke uvm_va_space_mm_shutdown() so the caller must not -// hold either mmap_lock or the VA space lock. Since this API must provide the -// same guarantees as uvm_va_space_mm_shutdown(), the caller must also guarantee -// prior to calling this function that all GPUs in this VA space have stopped -// making accesses under this mm and will not be able to start again under that -// VA space. +// 1) GPUs will not issue any more memory accesses under this mm +// 2) [ATS only] GPUs will not issue any more ATRs under this mm +// 3) The driver will not ask the kernel to service faults on this mm // -// Locking: This function may take both mmap_lock and the VA space lock. +// Locking: This function will take both mmap_lock and the VA space lock. void uvm_va_space_mm_unregister(uvm_va_space_t *va_space); // Retains the current mm registered with this VA space. If no mm is currently @@ -114,26 +134,23 @@ void uvm_va_space_mm_unregister(uvm_va_space_t *va_space); // (locking mmap_lock, find_vma, get_user_pages, cgroup-accounted allocations, // etc) until uvm_va_space_mm_release() is called. // -// Please, note that a retained mm could have mm->users == 0. +// A retained mm is guaranteed to have mm->users >= 1. // // It is NOT necessary to hold the VA space lock when calling this function. struct mm_struct *uvm_va_space_mm_retain(uvm_va_space_t *va_space); -// Similar to uvm_va_space_mm_retain(), but falls back to returning current->mm -// when there is no mm registered with the VA space (that is, -// uvm_va_space_mm_enabled() would return false). This is both a convenience and -// an optimization of the common case in which current->mm == va_space_mm. -// uvm_va_space_mm_or_current_release() must be called to release the mm, and it -// must be called from the same thread which called +// Similar to uvm_va_space_mm_retain(), but falls back to returning +// current->mm when there is no mm registered with the VA space (that +// is, uvm_va_space_mm_enabled() would return false). +// uvm_va_space_mm_or_current_release() must be called to release the +// mm, and it must be called from the same thread which called // uvm_va_space_mm_or_current_retain(). // // If a non-NULL mm is returned, the guarantees described by -// uvm_va_space_mm_retain() apply. Unlike uvm_va_space_mm_retain() however, -// mm_users is guaranteed to be greater than 0 until -// uvm_va_space_mm_or_current_release(). -// If uvm_va_space_mm_enabled() is false, the caller is responsible for -// validating that the returned mm matches the desired mm before performing an -// operation such as vm_insert_page(). See uvm_va_range_vma_check(). +// uvm_va_space_mm_retain() apply. If uvm_va_space_mm_enabled() is +// false, the caller is responsible for validating that the returned +// mm matches the desired mm before performing an operation such as +// vm_insert_page(). See uvm_va_range_vma_check(). // // This should not be called from a kernel thread. struct mm_struct *uvm_va_space_mm_or_current_retain(uvm_va_space_t *va_space); @@ -185,8 +202,50 @@ static void uvm_va_space_mm_or_current_release_unlock(uvm_va_space_t *va_space, } } +#if !defined(NV_MMGET_NOT_ZERO_PRESENT) +static bool mmget_not_zero(struct mm_struct *mm) +{ + return atomic_inc_not_zero(&mm->mm_users); +} +#endif + +#if UVM_CAN_USE_MMU_NOTIFIERS() +static void uvm_mmput(struct mm_struct *mm) +{ + mmput(mm); +} + +static void uvm_mmgrab(struct mm_struct *mm) +{ +#if defined(NV_MMGRAB_PRESENT) + mmgrab(mm); +#else + atomic_inc(&mm->mm_count); +#endif +} + +static void uvm_mmdrop(struct mm_struct *mm) +{ + mmdrop(mm); +} +#else +static void uvm_mmput(struct mm_struct *mm) +{ + UVM_ASSERT(0); +} + +static void uvm_mmgrab(struct mm_struct *mm) +{ + UVM_ASSERT(0); +} + +static void uvm_mmdrop(struct mm_struct *mm) +{ + UVM_ASSERT(0); +} +#endif + NV_STATUS uvm_test_va_space_mm_retain(UVM_TEST_VA_SPACE_MM_RETAIN_PARAMS *params, struct file *filp); -NV_STATUS uvm_test_va_space_mm_delay_shutdown(UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN_PARAMS *params, struct file *filp); NV_STATUS uvm_test_va_space_mm_or_current_retain(UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN_PARAMS *params, struct file *filp); diff --git a/kernel-open/nvidia-uvm/uvm_volta.c b/kernel-open/nvidia-uvm/uvm_volta.c index 5fb96bb248..058449086e 100644 --- a/kernel-open/nvidia-uvm/uvm_volta.c +++ b/kernel-open/nvidia-uvm/uvm_volta.c @@ -46,11 +46,13 @@ void uvm_hal_volta_arch_init_properties(uvm_parent_gpu_t *parent_gpu) // A single top level PDE on Volta covers 128 TB and that's the minimum // size that can be used. parent_gpu->rm_va_base = 0; - parent_gpu->rm_va_size = 128ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB; - parent_gpu->uvm_mem_va_base = 384ull * 1024 * 1024 * 1024 * 1024; + parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->ce_phys_vidmem_write_supported = true; + parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_VIRTUAL; // Not all units on Volta support 49-bit addressing, including those which diff --git a/kernel-open/nvidia-uvm/uvm_volta_ce.c b/kernel-open/nvidia-uvm/uvm_volta_ce.c index 6fad6a7f57..d8b7e09545 100644 --- a/kernel-open/nvidia-uvm/uvm_volta_ce.c +++ b/kernel-open/nvidia-uvm/uvm_volta_ce.c @@ -113,6 +113,7 @@ void uvm_hal_volta_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_a NvU32 launch_dma_src_dst_type; NvU32 launch_dma_plc_mode; NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + NvU32 copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(push, dst, src); UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_is_valid(push, dst, src), "Memcopy validation failed in channel %s, GPU %s.\n", @@ -148,6 +149,7 @@ void uvm_hal_volta_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_a flush_value | launch_dma_src_dst_type | launch_dma_plc_mode | + copy_type_value | pipelined_value); pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); @@ -193,7 +195,7 @@ static void memset_common(uvm_push_t *push, uvm_gpu_address_t dst, size_t size, NvU32 launch_dma_plc_mode; NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); - UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, memset_element_size), + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, size, memset_element_size), "Memset validation failed in channel %s, GPU %s.\n", push->channel->name, uvm_gpu_name(gpu)); diff --git a/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c b/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c index 07ca09263f..993a605207 100644 --- a/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c +++ b/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -56,21 +56,29 @@ NvU32 uvm_hal_volta_fault_buffer_read_get(uvm_parent_gpu_t *parent_gpu) void uvm_hal_volta_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index) { NvU32 get = HWVALUE(_PFB_PRI_MMU, FAULT_BUFFER_GET, PTR, index); + UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults); // If HW has detected an overflow condition (PUT == GET - 1 and a fault has - // arrived, which is dropped due to no more space in the fault buffer), it will - // not deliver any more faults into the buffer until the overflow condition has - // been cleared. The overflow condition is cleared by updating the GET index to - // indicate space in the buffer and writing 1 to the OVERFLOW bit in GET. - // Unfortunately, this can not be done in the same write because it can collide - // with an arriving fault on the same cycle, resulting in the overflow condition - // being instantly reasserted. - // However, if the index is updated first and then the OVERFLOW bit is cleared - // such a collision will not cause a reassertion of the overflow condition. + // arrived, which is dropped due to no more space in the fault buffer), it + // will not deliver any more faults into the buffer until the overflow + // condition has been cleared. The overflow condition is cleared by + // updating the GET index to indicate space in the buffer and writing 1 to + // the OVERFLOW bit in GET. Unfortunately, this can not be done in the same + // write because it can collide with an arriving fault on the same cycle, + // resulting in the overflow condition being instantly reasserted. However, + // if the index is updated first and then the OVERFLOW bit is cleared such + // a collision will not cause a reassertion of the overflow condition. UVM_GPU_WRITE_ONCE(*parent_gpu->fault_buffer_info.rm_info.replayable.pFaultBufferGet, get); - // Clear the getptr_corrupted/overflow bits. + // Clearing GETPTR_CORRUPTED and OVERFLOW is not needed when GSP-RM owns + // the HW replayable fault buffer, because UVM does not write to the actual + // GET register; GSP-RM is responsible for clearing the bits in the real + // GET register. + if (!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) + return; + + // Clear the GETPTR_CORRUPTED and OVERFLOW bits. get |= HWCONST(_PFB_PRI_MMU, FAULT_BUFFER_GET, GETPTR_CORRUPTED, CLEAR) | HWCONST(_PFB_PRI_MMU, FAULT_BUFFER_GET, OVERFLOW, CLEAR); UVM_GPU_WRITE_ONCE(*parent_gpu->fault_buffer_info.rm_info.replayable.pFaultBufferGet, get); @@ -144,7 +152,7 @@ static bool is_fault_address_virtual(const NvU32 *fault_entry) return UVM_FAULT_ACCESS_TYPE_COUNT; } -static uvm_fault_type_t get_fault_type(const NvU32 *fault_entry) +uvm_fault_type_t uvm_hal_volta_fault_buffer_get_fault_type(const NvU32 *fault_entry) { NvU32 hw_fault_type_value = READ_HWVALUE_MW(fault_entry, C369, BUF_ENTRY, FAULT_TYPE); @@ -242,13 +250,10 @@ static void parse_fault_entry_common(uvm_parent_gpu_t *parent_gpu, NvU32 *fault_entry, uvm_fault_buffer_entry_t *buffer_entry) { - NV_STATUS status; NvU64 addr_hi, addr_lo; NvU64 timestamp_hi, timestamp_lo; bool replayable_fault_enabled; - status = NV_OK; - addr_hi = READ_HWVALUE_MW(fault_entry, C369, BUF_ENTRY, INST_HI); addr_lo = READ_HWVALUE_MW(fault_entry, C369, BUF_ENTRY, INST_LO); buffer_entry->instance_ptr.address = addr_lo + (addr_hi << HWSIZE_MW(C369, BUF_ENTRY, INST_LO)); @@ -267,7 +272,7 @@ static void parse_fault_entry_common(uvm_parent_gpu_t *parent_gpu, timestamp_lo = READ_HWVALUE_MW(fault_entry, C369, BUF_ENTRY, TIMESTAMP_LO); buffer_entry->timestamp = timestamp_lo + (timestamp_hi << HWSIZE_MW(C369, BUF_ENTRY, TIMESTAMP_LO)); - buffer_entry->fault_type = get_fault_type(fault_entry); + buffer_entry->fault_type = parent_gpu->fault_buffer_hal->get_fault_type(fault_entry); buffer_entry->fault_access_type = get_fault_access_type(fault_entry); @@ -325,13 +330,15 @@ void uvm_hal_volta_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu, NvU32 *fault_entry; BUILD_BUG_ON(NVC369_BUF_SIZE > UVM_GPU_MMU_MAX_FAULT_PACKET_SIZE); - fault_entry = get_fault_buffer_entry(parent_gpu, index); - // Valid bit must be set before this function is called UVM_ASSERT(parent_gpu->fault_buffer_hal->entry_is_valid(parent_gpu, index)); + fault_entry = get_fault_buffer_entry(parent_gpu, index); + parse_fault_entry_common(parent_gpu, fault_entry, buffer_entry); + UVM_ASSERT(buffer_entry->is_replayable); + // Automatically clear valid bit for the entry in the fault buffer parent_gpu->fault_buffer_hal->entry_clear_valid(parent_gpu, index); } @@ -344,4 +351,5 @@ void uvm_hal_volta_fault_buffer_parse_non_replayable_entry(uvm_parent_gpu_t *par // No need to clear the valid bit since the fault buffer for non-replayable // faults is owned by RM and we are just parsing a copy of the packet + UVM_ASSERT(!buffer_entry->is_replayable); } diff --git a/kernel-open/nvidia/nv-acpi.c b/kernel-open/nvidia/nv-acpi.c index 4ef0c22810..3c892a1baa 100644 --- a/kernel-open/nvidia/nv-acpi.c +++ b/kernel-open/nvidia/nv-acpi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -98,9 +98,6 @@ static int nv_acpi_notifier_call_chain_handler( ) { struct acpi_bus_event *info = data; - nv_stack_t *sp = NULL; - nv_linux_state_t *nvl = container_of(nb, nv_linux_state_t, acpi_nb); - nv_state_t *nv = NV_STATE_PTR(nvl); /* * The ACPI_VIDEO_NOTIFY_PROBE will be sent for display hot-plug/unplug. @@ -1062,7 +1059,10 @@ static NV_STATUS nv_acpi_wmmx_method( union acpi_object mmx_params[3]; if (!wmmx_handle) + { + *outDataSize = 0; return NV_ERR_NOT_SUPPORTED; + } if (!NV_MAY_SLEEP()) { diff --git a/kernel-open/nvidia/nv-dmabuf.c b/kernel-open/nvidia/nv-dmabuf.c index 7491a17be2..23462567b3 100644 --- a/kernel-open/nvidia/nv-dmabuf.c +++ b/kernel-open/nvidia/nv-dmabuf.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,37 +25,74 @@ #if defined(CONFIG_DMA_SHARED_BUFFER) -// -// The Linux kernel's dma_length in struct scatterlist is unsigned int -// which limits the maximum sg length to 4GB - 1. -// To get around this limitation, the BAR1 scatterlist returned by RM -// is split into (4GB - PAGE_SIZE) sized chunks to build the sg_table. -// -#define NV_DMA_BUF_SG_MAX_LEN ((NvU32)(NVBIT64(32) - PAGE_SIZE)) - typedef struct nv_dma_buf_mem_handle { - NvHandle h_memory; - NvU64 offset; - NvU64 size; - NvU64 bar1_va; + // Memory handle, offset and size + NvHandle h_memory; + NvU64 offset; + NvU64 size; + + // RM memdesc specific data + void *static_mem_info; + + // + // Refcount for phys addresses + // If refcount > 0, phys address ranges in phys_range are reused. + // + NvU64 phys_refcount; + + // Number of scatterlist entries in phys_range[] array + NvU32 phys_range_count; + + // List of phys address ranges to be used to dma map + nv_phys_addr_range_t *phys_range; } nv_dma_buf_mem_handle_t; typedef struct nv_dma_buf_file_private { + // GPU device state nv_state_t *nv; + + // Client, device, subdevice handles NvHandle h_client; NvHandle h_device; NvHandle h_subdevice; + + // Total number of handles supposed to be attached to this dma-buf NvU32 total_objects; + + // + // Number of handles actually attached to this dma-buf. + // This should equal total_objects, or map fails. + // NvU32 num_objects; + + // Total size of all handles supposed to be attached to this dma-buf NvU64 total_size; + + // + // Size of all handles actually attached to the dma-buf + // If all handles are attached, total_size and attached_size must match. + // NvU64 attached_size; + + // Mutex to lock priv state during dma-buf callbacks struct mutex lock; + + // Handle info: see nv_dma_buf_mem_handle_t nv_dma_buf_mem_handle_t *handles; - NvU64 bar1_va_ref_count; + + // RM-private info for MIG configs void *mig_info; + + // Flag to indicate if dma-buf mmap is allowed NvBool can_mmap; + + // + // Flag to indicate if phys addresses are static and can be + // fetched during dma-buf create/reuse instead of in map. + // + NvBool static_phys_addrs; } nv_dma_buf_file_private_t; static void @@ -108,31 +145,94 @@ nv_dma_buf_alloc_file_private( return NULL; } +static void +nv_reset_phys_refcount( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count +) +{ + NvU32 i; + for (i = 0; i < handle_count; i++) + { + NvU32 index = start_index + i; + priv->handles[index].phys_refcount = 0; + } +} + +static NvBool +nv_dec_and_check_zero_phys_refcount( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count +) +{ + NvU32 i; + NvBool is_zero = NV_FALSE; + + for (i = 0; i < handle_count; i++) + { + NvU32 index = start_index + i; + priv->handles[index].phys_refcount--; + if (priv->handles[index].phys_refcount == 0) + { + is_zero = NV_TRUE; + } + } + + return is_zero; +} + +static NvBool +nv_inc_and_check_one_phys_refcount( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count +) +{ + NvU32 i; + NvBool is_one = NV_FALSE; + + for (i = 0; i < handle_count; i++) + { + NvU32 index = start_index + i; + priv->handles[index].phys_refcount++; + if (priv->handles[index].phys_refcount == 1) + { + is_one = NV_TRUE; + } + } + + return is_one; +} + // Must be called with RMAPI lock and GPU lock taken static void nv_dma_buf_undup_mem_handles_unlocked( nvidia_stack_t *sp, - NvU32 index, + NvU32 start_index, NvU32 num_objects, nv_dma_buf_file_private_t *priv ) { - NvU32 i = 0; + NvU32 index, i; - for (i = index; i < num_objects; i++) + for (i = 0; i < num_objects; i++) { - if (priv->handles[i].h_memory == 0) + index = start_index + i; + + if (priv->handles[index].h_memory == 0) { continue; } rm_dma_buf_undup_mem_handle(sp, priv->nv, priv->h_client, - priv->handles[i].h_memory); + priv->handles[index].h_memory); - priv->attached_size -= priv->handles[i].size; - priv->handles[i].h_memory = 0; - priv->handles[i].offset = 0; - priv->handles[i].size = 0; + priv->attached_size -= priv->handles[index].size; + priv->handles[index].h_memory = 0; + priv->handles[index].offset = 0; + priv->handles[index].size = 0; priv->num_objects--; } } @@ -194,6 +294,7 @@ nv_dma_buf_dup_mem_handles( for (i = 0; i < params->numObjects; i++) { NvHandle h_memory_duped = 0; + void *mem_info = NULL; if (priv->handles[index].h_memory != 0) { @@ -216,7 +317,8 @@ nv_dma_buf_dup_mem_handles( params->handles[i], params->offsets[i], params->sizes[i], - &h_memory_duped); + &h_memory_duped, + &mem_info); if (status != NV_OK) { goto failed; @@ -226,6 +328,7 @@ nv_dma_buf_dup_mem_handles( priv->handles[index].h_memory = h_memory_duped; priv->handles[index].offset = params->offsets[i]; priv->handles[index].size = params->sizes[i]; + priv->handles[index].static_mem_info = mem_info; priv->num_objects++; index++; count++; @@ -255,260 +358,439 @@ nv_dma_buf_dup_mem_handles( return status; } -// Must be called with RMAPI lock and GPU lock taken static void -nv_dma_buf_unmap_unlocked( +nv_put_phys_addresses( nvidia_stack_t *sp, - nv_dma_device_t *peer_dma_dev, nv_dma_buf_file_private_t *priv, - struct sg_table *sgt, + NvU32 start_index, NvU32 mapped_handle_count ) { - NV_STATUS status; NvU32 i; - NvU64 dma_len; - NvU64 dma_addr; - NvBool bar1_unmap_needed; - struct scatterlist *sg = NULL; - - bar1_unmap_needed = (priv->bar1_va_ref_count == 0); - sg = sgt->sgl; for (i = 0; i < mapped_handle_count; i++) { - NvU64 handle_size = priv->handles[i].size; - - dma_addr = sg_dma_address(sg); - dma_len = 0; + NvU32 index = start_index + i; - // - // Seek ahead in the scatterlist until the handle size is covered. - // IOVA unmap can then be done all at once instead of doing it - // one sg at a time. - // - while(handle_size != dma_len) + if (priv->handles[index].phys_refcount > 0) { - dma_len += sg_dma_len(sg); - sg = sg_next(sg); + continue; } - nv_dma_unmap_peer(peer_dma_dev, (dma_len / os_page_size), dma_addr); + // Per-handle phys_range is freed by RM + rm_dma_buf_unmap_mem_handle(sp, priv->nv, priv->h_client, + priv->handles[index].h_memory, + priv->handles[index].size, + &priv->handles[index].phys_range, + priv->handles[index].phys_range_count); - if (bar1_unmap_needed) + priv->handles[index].phys_range_count = 0; + } +} + +static void +nv_dma_buf_put_phys_addresses ( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count +) +{ + NV_STATUS status; + nvidia_stack_t *sp = NULL; + NvBool api_lock_taken = NV_FALSE; + NvBool gpu_lock_taken = NV_FALSE; + int rc = 0; + + if (!nv_dec_and_check_zero_phys_refcount(priv, start_index, handle_count)) + { + return; + } + + rc = nv_kmem_cache_alloc_stack(&sp); + if (WARN_ON(rc != 0)) + { + return; + } + + if (!priv->static_phys_addrs) + { + status = rm_acquire_api_lock(sp); + if (WARN_ON(status != NV_OK)) + { + goto free_sp; + } + api_lock_taken = NV_TRUE; + + status = rm_acquire_gpu_lock(sp, priv->nv); + if (WARN_ON(status != NV_OK)) { - status = rm_dma_buf_unmap_mem_handle(sp, priv->nv, priv->h_client, - priv->handles[i].h_memory, - priv->handles[i].size, - priv->handles[i].bar1_va); - WARN_ON(status != NV_OK); + goto unlock_api_lock; } + gpu_lock_taken = NV_TRUE; + } + + nv_put_phys_addresses(sp, priv, start_index, handle_count); + + if (gpu_lock_taken) + { + rm_release_gpu_lock(sp, priv->nv); + } + +unlock_api_lock: + if (api_lock_taken) + { + rm_release_api_lock(sp); } + +free_sp: + nv_kmem_cache_free_stack(sp); } -static struct sg_table* -nv_dma_buf_map( - struct dma_buf_attachment *attachment, - enum dma_data_direction direction +static NV_STATUS +nv_dma_buf_get_phys_addresses ( + nv_dma_buf_file_private_t *priv, + NvU32 start_index, + NvU32 handle_count ) { - NV_STATUS status; + NV_STATUS status = NV_OK; nvidia_stack_t *sp = NULL; - struct scatterlist *sg = NULL; - struct sg_table *sgt = NULL; - struct dma_buf *buf = attachment->dmabuf; - struct device *dev = attachment->dev; - nv_dma_buf_file_private_t *priv = buf->priv; - nv_dma_device_t peer_dma_dev = {{ 0 }}; - NvBool bar1_map_needed; - NvBool bar1_unmap_needed; - NvU32 mapped_handle_count = 0; - NvU32 num_sg_entries = 0; - NvU32 i = 0; + NvBool api_lock_taken = NV_FALSE; + NvBool gpu_lock_taken = NV_FALSE; + NvU32 i; int rc = 0; + if (!nv_inc_and_check_one_phys_refcount(priv, start_index, handle_count)) + { + return NV_OK; + } + + rc = nv_kmem_cache_alloc_stack(&sp); + if (rc != 0) + { + status = NV_ERR_NO_MEMORY; + goto failed; + } + // - // We support importers that are able to handle MMIO resources - // not backed by struct page. This will need to be revisited - // when dma-buf support for P9 will be added. + // Locking is not needed for static phys address configs because the memdesc + // is not expected to change in this case and we hold the refcount on the + // owner GPU and memory before referencing it. // -#if defined(NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT) && \ - defined(NV_DMA_BUF_ATTACHMENT_HAS_PEER2PEER) - if (dma_buf_attachment_is_dynamic(attachment) && - !attachment->peer2peer) + if (!priv->static_phys_addrs) { - nv_printf(NV_DBG_ERRORS, - "NVRM: failed to map dynamic attachment with no P2P support\n"); - return NULL; + status = rm_acquire_api_lock(sp); + if (status != NV_OK) + { + goto free_sp; + } + api_lock_taken = NV_TRUE; + + status = rm_acquire_gpu_lock(sp, priv->nv); + if (status != NV_OK) + { + goto unlock_api_lock; + } + gpu_lock_taken = NV_TRUE; } -#endif - mutex_lock(&priv->lock); + for (i = 0; i < handle_count; i++) + { + NvU32 index = start_index + i; - if (priv->num_objects != priv->total_objects) + if (priv->handles[index].phys_refcount > 1) + { + continue; + } + + // Per-handle phys_range is allocated by RM + status = rm_dma_buf_map_mem_handle(sp, priv->nv, priv->h_client, + priv->handles[index].h_memory, + priv->handles[index].offset, + priv->handles[index].size, + priv->handles[index].static_mem_info, + &priv->handles[index].phys_range, + &priv->handles[index].phys_range_count); + if (status != NV_OK) + { + goto unmap_handles; + } + } + + if (gpu_lock_taken) { - goto unlock_priv; + rm_release_gpu_lock(sp, priv->nv); } - rc = nv_kmem_cache_alloc_stack(&sp); - if (rc != 0) + if (api_lock_taken) { - goto unlock_priv; + rm_release_api_lock(sp); } - status = rm_acquire_api_lock(sp); - if (status != NV_OK) + nv_kmem_cache_free_stack(sp); + + return NV_OK; + +unmap_handles: + nv_put_phys_addresses(sp, priv, start_index, i); + + if (gpu_lock_taken) { - goto free_sp; + rm_release_gpu_lock(sp, priv->nv); } - status = rm_acquire_gpu_lock(sp, priv->nv); - if (status != NV_OK) +unlock_api_lock: + if (api_lock_taken) { - goto unlock_api_lock; + rm_release_api_lock(sp); } - NV_KZALLOC(sgt, sizeof(struct sg_table)); - if (sgt == NULL) +free_sp: + nv_kmem_cache_free_stack(sp); + +failed: + nv_reset_phys_refcount(priv, start_index, handle_count); + + return status; +} + +static void +nv_dma_buf_unmap_pages( + struct device *dev, + struct sg_table *sgt +) +{ + dma_unmap_sg(dev, sgt->sgl, sgt->nents, DMA_BIDIRECTIONAL); +} + +static void +nv_dma_buf_unmap_pfns( + struct device *dev, + struct sg_table *sgt +) +{ + nv_dma_device_t peer_dma_dev = {{ 0 }}; + struct scatterlist *sg = sgt->sgl; + NvU32 i; + + peer_dma_dev.dev = dev; + peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { - goto unlock_gpu_lock; + nv_dma_unmap_peer(&peer_dma_dev, + (sg_dma_len(sg) >> PAGE_SHIFT), + sg_dma_address(sg)); } +} - // - // Pre-calculate number of sg entries we need based on handle size. - // This is needed to allocate sg_table. - // +static struct sg_table* +nv_dma_buf_map_pages ( + struct device *dev, + nv_dma_buf_file_private_t *priv +) +{ + struct sg_table *sgt = NULL; + struct scatterlist *sg; + NvU32 nents = 0; + NvU32 i; + int rc; + + // Calculate nents needed to allocate sg_table for (i = 0; i < priv->num_objects; i++) { - NvU64 count = priv->handles[i].size + NV_DMA_BUF_SG_MAX_LEN - 1; - do_div(count, NV_DMA_BUF_SG_MAX_LEN); - num_sg_entries += count; + nents += priv->handles[i].phys_range_count; } - // - // RM currently returns contiguous BAR1, so we create as many - // sg entries as num_sg_entries calculated above. - // When RM can alloc discontiguous BAR1, this code will need to be revisited. - // - rc = sg_alloc_table(sgt, num_sg_entries, GFP_KERNEL); + NV_KZALLOC(sgt, sizeof(struct sg_table)); + if (sgt == NULL) + { + return NULL; + } + + rc = sg_alloc_table(sgt, nents, GFP_KERNEL); if (rc != 0) { goto free_sgt; } - peer_dma_dev.dev = dev; - peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; - bar1_map_needed = bar1_unmap_needed = (priv->bar1_va_ref_count == 0); - sg = sgt->sgl; + for (i = 0; i < priv->num_objects; i++) { - NvU64 dma_addr; - NvU64 dma_len; - - if (bar1_map_needed) + NvU32 range_count = priv->handles[i].phys_range_count; + NvU32 index = 0; + for (index = 0; index < range_count; index++) { - status = rm_dma_buf_map_mem_handle(sp, priv->nv, priv->h_client, - priv->handles[i].h_memory, - priv->handles[i].offset, - priv->handles[i].size, - &priv->handles[i].bar1_va); - if (status != NV_OK) + NvU64 addr = priv->handles[i].phys_range[index].addr; + NvU64 len = priv->handles[i].phys_range[index].len; + struct page *page = NV_GET_PAGE_STRUCT(addr); + + if ((page == NULL) || (sg == NULL)) { - goto unmap_handles; + goto free_table; } + + sg_set_page(sg, page, len, 0); + sg = sg_next(sg); } + } - mapped_handle_count++; + // DMA map the sg_table + rc = dma_map_sg(dev, sgt->sgl, sgt->orig_nents, DMA_BIDIRECTIONAL); + if (rc <= 0) + { + goto free_table; + } + sgt->nents = rc; - dma_addr = priv->handles[i].bar1_va; - dma_len = priv->handles[i].size; + return sgt; - // - // IOVA map the full handle at once and then breakdown the range - // (dma_addr, dma_addr + dma_len) into smaller sg entries. - // - status = nv_dma_map_peer(&peer_dma_dev, priv->nv->dma_dev, - 0x1, (dma_len / os_page_size), &dma_addr); - if (status != NV_OK) - { - if (bar1_unmap_needed) - { - // Unmap the recently mapped memory handle - (void) rm_dma_buf_unmap_mem_handle(sp, priv->nv, priv->h_client, - priv->handles[i].h_memory, - priv->handles[i].size, - priv->handles[i].bar1_va); - } +free_table: + sg_free_table(sgt); - mapped_handle_count--; +free_sgt: + NV_KFREE(sgt, sizeof(struct sg_table)); - // Unmap remaining memory handles - goto unmap_handles; - } + return NULL; +} - while(dma_len != 0) - { - NvU32 sg_len = NV_MIN(dma_len, NV_DMA_BUF_SG_MAX_LEN); +static struct sg_table* +nv_dma_buf_map_pfns ( + struct device *dev, + nv_dma_buf_file_private_t *priv +) +{ + NV_STATUS status; + struct sg_table *sgt = NULL; + struct scatterlist *sg; + nv_dma_device_t peer_dma_dev = {{ 0 }}; + NvU32 dma_max_seg_size; + NvU32 nents = 0; + NvU32 mapped_nents = 0; + NvU32 i = 0; + int rc = 0; - sg_set_page(sg, NULL, sg_len, 0); - sg_dma_address(sg) = (dma_addr_t)dma_addr; - sg_dma_len(sg) = sg_len; - dma_addr += sg_len; - dma_len -= sg_len; - sg = sg_next(sg); + peer_dma_dev.dev = dev; + peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; + + dma_max_seg_size = NV_ALIGN_DOWN(dma_get_max_seg_size(dev), PAGE_SIZE); + + if (dma_max_seg_size < PAGE_SIZE) + { + return NULL; + } + + // Calculate nents needed to allocate sg_table + for (i = 0; i < priv->num_objects; i++) + { + NvU32 range_count = priv->handles[i].phys_range_count; + NvU32 index; + + for (index = 0; index < range_count; index++) + { + NvU64 length = priv->handles[i].phys_range[index].len; + NvU64 count = length + dma_max_seg_size - 1; + do_div(count, dma_max_seg_size); + nents += count; } } - priv->bar1_va_ref_count++; + NV_KZALLOC(sgt, sizeof(struct sg_table)); + if (sgt == NULL) + { + return NULL; + } - rm_release_gpu_lock(sp, priv->nv); + rc = sg_alloc_table(sgt, nents, GFP_KERNEL); + if (rc != 0) + { + goto free_sgt; + } - rm_release_api_lock(sp); + sg = sgt->sgl; + for (i = 0; i < priv->num_objects; i++) + { + NvU32 range_count = priv->handles[i].phys_range_count; + NvU32 index = 0; - nv_kmem_cache_free_stack(sp); + for (index = 0; index < range_count; index++) + { + NvU64 dma_addr = priv->handles[i].phys_range[index].addr; + NvU64 dma_len = priv->handles[i].phys_range[index].len; - mutex_unlock(&priv->lock); + // Break the scatterlist into dma_max_seg_size chunks + while(dma_len != 0) + { + NvU32 sg_len = NV_MIN(dma_len, dma_max_seg_size); + + if (sg == NULL) + { + goto unmap_pfns; + } + + status = nv_dma_map_peer(&peer_dma_dev, priv->nv->dma_dev, 0x1, + (sg_len >> PAGE_SHIFT), &dma_addr); + if (status != NV_OK) + { + goto unmap_pfns; + } + + sg_set_page(sg, NULL, sg_len, 0); + sg_dma_address(sg) = (dma_addr_t) dma_addr; + sg_dma_len(sg) = sg_len; + dma_addr += sg_len; + dma_len -= sg_len; + mapped_nents++; + sg = sg_next(sg); + } + } + } + sgt->nents = mapped_nents; + + WARN_ON(sgt->nents != sgt->orig_nents); return sgt; -unmap_handles: - nv_dma_buf_unmap_unlocked(sp, &peer_dma_dev, priv, sgt, mapped_handle_count); +unmap_pfns: + sgt->nents = mapped_nents; + + nv_dma_buf_unmap_pfns(dev, sgt); sg_free_table(sgt); free_sgt: NV_KFREE(sgt, sizeof(struct sg_table)); -unlock_gpu_lock: - rm_release_gpu_lock(sp, priv->nv); - -unlock_api_lock: - rm_release_api_lock(sp); - -free_sp: - nv_kmem_cache_free_stack(sp); - -unlock_priv: - mutex_unlock(&priv->lock); - return NULL; } -static void -nv_dma_buf_unmap( +static struct sg_table* +nv_dma_buf_map( struct dma_buf_attachment *attachment, - struct sg_table *sgt, enum dma_data_direction direction ) { NV_STATUS status; + struct sg_table *sgt = NULL; struct dma_buf *buf = attachment->dmabuf; - struct device *dev = attachment->dev; - nvidia_stack_t *sp = NULL; nv_dma_buf_file_private_t *priv = buf->priv; - nv_dma_device_t peer_dma_dev = {{ 0 }}; - int rc = 0; + + // + // On non-coherent platforms, importers must be able to handle peer + // MMIO resources not backed by struct page. + // +#if defined(NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT) && \ + defined(NV_DMA_BUF_ATTACHMENT_HAS_PEER2PEER) + if (!priv->nv->coherent && + dma_buf_attachment_is_dynamic(attachment) && + !attachment->peer2peer) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: failed to map dynamic attachment with no P2P support\n"); + return NULL; + } +#endif mutex_lock(&priv->lock); @@ -517,44 +799,78 @@ nv_dma_buf_unmap( goto unlock_priv; } - rc = nv_kmem_cache_alloc_stack(&sp); - if (WARN_ON(rc != 0)) + if (!priv->static_phys_addrs) { - goto unlock_priv; + status = nv_dma_buf_get_phys_addresses(priv, 0, priv->num_objects); + if (status != NV_OK) + { + goto unlock_priv; + } } - status = rm_acquire_api_lock(sp); - if (WARN_ON(status != NV_OK)) + if (priv->nv->coherent) { - goto free_sp; + sgt = nv_dma_buf_map_pages(attachment->dev, priv); + } + else + { + sgt = nv_dma_buf_map_pfns(attachment->dev, priv); + } + if (sgt == NULL) + { + goto unmap_handles; } - status = rm_acquire_gpu_lock(sp, priv->nv); - if (WARN_ON(status != NV_OK)) + mutex_unlock(&priv->lock); + + return sgt; + +unmap_handles: + if (!priv->static_phys_addrs) { - goto unlock_api_lock; + nv_dma_buf_put_phys_addresses(priv, 0, priv->num_objects); } - peer_dma_dev.dev = dev; - peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; +unlock_priv: + mutex_unlock(&priv->lock); - priv->bar1_va_ref_count--; + return NULL; +} - nv_dma_buf_unmap_unlocked(sp, &peer_dma_dev, priv, sgt, priv->num_objects); +static void +nv_dma_buf_unmap( + struct dma_buf_attachment *attachment, + struct sg_table *sgt, + enum dma_data_direction direction +) +{ + struct dma_buf *buf = attachment->dmabuf; + nv_dma_buf_file_private_t *priv = buf->priv; - sg_free_table(sgt); + mutex_lock(&priv->lock); - NV_KFREE(sgt, sizeof(struct sg_table)); + if (priv->nv->coherent) + { + nv_dma_buf_unmap_pages(attachment->dev, sgt); + } + else + { + nv_dma_buf_unmap_pfns(attachment->dev, sgt); + } - rm_release_gpu_lock(sp, priv->nv); + // + // For static_phys_addrs platforms, this operation is done in release + // since getting the phys_addrs was done in create/reuse. + // + if (!priv->static_phys_addrs) + { + nv_dma_buf_put_phys_addresses(priv, 0, priv->num_objects); + } -unlock_api_lock: - rm_release_api_lock(sp); + sg_free_table(sgt); -free_sp: - nv_kmem_cache_free_stack(sp); + NV_KFREE(sgt, sizeof(struct sg_table)); -unlock_priv: mutex_unlock(&priv->lock); } @@ -564,6 +880,7 @@ nv_dma_buf_release( ) { int rc = 0; + NvU32 i; nvidia_stack_t *sp = NULL; nv_dma_buf_file_private_t *priv = buf->priv; nv_state_t *nv; @@ -575,17 +892,31 @@ nv_dma_buf_release( nv = priv->nv; + if (priv->static_phys_addrs) + { + nv_dma_buf_put_phys_addresses(priv, 0, priv->num_objects); + } + rc = nv_kmem_cache_alloc_stack(&sp); if (WARN_ON(rc != 0)) { return; } + // phys_addr refcounts must be zero at this point + for (i = 0; i < priv->num_objects; i++) + { + WARN_ON(priv->handles[i].phys_refcount > 0); + } + nv_dma_buf_undup_mem_handles(sp, 0, priv->num_objects, priv); rm_dma_buf_put_client_and_device(sp, priv->nv, priv->h_client, priv->h_device, priv->h_subdevice, priv->mig_info); + WARN_ON(priv->attached_size > 0); + WARN_ON(priv->num_objects > 0); + nv_dma_buf_free_file_private(priv); buf->priv = NULL; @@ -737,7 +1068,8 @@ nv_dma_buf_create( &priv->h_client, &priv->h_device, &priv->h_subdevice, - &priv->mig_info); + &priv->mig_info, + &priv->static_phys_addrs); if (status != NV_OK) { goto cleanup_device; @@ -749,6 +1081,17 @@ nv_dma_buf_create( goto cleanup_client_and_device; } + // Get CPU static phys addresses if possible to do so at this time. + if (priv->static_phys_addrs) + { + status = nv_dma_buf_get_phys_addresses(priv, params->index, + params->numObjects); + if (status != NV_OK) + { + goto cleanup_handles; + } + } + #if (NV_DMA_BUF_EXPORT_ARGUMENT_COUNT == 1) { DEFINE_DMA_BUF_EXPORT_INFO(exp_info); @@ -774,7 +1117,7 @@ nv_dma_buf_create( status = NV_ERR_OPERATING_SYSTEM; - goto cleanup_handles; + goto put_phys_addrs; } nv_kmem_cache_free_stack(sp); @@ -797,8 +1140,14 @@ nv_dma_buf_create( return NV_OK; +put_phys_addrs: + if (priv->static_phys_addrs) + { + nv_dma_buf_put_phys_addresses(priv, params->index, params->numObjects); + } + cleanup_handles: - nv_dma_buf_undup_mem_handles(sp, 0, priv->num_objects, priv); + nv_dma_buf_undup_mem_handles(sp, params->index, params->numObjects, priv); cleanup_client_and_device: rm_dma_buf_put_client_and_device(sp, priv->nv, priv->h_client, priv->h_device, @@ -877,6 +1226,28 @@ nv_dma_buf_reuse( goto cleanup_sp; } + // Get CPU static phys addresses if possible to do so at this time. + if (priv->static_phys_addrs) + { + status = nv_dma_buf_get_phys_addresses(priv, params->index, + params->numObjects); + if (status != NV_OK) + { + goto cleanup_handles; + } + } + + nv_kmem_cache_free_stack(sp); + + mutex_unlock(&priv->lock); + + dma_buf_put(buf); + + return NV_OK; + +cleanup_handles: + nv_dma_buf_undup_mem_handles(sp, params->index, params->numObjects, priv); + cleanup_sp: nv_kmem_cache_free_stack(sp); diff --git a/kernel-open/nvidia/nv-kthread-q.c b/kernel-open/nvidia/nv-kthread-q.c index 31a54cc05b..2098f27a70 100644 --- a/kernel-open/nvidia/nv-kthread-q.c +++ b/kernel-open/nvidia/nv-kthread-q.c @@ -301,7 +301,7 @@ static void _q_flush_function(void *args) static void _raw_q_flush(nv_kthread_q_t *q) { nv_kthread_q_item_t q_item; - DECLARE_COMPLETION(completion); + DECLARE_COMPLETION_ONSTACK(completion); nv_kthread_q_item_init(&q_item, _q_flush_function, &completion); diff --git a/kernel-open/nvidia/nv-nano-timer.c b/kernel-open/nvidia/nv-nano-timer.c index 453b669636..35220b4914 100644 --- a/kernel-open/nvidia/nv-nano-timer.c +++ b/kernel-open/nvidia/nv-nano-timer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -174,7 +174,7 @@ void NV_API_CALL nv_create_nano_timer( * * @param[in] nv Per gpu linux state * @param[in] nv_nstimer Pointer to nv_nano_timer_t object - * @param[in] timens time in nano seconds + * @param[in] time_ns Relative time in nano seconds */ void NV_API_CALL nv_start_nano_timer( nv_state_t *nv, @@ -213,7 +213,7 @@ void NV_API_CALL nv_cancel_nano_timer( #if NV_NANO_TIMER_USE_HRTIMER hrtimer_cancel(&nv_nstimer->hr_timer); #else - del_timer(&nv_nstimer->jiffy_timer); + del_timer_sync(&nv_nstimer->jiffy_timer); #endif } diff --git a/kernel-open/nvidia/nv-p2p.c b/kernel-open/nvidia/nv-p2p.c index 1f090fbd13..e6fa5c5e87 100644 --- a/kernel-open/nvidia/nv-p2p.c +++ b/kernel-open/nvidia/nv-p2p.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,11 @@ #include "nv-p2p.h" #include "rmp2pdefines.h" +typedef enum nv_p2p_page_table_type { + NV_P2P_PAGE_TABLE_TYPE_NON_PERSISTENT = 0, + NV_P2P_PAGE_TABLE_TYPE_PERSISTENT, +} nv_p2p_page_table_type_t; + typedef struct nv_p2p_dma_mapping { struct list_head list_node; struct nvidia_p2p_dma_mapping *dma_mapping; @@ -44,13 +49,9 @@ typedef struct nv_p2p_mem_info { struct list_head list_head; struct semaphore lock; } dma_mapping_list; - NvBool bPersistent; void *private; } nv_p2p_mem_info_t; -int nvidia_p2p_cap_persistent_pages = 1; -EXPORT_SYMBOL(nvidia_p2p_cap_persistent_pages); - // declared and created in nv.c extern void *nvidia_p2p_page_t_cache; @@ -238,6 +239,7 @@ static void nv_p2p_free_page_table( } static NV_STATUS nv_p2p_put_pages( + nv_p2p_page_table_type_t pt_type, nvidia_stack_t * sp, uint64_t p2p_token, uint32_t va_space, @@ -246,9 +248,6 @@ static NV_STATUS nv_p2p_put_pages( ) { NV_STATUS status; - struct nv_p2p_mem_info *mem_info = NULL; - - mem_info = container_of(*page_table, nv_p2p_mem_info_t, page_table); /* * rm_p2p_put_pages returns NV_OK if the page_table was found and @@ -258,8 +257,15 @@ static NV_STATUS nv_p2p_put_pages( * rm_p2p_put_pages returns NV_ERR_OBJECT_NOT_FOUND if the page_table * was already unlinked. */ - if (mem_info->bPersistent) + if (pt_type == NV_P2P_PAGE_TABLE_TYPE_PERSISTENT) { + struct nv_p2p_mem_info *mem_info = NULL; + + /* + * It is safe to access persistent page_table as there is no async + * callback which can free it unlike non-persistent page_table. + */ + mem_info = container_of(*page_table, nv_p2p_mem_info_t, page_table); status = rm_p2p_put_pages_persistent(sp, mem_info->private, *page_table); } else @@ -273,7 +279,8 @@ static NV_STATUS nv_p2p_put_pages( nv_p2p_free_page_table(*page_table); *page_table = NULL; } - else if (!mem_info->bPersistent && (status == NV_ERR_OBJECT_NOT_FOUND)) + else if ((pt_type == NV_P2P_PAGE_TABLE_TYPE_NON_PERSISTENT) && + (status == NV_ERR_OBJECT_NOT_FOUND)) { status = NV_OK; *page_table = NULL; @@ -327,7 +334,8 @@ static void nv_p2p_mem_info_free_callback(void *data) nv_p2p_free_platform_data(&mem_info->page_table); } -int nvidia_p2p_get_pages( +static int nv_p2p_get_pages( + nv_p2p_page_table_type_t pt_type, uint64_t p2p_token, uint32_t va_space, uint64_t virtual_address, @@ -376,9 +384,10 @@ int nvidia_p2p_get_pages( *page_table = &(mem_info->page_table); - mem_info->bPersistent = (free_callback == NULL); - - //asign length to temporary variable since do_div macro does in-place division + /* + * assign length to temporary variable since do_div macro does in-place + * division + */ temp_length = length; do_div(temp_length, page_size); page_count = temp_length; @@ -405,7 +414,7 @@ int nvidia_p2p_get_pages( goto failed; } - if (mem_info->bPersistent) + if (pt_type == NV_P2P_PAGE_TABLE_TYPE_PERSISTENT) { void *gpu_info = NULL; @@ -415,12 +424,15 @@ int nvidia_p2p_get_pages( goto failed; } - status = rm_p2p_get_gpu_info(sp, virtual_address, length, &gpu_uuid, &gpu_info); + status = rm_p2p_get_gpu_info(sp, virtual_address, length, + &gpu_uuid, &gpu_info); if (status != NV_OK) { goto failed; } + (*page_table)->gpu_uuid = gpu_uuid; + rc = nvidia_dev_get_uuid(gpu_uuid, sp); if (rc != 0) { @@ -432,8 +444,10 @@ int nvidia_p2p_get_pages( bGetUuid = NV_TRUE; - status = rm_p2p_get_pages_persistent(sp, virtual_address, length, &mem_info->private, - physical_addresses, &entries, *page_table, gpu_info); + status = rm_p2p_get_pages_persistent(sp, virtual_address, length, + &mem_info->private, + physical_addresses, &entries, + *page_table, gpu_info); if (status != NV_OK) { goto failed; @@ -449,10 +463,11 @@ int nvidia_p2p_get_pages( { goto failed; } + + (*page_table)->gpu_uuid = gpu_uuid; } bGetPages = NV_TRUE; - (*page_table)->gpu_uuid = gpu_uuid; status = os_alloc_mem((void *)&(*page_table)->pages, (entries * sizeof(page))); @@ -516,10 +531,12 @@ int nvidia_p2p_get_pages( { os_free_mem(physical_addresses); } + if (wreqmb_h != NULL) { os_free_mem(wreqmb_h); } + if (rreqmb_h != NULL) { os_free_mem(rreqmb_h); @@ -527,7 +544,7 @@ int nvidia_p2p_get_pages( if (bGetPages) { - (void)nv_p2p_put_pages(sp, p2p_token, va_space, + (void)nv_p2p_put_pages(pt_type, sp, p2p_token, va_space, virtual_address, page_table); } @@ -546,8 +563,45 @@ int nvidia_p2p_get_pages( return nvidia_p2p_map_status(status); } +int nvidia_p2p_get_pages( + uint64_t p2p_token, + uint32_t va_space, + uint64_t virtual_address, + uint64_t length, + struct nvidia_p2p_page_table **page_table, + void (*free_callback)(void * data), + void *data +) +{ + if (free_callback == NULL) + { + return -EINVAL; + } + + return nv_p2p_get_pages(NV_P2P_PAGE_TABLE_TYPE_NON_PERSISTENT, + p2p_token, va_space, virtual_address, + length, page_table, free_callback, data); +} EXPORT_SYMBOL(nvidia_p2p_get_pages); +int nvidia_p2p_get_pages_persistent( + uint64_t virtual_address, + uint64_t length, + struct nvidia_p2p_page_table **page_table, + uint32_t flags +) +{ + if (flags != 0) + { + return -EINVAL; + } + + return nv_p2p_get_pages(NV_P2P_PAGE_TABLE_TYPE_PERSISTENT, 0, 0, + virtual_address, length, page_table, + NULL, NULL); +} +EXPORT_SYMBOL(nvidia_p2p_get_pages_persistent); + /* * This function is a no-op, but is left in place (for now), in order to allow * third-party callers to build and run without errors or warnings. This is OK, @@ -568,15 +622,14 @@ int nvidia_p2p_put_pages( struct nvidia_p2p_page_table *page_table ) { - struct nv_p2p_mem_info *mem_info = NULL; - NvU8 uuid[NVIDIA_P2P_GPU_UUID_LEN] = {0}; NV_STATUS status; nvidia_stack_t *sp = NULL; int rc = 0; - os_mem_copy(uuid, page_table->gpu_uuid, NVIDIA_P2P_GPU_UUID_LEN); - - mem_info = container_of(page_table, nv_p2p_mem_info_t, page_table); + if (page_table == NULL) + { + return 0; + } rc = nv_kmem_cache_alloc_stack(&sp); if (rc != 0) @@ -584,20 +637,55 @@ int nvidia_p2p_put_pages( return -ENOMEM; } - status = nv_p2p_put_pages(sp, p2p_token, va_space, + status = nv_p2p_put_pages(NV_P2P_PAGE_TABLE_TYPE_NON_PERSISTENT, + sp, p2p_token, va_space, virtual_address, &page_table); - if (mem_info->bPersistent) + nv_kmem_cache_free_stack(sp); + + return nvidia_p2p_map_status(status); +} +EXPORT_SYMBOL(nvidia_p2p_put_pages); + +int nvidia_p2p_put_pages_persistent( + uint64_t virtual_address, + struct nvidia_p2p_page_table *page_table, + uint32_t flags +) +{ + NvU8 uuid[NVIDIA_P2P_GPU_UUID_LEN] = {0}; + NV_STATUS status; + nvidia_stack_t *sp = NULL; + int rc = 0; + + if (flags != 0) { - nvidia_dev_put_uuid(uuid, sp); + return -EINVAL; + } + + if (page_table == NULL) + { + return 0; + } + + rc = nv_kmem_cache_alloc_stack(&sp); + if (rc != 0) + { + return -ENOMEM; } + os_mem_copy(uuid, page_table->gpu_uuid, NVIDIA_P2P_GPU_UUID_LEN); + + status = nv_p2p_put_pages(NV_P2P_PAGE_TABLE_TYPE_PERSISTENT, + sp, 0, 0, virtual_address, &page_table); + + nvidia_dev_put_uuid(uuid, sp); + nv_kmem_cache_free_stack(sp); return nvidia_p2p_map_status(status); } - -EXPORT_SYMBOL(nvidia_p2p_put_pages); +EXPORT_SYMBOL(nvidia_p2p_put_pages_persistent); int nvidia_p2p_dma_map_pages( struct pci_dev *peer, diff --git a/kernel-open/nvidia/nv-p2p.h b/kernel-open/nvidia/nv-p2p.h index a9469bdbb2..e19b38a8f7 100644 --- a/kernel-open/nvidia/nv-p2p.h +++ b/kernel-open/nvidia/nv-p2p.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -94,11 +94,10 @@ struct nvidia_p2p_params { } nvidia_p2p_params_t; /* - * Capability flag for users to detect + * Macro for users to detect * driver support for persistent pages. */ -extern int nvidia_p2p_cap_persistent_pages; -#define NVIDIA_P2P_CAP_PERSISTENT_PAGES +#define NVIDIA_P2P_CAP_GET_PAGES_PERSISTENT_API /* * This API is not supported. @@ -173,11 +172,6 @@ struct nvidia_p2p_page_table { * A pointer to the function to be invoked when the pages * underlying the virtual address range are freed * implicitly. - * If NULL, persistent pages will be returned. - * This means the pages underlying the range of GPU virtual memory - * will persist until explicitly freed by nvidia_p2p_put_pages(). - * Persistent GPU memory mappings are not supported on PowerPC, - * MIG-enabled devices and vGPU. * @param[in] data * A non-NULL opaque pointer to private data to be passed to the * callback function. @@ -190,12 +184,48 @@ struct nvidia_p2p_page_table { * insufficient resources were available to complete the operation. * -EIO if an unknown error occurred. */ -int nvidia_p2p_get_pages(uint64_t p2p_token, uint32_t va_space, - uint64_t virtual_address, +int nvidia_p2p_get_pages( uint64_t p2p_token, uint32_t va_space, + uint64_t virtual_address, uint64_t length, + struct nvidia_p2p_page_table **page_table, + void (*free_callback)(void *data), void *data); + +/* + * @brief + * Pin and make the pages underlying a range of GPU virtual memory + * accessible to a third-party device. The pages will persist until + * explicitly freed by nvidia_p2p_put_pages_persistent(). + * + * Persistent GPU memory mappings are not supported on PowerPC, + * MIG-enabled devices and vGPU. + * + * This API only supports pinned, GPU-resident memory, such as that provided + * by cudaMalloc(). + * + * This API may sleep. + * + * @param[in] virtual_address + * The start address in the specified virtual address space. + * Address must be aligned to the 64KB boundary. + * @param[in] length + * The length of the requested P2P mapping. + * Length must be a multiple of 64KB. + * @param[out] page_table + * A pointer to an array of structures with P2P PTEs. + * @param[in] flags + * Must be set to zero for now. + * + * @return + * 0 upon successful completion. + * -EINVAL if an invalid argument was supplied. + * -ENOTSUPP if the requested operation is not supported. + * -ENOMEM if the driver failed to allocate memory or if + * insufficient resources were available to complete the operation. + * -EIO if an unknown error occurred. + */ +int nvidia_p2p_get_pages_persistent(uint64_t virtual_address, uint64_t length, struct nvidia_p2p_page_table **page_table, - void (*free_callback)(void *data), - void *data); + uint32_t flags); #define NVIDIA_P2P_DMA_MAPPING_VERSION 0x00020003 @@ -268,6 +298,8 @@ int nvidia_p2p_dma_unmap_pages(struct pci_dev *peer, * Release a set of pages previously made accessible to * a third-party device. * + * This API may sleep. + * * @param[in] p2p_token * A token that uniquely identifies the P2P mapping. * @param[in] va_space @@ -282,10 +314,33 @@ int nvidia_p2p_dma_unmap_pages(struct pci_dev *peer, * -EINVAL if an invalid argument was supplied. * -EIO if an unknown error occurred. */ -int nvidia_p2p_put_pages(uint64_t p2p_token, uint32_t va_space, - uint64_t virtual_address, +int nvidia_p2p_put_pages(uint64_t p2p_token, + uint32_t va_space, uint64_t virtual_address, struct nvidia_p2p_page_table *page_table); +/* + * @brief + * Release a set of persistent pages previously made accessible to + * a third-party device. + * + * This API may sleep. + * + * @param[in] virtual_address + * The start address in the specified virtual address space. + * @param[in] page_table + * A pointer to the array of structures with P2P PTEs. + * @param[in] flags + * Must be set to zero for now. + * + * @return + * 0 upon successful completion. + * -EINVAL if an invalid argument was supplied. + * -EIO if an unknown error occurred. + */ +int nvidia_p2p_put_pages_persistent(uint64_t virtual_address, + struct nvidia_p2p_page_table *page_table, + uint32_t flags); + /* * @brief * Free a third-party P2P page table. (This function is a no-op.) diff --git a/kernel-open/nvidia/nv-pci.c b/kernel-open/nvidia/nv-pci.c index ad2bfee1ce..79c9fc7dd9 100644 --- a/kernel-open/nvidia/nv-pci.c +++ b/kernel-open/nvidia/nv-pci.c @@ -269,6 +269,72 @@ static int nv_resize_pcie_bars(struct pci_dev *pci_dev) { #endif /* NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT */ } +static void +nv_init_coherent_link_info +( + nv_state_t *nv +) +{ +#if defined(NV_DEVICE_PROPERTY_READ_U64_PRESENT) && \ + defined(CONFIG_ACPI_NUMA) && \ + NV_IS_EXPORT_SYMBOL_PRESENT_pxm_to_node + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + NvU64 pa = 0; + NvU64 pxm_start = 0; + NvU64 pxm_count = 0; + NvU32 pxm; + + if (!NVCPU_IS_AARCH64) + return; + + if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-base-pa", &pa) != 0) + goto failed; + if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-start", &pxm_start) != 0) + goto failed; + if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-count", &pxm_count) != 0) + goto failed; + + NV_DEV_PRINTF(NV_DBG_INFO, nv, "DSD properties: \n"); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PA: 0x%lx \n", pa); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PXM start: %u \n", pxm_start); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PXM count: %u \n", pxm_count); + + nvl->coherent_link_info.gpu_mem_pa = pa; + + for (pxm = pxm_start; pxm < (pxm_start + pxm_count); pxm++) + { + NvU32 node = pxm_to_node(pxm); + if (node != NUMA_NO_NODE) + { + set_bit(node, nvl->coherent_link_info.free_node_bitmap); + } + } + + if (NVreg_EnableUserNUMAManagement) + { + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE); + nvl->numa_info.use_auto_online = NV_TRUE; + + if (!bitmap_empty(nvl->coherent_link_info.free_node_bitmap, MAX_NUMNODES)) + { + nvl->numa_info.node_id = find_first_bit(nvl->coherent_link_info.free_node_bitmap, MAX_NUMNODES); + } + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "GPU NUMA information: node id: %u PA: 0x%llx\n", + nvl->numa_info.node_id, nvl->coherent_link_info.gpu_mem_pa); + } + else + { + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "User-mode NUMA onlining disabled.\n"); + } + + return; + +failed: + NV_DEV_PRINTF(NV_DBG_SETUP, nv, "Cannot get coherent link info.\n"); +#endif + return; +} + /* find nvidia devices and set initial state */ static int nv_pci_probe @@ -463,6 +529,13 @@ nv_pci_probe NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); + // With GH180 C2C, VF BAR1/2 are disabled and therefore expected to be 0. + if (j != NV_GPU_BAR_INDEX_REGS) + { + nv_printf(NV_DBG_INFO, "NVRM: ignore invalid BAR failure for BAR%d\n", j); + continue; + } + goto failed; } @@ -547,11 +620,16 @@ nv_pci_probe nv_init_ibmnpu_info(nv); + nv_init_coherent_link_info(nv); + #if defined(NVCPU_PPC64LE) // Use HW NUMA support as a proxy for ATS support. This is true in the only // PPC64LE platform where ATS is currently supported (IBM P9). nv_ats_supported &= nv_platform_supports_numa(nvl); #else +#if defined(NV_PCI_DEV_HAS_ATS_ENABLED) + nv_ats_supported &= pci_dev->ats_enabled; +#endif #endif if (nv_ats_supported) { diff --git a/kernel-open/nvidia/nv-procfs.c b/kernel-open/nvidia/nv-procfs.c index fae10184c2..d4d2007602 100644 --- a/kernel-open/nvidia/nv-procfs.c +++ b/kernel-open/nvidia/nv-procfs.c @@ -1016,6 +1016,23 @@ numa_status_read( rm_status = rm_get_gpu_numa_info(sp, nv, nid, numa_mem_addr, numa_mem_size, list->addresses, &list->numEntries); + + if (rm_status == NV_OK && *nid == NUMA_NO_NODE) + { + // + // RM returns NUMA_NO_NODE when running MIG instances because + // this rmClient is not subscribed to any MIG partition since + // it was subscribed to whole GPU only during RMInit and is not + // updated when MIG partitions are created. + // Returning error here so that numa_status results in EIO + // because of missing support in numa_status to use it for multiple + // numa nodes. + // + // TODO: add support for multiple numa nodes in numa_status interface + // and remove this check, bug 4006012 + // + rm_status = NV_ERR_NOT_SUPPORTED; + } *status = nv_get_numa_status(nvl); done: diff --git a/kernel-open/nvidia/nv-reg.h b/kernel-open/nvidia/nv-reg.h index cdb51417fe..c8ea2ced09 100644 --- a/kernel-open/nvidia/nv-reg.h +++ b/kernel-open/nvidia/nv-reg.h @@ -21,10 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// +// This file holds Unix-specific NVIDIA driver options +// + #ifndef _RM_REG_H_ #define _RM_REG_H_ #include "nvtypes.h" +#include "nv-firmware-registry.h" /* * use NV_REG_STRING to stringify a registry key when using that registry key @@ -723,72 +728,33 @@ * When this option is enabled, the NVIDIA driver will enable use of GPU * firmware. * - * Possible mode values: - * 0 - Do not enable GPU firmware - * 1 - Enable GPU firmware - * 2 - (Default) Use the default enablement policy for GPU firmware - * - * Setting this to anything other than 2 will alter driver firmware- - * enablement policies, possibly disabling GPU firmware where it would - * have otherwise been enabled by default. - * * If this key is set globally to the system, the driver may still attempt * to apply some policies to maintain uniform firmware modes across all * GPUS. This may result in the driver failing initialization on some GPUs * to maintain such a policy. - * + * * If this key is set using NVreg_RegistryDwordsPerDevice, then the driver * will attempt to honor whatever configuration is specified without applying * additional policies. This may also result in failed GPU initialzations if * the configuration is not possible (for example if the firmware is missing - * from the filesystem, or the GPU is not capable). - * - * Policy bits: - * - * POLICY_ALLOW_FALLBACK: - * As the normal behavior is to fail GPU initialization if this registry - * entry is set in such a way that results in an invalid configuration, if - * instead the user would like the driver to automatically try to fallback - * to initializing the failing GPU with firmware disabled, then this bit can - * be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). - * Note that this can result in a mixed mode configuration (ex: GPU0 has - * firmware enabled, but GPU1 does not). + * from the filesystem, or the GPU is not capable). * + * NOTE: More details for this regkey can be found in nv-firmware-registry.h */ - #define __NV_ENABLE_GPU_FIRMWARE EnableGpuFirmware #define NV_REG_ENABLE_GPU_FIRMWARE NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE) -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 - -#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 -#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 - -#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 -#define NV_REG_ENABLE_GPU_FIRMWARE_INVALID_VALUE 0xFFFFFFFF - /* * Option: EnableGpuFirmwareLogs * * When this option is enabled, the NVIDIA driver will send GPU firmware logs * to the system log, when possible. * - * Possible values: - * 0 - Do not send GPU firmware logs to the system log - * 1 - Enable sending of GPU firmware logs to the system log - * 2 - (Default) Enable sending of GPU firmware logs to the system log for - * the debug kernel driver build only + * NOTE: More details for this regkey can be found in nv-firmware-registry.h */ #define __NV_ENABLE_GPU_FIRMWARE_LOGS EnableGpuFirmwareLogs #define NV_REG_ENABLE_GPU_FIRMWARE_LOGS NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE_LOGS) -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 - /* * Option: EnableDbgBreakpoint * diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 339d315e9c..cbb37254b3 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -139,9 +139,14 @@ struct semaphore nv_linux_devices_lock; static NvTristate nv_chipset_is_io_coherent = NV_TRISTATE_INDETERMINATE; +NvU64 nv_shared_gpa_boundary = 0; + // True if all the successfully probed devices support ATS // Assigned at device probe (module init) time NvBool nv_ats_supported = NVCPU_IS_PPC64LE +#if defined(NV_PCI_DEV_HAS_ATS_ENABLED) + || NV_TRUE +#endif ; // allow an easy way to convert all debug printfs related to events @@ -232,6 +237,22 @@ struct dev_pm_ops nv_pm_ops = { #if defined(NVCPU_X86_64) #define NV_AMD_SEV_BIT BIT(1) +#define NV_GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +static +void get_shared_gpa_boundary( + void +) +{ + NvU32 priv_high = cpuid_ebx(0x40000003); + if (priv_high & BIT(22)) + { + NvU32 isolation_config_b = cpuid_ebx(0x4000000C); + nv_shared_gpa_boundary = ((NvU64)1) << ((isolation_config_b & NV_GENMASK_ULL(11, 6)) >> 6); + } +} + static NvBool nv_is_sev_supported( void @@ -246,6 +267,11 @@ NvBool nv_is_sev_supported( if (eax < 0x8000001f) return NV_FALSE; + /* By design, a VM using vTOM doesn't see the SEV setting */ + get_shared_gpa_boundary(); + if (nv_shared_gpa_boundary != 0) + return NV_TRUE; + eax = 0x8000001f; ecx = 0; native_cpuid(&eax, &ebx, &ecx, &edx); @@ -274,6 +300,11 @@ void nv_sev_init( #if defined(MSR_AMD64_SEV_ENABLED) os_sev_enabled = (os_sev_status & MSR_AMD64_SEV_ENABLED); #endif + + /* By design, a VM using vTOM doesn't see the SEV setting */ + if (nv_shared_gpa_boundary != 0) + os_sev_enabled = NV_TRUE; + #endif } @@ -1174,6 +1205,7 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) #endif int rc = 0; NvBool kthread_init = NV_FALSE; + NvBool remove_numa_memory_kthread_init = NV_FALSE; NvBool power_ref = NV_FALSE; rc = nv_get_rsync_info(); @@ -1311,6 +1343,15 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) if (rc) goto failed; nv->queue = &nvl->queue; + + if (nv_platform_use_auto_online(nvl)) + { + rc = nv_kthread_q_init(&nvl->remove_numa_memory_q, + "nv_remove_numa_memory"); + if (rc) + goto failed; + remove_numa_memory_kthread_init = NV_TRUE; + } } if (!rm_init_adapter(sp, nv)) @@ -1399,6 +1440,12 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) if (kthread_init && !(nv->flags & NV_FLAG_PERSISTENT_SW_STATE)) nv_kthread_q_stop(&nvl->bottom_half_q); + if (remove_numa_memory_kthread_init && + !(nv->flags & NV_FLAG_PERSISTENT_SW_STATE)) + { + nv_kthread_q_stop(&nvl->remove_numa_memory_q); + } + if (nvl->isr_bh_unlocked_mutex) { os_free_mutex(nvl->isr_bh_unlocked_mutex); @@ -1635,7 +1682,9 @@ void nv_shutdown_adapter(nvidia_stack_t *sp, nv_state_t *nv, nv_linux_state_t *nvl) { +#if defined(NVCPU_PPC64LE) validate_numa_shutdown_state(nvl); +#endif rm_disable_adapter(sp, nv); @@ -1687,6 +1736,9 @@ void nv_shutdown_adapter(nvidia_stack_t *sp, } rm_shutdown_adapter(sp, nv); + + if (nv_platform_use_auto_online(nvl)) + nv_kthread_q_stop(&nvl->remove_numa_memory_q); } /* @@ -2241,6 +2293,7 @@ nvidia_ioctl( } api->status = nv_get_numa_status(nvl); + api->use_auto_online = nv_platform_use_auto_online(nvl); api->memblock_size = nv_ctl_device.numa_memblock_size; break; } @@ -4913,6 +4966,28 @@ NV_STATUS NV_API_CALL nv_get_device_memory_config( status = NV_OK; #endif +#if defined(NVCPU_AARCH64) + if (node_id != NULL) + { + *node_id = nvl->numa_info.node_id; + } + + if (compr_addr_sys_phys) + { + *compr_addr_sys_phys = nvl->coherent_link_info.gpu_mem_pa; + } + if (addr_guest_phys) + { + *addr_guest_phys = nvl->coherent_link_info.gpu_mem_pa; + } + if (addr_width) + { + // TH500 PA width - NV_PFB_PRI_MMU_ATS_ADDR_RANGE_GRANULARITY + *addr_width = 48 - 37; + } + + status = NV_OK; +#endif return status; } @@ -5551,3 +5626,62 @@ void NV_API_CALL nv_get_updated_emu_seg( } } +NV_STATUS NV_API_CALL nv_get_egm_info( + nv_state_t *nv, + NvU64 *phys_addr, + NvU64 *size, + NvS32 *egm_node_id +) +{ +#if defined(NV_DEVICE_PROPERTY_READ_U64_PRESENT) && \ + defined(CONFIG_ACPI_NUMA) && \ + NV_IS_EXPORT_SYMBOL_PRESENT_pxm_to_node + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + NvU64 pa, sz, pxm; + + if (device_property_read_u64(nvl->dev, "nvidia,egm-pxm", &pxm) != 0) + { + goto failed; + } + + if (device_property_read_u64(nvl->dev, "nvidia,egm-base-pa", &pa) != 0) + { + goto failed; + } + + if (device_property_read_u64(nvl->dev, "nvidia,egm-size", &sz) != 0) + { + goto failed; + } + + NV_DEV_PRINTF(NV_DBG_INFO, nv, "DSD properties: \n"); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tEGM base PA: 0x%llx \n", pa); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tEGM size: 0x%llx \n", sz); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tEGM _PXM: 0x%llx \n", pxm); + + if (egm_node_id != NULL) + { + *egm_node_id = pxm_to_node(pxm); + nv_printf(NV_DBG_INFO, "EGM node id: %d\n", *egm_node_id); + } + + if (phys_addr != NULL) + { + *phys_addr = pa; + nv_printf(NV_DBG_INFO, "EGM base addr: 0x%llx\n", *phys_addr); + } + + if (size != NULL) + { + *size = sz; + nv_printf(NV_DBG_INFO, "EGM size: 0x%llx\n", *size); + } + + return NV_OK; + +failed: +#endif // NV_DEVICE_PROPERTY_READ_U64_PRESENT + + NV_DEV_PRINTF(NV_DBG_INFO, nv, "Cannot get EGM info\n"); + return NV_ERR_NOT_SUPPORTED; +} diff --git a/kernel-open/nvidia/nv_gpu_ops.h b/kernel-open/nvidia/nv_gpu_ops.h index 7a5dcadb85..26da9c7b51 100644 --- a/kernel-open/nvidia/nv_gpu_ops.h +++ b/kernel-open/nvidia/nv_gpu_ops.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,6 +39,7 @@ typedef struct gpuSession *gpuSessionHandle; typedef struct gpuDevice *gpuDeviceHandle; typedef struct gpuAddressSpace *gpuAddressSpaceHandle; +typedef struct gpuTsg *gpuTsgHandle; typedef struct gpuChannel *gpuChannelHandle; typedef struct gpuObject *gpuObjectHandle; @@ -97,7 +98,11 @@ NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, NvLength pageCount, NvU64 pageSize); -NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace, +NV_STATUS nvGpuOpsTsgAllocate(gpuAddressSpaceHandle vaSpace, + const gpuTsgAllocParams *params, + gpuTsgHandle *tsgHandle); + +NV_STATUS nvGpuOpsChannelAllocate(const gpuTsgHandle tsgHandle, const gpuChannelAllocParams *params, gpuChannelHandle *channelHandle, gpuChannelInfo *channelInfo); @@ -105,6 +110,8 @@ NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace, NV_STATUS nvGpuOpsMemoryReopen(struct gpuAddressSpace *vaSpace, NvHandle hSrcClient, NvHandle hSrcAllocation, NvLength length, NvU64 *gpuOffset); +void nvGpuOpsTsgDestroy(struct gpuTsg *tsg); + void nvGpuOpsChannelDestroy(struct gpuChannel *channel); void nvGpuOpsMemoryFree(gpuAddressSpaceHandle vaSpace, @@ -196,7 +203,7 @@ NV_STATUS nvGpuOpsGetPmaObject(struct gpuDevice *device, void **pPma, const UvmPmaStatistics **pPmaPubStats); -NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo); +NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo, NvU32 accessCntrIndex); NV_STATUS nvGpuOpsDestroyAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo); @@ -278,4 +285,40 @@ NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel, NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device); +// Interface used for CCSL + +NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx, + gpuChannelHandle channel); +NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx); +NV_STATUS nvGpuOpsCcslLogDeviceEncryption(struct ccslContext_t *ctx, + NvU8 *decryptIv); +NV_STATUS nvGpuOpsCcslAcquireEncryptionIv(struct ccslContext_t *ctx, + NvU8 *encryptIv); +NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, + NvU8 direction); +NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsCcslEncryptWithIv(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsCcslDecrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *authTagBuffer); +NV_STATUS nvGpuOpsCcslSign(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsQueryMessagePool(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum); + #endif /* _NV_GPU_OPS_H_*/ diff --git a/kernel-open/nvidia/nv_uvm_interface.c b/kernel-open/nvidia/nv_uvm_interface.c index 5fd6036367..eaf2a3cf41 100644 --- a/kernel-open/nvidia/nv_uvm_interface.c +++ b/kernel-open/nvidia/nv_uvm_interface.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -435,7 +435,7 @@ EXPORT_SYMBOL(nvUvmInterfacePmaUnregisterEvictionCallbacks); NV_STATUS nvUvmInterfacePmaAllocPages(void *pPma, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, UvmPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages) { @@ -462,7 +462,7 @@ EXPORT_SYMBOL(nvUvmInterfacePmaAllocPages); NV_STATUS nvUvmInterfacePmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags) { nvidia_stack_t *sp = NULL; @@ -483,7 +483,7 @@ EXPORT_SYMBOL(nvUvmInterfacePmaPinPages); NV_STATUS nvUvmInterfacePmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize) + NvU64 pageSize) { nvidia_stack_t *sp = NULL; NV_STATUS status; @@ -516,7 +516,7 @@ EXPORT_SYMBOL(nvUvmInterfaceMemoryFree); void nvUvmInterfacePmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags) { nvidia_stack_t *sp = nvUvmGetSafeStack(); @@ -529,7 +529,7 @@ EXPORT_SYMBOL(nvUvmInterfacePmaFreePages); NV_STATUS nvUvmInterfaceMemoryCpuMap(uvmGpuAddressSpaceHandle vaSpace, UvmGpuPointer gpuPointer, NvLength length, void **cpuPtr, - NvU32 pageSize) + NvU64 pageSize) { nvidia_stack_t *sp = NULL; NV_STATUS status; @@ -557,7 +557,39 @@ void nvUvmInterfaceMemoryCpuUnMap(uvmGpuAddressSpaceHandle vaSpace, } EXPORT_SYMBOL(nvUvmInterfaceMemoryCpuUnMap); -NV_STATUS nvUvmInterfaceChannelAllocate(uvmGpuAddressSpaceHandle vaSpace, +NV_STATUS nvUvmInterfaceTsgAllocate(uvmGpuAddressSpaceHandle vaSpace, + const UvmGpuTsgAllocParams *allocParams, + uvmGpuTsgHandle *tsg) +{ + nvidia_stack_t *sp = NULL; + NV_STATUS status; + + if (nv_kmem_cache_alloc_stack(&sp) != 0) + { + return NV_ERR_NO_MEMORY; + } + + status = rm_gpu_ops_tsg_allocate(sp, + (gpuAddressSpaceHandle)vaSpace, + allocParams, + (gpuTsgHandle *)tsg); + + nv_kmem_cache_free_stack(sp); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceTsgAllocate); + +void nvUvmInterfaceTsgDestroy(uvmGpuTsgHandle tsg) +{ + nvidia_stack_t *sp = nvUvmGetSafeStack(); + rm_gpu_ops_tsg_destroy(sp, (gpuTsgHandle)tsg); + nvUvmFreeSafeStack(sp); +} +EXPORT_SYMBOL(nvUvmInterfaceTsgDestroy); + + +NV_STATUS nvUvmInterfaceChannelAllocate(const uvmGpuTsgHandle tsg, const UvmGpuChannelAllocParams *allocParams, uvmGpuChannelHandle *channel, UvmGpuChannelInfo *channelInfo) @@ -571,7 +603,7 @@ NV_STATUS nvUvmInterfaceChannelAllocate(uvmGpuAddressSpaceHandle vaSpace, } status = rm_gpu_ops_channel_allocate(sp, - (gpuAddressSpaceHandle)vaSpace, + (gpuTsgHandle)tsg, allocParams, (gpuChannelHandle *)channel, channelInfo); @@ -868,7 +900,8 @@ NV_STATUS nvUvmInterfaceInitFaultInfo(uvmGpuDeviceHandle device, EXPORT_SYMBOL(nvUvmInterfaceInitFaultInfo); NV_STATUS nvUvmInterfaceInitAccessCntrInfo(uvmGpuDeviceHandle device, - UvmGpuAccessCntrInfo *pAccessCntrInfo) + UvmGpuAccessCntrInfo *pAccessCntrInfo, + NvU32 accessCntrIndex) { nvidia_stack_t *sp = NULL; NV_STATUS status; @@ -880,7 +913,8 @@ NV_STATUS nvUvmInterfaceInitAccessCntrInfo(uvmGpuDeviceHandle device, status = rm_gpu_ops_init_access_cntr_info(sp, (gpuDeviceHandle)device, - pAccessCntrInfo); + pAccessCntrInfo, + accessCntrIndex); nv_kmem_cache_free_stack(sp); return status; @@ -1432,6 +1466,150 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe } EXPORT_SYMBOL(nvUvmInterfacePagingChannelPushStream); +NV_STATUS nvUvmInterfaceCslInitContext(UvmCslContext *uvmCslContext, + uvmGpuChannelHandle channel) +{ + nvidia_stack_t *sp = NULL; + NV_STATUS status; + + if (nv_kmem_cache_alloc_stack(&sp) != 0) + { + return NV_ERR_NO_MEMORY; + } + + status = rm_gpu_ops_ccsl_context_init(sp, &uvmCslContext->ctx, (gpuChannelHandle)channel); + + // Saving the stack in the context allows UVM to safely use the CSL layer + // in interrupt context without making new allocations. UVM serializes CSL + // API usage for a given context so the stack pointer does not need + // additional protection. + if (status != NV_OK) + { + nv_kmem_cache_free_stack(sp); + } + else + { + uvmCslContext->nvidia_stack = sp; + } + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslInitContext); + +void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext) +{ + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + rm_gpu_ops_ccsl_context_clear(sp, uvmCslContext->ctx); + nvUvmFreeSafeStack(sp); +} +EXPORT_SYMBOL(nvUvmInterfaceDeinitCslContext); + +NV_STATUS nvUvmInterfaceCslLogDeviceEncryption(UvmCslContext *uvmCslContext, + UvmCslIv *decryptIv) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_log_device_encryption(sp, uvmCslContext->ctx, (NvU8 *)decryptIv); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslLogDeviceEncryption); + +NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext, + UvmCslDirection direction) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_rotate_iv(sp, uvmCslContext->ctx, direction); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslRotateIv); + +NV_STATUS nvUvmInterfaceCslAcquireEncryptionIv(UvmCslContext *uvmCslContext, + UvmCslIv *encryptIv) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + BUILD_BUG_ON(NV_OFFSETOF(UvmCslIv, fresh) != sizeof(encryptIv->iv)); + + status = rm_gpu_ops_ccsl_acquire_encryption_iv(sp, uvmCslContext->ctx, (NvU8*)encryptIv); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslAcquireEncryptionIv); + +NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + UvmCslIv *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + if (encryptIv != NULL) + status = rm_gpu_ops_ccsl_encrypt_with_iv(sp, uvmCslContext->ctx, bufferSize, inputBuffer, (NvU8*)encryptIv, outputBuffer, authTagBuffer); + else + status = rm_gpu_ops_ccsl_encrypt(sp, uvmCslContext->ctx, bufferSize, inputBuffer, outputBuffer, authTagBuffer); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslEncrypt); + +NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + UvmCslIv const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *authTagBuffer) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_decrypt(sp, + uvmCslContext->ctx, + bufferSize, + inputBuffer, + (NvU8 *)decryptIv, + outputBuffer, + authTagBuffer); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslDecrypt); + +NV_STATUS nvUvmInterfaceCslSign(UvmCslContext *uvmCslContext, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_sign(sp, uvmCslContext->ctx, bufferSize, inputBuffer, authTagBuffer); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslSign); + +NV_STATUS nvUvmInterfaceCslQueryMessagePool(UvmCslContext *uvmCslContext, + UvmCslDirection direction, + NvU64 *messageNum) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_query_message_pool(sp, uvmCslContext->ctx, direction, messageNum); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslQueryMessagePool); + #else // NV_UVM_ENABLE NV_STATUS nv_uvm_suspend(void) diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild index b147c480d8..1f8ca33e9f 100644 --- a/kernel-open/nvidia/nvidia.Kbuild +++ b/kernel-open/nvidia/nvidia.Kbuild @@ -136,6 +136,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_get_ibm_chip_id NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_bus_address NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_stop_and_remove_bus_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_rebar_get_possible_sizes +NV_CONFTEST_FUNCTION_COMPILE_TESTS += wait_for_random_bytes NV_CONFTEST_FUNCTION_COMPILE_TESTS += register_cpu_notifier NV_CONFTEST_FUNCTION_COMPILE_TESTS += cpuhp_setup_state NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_map_resource @@ -216,6 +217,11 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_i2c_bus_status NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_fuse_control_read NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_get_platform NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pci_find_host_bridge +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_send_cmd +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_set_init_cb +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_clear_init_cb +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_alloc_mem_from_gscco +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_free_gscco_mem NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops @@ -237,6 +243,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += add_memory_driver_managed_has_mhp_flags_arg NV_CONFTEST_TYPE_COMPILE_TESTS += num_registered_fb NV_CONFTEST_TYPE_COMPILE_TESTS += pci_driver_has_driver_managed_dma NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += memory_failure_has_trapno_arg NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build @@ -251,5 +258,7 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += vm_fault_t NV_CONFTEST_GENERIC_COMPILE_TESTS += pci_class_multimedia_hd_audio NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available NV_CONFTEST_GENERIC_COMPILE_TESTS += vfio_pci_core_available +NV_CONFTEST_GENERIC_COMPILE_TESTS += mdev_available NV_CONFTEST_GENERIC_COMPILE_TESTS += cmd_uphy_display_port_init NV_CONFTEST_GENERIC_COMPILE_TESTS += cmd_uphy_display_port_off +NV_CONFTEST_GENERIC_COMPILE_TESTS += memory_failure_mf_sw_simulated_defined \ No newline at end of file diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index 1885030ac8..2466b17685 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -173,7 +173,7 @@ void* NV_API_CALL os_alloc_semaphore return NULL; } - NV_INIT_SEMA(os_sema, initialValue); + sema_init(os_sema, initialValue); return (void *)os_sema; } @@ -1422,8 +1422,7 @@ NV_STATUS NV_API_CALL os_get_euid(NvU32 *pSecToken) return NV_OK; } -// These functions are needed only on x86_64 platforms. -#if defined(NVCPU_X86_64) +#if defined(NVCPU_X86_64) || defined(NVCPU_AARCH64) static NvBool os_verify_checksum(const NvU8 *pMappedAddr, NvU32 length) { @@ -1461,6 +1460,9 @@ static NvBool os_verify_checksum(const NvU8 *pMappedAddr, NvU32 length) static NV_STATUS os_get_smbios_header_legacy(NvU64 *pSmbsAddr) { +#if !defined(NVCPU_X86_64) + return NV_ERR_NOT_SUPPORTED; +#else NV_STATUS status = NV_ERR_OPERATING_SYSTEM; NvU8 *pMappedAddr = NULL; NvU8 *pIterAddr = NULL; @@ -1495,6 +1497,7 @@ static NV_STATUS os_get_smbios_header_legacy(NvU64 *pSmbsAddr) os_unmap_kernel_space(pMappedAddr, SMBIOS_LEGACY_SIZE); return status; +#endif } // This function is needed only if "efi" is enabled. @@ -1571,13 +1574,13 @@ static NV_STATUS os_get_smbios_header_uefi(NvU64 *pSmbsAddr) return status; } -#endif // defined(NVCPU_X86_64) +#endif // defined(NVCPU_X86_64) || defined(NVCPU_AARCH64) // The function locates the SMBIOS entry point. NV_STATUS NV_API_CALL os_get_smbios_header(NvU64 *pSmbsAddr) { -#if !defined(NVCPU_X86_64) +#if !defined(NVCPU_X86_64) && !defined(NVCPU_AARCH64) return NV_ERR_NOT_SUPPORTED; #else NV_STATUS status = NV_OK; @@ -1998,13 +2001,22 @@ NvBool NV_API_CALL os_is_nvswitch_present(void) return !!pci_dev_present(nvswitch_pci_table); } -void NV_API_CALL os_get_random_bytes +/* + * This function may sleep (interruptible). + */ +NV_STATUS NV_API_CALL os_get_random_bytes ( NvU8 *bytes, NvU16 numBytes ) { +#if defined NV_WAIT_FOR_RANDOM_BYTES_PRESENT + if (wait_for_random_bytes() < 0) + return NV_ERR_NOT_READY; +#endif + get_random_bytes(bytes, numBytes); + return NV_OK; } NV_STATUS NV_API_CALL os_alloc_wait_queue @@ -2106,3 +2118,189 @@ void NV_API_CALL os_nv_cap_close_fd nv_cap_close_fd(fd); } +NV_STATUS NV_API_CALL os_numa_add_gpu_memory +( + void *handle, + NvU64 offset, + NvU64 size, + NvU32 *nodeId +) +{ +#if defined(NV_ADD_MEMORY_DRIVER_MANAGED_PRESENT) + int node = 0; + nv_linux_state_t *nvl = pci_get_drvdata(handle); + NvU64 base = offset + nvl->coherent_link_info.gpu_mem_pa; + int ret; + + if (nodeId == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (bitmap_empty(nvl->coherent_link_info.free_node_bitmap, MAX_NUMNODES)) + { + return NV_ERR_IN_USE; + } + node = find_first_bit(nvl->coherent_link_info.free_node_bitmap, MAX_NUMNODES); + if (node == MAX_NUMNODES) + { + return NV_ERR_INVALID_STATE; + } + + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS); + +#ifdef NV_ADD_MEMORY_DRIVER_MANAGED_HAS_MHP_FLAGS_ARG + ret = add_memory_driver_managed(node, base, size, "System RAM (NVIDIA)", MHP_NONE); +#else + ret = add_memory_driver_managed(node, base, size, "System RAM (NVIDIA)"); +#endif + if (ret == 0) + { + struct zone *zone = &NODE_DATA(node)->node_zones[ZONE_MOVABLE]; + NvU64 start_pfn = base >> PAGE_SHIFT; + NvU64 end_pfn = (base + size) >> PAGE_SHIFT; + + if (zone->zone_start_pfn != start_pfn || + zone_end_pfn(zone) != end_pfn) + { + nv_printf(NV_DBG_ERRORS, "GPU memory zone movable auto onlining failed!\n"); +#ifdef NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT +#ifdef NV_REMOVE_MEMORY_HAS_NID_ARG + if (offline_and_remove_memory(node, base, size) != 0) +#else + if (offline_and_remove_memory(base, size) != 0) +#endif + { + nv_printf(NV_DBG_ERRORS, "offline_and_remove_memory failed\n"); + } +#endif + goto failed; + } + + *nodeId = node; + clear_bit(node, nvl->coherent_link_info.free_node_bitmap); + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_ONLINE); + return NV_OK; + } + nv_printf(NV_DBG_ERRORS, "NVRM: Memory add failed. base: 0x%lx size: 0x%lx ret: %d\n", + base, size, ret); +failed: + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_ONLINE_FAILED); + return NV_ERR_OPERATING_SYSTEM; +#endif + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS NV_API_CALL os_numa_remove_gpu_memory +( + void *handle, + NvU64 offset, + NvU64 size, + NvU32 nodeId +) +{ +#ifdef NV_ADD_MEMORY_DRIVER_MANAGED_PRESENT + nv_linux_state_t *nvl = pci_get_drvdata(handle); +#ifdef NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT + NvU64 base = offset + nvl->coherent_link_info.gpu_mem_pa; + remove_numa_memory_info_t numa_info; + nv_kthread_q_item_t remove_numa_memory_q_item; + int ret; +#endif + + if (nodeId >= MAX_NUMNODES) + { + return NV_ERR_INVALID_ARGUMENT; + } + if ((nodeId == NUMA_NO_NODE) || test_bit(nodeId, nvl->coherent_link_info.free_node_bitmap)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS); + +#ifdef NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT + numa_info.base = base; + numa_info.size = size; + numa_info.nodeId = nodeId; + numa_info.ret = 0; + + nv_kthread_q_item_init(&remove_numa_memory_q_item, + offline_numa_memory_callback, + &numa_info); + nv_kthread_q_schedule_q_item(&nvl->remove_numa_memory_q, + &remove_numa_memory_q_item); + nv_kthread_q_flush(&nvl->remove_numa_memory_q); + + ret = numa_info.ret; + + if (ret == 0) + { + set_bit(nodeId, nvl->coherent_link_info.free_node_bitmap); + + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE); + return NV_OK; + } + + nv_printf(NV_DBG_ERRORS, "NVRM: Memory remove failed. base: 0x%lx size: 0x%lx ret: %d\n", + base, size, ret); +#endif + NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED); + return NV_ERR_OPERATING_SYSTEM; +#endif + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS NV_API_CALL os_offline_page_at_address +( + NvU64 address +) +{ +#if defined(CONFIG_MEMORY_FAILURE) + int flags = 0; + int ret; + NvU64 pfn; + struct page *page = NV_GET_PAGE_STRUCT(address); + + if (page == NULL) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Failed to get page struct for address: 0x%llx\n", + address); + return NV_ERR_INVALID_ARGUMENT; + } + + pfn = page_to_pfn(page); + +#ifdef NV_MEMORY_FAILURE_MF_SW_SIMULATED_DEFINED + // + // Set MF_SW_SIMULATED flag so Linux kernel can differentiate this from a HW + // memory failure. HW memory failures cannot be unset via unpoison_memory() API. + // + // Currently, RM does not use unpoison_memory(), so it makes no difference + // whether or not MF_SW_SIMULATED is set. Regardless, it is semantically more + // correct to set MF_SW_SIMULATED. + // + flags |= MF_SW_SIMULATED; +#endif + +#ifdef NV_MEMORY_FAILURE_HAS_TRAPNO_ARG + ret = memory_failure(pfn, 0, flags); +#else + ret = memory_failure(pfn, flags); +#endif + + if (ret != 0) + { + nv_printf(NV_DBG_ERRORS, "NVRM: page offlining failed. address: 0x%llx pfn: 0x%llx ret: %d\n", + address, pfn, ret); + return NV_ERR_OPERATING_SYSTEM; + } + + return NV_OK; +#else // !defined(CONFIG_MEMORY_FAILURE) + nv_printf(NV_DBG_ERRORS, "NVRM: memory_failure() not supported by kernel. page offlining failed. address: 0x%llx\n", + address); + return NV_ERR_NOT_SUPPORTED; +#endif +} + diff --git a/nouveau/extract-firmware-nouveau.py b/nouveau/extract-firmware-nouveau.py new file mode 100755 index 0000000000..837edc8de2 --- /dev/null +++ b/nouveau/extract-firmware-nouveau.py @@ -0,0 +1,342 @@ +#!/usr/bin/env python3 + +# SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: MIT +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +# Converts OpenRM binhex-encoded images to Nouveau-compatible binary blobs +# See nouveau_firmware_layout.ods for documentation on the file format + +import sys +import os +import argparse +import shutil +import re +import gzip +import struct + +class MyException(Exception): + pass + +def round_up_to_base(x, base = 10): + return x + (base - x) % base + +def getbytes(filename, array): + """Extract the bytes for the given array in the given file. + + :param filename: the file to parse + :param array: the name of the array to parse + :returns: byte array + + This function scans the file for the array and returns a bytearray of + its contents, uncompressing the data if it is tagged as compressed. + + This function assumes that each array is immediately preceded with a comment + section that specifies whether the array is compressed and how many bytes of + data there should be. Example: + + #if defined(BINDATA_INCLUDE_DATA) + // + // FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("header_prod") + // FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_prod.h + // FILE TYPE: TEXT + // VAR NAME: securescrub_ucode_header_ad10x_boot_from_hs + // COMPRESSION: YES + // COMPLEX_STRUCT: NO + // DATA SIZE (bytes): 36 + // COMPRESSED SIZE (bytes): 27 + // + static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_header_prod_data[] = + { + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x66, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x30, 0x39, 0x0a, 0xfc, 0x24, 0x00, 0x00, 0x00, + }; + #endif // defined(BINDATA_INCLUDE_DATA) + """ + + with open(filename) as f: + for line in f: + if "COMPRESSION: NO" in line: + compressed = False + if "COMPRESSION: YES" in line: + compressed = True + m = re.search("DATA SIZE \(bytes\): (\d+)", line) + if m: + data_size = int(m.group(1)) + m = re.search("COMPRESSED SIZE \(bytes\): (\d+)", line) + if m: + compressed_size = int(m.group(1)) + if "static BINDATA_CONST NvU8 " + array in line: + break + else: + raise MyException(f"array {array} not found in {filename}") + + output = b'' + for line in f: + if "};" in line: + break + bytes = [int(b, 16) for b in re.findall('0x[0-9a-f][0-9a-f]', line)] + if len(bytes) > 0: + output += struct.pack(f"{len(bytes)}B", *bytes) + + if len(output) == 0: + raise MyException(f"no data found for {array}") + + if compressed: + if len(output) != compressed_size: + raise MyException(f"compressed array {array} in {filename} should be {compressed_size} bytes but is actually {len(output)}.") + gzipheader = struct.pack("<4BL2B", 0x1f, 0x8b, 8, 0, 0, 0, 3) + output = gzip.decompress(gzipheader + output) + if len(output) != data_size: + raise MyException(f"array {array} in {filename} decompressed to {len(output)} bytes but should have been {data_size} bytes.") + return output + else: + if len(output) != data_size: + raise MyException(f"array {array} in {filename} should be {compressed_size} bytes but is actually {len(output)}.") + return output + +# GSP bootloader +def bootloader(gpu, type): + global outputpath + global version + + GPU=gpu.upper() + filename = f"src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_{GPU}.c" + + print(f"Creating nvidia/{gpu}/gsp/bootloader-{version}.bin") + os.makedirs(f"{outputpath}/nvidia/{gpu}/gsp/", exist_ok = True) + + with open(f"{outputpath}/nvidia/{gpu}/gsp/bootloader-{version}.bin", "wb") as f: + # Extract the actual bootloader firmware + array = f"kgspBinArchiveGspRmBoot_{GPU}_ucode_image{type}data" + firmware = getbytes(filename, array) + firmware_size = len(firmware) + + # Extract the descriptor (RM_RISCV_UCODE_DESC) + array = f"kgspBinArchiveGspRmBoot_{GPU}_ucode_desc{type}data" + descriptor = getbytes(filename, array) + descriptor_size = len(descriptor) + + # First, add the nvfw_bin_hdr header + total_size = round_up_to_base(24 + firmware_size + descriptor_size, 256) + firmware_offset = 24 + descriptor_size + f.write(struct.pack("<6L", 0x10de, 1, total_size, 24, firmware_offset, firmware_size)) + + # Second, add the descriptor + f.write(descriptor) + + # Finally, the actual bootloader image + f.write(firmware) + +# GSP Booter load and unload +def booter(gpu, load, sigsize): + global outputpath + global version + + GPU = gpu.upper() + LOAD = load.capitalize() + + filename = f"src/nvidia/generated/g_bindata_kgspGetBinArchiveBooter{LOAD}Ucode_{GPU}.c" + + print(f"Creating nvidia/{gpu}/gsp/booter_{load}-{version}.bin") + os.makedirs(f"{outputpath}/nvidia/{gpu}/gsp/", exist_ok = True) + + with open(f"{outputpath}/nvidia/{gpu}/gsp/booter_{load}-{version}.bin", "wb") as f: + # Extract the actual scrubber firmware + array = f"kgspBinArchiveBooter{LOAD}Ucode_{GPU}_image_prod_data" + firmware = getbytes(filename, array) + firmware_size = len(firmware) + + # Extract the signatures + array = f"kgspBinArchiveBooter{LOAD}Ucode_{GPU}_sig_prod_data" + signatures = getbytes(filename, array) + signatures_size = len(signatures) + if signatures_size % sigsize: + raise MyException(f"signature file size for {array} is uneven value of {sigsize}") + num_sigs = int(signatures_size / sigsize); + if num_sigs < 1: + raise MyException(f"invalid number of signatures {num_sigs}") + + # First, add the nvfw_bin_hdr header + total_size = round_up_to_base(120 + signatures_size + firmware_size, 256) + firmware_offset = 120 + signatures_size + f.write(struct.pack("<6L", 0x10de, 1, total_size, 24, firmware_offset, firmware_size)) + + # Second, add the nvfw_hs_header_v2 header + patch_loc_offset = 60 + signatures_size + patch_sig_offset = patch_loc_offset + 4 + meta_data_offset = patch_sig_offset + 4 + num_sig_offset = meta_data_offset + 12 + header_offset = num_sig_offset + 4 + f.write(struct.pack("<9L", 60, signatures_size, patch_loc_offset, + patch_sig_offset, meta_data_offset, 12, + num_sig_offset, header_offset, 36)) + + # Third, the actual signatures + f.write(signatures) + + # Extract the patch location + array = f"kgspBinArchiveBooter{LOAD}Ucode_{GPU}_patch_loc_data" + bytes = getbytes(filename, array) + patchloc = struct.unpack("FNn ztFkJyDzoazTuWIF90CIb1O@~|FGp50)Q%^L5d;L}pZd26#NOK8+||p`+}P34&f3)2 z)!G5TL!C3XAnbK(652^}3A-5md6{Vy^S z{0BZ`Q&V$0^S_EZ{5Ls?{{yGBy|Jaa3zMj|tG%(K%YT{nKZ*O#f;t)l%>eR=+qnvTv6md@rb|1VA$7?^*V(_hX0Z$bD=*&73_EzDh98J*26W|C(B!OSQj zxBQ{zv+Kf4kdV&QlN~ns{TyN1kWBYkXgj@e$(kx9RTufohjo%{yK&9g*Tw|n(Tx=Y z>g=X86qC|cE$4K+U5p*2TfCd=t#rg$guiTpOY>u9pP~UN7GSqPKY~3mV~!TUC3)TfZd+ z3dh3APlmV#6Lc!djj*LXsPGIFULTAZ^(+M!@f+RI#m%knL?DzM8|?M`ywMNd^-Z<% zzA^Q7TN?SbOO|4k!+N81(Z%QW=kzz@+#lS7`et`=JK@=4%lCxS=6hldsd{BOXqe^~ zt3^mq5RhPS5Rm`zf&a98|MEt2S7Sy`d%IXw1tlOeO3wow=@3T)I#oyu8rjo4x<=x< zY)@_DGm3oA^Q8Ou^KSASgEA73b?$bin=A9;*>!#ap1Z!LQY8xoBM?=Sc4_r&?b*jS z81N=xPE4E%LRou;WF+bvFfSgw?77NI;})AI%FP<{(W~U0rM-3#gA%1jpFKa!1otl2 zOfBgY%WIio-+e#L4t+-tV-at(ih4zyuF!g-8}(3OdiuyN4TpdynK)*hbdc(^IQjWD zt<$+-clX$-TH9iIaAq>wH9G!FKYv5*X$5BLrVM53B|B7Yc!LZRj! zkgp)~I!?Fljji^B(H26&E$T_ITGlFBNd3!!G0;QEj<-iC~ny)_J^#UBCN~oi}xlPR}BLhZyJsPy(d_RUv_iT|fq(T<5 zBfVI1tulD0DO|nS-X50b-k*-bw|;b+=SdOpdt{q9qj6$(bL1M}5`@P@BW$`k?=heBg1Hcae`vE};huzMn!0O7ME4F-?=@m9 z3^m^Bf~*i?g%m`F#!pG>$F2G`NNY3ecy*|&?;fMIcBiqNxKckaIwss64aypxG1NiS zCF*)4>AH|I&-H`TD;w&fwaQ;CP(9vK?y_1oWfoenDaSui+~d4;j_Jz747yFG`OX!t zwDpE8CDd@oTt9o@Y}IppT7fic#XIsNSK=CUWBFC+H+f(&=lB&yhp3@v{!&nxD~ zQsbIng5~_gF;P6ixL;}Xf*cCt?2P4N!%*hY=EKfV6B{(Ule_8kPi6wM*$U`};9Vq! zG3cAre6t#1K32XR7a&Bii$97_2LWOO5!vRV}&8_(o(JZAo+HX7ZNZ z=_Afn7LoJM8mI6e|XdaS3so>XRYAhUHL2X*l6^x3fGlvFA!WND>hACp+A0;gCnC#$;Az(5{bH} zx`&JMXM$Pv4~lM6BnqpqqAf+!iNeQDh&s6B9yC$V@~6p59l^_IFDX~B5HFa=q%nt7 z;yD@-qY-HTe(+b7sur7+a3w>=5JvNYN=cBWWTV{xrfYB}CrwfAY}=!yQe?&xw9>{{Ff zVSPG+w@tjn(~KMkOuIF3!Dy2#G}c3D1KPBOsm-!v6xjrezI<|-@eI~W^= zDz+jDzE@MM!ZZ3X1CF^xz?Vh9E@LhbqLAj&p=prcP#Ht?8ZxB5hPg|K!eniU#^krJ zcvwy|c$H%56=$Zn`jncM@A`embJ6PW=VCNDbS$joV4DJ0)qWcJlVnQy8m9X}9SKJO zZFq)SB2V;HU;3;q)s=iCpOTum)nkk3@us}jY%G}ZRyu;yW*(LrldiTbe(?1`_Tq1W zt!C;9?=GyVV=hx3gIMEz^~l4s#s~D+%7u`3Lr_n{BVHtxRKod~#PogLWS71QDsfUH ze5tecq{YP;jDHG_Py3GpT1^{iy*Rl<@)sdjx5z9u7=8Q%BHh>Cm1(@X$@$8X@-6cS z%>sToU!6f&DKy0fxl`zTbWrK|Oq1Kjr;m9F5XuVzw6`m{!aW$7_g zNgc5Hvw0nRsl6_55T@+L6^?oPUt)`HCdTlN}A4Y<&q9j!p+} ze(laS`u3RMZ0#y`J>K+GgSbM5rd$v{;P{nsT9m(k;AY-+K5ti^nh|-N98iW)-&Wpw zv%EOa*rFD@mgT0WeVJzeZEUUl@O5t$XEB`b-hG2)BhBDqW#z%g!f_IP>t`H?)myc< zg=19H&JGs$mL=4fV6PoP!Kjaw6UULAlj0Y9D)QJxdF4;y()==DTUUN71xU@>nDk@0 z68<42;PUDG9ow?zXo#INB^u8s`-&QK=G>mSu^3qq$h4z(-}TkwFUUJ+>?xQMVDr^@{X6vC2tx_s1!CaBAuRPYVVm_UYiuN>$2xvDi4eME}rZ3{HVei zJ^37pdi43k`nm{ZNhcymv_(*kG8cGC2>8ugiPXu(%6B_`rb!2D3+$4rboQ+}VUF+D zbl;XPEoiRh>HIg|Tc>O`eErR9zb=-`m}x5U#GU?FM_2xdP4sOO53gLxMEUh8f$qJc z;Lfc3^ql3Exnm$VnpDn{@~gmZjDvD2HG%P_Bg=obS}0u{rA5gbQj`sPBJbS( z=hev*Qe*j{SV>!FX`3Q>kDKth5Ga=qPxC_DM;t6aOq)p+pM4Mz{^*mz1McEtga!CO zQ2vutmlZD3W&birE7?Yn%7`~VSsT~m`0`sBw!^oB=7_i96@%|e$N2_4Ynu71Q{~~z z2Xis7ym5_N$FdspQjDZV)y|SIGgNzIUM&-#kjX6JzZ9Y9_90%>_zw^yz2xD?v)b=R zP^qzMAd6xv3u(K8um&X52a;g z&<%-8r!AzkCY8?43`kcN)JWo%+AoPzN&blCAk~sz%JR?+{2t*s9GipDdGM>2<$v0c zqv%>$72-vb_Rb<38W_3YW+4XwM@Fbz40{!=iX?j*tlL+qs6DPotg>I1F-2~5Zl3gez>JIFv$%6uPo3i3FzcIqCMJcb z_a~-FB3;@Yb*{X3F&Fwubi()3s`KRG4Kk=$Vwyff6?TqEKRpGj*Y!fOFPJeE2&Slw113kq8a-C~ z=1M~R?36=&8-_gH+dVwHwe8wO32#QA^z4k-%c+asR(9L|K>q_XQ}PzVnf{_kUj6?T zA^a0yxtP1US_3Tq2WaZ*d2Di{`0pAf4qfJ9;BPiNqIo0iC)qI?;fsD!Zh=*gC&iPS zj@KJ*2)CAIpqP4e`Hai`r1xXPoAbqsb$xT&KWySLBT#YHP!*ysWs@ejAZ6{LMVy&^ zOJ7_YB~Eu`6+x=$T88zL9_9%b9cTQMN22P!QDzl!79N+*1&i~{1tGrgbi7~>Fk`Fv z?RV=&cWkbV|#e3}3lfLGk*~9>UyX+=67y7Fza*et<)EI+W%}tJ* zF&47n#Mr{oZ_L)po81^w!oA|+DR`6SZ($Mv9OH!v9?Jhau%qy(KT7w3FfdW1!F^U|!`!-{~)r$0sEL})^T z)AW&Aj41^sfPz9b#=c+G&Xh!N5VaqW8--0rX!>2x5~&PQ94H1s<}Cs+wgFUu9k>N%^MW15i*h)S>z7+K!ow zAn8w=X``_yMZ)!YwQSt0H3cn8y6j(bX>J-@W1*

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zM@K2*a0pbQN)&H{icWYg2tYhKd0@h*9ghz2o4v*cty}Xw_|%U2N{eO#Fd!ws15J*Fw;s5O#nL$xAIFb5j;+U?5w5QAWq#lrjFVl<~-` zLVIxVLmU%#q#_>9F1M|p@-=;%IpLe$rR3E>$7HmX8o%-wCXLv|t4b5B@a%Fl7DDS$}%U z|5yV2K34@F{tDtKzt1E72IaQ}>wk;V@i!>HEm{8=<(JFp?{N)2{Ld@; zvqkGa>qF9KW6^fPV<-F z>F@Cw>{tPIBK{xu)Bl|HXLqDuRu{jAG}t}kxAEqG&ik{!#$V&CLj9|g(jPPb$$#Vb ziiKcp)<3y%{DJbv)&5y{^h?t9d!(uSgTU)QA^!Y-T)FVVq2 NreL9yzss+){{`MvtlIzp literal 0 HcmV?d00001 diff --git a/src/common/displayport/inc/dp_connectorimpl.h b/src/common/displayport/inc/dp_connectorimpl.h index 496946700a..7920a2710e 100644 --- a/src/common/displayport/inc/dp_connectorimpl.h +++ b/src/common/displayport/inc/dp_connectorimpl.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -125,6 +125,7 @@ namespace DisplayPort bool bPConConnected; // HDMI2.1-Protocol Converter (Support SRC control mode) connected. bool bSkipAssessLinkForPCon; // Skip assessLink() for PCON. DD will call assessFRLLink later. bool bHdcpAuthOnlyOnDemand; // True if only initiate Hdcp authentication on demand and MST won't auto-trigger authenticate at device attach. + bool bReassessMaxLink; // Retry assessLink() if the first assessed link config is lower than the panel max config. bool constructorFailed; @@ -333,6 +334,14 @@ namespace DisplayPort // bool bPowerDownPhyBeforeD3; + // + // Reset the MSTM_CTRL registers on Synaptics branch device irrespective of + // IRQ VECTOR register having stale message. Synaptics device needs to reset + // the topology before issue of new LAM message if previous LAM was not finished + // bug 3928070 + // + bool bForceClearPendingMsg; + void sharedInit(); ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink); diff --git a/src/common/displayport/inc/dp_deviceimpl.h b/src/common/displayport/inc/dp_deviceimpl.h index c0e14f4e57..ef2dd0a264 100644 --- a/src/common/displayport/inc/dp_deviceimpl.h +++ b/src/common/displayport/inc/dp_deviceimpl.h @@ -39,6 +39,7 @@ namespace DisplayPort { #define PREDEFINED_DSC_MST_BPPX16 160; + #define MAX_DSC_COMPRESSION_BPPX16 128; #define HDCP_BCAPS_DDC_OFFSET 0x40 #define HDCP_BCAPS_DDC_EN_BIT 0x80 #define HDCP_BCAPS_DP_EN_BIT 0x01 diff --git a/src/common/displayport/inc/dp_evoadapter.h b/src/common/displayport/inc/dp_evoadapter.h index 733817e2b6..30607f7fb9 100644 --- a/src/common/displayport/inc/dp_evoadapter.h +++ b/src/common/displayport/inc/dp_evoadapter.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -160,6 +160,7 @@ namespace DisplayPort bool _applyLinkBwOverrideWarRegVal; bool _isDynamicMuxCapable; bool _enableMSAOverrideOverMST; + bool _enableFecCheckForDDS; bool _isLTPhyRepeaterSupported; // diff --git a/src/common/displayport/inc/dp_linkconfig.h b/src/common/displayport/inc/dp_linkconfig.h index 0a565fc8c9..c3b8823abf 100644 --- a/src/common/displayport/inc/dp_linkconfig.h +++ b/src/common/displayport/inc/dp_linkconfig.h @@ -36,6 +36,7 @@ #include "ctrl/ctrl0073/ctrl0073specific.h" // NV0073_CTRL_HDCP_VPRIME_SIZE #include "displayport.h" + namespace DisplayPort { typedef NvU64 LinkRate; @@ -45,7 +46,7 @@ namespace DisplayPort public: // Store link rate in multipler of 270MBPS to save space NvU8 element[NV_DPCD_SUPPORTED_LINK_RATES__SIZE]; - NvU8 entries; + NvU8 entries; LinkRates() { @@ -143,18 +144,17 @@ namespace DisplayPort totalUsableTimeslots = totalTimeslots - 1 }; - // in MBps + // in 10bps enum { - RBR = 162000000, - EDP_2_16GHZ = 216000000, - EDP_2_43GHZ = 243000000, - HBR = 270000000, - EDP_3_24GHZ = 324000000, - EDP_4_32GHZ = 432000000, - HBR2 = 540000000, - EDP_6_75GHZ = 675000000, - HBR3 = 810000000 + RBR = 162000000, + EDP_2_16GHZ = 216000000, + EDP_2_43GHZ = 243000000, + HBR = 270000000, + EDP_3_24GHZ = 324000000, + EDP_4_32GHZ = 432000000, + HBR2 = 540000000, + HBR3 = 810000000 }; struct HDCPState diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h index 7e3b11a6b2..ec78f8374c 100644 --- a/src/common/displayport/inc/dp_regkeydatabase.h +++ b/src/common/displayport/inc/dp_regkeydatabase.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,15 +59,25 @@ #define NV_DP_REGKEY_FORCE_EDP_ILR "DP_BYPASS_EDP_ILR_REV_CHECK" +// Regkey to make sure enable FEC only when RM notified sink successfully +#define NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL "DP_DDS_CHECK_FEC_TO_ENABLE" + // Message to power down video stream before power down link (set D3) #define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY" +// +// Regkey to re-assess max link if the first assessed link config +// is lower than the panel max +// +#define NV_DP_REGKEY_REASSESS_MAX_LINK "DP_REASSESS_MAX_LINK" + // // DSC capability of downstream device should be decided based on device's own // and its parent's DSC capability. // #define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315" + // // Data Base used to store all the regkey values. // The actual data base is declared statically in dp_evoadapter.cpp. @@ -100,6 +110,8 @@ struct DP_REGKEY_DATABASE bool bBypassEDPRevCheck; bool bDscMstCapBug3143315; bool bPowerDownPhyBeforeD3; + bool bCheckFECForDynamicMuxDSCPanel; + bool bReassessMaxLink; }; #endif //INCLUDED_DP_REGKEYDATABASE_H diff --git a/src/common/displayport/src/dp_configcaps.cpp b/src/common/displayport/src/dp_configcaps.cpp index 49f156e4c3..ca25affee6 100644 --- a/src/common/displayport/src/dp_configcaps.cpp +++ b/src/common/displayport/src/dp_configcaps.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -739,7 +739,7 @@ struct DPCDHALImpl : DPCDHAL } return bSDPExtnForColorimetry; } - + virtual bool getRootAsyncSDPSupported() { NvU8 byte = 0; @@ -758,7 +758,6 @@ struct DPCDHALImpl : DPCDHAL return true; } - virtual AuxRetry::status setOuiSource(unsigned ouiId, const char * model, size_t modelNameLength, NvU8 chipRevision) { NvU8 ouiBuffer[16]; diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index 244d9a014c..0ad78f8836 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -195,6 +195,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled; this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315; this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3; + this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink; } void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled) @@ -691,6 +692,25 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device, } } + if (newDev->peerDevice == Dongle) + { + // For Dongle, we need to read detailed port caps if DPCD access is available on DP 1.4+. + if (newDev->isAtLeastVersion(1,4)) + { + newDev->getPCONCaps(&(newDev->pconCaps)); + } + + // + // If dongle does not have DPCD access but it is native PCON with Virtual peer support, + // we can get dongle port capabilities from parent VP DPCD detailed port descriptors. + // + else if (newDev->parent && (newDev->parent)->isVirtualPeerDevice()) + { + newDev->parent->getPCONCaps(&(newDev->pconCaps)); + newDev->connectorType = newDev->parent->getConnectorType(); + } + } + // Read panel replay capabilities newDev->getPanelReplayCaps(); @@ -1107,6 +1127,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, { DP_ASSERT( compoundQueryActive ); ModesetInfo localModesetInfo = modesetParams.modesetInfo; + NVT_STATUS result; compoundQueryCount++; @@ -1202,6 +1223,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, NvU64 availableBandwidthBitsPerSecond = 0; unsigned PPS[DSC_MAX_PPS_SIZE_DWORD]; unsigned bitsPerPixelX16 = 0; + bool bDscBppForced = false; if (!pDscParams->bitsPerPixelX16) { @@ -1211,6 +1233,10 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, // pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16; } + else + { + bDscBppForced = true; + } bitsPerPixelX16 = pDscParams->bitsPerPixelX16; @@ -1283,10 +1309,25 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth; warData.connectorType = DSC_DP; - if ((DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, - &warData, availableBandwidthBitsPerSecond, - (NvU32*)(PPS), - (NvU32*)(&bitsPerPixelX16))) != NVT_STATUS_SUCCESS) + result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16)); + + // Try max dsc compression bpp = 8 once to check if that can support that mode. + if (result != NVT_STATUS_SUCCESS && !bDscBppForced) + { + pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16; + + bitsPerPixelX16 = pDscParams->bitsPerPixelX16; + + result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16)); + } + + if (result != NVT_STATUS_SUCCESS) { // // If generating PPS failed @@ -1325,7 +1366,50 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, localModesetInfo.bEnableDsc = true; localModesetInfo.depth = bitsPerPixelX16; - if (dev->devDoingDscDecompression != dev) + if (dev->peerDevice == Dongle && dev->connectorType == connectorHDMI) + { + // + // For DP2HDMI PCON, if FRL BW is available in detailed caps, + // we need to check if we have enough BW for the stream on FRL link. + // + if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0) + { + NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * 1000000000); + if (requiredBW > availableBw) + { + compoundQueryResult = false; + pDscParams->bEnableDsc = false; + return false; + } + } + // + // If DP2HDMI PCON does not support FRL, but advertises TMDS + // Character clock rate on detailed caps, we need to honor that. + // + else if (dev->pconCaps.maxTmdsClkRate != 0) + { + NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate); + NvU64 requireBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + if (modesetParams.colorFormat == dpColorFormat_YCbCr420) + { + if (maxTmdsClkRateU64 < ((requireBw/24)/2)) + { + compoundQueryResult = false; + return false; + } + } + else + { + if (maxTmdsClkRateU64 < (requireBw/24)) + { + compoundQueryResult = false; + return false; + } + } + } + } + else if (dev->devDoingDscDecompression != dev) { // // Device's parent is doing DSC decompression so we need to check @@ -2696,8 +2780,15 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr DP_ASSERT(!this->isLinkQuiesced && "TMDS is attached, NABegin is impossible!"); + // // Update the FEC enabled flag according to the mode requested. + // + // In MST config, if one panel needs DSC/FEC and the other one does not, + // we still need to keep FEC enabled on the connector since at least one + // stream needs it. + // this->bFECEnable |= bEnableFEC; + highestAssessedLC.enableFEC(this->bFECEnable); if (main->isEDP()) @@ -4653,6 +4744,7 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, { LinkTrainingType preferredTrainingType = trainType; bool result; + bool bEnableFecOnSor; // // Validate link config against caps // @@ -4739,14 +4831,21 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, this->hal->setDirtyLinkStatus(true); // We don't need post LQA while powering down the lanes. - if ((lConfig.lanes != 0) && - hal->isPostLtAdjustRequestSupported() && - result) + if ((lConfig.lanes != 0) && hal->isPostLtAdjustRequestSupported() && result) { result = postLTAdjustment(activeLinkConfig, force); } - if((lConfig.lanes != 0) && result && lConfig.bEnableFEC) + bEnableFecOnSor = lConfig.bEnableFEC; + + if (main->isEDP()) + { + DeviceImpl * nativeDev = findDeviceInList(Address()); + if (nativeDev && nativeDev->bIsPreviouslyFakedMuxDevice) + bEnableFecOnSor = activeLinkConfig.bEnableFEC; + } + + if((lConfig.lanes != 0) && result && bEnableFecOnSor) { // // Extended latency from link-train end to FEC enable pattern @@ -4762,7 +4861,14 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, DP_ASSERT(result); } - if (lConfig != activeLinkConfig) + // + // Do not compare bEnableFEC here. In DDS case FEC might be requested but + // not performed in RM. + // + if ((lConfig.lanes != activeLinkConfig.lanes) || + (lConfig.peakRate != activeLinkConfig.peakRate) || + (lConfig.enhancedFraming != activeLinkConfig.enhancedFraming) || + (lConfig.multistream != activeLinkConfig.multistream)) { // fallback happens, returns fail to make sure clients notice it. result = false; @@ -5763,7 +5869,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) discoveryManager = new DiscoveryManager(messageManager, this, timer, hal); // Check and clear if any pending message here - if (hal->clearPendingMsg()) + if (hal->clearPendingMsg() || bForceClearPendingMsg) { DP_LOG(("DP> Stale MSG found: set branch to D3 and back to D0...")); if (hal->isAtLeastVersion(1, 4)) @@ -5930,11 +6036,13 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) bPConConnected = true; } + LinkConfiguration maxLinkConfig = getMaxLinkConfig(); + if (bPConConnected || (main->isEDP() && this->bSkipAssessLinkForEDP) || (main->isInternalPanelDynamicMuxCapable())) { - this->highestAssessedLC = getMaxLinkConfig(); + this->highestAssessedLC = maxLinkConfig; this->linkGuessed = bPConConnected; this->bSkipAssessLinkForPCon = bPConConnected; } @@ -5949,6 +6057,22 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) hal->setPowerState(PowerStateD0); } this->assessLink(); + + if (this->bReassessMaxLink) + { + // + // If the highest assessed LC is not equal to + // max possible link config, re-assess link + // + NvU8 retries = 0U; + + while((retries < WAR_MAX_REASSESS_ATTEMPT) && (highestAssessedLC != maxLinkConfig)) + { + DP_LOG(("DP> Assessed link is not equal to highest possible config. Reassess link.")); + this->assessLink(); + retries++; + } + } } if (hal->getLegacyPortCount() != 0) @@ -6806,6 +6930,7 @@ bool ConnectorImpl::updatePsrLinkState(bool bTrainLink) { // Bug 3438892 If the panel is turned off the reciever on its side, // force panel link on by writting 600 = 1 + this->hal->setDirtyLinkStatus(true); if (this->isLinkLost()) { hal->setPowerState(PowerStateD0); @@ -6969,5 +7094,6 @@ void ConnectorImpl::configInit() bNoFallbackInPostLQA = 0; LT2FecLatencyMs = 0; bDscCapBasedOnParent = false; + bForceClearPendingMsg = false; } diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp index 09b04fbc49..7600a342ab 100644 --- a/src/common/displayport/src/dp_deviceimpl.cpp +++ b/src/common/displayport/src/dp_deviceimpl.cpp @@ -929,7 +929,7 @@ void DeviceImpl::applyOUIOverrides() // color formats that are listed in 0x69h even in pass through mode. // this->bDscPassThroughColorFormatWar = true; - + if ((buffer[8] == 0x31) || (buffer[8] == 0x20)) { this->bSdpExtCapable = False; @@ -957,7 +957,7 @@ void DeviceImpl::applyOUIOverrides() bool DeviceImpl::getAsyncSDPSupported() { NvU8 byte = 0; - unsigned size = 0; + unsigned size = 1; unsigned sizeCompleted; unsigned nakReason = NakUndefined; // @@ -2102,7 +2102,7 @@ bool DeviceImpl::setDscEnable(bool enable) return false; } - if ((this->devDoingDscDecompression == this) && !this->isLogical() && this->parent != NULL) + if ((this->devDoingDscDecompression == this) && !this->isLogical() && !(this->peerDevice == Dongle) && this->parent != NULL) { // // If the device has a parent, that means the sink is on a MST link and @@ -2414,51 +2414,76 @@ AuxBus::status DeviceImpl::dscCrcControl(NvBool bEnable, gpuDscCrc *gpuData, sin bool DeviceImpl::getPCONCaps(PCONCaps *pPCONCaps) { AuxBus::status status = AuxBus::success; - NvU32 addr = NV_DPCD_DETAILED_CAP_INFO_ONE(0); - NvU8 data = 0; - unsigned size = 1; + NvU32 addr = NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT(0); + NvU8 data[4] = {0}; unsigned sizeCompleted = 0; unsigned nakReason = 0; + NvU8 pConType = 0; - if (isMultistream()) - return false; - - status = getDpcdData(addr, &data, size, &sizeCompleted, &nakReason); - if (status != AuxBus::success) + status = this->getDpcdData(addr, &data[0], sizeof(data), &sizeCompleted, &nakReason); + if (status == AuxBus::success) { - return false; - } - pPCONCaps->maxTmdsClkRate = data; + pConType = DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _DWNSTRM_PORT_TX_TYPE, data[0]); + if (pConType == NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_HDMI) + { + this->connectorType = connectorHDMI; + pPCONCaps->maxTmdsClkRate = data[1] * 2500000; - addr = NV_DPCD_DETAILED_CAP_INFO_TWO(0); - status = getDpcdData(addr, &data, size, &sizeCompleted, &nakReason); - if (status != AuxBus::success) - { - return false; - } + pPCONCaps->bSourceControlModeSupported = + FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _SRC_CONTROL_MODE_SUPPORT, _YES, data[2]); + pPCONCaps->bConcurrentLTSupported = + FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _CONCURRENT_LT_SUPPORT, _YES, data[2]); - pPCONCaps->bSourceControlModeSupported = - FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _SRC_CONTROL_MODE_SUPPORT, _YES, data); - pPCONCaps->bConcurrentLTSupported = - FLD_TEST_DRF(_DPCD, _DETAILED_CAP_INFO, _CONCURRENT_LT_SUPPORT, _YES, data); - pPCONCaps->maxHdmiLinkBandwidthGbps = - DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_FRL_LINK_BW_SUPPORT, data); + switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_FRL_LINK_BW_SUPPORT, data[2])) + { + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_9G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 9; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_18G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 18; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_24G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 24; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_32G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 32; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_40G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 40; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_FRL_LINK_BW_SUPPORT_48G: + pPCONCaps->maxHdmiLinkBandwidthGbps = 48; + break; + default: + pPCONCaps->maxHdmiLinkBandwidthGbps = 0; + break; + } + + switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_BITS_PER_COMPONENT_DEF, data[2])) + { + case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_10BPC: + pPCONCaps->maxBpc = 10; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_12BPC: + pPCONCaps->maxBpc = 12; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_16BPC: + pPCONCaps->maxBpc = 16; + break; + case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_8BPC: + default: + pPCONCaps->maxBpc = 8; + break; + } - switch (DRF_VAL(_DPCD, _DETAILED_CAP_INFO, _MAX_BITS_PER_COMPONENT_DEF, data)) + DP_LOG((" DP2HDMI PCON caps - Max TMDS Clk: %u LinkBWGbps: %u MaxBpc: %u", + pPCONCaps->maxTmdsClkRate, pPCONCaps->maxHdmiLinkBandwidthGbps, pPCONCaps->maxBpc)); + } + } + else { - case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_10BPC: - pPCONCaps->maxBpc = 10; - break; - case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_12BPC: - pPCONCaps->maxBpc = 12; - break; - case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_16BPC: - pPCONCaps->maxBpc = 16; - break; - case NV_DPCD_DETAILED_CAP_INFO_MAX_BITS_PER_COMPONENT_DEF_8BPC: - default: - pPCONCaps->maxBpc = 8; - break; + DP_LOG((" DP-DEV> Error - DPCD Read for detailed port capabilities (0x80) failed.")); + return false; } return true; } diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp index ebc306347e..f380248ab5 100644 --- a/src/common/displayport/src/dp_evoadapter.cpp +++ b/src/common/displayport/src/dp_evoadapter.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,7 +40,6 @@ #include #include #include - using namespace DisplayPort; // @@ -94,7 +93,9 @@ const struct {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, - {NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL} + {NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL, &dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel, DP_REG_VAL_BOOL}, + {NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL}, + {NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL} }; EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) : @@ -892,6 +893,7 @@ void EvoMainLink::applyRegkeyOverrides() _skipPowerdownEDPPanelWhenHeadDetach = dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped; _applyLinkBwOverrideWarRegVal = dpRegkeyDatabase.bLinkBwOverrideWarApplied; _enableMSAOverrideOverMST = dpRegkeyDatabase.bMsaOverMstEnabled; + _enableFecCheckForDDS = dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel; } NvU32 EvoMainLink::getRegkeyValue(const char *key) @@ -1043,7 +1045,6 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force, case EDP_3_24GHZ: case EDP_4_32GHZ: case HBR2: - case EDP_6_75GHZ: case HBR3: linkBw = linkrate / DP_LINK_BW_FREQ_MULTI_MBPS; dpCtrlData = FLD_SET_DRF_NUM(0073_CTRL, _DP_DATA, _SET_LINK_BW, @@ -1160,7 +1161,7 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force, // if (!requestRmLC.lowerConfig()) { - // If no valid link config could be found, break here. + // If no valid link config could be found, break here. break; } fallback = true; @@ -1235,6 +1236,16 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force, retLink->setLaneRate(requestRmLC.peakRate, result ? requestRmLC.lanes : 0); retLink->setLTCounter(ltCounter); + // For release branch only, check FEC return values and update to "retLink" + if (_enableFecCheckForDDS) + { + if (requestRmLC.bEnableFEC && (FLD_TEST_DRF(0073_CTRL_DP, _ERR, _ENABLE_FEC, _ERR, err))) + { + retLink->bEnableFEC = false; + DP_ASSERT(0); + } + } + NV_DPTRACE_INFO(LINK_TRAINING_DONE, status, requestRmLC.peakRate, requestRmLC.lanes); return result; @@ -1797,7 +1808,6 @@ bool EvoMainLink::configureLinkRateTable case linkBW_3_24Gbps: case linkBW_4_32Gbps: case linkBW_5_40Gbps: - case linkBW_6_75Gbps: case linkBW_8_10Gbps: pLinkRates->import(params.linkBwTbl[i]); break; diff --git a/src/common/displayport/src/dp_wardatabase.cpp b/src/common/displayport/src/dp_wardatabase.cpp index f4e6c483ef..6ad8c947c6 100644 --- a/src/common/displayport/src/dp_wardatabase.cpp +++ b/src/common/displayport/src/dp_wardatabase.cpp @@ -84,6 +84,17 @@ void ConnectorImpl::applyOuiWARs() // LT2FecLatencyMs = 57; + // + // This is to reset the MSTM control bit on the branch device. On this + // device, if continuous LAM message are sent very close then IRQ vector + // will fail to see stale/pending message and will not reset the MSTM_CTRL + // register. Currently making this specific to linux so as to have minimum + // effect on windows. Later proper fix for this will be generic. + // +#if defined(NV_UNIX) + bForceClearPendingMsg = true; +#endif + if (bDscMstCapBug3143315) { // diff --git a/src/common/inc/displayport/displayport.h b/src/common/inc/displayport/displayport.h index 5e582dc6c4..393a3e8c13 100644 --- a/src/common/inc/displayport/displayport.h +++ b/src/common/inc/displayport/displayport.h @@ -97,6 +97,7 @@ typedef enum typedef enum { + // enum value unit = 270M linkBW_1_62Gbps = 0x06, linkBW_2_16Gbps = 0x08, linkBW_2_43Gbps = 0x09, @@ -104,7 +105,6 @@ typedef enum linkBW_3_24Gbps = 0x0C, linkBW_4_32Gbps = 0x10, linkBW_5_40Gbps = 0x14, - linkBW_6_75Gbps = 0x19, linkBW_8_10Gbps = 0x1E, linkBW_Supported } DP_LINK_BANDWIDTH; @@ -119,11 +119,9 @@ typedef enum linkSpeedId_2_43Gbps = 0x05, linkSpeedId_3_24Gbps = 0x06, linkSpeedId_4_32Gbps = 0x07, - linkSpeedId_6_75Gbps = 0x08, linkSpeedId_Supported } DP_LINK_SPEED_INDEX; - typedef enum { postCursor2_Level0 = 0, @@ -291,7 +289,7 @@ typedef struct NvBool bSourceControlModeSupported; NvBool bConcurrentLTSupported; NvBool bConv444To420Supported; - NvU8 maxTmdsClkRate; + NvU32 maxTmdsClkRate; NvU8 maxBpc; NvU8 maxHdmiLinkBandwidthGbps; } PCONCaps; @@ -477,7 +475,7 @@ typedef struct // Multiplier constant to get link frequency in KHZ // Maximum link rate of Main Link lanes = Value x 270M. // To get it to KHz unit, we need to multiply 270K. -#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000) +#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000) // Multiplier constant to get link rate table's in KHZ #define DP_LINK_RATE_TABLE_MULTIPLIER_KHZ 200 @@ -553,11 +551,11 @@ typedef struct #define IS_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \ ((NvU32)(val)==linkBW_2_43Gbps) || \ ((NvU32)(val)==linkBW_3_24Gbps) || \ - ((NvU32)(val)==linkBW_4_32Gbps) || \ - ((NvU32)(val)==linkBW_6_75Gbps)) + ((NvU32)(val)==linkBW_4_32Gbps)) -#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \ +#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \ IS_INTERMEDIATE_LINKBW(val)) + // // Phy Repeater count read from DPCD offset F0002h is an // 8 bit value where each bit represents the total count diff --git a/src/common/inc/gps.h b/src/common/inc/gps.h index 671b0ebbcd..357ec3529a 100644 --- a/src/common/inc/gps.h +++ b/src/common/inc/gps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,6 +43,8 @@ #define GPS_FUNC_GETPPM 0x00000028 // Get system power modes #define GPS_FUNC_SETPPM 0x00000029 // Set system power modes #define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities +#define GPS_FUNC_SETEDPPLIMITINFO 0x0000002B // Send the GPU EDPPeak limit info to platform +#define GPS_FUNC_GETEDPPLIMIT 0x0000002C // Get EDPPeak limit from platform #define GPS_EVENT_STATUS_CHANGE 0x000000C0 // when received call GPS_FUNC_PCONTROL, // depends on whether system is GPS enabled. diff --git a/src/common/inc/jt.h b/src/common/inc/jt.h index d832df8b4e..3e526c8385 100644 --- a/src/common/inc/jt.h +++ b/src/common/inc/jt.h @@ -90,5 +90,26 @@ #define NV_JT_FUNC_CAPS_REVISION_ID_1_03 0x00000103 #define NV_JT_FUNC_CAPS_REVISION_ID_2_00 0x00000200 +// +// JT_FUNC_POWERCONTROL argument definitions (Rev 1.0) +// + +// +// GPU Power Control +// +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_CONTROL 2:0 +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_CONTROL_GSS 0x00000000 +// +// JT_FUNC_POWERCONTROL return buffer definitions +// +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE 2:0 +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_TRANSITION 0x00000000 +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_ON 0x00000001 +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_OFF 0x00000002 +#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_GC6 0x00000003 +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE 3:3 +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE_OFF 0x00000000 +#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE_PWOK 0x00000001 + #endif // JT_H diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index 7d5d721a50..cef8c9ef4c 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,26 +36,26 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r531_37 + #define NV_BUILD_BRANCH r535_87 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r531_37 + #define NV_PUBLIC_BRANCH r535_87 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r530/r531_37-121" -#define NV_BUILD_CHANGELIST_NUM (32603126) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r535_87-122" +#define NV_BUILD_CHANGELIST_NUM (32882771) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r530/r531_37-121" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32603126) +#define NV_BUILD_NAME "rel/gpu_drv/r535/r535_87-122" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32882771) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r531_37-1" -#define NV_BUILD_CHANGELIST_NUM (32601466) +#define NV_BUILD_BRANCH_VERSION "r535_87-4" +#define NV_BUILD_CHANGELIST_NUM (32875904) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "531.40" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32601466) -#define NV_BUILD_BRANCH_BASE_VERSION R530 +#define NV_BUILD_NAME "535.93" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32875904) +#define NV_BUILD_BRANCH_BASE_VERSION R535 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvSemaphoreCommon.h b/src/common/inc/nvSemaphoreCommon.h index 9179007a28..fad269f3ed 100644 --- a/src/common/inc/nvSemaphoreCommon.h +++ b/src/common/inc/nvSemaphoreCommon.h @@ -63,23 +63,23 @@ ct_assert(sizeof(NvReportSemaphore) == 16); * the CPU or submitted to be written by the GPU, which is stashed in the * timestamp field of the semaphore by the CPU in both these cases. */ -static inline void NvTimeSemFermiSetMaxSubmitted( - NvReportSemaphore32 *report, +static inline void NvTimeSemFermiSetMaxSubmittedVal( + volatile NvU64 *maxSubmittedPtr, const NvU64 value) { NvU64 oldValue = - (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer, + (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)maxSubmittedPtr, 0, 0); // Atomically set report->timer to max(value, report->time). while (oldValue < value) { const NvU64 prevValue = - (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer, + (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)maxSubmittedPtr, (NvS64)value, (NvS64)oldValue); if (prevValue == oldValue) { // The specified value was set. Done. - nvAssert(report->timer >= value); + nvAssert(*maxSubmittedPtr >= value); break; } @@ -87,6 +87,13 @@ static inline void NvTimeSemFermiSetMaxSubmitted( } } +static inline void NvTimeSemFermiSetMaxSubmitted( + NvReportSemaphore32 *report, + const NvU64 value) +{ + NvTimeSemFermiSetMaxSubmittedVal(&report->timer, value); +} + static inline NvU64 NvTimeSemFermiGetPayload( NvReportSemaphore32 *report) { @@ -150,7 +157,7 @@ static inline void NvTimeSemFermiSetPayload( const NvU64 payload) { // First save the actual value to the reserved/timer bits - NvTimeSemFermiSetMaxSubmitted(report, payload); + NvTimeSemFermiSetMaxSubmittedVal(&report->timer, payload); // Then write the low bits to the GPU-accessible semaphore value. report->payload = (NvU32)(payload & 0xFFFFFFFFULL); diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index a6ef8083a0..ab79fca6e9 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "530.41.03" +#define NV_VERSION_STRING "535.43.02" #else diff --git a/src/common/inc/swref/published/disp/v03_00/dev_disp.h b/src/common/inc/swref/published/disp/v03_00/dev_disp.h index 9b655541e9..79cf7a2c86 100644 --- a/src/common/inc/swref/published/disp/v03_00/dev_disp.h +++ b/src/common/inc/swref/published/disp/v03_00/dev_disp.h @@ -70,4 +70,8 @@ #define NV_PDISP_RG_DPCA_FRM_CNT 31:16 /* R--UF */ #define NV_PDISP_FE_FLIPLOCK 0x0061206C /* RW-4R */ #define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME 23:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */ #endif // __v03_00_dev_disp_h__ diff --git a/src/common/inc/swref/published/disp/v04_00/dev_disp.h b/src/common/inc/swref/published/disp/v04_00/dev_disp.h index 68e068d59c..6fa443759f 100644 --- a/src/common/inc/swref/published/disp/v04_00/dev_disp.h +++ b/src/common/inc/swref/published/disp/v04_00/dev_disp.h @@ -37,9 +37,18 @@ #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* R--VF */ #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* R---V */ #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* R---V */ -#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */ -#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */ -#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */ -#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */ - +#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */ +#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */ +#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */ +#define NV_PDISP_FE_CORE_HEAD_STATE(i) (0x00612078+(i)*2048) /* R--4A */ +#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE 9:8 /* R--VF */ +#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_SLEEP 0x00000000 /* R---V */ +#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_SNOOZE 0x00000001 /* R---V */ +#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_AWAKE 0x00000002 /* R---V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(i) (0x00611D80+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */ #endif // __v04_00_dev_disp_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fb.h b/src/common/inc/swref/published/hopper/gh100/dev_fb.h index 8bcb21316b..e40d088f00 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_fb.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_fb.h @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef __gh100_dev_fb_h +#ifndef __gh100_dev_fb_h_ #define __gh100_dev_fb_h_ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00100A34 /* RW-4R */ @@ -29,4 +29,4 @@ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */ -#endif // __gh100_dev_fb_h__ +#endif // __gh100_dev_fb_h_ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h new file mode 100644 index 0000000000..12cff251e5 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_fsp_addendum_h__ +#define __gh100_dev_fsp_addendum_h__ + +#define NV_GFW_FSP_UCODE_VERSION NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(1) +#define NV_GFW_FSP_UCODE_VERSION_FULL 11:0 +#define NV_GFW_FSP_UCODE_VERSION_MAJOR 11:8 +#define NV_GFW_FSP_UCODE_VERSION_MINOR 7:0 + +#endif // __gh100_dev_fsp_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h b/src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h index 6debb1627d..22d217203b 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -64,5 +64,9 @@ #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */ #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x008f0330+(i)*4) /* RW-4A */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #endif // __gh100_dev_fsp_pri_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fuse.h b/src/common/inc/swref/published/hopper/gh100/dev_fuse.h new file mode 100644 index 0000000000..5199f7d7d6 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_fuse.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_fuse_h__ +#define __gh100_dev_fuse_h__ + +#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */ +#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */ +#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */ +#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */ +#define NV_FUSE_SPARE_BIT_0 0x00824E04 /* RW-4R */ +#define NV_FUSE_SPARE_BIT_0_DATA 0:0 /* RWIVF */ +#define NV_FUSE_SPARE_BIT_0_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_FUSE_SPARE_BIT_0_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_FUSE_SPARE_BIT_0_DATA_ENABLE 0x00000001 /* RW--V */ +#define NV_FUSE_SPARE_BIT_1 0x00824E08 /* RW-4R */ +#define NV_FUSE_SPARE_BIT_1_DATA 0:0 /* RWIVF */ +#define NV_FUSE_SPARE_BIT_1_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_FUSE_SPARE_BIT_1_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_FUSE_SPARE_BIT_1_DATA_ENABLE 0x00000001 /* RW--V */ +#define NV_FUSE_SPARE_BIT_2 0x00824E0C /* RW-4R */ +#define NV_FUSE_SPARE_BIT_2_DATA 0:0 /* RWIVF */ +#define NV_FUSE_SPARE_BIT_2_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_FUSE_SPARE_BIT_2_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_FUSE_SPARE_BIT_2_DATA_ENABLE 0x00000001 /* RW--V */ +#define NV_FUSE_SPARE_BIT_3 0x00824E10 /* RW-4R */ +#define NV_FUSE_SPARE_BIT_3_DATA 0:0 /* RWIVF */ +#define NV_FUSE_SPARE_BIT_3_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_FUSE_SPARE_BIT_3_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_FUSE_SPARE_BIT_3_DATA_ENABLE 0x00000001 /* RW--V */ + +#endif // __gh100_dev_fuse_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h b/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h index fec06073b3..b11501a3db 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,14 @@ #ifndef __gh100_dev_gc6_island_h__ #define __gh100_dev_gc6_island_h__ +#define NV_PGC6_SCI_SEC_TIMER_TIME_0 0x00118f54 /* RW-4R */ +#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC 31:5 /* RWEUF */ +#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC_ZERO 0x00000000 /* RWE-V */ + +#define NV_PGC6_SCI_SEC_TIMER_TIME_1 0x00118f58 /* RW-4R */ +#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC 28:0 /* RWEUF */ +#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC_ZERO 0x00000000 /* RWE-V */ + #define NV_PGC6_SCI_SYS_TIMER_OFFSET_0 0x00118df4 /* RW-4R */ #define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE 0:0 /* RWEVF */ #define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE_DONE 0x00000000 /* R-E-V */ @@ -33,5 +41,8 @@ #define NV_PGC6_SCI_SYS_TIMER_OFFSET_1 0x00118df8 /* RW-4R */ #define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC 28:0 /* RWEUF */ #define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC_ZERO 0x00000000 /* RWE-V */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20 0x001182cc /* RW-4R */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA 31:0 /* RWIVF */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA_INIT 0x00000000 /* RWI-V */ #endif // __gh100_dev_gc6_island_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h index 5242524957..4dda835047 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h @@ -26,4 +26,12 @@ #define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1 +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0 + #endif // __gh100_dev_gc6_island_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_vm.h b/src/common/inc/swref/published/hopper/gh100/dev_vm.h index c306501237..396debdfeb 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_vm.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_vm.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -46,5 +46,19 @@ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 16 /* */ #define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i) (0x2300+(i)*4) /* RW-4A */ #define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1 2 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */ #endif // __gh100_dev_vm_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h index edb6dbe5e3..da4eb85031 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h @@ -50,4 +50,8 @@ // #define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT 0x00000081 +#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO +#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE +#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI + #endif // __gh100_dev_vm_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h index bd968a72f0..d602d66411 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h @@ -27,11 +27,20 @@ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE 1:1 /* RWIVF */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_DEFAULT 0x00000000 /* RWI-V */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_ENABLE 0x00000001 /* RW--V */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER 2:2 /* RWIVF */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_DISABLE 0x00000000 /* RWI-V */ +#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_ENABLE 0x00000001 /* RW--V */ #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE 0x00000008 /* R--4R */ #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_PGM_INTERFACE 15:8 /* R-IVF */ #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_SUB_CLASSCODE 23:16 /* R-IVF */ #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE 31:24 /* R-IVF */ #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE_3D 0x00000003 /* R-I-V */ +#define NV_EP_PCFG_GPU_BARREG0 0x00000010 /* RW-4R */ +#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS 31:18 /* RWIVF */ +#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_EP_PCFG_GPU_SUBSYSTEM_ID 0x0000002C /* R--4R */ #define NV_EP_PCFG_GPU_MSI_64_HEADER 0x00000048 /* RW-4R */ #define NV_EP_PCFG_GPU_MSI_64_HEADER_MSI_ENABLE 16:16 /* RWIVF */ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h b/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h index dc23abd45e..c4342f1677 100644 --- a/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h +++ b/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h @@ -31,9 +31,18 @@ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE 0:0 /* RWIVF */ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE_ENABLED 0x00000001 /* RW--V */ +#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE 1:1 /* RWIVF */ +#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */ +#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */ +#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER 2:2 /* RWIVF */ +#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */ +#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_REV_ID 0x00000008 /* R--4R */ #define NV_XVE_REV_ID_CLASS_CODE 31:8 /* R-CVF */ #define NV_XVE_REV_ID_CLASS_CODE_3D 0x00030200 /* ----V */ +#define NV_XVE_BAR0 0x00000010 /* RW-4R */ +#define NV_XVE_BAR0_BASE_ADDRESS 31:24 /* RWIVF */ +#define NV_XVE_BAR0_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_SUBSYSTEM 0x0000002C /* R--4R */ #define NV_XVE_MSI_CTRL 0x00000068 /* RW-4R */ #define NV_XVE_MSI_CTRL_MSI 16:16 /* RWIVF */ diff --git a/src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip_addendum.h b/src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip_addendum.h index 62a015e70b..905afce563 100644 --- a/src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip_addendum.h +++ b/src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip_addendum.h @@ -12,17 +12,13 @@ * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * - * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. */ #ifndef __lr10_dev_minion_ip_addendum_h__ #define __lr10_dev_minion_ip_addendum_h__ + +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITRXTXTERM 0x12 + #define NV_NVLSTAT 0x00000103:0x00000000 /* RW--D */ #define NV_NVLSTAT_UC01 0x00000001 /* R--4R */ #define NV_NVLSTAT_UC01_PM_STATE 31:31 /* R---F */ diff --git a/src/common/mbedtls/gpl-2.0.txt b/src/common/mbedtls/gpl-2.0.txt new file mode 100644 index 0000000000..d159169d10 --- /dev/null +++ b/src/common/mbedtls/gpl-2.0.txt @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/src/common/mbedtls/include/mbedtls/aes.h b/src/common/mbedtls/include/mbedtls/aes.h new file mode 100644 index 0000000000..9adf00be53 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/aes.h @@ -0,0 +1,685 @@ +/** + * \file aes.h + * + * \brief This file contains AES definitions and functions. + * + * The Advanced Encryption Standard (AES) specifies a FIPS-approved + * cryptographic algorithm that can be used to protect electronic + * data. + * + * The AES algorithm is a symmetric block cipher that can + * encrypt and decrypt information. For more information, see + * FIPS Publication 197: Advanced Encryption Standard and + * ISO/IEC 18033-2:2006: Information technology -- Security + * techniques -- Encryption algorithms -- Part 2: Asymmetric + * ciphers. + * + * The AES-XTS block mode is standardized by NIST SP 800-38E + * + * and described in detail by IEEE P1619 + * . + */ + +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_AES_H +#define MBEDTLS_AES_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include + +/* padlock.c and aesni.c rely on these values! */ +#define MBEDTLS_AES_ENCRYPT 1 /**< AES encryption. */ +#define MBEDTLS_AES_DECRYPT 0 /**< AES decryption. */ + +/* Error codes in range 0x0020-0x0022 */ +#define MBEDTLS_ERR_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ +#define MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ + +/* Error codes in range 0x0021-0x0025 */ +#define MBEDTLS_ERR_AES_BAD_INPUT_DATA -0x0021 /**< Invalid input data. */ + +/* MBEDTLS_ERR_AES_FEATURE_UNAVAILABLE is deprecated and should not be used. */ +#define MBEDTLS_ERR_AES_FEATURE_UNAVAILABLE -0x0023 /**< Feature not available. For example, an unsupported AES key size. */ + +/* MBEDTLS_ERR_AES_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_AES_HW_ACCEL_FAILED -0x0025 /**< AES hardware accelerator failed. */ + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_AES_ALT) +// Regular implementation +// + +/** + * \brief The AES context-type definition. + */ +typedef struct mbedtls_aes_context +{ + int nr; /*!< The number of rounds. */ + uint32_t *rk; /*!< AES round keys. */ + uint32_t buf[68]; /*!< Unaligned data buffer. This buffer can + hold 32 extra Bytes, which can be used for + one of the following purposes: +

*/ +} +mbedtls_aes_context; + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief The AES XTS context-type definition. + */ +typedef struct mbedtls_aes_xts_context +{ + mbedtls_aes_context crypt; /*!< The AES context to use for AES block + encryption or decryption. */ + mbedtls_aes_context tweak; /*!< The AES context used for tweak + computation. */ +} mbedtls_aes_xts_context; +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#else /* MBEDTLS_AES_ALT */ +#include "aes_alt.h" +#endif /* MBEDTLS_AES_ALT */ + +/** + * \brief This function initializes the specified AES context. + * + * It must be the first API called before using + * the context. + * + * \param ctx The AES context to initialize. This must not be \c NULL. + */ +void mbedtls_aes_init( mbedtls_aes_context *ctx ); + +/** + * \brief This function releases and clears the specified AES context. + * + * \param ctx The AES context to clear. + * If this is \c NULL, this function does nothing. + * Otherwise, the context must have been at least initialized. + */ +void mbedtls_aes_free( mbedtls_aes_context *ctx ); + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief This function initializes the specified AES XTS context. + * + * It must be the first API called before using + * the context. + * + * \param ctx The AES XTS context to initialize. This must not be \c NULL. + */ +void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx ); + +/** + * \brief This function releases and clears the specified AES XTS context. + * + * \param ctx The AES XTS context to clear. + * If this is \c NULL, this function does nothing. + * Otherwise, the context must have been at least initialized. + */ +void mbedtls_aes_xts_free( mbedtls_aes_xts_context *ctx ); +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/** + * \brief This function sets the encryption key. + * + * \param ctx The AES context to which the key should be bound. + * It must be initialized. + * \param key The encryption key. + * This must be a readable buffer of size \p keybits bits. + * \param keybits The size of data passed in bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ); + +/** + * \brief This function sets the decryption key. + * + * \param ctx The AES context to which the key should be bound. + * It must be initialized. + * \param key The decryption key. + * This must be a readable buffer of size \p keybits bits. + * \param keybits The size of data passed. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ); + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief This function prepares an XTS context for encryption and + * sets the encryption key. + * + * \param ctx The AES XTS context to which the key should be bound. + * It must be initialized. + * \param key The encryption key. This is comprised of the XTS key1 + * concatenated with the XTS key2. + * This must be a readable buffer of size \p keybits bits. + * \param keybits The size of \p key passed in bits. Valid options are: + *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • + *
  • 512 bits (each of key1 and key2 is a 256-bit key)
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief This function prepares an XTS context for decryption and + * sets the decryption key. + * + * \param ctx The AES XTS context to which the key should be bound. + * It must be initialized. + * \param key The decryption key. This is comprised of the XTS key1 + * concatenated with the XTS key2. + * This must be a readable buffer of size \p keybits bits. + * \param keybits The size of \p key passed in bits. Valid options are: + *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • + *
  • 512 bits (each of key1 and key2 is a 256-bit key)
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits ); +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/** + * \brief This function performs an AES single-block encryption or + * decryption operation. + * + * It performs the operation defined in the \p mode parameter + * (encrypt or decrypt), on the input data buffer defined in + * the \p input parameter. + * + * mbedtls_aes_init(), and either mbedtls_aes_setkey_enc() or + * mbedtls_aes_setkey_dec() must be called before the first + * call to this API with the same context. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT. + * \param input The buffer holding the input data. + * It must be readable and at least \c 16 Bytes long. + * \param output The buffer where the output data will be written. + * It must be writeable and at least \c 16 Bytes long. + + * \return \c 0 on success. + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief This function performs an AES-CBC encryption or decryption operation + * on full blocks. + * + * It performs the operation defined in the \p mode + * parameter (encrypt/decrypt), on the input data buffer defined in + * the \p input parameter. + * + * It can be called as many times as needed, until all the input + * data is processed. mbedtls_aes_init(), and either + * mbedtls_aes_setkey_enc() or mbedtls_aes_setkey_dec() must be called + * before the first call to this API with the same context. + * + * \note This function operates on full blocks, that is, the input size + * must be a multiple of the AES block size of \c 16 Bytes. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the next + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If you need to retain the contents of the IV, you should + * either save it manually or use the cipher module instead. + * + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT. + * \param length The length of the input data in Bytes. This must be a + * multiple of the block size (\c 16 Bytes). + * \param iv Initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH + * on failure. + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief This function performs an AES-XTS encryption or decryption + * operation for an entire XTS data unit. + * + * AES-XTS encrypts or decrypts blocks based on their location as + * defined by a data unit number. The data unit number must be + * provided by \p data_unit. + * + * NIST SP 800-38E limits the maximum size of a data unit to 2^20 + * AES blocks. If the data unit is larger than this, this function + * returns #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH. + * + * \param ctx The AES XTS context to use for AES XTS operations. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT. + * \param length The length of a data unit in Bytes. This can be any + * length between 16 bytes and 2^24 bytes inclusive + * (between 1 and 2^20 block cipher blocks). + * \param data_unit The address of the data unit encoded as an array of 16 + * bytes in little-endian format. For disk encryption, this + * is typically the index of the block device sector that + * contains the data. + * \param input The buffer holding the input data (which is an entire + * data unit). This function reads \p length Bytes from \p + * input. + * \param output The buffer holding the output data (which is an entire + * data unit). This function writes \p length Bytes to \p + * output. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH if \p length is + * smaller than an AES block in size (16 Bytes) or if \p + * length is larger than 2^20 blocks (16 MiB). + */ +int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx, + int mode, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/** + * \brief This function performs an AES-CFB128 encryption or decryption + * operation. + * + * It performs the operation defined in the \p mode + * parameter (encrypt or decrypt), on the input data buffer + * defined in the \p input parameter. + * + * For CFB, you must set up the context with mbedtls_aes_setkey_enc(), + * regardless of whether you are performing an encryption or decryption + * operation, that is, regardless of the \p mode parameter. This is + * because CFB mode uses the same key schedule for encryption and + * decryption. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the next + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If you need to retain the contents of the + * IV, you must either save it manually or use the cipher + * module instead. + * + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT. + * \param length The length of the input data in Bytes. + * \param iv_off The offset in IV (updated after use). + * It must point to a valid \c size_t. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function performs an AES-CFB8 encryption or decryption + * operation. + * + * It performs the operation defined in the \p mode + * parameter (encrypt/decrypt), on the input data buffer defined + * in the \p input parameter. + * + * Due to the nature of CFB, you must use the same key schedule for + * both encryption and decryption operations. Therefore, you must + * use the context initialized with mbedtls_aes_setkey_enc() for + * both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the next + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT + * \param length The length of the input data. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +/** + * \brief This function performs an AES-OFB (Output Feedback Mode) + * encryption or decryption operation. + * + * For OFB, you must set up the context with + * mbedtls_aes_setkey_enc(), regardless of whether you are + * performing an encryption or decryption operation. This is + * because OFB mode uses the same key schedule for encryption and + * decryption. + * + * The OFB operation is identical for encryption or decryption, + * therefore no operation mode needs to be specified. + * + * \note Upon exit, the content of iv, the Initialisation Vector, is + * updated so that you can call the same function again on the next + * block(s) of data and get the same result as if it was encrypted + * in one call. This allows a "streaming" usage, by initialising + * iv_off to 0 before the first call, and preserving its value + * between calls. + * + * For non-streaming use, the iv should be initialised on each call + * to a unique value, and iv_off set to 0 on each call. + * + * If you need to retain the contents of the initialisation vector, + * you must either save it manually or use the cipher module + * instead. + * + * \warning For the OFB mode, the initialisation vector must be unique + * every encryption operation. Reuse of an initialisation vector + * will compromise security. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param length The length of the input data. + * \param iv_off The offset in IV (updated after use). + * It must point to a valid \c size_t. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +int mbedtls_aes_crypt_ofb( mbedtls_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/** + * \brief This function performs an AES-CTR encryption or decryption + * operation. + * + * This function performs the operation defined in the \p mode + * parameter (encrypt/decrypt), on the input data buffer + * defined in the \p input parameter. + * + * Due to the nature of CTR, you must use the same key schedule + * for both encryption and decryption operations. Therefore, you + * must use the context initialized with mbedtls_aes_setkey_enc() + * for both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT. + * + * \warning You must never reuse a nonce value with the same key. Doing so + * would void the encryption for the two messages encrypted with + * the same nonce and key. + * + * There are two common strategies for managing nonces with CTR: + * + * 1. You can handle everything as a single message processed over + * successive calls to this function. In that case, you want to + * set \p nonce_counter and \p nc_off to 0 for the first call, and + * then preserve the values of \p nonce_counter, \p nc_off and \p + * stream_block across calls to this function as they will be + * updated by this function. + * + * With this strategy, you must not encrypt more than 2**128 + * blocks of data with the same key. + * + * 2. You can encrypt separate messages by dividing the \p + * nonce_counter buffer in two areas: the first one used for a + * per-message nonce, handled by yourself, and the second one + * updated by this function internally. + * + * For example, you might reserve the first 12 bytes for the + * per-message nonce, and the last 4 bytes for internal use. In that + * case, before calling this function on a new message you need to + * set the first 12 bytes of \p nonce_counter to your chosen nonce + * value, the last 4 to 0, and \p nc_off to 0 (which will cause \p + * stream_block to be ignored). That way, you can encrypt at most + * 2**96 messages of up to 2**32 blocks each with the same key. + * + * The per-message nonce (or information sufficient to reconstruct + * it) needs to be communicated with the ciphertext and must be unique. + * The recommended way to ensure uniqueness is to use a message + * counter. An alternative is to generate random nonces, but this + * limits the number of messages that can be securely encrypted: + * for example, with 96-bit random nonces, you should not encrypt + * more than 2**32 messages with the same key. + * + * Note that for both stategies, sizes are measured in blocks and + * that an AES block is 16 bytes. + * + * \warning Upon return, \p stream_block contains sensitive data. Its + * content must not be written to insecure storage and should be + * securely discarded as soon as it's no longer needed. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param length The length of the input data. + * \param nc_off The offset in the current \p stream_block, for + * resuming within the current cipher stream. The + * offset pointer should be 0 at the start of a stream. + * It must point to a valid \c size_t. + * \param nonce_counter The 128-bit nonce and counter. + * It must be a readable-writeable buffer of \c 16 Bytes. + * \param stream_block The saved stream block for resuming. This is + * overwritten by the function. + * It must be a readable-writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +/** + * \brief Internal AES block encryption function. This is only + * exposed to allow overriding it using + * \c MBEDTLS_AES_ENCRYPT_ALT. + * + * \param ctx The AES context to use for encryption. + * \param input The plaintext block. + * \param output The output (ciphertext) block. + * + * \return \c 0 on success. + */ +int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +/** + * \brief Internal AES block decryption function. This is only + * exposed to allow overriding it using see + * \c MBEDTLS_AES_DECRYPT_ALT. + * + * \param ctx The AES context to use for decryption. + * \param input The ciphertext block. + * \param output The output (plaintext) block. + * + * \return \c 0 on success. + */ +int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief Deprecated internal AES block encryption function + * without return value. + * + * \deprecated Superseded by mbedtls_internal_aes_encrypt() + * + * \param ctx The AES context to use for encryption. + * \param input Plaintext block. + * \param output Output (ciphertext) block. + */ +MBEDTLS_DEPRECATED void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +/** + * \brief Deprecated internal AES block decryption function + * without return value. + * + * \deprecated Superseded by mbedtls_internal_aes_decrypt() + * + * \param ctx The AES context to use for decryption. + * \param input Ciphertext block. + * \param output Output (plaintext) block. + */ +MBEDTLS_DEPRECATED void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_aes_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* aes.h */ diff --git a/src/common/mbedtls/include/mbedtls/asn1.h b/src/common/mbedtls/include/mbedtls/asn1.h new file mode 100644 index 0000000000..eac58c4ba7 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/asn1.h @@ -0,0 +1,368 @@ +/** + * \file asn1.h + * + * \brief Generic ASN.1 parsing + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_ASN1_H +#define MBEDTLS_ASN1_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include + +#if defined(MBEDTLS_BIGNUM_C) +#include "bignum.h" +#endif + +/** + * \addtogroup asn1_module + * \{ + */ + +/** + * \name ASN1 Error codes + * These error codes are OR'ed to X509 error codes for + * higher error granularity. + * ASN1 is a standard to specify data structures. + * \{ + */ +#define MBEDTLS_ERR_ASN1_OUT_OF_DATA -0x0060 /**< Out of data when parsing an ASN1 data structure. */ +#define MBEDTLS_ERR_ASN1_UNEXPECTED_TAG -0x0062 /**< ASN1 tag was of an unexpected value. */ +#define MBEDTLS_ERR_ASN1_INVALID_LENGTH -0x0064 /**< Error when trying to determine the length or invalid length. */ +#define MBEDTLS_ERR_ASN1_LENGTH_MISMATCH -0x0066 /**< Actual length differs from expected length. */ +#define MBEDTLS_ERR_ASN1_INVALID_DATA -0x0068 /**< Data is invalid. (not used) */ +#define MBEDTLS_ERR_ASN1_ALLOC_FAILED -0x006A /**< Memory allocation failed */ +#define MBEDTLS_ERR_ASN1_BUF_TOO_SMALL -0x006C /**< Buffer too small when writing ASN.1 data structure. */ + +/* \} name */ + +/** + * \name DER constants + * These constants comply with the DER encoded ASN.1 type tags. + * DER encoding uses hexadecimal representation. + * An example DER sequence is:\n + * - 0x02 -- tag indicating INTEGER + * - 0x01 -- length in octets + * - 0x05 -- value + * Such sequences are typically read into \c ::mbedtls_x509_buf. + * \{ + */ +#define MBEDTLS_ASN1_BOOLEAN 0x01 +#define MBEDTLS_ASN1_INTEGER 0x02 +#define MBEDTLS_ASN1_BIT_STRING 0x03 +#define MBEDTLS_ASN1_OCTET_STRING 0x04 +#define MBEDTLS_ASN1_NULL 0x05 +#define MBEDTLS_ASN1_OID 0x06 +#define MBEDTLS_ASN1_UTF8_STRING 0x0C +#define MBEDTLS_ASN1_SEQUENCE 0x10 +#define MBEDTLS_ASN1_SET 0x11 +#define MBEDTLS_ASN1_PRINTABLE_STRING 0x13 +#define MBEDTLS_ASN1_T61_STRING 0x14 +#define MBEDTLS_ASN1_IA5_STRING 0x16 +#define MBEDTLS_ASN1_UTC_TIME 0x17 +#define MBEDTLS_ASN1_GENERALIZED_TIME 0x18 +#define MBEDTLS_ASN1_UNIVERSAL_STRING 0x1C +#define MBEDTLS_ASN1_BMP_STRING 0x1E +#define MBEDTLS_ASN1_PRIMITIVE 0x00 +#define MBEDTLS_ASN1_CONSTRUCTED 0x20 +#define MBEDTLS_ASN1_CONTEXT_SPECIFIC 0x80 + +/* + * Bit masks for each of the components of an ASN.1 tag as specified in + * ITU X.690 (08/2015), section 8.1 "General rules for encoding", + * paragraph 8.1.2.2: + * + * Bit 8 7 6 5 1 + * +-------+-----+------------+ + * | Class | P/C | Tag number | + * +-------+-----+------------+ + */ +#define MBEDTLS_ASN1_TAG_CLASS_MASK 0xC0 +#define MBEDTLS_ASN1_TAG_PC_MASK 0x20 +#define MBEDTLS_ASN1_TAG_VALUE_MASK 0x1F + +/* \} name */ +/* \} addtogroup asn1_module */ + +/** Returns the size of the binary string, without the trailing \\0 */ +#define MBEDTLS_OID_SIZE(x) (sizeof(x) - 1) + +/** + * Compares an mbedtls_asn1_buf structure to a reference OID. + * + * Only works for 'defined' oid_str values (MBEDTLS_OID_HMAC_SHA1), you cannot use a + * 'unsigned char *oid' here! + */ +#define MBEDTLS_OID_CMP(oid_str, oid_buf) \ + ( ( MBEDTLS_OID_SIZE(oid_str) != (oid_buf)->len ) || \ + memcmp( (oid_str), (oid_buf)->p, (oid_buf)->len) != 0 ) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name Functions to parse ASN.1 data structures + * \{ + */ + +/** + * Type-length-value structure that allows for ASN1 using DER. + */ +typedef struct mbedtls_asn1_buf +{ + int tag; /**< ASN1 type, e.g. MBEDTLS_ASN1_UTF8_STRING. */ + size_t len; /**< ASN1 length, in octets. */ + unsigned char *p; /**< ASN1 data, e.g. in ASCII. */ +} +mbedtls_asn1_buf; + +/** + * Container for ASN1 bit strings. + */ +typedef struct mbedtls_asn1_bitstring +{ + size_t len; /**< ASN1 length, in octets. */ + unsigned char unused_bits; /**< Number of unused bits at the end of the string */ + unsigned char *p; /**< Raw ASN1 data for the bit string */ +} +mbedtls_asn1_bitstring; + +/** + * Container for a sequence of ASN.1 items + */ +typedef struct mbedtls_asn1_sequence +{ + mbedtls_asn1_buf buf; /**< Buffer containing the given ASN.1 item. */ + struct mbedtls_asn1_sequence *next; /**< The next entry in the sequence. */ +} +mbedtls_asn1_sequence; + +/** + * Container for a sequence or list of 'named' ASN.1 data items + */ +typedef struct mbedtls_asn1_named_data +{ + mbedtls_asn1_buf oid; /**< The object identifier. */ + mbedtls_asn1_buf val; /**< The named value. */ + struct mbedtls_asn1_named_data *next; /**< The next entry in the sequence. */ + unsigned char next_merged; /**< Merge next item into the current one? */ +} +mbedtls_asn1_named_data; + +/** + * \brief Get the length of an ASN.1 element. + * Updates the pointer to immediately behind the length. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param len The variable that will receive the value + * + * \return 0 if successful, MBEDTLS_ERR_ASN1_OUT_OF_DATA on reaching + * end of data, MBEDTLS_ERR_ASN1_INVALID_LENGTH if length is + * unparseable. + */ +int mbedtls_asn1_get_len( unsigned char **p, + const unsigned char *end, + size_t *len ); + +/** + * \brief Get the tag and length of the tag. Check for the requested tag. + * Updates the pointer to immediately behind the tag and length. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param len The variable that will receive the length + * \param tag The expected tag + * + * \return 0 if successful, MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if tag did + * not match requested tag, or another specific ASN.1 error code. + */ +int mbedtls_asn1_get_tag( unsigned char **p, + const unsigned char *end, + size_t *len, int tag ); + +/** + * \brief Retrieve a boolean ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param val The variable that will receive the value + * + * \return 0 if successful or a specific ASN.1 error code. + */ +int mbedtls_asn1_get_bool( unsigned char **p, + const unsigned char *end, + int *val ); + +/** + * \brief Retrieve an integer ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param val The variable that will receive the value + * + * \return 0 if successful or a specific ASN.1 error code. + */ +int mbedtls_asn1_get_int( unsigned char **p, + const unsigned char *end, + int *val ); + +/** + * \brief Retrieve a bitstring ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param bs The variable that will receive the value + * + * \return 0 if successful or a specific ASN.1 error code. + */ +int mbedtls_asn1_get_bitstring( unsigned char **p, const unsigned char *end, + mbedtls_asn1_bitstring *bs); + +/** + * \brief Retrieve a bitstring ASN.1 tag without unused bits and its + * value. + * Updates the pointer to the beginning of the bit/octet string. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param len Length of the actual bit/octect string in bytes + * + * \return 0 if successful or a specific ASN.1 error code. + */ +int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end, + size_t *len ); + +/** + * \brief Parses and splits an ASN.1 "SEQUENCE OF " + * Updated the pointer to immediately behind the full sequence tag. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param cur First variable in the chain to fill + * \param tag Type of sequence + * + * \return 0 if successful or a specific ASN.1 error code. + */ +int mbedtls_asn1_get_sequence_of( unsigned char **p, + const unsigned char *end, + mbedtls_asn1_sequence *cur, + int tag); + +#if defined(MBEDTLS_BIGNUM_C) +/** + * \brief Retrieve a MPI value from an integer ASN.1 tag. + * Updates the pointer to immediately behind the full tag. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param X The MPI that will receive the value + * + * \return 0 if successful or a specific ASN.1 or MPI error code. + */ +int mbedtls_asn1_get_mpi( unsigned char **p, + const unsigned char *end, + mbedtls_mpi *X ); +#endif /* MBEDTLS_BIGNUM_C */ + +/** + * \brief Retrieve an AlgorithmIdentifier ASN.1 sequence. + * Updates the pointer to immediately behind the full + * AlgorithmIdentifier. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param alg The buffer to receive the OID + * \param params The buffer to receive the params (if any) + * + * \return 0 if successful or a specific ASN.1 or MPI error code. + */ +int mbedtls_asn1_get_alg( unsigned char **p, + const unsigned char *end, + mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params ); + +/** + * \brief Retrieve an AlgorithmIdentifier ASN.1 sequence with NULL or no + * params. + * Updates the pointer to immediately behind the full + * AlgorithmIdentifier. + * + * \param p The position in the ASN.1 data + * \param end End of data + * \param alg The buffer to receive the OID + * + * \return 0 if successful or a specific ASN.1 or MPI error code. + */ +int mbedtls_asn1_get_alg_null( unsigned char **p, + const unsigned char *end, + mbedtls_asn1_buf *alg ); + +/** + * \brief Find a specific named_data entry in a sequence or list based on + * the OID. + * + * \param list The list to seek through + * \param oid The OID to look for + * \param len Size of the OID + * + * \return NULL if not found, or a pointer to the existing entry. + */ +mbedtls_asn1_named_data *mbedtls_asn1_find_named_data( mbedtls_asn1_named_data *list, + const char *oid, size_t len ); + +/** + * \brief Free a mbedtls_asn1_named_data entry + * + * \param entry The named data entry to free + */ +void mbedtls_asn1_free_named_data( mbedtls_asn1_named_data *entry ); + +/** + * \brief Free all entries in a mbedtls_asn1_named_data list + * Head will be set to NULL + * + * \param head Pointer to the head of the list of named data entries to free + */ +void mbedtls_asn1_free_named_data_list( mbedtls_asn1_named_data **head ); + +#ifdef __cplusplus +} +#endif + +#endif /* asn1.h */ diff --git a/src/common/mbedtls/include/mbedtls/asn1write.h b/src/common/mbedtls/include/mbedtls/asn1write.h new file mode 100644 index 0000000000..95d86df3ed --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/asn1write.h @@ -0,0 +1,339 @@ +/** + * \file asn1write.h + * + * \brief ASN.1 buffer writing functionality + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_ASN1_WRITE_H +#define MBEDTLS_ASN1_WRITE_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "asn1.h" + +#define MBEDTLS_ASN1_CHK_ADD(g, f) \ + do \ + { \ + if( ( ret = (f) ) < 0 ) \ + return( ret ); \ + else \ + (g) += ret; \ + } while( 0 ) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Write a length field in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param len The length value to write. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_len( unsigned char **p, unsigned char *start, + size_t len ); +/** + * \brief Write an ASN.1 tag in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param tag The tag to write. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_tag( unsigned char **p, unsigned char *start, + unsigned char tag ); + +/** + * \brief Write raw buffer data. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param buf The data buffer to write. + * \param size The length of the data buffer. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_raw_buffer( unsigned char **p, unsigned char *start, + const unsigned char *buf, size_t size ); + +#if defined(MBEDTLS_BIGNUM_C) +/** + * \brief Write a arbitrary-precision number (#MBEDTLS_ASN1_INTEGER) + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param X The MPI to write. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_mpi( unsigned char **p, unsigned char *start, + const mbedtls_mpi *X ); +#endif /* MBEDTLS_BIGNUM_C */ + +/** + * \brief Write a NULL tag (#MBEDTLS_ASN1_NULL) with zero data + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_null( unsigned char **p, unsigned char *start ); + +/** + * \brief Write an OID tag (#MBEDTLS_ASN1_OID) and data + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param oid The OID to write. + * \param oid_len The length of the OID. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_oid( unsigned char **p, unsigned char *start, + const char *oid, size_t oid_len ); + +/** + * \brief Write an AlgorithmIdentifier sequence in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param oid The OID of the algorithm to write. + * \param oid_len The length of the algorithm's OID. + * \param par_len The length of the parameters, which must be already written. + * If 0, NULL parameters are added + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_algorithm_identifier( unsigned char **p, + unsigned char *start, + const char *oid, size_t oid_len, + size_t par_len ); + +/** + * \brief Write a boolean tag (#MBEDTLS_ASN1_BOOLEAN) and value + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param boolean The boolean value to write, either \c 0 or \c 1. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_bool( unsigned char **p, unsigned char *start, + int boolean ); + +/** + * \brief Write an int tag (#MBEDTLS_ASN1_INTEGER) and value + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param val The integer value to write. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_int( unsigned char **p, unsigned char *start, int val ); + +/** + * \brief Write a string in ASN.1 format using a specific + * string encoding tag. + + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param tag The string encoding tag to write, e.g. + * #MBEDTLS_ASN1_UTF8_STRING. + * \param text The string to write. + * \param text_len The length of \p text in bytes (which might + * be strictly larger than the number of characters). + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_tagged_string( unsigned char **p, unsigned char *start, + int tag, const char *text, + size_t text_len ); + +/** + * \brief Write a string in ASN.1 format using the PrintableString + * string encoding tag (#MBEDTLS_ASN1_PRINTABLE_STRING). + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param text The string to write. + * \param text_len The length of \p text in bytes (which might + * be strictly larger than the number of characters). + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_printable_string( unsigned char **p, + unsigned char *start, + const char *text, size_t text_len ); + +/** + * \brief Write a UTF8 string in ASN.1 format using the UTF8String + * string encoding tag (#MBEDTLS_ASN1_PRINTABLE_STRING). + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param text The string to write. + * \param text_len The length of \p text in bytes (which might + * be strictly larger than the number of characters). + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_utf8_string( unsigned char **p, unsigned char *start, + const char *text, size_t text_len ); + +/** + * \brief Write a string in ASN.1 format using the IA5String + * string encoding tag (#MBEDTLS_ASN1_IA5_STRING). + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param text The string to write. + * \param text_len The length of \p text in bytes (which might + * be strictly larger than the number of characters). + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_ia5_string( unsigned char **p, unsigned char *start, + const char *text, size_t text_len ); + +/** + * \brief Write a bitstring tag (#MBEDTLS_ASN1_BIT_STRING) and + * value in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param buf The bitstring to write. + * \param bits The total number of bits in the bitstring. + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_bitstring( unsigned char **p, unsigned char *start, + const unsigned char *buf, size_t bits ); + +/** + * \brief Write an octet string tag (#MBEDTLS_ASN1_OCTET_STRING) + * and value in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param buf The buffer holding the data to write. + * \param size The length of the data buffer \p buf. + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_octet_string( unsigned char **p, unsigned char *start, + const unsigned char *buf, size_t size ); + +/** + * \brief Create or find a specific named_data entry for writing in a + * sequence or list based on the OID. If not already in there, + * a new entry is added to the head of the list. + * Warning: Destructive behaviour for the val data! + * + * \param list The pointer to the location of the head of the list to seek + * through (will be updated in case of a new entry). + * \param oid The OID to look for. + * \param oid_len The size of the OID. + * \param val The data to store (can be \c NULL if you want to fill + * it by hand). + * \param val_len The minimum length of the data buffer needed. + * + * \return A pointer to the new / existing entry on success. + * \return \c NULL if if there was a memory allocation error. + */ +mbedtls_asn1_named_data *mbedtls_asn1_store_named_data( mbedtls_asn1_named_data **list, + const char *oid, size_t oid_len, + const unsigned char *val, + size_t val_len ); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_ASN1_WRITE_H */ diff --git a/src/common/mbedtls/include/mbedtls/base64.h b/src/common/mbedtls/include/mbedtls/base64.h new file mode 100644 index 0000000000..ae82d541b4 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/base64.h @@ -0,0 +1,108 @@ +/** + * \file base64.h + * + * \brief RFC 1521 base64 encoding/decoding + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_BASE64_H +#define MBEDTLS_BASE64_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include + +#define MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL -0x002A /**< Output buffer too small. */ +#define MBEDTLS_ERR_BASE64_INVALID_CHARACTER -0x002C /**< Invalid character in input. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Encode a buffer into base64 format + * + * \param dst destination buffer + * \param dlen size of the destination buffer + * \param olen number of bytes written + * \param src source buffer + * \param slen amount of data to be encoded + * + * \return 0 if successful, or MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL. + * *olen is always updated to reflect the amount + * of data that has (or would have) been written. + * If that length cannot be represented, then no data is + * written to the buffer and *olen is set to the maximum + * length representable as a size_t. + * + * \note Call this function with dlen = 0 to obtain the + * required buffer size in *olen + */ +int mbedtls_base64_encode( unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen ); + +/** + * \brief Decode a base64-formatted buffer + * + * \param dst destination buffer (can be NULL for checking size) + * \param dlen size of the destination buffer + * \param olen number of bytes written + * \param src source buffer + * \param slen amount of data to be decoded + * + * \return 0 if successful, MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL, or + * MBEDTLS_ERR_BASE64_INVALID_CHARACTER if the input data is + * not correct. *olen is always updated to reflect the amount + * of data that has (or would have) been written. + * + * \note Call this function with *dst = NULL or dlen = 0 to obtain + * the required buffer size in *olen + */ +int mbedtls_base64_decode( unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen ); + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_base64_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* base64.h */ diff --git a/src/common/mbedtls/include/mbedtls/bignum.h b/src/common/mbedtls/include/mbedtls/bignum.h new file mode 100644 index 0000000000..805f13f0c3 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/bignum.h @@ -0,0 +1,987 @@ +/** + * \file bignum.h + * + * \brief Multi-precision integer library + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_BIGNUM_H +#define MBEDTLS_BIGNUM_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include + +#if defined(MBEDTLS_FS_IO) +#include +#endif + +#define MBEDTLS_ERR_MPI_FILE_IO_ERROR -0x0002 /**< An error occurred while reading from or writing to a file. */ +#define MBEDTLS_ERR_MPI_BAD_INPUT_DATA -0x0004 /**< Bad input parameters to function. */ +#define MBEDTLS_ERR_MPI_INVALID_CHARACTER -0x0006 /**< There is an invalid character in the digit string. */ +#define MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL -0x0008 /**< The buffer is too small to write to. */ +#define MBEDTLS_ERR_MPI_NEGATIVE_VALUE -0x000A /**< The input arguments are negative or result in illegal output. */ +#define MBEDTLS_ERR_MPI_DIVISION_BY_ZERO -0x000C /**< The input argument for division is zero, which is not allowed. */ +#define MBEDTLS_ERR_MPI_NOT_ACCEPTABLE -0x000E /**< The input arguments are not acceptable. */ +#define MBEDTLS_ERR_MPI_ALLOC_FAILED -0x0010 /**< Memory allocation failed. */ + +#define MBEDTLS_MPI_CHK(f) \ + do \ + { \ + if( ( ret = (f) ) != 0 ) \ + goto cleanup; \ + } while( 0 ) + +/* + * Maximum size MPIs are allowed to grow to in number of limbs. + */ +#define MBEDTLS_MPI_MAX_LIMBS 10000 + +#if !defined(MBEDTLS_MPI_WINDOW_SIZE) +/* + * Maximum window size used for modular exponentiation. Default: 6 + * Minimum value: 1. Maximum value: 6. + * + * Result is an array of ( 2 ** MBEDTLS_MPI_WINDOW_SIZE ) MPIs used + * for the sliding window calculation. (So 64 by default) + * + * Reduction in size, reduces speed. + */ +#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum window size used. */ +#endif /* !MBEDTLS_MPI_WINDOW_SIZE */ + +#if !defined(MBEDTLS_MPI_MAX_SIZE) +/* + * Maximum size of MPIs allowed in bits and bytes for user-MPIs. + * ( Default: 512 bytes => 4096 bits, Maximum tested: 2048 bytes => 16384 bits ) + * + * Note: Calculations can temporarily result in larger MPIs. So the number + * of limbs required (MBEDTLS_MPI_MAX_LIMBS) is higher. + */ +#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ +#endif /* !MBEDTLS_MPI_MAX_SIZE */ + +#define MBEDTLS_MPI_MAX_BITS ( 8 * MBEDTLS_MPI_MAX_SIZE ) /**< Maximum number of bits for usable MPIs. */ + +/* + * When reading from files with mbedtls_mpi_read_file() and writing to files with + * mbedtls_mpi_write_file() the buffer should have space + * for a (short) label, the MPI (in the provided radix), the newline + * characters and the '\0'. + * + * By default we assume at least a 10 char label, a minimum radix of 10 + * (decimal) and a maximum of 4096 bit numbers (1234 decimal chars). + * Autosized at compile time for at least a 10 char label, a minimum radix + * of 10 (decimal) for a number of MBEDTLS_MPI_MAX_BITS size. + * + * This used to be statically sized to 1250 for a maximum of 4096 bit + * numbers (1234 decimal chars). + * + * Calculate using the formula: + * MBEDTLS_MPI_RW_BUFFER_SIZE = ceil(MBEDTLS_MPI_MAX_BITS / ln(10) * ln(2)) + + * LabelSize + 6 + */ +#define MBEDTLS_MPI_MAX_BITS_SCALE100 ( 100 * MBEDTLS_MPI_MAX_BITS ) +#define MBEDTLS_LN_2_DIV_LN_10_SCALE100 332 +#define MBEDTLS_MPI_RW_BUFFER_SIZE ( ((MBEDTLS_MPI_MAX_BITS_SCALE100 + MBEDTLS_LN_2_DIV_LN_10_SCALE100 - 1) / MBEDTLS_LN_2_DIV_LN_10_SCALE100) + 10 + 6 ) + +/* + * Define the base integer type, architecture-wise. + * + * 32 or 64-bit integer types can be forced regardless of the underlying + * architecture by defining MBEDTLS_HAVE_INT32 or MBEDTLS_HAVE_INT64 + * respectively and undefining MBEDTLS_HAVE_ASM. + * + * Double-width integers (e.g. 128-bit in 64-bit architectures) can be + * disabled by defining MBEDTLS_NO_UDBL_DIVISION. + */ +#if !defined(MBEDTLS_HAVE_INT32) + #if defined(__GNUC__) && ( \ + defined(__amd64__) || defined(__x86_64__) || \ + defined(__ppc64__) || defined(__powerpc64__) || \ + defined(__ia64__) || defined(__alpha__) || \ + ( defined(__sparc__) && defined(__arch64__) ) || \ + defined(__s390x__) || defined(__mips64) ) + #if !defined(MBEDTLS_HAVE_INT64) + #define MBEDTLS_HAVE_INT64 + #endif /* MBEDTLS_HAVE_INT64 */ + typedef int64_t mbedtls_mpi_sint; + typedef uint64_t mbedtls_mpi_uint; + #if !defined(MBEDTLS_NO_UDBL_DIVISION) + /* mbedtls_t_udbl defined as 128-bit unsigned int */ + typedef unsigned int mbedtls_t_udbl __attribute__((mode(TI))); + #define MBEDTLS_HAVE_UDBL + #endif /* !MBEDTLS_NO_UDBL_DIVISION */ + #elif defined(__ARMCC_VERSION) && defined(__aarch64__) + /* + * __ARMCC_VERSION is defined for both armcc and armclang and + * __aarch64__ is only defined by armclang when compiling 64-bit code + */ + #if !defined(MBEDTLS_HAVE_INT64) + #define MBEDTLS_HAVE_INT64 + #endif /* !MBEDTLS_HAVE_INT64 */ + typedef int64_t mbedtls_mpi_sint; + typedef uint64_t mbedtls_mpi_uint; + #if !defined(MBEDTLS_NO_UDBL_DIVISION) + /* mbedtls_t_udbl defined as 128-bit unsigned int */ + typedef __uint128_t mbedtls_t_udbl; + #define MBEDTLS_HAVE_UDBL + #endif /* !MBEDTLS_NO_UDBL_DIVISION */ + #elif defined(MBEDTLS_HAVE_INT64) + /* Force 64-bit integers with unknown compiler */ + typedef int64_t mbedtls_mpi_sint; + typedef uint64_t mbedtls_mpi_uint; + #endif +#endif /* !MBEDTLS_HAVE_INT32 */ + +#if !defined(MBEDTLS_HAVE_INT64) + /* Default to 32-bit compilation */ + #if !defined(MBEDTLS_HAVE_INT32) + #define MBEDTLS_HAVE_INT32 + #endif /* !MBEDTLS_HAVE_INT32 */ + typedef int32_t mbedtls_mpi_sint; + typedef uint32_t mbedtls_mpi_uint; + #if !defined(MBEDTLS_NO_UDBL_DIVISION) + typedef uint64_t mbedtls_t_udbl; + #define MBEDTLS_HAVE_UDBL + #endif /* !MBEDTLS_NO_UDBL_DIVISION */ +#endif /* !MBEDTLS_HAVE_INT64 */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief MPI structure + */ +typedef struct mbedtls_mpi +{ + int s; /*!< Sign: -1 if the mpi is negative, 1 otherwise */ + size_t n; /*!< total # of limbs */ + mbedtls_mpi_uint *p; /*!< pointer to limbs */ +} +mbedtls_mpi; + +/** + * \brief Initialize an MPI context. + * + * This makes the MPI ready to be set or freed, + * but does not define a value for the MPI. + * + * \param X The MPI context to initialize. This must not be \c NULL. + */ +void mbedtls_mpi_init( mbedtls_mpi *X ); + +/** + * \brief This function frees the components of an MPI context. + * + * \param X The MPI context to be cleared. This may be \c NULL, + * in which case this function is a no-op. If it is + * not \c NULL, it must point to an initialized MPI. + */ +void mbedtls_mpi_free( mbedtls_mpi *X ); + +/** + * \brief Enlarge an MPI to the specified number of limbs. + * + * \note This function does nothing if the MPI is + * already large enough. + * + * \param X The MPI to grow. It must be initialized. + * \param nblimbs The target number of limbs. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_grow( mbedtls_mpi *X, size_t nblimbs ); + +/** + * \brief This function resizes an MPI downwards, keeping at least the + * specified number of limbs. + * + * If \c X is smaller than \c nblimbs, it is resized up + * instead. + * + * \param X The MPI to shrink. This must point to an initialized MPI. + * \param nblimbs The minimum number of limbs to keep. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed + * (this can only happen when resizing up). + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_shrink( mbedtls_mpi *X, size_t nblimbs ); + +/** + * \brief Make a copy of an MPI. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param Y The source MPI. This must point to an initialized MPI. + * + * \note The limb-buffer in the destination MPI is enlarged + * if necessary to hold the value in the source MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_copy( mbedtls_mpi *X, const mbedtls_mpi *Y ); + +/** + * \brief Swap the contents of two MPIs. + * + * \param X The first MPI. It must be initialized. + * \param Y The second MPI. It must be initialized. + */ +void mbedtls_mpi_swap( mbedtls_mpi *X, mbedtls_mpi *Y ); + +/** + * \brief Perform a safe conditional copy of MPI which doesn't + * reveal whether the condition was true or not. + * + * \param X The MPI to conditionally assign to. This must point + * to an initialized MPI. + * \param Y The MPI to be assigned from. This must point to an + * initialized MPI. + * \param assign The condition deciding whether to perform the + * assignment or not. Possible values: + * * \c 1: Perform the assignment `X = Y`. + * * \c 0: Keep the original value of \p X. + * + * \note This function is equivalent to + * `if( assign ) mbedtls_mpi_copy( X, Y );` + * except that it avoids leaking any information about whether + * the assignment was done or not (the above code may leak + * information through branch prediction and/or memory access + * patterns analysis). + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_safe_cond_assign( mbedtls_mpi *X, const mbedtls_mpi *Y, unsigned char assign ); + +/** + * \brief Perform a safe conditional swap which doesn't + * reveal whether the condition was true or not. + * + * \param X The first MPI. This must be initialized. + * \param Y The second MPI. This must be initialized. + * \param assign The condition deciding whether to perform + * the swap or not. Possible values: + * * \c 1: Swap the values of \p X and \p Y. + * * \c 0: Keep the original values of \p X and \p Y. + * + * \note This function is equivalent to + * if( assign ) mbedtls_mpi_swap( X, Y ); + * except that it avoids leaking any information about whether + * the assignment was done or not (the above code may leak + * information through branch prediction and/or memory access + * patterns analysis). + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + * + */ +int mbedtls_mpi_safe_cond_swap( mbedtls_mpi *X, mbedtls_mpi *Y, unsigned char assign ); + +/** + * \brief Store integer value in MPI. + * + * \param X The MPI to set. This must be initialized. + * \param z The value to use. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_lset( mbedtls_mpi *X, mbedtls_mpi_sint z ); + +/** + * \brief Get a specific bit from an MPI. + * + * \param X The MPI to query. This must be initialized. + * \param pos Zero-based index of the bit to query. + * + * \return \c 0 or \c 1 on success, depending on whether bit \c pos + * of \c X is unset or set. + * \return A negative error code on failure. + */ +int mbedtls_mpi_get_bit( const mbedtls_mpi *X, size_t pos ); + +/** + * \brief Modify a specific bit in an MPI. + * + * \note This function will grow the target MPI if necessary to set a + * bit to \c 1 in a not yet existing limb. It will not grow if + * the bit should be set to \c 0. + * + * \param X The MPI to modify. This must be initialized. + * \param pos Zero-based index of the bit to modify. + * \param val The desired value of bit \c pos: \c 0 or \c 1. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_set_bit( mbedtls_mpi *X, size_t pos, unsigned char val ); + +/** + * \brief Return the number of bits of value \c 0 before the + * least significant bit of value \c 1. + * + * \note This is the same as the zero-based index of + * the least significant bit of value \c 1. + * + * \param X The MPI to query. + * + * \return The number of bits of value \c 0 before the least significant + * bit of value \c 1 in \p X. + */ +size_t mbedtls_mpi_lsb( const mbedtls_mpi *X ); + +/** + * \brief Return the number of bits up to and including the most + * significant bit of value \c 1. + * + * * \note This is same as the one-based index of the most + * significant bit of value \c 1. + * + * \param X The MPI to query. This must point to an initialized MPI. + * + * \return The number of bits up to and including the most + * significant bit of value \c 1. + */ +size_t mbedtls_mpi_bitlen( const mbedtls_mpi *X ); + +/** + * \brief Return the total size of an MPI value in bytes. + * + * \param X The MPI to use. This must point to an initialized MPI. + * + * \note The value returned by this function may be less than + * the number of bytes used to store \p X internally. + * This happens if and only if there are trailing bytes + * of value zero. + * + * \return The least number of bytes capable of storing + * the absolute value of \p X. + */ +size_t mbedtls_mpi_size( const mbedtls_mpi *X ); + +/** + * \brief Import an MPI from an ASCII string. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param radix The numeric base of the input string. + * \param s Null-terminated string buffer. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_mpi_read_string( mbedtls_mpi *X, int radix, const char *s ); + +/** + * \brief Export an MPI to an ASCII string. + * + * \param X The source MPI. This must point to an initialized MPI. + * \param radix The numeric base of the output string. + * \param buf The buffer to write the string to. This must be writable + * buffer of length \p buflen Bytes. + * \param buflen The available size in Bytes of \p buf. + * \param olen The address at which to store the length of the string + * written, including the final \c NULL byte. This must + * not be \c NULL. + * + * \note You can call this function with `buflen == 0` to obtain the + * minimum required buffer size in `*olen`. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if the target buffer \p buf + * is too small to hold the value of \p X in the desired base. + * In this case, `*olen` is nonetheless updated to contain the + * size of \p buf required for a successful call. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_write_string( const mbedtls_mpi *X, int radix, + char *buf, size_t buflen, size_t *olen ); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Read an MPI from a line in an opened file. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param radix The numeric base of the string representation used + * in the source line. + * \param fin The input file handle to use. This must not be \c NULL. + * + * \note On success, this function advances the file stream + * to the end of the current line or to EOF. + * + * The function returns \c 0 on an empty line. + * + * Leading whitespaces are ignored, as is a + * '0x' prefix for radix \c 16. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if the file read buffer + * is too small. + * \return Another negative error code on failure. + */ +int mbedtls_mpi_read_file( mbedtls_mpi *X, int radix, FILE *fin ); + +/** + * \brief Export an MPI into an opened file. + * + * \param p A string prefix to emit prior to the MPI data. + * For example, this might be a label, or "0x" when + * printing in base \c 16. This may be \c NULL if no prefix + * is needed. + * \param X The source MPI. This must point to an initialized MPI. + * \param radix The numeric base to be used in the emitted string. + * \param fout The output file handle. This may be \c NULL, in which case + * the output is written to \c stdout. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_mpi_write_file( const char *p, const mbedtls_mpi *X, + int radix, FILE *fout ); +#endif /* MBEDTLS_FS_IO */ + +/** + * \brief Import an MPI from unsigned big endian binary data. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param buf The input buffer. This must be a readable buffer of length + * \p buflen Bytes. + * \param buflen The length of the input buffer \p p in Bytes. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_read_binary( mbedtls_mpi *X, const unsigned char *buf, + size_t buflen ); + +/** + * \brief Export an MPI into unsigned big endian binary data + * of fixed size. + * + * \param X The source MPI. This must point to an initialized MPI. + * \param buf The output buffer. This must be a writable buffer of length + * \p buflen Bytes. + * \param buflen The size of the output buffer \p buf in Bytes. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p buf isn't + * large enough to hold the value of \p X. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_write_binary( const mbedtls_mpi *X, unsigned char *buf, + size_t buflen ); + +/** + * \brief Perform a left-shift on an MPI: X <<= count + * + * \param X The MPI to shift. This must point to an initialized MPI. + * \param count The number of bits to shift by. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_shift_l( mbedtls_mpi *X, size_t count ); + +/** + * \brief Perform a right-shift on an MPI: X >>= count + * + * \param X The MPI to shift. This must point to an initialized MPI. + * \param count The number of bits to shift by. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_shift_r( mbedtls_mpi *X, size_t count ); + +/** + * \brief Compare the absolute values of two MPIs. + * + * \param X The left-hand MPI. This must point to an initialized MPI. + * \param Y The right-hand MPI. This must point to an initialized MPI. + * + * \return \c 1 if `|X|` is greater than `|Y|`. + * \return \c -1 if `|X|` is lesser than `|Y|`. + * \return \c 0 if `|X|` is equal to `|Y|`. + */ +int mbedtls_mpi_cmp_abs( const mbedtls_mpi *X, const mbedtls_mpi *Y ); + +/** + * \brief Compare two MPIs. + * + * \param X The left-hand MPI. This must point to an initialized MPI. + * \param Y The right-hand MPI. This must point to an initialized MPI. + * + * \return \c 1 if \p X is greater than \p Y. + * \return \c -1 if \p X is lesser than \p Y. + * \return \c 0 if \p X is equal to \p Y. + */ +int mbedtls_mpi_cmp_mpi( const mbedtls_mpi *X, const mbedtls_mpi *Y ); + +/** + * \brief Check if an MPI is less than the other in constant time. + * + * \param X The left-hand MPI. This must point to an initialized MPI + * with the same allocated length as Y. + * \param Y The right-hand MPI. This must point to an initialized MPI + * with the same allocated length as X. + * \param ret The result of the comparison: + * \c 1 if \p X is less than \p Y. + * \c 0 if \p X is greater than or equal to \p Y. + * + * \return 0 on success. + * \return MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the allocated length of + * the two input MPIs is not the same. + */ +int mbedtls_mpi_lt_mpi_ct( const mbedtls_mpi *X, const mbedtls_mpi *Y, + unsigned *ret ); + +/** + * \brief Compare an MPI with an integer. + * + * \param X The left-hand MPI. This must point to an initialized MPI. + * \param z The integer value to compare \p X to. + * + * \return \c 1 if \p X is greater than \p z. + * \return \c -1 if \p X is lesser than \p z. + * \return \c 0 if \p X is equal to \p z. + */ +int mbedtls_mpi_cmp_int( const mbedtls_mpi *X, mbedtls_mpi_sint z ); + +/** + * \brief Perform an unsigned addition of MPIs: X = |A| + |B| + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first summand. This must point to an initialized MPI. + * \param B The second summand. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_add_abs( mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B ); + +/** + * \brief Perform an unsigned subtraction of MPIs: X = |A| - |B| + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The minuend. This must point to an initialized MPI. + * \param B The subtrahend. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p B is greater than \p A. + * \return Another negative error code on different kinds of failure. + * + */ +int mbedtls_mpi_sub_abs( mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B ); + +/** + * \brief Perform a signed addition of MPIs: X = A + B + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first summand. This must point to an initialized MPI. + * \param B The second summand. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_add_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B ); + +/** + * \brief Perform a signed subtraction of MPIs: X = A - B + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The minuend. This must point to an initialized MPI. + * \param B The subtrahend. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_sub_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B ); + +/** + * \brief Perform a signed addition of an MPI and an integer: X = A + b + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first summand. This must point to an initialized MPI. + * \param b The second summand. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_add_int( mbedtls_mpi *X, const mbedtls_mpi *A, + mbedtls_mpi_sint b ); + +/** + * \brief Perform a signed subtraction of an MPI and an integer: + * X = A - b + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The minuend. This must point to an initialized MPI. + * \param b The subtrahend. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_sub_int( mbedtls_mpi *X, const mbedtls_mpi *A, + mbedtls_mpi_sint b ); + +/** + * \brief Perform a multiplication of two MPIs: X = A * B + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first factor. This must point to an initialized MPI. + * \param B The second factor. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + * + */ +int mbedtls_mpi_mul_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B ); + +/** + * \brief Perform a multiplication of an MPI with an unsigned integer: + * X = A * b + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first factor. This must point to an initialized MPI. + * \param b The second factor. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + * + */ +int mbedtls_mpi_mul_int( mbedtls_mpi *X, const mbedtls_mpi *A, + mbedtls_mpi_uint b ); + +/** + * \brief Perform a division with remainder of two MPIs: + * A = Q * B + R + * + * \param Q The destination MPI for the quotient. + * This may be \c NULL if the value of the + * quotient is not needed. + * \param R The destination MPI for the remainder value. + * This may be \c NULL if the value of the + * remainder is not needed. + * \param A The dividend. This must point to an initialized MPi. + * \param B The divisor. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p B equals zero. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, + const mbedtls_mpi *B ); + +/** + * \brief Perform a division with remainder of an MPI by an integer: + * A = Q * b + R + * + * \param Q The destination MPI for the quotient. + * This may be \c NULL if the value of the + * quotient is not needed. + * \param R The destination MPI for the remainder value. + * This may be \c NULL if the value of the + * remainder is not needed. + * \param A The dividend. This must point to an initialized MPi. + * \param b The divisor. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p b equals zero. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_div_int( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, + mbedtls_mpi_sint b ); + +/** + * \brief Perform a modular reduction. R = A mod B + * + * \param R The destination MPI for the residue value. + * This must point to an initialized MPI. + * \param A The MPI to compute the residue of. + * This must point to an initialized MPI. + * \param B The base of the modular reduction. + * This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p B equals zero. + * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p B is negative. + * \return Another negative error code on different kinds of failure. + * + */ +int mbedtls_mpi_mod_mpi( mbedtls_mpi *R, const mbedtls_mpi *A, + const mbedtls_mpi *B ); + +/** + * \brief Perform a modular reduction with respect to an integer. + * r = A mod b + * + * \param r The address at which to store the residue. + * This must not be \c NULL. + * \param A The MPI to compute the residue of. + * This must point to an initialized MPi. + * \param b The integer base of the modular reduction. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p b equals zero. + * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p b is negative. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_mod_int( mbedtls_mpi_uint *r, const mbedtls_mpi *A, + mbedtls_mpi_sint b ); + +/** + * \brief Perform a sliding-window exponentiation: X = A^E mod N + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The base of the exponentiation. + * This must point to an initialized MPI. + * \param E The exponent MPI. This must point to an initialized MPI. + * \param N The base for the modular reduction. This must point to an + * initialized MPI. + * \param _RR A helper MPI depending solely on \p N which can be used to + * speed-up multiple modular exponentiations for the same value + * of \p N. This may be \c NULL. If it is not \c NULL, it must + * point to an initialized MPI. If it hasn't been used after + * the call to mbedtls_mpi_init(), this function will compute + * the helper value and store it in \p _RR for reuse on + * subsequent calls to this function. Otherwise, the function + * will assume that \p _RR holds the helper value set by a + * previous call to mbedtls_mpi_exp_mod(), and reuse it. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \c N is negative or + * even, or if \c E is negative. + * \return Another negative error code on different kinds of failures. + * + */ +int mbedtls_mpi_exp_mod( mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *E, const mbedtls_mpi *N, + mbedtls_mpi *_RR ); + +/** + * \brief Fill an MPI with a number of random bytes. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param size The number of random bytes to generate. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on failure. + * + * \note The bytes obtained from the RNG are interpreted + * as a big-endian representation of an MPI; this can + * be relevant in applications like deterministic ECDSA. + */ +int mbedtls_mpi_fill_random( mbedtls_mpi *X, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief Compute the greatest common divisor: G = gcd(A, B) + * + * \param G The destination MPI. This must point to an initialized MPI. + * \param A The first operand. This must point to an initialized MPI. + * \param B The second operand. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_gcd( mbedtls_mpi *G, const mbedtls_mpi *A, + const mbedtls_mpi *B ); + +/** + * \brief Compute the modular inverse: X = A^-1 mod N + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The MPI to calculate the modular inverse of. This must point + * to an initialized MPI. + * \param N The base of the modular inversion. This must point to an + * initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p N is less than + * or equal to one. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p has no modular inverse + * with respect to \p N. + */ +int mbedtls_mpi_inv_mod( mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *N ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief Perform a Miller-Rabin primality test with error + * probability of 2-80. + * + * \deprecated Superseded by mbedtls_mpi_is_prime_ext() which allows + * specifying the number of Miller-Rabin rounds. + * + * \param X The MPI to check for primality. + * This must point to an initialized MPI. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * This may be \c NULL if \p f_rng doesn't use a + * context parameter. + * + * \return \c 0 if successful, i.e. \p X is probably prime. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p X is not prime. + * \return Another negative error code on other kinds of failure. + */ +MBEDTLS_DEPRECATED int mbedtls_mpi_is_prime( const mbedtls_mpi *X, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief Miller-Rabin primality test. + * + * \warning If \p X is potentially generated by an adversary, for example + * when validating cryptographic parameters that you didn't + * generate yourself and that are supposed to be prime, then + * \p rounds should be at least the half of the security + * strength of the cryptographic algorithm. On the other hand, + * if \p X is chosen uniformly or non-adversially (as is the + * case when mbedtls_mpi_gen_prime calls this function), then + * \p rounds can be much lower. + * + * \param X The MPI to check for primality. + * This must point to an initialized MPI. + * \param rounds The number of bases to perform the Miller-Rabin primality + * test for. The probability of returning 0 on a composite is + * at most 2-2*\p rounds. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * This may be \c NULL if \p f_rng doesn't use + * a context parameter. + * + * \return \c 0 if successful, i.e. \p X is probably prime. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p X is not prime. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_is_prime_ext( const mbedtls_mpi *X, int rounds, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); +/** + * \brief Flags for mbedtls_mpi_gen_prime() + * + * Each of these flags is a constraint on the result X returned by + * mbedtls_mpi_gen_prime(). + */ +typedef enum { + MBEDTLS_MPI_GEN_PRIME_FLAG_DH = 0x0001, /**< (X-1)/2 is prime too */ + MBEDTLS_MPI_GEN_PRIME_FLAG_LOW_ERR = 0x0002, /**< lower error rate from 2-80 to 2-128 */ +} mbedtls_mpi_gen_prime_flag_t; + +/** + * \brief Generate a prime number. + * + * \param X The destination MPI to store the generated prime in. + * This must point to an initialized MPi. + * \param nbits The required size of the destination MPI in bits. + * This must be between \c 3 and #MBEDTLS_MPI_MAX_BITS. + * \param flags A mask of flags of type #mbedtls_mpi_gen_prime_flag_t. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * This may be \c NULL if \p f_rng doesn't use + * a context parameter. + * + * \return \c 0 if successful, in which case \p X holds a + * probably prime number. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if `nbits` is not between + * \c 3 and #MBEDTLS_MPI_MAX_BITS. + */ +int mbedtls_mpi_gen_prime( mbedtls_mpi *X, size_t nbits, int flags, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_mpi_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* bignum.h */ diff --git a/src/common/mbedtls/include/mbedtls/bn_mul.h b/src/common/mbedtls/include/mbedtls/bn_mul.h new file mode 100644 index 0000000000..112b91bf4e --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/bn_mul.h @@ -0,0 +1,899 @@ +/** + * \file bn_mul.h + * + * \brief Multi-precision integer library + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +/* + * Multiply source vector [s] with b, add result + * to destination vector [d] and set carry c. + * + * Currently supports: + * + * . IA-32 (386+) . AMD64 / EM64T + * . IA-32 (SSE2) . Motorola 68000 + * . PowerPC, 32-bit . MicroBlaze + * . PowerPC, 64-bit . TriCore + * . SPARC v8 . ARM v3+ + * . Alpha . MIPS32 + * . C, longlong . C, generic + */ +#ifndef MBEDTLS_BN_MUL_H +#define MBEDTLS_BN_MUL_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "bignum.h" + + +/* + * Conversion macros for embedded constants: + * build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2 + */ +#if defined(MBEDTLS_HAVE_INT32) + +#define MBEDTLS_BYTES_TO_T_UINT_4( a, b, c, d ) \ + ( (mbedtls_mpi_uint) (a) << 0 ) | \ + ( (mbedtls_mpi_uint) (b) << 8 ) | \ + ( (mbedtls_mpi_uint) (c) << 16 ) | \ + ( (mbedtls_mpi_uint) (d) << 24 ) + +#define MBEDTLS_BYTES_TO_T_UINT_2( a, b ) \ + MBEDTLS_BYTES_TO_T_UINT_4( a, b, 0, 0 ) + +#define MBEDTLS_BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + MBEDTLS_BYTES_TO_T_UINT_4( a, b, c, d ), \ + MBEDTLS_BYTES_TO_T_UINT_4( e, f, g, h ) + +#else /* 64-bits */ + +#define MBEDTLS_BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + ( (mbedtls_mpi_uint) (a) << 0 ) | \ + ( (mbedtls_mpi_uint) (b) << 8 ) | \ + ( (mbedtls_mpi_uint) (c) << 16 ) | \ + ( (mbedtls_mpi_uint) (d) << 24 ) | \ + ( (mbedtls_mpi_uint) (e) << 32 ) | \ + ( (mbedtls_mpi_uint) (f) << 40 ) | \ + ( (mbedtls_mpi_uint) (g) << 48 ) | \ + ( (mbedtls_mpi_uint) (h) << 56 ) + +#define MBEDTLS_BYTES_TO_T_UINT_4( a, b, c, d ) \ + MBEDTLS_BYTES_TO_T_UINT_8( a, b, c, d, 0, 0, 0, 0 ) + +#define MBEDTLS_BYTES_TO_T_UINT_2( a, b ) \ + MBEDTLS_BYTES_TO_T_UINT_8( a, b, 0, 0, 0, 0, 0, 0 ) + +#endif /* bits in mbedtls_mpi_uint */ + +#if defined(MBEDTLS_HAVE_ASM) + +#ifndef asm +#define asm __asm +#endif + +/* armcc5 --gnu defines __GNUC__ but doesn't support GNU's extended asm */ +#if defined(__GNUC__) && \ + ( !defined(__ARMCC_VERSION) || __ARMCC_VERSION >= 6000000 ) + +/* + * Disable use of the i386 assembly code below if option -O0, to disable all + * compiler optimisations, is passed, detected with __OPTIMIZE__ + * This is done as the number of registers used in the assembly code doesn't + * work with the -O0 option. + */ +#if defined(__i386__) && defined(__OPTIMIZE__) + +#define MULADDC_INIT \ + asm( \ + "movl %%ebx, %0 \n\t" \ + "movl %5, %%esi \n\t" \ + "movl %6, %%edi \n\t" \ + "movl %7, %%ecx \n\t" \ + "movl %8, %%ebx \n\t" + +#define MULADDC_CORE \ + "lodsl \n\t" \ + "mull %%ebx \n\t" \ + "addl %%ecx, %%eax \n\t" \ + "adcl $0, %%edx \n\t" \ + "addl (%%edi), %%eax \n\t" \ + "adcl $0, %%edx \n\t" \ + "movl %%edx, %%ecx \n\t" \ + "stosl \n\t" + +#if defined(MBEDTLS_HAVE_SSE2) + +#define MULADDC_HUIT \ + "movd %%ecx, %%mm1 \n\t" \ + "movd %%ebx, %%mm0 \n\t" \ + "movd (%%edi), %%mm3 \n\t" \ + "paddq %%mm3, %%mm1 \n\t" \ + "movd (%%esi), %%mm2 \n\t" \ + "pmuludq %%mm0, %%mm2 \n\t" \ + "movd 4(%%esi), %%mm4 \n\t" \ + "pmuludq %%mm0, %%mm4 \n\t" \ + "movd 8(%%esi), %%mm6 \n\t" \ + "pmuludq %%mm0, %%mm6 \n\t" \ + "movd 12(%%esi), %%mm7 \n\t" \ + "pmuludq %%mm0, %%mm7 \n\t" \ + "paddq %%mm2, %%mm1 \n\t" \ + "movd 4(%%edi), %%mm3 \n\t" \ + "paddq %%mm4, %%mm3 \n\t" \ + "movd 8(%%edi), %%mm5 \n\t" \ + "paddq %%mm6, %%mm5 \n\t" \ + "movd 12(%%edi), %%mm4 \n\t" \ + "paddq %%mm4, %%mm7 \n\t" \ + "movd %%mm1, (%%edi) \n\t" \ + "movd 16(%%esi), %%mm2 \n\t" \ + "pmuludq %%mm0, %%mm2 \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "movd 20(%%esi), %%mm4 \n\t" \ + "pmuludq %%mm0, %%mm4 \n\t" \ + "paddq %%mm3, %%mm1 \n\t" \ + "movd 24(%%esi), %%mm6 \n\t" \ + "pmuludq %%mm0, %%mm6 \n\t" \ + "movd %%mm1, 4(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "movd 28(%%esi), %%mm3 \n\t" \ + "pmuludq %%mm0, %%mm3 \n\t" \ + "paddq %%mm5, %%mm1 \n\t" \ + "movd 16(%%edi), %%mm5 \n\t" \ + "paddq %%mm5, %%mm2 \n\t" \ + "movd %%mm1, 8(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm7, %%mm1 \n\t" \ + "movd 20(%%edi), %%mm5 \n\t" \ + "paddq %%mm5, %%mm4 \n\t" \ + "movd %%mm1, 12(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm2, %%mm1 \n\t" \ + "movd 24(%%edi), %%mm5 \n\t" \ + "paddq %%mm5, %%mm6 \n\t" \ + "movd %%mm1, 16(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm4, %%mm1 \n\t" \ + "movd 28(%%edi), %%mm5 \n\t" \ + "paddq %%mm5, %%mm3 \n\t" \ + "movd %%mm1, 20(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm6, %%mm1 \n\t" \ + "movd %%mm1, 24(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm3, %%mm1 \n\t" \ + "movd %%mm1, 28(%%edi) \n\t" \ + "addl $32, %%edi \n\t" \ + "addl $32, %%esi \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "movd %%mm1, %%ecx \n\t" + +#define MULADDC_STOP \ + "emms \n\t" \ + "movl %4, %%ebx \n\t" \ + "movl %%ecx, %1 \n\t" \ + "movl %%edi, %2 \n\t" \ + "movl %%esi, %3 \n\t" \ + : "=m" (t), "=m" (c), "=m" (d), "=m" (s) \ + : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b) \ + : "eax", "ebx", "ecx", "edx", "esi", "edi" \ + ); + +#else + +#define MULADDC_STOP \ + "movl %4, %%ebx \n\t" \ + "movl %%ecx, %1 \n\t" \ + "movl %%edi, %2 \n\t" \ + "movl %%esi, %3 \n\t" \ + : "=m" (t), "=m" (c), "=m" (d), "=m" (s) \ + : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b) \ + : "eax", "ebx", "ecx", "edx", "esi", "edi" \ + ); +#endif /* SSE2 */ +#endif /* i386 */ + +#if defined(__amd64__) || defined (__x86_64__) + +#define MULADDC_INIT \ + asm( \ + "xorq %%r8, %%r8\n" + +#define MULADDC_CORE \ + "movq (%%rsi), %%rax\n" \ + "mulq %%rbx\n" \ + "addq $8, %%rsi\n" \ + "addq %%rcx, %%rax\n" \ + "movq %%r8, %%rcx\n" \ + "adcq $0, %%rdx\n" \ + "nop \n" \ + "addq %%rax, (%%rdi)\n" \ + "adcq %%rdx, %%rcx\n" \ + "addq $8, %%rdi\n" + +#define MULADDC_STOP \ + : "+c" (c), "+D" (d), "+S" (s) \ + : "b" (b) \ + : "rax", "rdx", "r8" \ + ); + +#endif /* AMD64 */ + +#if defined(__mc68020__) || defined(__mcpu32__) + +#define MULADDC_INIT \ + asm( \ + "movl %3, %%a2 \n\t" \ + "movl %4, %%a3 \n\t" \ + "movl %5, %%d3 \n\t" \ + "movl %6, %%d2 \n\t" \ + "moveq #0, %%d0 \n\t" + +#define MULADDC_CORE \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "moveq #0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "addxl %%d4, %%d3 \n\t" + +#define MULADDC_STOP \ + "movl %%d3, %0 \n\t" \ + "movl %%a3, %1 \n\t" \ + "movl %%a2, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "d0", "d1", "d2", "d3", "d4", "a2", "a3" \ + ); + +#define MULADDC_HUIT \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addxl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d3:%%d1 \n\t" \ + "addxl %%d4, %%d1 \n\t" \ + "addxl %%d0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addxl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d3:%%d1 \n\t" \ + "addxl %%d4, %%d1 \n\t" \ + "addxl %%d0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addxl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d3:%%d1 \n\t" \ + "addxl %%d4, %%d1 \n\t" \ + "addxl %%d0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addxl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d3:%%d1 \n\t" \ + "addxl %%d4, %%d1 \n\t" \ + "addxl %%d0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "addxl %%d0, %%d3 \n\t" + +#endif /* MC68000 */ + +#if defined(__powerpc64__) || defined(__ppc64__) + +#if defined(__MACH__) && defined(__APPLE__) + +#define MULADDC_INIT \ + asm( \ + "ld r3, %3 \n\t" \ + "ld r4, %4 \n\t" \ + "ld r5, %5 \n\t" \ + "ld r6, %6 \n\t" \ + "addi r3, r3, -8 \n\t" \ + "addi r4, r4, -8 \n\t" \ + "addic r5, r5, 0 \n\t" + +#define MULADDC_CORE \ + "ldu r7, 8(r3) \n\t" \ + "mulld r8, r7, r6 \n\t" \ + "mulhdu r9, r7, r6 \n\t" \ + "adde r8, r8, r5 \n\t" \ + "ld r7, 8(r4) \n\t" \ + "addze r5, r9 \n\t" \ + "addc r8, r8, r7 \n\t" \ + "stdu r8, 8(r4) \n\t" + +#define MULADDC_STOP \ + "addze r5, r5 \n\t" \ + "addi r4, r4, 8 \n\t" \ + "addi r3, r3, 8 \n\t" \ + "std r5, %0 \n\t" \ + "std r4, %1 \n\t" \ + "std r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ + ); + + +#else /* __MACH__ && __APPLE__ */ + +#define MULADDC_INIT \ + asm( \ + "ld %%r3, %3 \n\t" \ + "ld %%r4, %4 \n\t" \ + "ld %%r5, %5 \n\t" \ + "ld %%r6, %6 \n\t" \ + "addi %%r3, %%r3, -8 \n\t" \ + "addi %%r4, %%r4, -8 \n\t" \ + "addic %%r5, %%r5, 0 \n\t" + +#define MULADDC_CORE \ + "ldu %%r7, 8(%%r3) \n\t" \ + "mulld %%r8, %%r7, %%r6 \n\t" \ + "mulhdu %%r9, %%r7, %%r6 \n\t" \ + "adde %%r8, %%r8, %%r5 \n\t" \ + "ld %%r7, 8(%%r4) \n\t" \ + "addze %%r5, %%r9 \n\t" \ + "addc %%r8, %%r8, %%r7 \n\t" \ + "stdu %%r8, 8(%%r4) \n\t" + +#define MULADDC_STOP \ + "addze %%r5, %%r5 \n\t" \ + "addi %%r4, %%r4, 8 \n\t" \ + "addi %%r3, %%r3, 8 \n\t" \ + "std %%r5, %0 \n\t" \ + "std %%r4, %1 \n\t" \ + "std %%r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ + ); + +#endif /* __MACH__ && __APPLE__ */ + +#elif defined(__powerpc__) || defined(__ppc__) /* end PPC64/begin PPC32 */ + +#if defined(__MACH__) && defined(__APPLE__) + +#define MULADDC_INIT \ + asm( \ + "lwz r3, %3 \n\t" \ + "lwz r4, %4 \n\t" \ + "lwz r5, %5 \n\t" \ + "lwz r6, %6 \n\t" \ + "addi r3, r3, -4 \n\t" \ + "addi r4, r4, -4 \n\t" \ + "addic r5, r5, 0 \n\t" + +#define MULADDC_CORE \ + "lwzu r7, 4(r3) \n\t" \ + "mullw r8, r7, r6 \n\t" \ + "mulhwu r9, r7, r6 \n\t" \ + "adde r8, r8, r5 \n\t" \ + "lwz r7, 4(r4) \n\t" \ + "addze r5, r9 \n\t" \ + "addc r8, r8, r7 \n\t" \ + "stwu r8, 4(r4) \n\t" + +#define MULADDC_STOP \ + "addze r5, r5 \n\t" \ + "addi r4, r4, 4 \n\t" \ + "addi r3, r3, 4 \n\t" \ + "stw r5, %0 \n\t" \ + "stw r4, %1 \n\t" \ + "stw r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ + ); + +#else /* __MACH__ && __APPLE__ */ + +#define MULADDC_INIT \ + asm( \ + "lwz %%r3, %3 \n\t" \ + "lwz %%r4, %4 \n\t" \ + "lwz %%r5, %5 \n\t" \ + "lwz %%r6, %6 \n\t" \ + "addi %%r3, %%r3, -4 \n\t" \ + "addi %%r4, %%r4, -4 \n\t" \ + "addic %%r5, %%r5, 0 \n\t" + +#define MULADDC_CORE \ + "lwzu %%r7, 4(%%r3) \n\t" \ + "mullw %%r8, %%r7, %%r6 \n\t" \ + "mulhwu %%r9, %%r7, %%r6 \n\t" \ + "adde %%r8, %%r8, %%r5 \n\t" \ + "lwz %%r7, 4(%%r4) \n\t" \ + "addze %%r5, %%r9 \n\t" \ + "addc %%r8, %%r8, %%r7 \n\t" \ + "stwu %%r8, 4(%%r4) \n\t" + +#define MULADDC_STOP \ + "addze %%r5, %%r5 \n\t" \ + "addi %%r4, %%r4, 4 \n\t" \ + "addi %%r3, %%r3, 4 \n\t" \ + "stw %%r5, %0 \n\t" \ + "stw %%r4, %1 \n\t" \ + "stw %%r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ + ); + +#endif /* __MACH__ && __APPLE__ */ + +#endif /* PPC32 */ + +/* + * The Sparc(64) assembly is reported to be broken. + * Disable it for now, until we're able to fix it. + */ + +#if defined(__microblaze__) || defined(microblaze) + +#define MULADDC_INIT \ + asm( \ + "lwi r3, %3 \n\t" \ + "lwi r4, %4 \n\t" \ + "lwi r5, %5 \n\t" \ + "lwi r6, %6 \n\t" \ + "andi r7, r6, 0xffff \n\t" \ + "bsrli r6, r6, 16 \n\t" + +#define MULADDC_CORE \ + "lhui r8, r3, 0 \n\t" \ + "addi r3, r3, 2 \n\t" \ + "lhui r9, r3, 0 \n\t" \ + "addi r3, r3, 2 \n\t" \ + "mul r10, r9, r6 \n\t" \ + "mul r11, r8, r7 \n\t" \ + "mul r12, r9, r7 \n\t" \ + "mul r13, r8, r6 \n\t" \ + "bsrli r8, r10, 16 \n\t" \ + "bsrli r9, r11, 16 \n\t" \ + "add r13, r13, r8 \n\t" \ + "add r13, r13, r9 \n\t" \ + "bslli r10, r10, 16 \n\t" \ + "bslli r11, r11, 16 \n\t" \ + "add r12, r12, r10 \n\t" \ + "addc r13, r13, r0 \n\t" \ + "add r12, r12, r11 \n\t" \ + "addc r13, r13, r0 \n\t" \ + "lwi r10, r4, 0 \n\t" \ + "add r12, r12, r10 \n\t" \ + "addc r13, r13, r0 \n\t" \ + "add r12, r12, r5 \n\t" \ + "addc r5, r13, r0 \n\t" \ + "swi r12, r4, 0 \n\t" \ + "addi r4, r4, 4 \n\t" + +#define MULADDC_STOP \ + "swi r5, %0 \n\t" \ + "swi r4, %1 \n\t" \ + "swi r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", \ + "r9", "r10", "r11", "r12", "r13" \ + ); + +#endif /* MicroBlaze */ + +#if defined(__tricore__) + +#define MULADDC_INIT \ + asm( \ + "ld.a %%a2, %3 \n\t" \ + "ld.a %%a3, %4 \n\t" \ + "ld.w %%d4, %5 \n\t" \ + "ld.w %%d1, %6 \n\t" \ + "xor %%d5, %%d5 \n\t" + +#define MULADDC_CORE \ + "ld.w %%d0, [%%a2+] \n\t" \ + "madd.u %%e2, %%e4, %%d0, %%d1 \n\t" \ + "ld.w %%d0, [%%a3] \n\t" \ + "addx %%d2, %%d2, %%d0 \n\t" \ + "addc %%d3, %%d3, 0 \n\t" \ + "mov %%d4, %%d3 \n\t" \ + "st.w [%%a3+], %%d2 \n\t" + +#define MULADDC_STOP \ + "st.w %0, %%d4 \n\t" \ + "st.a %1, %%a3 \n\t" \ + "st.a %2, %%a2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "d0", "d1", "e2", "d4", "a2", "a3" \ + ); + +#endif /* TriCore */ + +/* + * Note, gcc -O0 by default uses r7 for the frame pointer, so it complains about + * our use of r7 below, unless -fomit-frame-pointer is passed. + * + * On the other hand, -fomit-frame-pointer is implied by any -Ox options with + * x !=0, which we can detect using __OPTIMIZE__ (which is also defined by + * clang and armcc5 under the same conditions). + * + * So, only use the optimized assembly below for optimized build, which avoids + * the build error and is pretty reasonable anyway. + */ +#if defined(__GNUC__) && !defined(__OPTIMIZE__) +#define MULADDC_CANNOT_USE_R7 +#endif + +#if defined(__arm__) && !defined(MULADDC_CANNOT_USE_R7) + +#if defined(__thumb__) && !defined(__thumb2__) + +#define MULADDC_INIT \ + asm( \ + "ldr r0, %3 \n\t" \ + "ldr r1, %4 \n\t" \ + "ldr r2, %5 \n\t" \ + "ldr r3, %6 \n\t" \ + "lsr r7, r3, #16 \n\t" \ + "mov r9, r7 \n\t" \ + "lsl r7, r3, #16 \n\t" \ + "lsr r7, r7, #16 \n\t" \ + "mov r8, r7 \n\t" + +#define MULADDC_CORE \ + "ldmia r0!, {r6} \n\t" \ + "lsr r7, r6, #16 \n\t" \ + "lsl r6, r6, #16 \n\t" \ + "lsr r6, r6, #16 \n\t" \ + "mov r4, r8 \n\t" \ + "mul r4, r6 \n\t" \ + "mov r3, r9 \n\t" \ + "mul r6, r3 \n\t" \ + "mov r5, r9 \n\t" \ + "mul r5, r7 \n\t" \ + "mov r3, r8 \n\t" \ + "mul r7, r3 \n\t" \ + "lsr r3, r6, #16 \n\t" \ + "add r5, r5, r3 \n\t" \ + "lsr r3, r7, #16 \n\t" \ + "add r5, r5, r3 \n\t" \ + "add r4, r4, r2 \n\t" \ + "mov r2, #0 \n\t" \ + "adc r5, r2 \n\t" \ + "lsl r3, r6, #16 \n\t" \ + "add r4, r4, r3 \n\t" \ + "adc r5, r2 \n\t" \ + "lsl r3, r7, #16 \n\t" \ + "add r4, r4, r3 \n\t" \ + "adc r5, r2 \n\t" \ + "ldr r3, [r1] \n\t" \ + "add r4, r4, r3 \n\t" \ + "adc r2, r5 \n\t" \ + "stmia r1!, {r4} \n\t" + +#define MULADDC_STOP \ + "str r2, %0 \n\t" \ + "str r1, %1 \n\t" \ + "str r0, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r0", "r1", "r2", "r3", "r4", "r5", \ + "r6", "r7", "r8", "r9", "cc" \ + ); + +#elif (__ARM_ARCH >= 6) && \ + defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1) + +#define MULADDC_INIT \ + asm( + +#define MULADDC_CORE \ + "ldr r0, [%0], #4 \n\t" \ + "ldr r1, [%1] \n\t" \ + "umaal r1, %2, %3, r0 \n\t" \ + "str r1, [%1], #4 \n\t" + +#define MULADDC_STOP \ + : "=r" (s), "=r" (d), "=r" (c) \ + : "r" (b), "0" (s), "1" (d), "2" (c) \ + : "r0", "r1", "memory" \ + ); + +#else + +#define MULADDC_INIT \ + asm( \ + "ldr r0, %3 \n\t" \ + "ldr r1, %4 \n\t" \ + "ldr r2, %5 \n\t" \ + "ldr r3, %6 \n\t" + +#define MULADDC_CORE \ + "ldr r4, [r0], #4 \n\t" \ + "mov r5, #0 \n\t" \ + "ldr r6, [r1] \n\t" \ + "umlal r2, r5, r3, r4 \n\t" \ + "adds r7, r6, r2 \n\t" \ + "adc r2, r5, #0 \n\t" \ + "str r7, [r1], #4 \n\t" + +#define MULADDC_STOP \ + "str r2, %0 \n\t" \ + "str r1, %1 \n\t" \ + "str r0, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r0", "r1", "r2", "r3", "r4", "r5", \ + "r6", "r7", "cc" \ + ); + +#endif /* Thumb */ + +#endif /* ARMv3 */ + +#if defined(__alpha__) + +#define MULADDC_INIT \ + asm( \ + "ldq $1, %3 \n\t" \ + "ldq $2, %4 \n\t" \ + "ldq $3, %5 \n\t" \ + "ldq $4, %6 \n\t" + +#define MULADDC_CORE \ + "ldq $6, 0($1) \n\t" \ + "addq $1, 8, $1 \n\t" \ + "mulq $6, $4, $7 \n\t" \ + "umulh $6, $4, $6 \n\t" \ + "addq $7, $3, $7 \n\t" \ + "cmpult $7, $3, $3 \n\t" \ + "ldq $5, 0($2) \n\t" \ + "addq $7, $5, $7 \n\t" \ + "cmpult $7, $5, $5 \n\t" \ + "stq $7, 0($2) \n\t" \ + "addq $2, 8, $2 \n\t" \ + "addq $6, $3, $3 \n\t" \ + "addq $5, $3, $3 \n\t" + +#define MULADDC_STOP \ + "stq $3, %0 \n\t" \ + "stq $2, %1 \n\t" \ + "stq $1, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "$1", "$2", "$3", "$4", "$5", "$6", "$7" \ + ); +#endif /* Alpha */ + +#if defined(__mips__) && !defined(__mips64) + +#define MULADDC_INIT \ + asm( \ + "lw $10, %3 \n\t" \ + "lw $11, %4 \n\t" \ + "lw $12, %5 \n\t" \ + "lw $13, %6 \n\t" + +#define MULADDC_CORE \ + "lw $14, 0($10) \n\t" \ + "multu $13, $14 \n\t" \ + "addi $10, $10, 4 \n\t" \ + "mflo $14 \n\t" \ + "mfhi $9 \n\t" \ + "addu $14, $12, $14 \n\t" \ + "lw $15, 0($11) \n\t" \ + "sltu $12, $14, $12 \n\t" \ + "addu $15, $14, $15 \n\t" \ + "sltu $14, $15, $14 \n\t" \ + "addu $12, $12, $9 \n\t" \ + "sw $15, 0($11) \n\t" \ + "addu $12, $12, $14 \n\t" \ + "addi $11, $11, 4 \n\t" + +#define MULADDC_STOP \ + "sw $12, %0 \n\t" \ + "sw $11, %1 \n\t" \ + "sw $10, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "$9", "$10", "$11", "$12", "$13", "$14", "$15", "lo", "hi" \ + ); + +#endif /* MIPS */ +#endif /* GNUC */ + +#if (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__) + +#define MULADDC_INIT \ + __asm mov esi, s \ + __asm mov edi, d \ + __asm mov ecx, c \ + __asm mov ebx, b + +#define MULADDC_CORE \ + __asm lodsd \ + __asm mul ebx \ + __asm add eax, ecx \ + __asm adc edx, 0 \ + __asm add eax, [edi] \ + __asm adc edx, 0 \ + __asm mov ecx, edx \ + __asm stosd + +#if defined(MBEDTLS_HAVE_SSE2) + +#define EMIT __asm _emit + +#define MULADDC_HUIT \ + EMIT 0x0F EMIT 0x6E EMIT 0xC9 \ + EMIT 0x0F EMIT 0x6E EMIT 0xC3 \ + EMIT 0x0F EMIT 0x6E EMIT 0x1F \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ + EMIT 0x0F EMIT 0x6E EMIT 0x16 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xD0 \ + EMIT 0x0F EMIT 0x6E EMIT 0x66 EMIT 0x04 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xE0 \ + EMIT 0x0F EMIT 0x6E EMIT 0x76 EMIT 0x08 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xF0 \ + EMIT 0x0F EMIT 0x6E EMIT 0x7E EMIT 0x0C \ + EMIT 0x0F EMIT 0xF4 EMIT 0xF8 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCA \ + EMIT 0x0F EMIT 0x6E EMIT 0x5F EMIT 0x04 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xDC \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x08 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xEE \ + EMIT 0x0F EMIT 0x6E EMIT 0x67 EMIT 0x0C \ + EMIT 0x0F EMIT 0xD4 EMIT 0xFC \ + EMIT 0x0F EMIT 0x7E EMIT 0x0F \ + EMIT 0x0F EMIT 0x6E EMIT 0x56 EMIT 0x10 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xD0 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0x6E EMIT 0x66 EMIT 0x14 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xE0 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ + EMIT 0x0F EMIT 0x6E EMIT 0x76 EMIT 0x18 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xF0 \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x04 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0x6E EMIT 0x5E EMIT 0x1C \ + EMIT 0x0F EMIT 0xF4 EMIT 0xD8 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCD \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x10 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xD5 \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x08 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCF \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x14 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xE5 \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x0C \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCA \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x18 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xF5 \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x10 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCC \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x1C \ + EMIT 0x0F EMIT 0xD4 EMIT 0xDD \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x14 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCE \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x18 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x1C \ + EMIT 0x83 EMIT 0xC7 EMIT 0x20 \ + EMIT 0x83 EMIT 0xC6 EMIT 0x20 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0x7E EMIT 0xC9 + +#define MULADDC_STOP \ + EMIT 0x0F EMIT 0x77 \ + __asm mov c, ecx \ + __asm mov d, edi \ + __asm mov s, esi \ + +#else + +#define MULADDC_STOP \ + __asm mov c, ecx \ + __asm mov d, edi \ + __asm mov s, esi \ + +#endif /* SSE2 */ +#endif /* MSVC */ + +#endif /* MBEDTLS_HAVE_ASM */ + +#if !defined(MULADDC_CORE) +#if defined(MBEDTLS_HAVE_UDBL) + +#define MULADDC_INIT \ +{ \ + mbedtls_t_udbl r; \ + mbedtls_mpi_uint r0, r1; + +#define MULADDC_CORE \ + r = *(s++) * (mbedtls_t_udbl) b; \ + r0 = (mbedtls_mpi_uint) r; \ + r1 = (mbedtls_mpi_uint)( r >> biL ); \ + r0 += c; r1 += (r0 < c); \ + r0 += *d; r1 += (r0 < *d); \ + c = r1; *(d++) = r0; + +#define MULADDC_STOP \ +} + +#else +#define MULADDC_INIT \ +{ \ + mbedtls_mpi_uint s0, s1, b0, b1; \ + mbedtls_mpi_uint r0, r1, rx, ry; \ + b0 = ( b << biH ) >> biH; \ + b1 = ( b >> biH ); + +#define MULADDC_CORE \ + s0 = ( *s << biH ) >> biH; \ + s1 = ( *s >> biH ); s++; \ + rx = s0 * b1; r0 = s0 * b0; \ + ry = s1 * b0; r1 = s1 * b1; \ + r1 += ( rx >> biH ); \ + r1 += ( ry >> biH ); \ + rx <<= biH; ry <<= biH; \ + r0 += rx; r1 += (r0 < rx); \ + r0 += ry; r1 += (r0 < ry); \ + r0 += c; r1 += (r0 < c); \ + r0 += *d; r1 += (r0 < *d); \ + c = r1; *(d++) = r0; + +#define MULADDC_STOP \ +} + +#endif /* C (generic) */ +#endif /* C (longlong) */ + +#endif /* bn_mul.h */ diff --git a/src/common/mbedtls/include/mbedtls/certs.h b/src/common/mbedtls/include/mbedtls/certs.h new file mode 100644 index 0000000000..7b240f4e6a --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/certs.h @@ -0,0 +1,262 @@ +/** + * \file certs.h + * + * \brief Sample certificates and DHM parameters for testing + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_CERTS_H +#define MBEDTLS_CERTS_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* List of all PEM-encoded CA certificates, terminated by NULL; + * PEM encoded if MBEDTLS_PEM_PARSE_C is enabled, DER encoded + * otherwise. */ +extern const char * mbedtls_test_cas[]; +extern const size_t mbedtls_test_cas_len[]; + +/* List of all DER-encoded CA certificates, terminated by NULL */ +extern const unsigned char * mbedtls_test_cas_der[]; +extern const size_t mbedtls_test_cas_der_len[]; + +#if defined(MBEDTLS_PEM_PARSE_C) +/* Concatenation of all CA certificates in PEM format if available */ +extern const char mbedtls_test_cas_pem[]; +extern const size_t mbedtls_test_cas_pem_len; +#endif /* MBEDTLS_PEM_PARSE_C */ + +/* + * CA test certificates + */ + +extern const char mbedtls_test_ca_crt_ec_pem[]; +extern const char mbedtls_test_ca_key_ec_pem[]; +extern const char mbedtls_test_ca_pwd_ec_pem[]; +extern const char mbedtls_test_ca_key_rsa_pem[]; +extern const char mbedtls_test_ca_pwd_rsa_pem[]; +extern const char mbedtls_test_ca_crt_rsa_sha1_pem[]; +extern const char mbedtls_test_ca_crt_rsa_sha256_pem[]; + +extern const unsigned char mbedtls_test_ca_crt_ec_der[]; +extern const unsigned char mbedtls_test_ca_key_ec_der[]; +extern const unsigned char mbedtls_test_ca_key_rsa_der[]; +extern const unsigned char mbedtls_test_ca_crt_rsa_sha1_der[]; +extern const unsigned char mbedtls_test_ca_crt_rsa_sha256_der[]; + +extern const size_t mbedtls_test_ca_crt_ec_pem_len; +extern const size_t mbedtls_test_ca_key_ec_pem_len; +extern const size_t mbedtls_test_ca_pwd_ec_pem_len; +extern const size_t mbedtls_test_ca_key_rsa_pem_len; +extern const size_t mbedtls_test_ca_pwd_rsa_pem_len; +extern const size_t mbedtls_test_ca_crt_rsa_sha1_pem_len; +extern const size_t mbedtls_test_ca_crt_rsa_sha256_pem_len; + +extern const size_t mbedtls_test_ca_crt_ec_der_len; +extern const size_t mbedtls_test_ca_key_ec_der_len; +extern const size_t mbedtls_test_ca_pwd_ec_der_len; +extern const size_t mbedtls_test_ca_key_rsa_der_len; +extern const size_t mbedtls_test_ca_pwd_rsa_der_len; +extern const size_t mbedtls_test_ca_crt_rsa_sha1_der_len; +extern const size_t mbedtls_test_ca_crt_rsa_sha256_der_len; + +/* Config-dependent dispatch between PEM and DER encoding + * (PEM if enabled, otherwise DER) */ + +extern const char mbedtls_test_ca_crt_ec[]; +extern const char mbedtls_test_ca_key_ec[]; +extern const char mbedtls_test_ca_pwd_ec[]; +extern const char mbedtls_test_ca_key_rsa[]; +extern const char mbedtls_test_ca_pwd_rsa[]; +extern const char mbedtls_test_ca_crt_rsa_sha1[]; +extern const char mbedtls_test_ca_crt_rsa_sha256[]; + +extern const size_t mbedtls_test_ca_crt_ec_len; +extern const size_t mbedtls_test_ca_key_ec_len; +extern const size_t mbedtls_test_ca_pwd_ec_len; +extern const size_t mbedtls_test_ca_key_rsa_len; +extern const size_t mbedtls_test_ca_pwd_rsa_len; +extern const size_t mbedtls_test_ca_crt_rsa_sha1_len; +extern const size_t mbedtls_test_ca_crt_rsa_sha256_len; + +/* Config-dependent dispatch between SHA-1 and SHA-256 + * (SHA-256 if enabled, otherwise SHA-1) */ + +extern const char mbedtls_test_ca_crt_rsa[]; +extern const size_t mbedtls_test_ca_crt_rsa_len; + +/* Config-dependent dispatch between EC and RSA + * (RSA if enabled, otherwise EC) */ + +extern const char * mbedtls_test_ca_crt; +extern const char * mbedtls_test_ca_key; +extern const char * mbedtls_test_ca_pwd; +extern const size_t mbedtls_test_ca_crt_len; +extern const size_t mbedtls_test_ca_key_len; +extern const size_t mbedtls_test_ca_pwd_len; + +/* + * Server test certificates + */ + +extern const char mbedtls_test_srv_crt_ec_pem[]; +extern const char mbedtls_test_srv_key_ec_pem[]; +extern const char mbedtls_test_srv_pwd_ec_pem[]; +extern const char mbedtls_test_srv_key_rsa_pem[]; +extern const char mbedtls_test_srv_pwd_rsa_pem[]; +extern const char mbedtls_test_srv_crt_rsa_sha1_pem[]; +extern const char mbedtls_test_srv_crt_rsa_sha256_pem[]; + +extern const unsigned char mbedtls_test_srv_crt_ec_der[]; +extern const unsigned char mbedtls_test_srv_key_ec_der[]; +extern const unsigned char mbedtls_test_srv_key_rsa_der[]; +extern const unsigned char mbedtls_test_srv_crt_rsa_sha1_der[]; +extern const unsigned char mbedtls_test_srv_crt_rsa_sha256_der[]; + +extern const size_t mbedtls_test_srv_crt_ec_pem_len; +extern const size_t mbedtls_test_srv_key_ec_pem_len; +extern const size_t mbedtls_test_srv_pwd_ec_pem_len; +extern const size_t mbedtls_test_srv_key_rsa_pem_len; +extern const size_t mbedtls_test_srv_pwd_rsa_pem_len; +extern const size_t mbedtls_test_srv_crt_rsa_sha1_pem_len; +extern const size_t mbedtls_test_srv_crt_rsa_sha256_pem_len; + +extern const size_t mbedtls_test_srv_crt_ec_der_len; +extern const size_t mbedtls_test_srv_key_ec_der_len; +extern const size_t mbedtls_test_srv_pwd_ec_der_len; +extern const size_t mbedtls_test_srv_key_rsa_der_len; +extern const size_t mbedtls_test_srv_pwd_rsa_der_len; +extern const size_t mbedtls_test_srv_crt_rsa_sha1_der_len; +extern const size_t mbedtls_test_srv_crt_rsa_sha256_der_len; + +/* Config-dependent dispatch between PEM and DER encoding + * (PEM if enabled, otherwise DER) */ + +extern const char mbedtls_test_srv_crt_ec[]; +extern const char mbedtls_test_srv_key_ec[]; +extern const char mbedtls_test_srv_pwd_ec[]; +extern const char mbedtls_test_srv_key_rsa[]; +extern const char mbedtls_test_srv_pwd_rsa[]; +extern const char mbedtls_test_srv_crt_rsa_sha1[]; +extern const char mbedtls_test_srv_crt_rsa_sha256[]; + +extern const size_t mbedtls_test_srv_crt_ec_len; +extern const size_t mbedtls_test_srv_key_ec_len; +extern const size_t mbedtls_test_srv_pwd_ec_len; +extern const size_t mbedtls_test_srv_key_rsa_len; +extern const size_t mbedtls_test_srv_pwd_rsa_len; +extern const size_t mbedtls_test_srv_crt_rsa_sha1_len; +extern const size_t mbedtls_test_srv_crt_rsa_sha256_len; + +/* Config-dependent dispatch between SHA-1 and SHA-256 + * (SHA-256 if enabled, otherwise SHA-1) */ + +extern const char mbedtls_test_srv_crt_rsa[]; +extern const size_t mbedtls_test_srv_crt_rsa_len; + +/* Config-dependent dispatch between EC and RSA + * (RSA if enabled, otherwise EC) */ + +extern const char * mbedtls_test_srv_crt; +extern const char * mbedtls_test_srv_key; +extern const char * mbedtls_test_srv_pwd; +extern const size_t mbedtls_test_srv_crt_len; +extern const size_t mbedtls_test_srv_key_len; +extern const size_t mbedtls_test_srv_pwd_len; + +/* + * Client test certificates + */ + +extern const char mbedtls_test_cli_crt_ec_pem[]; +extern const char mbedtls_test_cli_key_ec_pem[]; +extern const char mbedtls_test_cli_pwd_ec_pem[]; +extern const char mbedtls_test_cli_key_rsa_pem[]; +extern const char mbedtls_test_cli_pwd_rsa_pem[]; +extern const char mbedtls_test_cli_crt_rsa_pem[]; + +extern const unsigned char mbedtls_test_cli_crt_ec_der[]; +extern const unsigned char mbedtls_test_cli_key_ec_der[]; +extern const unsigned char mbedtls_test_cli_key_rsa_der[]; +extern const unsigned char mbedtls_test_cli_crt_rsa_der[]; + +extern const size_t mbedtls_test_cli_crt_ec_pem_len; +extern const size_t mbedtls_test_cli_key_ec_pem_len; +extern const size_t mbedtls_test_cli_pwd_ec_pem_len; +extern const size_t mbedtls_test_cli_key_rsa_pem_len; +extern const size_t mbedtls_test_cli_pwd_rsa_pem_len; +extern const size_t mbedtls_test_cli_crt_rsa_pem_len; + +extern const size_t mbedtls_test_cli_crt_ec_der_len; +extern const size_t mbedtls_test_cli_key_ec_der_len; +extern const size_t mbedtls_test_cli_key_rsa_der_len; +extern const size_t mbedtls_test_cli_crt_rsa_der_len; + +/* Config-dependent dispatch between PEM and DER encoding + * (PEM if enabled, otherwise DER) */ + +extern const char mbedtls_test_cli_crt_ec[]; +extern const char mbedtls_test_cli_key_ec[]; +extern const char mbedtls_test_cli_pwd_ec[]; +extern const char mbedtls_test_cli_key_rsa[]; +extern const char mbedtls_test_cli_pwd_rsa[]; +extern const char mbedtls_test_cli_crt_rsa[]; + +extern const size_t mbedtls_test_cli_crt_ec_len; +extern const size_t mbedtls_test_cli_key_ec_len; +extern const size_t mbedtls_test_cli_pwd_ec_len; +extern const size_t mbedtls_test_cli_key_rsa_len; +extern const size_t mbedtls_test_cli_pwd_rsa_len; +extern const size_t mbedtls_test_cli_crt_rsa_len; + +/* Config-dependent dispatch between EC and RSA + * (RSA if enabled, otherwise EC) */ + +extern const char * mbedtls_test_cli_crt; +extern const char * mbedtls_test_cli_key; +extern const char * mbedtls_test_cli_pwd; +extern const size_t mbedtls_test_cli_crt_len; +extern const size_t mbedtls_test_cli_key_len; +extern const size_t mbedtls_test_cli_pwd_len; + +#ifdef __cplusplus +} +#endif + +#endif /* certs.h */ diff --git a/src/common/mbedtls/include/mbedtls/check_config.h b/src/common/mbedtls/include/mbedtls/check_config.h new file mode 100644 index 0000000000..26699f1adb --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/check_config.h @@ -0,0 +1,746 @@ +/** + * \file check_config.h + * + * \brief Consistency checks for configuration options + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +/* + * It is recommended to include this file from your config.h + * in order to catch dependency issues early. + */ + +#ifndef MBEDTLS_CHECK_CONFIG_H +#define MBEDTLS_CHECK_CONFIG_H + +/* + * We assume CHAR_BIT is 8 in many places. In practice, this is true on our + * target platforms, so not an issue, but let's just be extra sure. + */ +#include +#if CHAR_BIT != 8 +#error "mbed TLS requires a platform with 8-bit chars" +#endif + +#if defined(TARGET_LIKE_MBED) && \ + ( defined(MBEDTLS_NET_C) || defined(MBEDTLS_TIMING_C) ) +#error "The NET and TIMING modules are not available for mbed OS - please use the network and timing functions provided by mbed OS" +#endif + +#if defined(MBEDTLS_DEPRECATED_WARNING) && \ + !defined(__GNUC__) && !defined(__clang__) +#error "MBEDTLS_DEPRECATED_WARNING only works with GCC and Clang" +#endif + +#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_HAVE_TIME) +#error "MBEDTLS_HAVE_TIME_DATE without MBEDTLS_HAVE_TIME does not make sense" +#endif + +#if defined(MBEDTLS_AESNI_C) && !defined(MBEDTLS_HAVE_ASM) +#error "MBEDTLS_AESNI_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_CTR_DRBG_C) && !defined(MBEDTLS_AES_C) +#error "MBEDTLS_CTR_DRBG_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_DHM_C) && !defined(MBEDTLS_BIGNUM_C) +#error "MBEDTLS_DHM_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT) && !defined(MBEDTLS_SSL_TRUNCATED_HMAC) +#error "MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_CMAC_C) && \ + !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_DES_C) +#error "MBEDTLS_CMAC_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_NIST_KW_C) && \ + ( !defined(MBEDTLS_AES_C) || !defined(MBEDTLS_CIPHER_C) ) +#error "MBEDTLS_NIST_KW_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECDH_C) && !defined(MBEDTLS_ECP_C) +#error "MBEDTLS_ECDH_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECDSA_C) && \ + ( !defined(MBEDTLS_ECP_C) || \ + !defined(MBEDTLS_ASN1_PARSE_C) || \ + !defined(MBEDTLS_ASN1_WRITE_C) ) +#error "MBEDTLS_ECDSA_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECJPAKE_C) && \ + ( !defined(MBEDTLS_ECP_C) || !defined(MBEDTLS_MD_C) ) +#error "MBEDTLS_ECJPAKE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) && \ + ( defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) || \ + defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) || \ + defined(MBEDTLS_ECDSA_SIGN_ALT) || \ + defined(MBEDTLS_ECDSA_VERIFY_ALT) || \ + defined(MBEDTLS_ECDSA_GENKEY_ALT) || \ + defined(MBEDTLS_ECP_INTERNAL_ALT) || \ + defined(MBEDTLS_ECP_ALT) ) +#error "MBEDTLS_ECP_RESTARTABLE defined, but it cannot coexist with an alternative ECP implementation" +#endif + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) && !defined(MBEDTLS_HMAC_DRBG_C) +#error "MBEDTLS_ECDSA_DETERMINISTIC defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_C) && ( !defined(MBEDTLS_BIGNUM_C) || ( \ + !defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) ) ) +#error "MBEDTLS_ECP_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_C) && !( \ + defined(MBEDTLS_ECP_ALT) || \ + defined(MBEDTLS_CTR_DRBG_C) || \ + defined(MBEDTLS_HMAC_DRBG_C) || \ + defined(MBEDTLS_SHA512_C) || \ + defined(MBEDTLS_SHA256_C) || \ + defined(MBEDTLS_ECP_NO_INTERNAL_RNG)) +#error "MBEDTLS_ECP_C requires a DRBG or SHA-2 module unless MBEDTLS_ECP_NO_INTERNAL_RNG is defined or an alternative implementation is used" +#endif + +#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_ASN1_PARSE_C) +#error "MBEDTLS_PK_PARSE_C defined, but not all prerequesites" +#endif + +#if defined(MBEDTLS_ENTROPY_C) && (!defined(MBEDTLS_SHA512_C) && \ + !defined(MBEDTLS_SHA256_C)) +#error "MBEDTLS_ENTROPY_C defined, but not all prerequisites" +#endif +#if defined(MBEDTLS_ENTROPY_C) && defined(MBEDTLS_SHA512_C) && \ + defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 64) +#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high" +#endif +#if defined(MBEDTLS_ENTROPY_C) && \ + ( !defined(MBEDTLS_SHA512_C) || defined(MBEDTLS_ENTROPY_FORCE_SHA256) ) \ + && defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 32) +#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high" +#endif +#if defined(MBEDTLS_ENTROPY_C) && \ + defined(MBEDTLS_ENTROPY_FORCE_SHA256) && !defined(MBEDTLS_SHA256_C) +#error "MBEDTLS_ENTROPY_FORCE_SHA256 defined, but not all prerequisites" +#endif + +#if defined(__has_feature) +#if __has_feature(memory_sanitizer) +#define MBEDTLS_HAS_MEMSAN +#endif +#endif +#if defined(MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN) && !defined(MBEDTLS_HAS_MEMSAN) +#error "MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN requires building with MemorySanitizer" +#endif +#undef MBEDTLS_HAS_MEMSAN + +#if defined(MBEDTLS_TEST_NULL_ENTROPY) && \ + ( !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) ) +#error "MBEDTLS_TEST_NULL_ENTROPY defined, but not all prerequisites" +#endif +#if defined(MBEDTLS_TEST_NULL_ENTROPY) && \ + ( defined(MBEDTLS_ENTROPY_NV_SEED) || defined(MBEDTLS_ENTROPY_HARDWARE_ALT) || \ + defined(MBEDTLS_HAVEGE_C) ) +#error "MBEDTLS_TEST_NULL_ENTROPY defined, but entropy sources too" +#endif + +#if defined(MBEDTLS_GCM_C) && ( \ + !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_CAMELLIA_C) ) +#error "MBEDTLS_GCM_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_RANDOMIZE_JAC_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_ADD_MIXED_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_DOUBLE_JAC_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_NORMALIZE_JAC_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_RANDOMIZE_MXZ_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_NORMALIZE_MXZ_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_HAVEGE_C) && !defined(MBEDTLS_TIMING_C) +#error "MBEDTLS_HAVEGE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_HKDF_C) && !defined(MBEDTLS_MD_C) +#error "MBEDTLS_HKDF_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_HMAC_DRBG_C) && !defined(MBEDTLS_MD_C) +#error "MBEDTLS_HMAC_DRBG_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) && \ + ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) ) +#error "MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) && \ + ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) ) +#error "MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) && !defined(MBEDTLS_DHM_C) +#error "MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) && \ + !defined(MBEDTLS_ECDH_C) +#error "MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) && \ + ( !defined(MBEDTLS_DHM_C) || !defined(MBEDTLS_RSA_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) && \ + ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_RSA_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) && \ + ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_ECDSA_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) ) +#error "MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) && \ + ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \ + !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) && \ + ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \ + !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_KEY_EXCHANGE_RSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ + ( !defined(MBEDTLS_ECJPAKE_C) || !defined(MBEDTLS_SHA256_C) || \ + !defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) ) +#error "MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) && \ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) +#error "MBEDTLS_MEMORY_BUFFER_ALLOC_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_MEMORY_BACKTRACE) && !defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) +#error "MBEDTLS_MEMORY_BACKTRACE defined, but not all prerequesites" +#endif + +#if defined(MBEDTLS_MEMORY_DEBUG) && !defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) +#error "MBEDTLS_MEMORY_DEBUG defined, but not all prerequesites" +#endif + +#if defined(MBEDTLS_PADLOCK_C) && !defined(MBEDTLS_HAVE_ASM) +#error "MBEDTLS_PADLOCK_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) && !defined(MBEDTLS_BASE64_C) +#error "MBEDTLS_PEM_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PEM_WRITE_C) && !defined(MBEDTLS_BASE64_C) +#error "MBEDTLS_PEM_WRITE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PK_C) && \ + ( !defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_ECP_C) ) +#error "MBEDTLS_PK_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_PK_C) +#error "MBEDTLS_PK_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PK_WRITE_C) && !defined(MBEDTLS_PK_C) +#error "MBEDTLS_PK_WRITE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PKCS11_C) && !defined(MBEDTLS_PK_C) +#error "MBEDTLS_PKCS11_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_EXIT_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_EXIT_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_EXIT_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_EXIT) ||\ + defined(MBEDTLS_PLATFORM_EXIT_ALT) ) +#error "MBEDTLS_PLATFORM_EXIT_MACRO and MBEDTLS_PLATFORM_STD_EXIT/MBEDTLS_PLATFORM_EXIT_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_ALT) &&\ + ( !defined(MBEDTLS_PLATFORM_C) ||\ + !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_TIME_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) ||\ + !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_TIME_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) ||\ + !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_TIME_TYPE_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_TIME) ||\ + defined(MBEDTLS_PLATFORM_TIME_ALT) ) +#error "MBEDTLS_PLATFORM_TIME_MACRO and MBEDTLS_PLATFORM_STD_TIME/MBEDTLS_PLATFORM_TIME_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_TIME) ||\ + defined(MBEDTLS_PLATFORM_TIME_ALT) ) +#error "MBEDTLS_PLATFORM_TIME_TYPE_MACRO and MBEDTLS_PLATFORM_STD_TIME/MBEDTLS_PLATFORM_TIME_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_FPRINTF_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_FPRINTF_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_FPRINTF) ||\ + defined(MBEDTLS_PLATFORM_FPRINTF_ALT) ) +#error "MBEDTLS_PLATFORM_FPRINTF_MACRO and MBEDTLS_PLATFORM_STD_FPRINTF/MBEDTLS_PLATFORM_FPRINTF_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) +#error "MBEDTLS_PLATFORM_FREE_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\ + defined(MBEDTLS_PLATFORM_STD_FREE) +#error "MBEDTLS_PLATFORM_FREE_MACRO and MBEDTLS_PLATFORM_STD_FREE cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && !defined(MBEDTLS_PLATFORM_CALLOC_MACRO) +#error "MBEDTLS_PLATFORM_CALLOC_MACRO must be defined if MBEDTLS_PLATFORM_FREE_MACRO is" +#endif + +#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) +#error "MBEDTLS_PLATFORM_CALLOC_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\ + defined(MBEDTLS_PLATFORM_STD_CALLOC) +#error "MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_STD_CALLOC cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && !defined(MBEDTLS_PLATFORM_FREE_MACRO) +#error "MBEDTLS_PLATFORM_FREE_MACRO must be defined if MBEDTLS_PLATFORM_CALLOC_MACRO is" +#endif + +#if defined(MBEDTLS_PLATFORM_MEMORY) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_MEMORY defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_PRINTF_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_PRINTF_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_PRINTF) ||\ + defined(MBEDTLS_PLATFORM_PRINTF_ALT) ) +#error "MBEDTLS_PLATFORM_PRINTF_MACRO and MBEDTLS_PLATFORM_STD_PRINTF/MBEDTLS_PLATFORM_PRINTF_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_SNPRINTF_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_SNPRINTF) ||\ + defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) ) +#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO and MBEDTLS_PLATFORM_STD_SNPRINTF/MBEDTLS_PLATFORM_SNPRINTF_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR) &&\ + !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) +#error "MBEDTLS_PLATFORM_STD_MEM_HDR defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_CALLOC) && !defined(MBEDTLS_PLATFORM_MEMORY) +#error "MBEDTLS_PLATFORM_STD_CALLOC defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_CALLOC) && !defined(MBEDTLS_PLATFORM_MEMORY) +#error "MBEDTLS_PLATFORM_STD_CALLOC defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_FREE) && !defined(MBEDTLS_PLATFORM_MEMORY) +#error "MBEDTLS_PLATFORM_STD_FREE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_EXIT) &&\ + !defined(MBEDTLS_PLATFORM_EXIT_ALT) +#error "MBEDTLS_PLATFORM_STD_EXIT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_TIME) &&\ + ( !defined(MBEDTLS_PLATFORM_TIME_ALT) ||\ + !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_STD_TIME defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_FPRINTF) &&\ + !defined(MBEDTLS_PLATFORM_FPRINTF_ALT) +#error "MBEDTLS_PLATFORM_STD_FPRINTF defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_PRINTF) &&\ + !defined(MBEDTLS_PLATFORM_PRINTF_ALT) +#error "MBEDTLS_PLATFORM_STD_PRINTF defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_SNPRINTF) &&\ + !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) +#error "MBEDTLS_PLATFORM_STD_SNPRINTF defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ENTROPY_NV_SEED) &&\ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_ENTROPY_C) ) +#error "MBEDTLS_ENTROPY_NV_SEED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) &&\ + !defined(MBEDTLS_ENTROPY_NV_SEED) +#error "MBEDTLS_PLATFORM_NV_SEED_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) &&\ + !defined(MBEDTLS_PLATFORM_NV_SEED_ALT) +#error "MBEDTLS_PLATFORM_STD_NV_SEED_READ defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) &&\ + !defined(MBEDTLS_PLATFORM_NV_SEED_ALT) +#error "MBEDTLS_PLATFORM_STD_NV_SEED_WRITE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) ||\ + defined(MBEDTLS_PLATFORM_NV_SEED_ALT) ) +#error "MBEDTLS_PLATFORM_NV_SEED_READ_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_READ cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) ||\ + defined(MBEDTLS_PLATFORM_NV_SEED_ALT) ) +#error "MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_WRITE cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_BIGNUM_C) || \ + !defined(MBEDTLS_OID_C) ) +#error "MBEDTLS_RSA_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_PKCS1_V21) && \ + !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_RSA_C defined, but none of the PKCS1 versions enabled" +#endif + +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) && \ + ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_PKCS1_V21) ) +#error "MBEDTLS_X509_RSASSA_PSS_SUPPORT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_PROTO_SSL3) && ( !defined(MBEDTLS_MD5_C) || \ + !defined(MBEDTLS_SHA1_C) ) +#error "MBEDTLS_SSL_PROTO_SSL3 defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1) && ( !defined(MBEDTLS_MD5_C) || \ + !defined(MBEDTLS_SHA1_C) ) +#error "MBEDTLS_SSL_PROTO_TLS1 defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_1) && ( !defined(MBEDTLS_MD5_C) || \ + !defined(MBEDTLS_SHA1_C) ) +#error "MBEDTLS_SSL_PROTO_TLS1_1 defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && ( !defined(MBEDTLS_SHA1_C) && \ + !defined(MBEDTLS_SHA256_C) && !defined(MBEDTLS_SHA512_C) ) +#error "MBEDTLS_SSL_PROTO_TLS1_2 defined, but not all prerequisites" +#endif + +#if (defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2)) && \ + !(defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) ) +#error "One or more versions of the TLS protocol are enabled " \ + "but no key exchange methods defined with MBEDTLS_KEY_EXCHANGE_xxxx" +#endif + +#if defined(MBEDTLS_SSL_PROTO_DTLS) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_1) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_2) +#error "MBEDTLS_SSL_PROTO_DTLS defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_CLI_C) && !defined(MBEDTLS_SSL_TLS_C) +#error "MBEDTLS_SSL_CLI_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TLS_C) && ( !defined(MBEDTLS_CIPHER_C) || \ + !defined(MBEDTLS_MD_C) ) +#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_SRV_C) && !defined(MBEDTLS_SSL_TLS_C) +#error "MBEDTLS_SSL_SRV_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TLS_C) && (!defined(MBEDTLS_SSL_PROTO_SSL3) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1) && !defined(MBEDTLS_SSL_PROTO_TLS1_1) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_2)) +#error "MBEDTLS_SSL_TLS_C defined, but no protocols are active" +#endif + +#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_SSL3) && \ + defined(MBEDTLS_SSL_PROTO_TLS1_1) && !defined(MBEDTLS_SSL_PROTO_TLS1)) +#error "Illegal protocol selection" +#endif + +#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_TLS1) && \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) && !defined(MBEDTLS_SSL_PROTO_TLS1_1)) +#error "Illegal protocol selection" +#endif + +#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_SSL3) && \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) && (!defined(MBEDTLS_SSL_PROTO_TLS1) || \ + !defined(MBEDTLS_SSL_PROTO_TLS1_1))) +#error "Illegal protocol selection" +#endif + +#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && !defined(MBEDTLS_SSL_PROTO_DTLS) +#error "MBEDTLS_SSL_DTLS_HELLO_VERIFY defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && \ + !defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) +#error "MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) && \ + ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) ) +#error "MBEDTLS_SSL_DTLS_ANTI_REPLAY defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT) && \ + ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) ) +#error "MBEDTLS_SSL_DTLS_BADMAC_LIMIT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_1) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_2) +#error "MBEDTLS_SSL_ENCRYPT_THEN_MAC defined, but not all prerequsites" +#endif + +#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_1) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_2) +#error "MBEDTLS_SSL_EXTENDED_MASTER_SECRET defined, but not all prerequsites" +#endif + +#if defined(MBEDTLS_SSL_TICKET_C) && !defined(MBEDTLS_CIPHER_C) +#error "MBEDTLS_SSL_TICKET_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) && \ + !defined(MBEDTLS_SSL_PROTO_SSL3) && !defined(MBEDTLS_SSL_PROTO_TLS1) +#error "MBEDTLS_SSL_CBC_RECORD_SPLITTING defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && \ + !defined(MBEDTLS_X509_CRT_PARSE_C) +#error "MBEDTLS_SSL_SERVER_NAME_INDICATION defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_THREADING_PTHREAD) +#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL) +#error "MBEDTLS_THREADING_PTHREAD defined, but not all prerequisites" +#endif +#define MBEDTLS_THREADING_IMPL +#endif + +#if defined(MBEDTLS_THREADING_ALT) +#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL) +#error "MBEDTLS_THREADING_ALT defined, but not all prerequisites" +#endif +#define MBEDTLS_THREADING_IMPL +#endif + +#if defined(MBEDTLS_THREADING_C) && !defined(MBEDTLS_THREADING_IMPL) +#error "MBEDTLS_THREADING_C defined, single threading implementation required" +#endif +#undef MBEDTLS_THREADING_IMPL + +#if defined(MBEDTLS_VERSION_FEATURES) && !defined(MBEDTLS_VERSION_C) +#error "MBEDTLS_VERSION_FEATURES defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_USE_C) && ( !defined(MBEDTLS_BIGNUM_C) || \ + !defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_PARSE_C) || \ + !defined(MBEDTLS_PK_PARSE_C) ) +#error "MBEDTLS_X509_USE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CREATE_C) && ( !defined(MBEDTLS_BIGNUM_C) || \ + !defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_WRITE_C) || \ + !defined(MBEDTLS_PK_WRITE_C) ) +#error "MBEDTLS_X509_CREATE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_CERTS_C) && !defined(MBEDTLS_X509_USE_C) +#error "MBEDTLS_CERTS_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) +#error "MBEDTLS_X509_CRT_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CRL_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) +#error "MBEDTLS_X509_CRL_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CSR_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) +#error "MBEDTLS_X509_CSR_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CRT_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) ) +#error "MBEDTLS_X509_CRT_WRITE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CSR_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) ) +#error "MBEDTLS_X509_CSR_WRITE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_HAVE_INT32) && defined(MBEDTLS_HAVE_INT64) +#error "MBEDTLS_HAVE_INT32 and MBEDTLS_HAVE_INT64 cannot be defined simultaneously" +#endif /* MBEDTLS_HAVE_INT32 && MBEDTLS_HAVE_INT64 */ + +#if ( defined(MBEDTLS_HAVE_INT32) || defined(MBEDTLS_HAVE_INT64) ) && \ + defined(MBEDTLS_HAVE_ASM) +#error "MBEDTLS_HAVE_INT32/MBEDTLS_HAVE_INT64 and MBEDTLS_HAVE_ASM cannot be defined simultaneously" +#endif /* (MBEDTLS_HAVE_INT32 || MBEDTLS_HAVE_INT64) && MBEDTLS_HAVE_ASM */ + +/* + * Avoid warning from -pedantic. This is a convenient place for this + * workaround since this is included by every single file before the + * #if defined(MBEDTLS_xxx_C) that results in empty translation units. + */ +typedef int mbedtls_iso_c_forbids_empty_translation_units; + +#endif /* MBEDTLS_CHECK_CONFIG_H */ diff --git a/src/common/mbedtls/include/mbedtls/cipher.h b/src/common/mbedtls/include/mbedtls/cipher.h new file mode 100644 index 0000000000..a208849184 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/cipher.h @@ -0,0 +1,882 @@ +/** + * \file cipher.h + * + * \brief This file contains an abstraction interface for use with the cipher + * primitives provided by the library. It provides a common interface to all of + * the available cipher operations. + * + * \author Adriaan de Jong + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_CIPHER_H +#define MBEDTLS_CIPHER_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include "platform_util.h" + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +#define MBEDTLS_CIPHER_MODE_AEAD +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +#define MBEDTLS_CIPHER_MODE_WITH_PADDING +#endif + +#if defined(MBEDTLS_ARC4_C) || defined(MBEDTLS_CIPHER_NULL_CIPHER) || \ + defined(MBEDTLS_CHACHA20_C) +#define MBEDTLS_CIPHER_MODE_STREAM +#endif + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +#define MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE -0x6080 /**< The selected feature is not available. */ +#define MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA -0x6100 /**< Bad input parameters. */ +#define MBEDTLS_ERR_CIPHER_ALLOC_FAILED -0x6180 /**< Failed to allocate memory. */ +#define MBEDTLS_ERR_CIPHER_INVALID_PADDING -0x6200 /**< Input data contains invalid padding and is rejected. */ +#define MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED -0x6280 /**< Decryption of block requires a full block. */ +#define MBEDTLS_ERR_CIPHER_AUTH_FAILED -0x6300 /**< Authentication failed (for AEAD modes). */ +#define MBEDTLS_ERR_CIPHER_INVALID_CONTEXT -0x6380 /**< The context is invalid. For example, because it was freed. */ + +/* MBEDTLS_ERR_CIPHER_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_CIPHER_HW_ACCEL_FAILED -0x6400 /**< Cipher hardware accelerator failed. */ + +#define MBEDTLS_CIPHER_VARIABLE_IV_LEN 0x01 /**< Cipher accepts IVs of variable length. */ +#define MBEDTLS_CIPHER_VARIABLE_KEY_LEN 0x02 /**< Cipher accepts keys of variable length. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Supported cipher types. + * + * \warning RC4 and DES are considered weak ciphers and their use + * constitutes a security risk. Arm recommends considering stronger + * ciphers instead. + */ +typedef enum { + MBEDTLS_CIPHER_ID_NONE = 0, /**< Placeholder to mark the end of cipher ID lists. */ + MBEDTLS_CIPHER_ID_NULL, /**< The identity cipher, treated as a stream cipher. */ + MBEDTLS_CIPHER_ID_AES, /**< The AES cipher. */ + MBEDTLS_CIPHER_ID_DES, /**< The DES cipher. */ + MBEDTLS_CIPHER_ID_3DES, /**< The Triple DES cipher. */ + MBEDTLS_CIPHER_ID_CAMELLIA, /**< The Camellia cipher. */ + MBEDTLS_CIPHER_ID_BLOWFISH, /**< The Blowfish cipher. */ + MBEDTLS_CIPHER_ID_ARC4, /**< The RC4 cipher. */ + MBEDTLS_CIPHER_ID_ARIA, /**< The Aria cipher. */ + MBEDTLS_CIPHER_ID_CHACHA20, /**< The ChaCha20 cipher. */ +} mbedtls_cipher_id_t; + +/** + * \brief Supported {cipher type, cipher mode} pairs. + * + * \warning RC4 and DES are considered weak ciphers and their use + * constitutes a security risk. Arm recommends considering stronger + * ciphers instead. + */ +typedef enum { + MBEDTLS_CIPHER_NONE = 0, /**< Placeholder to mark the end of cipher-pair lists. */ + MBEDTLS_CIPHER_NULL, /**< The identity stream cipher. */ + MBEDTLS_CIPHER_AES_128_ECB, /**< AES cipher with 128-bit ECB mode. */ + MBEDTLS_CIPHER_AES_192_ECB, /**< AES cipher with 192-bit ECB mode. */ + MBEDTLS_CIPHER_AES_256_ECB, /**< AES cipher with 256-bit ECB mode. */ + MBEDTLS_CIPHER_AES_128_CBC, /**< AES cipher with 128-bit CBC mode. */ + MBEDTLS_CIPHER_AES_192_CBC, /**< AES cipher with 192-bit CBC mode. */ + MBEDTLS_CIPHER_AES_256_CBC, /**< AES cipher with 256-bit CBC mode. */ + MBEDTLS_CIPHER_AES_128_CFB128, /**< AES cipher with 128-bit CFB128 mode. */ + MBEDTLS_CIPHER_AES_192_CFB128, /**< AES cipher with 192-bit CFB128 mode. */ + MBEDTLS_CIPHER_AES_256_CFB128, /**< AES cipher with 256-bit CFB128 mode. */ + MBEDTLS_CIPHER_AES_128_CTR, /**< AES cipher with 128-bit CTR mode. */ + MBEDTLS_CIPHER_AES_192_CTR, /**< AES cipher with 192-bit CTR mode. */ + MBEDTLS_CIPHER_AES_256_CTR, /**< AES cipher with 256-bit CTR mode. */ + MBEDTLS_CIPHER_AES_128_GCM, /**< AES cipher with 128-bit GCM mode. */ + MBEDTLS_CIPHER_AES_192_GCM, /**< AES cipher with 192-bit GCM mode. */ + MBEDTLS_CIPHER_AES_256_GCM, /**< AES cipher with 256-bit GCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_ECB, /**< Camellia cipher with 128-bit ECB mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_ECB, /**< Camellia cipher with 192-bit ECB mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_ECB, /**< Camellia cipher with 256-bit ECB mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CBC, /**< Camellia cipher with 128-bit CBC mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CBC, /**< Camellia cipher with 192-bit CBC mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CBC, /**< Camellia cipher with 256-bit CBC mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CFB128, /**< Camellia cipher with 128-bit CFB128 mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CFB128, /**< Camellia cipher with 192-bit CFB128 mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CFB128, /**< Camellia cipher with 256-bit CFB128 mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CTR, /**< Camellia cipher with 128-bit CTR mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CTR, /**< Camellia cipher with 192-bit CTR mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CTR, /**< Camellia cipher with 256-bit CTR mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_GCM, /**< Camellia cipher with 128-bit GCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_GCM, /**< Camellia cipher with 192-bit GCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_GCM, /**< Camellia cipher with 256-bit GCM mode. */ + MBEDTLS_CIPHER_DES_ECB, /**< DES cipher with ECB mode. */ + MBEDTLS_CIPHER_DES_CBC, /**< DES cipher with CBC mode. */ + MBEDTLS_CIPHER_DES_EDE_ECB, /**< DES cipher with EDE ECB mode. */ + MBEDTLS_CIPHER_DES_EDE_CBC, /**< DES cipher with EDE CBC mode. */ + MBEDTLS_CIPHER_DES_EDE3_ECB, /**< DES cipher with EDE3 ECB mode. */ + MBEDTLS_CIPHER_DES_EDE3_CBC, /**< DES cipher with EDE3 CBC mode. */ + MBEDTLS_CIPHER_BLOWFISH_ECB, /**< Blowfish cipher with ECB mode. */ + MBEDTLS_CIPHER_BLOWFISH_CBC, /**< Blowfish cipher with CBC mode. */ + MBEDTLS_CIPHER_BLOWFISH_CFB64, /**< Blowfish cipher with CFB64 mode. */ + MBEDTLS_CIPHER_BLOWFISH_CTR, /**< Blowfish cipher with CTR mode. */ + MBEDTLS_CIPHER_ARC4_128, /**< RC4 cipher with 128-bit mode. */ + MBEDTLS_CIPHER_AES_128_CCM, /**< AES cipher with 128-bit CCM mode. */ + MBEDTLS_CIPHER_AES_192_CCM, /**< AES cipher with 192-bit CCM mode. */ + MBEDTLS_CIPHER_AES_256_CCM, /**< AES cipher with 256-bit CCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CCM, /**< Camellia cipher with 128-bit CCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CCM, /**< Camellia cipher with 192-bit CCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CCM, /**< Camellia cipher with 256-bit CCM mode. */ + MBEDTLS_CIPHER_ARIA_128_ECB, /**< Aria cipher with 128-bit key and ECB mode. */ + MBEDTLS_CIPHER_ARIA_192_ECB, /**< Aria cipher with 192-bit key and ECB mode. */ + MBEDTLS_CIPHER_ARIA_256_ECB, /**< Aria cipher with 256-bit key and ECB mode. */ + MBEDTLS_CIPHER_ARIA_128_CBC, /**< Aria cipher with 128-bit key and CBC mode. */ + MBEDTLS_CIPHER_ARIA_192_CBC, /**< Aria cipher with 192-bit key and CBC mode. */ + MBEDTLS_CIPHER_ARIA_256_CBC, /**< Aria cipher with 256-bit key and CBC mode. */ + MBEDTLS_CIPHER_ARIA_128_CFB128, /**< Aria cipher with 128-bit key and CFB-128 mode. */ + MBEDTLS_CIPHER_ARIA_192_CFB128, /**< Aria cipher with 192-bit key and CFB-128 mode. */ + MBEDTLS_CIPHER_ARIA_256_CFB128, /**< Aria cipher with 256-bit key and CFB-128 mode. */ + MBEDTLS_CIPHER_ARIA_128_CTR, /**< Aria cipher with 128-bit key and CTR mode. */ + MBEDTLS_CIPHER_ARIA_192_CTR, /**< Aria cipher with 192-bit key and CTR mode. */ + MBEDTLS_CIPHER_ARIA_256_CTR, /**< Aria cipher with 256-bit key and CTR mode. */ + MBEDTLS_CIPHER_ARIA_128_GCM, /**< Aria cipher with 128-bit key and GCM mode. */ + MBEDTLS_CIPHER_ARIA_192_GCM, /**< Aria cipher with 192-bit key and GCM mode. */ + MBEDTLS_CIPHER_ARIA_256_GCM, /**< Aria cipher with 256-bit key and GCM mode. */ + MBEDTLS_CIPHER_ARIA_128_CCM, /**< Aria cipher with 128-bit key and CCM mode. */ + MBEDTLS_CIPHER_ARIA_192_CCM, /**< Aria cipher with 192-bit key and CCM mode. */ + MBEDTLS_CIPHER_ARIA_256_CCM, /**< Aria cipher with 256-bit key and CCM mode. */ + MBEDTLS_CIPHER_AES_128_OFB, /**< AES 128-bit cipher in OFB mode. */ + MBEDTLS_CIPHER_AES_192_OFB, /**< AES 192-bit cipher in OFB mode. */ + MBEDTLS_CIPHER_AES_256_OFB, /**< AES 256-bit cipher in OFB mode. */ + MBEDTLS_CIPHER_AES_128_XTS, /**< AES 128-bit cipher in XTS block mode. */ + MBEDTLS_CIPHER_AES_256_XTS, /**< AES 256-bit cipher in XTS block mode. */ + MBEDTLS_CIPHER_CHACHA20, /**< ChaCha20 stream cipher. */ + MBEDTLS_CIPHER_CHACHA20_POLY1305, /**< ChaCha20-Poly1305 AEAD cipher. */ +} mbedtls_cipher_type_t; + +/** Supported cipher modes. */ +typedef enum { + MBEDTLS_MODE_NONE = 0, /**< None. */ + MBEDTLS_MODE_ECB, /**< The ECB cipher mode. */ + MBEDTLS_MODE_CBC, /**< The CBC cipher mode. */ + MBEDTLS_MODE_CFB, /**< The CFB cipher mode. */ + MBEDTLS_MODE_OFB, /**< The OFB cipher mode. */ + MBEDTLS_MODE_CTR, /**< The CTR cipher mode. */ + MBEDTLS_MODE_GCM, /**< The GCM cipher mode. */ + MBEDTLS_MODE_STREAM, /**< The stream cipher mode. */ + MBEDTLS_MODE_CCM, /**< The CCM cipher mode. */ + MBEDTLS_MODE_XTS, /**< The XTS cipher mode. */ + MBEDTLS_MODE_CHACHAPOLY, /**< The ChaCha-Poly cipher mode. */ +} mbedtls_cipher_mode_t; + +/** Supported cipher padding types. */ +typedef enum { + MBEDTLS_PADDING_PKCS7 = 0, /**< PKCS7 padding (default). */ + MBEDTLS_PADDING_ONE_AND_ZEROS, /**< ISO/IEC 7816-4 padding. */ + MBEDTLS_PADDING_ZEROS_AND_LEN, /**< ANSI X.923 padding. */ + MBEDTLS_PADDING_ZEROS, /**< Zero padding (not reversible). */ + MBEDTLS_PADDING_NONE, /**< Never pad (full blocks only). */ +} mbedtls_cipher_padding_t; + +/** Type of operation. */ +typedef enum { + MBEDTLS_OPERATION_NONE = -1, + MBEDTLS_DECRYPT = 0, + MBEDTLS_ENCRYPT, +} mbedtls_operation_t; + +enum { + /** Undefined key length. */ + MBEDTLS_KEY_LENGTH_NONE = 0, + /** Key length, in bits (including parity), for DES keys. */ + MBEDTLS_KEY_LENGTH_DES = 64, + /** Key length in bits, including parity, for DES in two-key EDE. */ + MBEDTLS_KEY_LENGTH_DES_EDE = 128, + /** Key length in bits, including parity, for DES in three-key EDE. */ + MBEDTLS_KEY_LENGTH_DES_EDE3 = 192, +}; + +/** Maximum length of any IV, in Bytes. */ +#define MBEDTLS_MAX_IV_LENGTH 16 +/** Maximum block size of any cipher, in Bytes. */ +#define MBEDTLS_MAX_BLOCK_LENGTH 16 + +/** + * Base cipher information (opaque struct). + */ +typedef struct mbedtls_cipher_base_t mbedtls_cipher_base_t; + +/** + * CMAC context (opaque struct). + */ +typedef struct mbedtls_cmac_context_t mbedtls_cmac_context_t; + +/** + * Cipher information. Allows calling cipher functions + * in a generic way. + */ +typedef struct mbedtls_cipher_info_t +{ + /** Full cipher identifier. For example, + * MBEDTLS_CIPHER_AES_256_CBC. + */ + mbedtls_cipher_type_t type; + + /** The cipher mode. For example, MBEDTLS_MODE_CBC. */ + mbedtls_cipher_mode_t mode; + + /** The cipher key length, in bits. This is the + * default length for variable sized ciphers. + * Includes parity bits for ciphers like DES. + */ + unsigned int key_bitlen; + + /** Name of the cipher. */ + const char * name; + + /** IV or nonce size, in Bytes. + * For ciphers that accept variable IV sizes, + * this is the recommended size. + */ + unsigned int iv_size; + + /** Bitflag comprised of MBEDTLS_CIPHER_VARIABLE_IV_LEN and + * MBEDTLS_CIPHER_VARIABLE_KEY_LEN indicating whether the + * cipher supports variable IV or variable key sizes, respectively. + */ + int flags; + + /** The block size, in Bytes. */ + unsigned int block_size; + + /** Struct for base cipher information and functions. */ + const mbedtls_cipher_base_t *base; + +} mbedtls_cipher_info_t; + +/** + * Generic cipher context. + */ +typedef struct mbedtls_cipher_context_t +{ + /** Information about the associated cipher. */ + const mbedtls_cipher_info_t *cipher_info; + + /** Key length to use. */ + int key_bitlen; + + /** Operation that the key of the context has been + * initialized for. + */ + mbedtls_operation_t operation; + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) + /** Padding functions to use, if relevant for + * the specific cipher mode. + */ + void (*add_padding)( unsigned char *output, size_t olen, size_t data_len ); + int (*get_padding)( unsigned char *input, size_t ilen, size_t *data_len ); +#endif + + /** Buffer for input that has not been processed yet. */ + unsigned char unprocessed_data[MBEDTLS_MAX_BLOCK_LENGTH]; + + /** Number of Bytes that have not been processed yet. */ + size_t unprocessed_len; + + /** Current IV or NONCE_COUNTER for CTR-mode, data unit (or sector) number + * for XTS-mode. */ + unsigned char iv[MBEDTLS_MAX_IV_LENGTH]; + + /** IV size in Bytes, for ciphers with variable-length IVs. */ + size_t iv_size; + + /** The cipher-specific context. */ + void *cipher_ctx; + +#if defined(MBEDTLS_CMAC_C) + /** CMAC-specific context. */ + mbedtls_cmac_context_t *cmac_ctx; +#endif +} mbedtls_cipher_context_t; + +/** + * \brief This function retrieves the list of ciphers supported by the generic + * cipher module. + * + * \return A statically-allocated array of ciphers. The last entry + * is zero. + */ +const int *mbedtls_cipher_list( void ); + +/** + * \brief This function retrieves the cipher-information + * structure associated with the given cipher name. + * + * \param cipher_name Name of the cipher to search for. This must not be + * \c NULL. + * + * \return The cipher information structure associated with the + * given \p cipher_name. + * \return \c NULL if the associated cipher information is not found. + */ +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_string( const char *cipher_name ); + +/** + * \brief This function retrieves the cipher-information + * structure associated with the given cipher type. + * + * \param cipher_type Type of the cipher to search for. + * + * \return The cipher information structure associated with the + * given \p cipher_type. + * \return \c NULL if the associated cipher information is not found. + */ +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_type( const mbedtls_cipher_type_t cipher_type ); + +/** + * \brief This function retrieves the cipher-information + * structure associated with the given cipher ID, + * key size and mode. + * + * \param cipher_id The ID of the cipher to search for. For example, + * #MBEDTLS_CIPHER_ID_AES. + * \param key_bitlen The length of the key in bits. + * \param mode The cipher mode. For example, #MBEDTLS_MODE_CBC. + * + * \return The cipher information structure associated with the + * given \p cipher_id. + * \return \c NULL if the associated cipher information is not found. + */ +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values( const mbedtls_cipher_id_t cipher_id, + int key_bitlen, + const mbedtls_cipher_mode_t mode ); + +/** + * \brief This function initializes a \p cipher_context as NONE. + * + * \param ctx The context to be initialized. This must not be \c NULL. + */ +void mbedtls_cipher_init( mbedtls_cipher_context_t *ctx ); + +/** + * \brief This function frees and clears the cipher-specific + * context of \p ctx. Freeing \p ctx itself remains the + * responsibility of the caller. + * + * \param ctx The context to be freed. If this is \c NULL, the + * function has no effect, otherwise this must point to an + * initialized context. + */ +void mbedtls_cipher_free( mbedtls_cipher_context_t *ctx ); + + +/** + * \brief This function initializes and fills the cipher-context + * structure with the appropriate values. It also clears + * the structure. + * + * \param ctx The context to initialize. This must be initialized. + * \param cipher_info The cipher to use. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_ALLOC_FAILED if allocation of the + * cipher-specific context fails. + * + * \internal Currently, the function also clears the structure. + * In future versions, the caller will be required to call + * mbedtls_cipher_init() on the structure first. + */ +int mbedtls_cipher_setup( mbedtls_cipher_context_t *ctx, + const mbedtls_cipher_info_t *cipher_info ); + +/** + * \brief This function returns the block size of the given cipher. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The block size of the underlying cipher. + * \return \c 0 if \p ctx has not been initialized. + */ +static inline unsigned int mbedtls_cipher_get_block_size( + const mbedtls_cipher_context_t *ctx ) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( ctx != NULL, 0 ); + if( ctx->cipher_info == NULL ) + return 0; + + return ctx->cipher_info->block_size; +} + +/** + * \brief This function returns the mode of operation for + * the cipher. For example, MBEDTLS_MODE_CBC. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The mode of operation. + * \return #MBEDTLS_MODE_NONE if \p ctx has not been initialized. + */ +static inline mbedtls_cipher_mode_t mbedtls_cipher_get_cipher_mode( + const mbedtls_cipher_context_t *ctx ) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( ctx != NULL, MBEDTLS_MODE_NONE ); + if( ctx->cipher_info == NULL ) + return MBEDTLS_MODE_NONE; + + return ctx->cipher_info->mode; +} + +/** + * \brief This function returns the size of the IV or nonce + * of the cipher, in Bytes. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The recommended IV size if no IV has been set. + * \return \c 0 for ciphers not using an IV or a nonce. + * \return The actual size if an IV has been set. + */ +static inline int mbedtls_cipher_get_iv_size( + const mbedtls_cipher_context_t *ctx ) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( ctx != NULL, 0 ); + if( ctx->cipher_info == NULL ) + return 0; + + if( ctx->iv_size != 0 ) + return (int) ctx->iv_size; + + return (int) ctx->cipher_info->iv_size; +} + +/** + * \brief This function returns the type of the given cipher. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The type of the cipher. + * \return #MBEDTLS_CIPHER_NONE if \p ctx has not been initialized. + */ +static inline mbedtls_cipher_type_t mbedtls_cipher_get_type( + const mbedtls_cipher_context_t *ctx ) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( + ctx != NULL, MBEDTLS_CIPHER_NONE ); + if( ctx->cipher_info == NULL ) + return MBEDTLS_CIPHER_NONE; + + return ctx->cipher_info->type; +} + +/** + * \brief This function returns the name of the given cipher + * as a string. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The name of the cipher. + * \return NULL if \p ctx has not been not initialized. + */ +static inline const char *mbedtls_cipher_get_name( + const mbedtls_cipher_context_t *ctx ) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( ctx != NULL, 0 ); + if( ctx->cipher_info == NULL ) + return 0; + + return ctx->cipher_info->name; +} + +/** + * \brief This function returns the key length of the cipher. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The key length of the cipher in bits. + * \return #MBEDTLS_KEY_LENGTH_NONE if ctx \p has not been + * initialized. + */ +static inline int mbedtls_cipher_get_key_bitlen( + const mbedtls_cipher_context_t *ctx ) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( + ctx != NULL, MBEDTLS_KEY_LENGTH_NONE ); + if( ctx->cipher_info == NULL ) + return MBEDTLS_KEY_LENGTH_NONE; + + return (int) ctx->cipher_info->key_bitlen; +} + +/** + * \brief This function returns the operation of the given cipher. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The type of operation: #MBEDTLS_ENCRYPT or #MBEDTLS_DECRYPT. + * \return #MBEDTLS_OPERATION_NONE if \p ctx has not been initialized. + */ +static inline mbedtls_operation_t mbedtls_cipher_get_operation( + const mbedtls_cipher_context_t *ctx ) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( + ctx != NULL, MBEDTLS_OPERATION_NONE ); + if( ctx->cipher_info == NULL ) + return MBEDTLS_OPERATION_NONE; + + return ctx->operation; +} + +/** + * \brief This function sets the key to use with the given context. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a cipher information structure. + * \param key The key to use. This must be a readable buffer of at + * least \p key_bitlen Bits. + * \param key_bitlen The key length to use, in Bits. + * \param operation The operation that the key will be used for: + * #MBEDTLS_ENCRYPT or #MBEDTLS_DECRYPT. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_setkey( mbedtls_cipher_context_t *ctx, + const unsigned char *key, + int key_bitlen, + const mbedtls_operation_t operation ); + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) +/** + * \brief This function sets the padding mode, for cipher modes + * that use padding. + * + * The default passing mode is PKCS7 padding. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a cipher information structure. + * \param mode The padding mode. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE + * if the selected padding mode is not supported. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA if the cipher mode + * does not support padding. + */ +int mbedtls_cipher_set_padding_mode( mbedtls_cipher_context_t *ctx, + mbedtls_cipher_padding_t mode ); +#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ + +/** + * \brief This function sets the initialization vector (IV) + * or nonce. + * + * \note Some ciphers do not use IVs nor nonce. For these + * ciphers, this function has no effect. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a cipher information structure. + * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. This + * must be a readable buffer of at least \p iv_len Bytes. + * \param iv_len The IV length for ciphers with variable-size IV. + * This parameter is discarded by ciphers with fixed-size IV. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + */ +int mbedtls_cipher_set_iv( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, + size_t iv_len ); + +/** + * \brief This function resets the cipher state. + * + * \param ctx The generic cipher context. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + */ +int mbedtls_cipher_reset( mbedtls_cipher_context_t *ctx ); + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +/** + * \brief This function adds additional data for AEAD ciphers. + * Currently supported with GCM and ChaCha20+Poly1305. + * This must be called exactly once, after + * mbedtls_cipher_reset(). + * + * \param ctx The generic cipher context. This must be initialized. + * \param ad The additional data to use. This must be a readable + * buffer of at least \p ad_len Bytes. + * \param ad_len the Length of \p ad Bytes. + * + * \return \c 0 on success. + * \return A specific error code on failure. + */ +int mbedtls_cipher_update_ad( mbedtls_cipher_context_t *ctx, + const unsigned char *ad, size_t ad_len ); +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +/** + * \brief The generic cipher update function. It encrypts or + * decrypts using the given cipher context. Writes as + * many block-sized blocks of data as possible to output. + * Any data that cannot be written immediately is either + * added to the next block, or flushed when + * mbedtls_cipher_finish() is called. + * Exception: For MBEDTLS_MODE_ECB, expects a single block + * in size. For example, 16 Bytes for AES. + * + * \note If the underlying cipher is used in GCM mode, all calls + * to this function, except for the last one before + * mbedtls_cipher_finish(), must have \p ilen as a + * multiple of the block size of the cipher. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes. + * \param ilen The length of the input data. + * \param output The buffer for the output data. This must be able to + * hold at least `ilen + block_size`. This must not be the + * same buffer as \p input. + * \param olen The length of the output data, to be updated with the + * actual number of Bytes written. This must not be + * \c NULL. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE on an + * unsupported mode for a cipher. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_update( mbedtls_cipher_context_t *ctx, const unsigned char *input, + size_t ilen, unsigned char *output, size_t *olen ); + +/** + * \brief The generic cipher finalization function. If data still + * needs to be flushed from an incomplete block, the data + * contained in it is padded to the size of + * the last block, and written to the \p output buffer. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key. + * \param output The buffer to write data to. This needs to be a writable + * buffer of at least \p block_size Bytes. + * \param olen The length of the data written to the \p output buffer. + * This may not be \c NULL. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED on decryption + * expecting a full block but not receiving one. + * \return #MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding + * while decrypting. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx, + unsigned char *output, size_t *olen ); + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +/** + * \brief This function writes a tag for AEAD ciphers. + * Currently supported with GCM and ChaCha20+Poly1305. + * This must be called after mbedtls_cipher_finish(). + * + * \param ctx The generic cipher context. This must be initialized, + * bound to a key, and have just completed a cipher + * operation through mbedtls_cipher_finish() the tag for + * which should be written. + * \param tag The buffer to write the tag to. This must be a writable + * buffer of at least \p tag_len Bytes. + * \param tag_len The length of the tag to write. + * + * \return \c 0 on success. + * \return A specific error code on failure. + */ +int mbedtls_cipher_write_tag( mbedtls_cipher_context_t *ctx, + unsigned char *tag, size_t tag_len ); + +/** + * \brief This function checks the tag for AEAD ciphers. + * Currently supported with GCM and ChaCha20+Poly1305. + * This must be called after mbedtls_cipher_finish(). + * + * \param ctx The generic cipher context. This must be initialized. + * \param tag The buffer holding the tag. This must be a readable + * buffer of at least \p tag_len Bytes. + * \param tag_len The length of the tag to check. + * + * \return \c 0 on success. + * \return A specific error code on failure. + */ +int mbedtls_cipher_check_tag( mbedtls_cipher_context_t *ctx, + const unsigned char *tag, size_t tag_len ); +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +/** + * \brief The generic all-in-one encryption/decryption function, + * for all ciphers except AEAD constructs. + * + * \param ctx The generic cipher context. This must be initialized. + * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. + * This must be a readable buffer of at least \p iv_len + * Bytes. + * \param iv_len The IV length for ciphers with variable-size IV. + * This parameter is discarded by ciphers with fixed-size + * IV. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The buffer for the output data. This must be able to + * hold at least `ilen + block_size`. This must not be the + * same buffer as \p input. + * \param olen The length of the output data, to be updated with the + * actual number of Bytes written. This must not be + * \c NULL. + * + * \note Some ciphers do not use IVs nor nonce. For these + * ciphers, use \p iv = NULL and \p iv_len = 0. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED on decryption + * expecting a full block but not receiving one. + * \return #MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding + * while decrypting. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_crypt( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen ); + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) +/** + * \brief The generic autenticated encryption (AEAD) function. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key. + * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. + * This must be a readable buffer of at least \p iv_len + * Bytes. + * \param iv_len The IV length for ciphers with variable-size IV. + * This parameter is discarded by ciphers with fixed-size IV. + * \param ad The additional data to authenticate. This must be a + * readable buffer of at least \p ad_len Bytes. + * \param ad_len The length of \p ad. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes. + * \param ilen The length of the input data. + * \param output The buffer for the output data. This must be able to + * hold at least \p ilen Bytes. + * \param olen The length of the output data, to be updated with the + * actual number of Bytes written. This must not be + * \c NULL. + * \param tag The buffer for the authentication tag. This must be a + * writable buffer of at least \p tag_len Bytes. + * \param tag_len The desired length of the authentication tag. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, + unsigned char *tag, size_t tag_len ); + +/** + * \brief The generic autenticated decryption (AEAD) function. + * + * \note If the data is not authentic, then the output buffer + * is zeroed out to prevent the unauthentic plaintext being + * used, making this interface safer. + * + * \param ctx The generic cipher context. This must be initialized and + * and bound to a key. + * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. + * This must be a readable buffer of at least \p iv_len + * Bytes. + * \param iv_len The IV length for ciphers with variable-size IV. + * This parameter is discarded by ciphers with fixed-size IV. + * \param ad The additional data to be authenticated. This must be a + * readable buffer of at least \p ad_len Bytes. + * \param ad_len The length of \p ad. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes. + * \param ilen The length of the input data. + * \param output The buffer for the output data. + * This must be able to hold at least \p ilen Bytes. + * \param olen The length of the output data, to be updated with the + * actual number of Bytes written. This must not be + * \c NULL. + * \param tag The buffer holding the authentication tag. This must be + * a readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication tag. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_AUTH_FAILED if data is not authentic. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, + const unsigned char *tag, size_t tag_len ); +#endif /* MBEDTLS_CIPHER_MODE_AEAD */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CIPHER_H */ diff --git a/src/common/mbedtls/include/mbedtls/cipher_internal.h b/src/common/mbedtls/include/mbedtls/cipher_internal.h new file mode 100644 index 0000000000..66fa09254f --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/cipher_internal.h @@ -0,0 +1,135 @@ +/** + * \file cipher_internal.h + * + * \brief Cipher wrappers. + * + * \author Adriaan de Jong + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_CIPHER_WRAP_H +#define MBEDTLS_CIPHER_WRAP_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "cipher.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Base cipher information. The non-mode specific functions and values. + */ +struct mbedtls_cipher_base_t +{ + /** Base Cipher type (e.g. MBEDTLS_CIPHER_ID_AES) */ + mbedtls_cipher_id_t cipher; + + /** Encrypt using ECB */ + int (*ecb_func)( void *ctx, mbedtls_operation_t mode, + const unsigned char *input, unsigned char *output ); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + /** Encrypt using CBC */ + int (*cbc_func)( void *ctx, mbedtls_operation_t mode, size_t length, + unsigned char *iv, const unsigned char *input, + unsigned char *output ); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CFB) + /** Encrypt using CFB (Full length) */ + int (*cfb_func)( void *ctx, mbedtls_operation_t mode, size_t length, size_t *iv_off, + unsigned char *iv, const unsigned char *input, + unsigned char *output ); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_OFB) + /** Encrypt using OFB (Full length) */ + int (*ofb_func)( void *ctx, size_t length, size_t *iv_off, + unsigned char *iv, + const unsigned char *input, + unsigned char *output ); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CTR) + /** Encrypt using CTR */ + int (*ctr_func)( void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output ); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_XTS) + /** Encrypt or decrypt using XTS. */ + int (*xts_func)( void *ctx, mbedtls_operation_t mode, size_t length, + const unsigned char data_unit[16], + const unsigned char *input, unsigned char *output ); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + /** Encrypt using STREAM */ + int (*stream_func)( void *ctx, size_t length, + const unsigned char *input, unsigned char *output ); +#endif + + /** Set key for encryption purposes */ + int (*setkey_enc_func)( void *ctx, const unsigned char *key, + unsigned int key_bitlen ); + + /** Set key for decryption purposes */ + int (*setkey_dec_func)( void *ctx, const unsigned char *key, + unsigned int key_bitlen); + + /** Allocate a new context */ + void * (*ctx_alloc_func)( void ); + + /** Free the given context */ + void (*ctx_free_func)( void *ctx ); + +}; + +typedef struct +{ + mbedtls_cipher_type_t type; + const mbedtls_cipher_info_t *info; +} mbedtls_cipher_definition_t; + +extern const mbedtls_cipher_definition_t mbedtls_cipher_definitions[]; + +extern int mbedtls_cipher_supported[]; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CIPHER_WRAP_H */ diff --git a/src/common/mbedtls/include/mbedtls/config.h b/src/common/mbedtls/include/mbedtls/config.h new file mode 100644 index 0000000000..868557565f --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/config.h @@ -0,0 +1,3425 @@ +/** + * \file config.h + * + * \brief Configuration options (set of defines) + * + * This set of compile-time options may be used to enable + * or disable features selectively, and reduce the global + * memory footprint. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +/** + * \name SECTION: System support + * + * This section sets system specific settings. + * \{ + */ + +/** + * \def MBEDTLS_HAVE_ASM + * + * The compiler has support for asm(). + * + * Requires support for asm() in compiler. + * + * Used in: + * library/aria.c + * library/timing.c + * include/mbedtls/bn_mul.h + * + * Required by: + * MBEDTLS_AESNI_C + * MBEDTLS_PADLOCK_C + * + * Comment to disable the use of assembly code. + */ +#define MBEDTLS_HAVE_ASM + +/** + * \def MBEDTLS_NO_UDBL_DIVISION + * + * The platform lacks support for double-width integer division (64-bit + * division on a 32-bit platform, 128-bit division on a 64-bit platform). + * + * Used in: + * include/mbedtls/bignum.h + * library/bignum.c + * + * The bignum code uses double-width division to speed up some operations. + * Double-width division is often implemented in software that needs to + * be linked with the program. The presence of a double-width integer + * type is usually detected automatically through preprocessor macros, + * but the automatic detection cannot know whether the code needs to + * and can be linked with an implementation of division for that type. + * By default division is assumed to be usable if the type is present. + * Uncomment this option to prevent the use of double-width division. + * + * Note that division for the native integer type is always required. + * Furthermore, a 64-bit type is always required even on a 32-bit + * platform, but it need not support multiplication or division. In some + * cases it is also desirable to disable some double-width operations. For + * example, if double-width division is implemented in software, disabling + * it can reduce code size in some embedded targets. + */ +//#define MBEDTLS_NO_UDBL_DIVISION + +/** + * \def MBEDTLS_NO_64BIT_MULTIPLICATION + * + * The platform lacks support for 32x32 -> 64-bit multiplication. + * + * Used in: + * library/poly1305.c + * + * Some parts of the library may use multiplication of two unsigned 32-bit + * operands with a 64-bit result in order to speed up computations. On some + * platforms, this is not available in hardware and has to be implemented in + * software, usually in a library provided by the toolchain. + * + * Sometimes it is not desirable to have to link to that library. This option + * removes the dependency of that library on platforms that lack a hardware + * 64-bit multiplier by embedding a software implementation in Mbed TLS. + * + * Note that depending on the compiler, this may decrease performance compared + * to using the library function provided by the toolchain. + */ +//#define MBEDTLS_NO_64BIT_MULTIPLICATION + +/** + * \def MBEDTLS_HAVE_SSE2 + * + * CPU supports SSE2 instruction set. + * + * Uncomment if the CPU supports SSE2 (IA-32 specific). + */ +//#define MBEDTLS_HAVE_SSE2 + +/** + * \def MBEDTLS_HAVE_TIME + * + * System has time.h and time(). + * The time does not need to be correct, only time differences are used, + * by contrast with MBEDTLS_HAVE_TIME_DATE + * + * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT, + * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and + * MBEDTLS_PLATFORM_STD_TIME. + * + * Comment if your system does not support time functions + */ +#define MBEDTLS_HAVE_TIME + +/** + * \def MBEDTLS_HAVE_TIME_DATE + * + * System has time.h, time(), and an implementation for + * mbedtls_platform_gmtime_r() (see below). + * The time needs to be correct (not necessarily very accurate, but at least + * the date should be correct). This is used to verify the validity period of + * X.509 certificates. + * + * Comment if your system does not have a correct clock. + * + * \note mbedtls_platform_gmtime_r() is an abstraction in platform_util.h that + * behaves similarly to the gmtime_r() function from the C standard. Refer to + * the documentation for mbedtls_platform_gmtime_r() for more information. + * + * \note It is possible to configure an implementation for + * mbedtls_platform_gmtime_r() at compile-time by using the macro + * MBEDTLS_PLATFORM_GMTIME_R_ALT. + */ +#define MBEDTLS_HAVE_TIME_DATE + +/** + * \def MBEDTLS_PLATFORM_MEMORY + * + * Enable the memory allocation layer. + * + * By default mbed TLS uses the system-provided calloc() and free(). + * This allows different allocators (self-implemented or provided) to be + * provided to the platform abstraction layer. + * + * Enabling MBEDTLS_PLATFORM_MEMORY without the + * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide + * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and + * free() function pointer at runtime. + * + * Enabling MBEDTLS_PLATFORM_MEMORY and specifying + * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the + * alternate function at compile time. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Enable this layer to allow use of alternative memory allocators. + */ +//#define MBEDTLS_PLATFORM_MEMORY + +/** + * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + * + * Do not assign standard functions in the platform layer (e.g. calloc() to + * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF) + * + * This makes sure there are no linking errors on platforms that do not support + * these functions. You will HAVE to provide alternatives, either at runtime + * via the platform_set_xxx() functions or at compile time by setting + * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a + * MBEDTLS_PLATFORM_XXX_MACRO. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Uncomment to prevent default assignment of standard functions in the + * platform layer. + */ +//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + +/** + * \def MBEDTLS_PLATFORM_EXIT_ALT + * + * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the + * function in the platform abstraction layer. + * + * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will + * provide a function "mbedtls_platform_set_printf()" that allows you to set an + * alternative printf function pointer. + * + * All these define require MBEDTLS_PLATFORM_C to be defined! + * + * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows; + * it will be enabled automatically by check_config.h + * + * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as + * MBEDTLS_PLATFORM_XXX_MACRO! + * + * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME + * + * Uncomment a macro to enable alternate implementation of specific base + * platform function + */ +//#define MBEDTLS_PLATFORM_EXIT_ALT +//#define MBEDTLS_PLATFORM_TIME_ALT +//#define MBEDTLS_PLATFORM_FPRINTF_ALT +//#define MBEDTLS_PLATFORM_PRINTF_ALT +//#define MBEDTLS_PLATFORM_SNPRINTF_ALT +//#define MBEDTLS_PLATFORM_NV_SEED_ALT +//#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT + +/** + * \def MBEDTLS_DEPRECATED_WARNING + * + * Mark deprecated functions so that they generate a warning if used. + * Functions deprecated in one version will usually be removed in the next + * version. You can enable this to help you prepare the transition to a new + * major version by making sure your code is not using these functions. + * + * This only works with GCC and Clang. With other compilers, you may want to + * use MBEDTLS_DEPRECATED_REMOVED + * + * Uncomment to get warnings on using deprecated functions. + */ +//#define MBEDTLS_DEPRECATED_WARNING + +/** + * \def MBEDTLS_DEPRECATED_REMOVED + * + * Remove deprecated functions so that they generate an error if used. + * Functions deprecated in one version will usually be removed in the next + * version. You can enable this to help you prepare the transition to a new + * major version by making sure your code is not using these functions. + * + * Uncomment to get errors on using deprecated functions. + */ +//#define MBEDTLS_DEPRECATED_REMOVED + +/** + * \def MBEDTLS_CHECK_PARAMS + * + * This configuration option controls whether the library validates more of + * the parameters passed to it. + * + * When this flag is not defined, the library only attempts to validate an + * input parameter if: (1) they may come from the outside world (such as the + * network, the filesystem, etc.) or (2) not validating them could result in + * internal memory errors such as overflowing a buffer controlled by the + * library. On the other hand, it doesn't attempt to validate parameters whose + * values are fully controlled by the application (such as pointers). + * + * When this flag is defined, the library additionally attempts to validate + * parameters that are fully controlled by the application, and should always + * be valid if the application code is fully correct and trusted. + * + * For example, when a function accepts as input a pointer to a buffer that may + * contain untrusted data, and its documentation mentions that this pointer + * must not be NULL: + * - The pointer is checked to be non-NULL only if this option is enabled. + * - The content of the buffer is always validated. + * + * When this flag is defined, if a library function receives a parameter that + * is invalid: + * 1. The function will invoke the macro MBEDTLS_PARAM_FAILED(). + * 2. If MBEDTLS_PARAM_FAILED() did not terminate the program, the function + * will immediately return. If the function returns an Mbed TLS error code, + * the error code in this case is MBEDTLS_ERR_xxx_BAD_INPUT_DATA. + * + * When defining this flag, you also need to arrange a definition for + * MBEDTLS_PARAM_FAILED(). You can do this by any of the following methods: + * - By default, the library defines MBEDTLS_PARAM_FAILED() to call a + * function mbedtls_param_failed(), but the library does not define this + * function. If you do not make any other arrangements, you must provide + * the function mbedtls_param_failed() in your application. + * See `platform_util.h` for its prototype. + * - If you enable the macro #MBEDTLS_CHECK_PARAMS_ASSERT, then the + * library defines #MBEDTLS_PARAM_FAILED(\c cond) to be `assert(cond)`. + * You can still supply an alternative definition of + * MBEDTLS_PARAM_FAILED(), which may call `assert`. + * - If you define a macro MBEDTLS_PARAM_FAILED() before including `config.h` + * or you uncomment the definition of MBEDTLS_PARAM_FAILED() in `config.h`, + * the library will call the macro that you defined and will not supply + * its own version. Note that if MBEDTLS_PARAM_FAILED() calls `assert`, + * you need to enable #MBEDTLS_CHECK_PARAMS_ASSERT so that library source + * files include ``. + * + * Uncomment to enable validation of application-controlled parameters. + */ +//#define MBEDTLS_CHECK_PARAMS + +/** + * \def MBEDTLS_CHECK_PARAMS_ASSERT + * + * Allow MBEDTLS_PARAM_FAILED() to call `assert`, and make it default to + * `assert`. This macro is only used if #MBEDTLS_CHECK_PARAMS is defined. + * + * If this macro is not defined, then MBEDTLS_PARAM_FAILED() defaults to + * calling a function mbedtls_param_failed(). See the documentation of + * #MBEDTLS_CHECK_PARAMS for details. + * + * Uncomment to allow MBEDTLS_PARAM_FAILED() to call `assert`. + */ +//#define MBEDTLS_CHECK_PARAMS_ASSERT + +/* \} name SECTION: System support */ + +/** + * \name SECTION: mbed TLS feature support + * + * This section sets support for features that are or are not needed + * within the modules that are enabled. + * \{ + */ + +/** + * \def MBEDTLS_TIMING_ALT + * + * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(), + * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay() + * + * Only works if you have MBEDTLS_TIMING_C enabled. + * + * You will need to provide a header "timing_alt.h" and an implementation at + * compile time. + */ +//#define MBEDTLS_TIMING_ALT + +/** + * \def MBEDTLS_AES_ALT + * + * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your + * alternate core implementation of a symmetric crypto, an arithmetic or hash + * module (e.g. platform specific assembly optimized implementations). Keep + * in mind that the function prototypes should remain the same. + * + * This replaces the whole module. If you only want to replace one of the + * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags. + * + * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer + * provide the "struct mbedtls_aes_context" definition and omit the base + * function declarations and implementations. "aes_alt.h" will be included from + * "aes.h" to include the new function definitions. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * module. + * + * \warning MD2, MD4, MD5, ARC4, DES and SHA-1 are considered weak and their + * use constitutes a security risk. If possible, we recommend + * avoiding dependencies on them, and considering stronger message + * digests and ciphers instead. + * + */ +//#define MBEDTLS_AES_ALT +//#define MBEDTLS_ARC4_ALT +//#define MBEDTLS_ARIA_ALT +//#define MBEDTLS_BLOWFISH_ALT +//#define MBEDTLS_CAMELLIA_ALT +//#define MBEDTLS_CCM_ALT +//#define MBEDTLS_CHACHA20_ALT +//#define MBEDTLS_CHACHAPOLY_ALT +//#define MBEDTLS_CMAC_ALT +//#define MBEDTLS_DES_ALT +//#define MBEDTLS_DHM_ALT +//#define MBEDTLS_ECJPAKE_ALT +//#define MBEDTLS_GCM_ALT +//#define MBEDTLS_NIST_KW_ALT +//#define MBEDTLS_MD2_ALT +//#define MBEDTLS_MD4_ALT +//#define MBEDTLS_MD5_ALT +//#define MBEDTLS_POLY1305_ALT +//#define MBEDTLS_RIPEMD160_ALT +//#define MBEDTLS_RSA_ALT +//#define MBEDTLS_SHA1_ALT +//#define MBEDTLS_SHA256_ALT +//#define MBEDTLS_SHA512_ALT +//#define MBEDTLS_XTEA_ALT + +/* + * When replacing the elliptic curve module, pleace consider, that it is + * implemented with two .c files: + * - ecp.c + * - ecp_curves.c + * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT + * macros as described above. The only difference is that you have to make sure + * that you provide functionality for both .c files. + */ +//#define MBEDTLS_ECP_ALT + +/** + * \def MBEDTLS_MD2_PROCESS_ALT + * + * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you + * alternate core implementation of symmetric crypto or hash function. Keep in + * mind that function prototypes should remain the same. + * + * This replaces only one function. The header file from mbed TLS is still + * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags. + * + * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will + * no longer provide the mbedtls_sha1_process() function, but it will still provide + * the other function (using your mbedtls_sha1_process() function) and the definition + * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible + * with this definition. + * + * \note Because of a signature change, the core AES encryption and decryption routines are + * currently named mbedtls_aes_internal_encrypt and mbedtls_aes_internal_decrypt, + * respectively. When setting up alternative implementations, these functions should + * be overridden, but the wrapper functions mbedtls_aes_decrypt and mbedtls_aes_encrypt + * must stay untouched. + * + * \note If you use the AES_xxx_ALT macros, then it is recommended to also set + * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES + * tables. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * function. + * + * \warning MD2, MD4, MD5, DES and SHA-1 are considered weak and their use + * constitutes a security risk. If possible, we recommend avoiding + * dependencies on them, and considering stronger message digests + * and ciphers instead. + * + * \warning If both MBEDTLS_ECDSA_SIGN_ALT and MBEDTLS_ECDSA_DETERMINISTIC are + * enabled, then the deterministic ECDH signature functions pass the + * the static HMAC-DRBG as RNG to mbedtls_ecdsa_sign(). Therefore + * alternative implementations should use the RNG only for generating + * the ephemeral key and nothing else. If this is not possible, then + * MBEDTLS_ECDSA_DETERMINISTIC should be disabled and an alternative + * implementation should be provided for mbedtls_ecdsa_sign_det_ext() + * (and for mbedtls_ecdsa_sign_det() too if backward compatibility is + * desirable). + * + */ +//#define MBEDTLS_MD2_PROCESS_ALT +//#define MBEDTLS_MD4_PROCESS_ALT +//#define MBEDTLS_MD5_PROCESS_ALT +//#define MBEDTLS_RIPEMD160_PROCESS_ALT +//#define MBEDTLS_SHA1_PROCESS_ALT +//#define MBEDTLS_SHA256_PROCESS_ALT +//#define MBEDTLS_SHA512_PROCESS_ALT +//#define MBEDTLS_DES_SETKEY_ALT +//#define MBEDTLS_DES_CRYPT_ECB_ALT +//#define MBEDTLS_DES3_CRYPT_ECB_ALT +//#define MBEDTLS_AES_SETKEY_ENC_ALT +//#define MBEDTLS_AES_SETKEY_DEC_ALT +//#define MBEDTLS_AES_ENCRYPT_ALT +//#define MBEDTLS_AES_DECRYPT_ALT +//#define MBEDTLS_ECDH_GEN_PUBLIC_ALT +//#define MBEDTLS_ECDH_COMPUTE_SHARED_ALT +//#define MBEDTLS_ECDSA_VERIFY_ALT +//#define MBEDTLS_ECDSA_SIGN_ALT +//#define MBEDTLS_ECDSA_GENKEY_ALT + +/** + * \def MBEDTLS_ECP_INTERNAL_ALT + * + * Expose a part of the internal interface of the Elliptic Curve Point module. + * + * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use your + * alternative core implementation of elliptic curve arithmetic. Keep in mind + * that function prototypes should remain the same. + * + * This partially replaces one function. The header file from mbed TLS is still + * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation + * is still present and it is used for group structures not supported by the + * alternative. + * + * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT + * and implementing the following functions: + * unsigned char mbedtls_internal_ecp_grp_capable( + * const mbedtls_ecp_group *grp ) + * int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ) + * void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ) + * The mbedtls_internal_ecp_grp_capable function should return 1 if the + * replacement functions implement arithmetic for the given group and 0 + * otherwise. + * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_free are + * called before and after each point operation and provide an opportunity to + * implement optimized set up and tear down instructions. + * + * Example: In case you uncomment MBEDTLS_ECP_INTERNAL_ALT and + * MBEDTLS_ECP_DOUBLE_JAC_ALT, mbed TLS will still provide the ecp_double_jac + * function, but will use your mbedtls_internal_ecp_double_jac if the group is + * supported (your mbedtls_internal_ecp_grp_capable function returns 1 when + * receives it as an argument). If the group is not supported then the original + * implementation is used. The other functions and the definition of + * mbedtls_ecp_group and mbedtls_ecp_point will not change, so your + * implementation of mbedtls_internal_ecp_double_jac and + * mbedtls_internal_ecp_grp_capable must be compatible with this definition. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * function. + */ +/* Required for all the functions in this section */ +//#define MBEDTLS_ECP_INTERNAL_ALT +/* Support for Weierstrass curves with Jacobi representation */ +//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT +//#define MBEDTLS_ECP_ADD_MIXED_ALT +//#define MBEDTLS_ECP_DOUBLE_JAC_ALT +//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT +//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT +/* Support for curves with Montgomery arithmetic */ +//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT +//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT +//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + * + * Enable testing of the constant-flow nature of some sensitive functions with + * clang's MemorySanitizer. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires compiling with clang -fsanitize=memory. The test + * suites can then be run normally. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +//#define MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + * + * Enable testing of the constant-flow nature of some sensitive functions with + * valgrind's memcheck tool. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires valgrind headers for building, and is only useful for + * testing if the tests suites are run with valgrind's memcheck. This can be + * done for an individual test suite with 'valgrind ./test_suite_xxx', or when + * using CMake, this can be done for all test suites with 'make memcheck'. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +//#define MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + +/** + * \def MBEDTLS_TEST_NULL_ENTROPY + * + * Enables testing and use of mbed TLS without any configured entropy sources. + * This permits use of the library on platforms before an entropy source has + * been integrated (see for example the MBEDTLS_ENTROPY_HARDWARE_ALT or the + * MBEDTLS_ENTROPY_NV_SEED switches). + * + * WARNING! This switch MUST be disabled in production builds, and is suitable + * only for development. + * Enabling the switch negates any security provided by the library. + * + * Requires MBEDTLS_ENTROPY_C, MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + * + */ +//#define MBEDTLS_TEST_NULL_ENTROPY + +/** + * \def MBEDTLS_ENTROPY_HARDWARE_ALT + * + * Uncomment this macro to let mbed TLS use your own implementation of a + * hardware entropy collector. + * + * Your function must be called \c mbedtls_hardware_poll(), have the same + * prototype as declared in entropy_poll.h, and accept NULL as first argument. + * + * Uncomment to use your own hardware entropy collector. + */ +//#define MBEDTLS_ENTROPY_HARDWARE_ALT + +/** + * \def MBEDTLS_AES_ROM_TABLES + * + * Use precomputed AES tables stored in ROM. + * + * Uncomment this macro to use precomputed AES tables stored in ROM. + * Comment this macro to generate AES tables in RAM at runtime. + * + * Tradeoff: Using precomputed ROM tables reduces RAM usage by ~8kb + * (or ~2kb if \c MBEDTLS_AES_FEWER_TABLES is used) and reduces the + * initialization time before the first AES operation can be performed. + * It comes at the cost of additional ~8kb ROM use (resp. ~2kb if \c + * MBEDTLS_AES_FEWER_TABLES below is used), and potentially degraded + * performance if ROM access is slower than RAM access. + * + * This option is independent of \c MBEDTLS_AES_FEWER_TABLES. + * + */ +//#define MBEDTLS_AES_ROM_TABLES + +/** + * \def MBEDTLS_AES_FEWER_TABLES + * + * Use less ROM/RAM for AES tables. + * + * Uncommenting this macro omits 75% of the AES tables from + * ROM / RAM (depending on the value of \c MBEDTLS_AES_ROM_TABLES) + * by computing their values on the fly during operations + * (the tables are entry-wise rotations of one another). + * + * Tradeoff: Uncommenting this reduces the RAM / ROM footprint + * by ~6kb but at the cost of more arithmetic operations during + * runtime. Specifically, one has to compare 4 accesses within + * different tables to 4 accesses with additional arithmetic + * operations within the same table. The performance gain/loss + * depends on the system and memory details. + * + * This option is independent of \c MBEDTLS_AES_ROM_TABLES. + * + */ +//#define MBEDTLS_AES_FEWER_TABLES + +/** + * \def MBEDTLS_CAMELLIA_SMALL_MEMORY + * + * Use less ROM for the Camellia implementation (saves about 768 bytes). + * + * Uncomment this macro to use less memory for Camellia. + */ +//#define MBEDTLS_CAMELLIA_SMALL_MEMORY + +/** + * \def MBEDTLS_CIPHER_MODE_CBC + * + * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CBC + +/** + * \def MBEDTLS_CIPHER_MODE_CFB + * + * Enable Cipher Feedback mode (CFB) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CFB + +/** + * \def MBEDTLS_CIPHER_MODE_CTR + * + * Enable Counter Block Cipher mode (CTR) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CTR + +/** + * \def MBEDTLS_CIPHER_MODE_OFB + * + * Enable Output Feedback mode (OFB) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_OFB + +/** + * \def MBEDTLS_CIPHER_MODE_XTS + * + * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES. + */ +#define MBEDTLS_CIPHER_MODE_XTS + +/** + * \def MBEDTLS_CIPHER_NULL_CIPHER + * + * Enable NULL cipher. + * Warning: Only do so when you know what you are doing. This allows for + * encryption or channels without any security! + * + * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable + * the following ciphersuites: + * MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_RSA_WITH_NULL_SHA256 + * MBEDTLS_TLS_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_RSA_WITH_NULL_MD5 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_PSK_WITH_NULL_SHA + * + * Uncomment this macro to enable the NULL cipher and ciphersuites + */ +//#define MBEDTLS_CIPHER_NULL_CIPHER + +/** + * \def MBEDTLS_CIPHER_PADDING_PKCS7 + * + * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for + * specific padding modes in the cipher layer with cipher modes that support + * padding (e.g. CBC) + * + * If you disable all padding modes, only full blocks can be used with CBC. + * + * Enable padding modes in the cipher layer. + */ +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS +#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN +#define MBEDTLS_CIPHER_PADDING_ZEROS + +/** \def MBEDTLS_CTR_DRBG_USE_128_BIT_KEY + * + * Uncomment this macro to use a 128-bit key in the CTR_DRBG module. + * By default, CTR_DRBG uses a 256-bit key. + */ +//#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY + +/** + * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES + * + * Enable weak ciphersuites in SSL / TLS. + * Warning: Only do so when you know what you are doing. This allows for + * channels with virtually no security at all! + * + * This enables the following ciphersuites: + * MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA + * + * Uncomment this macro to enable weak ciphersuites + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers instead. + */ +//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES + +/** + * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES + * + * Remove RC4 ciphersuites by default in SSL / TLS. + * This flag removes the ciphersuites based on RC4 from the default list as + * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to + * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them + * explicitly. + * + * Uncomment this macro to remove RC4 ciphersuites by default. + */ +#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES + +/** + * \def MBEDTLS_REMOVE_3DES_CIPHERSUITES + * + * Remove 3DES ciphersuites by default in SSL / TLS. + * This flag removes the ciphersuites based on 3DES from the default list as + * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible + * to enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including + * them explicitly. + * + * A man-in-the-browser attacker can recover authentication tokens sent through + * a TLS connection using a 3DES based cipher suite (see "On the Practical + * (In-)Security of 64-bit Block Ciphers" by Karthikeyan Bhargavan and Gaëtan + * Leurent, see sweet32.info/SWEET32_CCS16.pdf). If this attack falls + * in your threat model or you are unsure, then you should keep this option + * enabled to remove 3DES based cipher suites. + * + * Comment this macro to keep 3DES in the default ciphersuite list. + */ +#define MBEDTLS_REMOVE_3DES_CIPHERSUITES + +/** + * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED + * + * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve + * module. By default all supported curves are enabled. + * + * Comment macros to disable the curve and functions for it + */ +#define MBEDTLS_ECP_DP_SECP192R1_ENABLED +#define MBEDTLS_ECP_DP_SECP224R1_ENABLED +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#define MBEDTLS_ECP_DP_SECP521R1_ENABLED +#define MBEDTLS_ECP_DP_SECP192K1_ENABLED +#define MBEDTLS_ECP_DP_SECP224K1_ENABLED +#define MBEDTLS_ECP_DP_SECP256K1_ENABLED +#define MBEDTLS_ECP_DP_BP256R1_ENABLED +#define MBEDTLS_ECP_DP_BP384R1_ENABLED +#define MBEDTLS_ECP_DP_BP512R1_ENABLED +#define MBEDTLS_ECP_DP_CURVE25519_ENABLED +#define MBEDTLS_ECP_DP_CURVE448_ENABLED + +/** + * \def MBEDTLS_ECP_NIST_OPTIM + * + * Enable specific 'modulo p' routines for each NIST prime. + * Depending on the prime and architecture, makes operations 4 to 8 times + * faster on the corresponding curve. + * + * Comment this macro to disable NIST curves optimisation. + */ +#define MBEDTLS_ECP_NIST_OPTIM + +/** + * \def MBEDTLS_ECP_NO_INTERNAL_RNG + * + * When this option is disabled, mbedtls_ecp_mul() will make use of an + * internal RNG when called with a NULL \c f_rng argument, in order to protect + * against some side-channel attacks. + * + * This protection introduces a dependency of the ECP module on one of the + * DRBG or SHA modules (HMAC-DRBG, CTR-DRBG, SHA-512 or SHA-256.) For very + * constrained applications that don't require this protection (for example, + * because you're only doing signature verification, so not manipulating any + * secret, or because local/physical side-channel attacks are outside your + * threat model), it might be desirable to get rid of that dependency. + * + * \warning Enabling this option makes some uses of ECP vulnerable to some + * side-channel attacks. Only enable it if you know that's not a problem for + * your use case. + * + * Uncomment this macro to disable some counter-measures in ECP. + */ +//#define MBEDTLS_ECP_NO_INTERNAL_RNG + +/** + * \def MBEDTLS_ECP_RESTARTABLE + * + * Enable "non-blocking" ECC operations that can return early and be resumed. + * + * This allows various functions to pause by returning + * #MBEDTLS_ERR_ECP_IN_PROGRESS (or, for functions in the SSL module, + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS) and then be called later again in + * order to further progress and eventually complete their operation. This is + * controlled through mbedtls_ecp_set_max_ops() which limits the maximum + * number of ECC operations a function may perform before pausing; see + * mbedtls_ecp_set_max_ops() for more information. + * + * This is useful in non-threaded environments if you want to avoid blocking + * for too long on ECC (and, hence, X.509 or SSL/TLS) operations. + * + * Uncomment this macro to enable restartable ECC computations. + * + * \note This option only works with the default software implementation of + * elliptic curve functionality. It is incompatible with + * MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT and MBEDTLS_ECDSA_XXX_ALT. + */ +//#define MBEDTLS_ECP_RESTARTABLE + +/** + * \def MBEDTLS_ECDSA_DETERMINISTIC + * + * Enable deterministic ECDSA (RFC 6979). + * Standard ECDSA is "fragile" in the sense that lack of entropy when signing + * may result in a compromise of the long-term signing key. This is avoided by + * the deterministic variant. + * + * Requires: MBEDTLS_HMAC_DRBG_C + * + * Comment this macro to disable deterministic ECDSA. + */ +#define MBEDTLS_ECDSA_DETERMINISTIC + +/** + * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + * + * Enable the PSK based ciphersuite modes in SSL / TLS. + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + * + * Enable the DHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_DHM_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + * + * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + * + * Enable the RSA-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + * + * Enable the RSA-only based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5 + */ +#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + * + * Enable the DHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + * + * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + * + * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C, + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + * + * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + * + * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + * + * Enable the ECJPAKE based ciphersuite modes in SSL / TLS. + * + * \warning This is currently experimental. EC J-PAKE support is based on the + * Thread v1.0.0 specification; incompatible changes to the specification + * might still happen. For this reason, this is disabled by default. + * + * Requires: MBEDTLS_ECJPAKE_C + * MBEDTLS_SHA256_C + * MBEDTLS_ECP_DP_SECP256R1_ENABLED + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + */ +//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + +/** + * \def MBEDTLS_PK_PARSE_EC_EXTENDED + * + * Enhance support for reading EC keys using variants of SEC1 not allowed by + * RFC 5915 and RFC 5480. + * + * Currently this means parsing the SpecifiedECDomain choice of EC + * parameters (only known groups are supported, not arbitrary domains, to + * avoid validation issues). + * + * Disable if you only need to support RFC 5915 + 5480 key formats. + */ +#define MBEDTLS_PK_PARSE_EC_EXTENDED + +/** + * \def MBEDTLS_ERROR_STRERROR_DUMMY + * + * Enable a dummy error function to make use of mbedtls_strerror() in + * third party libraries easier when MBEDTLS_ERROR_C is disabled + * (no effect when MBEDTLS_ERROR_C is enabled). + * + * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're + * not using mbedtls_strerror() or error_strerror() in your application. + * + * Disable if you run into name conflicts and want to really remove the + * mbedtls_strerror() + */ +#define MBEDTLS_ERROR_STRERROR_DUMMY + +/** + * \def MBEDTLS_GENPRIME + * + * Enable the prime-number generation code. + * + * Requires: MBEDTLS_BIGNUM_C + */ +#define MBEDTLS_GENPRIME + +/** + * \def MBEDTLS_FS_IO + * + * Enable functions that use the filesystem. + */ +#define MBEDTLS_FS_IO + +/** + * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + * + * Do not add default entropy sources. These are the platform specific, + * mbedtls_timing_hardclock and HAVEGE based poll functions. + * + * This is useful to have more control over the added entropy sources in an + * application. + * + * Uncomment this macro to prevent loading of default entropy functions. + */ +//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + +/** + * \def MBEDTLS_NO_PLATFORM_ENTROPY + * + * Do not use built-in platform entropy functions. + * This is useful if your platform does not support + * standards like the /dev/urandom or Windows CryptoAPI. + * + * Uncomment this macro to disable the built-in platform entropy functions. + */ +//#define MBEDTLS_NO_PLATFORM_ENTROPY + +/** + * \def MBEDTLS_ENTROPY_FORCE_SHA256 + * + * Force the entropy accumulator to use a SHA-256 accumulator instead of the + * default SHA-512 based one (if both are available). + * + * Requires: MBEDTLS_SHA256_C + * + * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option + * if you have performance concerns. + * + * This option is only useful if both MBEDTLS_SHA256_C and + * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used. + */ +//#define MBEDTLS_ENTROPY_FORCE_SHA256 + +/** + * \def MBEDTLS_ENTROPY_NV_SEED + * + * Enable the non-volatile (NV) seed file-based entropy source. + * (Also enables the NV seed read/write functions in the platform layer) + * + * This is crucial (if not required) on systems that do not have a + * cryptographic entropy source (in hardware or kernel) available. + * + * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C + * + * \note The read/write functions that are used by the entropy source are + * determined in the platform layer, and can be modified at runtime and/or + * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used. + * + * \note If you use the default implementation functions that read a seedfile + * with regular fopen(), please make sure you make a seedfile with the + * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at + * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from + * and written to or you will get an entropy source error! The default + * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE + * bytes from the file. + * + * \note The entropy collector will write to the seed file before entropy is + * given to an external source, to update it. + */ +//#define MBEDTLS_ENTROPY_NV_SEED + +/** + * \def MBEDTLS_MEMORY_DEBUG + * + * Enable debugging of buffer allocator memory issues. Automatically prints + * (to stderr) all (fatal) messages on memory allocation issues. Enables + * function for 'debug output' of allocated memory. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Uncomment this macro to let the buffer allocator print out error messages. + */ +//#define MBEDTLS_MEMORY_DEBUG + +/** + * \def MBEDTLS_MEMORY_BACKTRACE + * + * Include backtrace information with each allocated block. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * GLIBC-compatible backtrace() an backtrace_symbols() support + * + * Uncomment this macro to include backtrace information + */ +//#define MBEDTLS_MEMORY_BACKTRACE + +/** + * \def MBEDTLS_PK_RSA_ALT_SUPPORT + * + * Support external private RSA keys (eg from a HSM) in the PK layer. + * + * Comment this macro to disable support for external private RSA keys. + */ +#define MBEDTLS_PK_RSA_ALT_SUPPORT + +/** + * \def MBEDTLS_PKCS1_V15 + * + * Enable support for PKCS#1 v1.5 encoding. + * + * Requires: MBEDTLS_RSA_C + * + * This enables support for PKCS#1 v1.5 operations. + */ +#define MBEDTLS_PKCS1_V15 + +/** + * \def MBEDTLS_PKCS1_V21 + * + * Enable support for PKCS#1 v2.1 encoding. + * + * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C + * + * This enables support for RSAES-OAEP and RSASSA-PSS operations. + */ +#define MBEDTLS_PKCS1_V21 + +/** + * \def MBEDTLS_RSA_NO_CRT + * + * Do not use the Chinese Remainder Theorem + * for the RSA private operation. + * + * Uncomment this macro to disable the use of CRT in RSA. + * + */ +//#define MBEDTLS_RSA_NO_CRT + +/** + * \def MBEDTLS_SELF_TEST + * + * Enable the checkup functions (*_self_test). + */ +#define MBEDTLS_SELF_TEST + +/** + * \def MBEDTLS_SHA256_SMALLER + * + * Enable an implementation of SHA-256 that has lower ROM footprint but also + * lower performance. + * + * The default implementation is meant to be a reasonnable compromise between + * performance and size. This version optimizes more aggressively for size at + * the expense of performance. Eg on Cortex-M4 it reduces the size of + * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about + * 30%. + * + * Uncomment to enable the smaller implementation of SHA256. + */ +//#define MBEDTLS_SHA256_SMALLER + +/** + * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES + * + * Enable sending of alert messages in case of encountered errors as per RFC. + * If you choose not to send the alert messages, mbed TLS can still communicate + * with other servers, only debugging of failures is harder. + * + * The advantage of not sending alert messages, is that no information is given + * about reasons for failures thus preventing adversaries of gaining intel. + * + * Enable sending of all alert messages + */ +#define MBEDTLS_SSL_ALL_ALERT_MESSAGES + +/** + * \def MBEDTLS_SSL_ASYNC_PRIVATE + * + * Enable asynchronous external private key operations in SSL. This allows + * you to configure an SSL connection to call an external cryptographic + * module to perform private key operations instead of performing the + * operation inside the library. + * + */ +//#define MBEDTLS_SSL_ASYNC_PRIVATE + +/** + * \def MBEDTLS_SSL_DEBUG_ALL + * + * Enable the debug messages in SSL module for all issues. + * Debug messages have been disabled in some places to prevent timing + * attacks due to (unbalanced) debugging function calls. + * + * If you need all error reporting you should enable this during debugging, + * but remove this for production servers that should log as well. + * + * Uncomment this macro to report all debug messages on errors introducing + * a timing side-channel. + * + */ +//#define MBEDTLS_SSL_DEBUG_ALL + +/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC + * + * Enable support for Encrypt-then-MAC, RFC 7366. + * + * This allows peers that both support it to use a more robust protection for + * ciphersuites using CBC, providing deep resistance against timing attacks + * on the padding or underlying cipher. + * + * This only affects CBC ciphersuites, and is useless if none is defined. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1 or + * MBEDTLS_SSL_PROTO_TLS1_1 or + * MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Encrypt-then-MAC + */ +#define MBEDTLS_SSL_ENCRYPT_THEN_MAC + +/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET + * + * Enable support for Extended Master Secret, aka Session Hash + * (draft-ietf-tls-session-hash-02). + * + * This was introduced as "the proper fix" to the Triple Handshake familiy of + * attacks, but it is recommended to always use it (even if you disable + * renegotiation), since it actually fixes a more fundamental issue in the + * original SSL/TLS design, and has implications beyond Triple Handshake. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1 or + * MBEDTLS_SSL_PROTO_TLS1_1 or + * MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Extended Master Secret. + */ +#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET + +/** + * \def MBEDTLS_SSL_FALLBACK_SCSV + * + * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00). + * + * For servers, it is recommended to always enable this, unless you support + * only one version of TLS, or know for sure that none of your clients + * implements a fallback strategy. + * + * For clients, you only need this if you're using a fallback strategy, which + * is not recommended in the first place, unless you absolutely need it to + * interoperate with buggy (version-intolerant) servers. + * + * Comment this macro to disable support for FALLBACK_SCSV + */ +#define MBEDTLS_SSL_FALLBACK_SCSV + +/** + * \def MBEDTLS_SSL_HW_RECORD_ACCEL + * + * Enable hooking functions in SSL module for hardware acceleration of + * individual records. + * + * Uncomment this macro to enable hooking functions. + */ +//#define MBEDTLS_SSL_HW_RECORD_ACCEL + +/** + * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING + * + * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0. + * + * This is a countermeasure to the BEAST attack, which also minimizes the risk + * of interoperability issues compared to sending 0-length records. + * + * Comment this macro to disable 1/n-1 record splitting. + */ +#define MBEDTLS_SSL_CBC_RECORD_SPLITTING + +/** + * \def MBEDTLS_SSL_RENEGOTIATION + * + * Enable support for TLS renegotiation. + * + * The two main uses of renegotiation are (1) refresh keys on long-lived + * connections and (2) client authentication after the initial handshake. + * If you don't need renegotiation, it's probably better to disable it, since + * it has been associated with security issues in the past and is easy to + * misuse/misunderstand. + * + * Comment this to disable support for renegotiation. + * + * \note Even if this option is disabled, both client and server are aware + * of the Renegotiation Indication Extension (RFC 5746) used to + * prevent the SSL renegotiation attack (see RFC 5746 Sect. 1). + * (See \c mbedtls_ssl_conf_legacy_renegotiation for the + * configuration of this extension). + * + */ +#define MBEDTLS_SSL_RENEGOTIATION + +/** + * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO + * + * Enable support for receiving and parsing SSLv2 Client Hello messages for the + * SSL Server module (MBEDTLS_SSL_SRV_C). + * + * Uncomment this macro to enable support for SSLv2 Client Hello messages. + */ +//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO + +/** + * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE + * + * Pick the ciphersuite according to the client's preferences rather than ours + * in the SSL Server module (MBEDTLS_SSL_SRV_C). + * + * Uncomment this macro to respect client's ciphersuite order + */ +//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE + +/** + * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + * + * Enable support for RFC 6066 max_fragment_length extension in SSL. + * + * Comment this macro to disable support for the max_fragment_length extension + */ +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/** + * \def MBEDTLS_SSL_PROTO_SSL3 + * + * Enable support for SSL 3.0. + * + * Requires: MBEDTLS_MD5_C + * MBEDTLS_SHA1_C + * + * Comment this macro to disable support for SSL 3.0 + */ +//#define MBEDTLS_SSL_PROTO_SSL3 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1 + * + * Enable support for TLS 1.0. + * + * Requires: MBEDTLS_MD5_C + * MBEDTLS_SHA1_C + * + * Comment this macro to disable support for TLS 1.0 + */ +#define MBEDTLS_SSL_PROTO_TLS1 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_1 + * + * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled). + * + * Requires: MBEDTLS_MD5_C + * MBEDTLS_SHA1_C + * + * Comment this macro to disable support for TLS 1.1 / DTLS 1.0 + */ +#define MBEDTLS_SSL_PROTO_TLS1_1 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_2 + * + * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled). + * + * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C + * (Depends on ciphersuites) + * + * Comment this macro to disable support for TLS 1.2 / DTLS 1.2 + */ +#define MBEDTLS_SSL_PROTO_TLS1_2 + +/** + * \def MBEDTLS_SSL_PROTO_DTLS + * + * Enable support for DTLS (all available versions). + * + * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0, + * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_1 + * or MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for DTLS + */ +#define MBEDTLS_SSL_PROTO_DTLS + +/** + * \def MBEDTLS_SSL_ALPN + * + * Enable support for RFC 7301 Application Layer Protocol Negotiation. + * + * Comment this macro to disable support for ALPN. + */ +#define MBEDTLS_SSL_ALPN + +/** + * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY + * + * Enable support for the anti-replay mechanism in DTLS. + * + * Requires: MBEDTLS_SSL_TLS_C + * MBEDTLS_SSL_PROTO_DTLS + * + * \warning Disabling this is often a security risk! + * See mbedtls_ssl_conf_dtls_anti_replay() for details. + * + * Comment this to disable anti-replay in DTLS. + */ +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY + +/** + * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Enable support for HelloVerifyRequest on DTLS servers. + * + * This feature is highly recommended to prevent DTLS servers being used as + * amplifiers in DoS attacks against other hosts. It should always be enabled + * unless you know for sure amplification cannot be a problem in the + * environment in which your server operates. + * + * \warning Disabling this can ba a security risk! (see above) + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Comment this to disable support for HelloVerifyRequest. + */ +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY + +/** + * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + * + * Enable server-side support for clients that reconnect from the same port. + * + * Some clients unexpectedly close the connection and try to reconnect using the + * same source port. This needs special support from the server to handle the + * new connection securely, as described in section 4.2.8 of RFC 6347. This + * flag enables that support. + * + * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Comment this to disable support for clients reusing the source port. + */ +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + +/** + * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT + * + * Enable support for a limit of records with bad MAC. + * + * See mbedtls_ssl_conf_dtls_badmac_limit(). + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + */ +#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT + +/** + * \def MBEDTLS_SSL_SESSION_TICKETS + * + * Enable support for RFC 5077 session tickets in SSL. + * Client-side, provides full support for session tickets (maintenance of a + * session store remains the responsibility of the application, though). + * Server-side, you also need to provide callbacks for writing and parsing + * tickets, including authenticated encryption and key management. Example + * callbacks are provided by MBEDTLS_SSL_TICKET_C. + * + * Comment this macro to disable support for SSL session tickets + */ +#define MBEDTLS_SSL_SESSION_TICKETS + +/** + * \def MBEDTLS_SSL_EXPORT_KEYS + * + * Enable support for exporting key block and master secret. + * This is required for certain users of TLS, e.g. EAP-TLS. + * + * Comment this macro to disable support for key export + */ +#define MBEDTLS_SSL_EXPORT_KEYS + +/** + * \def MBEDTLS_SSL_SERVER_NAME_INDICATION + * + * Enable support for RFC 6066 server name indication (SNI) in SSL. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + * + * Comment this macro to disable support for server name indication in SSL + */ +#define MBEDTLS_SSL_SERVER_NAME_INDICATION + +/** + * \def MBEDTLS_SSL_TRUNCATED_HMAC + * + * Enable support for RFC 6066 truncated HMAC in SSL. + * + * Comment this macro to disable support for truncated HMAC in SSL + */ +#define MBEDTLS_SSL_TRUNCATED_HMAC + +/** + * \def MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT + * + * Fallback to old (pre-2.7), non-conforming implementation of the truncated + * HMAC extension which also truncates the HMAC key. Note that this option is + * only meant for a transitory upgrade period and is likely to be removed in + * a future version of the library. + * + * \warning The old implementation is non-compliant and has a security weakness + * (2^80 brute force attack on the HMAC key used for a single, + * uninterrupted connection). This should only be enabled temporarily + * when (1) the use of truncated HMAC is essential in order to save + * bandwidth, and (2) the peer is an Mbed TLS stack that doesn't use + * the fixed implementation yet (pre-2.7). + * + * \deprecated This option is deprecated and will likely be removed in a + * future version of Mbed TLS. + * + * Uncomment to fallback to old, non-compliant truncated HMAC implementation. + * + * Requires: MBEDTLS_SSL_TRUNCATED_HMAC + */ +//#define MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT + +/** + * \def MBEDTLS_TEST_HOOKS + * + * Enable features for invasive testing such as introspection functions and + * hooks for fault injection. This enables additional unit tests. + * + * Merely enabling this feature should not change the behavior of the product. + * It only adds new code, and new branching points where the default behavior + * is the same as when this feature is disabled. + * However, this feature increases the attack surface: there is an added + * risk of vulnerabilities, and more gadgets that can make exploits easier. + * Therefore this feature must never be enabled in production. + * + * Uncomment to enable invasive tests. + */ +//#define MBEDTLS_TEST_HOOKS + +/** + * \def MBEDTLS_THREADING_ALT + * + * Provide your own alternate threading implementation. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to allow your own alternate threading implementation. + */ +//#define MBEDTLS_THREADING_ALT + +/** + * \def MBEDTLS_THREADING_PTHREAD + * + * Enable the pthread wrapper layer for the threading layer. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to enable pthread mutexes. + */ +//#define MBEDTLS_THREADING_PTHREAD + +/** + * \def MBEDTLS_VERSION_FEATURES + * + * Allow run-time checking of compile-time enabled features. Thus allowing users + * to check at run-time if the library is for instance compiled with threading + * support via mbedtls_version_check_feature(). + * + * Requires: MBEDTLS_VERSION_C + * + * Comment this to disable run-time checking and save ROM space + */ +#define MBEDTLS_VERSION_FEATURES + +/** + * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3 + * + * If set, the X509 parser will not break-off when parsing an X509 certificate + * and encountering an extension in a v1 or v2 certificate. + * + * Uncomment to prevent an error. + */ +//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3 + +/** + * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION + * + * If set, the X509 parser will not break-off when parsing an X509 certificate + * and encountering an unknown critical extension. + * + * \warning Depending on your PKI use, enabling this can be a security risk! + * + * Uncomment to prevent an error. + */ +//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION + +/** + * \def MBEDTLS_X509_CHECK_KEY_USAGE + * + * Enable verification of the keyUsage extension (CA and leaf certificates). + * + * Disabling this avoids problems with mis-issued and/or misused + * (intermediate) CA and leaf certificates. + * + * \warning Depending on your PKI use, disabling this can be a security risk! + * + * Comment to skip keyUsage checking for both CA and leaf certificates. + */ +#define MBEDTLS_X509_CHECK_KEY_USAGE + +/** + * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE + * + * Enable verification of the extendedKeyUsage extension (leaf certificates). + * + * Disabling this avoids problems with mis-issued and/or misused certificates. + * + * \warning Depending on your PKI use, disabling this can be a security risk! + * + * Comment to skip extendedKeyUsage checking for certificates. + */ +#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE + +/** + * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT + * + * Enable parsing and verification of X.509 certificates, CRLs and CSRS + * signed with RSASSA-PSS (aka PKCS#1 v2.1). + * + * Comment this macro to disallow using RSASSA-PSS in certificates. + */ +#define MBEDTLS_X509_RSASSA_PSS_SUPPORT + +/** + * \def MBEDTLS_ZLIB_SUPPORT + * + * If set, the SSL/TLS module uses ZLIB to support compression and + * decompression of packet data. + * + * \warning TLS-level compression MAY REDUCE SECURITY! See for example the + * CRIME attack. Before enabling this option, you should examine with care if + * CRIME or similar exploits may be applicable to your use case. + * + * \note Currently compression can't be used with DTLS. + * + * \deprecated This feature is deprecated and will be removed + * in the next major revision of the library. + * + * Used in: library/ssl_tls.c + * library/ssl_cli.c + * library/ssl_srv.c + * + * This feature requires zlib library and headers to be present. + * + * Uncomment to enable use of ZLIB + */ +//#define MBEDTLS_ZLIB_SUPPORT +/* \} name SECTION: mbed TLS feature support */ + +/** + * \name SECTION: mbed TLS modules + * + * This section enables or disables entire modules in mbed TLS + * \{ + */ + +/** + * \def MBEDTLS_AESNI_C + * + * Enable AES-NI support on x86-64. + * + * Module: library/aesni.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_HAVE_ASM + * + * This modules adds support for the AES-NI instructions on x86-64 + */ +#define MBEDTLS_AESNI_C + +/** + * \def MBEDTLS_AES_C + * + * Enable the AES block cipher. + * + * Module: library/aes.c + * Caller: library/cipher.c + * library/pem.c + * library/ctr_drbg.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * + * PEM_PARSE uses AES for decrypting encrypted keys. + */ +#define MBEDTLS_AES_C + +/** + * \def MBEDTLS_ARC4_C + * + * Enable the ARCFOUR stream cipher. + * + * Module: library/arc4.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA + * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5 + * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA + * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA + * + * \warning ARC4 is considered a weak cipher and its use constitutes a + * security risk. If possible, we recommend avoidng dependencies on + * it, and considering stronger ciphers instead. + * + */ +#define MBEDTLS_ARC4_C + +/** + * \def MBEDTLS_ASN1_PARSE_C + * + * Enable the generic ASN1 parser. + * + * Module: library/asn1.c + * Caller: library/x509.c + * library/dhm.c + * library/pkcs12.c + * library/pkcs5.c + * library/pkparse.c + */ +#define MBEDTLS_ASN1_PARSE_C + +/** + * \def MBEDTLS_ASN1_WRITE_C + * + * Enable the generic ASN1 writer. + * + * Module: library/asn1write.c + * Caller: library/ecdsa.c + * library/pkwrite.c + * library/x509_create.c + * library/x509write_crt.c + * library/x509write_csr.c + */ +#define MBEDTLS_ASN1_WRITE_C + +/** + * \def MBEDTLS_BASE64_C + * + * Enable the Base64 module. + * + * Module: library/base64.c + * Caller: library/pem.c + * + * This module is required for PEM support (required by X.509). + */ +#define MBEDTLS_BASE64_C + +/** + * \def MBEDTLS_BIGNUM_C + * + * Enable the multi-precision integer library. + * + * Module: library/bignum.c + * Caller: library/dhm.c + * library/ecp.c + * library/ecdsa.c + * library/rsa.c + * library/rsa_internal.c + * library/ssl_tls.c + * + * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support. + */ +#define MBEDTLS_BIGNUM_C + +/** + * \def MBEDTLS_BLOWFISH_C + * + * Enable the Blowfish block cipher. + * + * Module: library/blowfish.c + */ +#define MBEDTLS_BLOWFISH_C + +/** + * \def MBEDTLS_CAMELLIA_C + * + * Enable the Camellia block cipher. + * + * Module: library/camellia.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_CAMELLIA_C + +/** + * \def MBEDTLS_ARIA_C + * + * Enable the ARIA block cipher. + * + * Module: library/aria.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * + * MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384 + */ +//#define MBEDTLS_ARIA_C + +/** + * \def MBEDTLS_CCM_C + * + * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher. + * + * Module: library/ccm.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C + * + * This module enables the AES-CCM ciphersuites, if other requisites are + * enabled as well. + */ +#define MBEDTLS_CCM_C + +/** + * \def MBEDTLS_CERTS_C + * + * Enable the test certificates. + * + * Module: library/certs.c + * Caller: + * + * This module is used for testing (ssl_client/server). + */ +#define MBEDTLS_CERTS_C + +/** + * \def MBEDTLS_CHACHA20_C + * + * Enable the ChaCha20 stream cipher. + * + * Module: library/chacha20.c + */ +#define MBEDTLS_CHACHA20_C + +/** + * \def MBEDTLS_CHACHAPOLY_C + * + * Enable the ChaCha20-Poly1305 AEAD algorithm. + * + * Module: library/chachapoly.c + * + * This module requires: MBEDTLS_CHACHA20_C, MBEDTLS_POLY1305_C + */ +#define MBEDTLS_CHACHAPOLY_C + +/** + * \def MBEDTLS_CIPHER_C + * + * Enable the generic cipher layer. + * + * Module: library/cipher.c + * Caller: library/ssl_tls.c + * + * Uncomment to enable generic cipher wrappers. + */ +#define MBEDTLS_CIPHER_C + +/** + * \def MBEDTLS_CMAC_C + * + * Enable the CMAC (Cipher-based Message Authentication Code) mode for block + * ciphers. + * + * Module: library/cmac.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_DES_C + * + */ +//#define MBEDTLS_CMAC_C + +/** + * \def MBEDTLS_CTR_DRBG_C + * + * Enable the CTR_DRBG AES-based random generator. + * The CTR_DRBG generator uses AES-256 by default. + * To use AES-128 instead, enable \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY above. + * + * \note To achieve a 256-bit security strength with CTR_DRBG, + * you must use AES-256 *and* use sufficient entropy. + * See ctr_drbg.h for more details. + * + * Module: library/ctr_drbg.c + * Caller: + * + * Requires: MBEDTLS_AES_C + * + * This module provides the CTR_DRBG AES random number generator. + */ +#define MBEDTLS_CTR_DRBG_C + +/** + * \def MBEDTLS_DEBUG_C + * + * Enable the debug functions. + * + * Module: library/debug.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * This module provides debugging functions. + */ +#define MBEDTLS_DEBUG_C + +/** + * \def MBEDTLS_DES_C + * + * Enable the DES block cipher. + * + * Module: library/des.c + * Caller: library/pem.c + * library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA + * + * PEM_PARSE uses DES/3DES for decrypting encrypted keys. + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers instead. + */ +#define MBEDTLS_DES_C + +/** + * \def MBEDTLS_DHM_C + * + * Enable the Diffie-Hellman-Merkle module. + * + * Module: library/dhm.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * This module is used by the following key exchanges: + * DHE-RSA, DHE-PSK + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_DHM_C + +/** + * \def MBEDTLS_ECDH_C + * + * Enable the elliptic curve Diffie-Hellman library. + * + * Module: library/ecdh.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * This module is used by the following key exchanges: + * ECDHE-ECDSA, ECDHE-RSA, DHE-PSK + * + * Requires: MBEDTLS_ECP_C + */ +#define MBEDTLS_ECDH_C + +/** + * \def MBEDTLS_ECDSA_C + * + * Enable the elliptic curve DSA library. + * + * Module: library/ecdsa.c + * Caller: + * + * This module is used by the following key exchanges: + * ECDHE-ECDSA + * + * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C + */ +#define MBEDTLS_ECDSA_C + +/** + * \def MBEDTLS_ECJPAKE_C + * + * Enable the elliptic curve J-PAKE library. + * + * \warning This is currently experimental. EC J-PAKE support is based on the + * Thread v1.0.0 specification; incompatible changes to the specification + * might still happen. For this reason, this is disabled by default. + * + * Module: library/ecjpake.c + * Caller: + * + * This module is used by the following key exchanges: + * ECJPAKE + * + * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C + */ +//#define MBEDTLS_ECJPAKE_C + +/** + * \def MBEDTLS_ECP_C + * + * Enable the elliptic curve over GF(p) library. + * + * Module: library/ecp.c + * Caller: library/ecdh.c + * library/ecdsa.c + * library/ecjpake.c + * + * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED + */ +#define MBEDTLS_ECP_C + +/** + * \def MBEDTLS_ENTROPY_C + * + * Enable the platform-specific entropy code. + * + * Module: library/entropy.c + * Caller: + * + * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C + * + * This module provides a generic entropy pool + */ +#define MBEDTLS_ENTROPY_C + +/** + * \def MBEDTLS_ERROR_C + * + * Enable error code to error string conversion. + * + * Module: library/error.c + * Caller: + * + * This module enables mbedtls_strerror(). + */ +#define MBEDTLS_ERROR_C + +/** + * \def MBEDTLS_GCM_C + * + * Enable the Galois/Counter Mode (GCM) for AES. + * + * Module: library/gcm.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C + * + * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other + * requisites are enabled as well. + */ +#define MBEDTLS_GCM_C + +/** + * \def MBEDTLS_HAVEGE_C + * + * Enable the HAVEGE random generator. + * + * Warning: the HAVEGE random generator is not suitable for virtualized + * environments + * + * Warning: the HAVEGE random generator is dependent on timing and specific + * processor traits. It is therefore not advised to use HAVEGE as + * your applications primary random generator or primary entropy pool + * input. As a secondary input to your entropy pool, it IS able add + * the (limited) extra entropy it provides. + * + * Module: library/havege.c + * Caller: + * + * Requires: MBEDTLS_TIMING_C + * + * Uncomment to enable the HAVEGE random generator. + */ +//#define MBEDTLS_HAVEGE_C + +/** + * \def MBEDTLS_HKDF_C + * + * Enable the HKDF algorithm (RFC 5869). + * + * Module: library/hkdf.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * This module adds support for the Hashed Message Authentication Code + * (HMAC)-based key derivation function (HKDF). + */ +#define MBEDTLS_HKDF_C + +/** + * \def MBEDTLS_HMAC_DRBG_C + * + * Enable the HMAC_DRBG random generator. + * + * Module: library/hmac_drbg.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * Uncomment to enable the HMAC_DRBG random number geerator. + */ +#define MBEDTLS_HMAC_DRBG_C + +/** + * \def MBEDTLS_NIST_KW_C + * + * Enable the Key Wrapping mode for 128-bit block ciphers, + * as defined in NIST SP 800-38F. Only KW and KWP modes + * are supported. At the moment, only AES is approved by NIST. + * + * Module: library/nist_kw.c + * + * Requires: MBEDTLS_AES_C and MBEDTLS_CIPHER_C + */ +//#define MBEDTLS_NIST_KW_C + +/** + * \def MBEDTLS_MD_C + * + * Enable the generic message digest layer. + * + * Module: library/md.c + * Caller: + * + * Uncomment to enable generic message digest wrappers. + */ +#define MBEDTLS_MD_C + +/** + * \def MBEDTLS_MD2_C + * + * Enable the MD2 hash algorithm. + * + * Module: library/md2.c + * Caller: + * + * Uncomment to enable support for (rare) MD2-signed X.509 certs. + * + * \warning MD2 is considered a weak message digest and its use constitutes a + * security risk. If possible, we recommend avoiding dependencies on + * it, and considering stronger message digests instead. + * + */ +//#define MBEDTLS_MD2_C + +/** + * \def MBEDTLS_MD4_C + * + * Enable the MD4 hash algorithm. + * + * Module: library/md4.c + * Caller: + * + * Uncomment to enable support for (rare) MD4-signed X.509 certs. + * + * \warning MD4 is considered a weak message digest and its use constitutes a + * security risk. If possible, we recommend avoiding dependencies on + * it, and considering stronger message digests instead. + * + */ +//#define MBEDTLS_MD4_C + +/** + * \def MBEDTLS_MD5_C + * + * Enable the MD5 hash algorithm. + * + * Module: library/md5.c + * Caller: library/md.c + * library/pem.c + * library/ssl_tls.c + * + * This module is required for SSL/TLS up to version 1.1, and for TLS 1.2 + * depending on the handshake parameters. Further, it is used for checking + * MD5-signed certificates, and for PBKDF1 when decrypting PEM-encoded + * encrypted keys. + * + * \warning MD5 is considered a weak message digest and its use constitutes a + * security risk. If possible, we recommend avoiding dependencies on + * it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_MD5_C + +/** + * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Enable the buffer allocator implementation that makes use of a (stack) + * based buffer to 'allocate' dynamic memory. (replaces calloc() and free() + * calls) + * + * Module: library/memory_buffer_alloc.c + * + * Requires: MBEDTLS_PLATFORM_C + * MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS) + * + * Enable this module to enable the buffer memory allocator. + */ +//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C + +/** + * \def MBEDTLS_NET_C + * + * Enable the TCP and UDP over IPv6/IPv4 networking routines. + * + * \note This module only works on POSIX/Unix (including Linux, BSD and OS X) + * and Windows. For other platforms, you'll want to disable it, and write your + * own networking callbacks to be passed to \c mbedtls_ssl_set_bio(). + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/net_sockets.c + * + * This module provides networking routines. + */ +#define MBEDTLS_NET_C + +/** + * \def MBEDTLS_OID_C + * + * Enable the OID database. + * + * Module: library/oid.c + * Caller: library/asn1write.c + * library/pkcs5.c + * library/pkparse.c + * library/pkwrite.c + * library/rsa.c + * library/x509.c + * library/x509_create.c + * library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * This modules translates between OIDs and internal values. + */ +#define MBEDTLS_OID_C + +/** + * \def MBEDTLS_PADLOCK_C + * + * Enable VIA Padlock support on x86. + * + * Module: library/padlock.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_HAVE_ASM + * + * This modules adds support for the VIA PadLock on x86. + */ +#define MBEDTLS_PADLOCK_C + +/** + * \def MBEDTLS_PEM_PARSE_C + * + * Enable PEM decoding / parsing. + * + * Module: library/pem.c + * Caller: library/dhm.c + * library/pkparse.c + * library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_BASE64_C + * + * This modules adds support for decoding / parsing PEM files. + */ +#define MBEDTLS_PEM_PARSE_C + +/** + * \def MBEDTLS_PEM_WRITE_C + * + * Enable PEM encoding / writing. + * + * Module: library/pem.c + * Caller: library/pkwrite.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * Requires: MBEDTLS_BASE64_C + * + * This modules adds support for encoding / writing PEM files. + */ +#define MBEDTLS_PEM_WRITE_C + +/** + * \def MBEDTLS_PK_C + * + * Enable the generic public (asymetric) key layer. + * + * Module: library/pk.c + * Caller: library/ssl_tls.c + * library/ssl_cli.c + * library/ssl_srv.c + * + * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C + * + * Uncomment to enable generic public key wrappers. + */ +#define MBEDTLS_PK_C + +/** + * \def MBEDTLS_PK_PARSE_C + * + * Enable the generic public (asymetric) key parser. + * + * Module: library/pkparse.c + * Caller: library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_PK_C + * + * Uncomment to enable generic public key parse functions. + */ +#define MBEDTLS_PK_PARSE_C + +/** + * \def MBEDTLS_PK_WRITE_C + * + * Enable the generic public (asymetric) key writer. + * + * Module: library/pkwrite.c + * Caller: library/x509write.c + * + * Requires: MBEDTLS_PK_C + * + * Uncomment to enable generic public key write functions. + */ +#define MBEDTLS_PK_WRITE_C + +/** + * \def MBEDTLS_PKCS5_C + * + * Enable PKCS#5 functions. + * + * Module: library/pkcs5.c + * + * Requires: MBEDTLS_MD_C + * + * This module adds support for the PKCS#5 functions. + */ +#define MBEDTLS_PKCS5_C + +/** + * \def MBEDTLS_PKCS11_C + * + * Enable wrapper for PKCS#11 smartcard support. + * + * Module: library/pkcs11.c + * Caller: library/pk.c + * + * Requires: MBEDTLS_PK_C + * + * This module enables SSL/TLS PKCS #11 smartcard support. + * Requires the presence of the PKCS#11 helper library (libpkcs11-helper) + */ +//#define MBEDTLS_PKCS11_C + +/** + * \def MBEDTLS_PKCS12_C + * + * Enable PKCS#12 PBE functions. + * Adds algorithms for parsing PKCS#8 encrypted private keys + * + * Module: library/pkcs12.c + * Caller: library/pkparse.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * Can use: MBEDTLS_ARC4_C + * + * This module enables PKCS#12 functions. + */ +#define MBEDTLS_PKCS12_C + +/** + * \def MBEDTLS_PLATFORM_C + * + * Enable the platform abstraction layer that allows you to re-assign + * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit(). + * + * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT + * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned + * above to be specified at runtime or compile time respectively. + * + * \note This abstraction layer must be enabled on Windows (including MSYS2) + * as other module rely on it for a fixed snprintf implementation. + * + * Module: library/platform.c + * Caller: Most other .c files + * + * This module enables abstraction of common (libc) functions. + */ +#define MBEDTLS_PLATFORM_C + +/** + * \def MBEDTLS_POLY1305_C + * + * Enable the Poly1305 MAC algorithm. + * + * Module: library/poly1305.c + * Caller: library/chachapoly.c + */ +#define MBEDTLS_POLY1305_C + +/** + * \def MBEDTLS_RIPEMD160_C + * + * Enable the RIPEMD-160 hash algorithm. + * + * Module: library/ripemd160.c + * Caller: library/md.c + * + */ +#define MBEDTLS_RIPEMD160_C + +/** + * \def MBEDTLS_RSA_C + * + * Enable the RSA public-key cryptosystem. + * + * Module: library/rsa.c + * library/rsa_internal.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * library/x509.c + * + * This module is used by the following key exchanges: + * RSA, DHE-RSA, ECDHE-RSA, RSA-PSK + * + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C + */ +#define MBEDTLS_RSA_C + +/** + * \def MBEDTLS_SHA1_C + * + * Enable the SHA1 cryptographic hash algorithm. + * + * Module: library/sha1.c + * Caller: library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * library/x509write_crt.c + * + * This module is required for SSL/TLS up to version 1.1, for TLS 1.2 + * depending on the handshake parameters, and for SHA1-signed certificates. + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. If possible, we recommend avoiding dependencies + * on it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_SHA1_C + +/** + * \def MBEDTLS_SHA256_C + * + * Enable the SHA-224 and SHA-256 cryptographic hash algorithms. + * + * Module: library/sha256.c + * Caller: library/entropy.c + * library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * This module adds support for SHA-224 and SHA-256. + * This module is required for the SSL/TLS 1.2 PRF function. + */ +#define MBEDTLS_SHA256_C + +/** + * \def MBEDTLS_SHA512_C + * + * Enable the SHA-384 and SHA-512 cryptographic hash algorithms. + * + * Module: library/sha512.c + * Caller: library/entropy.c + * library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * + * This module adds support for SHA-384 and SHA-512. + */ +#define MBEDTLS_SHA512_C + +/** + * \def MBEDTLS_SSL_CACHE_C + * + * Enable simple SSL cache implementation. + * + * Module: library/ssl_cache.c + * Caller: + * + * Requires: MBEDTLS_SSL_CACHE_C + */ +#define MBEDTLS_SSL_CACHE_C + +/** + * \def MBEDTLS_SSL_COOKIE_C + * + * Enable basic implementation of DTLS cookies for hello verification. + * + * Module: library/ssl_cookie.c + * Caller: + */ +#define MBEDTLS_SSL_COOKIE_C + +/** + * \def MBEDTLS_SSL_TICKET_C + * + * Enable an implementation of TLS server-side callbacks for session tickets. + * + * Module: library/ssl_ticket.c + * Caller: + * + * Requires: MBEDTLS_CIPHER_C + */ +#define MBEDTLS_SSL_TICKET_C + +/** + * \def MBEDTLS_SSL_CLI_C + * + * Enable the SSL/TLS client code. + * + * Module: library/ssl_cli.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * This module is required for SSL/TLS client support. + */ +#define MBEDTLS_SSL_CLI_C + +/** + * \def MBEDTLS_SSL_SRV_C + * + * Enable the SSL/TLS server code. + * + * Module: library/ssl_srv.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * This module is required for SSL/TLS server support. + */ +#define MBEDTLS_SSL_SRV_C + +/** + * \def MBEDTLS_SSL_TLS_C + * + * Enable the generic SSL/TLS code. + * + * Module: library/ssl_tls.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * and at least one of the MBEDTLS_SSL_PROTO_XXX defines + * + * This module is required for SSL/TLS. + */ +#define MBEDTLS_SSL_TLS_C + +/** + * \def MBEDTLS_THREADING_C + * + * Enable the threading abstraction layer. + * By default mbed TLS assumes it is used in a non-threaded environment or that + * contexts are not shared between threads. If you do intend to use contexts + * between threads, you will need to enable this layer to prevent race + * conditions. See also our Knowledge Base article about threading: + * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading + * + * Module: library/threading.c + * + * This allows different threading implementations (self-implemented or + * provided). + * + * You will have to enable either MBEDTLS_THREADING_ALT or + * MBEDTLS_THREADING_PTHREAD. + * + * Enable this layer to allow use of mutexes within mbed TLS + */ +//#define MBEDTLS_THREADING_C + +/** + * \def MBEDTLS_TIMING_C + * + * Enable the semi-portable timing interface. + * + * \note The provided implementation only works on POSIX/Unix (including Linux, + * BSD and OS X) and Windows. On other platforms, you can either disable that + * module and provide your own implementations of the callbacks needed by + * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide + * your own implementation of the whole module by setting + * \c MBEDTLS_TIMING_ALT in the current file. + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/timing.c + * Caller: library/havege.c + * + * This module is used by the HAVEGE random number generator. + */ +#define MBEDTLS_TIMING_C + +/** + * \def MBEDTLS_VERSION_C + * + * Enable run-time version information. + * + * Module: library/version.c + * + * This module provides run-time version information. + */ +#define MBEDTLS_VERSION_C + +/** + * \def MBEDTLS_X509_USE_C + * + * Enable X.509 core for using certificates. + * + * Module: library/x509.c + * Caller: library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, + * MBEDTLS_PK_PARSE_C + * + * This module is required for the X.509 parsing modules. + */ +#define MBEDTLS_X509_USE_C + +/** + * \def MBEDTLS_X509_CRT_PARSE_C + * + * Enable X.509 certificate parsing. + * + * Module: library/x509_crt.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 certificate parsing. + */ +#define MBEDTLS_X509_CRT_PARSE_C + +/** + * \def MBEDTLS_X509_CRL_PARSE_C + * + * Enable X.509 CRL parsing. + * + * Module: library/x509_crl.c + * Caller: library/x509_crt.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 CRL parsing. + */ +#define MBEDTLS_X509_CRL_PARSE_C + +/** + * \def MBEDTLS_X509_CSR_PARSE_C + * + * Enable X.509 Certificate Signing Request (CSR) parsing. + * + * Module: library/x509_csr.c + * Caller: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is used for reading X.509 certificate request. + */ +#define MBEDTLS_X509_CSR_PARSE_C + +/** + * \def MBEDTLS_X509_CREATE_C + * + * Enable X.509 core for creating certificates. + * + * Module: library/x509_create.c + * + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C + * + * This module is the basis for creating X.509 certificates and CSRs. + */ +#define MBEDTLS_X509_CREATE_C + +/** + * \def MBEDTLS_X509_CRT_WRITE_C + * + * Enable creating X.509 certificates. + * + * Module: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate creation. + */ +#define MBEDTLS_X509_CRT_WRITE_C + +/** + * \def MBEDTLS_X509_CSR_WRITE_C + * + * Enable creating X.509 Certificate Signing Requests (CSR). + * + * Module: library/x509_csr_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate request writing. + */ +#define MBEDTLS_X509_CSR_WRITE_C + +/** + * \def MBEDTLS_XTEA_C + * + * Enable the XTEA block cipher. + * + * Module: library/xtea.c + * Caller: + */ +#define MBEDTLS_XTEA_C + +/* \} name SECTION: mbed TLS modules */ + +/** + * \name SECTION: Module configuration options + * + * This section allows for the setting of module specific sizes and + * configuration options. The default values are already present in the + * relevant header files and should suffice for the regular use cases. + * + * Our advice is to enable options and change their values here + * only if you have a good reason and know the consequences. + * + * Please check the respective header file for documentation on these + * parameters (to prevent duplicate documentation). + * \{ + */ + +/* MPI / BIGNUM options */ +//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum window size used. */ +//#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ + +/* CTR_DRBG options */ +//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */ +//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +//#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +//#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ + +/* HMAC_DRBG options */ +//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +//#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ + +/* ECP options */ +//#define MBEDTLS_ECP_MAX_BITS 521 /**< Maximum bit size of groups */ +//#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< Maximum window size used */ +//#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */ + +/* Entropy options */ +//#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ +//#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ +//#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */ + +/* Memory buffer allocator options */ +//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ + +/* Platform options */ +//#define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ +//#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< Default allocator to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_FREE free /**< Default free to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +/* Note: your snprintf must correctly zero-terminate the buffer! */ +//#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */ + +/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */ +/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ +//#define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */ +/* Note: your snprintf must correctly zero-terminate the buffer! */ +//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ + +/** + * \brief This macro is invoked by the library when an invalid parameter + * is detected that is only checked with #MBEDTLS_CHECK_PARAMS + * (see the documentation of that option for context). + * + * When you leave this undefined here, the library provides + * a default definition. If the macro #MBEDTLS_CHECK_PARAMS_ASSERT + * is defined, the default definition is `assert(cond)`, + * otherwise the default definition calls a function + * mbedtls_param_failed(). This function is declared in + * `platform_util.h` for the benefit of the library, but + * you need to define in your application. + * + * When you define this here, this replaces the default + * definition in platform_util.h (which no longer declares the + * function mbedtls_param_failed()) and it is your responsibility + * to make sure this macro expands to something suitable (in + * particular, that all the necessary declarations are visible + * from within the library - you can ensure that by providing + * them in this file next to the macro definition). + * If you define this macro to call `assert`, also define + * #MBEDTLS_CHECK_PARAMS_ASSERT so that library source files + * include ``. + * + * Note that you may define this macro to expand to nothing, in + * which case you don't have to worry about declarations or + * definitions. However, you will then be notified about invalid + * parameters only in non-void functions, and void function will + * just silently return early on invalid parameters, which + * partially negates the benefits of enabling + * #MBEDTLS_CHECK_PARAMS in the first place, so is discouraged. + * + * \param cond The expression that should evaluate to true, but doesn't. + */ +//#define MBEDTLS_PARAM_FAILED( cond ) assert( cond ) + +/* SSL Cache options */ +//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ +//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ + +/* SSL options */ + +/** \def MBEDTLS_SSL_MAX_CONTENT_LEN + * + * Maximum length (in bytes) of incoming and outgoing plaintext fragments. + * + * This determines the size of both the incoming and outgoing TLS I/O buffers + * in such a way that both are capable of holding the specified amount of + * plaintext data, regardless of the protection mechanism used. + * + * To configure incoming and outgoing I/O buffers separately, use + * #MBEDTLS_SSL_IN_CONTENT_LEN and #MBEDTLS_SSL_OUT_CONTENT_LEN, + * which overwrite the value set by this option. + * + * \note When using a value less than the default of 16KB on the client, it is + * recommended to use the Maximum Fragment Length (MFL) extension to + * inform the server about this limitation. On the server, there + * is no supported, standardized way of informing the client about + * restriction on the maximum size of incoming messages, and unless + * the limitation has been communicated by other means, it is recommended + * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN + * while keeping the default value of 16KB for the incoming buffer. + * + * Uncomment to set the maximum plaintext size of both + * incoming and outgoing I/O buffers. + */ +//#define MBEDTLS_SSL_MAX_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_IN_CONTENT_LEN + * + * Maximum length (in bytes) of incoming plaintext fragments. + * + * This determines the size of the incoming TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * If this option is undefined, it inherits its value from + * #MBEDTLS_SSL_MAX_CONTENT_LEN. + * + * \note When using a value less than the default of 16KB on the client, it is + * recommended to use the Maximum Fragment Length (MFL) extension to + * inform the server about this limitation. On the server, there + * is no supported, standardized way of informing the client about + * restriction on the maximum size of incoming messages, and unless + * the limitation has been communicated by other means, it is recommended + * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN + * while keeping the default value of 16KB for the incoming buffer. + * + * Uncomment to set the maximum plaintext size of the incoming I/O buffer + * independently of the outgoing I/O buffer. + */ +//#define MBEDTLS_SSL_IN_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_OUT_CONTENT_LEN + * + * Maximum length (in bytes) of outgoing plaintext fragments. + * + * This determines the size of the outgoing TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * If this option undefined, it inherits its value from + * #MBEDTLS_SSL_MAX_CONTENT_LEN. + * + * It is possible to save RAM by setting a smaller outward buffer, while keeping + * the default inward 16384 byte buffer to conform to the TLS specification. + * + * The minimum required outward buffer size is determined by the handshake + * protocol's usage. Handshaking will fail if the outward buffer is too small. + * The specific size requirement depends on the configured ciphers and any + * certificate data which is sent during the handshake. + * + * Uncomment to set the maximum plaintext size of the outgoing I/O buffer + * independently of the incoming I/O buffer. + */ +//#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING + * + * Maximum number of heap-allocated bytes for the purpose of + * DTLS handshake message reassembly and future message buffering. + * + * This should be at least 9/8 * MBEDTLSSL_IN_CONTENT_LEN + * to account for a reassembled handshake message of maximum size, + * together with its reassembly bitmap. + * + * A value of 2 * MBEDTLS_SSL_IN_CONTENT_LEN (32768 by default) + * should be sufficient for all practical situations as it allows + * to reassembly a large handshake message (such as a certificate) + * while buffering multiple smaller handshake messages. + * + */ +//#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 + +//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME 86400 /**< Lifetime of session tickets (if enabled) */ +//#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */ +//#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ + +/** + * Complete list of ciphersuites to use, in order of preference. + * + * \warning No dependency checking is done on that field! This option can only + * be used to restrict the set of available ciphersuites. It is your + * responsibility to make sure the needed modules are active. + * + * Use this to save a few hundred bytes of ROM (default ordering of all + * available ciphersuites) and a few to a few hundred bytes of RAM. + * + * The value below is only an example, not the default. + */ +//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + +/* X509 options */ +//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */ +//#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */ + +/** + * Allow SHA-1 in the default TLS configuration for certificate signing. + * Without this build-time option, SHA-1 support must be activated explicitly + * through mbedtls_ssl_conf_cert_profile. Turning on this option is not + * recommended because of it is possible to generate SHA-1 collisions, however + * this may be safe for legacy infrastructure where additional controls apply. + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. If possible, we recommend avoiding dependencies + * on it, and considering stronger message digests instead. + * + */ +// #define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES + +/** + * Allow SHA-1 in the default TLS configuration for TLS 1.2 handshake + * signature and ciphersuite selection. Without this build-time option, SHA-1 + * support must be activated explicitly through mbedtls_ssl_conf_sig_hashes. + * The use of SHA-1 in TLS <= 1.1 and in HMAC-SHA-1 is always allowed by + * default. At the time of writing, there is no practical attack on the use + * of SHA-1 in handshake signatures, hence this option is turned on by default + * to preserve compatibility with existing peers, but the general + * warning applies nonetheless: + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. If possible, we recommend avoiding dependencies + * on it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE + +/** + * Uncomment the macro to let mbed TLS use your alternate implementation of + * mbedtls_platform_zeroize(). This replaces the default implementation in + * platform_util.c. + * + * mbedtls_platform_zeroize() is a widely used function across the library to + * zero a block of memory. The implementation is expected to be secure in the + * sense that it has been written to prevent the compiler from removing calls + * to mbedtls_platform_zeroize() as part of redundant code elimination + * optimizations. However, it is difficult to guarantee that calls to + * mbedtls_platform_zeroize() will not be optimized by the compiler as older + * versions of the C language standards do not provide a secure implementation + * of memset(). Therefore, MBEDTLS_PLATFORM_ZEROIZE_ALT enables users to + * configure their own implementation of mbedtls_platform_zeroize(), for + * example by using directives specific to their compiler, features from newer + * C standards (e.g using memset_s() in C11) or calling a secure memset() from + * their system (e.g explicit_bzero() in BSD). + */ +//#define MBEDTLS_PLATFORM_ZEROIZE_ALT + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_gmtime_r(). This replaces the default implementation in + * platform_util.c. + * + * gmtime() is not a thread-safe function as defined in the C standard. The + * library will try to use safer implementations of this function, such as + * gmtime_r() when available. However, if Mbed TLS cannot identify the target + * system, the implementation of mbedtls_platform_gmtime_r() will default to + * using the standard gmtime(). In this case, calls from the library to + * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex + * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the + * library are also guarded with this mutex to avoid race conditions. However, + * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will + * unconditionally use the implementation for mbedtls_platform_gmtime_r() + * supplied at compile time. + */ +//#define MBEDTLS_PLATFORM_GMTIME_R_ALT + +/* \} name SECTION: Customisation configuration options */ + +/* Target and application specific configurations + * + * Allow user to override any previous default. + * + */ +#if defined(MBEDTLS_USER_CONFIG_FILE) +#include MBEDTLS_USER_CONFIG_FILE +#endif + +#include "check_config.h" + +#endif /* MBEDTLS_CONFIG_H */ diff --git a/src/common/mbedtls/include/mbedtls/ctr_drbg.h b/src/common/mbedtls/include/mbedtls/ctr_drbg.h new file mode 100644 index 0000000000..86cdc12a35 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/ctr_drbg.h @@ -0,0 +1,569 @@ +/** + * \file ctr_drbg.h + * + * \brief This file contains definitions and functions for the + * CTR_DRBG pseudorandom generator. + * + * CTR_DRBG is a standardized way of building a PRNG from a block-cipher + * in counter mode operation, as defined in NIST SP 800-90A: + * Recommendation for Random Number Generation Using Deterministic Random + * Bit Generators. + * + * The Mbed TLS implementation of CTR_DRBG uses AES-256 (default) or AES-128 + * (if \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled at compile time) + * as the underlying block cipher, with a derivation function. + * The initial seeding grabs #MBEDTLS_CTR_DRBG_ENTROPY_LEN bytes of entropy. + * See the documentation of mbedtls_ctr_drbg_seed() for more details. + * + * Based on NIST SP 800-90A §10.2.1 table 3 and NIST SP 800-57 part 1 table 2, + * here are the security strengths achieved in typical configuration: + * - 256 bits under the default configuration of the library, with AES-256 + * and with #MBEDTLS_CTR_DRBG_ENTROPY_LEN set to 48 or more. + * - 256 bits if AES-256 is used, #MBEDTLS_CTR_DRBG_ENTROPY_LEN is set + * to 32 or more, and the DRBG is initialized with an explicit + * nonce in the \c custom parameter to mbedtls_ctr_drbg_seed(). + * - 128 bits if AES-256 is used but #MBEDTLS_CTR_DRBG_ENTROPY_LEN is + * between 24 and 47 and the DRBG is not initialized with an explicit + * nonce (see mbedtls_ctr_drbg_seed()). + * - 128 bits if AES-128 is used (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY enabled) + * and #MBEDTLS_CTR_DRBG_ENTROPY_LEN is set to 24 or more (which is + * always the case unless it is explicitly set to a different value + * in config.h). + * + * Note that the value of #MBEDTLS_CTR_DRBG_ENTROPY_LEN defaults to: + * - \c 48 if the module \c MBEDTLS_SHA512_C is enabled and the symbol + * \c MBEDTLS_ENTROPY_FORCE_SHA256 is disabled at compile time. + * This is the default configuration of the library. + * - \c 32 if the module \c MBEDTLS_SHA512_C is disabled at compile time. + * - \c 32 if \c MBEDTLS_ENTROPY_FORCE_SHA256 is enabled at compile time. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_CTR_DRBG_H +#define MBEDTLS_CTR_DRBG_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "aes.h" + +#if defined(MBEDTLS_THREADING_C) +#include "threading.h" +#endif + +#define MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED -0x0034 /**< The entropy source failed. */ +#define MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG -0x0036 /**< The requested random buffer length is too big. */ +#define MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG -0x0038 /**< The input (entropy + additional data) is too large. */ +#define MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR -0x003A /**< Read or write error in file. */ + +#define MBEDTLS_CTR_DRBG_BLOCKSIZE 16 /**< The block size used by the cipher. */ + +#if defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) +#define MBEDTLS_CTR_DRBG_KEYSIZE 16 +/**< The key size in bytes used by the cipher. + * + * Compile-time choice: 16 bytes (128 bits) + * because #MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled. + */ +#else +#define MBEDTLS_CTR_DRBG_KEYSIZE 32 +/**< The key size in bytes used by the cipher. + * + * Compile-time choice: 32 bytes (256 bits) + * because \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled. + */ +#endif + +#define MBEDTLS_CTR_DRBG_KEYBITS ( MBEDTLS_CTR_DRBG_KEYSIZE * 8 ) /**< The key size for the DRBG operation, in bits. */ +#define MBEDTLS_CTR_DRBG_SEEDLEN ( MBEDTLS_CTR_DRBG_KEYSIZE + MBEDTLS_CTR_DRBG_BLOCKSIZE ) /**< The seed length, calculated as (counter + AES key). */ + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in config.h or define them using the compiler command + * line. + * \{ + */ + +/** \def MBEDTLS_CTR_DRBG_ENTROPY_LEN + * + * \brief The amount of entropy used per seed by default, in bytes. + */ +#if !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) +#if defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) +/** This is 48 bytes because the entropy module uses SHA-512 + * (\c MBEDTLS_ENTROPY_FORCE_SHA256 is disabled). + */ +#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 + +#else /* defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) */ + +/** This is 32 bytes because the entropy module uses SHA-256 + * (the SHA512 module is disabled or + * \c MBEDTLS_ENTROPY_FORCE_SHA256 is enabled). + */ +#if !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) +/** \warning To achieve a 256-bit security strength, you must pass a nonce + * to mbedtls_ctr_drbg_seed(). + */ +#endif /* !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) */ +#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 32 +#endif /* defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) */ +#endif /* !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) */ + +#if !defined(MBEDTLS_CTR_DRBG_RESEED_INTERVAL) +#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 +/**< The interval before reseed is performed by default. */ +#endif + +#if !defined(MBEDTLS_CTR_DRBG_MAX_INPUT) +#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 +/**< The maximum number of additional input Bytes. */ +#endif + +#if !defined(MBEDTLS_CTR_DRBG_MAX_REQUEST) +#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 +/**< The maximum number of requested Bytes per call. */ +#endif + +#if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT) +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 +/**< The maximum size of seed or reseed buffer in bytes. */ +#endif + +/* \} name SECTION: Module settings */ + +#define MBEDTLS_CTR_DRBG_PR_OFF 0 +/**< Prediction resistance is disabled. */ +#define MBEDTLS_CTR_DRBG_PR_ON 1 +/**< Prediction resistance is enabled. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief The CTR_DRBG context structure. + */ +typedef struct mbedtls_ctr_drbg_context +{ + unsigned char counter[16]; /*!< The counter (V). */ + int reseed_counter; /*!< The reseed counter. */ + int prediction_resistance; /*!< This determines whether prediction + resistance is enabled, that is + whether to systematically reseed before + each random generation. */ + size_t entropy_len; /*!< The amount of entropy grabbed on each + seed or reseed operation. */ + int reseed_interval; /*!< The reseed interval. */ + + mbedtls_aes_context aes_ctx; /*!< The AES context. */ + + /* + * Callbacks (Entropy) + */ + int (*f_entropy)(void *, unsigned char *, size_t); + /*!< The entropy callback function. */ + + void *p_entropy; /*!< The context for the entropy function. */ + +#if defined(MBEDTLS_THREADING_C) + /* Invariant: the mutex is initialized if and only if f_entropy != NULL. + * This means that the mutex is initialized during the initial seeding + * in mbedtls_ctr_drbg_seed() and freed in mbedtls_ctr_drbg_free(). + * + * Note that this invariant may change without notice. Do not rely on it + * and do not access the mutex directly in application code. + */ + mbedtls_threading_mutex_t mutex; +#endif +} +mbedtls_ctr_drbg_context; + +/** + * \brief This function initializes the CTR_DRBG context, + * and prepares it for mbedtls_ctr_drbg_seed() + * or mbedtls_ctr_drbg_free(). + * + * \note The reseed interval is + * #MBEDTLS_CTR_DRBG_RESEED_INTERVAL by default. + * You can override it by calling + * mbedtls_ctr_drbg_set_reseed_interval(). + * + * \param ctx The CTR_DRBG context to initialize. + */ +void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ); + +/** + * \brief This function seeds and sets up the CTR_DRBG + * entropy source for future reseeds. + * + * A typical choice for the \p f_entropy and \p p_entropy parameters is + * to use the entropy module: + * - \p f_entropy is mbedtls_entropy_func(); + * - \p p_entropy is an instance of ::mbedtls_entropy_context initialized + * with mbedtls_entropy_init() (which registers the platform's default + * entropy sources). + * + * The entropy length is #MBEDTLS_CTR_DRBG_ENTROPY_LEN by default. + * You can override it by calling mbedtls_ctr_drbg_set_entropy_len(). + * + * You can provide a personalization string in addition to the + * entropy source, to make this instantiation as unique as possible. + * + * \note The _seed_material_ value passed to the derivation + * function in the CTR_DRBG Instantiate Process + * described in NIST SP 800-90A §10.2.1.3.2 + * is the concatenation of the string obtained from + * calling \p f_entropy and the \p custom string. + * The origin of the nonce depends on the value of + * the entropy length relative to the security strength. + * - If the entropy length is at least 1.5 times the + * security strength then the nonce is taken from the + * string obtained with \p f_entropy. + * - If the entropy length is less than the security + * strength, then the nonce is taken from \p custom. + * In this case, for compliance with SP 800-90A, + * you must pass a unique value of \p custom at + * each invocation. See SP 800-90A §8.6.7 for more + * details. + */ +#if MBEDTLS_CTR_DRBG_ENTROPY_LEN < MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 +/** \warning When #MBEDTLS_CTR_DRBG_ENTROPY_LEN is less than + * #MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2, to achieve the + * maximum security strength permitted by CTR_DRBG, + * you must pass a value of \p custom that is a nonce: + * this value must never be repeated in subsequent + * runs of the same application or on a different + * device. + */ +#endif +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * after this function returns successfully, + * it is safe to call mbedtls_ctr_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** + * \param ctx The CTR_DRBG context to seed. + * It must have been initialized with + * mbedtls_ctr_drbg_init(). + * After a successful call to mbedtls_ctr_drbg_seed(), + * you may not call mbedtls_ctr_drbg_seed() again on + * the same context unless you call + * mbedtls_ctr_drbg_free() and mbedtls_ctr_drbg_init() + * again first. + * After a failed call to mbedtls_ctr_drbg_seed(), + * you must call mbedtls_ctr_drbg_free(). + * \param f_entropy The entropy callback, taking as arguments the + * \p p_entropy context, the buffer to fill, and the + * length of the buffer. + * \p f_entropy is always called with a buffer size + * equal to the entropy length. + * \param p_entropy The entropy context to pass to \p f_entropy. + * \param custom The personalization string. + * This can be \c NULL, in which case the personalization + * string is empty regardless of the value of \p len. + * \param len The length of the personalization string. + * This must be at most + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * - #MBEDTLS_CTR_DRBG_ENTROPY_LEN. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure. + */ +int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len ); + +/** + * \brief This function resets CTR_DRBG context to the state immediately + * after initial call of mbedtls_ctr_drbg_init(). + * + * \param ctx The CTR_DRBG context to clear. + */ +void mbedtls_ctr_drbg_free( mbedtls_ctr_drbg_context *ctx ); + +/** + * \brief This function turns prediction resistance on or off. + * The default value is off. + * + * \note If enabled, entropy is gathered at the beginning of + * every call to mbedtls_ctr_drbg_random_with_add() + * or mbedtls_ctr_drbg_random(). + * Only use this if your entropy source has sufficient + * throughput. + * + * \param ctx The CTR_DRBG context. + * \param resistance #MBEDTLS_CTR_DRBG_PR_ON or #MBEDTLS_CTR_DRBG_PR_OFF. + */ +void mbedtls_ctr_drbg_set_prediction_resistance( mbedtls_ctr_drbg_context *ctx, + int resistance ); + +/** + * \brief This function sets the amount of entropy grabbed on each + * seed or reseed. + * + * The default value is #MBEDTLS_CTR_DRBG_ENTROPY_LEN. + * + * \note The security strength of CTR_DRBG is bounded by the + * entropy length. Thus: + * - When using AES-256 + * (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled, + * which is the default), + * \p len must be at least 32 (in bytes) + * to achieve a 256-bit strength. + * - When using AES-128 + * (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled) + * \p len must be at least 16 (in bytes) + * to achieve a 128-bit strength. + * + * \param ctx The CTR_DRBG context. + * \param len The amount of entropy to grab, in bytes. + * This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + */ +void mbedtls_ctr_drbg_set_entropy_len( mbedtls_ctr_drbg_context *ctx, + size_t len ); + +/** + * \brief This function sets the reseed interval. + * + * The reseed interval is the number of calls to mbedtls_ctr_drbg_random() + * or mbedtls_ctr_drbg_random_with_add() after which the entropy function + * is called again. + * + * The default value is #MBEDTLS_CTR_DRBG_RESEED_INTERVAL. + * + * \param ctx The CTR_DRBG context. + * \param interval The reseed interval. + */ +void mbedtls_ctr_drbg_set_reseed_interval( mbedtls_ctr_drbg_context *ctx, + int interval ); + +/** + * \brief This function reseeds the CTR_DRBG context, that is + * extracts data from the entropy source. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param ctx The CTR_DRBG context. + * \param additional Additional data to add to the state. Can be \c NULL. + * \param len The length of the additional data. + * This must be less than + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len + * where \c entropy_len is the entropy length + * configured for the context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure. + */ +int mbedtls_ctr_drbg_reseed( mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, size_t len ); + +/** + * \brief This function updates the state of the CTR_DRBG context. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param ctx The CTR_DRBG context. + * \param additional The data to update the state with. This must not be + * \c NULL unless \p add_len is \c 0. + * \param add_len Length of \p additional in bytes. This must be at + * most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if + * \p add_len is more than + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * \return An error from the underlying AES cipher on failure. + */ +int mbedtls_ctr_drbg_update_ret( mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, + size_t add_len ); + +/** + * \brief This function updates a CTR_DRBG instance with additional + * data and uses it to generate random data. + * + * This function automatically reseeds if the reseed counter is exceeded + * or prediction resistance is enabled. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param p_rng The CTR_DRBG context. This must be a pointer to a + * #mbedtls_ctr_drbg_context structure. + * \param output The buffer to fill. + * \param output_len The length of the buffer in bytes. + * \param additional Additional data to update. Can be \c NULL, in which + * case the additional data is empty regardless of + * the value of \p add_len. + * \param add_len The length of the additional data + * if \p additional is not \c NULL. + * This must be less than #MBEDTLS_CTR_DRBG_MAX_INPUT + * and less than + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len + * where \c entropy_len is the entropy length + * configured for the context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or + * #MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure. + */ +int mbedtls_ctr_drbg_random_with_add( void *p_rng, + unsigned char *output, size_t output_len, + const unsigned char *additional, size_t add_len ); + +/** + * \brief This function uses CTR_DRBG to generate random data. + * + * This function automatically reseeds if the reseed counter is exceeded + * or prediction resistance is enabled. + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * it is safe to call mbedtls_ctr_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** + * \param p_rng The CTR_DRBG context. This must be a pointer to a + * #mbedtls_ctr_drbg_context structure. + * \param output The buffer to fill. + * \param output_len The length of the buffer in bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or + * #MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure. + */ +int mbedtls_ctr_drbg_random( void *p_rng, + unsigned char *output, size_t output_len ); + + +#if ! defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief This function updates the state of the CTR_DRBG context. + * + * \deprecated Superseded by mbedtls_ctr_drbg_update_ret() + * in 2.16.0. + * + * \note If \p add_len is greater than + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT, only the first + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT Bytes are used. + * The remaining Bytes are silently discarded. + * + * \param ctx The CTR_DRBG context. + * \param additional The data to update the state with. + * \param add_len Length of \p additional data. + */ +MBEDTLS_DEPRECATED void mbedtls_ctr_drbg_update( + mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, + size_t add_len ); +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_FS_IO) +/** + * \brief This function writes a seed file. + * + * \param ctx The CTR_DRBG context. + * \param path The name of the file. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on reseed + * failure. + */ +int mbedtls_ctr_drbg_write_seed_file( mbedtls_ctr_drbg_context *ctx, const char *path ); + +/** + * \brief This function reads and updates a seed file. The seed + * is added to this instance. + * + * \param ctx The CTR_DRBG context. + * \param path The name of the file. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on + * reseed failure. + * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if the existing + * seed file is too large. + */ +int mbedtls_ctr_drbg_update_seed_file( mbedtls_ctr_drbg_context *ctx, const char *path ); +#endif /* MBEDTLS_FS_IO */ + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The CTR_DRBG checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_ctr_drbg_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +/* Internal functions (do not call directly) */ +int mbedtls_ctr_drbg_seed_entropy_len( mbedtls_ctr_drbg_context *, + int (*)(void *, unsigned char *, size_t), void *, + const unsigned char *, size_t, size_t ); + +#ifdef __cplusplus +} +#endif + +#endif /* ctr_drbg.h */ diff --git a/src/common/mbedtls/include/mbedtls/des.h b/src/common/mbedtls/include/mbedtls/des.h new file mode 100644 index 0000000000..c49febe776 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/des.h @@ -0,0 +1,365 @@ +/** + * \file des.h + * + * \brief DES block cipher + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_DES_H +#define MBEDTLS_DES_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include + +#define MBEDTLS_DES_ENCRYPT 1 +#define MBEDTLS_DES_DECRYPT 0 + +#define MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH -0x0032 /**< The data input has an invalid length. */ + +/* MBEDTLS_ERR_DES_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_DES_HW_ACCEL_FAILED -0x0033 /**< DES hardware accelerator failed. */ + +#define MBEDTLS_DES_KEY_SIZE 8 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_DES_ALT) +// Regular implementation +// + +/** + * \brief DES context structure + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +typedef struct mbedtls_des_context +{ + uint32_t sk[32]; /*!< DES subkeys */ +} +mbedtls_des_context; + +/** + * \brief Triple-DES context structure + */ +typedef struct mbedtls_des3_context +{ + uint32_t sk[96]; /*!< 3DES subkeys */ +} +mbedtls_des3_context; + +#else /* MBEDTLS_DES_ALT */ +#include "des_alt.h" +#endif /* MBEDTLS_DES_ALT */ + +/** + * \brief Initialize DES context + * + * \param ctx DES context to be initialized + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des_init( mbedtls_des_context *ctx ); + +/** + * \brief Clear DES context + * + * \param ctx DES context to be cleared + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des_free( mbedtls_des_context *ctx ); + +/** + * \brief Initialize Triple-DES context + * + * \param ctx DES3 context to be initialized + */ +void mbedtls_des3_init( mbedtls_des3_context *ctx ); + +/** + * \brief Clear Triple-DES context + * + * \param ctx DES3 context to be cleared + */ +void mbedtls_des3_free( mbedtls_des3_context *ctx ); + +/** + * \brief Set key parity on the given key to odd. + * + * DES keys are 56 bits long, but each byte is padded with + * a parity bit to allow verification. + * + * \param key 8-byte secret key + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ); + +/** + * \brief Check that key parity on the given key is odd. + * + * DES keys are 56 bits long, but each byte is padded with + * a parity bit to allow verification. + * + * \param key 8-byte secret key + * + * \return 0 is parity was ok, 1 if parity was not correct. + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); + +/** + * \brief Check that key is not a weak or semi-weak DES key + * + * \param key 8-byte secret key + * + * \return 0 if no weak key was found, 1 if a weak key was identified. + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); + +/** + * \brief DES key schedule (56-bit, encryption) + * + * \param ctx DES context to be initialized + * \param key 8-byte secret key + * + * \return 0 + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); + +/** + * \brief DES key schedule (56-bit, decryption) + * + * \param ctx DES context to be initialized + * \param key 8-byte secret key + * + * \return 0 + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); + +/** + * \brief Triple-DES key schedule (112-bit, encryption) + * + * \param ctx 3DES context to be initialized + * \param key 16-byte secret key + * + * \return 0 + */ +int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + +/** + * \brief Triple-DES key schedule (112-bit, decryption) + * + * \param ctx 3DES context to be initialized + * \param key 16-byte secret key + * + * \return 0 + */ +int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + +/** + * \brief Triple-DES key schedule (168-bit, encryption) + * + * \param ctx 3DES context to be initialized + * \param key 24-byte secret key + * + * \return 0 + */ +int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + +/** + * \brief Triple-DES key schedule (168-bit, decryption) + * + * \param ctx 3DES context to be initialized + * \param key 24-byte secret key + * + * \return 0 + */ +int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + +/** + * \brief DES-ECB block encryption/decryption + * + * \param ctx DES context + * \param input 64-bit input block + * \param output 64-bit output block + * + * \return 0 if successful + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, + const unsigned char input[8], + unsigned char output[8] ); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief DES-CBC buffer encryption/decryption + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx DES context + * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +/** + * \brief 3DES-ECB block encryption/decryption + * + * \param ctx 3DES context + * \param input 64-bit input block + * \param output 64-bit output block + * + * \return 0 if successful + */ +int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, + const unsigned char input[8], + unsigned char output[8] ); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief 3DES-CBC buffer encryption/decryption + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx 3DES context + * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH + */ +int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +/** + * \brief Internal function for key expansion. + * (Only exposed to allow overriding it, + * see MBEDTLS_DES_SETKEY_ALT) + * + * \param SK Round keys + * \param key Base key + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des_setkey( uint32_t SK[32], + const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_des_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* des.h */ diff --git a/src/common/mbedtls/include/mbedtls/ecdh.h b/src/common/mbedtls/include/mbedtls/ecdh.h new file mode 100644 index 0000000000..8c02034316 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/ecdh.h @@ -0,0 +1,450 @@ +/** + * \file ecdh.h + * + * \brief This file contains ECDH definitions and functions. + * + * The Elliptic Curve Diffie-Hellman (ECDH) protocol is an anonymous + * key agreement protocol allowing two parties to establish a shared + * secret over an insecure channel. Each party must have an + * elliptic-curve public–private key pair. + * + * For more information, see NIST SP 800-56A Rev. 2: Recommendation for + * Pair-Wise Key Establishment Schemes Using Discrete Logarithm + * Cryptography. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_ECDH_H +#define MBEDTLS_ECDH_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "ecp.h" + +/* + * Use a backward compatible ECDH context. + * + * This flag is always enabled for now and future versions might add a + * configuration option that conditionally undefines this flag. + * The configuration option in question may have a different name. + * + * Features undefining this flag, must have a warning in their description in + * config.h stating that the feature breaks backward compatibility. + */ +#define MBEDTLS_ECDH_LEGACY_CONTEXT + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Defines the source of the imported EC key. + */ +typedef enum +{ + MBEDTLS_ECDH_OURS, /**< Our key. */ + MBEDTLS_ECDH_THEIRS, /**< The key of the peer. */ +} mbedtls_ecdh_side; + +#if !defined(MBEDTLS_ECDH_LEGACY_CONTEXT) +/** + * Defines the ECDH implementation used. + * + * Later versions of the library may add new variants, therefore users should + * not make any assumptions about them. + */ +typedef enum +{ + MBEDTLS_ECDH_VARIANT_NONE = 0, /*!< Implementation not defined. */ + MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0,/*!< The default Mbed TLS implementation */ +} mbedtls_ecdh_variant; + +/** + * The context used by the default ECDH implementation. + * + * Later versions might change the structure of this context, therefore users + * should not make any assumptions about the structure of + * mbedtls_ecdh_context_mbed. + */ +typedef struct mbedtls_ecdh_context_mbed +{ + mbedtls_ecp_group grp; /*!< The elliptic curve used. */ + mbedtls_mpi d; /*!< The private key. */ + mbedtls_ecp_point Q; /*!< The public key. */ + mbedtls_ecp_point Qp; /*!< The value of the public key of the peer. */ + mbedtls_mpi z; /*!< The shared secret. */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_ctx rs; /*!< The restart context for EC computations. */ +#endif +} mbedtls_ecdh_context_mbed; +#endif + +/** + * + * \warning Performing multiple operations concurrently on the same + * ECDSA context is not supported; objects of this type + * should not be shared between multiple threads. + * \brief The ECDH context structure. + */ +typedef struct mbedtls_ecdh_context +{ +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + mbedtls_ecp_group grp; /*!< The elliptic curve used. */ + mbedtls_mpi d; /*!< The private key. */ + mbedtls_ecp_point Q; /*!< The public key. */ + mbedtls_ecp_point Qp; /*!< The value of the public key of the peer. */ + mbedtls_mpi z; /*!< The shared secret. */ + int point_format; /*!< The format of point export in TLS messages. */ + mbedtls_ecp_point Vi; /*!< The blinding value. */ + mbedtls_ecp_point Vf; /*!< The unblinding value. */ + mbedtls_mpi _d; /*!< The previous \p d. */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + int restart_enabled; /*!< The flag for restartable mode. */ + mbedtls_ecp_restart_ctx rs; /*!< The restart context for EC computations. */ +#endif /* MBEDTLS_ECP_RESTARTABLE */ +#else + uint8_t point_format; /*!< The format of point export in TLS messages + as defined in RFC 4492. */ + mbedtls_ecp_group_id grp_id;/*!< The elliptic curve used. */ + mbedtls_ecdh_variant var; /*!< The ECDH implementation/structure used. */ + union + { + mbedtls_ecdh_context_mbed mbed_ecdh; + } ctx; /*!< Implementation-specific context. The + context in use is specified by the \c var + field. */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + uint8_t restart_enabled; /*!< The flag for restartable mode. Functions of + an alternative implementation not supporting + restartable mode must return + MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED error + if this flag is set. */ +#endif /* MBEDTLS_ECP_RESTARTABLE */ +#endif /* MBEDTLS_ECDH_LEGACY_CONTEXT */ +} +mbedtls_ecdh_context; + +/** + * \brief This function generates an ECDH keypair on an elliptic + * curve. + * + * This function performs the first of two core computations + * implemented during the ECDH key exchange. The second core + * computation is performed by mbedtls_ecdh_compute_shared(). + * + * \see ecp.h + * + * \param grp The ECP group to use. This must be initialized and have + * domain parameters loaded, for example through + * mbedtls_ecp_load() or mbedtls_ecp_tls_read_group(). + * \param d The destination MPI (private key). + * This must be initialized. + * \param Q The destination point (public key). + * This must be initialized. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL in case \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return Another \c MBEDTLS_ERR_ECP_XXX or + * \c MBEDTLS_MPI_XXX error code on failure. + */ +int mbedtls_ecdh_gen_public( mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function computes the shared secret. + * + * This function performs the second of two core computations + * implemented during the ECDH key exchange. The first core + * computation is performed by mbedtls_ecdh_gen_public(). + * + * \see ecp.h + * + * \note If \p f_rng is not NULL, it is used to implement + * countermeasures against side-channel attacks. + * For more information, see mbedtls_ecp_mul(). + * + * \param grp The ECP group to use. This must be initialized and have + * domain parameters loaded, for example through + * mbedtls_ecp_load() or mbedtls_ecp_tls_read_group(). + * \param z The destination MPI (shared secret). + * This must be initialized. + * \param Q The public key from another party. + * This must be initialized. + * \param d Our secret exponent (private key). + * This must be initialized. + * \param f_rng The RNG function. This may be \c NULL if randomization + * of intermediate results during the ECP computations is + * not needed (discouraged). See the documentation of + * mbedtls_ecp_mul() for more. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a + * context argument. + * + * \return \c 0 on success. + * \return Another \c MBEDTLS_ERR_ECP_XXX or + * \c MBEDTLS_MPI_XXX error code on failure. + */ +int mbedtls_ecdh_compute_shared( mbedtls_ecp_group *grp, mbedtls_mpi *z, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function initializes an ECDH context. + * + * \param ctx The ECDH context to initialize. This must not be \c NULL. + */ +void mbedtls_ecdh_init( mbedtls_ecdh_context *ctx ); + +/** + * \brief This function sets up the ECDH context with the information + * given. + * + * This function should be called after mbedtls_ecdh_init() but + * before mbedtls_ecdh_make_params(). There is no need to call + * this function before mbedtls_ecdh_read_params(). + * + * This is the first function used by a TLS server for ECDHE + * ciphersuites. + * + * \param ctx The ECDH context to set up. This must be initialized. + * \param grp_id The group id of the group to set up the context for. + * + * \return \c 0 on success. + */ +int mbedtls_ecdh_setup( mbedtls_ecdh_context *ctx, + mbedtls_ecp_group_id grp_id ); + +/** + * \brief This function frees a context. + * + * \param ctx The context to free. This may be \c NULL, in which + * case this function does nothing. If it is not \c NULL, + * it must point to an initialized ECDH context. + */ +void mbedtls_ecdh_free( mbedtls_ecdh_context *ctx ); + +/** + * \brief This function generates an EC key pair and exports its + * in the format used in a TLS ServerKeyExchange handshake + * message. + * + * This is the second function used by a TLS server for ECDHE + * ciphersuites. (It is called after mbedtls_ecdh_setup().) + * + * \see ecp.h + * + * \param ctx The ECDH context to use. This must be initialized + * and bound to a group, for example via mbedtls_ecdh_setup(). + * \param olen The address at which to store the number of Bytes written. + * \param buf The destination buffer. This must be a writable buffer of + * length \p blen Bytes. + * \param blen The length of the destination buffer \p buf in Bytes. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL in case \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. + */ +int mbedtls_ecdh_make_params( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function parses the ECDHE parameters in a + * TLS ServerKeyExchange handshake message. + * + * \note In a TLS handshake, this is the how the client + * sets up its ECDHE context from the server's public + * ECDHE key material. + * + * \see ecp.h + * + * \param ctx The ECDHE context to use. This must be initialized. + * \param buf On input, \c *buf must be the start of the input buffer. + * On output, \c *buf is updated to point to the end of the + * data that has been read. On success, this is the first byte + * past the end of the ServerKeyExchange parameters. + * On error, this is the point at which an error has been + * detected, which is usually not useful except to debug + * failures. + * \param end The end of the input buffer. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX error code on failure. + * + */ +int mbedtls_ecdh_read_params( mbedtls_ecdh_context *ctx, + const unsigned char **buf, + const unsigned char *end ); + +/** + * \brief This function sets up an ECDH context from an EC key. + * + * It is used by clients and servers in place of the + * ServerKeyEchange for static ECDH, and imports ECDH + * parameters from the EC key information of a certificate. + * + * \see ecp.h + * + * \param ctx The ECDH context to set up. This must be initialized. + * \param key The EC key to use. This must be initialized. + * \param side Defines the source of the key. Possible values are: + * - #MBEDTLS_ECDH_OURS: The key is ours. + * - #MBEDTLS_ECDH_THEIRS: The key is that of the peer. + * + * \return \c 0 on success. + * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. + * + */ +int mbedtls_ecdh_get_params( mbedtls_ecdh_context *ctx, + const mbedtls_ecp_keypair *key, + mbedtls_ecdh_side side ); + +/** + * \brief This function generates a public key and exports it + * as a TLS ClientKeyExchange payload. + * + * This is the second function used by a TLS client for ECDH(E) + * ciphersuites. + * + * \see ecp.h + * + * \param ctx The ECDH context to use. This must be initialized + * and bound to a group, the latter usually by + * mbedtls_ecdh_read_params(). + * \param olen The address at which to store the number of Bytes written. + * This must not be \c NULL. + * \param buf The destination buffer. This must be a writable buffer + * of length \p blen Bytes. + * \param blen The size of the destination buffer \p buf in Bytes. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL in case \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. + */ +int mbedtls_ecdh_make_public( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function parses and processes the ECDHE payload of a + * TLS ClientKeyExchange message. + * + * This is the third function used by a TLS server for ECDH(E) + * ciphersuites. (It is called after mbedtls_ecdh_setup() and + * mbedtls_ecdh_make_params().) + * + * \see ecp.h + * + * \param ctx The ECDH context to use. This must be initialized + * and bound to a group, for example via mbedtls_ecdh_setup(). + * \param buf The pointer to the ClientKeyExchange payload. This must + * be a readable buffer of length \p blen Bytes. + * \param blen The length of the input buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX error code on failure. + */ +int mbedtls_ecdh_read_public( mbedtls_ecdh_context *ctx, + const unsigned char *buf, size_t blen ); + +/** + * \brief This function derives and exports the shared secret. + * + * This is the last function used by both TLS client + * and servers. + * + * \note If \p f_rng is not NULL, it is used to implement + * countermeasures against side-channel attacks. + * For more information, see mbedtls_ecp_mul(). + * + * \see ecp.h + + * \param ctx The ECDH context to use. This must be initialized + * and have its own private key generated and the peer's + * public key imported. + * \param olen The address at which to store the total number of + * Bytes written on success. This must not be \c NULL. + * \param buf The buffer to write the generated shared key to. This + * must be a writable buffer of size \p blen Bytes. + * \param blen The length of the destination buffer \p buf in Bytes. + * \param f_rng The RNG function, for blinding purposes. This may + * b \c NULL if blinding isn't needed. + * \param p_rng The RNG context. This may be \c NULL if \p f_rng + * doesn't need a context argument. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. + */ +int mbedtls_ecdh_calc_secret( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief This function enables restartable EC computations for this + * context. (Default: disabled.) + * + * \see \c mbedtls_ecp_set_max_ops() + * + * \note It is not possible to safely disable restartable + * computations once enabled, except by free-ing the context, + * which cancels possible in-progress operations. + * + * \param ctx The ECDH context to use. This must be initialized. + */ +void mbedtls_ecdh_enable_restart( mbedtls_ecdh_context *ctx ); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +#ifdef __cplusplus +} +#endif + +#endif /* ecdh.h */ diff --git a/src/common/mbedtls/include/mbedtls/ecdsa.h b/src/common/mbedtls/include/mbedtls/ecdsa.h new file mode 100644 index 0000000000..fdb1eed06d --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/ecdsa.h @@ -0,0 +1,614 @@ +/** + * \file ecdsa.h + * + * \brief This file contains ECDSA definitions and functions. + * + * The Elliptic Curve Digital Signature Algorithm (ECDSA) is defined in + * Standards for Efficient Cryptography Group (SECG): + * SEC1 Elliptic Curve Cryptography. + * The use of ECDSA for TLS is defined in RFC-4492: Elliptic Curve + * Cryptography (ECC) Cipher Suites for Transport Layer Security (TLS). + * + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_ECDSA_H +#define MBEDTLS_ECDSA_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "ecp.h" +#include "md.h" + +/* + * RFC-4492 page 20: + * + * Ecdsa-Sig-Value ::= SEQUENCE { + * r INTEGER, + * s INTEGER + * } + * + * Size is at most + * 1 (tag) + 1 (len) + 1 (initial 0) + ECP_MAX_BYTES for each of r and s, + * twice that + 1 (tag) + 2 (len) for the sequence + * (assuming ECP_MAX_BYTES is less than 126 for r and s, + * and less than 124 (total len <= 255) for the sequence) + */ +#if MBEDTLS_ECP_MAX_BYTES > 124 +#error "MBEDTLS_ECP_MAX_BYTES bigger than expected, please fix MBEDTLS_ECDSA_MAX_LEN" +#endif +/** The maximal size of an ECDSA signature in Bytes. */ +#define MBEDTLS_ECDSA_MAX_LEN ( 3 + 2 * ( 3 + MBEDTLS_ECP_MAX_BYTES ) ) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief The ECDSA context structure. + * + * \warning Performing multiple operations concurrently on the same + * ECDSA context is not supported; objects of this type + * should not be shared between multiple threads. + */ +typedef mbedtls_ecp_keypair mbedtls_ecdsa_context; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + +/** + * \brief Internal restart context for ecdsa_verify() + * + * \note Opaque struct, defined in ecdsa.c + */ +typedef struct mbedtls_ecdsa_restart_ver mbedtls_ecdsa_restart_ver_ctx; + +/** + * \brief Internal restart context for ecdsa_sign() + * + * \note Opaque struct, defined in ecdsa.c + */ +typedef struct mbedtls_ecdsa_restart_sig mbedtls_ecdsa_restart_sig_ctx; + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +/** + * \brief Internal restart context for ecdsa_sign_det() + * + * \note Opaque struct, defined in ecdsa.c + */ +typedef struct mbedtls_ecdsa_restart_det mbedtls_ecdsa_restart_det_ctx; +#endif + +/** + * \brief General context for resuming ECDSA operations + */ +typedef struct +{ + mbedtls_ecp_restart_ctx ecp; /*!< base context for ECP restart and + shared administrative info */ + mbedtls_ecdsa_restart_ver_ctx *ver; /*!< ecdsa_verify() sub-context */ + mbedtls_ecdsa_restart_sig_ctx *sig; /*!< ecdsa_sign() sub-context */ +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) + mbedtls_ecdsa_restart_det_ctx *det; /*!< ecdsa_sign_det() sub-context */ +#endif +} mbedtls_ecdsa_restart_ctx; + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +/* Now we can declare functions that take a pointer to that */ +typedef void mbedtls_ecdsa_restart_ctx; + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief This function computes the ECDSA signature of a + * previously-hashed message. + * + * \note The deterministic version implemented in + * mbedtls_ecdsa_sign_det() is usually preferred. + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated + * as defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \see ecp.h + * + * \param grp The context for the elliptic curve to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param r The MPI context in which to store the first part + * the signature. This must be initialized. + * \param s The MPI context in which to store the second part + * the signature. This must be initialized. + * \param d The private signing key. This must be initialized. + * \param buf The content to be signed. This is usually the hash of + * the original data to be signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context parameter. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX + * or \c MBEDTLS_MPI_XXX error code on failure. + */ +int mbedtls_ecdsa_sign( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +/** + * \brief This function computes the ECDSA signature of a + * previously-hashed message, deterministic version. + * + * For more information, see RFC-6979: Deterministic + * Usage of the Digital Signature Algorithm (DSA) and Elliptic + * Curve Digital Signature Algorithm (ECDSA). + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \warning Since the output of the internal RNG is always the same for + * the same key and message, this limits the efficiency of + * blinding and leaks information through side channels. For + * secure behavior use mbedtls_ecdsa_sign_det_ext() instead. + * + * (Optimally the blinding is a random value that is different + * on every execution. In this case the blinding is still + * random from the attackers perspective, but is the same on + * each execution. This means that this blinding does not + * prevent attackers from recovering secrets by combining + * several measurement traces, but may prevent some attacks + * that exploit relationships between secret data.) + * + * \see ecp.h + * + * \param grp The context for the elliptic curve to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param r The MPI context in which to store the first part + * the signature. This must be initialized. + * \param s The MPI context in which to store the second part + * the signature. This must be initialized. + * \param d The private signing key. This must be initialized + * and setup, for example through mbedtls_ecp_gen_privkey(). + * \param buf The hashed content to be signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param md_alg The hash algorithm used to hash the original data. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX + * error code on failure. + */ +int mbedtls_ecdsa_sign_det( mbedtls_ecp_group *grp, mbedtls_mpi *r, + mbedtls_mpi *s, const mbedtls_mpi *d, + const unsigned char *buf, size_t blen, + mbedtls_md_type_t md_alg ); +/** + * \brief This function computes the ECDSA signature of a + * previously-hashed message, deterministic version. + * + * For more information, see RFC-6979: Deterministic + * Usage of the Digital Signature Algorithm (DSA) and Elliptic + * Curve Digital Signature Algorithm (ECDSA). + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \see ecp.h + * + * \param grp The context for the elliptic curve to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param r The MPI context in which to store the first part + * the signature. This must be initialized. + * \param s The MPI context in which to store the second part + * the signature. This must be initialized. + * \param d The private signing key. This must be initialized + * and setup, for example through mbedtls_ecp_gen_privkey(). + * \param buf The hashed content to be signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param md_alg The hash algorithm used to hash the original data. + * \param f_rng_blind The RNG function used for blinding. This must not be + * \c NULL. + * \param p_rng_blind The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context parameter. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX + * error code on failure. + */ +int mbedtls_ecdsa_sign_det_ext( mbedtls_ecp_group *grp, mbedtls_mpi *r, + mbedtls_mpi *s, const mbedtls_mpi *d, + const unsigned char *buf, size_t blen, + mbedtls_md_type_t md_alg, + int (*f_rng_blind)(void *, unsigned char *, + size_t), + void *p_rng_blind ); +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +/** + * \brief This function verifies the ECDSA signature of a + * previously-hashed message. + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.4, step 3. + * + * \see ecp.h + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param buf The hashed content that was signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param Q The public key to use for verification. This must be + * initialized and setup. + * \param r The first integer of the signature. + * This must be initialized. + * \param s The second integer of the signature. + * This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the signature + * is invalid. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX + * error code on failure for any other reason. + */ +int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp, + const unsigned char *buf, size_t blen, + const mbedtls_ecp_point *Q, const mbedtls_mpi *r, + const mbedtls_mpi *s); + +/** + * \brief This function computes the ECDSA signature and writes it + * to a buffer, serialized as defined in RFC-4492: + * Elliptic Curve Cryptography (ECC) Cipher Suites for + * Transport Layer Security (TLS). + * + * \warning It is not thread-safe to use the same context in + * multiple threads. + * + * \note The deterministic version is used if + * #MBEDTLS_ECDSA_DETERMINISTIC is defined. For more + * information, see RFC-6979: Deterministic Usage + * of the Digital Signature Algorithm (DSA) and Elliptic + * Curve Digital Signature Algorithm (ECDSA). + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \see ecp.h + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and private key bound to it, for example + * via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair(). + * \param md_alg The message digest that was used to hash the message. + * \param hash The message hash to be signed. This must be a readable + * buffer of length \p blen Bytes. + * \param hlen The length of the hash \p hash in Bytes. + * \param sig The buffer to which to write the signature. This must be a + * writable buffer of length at least twice as large as the + * size of the curve used, plus 9. For example, 73 Bytes if + * a 256-bit curve is used. A buffer length of + * #MBEDTLS_ECDSA_MAX_LEN is always safe. + * \param slen The address at which to store the actual length of + * the signature written. Must not be \c NULL. + * \param f_rng The RNG function. This must not be \c NULL if + * #MBEDTLS_ECDSA_DETERMINISTIC is unset. Otherwise, + * it is unused and may be set to \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't use a context. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or + * \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_ecdsa_write_signature( mbedtls_ecdsa_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hlen, + unsigned char *sig, size_t *slen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function computes the ECDSA signature and writes it + * to a buffer, in a restartable way. + * + * \see \c mbedtls_ecdsa_write_signature() + * + * \note This function is like \c mbedtls_ecdsa_write_signature() + * but it can return early and restart according to the limit + * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and private key bound to it, for example + * via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair(). + * \param md_alg The message digest that was used to hash the message. + * \param hash The message hash to be signed. This must be a readable + * buffer of length \p blen Bytes. + * \param hlen The length of the hash \p hash in Bytes. + * \param sig The buffer to which to write the signature. This must be a + * writable buffer of length at least twice as large as the + * size of the curve used, plus 9. For example, 73 Bytes if + * a 256-bit curve is used. A buffer length of + * #MBEDTLS_ECDSA_MAX_LEN is always safe. + * \param slen The address at which to store the actual length of + * the signature written. Must not be \c NULL. + * \param f_rng The RNG function. This must not be \c NULL if + * #MBEDTLS_ECDSA_DETERMINISTIC is unset. Otherwise, + * it is unused and may be set to \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't use a context. + * \param rs_ctx The restart context to use. This may be \c NULL to disable + * restarting. If it is not \c NULL, it must point to an + * initialized restart context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or + * \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_ecdsa_write_signature_restartable( mbedtls_ecdsa_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hlen, + unsigned char *sig, size_t *slen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecdsa_restart_ctx *rs_ctx ); + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +#if ! defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief This function computes an ECDSA signature and writes + * it to a buffer, serialized as defined in RFC-4492: + * Elliptic Curve Cryptography (ECC) Cipher Suites for + * Transport Layer Security (TLS). + * + * The deterministic version is defined in RFC-6979: + * Deterministic Usage of the Digital Signature Algorithm (DSA) + * and Elliptic Curve Digital Signature Algorithm (ECDSA). + * + * \warning It is not thread-safe to use the same context in + * multiple threads. + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \see ecp.h + * + * \deprecated Superseded by mbedtls_ecdsa_write_signature() in + * Mbed TLS version 2.0 and later. + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and private key bound to it, for example + * via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair(). + * \param hash The message hash to be signed. This must be a readable + * buffer of length \p blen Bytes. + * \param hlen The length of the hash \p hash in Bytes. + * \param sig The buffer to which to write the signature. This must be a + * writable buffer of length at least twice as large as the + * size of the curve used, plus 9. For example, 73 Bytes if + * a 256-bit curve is used. A buffer length of + * #MBEDTLS_ECDSA_MAX_LEN is always safe. + * \param slen The address at which to store the actual length of + * the signature written. Must not be \c NULL. + * \param md_alg The message digest that was used to hash the message. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or + * \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_ecdsa_write_signature_det( mbedtls_ecdsa_context *ctx, + const unsigned char *hash, size_t hlen, + unsigned char *sig, size_t *slen, + mbedtls_md_type_t md_alg ) MBEDTLS_DEPRECATED; +#undef MBEDTLS_DEPRECATED +#endif /* MBEDTLS_DEPRECATED_REMOVED */ +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +/** + * \brief This function reads and verifies an ECDSA signature. + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.4, step 3. + * + * \see ecp.h + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and public key bound to it. + * \param hash The message hash that was signed. This must be a readable + * buffer of length \p size Bytes. + * \param hlen The size of the hash \p hash. + * \param sig The signature to read and verify. This must be a readable + * buffer of length \p slen Bytes. + * \param slen The size of \p sig in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid. + * \return #MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if there is a valid + * signature in \p sig, but its length is less than \p siglen. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_ERR_MPI_XXX + * error code on failure for any other reason. + */ +int mbedtls_ecdsa_read_signature( mbedtls_ecdsa_context *ctx, + const unsigned char *hash, size_t hlen, + const unsigned char *sig, size_t slen ); + +/** + * \brief This function reads and verifies an ECDSA signature, + * in a restartable way. + * + * \see \c mbedtls_ecdsa_read_signature() + * + * \note This function is like \c mbedtls_ecdsa_read_signature() + * but it can return early and restart according to the limit + * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and public key bound to it. + * \param hash The message hash that was signed. This must be a readable + * buffer of length \p size Bytes. + * \param hlen The size of the hash \p hash. + * \param sig The signature to read and verify. This must be a readable + * buffer of length \p slen Bytes. + * \param slen The size of \p sig in Bytes. + * \param rs_ctx The restart context to use. This may be \c NULL to disable + * restarting. If it is not \c NULL, it must point to an + * initialized restart context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid. + * \return #MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if there is a valid + * signature in \p sig, but its length is less than \p siglen. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_ERR_MPI_XXX + * error code on failure for any other reason. + */ +int mbedtls_ecdsa_read_signature_restartable( mbedtls_ecdsa_context *ctx, + const unsigned char *hash, size_t hlen, + const unsigned char *sig, size_t slen, + mbedtls_ecdsa_restart_ctx *rs_ctx ); + +/** + * \brief This function generates an ECDSA keypair on the given curve. + * + * \see ecp.h + * + * \param ctx The ECDSA context to store the keypair in. + * This must be initialized. + * \param gid The elliptic curve to use. One of the various + * \c MBEDTLS_ECP_DP_XXX macros depending on configuration. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX code on failure. + */ +int mbedtls_ecdsa_genkey( mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); + +/** + * \brief This function sets up an ECDSA context from an EC key pair. + * + * \see ecp.h + * + * \param ctx The ECDSA context to setup. This must be initialized. + * \param key The EC key to use. This must be initialized and hold + * a private-public key pair or a public key. In the former + * case, the ECDSA context may be used for signature creation + * and verification after this call. In the latter case, it + * may be used for signature verification. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX code on failure. + */ +int mbedtls_ecdsa_from_keypair( mbedtls_ecdsa_context *ctx, + const mbedtls_ecp_keypair *key ); + +/** + * \brief This function initializes an ECDSA context. + * + * \param ctx The ECDSA context to initialize. + * This must not be \c NULL. + */ +void mbedtls_ecdsa_init( mbedtls_ecdsa_context *ctx ); + +/** + * \brief This function frees an ECDSA context. + * + * \param ctx The ECDSA context to free. This may be \c NULL, + * in which case this function does nothing. If it + * is not \c NULL, it must be initialized. + */ +void mbedtls_ecdsa_free( mbedtls_ecdsa_context *ctx ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Initialize a restart context. + * + * \param ctx The restart context to initialize. + * This must not be \c NULL. + */ +void mbedtls_ecdsa_restart_init( mbedtls_ecdsa_restart_ctx *ctx ); + +/** + * \brief Free the components of a restart context. + * + * \param ctx The restart context to free. This may be \c NULL, + * in which case this function does nothing. If it + * is not \c NULL, it must be initialized. + */ +void mbedtls_ecdsa_restart_free( mbedtls_ecdsa_restart_ctx *ctx ); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +#ifdef __cplusplus +} +#endif + +#endif /* ecdsa.h */ diff --git a/src/common/mbedtls/include/mbedtls/ecp.h b/src/common/mbedtls/include/mbedtls/ecp.h new file mode 100644 index 0000000000..7de7106764 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/ecp.h @@ -0,0 +1,1185 @@ +/** + * \file ecp.h + * + * \brief This file provides an API for Elliptic Curves over GF(P) (ECP). + * + * The use of ECP in cryptography and TLS is defined in + * Standards for Efficient Cryptography Group (SECG): SEC1 + * Elliptic Curve Cryptography and + * RFC-4492: Elliptic Curve Cryptography (ECC) Cipher Suites + * for Transport Layer Security (TLS). + * + * RFC-2409: The Internet Key Exchange (IKE) defines ECP + * group types. + * + */ + +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_ECP_H +#define MBEDTLS_ECP_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "bignum.h" + +/* + * ECP error codes + */ +#define MBEDTLS_ERR_ECP_BAD_INPUT_DATA -0x4F80 /**< Bad input parameters to function. */ +#define MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL -0x4F00 /**< The buffer is too small to write to. */ +#define MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE -0x4E80 /**< The requested feature is not available, for example, the requested curve is not supported. */ +#define MBEDTLS_ERR_ECP_VERIFY_FAILED -0x4E00 /**< The signature is not valid. */ +#define MBEDTLS_ERR_ECP_ALLOC_FAILED -0x4D80 /**< Memory allocation failed. */ +#define MBEDTLS_ERR_ECP_RANDOM_FAILED -0x4D00 /**< Generation of random value, such as ephemeral key, failed. */ +#define MBEDTLS_ERR_ECP_INVALID_KEY -0x4C80 /**< Invalid private or public key. */ +#define MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH -0x4C00 /**< The buffer contains a valid signature followed by more data. */ + +/* MBEDTLS_ERR_ECP_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_ECP_HW_ACCEL_FAILED -0x4B80 /**< The ECP hardware accelerator failed. */ + +#define MBEDTLS_ERR_ECP_IN_PROGRESS -0x4B00 /**< Operation in progress, call again with the same parameters to continue. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Domain-parameter identifiers: curve, subgroup, and generator. + * + * \note Only curves over prime fields are supported. + * + * \warning This library does not support validation of arbitrary domain + * parameters. Therefore, only standardized domain parameters from trusted + * sources should be used. See mbedtls_ecp_group_load(). + */ +typedef enum +{ + MBEDTLS_ECP_DP_NONE = 0, /*!< Curve not defined. */ + MBEDTLS_ECP_DP_SECP192R1, /*!< Domain parameters for the 192-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_SECP224R1, /*!< Domain parameters for the 224-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_SECP256R1, /*!< Domain parameters for the 256-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_SECP384R1, /*!< Domain parameters for the 384-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_SECP521R1, /*!< Domain parameters for the 521-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_BP256R1, /*!< Domain parameters for 256-bit Brainpool curve. */ + MBEDTLS_ECP_DP_BP384R1, /*!< Domain parameters for 384-bit Brainpool curve. */ + MBEDTLS_ECP_DP_BP512R1, /*!< Domain parameters for 512-bit Brainpool curve. */ + MBEDTLS_ECP_DP_CURVE25519, /*!< Domain parameters for Curve25519. */ + MBEDTLS_ECP_DP_SECP192K1, /*!< Domain parameters for 192-bit "Koblitz" curve. */ + MBEDTLS_ECP_DP_SECP224K1, /*!< Domain parameters for 224-bit "Koblitz" curve. */ + MBEDTLS_ECP_DP_SECP256K1, /*!< Domain parameters for 256-bit "Koblitz" curve. */ + MBEDTLS_ECP_DP_CURVE448, /*!< Domain parameters for Curve448. */ +} mbedtls_ecp_group_id; + +/** + * The number of supported curves, plus one for #MBEDTLS_ECP_DP_NONE. + * + * \note Montgomery curves are currently excluded. + */ +#define MBEDTLS_ECP_DP_MAX 12 + +/** + * Curve information, for use by other modules. + */ +typedef struct mbedtls_ecp_curve_info +{ + mbedtls_ecp_group_id grp_id; /*!< An internal identifier. */ + uint16_t tls_id; /*!< The TLS NamedCurve identifier. */ + uint16_t bit_size; /*!< The curve size in bits. */ + const char *name; /*!< A human-friendly name. */ +} mbedtls_ecp_curve_info; + +/** + * \brief The ECP point structure, in Jacobian coordinates. + * + * \note All functions expect and return points satisfying + * the following condition: Z == 0 or + * Z == 1. Other values of \p Z are + * used only by internal functions. + * The point is zero, or "at infinity", if Z == 0. + * Otherwise, \p X and \p Y are its standard (affine) + * coordinates. + */ +typedef struct mbedtls_ecp_point +{ + mbedtls_mpi X; /*!< The X coordinate of the ECP point. */ + mbedtls_mpi Y; /*!< The Y coordinate of the ECP point. */ + mbedtls_mpi Z; /*!< The Z coordinate of the ECP point. */ +} +mbedtls_ecp_point; + +/* Determine the minimum safe value of MBEDTLS_ECP_MAX_BITS. */ +#if !defined(MBEDTLS_ECP_C) +#define MBEDTLS_ECP_MAX_BITS_MIN 0 +/* Note: the curves must be listed in DECREASING size! */ +#elif defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 521 +#elif defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 512 +#elif defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 448 +#elif defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 384 +#elif defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 384 +#elif defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 256 +#elif defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 256 +#elif defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 256 +#elif defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 255 +#elif defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 225 // n is slightly above 2^224 +#elif defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 224 +#elif defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 192 +#elif defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS_MIN 192 +#else +#error "MBEDTLS_ECP_C enabled, but no curve?" +#endif + +#if !defined(MBEDTLS_ECP_ALT) +/* + * default mbed TLS elliptic curve arithmetic implementation + * + * (in case MBEDTLS_ECP_ALT is defined then the developer has to provide an + * alternative implementation for the whole module and it will replace this + * one.) + */ + +/** + * \brief The ECP group structure. + * + * We consider two types of curve equations: + *
  • Short Weierstrass: y^2 = x^3 + A x + B mod P + * (SEC1 + RFC-4492)
    • + *
  • Montgomery: y^2 = x^3 + A x^2 + x mod P (Curve25519, + * Curve448)
+ * In both cases, the generator (\p G) for a prime-order subgroup is fixed. + * + * For Short Weierstrass, this subgroup is the whole curve, and its + * cardinality is denoted by \p N. Our code requires that \p N is an + * odd prime as mbedtls_ecp_mul() requires an odd number, and + * mbedtls_ecdsa_sign() requires that it is prime for blinding purposes. + * + * For Montgomery curves, we do not store \p A, but (A + 2) / 4, + * which is the quantity used in the formulas. Additionally, \p nbits is + * not the size of \p N but the required size for private keys. + * + * If \p modp is NULL, reduction modulo \p P is done using a generic algorithm. + * Otherwise, \p modp must point to a function that takes an \p mbedtls_mpi in the + * range of 0..2^(2*pbits)-1, and transforms it in-place to an integer + * which is congruent mod \p P to the given MPI, and is close enough to \p pbits + * in size, so that it may be efficiently brought in the 0..P-1 range by a few + * additions or subtractions. Therefore, it is only an approximative modular + * reduction. It must return 0 on success and non-zero on failure. + * + * \note Alternative implementations must keep the group IDs distinct. If + * two group structures have the same ID, then they must be + * identical. + * + */ +typedef struct mbedtls_ecp_group +{ + mbedtls_ecp_group_id id; /*!< An internal group identifier. */ + mbedtls_mpi P; /*!< The prime modulus of the base field. */ + mbedtls_mpi A; /*!< For Short Weierstrass: \p A in the equation. For + Montgomery curves: (A + 2) / 4. */ + mbedtls_mpi B; /*!< For Short Weierstrass: \p B in the equation. + For Montgomery curves: unused. */ + mbedtls_ecp_point G; /*!< The generator of the subgroup used. */ + mbedtls_mpi N; /*!< The order of \p G. */ + size_t pbits; /*!< The number of bits in \p P.*/ + size_t nbits; /*!< For Short Weierstrass: The number of bits in \p P. + For Montgomery curves: the number of bits in the + private keys. */ + unsigned int h; /*!< \internal 1 if the constants are static. */ + int (*modp)(mbedtls_mpi *); /*!< The function for fast pseudo-reduction + mod \p P (see above).*/ + int (*t_pre)(mbedtls_ecp_point *, void *); /*!< Unused. */ + int (*t_post)(mbedtls_ecp_point *, void *); /*!< Unused. */ + void *t_data; /*!< Unused. */ + mbedtls_ecp_point *T; /*!< Pre-computed points for ecp_mul_comb(). */ + size_t T_size; /*!< The number of pre-computed points. */ +} +mbedtls_ecp_group; + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in config.h, or define them using the compiler command line. + * \{ + */ + +#if defined(MBEDTLS_ECP_MAX_BITS) + +#if MBEDTLS_ECP_MAX_BITS < MBEDTLS_ECP_MAX_BITS_MIN +#error "MBEDTLS_ECP_MAX_BITS is smaller than the largest supported curve" +#endif + +#else +/** + * The maximum size of the groups, that is, of \c N and \c P. + */ +#define MBEDTLS_ECP_MAX_BITS 521 /**< The maximum size of groups, in bits. */ +#endif + +#define MBEDTLS_ECP_MAX_BYTES ( ( MBEDTLS_ECP_MAX_BITS + 7 ) / 8 ) +#define MBEDTLS_ECP_MAX_PT_LEN ( 2 * MBEDTLS_ECP_MAX_BYTES + 1 ) + +#if !defined(MBEDTLS_ECP_WINDOW_SIZE) +/* + * Maximum "window" size used for point multiplication. + * Default: 6. + * Minimum value: 2. Maximum value: 7. + * + * Result is an array of at most ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + * points used for point multiplication. This value is directly tied to EC + * peak memory usage, so decreasing it by one should roughly cut memory usage + * by two (if large curves are in use). + * + * Reduction in size may reduce speed, but larger curves are impacted first. + * Sample performances (in ECDHE handshakes/s, with FIXED_POINT_OPTIM = 1): + * w-size: 6 5 4 3 2 + * 521 145 141 135 120 97 + * 384 214 209 198 177 146 + * 256 320 320 303 262 226 + * 224 475 475 453 398 342 + * 192 640 640 633 587 476 + */ +#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< The maximum window size used. */ +#endif /* MBEDTLS_ECP_WINDOW_SIZE */ + +#if !defined(MBEDTLS_ECP_FIXED_POINT_OPTIM) +/* + * Trade memory for speed on fixed-point multiplication. + * + * This speeds up repeated multiplication of the generator (that is, the + * multiplication in ECDSA signatures, and half of the multiplications in + * ECDSA verification and ECDHE) by a factor roughly 3 to 4. + * + * The cost is increasing EC peak memory usage by a factor roughly 2. + * + * Change this value to 0 to reduce peak memory usage. + */ +#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up. */ +#endif /* MBEDTLS_ECP_FIXED_POINT_OPTIM */ + +/* \} name SECTION: Module settings */ + +#else /* MBEDTLS_ECP_ALT */ +#include "ecp_alt.h" +#endif /* MBEDTLS_ECP_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + +/** + * \brief Internal restart context for multiplication + * + * \note Opaque struct + */ +typedef struct mbedtls_ecp_restart_mul mbedtls_ecp_restart_mul_ctx; + +/** + * \brief Internal restart context for ecp_muladd() + * + * \note Opaque struct + */ +typedef struct mbedtls_ecp_restart_muladd mbedtls_ecp_restart_muladd_ctx; + +/** + * \brief General context for resuming ECC operations + */ +typedef struct +{ + unsigned ops_done; /*!< current ops count */ + unsigned depth; /*!< call depth (0 = top-level) */ + mbedtls_ecp_restart_mul_ctx *rsm; /*!< ecp_mul_comb() sub-context */ + mbedtls_ecp_restart_muladd_ctx *ma; /*!< ecp_muladd() sub-context */ +} mbedtls_ecp_restart_ctx; + +/* + * Operation counts for restartable functions + */ +#define MBEDTLS_ECP_OPS_CHK 3 /*!< basic ops count for ecp_check_pubkey() */ +#define MBEDTLS_ECP_OPS_DBL 8 /*!< basic ops count for ecp_double_jac() */ +#define MBEDTLS_ECP_OPS_ADD 11 /*!< basic ops count for see ecp_add_mixed() */ +#define MBEDTLS_ECP_OPS_INV 120 /*!< empirical equivalent for mpi_mod_inv() */ + +/** + * \brief Internal; for restartable functions in other modules. + * Check and update basic ops budget. + * + * \param grp Group structure + * \param rs_ctx Restart context + * \param ops Number of basic ops to do + * + * \return \c 0 if doing \p ops basic ops is still allowed, + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS otherwise. + */ +int mbedtls_ecp_check_budget( const mbedtls_ecp_group *grp, + mbedtls_ecp_restart_ctx *rs_ctx, + unsigned ops ); + +/* Utility macro for checking and updating ops budget */ +#define MBEDTLS_ECP_BUDGET( ops ) \ + MBEDTLS_MPI_CHK( mbedtls_ecp_check_budget( grp, rs_ctx, \ + (unsigned) (ops) ) ); + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +#define MBEDTLS_ECP_BUDGET( ops ) /* no-op; for compatibility */ + +/* We want to declare restartable versions of existing functions anyway */ +typedef void mbedtls_ecp_restart_ctx; + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief The ECP key-pair structure. + * + * A generic key-pair that may be used for ECDSA and fixed ECDH, for example. + * + * \note Members are deliberately in the same order as in the + * ::mbedtls_ecdsa_context structure. + */ +typedef struct mbedtls_ecp_keypair +{ + mbedtls_ecp_group grp; /*!< Elliptic curve and base point */ + mbedtls_mpi d; /*!< our secret value */ + mbedtls_ecp_point Q; /*!< our public value */ +} +mbedtls_ecp_keypair; + +/* + * Point formats, from RFC 4492's enum ECPointFormat + */ +#define MBEDTLS_ECP_PF_UNCOMPRESSED 0 /**< Uncompressed point format. */ +#define MBEDTLS_ECP_PF_COMPRESSED 1 /**< Compressed point format. */ + +/* + * Some other constants from RFC 4492 + */ +#define MBEDTLS_ECP_TLS_NAMED_CURVE 3 /**< The named_curve of ECCurveType. */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Set the maximum number of basic operations done in a row. + * + * If more operations are needed to complete a computation, + * #MBEDTLS_ERR_ECP_IN_PROGRESS will be returned by the + * function performing the computation. It is then the + * caller's responsibility to either call again with the same + * parameters until it returns 0 or an error code; or to free + * the restart context if the operation is to be aborted. + * + * It is strictly required that all input parameters and the + * restart context be the same on successive calls for the + * same operation, but output parameters need not be the + * same; they must not be used until the function finally + * returns 0. + * + * This only applies to functions whose documentation + * mentions they may return #MBEDTLS_ERR_ECP_IN_PROGRESS (or + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS for functions in the + * SSL module). For functions that accept a "restart context" + * argument, passing NULL disables restart and makes the + * function equivalent to the function with the same name + * with \c _restartable removed. For functions in the ECDH + * module, restart is disabled unless the function accepts + * an "ECDH context" argument and + * mbedtls_ecdh_enable_restart() was previously called on + * that context. For function in the SSL module, restart is + * only enabled for specific sides and key exchanges + * (currently only for clients and ECDHE-ECDSA). + * + * \param max_ops Maximum number of basic operations done in a row. + * Default: 0 (unlimited). + * Lower (non-zero) values mean ECC functions will block for + * a lesser maximum amount of time. + * + * \note A "basic operation" is defined as a rough equivalent of a + * multiplication in GF(p) for the NIST P-256 curve. + * As an indication, with default settings, a scalar + * multiplication (full run of \c mbedtls_ecp_mul()) is: + * - about 3300 basic operations for P-256 + * - about 9400 basic operations for P-384 + * + * \note Very low values are not always respected: sometimes + * functions need to block for a minimum number of + * operations, and will do so even if max_ops is set to a + * lower value. That minimum depends on the curve size, and + * can be made lower by decreasing the value of + * \c MBEDTLS_ECP_WINDOW_SIZE. As an indication, here is the + * lowest effective value for various curves and values of + * that parameter (w for short): + * w=6 w=5 w=4 w=3 w=2 + * P-256 208 208 160 136 124 + * P-384 682 416 320 272 248 + * P-521 1364 832 640 544 496 + * + * \note This setting is currently ignored by Curve25519. + */ +void mbedtls_ecp_set_max_ops( unsigned max_ops ); + +/** + * \brief Check if restart is enabled (max_ops != 0) + * + * \return \c 0 if \c max_ops == 0 (restart disabled) + * \return \c 1 otherwise (restart enabled) + */ +int mbedtls_ecp_restart_is_enabled( void ); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief This function retrieves the information defined in + * mbedtls_ecp_curve_info() for all supported curves in order + * of preference. + * + * \return A statically allocated array. The last entry is 0. + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list( void ); + +/** + * \brief This function retrieves the list of internal group + * identifiers of all supported curves in the order of + * preference. + * + * \return A statically allocated array, + * terminated with MBEDTLS_ECP_DP_NONE. + */ +const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list( void ); + +/** + * \brief This function retrieves curve information from an internal + * group identifier. + * + * \param grp_id An \c MBEDTLS_ECP_DP_XXX value. + * + * \return The associated curve information on success. + * \return NULL on failure. + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id( mbedtls_ecp_group_id grp_id ); + +/** + * \brief This function retrieves curve information from a TLS + * NamedCurve value. + * + * \param tls_id An \c MBEDTLS_ECP_DP_XXX value. + * + * \return The associated curve information on success. + * \return NULL on failure. + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id( uint16_t tls_id ); + +/** + * \brief This function retrieves curve information from a + * human-readable name. + * + * \param name The human-readable name. + * + * \return The associated curve information on success. + * \return NULL on failure. + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name( const char *name ); + +/** + * \brief This function initializes a point as zero. + * + * \param pt The point to initialize. + */ +void mbedtls_ecp_point_init( mbedtls_ecp_point *pt ); + +/** + * \brief This function initializes an ECP group context + * without loading any domain parameters. + * + * \note After this function is called, domain parameters + * for various ECP groups can be loaded through the + * mbedtls_ecp_group_load() or mbedtls_ecp_tls_read_group() + * functions. + */ +void mbedtls_ecp_group_init( mbedtls_ecp_group *grp ); + +/** + * \brief This function initializes a key pair as an invalid one. + * + * \param key The key pair to initialize. + */ +void mbedtls_ecp_keypair_init( mbedtls_ecp_keypair *key ); + +/** + * \brief This function frees the components of a point. + * + * \param pt The point to free. + */ +void mbedtls_ecp_point_free( mbedtls_ecp_point *pt ); + +/** + * \brief This function frees the components of an ECP group. + * + * \param grp The group to free. This may be \c NULL, in which + * case this function returns immediately. If it is not + * \c NULL, it must point to an initialized ECP group. + */ +void mbedtls_ecp_group_free( mbedtls_ecp_group *grp ); + +/** + * \brief This function frees the components of a key pair. + * + * \param key The key pair to free. This may be \c NULL, in which + * case this function returns immediately. If it is not + * \c NULL, it must point to an initialized ECP key pair. + */ +void mbedtls_ecp_keypair_free( mbedtls_ecp_keypair *key ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Initialize a restart context. + * + * \param ctx The restart context to initialize. This must + * not be \c NULL. + */ +void mbedtls_ecp_restart_init( mbedtls_ecp_restart_ctx *ctx ); + +/** + * \brief Free the components of a restart context. + * + * \param ctx The restart context to free. This may be \c NULL, in which + * case this function returns immediately. If it is not + * \c NULL, it must point to an initialized restart context. + */ +void mbedtls_ecp_restart_free( mbedtls_ecp_restart_ctx *ctx ); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief This function copies the contents of point \p Q into + * point \p P. + * + * \param P The destination point. This must be initialized. + * \param Q The source point. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code for other kinds of failure. + */ +int mbedtls_ecp_copy( mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ); + +/** + * \brief This function copies the contents of group \p src into + * group \p dst. + * + * \param dst The destination group. This must be initialized. + * \param src The source group. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_group_copy( mbedtls_ecp_group *dst, + const mbedtls_ecp_group *src ); + +/** + * \brief This function sets a point to the point at infinity. + * + * \param pt The point to set. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_set_zero( mbedtls_ecp_point *pt ); + +/** + * \brief This function checks if a point is the point at infinity. + * + * \param pt The point to test. This must be initialized. + * + * \return \c 1 if the point is zero. + * \return \c 0 if the point is non-zero. + * \return A negative error code on failure. + */ +int mbedtls_ecp_is_zero( mbedtls_ecp_point *pt ); + +/** + * \brief This function compares two points. + * + * \note This assumes that the points are normalized. Otherwise, + * they may compare as "not equal" even if they are. + * + * \param P The first point to compare. This must be initialized. + * \param Q The second point to compare. This must be initialized. + * + * \return \c 0 if the points are equal. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the points are not equal. + */ +int mbedtls_ecp_point_cmp( const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q ); + +/** + * \brief This function imports a non-zero point from two ASCII + * strings. + * + * \param P The destination point. This must be initialized. + * \param radix The numeric base of the input. + * \param x The first affine coordinate, as a null-terminated string. + * \param y The second affine coordinate, as a null-terminated string. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_MPI_XXX error code on failure. + */ +int mbedtls_ecp_point_read_string( mbedtls_ecp_point *P, int radix, + const char *x, const char *y ); + +/** + * \brief This function exports a point into unsigned binary data. + * + * \param grp The group to which the point should belong. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param P The point to export. This must be initialized. + * \param format The point format. This must be either + * #MBEDTLS_ECP_PF_COMPRESSED or #MBEDTLS_ECP_PF_UNCOMPRESSED. + * \param olen The address at which to store the length of + * the output in Bytes. This must not be \c NULL. + * \param buf The output buffer. This must be a writable buffer + * of length \p buflen Bytes. + * \param buflen The length of the output buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the output buffer + * is too small to hold the point. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_point_write_binary( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *P, + int format, size_t *olen, + unsigned char *buf, size_t buflen ); + +/** + * \brief This function imports a point from unsigned binary data. + * + * \note This function does not check that the point actually + * belongs to the given group, see mbedtls_ecp_check_pubkey() + * for that. + * + * \param grp The group to which the point should belong. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param P The destination context to import the point to. + * This must be initialized. + * \param buf The input buffer. This must be a readable buffer + * of length \p ilen Bytes. + * \param ilen The length of the input buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the input is invalid. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the point format + * is not implemented. + */ +int mbedtls_ecp_point_read_binary( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *P, + const unsigned char *buf, size_t ilen ); + +/** + * \brief This function imports a point from a TLS ECPoint record. + * + * \note On function return, \p *buf is updated to point immediately + * after the ECPoint record. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param pt The destination point. + * \param buf The address of the pointer to the start of the input buffer. + * \param len The length of the buffer. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_MPI_XXX error code on initialization + * failure. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. + */ +int mbedtls_ecp_tls_read_point( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char **buf, size_t len ); + +/** + * \brief This function exports a point as a TLS ECPoint record + * defined in RFC 4492, Section 5.4. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param pt The point to be exported. This must be initialized. + * \param format The point format to use. This must be either + * #MBEDTLS_ECP_PF_COMPRESSED or #MBEDTLS_ECP_PF_UNCOMPRESSED. + * \param olen The address at which to store the length in Bytes + * of the data written. + * \param buf The target buffer. This must be a writable buffer of + * length \p blen Bytes. + * \param blen The length of the target buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the input is invalid. + * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the target buffer + * is too small to hold the exported point. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *pt, + int format, size_t *olen, + unsigned char *buf, size_t blen ); + +/** + * \brief This function sets up an ECP group context + * from a standardized set of domain parameters. + * + * \note The index should be a value of the NamedCurve enum, + * as defined in RFC-4492: Elliptic Curve Cryptography + * (ECC) Cipher Suites for Transport Layer Security (TLS), + * usually in the form of an \c MBEDTLS_ECP_DP_XXX macro. + * + * \param grp The group context to setup. This must be initialized. + * \param id The identifier of the domain parameter set to load. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p id doesn't + * correspond to a known group. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_group_load( mbedtls_ecp_group *grp, mbedtls_ecp_group_id id ); + +/** + * \brief This function sets up an ECP group context from a TLS + * ECParameters record as defined in RFC 4492, Section 5.4. + * + * \note The read pointer \p buf is updated to point right after + * the ECParameters record on exit. + * + * \param grp The group context to setup. This must be initialized. + * \param buf The address of the pointer to the start of the input buffer. + * \param len The length of the input buffer \c *buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the group is not + * recognized. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp, + const unsigned char **buf, size_t len ); + +/** + * \brief This function extracts an elliptic curve group ID from a + * TLS ECParameters record as defined in RFC 4492, Section 5.4. + * + * \note The read pointer \p buf is updated to point right after + * the ECParameters record on exit. + * + * \param grp The address at which to store the group id. + * This must not be \c NULL. + * \param buf The address of the pointer to the start of the input buffer. + * \param len The length of the input buffer \c *buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the group is not + * recognized. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_tls_read_group_id( mbedtls_ecp_group_id *grp, + const unsigned char **buf, + size_t len ); +/** + * \brief This function exports an elliptic curve as a TLS + * ECParameters record as defined in RFC 4492, Section 5.4. + * + * \param grp The ECP group to be exported. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param olen The address at which to store the number of Bytes written. + * This must not be \c NULL. + * \param buf The buffer to write to. This must be a writable buffer + * of length \p blen Bytes. + * \param blen The length of the output buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the output + * buffer is too small to hold the exported group. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp, + size_t *olen, + unsigned char *buf, size_t blen ); + +/** + * \brief This function performs a scalar multiplication of a point + * by an integer: \p R = \p m * \p P. + * + * It is not thread-safe to use same group in multiple threads. + * + * \note To prevent timing attacks, this function + * executes the exact same sequence of base-field + * operations for any valid \p m. It avoids any if-branch or + * array index depending on the value of \p m. + * + * \note If \p f_rng is not NULL, it is used to randomize + * intermediate results to prevent potential timing attacks + * targeting these results. We recommend always providing + * a non-NULL \p f_rng. The overhead is negligible. + * Note: unless #MBEDTLS_ECP_NO_INTERNAL_RNG is defined, when + * \p f_rng is NULL, an internal RNG (seeded from the value + * of \p m) will be used instead. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param R The point in which to store the result of the calculation. + * This must be initialized. + * \param m The integer by which to multiply. This must be initialized. + * \param P The point to multiply. This must be initialized. + * \param f_rng The RNG function. This may be \c NULL if randomization + * of intermediate results isn't desired (discouraged). + * \param p_rng The RNG context to be passed to \p p_rng. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m is not a valid private + * key, or \p P is not a valid public key. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_mul( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); + +/** + * \brief This function performs multiplication of a point by + * an integer: \p R = \p m * \p P in a restartable way. + * + * \see mbedtls_ecp_mul() + * + * \note This function does the same as \c mbedtls_ecp_mul(), but + * it can return early and restart according to the limit set + * with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param R The point in which to store the result of the calculation. + * This must be initialized. + * \param m The integer by which to multiply. This must be initialized. + * \param P The point to multiply. This must be initialized. + * \param f_rng The RNG function. This may be \c NULL if randomization + * of intermediate results isn't desired (discouraged). + * \param p_rng The RNG context to be passed to \p p_rng. + * \param rs_ctx The restart context (NULL disables restart). + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m is not a valid private + * key, or \p P is not a valid public key. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_mul_restartable( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ); + +/** + * \brief This function performs multiplication and addition of two + * points by integers: \p R = \p m * \p P + \p n * \p Q + * + * It is not thread-safe to use same group in multiple threads. + * + * \note In contrast to mbedtls_ecp_mul(), this function does not + * guarantee a constant execution flow and timing. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param R The point in which to store the result of the calculation. + * This must be initialized. + * \param m The integer by which to multiply \p P. + * This must be initialized. + * \param P The point to multiply by \p m. This must be initialized. + * \param n The integer by which to multiply \p Q. + * This must be initialized. + * \param Q The point to be multiplied by \p n. + * This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m or \p n are not + * valid private keys, or \p P or \p Q are not valid public + * keys. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_muladd( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q ); + +/** + * \brief This function performs multiplication and addition of two + * points by integers: \p R = \p m * \p P + \p n * \p Q in a + * restartable way. + * + * \see \c mbedtls_ecp_muladd() + * + * \note This function works the same as \c mbedtls_ecp_muladd(), + * but it can return early and restart according to the limit + * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param R The point in which to store the result of the calculation. + * This must be initialized. + * \param m The integer by which to multiply \p P. + * This must be initialized. + * \param P The point to multiply by \p m. This must be initialized. + * \param n The integer by which to multiply \p Q. + * This must be initialized. + * \param Q The point to be multiplied by \p n. + * This must be initialized. + * \param rs_ctx The restart context (NULL disables restart). + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m or \p n are not + * valid private keys, or \p P or \p Q are not valid public + * keys. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_muladd_restartable( + mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q, + mbedtls_ecp_restart_ctx *rs_ctx ); + +/** + * \brief This function checks that a point is a valid public key + * on this curve. + * + * It only checks that the point is non-zero, has + * valid coordinates and lies on the curve. It does not verify + * that it is indeed a multiple of \p G. This additional + * check is computationally more expensive, is not required + * by standards, and should not be necessary if the group + * used has a small cofactor. In particular, it is useless for + * the NIST groups which all have a cofactor of 1. + * + * \note This function uses bare components rather than an + * ::mbedtls_ecp_keypair structure, to ease use with other + * structures, such as ::mbedtls_ecdh_context or + * ::mbedtls_ecdsa_context. + * + * \param grp The ECP group the point should belong to. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param pt The point to check. This must be initialized. + * + * \return \c 0 if the point is a valid public key. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if the point is not + * a valid public key for the given curve. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *pt ); + +/** + * \brief This function checks that an \p mbedtls_mpi is a + * valid private key for this curve. + * + * \note This function uses bare components rather than an + * ::mbedtls_ecp_keypair structure to ease use with other + * structures, such as ::mbedtls_ecdh_context or + * ::mbedtls_ecdsa_context. + * + * \param grp The ECP group the private key should belong to. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param d The integer to check. This must be initialized. + * + * \return \c 0 if the point is a valid private key. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if the point is not a valid + * private key for the given curve. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_check_privkey( const mbedtls_ecp_group *grp, + const mbedtls_mpi *d ); + +/** + * \brief This function generates a private key. + * + * \param grp The ECP group to generate a private key for. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param d The destination MPI (secret part). This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code + * on failure. + */ +int mbedtls_ecp_gen_privkey( const mbedtls_ecp_group *grp, + mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function generates a keypair with a configurable base + * point. + * + * \note This function uses bare components rather than an + * ::mbedtls_ecp_keypair structure to ease use with other + * structures, such as ::mbedtls_ecdh_context or + * ::mbedtls_ecdsa_context. + * + * \param grp The ECP group to generate a key pair for. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param G The base point to use. This must be initialized + * and belong to \p grp. It replaces the default base + * point \c grp->G used by mbedtls_ecp_gen_keypair(). + * \param d The destination MPI (secret part). + * This must be initialized. + * \param Q The destination point (public part). + * This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code + * on failure. + */ +int mbedtls_ecp_gen_keypair_base( mbedtls_ecp_group *grp, + const mbedtls_ecp_point *G, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function generates an ECP keypair. + * + * \note This function uses bare components rather than an + * ::mbedtls_ecp_keypair structure to ease use with other + * structures, such as ::mbedtls_ecdh_context or + * ::mbedtls_ecdsa_context. + * + * \param grp The ECP group to generate a key pair for. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param d The destination MPI (secret part). + * This must be initialized. + * \param Q The destination point (public part). + * This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code + * on failure. + */ +int mbedtls_ecp_gen_keypair( mbedtls_ecp_group *grp, mbedtls_mpi *d, + mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function generates an ECP key. + * + * \param grp_id The ECP group identifier. + * \param key The destination key. This must be initialized. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code + * on failure. + */ +int mbedtls_ecp_gen_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief This function checks that the keypair objects + * \p pub and \p prv have the same group and the + * same public point, and that the private key in + * \p prv is consistent with the public key. + * + * \param pub The keypair structure holding the public key. This + * must be initialized. If it contains a private key, that + * part is ignored. + * \param prv The keypair structure holding the full keypair. + * This must be initialized. + * + * \return \c 0 on success, meaning that the keys are valid and match. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the keys are invalid or do not match. + * \return An \c MBEDTLS_ERR_ECP_XXX or an \c MBEDTLS_ERR_MPI_XXX + * error code on calculation failure. + */ +int mbedtls_ecp_check_pub_priv( const mbedtls_ecp_keypair *pub, + const mbedtls_ecp_keypair *prv ); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The ECP checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_ecp_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* ecp.h */ diff --git a/src/common/mbedtls/include/mbedtls/ecp_internal.h b/src/common/mbedtls/include/mbedtls/ecp_internal.h new file mode 100644 index 0000000000..c6682babba --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/ecp_internal.h @@ -0,0 +1,309 @@ +/** + * \file ecp_internal.h + * + * \brief Function declarations for alternative implementation of elliptic curve + * point arithmetic. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +/* + * References: + * + * [1] BERNSTEIN, Daniel J. Curve25519: new Diffie-Hellman speed records. + * + * + * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis + * for elliptic curve cryptosystems. In : Cryptographic Hardware and + * Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302. + * + * + * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to + * render ECC resistant against Side Channel Attacks. IACR Cryptology + * ePrint Archive, 2004, vol. 2004, p. 342. + * + * + * [4] Certicom Research. SEC 2: Recommended Elliptic Curve Domain Parameters. + * + * + * [5] HANKERSON, Darrel, MENEZES, Alfred J., VANSTONE, Scott. Guide to Elliptic + * Curve Cryptography. + * + * [6] Digital Signature Standard (DSS), FIPS 186-4. + * + * + * [7] Elliptic Curve Cryptography (ECC) Cipher Suites for Transport Layer + * Security (TLS), RFC 4492. + * + * + * [8] + * + * [9] COHEN, Henri. A Course in Computational Algebraic Number Theory. + * Springer Science & Business Media, 1 Aug 2000 + */ + +#ifndef MBEDTLS_ECP_INTERNAL_H +#define MBEDTLS_ECP_INTERNAL_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + +/** + * \brief Indicate if the Elliptic Curve Point module extension can + * handle the group. + * + * \param grp The pointer to the elliptic curve group that will be the + * basis of the cryptographic computations. + * + * \return Non-zero if successful. + */ +unsigned char mbedtls_internal_ecp_grp_capable( const mbedtls_ecp_group *grp ); + +/** + * \brief Initialise the Elliptic Curve Point module extension. + * + * If mbedtls_internal_ecp_grp_capable returns true for a + * group, this function has to be able to initialise the + * module for it. + * + * This module can be a driver to a crypto hardware + * accelerator, for which this could be an initialise function. + * + * \param grp The pointer to the group the module needs to be + * initialised for. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ); + +/** + * \brief Frees and deallocates the Elliptic Curve Point module + * extension. + * + * \param grp The pointer to the group the module was initialised for. + */ +void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ); + +#if defined(ECP_SHORTWEIERSTRASS) + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) +/** + * \brief Randomize jacobian coordinates: + * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l. + * + * \param grp Pointer to the group representing the curve. + * + * \param pt The point on the curve to be randomised, given with Jacobian + * coordinates. + * + * \param f_rng A function pointer to the random number generator. + * + * \param p_rng A pointer to the random number generator state. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_randomize_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) +/** + * \brief Addition: R = P + Q, mixed affine-Jacobian coordinates. + * + * The coordinates of Q must be normalized (= affine), + * but those of P don't need to. R is not normalized. + * + * This function is used only as a subrutine of + * ecp_mul_comb(). + * + * Special cases: (1) P or Q is zero, (2) R is zero, + * (3) P == Q. + * None of these cases can happen as intermediate step in + * ecp_mul_comb(): + * - at each step, P, Q and R are multiples of the base + * point, the factor being less than its order, so none of + * them is zero; + * - Q is an odd multiple of the base point, P an even + * multiple, due to the choice of precomputed points in the + * modified comb method. + * So branches for these cases do not leak secret information. + * + * We accept Q->Z being unset (saving memory in tables) as + * meaning 1. + * + * Cost in field operations if done by [5] 3.22: + * 1A := 8M + 3S + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result. + * + * \param P Pointer to the first summand, given with Jacobian + * coordinates + * + * \param Q Pointer to the second summand, given with affine + * coordinates. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_add_mixed( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q ); +#endif + +/** + * \brief Point doubling R = 2 P, Jacobian coordinates. + * + * Cost: 1D := 3M + 4S (A == 0) + * 4M + 4S (A == -3) + * 3M + 6S + 1a otherwise + * when the implementation is based on the "dbl-1998-cmo-2" + * doubling formulas in [8] and standard optimizations are + * applied when curve parameter A is one of { 0, -3 }. + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result. + * + * \param P Pointer to the point that has to be doubled, given with + * Jacobian coordinates. + * + * \return 0 if successful. + */ +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) +int mbedtls_internal_ecp_double_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, const mbedtls_ecp_point *P ); +#endif + +/** + * \brief Normalize jacobian coordinates of an array of (pointers to) + * points. + * + * Using Montgomery's trick to perform only one inversion mod P + * the cost is: + * 1N(t) := 1I + (6t - 3)M + 1S + * (See for example Algorithm 10.3.4. in [9]) + * + * This function is used only as a subrutine of + * ecp_mul_comb(). + * + * Warning: fails (returning an error) if one of the points is + * zero! + * This should never happen, see choice of w in ecp_mul_comb(). + * + * \param grp Pointer to the group representing the curve. + * + * \param T Array of pointers to the points to normalise. + * + * \param t_len Number of elements in the array. + * + * \return 0 if successful, + * an error if one of the points is zero. + */ +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) +int mbedtls_internal_ecp_normalize_jac_many( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *T[], size_t t_len ); +#endif + +/** + * \brief Normalize jacobian coordinates so that Z == 0 || Z == 1. + * + * Cost in field operations if done by [5] 3.2.1: + * 1N := 1I + 3M + 1S + * + * \param grp Pointer to the group representing the curve. + * + * \param pt pointer to the point to be normalised. This is an + * input/output parameter. + * + * \return 0 if successful. + */ +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) +int mbedtls_internal_ecp_normalize_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt ); +#endif + +#endif /* ECP_SHORTWEIERSTRASS */ + +#if defined(ECP_MONTGOMERY) + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) +int mbedtls_internal_ecp_double_add_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, mbedtls_ecp_point *S, const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d ); +#endif + +/** + * \brief Randomize projective x/z coordinates: + * (X, Z) -> (l X, l Z) for random l + * + * \param grp pointer to the group representing the curve + * + * \param P the point on the curve to be randomised given with + * projective coordinates. This is an input/output parameter. + * + * \param f_rng a function pointer to the random number generator + * + * \param p_rng a pointer to the random number generator state + * + * \return 0 if successful + */ +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) +int mbedtls_internal_ecp_randomize_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *P, int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); +#endif + +/** + * \brief Normalize Montgomery x/z coordinates: X = X/Z, Z = 1. + * + * \param grp pointer to the group representing the curve + * + * \param P pointer to the point to be normalised. This is an + * input/output parameter. + * + * \return 0 if successful + */ +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) +int mbedtls_internal_ecp_normalize_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *P ); +#endif + +#endif /* ECP_MONTGOMERY */ + +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#endif /* ecp_internal.h */ + diff --git a/src/common/mbedtls/include/mbedtls/entropy.h b/src/common/mbedtls/include/mbedtls/entropy.h new file mode 100644 index 0000000000..f64d9086f8 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/entropy.h @@ -0,0 +1,301 @@ +/** + * \file entropy.h + * + * \brief Entropy accumulator implementation + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_ENTROPY_H +#define MBEDTLS_ENTROPY_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include + +#if defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) +#include "sha512.h" +#define MBEDTLS_ENTROPY_SHA512_ACCUMULATOR +#else +#if defined(MBEDTLS_SHA256_C) +#define MBEDTLS_ENTROPY_SHA256_ACCUMULATOR +#include "sha256.h" +#endif +#endif + +#if defined(MBEDTLS_THREADING_C) +#include "threading.h" +#endif + +#if defined(MBEDTLS_HAVEGE_C) +#include "havege.h" +#endif + +#define MBEDTLS_ERR_ENTROPY_SOURCE_FAILED -0x003C /**< Critical entropy source failure. */ +#define MBEDTLS_ERR_ENTROPY_MAX_SOURCES -0x003E /**< No more sources can be added. */ +#define MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED -0x0040 /**< No sources have been added to poll. */ +#define MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE -0x003D /**< No strong sources have been added to poll. */ +#define MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR -0x003F /**< Read/write error in file. */ + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in config.h or define them on the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_ENTROPY_MAX_SOURCES) +#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ +#endif + +#if !defined(MBEDTLS_ENTROPY_MAX_GATHER) +#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ +#endif + +/* \} name SECTION: Module settings */ + +#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR) +#define MBEDTLS_ENTROPY_BLOCK_SIZE 64 /**< Block size of entropy accumulator (SHA-512) */ +#else +#define MBEDTLS_ENTROPY_BLOCK_SIZE 32 /**< Block size of entropy accumulator (SHA-256) */ +#endif + +#define MBEDTLS_ENTROPY_MAX_SEED_SIZE 1024 /**< Maximum size of seed we read from seed file */ +#define MBEDTLS_ENTROPY_SOURCE_MANUAL MBEDTLS_ENTROPY_MAX_SOURCES + +#define MBEDTLS_ENTROPY_SOURCE_STRONG 1 /**< Entropy source is strong */ +#define MBEDTLS_ENTROPY_SOURCE_WEAK 0 /**< Entropy source is weak */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Entropy poll callback pointer + * + * \param data Callback-specific data pointer + * \param output Data to fill + * \param len Maximum size to provide + * \param olen The actual amount of bytes put into the buffer (Can be 0) + * + * \return 0 if no critical failures occurred, + * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED otherwise + */ +typedef int (*mbedtls_entropy_f_source_ptr)(void *data, unsigned char *output, size_t len, + size_t *olen); + +/** + * \brief Entropy source state + */ +typedef struct mbedtls_entropy_source_state +{ + mbedtls_entropy_f_source_ptr f_source; /**< The entropy source callback */ + void * p_source; /**< The callback data pointer */ + size_t size; /**< Amount received in bytes */ + size_t threshold; /**< Minimum bytes required before release */ + int strong; /**< Is the source strong? */ +} +mbedtls_entropy_source_state; + +/** + * \brief Entropy context structure + */ +typedef struct mbedtls_entropy_context +{ + int accumulator_started; /* 0 after init. + * 1 after the first update. + * -1 after free. */ +#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR) + mbedtls_sha512_context accumulator; +#else + mbedtls_sha256_context accumulator; +#endif + int source_count; /* Number of entries used in source. */ + mbedtls_entropy_source_state source[MBEDTLS_ENTROPY_MAX_SOURCES]; +#if defined(MBEDTLS_HAVEGE_C) + mbedtls_havege_state havege_data; +#endif +#if defined(MBEDTLS_THREADING_C) + mbedtls_threading_mutex_t mutex; /*!< mutex */ +#endif +#if defined(MBEDTLS_ENTROPY_NV_SEED) + int initial_entropy_run; +#endif +} +mbedtls_entropy_context; + +/** + * \brief Initialize the context + * + * \param ctx Entropy context to initialize + */ +void mbedtls_entropy_init( mbedtls_entropy_context *ctx ); + +/** + * \brief Free the data in the context + * + * \param ctx Entropy context to free + */ +void mbedtls_entropy_free( mbedtls_entropy_context *ctx ); + +/** + * \brief Adds an entropy source to poll + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param ctx Entropy context + * \param f_source Entropy function + * \param p_source Function data + * \param threshold Minimum required from source before entropy is released + * ( with mbedtls_entropy_func() ) (in bytes) + * \param strong MBEDTLS_ENTROPY_SOURCE_STRONG or + * MBEDTLS_ENTROPY_SOURCE_WEAK. + * At least one strong source needs to be added. + * Weaker sources (such as the cycle counter) can be used as + * a complement. + * + * \return 0 if successful or MBEDTLS_ERR_ENTROPY_MAX_SOURCES + */ +int mbedtls_entropy_add_source( mbedtls_entropy_context *ctx, + mbedtls_entropy_f_source_ptr f_source, void *p_source, + size_t threshold, int strong ); + +/** + * \brief Trigger an extra gather poll for the accumulator + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param ctx Entropy context + * + * \return 0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED + */ +int mbedtls_entropy_gather( mbedtls_entropy_context *ctx ); + +/** + * \brief Retrieve entropy from the accumulator + * (Maximum length: MBEDTLS_ENTROPY_BLOCK_SIZE) + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param data Entropy context + * \param output Buffer to fill + * \param len Number of bytes desired, must be at most MBEDTLS_ENTROPY_BLOCK_SIZE + * + * \return 0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED + */ +int mbedtls_entropy_func( void *data, unsigned char *output, size_t len ); + +/** + * \brief Add data to the accumulator manually + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param ctx Entropy context + * \param data Data to add + * \param len Length of data + * + * \return 0 if successful + */ +int mbedtls_entropy_update_manual( mbedtls_entropy_context *ctx, + const unsigned char *data, size_t len ); + +#if defined(MBEDTLS_ENTROPY_NV_SEED) +/** + * \brief Trigger an update of the seed file in NV by using the + * current entropy pool. + * + * \param ctx Entropy context + * + * \return 0 if successful + */ +int mbedtls_entropy_update_nv_seed( mbedtls_entropy_context *ctx ); +#endif /* MBEDTLS_ENTROPY_NV_SEED */ + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Write a seed file + * + * \param ctx Entropy context + * \param path Name of the file + * + * \return 0 if successful, + * MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error, or + * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED + */ +int mbedtls_entropy_write_seed_file( mbedtls_entropy_context *ctx, const char *path ); + +/** + * \brief Read and update a seed file. Seed is added to this + * instance. No more than MBEDTLS_ENTROPY_MAX_SEED_SIZE bytes are + * read from the seed file. The rest is ignored. + * + * \param ctx Entropy context + * \param path Name of the file + * + * \return 0 if successful, + * MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error, + * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED + */ +int mbedtls_entropy_update_seed_file( mbedtls_entropy_context *ctx, const char *path ); +#endif /* MBEDTLS_FS_IO */ + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine + * + * This module self-test also calls the entropy self-test, + * mbedtls_entropy_source_self_test(); + * + * \return 0 if successful, or 1 if a test failed + */ +int mbedtls_entropy_self_test( int verbose ); + +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) +/** + * \brief Checkup routine + * + * Verifies the integrity of the hardware entropy source + * provided by the function 'mbedtls_hardware_poll()'. + * + * Note this is the only hardware entropy source that is known + * at link time, and other entropy sources configured + * dynamically at runtime by the function + * mbedtls_entropy_add_source() will not be tested. + * + * \return 0 if successful, or 1 if a test failed + */ +int mbedtls_entropy_source_self_test( int verbose ); +#endif /* MBEDTLS_ENTROPY_HARDWARE_ALT */ +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* entropy.h */ diff --git a/src/common/mbedtls/include/mbedtls/error.h b/src/common/mbedtls/include/mbedtls/error.h new file mode 100644 index 0000000000..7cae946641 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/error.h @@ -0,0 +1,140 @@ +/** + * \file error.h + * + * \brief Error to string translation + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_ERROR_H +#define MBEDTLS_ERROR_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include + +/** + * Error code layout. + * + * Currently we try to keep all error codes within the negative space of 16 + * bits signed integers to support all platforms (-0x0001 - -0x7FFF). In + * addition we'd like to give two layers of information on the error if + * possible. + * + * For that purpose the error codes are segmented in the following manner: + * + * 16 bit error code bit-segmentation + * + * 1 bit - Unused (sign bit) + * 3 bits - High level module ID + * 5 bits - Module-dependent error code + * 7 bits - Low level module errors + * + * For historical reasons, low-level error codes are divided in even and odd, + * even codes were assigned first, and -1 is reserved for other errors. + * + * Low-level module errors (0x0002-0x007E, 0x0003-0x007F) + * + * Module Nr Codes assigned + * MPI 7 0x0002-0x0010 + * GCM 3 0x0012-0x0014 0x0013-0x0013 + * BLOWFISH 3 0x0016-0x0018 0x0017-0x0017 + * THREADING 3 0x001A-0x001E + * AES 5 0x0020-0x0022 0x0021-0x0025 + * CAMELLIA 3 0x0024-0x0026 0x0027-0x0027 + * XTEA 2 0x0028-0x0028 0x0029-0x0029 + * BASE64 2 0x002A-0x002C + * OID 1 0x002E-0x002E 0x000B-0x000B + * PADLOCK 1 0x0030-0x0030 + * DES 2 0x0032-0x0032 0x0033-0x0033 + * CTR_DBRG 4 0x0034-0x003A + * ENTROPY 3 0x003C-0x0040 0x003D-0x003F + * NET 13 0x0042-0x0052 0x0043-0x0049 + * ARIA 4 0x0058-0x005E + * ASN1 7 0x0060-0x006C + * CMAC 1 0x007A-0x007A + * PBKDF2 1 0x007C-0x007C + * HMAC_DRBG 4 0x0003-0x0009 + * CCM 3 0x000D-0x0011 + * ARC4 1 0x0019-0x0019 + * MD2 1 0x002B-0x002B + * MD4 1 0x002D-0x002D + * MD5 1 0x002F-0x002F + * RIPEMD160 1 0x0031-0x0031 + * SHA1 1 0x0035-0x0035 0x0073-0x0073 + * SHA256 1 0x0037-0x0037 0x0074-0x0074 + * SHA512 1 0x0039-0x0039 0x0075-0x0075 + * CHACHA20 3 0x0051-0x0055 + * POLY1305 3 0x0057-0x005B + * CHACHAPOLY 2 0x0054-0x0056 + * PLATFORM 1 0x0070-0x0072 + * + * High-level module nr (3 bits - 0x0...-0x7...) + * Name ID Nr of Errors + * PEM 1 9 + * PKCS#12 1 4 (Started from top) + * X509 2 20 + * PKCS5 2 4 (Started from top) + * DHM 3 11 + * PK 3 15 (Started from top) + * RSA 4 11 + * ECP 4 10 (Started from top) + * MD 5 5 + * HKDF 5 1 (Started from top) + * SSL 5 1 (Started from 0x5E80) + * CIPHER 6 8 + * SSL 6 23 (Started from top) + * SSL 7 32 + * + * Module dependent error code (5 bits 0x.00.-0x.F8.) + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Translate a mbed TLS error code into a string representation, + * Result is truncated if necessary and always includes a terminating + * null byte. + * + * \param errnum error code + * \param buffer buffer to place representation in + * \param buflen length of the buffer + */ +void mbedtls_strerror( int errnum, char *buffer, size_t buflen ); + +#ifdef __cplusplus +} +#endif + +#endif /* error.h */ diff --git a/src/common/mbedtls/include/mbedtls/gcm.h b/src/common/mbedtls/include/mbedtls/gcm.h new file mode 100644 index 0000000000..5c9ae29749 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/gcm.h @@ -0,0 +1,336 @@ +/** + * \file gcm.h + * + * \brief This file contains GCM definitions and functions. + * + * The Galois/Counter Mode (GCM) for 128-bit block ciphers is defined + * in D. McGrew, J. Viega, The Galois/Counter Mode of Operation + * (GCM), Natl. Inst. Stand. Technol. + * + * For more information on GCM, see NIST SP 800-38D: Recommendation for + * Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC. + * + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_GCM_H +#define MBEDTLS_GCM_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "cipher.h" + +#include + +#define MBEDTLS_GCM_ENCRYPT 1 +#define MBEDTLS_GCM_DECRYPT 0 + +#define MBEDTLS_ERR_GCM_AUTH_FAILED -0x0012 /**< Authenticated decryption failed. */ + +/* MBEDTLS_ERR_GCM_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_GCM_HW_ACCEL_FAILED -0x0013 /**< GCM hardware accelerator failed. */ + +#define MBEDTLS_ERR_GCM_BAD_INPUT -0x0014 /**< Bad input parameters to function. */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_GCM_ALT) + +/** + * \brief The GCM context structure. + */ +typedef struct mbedtls_gcm_context +{ + mbedtls_cipher_context_t cipher_ctx; /*!< The cipher context used. */ + uint64_t HL[16]; /*!< Precalculated HTable low. */ + uint64_t HH[16]; /*!< Precalculated HTable high. */ + uint64_t len; /*!< The total length of the encrypted data. */ + uint64_t add_len; /*!< The total length of the additional data. */ + unsigned char base_ectr[16]; /*!< The first ECTR for tag. */ + unsigned char y[16]; /*!< The Y working value. */ + unsigned char buf[16]; /*!< The buf working value. */ + int mode; /*!< The operation to perform: + #MBEDTLS_GCM_ENCRYPT or + #MBEDTLS_GCM_DECRYPT. */ +} +mbedtls_gcm_context; + +#else /* !MBEDTLS_GCM_ALT */ +#include "gcm_alt.h" +#endif /* !MBEDTLS_GCM_ALT */ + +/** + * \brief This function initializes the specified GCM context, + * to make references valid, and prepares the context + * for mbedtls_gcm_setkey() or mbedtls_gcm_free(). + * + * The function does not bind the GCM context to a particular + * cipher, nor set the key. For this purpose, use + * mbedtls_gcm_setkey(). + * + * \param ctx The GCM context to initialize. This must not be \c NULL. + */ +void mbedtls_gcm_init( mbedtls_gcm_context *ctx ); + +/** + * \brief This function associates a GCM context with a + * cipher algorithm and a key. + * + * \param ctx The GCM context. This must be initialized. + * \param cipher The 128-bit block cipher to use. + * \param key The encryption key. This must be a readable buffer of at + * least \p keybits bits. + * \param keybits The key size in bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return A cipher-specific error code on failure. + */ +int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief This function performs GCM encryption or decryption of a buffer. + * + * \note For encryption, the output buffer can be the same as the + * input buffer. For decryption, the output buffer cannot be + * the same as input buffer. If the buffers overlap, the output + * buffer must trail at least 8 Bytes behind the input buffer. + * + * \warning When this function performs a decryption, it outputs the + * authentication tag and does not verify that the data is + * authentic. You should use this function to perform encryption + * only. For decryption, use mbedtls_gcm_auth_decrypt() instead. + * + * \param ctx The GCM context to use for encryption or decryption. This + * must be initialized. + * \param mode The operation to perform: + * - #MBEDTLS_GCM_ENCRYPT to perform authenticated encryption. + * The ciphertext is written to \p output and the + * authentication tag is written to \p tag. + * - #MBEDTLS_GCM_DECRYPT to perform decryption. + * The plaintext is written to \p output and the + * authentication tag is written to \p tag. + * Note that this mode is not recommended, because it does + * not verify the authenticity of the data. For this reason, + * you should use mbedtls_gcm_auth_decrypt() instead of + * calling this function in decryption mode. + * \param length The length of the input data, which is equal to the length + * of the output data. + * \param iv The initialization vector. This must be a readable buffer of + * at least \p iv_len Bytes. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. This must be of at + * least that size in Bytes. + * \param add_len The length of the additional data. + * \param input The buffer holding the input data. If \p length is greater + * than zero, this must be a readable buffer of at least that + * size in Bytes. + * \param output The buffer for holding the output data. If \p length is greater + * than zero, this must be a writable buffer of at least that + * size in Bytes. + * \param tag_len The length of the tag to generate. + * \param tag The buffer for holding the tag. This must be a writable + * buffer of at least \p tag_len Bytes. + * + * \return \c 0 if the encryption or decryption was performed + * successfully. Note that in #MBEDTLS_GCM_DECRYPT mode, + * this does not indicate that the data is authentic. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT if the lengths or pointers are + * not valid or a cipher-specific error code if the encryption + * or decryption failed. + */ +int mbedtls_gcm_crypt_and_tag( mbedtls_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ); + +/** + * \brief This function performs a GCM authenticated decryption of a + * buffer. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. This must be initialized. + * \param length The length of the ciphertext to decrypt, which is also + * the length of the decrypted plaintext. + * \param iv The initialization vector. This must be a readable buffer + * of at least \p iv_len Bytes. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. This must be of at + * least that size in Bytes. + * \param add_len The length of the additional data. + * \param tag The buffer holding the tag to verify. This must be a + * readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the tag to verify. + * \param input The buffer holding the ciphertext. If \p length is greater + * than zero, this must be a readable buffer of at least that + * size. + * \param output The buffer for holding the decrypted plaintext. If \p length + * is greater than zero, this must be a writable buffer of at + * least that size. + * + * \return \c 0 if successful and authenticated. + * \return #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT if the lengths or pointers are + * not valid or a cipher-specific error code if the decryption + * failed. + */ +int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function starts a GCM encryption or decryption + * operation. + * + * \param ctx The GCM context. This must be initialized. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param iv The initialization vector. This must be a readable buffer of + * at least \p iv_len Bytes. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data, or \c NULL + * if \p add_len is \c 0. + * \param add_len The length of the additional data. If \c 0, + * \p add may be \c NULL. + * + * \return \c 0 on success. + */ +int mbedtls_gcm_starts( mbedtls_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len ); + +/** + * \brief This function feeds an input buffer into an ongoing GCM + * encryption or decryption operation. + * + * ` The function expects input to be a multiple of 16 + * Bytes. Only the last call before calling + * mbedtls_gcm_finish() can be less than 16 Bytes. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. This must be initialized. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param input The buffer holding the input data. If \p length is greater + * than zero, this must be a readable buffer of at least that + * size in Bytes. + * \param output The buffer for holding the output data. If \p length is + * greater than zero, this must be a writable buffer of at + * least that size in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int mbedtls_gcm_update( mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function finishes the GCM operation and generates + * the authentication tag. + * + * It wraps up the GCM stream, and generates the + * tag. The tag can have a maximum length of 16 Bytes. + * + * \param ctx The GCM context. This must be initialized. + * \param tag The buffer for holding the tag. This must be a writable + * buffer of at least \p tag_len Bytes. + * \param tag_len The length of the tag to generate. This must be at least + * four. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int mbedtls_gcm_finish( mbedtls_gcm_context *ctx, + unsigned char *tag, + size_t tag_len ); + +/** + * \brief This function clears a GCM context and the underlying + * cipher sub-context. + * + * \param ctx The GCM context to clear. If this is \c NULL, the call has + * no effect. Otherwise, this must be initialized. + */ +void mbedtls_gcm_free( mbedtls_gcm_context *ctx ); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The GCM checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_gcm_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + + +#endif /* gcm.h */ diff --git a/src/common/mbedtls/include/mbedtls/hkdf.h b/src/common/mbedtls/include/mbedtls/hkdf.h new file mode 100644 index 0000000000..92d438b92f --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/hkdf.h @@ -0,0 +1,151 @@ +/** + * \file hkdf.h + * + * \brief This file contains the HKDF interface. + * + * The HMAC-based Extract-and-Expand Key Derivation Function (HKDF) is + * specified by RFC 5869. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_HKDF_H +#define MBEDTLS_HKDF_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "md.h" + +/** + * \name HKDF Error codes + * \{ + */ +#define MBEDTLS_ERR_HKDF_BAD_INPUT_DATA -0x5F80 /**< Bad input parameters to function. */ +/* \} name */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief This is the HMAC-based Extract-and-Expand Key Derivation Function + * (HKDF). + * + * \param md A hash function; md.size denotes the length of the hash + * function output in bytes. + * \param salt An optional salt value (a non-secret random value); + * if the salt is not provided, a string of all zeros of + * md.size length is used as the salt. + * \param salt_len The length in bytes of the optional \p salt. + * \param ikm The input keying material. + * \param ikm_len The length in bytes of \p ikm. + * \param info An optional context and application specific information + * string. This can be a zero-length string. + * \param info_len The length of \p info in bytes. + * \param okm The output keying material of \p okm_len bytes. + * \param okm_len The length of the output keying material in bytes. This + * must be less than or equal to 255 * md.size bytes. + * + * \return 0 on success. + * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. + * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying + * MD layer. + */ +int mbedtls_hkdf( const mbedtls_md_info_t *md, const unsigned char *salt, + size_t salt_len, const unsigned char *ikm, size_t ikm_len, + const unsigned char *info, size_t info_len, + unsigned char *okm, size_t okm_len ); + +/** + * \brief Take the input keying material \p ikm and extract from it a + * fixed-length pseudorandom key \p prk. + * + * \warning This function should only be used if the security of it has been + * studied and established in that particular context (eg. TLS 1.3 + * key schedule). For standard HKDF security guarantees use + * \c mbedtls_hkdf instead. + * + * \param md A hash function; md.size denotes the length of the + * hash function output in bytes. + * \param salt An optional salt value (a non-secret random value); + * if the salt is not provided, a string of all zeros + * of md.size length is used as the salt. + * \param salt_len The length in bytes of the optional \p salt. + * \param ikm The input keying material. + * \param ikm_len The length in bytes of \p ikm. + * \param[out] prk A pseudorandom key of at least md.size bytes. + * + * \return 0 on success. + * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. + * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying + * MD layer. + */ +int mbedtls_hkdf_extract( const mbedtls_md_info_t *md, + const unsigned char *salt, size_t salt_len, + const unsigned char *ikm, size_t ikm_len, + unsigned char *prk ); + +/** + * \brief Expand the supplied \p prk into several additional pseudorandom + * keys, which is the output of the HKDF. + * + * \warning This function should only be used if the security of it has been + * studied and established in that particular context (eg. TLS 1.3 + * key schedule). For standard HKDF security guarantees use + * \c mbedtls_hkdf instead. + * + * \param md A hash function; md.size denotes the length of the hash + * function output in bytes. + * \param prk A pseudorandom key of at least md.size bytes. \p prk is + * usually the output from the HKDF extract step. + * \param prk_len The length in bytes of \p prk. + * \param info An optional context and application specific information + * string. This can be a zero-length string. + * \param info_len The length of \p info in bytes. + * \param okm The output keying material of \p okm_len bytes. + * \param okm_len The length of the output keying material in bytes. This + * must be less than or equal to 255 * md.size bytes. + * + * \return 0 on success. + * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. + * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying + * MD layer. + */ +int mbedtls_hkdf_expand( const mbedtls_md_info_t *md, const unsigned char *prk, + size_t prk_len, const unsigned char *info, + size_t info_len, unsigned char *okm, size_t okm_len ); + +#ifdef __cplusplus +} +#endif + +#endif /* hkdf.h */ diff --git a/src/common/mbedtls/include/mbedtls/md.h b/src/common/mbedtls/include/mbedtls/md.h new file mode 100644 index 0000000000..79b803eb78 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/md.h @@ -0,0 +1,480 @@ + /** + * \file md.h + * + * \brief This file contains the generic message-digest wrapper. + * + * \author Adriaan de Jong + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_MD_H +#define MBEDTLS_MD_H + +#include + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#define MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE -0x5080 /**< The selected feature is not available. */ +#define MBEDTLS_ERR_MD_BAD_INPUT_DATA -0x5100 /**< Bad input parameters to function. */ +#define MBEDTLS_ERR_MD_ALLOC_FAILED -0x5180 /**< Failed to allocate memory. */ +#define MBEDTLS_ERR_MD_FILE_IO_ERROR -0x5200 /**< Opening or reading of file failed. */ + +/* MBEDTLS_ERR_MD_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_MD_HW_ACCEL_FAILED -0x5280 /**< MD hardware accelerator failed. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Supported message digests. + * + * \warning MD2, MD4, MD5 and SHA-1 are considered weak message digests and + * their use constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +typedef enum { + MBEDTLS_MD_NONE=0, /**< None. */ + MBEDTLS_MD_MD2, /**< The MD2 message digest. */ + MBEDTLS_MD_MD4, /**< The MD4 message digest. */ + MBEDTLS_MD_MD5, /**< The MD5 message digest. */ + MBEDTLS_MD_SHA1, /**< The SHA-1 message digest. */ + MBEDTLS_MD_SHA224, /**< The SHA-224 message digest. */ + MBEDTLS_MD_SHA256, /**< The SHA-256 message digest. */ + MBEDTLS_MD_SHA384, /**< The SHA-384 message digest. */ + MBEDTLS_MD_SHA512, /**< The SHA-512 message digest. */ + MBEDTLS_MD_RIPEMD160, /**< The RIPEMD-160 message digest. */ +} mbedtls_md_type_t; + +#if defined(MBEDTLS_SHA512_C) +#define MBEDTLS_MD_MAX_SIZE 64 /* longest known is SHA512 */ +#else +#define MBEDTLS_MD_MAX_SIZE 32 /* longest known is SHA256 or less */ +#endif + +/** + * Opaque struct defined in md_internal.h. + */ +typedef struct mbedtls_md_info_t mbedtls_md_info_t; + +/** + * The generic message-digest context. + */ +typedef struct mbedtls_md_context_t +{ + /** Information about the associated message digest. */ + const mbedtls_md_info_t *md_info; + + /** The digest-specific context. */ + void *md_ctx; + + /** The HMAC part of the context. */ + void *hmac_ctx; +} mbedtls_md_context_t; + +/** + * \brief This function returns the list of digests supported by the + * generic digest module. + * + * \note The list starts with the strongest available hashes. + * + * \return A statically allocated array of digests. Each element + * in the returned list is an integer belonging to the + * message-digest enumeration #mbedtls_md_type_t. + * The last entry is 0. + */ +const int *mbedtls_md_list( void ); + +/** + * \brief This function returns the message-digest information + * associated with the given digest name. + * + * \param md_name The name of the digest to search for. + * + * \return The message-digest information associated with \p md_name. + * \return NULL if the associated message-digest information is not found. + */ +const mbedtls_md_info_t *mbedtls_md_info_from_string( const char *md_name ); + +/** + * \brief This function returns the message-digest information + * associated with the given digest type. + * + * \param md_type The type of digest to search for. + * + * \return The message-digest information associated with \p md_type. + * \return NULL if the associated message-digest information is not found. + */ +const mbedtls_md_info_t *mbedtls_md_info_from_type( mbedtls_md_type_t md_type ); + +/** + * \brief This function initializes a message-digest context without + * binding it to a particular message-digest algorithm. + * + * This function should always be called first. It prepares the + * context for mbedtls_md_setup() for binding it to a + * message-digest algorithm. + */ +void mbedtls_md_init( mbedtls_md_context_t *ctx ); + +/** + * \brief This function clears the internal structure of \p ctx and + * frees any embedded internal structure, but does not free + * \p ctx itself. + * + * If you have called mbedtls_md_setup() on \p ctx, you must + * call mbedtls_md_free() when you are no longer using the + * context. + * Calling this function if you have previously + * called mbedtls_md_init() and nothing else is optional. + * You must not call this function if you have not called + * mbedtls_md_init(). + */ +void mbedtls_md_free( mbedtls_md_context_t *ctx ); + +#if ! defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief This function selects the message digest algorithm to use, + * and allocates internal structures. + * + * It should be called after mbedtls_md_init() or mbedtls_md_free(). + * Makes it necessary to call mbedtls_md_free() later. + * + * \deprecated Superseded by mbedtls_md_setup() in 2.0.0 + * + * \param ctx The context to set up. + * \param md_info The information structure of the message-digest algorithm + * to use. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + * \return #MBEDTLS_ERR_MD_ALLOC_FAILED on memory-allocation failure. + */ +int mbedtls_md_init_ctx( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info ) MBEDTLS_DEPRECATED; +#undef MBEDTLS_DEPRECATED +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief This function selects the message digest algorithm to use, + * and allocates internal structures. + * + * It should be called after mbedtls_md_init() or + * mbedtls_md_free(). Makes it necessary to call + * mbedtls_md_free() later. + * + * \param ctx The context to set up. + * \param md_info The information structure of the message-digest algorithm + * to use. + * \param hmac Defines if HMAC is used. 0: HMAC is not used (saves some memory), + * or non-zero: HMAC is used with this context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + * \return #MBEDTLS_ERR_MD_ALLOC_FAILED on memory-allocation failure. + */ +int mbedtls_md_setup( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info, int hmac ); + +/** + * \brief This function clones the state of an message-digest + * context. + * + * \note You must call mbedtls_md_setup() on \c dst before calling + * this function. + * + * \note The two contexts must have the same type, + * for example, both are SHA-256. + * + * \warning This function clones the message-digest state, not the + * HMAC state. + * + * \param dst The destination context. + * \param src The context to be cloned. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification failure. + */ +int mbedtls_md_clone( mbedtls_md_context_t *dst, + const mbedtls_md_context_t *src ); + +/** + * \brief This function extracts the message-digest size from the + * message-digest information structure. + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * + * \return The size of the message-digest output in Bytes. + */ +unsigned char mbedtls_md_get_size( const mbedtls_md_info_t *md_info ); + +/** + * \brief This function extracts the message-digest type from the + * message-digest information structure. + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * + * \return The type of the message digest. + */ +mbedtls_md_type_t mbedtls_md_get_type( const mbedtls_md_info_t *md_info ); + +/** + * \brief This function extracts the message-digest name from the + * message-digest information structure. + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * + * \return The name of the message digest. + */ +const char *mbedtls_md_get_name( const mbedtls_md_info_t *md_info ); + +/** + * \brief This function starts a message-digest computation. + * + * You must call this function after setting up the context + * with mbedtls_md_setup(), and before passing data with + * mbedtls_md_update(). + * + * \param ctx The generic message-digest context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md_starts( mbedtls_md_context_t *ctx ); + +/** + * \brief This function feeds an input buffer into an ongoing + * message-digest computation. + * + * You must call mbedtls_md_starts() before calling this + * function. You may call this function multiple times. + * Afterwards, call mbedtls_md_finish(). + * + * \param ctx The generic message-digest context. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md_update( mbedtls_md_context_t *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief This function finishes the digest operation, + * and writes the result to the output buffer. + * + * Call this function after a call to mbedtls_md_starts(), + * followed by any number of calls to mbedtls_md_update(). + * Afterwards, you may either clear the context with + * mbedtls_md_free(), or call mbedtls_md_starts() to reuse + * the context for another digest operation with the same + * algorithm. + * + * \param ctx The generic message-digest context. + * \param output The buffer for the generic message-digest checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md_finish( mbedtls_md_context_t *ctx, unsigned char *output ); + +/** + * \brief This function calculates the message-digest of a buffer, + * with respect to a configurable message-digest algorithm + * in a single call. + * + * The result is calculated as + * Output = message_digest(input buffer). + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * \param input The buffer holding the data. + * \param ilen The length of the input data. + * \param output The generic message-digest checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md( const mbedtls_md_info_t *md_info, const unsigned char *input, size_t ilen, + unsigned char *output ); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief This function calculates the message-digest checksum + * result of the contents of the provided file. + * + * The result is calculated as + * Output = message_digest(file contents). + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * \param path The input file name. + * \param output The generic message-digest checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_FILE_IO_ERROR on an I/O error accessing + * the file pointed by \p path. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info was NULL. + */ +int mbedtls_md_file( const mbedtls_md_info_t *md_info, const char *path, + unsigned char *output ); +#endif /* MBEDTLS_FS_IO */ + +/** + * \brief This function sets the HMAC key and prepares to + * authenticate a new message. + * + * Call this function after mbedtls_md_setup(), to use + * the MD context for an HMAC calculation, then call + * mbedtls_md_hmac_update() to provide the input data, and + * mbedtls_md_hmac_finish() to get the HMAC value. + * + * \param ctx The message digest context containing an embedded HMAC + * context. + * \param key The HMAC secret key. + * \param keylen The length of the HMAC key in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md_hmac_starts( mbedtls_md_context_t *ctx, const unsigned char *key, + size_t keylen ); + +/** + * \brief This function feeds an input buffer into an ongoing HMAC + * computation. + * + * Call mbedtls_md_hmac_starts() or mbedtls_md_hmac_reset() + * before calling this function. + * You may call this function multiple times to pass the + * input piecewise. + * Afterwards, call mbedtls_md_hmac_finish(). + * + * \param ctx The message digest context containing an embedded HMAC + * context. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md_hmac_update( mbedtls_md_context_t *ctx, const unsigned char *input, + size_t ilen ); + +/** + * \brief This function finishes the HMAC operation, and writes + * the result to the output buffer. + * + * Call this function after mbedtls_md_hmac_starts() and + * mbedtls_md_hmac_update() to get the HMAC value. Afterwards + * you may either call mbedtls_md_free() to clear the context, + * or call mbedtls_md_hmac_reset() to reuse the context with + * the same HMAC key. + * + * \param ctx The message digest context containing an embedded HMAC + * context. + * \param output The generic HMAC checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md_hmac_finish( mbedtls_md_context_t *ctx, unsigned char *output); + +/** + * \brief This function prepares to authenticate a new message with + * the same key as the previous HMAC operation. + * + * You may call this function after mbedtls_md_hmac_finish(). + * Afterwards call mbedtls_md_hmac_update() to pass the new + * input. + * + * \param ctx The message digest context containing an embedded HMAC + * context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md_hmac_reset( mbedtls_md_context_t *ctx ); + +/** + * \brief This function calculates the full generic HMAC + * on the input buffer with the provided key. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The HMAC result is calculated as + * output = generic HMAC(hmac key, input buffer). + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * \param key The HMAC secret key. + * \param keylen The length of the HMAC secret key in Bytes. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * \param output The generic HMAC result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +int mbedtls_md_hmac( const mbedtls_md_info_t *md_info, const unsigned char *key, size_t keylen, + const unsigned char *input, size_t ilen, + unsigned char *output ); + +/* Internal use */ +int mbedtls_md_process( mbedtls_md_context_t *ctx, const unsigned char *data ); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_MD_H */ diff --git a/src/common/mbedtls/include/mbedtls/md5.h b/src/common/mbedtls/include/mbedtls/md5.h new file mode 100644 index 0000000000..5d75cf6352 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/md5.h @@ -0,0 +1,321 @@ +/** + * \file md5.h + * + * \brief MD5 message digest algorithm (hash function) + * + * \warning MD5 is considered a weak message digest and its use constitutes a + * security risk. We recommend considering stronger message + * digests instead. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_MD5_H +#define MBEDTLS_MD5_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include + +/* MBEDTLS_ERR_MD5_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_MD5_HW_ACCEL_FAILED -0x002F /**< MD5 hardware accelerator failed */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_MD5_ALT) +// Regular implementation +// + +/** + * \brief MD5 context structure + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +typedef struct mbedtls_md5_context +{ + uint32_t total[2]; /*!< number of bytes processed */ + uint32_t state[4]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ +} +mbedtls_md5_context; + +#else /* MBEDTLS_MD5_ALT */ +#include "md5_alt.h" +#endif /* MBEDTLS_MD5_ALT */ + +/** + * \brief Initialize MD5 context + * + * \param ctx MD5 context to be initialized + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +void mbedtls_md5_init( mbedtls_md5_context *ctx ); + +/** + * \brief Clear MD5 context + * + * \param ctx MD5 context to be cleared + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +void mbedtls_md5_free( mbedtls_md5_context *ctx ); + +/** + * \brief Clone (the state of) an MD5 context + * + * \param dst The destination context + * \param src The context to be cloned + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +void mbedtls_md5_clone( mbedtls_md5_context *dst, + const mbedtls_md5_context *src ); + +/** + * \brief MD5 context setup + * + * \param ctx context to be initialized + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx ); + +/** + * \brief MD5 process buffer + * + * \param ctx MD5 context + * \param input buffer holding the data + * \param ilen length of the input data + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief MD5 final digest + * + * \param ctx MD5 context + * \param output MD5 checksum result + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx, + unsigned char output[16] ); + +/** + * \brief MD5 process data block (internal use only) + * + * \param ctx MD5 context + * \param data buffer holding one block of data + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, + const unsigned char data[64] ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief MD5 context setup + * + * \deprecated Superseded by mbedtls_md5_starts_ret() in 2.7.0 + * + * \param ctx context to be initialized + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_md5_starts( mbedtls_md5_context *ctx ); + +/** + * \brief MD5 process buffer + * + * \deprecated Superseded by mbedtls_md5_update_ret() in 2.7.0 + * + * \param ctx MD5 context + * \param input buffer holding the data + * \param ilen length of the input data + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_md5_update( mbedtls_md5_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief MD5 final digest + * + * \deprecated Superseded by mbedtls_md5_finish_ret() in 2.7.0 + * + * \param ctx MD5 context + * \param output MD5 checksum result + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_md5_finish( mbedtls_md5_context *ctx, + unsigned char output[16] ); + +/** + * \brief MD5 process data block (internal use only) + * + * \deprecated Superseded by mbedtls_internal_md5_process() in 2.7.0 + * + * \param ctx MD5 context + * \param data buffer holding one block of data + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_md5_process( mbedtls_md5_context *ctx, + const unsigned char data[64] ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief Output = MD5( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output MD5 checksum result + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_ret( const unsigned char *input, + size_t ilen, + unsigned char output[16] ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief Output = MD5( input buffer ) + * + * \deprecated Superseded by mbedtls_md5_ret() in 2.7.0 + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output MD5 checksum result + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_md5( const unsigned char *input, + size_t ilen, + unsigned char output[16] ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_md5.h */ diff --git a/src/common/mbedtls/include/mbedtls/md_internal.h b/src/common/mbedtls/include/mbedtls/md_internal.h new file mode 100644 index 0000000000..bec54ec8a6 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/md_internal.h @@ -0,0 +1,125 @@ +/** + * \file md_internal.h + * + * \brief Message digest wrappers. + * + * \warning This in an internal header. Do not include directly. + * + * \author Adriaan de Jong + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_MD_WRAP_H +#define MBEDTLS_MD_WRAP_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "md.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Message digest information. + * Allows message digest functions to be called in a generic way. + */ +struct mbedtls_md_info_t +{ + /** Digest identifier */ + mbedtls_md_type_t type; + + /** Name of the message digest */ + const char * name; + + /** Output length of the digest function in bytes */ + int size; + + /** Block length of the digest function in bytes */ + int block_size; + + /** Digest initialisation function */ + int (*starts_func)( void *ctx ); + + /** Digest update function */ + int (*update_func)( void *ctx, const unsigned char *input, size_t ilen ); + + /** Digest finalisation function */ + int (*finish_func)( void *ctx, unsigned char *output ); + + /** Generic digest function */ + int (*digest_func)( const unsigned char *input, size_t ilen, + unsigned char *output ); + + /** Allocate a new context */ + void * (*ctx_alloc_func)( void ); + + /** Free the given context */ + void (*ctx_free_func)( void *ctx ); + + /** Clone state from a context */ + void (*clone_func)( void *dst, const void *src ); + + /** Internal use only */ + int (*process_func)( void *ctx, const unsigned char *input ); +}; + +#if defined(MBEDTLS_MD2_C) +extern const mbedtls_md_info_t mbedtls_md2_info; +#endif +#if defined(MBEDTLS_MD4_C) +extern const mbedtls_md_info_t mbedtls_md4_info; +#endif +#if defined(MBEDTLS_MD5_C) +extern const mbedtls_md_info_t mbedtls_md5_info; +#endif +#if defined(MBEDTLS_RIPEMD160_C) +extern const mbedtls_md_info_t mbedtls_ripemd160_info; +#endif +#if defined(MBEDTLS_SHA1_C) +extern const mbedtls_md_info_t mbedtls_sha1_info; +#endif +#if defined(MBEDTLS_SHA256_C) +extern const mbedtls_md_info_t mbedtls_sha224_info; +extern const mbedtls_md_info_t mbedtls_sha256_info; +#endif +#if defined(MBEDTLS_SHA512_C) +extern const mbedtls_md_info_t mbedtls_sha384_info; +extern const mbedtls_md_info_t mbedtls_sha512_info; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_MD_WRAP_H */ diff --git a/src/common/mbedtls/include/mbedtls/nist_kw.h b/src/common/mbedtls/include/mbedtls/nist_kw.h new file mode 100644 index 0000000000..1c65e471f8 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/nist_kw.h @@ -0,0 +1,194 @@ +/** + * \file nist_kw.h + * + * \brief This file provides an API for key wrapping (KW) and key wrapping with + * padding (KWP) as defined in NIST SP 800-38F. + * https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-38F.pdf + * + * Key wrapping specifies a deterministic authenticated-encryption mode + * of operation, according to NIST SP 800-38F: Recommendation for + * Block Cipher Modes of Operation: Methods for Key Wrapping. Its + * purpose is to protect cryptographic keys. + * + * Its equivalent is RFC 3394 for KW, and RFC 5649 for KWP. + * https://tools.ietf.org/html/rfc3394 + * https://tools.ietf.org/html/rfc5649 + * + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_NIST_KW_H +#define MBEDTLS_NIST_KW_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "cipher.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum +{ + MBEDTLS_KW_MODE_KW = 0, + MBEDTLS_KW_MODE_KWP = 1 +} mbedtls_nist_kw_mode_t; + +#if !defined(MBEDTLS_NIST_KW_ALT) +// Regular implementation +// + +/** + * \brief The key wrapping context-type definition. The key wrapping context is passed + * to the APIs called. + * + * \note The definition of this type may change in future library versions. + * Don't make any assumptions on this context! + */ +typedef struct { + mbedtls_cipher_context_t cipher_ctx; /*!< The cipher context used. */ +} mbedtls_nist_kw_context; + +#else /* MBEDTLS_NIST_key wrapping_ALT */ +#include "nist_kw_alt.h" +#endif /* MBEDTLS_NIST_KW_ALT */ + +/** + * \brief This function initializes the specified key wrapping context + * to make references valid and prepare the context + * for mbedtls_nist_kw_setkey() or mbedtls_nist_kw_free(). + * + * \param ctx The key wrapping context to initialize. + * + */ +void mbedtls_nist_kw_init( mbedtls_nist_kw_context *ctx ); + +/** + * \brief This function initializes the key wrapping context set in the + * \p ctx parameter and sets the encryption key. + * + * \param ctx The key wrapping context. + * \param cipher The 128-bit block cipher to use. Only AES is supported. + * \param key The Key Encryption Key (KEK). + * \param keybits The KEK size in bits. This must be acceptable by the cipher. + * \param is_wrap Specify whether the operation within the context is wrapping or unwrapping + * + * \return \c 0 on success. + * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for any invalid input. + * \return \c MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE for 128-bit block ciphers + * which are not supported. + * \return cipher-specific error code on failure of the underlying cipher. + */ +int mbedtls_nist_kw_setkey( mbedtls_nist_kw_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits, + const int is_wrap ); + +/** + * \brief This function releases and clears the specified key wrapping context + * and underlying cipher sub-context. + * + * \param ctx The key wrapping context to clear. + */ +void mbedtls_nist_kw_free( mbedtls_nist_kw_context *ctx ); + +/** + * \brief This function encrypts a buffer using key wrapping. + * + * \param ctx The key wrapping context to use for encryption. + * \param mode The key wrapping mode to use (MBEDTLS_KW_MODE_KW or MBEDTLS_KW_MODE_KWP) + * \param input The buffer holding the input data. + * \param in_len The length of the input data in Bytes. + * The input uses units of 8 Bytes called semiblocks. + *
  • For KW mode: a multiple of 8 bytes between 16 and 2^57-8 inclusive.
    • + *
  • For KWP mode: any length between 1 and 2^32-1 inclusive.
+ * \param[out] output The buffer holding the output data. + *
  • For KW mode: Must be at least 8 bytes larger than \p in_len.
    • + *
  • For KWP mode: Must be at least 8 bytes larger rounded up to a multiple of + * 8 bytes for KWP (15 bytes at most).
+ * \param[out] out_len The number of bytes written to the output buffer. \c 0 on failure. + * \param[in] out_size The capacity of the output buffer. + * + * \return \c 0 on success. + * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for invalid input length. + * \return cipher-specific error code on failure of the underlying cipher. + */ +int mbedtls_nist_kw_wrap( mbedtls_nist_kw_context *ctx, mbedtls_nist_kw_mode_t mode, + const unsigned char *input, size_t in_len, + unsigned char *output, size_t* out_len, size_t out_size ); + +/** + * \brief This function decrypts a buffer using key wrapping. + * + * \param ctx The key wrapping context to use for decryption. + * \param mode The key wrapping mode to use (MBEDTLS_KW_MODE_KW or MBEDTLS_KW_MODE_KWP) + * \param input The buffer holding the input data. + * \param in_len The length of the input data in Bytes. + * The input uses units of 8 Bytes called semiblocks. + * The input must be a multiple of semiblocks. + *
  • For KW mode: a multiple of 8 bytes between 24 and 2^57 inclusive.
    • + *
  • For KWP mode: a multiple of 8 bytes between 16 and 2^32 inclusive.
+ * \param[out] output The buffer holding the output data. + * The output buffer's minimal length is 8 bytes shorter than \p in_len. + * \param[out] out_len The number of bytes written to the output buffer. \c 0 on failure. + * For KWP mode, the length could be up to 15 bytes shorter than \p in_len, + * depending on how much padding was added to the data. + * \param[in] out_size The capacity of the output buffer. + * + * \return \c 0 on success. + * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for invalid input length. + * \return \c MBEDTLS_ERR_CIPHER_AUTH_FAILED for verification failure of the ciphertext. + * \return cipher-specific error code on failure of the underlying cipher. + */ +int mbedtls_nist_kw_unwrap( mbedtls_nist_kw_context *ctx, mbedtls_nist_kw_mode_t mode, + const unsigned char *input, size_t in_len, + unsigned char *output, size_t* out_len, size_t out_size); + + +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +/** + * \brief The key wrapping checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_nist_kw_self_test( int verbose ); +#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_NIST_KW_H */ diff --git a/src/common/mbedtls/include/mbedtls/oid.h b/src/common/mbedtls/include/mbedtls/oid.h new file mode 100644 index 0000000000..24e814df9f --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/oid.h @@ -0,0 +1,615 @@ +/** + * \file oid.h + * + * \brief Object Identifier (OID) database + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_OID_H +#define MBEDTLS_OID_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "asn1.h" +#include "pk.h" + +#include + +#if defined(MBEDTLS_CIPHER_C) +#include "cipher.h" +#endif + +#if defined(MBEDTLS_MD_C) +#include "md.h" +#endif + +#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C) +#include "x509.h" +#endif + +#define MBEDTLS_ERR_OID_NOT_FOUND -0x002E /**< OID is not found. */ +#define MBEDTLS_ERR_OID_BUF_TOO_SMALL -0x000B /**< output buffer is too small */ + +/* + * Top level OID tuples + */ +#define MBEDTLS_OID_ISO_MEMBER_BODIES "\x2a" /* {iso(1) member-body(2)} */ +#define MBEDTLS_OID_ISO_IDENTIFIED_ORG "\x2b" /* {iso(1) identified-organization(3)} */ +#define MBEDTLS_OID_ISO_CCITT_DS "\x55" /* {joint-iso-ccitt(2) ds(5)} */ +#define MBEDTLS_OID_ISO_ITU_COUNTRY "\x60" /* {joint-iso-itu-t(2) country(16)} */ + +/* + * ISO Member bodies OID parts + */ +#define MBEDTLS_OID_COUNTRY_US "\x86\x48" /* {us(840)} */ +#define MBEDTLS_OID_ORG_RSA_DATA_SECURITY "\x86\xf7\x0d" /* {rsadsi(113549)} */ +#define MBEDTLS_OID_RSA_COMPANY MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \ + MBEDTLS_OID_ORG_RSA_DATA_SECURITY /* {iso(1) member-body(2) us(840) rsadsi(113549)} */ +#define MBEDTLS_OID_ORG_ANSI_X9_62 "\xce\x3d" /* ansi-X9-62(10045) */ +#define MBEDTLS_OID_ANSI_X9_62 MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \ + MBEDTLS_OID_ORG_ANSI_X9_62 + +/* + * ISO Identified organization OID parts + */ +#define MBEDTLS_OID_ORG_DOD "\x06" /* {dod(6)} */ +#define MBEDTLS_OID_ORG_OIW "\x0e" +#define MBEDTLS_OID_OIW_SECSIG MBEDTLS_OID_ORG_OIW "\x03" +#define MBEDTLS_OID_OIW_SECSIG_ALG MBEDTLS_OID_OIW_SECSIG "\x02" +#define MBEDTLS_OID_OIW_SECSIG_SHA1 MBEDTLS_OID_OIW_SECSIG_ALG "\x1a" +#define MBEDTLS_OID_ORG_CERTICOM "\x81\x04" /* certicom(132) */ +#define MBEDTLS_OID_CERTICOM MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_CERTICOM +#define MBEDTLS_OID_ORG_TELETRUST "\x24" /* teletrust(36) */ +#define MBEDTLS_OID_TELETRUST MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_TELETRUST + +/* + * ISO ITU OID parts + */ +#define MBEDTLS_OID_ORGANIZATION "\x01" /* {organization(1)} */ +#define MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ISO_ITU_COUNTRY MBEDTLS_OID_COUNTRY_US MBEDTLS_OID_ORGANIZATION /* {joint-iso-itu-t(2) country(16) us(840) organization(1)} */ + +#define MBEDTLS_OID_ORG_GOV "\x65" /* {gov(101)} */ +#define MBEDTLS_OID_GOV MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_GOV /* {joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101)} */ + +#define MBEDTLS_OID_ORG_NETSCAPE "\x86\xF8\x42" /* {netscape(113730)} */ +#define MBEDTLS_OID_NETSCAPE MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_NETSCAPE /* Netscape OID {joint-iso-itu-t(2) country(16) us(840) organization(1) netscape(113730)} */ + +/* ISO arc for standard certificate and CRL extensions */ +#define MBEDTLS_OID_ID_CE MBEDTLS_OID_ISO_CCITT_DS "\x1D" /**< id-ce OBJECT IDENTIFIER ::= {joint-iso-ccitt(2) ds(5) 29} */ + +#define MBEDTLS_OID_NIST_ALG MBEDTLS_OID_GOV "\x03\x04" /** { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithm(4) */ + +/** + * Private Internet Extensions + * { iso(1) identified-organization(3) dod(6) internet(1) + * security(5) mechanisms(5) pkix(7) } + */ +#define MBEDTLS_OID_PKIX MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_DOD "\x01\x05\x05\x07" + +/* + * Arc for standard naming attributes + */ +#define MBEDTLS_OID_AT MBEDTLS_OID_ISO_CCITT_DS "\x04" /**< id-at OBJECT IDENTIFIER ::= {joint-iso-ccitt(2) ds(5) 4} */ +#define MBEDTLS_OID_AT_CN MBEDTLS_OID_AT "\x03" /**< id-at-commonName AttributeType:= {id-at 3} */ +#define MBEDTLS_OID_AT_SUR_NAME MBEDTLS_OID_AT "\x04" /**< id-at-surName AttributeType:= {id-at 4} */ +#define MBEDTLS_OID_AT_SERIAL_NUMBER MBEDTLS_OID_AT "\x05" /**< id-at-serialNumber AttributeType:= {id-at 5} */ +#define MBEDTLS_OID_AT_COUNTRY MBEDTLS_OID_AT "\x06" /**< id-at-countryName AttributeType:= {id-at 6} */ +#define MBEDTLS_OID_AT_LOCALITY MBEDTLS_OID_AT "\x07" /**< id-at-locality AttributeType:= {id-at 7} */ +#define MBEDTLS_OID_AT_STATE MBEDTLS_OID_AT "\x08" /**< id-at-state AttributeType:= {id-at 8} */ +#define MBEDTLS_OID_AT_ORGANIZATION MBEDTLS_OID_AT "\x0A" /**< id-at-organizationName AttributeType:= {id-at 10} */ +#define MBEDTLS_OID_AT_ORG_UNIT MBEDTLS_OID_AT "\x0B" /**< id-at-organizationalUnitName AttributeType:= {id-at 11} */ +#define MBEDTLS_OID_AT_TITLE MBEDTLS_OID_AT "\x0C" /**< id-at-title AttributeType:= {id-at 12} */ +#define MBEDTLS_OID_AT_POSTAL_ADDRESS MBEDTLS_OID_AT "\x10" /**< id-at-postalAddress AttributeType:= {id-at 16} */ +#define MBEDTLS_OID_AT_POSTAL_CODE MBEDTLS_OID_AT "\x11" /**< id-at-postalCode AttributeType:= {id-at 17} */ +#define MBEDTLS_OID_AT_GIVEN_NAME MBEDTLS_OID_AT "\x2A" /**< id-at-givenName AttributeType:= {id-at 42} */ +#define MBEDTLS_OID_AT_INITIALS MBEDTLS_OID_AT "\x2B" /**< id-at-initials AttributeType:= {id-at 43} */ +#define MBEDTLS_OID_AT_GENERATION_QUALIFIER MBEDTLS_OID_AT "\x2C" /**< id-at-generationQualifier AttributeType:= {id-at 44} */ +#define MBEDTLS_OID_AT_UNIQUE_IDENTIFIER MBEDTLS_OID_AT "\x2D" /**< id-at-uniqueIdentifier AttributType:= {id-at 45} */ +#define MBEDTLS_OID_AT_DN_QUALIFIER MBEDTLS_OID_AT "\x2E" /**< id-at-dnQualifier AttributeType:= {id-at 46} */ +#define MBEDTLS_OID_AT_PSEUDONYM MBEDTLS_OID_AT "\x41" /**< id-at-pseudonym AttributeType:= {id-at 65} */ + +#define MBEDTLS_OID_DOMAIN_COMPONENT "\x09\x92\x26\x89\x93\xF2\x2C\x64\x01\x19" /** id-domainComponent AttributeType:= {itu-t(0) data(9) pss(2342) ucl(19200300) pilot(100) pilotAttributeType(1) domainComponent(25)} */ + +/* + * OIDs for standard certificate extensions + */ +#define MBEDTLS_OID_AUTHORITY_KEY_IDENTIFIER MBEDTLS_OID_ID_CE "\x23" /**< id-ce-authorityKeyIdentifier OBJECT IDENTIFIER ::= { id-ce 35 } */ +#define MBEDTLS_OID_SUBJECT_KEY_IDENTIFIER MBEDTLS_OID_ID_CE "\x0E" /**< id-ce-subjectKeyIdentifier OBJECT IDENTIFIER ::= { id-ce 14 } */ +#define MBEDTLS_OID_KEY_USAGE MBEDTLS_OID_ID_CE "\x0F" /**< id-ce-keyUsage OBJECT IDENTIFIER ::= { id-ce 15 } */ +#define MBEDTLS_OID_CERTIFICATE_POLICIES MBEDTLS_OID_ID_CE "\x20" /**< id-ce-certificatePolicies OBJECT IDENTIFIER ::= { id-ce 32 } */ +#define MBEDTLS_OID_POLICY_MAPPINGS MBEDTLS_OID_ID_CE "\x21" /**< id-ce-policyMappings OBJECT IDENTIFIER ::= { id-ce 33 } */ +#define MBEDTLS_OID_SUBJECT_ALT_NAME MBEDTLS_OID_ID_CE "\x11" /**< id-ce-subjectAltName OBJECT IDENTIFIER ::= { id-ce 17 } */ +#define MBEDTLS_OID_ISSUER_ALT_NAME MBEDTLS_OID_ID_CE "\x12" /**< id-ce-issuerAltName OBJECT IDENTIFIER ::= { id-ce 18 } */ +#define MBEDTLS_OID_SUBJECT_DIRECTORY_ATTRS MBEDTLS_OID_ID_CE "\x09" /**< id-ce-subjectDirectoryAttributes OBJECT IDENTIFIER ::= { id-ce 9 } */ +#define MBEDTLS_OID_BASIC_CONSTRAINTS MBEDTLS_OID_ID_CE "\x13" /**< id-ce-basicConstraints OBJECT IDENTIFIER ::= { id-ce 19 } */ +#define MBEDTLS_OID_NAME_CONSTRAINTS MBEDTLS_OID_ID_CE "\x1E" /**< id-ce-nameConstraints OBJECT IDENTIFIER ::= { id-ce 30 } */ +#define MBEDTLS_OID_POLICY_CONSTRAINTS MBEDTLS_OID_ID_CE "\x24" /**< id-ce-policyConstraints OBJECT IDENTIFIER ::= { id-ce 36 } */ +#define MBEDTLS_OID_EXTENDED_KEY_USAGE MBEDTLS_OID_ID_CE "\x25" /**< id-ce-extKeyUsage OBJECT IDENTIFIER ::= { id-ce 37 } */ +#define MBEDTLS_OID_CRL_DISTRIBUTION_POINTS MBEDTLS_OID_ID_CE "\x1F" /**< id-ce-cRLDistributionPoints OBJECT IDENTIFIER ::= { id-ce 31 } */ +#define MBEDTLS_OID_INIHIBIT_ANYPOLICY MBEDTLS_OID_ID_CE "\x36" /**< id-ce-inhibitAnyPolicy OBJECT IDENTIFIER ::= { id-ce 54 } */ +#define MBEDTLS_OID_FRESHEST_CRL MBEDTLS_OID_ID_CE "\x2E" /**< id-ce-freshestCRL OBJECT IDENTIFIER ::= { id-ce 46 } */ + +/* + * Netscape certificate extensions + */ +#define MBEDTLS_OID_NS_CERT MBEDTLS_OID_NETSCAPE "\x01" +#define MBEDTLS_OID_NS_CERT_TYPE MBEDTLS_OID_NS_CERT "\x01" +#define MBEDTLS_OID_NS_BASE_URL MBEDTLS_OID_NS_CERT "\x02" +#define MBEDTLS_OID_NS_REVOCATION_URL MBEDTLS_OID_NS_CERT "\x03" +#define MBEDTLS_OID_NS_CA_REVOCATION_URL MBEDTLS_OID_NS_CERT "\x04" +#define MBEDTLS_OID_NS_RENEWAL_URL MBEDTLS_OID_NS_CERT "\x07" +#define MBEDTLS_OID_NS_CA_POLICY_URL MBEDTLS_OID_NS_CERT "\x08" +#define MBEDTLS_OID_NS_SSL_SERVER_NAME MBEDTLS_OID_NS_CERT "\x0C" +#define MBEDTLS_OID_NS_COMMENT MBEDTLS_OID_NS_CERT "\x0D" +#define MBEDTLS_OID_NS_DATA_TYPE MBEDTLS_OID_NETSCAPE "\x02" +#define MBEDTLS_OID_NS_CERT_SEQUENCE MBEDTLS_OID_NS_DATA_TYPE "\x05" + +/* + * OIDs for CRL extensions + */ +#define MBEDTLS_OID_PRIVATE_KEY_USAGE_PERIOD MBEDTLS_OID_ID_CE "\x10" +#define MBEDTLS_OID_CRL_NUMBER MBEDTLS_OID_ID_CE "\x14" /**< id-ce-cRLNumber OBJECT IDENTIFIER ::= { id-ce 20 } */ + +/* + * X.509 v3 Extended key usage OIDs + */ +#define MBEDTLS_OID_ANY_EXTENDED_KEY_USAGE MBEDTLS_OID_EXTENDED_KEY_USAGE "\x00" /**< anyExtendedKeyUsage OBJECT IDENTIFIER ::= { id-ce-extKeyUsage 0 } */ + +#define MBEDTLS_OID_KP MBEDTLS_OID_PKIX "\x03" /**< id-kp OBJECT IDENTIFIER ::= { id-pkix 3 } */ +#define MBEDTLS_OID_SERVER_AUTH MBEDTLS_OID_KP "\x01" /**< id-kp-serverAuth OBJECT IDENTIFIER ::= { id-kp 1 } */ +#define MBEDTLS_OID_CLIENT_AUTH MBEDTLS_OID_KP "\x02" /**< id-kp-clientAuth OBJECT IDENTIFIER ::= { id-kp 2 } */ +#define MBEDTLS_OID_CODE_SIGNING MBEDTLS_OID_KP "\x03" /**< id-kp-codeSigning OBJECT IDENTIFIER ::= { id-kp 3 } */ +#define MBEDTLS_OID_EMAIL_PROTECTION MBEDTLS_OID_KP "\x04" /**< id-kp-emailProtection OBJECT IDENTIFIER ::= { id-kp 4 } */ +#define MBEDTLS_OID_TIME_STAMPING MBEDTLS_OID_KP "\x08" /**< id-kp-timeStamping OBJECT IDENTIFIER ::= { id-kp 8 } */ +#define MBEDTLS_OID_OCSP_SIGNING MBEDTLS_OID_KP "\x09" /**< id-kp-OCSPSigning OBJECT IDENTIFIER ::= { id-kp 9 } */ + +/* + * PKCS definition OIDs + */ + +#define MBEDTLS_OID_PKCS MBEDTLS_OID_RSA_COMPANY "\x01" /**< pkcs OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) 1 } */ +#define MBEDTLS_OID_PKCS1 MBEDTLS_OID_PKCS "\x01" /**< pkcs-1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 1 } */ +#define MBEDTLS_OID_PKCS5 MBEDTLS_OID_PKCS "\x05" /**< pkcs-5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 5 } */ +#define MBEDTLS_OID_PKCS9 MBEDTLS_OID_PKCS "\x09" /**< pkcs-9 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 9 } */ +#define MBEDTLS_OID_PKCS12 MBEDTLS_OID_PKCS "\x0c" /**< pkcs-12 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 12 } */ + +/* + * PKCS#1 OIDs + */ +#define MBEDTLS_OID_PKCS1_RSA MBEDTLS_OID_PKCS1 "\x01" /**< rsaEncryption OBJECT IDENTIFIER ::= { pkcs-1 1 } */ +#define MBEDTLS_OID_PKCS1_MD2 MBEDTLS_OID_PKCS1 "\x02" /**< md2WithRSAEncryption ::= { pkcs-1 2 } */ +#define MBEDTLS_OID_PKCS1_MD4 MBEDTLS_OID_PKCS1 "\x03" /**< md4WithRSAEncryption ::= { pkcs-1 3 } */ +#define MBEDTLS_OID_PKCS1_MD5 MBEDTLS_OID_PKCS1 "\x04" /**< md5WithRSAEncryption ::= { pkcs-1 4 } */ +#define MBEDTLS_OID_PKCS1_SHA1 MBEDTLS_OID_PKCS1 "\x05" /**< sha1WithRSAEncryption ::= { pkcs-1 5 } */ +#define MBEDTLS_OID_PKCS1_SHA224 MBEDTLS_OID_PKCS1 "\x0e" /**< sha224WithRSAEncryption ::= { pkcs-1 14 } */ +#define MBEDTLS_OID_PKCS1_SHA256 MBEDTLS_OID_PKCS1 "\x0b" /**< sha256WithRSAEncryption ::= { pkcs-1 11 } */ +#define MBEDTLS_OID_PKCS1_SHA384 MBEDTLS_OID_PKCS1 "\x0c" /**< sha384WithRSAEncryption ::= { pkcs-1 12 } */ +#define MBEDTLS_OID_PKCS1_SHA512 MBEDTLS_OID_PKCS1 "\x0d" /**< sha512WithRSAEncryption ::= { pkcs-1 13 } */ + +#define MBEDTLS_OID_RSA_SHA_OBS "\x2B\x0E\x03\x02\x1D" + +#define MBEDTLS_OID_PKCS9_EMAIL MBEDTLS_OID_PKCS9 "\x01" /**< emailAddress AttributeType ::= { pkcs-9 1 } */ + +/* RFC 4055 */ +#define MBEDTLS_OID_RSASSA_PSS MBEDTLS_OID_PKCS1 "\x0a" /**< id-RSASSA-PSS ::= { pkcs-1 10 } */ +#define MBEDTLS_OID_MGF1 MBEDTLS_OID_PKCS1 "\x08" /**< id-mgf1 ::= { pkcs-1 8 } */ + +/* + * Digest algorithms + */ +#define MBEDTLS_OID_DIGEST_ALG_MD2 MBEDTLS_OID_RSA_COMPANY "\x02\x02" /**< id-mbedtls_md2 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 2 } */ +#define MBEDTLS_OID_DIGEST_ALG_MD4 MBEDTLS_OID_RSA_COMPANY "\x02\x04" /**< id-mbedtls_md4 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 4 } */ +#define MBEDTLS_OID_DIGEST_ALG_MD5 MBEDTLS_OID_RSA_COMPANY "\x02\x05" /**< id-mbedtls_md5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 5 } */ +#define MBEDTLS_OID_DIGEST_ALG_SHA1 MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_OIW_SECSIG_SHA1 /**< id-mbedtls_sha1 OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 26 } */ +#define MBEDTLS_OID_DIGEST_ALG_SHA224 MBEDTLS_OID_NIST_ALG "\x02\x04" /**< id-sha224 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 4 } */ +#define MBEDTLS_OID_DIGEST_ALG_SHA256 MBEDTLS_OID_NIST_ALG "\x02\x01" /**< id-mbedtls_sha256 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 1 } */ + +#define MBEDTLS_OID_DIGEST_ALG_SHA384 MBEDTLS_OID_NIST_ALG "\x02\x02" /**< id-sha384 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 2 } */ + +#define MBEDTLS_OID_DIGEST_ALG_SHA512 MBEDTLS_OID_NIST_ALG "\x02\x03" /**< id-mbedtls_sha512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 3 } */ + +#define MBEDTLS_OID_HMAC_SHA1 MBEDTLS_OID_RSA_COMPANY "\x02\x07" /**< id-hmacWithSHA1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 7 } */ + +#define MBEDTLS_OID_HMAC_SHA224 MBEDTLS_OID_RSA_COMPANY "\x02\x08" /**< id-hmacWithSHA224 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 8 } */ + +#define MBEDTLS_OID_HMAC_SHA256 MBEDTLS_OID_RSA_COMPANY "\x02\x09" /**< id-hmacWithSHA256 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 9 } */ + +#define MBEDTLS_OID_HMAC_SHA384 MBEDTLS_OID_RSA_COMPANY "\x02\x0A" /**< id-hmacWithSHA384 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 10 } */ + +#define MBEDTLS_OID_HMAC_SHA512 MBEDTLS_OID_RSA_COMPANY "\x02\x0B" /**< id-hmacWithSHA512 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 11 } */ + +/* + * Encryption algorithms + */ +#define MBEDTLS_OID_DES_CBC MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_OIW_SECSIG_ALG "\x07" /**< desCBC OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 7 } */ +#define MBEDTLS_OID_DES_EDE3_CBC MBEDTLS_OID_RSA_COMPANY "\x03\x07" /**< des-ede3-cbc OBJECT IDENTIFIER ::= { iso(1) member-body(2) -- us(840) rsadsi(113549) encryptionAlgorithm(3) 7 } */ +#define MBEDTLS_OID_AES MBEDTLS_OID_NIST_ALG "\x01" /** aes OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithm(4) 1 } */ + +/* + * Key Wrapping algorithms + */ +/* + * RFC 5649 + */ +#define MBEDTLS_OID_AES128_KW MBEDTLS_OID_AES "\x05" /** id-aes128-wrap OBJECT IDENTIFIER ::= { aes 5 } */ +#define MBEDTLS_OID_AES128_KWP MBEDTLS_OID_AES "\x08" /** id-aes128-wrap-pad OBJECT IDENTIFIER ::= { aes 8 } */ +#define MBEDTLS_OID_AES192_KW MBEDTLS_OID_AES "\x19" /** id-aes192-wrap OBJECT IDENTIFIER ::= { aes 25 } */ +#define MBEDTLS_OID_AES192_KWP MBEDTLS_OID_AES "\x1c" /** id-aes192-wrap-pad OBJECT IDENTIFIER ::= { aes 28 } */ +#define MBEDTLS_OID_AES256_KW MBEDTLS_OID_AES "\x2d" /** id-aes256-wrap OBJECT IDENTIFIER ::= { aes 45 } */ +#define MBEDTLS_OID_AES256_KWP MBEDTLS_OID_AES "\x30" /** id-aes256-wrap-pad OBJECT IDENTIFIER ::= { aes 48 } */ +/* + * PKCS#5 OIDs + */ +#define MBEDTLS_OID_PKCS5_PBKDF2 MBEDTLS_OID_PKCS5 "\x0c" /**< id-PBKDF2 OBJECT IDENTIFIER ::= {pkcs-5 12} */ +#define MBEDTLS_OID_PKCS5_PBES2 MBEDTLS_OID_PKCS5 "\x0d" /**< id-PBES2 OBJECT IDENTIFIER ::= {pkcs-5 13} */ +#define MBEDTLS_OID_PKCS5_PBMAC1 MBEDTLS_OID_PKCS5 "\x0e" /**< id-PBMAC1 OBJECT IDENTIFIER ::= {pkcs-5 14} */ + +/* + * PKCS#5 PBES1 algorithms + */ +#define MBEDTLS_OID_PKCS5_PBE_MD2_DES_CBC MBEDTLS_OID_PKCS5 "\x01" /**< pbeWithMD2AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 1} */ +#define MBEDTLS_OID_PKCS5_PBE_MD2_RC2_CBC MBEDTLS_OID_PKCS5 "\x04" /**< pbeWithMD2AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 4} */ +#define MBEDTLS_OID_PKCS5_PBE_MD5_DES_CBC MBEDTLS_OID_PKCS5 "\x03" /**< pbeWithMD5AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 3} */ +#define MBEDTLS_OID_PKCS5_PBE_MD5_RC2_CBC MBEDTLS_OID_PKCS5 "\x06" /**< pbeWithMD5AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 6} */ +#define MBEDTLS_OID_PKCS5_PBE_SHA1_DES_CBC MBEDTLS_OID_PKCS5 "\x0a" /**< pbeWithSHA1AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 10} */ +#define MBEDTLS_OID_PKCS5_PBE_SHA1_RC2_CBC MBEDTLS_OID_PKCS5 "\x0b" /**< pbeWithSHA1AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 11} */ + +/* + * PKCS#8 OIDs + */ +#define MBEDTLS_OID_PKCS9_CSR_EXT_REQ MBEDTLS_OID_PKCS9 "\x0e" /**< extensionRequest OBJECT IDENTIFIER ::= {pkcs-9 14} */ + +/* + * PKCS#12 PBE OIDs + */ +#define MBEDTLS_OID_PKCS12_PBE MBEDTLS_OID_PKCS12 "\x01" /**< pkcs-12PbeIds OBJECT IDENTIFIER ::= {pkcs-12 1} */ + +#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_128 MBEDTLS_OID_PKCS12_PBE "\x01" /**< pbeWithSHAAnd128BitRC4 OBJECT IDENTIFIER ::= {pkcs-12PbeIds 1} */ +#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_40 MBEDTLS_OID_PKCS12_PBE "\x02" /**< pbeWithSHAAnd40BitRC4 OBJECT IDENTIFIER ::= {pkcs-12PbeIds 2} */ +#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES3_EDE_CBC MBEDTLS_OID_PKCS12_PBE "\x03" /**< pbeWithSHAAnd3-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 3} */ +#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES2_EDE_CBC MBEDTLS_OID_PKCS12_PBE "\x04" /**< pbeWithSHAAnd2-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 4} */ +#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_128_CBC MBEDTLS_OID_PKCS12_PBE "\x05" /**< pbeWithSHAAnd128BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 5} */ +#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_40_CBC MBEDTLS_OID_PKCS12_PBE "\x06" /**< pbeWithSHAAnd40BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 6} */ + +/* + * EC key algorithms from RFC 5480 + */ + +/* id-ecPublicKey OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) keyType(2) 1 } */ +#define MBEDTLS_OID_EC_ALG_UNRESTRICTED MBEDTLS_OID_ANSI_X9_62 "\x02\01" + +/* id-ecDH OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) + * schemes(1) ecdh(12) } */ +#define MBEDTLS_OID_EC_ALG_ECDH MBEDTLS_OID_CERTICOM "\x01\x0c" + +/* + * ECParameters namedCurve identifiers, from RFC 5480, RFC 5639, and SEC2 + */ + +/* secp192r1 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 1 } */ +#define MBEDTLS_OID_EC_GRP_SECP192R1 MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x01" + +/* secp224r1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 33 } */ +#define MBEDTLS_OID_EC_GRP_SECP224R1 MBEDTLS_OID_CERTICOM "\x00\x21" + +/* secp256r1 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 7 } */ +#define MBEDTLS_OID_EC_GRP_SECP256R1 MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x07" + +/* secp384r1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 34 } */ +#define MBEDTLS_OID_EC_GRP_SECP384R1 MBEDTLS_OID_CERTICOM "\x00\x22" + +/* secp521r1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 35 } */ +#define MBEDTLS_OID_EC_GRP_SECP521R1 MBEDTLS_OID_CERTICOM "\x00\x23" + +/* secp192k1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 31 } */ +#define MBEDTLS_OID_EC_GRP_SECP192K1 MBEDTLS_OID_CERTICOM "\x00\x1f" + +/* secp224k1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 32 } */ +#define MBEDTLS_OID_EC_GRP_SECP224K1 MBEDTLS_OID_CERTICOM "\x00\x20" + +/* secp256k1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 10 } */ +#define MBEDTLS_OID_EC_GRP_SECP256K1 MBEDTLS_OID_CERTICOM "\x00\x0a" + +/* RFC 5639 4.1 + * ecStdCurvesAndGeneration OBJECT IDENTIFIER::= {iso(1) + * identified-organization(3) teletrust(36) algorithm(3) signature- + * algorithm(3) ecSign(2) 8} + * ellipticCurve OBJECT IDENTIFIER ::= {ecStdCurvesAndGeneration 1} + * versionOne OBJECT IDENTIFIER ::= {ellipticCurve 1} */ +#define MBEDTLS_OID_EC_BRAINPOOL_V1 MBEDTLS_OID_TELETRUST "\x03\x03\x02\x08\x01\x01" + +/* brainpoolP256r1 OBJECT IDENTIFIER ::= {versionOne 7} */ +#define MBEDTLS_OID_EC_GRP_BP256R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x07" + +/* brainpoolP384r1 OBJECT IDENTIFIER ::= {versionOne 11} */ +#define MBEDTLS_OID_EC_GRP_BP384R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0B" + +/* brainpoolP512r1 OBJECT IDENTIFIER ::= {versionOne 13} */ +#define MBEDTLS_OID_EC_GRP_BP512R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0D" + +/* + * SEC1 C.1 + * + * prime-field OBJECT IDENTIFIER ::= { id-fieldType 1 } + * id-fieldType OBJECT IDENTIFIER ::= { ansi-X9-62 fieldType(1)} + */ +#define MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE MBEDTLS_OID_ANSI_X9_62 "\x01" +#define MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE "\x01" + +/* + * ECDSA signature identifiers, from RFC 5480 + */ +#define MBEDTLS_OID_ANSI_X9_62_SIG MBEDTLS_OID_ANSI_X9_62 "\x04" /* signatures(4) */ +#define MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 MBEDTLS_OID_ANSI_X9_62_SIG "\x03" /* ecdsa-with-SHA2(3) */ + +/* ecdsa-with-SHA1 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) 1 } */ +#define MBEDTLS_OID_ECDSA_SHA1 MBEDTLS_OID_ANSI_X9_62_SIG "\x01" + +/* ecdsa-with-SHA224 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) + * ecdsa-with-SHA2(3) 1 } */ +#define MBEDTLS_OID_ECDSA_SHA224 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x01" + +/* ecdsa-with-SHA256 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) + * ecdsa-with-SHA2(3) 2 } */ +#define MBEDTLS_OID_ECDSA_SHA256 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x02" + +/* ecdsa-with-SHA384 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) + * ecdsa-with-SHA2(3) 3 } */ +#define MBEDTLS_OID_ECDSA_SHA384 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x03" + +/* ecdsa-with-SHA512 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) + * ecdsa-with-SHA2(3) 4 } */ +#define MBEDTLS_OID_ECDSA_SHA512 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x04" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Base OID descriptor structure + */ +typedef struct mbedtls_oid_descriptor_t +{ + const char *asn1; /*!< OID ASN.1 representation */ + size_t asn1_len; /*!< length of asn1 */ + const char *name; /*!< official name (e.g. from RFC) */ + const char *description; /*!< human friendly description */ +} mbedtls_oid_descriptor_t; + +/** + * \brief Translate an ASN.1 OID into its numeric representation + * (e.g. "\x2A\x86\x48\x86\xF7\x0D" into "1.2.840.113549") + * + * \param buf buffer to put representation in + * \param size size of the buffer + * \param oid OID to translate + * + * \return Length of the string written (excluding final NULL) or + * MBEDTLS_ERR_OID_BUF_TOO_SMALL in case of error + */ +int mbedtls_oid_get_numeric_string( char *buf, size_t size, const mbedtls_asn1_buf *oid ); + +#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C) +/** + * \brief Translate an X.509 extension OID into local values + * + * \param oid OID to use + * \param ext_type place to store the extension type + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_x509_ext_type( const mbedtls_asn1_buf *oid, int *ext_type ); +#endif + +/** + * \brief Translate an X.509 attribute type OID into the short name + * (e.g. the OID for an X520 Common Name into "CN") + * + * \param oid OID to use + * \param short_name place to store the string pointer + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_attr_short_name( const mbedtls_asn1_buf *oid, const char **short_name ); + +/** + * \brief Translate PublicKeyAlgorithm OID into pk_type + * + * \param oid OID to use + * \param pk_alg place to store public key algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_pk_alg( const mbedtls_asn1_buf *oid, mbedtls_pk_type_t *pk_alg ); + +/** + * \brief Translate pk_type into PublicKeyAlgorithm OID + * + * \param pk_alg Public key type to look for + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_pk_alg( mbedtls_pk_type_t pk_alg, + const char **oid, size_t *olen ); + +#if defined(MBEDTLS_ECP_C) +/** + * \brief Translate NamedCurve OID into an EC group identifier + * + * \param oid OID to use + * \param grp_id place to store group id + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_ec_grp( const mbedtls_asn1_buf *oid, mbedtls_ecp_group_id *grp_id ); + +/** + * \brief Translate EC group identifier into NamedCurve OID + * + * \param grp_id EC group identifier + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_ec_grp( mbedtls_ecp_group_id grp_id, + const char **oid, size_t *olen ); +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_MD_C) +/** + * \brief Translate SignatureAlgorithm OID into md_type and pk_type + * + * \param oid OID to use + * \param md_alg place to store message digest algorithm + * \param pk_alg place to store public key algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_sig_alg( const mbedtls_asn1_buf *oid, + mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg ); + +/** + * \brief Translate SignatureAlgorithm OID into description + * + * \param oid OID to use + * \param desc place to store string pointer + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_sig_alg_desc( const mbedtls_asn1_buf *oid, const char **desc ); + +/** + * \brief Translate md_type and pk_type into SignatureAlgorithm OID + * + * \param md_alg message digest algorithm + * \param pk_alg public key algorithm + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_sig_alg( mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg, + const char **oid, size_t *olen ); + +/** + * \brief Translate hash algorithm OID into md_type + * + * \param oid OID to use + * \param md_alg place to store message digest algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_md_alg( const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg ); + +/** + * \brief Translate hmac algorithm OID into md_type + * + * \param oid OID to use + * \param md_hmac place to store message hmac algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_md_hmac( const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_hmac ); +#endif /* MBEDTLS_MD_C */ + +/** + * \brief Translate Extended Key Usage OID into description + * + * \param oid OID to use + * \param desc place to store string pointer + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_extended_key_usage( const mbedtls_asn1_buf *oid, const char **desc ); + +/** + * \brief Translate md_type into hash algorithm OID + * + * \param md_alg message digest algorithm + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_md( mbedtls_md_type_t md_alg, const char **oid, size_t *olen ); + +#if defined(MBEDTLS_CIPHER_C) +/** + * \brief Translate encryption algorithm OID into cipher_type + * + * \param oid OID to use + * \param cipher_alg place to store cipher algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_cipher_alg( const mbedtls_asn1_buf *oid, mbedtls_cipher_type_t *cipher_alg ); +#endif /* MBEDTLS_CIPHER_C */ + +#if defined(MBEDTLS_PKCS12_C) +/** + * \brief Translate PKCS#12 PBE algorithm OID into md_type and + * cipher_type + * + * \param oid OID to use + * \param md_alg place to store message digest algorithm + * \param cipher_alg place to store cipher algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_pkcs12_pbe_alg( const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg, + mbedtls_cipher_type_t *cipher_alg ); +#endif /* MBEDTLS_PKCS12_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* oid.h */ diff --git a/src/common/mbedtls/include/mbedtls/pem.h b/src/common/mbedtls/include/mbedtls/pem.h new file mode 100644 index 0000000000..6909d15b1a --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/pem.h @@ -0,0 +1,156 @@ +/** + * \file pem.h + * + * \brief Privacy Enhanced Mail (PEM) decoding + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_PEM_H +#define MBEDTLS_PEM_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include + +/** + * \name PEM Error codes + * These error codes are returned in case of errors reading the + * PEM data. + * \{ + */ +#define MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT -0x1080 /**< No PEM header or footer found. */ +#define MBEDTLS_ERR_PEM_INVALID_DATA -0x1100 /**< PEM string is not as expected. */ +#define MBEDTLS_ERR_PEM_ALLOC_FAILED -0x1180 /**< Failed to allocate memory. */ +#define MBEDTLS_ERR_PEM_INVALID_ENC_IV -0x1200 /**< RSA IV is not in hex-format. */ +#define MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG -0x1280 /**< Unsupported key encryption algorithm. */ +#define MBEDTLS_ERR_PEM_PASSWORD_REQUIRED -0x1300 /**< Private key password can't be empty. */ +#define MBEDTLS_ERR_PEM_PASSWORD_MISMATCH -0x1380 /**< Given private key password does not allow for correct decryption. */ +#define MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE -0x1400 /**< Unavailable feature, e.g. hashing/encryption combination. */ +#define MBEDTLS_ERR_PEM_BAD_INPUT_DATA -0x1480 /**< Bad input parameters to function. */ +/* \} name */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) +/** + * \brief PEM context structure + */ +typedef struct mbedtls_pem_context +{ + unsigned char *buf; /*!< buffer for decoded data */ + size_t buflen; /*!< length of the buffer */ + unsigned char *info; /*!< buffer for extra header information */ +} +mbedtls_pem_context; + +/** + * \brief PEM context setup + * + * \param ctx context to be initialized + */ +void mbedtls_pem_init( mbedtls_pem_context *ctx ); + +/** + * \brief Read a buffer for PEM information and store the resulting + * data into the specified context buffers. + * + * \param ctx context to use + * \param header header string to seek and expect + * \param footer footer string to seek and expect + * \param data source data to look in (must be nul-terminated) + * \param pwd password for decryption (can be NULL) + * \param pwdlen length of password + * \param use_len destination for total length used (set after header is + * correctly read, so unless you get + * MBEDTLS_ERR_PEM_BAD_INPUT_DATA or + * MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT, use_len is + * the length to skip) + * + * \note Attempts to check password correctness by verifying if + * the decrypted text starts with an ASN.1 sequence of + * appropriate length + * + * \return 0 on success, or a specific PEM error code + */ +int mbedtls_pem_read_buffer( mbedtls_pem_context *ctx, const char *header, const char *footer, + const unsigned char *data, + const unsigned char *pwd, + size_t pwdlen, size_t *use_len ); + +/** + * \brief PEM context memory freeing + * + * \param ctx context to be freed + */ +void mbedtls_pem_free( mbedtls_pem_context *ctx ); +#endif /* MBEDTLS_PEM_PARSE_C */ + +#if defined(MBEDTLS_PEM_WRITE_C) +/** + * \brief Write a buffer of PEM information from a DER encoded + * buffer. + * + * \param header The header string to write. + * \param footer The footer string to write. + * \param der_data The DER data to encode. + * \param der_len The length of the DER data \p der_data in Bytes. + * \param buf The buffer to write to. + * \param buf_len The length of the output buffer \p buf in Bytes. + * \param olen The address at which to store the total length written + * or required (if \p buf_len is not enough). + * + * \note You may pass \c NULL for \p buf and \c 0 for \p buf_len + * to request the length of the resulting PEM buffer in + * `*olen`. + * + * \note This function may be called with overlapping \p der_data + * and \p buf buffers. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL if \p buf isn't large + * enough to hold the PEM buffer. In this case, `*olen` holds + * the required minimum size of \p buf. + * \return Another PEM or BASE64 error code on other kinds of failure. + */ +int mbedtls_pem_write_buffer( const char *header, const char *footer, + const unsigned char *der_data, size_t der_len, + unsigned char *buf, size_t buf_len, size_t *olen ); +#endif /* MBEDTLS_PEM_WRITE_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* pem.h */ diff --git a/src/common/mbedtls/include/mbedtls/pk.h b/src/common/mbedtls/include/mbedtls/pk.h new file mode 100644 index 0000000000..c8b0aa841f --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/pk.h @@ -0,0 +1,765 @@ +/** + * \file pk.h + * + * \brief Public Key abstraction layer + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_PK_H +#define MBEDTLS_PK_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "md.h" + +#if defined(MBEDTLS_RSA_C) +#include "rsa.h" +#endif + +#if defined(MBEDTLS_ECP_C) +#include "ecp.h" +#endif + +#if defined(MBEDTLS_ECDSA_C) +#include "ecdsa.h" +#endif + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +#define MBEDTLS_ERR_PK_ALLOC_FAILED -0x3F80 /**< Memory allocation failed. */ +#define MBEDTLS_ERR_PK_TYPE_MISMATCH -0x3F00 /**< Type mismatch, eg attempt to encrypt with an ECDSA key */ +#define MBEDTLS_ERR_PK_BAD_INPUT_DATA -0x3E80 /**< Bad input parameters to function. */ +#define MBEDTLS_ERR_PK_FILE_IO_ERROR -0x3E00 /**< Read/write of file failed. */ +#define MBEDTLS_ERR_PK_KEY_INVALID_VERSION -0x3D80 /**< Unsupported key version */ +#define MBEDTLS_ERR_PK_KEY_INVALID_FORMAT -0x3D00 /**< Invalid key tag or value. */ +#define MBEDTLS_ERR_PK_UNKNOWN_PK_ALG -0x3C80 /**< Key algorithm is unsupported (only RSA and EC are supported). */ +#define MBEDTLS_ERR_PK_PASSWORD_REQUIRED -0x3C00 /**< Private key password can't be empty. */ +#define MBEDTLS_ERR_PK_PASSWORD_MISMATCH -0x3B80 /**< Given private key password does not allow for correct decryption. */ +#define MBEDTLS_ERR_PK_INVALID_PUBKEY -0x3B00 /**< The pubkey tag or value is invalid (only RSA and EC are supported). */ +#define MBEDTLS_ERR_PK_INVALID_ALG -0x3A80 /**< The algorithm tag or value is invalid. */ +#define MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE -0x3A00 /**< Elliptic curve is unsupported (only NIST curves are supported). */ +#define MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE -0x3980 /**< Unavailable feature, e.g. RSA disabled for RSA key. */ +#define MBEDTLS_ERR_PK_SIG_LEN_MISMATCH -0x3900 /**< The buffer contains a valid signature followed by more data. */ + +/* MBEDTLS_ERR_PK_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_PK_HW_ACCEL_FAILED -0x3880 /**< PK hardware accelerator failed. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Public key types + */ +typedef enum { + MBEDTLS_PK_NONE=0, + MBEDTLS_PK_RSA, + MBEDTLS_PK_ECKEY, + MBEDTLS_PK_ECKEY_DH, + MBEDTLS_PK_ECDSA, + MBEDTLS_PK_RSA_ALT, + MBEDTLS_PK_RSASSA_PSS, +} mbedtls_pk_type_t; + +/** + * \brief Options for RSASSA-PSS signature verification. + * See \c mbedtls_rsa_rsassa_pss_verify_ext() + */ +typedef struct mbedtls_pk_rsassa_pss_options +{ + mbedtls_md_type_t mgf1_hash_id; + int expected_salt_len; + +} mbedtls_pk_rsassa_pss_options; + +/** + * \brief Types for interfacing with the debug module + */ +typedef enum +{ + MBEDTLS_PK_DEBUG_NONE = 0, + MBEDTLS_PK_DEBUG_MPI, + MBEDTLS_PK_DEBUG_ECP, +} mbedtls_pk_debug_type; + +/** + * \brief Item to send to the debug module + */ +typedef struct mbedtls_pk_debug_item +{ + mbedtls_pk_debug_type type; + const char *name; + void *value; +} mbedtls_pk_debug_item; + +/** Maximum number of item send for debugging, plus 1 */ +#define MBEDTLS_PK_DEBUG_MAX_ITEMS 3 + +/** + * \brief Public key information and operations + */ +typedef struct mbedtls_pk_info_t mbedtls_pk_info_t; + +/** + * \brief Public key container + */ +typedef struct mbedtls_pk_context +{ + const mbedtls_pk_info_t * pk_info; /**< Public key information */ + void * pk_ctx; /**< Underlying public key context */ +} mbedtls_pk_context; + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Context for resuming operations + */ +typedef struct +{ + const mbedtls_pk_info_t * pk_info; /**< Public key information */ + void * rs_ctx; /**< Underlying restart context */ +} mbedtls_pk_restart_ctx; +#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ +/* Now we can declare functions that take a pointer to that */ +typedef void mbedtls_pk_restart_ctx; +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +#if defined(MBEDTLS_RSA_C) +/** + * Quick access to an RSA context inside a PK context. + * + * \warning You must make sure the PK context actually holds an RSA context + * before using this function! + */ +static inline mbedtls_rsa_context *mbedtls_pk_rsa( const mbedtls_pk_context pk ) +{ + return( (mbedtls_rsa_context *) (pk).pk_ctx ); +} +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_ECP_C) +/** + * Quick access to an EC context inside a PK context. + * + * \warning You must make sure the PK context actually holds an EC context + * before using this function! + */ +static inline mbedtls_ecp_keypair *mbedtls_pk_ec( const mbedtls_pk_context pk ) +{ + return( (mbedtls_ecp_keypair *) (pk).pk_ctx ); +} +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +/** + * \brief Types for RSA-alt abstraction + */ +typedef int (*mbedtls_pk_rsa_alt_decrypt_func)( void *ctx, int mode, size_t *olen, + const unsigned char *input, unsigned char *output, + size_t output_max_len ); +typedef int (*mbedtls_pk_rsa_alt_sign_func)( void *ctx, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + int mode, mbedtls_md_type_t md_alg, unsigned int hashlen, + const unsigned char *hash, unsigned char *sig ); +typedef size_t (*mbedtls_pk_rsa_alt_key_len_func)( void *ctx ); +#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ + +/** + * \brief Return information associated with the given PK type + * + * \param pk_type PK type to search for. + * + * \return The PK info associated with the type or NULL if not found. + */ +const mbedtls_pk_info_t *mbedtls_pk_info_from_type( mbedtls_pk_type_t pk_type ); + +/** + * \brief Initialize a #mbedtls_pk_context (as NONE). + * + * \param ctx The context to initialize. + * This must not be \c NULL. + */ +void mbedtls_pk_init( mbedtls_pk_context *ctx ); + +/** + * \brief Free the components of a #mbedtls_pk_context. + * + * \param ctx The context to clear. It must have been initialized. + * If this is \c NULL, this function does nothing. + */ +void mbedtls_pk_free( mbedtls_pk_context *ctx ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Initialize a restart context + * + * \param ctx The context to initialize. + * This must not be \c NULL. + */ +void mbedtls_pk_restart_init( mbedtls_pk_restart_ctx *ctx ); + +/** + * \brief Free the components of a restart context + * + * \param ctx The context to clear. It must have been initialized. + * If this is \c NULL, this function does nothing. + */ +void mbedtls_pk_restart_free( mbedtls_pk_restart_ctx *ctx ); +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief Initialize a PK context with the information given + * and allocates the type-specific PK subcontext. + * + * \param ctx Context to initialize. It must not have been set + * up yet (type #MBEDTLS_PK_NONE). + * \param info Information to use + * + * \return 0 on success, + * MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input, + * MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure. + * + * \note For contexts holding an RSA-alt key, use + * \c mbedtls_pk_setup_rsa_alt() instead. + */ +int mbedtls_pk_setup( mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info ); + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +/** + * \brief Initialize an RSA-alt context + * + * \param ctx Context to initialize. It must not have been set + * up yet (type #MBEDTLS_PK_NONE). + * \param key RSA key pointer + * \param decrypt_func Decryption function + * \param sign_func Signing function + * \param key_len_func Function returning key length in bytes + * + * \return 0 on success, or MBEDTLS_ERR_PK_BAD_INPUT_DATA if the + * context wasn't already initialized as RSA_ALT. + * + * \note This function replaces \c mbedtls_pk_setup() for RSA-alt. + */ +int mbedtls_pk_setup_rsa_alt( mbedtls_pk_context *ctx, void * key, + mbedtls_pk_rsa_alt_decrypt_func decrypt_func, + mbedtls_pk_rsa_alt_sign_func sign_func, + mbedtls_pk_rsa_alt_key_len_func key_len_func ); +#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ + +/** + * \brief Get the size in bits of the underlying key + * + * \param ctx The context to query. It must have been initialized. + * + * \return Key size in bits, or 0 on error + */ +size_t mbedtls_pk_get_bitlen( const mbedtls_pk_context *ctx ); + +/** + * \brief Get the length in bytes of the underlying key + * + * \param ctx The context to query. It must have been initialized. + * + * \return Key length in bytes, or 0 on error + */ +static inline size_t mbedtls_pk_get_len( const mbedtls_pk_context *ctx ) +{ + return( ( mbedtls_pk_get_bitlen( ctx ) + 7 ) / 8 ); +} + +/** + * \brief Tell if a context can do the operation given by type + * + * \param ctx The context to query. It must have been initialized. + * \param type The desired type. + * + * \return 1 if the context can do operations on the given type. + * \return 0 if the context cannot do the operations on the given + * type. This is always the case for a context that has + * been initialized but not set up, or that has been + * cleared with mbedtls_pk_free(). + */ +int mbedtls_pk_can_do( const mbedtls_pk_context *ctx, mbedtls_pk_type_t type ); + +/** + * \brief Verify signature (including padding if relevant). + * + * \param ctx The PK context to use. It must have been set up. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length or 0 (see notes) + * \param sig Signature to verify + * \param sig_len Signature length + * + * \return 0 on success (signature is valid), + * #MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if there is a valid + * signature in sig but its length is less than \p siglen, + * or a specific error code. + * + * \note For RSA keys, the default padding type is PKCS#1 v1.5. + * Use \c mbedtls_pk_verify_ext( MBEDTLS_PK_RSASSA_PSS, ... ) + * to verify RSASSA_PSS signatures. + * + * \note If hash_len is 0, then the length associated with md_alg + * is used instead, or an error returned if it is invalid. + * + * \note md_alg may be MBEDTLS_MD_NONE, only if hash_len != 0 + */ +int mbedtls_pk_verify( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ); + +/** + * \brief Restartable version of \c mbedtls_pk_verify() + * + * \note Performs the same job as \c mbedtls_pk_verify(), but can + * return early and restart according to the limit set with + * \c mbedtls_ecp_set_max_ops() to reduce blocking for ECC + * operations. For RSA, same as \c mbedtls_pk_verify(). + * + * \param ctx The PK context to use. It must have been set up. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length or 0 (see notes) + * \param sig Signature to verify + * \param sig_len Signature length + * \param rs_ctx Restart context (NULL to disable restart) + * + * \return See \c mbedtls_pk_verify(), or + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + */ +int mbedtls_pk_verify_restartable( mbedtls_pk_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len, + mbedtls_pk_restart_ctx *rs_ctx ); + +/** + * \brief Verify signature, with options. + * (Includes verification of the padding depending on type.) + * + * \param type Signature type (inc. possible padding type) to verify + * \param options Pointer to type-specific options, or NULL + * \param ctx The PK context to use. It must have been set up. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length or 0 (see notes) + * \param sig Signature to verify + * \param sig_len Signature length + * + * \return 0 on success (signature is valid), + * #MBEDTLS_ERR_PK_TYPE_MISMATCH if the PK context can't be + * used for this type of signatures, + * #MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if there is a valid + * signature in sig but its length is less than \p siglen, + * or a specific error code. + * + * \note If hash_len is 0, then the length associated with md_alg + * is used instead, or an error returned if it is invalid. + * + * \note md_alg may be MBEDTLS_MD_NONE, only if hash_len != 0 + * + * \note If type is MBEDTLS_PK_RSASSA_PSS, then options must point + * to a mbedtls_pk_rsassa_pss_options structure, + * otherwise it must be NULL. + */ +int mbedtls_pk_verify_ext( mbedtls_pk_type_t type, const void *options, + mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ); + +/** + * \brief Make signature, including padding if relevant. + * + * \param ctx The PK context to use. It must have been set up + * with a private key. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length or 0 (see notes) + * \param sig Place to write the signature + * \param sig_len Number of bytes written + * \param f_rng RNG function + * \param p_rng RNG parameter + * + * \return 0 on success, or a specific error code. + * + * \note For RSA keys, the default padding type is PKCS#1 v1.5. + * There is no interface in the PK module to make RSASSA-PSS + * signatures yet. + * + * \note If hash_len is 0, then the length associated with md_alg + * is used instead, or an error returned if it is invalid. + * + * \note For RSA, md_alg may be MBEDTLS_MD_NONE if hash_len != 0. + * For ECDSA, md_alg may never be MBEDTLS_MD_NONE. + * + * \note In order to ensure enough space for the signature, the + * \p sig buffer size must be of at least + * `max(MBEDTLS_ECDSA_MAX_LEN, MBEDTLS_MPI_MAX_SIZE)` bytes. + */ +int mbedtls_pk_sign( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); + +/** + * \brief Restartable version of \c mbedtls_pk_sign() + * + * \note Performs the same job as \c mbedtls_pk_sign(), but can + * return early and restart according to the limit set with + * \c mbedtls_ecp_set_max_ops() to reduce blocking for ECC + * operations. For RSA, same as \c mbedtls_pk_sign(). + * + * \note In order to ensure enough space for the signature, the + * \p sig buffer size must be of at least + * `max(MBEDTLS_ECDSA_MAX_LEN, MBEDTLS_MPI_MAX_SIZE)` bytes. + * + * \param ctx The PK context to use. It must have been set up + * with a private key. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length or 0 (see notes) + * \param sig Place to write the signature + * \param sig_len Number of bytes written + * \param f_rng RNG function + * \param p_rng RNG parameter + * \param rs_ctx Restart context (NULL to disable restart) + * + * \return See \c mbedtls_pk_sign(), or + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + */ +int mbedtls_pk_sign_restartable( mbedtls_pk_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_pk_restart_ctx *rs_ctx ); + +/** + * \brief Decrypt message (including padding if relevant). + * + * \param ctx The PK context to use. It must have been set up + * with a private key. + * \param input Input to decrypt + * \param ilen Input size + * \param output Decrypted output + * \param olen Decrypted message length + * \param osize Size of the output buffer + * \param f_rng RNG function + * \param p_rng RNG parameter + * + * \note For RSA keys, the default padding type is PKCS#1 v1.5. + * + * \return 0 on success, or a specific error code. + */ +int mbedtls_pk_decrypt( mbedtls_pk_context *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); + +/** + * \brief Encrypt message (including padding if relevant). + * + * \param ctx The PK context to use. It must have been set up. + * \param input Message to encrypt + * \param ilen Message size + * \param output Encrypted output + * \param olen Encrypted output length + * \param osize Size of the output buffer + * \param f_rng RNG function + * \param p_rng RNG parameter + * + * \note For RSA keys, the default padding type is PKCS#1 v1.5. + * + * \return 0 on success, or a specific error code. + */ +int mbedtls_pk_encrypt( mbedtls_pk_context *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); + +/** + * \brief Check if a public-private pair of keys matches. + * + * \param pub Context holding a public key. + * \param prv Context holding a private (and public) key. + * + * \return 0 on success or MBEDTLS_ERR_PK_BAD_INPUT_DATA + */ +int mbedtls_pk_check_pair( const mbedtls_pk_context *pub, const mbedtls_pk_context *prv ); + +/** + * \brief Export debug information + * + * \param ctx The PK context to use. It must have been initialized. + * \param items Place to write debug items + * + * \return 0 on success or MBEDTLS_ERR_PK_BAD_INPUT_DATA + */ +int mbedtls_pk_debug( const mbedtls_pk_context *ctx, mbedtls_pk_debug_item *items ); + +/** + * \brief Access the type name + * + * \param ctx The PK context to use. It must have been initialized. + * + * \return Type name on success, or "invalid PK" + */ +const char * mbedtls_pk_get_name( const mbedtls_pk_context *ctx ); + +/** + * \brief Get the key type + * + * \param ctx The PK context to use. It must have been initialized. + * + * \return Type on success. + * \return #MBEDTLS_PK_NONE for a context that has not been set up. + */ +mbedtls_pk_type_t mbedtls_pk_get_type( const mbedtls_pk_context *ctx ); + +#if defined(MBEDTLS_PK_PARSE_C) +/** \ingroup pk_module */ +/** + * \brief Parse a private key in PEM or DER format + * + * \param ctx The PK context to fill. It must have been initialized + * but not set up. + * \param key Input buffer to parse. + * The buffer must contain the input exactly, with no + * extra trailing material. For PEM, the buffer must + * contain a null-terminated string. + * \param keylen Size of \b key in bytes. + * For PEM data, this includes the terminating null byte, + * so \p keylen must be equal to `strlen(key) + 1`. + * \param pwd Optional password for decryption. + * Pass \c NULL if expecting a non-encrypted key. + * Pass a string of \p pwdlen bytes if expecting an encrypted + * key; a non-encrypted key will also be accepted. + * The empty password is not supported. + * \param pwdlen Size of the password in bytes. + * Ignored if \p pwd is \c NULL. + * + * \note On entry, ctx must be empty, either freshly initialised + * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a + * specific key type, check the result with mbedtls_pk_can_do(). + * + * \note The key is also checked for correctness. + * + * \return 0 if successful, or a specific PK or PEM error code + */ +int mbedtls_pk_parse_key( mbedtls_pk_context *ctx, + const unsigned char *key, size_t keylen, + const unsigned char *pwd, size_t pwdlen ); + +/** \ingroup pk_module */ +/** + * \brief Parse a public key in PEM or DER format + * + * \param ctx The PK context to fill. It must have been initialized + * but not set up. + * \param key Input buffer to parse. + * The buffer must contain the input exactly, with no + * extra trailing material. For PEM, the buffer must + * contain a null-terminated string. + * \param keylen Size of \b key in bytes. + * For PEM data, this includes the terminating null byte, + * so \p keylen must be equal to `strlen(key) + 1`. + * + * \note On entry, ctx must be empty, either freshly initialised + * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a + * specific key type, check the result with mbedtls_pk_can_do(). + * + * \note The key is also checked for correctness. + * + * \return 0 if successful, or a specific PK or PEM error code + */ +int mbedtls_pk_parse_public_key( mbedtls_pk_context *ctx, + const unsigned char *key, size_t keylen ); + +#if defined(MBEDTLS_FS_IO) +/** \ingroup pk_module */ +/** + * \brief Load and parse a private key + * + * \param ctx The PK context to fill. It must have been initialized + * but not set up. + * \param path filename to read the private key from + * \param password Optional password to decrypt the file. + * Pass \c NULL if expecting a non-encrypted key. + * Pass a null-terminated string if expecting an encrypted + * key; a non-encrypted key will also be accepted. + * The empty password is not supported. + * + * \note On entry, ctx must be empty, either freshly initialised + * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a + * specific key type, check the result with mbedtls_pk_can_do(). + * + * \note The key is also checked for correctness. + * + * \return 0 if successful, or a specific PK or PEM error code + */ +int mbedtls_pk_parse_keyfile( mbedtls_pk_context *ctx, + const char *path, const char *password ); + +/** \ingroup pk_module */ +/** + * \brief Load and parse a public key + * + * \param ctx The PK context to fill. It must have been initialized + * but not set up. + * \param path filename to read the public key from + * + * \note On entry, ctx must be empty, either freshly initialised + * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If + * you need a specific key type, check the result with + * mbedtls_pk_can_do(). + * + * \note The key is also checked for correctness. + * + * \return 0 if successful, or a specific PK or PEM error code + */ +int mbedtls_pk_parse_public_keyfile( mbedtls_pk_context *ctx, const char *path ); +#endif /* MBEDTLS_FS_IO */ +#endif /* MBEDTLS_PK_PARSE_C */ + +#if defined(MBEDTLS_PK_WRITE_C) +/** + * \brief Write a private key to a PKCS#1 or SEC1 DER structure + * Note: data is written at the end of the buffer! Use the + * return value to determine where you should start + * using the buffer + * + * \param ctx PK context which must contain a valid private key. + * \param buf buffer to write to + * \param size size of the buffer + * + * \return length of data written if successful, or a specific + * error code + */ +int mbedtls_pk_write_key_der( mbedtls_pk_context *ctx, unsigned char *buf, size_t size ); + +/** + * \brief Write a public key to a SubjectPublicKeyInfo DER structure + * Note: data is written at the end of the buffer! Use the + * return value to determine where you should start + * using the buffer + * + * \param ctx PK context which must contain a valid public or private key. + * \param buf buffer to write to + * \param size size of the buffer + * + * \return length of data written if successful, or a specific + * error code + */ +int mbedtls_pk_write_pubkey_der( mbedtls_pk_context *ctx, unsigned char *buf, size_t size ); + +#if defined(MBEDTLS_PEM_WRITE_C) +/** + * \brief Write a public key to a PEM string + * + * \param ctx PK context which must contain a valid public or private key. + * \param buf Buffer to write to. The output includes a + * terminating null byte. + * \param size Size of the buffer in bytes. + * + * \return 0 if successful, or a specific error code + */ +int mbedtls_pk_write_pubkey_pem( mbedtls_pk_context *ctx, unsigned char *buf, size_t size ); + +/** + * \brief Write a private key to a PKCS#1 or SEC1 PEM string + * + * \param ctx PK context which must contain a valid private key. + * \param buf Buffer to write to. The output includes a + * terminating null byte. + * \param size Size of the buffer in bytes. + * + * \return 0 if successful, or a specific error code + */ +int mbedtls_pk_write_key_pem( mbedtls_pk_context *ctx, unsigned char *buf, size_t size ); +#endif /* MBEDTLS_PEM_WRITE_C */ +#endif /* MBEDTLS_PK_WRITE_C */ + +/* + * WARNING: Low-level functions. You probably do not want to use these unless + * you are certain you do ;) + */ + +#if defined(MBEDTLS_PK_PARSE_C) +/** + * \brief Parse a SubjectPublicKeyInfo DER structure + * + * \param p the position in the ASN.1 data + * \param end end of the buffer + * \param pk The PK context to fill. It must have been initialized + * but not set up. + * + * \return 0 if successful, or a specific PK error code + */ +int mbedtls_pk_parse_subpubkey( unsigned char **p, const unsigned char *end, + mbedtls_pk_context *pk ); +#endif /* MBEDTLS_PK_PARSE_C */ + +#if defined(MBEDTLS_PK_WRITE_C) +/** + * \brief Write a subjectPublicKey to ASN.1 data + * Note: function works backwards in data buffer + * + * \param p reference to current position pointer + * \param start start of the buffer (for bounds-checking) + * \param key PK context which must contain a valid public or private key. + * + * \return the length written or a negative error code + */ +int mbedtls_pk_write_pubkey( unsigned char **p, unsigned char *start, + const mbedtls_pk_context *key ); +#endif /* MBEDTLS_PK_WRITE_C */ + +/* + * Internal module functions. You probably do not want to use these unless you + * know you do. + */ +#if defined(MBEDTLS_FS_IO) +int mbedtls_pk_load_file( const char *path, unsigned char **buf, size_t *n ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_PK_H */ diff --git a/src/common/mbedtls/include/mbedtls/pk_internal.h b/src/common/mbedtls/include/mbedtls/pk_internal.h new file mode 100644 index 0000000000..e26b92b6c2 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/pk_internal.h @@ -0,0 +1,148 @@ +/** + * \file pk_internal.h + * + * \brief Public Key abstraction layer: wrapper functions + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#ifndef MBEDTLS_PK_WRAP_H +#define MBEDTLS_PK_WRAP_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "pk.h" + +struct mbedtls_pk_info_t +{ + /** Public key type */ + mbedtls_pk_type_t type; + + /** Type name */ + const char *name; + + /** Get key size in bits */ + size_t (*get_bitlen)( const void * ); + + /** Tell if the context implements this type (e.g. ECKEY can do ECDSA) */ + int (*can_do)( mbedtls_pk_type_t type ); + + /** Verify signature */ + int (*verify_func)( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ); + + /** Make signature */ + int (*sign_func)( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /** Verify signature (restartable) */ + int (*verify_rs_func)( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len, + void *rs_ctx ); + + /** Make signature (restartable) */ + int (*sign_rs_func)( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, void *rs_ctx ); +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + + /** Decrypt message */ + int (*decrypt_func)( void *ctx, const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + + /** Encrypt message */ + int (*encrypt_func)( void *ctx, const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + + /** Check public-private key pair */ + int (*check_pair_func)( const void *pub, const void *prv ); + + /** Allocate a new context */ + void * (*ctx_alloc_func)( void ); + + /** Free the given context */ + void (*ctx_free_func)( void *ctx ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /** Allocate the restart context */ + void * (*rs_alloc_func)( void ); + + /** Free the restart context */ + void (*rs_free_func)( void *rs_ctx ); +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + + /** Interface with the debug module */ + void (*debug_func)( const void *ctx, mbedtls_pk_debug_item *items ); + +}; +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +/* Container for RSA-alt */ +typedef struct +{ + void *key; + mbedtls_pk_rsa_alt_decrypt_func decrypt_func; + mbedtls_pk_rsa_alt_sign_func sign_func; + mbedtls_pk_rsa_alt_key_len_func key_len_func; +} mbedtls_rsa_alt_context; +#endif + +#if defined(MBEDTLS_RSA_C) +extern const mbedtls_pk_info_t mbedtls_rsa_info; +#endif + +#if defined(MBEDTLS_ECP_C) +extern const mbedtls_pk_info_t mbedtls_eckey_info; +extern const mbedtls_pk_info_t mbedtls_eckeydh_info; +#endif + +#if defined(MBEDTLS_ECDSA_C) +extern const mbedtls_pk_info_t mbedtls_ecdsa_info; +#endif + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +extern const mbedtls_pk_info_t mbedtls_rsa_alt_info; +#endif + +#endif /* MBEDTLS_PK_WRAP_H */ diff --git a/src/common/mbedtls/include/mbedtls/platform.h b/src/common/mbedtls/include/mbedtls/platform.h new file mode 100644 index 0000000000..7563945992 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/platform.h @@ -0,0 +1,369 @@ +/** + * \file platform.h + * + * \brief This file contains the definitions and functions of the + * Mbed TLS platform abstraction layer. + * + * The platform abstraction layer removes the need for the library + * to directly link to standard C library functions or operating + * system services, making the library easier to port and embed. + * Application developers and users of the library can provide their own + * implementations of these functions, or implementations specific to + * their platform, which can be statically linked to the library or + * dynamically configured at runtime. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_PLATFORM_H +#define MBEDTLS_PLATFORM_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_HAVE_TIME) +#include "platform_time.h" +#endif + +#define MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED -0x0070 /**< Hardware accelerator failed */ +#define MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED -0x0072 /**< The requested feature is not supported by the platform */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in config.h or define them on the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) +#include +#include +#include +#if !defined(MBEDTLS_PLATFORM_STD_SNPRINTF) +#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< The default \c snprintf function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_PRINTF) +#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< The default \c printf function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_FPRINTF) +#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< The default \c fprintf function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_CALLOC) +#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< The default \c calloc function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_FREE) +#define MBEDTLS_PLATFORM_STD_FREE free /**< The default \c free function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_EXIT) +#define MBEDTLS_PLATFORM_STD_EXIT exit /**< The default \c exit function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_TIME) +#define MBEDTLS_PLATFORM_STD_TIME time /**< The default \c time function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS) +#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS EXIT_SUCCESS /**< The default exit value to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE) +#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE EXIT_FAILURE /**< The default exit value to use. */ +#endif +#if defined(MBEDTLS_FS_IO) +#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) +#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read +#endif +#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) +#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write +#endif +#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_FILE) +#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" +#endif +#endif /* MBEDTLS_FS_IO */ +#else /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ +#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR) +#include MBEDTLS_PLATFORM_STD_MEM_HDR +#endif +#endif /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ + + +/* \} name SECTION: Module settings */ + +/* + * The function pointers for calloc and free. + */ +#if defined(MBEDTLS_PLATFORM_MEMORY) +#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && \ + defined(MBEDTLS_PLATFORM_CALLOC_MACRO) +#define mbedtls_free MBEDTLS_PLATFORM_FREE_MACRO +#define mbedtls_calloc MBEDTLS_PLATFORM_CALLOC_MACRO +#else +/* For size_t */ +#include +extern void *mbedtls_calloc( size_t n, size_t size ); +extern void mbedtls_free( void *ptr ); + +/** + * \brief This function dynamically sets the memory-management + * functions used by the library, during runtime. + * + * \param calloc_func The \c calloc function implementation. + * \param free_func The \c free function implementation. + * + * \return \c 0. + */ +int mbedtls_platform_set_calloc_free( void * (*calloc_func)( size_t, size_t ), + void (*free_func)( void * ) ); +#endif /* MBEDTLS_PLATFORM_FREE_MACRO && MBEDTLS_PLATFORM_CALLOC_MACRO */ +#else /* !MBEDTLS_PLATFORM_MEMORY */ +#define mbedtls_free free +#define mbedtls_calloc calloc +#endif /* MBEDTLS_PLATFORM_MEMORY && !MBEDTLS_PLATFORM_{FREE,CALLOC}_MACRO */ + +/* + * The function pointers for fprintf + */ +#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) +/* We need FILE * */ +#include +extern int (*mbedtls_fprintf)( FILE *stream, const char *format, ... ); + +/** + * \brief This function dynamically configures the fprintf + * function that is called when the + * mbedtls_fprintf() function is invoked by the library. + * + * \param fprintf_func The \c fprintf function implementation. + * + * \return \c 0. + */ +int mbedtls_platform_set_fprintf( int (*fprintf_func)( FILE *stream, const char *, + ... ) ); +#else +#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) +#define mbedtls_fprintf MBEDTLS_PLATFORM_FPRINTF_MACRO +#else +#define mbedtls_fprintf fprintf +#endif /* MBEDTLS_PLATFORM_FPRINTF_MACRO */ +#endif /* MBEDTLS_PLATFORM_FPRINTF_ALT */ + +/* + * The function pointers for printf + */ +#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) +extern int (*mbedtls_printf)( const char *format, ... ); + +/** + * \brief This function dynamically configures the snprintf + * function that is called when the mbedtls_snprintf() + * function is invoked by the library. + * + * \param printf_func The \c printf function implementation. + * + * \return \c 0 on success. + */ +int mbedtls_platform_set_printf( int (*printf_func)( const char *, ... ) ); +#else /* !MBEDTLS_PLATFORM_PRINTF_ALT */ +#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) +#define mbedtls_printf MBEDTLS_PLATFORM_PRINTF_MACRO +#else +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_PRINTF_MACRO */ +#endif /* MBEDTLS_PLATFORM_PRINTF_ALT */ + +/* + * The function pointers for snprintf + * + * The snprintf implementation should conform to C99: + * - it *must* always correctly zero-terminate the buffer + * (except when n == 0, then it must leave the buffer untouched) + * - however it is acceptable to return -1 instead of the required length when + * the destination buffer is too short. + */ + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) +extern int (*mbedtls_snprintf)( char * s, size_t n, const char * format, ... ); + +/** + * \brief This function allows configuring a custom + * \c snprintf function pointer. + * + * \param snprintf_func The \c snprintf function implementation. + * + * \return \c 0 on success. + */ +int mbedtls_platform_set_snprintf( int (*snprintf_func)( char * s, size_t n, + const char * format, ... ) ); +#else /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ +#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) +#define mbedtls_snprintf MBEDTLS_PLATFORM_SNPRINTF_MACRO +#else +#define mbedtls_snprintf MBEDTLS_PLATFORM_STD_SNPRINTF +#endif /* MBEDTLS_PLATFORM_SNPRINTF_MACRO */ +#endif /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ + +/* + * The function pointers for exit + */ +#if defined(MBEDTLS_PLATFORM_EXIT_ALT) +extern void (*mbedtls_exit)( int status ); + +/** + * \brief This function dynamically configures the exit + * function that is called when the mbedtls_exit() + * function is invoked by the library. + * + * \param exit_func The \c exit function implementation. + * + * \return \c 0 on success. + */ +int mbedtls_platform_set_exit( void (*exit_func)( int status ) ); +#else +#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) +#define mbedtls_exit MBEDTLS_PLATFORM_EXIT_MACRO +#else +#define mbedtls_exit exit +#endif /* MBEDTLS_PLATFORM_EXIT_MACRO */ +#endif /* MBEDTLS_PLATFORM_EXIT_ALT */ + +/* + * The default exit values + */ +#if defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS) +#define MBEDTLS_EXIT_SUCCESS MBEDTLS_PLATFORM_STD_EXIT_SUCCESS +#else +#define MBEDTLS_EXIT_SUCCESS 0 +#endif +#if defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE) +#define MBEDTLS_EXIT_FAILURE MBEDTLS_PLATFORM_STD_EXIT_FAILURE +#else +#define MBEDTLS_EXIT_FAILURE 1 +#endif + +/* + * The function pointers for reading from and writing a seed file to + * Non-Volatile storage (NV) in a platform-independent way + * + * Only enabled when the NV seed entropy source is enabled + */ +#if defined(MBEDTLS_ENTROPY_NV_SEED) +#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) && defined(MBEDTLS_FS_IO) +/* Internal standard platform definitions */ +int mbedtls_platform_std_nv_seed_read( unsigned char *buf, size_t buf_len ); +int mbedtls_platform_std_nv_seed_write( unsigned char *buf, size_t buf_len ); +#endif + +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) +extern int (*mbedtls_nv_seed_read)( unsigned char *buf, size_t buf_len ); +extern int (*mbedtls_nv_seed_write)( unsigned char *buf, size_t buf_len ); + +/** + * \brief This function allows configuring custom seed file writing and + * reading functions. + * + * \param nv_seed_read_func The seed reading function implementation. + * \param nv_seed_write_func The seed writing function implementation. + * + * \return \c 0 on success. + */ +int mbedtls_platform_set_nv_seed( + int (*nv_seed_read_func)( unsigned char *buf, size_t buf_len ), + int (*nv_seed_write_func)( unsigned char *buf, size_t buf_len ) + ); +#else +#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) && \ + defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO) +#define mbedtls_nv_seed_read MBEDTLS_PLATFORM_NV_SEED_READ_MACRO +#define mbedtls_nv_seed_write MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +#else +#define mbedtls_nv_seed_read mbedtls_platform_std_nv_seed_read +#define mbedtls_nv_seed_write mbedtls_platform_std_nv_seed_write +#endif +#endif /* MBEDTLS_PLATFORM_NV_SEED_ALT */ +#endif /* MBEDTLS_ENTROPY_NV_SEED */ + +#if !defined(MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT) + +/** + * \brief The platform context structure. + * + * \note This structure may be used to assist platform-specific + * setup or teardown operations. + */ +typedef struct mbedtls_platform_context +{ + char dummy; /**< A placeholder member, as empty structs are not portable. */ +} +mbedtls_platform_context; + +#else +#include "platform_alt.h" +#endif /* !MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */ + +/** + * \brief This function performs any platform-specific initialization + * operations. + * + * \note This function should be called before any other library functions. + * + * Its implementation is platform-specific, and unless + * platform-specific code is provided, it does nothing. + * + * \note The usage and necessity of this function is dependent on the platform. + * + * \param ctx The platform context. + * + * \return \c 0 on success. + */ +int mbedtls_platform_setup( mbedtls_platform_context *ctx ); +/** + * \brief This function performs any platform teardown operations. + * + * \note This function should be called after every other Mbed TLS module + * has been correctly freed using the appropriate free function. + * + * Its implementation is platform-specific, and unless + * platform-specific code is provided, it does nothing. + * + * \note The usage and necessity of this function is dependent on the platform. + * + * \param ctx The platform context. + * + */ +void mbedtls_platform_teardown( mbedtls_platform_context *ctx ); + +#ifdef __cplusplus +} +#endif + +#endif /* platform.h */ diff --git a/src/common/mbedtls/include/mbedtls/platform_util.h b/src/common/mbedtls/include/mbedtls/platform_util.h new file mode 100644 index 0000000000..fb66be3a0a --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/platform_util.h @@ -0,0 +1,206 @@ +/** + * \file platform_util.h + * + * \brief Common and shared functions used by multiple modules in the Mbed TLS + * library. + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_PLATFORM_UTIL_H +#define MBEDTLS_PLATFORM_UTIL_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#if defined(MBEDTLS_HAVE_TIME_DATE) +#include "platform_time.h" +#include +#endif /* MBEDTLS_HAVE_TIME_DATE */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_CHECK_PARAMS) + +#if defined(MBEDTLS_CHECK_PARAMS_ASSERT) +/* Allow the user to define MBEDTLS_PARAM_FAILED to something like assert + * (which is what our config.h suggests). */ +#include +#endif /* MBEDTLS_CHECK_PARAMS_ASSERT */ + +#if defined(MBEDTLS_PARAM_FAILED) +/** An alternative definition of MBEDTLS_PARAM_FAILED has been set in config.h. + * + * This flag can be used to check whether it is safe to assume that + * MBEDTLS_PARAM_FAILED() will expand to a call to mbedtls_param_failed(). + */ +#define MBEDTLS_PARAM_FAILED_ALT + +#elif defined(MBEDTLS_CHECK_PARAMS_ASSERT) +#define MBEDTLS_PARAM_FAILED( cond ) assert( cond ) +#define MBEDTLS_PARAM_FAILED_ALT + +#else /* MBEDTLS_PARAM_FAILED */ +#define MBEDTLS_PARAM_FAILED( cond ) \ + mbedtls_param_failed( #cond, __FILE__, __LINE__ ) + +/** + * \brief User supplied callback function for parameter validation failure. + * See #MBEDTLS_CHECK_PARAMS for context. + * + * This function will be called unless an alternative treatement + * is defined through the #MBEDTLS_PARAM_FAILED macro. + * + * This function can return, and the operation will be aborted, or + * alternatively, through use of setjmp()/longjmp() can resume + * execution in the application code. + * + * \param failure_condition The assertion that didn't hold. + * \param file The file where the assertion failed. + * \param line The line in the file where the assertion failed. + */ +void mbedtls_param_failed( const char *failure_condition, + const char *file, + int line ); +#endif /* MBEDTLS_PARAM_FAILED */ + +/* Internal macro meant to be called only from within the library. */ +#define MBEDTLS_INTERNAL_VALIDATE_RET( cond, ret ) \ + do { \ + if( !(cond) ) \ + { \ + MBEDTLS_PARAM_FAILED( cond ); \ + return( ret ); \ + } \ + } while( 0 ) + +/* Internal macro meant to be called only from within the library. */ +#define MBEDTLS_INTERNAL_VALIDATE( cond ) \ + do { \ + if( !(cond) ) \ + { \ + MBEDTLS_PARAM_FAILED( cond ); \ + return; \ + } \ + } while( 0 ) + +#else /* MBEDTLS_CHECK_PARAMS */ + +/* Internal macros meant to be called only from within the library. */ +#define MBEDTLS_INTERNAL_VALIDATE_RET( cond, ret ) do { } while( 0 ) +#define MBEDTLS_INTERNAL_VALIDATE( cond ) do { } while( 0 ) + +#endif /* MBEDTLS_CHECK_PARAMS */ + +/* Internal helper macros for deprecating API constants. */ +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +/* Deliberately don't (yet) export MBEDTLS_DEPRECATED here + * to avoid conflict with other headers which define and use + * it, too. We might want to move all these definitions here at + * some point for uniformity. */ +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +MBEDTLS_DEPRECATED typedef char const * mbedtls_deprecated_string_constant_t; +#define MBEDTLS_DEPRECATED_STRING_CONSTANT( VAL ) \ + ( (mbedtls_deprecated_string_constant_t) ( VAL ) ) +MBEDTLS_DEPRECATED typedef int mbedtls_deprecated_numeric_constant_t; +#define MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( VAL ) \ + ( (mbedtls_deprecated_numeric_constant_t) ( VAL ) ) +#undef MBEDTLS_DEPRECATED +#else /* MBEDTLS_DEPRECATED_WARNING */ +#define MBEDTLS_DEPRECATED_STRING_CONSTANT( VAL ) VAL +#define MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( VAL ) VAL +#endif /* MBEDTLS_DEPRECATED_WARNING */ +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief Securely zeroize a buffer + * + * The function is meant to wipe the data contained in a buffer so + * that it can no longer be recovered even if the program memory + * is later compromised. Call this function on sensitive data + * stored on the stack before returning from a function, and on + * sensitive data stored on the heap before freeing the heap + * object. + * + * It is extremely difficult to guarantee that calls to + * mbedtls_platform_zeroize() are not removed by aggressive + * compiler optimizations in a portable way. For this reason, Mbed + * TLS provides the configuration option + * MBEDTLS_PLATFORM_ZEROIZE_ALT, which allows users to configure + * mbedtls_platform_zeroize() to use a suitable implementation for + * their platform and needs + * + * \param buf Buffer to be zeroized + * \param len Length of the buffer in bytes + * + */ +void mbedtls_platform_zeroize( void *buf, size_t len ); + +#if defined(MBEDTLS_HAVE_TIME_DATE) +/** + * \brief Platform-specific implementation of gmtime_r() + * + * The function is a thread-safe abstraction that behaves + * similarly to the gmtime_r() function from Unix/POSIX. + * + * Mbed TLS will try to identify the underlying platform and + * make use of an appropriate underlying implementation (e.g. + * gmtime_r() for POSIX and gmtime_s() for Windows). If this is + * not possible, then gmtime() will be used. In this case, calls + * from the library to gmtime() will be guarded by the mutex + * mbedtls_threading_gmtime_mutex if MBEDTLS_THREADING_C is + * enabled. It is recommended that calls from outside the library + * are also guarded by this mutex. + * + * If MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, then Mbed TLS will + * unconditionally use the alternative implementation for + * mbedtls_platform_gmtime_r() supplied by the user at compile time. + * + * \param tt Pointer to an object containing time (in seconds) since the + * epoch to be converted + * \param tm_buf Pointer to an object where the results will be stored + * + * \return Pointer to an object of type struct tm on success, otherwise + * NULL + */ +struct tm *mbedtls_platform_gmtime_r( const mbedtls_time_t *tt, + struct tm *tm_buf ); +#endif /* MBEDTLS_HAVE_TIME_DATE */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_PLATFORM_UTIL_H */ diff --git a/src/common/mbedtls/include/mbedtls/rsa.h b/src/common/mbedtls/include/mbedtls/rsa.h new file mode 100644 index 0000000000..0752e5454e --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/rsa.h @@ -0,0 +1,1288 @@ +/** + * \file rsa.h + * + * \brief This file provides an API for the RSA public-key cryptosystem. + * + * The RSA public-key cryptosystem is defined in Public-Key + * Cryptography Standards (PKCS) #1 v1.5: RSA Encryption + * and Public-Key Cryptography Standards (PKCS) #1 v2.1: + * RSA Cryptography Specifications. + * + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_RSA_H +#define MBEDTLS_RSA_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "bignum.h" +#include "md.h" + +#if defined(MBEDTLS_THREADING_C) +#include "threading.h" +#endif + +/* + * RSA Error codes + */ +#define MBEDTLS_ERR_RSA_BAD_INPUT_DATA -0x4080 /**< Bad input parameters to function. */ +#define MBEDTLS_ERR_RSA_INVALID_PADDING -0x4100 /**< Input data contains invalid padding and is rejected. */ +#define MBEDTLS_ERR_RSA_KEY_GEN_FAILED -0x4180 /**< Something failed during generation of a key. */ +#define MBEDTLS_ERR_RSA_KEY_CHECK_FAILED -0x4200 /**< Key failed to pass the validity check of the library. */ +#define MBEDTLS_ERR_RSA_PUBLIC_FAILED -0x4280 /**< The public key operation failed. */ +#define MBEDTLS_ERR_RSA_PRIVATE_FAILED -0x4300 /**< The private key operation failed. */ +#define MBEDTLS_ERR_RSA_VERIFY_FAILED -0x4380 /**< The PKCS#1 verification failed. */ +#define MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 /**< The output buffer for decryption is not large enough. */ +#define MBEDTLS_ERR_RSA_RNG_FAILED -0x4480 /**< The random generator failed to generate non-zeros. */ + +/* MBEDTLS_ERR_RSA_UNSUPPORTED_OPERATION is deprecated and should not be used. + */ +#define MBEDTLS_ERR_RSA_UNSUPPORTED_OPERATION -0x4500 /**< The implementation does not offer the requested operation, for example, because of security violations or lack of functionality. */ + +/* MBEDTLS_ERR_RSA_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_RSA_HW_ACCEL_FAILED -0x4580 /**< RSA hardware accelerator failed. */ + +/* + * RSA constants + */ +#define MBEDTLS_RSA_PUBLIC 0 /**< Request private key operation. */ +#define MBEDTLS_RSA_PRIVATE 1 /**< Request public key operation. */ + +#define MBEDTLS_RSA_PKCS_V15 0 /**< Use PKCS#1 v1.5 encoding. */ +#define MBEDTLS_RSA_PKCS_V21 1 /**< Use PKCS#1 v2.1 encoding. */ + +#define MBEDTLS_RSA_SIGN 1 /**< Identifier for RSA signature operations. */ +#define MBEDTLS_RSA_CRYPT 2 /**< Identifier for RSA encryption and decryption operations. */ + +#define MBEDTLS_RSA_SALT_LEN_ANY -1 + +/* + * The above constants may be used even if the RSA module is compile out, + * eg for alternative (PKCS#11) RSA implemenations in the PK layers. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_RSA_ALT) +// Regular implementation +// + +/** + * \brief The RSA context structure. + * + * \note Direct manipulation of the members of this structure + * is deprecated. All manipulation should instead be done through + * the public interface functions. + */ +typedef struct mbedtls_rsa_context +{ + int ver; /*!< Reserved for internal purposes. + * Do not set this field in application + * code. Its meaning might change without + * notice. */ + size_t len; /*!< The size of \p N in Bytes. */ + + mbedtls_mpi N; /*!< The public modulus. */ + mbedtls_mpi E; /*!< The public exponent. */ + + mbedtls_mpi D; /*!< The private exponent. */ + mbedtls_mpi P; /*!< The first prime factor. */ + mbedtls_mpi Q; /*!< The second prime factor. */ + + mbedtls_mpi DP; /*!< D % (P - 1). */ + mbedtls_mpi DQ; /*!< D % (Q - 1). */ + mbedtls_mpi QP; /*!< 1 / (Q % P). */ + + mbedtls_mpi RN; /*!< cached R^2 mod N. */ + + mbedtls_mpi RP; /*!< cached R^2 mod P. */ + mbedtls_mpi RQ; /*!< cached R^2 mod Q. */ + + mbedtls_mpi Vi; /*!< The cached blinding value. */ + mbedtls_mpi Vf; /*!< The cached un-blinding value. */ + + int padding; /*!< Selects padding mode: + #MBEDTLS_RSA_PKCS_V15 for 1.5 padding and + #MBEDTLS_RSA_PKCS_V21 for OAEP or PSS. */ + int hash_id; /*!< Hash identifier of mbedtls_md_type_t type, + as specified in md.h for use in the MGF + mask generating function used in the + EME-OAEP and EMSA-PSS encodings. */ +#if defined(MBEDTLS_THREADING_C) + /* Invariant: the mutex is initialized iff ver != 0. */ + mbedtls_threading_mutex_t mutex; /*!< Thread-safety mutex. */ +#endif +} +mbedtls_rsa_context; + +#else /* MBEDTLS_RSA_ALT */ +#include "rsa_alt.h" +#endif /* MBEDTLS_RSA_ALT */ + +/** + * \brief This function initializes an RSA context. + * + * \note Set padding to #MBEDTLS_RSA_PKCS_V21 for the RSAES-OAEP + * encryption scheme and the RSASSA-PSS signature scheme. + * + * \note The \p hash_id parameter is ignored when using + * #MBEDTLS_RSA_PKCS_V15 padding. + * + * \note The choice of padding mode is strictly enforced for private key + * operations, since there might be security concerns in + * mixing padding modes. For public key operations it is + * a default value, which can be overridden by calling specific + * \c rsa_rsaes_xxx or \c rsa_rsassa_xxx functions. + * + * \note The hash selected in \p hash_id is always used for OEAP + * encryption. For PSS signatures, it is always used for + * making signatures, but can be overridden for verifying them. + * If set to #MBEDTLS_MD_NONE, it is always overridden. + * + * \param ctx The RSA context to initialize. This must not be \c NULL. + * \param padding The padding mode to use. This must be either + * #MBEDTLS_RSA_PKCS_V15 or #MBEDTLS_RSA_PKCS_V21. + * \param hash_id The hash identifier of ::mbedtls_md_type_t type, if + * \p padding is #MBEDTLS_RSA_PKCS_V21. It is unused + * otherwise. + */ +void mbedtls_rsa_init( mbedtls_rsa_context *ctx, + int padding, + int hash_id ); + +/** + * \brief This function imports a set of core parameters into an + * RSA context. + * + * \note This function can be called multiple times for successive + * imports, if the parameters are not simultaneously present. + * + * Any sequence of calls to this function should be followed + * by a call to mbedtls_rsa_complete(), which checks and + * completes the provided information to a ready-for-use + * public or private RSA key. + * + * \note See mbedtls_rsa_complete() for more information on which + * parameters are necessary to set up a private or public + * RSA key. + * + * \note The imported parameters are copied and need not be preserved + * for the lifetime of the RSA context being set up. + * + * \param ctx The initialized RSA context to store the parameters in. + * \param N The RSA modulus. This may be \c NULL. + * \param P The first prime factor of \p N. This may be \c NULL. + * \param Q The second prime factor of \p N. This may be \c NULL. + * \param D The private exponent. This may be \c NULL. + * \param E The public exponent. This may be \c NULL. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_rsa_import( mbedtls_rsa_context *ctx, + const mbedtls_mpi *N, + const mbedtls_mpi *P, const mbedtls_mpi *Q, + const mbedtls_mpi *D, const mbedtls_mpi *E ); + +/** + * \brief This function imports core RSA parameters, in raw big-endian + * binary format, into an RSA context. + * + * \note This function can be called multiple times for successive + * imports, if the parameters are not simultaneously present. + * + * Any sequence of calls to this function should be followed + * by a call to mbedtls_rsa_complete(), which checks and + * completes the provided information to a ready-for-use + * public or private RSA key. + * + * \note See mbedtls_rsa_complete() for more information on which + * parameters are necessary to set up a private or public + * RSA key. + * + * \note The imported parameters are copied and need not be preserved + * for the lifetime of the RSA context being set up. + * + * \param ctx The initialized RSA context to store the parameters in. + * \param N The RSA modulus. This may be \c NULL. + * \param N_len The Byte length of \p N; it is ignored if \p N == NULL. + * \param P The first prime factor of \p N. This may be \c NULL. + * \param P_len The Byte length of \p P; it ns ignored if \p P == NULL. + * \param Q The second prime factor of \p N. This may be \c NULL. + * \param Q_len The Byte length of \p Q; it is ignored if \p Q == NULL. + * \param D The private exponent. This may be \c NULL. + * \param D_len The Byte length of \p D; it is ignored if \p D == NULL. + * \param E The public exponent. This may be \c NULL. + * \param E_len The Byte length of \p E; it is ignored if \p E == NULL. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_rsa_import_raw( mbedtls_rsa_context *ctx, + unsigned char const *N, size_t N_len, + unsigned char const *P, size_t P_len, + unsigned char const *Q, size_t Q_len, + unsigned char const *D, size_t D_len, + unsigned char const *E, size_t E_len ); + +/** + * \brief This function completes an RSA context from + * a set of imported core parameters. + * + * To setup an RSA public key, precisely \p N and \p E + * must have been imported. + * + * To setup an RSA private key, sufficient information must + * be present for the other parameters to be derivable. + * + * The default implementation supports the following: + *
  • Derive \p P, \p Q from \p N, \p D, \p E.
    • + *
  • Derive \p N, \p D from \p P, \p Q, \p E.
+ * Alternative implementations need not support these. + * + * If this function runs successfully, it guarantees that + * the RSA context can be used for RSA operations without + * the risk of failure or crash. + * + * \warning This function need not perform consistency checks + * for the imported parameters. In particular, parameters that + * are not needed by the implementation might be silently + * discarded and left unchecked. To check the consistency + * of the key material, see mbedtls_rsa_check_privkey(). + * + * \param ctx The initialized RSA context holding imported parameters. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_RSA_BAD_INPUT_DATA if the attempted derivations + * failed. + * + */ +int mbedtls_rsa_complete( mbedtls_rsa_context *ctx ); + +/** + * \brief This function exports the core parameters of an RSA key. + * + * If this function runs successfully, the non-NULL buffers + * pointed to by \p N, \p P, \p Q, \p D, and \p E are fully + * written, with additional unused space filled leading by + * zero Bytes. + * + * Possible reasons for returning + * #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED:
    + *
  • An alternative RSA implementation is in use, which + * stores the key externally, and either cannot or should + * not export it into RAM.
    • + *
  • A SW or HW implementation might not support a certain + * deduction. For example, \p P, \p Q from \p N, \p D, + * and \p E if the former are not part of the + * implementation.
+ * + * If the function fails due to an unsupported operation, + * the RSA context stays intact and remains usable. + * + * \param ctx The initialized RSA context. + * \param N The MPI to hold the RSA modulus. + * This may be \c NULL if this field need not be exported. + * \param P The MPI to hold the first prime factor of \p N. + * This may be \c NULL if this field need not be exported. + * \param Q The MPI to hold the second prime factor of \p N. + * This may be \c NULL if this field need not be exported. + * \param D The MPI to hold the private exponent. + * This may be \c NULL if this field need not be exported. + * \param E The MPI to hold the public exponent. + * This may be \c NULL if this field need not be exported. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED if exporting the + * requested parameters cannot be done due to missing + * functionality or because of security policies. + * \return A non-zero return code on any other failure. + * + */ +int mbedtls_rsa_export( const mbedtls_rsa_context *ctx, + mbedtls_mpi *N, mbedtls_mpi *P, mbedtls_mpi *Q, + mbedtls_mpi *D, mbedtls_mpi *E ); + +/** + * \brief This function exports core parameters of an RSA key + * in raw big-endian binary format. + * + * If this function runs successfully, the non-NULL buffers + * pointed to by \p N, \p P, \p Q, \p D, and \p E are fully + * written, with additional unused space filled leading by + * zero Bytes. + * + * Possible reasons for returning + * #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED:
    + *
  • An alternative RSA implementation is in use, which + * stores the key externally, and either cannot or should + * not export it into RAM.
    • + *
  • A SW or HW implementation might not support a certain + * deduction. For example, \p P, \p Q from \p N, \p D, + * and \p E if the former are not part of the + * implementation.
+ * If the function fails due to an unsupported operation, + * the RSA context stays intact and remains usable. + * + * \note The length parameters are ignored if the corresponding + * buffer pointers are NULL. + * + * \param ctx The initialized RSA context. + * \param N The Byte array to store the RSA modulus, + * or \c NULL if this field need not be exported. + * \param N_len The size of the buffer for the modulus. + * \param P The Byte array to hold the first prime factor of \p N, + * or \c NULL if this field need not be exported. + * \param P_len The size of the buffer for the first prime factor. + * \param Q The Byte array to hold the second prime factor of \p N, + * or \c NULL if this field need not be exported. + * \param Q_len The size of the buffer for the second prime factor. + * \param D The Byte array to hold the private exponent, + * or \c NULL if this field need not be exported. + * \param D_len The size of the buffer for the private exponent. + * \param E The Byte array to hold the public exponent, + * or \c NULL if this field need not be exported. + * \param E_len The size of the buffer for the public exponent. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED if exporting the + * requested parameters cannot be done due to missing + * functionality or because of security policies. + * \return A non-zero return code on any other failure. + */ +int mbedtls_rsa_export_raw( const mbedtls_rsa_context *ctx, + unsigned char *N, size_t N_len, + unsigned char *P, size_t P_len, + unsigned char *Q, size_t Q_len, + unsigned char *D, size_t D_len, + unsigned char *E, size_t E_len ); + +/** + * \brief This function exports CRT parameters of a private RSA key. + * + * \note Alternative RSA implementations not using CRT-parameters + * internally can implement this function based on + * mbedtls_rsa_deduce_opt(). + * + * \param ctx The initialized RSA context. + * \param DP The MPI to hold \c D modulo `P-1`, + * or \c NULL if it need not be exported. + * \param DQ The MPI to hold \c D modulo `Q-1`, + * or \c NULL if it need not be exported. + * \param QP The MPI to hold modular inverse of \c Q modulo \c P, + * or \c NULL if it need not be exported. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + * + */ +int mbedtls_rsa_export_crt( const mbedtls_rsa_context *ctx, + mbedtls_mpi *DP, mbedtls_mpi *DQ, mbedtls_mpi *QP ); + +/** + * \brief This function sets padding for an already initialized RSA + * context. See mbedtls_rsa_init() for details. + * + * \param ctx The initialized RSA context to be configured. + * \param padding The padding mode to use. This must be either + * #MBEDTLS_RSA_PKCS_V15 or #MBEDTLS_RSA_PKCS_V21. + * \param hash_id The #MBEDTLS_RSA_PKCS_V21 hash identifier. + */ +void mbedtls_rsa_set_padding( mbedtls_rsa_context *ctx, int padding, + int hash_id ); + +/** + * \brief This function retrieves the length of RSA modulus in Bytes. + * + * \param ctx The initialized RSA context. + * + * \return The length of the RSA modulus in Bytes. + * + */ +size_t mbedtls_rsa_get_len( const mbedtls_rsa_context *ctx ); + +/** + * \brief This function generates an RSA keypair. + * + * \note mbedtls_rsa_init() must be called before this function, + * to set up the RSA context. + * + * \param ctx The initialized RSA context used to hold the key. + * \param f_rng The RNG function to be used for key generation. + * This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. + * This may be \c NULL if \p f_rng doesn't need a context. + * \param nbits The size of the public key in bits. + * \param exponent The public exponent to use. For example, \c 65537. + * This must be odd and greater than \c 1. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + unsigned int nbits, int exponent ); + +/** + * \brief This function checks if a context contains at least an RSA + * public key. + * + * If the function runs successfully, it is guaranteed that + * enough information is present to perform an RSA public key + * operation using mbedtls_rsa_public(). + * + * \param ctx The initialized RSA context to check. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + * + */ +int mbedtls_rsa_check_pubkey( const mbedtls_rsa_context *ctx ); + +/** + * \brief This function checks if a context contains an RSA private key + * and perform basic consistency checks. + * + * \note The consistency checks performed by this function not only + * ensure that mbedtls_rsa_private() can be called successfully + * on the given context, but that the various parameters are + * mutually consistent with high probability, in the sense that + * mbedtls_rsa_public() and mbedtls_rsa_private() are inverses. + * + * \warning This function should catch accidental misconfigurations + * like swapping of parameters, but it cannot establish full + * trust in neither the quality nor the consistency of the key + * material that was used to setup the given RSA context: + *
  • Consistency: Imported parameters that are irrelevant + * for the implementation might be silently dropped. If dropped, + * the current function does not have access to them, + * and therefore cannot check them. See mbedtls_rsa_complete(). + * If you want to check the consistency of the entire + * content of an PKCS1-encoded RSA private key, for example, you + * should use mbedtls_rsa_validate_params() before setting + * up the RSA context. + * Additionally, if the implementation performs empirical checks, + * these checks substantiate but do not guarantee consistency.
    • + *
  • Quality: This function is not expected to perform + * extended quality assessments like checking that the prime + * factors are safe. Additionally, it is the responsibility of the + * user to ensure the trustworthiness of the source of his RSA + * parameters, which goes beyond what is effectively checkable + * by the library.
+ * + * \param ctx The initialized RSA context to check. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_check_privkey( const mbedtls_rsa_context *ctx ); + +/** + * \brief This function checks a public-private RSA key pair. + * + * It checks each of the contexts, and makes sure they match. + * + * \param pub The initialized RSA context holding the public key. + * \param prv The initialized RSA context holding the private key. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_check_pub_priv( const mbedtls_rsa_context *pub, + const mbedtls_rsa_context *prv ); + +/** + * \brief This function performs an RSA public key operation. + * + * \param ctx The initialized RSA context to use. + * \param input The input buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \note This function does not handle message padding. + * + * \note Make sure to set \p input[0] = 0 or ensure that + * input is smaller than \p N. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_public( mbedtls_rsa_context *ctx, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function performs an RSA private key operation. + * + * \note Blinding is used if and only if a PRNG is provided. + * + * \note If blinding is used, both the base of exponentation + * and the exponent are blinded, providing protection + * against some side-channel attacks. + * + * \warning It is deprecated and a security risk to not provide + * a PRNG here and thereby prevent the use of blinding. + * Future versions of the library may enforce the presence + * of a PRNG. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function, used for blinding. It is discouraged + * and deprecated to pass \c NULL here, in which case + * blinding will be omitted. + * \param p_rng The RNG context to pass to \p f_rng. This may be \c NULL + * if \p f_rng is \c NULL or if \p f_rng doesn't need a context. + * \param input The input buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + * + */ +int mbedtls_rsa_private( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function adds the message padding, then performs an RSA + * operation. + * + * It is the generic wrapper for performing a PKCS#1 encryption + * operation using the \p mode from the context. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PUBLIC. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PRIVATE and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG to use. It is mandatory for PKCS#1 v2.1 padding + * encoding, and for PKCS#1 v1.5 padding encoding when used + * with \p mode set to #MBEDTLS_RSA_PUBLIC. For PKCS#1 v1.5 + * padding encoding and \p mode set to #MBEDTLS_RSA_PRIVATE, + * it is used for blinding and should be provided in this + * case; see mbedtls_rsa_private() for more. + * \param p_rng The RNG context to be passed to \p f_rng. May be + * \c NULL if \p f_rng is \c NULL or if \p f_rng doesn't + * need a context argument. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated). + * \param ilen The length of the plaintext in Bytes. + * \param input The input data to encrypt. This must be a readable + * buffer of size \p ilen Bytes. This must not be \c NULL. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_pkcs1_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function performs a PKCS#1 v1.5 encryption operation + * (RSAES-PKCS1-v1_5-ENCRYPT). + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PUBLIC. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PRIVATE and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function to use. It is needed for padding generation + * if \p mode is #MBEDTLS_RSA_PUBLIC. If \p mode is + * #MBEDTLS_RSA_PRIVATE (discouraged), it is used for + * blinding and should be provided; see mbedtls_rsa_private(). + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng is \c NULL or if \p f_rng + * doesn't need a context argument. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated). + * \param ilen The length of the plaintext in Bytes. + * \param input The input data to encrypt. This must be a readable + * buffer of size \p ilen Bytes. This must not be \c NULL. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsaes_pkcs1_v15_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function performs a PKCS#1 v2.1 OAEP encryption + * operation (RSAES-OAEP-ENCRYPT). + * + * \note The output buffer must be as large as the size + * of ctx->N. For example, 128 Bytes if RSA-1024 is used. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PUBLIC. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PRIVATE and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initnialized RSA context to use. + * \param f_rng The RNG function to use. This is needed for padding + * generation and must be provided. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated). + * \param label The buffer holding the custom label to use. + * This must be a readable buffer of length \p label_len + * Bytes. It may be \c NULL if \p label_len is \c 0. + * \param label_len The length of the label in Bytes. + * \param ilen The length of the plaintext buffer \p input in Bytes. + * \param input The input data to encrypt. This must be a readable + * buffer of size \p ilen Bytes. This must not be \c NULL. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsaes_oaep_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + const unsigned char *label, size_t label_len, + size_t ilen, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function performs an RSA operation, then removes the + * message padding. + * + * It is the generic wrapper for performing a PKCS#1 decryption + * operation using the \p mode from the context. + * + * \note The output buffer length \c output_max_len should be + * as large as the size \p ctx->len of \p ctx->N (for example, + * 128 Bytes if RSA-1024 is used) to be able to hold an + * arbitrary decrypted message. If it is not large enough to + * hold the decryption of the particular ciphertext provided, + * the function returns \c MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PRIVATE. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PUBLIC and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. If \p mode is #MBEDTLS_RSA_PRIVATE, + * this is used for blinding and should be provided; see + * mbedtls_rsa_private() for more. If \p mode is + * #MBEDTLS_RSA_PUBLIC, it is ignored. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a context. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated). + * \param olen The address at which to store the length of + * the plaintext. This must not be \c NULL. + * \param input The ciphertext buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The buffer used to hold the plaintext. This must + * be a writable buffer of length \p output_max_len Bytes. + * \param output_max_len The length in Bytes of the output buffer \p output. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_pkcs1_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len ); + +/** + * \brief This function performs a PKCS#1 v1.5 decryption + * operation (RSAES-PKCS1-v1_5-DECRYPT). + * + * \note The output buffer length \c output_max_len should be + * as large as the size \p ctx->len of \p ctx->N, for example, + * 128 Bytes if RSA-1024 is used, to be able to hold an + * arbitrary decrypted message. If it is not large enough to + * hold the decryption of the particular ciphertext provided, + * the function returns #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PRIVATE. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PUBLIC and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. If \p mode is #MBEDTLS_RSA_PRIVATE, + * this is used for blinding and should be provided; see + * mbedtls_rsa_private() for more. If \p mode is + * #MBEDTLS_RSA_PUBLIC, it is ignored. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a context. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated). + * \param olen The address at which to store the length of + * the plaintext. This must not be \c NULL. + * \param input The ciphertext buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The buffer used to hold the plaintext. This must + * be a writable buffer of length \p output_max_len Bytes. + * \param output_max_len The length in Bytes of the output buffer \p output. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + * + */ +int mbedtls_rsa_rsaes_pkcs1_v15_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len ); + +/** + * \brief This function performs a PKCS#1 v2.1 OAEP decryption + * operation (RSAES-OAEP-DECRYPT). + * + * \note The output buffer length \c output_max_len should be + * as large as the size \p ctx->len of \p ctx->N, for + * example, 128 Bytes if RSA-1024 is used, to be able to + * hold an arbitrary decrypted message. If it is not + * large enough to hold the decryption of the particular + * ciphertext provided, the function returns + * #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PRIVATE. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PUBLIC and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. If \p mode is #MBEDTLS_RSA_PRIVATE, + * this is used for blinding and should be provided; see + * mbedtls_rsa_private() for more. If \p mode is + * #MBEDTLS_RSA_PUBLIC, it is ignored. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a context. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated). + * \param label The buffer holding the custom label to use. + * This must be a readable buffer of length \p label_len + * Bytes. It may be \c NULL if \p label_len is \c 0. + * \param label_len The length of the label in Bytes. + * \param olen The address at which to store the length of + * the plaintext. This must not be \c NULL. + * \param input The ciphertext buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The buffer used to hold the plaintext. This must + * be a writable buffer of length \p output_max_len Bytes. + * \param output_max_len The length in Bytes of the output buffer \p output. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsaes_oaep_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + const unsigned char *label, size_t label_len, + size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len ); + +/** + * \brief This function performs a private RSA operation to sign + * a message digest using PKCS#1. + * + * It is the generic wrapper for performing a PKCS#1 + * signature using the \p mode from the context. + * + * \note The \p sig buffer must be as large as the size + * of \p ctx->N. For example, 128 Bytes if RSA-1024 is used. + * + * \note For PKCS#1 v2.1 encoding, see comments on + * mbedtls_rsa_rsassa_pss_sign() for details on + * \p md_alg and \p hash_id. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PRIVATE. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PUBLIC and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function to use. If the padding mode is PKCS#1 v2.1, + * this must be provided. If the padding mode is PKCS#1 v1.5 and + * \p mode is #MBEDTLS_RSA_PRIVATE, it is used for blinding + * and should be provided; see mbedtls_rsa_private() for more + * more. It is ignored otherwise. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL + * if \p f_rng is \c NULL or doesn't need a context argument. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated). + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest. + * Ths is only used if \p md_alg is #MBEDTLS_MD_NONE. + * \param hash The buffer holding the message digest or raw data. + * If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable + * buffer of length \p hashlen Bytes. If \p md_alg is not + * #MBEDTLS_MD_NONE, it must be a readable buffer of length + * the size of the hash corresponding to \p md_alg. + * \param sig The buffer to hold the signature. This must be a writable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. + * + * \return \c 0 if the signing operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_pkcs1_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ); + +/** + * \brief This function performs a PKCS#1 v1.5 signature + * operation (RSASSA-PKCS1-v1_5-SIGN). + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PRIVATE. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PUBLIC and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. If \p mode is #MBEDTLS_RSA_PRIVATE, + * this is used for blinding and should be provided; see + * mbedtls_rsa_private() for more. If \p mode is + * #MBEDTLS_RSA_PUBLIC, it is ignored. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL + * if \p f_rng is \c NULL or doesn't need a context argument. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated). + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest. + * Ths is only used if \p md_alg is #MBEDTLS_MD_NONE. + * \param hash The buffer holding the message digest or raw data. + * If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable + * buffer of length \p hashlen Bytes. If \p md_alg is not + * #MBEDTLS_MD_NONE, it must be a readable buffer of length + * the size of the hash corresponding to \p md_alg. + * \param sig The buffer to hold the signature. This must be a writable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. + * + * \return \c 0 if the signing operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pkcs1_v15_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ); + +/** + * \brief This function performs a PKCS#1 v2.1 PSS signature + * operation (RSASSA-PSS-SIGN). + * + * \note The \p hash_id in the RSA context is the one used for the + * encoding. \p md_alg in the function call is the type of hash + * that is encoded. According to RFC-3447: Public-Key + * Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography + * Specifications it is advised to keep both hashes the + * same. + * + * \note This function always uses the maximum possible salt size, + * up to the length of the payload hash. This choice of salt + * size complies with FIPS 186-4 §5.5 (e) and RFC 8017 (PKCS#1 + * v2.2) §9.1.1 step 3. Furthermore this function enforces a + * minimum salt size which is the hash size minus 2 bytes. If + * this minimum size is too large given the key size (the salt + * size, plus the hash size, plus 2 bytes must be no more than + * the key size in bytes), this function returns + * #MBEDTLS_ERR_RSA_BAD_INPUT_DATA. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PRIVATE. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PUBLIC and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. It must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL + * if \p f_rng doesn't need a context argument. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated). + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest. + * Ths is only used if \p md_alg is #MBEDTLS_MD_NONE. + * \param hash The buffer holding the message digest or raw data. + * If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable + * buffer of length \p hashlen Bytes. If \p md_alg is not + * #MBEDTLS_MD_NONE, it must be a readable buffer of length + * the size of the hash corresponding to \p md_alg. + * \param sig The buffer to hold the signature. This must be a writable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. + * + * \return \c 0 if the signing operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pss_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ); + +/** + * \brief This function performs a public RSA operation and checks + * the message digest. + * + * This is the generic wrapper for performing a PKCS#1 + * verification using the mode from the context. + * + * \note For PKCS#1 v2.1 encoding, see comments on + * mbedtls_rsa_rsassa_pss_verify() about \p md_alg and + * \p hash_id. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * set to #MBEDTLS_RSA_PUBLIC. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PRIVATE and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA public key context to use. + * \param f_rng The RNG function to use. If \p mode is #MBEDTLS_RSA_PRIVATE, + * this is used for blinding and should be provided; see + * mbedtls_rsa_private() for more. Otherwise, it is ignored. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a context. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated). + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest. + * This is only used if \p md_alg is #MBEDTLS_MD_NONE. + * \param hash The buffer holding the message digest or raw data. + * If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable + * buffer of length \p hashlen Bytes. If \p md_alg is not + * #MBEDTLS_MD_NONE, it must be a readable buffer of length + * the size of the hash corresponding to \p md_alg. + * \param sig The buffer holding the signature. This must be a readable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 if the verify operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_pkcs1_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ); + +/** + * \brief This function performs a PKCS#1 v1.5 verification + * operation (RSASSA-PKCS1-v1_5-VERIFY). + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * set to #MBEDTLS_RSA_PUBLIC. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PRIVATE and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA public key context to use. + * \param f_rng The RNG function to use. If \p mode is #MBEDTLS_RSA_PRIVATE, + * this is used for blinding and should be provided; see + * mbedtls_rsa_private() for more. Otherwise, it is ignored. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a context. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated). + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest. + * This is only used if \p md_alg is #MBEDTLS_MD_NONE. + * \param hash The buffer holding the message digest or raw data. + * If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable + * buffer of length \p hashlen Bytes. If \p md_alg is not + * #MBEDTLS_MD_NONE, it must be a readable buffer of length + * the size of the hash corresponding to \p md_alg. + * \param sig The buffer holding the signature. This must be a readable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 if the verify operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pkcs1_v15_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ); + +/** + * \brief This function performs a PKCS#1 v2.1 PSS verification + * operation (RSASSA-PSS-VERIFY). + * + * The hash function for the MGF mask generating function + * is that specified in the RSA context. + * + * \note The \p hash_id in the RSA context is the one used for the + * verification. \p md_alg in the function call is the type of + * hash that is verified. According to RFC-3447: Public-Key + * Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography + * Specifications it is advised to keep both hashes the + * same. If \p hash_id in the RSA context is unset, + * the \p md_alg from the function call is used. + * + * \deprecated It is deprecated and discouraged to call this function + * in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library + * are likely to remove the \p mode argument and have it + * implicitly set to #MBEDTLS_RSA_PUBLIC. + * + * \note Alternative implementations of RSA need not support + * mode being set to #MBEDTLS_RSA_PRIVATE and might instead + * return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED. + * + * \param ctx The initialized RSA public key context to use. + * \param f_rng The RNG function to use. If \p mode is #MBEDTLS_RSA_PRIVATE, + * this is used for blinding and should be provided; see + * mbedtls_rsa_private() for more. Otherwise, it is ignored. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a context. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated). + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest. + * This is only used if \p md_alg is #MBEDTLS_MD_NONE. + * \param hash The buffer holding the message digest or raw data. + * If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable + * buffer of length \p hashlen Bytes. If \p md_alg is not + * #MBEDTLS_MD_NONE, it must be a readable buffer of length + * the size of the hash corresponding to \p md_alg. + * \param sig The buffer holding the signature. This must be a readable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 if the verify operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pss_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ); + +/** + * \brief This function performs a PKCS#1 v2.1 PSS verification + * operation (RSASSA-PSS-VERIFY). + * + * The hash function for the MGF mask generating function + * is that specified in \p mgf1_hash_id. + * + * \note The \p sig buffer must be as large as the size + * of \p ctx->N. For example, 128 Bytes if RSA-1024 is used. + * + * \note The \p hash_id in the RSA context is ignored. + * + * \param ctx The initialized RSA public key context to use. + * \param f_rng The RNG function to use. If \p mode is #MBEDTLS_RSA_PRIVATE, + * this is used for blinding and should be provided; see + * mbedtls_rsa_private() for more. Otherwise, it is ignored. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a context. + * \param mode The mode of operation. This must be either + * #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest. + * This is only used if \p md_alg is #MBEDTLS_MD_NONE. + * \param hash The buffer holding the message digest or raw data. + * If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable + * buffer of length \p hashlen Bytes. If \p md_alg is not + * #MBEDTLS_MD_NONE, it must be a readable buffer of length + * the size of the hash corresponding to \p md_alg. + * \param mgf1_hash_id The message digest used for mask generation. + * \param expected_salt_len The length of the salt used in padding. Use + * #MBEDTLS_RSA_SALT_LEN_ANY to accept any salt length. + * \param sig The buffer holding the signature. This must be a readable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 if the verify operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pss_verify_ext( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + mbedtls_md_type_t mgf1_hash_id, + int expected_salt_len, + const unsigned char *sig ); + +/** + * \brief This function copies the components of an RSA context. + * + * \param dst The destination context. This must be initialized. + * \param src The source context. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory allocation failure. + */ +int mbedtls_rsa_copy( mbedtls_rsa_context *dst, const mbedtls_rsa_context *src ); + +/** + * \brief This function frees the components of an RSA key. + * + * \param ctx The RSA context to free. May be \c NULL, in which case + * this function is a no-op. If it is not \c NULL, it must + * point to an initialized RSA context. + */ +void mbedtls_rsa_free( mbedtls_rsa_context *ctx ); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The RSA checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_rsa_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* rsa.h */ diff --git a/src/common/mbedtls/include/mbedtls/sha256.h b/src/common/mbedtls/include/mbedtls/sha256.h new file mode 100644 index 0000000000..562198f055 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/sha256.h @@ -0,0 +1,307 @@ +/** + * \file sha256.h + * + * \brief This file contains SHA-224 and SHA-256 definitions and functions. + * + * The Secure Hash Algorithms 224 and 256 (SHA-224 and SHA-256) cryptographic + * hash functions are defined in FIPS 180-4: Secure Hash Standard (SHS). + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_SHA256_H +#define MBEDTLS_SHA256_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include + +/* MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED -0x0037 /**< SHA-256 hardware accelerator failed */ +#define MBEDTLS_ERR_SHA256_BAD_INPUT_DATA -0x0074 /**< SHA-256 input data was malformed. */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_SHA256_ALT) +// Regular implementation +// + +/** + * \brief The SHA-256 context structure. + * + * The structure is used both for SHA-256 and for SHA-224 + * checksum calculations. The choice between these two is + * made in the call to mbedtls_sha256_starts_ret(). + */ +typedef struct mbedtls_sha256_context +{ + uint32_t total[2]; /*!< The number of Bytes processed. */ + uint32_t state[8]; /*!< The intermediate digest state. */ + unsigned char buffer[64]; /*!< The data block being processed. */ + int is224; /*!< Determines which function to use: + 0: Use SHA-256, or 1: Use SHA-224. */ +} +mbedtls_sha256_context; + +#else /* MBEDTLS_SHA256_ALT */ +#include "sha256_alt.h" +#endif /* MBEDTLS_SHA256_ALT */ + +/** + * \brief This function initializes a SHA-256 context. + * + * \param ctx The SHA-256 context to initialize. This must not be \c NULL. + */ +void mbedtls_sha256_init( mbedtls_sha256_context *ctx ); + +/** + * \brief This function clears a SHA-256 context. + * + * \param ctx The SHA-256 context to clear. This may be \c NULL, in which + * case this function returns immediately. If it is not \c NULL, + * it must point to an initialized SHA-256 context. + */ +void mbedtls_sha256_free( mbedtls_sha256_context *ctx ); + +/** + * \brief This function clones the state of a SHA-256 context. + * + * \param dst The destination context. This must be initialized. + * \param src The context to clone. This must be initialized. + */ +void mbedtls_sha256_clone( mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src ); + +/** + * \brief This function starts a SHA-224 or SHA-256 checksum + * calculation. + * + * \param ctx The context to use. This must be initialized. + * \param is224 This determines which function to use. This must be + * either \c 0 for SHA-256, or \c 1 for SHA-224. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-256 checksum calculation. + * + * \param ctx The SHA-256 context. This must be initialized + * and have a hash operation started. + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief This function finishes the SHA-256 operation, and writes + * the result to the output buffer. + * + * \param ctx The SHA-256 context. This must be initialized + * and have a hash operation started. + * \param output The SHA-224 or SHA-256 checksum result. + * This must be a writable buffer of length \c 32 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, + unsigned char output[32] ); + +/** + * \brief This function processes a single data block within + * the ongoing SHA-256 computation. This function is for + * internal use only. + * + * \param ctx The SHA-256 context. This must be initialized. + * \param data The buffer holding one block of data. This must + * be a readable buffer of length \c 64 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, + const unsigned char data[64] ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief This function starts a SHA-224 or SHA-256 checksum + * calculation. + * + * \deprecated Superseded by mbedtls_sha256_starts_ret() in 2.7.0. + * + * \param ctx The context to use. This must be initialized. + * \param is224 Determines which function to use. This must be + * either \c 0 for SHA-256, or \c 1 for SHA-224. + */ +MBEDTLS_DEPRECATED void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, + int is224 ); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-256 checksum calculation. + * + * \deprecated Superseded by mbedtls_sha256_update_ret() in 2.7.0. + * + * \param ctx The SHA-256 context to use. This must be + * initialized and have a hash operation started. + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + */ +MBEDTLS_DEPRECATED void mbedtls_sha256_update( mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief This function finishes the SHA-256 operation, and writes + * the result to the output buffer. + * + * \deprecated Superseded by mbedtls_sha256_finish_ret() in 2.7.0. + * + * \param ctx The SHA-256 context. This must be initialized and + * have a hash operation started. + * \param output The SHA-224 or SHA-256 checksum result. This must be + * a writable buffer of length \c 32 Bytes. + */ +MBEDTLS_DEPRECATED void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, + unsigned char output[32] ); + +/** + * \brief This function processes a single data block within + * the ongoing SHA-256 computation. This function is for + * internal use only. + * + * \deprecated Superseded by mbedtls_internal_sha256_process() in 2.7.0. + * + * \param ctx The SHA-256 context. This must be initialized. + * \param data The buffer holding one block of data. This must be + * a readable buffer of size \c 64 Bytes. + */ +MBEDTLS_DEPRECATED void mbedtls_sha256_process( mbedtls_sha256_context *ctx, + const unsigned char data[64] ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief This function calculates the SHA-224 or SHA-256 + * checksum of a buffer. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The SHA-256 result is calculated as + * output = SHA-256(input buffer). + * + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The SHA-224 or SHA-256 checksum result. This must + * be a writable buffer of length \c 32 Bytes. + * \param is224 Determines which function to use. This must be + * either \c 0 for SHA-256, or \c 1 for SHA-224. + */ +int mbedtls_sha256_ret( const unsigned char *input, + size_t ilen, + unsigned char output[32], + int is224 ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif + +/** + * \brief This function calculates the SHA-224 or SHA-256 checksum + * of a buffer. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The SHA-256 result is calculated as + * output = SHA-256(input buffer). + * + * \deprecated Superseded by mbedtls_sha256_ret() in 2.7.0. + * + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The SHA-224 or SHA-256 checksum result. This must be + * a writable buffer of length \c 32 Bytes. + * \param is224 Determines which function to use. This must be either + * \c 0 for SHA-256, or \c 1 for SHA-224. + */ +MBEDTLS_DEPRECATED void mbedtls_sha256( const unsigned char *input, + size_t ilen, + unsigned char output[32], + int is224 ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The SHA-224 and SHA-256 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_sha256_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_sha256.h */ diff --git a/src/common/mbedtls/include/mbedtls/sha512.h b/src/common/mbedtls/include/mbedtls/sha512.h new file mode 100644 index 0000000000..1b4dec26c5 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/sha512.h @@ -0,0 +1,310 @@ +/** + * \file sha512.h + * \brief This file contains SHA-384 and SHA-512 definitions and functions. + * + * The Secure Hash Algorithms 384 and 512 (SHA-384 and SHA-512) cryptographic + * hash functions are defined in FIPS 180-4: Secure Hash Standard (SHS). + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_SHA512_H +#define MBEDTLS_SHA512_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include + +/* MBEDTLS_ERR_SHA512_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_SHA512_HW_ACCEL_FAILED -0x0039 /**< SHA-512 hardware accelerator failed */ +#define MBEDTLS_ERR_SHA512_BAD_INPUT_DATA -0x0075 /**< SHA-512 input data was malformed. */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_SHA512_ALT) +// Regular implementation +// + +/** + * \brief The SHA-512 context structure. + * + * The structure is used both for SHA-384 and for SHA-512 + * checksum calculations. The choice between these two is + * made in the call to mbedtls_sha512_starts_ret(). + */ +typedef struct mbedtls_sha512_context +{ + uint64_t total[2]; /*!< The number of Bytes processed. */ + uint64_t state[8]; /*!< The intermediate digest state. */ + unsigned char buffer[128]; /*!< The data block being processed. */ + int is384; /*!< Determines which function to use: + 0: Use SHA-512, or 1: Use SHA-384. */ +} +mbedtls_sha512_context; + +#else /* MBEDTLS_SHA512_ALT */ +#include "sha512_alt.h" +#endif /* MBEDTLS_SHA512_ALT */ + +/** + * \brief This function initializes a SHA-512 context. + * + * \param ctx The SHA-512 context to initialize. This must + * not be \c NULL. + */ +void mbedtls_sha512_init( mbedtls_sha512_context *ctx ); + +/** + * \brief This function clears a SHA-512 context. + * + * \param ctx The SHA-512 context to clear. This may be \c NULL, + * in which case this function does nothing. If it + * is not \c NULL, it must point to an initialized + * SHA-512 context. + */ +void mbedtls_sha512_free( mbedtls_sha512_context *ctx ); + +/** + * \brief This function clones the state of a SHA-512 context. + * + * \param dst The destination context. This must be initialized. + * \param src The context to clone. This must be initialized. + */ +void mbedtls_sha512_clone( mbedtls_sha512_context *dst, + const mbedtls_sha512_context *src ); + +/** + * \brief This function starts a SHA-384 or SHA-512 checksum + * calculation. + * + * \param ctx The SHA-512 context to use. This must be initialized. + * \param is384 Determines which function to use. This must be + * either \c for SHA-512, or \c 1 for SHA-384. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384 ); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-512 checksum calculation. + * + * \param ctx The SHA-512 context. This must be initialized + * and have a hash operation started. + * \param input The buffer holding the input data. This must + * be a readable buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief This function finishes the SHA-512 operation, and writes + * the result to the output buffer. + * + * \param ctx The SHA-512 context. This must be initialized + * and have a hash operation started. + * \param output The SHA-384 or SHA-512 checksum result. + * This must be a writable buffer of length \c 64 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, + unsigned char output[64] ); + +/** + * \brief This function processes a single data block within + * the ongoing SHA-512 computation. + * This function is for internal use only. + * + * \param ctx The SHA-512 context. This must be initialized. + * \param data The buffer holding one block of data. This + * must be a readable buffer of length \c 128 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx, + const unsigned char data[128] ); +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief This function starts a SHA-384 or SHA-512 checksum + * calculation. + * + * \deprecated Superseded by mbedtls_sha512_starts_ret() in 2.7.0 + * + * \param ctx The SHA-512 context to use. This must be initialized. + * \param is384 Determines which function to use. This must be either + * \c 0 for SHA-512 or \c 1 for SHA-384. + */ +MBEDTLS_DEPRECATED void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, + int is384 ); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-512 checksum calculation. + * + * \deprecated Superseded by mbedtls_sha512_update_ret() in 2.7.0. + * + * \param ctx The SHA-512 context. This must be initialized + * and have a hash operation started. + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + */ +MBEDTLS_DEPRECATED void mbedtls_sha512_update( mbedtls_sha512_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief This function finishes the SHA-512 operation, and writes + * the result to the output buffer. + * + * \deprecated Superseded by mbedtls_sha512_finish_ret() in 2.7.0. + * + * \param ctx The SHA-512 context. This must be initialized + * and have a hash operation started. + * \param output The SHA-384 or SHA-512 checksum result. This must + * be a writable buffer of size \c 64 Bytes. + */ +MBEDTLS_DEPRECATED void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, + unsigned char output[64] ); + +/** + * \brief This function processes a single data block within + * the ongoing SHA-512 computation. This function is for + * internal use only. + * + * \deprecated Superseded by mbedtls_internal_sha512_process() in 2.7.0. + * + * \param ctx The SHA-512 context. This must be initialized. + * \param data The buffer holding one block of data. This must be + * a readable buffer of length \c 128 Bytes. + */ +MBEDTLS_DEPRECATED void mbedtls_sha512_process( + mbedtls_sha512_context *ctx, + const unsigned char data[128] ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief This function calculates the SHA-512 or SHA-384 + * checksum of a buffer. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The SHA-512 result is calculated as + * output = SHA-512(input buffer). + * + * \param input The buffer holding the input data. This must be + * a readable buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The SHA-384 or SHA-512 checksum result. + * This must be a writable buffer of length \c 64 Bytes. + * \param is384 Determines which function to use. This must be either + * \c 0 for SHA-512, or \c 1 for SHA-384. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha512_ret( const unsigned char *input, + size_t ilen, + unsigned char output[64], + int is384 ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif + +/** + * \brief This function calculates the SHA-512 or SHA-384 + * checksum of a buffer. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The SHA-512 result is calculated as + * output = SHA-512(input buffer). + * + * \deprecated Superseded by mbedtls_sha512_ret() in 2.7.0 + * + * \param input The buffer holding the data. This must be a + * readable buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The SHA-384 or SHA-512 checksum result. This must + * be a writable buffer of length \c 64 Bytes. + * \param is384 Determines which function to use. This must be either + * \c 0 for SHA-512, or \c 1 for SHA-384. + */ +MBEDTLS_DEPRECATED void mbedtls_sha512( const unsigned char *input, + size_t ilen, + unsigned char output[64], + int is384 ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_SELF_TEST) + + /** + * \brief The SHA-384 or SHA-512 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_sha512_self_test( int verbose ); +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_sha512.h */ diff --git a/src/common/mbedtls/include/mbedtls/version.h b/src/common/mbedtls/include/mbedtls/version.h new file mode 100644 index 0000000000..f6779bcaa3 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/version.h @@ -0,0 +1,122 @@ +/** + * \file version.h + * + * \brief Run-time version information + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +/* + * This set of compile-time defines and run-time variables can be used to + * determine the version number of the mbed TLS library used. + */ +#ifndef MBEDTLS_VERSION_H +#define MBEDTLS_VERSION_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +/** + * The version number x.y.z is split into three parts. + * Major, Minor, Patchlevel + */ +#define MBEDTLS_VERSION_MAJOR 2 +#define MBEDTLS_VERSION_MINOR 16 +#define MBEDTLS_VERSION_PATCH 11 + +/** + * The single version number has the following structure: + * MMNNPP00 + * Major version | Minor version | Patch version + */ +#define MBEDTLS_VERSION_NUMBER 0x02100B00 +#define MBEDTLS_VERSION_STRING "2.16.11" +#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.16.11" + +#if defined(MBEDTLS_VERSION_C) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Get the version number. + * + * \return The constructed version number in the format + * MMNNPP00 (Major, Minor, Patch). + */ +unsigned int mbedtls_version_get_number( void ); + +/** + * Get the version string ("x.y.z"). + * + * \param string The string that will receive the value. + * (Should be at least 9 bytes in size) + */ +void mbedtls_version_get_string( char *string ); + +/** + * Get the full version string ("mbed TLS x.y.z"). + * + * \param string The string that will receive the value. The mbed TLS version + * string will use 18 bytes AT MOST including a terminating + * null byte. + * (So the buffer should be at least 18 bytes to receive this + * version string). + */ +void mbedtls_version_get_string_full( char *string ); + +/** + * \brief Check if support for a feature was compiled into this + * mbed TLS binary. This allows you to see at runtime if the + * library was for instance compiled with or without + * Multi-threading support. + * + * \note only checks against defines in the sections "System + * support", "mbed TLS modules" and "mbed TLS feature + * support" in config.h + * + * \param feature The string for the define to check (e.g. "MBEDTLS_AES_C") + * + * \return 0 if the feature is present, + * -1 if the feature is not present and + * -2 if support for feature checking as a whole was not + * compiled in. + */ +int mbedtls_version_check_feature( const char *feature ); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_VERSION_C */ + +#endif /* version.h */ diff --git a/src/common/mbedtls/include/mbedtls/x509.h b/src/common/mbedtls/include/mbedtls/x509.h new file mode 100644 index 0000000000..302603f809 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/x509.h @@ -0,0 +1,347 @@ +/** + * \file x509.h + * + * \brief X.509 generic defines and structures + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_X509_H +#define MBEDTLS_X509_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "asn1.h" +#include "pk.h" + +#if defined(MBEDTLS_RSA_C) +#include "rsa.h" +#endif + +/** + * \addtogroup x509_module + * \{ + */ + +#if !defined(MBEDTLS_X509_MAX_INTERMEDIATE_CA) +/** + * Maximum number of intermediate CAs in a verification chain. + * That is, maximum length of the chain, excluding the end-entity certificate + * and the trusted root certificate. + * + * Set this to a low value to prevent an adversary from making you waste + * resources verifying an overlong certificate chain. + */ +#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +#endif + +/** + * \name X509 Error codes + * \{ + */ +#define MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE -0x2080 /**< Unavailable feature, e.g. RSA hashing/encryption combination. */ +#define MBEDTLS_ERR_X509_UNKNOWN_OID -0x2100 /**< Requested OID is unknown. */ +#define MBEDTLS_ERR_X509_INVALID_FORMAT -0x2180 /**< The CRT/CRL/CSR format is invalid, e.g. different type expected. */ +#define MBEDTLS_ERR_X509_INVALID_VERSION -0x2200 /**< The CRT/CRL/CSR version element is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_SERIAL -0x2280 /**< The serial tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_ALG -0x2300 /**< The algorithm tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_NAME -0x2380 /**< The name tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_DATE -0x2400 /**< The date tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_SIGNATURE -0x2480 /**< The signature tag or value invalid. */ +#define MBEDTLS_ERR_X509_INVALID_EXTENSIONS -0x2500 /**< The extension tag or value is invalid. */ +#define MBEDTLS_ERR_X509_UNKNOWN_VERSION -0x2580 /**< CRT/CRL/CSR has an unsupported version number. */ +#define MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG -0x2600 /**< Signature algorithm (oid) is unsupported. */ +#define MBEDTLS_ERR_X509_SIG_MISMATCH -0x2680 /**< Signature algorithms do not match. (see \c ::mbedtls_x509_crt sig_oid) */ +#define MBEDTLS_ERR_X509_CERT_VERIFY_FAILED -0x2700 /**< Certificate verification failed, e.g. CRL, CA or signature check failed. */ +#define MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT -0x2780 /**< Format not recognized as DER or PEM. */ +#define MBEDTLS_ERR_X509_BAD_INPUT_DATA -0x2800 /**< Input invalid. */ +#define MBEDTLS_ERR_X509_ALLOC_FAILED -0x2880 /**< Allocation of memory failed. */ +#define MBEDTLS_ERR_X509_FILE_IO_ERROR -0x2900 /**< Read/write of file failed. */ +#define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL -0x2980 /**< Destination buffer is too small. */ +#define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 /**< A fatal error occurred, eg the chain is too long or the vrfy callback failed. */ +/* \} name */ + +/** + * \name X509 Verify codes + * \{ + */ +/* Reminder: update x509_crt_verify_strings[] in library/x509_crt.c */ +#define MBEDTLS_X509_BADCERT_EXPIRED 0x01 /**< The certificate validity has expired. */ +#define MBEDTLS_X509_BADCERT_REVOKED 0x02 /**< The certificate has been revoked (is on a CRL). */ +#define MBEDTLS_X509_BADCERT_CN_MISMATCH 0x04 /**< The certificate Common Name (CN) does not match with the expected CN. */ +#define MBEDTLS_X509_BADCERT_NOT_TRUSTED 0x08 /**< The certificate is not correctly signed by the trusted CA. */ +#define MBEDTLS_X509_BADCRL_NOT_TRUSTED 0x10 /**< The CRL is not correctly signed by the trusted CA. */ +#define MBEDTLS_X509_BADCRL_EXPIRED 0x20 /**< The CRL is expired. */ +#define MBEDTLS_X509_BADCERT_MISSING 0x40 /**< Certificate was missing. */ +#define MBEDTLS_X509_BADCERT_SKIP_VERIFY 0x80 /**< Certificate verification was skipped. */ +#define MBEDTLS_X509_BADCERT_OTHER 0x0100 /**< Other reason (can be used by verify callback) */ +#define MBEDTLS_X509_BADCERT_FUTURE 0x0200 /**< The certificate validity starts in the future. */ +#define MBEDTLS_X509_BADCRL_FUTURE 0x0400 /**< The CRL is from the future */ +#define MBEDTLS_X509_BADCERT_KEY_USAGE 0x0800 /**< Usage does not match the keyUsage extension. */ +#define MBEDTLS_X509_BADCERT_EXT_KEY_USAGE 0x1000 /**< Usage does not match the extendedKeyUsage extension. */ +#define MBEDTLS_X509_BADCERT_NS_CERT_TYPE 0x2000 /**< Usage does not match the nsCertType extension. */ +#define MBEDTLS_X509_BADCERT_BAD_MD 0x4000 /**< The certificate is signed with an unacceptable hash. */ +#define MBEDTLS_X509_BADCERT_BAD_PK 0x8000 /**< The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA). */ +#define MBEDTLS_X509_BADCERT_BAD_KEY 0x010000 /**< The certificate is signed with an unacceptable key (eg bad curve, RSA too short). */ +#define MBEDTLS_X509_BADCRL_BAD_MD 0x020000 /**< The CRL is signed with an unacceptable hash. */ +#define MBEDTLS_X509_BADCRL_BAD_PK 0x040000 /**< The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA). */ +#define MBEDTLS_X509_BADCRL_BAD_KEY 0x080000 /**< The CRL is signed with an unacceptable key (eg bad curve, RSA too short). */ + +/* \} name */ +/* \} addtogroup x509_module */ + +/* + * X.509 v3 Key Usage Extension flags + * Reminder: update x509_info_key_usage() when adding new flags. + */ +#define MBEDTLS_X509_KU_DIGITAL_SIGNATURE (0x80) /* bit 0 */ +#define MBEDTLS_X509_KU_NON_REPUDIATION (0x40) /* bit 1 */ +#define MBEDTLS_X509_KU_KEY_ENCIPHERMENT (0x20) /* bit 2 */ +#define MBEDTLS_X509_KU_DATA_ENCIPHERMENT (0x10) /* bit 3 */ +#define MBEDTLS_X509_KU_KEY_AGREEMENT (0x08) /* bit 4 */ +#define MBEDTLS_X509_KU_KEY_CERT_SIGN (0x04) /* bit 5 */ +#define MBEDTLS_X509_KU_CRL_SIGN (0x02) /* bit 6 */ +#define MBEDTLS_X509_KU_ENCIPHER_ONLY (0x01) /* bit 7 */ +#define MBEDTLS_X509_KU_DECIPHER_ONLY (0x8000) /* bit 8 */ + +/* + * Netscape certificate types + * (https://www.mozilla.org/projects/security/pki/nss/tech-notes/tn3.html) + */ + +#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT (0x80) /* bit 0 */ +#define MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER (0x40) /* bit 1 */ +#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL (0x20) /* bit 2 */ +#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING (0x10) /* bit 3 */ +#define MBEDTLS_X509_NS_CERT_TYPE_RESERVED (0x08) /* bit 4 */ +#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CA (0x04) /* bit 5 */ +#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA (0x02) /* bit 6 */ +#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA (0x01) /* bit 7 */ + +/* + * X.509 extension types + * + * Comments refer to the status for using certificates. Status can be + * different for writing certificates or reading CRLs or CSRs. + */ +#define MBEDTLS_X509_EXT_AUTHORITY_KEY_IDENTIFIER (1 << 0) +#define MBEDTLS_X509_EXT_SUBJECT_KEY_IDENTIFIER (1 << 1) +#define MBEDTLS_X509_EXT_KEY_USAGE (1 << 2) +#define MBEDTLS_X509_EXT_CERTIFICATE_POLICIES (1 << 3) +#define MBEDTLS_X509_EXT_POLICY_MAPPINGS (1 << 4) +#define MBEDTLS_X509_EXT_SUBJECT_ALT_NAME (1 << 5) /* Supported (DNS) */ +#define MBEDTLS_X509_EXT_ISSUER_ALT_NAME (1 << 6) +#define MBEDTLS_X509_EXT_SUBJECT_DIRECTORY_ATTRS (1 << 7) +#define MBEDTLS_X509_EXT_BASIC_CONSTRAINTS (1 << 8) /* Supported */ +#define MBEDTLS_X509_EXT_NAME_CONSTRAINTS (1 << 9) +#define MBEDTLS_X509_EXT_POLICY_CONSTRAINTS (1 << 10) +#define MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE (1 << 11) +#define MBEDTLS_X509_EXT_CRL_DISTRIBUTION_POINTS (1 << 12) +#define MBEDTLS_X509_EXT_INIHIBIT_ANYPOLICY (1 << 13) +#define MBEDTLS_X509_EXT_FRESHEST_CRL (1 << 14) + +#define MBEDTLS_X509_EXT_NS_CERT_TYPE (1 << 16) + +/* + * Storage format identifiers + * Recognized formats: PEM and DER + */ +#define MBEDTLS_X509_FORMAT_DER 1 +#define MBEDTLS_X509_FORMAT_PEM 2 + +#define MBEDTLS_X509_MAX_DN_NAME_SIZE 256 /**< Maximum value size of a DN entry */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup x509_module + * \{ */ + +/** + * \name Structures for parsing X.509 certificates, CRLs and CSRs + * \{ + */ + +/** + * Type-length-value structure that allows for ASN1 using DER. + */ +typedef mbedtls_asn1_buf mbedtls_x509_buf; + +/** + * Container for ASN1 bit strings. + */ +typedef mbedtls_asn1_bitstring mbedtls_x509_bitstring; + +/** + * Container for ASN1 named information objects. + * It allows for Relative Distinguished Names (e.g. cn=localhost,ou=code,etc.). + */ +typedef mbedtls_asn1_named_data mbedtls_x509_name; + +/** + * Container for a sequence of ASN.1 items + */ +typedef mbedtls_asn1_sequence mbedtls_x509_sequence; + +/** Container for date and time (precision in seconds). */ +typedef struct mbedtls_x509_time +{ + int year, mon, day; /**< Date. */ + int hour, min, sec; /**< Time. */ +} +mbedtls_x509_time; + +/** \} name Structures for parsing X.509 certificates, CRLs and CSRs */ +/** \} addtogroup x509_module */ + +/** + * \brief Store the certificate DN in printable form into buf; + * no more than size characters will be written. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param dn The X509 name to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_dn_gets( char *buf, size_t size, const mbedtls_x509_name *dn ); + +/** + * \brief Store the certificate serial in printable form into buf; + * no more than size characters will be written. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param serial The X509 serial to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_serial_gets( char *buf, size_t size, const mbedtls_x509_buf *serial ); + +/** + * \brief Check a given mbedtls_x509_time against the system time + * and tell if it's in the past. + * + * \note Intended usage is "if( is_past( valid_to ) ) ERROR". + * Hence the return value of 1 if on internal errors. + * + * \param to mbedtls_x509_time to check + * + * \return 1 if the given time is in the past or an error occurred, + * 0 otherwise. + */ +int mbedtls_x509_time_is_past( const mbedtls_x509_time *to ); + +/** + * \brief Check a given mbedtls_x509_time against the system time + * and tell if it's in the future. + * + * \note Intended usage is "if( is_future( valid_from ) ) ERROR". + * Hence the return value of 1 if on internal errors. + * + * \param from mbedtls_x509_time to check + * + * \return 1 if the given time is in the future or an error occurred, + * 0 otherwise. + */ +int mbedtls_x509_time_is_future( const mbedtls_x509_time *from ); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_x509_self_test( int verbose ); + +#endif /* MBEDTLS_SELF_TEST */ + +/* + * Internal module functions. You probably do not want to use these unless you + * know you do. + */ +int mbedtls_x509_get_name( unsigned char **p, const unsigned char *end, + mbedtls_x509_name *cur ); +int mbedtls_x509_get_alg_null( unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *alg ); +int mbedtls_x509_get_alg( unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *alg, mbedtls_x509_buf *params ); +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) +int mbedtls_x509_get_rsassa_pss_params( const mbedtls_x509_buf *params, + mbedtls_md_type_t *md_alg, mbedtls_md_type_t *mgf_md, + int *salt_len ); +#endif +int mbedtls_x509_get_sig( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *sig ); +int mbedtls_x509_get_sig_alg( const mbedtls_x509_buf *sig_oid, const mbedtls_x509_buf *sig_params, + mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg, + void **sig_opts ); +int mbedtls_x509_get_time( unsigned char **p, const unsigned char *end, + mbedtls_x509_time *t ); +int mbedtls_x509_get_serial( unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *serial ); +int mbedtls_x509_get_ext( unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *ext, int tag ); +int mbedtls_x509_sig_alg_gets( char *buf, size_t size, const mbedtls_x509_buf *sig_oid, + mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg, + const void *sig_opts ); +int mbedtls_x509_key_size_helper( char *buf, size_t buf_size, const char *name ); +int mbedtls_x509_string_to_names( mbedtls_asn1_named_data **head, const char *name ); +int mbedtls_x509_set_extension( mbedtls_asn1_named_data **head, const char *oid, size_t oid_len, + int critical, const unsigned char *val, + size_t val_len ); +int mbedtls_x509_write_extensions( unsigned char **p, unsigned char *start, + mbedtls_asn1_named_data *first ); +int mbedtls_x509_write_names( unsigned char **p, unsigned char *start, + mbedtls_asn1_named_data *first ); +int mbedtls_x509_write_sig( unsigned char **p, unsigned char *start, + const char *oid, size_t oid_len, + unsigned char *sig, size_t size ); + +#define MBEDTLS_X509_SAFE_SNPRINTF \ + do { \ + if( ret < 0 || (size_t) ret >= n ) \ + return( MBEDTLS_ERR_X509_BUFFER_TOO_SMALL ); \ + \ + n -= (size_t) ret; \ + p += (size_t) ret; \ + } while( 0 ) + +#ifdef __cplusplus +} +#endif + +#endif /* x509.h */ diff --git a/src/common/mbedtls/include/mbedtls/x509_crl.h b/src/common/mbedtls/include/mbedtls/x509_crl.h new file mode 100644 index 0000000000..54bd4ef735 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/x509_crl.h @@ -0,0 +1,184 @@ +/** + * \file x509_crl.h + * + * \brief X.509 certificate revocation list parsing + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_X509_CRL_H +#define MBEDTLS_X509_CRL_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "x509.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup x509_module + * \{ */ + +/** + * \name Structures and functions for parsing CRLs + * \{ + */ + +/** + * Certificate revocation list entry. + * Contains the CA-specific serial numbers and revocation dates. + */ +typedef struct mbedtls_x509_crl_entry +{ + mbedtls_x509_buf raw; + + mbedtls_x509_buf serial; + + mbedtls_x509_time revocation_date; + + mbedtls_x509_buf entry_ext; + + struct mbedtls_x509_crl_entry *next; +} +mbedtls_x509_crl_entry; + +/** + * Certificate revocation list structure. + * Every CRL may have multiple entries. + */ +typedef struct mbedtls_x509_crl +{ + mbedtls_x509_buf raw; /**< The raw certificate data (DER). */ + mbedtls_x509_buf tbs; /**< The raw certificate body (DER). The part that is To Be Signed. */ + + int version; /**< CRL version (1=v1, 2=v2) */ + mbedtls_x509_buf sig_oid; /**< CRL signature type identifier */ + + mbedtls_x509_buf issuer_raw; /**< The raw issuer data (DER). */ + + mbedtls_x509_name issuer; /**< The parsed issuer data (named information object). */ + + mbedtls_x509_time this_update; + mbedtls_x509_time next_update; + + mbedtls_x509_crl_entry entry; /**< The CRL entries containing the certificate revocation times for this CA. */ + + mbedtls_x509_buf crl_ext; + + mbedtls_x509_buf sig_oid2; + mbedtls_x509_buf sig; + mbedtls_md_type_t sig_md; /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ + mbedtls_pk_type_t sig_pk; /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ + void *sig_opts; /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ + + struct mbedtls_x509_crl *next; +} +mbedtls_x509_crl; + +/** + * \brief Parse a DER-encoded CRL and append it to the chained list + * + * \param chain points to the start of the chain + * \param buf buffer holding the CRL data in DER format + * \param buflen size of the buffer + * (including the terminating null byte for PEM data) + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_crl_parse_der( mbedtls_x509_crl *chain, + const unsigned char *buf, size_t buflen ); +/** + * \brief Parse one or more CRLs and append them to the chained list + * + * \note Multiple CRLs are accepted only if using PEM format + * + * \param chain points to the start of the chain + * \param buf buffer holding the CRL data in PEM or DER format + * \param buflen size of the buffer + * (including the terminating null byte for PEM data) + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_crl_parse( mbedtls_x509_crl *chain, const unsigned char *buf, size_t buflen ); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Load one or more CRLs and append them to the chained list + * + * \note Multiple CRLs are accepted only if using PEM format + * + * \param chain points to the start of the chain + * \param path filename to read the CRLs from (in PEM or DER encoding) + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_crl_parse_file( mbedtls_x509_crl *chain, const char *path ); +#endif /* MBEDTLS_FS_IO */ + +/** + * \brief Returns an informational string about the CRL. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param prefix A line prefix + * \param crl The X509 CRL to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_crl_info( char *buf, size_t size, const char *prefix, + const mbedtls_x509_crl *crl ); + +/** + * \brief Initialize a CRL (chain) + * + * \param crl CRL chain to initialize + */ +void mbedtls_x509_crl_init( mbedtls_x509_crl *crl ); + +/** + * \brief Unallocate all CRL data + * + * \param crl CRL chain to free + */ +void mbedtls_x509_crl_free( mbedtls_x509_crl *crl ); + +/* \} name */ +/* \} addtogroup x509_module */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_x509_crl.h */ diff --git a/src/common/mbedtls/include/mbedtls/x509_crt.h b/src/common/mbedtls/include/mbedtls/x509_crt.h new file mode 100644 index 0000000000..09edb22c21 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/x509_crt.h @@ -0,0 +1,804 @@ +/** + * \file x509_crt.h + * + * \brief X.509 certificate parsing and writing + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_X509_CRT_H +#define MBEDTLS_X509_CRT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "x509.h" +#include "x509_crl.h" + +/** + * \addtogroup x509_module + * \{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name Structures and functions for parsing and writing X.509 certificates + * \{ + */ + +/** + * Container for an X.509 certificate. The certificate may be chained. + */ +typedef struct mbedtls_x509_crt +{ + mbedtls_x509_buf raw; /**< The raw certificate data (DER). */ + mbedtls_x509_buf tbs; /**< The raw certificate body (DER). The part that is To Be Signed. */ + + int version; /**< The X.509 version. (1=v1, 2=v2, 3=v3) */ + mbedtls_x509_buf serial; /**< Unique id for certificate issued by a specific CA. */ + mbedtls_x509_buf sig_oid; /**< Signature algorithm, e.g. sha1RSA */ + + mbedtls_x509_buf issuer_raw; /**< The raw issuer data (DER). Used for quick comparison. */ + mbedtls_x509_buf subject_raw; /**< The raw subject data (DER). Used for quick comparison. */ + + mbedtls_x509_name issuer; /**< The parsed issuer data (named information object). */ + mbedtls_x509_name subject; /**< The parsed subject data (named information object). */ + + mbedtls_x509_time valid_from; /**< Start time of certificate validity. */ + mbedtls_x509_time valid_to; /**< End time of certificate validity. */ + + mbedtls_pk_context pk; /**< Container for the public key context. */ + + mbedtls_x509_buf issuer_id; /**< Optional X.509 v2/v3 issuer unique identifier. */ + mbedtls_x509_buf subject_id; /**< Optional X.509 v2/v3 subject unique identifier. */ + mbedtls_x509_buf v3_ext; /**< Optional X.509 v3 extensions. */ + mbedtls_x509_sequence subject_alt_names; /**< Optional list of Subject Alternative Names (Only dNSName supported). */ + + int ext_types; /**< Bit string containing detected and parsed extensions */ + int ca_istrue; /**< Optional Basic Constraint extension value: 1 if this certificate belongs to a CA, 0 otherwise. */ + int max_pathlen; /**< Optional Basic Constraint extension value: The maximum path length to the root certificate. Path length is 1 higher than RFC 5280 'meaning', so 1+ */ + + unsigned int key_usage; /**< Optional key usage extension value: See the values in x509.h */ + + mbedtls_x509_sequence ext_key_usage; /**< Optional list of extended key usage OIDs. */ + + unsigned char ns_cert_type; /**< Optional Netscape certificate type extension value: See the values in x509.h */ + + mbedtls_x509_buf sig; /**< Signature: hash of the tbs part signed with the private key. */ + mbedtls_md_type_t sig_md; /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ + mbedtls_pk_type_t sig_pk; /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ + void *sig_opts; /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ + + struct mbedtls_x509_crt *next; /**< Next certificate in the CA-chain. */ +} +mbedtls_x509_crt; + +/** + * Build flag from an algorithm/curve identifier (pk, md, ecp) + * Since 0 is always XXX_NONE, ignore it. + */ +#define MBEDTLS_X509_ID_FLAG( id ) ( 1 << ( (id) - 1 ) ) + +/** + * Security profile for certificate verification. + * + * All lists are bitfields, built by ORing flags from MBEDTLS_X509_ID_FLAG(). + */ +typedef struct mbedtls_x509_crt_profile +{ + uint32_t allowed_mds; /**< MDs for signatures */ + uint32_t allowed_pks; /**< PK algs for signatures */ + uint32_t allowed_curves; /**< Elliptic curves for ECDSA */ + uint32_t rsa_min_bitlen; /**< Minimum size for RSA keys */ +} +mbedtls_x509_crt_profile; + +#define MBEDTLS_X509_CRT_VERSION_1 0 +#define MBEDTLS_X509_CRT_VERSION_2 1 +#define MBEDTLS_X509_CRT_VERSION_3 2 + +#define MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN 32 +#define MBEDTLS_X509_RFC5280_UTC_TIME_LEN 15 + +#if !defined( MBEDTLS_X509_MAX_FILE_PATH_LEN ) +#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 +#endif + +/** + * Container for writing a certificate (CRT) + */ +typedef struct mbedtls_x509write_cert +{ + int version; + mbedtls_mpi serial; + mbedtls_pk_context *subject_key; + mbedtls_pk_context *issuer_key; + mbedtls_asn1_named_data *subject; + mbedtls_asn1_named_data *issuer; + mbedtls_md_type_t md_alg; + char not_before[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1]; + char not_after[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1]; + mbedtls_asn1_named_data *extensions; +} +mbedtls_x509write_cert; + +/** + * Item in a verification chain: cert and flags for it + */ +typedef struct { + mbedtls_x509_crt *crt; + uint32_t flags; +} mbedtls_x509_crt_verify_chain_item; + +/** + * Max size of verification chain: end-entity + intermediates + trusted root + */ +#define MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE ( MBEDTLS_X509_MAX_INTERMEDIATE_CA + 2 ) + +/** + * Verification chain as built by \c mbedtls_crt_verify_chain() + */ +typedef struct +{ + mbedtls_x509_crt_verify_chain_item items[MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE]; + unsigned len; +} mbedtls_x509_crt_verify_chain; + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + +/** + * \brief Context for resuming X.509 verify operations + */ +typedef struct +{ + /* for check_signature() */ + mbedtls_pk_restart_ctx pk; + + /* for find_parent_in() */ + mbedtls_x509_crt *parent; /* non-null iff parent_in in progress */ + mbedtls_x509_crt *fallback_parent; + int fallback_signature_is_good; + + /* for find_parent() */ + int parent_is_trusted; /* -1 if find_parent is not in progress */ + + /* for verify_chain() */ + enum { + x509_crt_rs_none, + x509_crt_rs_find_parent, + } in_progress; /* none if no operation is in progress */ + int self_cnt; + mbedtls_x509_crt_verify_chain ver_chain; + +} mbedtls_x509_crt_restart_ctx; + +#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +/* Now we can declare functions that take a pointer to that */ +typedef void mbedtls_x509_crt_restart_ctx; + +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/** + * Default security profile. Should provide a good balance between security + * and compatibility with current deployments. + * + * This profile permits: + * - SHA2 hashes. + * - All supported elliptic curves. + * - RSA with 2048 bits and above. + * + * New minor versions of Mbed TLS may extend this profile, for example if + * new curves are added to the library. New minor versions of Mbed TLS will + * not reduce this profile unless serious security concerns require it. + */ +extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default; + +/** + * Expected next default profile. Recommended for new deployments. + * Currently targets a 128-bit security level, except for allowing RSA-2048. + */ +extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_next; + +/** + * NSA Suite B profile. + */ +extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_suiteb; + +/** + * \brief Parse a single DER formatted certificate and add it + * to the chained list. + * + * \param chain points to the start of the chain + * \param buf buffer holding the certificate DER data + * \param buflen size of the buffer + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_crt_parse_der( mbedtls_x509_crt *chain, const unsigned char *buf, + size_t buflen ); + +/** + * \brief Parse one DER-encoded or one or more concatenated PEM-encoded + * certificates and add them to the chained list. + * + * For CRTs in PEM encoding, the function parses permissively: + * if at least one certificate can be parsed, the function + * returns the number of certificates for which parsing failed + * (hence \c 0 if all certificates were parsed successfully). + * If no certificate could be parsed, the function returns + * the first (negative) error encountered during parsing. + * + * PEM encoded certificates may be interleaved by other data + * such as human readable descriptions of their content, as + * long as the certificates are enclosed in the PEM specific + * '-----{BEGIN/END} CERTIFICATE-----' delimiters. + * + * \param chain The chain to which to add the parsed certificates. + * \param buf The buffer holding the certificate data in PEM or DER format. + * For certificates in PEM encoding, this may be a concatenation + * of multiple certificates; for DER encoding, the buffer must + * comprise exactly one certificate. + * \param buflen The size of \p buf, including the terminating \c NULL byte + * in case of PEM encoded data. + * + * \return \c 0 if all certificates were parsed successfully. + * \return The (positive) number of certificates that couldn't + * be parsed if parsing was partly successful (see above). + * \return A negative X509 or PEM error code otherwise. + * + */ +int mbedtls_x509_crt_parse( mbedtls_x509_crt *chain, const unsigned char *buf, size_t buflen ); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Load one or more certificates and add them + * to the chained list. Parses permissively. If some + * certificates can be parsed, the result is the number + * of failed certificates it encountered. If none complete + * correctly, the first error is returned. + * + * \param chain points to the start of the chain + * \param path filename to read the certificates from + * + * \return 0 if all certificates parsed successfully, a positive number + * if partly successful or a specific X509 or PEM error code + */ +int mbedtls_x509_crt_parse_file( mbedtls_x509_crt *chain, const char *path ); + +/** + * \brief Load one or more certificate files from a path and add them + * to the chained list. Parses permissively. If some + * certificates can be parsed, the result is the number + * of failed certificates it encountered. If none complete + * correctly, the first error is returned. + * + * \param chain points to the start of the chain + * \param path directory / folder to read the certificate files from + * + * \return 0 if all certificates parsed successfully, a positive number + * if partly successful or a specific X509 or PEM error code + */ +int mbedtls_x509_crt_parse_path( mbedtls_x509_crt *chain, const char *path ); +#endif /* MBEDTLS_FS_IO */ + +/** + * \brief Returns an informational string about the + * certificate. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param prefix A line prefix + * \param crt The X509 certificate to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_crt_info( char *buf, size_t size, const char *prefix, + const mbedtls_x509_crt *crt ); + +/** + * \brief Returns an informational string about the + * verification status of a certificate. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param prefix A line prefix + * \param flags Verification flags created by mbedtls_x509_crt_verify() + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_crt_verify_info( char *buf, size_t size, const char *prefix, + uint32_t flags ); + +/** + * \brief Verify the certificate signature + * + * The verify callback is a user-supplied callback that + * can clear / modify / add flags for a certificate. If set, + * the verification callback is called for each + * certificate in the chain (from the trust-ca down to the + * presented crt). The parameters for the callback are: + * (void *parameter, mbedtls_x509_crt *crt, int certificate_depth, + * int *flags). With the flags representing current flags for + * that specific certificate and the certificate depth from + * the bottom (Peer cert depth = 0). + * + * All flags left after returning from the callback + * are also returned to the application. The function should + * return 0 for anything (including invalid certificates) + * other than fatal error, as a non-zero return code + * immediately aborts the verification process. For fatal + * errors, a specific error code should be used (different + * from MBEDTLS_ERR_X509_CERT_VERIFY_FAILED which should not + * be returned at this point), or MBEDTLS_ERR_X509_FATAL_ERROR + * can be used if no better code is available. + * + * \note In case verification failed, the results can be displayed + * using \c mbedtls_x509_crt_verify_info() + * + * \note Same as \c mbedtls_x509_crt_verify_with_profile() with the + * default security profile. + * + * \note It is your responsibility to provide up-to-date CRLs for + * all trusted CAs. If no CRL is provided for the CA that was + * used to sign the certificate, CRL verification is skipped + * silently, that is *without* setting any flag. + * + * \note The \c trust_ca list can contain two types of certificates: + * (1) those of trusted root CAs, so that certificates + * chaining up to those CAs will be trusted, and (2) + * self-signed end-entity certificates to be trusted (for + * specific peers you know) - in that case, the self-signed + * certificate doesn't need to have the CA bit set. + * + * \param crt a certificate (chain) to be verified + * \param trust_ca the list of trusted CAs (see note above) + * \param ca_crl the list of CRLs for trusted CAs (see note above) + * \param cn expected Common Name (can be set to + * NULL if the CN must not be verified) + * \param flags result of the verification + * \param f_vrfy verification function + * \param p_vrfy verification parameter + * + * \return 0 (and flags set to 0) if the chain was verified and valid, + * MBEDTLS_ERR_X509_CERT_VERIFY_FAILED if the chain was verified + * but found to be invalid, in which case *flags will have one + * or more MBEDTLS_X509_BADCERT_XXX or MBEDTLS_X509_BADCRL_XXX + * flags set, or another error (and flags set to 0xffffffff) + * in case of a fatal error encountered during the + * verification process. + */ +int mbedtls_x509_crt_verify( mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy ); + +/** + * \brief Verify the certificate signature according to profile + * + * \note Same as \c mbedtls_x509_crt_verify(), but with explicit + * security profile. + * + * \note The restrictions on keys (RSA minimum size, allowed curves + * for ECDSA) apply to all certificates: trusted root, + * intermediate CAs if any, and end entity certificate. + * + * \param crt a certificate (chain) to be verified + * \param trust_ca the list of trusted CAs + * \param ca_crl the list of CRLs for trusted CAs + * \param profile security profile for verification + * \param cn expected Common Name (can be set to + * NULL if the CN must not be verified) + * \param flags result of the verification + * \param f_vrfy verification function + * \param p_vrfy verification parameter + * + * \return 0 if successful or MBEDTLS_ERR_X509_CERT_VERIFY_FAILED + * in which case *flags will have one or more + * MBEDTLS_X509_BADCERT_XXX or MBEDTLS_X509_BADCRL_XXX flags + * set, + * or another error in case of a fatal error encountered + * during the verification process. + */ +int mbedtls_x509_crt_verify_with_profile( mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const mbedtls_x509_crt_profile *profile, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy ); + +/** + * \brief Restartable version of \c mbedtls_crt_verify_with_profile() + * + * \note Performs the same job as \c mbedtls_crt_verify_with_profile() + * but can return early and restart according to the limit + * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param crt a certificate (chain) to be verified + * \param trust_ca the list of trusted CAs + * \param ca_crl the list of CRLs for trusted CAs + * \param profile security profile for verification + * \param cn expected Common Name (can be set to + * NULL if the CN must not be verified) + * \param flags result of the verification + * \param f_vrfy verification function + * \param p_vrfy verification parameter + * \param rs_ctx restart context (NULL to disable restart) + * + * \return See \c mbedtls_crt_verify_with_profile(), or + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + */ +int mbedtls_x509_crt_verify_restartable( mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const mbedtls_x509_crt_profile *profile, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy, + mbedtls_x509_crt_restart_ctx *rs_ctx ); + +#if defined(MBEDTLS_X509_CHECK_KEY_USAGE) +/** + * \brief Check usage of certificate against keyUsage extension. + * + * \param crt Leaf certificate used. + * \param usage Intended usage(s) (eg MBEDTLS_X509_KU_KEY_ENCIPHERMENT + * before using the certificate to perform an RSA key + * exchange). + * + * \note Except for decipherOnly and encipherOnly, a bit set in the + * usage argument means this bit MUST be set in the + * certificate. For decipherOnly and encipherOnly, it means + * that bit MAY be set. + * + * \return 0 is these uses of the certificate are allowed, + * MBEDTLS_ERR_X509_BAD_INPUT_DATA if the keyUsage extension + * is present but does not match the usage argument. + * + * \note You should only call this function on leaf certificates, on + * (intermediate) CAs the keyUsage extension is automatically + * checked by \c mbedtls_x509_crt_verify(). + */ +int mbedtls_x509_crt_check_key_usage( const mbedtls_x509_crt *crt, + unsigned int usage ); +#endif /* MBEDTLS_X509_CHECK_KEY_USAGE) */ + +#if defined(MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE) +/** + * \brief Check usage of certificate against extendedKeyUsage. + * + * \param crt Leaf certificate used. + * \param usage_oid Intended usage (eg MBEDTLS_OID_SERVER_AUTH or + * MBEDTLS_OID_CLIENT_AUTH). + * \param usage_len Length of usage_oid (eg given by MBEDTLS_OID_SIZE()). + * + * \return 0 if this use of the certificate is allowed, + * MBEDTLS_ERR_X509_BAD_INPUT_DATA if not. + * + * \note Usually only makes sense on leaf certificates. + */ +int mbedtls_x509_crt_check_extended_key_usage( const mbedtls_x509_crt *crt, + const char *usage_oid, + size_t usage_len ); +#endif /* MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE */ + +#if defined(MBEDTLS_X509_CRL_PARSE_C) +/** + * \brief Verify the certificate revocation status + * + * \param crt a certificate to be verified + * \param crl the CRL to verify against + * + * \return 1 if the certificate is revoked, 0 otherwise + * + */ +int mbedtls_x509_crt_is_revoked( const mbedtls_x509_crt *crt, const mbedtls_x509_crl *crl ); +#endif /* MBEDTLS_X509_CRL_PARSE_C */ + +/** + * \brief Initialize a certificate (chain) + * + * \param crt Certificate chain to initialize + */ +void mbedtls_x509_crt_init( mbedtls_x509_crt *crt ); + +/** + * \brief Unallocate all certificate data + * + * \param crt Certificate chain to free + */ +void mbedtls_x509_crt_free( mbedtls_x509_crt *crt ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Initialize a restart context + */ +void mbedtls_x509_crt_restart_init( mbedtls_x509_crt_restart_ctx *ctx ); + +/** + * \brief Free the components of a restart context + */ +void mbedtls_x509_crt_restart_free( mbedtls_x509_crt_restart_ctx *ctx ); +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +/* \} name */ +/* \} addtogroup x509_module */ + +#if defined(MBEDTLS_X509_CRT_WRITE_C) +/** + * \brief Initialize a CRT writing context + * + * \param ctx CRT context to initialize + */ +void mbedtls_x509write_crt_init( mbedtls_x509write_cert *ctx ); + +/** + * \brief Set the verion for a Certificate + * Default: MBEDTLS_X509_CRT_VERSION_3 + * + * \param ctx CRT context to use + * \param version version to set (MBEDTLS_X509_CRT_VERSION_1, MBEDTLS_X509_CRT_VERSION_2 or + * MBEDTLS_X509_CRT_VERSION_3) + */ +void mbedtls_x509write_crt_set_version( mbedtls_x509write_cert *ctx, int version ); + +/** + * \brief Set the serial number for a Certificate. + * + * \param ctx CRT context to use + * \param serial serial number to set + * + * \return 0 if successful + */ +int mbedtls_x509write_crt_set_serial( mbedtls_x509write_cert *ctx, const mbedtls_mpi *serial ); + +/** + * \brief Set the validity period for a Certificate + * Timestamps should be in string format for UTC timezone + * i.e. "YYYYMMDDhhmmss" + * e.g. "20131231235959" for December 31st 2013 + * at 23:59:59 + * + * \param ctx CRT context to use + * \param not_before not_before timestamp + * \param not_after not_after timestamp + * + * \return 0 if timestamp was parsed successfully, or + * a specific error code + */ +int mbedtls_x509write_crt_set_validity( mbedtls_x509write_cert *ctx, const char *not_before, + const char *not_after ); + +/** + * \brief Set the issuer name for a Certificate + * Issuer names should contain a comma-separated list + * of OID types and values: + * e.g. "C=UK,O=ARM,CN=mbed TLS CA" + * + * \param ctx CRT context to use + * \param issuer_name issuer name to set + * + * \return 0 if issuer name was parsed successfully, or + * a specific error code + */ +int mbedtls_x509write_crt_set_issuer_name( mbedtls_x509write_cert *ctx, + const char *issuer_name ); + +/** + * \brief Set the subject name for a Certificate + * Subject names should contain a comma-separated list + * of OID types and values: + * e.g. "C=UK,O=ARM,CN=mbed TLS Server 1" + * + * \param ctx CRT context to use + * \param subject_name subject name to set + * + * \return 0 if subject name was parsed successfully, or + * a specific error code + */ +int mbedtls_x509write_crt_set_subject_name( mbedtls_x509write_cert *ctx, + const char *subject_name ); + +/** + * \brief Set the subject public key for the certificate + * + * \param ctx CRT context to use + * \param key public key to include + */ +void mbedtls_x509write_crt_set_subject_key( mbedtls_x509write_cert *ctx, mbedtls_pk_context *key ); + +/** + * \brief Set the issuer key used for signing the certificate + * + * \param ctx CRT context to use + * \param key private key to sign with + */ +void mbedtls_x509write_crt_set_issuer_key( mbedtls_x509write_cert *ctx, mbedtls_pk_context *key ); + +/** + * \brief Set the MD algorithm to use for the signature + * (e.g. MBEDTLS_MD_SHA1) + * + * \param ctx CRT context to use + * \param md_alg MD algorithm to use + */ +void mbedtls_x509write_crt_set_md_alg( mbedtls_x509write_cert *ctx, mbedtls_md_type_t md_alg ); + +/** + * \brief Generic function to add to or replace an extension in the + * CRT + * + * \param ctx CRT context to use + * \param oid OID of the extension + * \param oid_len length of the OID + * \param critical if the extension is critical (per the RFC's definition) + * \param val value of the extension OCTET STRING + * \param val_len length of the value data + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_extension( mbedtls_x509write_cert *ctx, + const char *oid, size_t oid_len, + int critical, + const unsigned char *val, size_t val_len ); + +/** + * \brief Set the basicConstraints extension for a CRT + * + * \param ctx CRT context to use + * \param is_ca is this a CA certificate + * \param max_pathlen maximum length of certificate chains below this + * certificate (only for CA certificates, -1 is + * inlimited) + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_basic_constraints( mbedtls_x509write_cert *ctx, + int is_ca, int max_pathlen ); + +#if defined(MBEDTLS_SHA1_C) +/** + * \brief Set the subjectKeyIdentifier extension for a CRT + * Requires that mbedtls_x509write_crt_set_subject_key() has been + * called before + * + * \param ctx CRT context to use + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_subject_key_identifier( mbedtls_x509write_cert *ctx ); + +/** + * \brief Set the authorityKeyIdentifier extension for a CRT + * Requires that mbedtls_x509write_crt_set_issuer_key() has been + * called before + * + * \param ctx CRT context to use + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_authority_key_identifier( mbedtls_x509write_cert *ctx ); +#endif /* MBEDTLS_SHA1_C */ + +/** + * \brief Set the Key Usage Extension flags + * (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN) + * + * \param ctx CRT context to use + * \param key_usage key usage flags to set + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_key_usage( mbedtls_x509write_cert *ctx, + unsigned int key_usage ); + +/** + * \brief Set the Netscape Cert Type flags + * (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL) + * + * \param ctx CRT context to use + * \param ns_cert_type Netscape Cert Type flags to set + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_ns_cert_type( mbedtls_x509write_cert *ctx, + unsigned char ns_cert_type ); + +/** + * \brief Free the contents of a CRT write context + * + * \param ctx CRT context to free + */ +void mbedtls_x509write_crt_free( mbedtls_x509write_cert *ctx ); + +/** + * \brief Write a built up certificate to a X509 DER structure + * Note: data is written at the end of the buffer! Use the + * return value to determine where you should start + * using the buffer + * + * \param ctx certificate to write away + * \param buf buffer to write to + * \param size size of the buffer + * \param f_rng RNG function (for signature, see note) + * \param p_rng RNG parameter + * + * \return length of data written if successful, or a specific + * error code + * + * \note f_rng may be NULL if RSA is used for signature and the + * signature is made offline (otherwise f_rng is desirable + * for countermeasures against timing attacks). + * ECDSA signatures always require a non-NULL f_rng. + */ +int mbedtls_x509write_crt_der( mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +#if defined(MBEDTLS_PEM_WRITE_C) +/** + * \brief Write a built up certificate to a X509 PEM string + * + * \param ctx certificate to write away + * \param buf buffer to write to + * \param size size of the buffer + * \param f_rng RNG function (for signature, see note) + * \param p_rng RNG parameter + * + * \return 0 if successful, or a specific error code + * + * \note f_rng may be NULL if RSA is used for signature and the + * signature is made offline (otherwise f_rng is desirable + * for countermeasures against timing attacks). + * ECDSA signatures always require a non-NULL f_rng. + */ +int mbedtls_x509write_crt_pem( mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); +#endif /* MBEDTLS_PEM_WRITE_C */ +#endif /* MBEDTLS_X509_CRT_WRITE_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_x509_crt.h */ diff --git a/src/common/mbedtls/include/mbedtls/x509_csr.h b/src/common/mbedtls/include/mbedtls/x509_csr.h new file mode 100644 index 0000000000..a04d473b07 --- /dev/null +++ b/src/common/mbedtls/include/mbedtls/x509_csr.h @@ -0,0 +1,317 @@ +/** + * \file x509_csr.h + * + * \brief X.509 certificate signing request parsing and writing + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#ifndef MBEDTLS_X509_CSR_H +#define MBEDTLS_X509_CSR_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "x509.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup x509_module + * \{ */ + +/** + * \name Structures and functions for X.509 Certificate Signing Requests (CSR) + * \{ + */ + +/** + * Certificate Signing Request (CSR) structure. + */ +typedef struct mbedtls_x509_csr +{ + mbedtls_x509_buf raw; /**< The raw CSR data (DER). */ + mbedtls_x509_buf cri; /**< The raw CertificateRequestInfo body (DER). */ + + int version; /**< CSR version (1=v1). */ + + mbedtls_x509_buf subject_raw; /**< The raw subject data (DER). */ + mbedtls_x509_name subject; /**< The parsed subject data (named information object). */ + + mbedtls_pk_context pk; /**< Container for the public key context. */ + + mbedtls_x509_buf sig_oid; + mbedtls_x509_buf sig; + mbedtls_md_type_t sig_md; /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ + mbedtls_pk_type_t sig_pk; /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ + void *sig_opts; /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ +} +mbedtls_x509_csr; + +/** + * Container for writing a CSR + */ +typedef struct mbedtls_x509write_csr +{ + mbedtls_pk_context *key; + mbedtls_asn1_named_data *subject; + mbedtls_md_type_t md_alg; + mbedtls_asn1_named_data *extensions; +} +mbedtls_x509write_csr; + +#if defined(MBEDTLS_X509_CSR_PARSE_C) +/** + * \brief Load a Certificate Signing Request (CSR) in DER format + * + * \note CSR attributes (if any) are currently silently ignored. + * + * \param csr CSR context to fill + * \param buf buffer holding the CRL data + * \param buflen size of the buffer + * + * \return 0 if successful, or a specific X509 error code + */ +int mbedtls_x509_csr_parse_der( mbedtls_x509_csr *csr, + const unsigned char *buf, size_t buflen ); + +/** + * \brief Load a Certificate Signing Request (CSR), DER or PEM format + * + * \note See notes for \c mbedtls_x509_csr_parse_der() + * + * \param csr CSR context to fill + * \param buf buffer holding the CRL data + * \param buflen size of the buffer + * (including the terminating null byte for PEM data) + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_csr_parse( mbedtls_x509_csr *csr, const unsigned char *buf, size_t buflen ); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Load a Certificate Signing Request (CSR) + * + * \note See notes for \c mbedtls_x509_csr_parse() + * + * \param csr CSR context to fill + * \param path filename to read the CSR from + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_csr_parse_file( mbedtls_x509_csr *csr, const char *path ); +#endif /* MBEDTLS_FS_IO */ + +/** + * \brief Returns an informational string about the + * CSR. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param prefix A line prefix + * \param csr The X509 CSR to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_csr_info( char *buf, size_t size, const char *prefix, + const mbedtls_x509_csr *csr ); + +/** + * \brief Initialize a CSR + * + * \param csr CSR to initialize + */ +void mbedtls_x509_csr_init( mbedtls_x509_csr *csr ); + +/** + * \brief Unallocate all CSR data + * + * \param csr CSR to free + */ +void mbedtls_x509_csr_free( mbedtls_x509_csr *csr ); +#endif /* MBEDTLS_X509_CSR_PARSE_C */ + +/* \} name */ +/* \} addtogroup x509_module */ + +#if defined(MBEDTLS_X509_CSR_WRITE_C) +/** + * \brief Initialize a CSR context + * + * \param ctx CSR context to initialize + */ +void mbedtls_x509write_csr_init( mbedtls_x509write_csr *ctx ); + +/** + * \brief Set the subject name for a CSR + * Subject names should contain a comma-separated list + * of OID types and values: + * e.g. "C=UK,O=ARM,CN=mbed TLS Server 1" + * + * \param ctx CSR context to use + * \param subject_name subject name to set + * + * \return 0 if subject name was parsed successfully, or + * a specific error code + */ +int mbedtls_x509write_csr_set_subject_name( mbedtls_x509write_csr *ctx, + const char *subject_name ); + +/** + * \brief Set the key for a CSR (public key will be included, + * private key used to sign the CSR when writing it) + * + * \param ctx CSR context to use + * \param key Asymetric key to include + */ +void mbedtls_x509write_csr_set_key( mbedtls_x509write_csr *ctx, mbedtls_pk_context *key ); + +/** + * \brief Set the MD algorithm to use for the signature + * (e.g. MBEDTLS_MD_SHA1) + * + * \param ctx CSR context to use + * \param md_alg MD algorithm to use + */ +void mbedtls_x509write_csr_set_md_alg( mbedtls_x509write_csr *ctx, mbedtls_md_type_t md_alg ); + +/** + * \brief Set the Key Usage Extension flags + * (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN) + * + * \param ctx CSR context to use + * \param key_usage key usage flags to set + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + * + * \note The decipherOnly flag from the Key Usage + * extension is represented by bit 8 (i.e. + * 0x8000), which cannot typically be represented + * in an unsigned char. Therefore, the flag + * decipherOnly (i.e. + * #MBEDTLS_X509_KU_DECIPHER_ONLY) cannot be set using this + * function. + */ +int mbedtls_x509write_csr_set_key_usage( mbedtls_x509write_csr *ctx, unsigned char key_usage ); + +/** + * \brief Set the Netscape Cert Type flags + * (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL) + * + * \param ctx CSR context to use + * \param ns_cert_type Netscape Cert Type flags to set + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_csr_set_ns_cert_type( mbedtls_x509write_csr *ctx, + unsigned char ns_cert_type ); + +/** + * \brief Generic function to add to or replace an extension in the + * CSR + * + * \param ctx CSR context to use + * \param oid OID of the extension + * \param oid_len length of the OID + * \param val value of the extension OCTET STRING + * \param val_len length of the value data + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_csr_set_extension( mbedtls_x509write_csr *ctx, + const char *oid, size_t oid_len, + const unsigned char *val, size_t val_len ); + +/** + * \brief Free the contents of a CSR context + * + * \param ctx CSR context to free + */ +void mbedtls_x509write_csr_free( mbedtls_x509write_csr *ctx ); + +/** + * \brief Write a CSR (Certificate Signing Request) to a + * DER structure + * Note: data is written at the end of the buffer! Use the + * return value to determine where you should start + * using the buffer + * + * \param ctx CSR to write away + * \param buf buffer to write to + * \param size size of the buffer + * \param f_rng RNG function (for signature, see note) + * \param p_rng RNG parameter + * + * \return length of data written if successful, or a specific + * error code + * + * \note f_rng may be NULL if RSA is used for signature and the + * signature is made offline (otherwise f_rng is desirable + * for countermeasures against timing attacks). + * ECDSA signatures always require a non-NULL f_rng. + */ +int mbedtls_x509write_csr_der( mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +#if defined(MBEDTLS_PEM_WRITE_C) +/** + * \brief Write a CSR (Certificate Signing Request) to a + * PEM string + * + * \param ctx CSR to write away + * \param buf buffer to write to + * \param size size of the buffer + * \param f_rng RNG function (for signature, see note) + * \param p_rng RNG parameter + * + * \return 0 if successful, or a specific error code + * + * \note f_rng may be NULL if RSA is used for signature and the + * signature is made offline (otherwise f_rng is desirable + * for countermeasures against timing attacks). + * ECDSA signatures always require a non-NULL f_rng. + */ +int mbedtls_x509write_csr_pem( mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); +#endif /* MBEDTLS_PEM_WRITE_C */ +#endif /* MBEDTLS_X509_CSR_WRITE_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_x509_csr.h */ diff --git a/src/common/mbedtls/library/mbedtls_aes.c b/src/common/mbedtls/library/mbedtls_aes.c new file mode 100644 index 0000000000..036c4b6a97 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_aes.c @@ -0,0 +1,2231 @@ +/* + * FIPS-197 compliant AES implementation + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +/* + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * https://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * https://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_AES_C) + +#ifndef NVRM +#include +#endif + +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#if defined(MBEDTLS_PADLOCK_C) +#include "mbedtls/padlock.h" +#endif +#if defined(MBEDTLS_AESNI_C) +#include "mbedtls/aesni.h" +#endif + +#if defined(MBEDTLS_SELF_TEST) +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST */ + +#if !defined(MBEDTLS_AES_ALT) + +/* Parameter validation macros based on platform_util.h */ +#define AES_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_AES_BAD_INPUT_DATA ) +#define AES_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +/* + * 32-bit integer manipulation macros (little endian) + */ +#ifndef GET_UINT32_LE +#define GET_UINT32_LE(n,b,i) \ +{ \ + (n) = ( (uint32_t) (b)[(i) ] ) \ + | ( (uint32_t) (b)[(i) + 1] << 8 ) \ + | ( (uint32_t) (b)[(i) + 2] << 16 ) \ + | ( (uint32_t) (b)[(i) + 3] << 24 ); \ +} +#endif + +#ifndef PUT_UINT32_LE +#define PUT_UINT32_LE(n,b,i) \ +{ \ + (b)[(i) ] = (unsigned char) ( ( (n) ) & 0xFF ); \ + (b)[(i) + 1] = (unsigned char) ( ( (n) >> 8 ) & 0xFF ); \ + (b)[(i) + 2] = (unsigned char) ( ( (n) >> 16 ) & 0xFF ); \ + (b)[(i) + 3] = (unsigned char) ( ( (n) >> 24 ) & 0xFF ); \ +} +#endif + +#if defined(MBEDTLS_PADLOCK_C) && \ + ( defined(MBEDTLS_HAVE_X86) || defined(MBEDTLS_PADLOCK_ALIGN16) ) +static int aes_padlock_ace = -1; +#endif + +#if defined(MBEDTLS_AES_ROM_TABLES) +/* + * Forward S-box + */ +static const unsigned char FSb[256] = +{ + 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, + 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, + 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, + 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, + 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, + 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15, + 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, + 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, + 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, + 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, + 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, + 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, + 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, + 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8, + 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, + 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, + 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, + 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, + 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, + 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, + 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, + 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, + 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, + 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, + 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, + 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, + 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, + 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, + 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, + 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, + 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, + 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 +}; + +/* + * Forward tables + */ +#define FT \ +\ + V(A5,63,63,C6), V(84,7C,7C,F8), V(99,77,77,EE), V(8D,7B,7B,F6), \ + V(0D,F2,F2,FF), V(BD,6B,6B,D6), V(B1,6F,6F,DE), V(54,C5,C5,91), \ + V(50,30,30,60), V(03,01,01,02), V(A9,67,67,CE), V(7D,2B,2B,56), \ + V(19,FE,FE,E7), V(62,D7,D7,B5), V(E6,AB,AB,4D), V(9A,76,76,EC), \ + V(45,CA,CA,8F), V(9D,82,82,1F), V(40,C9,C9,89), V(87,7D,7D,FA), \ + V(15,FA,FA,EF), V(EB,59,59,B2), V(C9,47,47,8E), V(0B,F0,F0,FB), \ + V(EC,AD,AD,41), V(67,D4,D4,B3), V(FD,A2,A2,5F), V(EA,AF,AF,45), \ + V(BF,9C,9C,23), V(F7,A4,A4,53), V(96,72,72,E4), V(5B,C0,C0,9B), \ + V(C2,B7,B7,75), V(1C,FD,FD,E1), V(AE,93,93,3D), V(6A,26,26,4C), \ + V(5A,36,36,6C), V(41,3F,3F,7E), V(02,F7,F7,F5), V(4F,CC,CC,83), \ + V(5C,34,34,68), V(F4,A5,A5,51), V(34,E5,E5,D1), V(08,F1,F1,F9), \ + V(93,71,71,E2), V(73,D8,D8,AB), V(53,31,31,62), V(3F,15,15,2A), \ + V(0C,04,04,08), V(52,C7,C7,95), V(65,23,23,46), V(5E,C3,C3,9D), \ + V(28,18,18,30), V(A1,96,96,37), V(0F,05,05,0A), V(B5,9A,9A,2F), \ + V(09,07,07,0E), V(36,12,12,24), V(9B,80,80,1B), V(3D,E2,E2,DF), \ + V(26,EB,EB,CD), V(69,27,27,4E), V(CD,B2,B2,7F), V(9F,75,75,EA), \ + V(1B,09,09,12), V(9E,83,83,1D), V(74,2C,2C,58), V(2E,1A,1A,34), \ + V(2D,1B,1B,36), V(B2,6E,6E,DC), V(EE,5A,5A,B4), V(FB,A0,A0,5B), \ + V(F6,52,52,A4), V(4D,3B,3B,76), V(61,D6,D6,B7), V(CE,B3,B3,7D), \ + V(7B,29,29,52), V(3E,E3,E3,DD), V(71,2F,2F,5E), V(97,84,84,13), \ + V(F5,53,53,A6), V(68,D1,D1,B9), V(00,00,00,00), V(2C,ED,ED,C1), \ + V(60,20,20,40), V(1F,FC,FC,E3), V(C8,B1,B1,79), V(ED,5B,5B,B6), \ + V(BE,6A,6A,D4), V(46,CB,CB,8D), V(D9,BE,BE,67), V(4B,39,39,72), \ + V(DE,4A,4A,94), V(D4,4C,4C,98), V(E8,58,58,B0), V(4A,CF,CF,85), \ + V(6B,D0,D0,BB), V(2A,EF,EF,C5), V(E5,AA,AA,4F), V(16,FB,FB,ED), \ + V(C5,43,43,86), V(D7,4D,4D,9A), V(55,33,33,66), V(94,85,85,11), \ + V(CF,45,45,8A), V(10,F9,F9,E9), V(06,02,02,04), V(81,7F,7F,FE), \ + V(F0,50,50,A0), V(44,3C,3C,78), V(BA,9F,9F,25), V(E3,A8,A8,4B), \ + V(F3,51,51,A2), V(FE,A3,A3,5D), V(C0,40,40,80), V(8A,8F,8F,05), \ + V(AD,92,92,3F), V(BC,9D,9D,21), V(48,38,38,70), V(04,F5,F5,F1), \ + V(DF,BC,BC,63), V(C1,B6,B6,77), V(75,DA,DA,AF), V(63,21,21,42), \ + V(30,10,10,20), V(1A,FF,FF,E5), V(0E,F3,F3,FD), V(6D,D2,D2,BF), \ + V(4C,CD,CD,81), V(14,0C,0C,18), V(35,13,13,26), V(2F,EC,EC,C3), \ + V(E1,5F,5F,BE), V(A2,97,97,35), V(CC,44,44,88), V(39,17,17,2E), \ + V(57,C4,C4,93), V(F2,A7,A7,55), V(82,7E,7E,FC), V(47,3D,3D,7A), \ + V(AC,64,64,C8), V(E7,5D,5D,BA), V(2B,19,19,32), V(95,73,73,E6), \ + V(A0,60,60,C0), V(98,81,81,19), V(D1,4F,4F,9E), V(7F,DC,DC,A3), \ + V(66,22,22,44), V(7E,2A,2A,54), V(AB,90,90,3B), V(83,88,88,0B), \ + V(CA,46,46,8C), V(29,EE,EE,C7), V(D3,B8,B8,6B), V(3C,14,14,28), \ + V(79,DE,DE,A7), V(E2,5E,5E,BC), V(1D,0B,0B,16), V(76,DB,DB,AD), \ + V(3B,E0,E0,DB), V(56,32,32,64), V(4E,3A,3A,74), V(1E,0A,0A,14), \ + V(DB,49,49,92), V(0A,06,06,0C), V(6C,24,24,48), V(E4,5C,5C,B8), \ + V(5D,C2,C2,9F), V(6E,D3,D3,BD), V(EF,AC,AC,43), V(A6,62,62,C4), \ + V(A8,91,91,39), V(A4,95,95,31), V(37,E4,E4,D3), V(8B,79,79,F2), \ + V(32,E7,E7,D5), V(43,C8,C8,8B), V(59,37,37,6E), V(B7,6D,6D,DA), \ + V(8C,8D,8D,01), V(64,D5,D5,B1), V(D2,4E,4E,9C), V(E0,A9,A9,49), \ + V(B4,6C,6C,D8), V(FA,56,56,AC), V(07,F4,F4,F3), V(25,EA,EA,CF), \ + V(AF,65,65,CA), V(8E,7A,7A,F4), V(E9,AE,AE,47), V(18,08,08,10), \ + V(D5,BA,BA,6F), V(88,78,78,F0), V(6F,25,25,4A), V(72,2E,2E,5C), \ + V(24,1C,1C,38), V(F1,A6,A6,57), V(C7,B4,B4,73), V(51,C6,C6,97), \ + V(23,E8,E8,CB), V(7C,DD,DD,A1), V(9C,74,74,E8), V(21,1F,1F,3E), \ + V(DD,4B,4B,96), V(DC,BD,BD,61), V(86,8B,8B,0D), V(85,8A,8A,0F), \ + V(90,70,70,E0), V(42,3E,3E,7C), V(C4,B5,B5,71), V(AA,66,66,CC), \ + V(D8,48,48,90), V(05,03,03,06), V(01,F6,F6,F7), V(12,0E,0E,1C), \ + V(A3,61,61,C2), V(5F,35,35,6A), V(F9,57,57,AE), V(D0,B9,B9,69), \ + V(91,86,86,17), V(58,C1,C1,99), V(27,1D,1D,3A), V(B9,9E,9E,27), \ + V(38,E1,E1,D9), V(13,F8,F8,EB), V(B3,98,98,2B), V(33,11,11,22), \ + V(BB,69,69,D2), V(70,D9,D9,A9), V(89,8E,8E,07), V(A7,94,94,33), \ + V(B6,9B,9B,2D), V(22,1E,1E,3C), V(92,87,87,15), V(20,E9,E9,C9), \ + V(49,CE,CE,87), V(FF,55,55,AA), V(78,28,28,50), V(7A,DF,DF,A5), \ + V(8F,8C,8C,03), V(F8,A1,A1,59), V(80,89,89,09), V(17,0D,0D,1A), \ + V(DA,BF,BF,65), V(31,E6,E6,D7), V(C6,42,42,84), V(B8,68,68,D0), \ + V(C3,41,41,82), V(B0,99,99,29), V(77,2D,2D,5A), V(11,0F,0F,1E), \ + V(CB,B0,B0,7B), V(FC,54,54,A8), V(D6,BB,BB,6D), V(3A,16,16,2C) + +#define V(a,b,c,d) 0x##a##b##c##d +static const uint32_t FT0[256] = { FT }; +#undef V + +#if !defined(MBEDTLS_AES_FEWER_TABLES) + +#define V(a,b,c,d) 0x##b##c##d##a +static const uint32_t FT1[256] = { FT }; +#undef V + +#define V(a,b,c,d) 0x##c##d##a##b +static const uint32_t FT2[256] = { FT }; +#undef V + +#define V(a,b,c,d) 0x##d##a##b##c +static const uint32_t FT3[256] = { FT }; +#undef V + +#endif /* !MBEDTLS_AES_FEWER_TABLES */ + +#undef FT + +/* + * Reverse S-box + */ +static const unsigned char RSb[256] = +{ + 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, + 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, + 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, + 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, + 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, + 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E, + 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, + 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25, + 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16, + 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, + 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA, + 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84, + 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, + 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06, + 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02, + 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, + 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA, + 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73, + 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, + 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E, + 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89, + 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, + 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20, + 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4, + 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, + 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F, + 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, + 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, + 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, + 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, + 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D +}; + +/* + * Reverse tables + */ +#define RT \ +\ + V(50,A7,F4,51), V(53,65,41,7E), V(C3,A4,17,1A), V(96,5E,27,3A), \ + V(CB,6B,AB,3B), V(F1,45,9D,1F), V(AB,58,FA,AC), V(93,03,E3,4B), \ + V(55,FA,30,20), V(F6,6D,76,AD), V(91,76,CC,88), V(25,4C,02,F5), \ + V(FC,D7,E5,4F), V(D7,CB,2A,C5), V(80,44,35,26), V(8F,A3,62,B5), \ + V(49,5A,B1,DE), V(67,1B,BA,25), V(98,0E,EA,45), V(E1,C0,FE,5D), \ + V(02,75,2F,C3), V(12,F0,4C,81), V(A3,97,46,8D), V(C6,F9,D3,6B), \ + V(E7,5F,8F,03), V(95,9C,92,15), V(EB,7A,6D,BF), V(DA,59,52,95), \ + V(2D,83,BE,D4), V(D3,21,74,58), V(29,69,E0,49), V(44,C8,C9,8E), \ + V(6A,89,C2,75), V(78,79,8E,F4), V(6B,3E,58,99), V(DD,71,B9,27), \ + V(B6,4F,E1,BE), V(17,AD,88,F0), V(66,AC,20,C9), V(B4,3A,CE,7D), \ + V(18,4A,DF,63), V(82,31,1A,E5), V(60,33,51,97), V(45,7F,53,62), \ + V(E0,77,64,B1), V(84,AE,6B,BB), V(1C,A0,81,FE), V(94,2B,08,F9), \ + V(58,68,48,70), V(19,FD,45,8F), V(87,6C,DE,94), V(B7,F8,7B,52), \ + V(23,D3,73,AB), V(E2,02,4B,72), V(57,8F,1F,E3), V(2A,AB,55,66), \ + V(07,28,EB,B2), V(03,C2,B5,2F), V(9A,7B,C5,86), V(A5,08,37,D3), \ + V(F2,87,28,30), V(B2,A5,BF,23), V(BA,6A,03,02), V(5C,82,16,ED), \ + V(2B,1C,CF,8A), V(92,B4,79,A7), V(F0,F2,07,F3), V(A1,E2,69,4E), \ + V(CD,F4,DA,65), V(D5,BE,05,06), V(1F,62,34,D1), V(8A,FE,A6,C4), \ + V(9D,53,2E,34), V(A0,55,F3,A2), V(32,E1,8A,05), V(75,EB,F6,A4), \ + V(39,EC,83,0B), V(AA,EF,60,40), V(06,9F,71,5E), V(51,10,6E,BD), \ + V(F9,8A,21,3E), V(3D,06,DD,96), V(AE,05,3E,DD), V(46,BD,E6,4D), \ + V(B5,8D,54,91), V(05,5D,C4,71), V(6F,D4,06,04), V(FF,15,50,60), \ + V(24,FB,98,19), V(97,E9,BD,D6), V(CC,43,40,89), V(77,9E,D9,67), \ + V(BD,42,E8,B0), V(88,8B,89,07), V(38,5B,19,E7), V(DB,EE,C8,79), \ + V(47,0A,7C,A1), V(E9,0F,42,7C), V(C9,1E,84,F8), V(00,00,00,00), \ + V(83,86,80,09), V(48,ED,2B,32), V(AC,70,11,1E), V(4E,72,5A,6C), \ + V(FB,FF,0E,FD), V(56,38,85,0F), V(1E,D5,AE,3D), V(27,39,2D,36), \ + V(64,D9,0F,0A), V(21,A6,5C,68), V(D1,54,5B,9B), V(3A,2E,36,24), \ + V(B1,67,0A,0C), V(0F,E7,57,93), V(D2,96,EE,B4), V(9E,91,9B,1B), \ + V(4F,C5,C0,80), V(A2,20,DC,61), V(69,4B,77,5A), V(16,1A,12,1C), \ + V(0A,BA,93,E2), V(E5,2A,A0,C0), V(43,E0,22,3C), V(1D,17,1B,12), \ + V(0B,0D,09,0E), V(AD,C7,8B,F2), V(B9,A8,B6,2D), V(C8,A9,1E,14), \ + V(85,19,F1,57), V(4C,07,75,AF), V(BB,DD,99,EE), V(FD,60,7F,A3), \ + V(9F,26,01,F7), V(BC,F5,72,5C), V(C5,3B,66,44), V(34,7E,FB,5B), \ + V(76,29,43,8B), V(DC,C6,23,CB), V(68,FC,ED,B6), V(63,F1,E4,B8), \ + V(CA,DC,31,D7), V(10,85,63,42), V(40,22,97,13), V(20,11,C6,84), \ + V(7D,24,4A,85), V(F8,3D,BB,D2), V(11,32,F9,AE), V(6D,A1,29,C7), \ + V(4B,2F,9E,1D), V(F3,30,B2,DC), V(EC,52,86,0D), V(D0,E3,C1,77), \ + V(6C,16,B3,2B), V(99,B9,70,A9), V(FA,48,94,11), V(22,64,E9,47), \ + V(C4,8C,FC,A8), V(1A,3F,F0,A0), V(D8,2C,7D,56), V(EF,90,33,22), \ + V(C7,4E,49,87), V(C1,D1,38,D9), V(FE,A2,CA,8C), V(36,0B,D4,98), \ + V(CF,81,F5,A6), V(28,DE,7A,A5), V(26,8E,B7,DA), V(A4,BF,AD,3F), \ + V(E4,9D,3A,2C), V(0D,92,78,50), V(9B,CC,5F,6A), V(62,46,7E,54), \ + V(C2,13,8D,F6), V(E8,B8,D8,90), V(5E,F7,39,2E), V(F5,AF,C3,82), \ + V(BE,80,5D,9F), V(7C,93,D0,69), V(A9,2D,D5,6F), V(B3,12,25,CF), \ + V(3B,99,AC,C8), V(A7,7D,18,10), V(6E,63,9C,E8), V(7B,BB,3B,DB), \ + V(09,78,26,CD), V(F4,18,59,6E), V(01,B7,9A,EC), V(A8,9A,4F,83), \ + V(65,6E,95,E6), V(7E,E6,FF,AA), V(08,CF,BC,21), V(E6,E8,15,EF), \ + V(D9,9B,E7,BA), V(CE,36,6F,4A), V(D4,09,9F,EA), V(D6,7C,B0,29), \ + V(AF,B2,A4,31), V(31,23,3F,2A), V(30,94,A5,C6), V(C0,66,A2,35), \ + V(37,BC,4E,74), V(A6,CA,82,FC), V(B0,D0,90,E0), V(15,D8,A7,33), \ + V(4A,98,04,F1), V(F7,DA,EC,41), V(0E,50,CD,7F), V(2F,F6,91,17), \ + V(8D,D6,4D,76), V(4D,B0,EF,43), V(54,4D,AA,CC), V(DF,04,96,E4), \ + V(E3,B5,D1,9E), V(1B,88,6A,4C), V(B8,1F,2C,C1), V(7F,51,65,46), \ + V(04,EA,5E,9D), V(5D,35,8C,01), V(73,74,87,FA), V(2E,41,0B,FB), \ + V(5A,1D,67,B3), V(52,D2,DB,92), V(33,56,10,E9), V(13,47,D6,6D), \ + V(8C,61,D7,9A), V(7A,0C,A1,37), V(8E,14,F8,59), V(89,3C,13,EB), \ + V(EE,27,A9,CE), V(35,C9,61,B7), V(ED,E5,1C,E1), V(3C,B1,47,7A), \ + V(59,DF,D2,9C), V(3F,73,F2,55), V(79,CE,14,18), V(BF,37,C7,73), \ + V(EA,CD,F7,53), V(5B,AA,FD,5F), V(14,6F,3D,DF), V(86,DB,44,78), \ + V(81,F3,AF,CA), V(3E,C4,68,B9), V(2C,34,24,38), V(5F,40,A3,C2), \ + V(72,C3,1D,16), V(0C,25,E2,BC), V(8B,49,3C,28), V(41,95,0D,FF), \ + V(71,01,A8,39), V(DE,B3,0C,08), V(9C,E4,B4,D8), V(90,C1,56,64), \ + V(61,84,CB,7B), V(70,B6,32,D5), V(74,5C,6C,48), V(42,57,B8,D0) + +#define V(a,b,c,d) 0x##a##b##c##d +static const uint32_t RT0[256] = { RT }; +#undef V + +#if !defined(MBEDTLS_AES_FEWER_TABLES) + +#define V(a,b,c,d) 0x##b##c##d##a +static const uint32_t RT1[256] = { RT }; +#undef V + +#define V(a,b,c,d) 0x##c##d##a##b +static const uint32_t RT2[256] = { RT }; +#undef V + +#define V(a,b,c,d) 0x##d##a##b##c +static const uint32_t RT3[256] = { RT }; +#undef V + +#endif /* !MBEDTLS_AES_FEWER_TABLES */ + +#undef RT + +/* + * Round constants + */ +static const uint32_t RCON[10] = +{ + 0x00000001, 0x00000002, 0x00000004, 0x00000008, + 0x00000010, 0x00000020, 0x00000040, 0x00000080, + 0x0000001B, 0x00000036 +}; + +#else /* MBEDTLS_AES_ROM_TABLES */ + +/* + * Forward S-box & tables + */ +static unsigned char FSb[256]; +static uint32_t FT0[256]; +#if !defined(MBEDTLS_AES_FEWER_TABLES) +static uint32_t FT1[256]; +static uint32_t FT2[256]; +static uint32_t FT3[256]; +#endif /* !MBEDTLS_AES_FEWER_TABLES */ + +/* + * Reverse S-box & tables + */ +static unsigned char RSb[256]; +static uint32_t RT0[256]; +#if !defined(MBEDTLS_AES_FEWER_TABLES) +static uint32_t RT1[256]; +static uint32_t RT2[256]; +static uint32_t RT3[256]; +#endif /* !MBEDTLS_AES_FEWER_TABLES */ + +/* + * Round constants + */ +static uint32_t RCON[10]; + +/* + * Tables generation code + */ +#define ROTL8(x) ( ( (x) << 8 ) & 0xFFFFFFFF ) | ( (x) >> 24 ) +#define XTIME(x) ( ( (x) << 1 ) ^ ( ( (x) & 0x80 ) ? 0x1B : 0x00 ) ) +#define MUL(x,y) ( ( (x) && (y) ) ? pow[(log[(x)]+log[(y)]) % 255] : 0 ) + +static int aes_init_done = 0; + +static void aes_gen_tables( void ) +{ + int i, x, y, z; + int pow[256]; + int log[256]; + + /* + * compute pow and log tables over GF(2^8) + */ + for( i = 0, x = 1; i < 256; i++ ) + { + pow[i] = x; + log[x] = i; + x = ( x ^ XTIME( x ) ) & 0xFF; + } + + /* + * calculate the round constants + */ + for( i = 0, x = 1; i < 10; i++ ) + { + RCON[i] = (uint32_t) x; + x = XTIME( x ) & 0xFF; + } + + /* + * generate the forward and reverse S-boxes + */ + FSb[0x00] = 0x63; + RSb[0x63] = 0x00; + + for( i = 1; i < 256; i++ ) + { + x = pow[255 - log[i]]; + + y = x; y = ( ( y << 1 ) | ( y >> 7 ) ) & 0xFF; + x ^= y; y = ( ( y << 1 ) | ( y >> 7 ) ) & 0xFF; + x ^= y; y = ( ( y << 1 ) | ( y >> 7 ) ) & 0xFF; + x ^= y; y = ( ( y << 1 ) | ( y >> 7 ) ) & 0xFF; + x ^= y ^ 0x63; + + FSb[i] = (unsigned char) x; + RSb[x] = (unsigned char) i; + } + + /* + * generate the forward and reverse tables + */ + for( i = 0; i < 256; i++ ) + { + x = FSb[i]; + y = XTIME( x ) & 0xFF; + z = ( y ^ x ) & 0xFF; + + FT0[i] = ( (uint32_t) y ) ^ + ( (uint32_t) x << 8 ) ^ + ( (uint32_t) x << 16 ) ^ + ( (uint32_t) z << 24 ); + +#if !defined(MBEDTLS_AES_FEWER_TABLES) + FT1[i] = ROTL8( FT0[i] ); + FT2[i] = ROTL8( FT1[i] ); + FT3[i] = ROTL8( FT2[i] ); +#endif /* !MBEDTLS_AES_FEWER_TABLES */ + + x = RSb[i]; + + RT0[i] = ( (uint32_t) MUL( 0x0E, x ) ) ^ + ( (uint32_t) MUL( 0x09, x ) << 8 ) ^ + ( (uint32_t) MUL( 0x0D, x ) << 16 ) ^ + ( (uint32_t) MUL( 0x0B, x ) << 24 ); + +#if !defined(MBEDTLS_AES_FEWER_TABLES) + RT1[i] = ROTL8( RT0[i] ); + RT2[i] = ROTL8( RT1[i] ); + RT3[i] = ROTL8( RT2[i] ); +#endif /* !MBEDTLS_AES_FEWER_TABLES */ + } +} + +#undef ROTL8 + +#endif /* MBEDTLS_AES_ROM_TABLES */ + +#if defined(MBEDTLS_AES_FEWER_TABLES) + +#define ROTL8(x) ( (uint32_t)( ( x ) << 8 ) + (uint32_t)( ( x ) >> 24 ) ) +#define ROTL16(x) ( (uint32_t)( ( x ) << 16 ) + (uint32_t)( ( x ) >> 16 ) ) +#define ROTL24(x) ( (uint32_t)( ( x ) << 24 ) + (uint32_t)( ( x ) >> 8 ) ) + +#define AES_RT0(idx) RT0[idx] +#define AES_RT1(idx) ROTL8( RT0[idx] ) +#define AES_RT2(idx) ROTL16( RT0[idx] ) +#define AES_RT3(idx) ROTL24( RT0[idx] ) + +#define AES_FT0(idx) FT0[idx] +#define AES_FT1(idx) ROTL8( FT0[idx] ) +#define AES_FT2(idx) ROTL16( FT0[idx] ) +#define AES_FT3(idx) ROTL24( FT0[idx] ) + +#else /* MBEDTLS_AES_FEWER_TABLES */ + +#define AES_RT0(idx) RT0[idx] +#define AES_RT1(idx) RT1[idx] +#define AES_RT2(idx) RT2[idx] +#define AES_RT3(idx) RT3[idx] + +#define AES_FT0(idx) FT0[idx] +#define AES_FT1(idx) FT1[idx] +#define AES_FT2(idx) FT2[idx] +#define AES_FT3(idx) FT3[idx] + +#endif /* MBEDTLS_AES_FEWER_TABLES */ + +void mbedtls_aes_init( mbedtls_aes_context *ctx ) +{ + AES_VALIDATE( ctx != NULL ); + + memset( ctx, 0, sizeof( mbedtls_aes_context ) ); +} + +void mbedtls_aes_free( mbedtls_aes_context *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_aes_context ) ); +} + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx ) +{ + AES_VALIDATE( ctx != NULL ); + + mbedtls_aes_init( &ctx->crypt ); + mbedtls_aes_init( &ctx->tweak ); +} + +void mbedtls_aes_xts_free( mbedtls_aes_xts_context *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_aes_free( &ctx->crypt ); + mbedtls_aes_free( &ctx->tweak ); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/* + * AES key schedule (encryption) + */ +#if !defined(MBEDTLS_AES_SETKEY_ENC_ALT) +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + unsigned int i; + uint32_t *RK; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + + switch( keybits ) + { + case 128: ctx->nr = 10; break; + case 192: ctx->nr = 12; break; + case 256: ctx->nr = 14; break; + default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + +#if !defined(MBEDTLS_AES_ROM_TABLES) + if( aes_init_done == 0 ) + { + aes_gen_tables(); + aes_init_done = 1; + } +#endif + +#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_PADLOCK_ALIGN16) + if( aes_padlock_ace == -1 ) + aes_padlock_ace = mbedtls_padlock_has_support( MBEDTLS_PADLOCK_ACE ); + + if( aes_padlock_ace ) + ctx->rk = RK = MBEDTLS_PADLOCK_ALIGN16( ctx->buf ); + else +#endif + ctx->rk = RK = ctx->buf; + +#if defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_HAVE_X86_64) + if( mbedtls_aesni_has_support( MBEDTLS_AESNI_AES ) ) + return( mbedtls_aesni_setkey_enc( (unsigned char *) ctx->rk, key, keybits ) ); +#endif + + for( i = 0; i < ( keybits >> 5 ); i++ ) + { + GET_UINT32_LE( RK[i], key, i << 2 ); + } + + switch( ctx->nr ) + { + case 10: + + for( i = 0; i < 10; i++, RK += 4 ) + { + RK[4] = RK[0] ^ RCON[i] ^ + ( (uint32_t) FSb[ ( RK[3] >> 8 ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( RK[3] >> 16 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( RK[3] >> 24 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( RK[3] ) & 0xFF ] << 24 ); + + RK[5] = RK[1] ^ RK[4]; + RK[6] = RK[2] ^ RK[5]; + RK[7] = RK[3] ^ RK[6]; + } + break; + + case 12: + + for( i = 0; i < 8; i++, RK += 6 ) + { + RK[6] = RK[0] ^ RCON[i] ^ + ( (uint32_t) FSb[ ( RK[5] >> 8 ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( RK[5] >> 16 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( RK[5] >> 24 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( RK[5] ) & 0xFF ] << 24 ); + + RK[7] = RK[1] ^ RK[6]; + RK[8] = RK[2] ^ RK[7]; + RK[9] = RK[3] ^ RK[8]; + RK[10] = RK[4] ^ RK[9]; + RK[11] = RK[5] ^ RK[10]; + } + break; + + case 14: + + for( i = 0; i < 7; i++, RK += 8 ) + { + RK[8] = RK[0] ^ RCON[i] ^ + ( (uint32_t) FSb[ ( RK[7] >> 8 ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( RK[7] >> 16 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( RK[7] >> 24 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( RK[7] ) & 0xFF ] << 24 ); + + RK[9] = RK[1] ^ RK[8]; + RK[10] = RK[2] ^ RK[9]; + RK[11] = RK[3] ^ RK[10]; + + RK[12] = RK[4] ^ + ( (uint32_t) FSb[ ( RK[11] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( RK[11] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( RK[11] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( RK[11] >> 24 ) & 0xFF ] << 24 ); + + RK[13] = RK[5] ^ RK[12]; + RK[14] = RK[6] ^ RK[13]; + RK[15] = RK[7] ^ RK[14]; + } + break; + } + + return( 0 ); +} +#endif /* !MBEDTLS_AES_SETKEY_ENC_ALT */ + +/* + * AES key schedule (decryption) + */ +#if !defined(MBEDTLS_AES_SETKEY_DEC_ALT) +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + int i, j, ret; + mbedtls_aes_context cty; + uint32_t *RK; + uint32_t *SK; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + + mbedtls_aes_init( &cty ); + +#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_PADLOCK_ALIGN16) + if( aes_padlock_ace == -1 ) + aes_padlock_ace = mbedtls_padlock_has_support( MBEDTLS_PADLOCK_ACE ); + + if( aes_padlock_ace ) + ctx->rk = RK = MBEDTLS_PADLOCK_ALIGN16( ctx->buf ); + else +#endif + ctx->rk = RK = ctx->buf; + + /* Also checks keybits */ + if( ( ret = mbedtls_aes_setkey_enc( &cty, key, keybits ) ) != 0 ) + goto exit; + + ctx->nr = cty.nr; + +#if defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_HAVE_X86_64) + if( mbedtls_aesni_has_support( MBEDTLS_AESNI_AES ) ) + { + mbedtls_aesni_inverse_key( (unsigned char *) ctx->rk, + (const unsigned char *) cty.rk, ctx->nr ); + goto exit; + } +#endif + + SK = cty.rk + cty.nr * 4; + + *RK++ = *SK++; + *RK++ = *SK++; + *RK++ = *SK++; + *RK++ = *SK++; + + for( i = ctx->nr - 1, SK -= 8; i > 0; i--, SK -= 8 ) + { + for( j = 0; j < 4; j++, SK++ ) + { + *RK++ = AES_RT0( FSb[ ( *SK ) & 0xFF ] ) ^ + AES_RT1( FSb[ ( *SK >> 8 ) & 0xFF ] ) ^ + AES_RT2( FSb[ ( *SK >> 16 ) & 0xFF ] ) ^ + AES_RT3( FSb[ ( *SK >> 24 ) & 0xFF ] ); + } + } + + *RK++ = *SK++; + *RK++ = *SK++; + *RK++ = *SK++; + *RK++ = *SK++; + +exit: + mbedtls_aes_free( &cty ); + + return( ret ); +} +#endif /* !MBEDTLS_AES_SETKEY_DEC_ALT */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +static int mbedtls_aes_xts_decode_keys( const unsigned char *key, + unsigned int keybits, + const unsigned char **key1, + unsigned int *key1bits, + const unsigned char **key2, + unsigned int *key2bits ) +{ + const unsigned int half_keybits = keybits / 2; + const unsigned int half_keybytes = half_keybits / 8; + + switch( keybits ) + { + case 256: break; + case 512: break; + default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + *key1bits = half_keybits; + *key2bits = half_keybits; + *key1 = &key[0]; + *key2 = &key[half_keybytes]; + + return 0; +} + +int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1, *key2; + unsigned int key1bits, key2bits; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + + ret = mbedtls_aes_xts_decode_keys( key, keybits, &key1, &key1bits, + &key2, &key2bits ); + if( ret != 0 ) + return( ret ); + + /* Set the tweak key. Always set tweak key for the encryption mode. */ + ret = mbedtls_aes_setkey_enc( &ctx->tweak, key2, key2bits ); + if( ret != 0 ) + return( ret ); + + /* Set crypt key for encryption. */ + return mbedtls_aes_setkey_enc( &ctx->crypt, key1, key1bits ); +} + +int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1, *key2; + unsigned int key1bits, key2bits; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + + ret = mbedtls_aes_xts_decode_keys( key, keybits, &key1, &key1bits, + &key2, &key2bits ); + if( ret != 0 ) + return( ret ); + + /* Set the tweak key. Always set tweak key for encryption. */ + ret = mbedtls_aes_setkey_enc( &ctx->tweak, key2, key2bits ); + if( ret != 0 ) + return( ret ); + + /* Set crypt key for decryption. */ + return mbedtls_aes_setkey_dec( &ctx->crypt, key1, key1bits ); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#define AES_FROUND(X0,X1,X2,X3,Y0,Y1,Y2,Y3) \ + do \ + { \ + (X0) = *RK++ ^ AES_FT0( ( (Y0) ) & 0xFF ) ^ \ + AES_FT1( ( (Y1) >> 8 ) & 0xFF ) ^ \ + AES_FT2( ( (Y2) >> 16 ) & 0xFF ) ^ \ + AES_FT3( ( (Y3) >> 24 ) & 0xFF ); \ + \ + (X1) = *RK++ ^ AES_FT0( ( (Y1) ) & 0xFF ) ^ \ + AES_FT1( ( (Y2) >> 8 ) & 0xFF ) ^ \ + AES_FT2( ( (Y3) >> 16 ) & 0xFF ) ^ \ + AES_FT3( ( (Y0) >> 24 ) & 0xFF ); \ + \ + (X2) = *RK++ ^ AES_FT0( ( (Y2) ) & 0xFF ) ^ \ + AES_FT1( ( (Y3) >> 8 ) & 0xFF ) ^ \ + AES_FT2( ( (Y0) >> 16 ) & 0xFF ) ^ \ + AES_FT3( ( (Y1) >> 24 ) & 0xFF ); \ + \ + (X3) = *RK++ ^ AES_FT0( ( (Y3) ) & 0xFF ) ^ \ + AES_FT1( ( (Y0) >> 8 ) & 0xFF ) ^ \ + AES_FT2( ( (Y1) >> 16 ) & 0xFF ) ^ \ + AES_FT3( ( (Y2) >> 24 ) & 0xFF ); \ + } while( 0 ) + +#define AES_RROUND(X0,X1,X2,X3,Y0,Y1,Y2,Y3) \ + do \ + { \ + (X0) = *RK++ ^ AES_RT0( ( (Y0) ) & 0xFF ) ^ \ + AES_RT1( ( (Y3) >> 8 ) & 0xFF ) ^ \ + AES_RT2( ( (Y2) >> 16 ) & 0xFF ) ^ \ + AES_RT3( ( (Y1) >> 24 ) & 0xFF ); \ + \ + (X1) = *RK++ ^ AES_RT0( ( (Y1) ) & 0xFF ) ^ \ + AES_RT1( ( (Y0) >> 8 ) & 0xFF ) ^ \ + AES_RT2( ( (Y3) >> 16 ) & 0xFF ) ^ \ + AES_RT3( ( (Y2) >> 24 ) & 0xFF ); \ + \ + (X2) = *RK++ ^ AES_RT0( ( (Y2) ) & 0xFF ) ^ \ + AES_RT1( ( (Y1) >> 8 ) & 0xFF ) ^ \ + AES_RT2( ( (Y0) >> 16 ) & 0xFF ) ^ \ + AES_RT3( ( (Y3) >> 24 ) & 0xFF ); \ + \ + (X3) = *RK++ ^ AES_RT0( ( (Y3) ) & 0xFF ) ^ \ + AES_RT1( ( (Y2) >> 8 ) & 0xFF ) ^ \ + AES_RT2( ( (Y1) >> 16 ) & 0xFF ) ^ \ + AES_RT3( ( (Y0) >> 24 ) & 0xFF ); \ + } while( 0 ) + +/* + * AES-ECB block encryption + */ +#if !defined(MBEDTLS_AES_ENCRYPT_ALT) +int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + int i; + uint32_t *RK = ctx->rk; + struct + { + uint32_t X[4]; + uint32_t Y[4]; + } t; + + GET_UINT32_LE( t.X[0], input, 0 ); t.X[0] ^= *RK++; + GET_UINT32_LE( t.X[1], input, 4 ); t.X[1] ^= *RK++; + GET_UINT32_LE( t.X[2], input, 8 ); t.X[2] ^= *RK++; + GET_UINT32_LE( t.X[3], input, 12 ); t.X[3] ^= *RK++; + + for( i = ( ctx->nr >> 1 ) - 1; i > 0; i-- ) + { + AES_FROUND( t.Y[0], t.Y[1], t.Y[2], t.Y[3], t.X[0], t.X[1], t.X[2], t.X[3] ); + AES_FROUND( t.X[0], t.X[1], t.X[2], t.X[3], t.Y[0], t.Y[1], t.Y[2], t.Y[3] ); + } + + AES_FROUND( t.Y[0], t.Y[1], t.Y[2], t.Y[3], t.X[0], t.X[1], t.X[2], t.X[3] ); + + t.X[0] = *RK++ ^ \ + ( (uint32_t) FSb[ ( t.Y[0] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( t.Y[1] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( t.Y[2] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( t.Y[3] >> 24 ) & 0xFF ] << 24 ); + + t.X[1] = *RK++ ^ \ + ( (uint32_t) FSb[ ( t.Y[1] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( t.Y[2] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( t.Y[3] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( t.Y[0] >> 24 ) & 0xFF ] << 24 ); + + t.X[2] = *RK++ ^ \ + ( (uint32_t) FSb[ ( t.Y[2] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( t.Y[3] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( t.Y[0] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( t.Y[1] >> 24 ) & 0xFF ] << 24 ); + + t.X[3] = *RK++ ^ \ + ( (uint32_t) FSb[ ( t.Y[3] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( t.Y[0] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( t.Y[1] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( t.Y[2] >> 24 ) & 0xFF ] << 24 ); + + PUT_UINT32_LE( t.X[0], output, 0 ); + PUT_UINT32_LE( t.X[1], output, 4 ); + PUT_UINT32_LE( t.X[2], output, 8 ); + PUT_UINT32_LE( t.X[3], output, 12 ); + + mbedtls_platform_zeroize( &t, sizeof( t ) ); + + return( 0 ); +} +#endif /* !MBEDTLS_AES_ENCRYPT_ALT */ + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + mbedtls_internal_aes_encrypt( ctx, input, output ); +} +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +/* + * AES-ECB block decryption + */ +#if !defined(MBEDTLS_AES_DECRYPT_ALT) +int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + int i; + uint32_t *RK = ctx->rk; + struct + { + uint32_t X[4]; + uint32_t Y[4]; + } t; + + GET_UINT32_LE( t.X[0], input, 0 ); t.X[0] ^= *RK++; + GET_UINT32_LE( t.X[1], input, 4 ); t.X[1] ^= *RK++; + GET_UINT32_LE( t.X[2], input, 8 ); t.X[2] ^= *RK++; + GET_UINT32_LE( t.X[3], input, 12 ); t.X[3] ^= *RK++; + + for( i = ( ctx->nr >> 1 ) - 1; i > 0; i-- ) + { + AES_RROUND( t.Y[0], t.Y[1], t.Y[2], t.Y[3], t.X[0], t.X[1], t.X[2], t.X[3] ); + AES_RROUND( t.X[0], t.X[1], t.X[2], t.X[3], t.Y[0], t.Y[1], t.Y[2], t.Y[3] ); + } + + AES_RROUND( t.Y[0], t.Y[1], t.Y[2], t.Y[3], t.X[0], t.X[1], t.X[2], t.X[3] ); + + t.X[0] = *RK++ ^ \ + ( (uint32_t) RSb[ ( t.Y[0] ) & 0xFF ] ) ^ + ( (uint32_t) RSb[ ( t.Y[3] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) RSb[ ( t.Y[2] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) RSb[ ( t.Y[1] >> 24 ) & 0xFF ] << 24 ); + + t.X[1] = *RK++ ^ \ + ( (uint32_t) RSb[ ( t.Y[1] ) & 0xFF ] ) ^ + ( (uint32_t) RSb[ ( t.Y[0] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) RSb[ ( t.Y[3] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) RSb[ ( t.Y[2] >> 24 ) & 0xFF ] << 24 ); + + t.X[2] = *RK++ ^ \ + ( (uint32_t) RSb[ ( t.Y[2] ) & 0xFF ] ) ^ + ( (uint32_t) RSb[ ( t.Y[1] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) RSb[ ( t.Y[0] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) RSb[ ( t.Y[3] >> 24 ) & 0xFF ] << 24 ); + + t.X[3] = *RK++ ^ \ + ( (uint32_t) RSb[ ( t.Y[3] ) & 0xFF ] ) ^ + ( (uint32_t) RSb[ ( t.Y[2] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) RSb[ ( t.Y[1] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) RSb[ ( t.Y[0] >> 24 ) & 0xFF ] << 24 ); + + PUT_UINT32_LE( t.X[0], output, 0 ); + PUT_UINT32_LE( t.X[1], output, 4 ); + PUT_UINT32_LE( t.X[2], output, 8 ); + PUT_UINT32_LE( t.X[3], output, 12 ); + + mbedtls_platform_zeroize( &t, sizeof( t ) ); + + return( 0 ); +} +#endif /* !MBEDTLS_AES_DECRYPT_ALT */ + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + mbedtls_internal_aes_decrypt( ctx, input, output ); +} +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +/* + * AES-ECB block encryption/decryption + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) +{ + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + +#if defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_HAVE_X86_64) + if( mbedtls_aesni_has_support( MBEDTLS_AESNI_AES ) ) + return( mbedtls_aesni_crypt_ecb( ctx, mode, input, output ) ); +#endif + +#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86) + if( aes_padlock_ace ) + { + if( mbedtls_padlock_xcryptecb( ctx, mode, input, output ) == 0 ) + return( 0 ); + + // If padlock data misaligned, we just fall back to + // unaccelerated mode + // + } +#endif + + if( mode == MBEDTLS_AES_ENCRYPT ) + return( mbedtls_internal_aes_encrypt( ctx, input, output ) ); + else + return( mbedtls_internal_aes_decrypt( ctx, input, output ) ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/* + * AES-CBC buffer encryption/decryption + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int i; + unsigned char temp[16]; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + AES_VALIDATE_RET( iv != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + if( length % 16 ) + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + +#if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86) + if( aes_padlock_ace ) + { + if( mbedtls_padlock_xcryptcbc( ctx, mode, length, iv, input, output ) == 0 ) + return( 0 ); + + // If padlock data misaligned, we just fall back to + // unaccelerated mode + // + } +#endif + + if( mode == MBEDTLS_AES_DECRYPT ) + { + while( length > 0 ) + { + memcpy( temp, input, 16 ); + mbedtls_aes_crypt_ecb( ctx, mode, input, output ); + + for( i = 0; i < 16; i++ ) + output[i] = (unsigned char)( output[i] ^ iv[i] ); + + memcpy( iv, temp, 16 ); + + input += 16; + output += 16; + length -= 16; + } + } + else + { + while( length > 0 ) + { + for( i = 0; i < 16; i++ ) + output[i] = (unsigned char)( input[i] ^ iv[i] ); + + mbedtls_aes_crypt_ecb( ctx, mode, output, output ); + memcpy( iv, output, 16 ); + + input += 16; + output += 16; + length -= 16; + } + } + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) + +/* Endianess with 64 bits values */ +#ifndef GET_UINT64_LE +#define GET_UINT64_LE(n,b,i) \ +{ \ + (n) = ( (uint64_t) (b)[(i) + 7] << 56 ) \ + | ( (uint64_t) (b)[(i) + 6] << 48 ) \ + | ( (uint64_t) (b)[(i) + 5] << 40 ) \ + | ( (uint64_t) (b)[(i) + 4] << 32 ) \ + | ( (uint64_t) (b)[(i) + 3] << 24 ) \ + | ( (uint64_t) (b)[(i) + 2] << 16 ) \ + | ( (uint64_t) (b)[(i) + 1] << 8 ) \ + | ( (uint64_t) (b)[(i) ] ); \ +} +#endif + +#ifndef PUT_UINT64_LE +#define PUT_UINT64_LE(n,b,i) \ +{ \ + (b)[(i) + 7] = (unsigned char) ( (n) >> 56 ); \ + (b)[(i) + 6] = (unsigned char) ( (n) >> 48 ); \ + (b)[(i) + 5] = (unsigned char) ( (n) >> 40 ); \ + (b)[(i) + 4] = (unsigned char) ( (n) >> 32 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) ] = (unsigned char) ( (n) ); \ +} +#endif + +typedef unsigned char mbedtls_be128[16]; + +/* + * GF(2^128) multiplication function + * + * This function multiplies a field element by x in the polynomial field + * representation. It uses 64-bit word operations to gain speed but compensates + * for machine endianess and hence works correctly on both big and little + * endian machines. + */ +static void mbedtls_gf128mul_x_ble( unsigned char r[16], + const unsigned char x[16] ) +{ + uint64_t a, b, ra, rb; + + GET_UINT64_LE( a, x, 0 ); + GET_UINT64_LE( b, x, 8 ); + + ra = ( a << 1 ) ^ 0x0087 >> ( 8 - ( ( b >> 63 ) << 3 ) ); + rb = ( a >> 63 ) | ( b << 1 ); + + PUT_UINT64_LE( ra, r, 0 ); + PUT_UINT64_LE( rb, r, 8 ); +} + +/* + * AES-XTS buffer encryption/decryption + */ +int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx, + int mode, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output ) +{ + int ret; + size_t blocks = length / 16; + size_t leftover = length % 16; + unsigned char tweak[16]; + unsigned char prev_tweak[16]; + unsigned char tmp[16]; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + AES_VALIDATE_RET( data_unit != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + /* Data units must be at least 16 bytes long. */ + if( length < 16 ) + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + + /* NIST SP 800-38E disallows data units larger than 2**20 blocks. */ + if( length > ( 1 << 20 ) * 16 ) + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + + /* Compute the tweak. */ + ret = mbedtls_aes_crypt_ecb( &ctx->tweak, MBEDTLS_AES_ENCRYPT, + data_unit, tweak ); + if( ret != 0 ) + return( ret ); + + while( blocks-- ) + { + size_t i; + + if( leftover && ( mode == MBEDTLS_AES_DECRYPT ) && blocks == 0 ) + { + /* We are on the last block in a decrypt operation that has + * leftover bytes, so we need to use the next tweak for this block, + * and this tweak for the lefover bytes. Save the current tweak for + * the leftovers and then update the current tweak for use on this, + * the last full block. */ + memcpy( prev_tweak, tweak, sizeof( tweak ) ); + mbedtls_gf128mul_x_ble( tweak, tweak ); + } + + for( i = 0; i < 16; i++ ) + tmp[i] = input[i] ^ tweak[i]; + + ret = mbedtls_aes_crypt_ecb( &ctx->crypt, mode, tmp, tmp ); + if( ret != 0 ) + return( ret ); + + for( i = 0; i < 16; i++ ) + output[i] = tmp[i] ^ tweak[i]; + + /* Update the tweak for the next block. */ + mbedtls_gf128mul_x_ble( tweak, tweak ); + + output += 16; + input += 16; + } + + if( leftover ) + { + /* If we are on the leftover bytes in a decrypt operation, we need to + * use the previous tweak for these bytes (as saved in prev_tweak). */ + unsigned char *t = mode == MBEDTLS_AES_DECRYPT ? prev_tweak : tweak; + + /* We are now on the final part of the data unit, which doesn't divide + * evenly by 16. It's time for ciphertext stealing. */ + size_t i; + unsigned char *prev_output = output - 16; + + /* Copy ciphertext bytes from the previous block to our output for each + * byte of cyphertext we won't steal. At the same time, copy the + * remainder of the input for this final round (since the loop bounds + * are the same). */ + for( i = 0; i < leftover; i++ ) + { + output[i] = prev_output[i]; + tmp[i] = input[i] ^ t[i]; + } + + /* Copy ciphertext bytes from the previous block for input in this + * round. */ + for( ; i < 16; i++ ) + tmp[i] = prev_output[i] ^ t[i]; + + ret = mbedtls_aes_crypt_ecb( &ctx->crypt, mode, tmp, tmp ); + if( ret != 0 ) + return ret; + + /* Write the result back to the previous block, overriding the previous + * output we copied. */ + for( i = 0; i < 16; i++ ) + prev_output[i] = tmp[i] ^ t[i]; + } + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/* + * AES-CFB128 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int c; + size_t n; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + AES_VALIDATE_RET( iv_off != NULL ); + AES_VALIDATE_RET( iv != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + n = *iv_off; + + if( n > 15 ) + return( MBEDTLS_ERR_AES_BAD_INPUT_DATA ); + + if( mode == MBEDTLS_AES_DECRYPT ) + { + while( length-- ) + { + if( n == 0 ) + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + + n = ( n + 1 ) & 0x0F; + } + } + else + { + while( length-- ) + { + if( n == 0 ) + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + + n = ( n + 1 ) & 0x0F; + } + } + + *iv_off = n; + + return( 0 ); +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char c; + unsigned char ov[17]; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + AES_VALIDATE_RET( iv != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + while( length-- ) + { + memcpy( ov, iv, 16 ); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + if( mode == MBEDTLS_AES_DECRYPT ) + ov[16] = *input; + + c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + + if( mode == MBEDTLS_AES_ENCRYPT ) + ov[16] = c; + + memcpy( iv, ov + 1, 16 ); + } + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +/* + * AES-OFB (Output Feedback Mode) buffer encryption/decryption + */ +int mbedtls_aes_crypt_ofb( mbedtls_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int ret = 0; + size_t n; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( iv_off != NULL ); + AES_VALIDATE_RET( iv != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + n = *iv_off; + + if( n > 15 ) + return( MBEDTLS_ERR_AES_BAD_INPUT_DATA ); + + while( length-- ) + { + if( n == 0 ) + { + ret = mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + if( ret != 0 ) + goto exit; + } + *output++ = *input++ ^ iv[n]; + + n = ( n + 1 ) & 0x0F; + } + + *iv_off = n; + +exit: + return( ret ); +} +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR buffer encryption/decryption + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) +{ + int c, i; + size_t n; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( nc_off != NULL ); + AES_VALIDATE_RET( nonce_counter != NULL ); + AES_VALIDATE_RET( stream_block != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + n = *nc_off; + + if ( n > 0x0F ) + return( MBEDTLS_ERR_AES_BAD_INPUT_DATA ); + + while( length-- ) + { + if( n == 0 ) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); + + for( i = 16; i > 0; i-- ) + if( ++nonce_counter[i - 1] != 0 ) + break; + } + c = *input++; + *output++ = (unsigned char)( c ^ stream_block[n] ); + + n = ( n + 1 ) & 0x0F; + } + + *nc_off = n; + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#endif /* !MBEDTLS_AES_ALT */ + +#if defined(MBEDTLS_SELF_TEST) +/* + * AES test vectors from: + * + * https://csrc.nist.gov/archive/aes/rijndael/rijndael-vals.zip + */ +static const unsigned char aes_test_ecb_dec[3][16] = +{ + { 0x44, 0x41, 0x6A, 0xC2, 0xD1, 0xF5, 0x3C, 0x58, + 0x33, 0x03, 0x91, 0x7E, 0x6B, 0xE9, 0xEB, 0xE0 }, + { 0x48, 0xE3, 0x1E, 0x9E, 0x25, 0x67, 0x18, 0xF2, + 0x92, 0x29, 0x31, 0x9C, 0x19, 0xF1, 0x5B, 0xA4 }, + { 0x05, 0x8C, 0xCF, 0xFD, 0xBB, 0xCB, 0x38, 0x2D, + 0x1F, 0x6F, 0x56, 0x58, 0x5D, 0x8A, 0x4A, 0xDE } +}; + +static const unsigned char aes_test_ecb_enc[3][16] = +{ + { 0xC3, 0x4C, 0x05, 0x2C, 0xC0, 0xDA, 0x8D, 0x73, + 0x45, 0x1A, 0xFE, 0x5F, 0x03, 0xBE, 0x29, 0x7F }, + { 0xF3, 0xF6, 0x75, 0x2A, 0xE8, 0xD7, 0x83, 0x11, + 0x38, 0xF0, 0x41, 0x56, 0x06, 0x31, 0xB1, 0x14 }, + { 0x8B, 0x79, 0xEE, 0xCC, 0x93, 0xA0, 0xEE, 0x5D, + 0xFF, 0x30, 0xB4, 0xEA, 0x21, 0x63, 0x6D, 0xA4 } +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const unsigned char aes_test_cbc_dec[3][16] = +{ + { 0xFA, 0xCA, 0x37, 0xE0, 0xB0, 0xC8, 0x53, 0x73, + 0xDF, 0x70, 0x6E, 0x73, 0xF7, 0xC9, 0xAF, 0x86 }, + { 0x5D, 0xF6, 0x78, 0xDD, 0x17, 0xBA, 0x4E, 0x75, + 0xB6, 0x17, 0x68, 0xC6, 0xAD, 0xEF, 0x7C, 0x7B }, + { 0x48, 0x04, 0xE1, 0x81, 0x8F, 0xE6, 0x29, 0x75, + 0x19, 0xA3, 0xE8, 0x8C, 0x57, 0x31, 0x04, 0x13 } +}; + +static const unsigned char aes_test_cbc_enc[3][16] = +{ + { 0x8A, 0x05, 0xFC, 0x5E, 0x09, 0x5A, 0xF4, 0x84, + 0x8A, 0x08, 0xD3, 0x28, 0xD3, 0x68, 0x8E, 0x3D }, + { 0x7B, 0xD9, 0x66, 0xD5, 0x3A, 0xD8, 0xC1, 0xBB, + 0x85, 0xD2, 0xAD, 0xFA, 0xE8, 0x7B, 0xB1, 0x04 }, + { 0xFE, 0x3C, 0x53, 0x65, 0x3E, 0x2F, 0x45, 0xB5, + 0x6F, 0xCD, 0x88, 0xB2, 0xCC, 0x89, 0x8F, 0xF0 } +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/* + * AES-CFB128 test vectors from: + * + * https://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf + */ +static const unsigned char aes_test_cfb128_key[3][32] = +{ + { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }, + { 0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52, + 0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5, + 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B }, + { 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, + 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, + 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, + 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 } +}; + +static const unsigned char aes_test_cfb128_iv[16] = +{ + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +}; + +static const unsigned char aes_test_cfb128_pt[64] = +{ + 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A, + 0xAE, 0x2D, 0x8A, 0x57, 0x1E, 0x03, 0xAC, 0x9C, + 0x9E, 0xB7, 0x6F, 0xAC, 0x45, 0xAF, 0x8E, 0x51, + 0x30, 0xC8, 0x1C, 0x46, 0xA3, 0x5C, 0xE4, 0x11, + 0xE5, 0xFB, 0xC1, 0x19, 0x1A, 0x0A, 0x52, 0xEF, + 0xF6, 0x9F, 0x24, 0x45, 0xDF, 0x4F, 0x9B, 0x17, + 0xAD, 0x2B, 0x41, 0x7B, 0xE6, 0x6C, 0x37, 0x10 +}; + +static const unsigned char aes_test_cfb128_ct[3][64] = +{ + { 0x3B, 0x3F, 0xD9, 0x2E, 0xB7, 0x2D, 0xAD, 0x20, + 0x33, 0x34, 0x49, 0xF8, 0xE8, 0x3C, 0xFB, 0x4A, + 0xC8, 0xA6, 0x45, 0x37, 0xA0, 0xB3, 0xA9, 0x3F, + 0xCD, 0xE3, 0xCD, 0xAD, 0x9F, 0x1C, 0xE5, 0x8B, + 0x26, 0x75, 0x1F, 0x67, 0xA3, 0xCB, 0xB1, 0x40, + 0xB1, 0x80, 0x8C, 0xF1, 0x87, 0xA4, 0xF4, 0xDF, + 0xC0, 0x4B, 0x05, 0x35, 0x7C, 0x5D, 0x1C, 0x0E, + 0xEA, 0xC4, 0xC6, 0x6F, 0x9F, 0xF7, 0xF2, 0xE6 }, + { 0xCD, 0xC8, 0x0D, 0x6F, 0xDD, 0xF1, 0x8C, 0xAB, + 0x34, 0xC2, 0x59, 0x09, 0xC9, 0x9A, 0x41, 0x74, + 0x67, 0xCE, 0x7F, 0x7F, 0x81, 0x17, 0x36, 0x21, + 0x96, 0x1A, 0x2B, 0x70, 0x17, 0x1D, 0x3D, 0x7A, + 0x2E, 0x1E, 0x8A, 0x1D, 0xD5, 0x9B, 0x88, 0xB1, + 0xC8, 0xE6, 0x0F, 0xED, 0x1E, 0xFA, 0xC4, 0xC9, + 0xC0, 0x5F, 0x9F, 0x9C, 0xA9, 0x83, 0x4F, 0xA0, + 0x42, 0xAE, 0x8F, 0xBA, 0x58, 0x4B, 0x09, 0xFF }, + { 0xDC, 0x7E, 0x84, 0xBF, 0xDA, 0x79, 0x16, 0x4B, + 0x7E, 0xCD, 0x84, 0x86, 0x98, 0x5D, 0x38, 0x60, + 0x39, 0xFF, 0xED, 0x14, 0x3B, 0x28, 0xB1, 0xC8, + 0x32, 0x11, 0x3C, 0x63, 0x31, 0xE5, 0x40, 0x7B, + 0xDF, 0x10, 0x13, 0x24, 0x15, 0xE5, 0x4B, 0x92, + 0xA1, 0x3E, 0xD0, 0xA8, 0x26, 0x7A, 0xE2, 0xF9, + 0x75, 0xA3, 0x85, 0x74, 0x1A, 0xB9, 0xCE, 0xF8, + 0x20, 0x31, 0x62, 0x3D, 0x55, 0xB1, 0xE4, 0x71 } +}; +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +/* + * AES-OFB test vectors from: + * + * https://csrc.nist.gov/publications/detail/sp/800-38a/final + */ +static const unsigned char aes_test_ofb_key[3][32] = +{ + { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }, + { 0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52, + 0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5, + 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B }, + { 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, + 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, + 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, + 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 } +}; + +static const unsigned char aes_test_ofb_iv[16] = +{ + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +}; + +static const unsigned char aes_test_ofb_pt[64] = +{ + 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A, + 0xAE, 0x2D, 0x8A, 0x57, 0x1E, 0x03, 0xAC, 0x9C, + 0x9E, 0xB7, 0x6F, 0xAC, 0x45, 0xAF, 0x8E, 0x51, + 0x30, 0xC8, 0x1C, 0x46, 0xA3, 0x5C, 0xE4, 0x11, + 0xE5, 0xFB, 0xC1, 0x19, 0x1A, 0x0A, 0x52, 0xEF, + 0xF6, 0x9F, 0x24, 0x45, 0xDF, 0x4F, 0x9B, 0x17, + 0xAD, 0x2B, 0x41, 0x7B, 0xE6, 0x6C, 0x37, 0x10 +}; + +static const unsigned char aes_test_ofb_ct[3][64] = +{ + { 0x3B, 0x3F, 0xD9, 0x2E, 0xB7, 0x2D, 0xAD, 0x20, + 0x33, 0x34, 0x49, 0xF8, 0xE8, 0x3C, 0xFB, 0x4A, + 0x77, 0x89, 0x50, 0x8d, 0x16, 0x91, 0x8f, 0x03, + 0xf5, 0x3c, 0x52, 0xda, 0xc5, 0x4e, 0xd8, 0x25, + 0x97, 0x40, 0x05, 0x1e, 0x9c, 0x5f, 0xec, 0xf6, + 0x43, 0x44, 0xf7, 0xa8, 0x22, 0x60, 0xed, 0xcc, + 0x30, 0x4c, 0x65, 0x28, 0xf6, 0x59, 0xc7, 0x78, + 0x66, 0xa5, 0x10, 0xd9, 0xc1, 0xd6, 0xae, 0x5e }, + { 0xCD, 0xC8, 0x0D, 0x6F, 0xDD, 0xF1, 0x8C, 0xAB, + 0x34, 0xC2, 0x59, 0x09, 0xC9, 0x9A, 0x41, 0x74, + 0xfc, 0xc2, 0x8b, 0x8d, 0x4c, 0x63, 0x83, 0x7c, + 0x09, 0xe8, 0x17, 0x00, 0xc1, 0x10, 0x04, 0x01, + 0x8d, 0x9a, 0x9a, 0xea, 0xc0, 0xf6, 0x59, 0x6f, + 0x55, 0x9c, 0x6d, 0x4d, 0xaf, 0x59, 0xa5, 0xf2, + 0x6d, 0x9f, 0x20, 0x08, 0x57, 0xca, 0x6c, 0x3e, + 0x9c, 0xac, 0x52, 0x4b, 0xd9, 0xac, 0xc9, 0x2a }, + { 0xDC, 0x7E, 0x84, 0xBF, 0xDA, 0x79, 0x16, 0x4B, + 0x7E, 0xCD, 0x84, 0x86, 0x98, 0x5D, 0x38, 0x60, + 0x4f, 0xeb, 0xdc, 0x67, 0x40, 0xd2, 0x0b, 0x3a, + 0xc8, 0x8f, 0x6a, 0xd8, 0x2a, 0x4f, 0xb0, 0x8d, + 0x71, 0xab, 0x47, 0xa0, 0x86, 0xe8, 0x6e, 0xed, + 0xf3, 0x9d, 0x1c, 0x5b, 0xba, 0x97, 0xc4, 0x08, + 0x01, 0x26, 0x14, 0x1d, 0x67, 0xf3, 0x7b, 0xe8, + 0x53, 0x8f, 0x5a, 0x8b, 0xe7, 0x40, 0xe4, 0x84 } +}; +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR test vectors from: + * + * https://www.faqs.org/rfcs/rfc3686.html + */ + +static const unsigned char aes_test_ctr_key[3][16] = +{ + { 0xAE, 0x68, 0x52, 0xF8, 0x12, 0x10, 0x67, 0xCC, + 0x4B, 0xF7, 0xA5, 0x76, 0x55, 0x77, 0xF3, 0x9E }, + { 0x7E, 0x24, 0x06, 0x78, 0x17, 0xFA, 0xE0, 0xD7, + 0x43, 0xD6, 0xCE, 0x1F, 0x32, 0x53, 0x91, 0x63 }, + { 0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC } +}; + +static const unsigned char aes_test_ctr_nonce_counter[3][16] = +{ + { 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }, + { 0x00, 0x6C, 0xB6, 0xDB, 0xC0, 0x54, 0x3B, 0x59, + 0xDA, 0x48, 0xD9, 0x0B, 0x00, 0x00, 0x00, 0x01 }, + { 0x00, 0xE0, 0x01, 0x7B, 0x27, 0x77, 0x7F, 0x3F, + 0x4A, 0x17, 0x86, 0xF0, 0x00, 0x00, 0x00, 0x01 } +}; + +static const unsigned char aes_test_ctr_pt[3][48] = +{ + { 0x53, 0x69, 0x6E, 0x67, 0x6C, 0x65, 0x20, 0x62, + 0x6C, 0x6F, 0x63, 0x6B, 0x20, 0x6D, 0x73, 0x67 }, + + { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F }, + + { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23 } +}; + +static const unsigned char aes_test_ctr_ct[3][48] = +{ + { 0xE4, 0x09, 0x5D, 0x4F, 0xB7, 0xA7, 0xB3, 0x79, + 0x2D, 0x61, 0x75, 0xA3, 0x26, 0x13, 0x11, 0xB8 }, + { 0x51, 0x04, 0xA1, 0x06, 0x16, 0x8A, 0x72, 0xD9, + 0x79, 0x0D, 0x41, 0xEE, 0x8E, 0xDA, 0xD3, 0x88, + 0xEB, 0x2E, 0x1E, 0xFC, 0x46, 0xDA, 0x57, 0xC8, + 0xFC, 0xE6, 0x30, 0xDF, 0x91, 0x41, 0xBE, 0x28 }, + { 0xC1, 0xCF, 0x48, 0xA8, 0x9F, 0x2F, 0xFD, 0xD9, + 0xCF, 0x46, 0x52, 0xE9, 0xEF, 0xDB, 0x72, 0xD7, + 0x45, 0x40, 0xA4, 0x2B, 0xDE, 0x6D, 0x78, 0x36, + 0xD5, 0x9A, 0x5C, 0xEA, 0xAE, 0xF3, 0x10, 0x53, + 0x25, 0xB2, 0x07, 0x2F } +}; + +static const int aes_test_ctr_len[3] = + { 16, 32, 36 }; +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/* + * AES-XTS test vectors from: + * + * IEEE P1619/D16 Annex B + * https://web.archive.org/web/20150629024421/https://grouper.ieee.org/groups/1619/email/pdf00086.pdf + * (Archived from original at https://grouper.ieee.org/groups/1619/email/pdf00086.pdf) + */ +static const unsigned char aes_test_xts_key[][32] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, + 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22 }, + { 0xff, 0xfe, 0xfd, 0xfc, 0xfb, 0xfa, 0xf9, 0xf8, + 0xf7, 0xf6, 0xf5, 0xf4, 0xf3, 0xf2, 0xf1, 0xf0, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22 }, +}; + +static const unsigned char aes_test_xts_pt32[][32] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44 }, + { 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44 }, +}; + +static const unsigned char aes_test_xts_ct32[][32] = +{ + { 0x91, 0x7c, 0xf6, 0x9e, 0xbd, 0x68, 0xb2, 0xec, + 0x9b, 0x9f, 0xe9, 0xa3, 0xea, 0xdd, 0xa6, 0x92, + 0xcd, 0x43, 0xd2, 0xf5, 0x95, 0x98, 0xed, 0x85, + 0x8c, 0x02, 0xc2, 0x65, 0x2f, 0xbf, 0x92, 0x2e }, + { 0xc4, 0x54, 0x18, 0x5e, 0x6a, 0x16, 0x93, 0x6e, + 0x39, 0x33, 0x40, 0x38, 0xac, 0xef, 0x83, 0x8b, + 0xfb, 0x18, 0x6f, 0xff, 0x74, 0x80, 0xad, 0xc4, + 0x28, 0x93, 0x82, 0xec, 0xd6, 0xd3, 0x94, 0xf0 }, + { 0xaf, 0x85, 0x33, 0x6b, 0x59, 0x7a, 0xfc, 0x1a, + 0x90, 0x0b, 0x2e, 0xb2, 0x1e, 0xc9, 0x49, 0xd2, + 0x92, 0xdf, 0x4c, 0x04, 0x7e, 0x0b, 0x21, 0x53, + 0x21, 0x86, 0xa5, 0x97, 0x1a, 0x22, 0x7a, 0x89 }, +}; + +static const unsigned char aes_test_xts_data_unit[][16] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, +}; + +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/* + * Checkup routine + */ +int mbedtls_aes_self_test( int verbose ) +{ + int ret = 0, i, j, u, mode; + unsigned int keybits; + unsigned char key[32]; + unsigned char buf[64]; + const unsigned char *aes_tests; +#if defined(MBEDTLS_CIPHER_MODE_CBC) || defined(MBEDTLS_CIPHER_MODE_CFB) + unsigned char iv[16]; +#endif +#if defined(MBEDTLS_CIPHER_MODE_CBC) + unsigned char prv[16]; +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) || defined(MBEDTLS_CIPHER_MODE_CFB) || \ + defined(MBEDTLS_CIPHER_MODE_OFB) + size_t offset; +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) || defined(MBEDTLS_CIPHER_MODE_XTS) + int len; +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + unsigned char nonce_counter[16]; + unsigned char stream_block[16]; +#endif + mbedtls_aes_context ctx; + + memset( key, 0, 32 ); + mbedtls_aes_init( &ctx ); + + /* + * ECB mode + */ + for( i = 0; i < 6; i++ ) + { + u = i >> 1; + keybits = 128 + u * 64; + mode = i & 1; + + if( verbose != 0 ) + mbedtls_printf( " AES-ECB-%3d (%s): ", keybits, + ( mode == MBEDTLS_AES_DECRYPT ) ? "dec" : "enc" ); + + memset( buf, 0, 16 ); + + if( mode == MBEDTLS_AES_DECRYPT ) + { + ret = mbedtls_aes_setkey_dec( &ctx, key, keybits ); + aes_tests = aes_test_ecb_dec[u]; + } + else + { + ret = mbedtls_aes_setkey_enc( &ctx, key, keybits ); + aes_tests = aes_test_ecb_enc[u]; + } + + /* + * AES-192 is an optional feature that may be unavailable when + * there is an alternative underlying implementation i.e. when + * MBEDTLS_AES_ALT is defined. + */ + if( ret == MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED && keybits == 192 ) + { + mbedtls_printf( "skipped\n" ); + continue; + } + else if( ret != 0 ) + { + goto exit; + } + + for( j = 0; j < 10000; j++ ) + { + ret = mbedtls_aes_crypt_ecb( &ctx, mode, buf, buf ); + if( ret != 0 ) + goto exit; + } + + if( memcmp( buf, aes_tests, 16 ) != 0 ) + { + ret = 1; + goto exit; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + /* + * CBC mode + */ + for( i = 0; i < 6; i++ ) + { + u = i >> 1; + keybits = 128 + u * 64; + mode = i & 1; + + if( verbose != 0 ) + mbedtls_printf( " AES-CBC-%3d (%s): ", keybits, + ( mode == MBEDTLS_AES_DECRYPT ) ? "dec" : "enc" ); + + memset( iv , 0, 16 ); + memset( prv, 0, 16 ); + memset( buf, 0, 16 ); + + if( mode == MBEDTLS_AES_DECRYPT ) + { + ret = mbedtls_aes_setkey_dec( &ctx, key, keybits ); + aes_tests = aes_test_cbc_dec[u]; + } + else + { + ret = mbedtls_aes_setkey_enc( &ctx, key, keybits ); + aes_tests = aes_test_cbc_enc[u]; + } + + /* + * AES-192 is an optional feature that may be unavailable when + * there is an alternative underlying implementation i.e. when + * MBEDTLS_AES_ALT is defined. + */ + if( ret == MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED && keybits == 192 ) + { + mbedtls_printf( "skipped\n" ); + continue; + } + else if( ret != 0 ) + { + goto exit; + } + + for( j = 0; j < 10000; j++ ) + { + if( mode == MBEDTLS_AES_ENCRYPT ) + { + unsigned char tmp[16]; + + memcpy( tmp, prv, 16 ); + memcpy( prv, buf, 16 ); + memcpy( buf, tmp, 16 ); + } + + ret = mbedtls_aes_crypt_cbc( &ctx, mode, 16, iv, buf, buf ); + if( ret != 0 ) + goto exit; + + } + + if( memcmp( buf, aes_tests, 16 ) != 0 ) + { + ret = 1; + goto exit; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) + /* + * CFB128 mode + */ + for( i = 0; i < 6; i++ ) + { + u = i >> 1; + keybits = 128 + u * 64; + mode = i & 1; + + if( verbose != 0 ) + mbedtls_printf( " AES-CFB128-%3d (%s): ", keybits, + ( mode == MBEDTLS_AES_DECRYPT ) ? "dec" : "enc" ); + + memcpy( iv, aes_test_cfb128_iv, 16 ); + memcpy( key, aes_test_cfb128_key[u], keybits / 8 ); + + offset = 0; + ret = mbedtls_aes_setkey_enc( &ctx, key, keybits ); + /* + * AES-192 is an optional feature that may be unavailable when + * there is an alternative underlying implementation i.e. when + * MBEDTLS_AES_ALT is defined. + */ + if( ret == MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED && keybits == 192 ) + { + mbedtls_printf( "skipped\n" ); + continue; + } + else if( ret != 0 ) + { + goto exit; + } + + if( mode == MBEDTLS_AES_DECRYPT ) + { + memcpy( buf, aes_test_cfb128_ct[u], 64 ); + aes_tests = aes_test_cfb128_pt; + } + else + { + memcpy( buf, aes_test_cfb128_pt, 64 ); + aes_tests = aes_test_cfb128_ct[u]; + } + + ret = mbedtls_aes_crypt_cfb128( &ctx, mode, 64, &offset, iv, buf, buf ); + if( ret != 0 ) + goto exit; + + if( memcmp( buf, aes_tests, 64 ) != 0 ) + { + ret = 1; + goto exit; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) + /* + * OFB mode + */ + for( i = 0; i < 6; i++ ) + { + u = i >> 1; + keybits = 128 + u * 64; + mode = i & 1; + + if( verbose != 0 ) + mbedtls_printf( " AES-OFB-%3d (%s): ", keybits, + ( mode == MBEDTLS_AES_DECRYPT ) ? "dec" : "enc" ); + + memcpy( iv, aes_test_ofb_iv, 16 ); + memcpy( key, aes_test_ofb_key[u], keybits / 8 ); + + offset = 0; + ret = mbedtls_aes_setkey_enc( &ctx, key, keybits ); + /* + * AES-192 is an optional feature that may be unavailable when + * there is an alternative underlying implementation i.e. when + * MBEDTLS_AES_ALT is defined. + */ + if( ret == MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED && keybits == 192 ) + { + mbedtls_printf( "skipped\n" ); + continue; + } + else if( ret != 0 ) + { + goto exit; + } + + if( mode == MBEDTLS_AES_DECRYPT ) + { + memcpy( buf, aes_test_ofb_ct[u], 64 ); + aes_tests = aes_test_ofb_pt; + } + else + { + memcpy( buf, aes_test_ofb_pt, 64 ); + aes_tests = aes_test_ofb_ct[u]; + } + + ret = mbedtls_aes_crypt_ofb( &ctx, 64, &offset, iv, buf, buf ); + if( ret != 0 ) + goto exit; + + if( memcmp( buf, aes_tests, 64 ) != 0 ) + { + ret = 1; + goto exit; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) + /* + * CTR mode + */ + for( i = 0; i < 6; i++ ) + { + u = i >> 1; + mode = i & 1; + + if( verbose != 0 ) + mbedtls_printf( " AES-CTR-128 (%s): ", + ( mode == MBEDTLS_AES_DECRYPT ) ? "dec" : "enc" ); + + memcpy( nonce_counter, aes_test_ctr_nonce_counter[u], 16 ); + memcpy( key, aes_test_ctr_key[u], 16 ); + + offset = 0; + if( ( ret = mbedtls_aes_setkey_enc( &ctx, key, 128 ) ) != 0 ) + goto exit; + + len = aes_test_ctr_len[u]; + + if( mode == MBEDTLS_AES_DECRYPT ) + { + memcpy( buf, aes_test_ctr_ct[u], len ); + aes_tests = aes_test_ctr_pt[u]; + } + else + { + memcpy( buf, aes_test_ctr_pt[u], len ); + aes_tests = aes_test_ctr_ct[u]; + } + + ret = mbedtls_aes_crypt_ctr( &ctx, len, &offset, nonce_counter, + stream_block, buf, buf ); + if( ret != 0 ) + goto exit; + + if( memcmp( buf, aes_tests, len ) != 0 ) + { + ret = 1; + goto exit; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) + { + static const int num_tests = + sizeof(aes_test_xts_key) / sizeof(*aes_test_xts_key); + mbedtls_aes_xts_context ctx_xts; + + /* + * XTS mode + */ + mbedtls_aes_xts_init( &ctx_xts ); + + for( i = 0; i < num_tests << 1; i++ ) + { + const unsigned char *data_unit; + u = i >> 1; + mode = i & 1; + + if( verbose != 0 ) + mbedtls_printf( " AES-XTS-128 (%s): ", + ( mode == MBEDTLS_AES_DECRYPT ) ? "dec" : "enc" ); + + memset( key, 0, sizeof( key ) ); + memcpy( key, aes_test_xts_key[u], 32 ); + data_unit = aes_test_xts_data_unit[u]; + + len = sizeof( *aes_test_xts_ct32 ); + + if( mode == MBEDTLS_AES_DECRYPT ) + { + ret = mbedtls_aes_xts_setkey_dec( &ctx_xts, key, 256 ); + if( ret != 0) + goto exit; + memcpy( buf, aes_test_xts_ct32[u], len ); + aes_tests = aes_test_xts_pt32[u]; + } + else + { + ret = mbedtls_aes_xts_setkey_enc( &ctx_xts, key, 256 ); + if( ret != 0) + goto exit; + memcpy( buf, aes_test_xts_pt32[u], len ); + aes_tests = aes_test_xts_ct32[u]; + } + + + ret = mbedtls_aes_crypt_xts( &ctx_xts, mode, len, data_unit, + buf, buf ); + if( ret != 0 ) + goto exit; + + if( memcmp( buf, aes_tests, len ) != 0 ) + { + ret = 1; + goto exit; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + mbedtls_aes_xts_free( &ctx_xts ); + } +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + + ret = 0; + +exit: + if( ret != 0 && verbose != 0 ) + mbedtls_printf( "failed\n" ); + + mbedtls_aes_free( &ctx ); + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_AES_C */ diff --git a/src/common/mbedtls/library/mbedtls_asn1parse.c b/src/common/mbedtls/library/mbedtls_asn1parse.c new file mode 100644 index 0000000000..fa5a237ad7 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_asn1parse.c @@ -0,0 +1,402 @@ +/* + * Generic ASN.1 parsing + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ASN1_PARSE_C) + +#include "mbedtls/asn1.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_BIGNUM_C) +#include "mbedtls/bignum.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +/* + * ASN.1 DER decoding routines + */ +int mbedtls_asn1_get_len( unsigned char **p, + const unsigned char *end, + size_t *len ) +{ + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + if( ( **p & 0x80 ) == 0 ) + *len = *(*p)++; + else + { + switch( **p & 0x7F ) + { + case 1: + if( ( end - *p ) < 2 ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + *len = (*p)[1]; + (*p) += 2; + break; + + case 2: + if( ( end - *p ) < 3 ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + *len = ( (size_t)(*p)[1] << 8 ) | (*p)[2]; + (*p) += 3; + break; + + case 3: + if( ( end - *p ) < 4 ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + *len = ( (size_t)(*p)[1] << 16 ) | + ( (size_t)(*p)[2] << 8 ) | (*p)[3]; + (*p) += 4; + break; + + case 4: + if( ( end - *p ) < 5 ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + *len = ( (size_t)(*p)[1] << 24 ) | ( (size_t)(*p)[2] << 16 ) | + ( (size_t)(*p)[3] << 8 ) | (*p)[4]; + (*p) += 5; + break; + + default: + return( MBEDTLS_ERR_ASN1_INVALID_LENGTH ); + } + } + + if( *len > (size_t) ( end - *p ) ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + return( 0 ); +} + +int mbedtls_asn1_get_tag( unsigned char **p, + const unsigned char *end, + size_t *len, int tag ) +{ + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + if( **p != tag ) + return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + + (*p)++; + + return( mbedtls_asn1_get_len( p, end, len ) ); +} + +int mbedtls_asn1_get_bool( unsigned char **p, + const unsigned char *end, + int *val ) +{ + int ret; + size_t len; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_BOOLEAN ) ) != 0 ) + return( ret ); + + if( len != 1 ) + return( MBEDTLS_ERR_ASN1_INVALID_LENGTH ); + + *val = ( **p != 0 ) ? 1 : 0; + (*p)++; + + return( 0 ); +} + +int mbedtls_asn1_get_int( unsigned char **p, + const unsigned char *end, + int *val ) +{ + int ret; + size_t len; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 ) + return( ret ); + + if( len == 0 || len > sizeof( int ) || ( **p & 0x80 ) != 0 ) + return( MBEDTLS_ERR_ASN1_INVALID_LENGTH ); + + *val = 0; + + while( len-- > 0 ) + { + *val = ( *val << 8 ) | **p; + (*p)++; + } + + return( 0 ); +} + +#if defined(MBEDTLS_BIGNUM_C) +int mbedtls_asn1_get_mpi( unsigned char **p, + const unsigned char *end, + mbedtls_mpi *X ) +{ + int ret; + size_t len; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 ) + return( ret ); + + ret = mbedtls_mpi_read_binary( X, *p, len ); + + *p += len; + + return( ret ); +} +#endif /* MBEDTLS_BIGNUM_C */ + +int mbedtls_asn1_get_bitstring( unsigned char **p, const unsigned char *end, + mbedtls_asn1_bitstring *bs) +{ + int ret; + + /* Certificate type is a single byte bitstring */ + if( ( ret = mbedtls_asn1_get_tag( p, end, &bs->len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 ) + return( ret ); + + /* Check length, subtract one for actual bit string length */ + if( bs->len < 1 ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + bs->len -= 1; + + /* Get number of unused bits, ensure unused bits <= 7 */ + bs->unused_bits = **p; + if( bs->unused_bits > 7 ) + return( MBEDTLS_ERR_ASN1_INVALID_LENGTH ); + (*p)++; + + /* Get actual bitstring */ + bs->p = *p; + *p += bs->len; + + if( *p != end ) + return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +/* + * Get a bit string without unused bits + */ +int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end, + size_t *len ) +{ + int ret; + + if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 ) + return( ret ); + + if( (*len)-- < 2 || *(*p)++ != 0 ) + return( MBEDTLS_ERR_ASN1_INVALID_DATA ); + + return( 0 ); +} + + + +/* + * Parses and splits an ASN.1 "SEQUENCE OF " + */ +int mbedtls_asn1_get_sequence_of( unsigned char **p, + const unsigned char *end, + mbedtls_asn1_sequence *cur, + int tag) +{ + int ret; + size_t len; + mbedtls_asn1_buf *buf; + + /* Get main sequence tag */ + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( ret ); + + if( *p + len != end ) + return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + while( *p < end ) + { + buf = &(cur->buf); + buf->tag = **p; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &buf->len, tag ) ) != 0 ) + return( ret ); + + buf->p = *p; + *p += buf->len; + + /* Allocate and assign next pointer */ + if( *p < end ) + { + cur->next = (mbedtls_asn1_sequence*)mbedtls_calloc( 1, + sizeof( mbedtls_asn1_sequence ) ); + + if( cur->next == NULL ) + return( MBEDTLS_ERR_ASN1_ALLOC_FAILED ); + + cur = cur->next; + } + } + + /* Set final sequence entry's next pointer to NULL */ + cur->next = NULL; + + if( *p != end ) + return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +int mbedtls_asn1_get_alg( unsigned char **p, + const unsigned char *end, + mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params ) +{ + int ret; + size_t len; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( ret ); + + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + alg->tag = **p; + end = *p + len; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &alg->len, MBEDTLS_ASN1_OID ) ) != 0 ) + return( ret ); + + alg->p = *p; + *p += alg->len; + + if( *p == end ) + { + mbedtls_platform_zeroize( params, sizeof(mbedtls_asn1_buf) ); + return( 0 ); + } + + params->tag = **p; + (*p)++; + + if( ( ret = mbedtls_asn1_get_len( p, end, ¶ms->len ) ) != 0 ) + return( ret ); + + params->p = *p; + *p += params->len; + + if( *p != end ) + return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +int mbedtls_asn1_get_alg_null( unsigned char **p, + const unsigned char *end, + mbedtls_asn1_buf *alg ) +{ + int ret; + mbedtls_asn1_buf params; + + memset( ¶ms, 0, sizeof(mbedtls_asn1_buf) ); + + if( ( ret = mbedtls_asn1_get_alg( p, end, alg, ¶ms ) ) != 0 ) + return( ret ); + + if( ( params.tag != MBEDTLS_ASN1_NULL && params.tag != 0 ) || params.len != 0 ) + return( MBEDTLS_ERR_ASN1_INVALID_DATA ); + + return( 0 ); +} + +void mbedtls_asn1_free_named_data( mbedtls_asn1_named_data *cur ) +{ + if( cur == NULL ) + return; + + mbedtls_free( cur->oid.p ); + mbedtls_free( cur->val.p ); + + mbedtls_platform_zeroize( cur, sizeof( mbedtls_asn1_named_data ) ); +} + +void mbedtls_asn1_free_named_data_list( mbedtls_asn1_named_data **head ) +{ + mbedtls_asn1_named_data *cur; + + while( ( cur = *head ) != NULL ) + { + *head = cur->next; + mbedtls_asn1_free_named_data( cur ); + mbedtls_free( cur ); + } +} + +mbedtls_asn1_named_data *mbedtls_asn1_find_named_data( mbedtls_asn1_named_data *list, + const char *oid, size_t len ) +{ + while( list != NULL ) + { + if( list->oid.len == len && + memcmp( list->oid.p, oid, len ) == 0 ) + { + break; + } + + list = list->next; + } + + return( list ); +} + +#endif /* MBEDTLS_ASN1_PARSE_C */ diff --git a/src/common/mbedtls/library/mbedtls_asn1write.c b/src/common/mbedtls/library/mbedtls_asn1write.c new file mode 100644 index 0000000000..8d931a8de0 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_asn1write.c @@ -0,0 +1,434 @@ +/* + * ASN.1 buffer writing functionality + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ASN1_WRITE_C) + +#include "mbedtls/asn1write.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +int mbedtls_asn1_write_len( unsigned char **p, unsigned char *start, size_t len ) +{ + if( len < 0x80 ) + { + if( *p - start < 1 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = (unsigned char) len; + return( 1 ); + } + + if( len <= 0xFF ) + { + if( *p - start < 2 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = (unsigned char) len; + *--(*p) = 0x81; + return( 2 ); + } + + if( len <= 0xFFFF ) + { + if( *p - start < 3 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = ( len ) & 0xFF; + *--(*p) = ( len >> 8 ) & 0xFF; + *--(*p) = 0x82; + return( 3 ); + } + + if( len <= 0xFFFFFF ) + { + if( *p - start < 4 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = ( len ) & 0xFF; + *--(*p) = ( len >> 8 ) & 0xFF; + *--(*p) = ( len >> 16 ) & 0xFF; + *--(*p) = 0x83; + return( 4 ); + } + +#if SIZE_MAX > 0xFFFFFFFF + if( len <= 0xFFFFFFFF ) +#endif + { + if( *p - start < 5 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = ( len ) & 0xFF; + *--(*p) = ( len >> 8 ) & 0xFF; + *--(*p) = ( len >> 16 ) & 0xFF; + *--(*p) = ( len >> 24 ) & 0xFF; + *--(*p) = 0x84; + return( 5 ); + } + +#if SIZE_MAX > 0xFFFFFFFF + return( MBEDTLS_ERR_ASN1_INVALID_LENGTH ); +#endif +} + +int mbedtls_asn1_write_tag( unsigned char **p, unsigned char *start, unsigned char tag ) +{ + if( *p - start < 1 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = tag; + + return( 1 ); +} + +int mbedtls_asn1_write_raw_buffer( unsigned char **p, unsigned char *start, + const unsigned char *buf, size_t size ) +{ + size_t len = 0; + + if( *p < start || (size_t)( *p - start ) < size ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + len = size; + (*p) -= len; + memcpy( *p, buf, len ); + + return( (int) len ); +} + +#if defined(MBEDTLS_BIGNUM_C) +int mbedtls_asn1_write_mpi( unsigned char **p, unsigned char *start, const mbedtls_mpi *X ) +{ + int ret; + size_t len = 0; + + // Write the MPI + // + len = mbedtls_mpi_size( X ); + + if( *p < start || (size_t)( *p - start ) < len ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + (*p) -= len; + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( X, *p, len ) ); + + // DER format assumes 2s complement for numbers, so the leftmost bit + // should be 0 for positive numbers and 1 for negative numbers. + // + if( X->s ==1 && **p & 0x80 ) + { + if( *p - start < 1 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = 0x00; + len += 1; + } + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, len ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, MBEDTLS_ASN1_INTEGER ) ); + + ret = (int) len; + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_BIGNUM_C */ + +int mbedtls_asn1_write_null( unsigned char **p, unsigned char *start ) +{ + int ret; + size_t len = 0; + + // Write NULL + // + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, 0) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, MBEDTLS_ASN1_NULL ) ); + + return( (int) len ); +} + +int mbedtls_asn1_write_oid( unsigned char **p, unsigned char *start, + const char *oid, size_t oid_len ) +{ + int ret; + size_t len = 0; + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_raw_buffer( p, start, + (const unsigned char *) oid, oid_len ) ); + MBEDTLS_ASN1_CHK_ADD( len , mbedtls_asn1_write_len( p, start, len ) ); + MBEDTLS_ASN1_CHK_ADD( len , mbedtls_asn1_write_tag( p, start, MBEDTLS_ASN1_OID ) ); + + return( (int) len ); +} + +int mbedtls_asn1_write_algorithm_identifier( unsigned char **p, unsigned char *start, + const char *oid, size_t oid_len, + size_t par_len ) +{ + int ret; + size_t len = 0; + + if( par_len == 0 ) + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_null( p, start ) ); + else + len += par_len; + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_oid( p, start, oid, oid_len ) ); + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, len ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ); + + return( (int) len ); +} + +int mbedtls_asn1_write_bool( unsigned char **p, unsigned char *start, int boolean ) +{ + int ret; + size_t len = 0; + + if( *p - start < 1 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = (boolean) ? 255 : 0; + len++; + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, len ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, MBEDTLS_ASN1_BOOLEAN ) ); + + return( (int) len ); +} + +int mbedtls_asn1_write_int( unsigned char **p, unsigned char *start, int val ) +{ + int ret; + size_t len = 0; + + if( *p - start < 1 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + len += 1; + *--(*p) = val; + + if( val > 0 && **p & 0x80 ) + { + if( *p - start < 1 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + *--(*p) = 0x00; + len += 1; + } + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, len ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, MBEDTLS_ASN1_INTEGER ) ); + + return( (int) len ); +} + +int mbedtls_asn1_write_tagged_string( unsigned char **p, unsigned char *start, int tag, + const char *text, size_t text_len ) +{ + int ret; + size_t len = 0; + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_raw_buffer( p, start, + (const unsigned char *) text, text_len ) ); + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, len ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, tag ) ); + + return( (int) len ); +} + +int mbedtls_asn1_write_utf8_string( unsigned char **p, unsigned char *start, + const char *text, size_t text_len ) +{ + return( mbedtls_asn1_write_tagged_string(p, start, MBEDTLS_ASN1_UTF8_STRING, text, text_len) ); +} + +int mbedtls_asn1_write_printable_string( unsigned char **p, unsigned char *start, + const char *text, size_t text_len ) +{ + return( mbedtls_asn1_write_tagged_string(p, start, MBEDTLS_ASN1_PRINTABLE_STRING, text, text_len) ); +} + +int mbedtls_asn1_write_ia5_string( unsigned char **p, unsigned char *start, + const char *text, size_t text_len ) +{ + return( mbedtls_asn1_write_tagged_string(p, start, MBEDTLS_ASN1_IA5_STRING, text, text_len) ); +} + +int mbedtls_asn1_write_bitstring( unsigned char **p, unsigned char *start, + const unsigned char *buf, size_t bits ) +{ + int ret; + size_t len = 0; + size_t unused_bits, byte_len; + + byte_len = ( bits + 7 ) / 8; + unused_bits = ( byte_len * 8 ) - bits; + + if( *p < start || (size_t)( *p - start ) < byte_len + 1 ) + return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL ); + + len = byte_len + 1; + + /* Write the bitstring. Ensure the unused bits are zeroed */ + if( byte_len > 0 ) + { + byte_len--; + *--( *p ) = buf[byte_len] & ~( ( 0x1 << unused_bits ) - 1 ); + ( *p ) -= byte_len; + memcpy( *p, buf, byte_len ); + } + + /* Write unused bits */ + *--( *p ) = (unsigned char)unused_bits; + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, len ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, MBEDTLS_ASN1_BIT_STRING ) ); + + return( (int) len ); +} + +int mbedtls_asn1_write_octet_string( unsigned char **p, unsigned char *start, + const unsigned char *buf, size_t size ) +{ + int ret; + size_t len = 0; + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_raw_buffer( p, start, buf, size ) ); + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, len ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, MBEDTLS_ASN1_OCTET_STRING ) ); + + return( (int) len ); +} + + +/* This is a copy of the ASN.1 parsing function mbedtls_asn1_find_named_data(), + * which is replicated to avoid a dependency ASN1_WRITE_C on ASN1_PARSE_C. */ +static mbedtls_asn1_named_data *asn1_find_named_data( + mbedtls_asn1_named_data *list, + const char *oid, size_t len ) +{ + while( list != NULL ) + { + if( list->oid.len == len && + memcmp( list->oid.p, oid, len ) == 0 ) + { + break; + } + + list = list->next; + } + + return( list ); +} + +mbedtls_asn1_named_data *mbedtls_asn1_store_named_data( + mbedtls_asn1_named_data **head, + const char *oid, size_t oid_len, + const unsigned char *val, + size_t val_len ) +{ + mbedtls_asn1_named_data *cur; + + if( ( cur = asn1_find_named_data( *head, oid, oid_len ) ) == NULL ) + { + // Add new entry if not present yet based on OID + // + cur = (mbedtls_asn1_named_data*)mbedtls_calloc( 1, + sizeof(mbedtls_asn1_named_data) ); + if( cur == NULL ) + return( NULL ); + + cur->oid.len = oid_len; + cur->oid.p = mbedtls_calloc( 1, oid_len ); + if( cur->oid.p == NULL ) + { + mbedtls_free( cur ); + return( NULL ); + } + + memcpy( cur->oid.p, oid, oid_len ); + + cur->val.len = val_len; + cur->val.p = mbedtls_calloc( 1, val_len ); + if( cur->val.p == NULL ) + { + mbedtls_free( cur->oid.p ); + mbedtls_free( cur ); + return( NULL ); + } + + cur->next = *head; + *head = cur; + } + else if( cur->val.len < val_len ) + { + /* + * Enlarge existing value buffer if needed + * Preserve old data until the allocation succeeded, to leave list in + * a consistent state in case allocation fails. + */ + void *p = mbedtls_calloc( 1, val_len ); + if( p == NULL ) + return( NULL ); + + mbedtls_free( cur->val.p ); + cur->val.p = p; + cur->val.len = val_len; + } + + if( val != NULL ) + memcpy( cur->val.p, val, val_len ); + + return( cur ); +} +#endif /* MBEDTLS_ASN1_WRITE_C */ diff --git a/src/common/mbedtls/library/mbedtls_base64.c b/src/common/mbedtls/library/mbedtls_base64.c new file mode 100644 index 0000000000..294702d2db --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_base64.c @@ -0,0 +1,391 @@ +/* + * RFC 1521 base64 encoding/decoding + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_BASE64_C) + +#include "mbedtls/base64.h" + +#include + +#if defined(MBEDTLS_SELF_TEST) +#ifndef NVRM +#include +#endif +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST */ + +static const unsigned char base64_enc_map[64] = +{ + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', + 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', + 'U', 'V', 'W', 'X', 'Y', 'Z', 'a', 'b', 'c', 'd', + 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', + 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', + 'y', 'z', '0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', '+', '/' +}; + +static const unsigned char base64_dec_map[128] = +{ + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, + 127, 127, 127, 62, 127, 127, 127, 63, 52, 53, + 54, 55, 56, 57, 58, 59, 60, 61, 127, 127, + 127, 64, 127, 127, 127, 0, 1, 2, 3, 4, + 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, + 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 127, 127, 127, 127, 127, 127, 26, 27, 28, + 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 127, 127, 127, 127, 127 +}; + +#define BASE64_SIZE_T_MAX ( (size_t) -1 ) /* SIZE_T_MAX is not standard */ + +/* + * Constant flow conditional assignment to unsigned char + */ +static void mbedtls_base64_cond_assign_uchar( unsigned char * dest, const unsigned char * const src, + unsigned char condition ) +{ + /* MSVC has a warning about unary minus on unsigned integer types, + * but this is well-defined and precisely what we want to do here. */ + + /* Generate bitmask from condition, mask will either be 0xFF or 0 */ + unsigned char mask = ( condition | -condition ); + mask >>= 7; + mask = -mask; + + *dest = ( ( *src ) & mask ) | ( ( *dest ) & ~mask ); +} + +/* + * Constant flow conditional assignment to uint_32 + */ +static void mbedtls_base64_cond_assign_uint32( uint32_t * dest, const uint32_t src, + uint32_t condition ) +{ + /* MSVC has a warning about unary minus on unsigned integer types, + * but this is well-defined and precisely what we want to do here. */ + + /* Generate bitmask from condition, mask will either be 0xFFFFFFFF or 0 */ + uint32_t mask = ( condition | -condition ); + mask >>= 31; + mask = -mask; + + *dest = ( src & mask ) | ( ( *dest ) & ~mask ); +} + +/* + * Constant flow check for equality + */ +static unsigned char mbedtls_base64_eq( size_t in_a, size_t in_b ) +{ + size_t difference = in_a ^ in_b; + + /* MSVC has a warning about unary minus on unsigned integer types, + * but this is well-defined and precisely what we want to do here. */ + + difference |= -difference; + + /* cope with the varying size of size_t per platform */ + difference >>= ( sizeof( difference ) * 8 - 1 ); + + return (unsigned char) ( 1 ^ difference ); +} + +/* + * Constant flow lookup into table. + */ +static unsigned char mbedtls_base64_table_lookup( const unsigned char * const table, + const size_t table_size, const size_t table_index ) +{ + size_t i; + unsigned char result = 0; + + for( i = 0; i < table_size; ++i ) + { + mbedtls_base64_cond_assign_uchar( &result, &table[i], mbedtls_base64_eq( i, table_index ) ); + } + + return result; +} + +/* + * Encode a buffer into base64 format + */ +int mbedtls_base64_encode( unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen ) +{ + size_t i, n; + int C1, C2, C3; + unsigned char *p; + + if( slen == 0 ) + { + *olen = 0; + return( 0 ); + } + + n = slen / 3 + ( slen % 3 != 0 ); + + if( n > ( BASE64_SIZE_T_MAX - 1 ) / 4 ) + { + *olen = BASE64_SIZE_T_MAX; + return( MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL ); + } + + n *= 4; + + if( ( dlen < n + 1 ) || ( NULL == dst ) ) + { + *olen = n + 1; + return( MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL ); + } + + n = ( slen / 3 ) * 3; + + for( i = 0, p = dst; i < n; i += 3 ) + { + C1 = *src++; + C2 = *src++; + C3 = *src++; + + *p++ = mbedtls_base64_table_lookup( base64_enc_map, sizeof( base64_enc_map ), + ( ( C1 >> 2 ) & 0x3F ) ); + + *p++ = mbedtls_base64_table_lookup( base64_enc_map, sizeof( base64_enc_map ), + ( ( ( ( C1 & 3 ) << 4 ) + ( C2 >> 4 ) ) & 0x3F ) ); + + *p++ = mbedtls_base64_table_lookup( base64_enc_map, sizeof( base64_enc_map ), + ( ( ( ( C2 & 15 ) << 2 ) + ( C3 >> 6 ) ) & 0x3F ) ); + + *p++ = mbedtls_base64_table_lookup( base64_enc_map, sizeof( base64_enc_map ), + ( C3 & 0x3F ) ); + } + + if( i < slen ) + { + C1 = *src++; + C2 = ( ( i + 1 ) < slen ) ? *src++ : 0; + + *p++ = mbedtls_base64_table_lookup( base64_enc_map, sizeof( base64_enc_map ), + ( ( C1 >> 2 ) & 0x3F ) ); + + *p++ = mbedtls_base64_table_lookup( base64_enc_map, sizeof( base64_enc_map ), + ( ( ( ( C1 & 3 ) << 4 ) + ( C2 >> 4 ) ) & 0x3F ) ); + + if( ( i + 1 ) < slen ) + *p++ = mbedtls_base64_table_lookup( base64_enc_map, sizeof( base64_enc_map ), + ( ( ( C2 & 15 ) << 2 ) & 0x3F ) ); + else *p++ = '='; + + *p++ = '='; + } + + *olen = p - dst; + *p = 0; + + return( 0 ); +} + +/* + * Decode a base64-formatted buffer + */ +int mbedtls_base64_decode( unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen ) +{ + size_t i, n; + uint32_t j, x; + unsigned char *p; + unsigned char dec_map_lookup; + + /* First pass: check for validity and get output length */ + for( i = n = j = 0; i < slen; i++ ) + { + /* Skip spaces before checking for EOL */ + x = 0; + while( i < slen && src[i] == ' ' ) + { + ++i; + ++x; + } + + /* Spaces at end of buffer are OK */ + if( i == slen ) + break; + + if( ( slen - i ) >= 2 && + src[i] == '\r' && src[i + 1] == '\n' ) + continue; + + if( src[i] == '\n' ) + continue; + + /* Space inside a line is an error */ + if( x != 0 ) + return( MBEDTLS_ERR_BASE64_INVALID_CHARACTER ); + + if( src[i] == '=' && ++j > 2 ) + return( MBEDTLS_ERR_BASE64_INVALID_CHARACTER ); + + dec_map_lookup = mbedtls_base64_table_lookup( base64_dec_map, sizeof( base64_dec_map ), src[i] ); + + if( src[i] > 127 || dec_map_lookup == 127 ) + return( MBEDTLS_ERR_BASE64_INVALID_CHARACTER ); + + if( dec_map_lookup < 64 && j != 0 ) + return( MBEDTLS_ERR_BASE64_INVALID_CHARACTER ); + + n++; + } + + if( n == 0 ) + { + *olen = 0; + return( 0 ); + } + + /* The following expression is to calculate the following formula without + * risk of integer overflow in n: + * n = ( ( n * 6 ) + 7 ) >> 3; + */ + n = ( 6 * ( n >> 3 ) ) + ( ( 6 * ( n & 0x7 ) + 7 ) >> 3 ); + n -= j; + + if( dst == NULL || dlen < n ) + { + *olen = n; + return( MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL ); + } + + for( j = 3, n = x = 0, p = dst; i > 0; i--, src++ ) + { + if( *src == '\r' || *src == '\n' || *src == ' ' ) + continue; + + dec_map_lookup = mbedtls_base64_table_lookup( base64_dec_map, sizeof( base64_dec_map ), *src ); + + mbedtls_base64_cond_assign_uint32( &j, j - 1, mbedtls_base64_eq( dec_map_lookup, 64 ) ); + x = ( x << 6 ) | ( dec_map_lookup & 0x3F ); + + if( ++n == 4 ) + { + n = 0; + if( j > 0 ) *p++ = (unsigned char)( x >> 16 ); + if( j > 1 ) *p++ = (unsigned char)( x >> 8 ); + if( j > 2 ) *p++ = (unsigned char)( x ); + } + } + + *olen = p - dst; + + return( 0 ); +} + +#if defined(MBEDTLS_SELF_TEST) + +static const unsigned char base64_test_dec[64] = +{ + 0x24, 0x48, 0x6E, 0x56, 0x87, 0x62, 0x5A, 0xBD, + 0xBF, 0x17, 0xD9, 0xA2, 0xC4, 0x17, 0x1A, 0x01, + 0x94, 0xED, 0x8F, 0x1E, 0x11, 0xB3, 0xD7, 0x09, + 0x0C, 0xB6, 0xE9, 0x10, 0x6F, 0x22, 0xEE, 0x13, + 0xCA, 0xB3, 0x07, 0x05, 0x76, 0xC9, 0xFA, 0x31, + 0x6C, 0x08, 0x34, 0xFF, 0x8D, 0xC2, 0x6C, 0x38, + 0x00, 0x43, 0xE9, 0x54, 0x97, 0xAF, 0x50, 0x4B, + 0xD1, 0x41, 0xBA, 0x95, 0x31, 0x5A, 0x0B, 0x97 +}; + +static const unsigned char base64_test_enc[] = + "JEhuVodiWr2/F9mixBcaAZTtjx4Rs9cJDLbpEG8i7hPK" + "swcFdsn6MWwINP+Nwmw4AEPpVJevUEvRQbqVMVoLlw=="; + +/* + * Checkup routine + */ +int mbedtls_base64_self_test( int verbose ) +{ + size_t len; + const unsigned char *src; + unsigned char buffer[128]; + + if( verbose != 0 ) + mbedtls_printf( " Base64 encoding test: " ); + + src = base64_test_dec; + + if( mbedtls_base64_encode( buffer, sizeof( buffer ), &len, src, 64 ) != 0 || + memcmp( base64_test_enc, buffer, 88 ) != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + return( 1 ); + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n Base64 decoding test: " ); + + src = base64_test_enc; + + if( mbedtls_base64_decode( buffer, sizeof( buffer ), &len, src, 88 ) != 0 || + memcmp( base64_test_dec, buffer, 64 ) != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + return( 1 ); + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n\n" ); + + return( 0 ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_BASE64_C */ diff --git a/src/common/mbedtls/library/mbedtls_bignum.c b/src/common/mbedtls/library/mbedtls_bignum.c new file mode 100644 index 0000000000..719dc955e2 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_bignum.c @@ -0,0 +1,3136 @@ +/* + * Multi-precision integer library + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +/* + * The following sources were referenced in the design of this Multi-precision + * Integer library: + * + * [1] Handbook of Applied Cryptography - 1997 + * Menezes, van Oorschot and Vanstone + * + * [2] Multi-Precision Math + * Tom St Denis + * https://github.com/libtom/libtommath/blob/develop/tommath.pdf + * + * [3] GNU Multi-Precision Arithmetic Library + * https://gmplib.org/manual/index.html + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_BIGNUM_C) + +#include "mbedtls/bignum.h" +#include "mbedtls/bn_mul.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#define MPI_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_MPI_BAD_INPUT_DATA ) +#define MPI_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#define ciL (sizeof(mbedtls_mpi_uint)) /* chars in limb */ +#define biL (ciL << 3) /* bits in limb */ +#define biH (ciL << 2) /* half limb size */ + +#define MPI_SIZE_T_MAX ( (size_t) -1 ) /* SIZE_T_MAX is not standard */ + +/* + * Convert between bits/chars and number of limbs + * Divide first in order to avoid potential overflows + */ +#define BITS_TO_LIMBS(i) ( (i) / biL + ( (i) % biL != 0 ) ) +#define CHARS_TO_LIMBS(i) ( (i) / ciL + ( (i) % ciL != 0 ) ) + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_mpi_zeroize( mbedtls_mpi_uint *v, size_t n ) +{ + mbedtls_platform_zeroize( v, ciL * n ); +} + +/* + * Initialize one MPI + */ +void mbedtls_mpi_init( mbedtls_mpi *X ) +{ + MPI_VALIDATE( X != NULL ); + + X->s = 1; + X->n = 0; + X->p = NULL; +} + +/* + * Unallocate one MPI + */ +void mbedtls_mpi_free( mbedtls_mpi *X ) +{ + if( X == NULL ) + return; + + if( X->p != NULL ) + { + mbedtls_mpi_zeroize( X->p, X->n ); + mbedtls_free( X->p ); + } + + X->s = 1; + X->n = 0; + X->p = NULL; +} + +/* + * Enlarge to the specified number of limbs + */ +int mbedtls_mpi_grow( mbedtls_mpi *X, size_t nblimbs ) +{ + mbedtls_mpi_uint *p; + MPI_VALIDATE_RET( X != NULL ); + + if( nblimbs > MBEDTLS_MPI_MAX_LIMBS ) + return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); + + if( X->n < nblimbs ) + { + if( ( p = (mbedtls_mpi_uint*)mbedtls_calloc( nblimbs, ciL ) ) == NULL ) + return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); + + if( X->p != NULL ) + { + memcpy( p, X->p, X->n * ciL ); + mbedtls_mpi_zeroize( X->p, X->n ); + mbedtls_free( X->p ); + } + + X->n = nblimbs; + X->p = p; + } + + return( 0 ); +} + +/* + * Resize down as much as possible, + * while keeping at least the specified number of limbs + */ +int mbedtls_mpi_shrink( mbedtls_mpi *X, size_t nblimbs ) +{ + mbedtls_mpi_uint *p; + size_t i; + MPI_VALIDATE_RET( X != NULL ); + + if( nblimbs > MBEDTLS_MPI_MAX_LIMBS ) + return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); + + /* Actually resize up if there are currently fewer than nblimbs limbs. */ + if( X->n <= nblimbs ) + return( mbedtls_mpi_grow( X, nblimbs ) ); + /* After this point, then X->n > nblimbs and in particular X->n > 0. */ + + for( i = X->n - 1; i > 0; i-- ) + if( X->p[i] != 0 ) + break; + i++; + + if( i < nblimbs ) + i = nblimbs; + + if( ( p = (mbedtls_mpi_uint*)mbedtls_calloc( i, ciL ) ) == NULL ) + return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); + + if( X->p != NULL ) + { + memcpy( p, X->p, i * ciL ); + mbedtls_mpi_zeroize( X->p, X->n ); + mbedtls_free( X->p ); + } + + X->n = i; + X->p = p; + + return( 0 ); +} + +/* + * Copy the contents of Y into X + */ +int mbedtls_mpi_copy( mbedtls_mpi *X, const mbedtls_mpi *Y ) +{ + int ret = 0; + size_t i; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( Y != NULL ); + + if( X == Y ) + return( 0 ); + + if( Y->n == 0 ) + { + mbedtls_mpi_free( X ); + return( 0 ); + } + + for( i = Y->n - 1; i > 0; i-- ) + if( Y->p[i] != 0 ) + break; + i++; + + X->s = Y->s; + + if( X->n < i ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, i ) ); + } + else + { + memset( X->p + i, 0, ( X->n - i ) * ciL ); + } + + memcpy( X->p, Y->p, i * ciL ); + +cleanup: + + return( ret ); +} + +/* + * Swap the contents of X and Y + */ +void mbedtls_mpi_swap( mbedtls_mpi *X, mbedtls_mpi *Y ) +{ + mbedtls_mpi T; + MPI_VALIDATE( X != NULL ); + MPI_VALIDATE( Y != NULL ); + + memcpy( &T, X, sizeof( mbedtls_mpi ) ); + memcpy( X, Y, sizeof( mbedtls_mpi ) ); + memcpy( Y, &T, sizeof( mbedtls_mpi ) ); +} + +/** + * Select between two sign values in constant-time. + * + * This is functionally equivalent to second ? a : b but uses only bit + * operations in order to avoid branches. + * + * \param[in] a The first sign; must be either +1 or -1. + * \param[in] b The second sign; must be either +1 or -1. + * \param[in] second Must be either 1 (return b) or 0 (return a). + * + * \return The selected sign value. + */ +static int mpi_safe_cond_select_sign( int a, int b, unsigned char second ) +{ + /* In order to avoid questions about what we can reasonnably assume about + * the representations of signed integers, move everything to unsigned + * by taking advantage of the fact that a and b are either +1 or -1. */ + unsigned ua = a + 1; + unsigned ub = b + 1; + + /* second was 0 or 1, mask is 0 or 2 as are ua and ub */ + const unsigned mask = second << 1; + + /* select ua or ub */ + unsigned ur = ( ua & ~mask ) | ( ub & mask ); + + /* ur is now 0 or 2, convert back to -1 or +1 */ + return( (int) ur - 1 ); +} + +/* + * Conditionally assign dest = src, without leaking information + * about whether the assignment was made or not. + * dest and src must be arrays of limbs of size n. + * assign must be 0 or 1. + */ +static void mpi_safe_cond_assign( size_t n, + mbedtls_mpi_uint *dest, + const mbedtls_mpi_uint *src, + unsigned char assign ) +{ + size_t i; + + /* MSVC has a warning about unary minus on unsigned integer types, + * but this is well-defined and precisely what we want to do here. */ + + /* all-bits 1 if assign is 1, all-bits 0 if assign is 0 */ + const mbedtls_mpi_uint mask = -assign; + + for( i = 0; i < n; i++ ) + dest[i] = ( src[i] & mask ) | ( dest[i] & ~mask ); +} + +/* + * Conditionally assign X = Y, without leaking information + * about whether the assignment was made or not. + * (Leaking information about the respective sizes of X and Y is ok however.) + */ +int mbedtls_mpi_safe_cond_assign( mbedtls_mpi *X, const mbedtls_mpi *Y, unsigned char assign ) +{ + int ret = 0; + size_t i; + mbedtls_mpi_uint limb_mask; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( Y != NULL ); + + /* MSVC has a warning about unary minus on unsigned integer types, + * but this is well-defined and precisely what we want to do here. */ + + /* make sure assign is 0 or 1 in a time-constant manner */ + assign = (assign | (unsigned char)-assign) >> (sizeof( assign ) * 8 - 1); + /* all-bits 1 if assign is 1, all-bits 0 if assign is 0 */ + limb_mask = -assign; + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, Y->n ) ); + + X->s = mpi_safe_cond_select_sign( X->s, Y->s, assign ); + + mpi_safe_cond_assign( Y->n, X->p, Y->p, assign ); + + for( i = Y->n; i < X->n; i++ ) + X->p[i] &= ~limb_mask; + +cleanup: + return( ret ); +} + +/* + * Conditionally swap X and Y, without leaking information + * about whether the swap was made or not. + * Here it is not ok to simply swap the pointers, which whould lead to + * different memory access patterns when X and Y are used afterwards. + */ +int mbedtls_mpi_safe_cond_swap( mbedtls_mpi *X, mbedtls_mpi *Y, unsigned char swap ) +{ + int ret, s; + size_t i; + mbedtls_mpi_uint limb_mask; + mbedtls_mpi_uint tmp; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( Y != NULL ); + + if( X == Y ) + return( 0 ); + + /* MSVC has a warning about unary minus on unsigned integer types, + * but this is well-defined and precisely what we want to do here. */ + + /* make sure swap is 0 or 1 in a time-constant manner */ + swap = (swap | (unsigned char)-swap) >> (sizeof( swap ) * 8 - 1); + /* all-bits 1 if swap is 1, all-bits 0 if swap is 0 */ + limb_mask = -swap; + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, Y->n ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( Y, X->n ) ); + + s = X->s; + X->s = mpi_safe_cond_select_sign( X->s, Y->s, swap ); + Y->s = mpi_safe_cond_select_sign( Y->s, s, swap ); + + + for( i = 0; i < X->n; i++ ) + { + tmp = X->p[i]; + X->p[i] = ( X->p[i] & ~limb_mask ) | ( Y->p[i] & limb_mask ); + Y->p[i] = ( Y->p[i] & ~limb_mask ) | ( tmp & limb_mask ); + } + +cleanup: + return( ret ); +} + +/* + * Set value from integer + */ +int mbedtls_mpi_lset( mbedtls_mpi *X, mbedtls_mpi_sint z ) +{ + int ret; + MPI_VALIDATE_RET( X != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, 1 ) ); + memset( X->p, 0, X->n * ciL ); + + X->p[0] = ( z < 0 ) ? -z : z; + X->s = ( z < 0 ) ? -1 : 1; + +cleanup: + + return( ret ); +} + +/* + * Get a specific bit + */ +int mbedtls_mpi_get_bit( const mbedtls_mpi *X, size_t pos ) +{ + MPI_VALIDATE_RET( X != NULL ); + + if( X->n * biL <= pos ) + return( 0 ); + + return( ( X->p[pos / biL] >> ( pos % biL ) ) & 0x01 ); +} + +/* Get a specific byte, without range checks. */ +#define GET_BYTE( X, i ) \ + ( ( ( X )->p[( i ) / ciL] >> ( ( ( i ) % ciL ) * 8 ) ) & 0xff ) + +/* + * Set a bit to a specific value of 0 or 1 + */ +int mbedtls_mpi_set_bit( mbedtls_mpi *X, size_t pos, unsigned char val ) +{ + int ret = 0; + size_t off = pos / biL; + size_t idx = pos % biL; + MPI_VALIDATE_RET( X != NULL ); + + if( val != 0 && val != 1 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + if( X->n * biL <= pos ) + { + if( val == 0 ) + return( 0 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, off + 1 ) ); + } + + X->p[off] &= ~( (mbedtls_mpi_uint) 0x01 << idx ); + X->p[off] |= (mbedtls_mpi_uint) val << idx; + +cleanup: + + return( ret ); +} + +/* + * Return the number of less significant zero-bits + */ +size_t mbedtls_mpi_lsb( const mbedtls_mpi *X ) +{ + size_t i, j, count = 0; + MBEDTLS_INTERNAL_VALIDATE_RET( X != NULL, 0 ); + + for( i = 0; i < X->n; i++ ) + for( j = 0; j < biL; j++, count++ ) + if( ( ( X->p[i] >> j ) & 1 ) != 0 ) + return( count ); + + return( 0 ); +} + +/* + * Count leading zero bits in a given integer + */ +static size_t mbedtls_clz( const mbedtls_mpi_uint x ) +{ + size_t j; + mbedtls_mpi_uint mask = (mbedtls_mpi_uint) 1 << (biL - 1); + + for( j = 0; j < biL; j++ ) + { + if( x & mask ) break; + + mask >>= 1; + } + + return j; +} + +/* + * Return the number of bits + */ +size_t mbedtls_mpi_bitlen( const mbedtls_mpi *X ) +{ + size_t i, j; + + if( X->n == 0 ) + return( 0 ); + + for( i = X->n - 1; i > 0; i-- ) + if( X->p[i] != 0 ) + break; + + j = biL - mbedtls_clz( X->p[i] ); + + return( ( i * biL ) + j ); +} + +/* + * Return the total size in bytes + */ +size_t mbedtls_mpi_size( const mbedtls_mpi *X ) +{ + return( ( mbedtls_mpi_bitlen( X ) + 7 ) >> 3 ); +} + +/* + * Convert an ASCII character to digit value + */ +static int mpi_get_digit( mbedtls_mpi_uint *d, int radix, char c ) +{ + *d = 255; + + if( c >= 0x30 && c <= 0x39 ) *d = c - 0x30; + if( c >= 0x41 && c <= 0x46 ) *d = c - 0x37; + if( c >= 0x61 && c <= 0x66 ) *d = c - 0x57; + + if( *d >= (mbedtls_mpi_uint) radix ) + return( MBEDTLS_ERR_MPI_INVALID_CHARACTER ); + + return( 0 ); +} + +/* + * Import from an ASCII string + */ +int mbedtls_mpi_read_string( mbedtls_mpi *X, int radix, const char *s ) +{ + int ret; + size_t i, j, slen, n; + int sign = 1; + mbedtls_mpi_uint d; + mbedtls_mpi T; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( s != NULL ); + + if( radix < 2 || radix > 16 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &T ); + + if( s[0] == '-' ) + { + ++s; + sign = -1; + } + + slen = strlen( s ); + + if( radix == 16 ) + { + if( slen > MPI_SIZE_T_MAX >> 2 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + n = BITS_TO_LIMBS( slen << 2 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, n ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( X, 0 ) ); + + for( i = slen, j = 0; i > 0; i--, j++ ) + { + MBEDTLS_MPI_CHK( mpi_get_digit( &d, radix, s[i - 1] ) ); + X->p[j / ( 2 * ciL )] |= d << ( ( j % ( 2 * ciL ) ) << 2 ); + } + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( X, 0 ) ); + + for( i = 0; i < slen; i++ ) + { + MBEDTLS_MPI_CHK( mpi_get_digit( &d, radix, s[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T, X, radix ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( X, &T, d ) ); + } + } + + if( sign < 0 && mbedtls_mpi_bitlen( X ) != 0 ) + X->s = -1; + +cleanup: + + mbedtls_mpi_free( &T ); + + return( ret ); +} + +/* + * Helper to write the digits high-order first. + */ +static int mpi_write_hlp( mbedtls_mpi *X, int radix, + char **p, const size_t buflen ) +{ + int ret; + mbedtls_mpi_uint r; + size_t length = 0; + char *p_end = *p + buflen; + + do + { + if( length >= buflen ) + { + return( MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL ); + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_int( &r, X, radix ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_div_int( X, NULL, X, radix ) ); + /* + * Write the residue in the current position, as an ASCII character. + */ + if( r < 0xA ) + *(--p_end) = (char)( '0' + r ); + else + *(--p_end) = (char)( 'A' + ( r - 0xA ) ); + + length++; + } while( mbedtls_mpi_cmp_int( X, 0 ) != 0 ); + + memmove( *p, p_end, length ); + *p += length; + +cleanup: + + return( ret ); +} + +/* + * Export into an ASCII string + */ +int mbedtls_mpi_write_string( const mbedtls_mpi *X, int radix, + char *buf, size_t buflen, size_t *olen ) +{ + int ret = 0; + size_t n; + char *p; + mbedtls_mpi T; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( olen != NULL ); + MPI_VALIDATE_RET( buflen == 0 || buf != NULL ); + + if( radix < 2 || radix > 16 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + n = mbedtls_mpi_bitlen( X ); /* Number of bits necessary to present `n`. */ + if( radix >= 4 ) n >>= 1; /* Number of 4-adic digits necessary to present + * `n`. If radix > 4, this might be a strict + * overapproximation of the number of + * radix-adic digits needed to present `n`. */ + if( radix >= 16 ) n >>= 1; /* Number of hexadecimal digits necessary to + * present `n`. */ + + n += 1; /* Terminating null byte */ + n += 1; /* Compensate for the divisions above, which round down `n` + * in case it's not even. */ + n += 1; /* Potential '-'-sign. */ + n += ( n & 1 ); /* Make n even to have enough space for hexadecimal writing, + * which always uses an even number of hex-digits. */ + + if( buflen < n ) + { + *olen = n; + return( MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL ); + } + + p = buf; + mbedtls_mpi_init( &T ); + + if( X->s == -1 ) + { + *p++ = '-'; + buflen--; + } + + if( radix == 16 ) + { + int c; + size_t i, j, k; + + for( i = X->n, k = 0; i > 0; i-- ) + { + for( j = ciL; j > 0; j-- ) + { + c = ( X->p[i - 1] >> ( ( j - 1 ) << 3) ) & 0xFF; + + if( c == 0 && k == 0 && ( i + j ) != 2 ) + continue; + + *(p++) = "0123456789ABCDEF" [c / 16]; + *(p++) = "0123456789ABCDEF" [c % 16]; + k = 1; + } + } + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &T, X ) ); + + if( T.s == -1 ) + T.s = 1; + + MBEDTLS_MPI_CHK( mpi_write_hlp( &T, radix, &p, buflen ) ); + } + + *p++ = '\0'; + *olen = p - buf; + +cleanup: + + mbedtls_mpi_free( &T ); + + return( ret ); +} + +#if defined(MBEDTLS_FS_IO) +/* + * Read X from an opened file + */ +int mbedtls_mpi_read_file( mbedtls_mpi *X, int radix, FILE *fin ) +{ + mbedtls_mpi_uint d; + size_t slen; + char *p; + /* + * Buffer should have space for (short) label and decimal formatted MPI, + * newline characters and '\0' + */ + char s[ MBEDTLS_MPI_RW_BUFFER_SIZE ]; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( fin != NULL ); + + if( radix < 2 || radix > 16 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + memset( s, 0, sizeof( s ) ); + if( fgets( s, sizeof( s ) - 1, fin ) == NULL ) + return( MBEDTLS_ERR_MPI_FILE_IO_ERROR ); + + slen = strlen( s ); + if( slen == sizeof( s ) - 2 ) + return( MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL ); + + if( slen > 0 && s[slen - 1] == '\n' ) { slen--; s[slen] = '\0'; } + if( slen > 0 && s[slen - 1] == '\r' ) { slen--; s[slen] = '\0'; } + + p = s + slen; + while( p-- > s ) + if( mpi_get_digit( &d, radix, *p ) != 0 ) + break; + + return( mbedtls_mpi_read_string( X, radix, p + 1 ) ); +} + +/* + * Write X into an opened file (or stdout if fout == NULL) + */ +int mbedtls_mpi_write_file( const char *p, const mbedtls_mpi *X, int radix, FILE *fout ) +{ + int ret; + size_t n, slen, plen; + /* + * Buffer should have space for (short) label and decimal formatted MPI, + * newline characters and '\0' + */ + char s[ MBEDTLS_MPI_RW_BUFFER_SIZE ]; + MPI_VALIDATE_RET( X != NULL ); + + if( radix < 2 || radix > 16 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + memset( s, 0, sizeof( s ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_string( X, radix, s, sizeof( s ) - 2, &n ) ); + + if( p == NULL ) p = ""; + + plen = strlen( p ); + slen = strlen( s ); + s[slen++] = '\r'; + s[slen++] = '\n'; + + if( fout != NULL ) + { + if( fwrite( p, 1, plen, fout ) != plen || + fwrite( s, 1, slen, fout ) != slen ) + return( MBEDTLS_ERR_MPI_FILE_IO_ERROR ); + } + else + mbedtls_printf( "%s%s", p, s ); + +cleanup: + + return( ret ); +} +#endif /* MBEDTLS_FS_IO */ + + +/* Convert a big-endian byte array aligned to the size of mbedtls_mpi_uint + * into the storage form used by mbedtls_mpi. */ + +static mbedtls_mpi_uint mpi_uint_bigendian_to_host_c( mbedtls_mpi_uint x ) +{ + uint8_t i; + unsigned char *x_ptr; + mbedtls_mpi_uint tmp = 0; + + for( i = 0, x_ptr = (unsigned char*) &x; i < ciL; i++, x_ptr++ ) + { + tmp <<= CHAR_BIT; + tmp |= (mbedtls_mpi_uint) *x_ptr; + } + + return( tmp ); +} + +static mbedtls_mpi_uint mpi_uint_bigendian_to_host( mbedtls_mpi_uint x ) +{ +#if defined(__BYTE_ORDER__) + +/* Nothing to do on bigendian systems. */ +#if ( __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ) + return( x ); +#endif /* __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ */ + +#if ( __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ) + +/* For GCC and Clang, have builtins for byte swapping. */ +#if defined(__GNUC__) && defined(__GNUC_PREREQ) +#if __GNUC_PREREQ(4,3) +#define have_bswap +#endif +#endif + +#if defined(__clang__) && defined(__has_builtin) +#if __has_builtin(__builtin_bswap32) && \ + __has_builtin(__builtin_bswap64) +#define have_bswap +#endif +#endif + +#if defined(have_bswap) + /* The compiler is hopefully able to statically evaluate this! */ + switch( sizeof(mbedtls_mpi_uint) ) + { + case 4: + return( __builtin_bswap32(x) ); + case 8: + return( __builtin_bswap64(x) ); + } +#endif +#endif /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */ +#endif /* __BYTE_ORDER__ */ + + /* Fall back to C-based reordering if we don't know the byte order + * or we couldn't use a compiler-specific builtin. */ + return( mpi_uint_bigendian_to_host_c( x ) ); +} + +static void mpi_bigendian_to_host( mbedtls_mpi_uint * const p, size_t limbs ) +{ + mbedtls_mpi_uint *cur_limb_left; + mbedtls_mpi_uint *cur_limb_right; + if( limbs == 0 ) + return; + + /* + * Traverse limbs and + * - adapt byte-order in each limb + * - swap the limbs themselves. + * For that, simultaneously traverse the limbs from left to right + * and from right to left, as long as the left index is not bigger + * than the right index (it's not a problem if limbs is odd and the + * indices coincide in the last iteration). + */ + for( cur_limb_left = p, cur_limb_right = p + ( limbs - 1 ); + cur_limb_left <= cur_limb_right; + cur_limb_left++, cur_limb_right-- ) + { + mbedtls_mpi_uint tmp; + /* Note that if cur_limb_left == cur_limb_right, + * this code effectively swaps the bytes only once. */ + tmp = mpi_uint_bigendian_to_host( *cur_limb_left ); + *cur_limb_left = mpi_uint_bigendian_to_host( *cur_limb_right ); + *cur_limb_right = tmp; + } +} + +/* + * Import X from unsigned binary data, big endian + */ +int mbedtls_mpi_read_binary( mbedtls_mpi *X, const unsigned char *buf, size_t buflen ) +{ + int ret; + size_t const limbs = CHARS_TO_LIMBS( buflen ); + size_t const overhead = ( limbs * ciL ) - buflen; + unsigned char *Xp; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( buflen == 0 || buf != NULL ); + + /* Ensure that target MPI has exactly the necessary number of limbs */ + if( X->n != limbs ) + { + mbedtls_mpi_free( X ); + mbedtls_mpi_init( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, limbs ) ); + } + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( X, 0 ) ); + + /* Avoid calling `memcpy` with NULL source argument, + * even if buflen is 0. */ + if( buf != NULL ) + { + Xp = (unsigned char*) X->p; + memcpy( Xp + overhead, buf, buflen ); + + mpi_bigendian_to_host( X->p, limbs ); + } + +cleanup: + + return( ret ); +} + +/* + * Export X into unsigned binary data, big endian + */ +int mbedtls_mpi_write_binary( const mbedtls_mpi *X, + unsigned char *buf, size_t buflen ) +{ + size_t stored_bytes; + size_t bytes_to_copy; + unsigned char *p; + size_t i; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( buflen == 0 || buf != NULL ); + + stored_bytes = X->n * ciL; + + if( stored_bytes < buflen ) + { + /* There is enough space in the output buffer. Write initial + * null bytes and record the position at which to start + * writing the significant bytes. In this case, the execution + * trace of this function does not depend on the value of the + * number. */ + bytes_to_copy = stored_bytes; + p = buf + buflen - stored_bytes; + memset( buf, 0, buflen - stored_bytes ); + } + else + { + /* The output buffer is smaller than the allocated size of X. + * However X may fit if its leading bytes are zero. */ + bytes_to_copy = buflen; + p = buf; + for( i = bytes_to_copy; i < stored_bytes; i++ ) + { + if( GET_BYTE( X, i ) != 0 ) + return( MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL ); + } + } + + for( i = 0; i < bytes_to_copy; i++ ) + p[bytes_to_copy - i - 1] = GET_BYTE( X, i ); + + return( 0 ); +} + +/* + * Left-shift: X <<= count + */ +int mbedtls_mpi_shift_l( mbedtls_mpi *X, size_t count ) +{ + int ret; + size_t i, v0, t1; + mbedtls_mpi_uint r0 = 0, r1; + MPI_VALIDATE_RET( X != NULL ); + + v0 = count / (biL ); + t1 = count & (biL - 1); + + i = mbedtls_mpi_bitlen( X ) + count; + + if( X->n * biL < i ) + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, BITS_TO_LIMBS( i ) ) ); + + ret = 0; + + /* + * shift by count / limb_size + */ + if( v0 > 0 ) + { + for( i = X->n; i > v0; i-- ) + X->p[i - 1] = X->p[i - v0 - 1]; + + for( ; i > 0; i-- ) + X->p[i - 1] = 0; + } + + /* + * shift by count % limb_size + */ + if( t1 > 0 ) + { + for( i = v0; i < X->n; i++ ) + { + r1 = X->p[i] >> (biL - t1); + X->p[i] <<= t1; + X->p[i] |= r0; + r0 = r1; + } + } + +cleanup: + + return( ret ); +} + +/* + * Right-shift: X >>= count + */ +int mbedtls_mpi_shift_r( mbedtls_mpi *X, size_t count ) +{ + size_t i, v0, v1; + mbedtls_mpi_uint r0 = 0, r1; + MPI_VALIDATE_RET( X != NULL ); + + v0 = count / biL; + v1 = count & (biL - 1); + + if( v0 > X->n || ( v0 == X->n && v1 > 0 ) ) + return mbedtls_mpi_lset( X, 0 ); + + /* + * shift by count / limb_size + */ + if( v0 > 0 ) + { + for( i = 0; i < X->n - v0; i++ ) + X->p[i] = X->p[i + v0]; + + for( ; i < X->n; i++ ) + X->p[i] = 0; + } + + /* + * shift by count % limb_size + */ + if( v1 > 0 ) + { + for( i = X->n; i > 0; i-- ) + { + r1 = X->p[i - 1] << (biL - v1); + X->p[i - 1] >>= v1; + X->p[i - 1] |= r0; + r0 = r1; + } + } + + return( 0 ); +} + +/* + * Compare unsigned values + */ +int mbedtls_mpi_cmp_abs( const mbedtls_mpi *X, const mbedtls_mpi *Y ) +{ + size_t i, j; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( Y != NULL ); + + for( i = X->n; i > 0; i-- ) + if( X->p[i - 1] != 0 ) + break; + + for( j = Y->n; j > 0; j-- ) + if( Y->p[j - 1] != 0 ) + break; + + if( i == 0 && j == 0 ) + return( 0 ); + + if( i > j ) return( 1 ); + if( j > i ) return( -1 ); + + for( ; i > 0; i-- ) + { + if( X->p[i - 1] > Y->p[i - 1] ) return( 1 ); + if( X->p[i - 1] < Y->p[i - 1] ) return( -1 ); + } + + return( 0 ); +} + +/* + * Compare signed values + */ +int mbedtls_mpi_cmp_mpi( const mbedtls_mpi *X, const mbedtls_mpi *Y ) +{ + size_t i, j; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( Y != NULL ); + + for( i = X->n; i > 0; i-- ) + if( X->p[i - 1] != 0 ) + break; + + for( j = Y->n; j > 0; j-- ) + if( Y->p[j - 1] != 0 ) + break; + + if( i == 0 && j == 0 ) + return( 0 ); + + if( i > j ) return( X->s ); + if( j > i ) return( -Y->s ); + + if( X->s > 0 && Y->s < 0 ) return( 1 ); + if( Y->s > 0 && X->s < 0 ) return( -1 ); + + for( ; i > 0; i-- ) + { + if( X->p[i - 1] > Y->p[i - 1] ) return( X->s ); + if( X->p[i - 1] < Y->p[i - 1] ) return( -X->s ); + } + + return( 0 ); +} + +/** Decide if an integer is less than the other, without branches. + * + * \param x First integer. + * \param y Second integer. + * + * \return 1 if \p x is less than \p y, 0 otherwise + */ +static unsigned ct_lt_mpi_uint( const mbedtls_mpi_uint x, + const mbedtls_mpi_uint y ) +{ + mbedtls_mpi_uint ret; + mbedtls_mpi_uint cond; + + /* + * Check if the most significant bits (MSB) of the operands are different. + */ + cond = ( x ^ y ); + /* + * If the MSB are the same then the difference x-y will be negative (and + * have its MSB set to 1 during conversion to unsigned) if and only if x> ( biL - 1 ); + + return (unsigned) ret; +} + +/* + * Compare signed values in constant time + */ +int mbedtls_mpi_lt_mpi_ct( const mbedtls_mpi *X, const mbedtls_mpi *Y, + unsigned *ret ) +{ + size_t i; + /* The value of any of these variables is either 0 or 1 at all times. */ + unsigned cond, done, X_is_negative, Y_is_negative; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( Y != NULL ); + MPI_VALIDATE_RET( ret != NULL ); + + if( X->n != Y->n ) + return MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + + /* + * Set sign_N to 1 if N >= 0, 0 if N < 0. + * We know that N->s == 1 if N >= 0 and N->s == -1 if N < 0. + */ + X_is_negative = ( X->s & 2 ) >> 1; + Y_is_negative = ( Y->s & 2 ) >> 1; + + /* + * If the signs are different, then the positive operand is the bigger. + * That is if X is negative (X_is_negative == 1), then X < Y is true and it + * is false if X is positive (X_is_negative == 0). + */ + cond = ( X_is_negative ^ Y_is_negative ); + *ret = cond & X_is_negative; + + /* + * This is a constant-time function. We might have the result, but we still + * need to go through the loop. Record if we have the result already. + */ + done = cond; + + for( i = X->n; i > 0; i-- ) + { + /* + * If Y->p[i - 1] < X->p[i - 1] then X < Y is true if and only if both + * X and Y are negative. + * + * Again even if we can make a decision, we just mark the result and + * the fact that we are done and continue looping. + */ + cond = ct_lt_mpi_uint( Y->p[i - 1], X->p[i - 1] ); + *ret |= cond & ( 1 - done ) & X_is_negative; + done |= cond; + + /* + * If X->p[i - 1] < Y->p[i - 1] then X < Y is true if and only if both + * X and Y are positive. + * + * Again even if we can make a decision, we just mark the result and + * the fact that we are done and continue looping. + */ + cond = ct_lt_mpi_uint( X->p[i - 1], Y->p[i - 1] ); + *ret |= cond & ( 1 - done ) & ( 1 - X_is_negative ); + done |= cond; + } + + return( 0 ); +} + +/* + * Compare signed values + */ +int mbedtls_mpi_cmp_int( const mbedtls_mpi *X, mbedtls_mpi_sint z ) +{ + mbedtls_mpi Y; + mbedtls_mpi_uint p[1]; + MPI_VALIDATE_RET( X != NULL ); + + *p = ( z < 0 ) ? -z : z; + Y.s = ( z < 0 ) ? -1 : 1; + Y.n = 1; + Y.p = p; + + return( mbedtls_mpi_cmp_mpi( X, &Y ) ); +} + +/* + * Unsigned addition: X = |A| + |B| (HAC 14.7) + */ +int mbedtls_mpi_add_abs( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) +{ + int ret; + size_t i, j; + mbedtls_mpi_uint *o, *p, c, tmp; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( B != NULL ); + + if( X == B ) + { + const mbedtls_mpi *T = A; A = X; B = T; + } + + if( X != A ) + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( X, A ) ); + + /* + * X should always be positive as a result of unsigned additions. + */ + X->s = 1; + + for( j = B->n; j > 0; j-- ) + if( B->p[j - 1] != 0 ) + break; + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, j ) ); + + o = B->p; p = X->p; c = 0; + + /* + * tmp is used because it might happen that p == o + */ + for( i = 0; i < j; i++, o++, p++ ) + { + tmp= *o; + *p += c; c = ( *p < c ); + *p += tmp; c += ( *p < tmp ); + } + + while( c != 0 ) + { + if( i >= X->n ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, i + 1 ) ); + p = X->p + i; + } + + *p += c; c = ( *p < c ); i++; p++; + } + +cleanup: + + return( ret ); +} + +/** + * Helper for mbedtls_mpi subtraction. + * + * Calculate d - s where d and s have the same size. + * This function operates modulo (2^ciL)^n and returns the carry + * (1 if there was a wraparound, i.e. if `d < s`, and 0 otherwise). + * + * \param n Number of limbs of \p d and \p s. + * \param[in,out] d On input, the left operand. + * On output, the result of the subtraction: + * \param[in] s The right operand. + * + * \return 1 if `d < s`. + * 0 if `d >= s`. + */ +static mbedtls_mpi_uint mpi_sub_hlp( size_t n, + mbedtls_mpi_uint *d, + const mbedtls_mpi_uint *s ) +{ + size_t i; + mbedtls_mpi_uint c, z; + + for( i = c = 0; i < n; i++, s++, d++ ) + { + z = ( *d < c ); *d -= c; + c = ( *d < *s ) + z; *d -= *s; + } + + return( c ); +} + +/* + * Unsigned subtraction: X = |A| - |B| (HAC 14.9, 14.10) + */ +int mbedtls_mpi_sub_abs( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) +{ + mbedtls_mpi TB; + int ret; + size_t n; + mbedtls_mpi_uint carry; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( B != NULL ); + + mbedtls_mpi_init( &TB ); + + if( X == B ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TB, B ) ); + B = &TB; + } + + if( X != A ) + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( X, A ) ); + + /* + * X should always be positive as a result of unsigned subtractions. + */ + X->s = 1; + + ret = 0; + + for( n = B->n; n > 0; n-- ) + if( B->p[n - 1] != 0 ) + break; + if( n > A->n ) + { + /* B >= (2^ciL)^n > A */ + ret = MBEDTLS_ERR_MPI_NEGATIVE_VALUE; + goto cleanup; + } + + carry = mpi_sub_hlp( n, X->p, B->p ); + if( carry != 0 ) + { + /* Propagate the carry to the first nonzero limb of X. */ + for( ; n < X->n && X->p[n] == 0; n++ ) + --X->p[n]; + /* If we ran out of space for the carry, it means that the result + * is negative. */ + if( n == X->n ) + { + ret = MBEDTLS_ERR_MPI_NEGATIVE_VALUE; + goto cleanup; + } + --X->p[n]; + } + +cleanup: + + mbedtls_mpi_free( &TB ); + + return( ret ); +} + +/* + * Signed addition: X = A + B + */ +int mbedtls_mpi_add_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) +{ + int ret, s; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( B != NULL ); + + s = A->s; + if( A->s * B->s < 0 ) + { + if( mbedtls_mpi_cmp_abs( A, B ) >= 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( X, A, B ) ); + X->s = s; + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( X, B, A ) ); + X->s = -s; + } + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( X, A, B ) ); + X->s = s; + } + +cleanup: + + return( ret ); +} + +/* + * Signed subtraction: X = A - B + */ +int mbedtls_mpi_sub_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) +{ + int ret, s; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( B != NULL ); + + s = A->s; + if( A->s * B->s > 0 ) + { + if( mbedtls_mpi_cmp_abs( A, B ) >= 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( X, A, B ) ); + X->s = s; + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( X, B, A ) ); + X->s = -s; + } + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( X, A, B ) ); + X->s = s; + } + +cleanup: + + return( ret ); +} + +/* + * Signed addition: X = A + b + */ +int mbedtls_mpi_add_int( mbedtls_mpi *X, const mbedtls_mpi *A, mbedtls_mpi_sint b ) +{ + mbedtls_mpi _B; + mbedtls_mpi_uint p[1]; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + + p[0] = ( b < 0 ) ? -b : b; + _B.s = ( b < 0 ) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return( mbedtls_mpi_add_mpi( X, A, &_B ) ); +} + +/* + * Signed subtraction: X = A - b + */ +int mbedtls_mpi_sub_int( mbedtls_mpi *X, const mbedtls_mpi *A, mbedtls_mpi_sint b ) +{ + mbedtls_mpi _B; + mbedtls_mpi_uint p[1]; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + + p[0] = ( b < 0 ) ? -b : b; + _B.s = ( b < 0 ) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return( mbedtls_mpi_sub_mpi( X, A, &_B ) ); +} + +/* + * Helper for mbedtls_mpi multiplication + */ +static +#if defined(__APPLE__) && defined(__arm__) +/* + * Apple LLVM version 4.2 (clang-425.0.24) (based on LLVM 3.2svn) + * appears to need this to prevent bad ARM code generation at -O3. + */ +__attribute__ ((noinline)) +#endif +void mpi_mul_hlp( size_t i, mbedtls_mpi_uint *s, mbedtls_mpi_uint *d, mbedtls_mpi_uint b ) +{ + mbedtls_mpi_uint c = 0, t = 0; + +#if defined(MULADDC_HUIT) + for( ; i >= 8; i -= 8 ) + { + MULADDC_INIT + MULADDC_HUIT + MULADDC_STOP + } + + for( ; i > 0; i-- ) + { + MULADDC_INIT + MULADDC_CORE + MULADDC_STOP + } +#else /* MULADDC_HUIT */ + for( ; i >= 16; i -= 16 ) + { + MULADDC_INIT + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_STOP + } + + for( ; i >= 8; i -= 8 ) + { + MULADDC_INIT + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_STOP + } + + for( ; i > 0; i-- ) + { + MULADDC_INIT + MULADDC_CORE + MULADDC_STOP + } +#endif /* MULADDC_HUIT */ + + t++; + + do { + *d += c; c = ( *d < c ); d++; + } + while( c != 0 ); +} + +/* + * Baseline multiplication: X = A * B (HAC 14.12) + */ +int mbedtls_mpi_mul_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) +{ + int ret; + size_t i, j; + mbedtls_mpi TA, TB; + int result_is_zero = 0; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( B != NULL ); + + mbedtls_mpi_init( &TA ); mbedtls_mpi_init( &TB ); + + if( X == A ) { MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TA, A ) ); A = &TA; } + if( X == B ) { MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TB, B ) ); B = &TB; } + + for( i = A->n; i > 0; i-- ) + if( A->p[i - 1] != 0 ) + break; + if( i == 0 ) + result_is_zero = 1; + + for( j = B->n; j > 0; j-- ) + if( B->p[j - 1] != 0 ) + break; + if( j == 0 ) + result_is_zero = 1; + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, i + j ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( X, 0 ) ); + + for( ; j > 0; j-- ) + mpi_mul_hlp( i, A->p, X->p + j - 1, B->p[j - 1] ); + + /* If the result is 0, we don't shortcut the operation, which reduces + * but does not eliminate side channels leaking the zero-ness. We do + * need to take care to set the sign bit properly since the library does + * not fully support an MPI object with a value of 0 and s == -1. */ + if( result_is_zero ) + X->s = 1; + else + X->s = A->s * B->s; + +cleanup: + + mbedtls_mpi_free( &TB ); mbedtls_mpi_free( &TA ); + + return( ret ); +} + +/* + * Baseline multiplication: X = A * b + */ +int mbedtls_mpi_mul_int( mbedtls_mpi *X, const mbedtls_mpi *A, mbedtls_mpi_uint b ) +{ + mbedtls_mpi _B; + mbedtls_mpi_uint p[1]; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + + _B.s = 1; + _B.n = 1; + _B.p = p; + p[0] = b; + + return( mbedtls_mpi_mul_mpi( X, A, &_B ) ); +} + +/* + * Unsigned integer divide - double mbedtls_mpi_uint dividend, u1/u0, and + * mbedtls_mpi_uint divisor, d + */ +static mbedtls_mpi_uint mbedtls_int_div_int( mbedtls_mpi_uint u1, + mbedtls_mpi_uint u0, mbedtls_mpi_uint d, mbedtls_mpi_uint *r ) +{ +#if defined(MBEDTLS_HAVE_UDBL) + mbedtls_t_udbl dividend, quotient; +#else + const mbedtls_mpi_uint radix = (mbedtls_mpi_uint) 1 << biH; + const mbedtls_mpi_uint uint_halfword_mask = ( (mbedtls_mpi_uint) 1 << biH ) - 1; + mbedtls_mpi_uint d0, d1, q0, q1, rAX, r0, quotient; + mbedtls_mpi_uint u0_msw, u0_lsw; + size_t s; +#endif + + /* + * Check for overflow + */ + if( 0 == d || u1 >= d ) + { + if (r != NULL) *r = ~0; + + return ( ~0 ); + } + +#if defined(MBEDTLS_HAVE_UDBL) + dividend = (mbedtls_t_udbl) u1 << biL; + dividend |= (mbedtls_t_udbl) u0; + quotient = dividend / d; + if( quotient > ( (mbedtls_t_udbl) 1 << biL ) - 1 ) + quotient = ( (mbedtls_t_udbl) 1 << biL ) - 1; + + if( r != NULL ) + *r = (mbedtls_mpi_uint)( dividend - (quotient * d ) ); + + return (mbedtls_mpi_uint) quotient; +#else + + /* + * Algorithm D, Section 4.3.1 - The Art of Computer Programming + * Vol. 2 - Seminumerical Algorithms, Knuth + */ + + /* + * Normalize the divisor, d, and dividend, u0, u1 + */ + s = mbedtls_clz( d ); + d = d << s; + + u1 = u1 << s; + u1 |= ( u0 >> ( biL - s ) ) & ( -(mbedtls_mpi_sint)s >> ( biL - 1 ) ); + u0 = u0 << s; + + d1 = d >> biH; + d0 = d & uint_halfword_mask; + + u0_msw = u0 >> biH; + u0_lsw = u0 & uint_halfword_mask; + + /* + * Find the first quotient and remainder + */ + q1 = u1 / d1; + r0 = u1 - d1 * q1; + + while( q1 >= radix || ( q1 * d0 > radix * r0 + u0_msw ) ) + { + q1 -= 1; + r0 += d1; + + if ( r0 >= radix ) break; + } + + rAX = ( u1 * radix ) + ( u0_msw - q1 * d ); + q0 = rAX / d1; + r0 = rAX - q0 * d1; + + while( q0 >= radix || ( q0 * d0 > radix * r0 + u0_lsw ) ) + { + q0 -= 1; + r0 += d1; + + if ( r0 >= radix ) break; + } + + if (r != NULL) + *r = ( rAX * radix + u0_lsw - q0 * d ) >> s; + + quotient = q1 * radix + q0; + + return quotient; +#endif +} + +/* + * Division by mbedtls_mpi: A = Q * B + R (HAC 14.20) + */ +int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, + const mbedtls_mpi *B ) +{ + int ret; + size_t i, n, t, k; + mbedtls_mpi X, Y, Z, T1, T2; + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( B != NULL ); + + if( mbedtls_mpi_cmp_int( B, 0 ) == 0 ) + return( MBEDTLS_ERR_MPI_DIVISION_BY_ZERO ); + + mbedtls_mpi_init( &X ); mbedtls_mpi_init( &Y ); mbedtls_mpi_init( &Z ); + mbedtls_mpi_init( &T1 ); mbedtls_mpi_init( &T2 ); + + if( mbedtls_mpi_cmp_abs( A, B ) < 0 ) + { + if( Q != NULL ) MBEDTLS_MPI_CHK( mbedtls_mpi_lset( Q, 0 ) ); + if( R != NULL ) MBEDTLS_MPI_CHK( mbedtls_mpi_copy( R, A ) ); + return( 0 ); + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &X, A ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Y, B ) ); + X.s = Y.s = 1; + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &Z, A->n + 2 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &Z, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &T1, 2 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &T2, 3 ) ); + + k = mbedtls_mpi_bitlen( &Y ) % biL; + if( k < biL - 1 ) + { + k = biL - 1 - k; + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &X, k ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &Y, k ) ); + } + else k = 0; + + n = X.n - 1; + t = Y.n - 1; + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &Y, biL * ( n - t ) ) ); + + while( mbedtls_mpi_cmp_mpi( &X, &Y ) >= 0 ) + { + Z.p[n - t]++; + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &Y ) ); + } + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &Y, biL * ( n - t ) ) ); + + for( i = n; i > t ; i-- ) + { + if( X.p[i] >= Y.p[t] ) + Z.p[i - t - 1] = ~0; + else + { + Z.p[i - t - 1] = mbedtls_int_div_int( X.p[i], X.p[i - 1], + Y.p[t], NULL); + } + + Z.p[i - t - 1]++; + do + { + Z.p[i - t - 1]--; + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &T1, 0 ) ); + T1.p[0] = ( t < 1 ) ? 0 : Y.p[t - 1]; + T1.p[1] = Y.p[t]; + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T1, &T1, Z.p[i - t - 1] ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &T2, 0 ) ); + T2.p[0] = ( i < 2 ) ? 0 : X.p[i - 2]; + T2.p[1] = ( i < 1 ) ? 0 : X.p[i - 1]; + T2.p[2] = X.p[i]; + } + while( mbedtls_mpi_cmp_mpi( &T1, &T2 ) > 0 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T1, &Y, Z.p[i - t - 1] ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &T1 ) ); + + if( mbedtls_mpi_cmp_int( &X, 0 ) < 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &T1, &Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &X, &X, &T1 ) ); + Z.p[i - t - 1]--; + } + } + + if( Q != NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( Q, &Z ) ); + Q->s = A->s * B->s; + } + + if( R != NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &X, k ) ); + X.s = A->s; + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( R, &X ) ); + + if( mbedtls_mpi_cmp_int( R, 0 ) == 0 ) + R->s = 1; + } + +cleanup: + + mbedtls_mpi_free( &X ); mbedtls_mpi_free( &Y ); mbedtls_mpi_free( &Z ); + mbedtls_mpi_free( &T1 ); mbedtls_mpi_free( &T2 ); + + return( ret ); +} + +/* + * Division by int: A = Q * b + R + */ +int mbedtls_mpi_div_int( mbedtls_mpi *Q, mbedtls_mpi *R, + const mbedtls_mpi *A, + mbedtls_mpi_sint b ) +{ + mbedtls_mpi _B; + mbedtls_mpi_uint p[1]; + MPI_VALIDATE_RET( A != NULL ); + + p[0] = ( b < 0 ) ? -b : b; + _B.s = ( b < 0 ) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return( mbedtls_mpi_div_mpi( Q, R, A, &_B ) ); +} + +/* + * Modulo: R = A mod B + */ +int mbedtls_mpi_mod_mpi( mbedtls_mpi *R, const mbedtls_mpi *A, const mbedtls_mpi *B ) +{ + int ret; + MPI_VALIDATE_RET( R != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( B != NULL ); + + if( mbedtls_mpi_cmp_int( B, 0 ) < 0 ) + return( MBEDTLS_ERR_MPI_NEGATIVE_VALUE ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_div_mpi( NULL, R, A, B ) ); + + while( mbedtls_mpi_cmp_int( R, 0 ) < 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( R, R, B ) ); + + while( mbedtls_mpi_cmp_mpi( R, B ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( R, R, B ) ); + +cleanup: + + return( ret ); +} + +/* + * Modulo: r = A mod b + */ +int mbedtls_mpi_mod_int( mbedtls_mpi_uint *r, const mbedtls_mpi *A, mbedtls_mpi_sint b ) +{ + size_t i; + mbedtls_mpi_uint x, y, z; + MPI_VALIDATE_RET( r != NULL ); + MPI_VALIDATE_RET( A != NULL ); + + if( b == 0 ) + return( MBEDTLS_ERR_MPI_DIVISION_BY_ZERO ); + + if( b < 0 ) + return( MBEDTLS_ERR_MPI_NEGATIVE_VALUE ); + + /* + * handle trivial cases + */ + if( b == 1 ) + { + *r = 0; + return( 0 ); + } + + if( b == 2 ) + { + *r = A->p[0] & 1; + return( 0 ); + } + + /* + * general case + */ + for( i = A->n, y = 0; i > 0; i-- ) + { + x = A->p[i - 1]; + y = ( y << biH ) | ( x >> biH ); + z = y / b; + y -= z * b; + + x <<= biH; + y = ( y << biH ) | ( x >> biH ); + z = y / b; + y -= z * b; + } + + /* + * If A is negative, then the current y represents a negative value. + * Flipping it to the positive side. + */ + if( A->s < 0 && y != 0 ) + y = b - y; + + *r = y; + + return( 0 ); +} + +/* + * Fast Montgomery initialization (thanks to Tom St Denis) + */ +static void mpi_montg_init( mbedtls_mpi_uint *mm, const mbedtls_mpi *N ) +{ + mbedtls_mpi_uint x, m0 = N->p[0]; + unsigned int i; + + x = m0; + x += ( ( m0 + 2 ) & 4 ) << 1; + + for( i = biL; i >= 8; i /= 2 ) + x *= ( 2 - ( m0 * x ) ); + + *mm = ~x + 1; +} + +/** Montgomery multiplication: A = A * B * R^-1 mod N (HAC 14.36) + * + * \param[in,out] A One of the numbers to multiply. + * It must have at least as many limbs as N + * (A->n >= N->n), and any limbs beyond n are ignored. + * On successful completion, A contains the result of + * the multiplication A * B * R^-1 mod N where + * R = (2^ciL)^n. + * \param[in] B One of the numbers to multiply. + * It must be nonzero and must not have more limbs than N + * (B->n <= N->n). + * \param[in] N The modulo. N must be odd. + * \param mm The value calculated by `mpi_montg_init(&mm, N)`. + * This is -N^-1 mod 2^ciL. + * \param[in,out] T A bignum for temporary storage. + * It must be at least twice the limb size of N plus 2 + * (T->n >= 2 * (N->n + 1)). + * Its initial content is unused and + * its final content is indeterminate. + * Note that unlike the usual convention in the library + * for `const mbedtls_mpi*`, the content of T can change. + */ +static void mpi_montmul( mbedtls_mpi *A, const mbedtls_mpi *B, const mbedtls_mpi *N, mbedtls_mpi_uint mm, + const mbedtls_mpi *T ) +{ + size_t i, n, m; + mbedtls_mpi_uint u0, u1, *d; + + memset( T->p, 0, T->n * ciL ); + + d = T->p; + n = N->n; + m = ( B->n < n ) ? B->n : n; + + for( i = 0; i < n; i++ ) + { + /* + * T = (T + u0*B + u1*N) / 2^biL + */ + u0 = A->p[i]; + u1 = ( d[0] + u0 * B->p[0] ) * mm; + + mpi_mul_hlp( m, B->p, d, u0 ); + mpi_mul_hlp( n, N->p, d, u1 ); + + *d++ = u0; d[n + 1] = 0; + } + + /* At this point, d is either the desired result or the desired result + * plus N. We now potentially subtract N, avoiding leaking whether the + * subtraction is performed through side channels. */ + + /* Copy the n least significant limbs of d to A, so that + * A = d if d < N (recall that N has n limbs). */ + memcpy( A->p, d, n * ciL ); + /* If d >= N then we want to set A to d - N. To prevent timing attacks, + * do the calculation without using conditional tests. */ + /* Set d to d0 + (2^biL)^n - N where d0 is the current value of d. */ + d[n] += 1; + d[n] -= mpi_sub_hlp( n, d, N->p ); + /* If d0 < N then d < (2^biL)^n + * so d[n] == 0 and we want to keep A as it is. + * If d0 >= N then d >= (2^biL)^n, and d <= (2^biL)^n + N < 2 * (2^biL)^n + * so d[n] == 1 and we want to set A to the result of the subtraction + * which is d - (2^biL)^n, i.e. the n least significant limbs of d. + * This exactly corresponds to a conditional assignment. */ + mpi_safe_cond_assign( n, A->p, d, (unsigned char) d[n] ); +} + +/* + * Montgomery reduction: A = A * R^-1 mod N + * + * See mpi_montmul() regarding constraints and guarantees on the parameters. + */ +static void mpi_montred( mbedtls_mpi *A, const mbedtls_mpi *N, + mbedtls_mpi_uint mm, const mbedtls_mpi *T ) +{ + mbedtls_mpi_uint z = 1; + mbedtls_mpi U; + + U.n = U.s = (int) z; + U.p = &z; + + mpi_montmul( A, &U, N, mm, T ); +} + +/* + * Constant-flow boolean "equal" comparison: + * return x == y + * + * This function can be used to write constant-time code by replacing branches + * with bit operations - it can be used in conjunction with + * mbedtls_ssl_cf_mask_from_bit(). + * + * This function is implemented without using comparison operators, as those + * might be translated to branches by some compilers on some platforms. + */ +static size_t mbedtls_mpi_cf_bool_eq( size_t x, size_t y ) +{ + /* diff = 0 if x == y, non-zero otherwise */ + const size_t diff = x ^ y; + + /* MSVC has a warning about unary minus on unsigned integer types, + * but this is well-defined and precisely what we want to do here. */ + + /* diff_msb's most significant bit is equal to x != y */ + const size_t diff_msb = ( diff | (size_t) -diff ); + + /* diff1 = (x != y) ? 1 : 0 */ + const size_t diff1 = diff_msb >> ( sizeof( diff_msb ) * 8 - 1 ); + + return( 1 ^ diff1 ); +} + +/** + * Select an MPI from a table without leaking the index. + * + * This is functionally equivalent to mbedtls_mpi_copy(R, T[idx]) except it + * reads the entire table in order to avoid leaking the value of idx to an + * attacker able to observe memory access patterns. + * + * \param[out] R Where to write the selected MPI. + * \param[in] T The table to read from. + * \param[in] T_size The number of elements in the table. + * \param[in] idx The index of the element to select; + * this must satisfy 0 <= idx < T_size. + * + * \return \c 0 on success, or a negative error code. + */ +static int mpi_select( mbedtls_mpi *R, const mbedtls_mpi *T, size_t T_size, size_t idx ) +{ + int ret = MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + size_t i; + + for( i = 0; i < T_size; i++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( R, &T[i], + (unsigned char) mbedtls_mpi_cf_bool_eq( i, idx ) ) ); + } + +cleanup: + return( ret ); +} + +/* + * Sliding-window exponentiation: X = A^E mod N (HAC 14.85) + */ +int mbedtls_mpi_exp_mod( mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *E, const mbedtls_mpi *N, + mbedtls_mpi *_RR ) +{ + int ret; + size_t wbits, wsize, one = 1; + size_t i, j, nblimbs; + size_t bufsize, nbits; + mbedtls_mpi_uint ei, mm, state; + mbedtls_mpi RR, T, W[ 1 << MBEDTLS_MPI_WINDOW_SIZE ], WW, Apos; + int neg; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( E != NULL ); + MPI_VALIDATE_RET( N != NULL ); + + if( mbedtls_mpi_cmp_int( N, 0 ) <= 0 || ( N->p[0] & 1 ) == 0 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + if( mbedtls_mpi_cmp_int( E, 0 ) < 0 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + if( mbedtls_mpi_bitlen( E ) > MBEDTLS_MPI_MAX_BITS || + mbedtls_mpi_bitlen( N ) > MBEDTLS_MPI_MAX_BITS ) + return ( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + /* + * Init temps and window size + */ + mpi_montg_init( &mm, N ); + mbedtls_mpi_init( &RR ); mbedtls_mpi_init( &T ); + mbedtls_mpi_init( &Apos ); + mbedtls_mpi_init( &WW ); + memset( W, 0, sizeof( W ) ); + + i = mbedtls_mpi_bitlen( E ); + + wsize = ( i > 671 ) ? 6 : ( i > 239 ) ? 5 : + ( i > 79 ) ? 4 : ( i > 23 ) ? 3 : 1; + +#if( MBEDTLS_MPI_WINDOW_SIZE < 6 ) + if( wsize > MBEDTLS_MPI_WINDOW_SIZE ) + wsize = MBEDTLS_MPI_WINDOW_SIZE; +#endif + + j = N->n + 1; + /* All W[i] and X must have at least N->n limbs for the mpi_montmul() + * and mpi_montred() calls later. Here we ensure that W[1] and X are + * large enough, and later we'll grow other W[i] to the same length. + * They must not be shrunk midway through this function! + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, j ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[1], j ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &T, j * 2 ) ); + + /* + * Compensate for negative A (and correct at the end) + */ + neg = ( A->s == -1 ); + if( neg ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Apos, A ) ); + Apos.s = 1; + A = &Apos; + } + + /* + * If 1st call, pre-compute R^2 mod N + */ + if( _RR == NULL || _RR->p == NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &RR, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &RR, N->n * 2 * biL ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &RR, &RR, N ) ); + + if( _RR != NULL ) + memcpy( _RR, &RR, sizeof( mbedtls_mpi ) ); + } + else + memcpy( &RR, _RR, sizeof( mbedtls_mpi ) ); + + /* + * W[1] = A * R^2 * R^-1 mod N = A * R mod N + */ + if( mbedtls_mpi_cmp_mpi( A, N ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &W[1], A, N ) ); + else + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[1], A ) ); + /* Re-grow W[1] if necessary. This should be only necessary in one corner + * case: when A == 0 represented with A.n == 0, mbedtls_mpi_copy shrinks + * W[1] to 0 limbs. */ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[1], N->n +1 ) ); + + mpi_montmul( &W[1], &RR, N, mm, &T ); + + /* + * X = R^2 * R^-1 mod N = R mod N + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( X, &RR ) ); + mpi_montred( X, N, mm, &T ); + + if( wsize > 1 ) + { + /* + * W[1 << (wsize - 1)] = W[1] ^ (wsize - 1) + */ + j = one << ( wsize - 1 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[j], N->n + 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[j], &W[1] ) ); + + for( i = 0; i < wsize - 1; i++ ) + mpi_montmul( &W[j], &W[j], N, mm, &T ); + + /* + * W[i] = W[i - 1] * W[1] + */ + for( i = j + 1; i < ( one << wsize ); i++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[i], N->n + 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[i], &W[i - 1] ) ); + + mpi_montmul( &W[i], &W[1], N, mm, &T ); + } + } + + nblimbs = E->n; + bufsize = 0; + nbits = 0; + wbits = 0; + state = 0; + + while( 1 ) + { + if( bufsize == 0 ) + { + if( nblimbs == 0 ) + break; + + nblimbs--; + + bufsize = sizeof( mbedtls_mpi_uint ) << 3; + } + + bufsize--; + + ei = (E->p[nblimbs] >> bufsize) & 1; + + /* + * skip leading 0s + */ + if( ei == 0 && state == 0 ) + continue; + + if( ei == 0 && state == 1 ) + { + /* + * out of window, square X + */ + mpi_montmul( X, X, N, mm, &T ); + continue; + } + + /* + * add ei to current window + */ + state = 2; + + nbits++; + wbits |= ( ei << ( wsize - nbits ) ); + + if( nbits == wsize ) + { + /* + * X = X^wsize R^-1 mod N + */ + for( i = 0; i < wsize; i++ ) + mpi_montmul( X, X, N, mm, &T ); + + /* + * X = X * W[wbits] R^-1 mod N + */ + MBEDTLS_MPI_CHK( mpi_select( &WW, W, (size_t) 1 << wsize, wbits ) ); + mpi_montmul( X, &WW, N, mm, &T ); + + state--; + nbits = 0; + wbits = 0; + } + } + + /* + * process the remaining bits + */ + for( i = 0; i < nbits; i++ ) + { + mpi_montmul( X, X, N, mm, &T ); + + wbits <<= 1; + + if( ( wbits & ( one << wsize ) ) != 0 ) + mpi_montmul( X, &W[1], N, mm, &T ); + } + + /* + * X = A^E * R * R^-1 mod N = A^E mod N + */ + mpi_montred( X, N, mm, &T ); + + if( neg && E->n != 0 && ( E->p[0] & 1 ) != 0 ) + { + X->s = -1; + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( X, N, X ) ); + } + +cleanup: + + for( i = ( one << ( wsize - 1 ) ); i < ( one << wsize ); i++ ) + mbedtls_mpi_free( &W[i] ); + + mbedtls_mpi_free( &W[1] ); mbedtls_mpi_free( &T ); mbedtls_mpi_free( &Apos ); + mbedtls_mpi_free( &WW ); + + if( _RR == NULL || _RR->p == NULL ) + mbedtls_mpi_free( &RR ); + + return( ret ); +} + +/* + * Greatest common divisor: G = gcd(A, B) (HAC 14.54) + */ +int mbedtls_mpi_gcd( mbedtls_mpi *G, const mbedtls_mpi *A, const mbedtls_mpi *B ) +{ + int ret; + size_t lz, lzt; + mbedtls_mpi TG, TA, TB; + + MPI_VALIDATE_RET( G != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( B != NULL ); + + mbedtls_mpi_init( &TG ); mbedtls_mpi_init( &TA ); mbedtls_mpi_init( &TB ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TA, A ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TB, B ) ); + + lz = mbedtls_mpi_lsb( &TA ); + lzt = mbedtls_mpi_lsb( &TB ); + + /* The loop below gives the correct result when A==0 but not when B==0. + * So have a special case for B==0. Leverage the fact that we just + * calculated the lsb and lsb(B)==0 iff B is odd or 0 to make the test + * slightly more efficient than cmp_int(). */ + if( lzt == 0 && mbedtls_mpi_get_bit( &TB, 0 ) == 0 ) + { + ret = mbedtls_mpi_copy( G, A ); + goto cleanup; + } + + if( lzt < lz ) + lz = lzt; + + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &TA, lz ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &TB, lz ) ); + + TA.s = TB.s = 1; + + /* We mostly follow the procedure described in HAC 14.54, but with some + * minor differences: + * - Sequences of multiplications or divisions by 2 are grouped into a + * single shift operation. + * - The procedure in HAC assumes that 0 < TB <= TA. + * - The condition TB <= TA is not actually necessary for correctness. + * TA and TB have symmetric roles except for the loop termination + * condition, and the shifts at the beginning of the loop body + * remove any significance from the ordering of TA vs TB before + * the shifts. + * - If TA = 0, the loop goes through 0 iterations and the result is + * correctly TB. + * - The case TB = 0 was short-circuited above. + * + * For the correctness proof below, decompose the original values of + * A and B as + * A = sa * 2^a * A' with A'=0 or A' odd, and sa = +-1 + * B = sb * 2^b * B' with B'=0 or B' odd, and sb = +-1 + * Then gcd(A, B) = 2^{min(a,b)} * gcd(A',B'), + * and gcd(A',B') is odd or 0. + * + * At the beginning, we have TA = |A|/2^a and TB = |B|/2^b. + * The code maintains the following invariant: + * gcd(A,B) = 2^k * gcd(TA,TB) for some k (I) + */ + + /* Proof that the loop terminates: + * At each iteration, either the right-shift by 1 is made on a nonzero + * value and the nonnegative integer bitlen(TA) + bitlen(TB) decreases + * by at least 1, or the right-shift by 1 is made on zero and then + * TA becomes 0 which ends the loop (TB cannot be 0 if it is right-shifted + * since in that case TB is calculated from TB-TA with the condition TB>TA). + */ + while( mbedtls_mpi_cmp_int( &TA, 0 ) != 0 ) + { + /* Divisions by 2 preserve the invariant (I). */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &TA, mbedtls_mpi_lsb( &TA ) ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &TB, mbedtls_mpi_lsb( &TB ) ) ); + + /* Set either TA or TB to |TA-TB|/2. Since TA and TB are both odd, + * TA-TB is even so the division by 2 has an integer result. + * Invariant (I) is preserved since any odd divisor of both TA and TB + * also divides |TA-TB|/2, and any odd divisor of both TA and |TA-TB|/2 + * also divides TB, and any odd divisior of both TB and |TA-TB|/2 also + * divides TA. + */ + if( mbedtls_mpi_cmp_mpi( &TA, &TB ) >= 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( &TA, &TA, &TB ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &TA, 1 ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( &TB, &TB, &TA ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &TB, 1 ) ); + } + /* Note that one of TA or TB is still odd. */ + } + + /* By invariant (I), gcd(A,B) = 2^k * gcd(TA,TB) for some k. + * At the loop exit, TA = 0, so gcd(TA,TB) = TB. + * - If there was at least one loop iteration, then one of TA or TB is odd, + * and TA = 0, so TB is odd and gcd(TA,TB) = gcd(A',B'). In this case, + * lz = min(a,b) so gcd(A,B) = 2^lz * TB. + * - If there was no loop iteration, then A was 0, and gcd(A,B) = B. + * In this case, lz = 0 and B = TB so gcd(A,B) = B = 2^lz * TB as well. + */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &TB, lz ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( G, &TB ) ); + +cleanup: + + mbedtls_mpi_free( &TG ); mbedtls_mpi_free( &TA ); mbedtls_mpi_free( &TB ); + + return( ret ); +} + +/* + * Fill X with size bytes of random. + * + * Use a temporary bytes representation to make sure the result is the same + * regardless of the platform endianness (useful when f_rng is actually + * deterministic, eg for tests). + */ +int mbedtls_mpi_fill_random( mbedtls_mpi *X, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + size_t const limbs = CHARS_TO_LIMBS( size ); + size_t const overhead = ( limbs * ciL ) - size; + unsigned char *Xp; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( f_rng != NULL ); + + /* Ensure that target MPI has exactly the necessary number of limbs */ + if( X->n != limbs ) + { + mbedtls_mpi_free( X ); + mbedtls_mpi_init( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, limbs ) ); + } + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( X, 0 ) ); + + Xp = (unsigned char*) X->p; + MBEDTLS_MPI_CHK( f_rng( p_rng, Xp + overhead, size ) ); + + mpi_bigendian_to_host( X->p, limbs ); + +cleanup: + return( ret ); +} + +/* + * Modular inverse: X = A^-1 mod N (HAC 14.61 / 14.64) + */ +int mbedtls_mpi_inv_mod( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *N ) +{ + int ret; + mbedtls_mpi G, TA, TU, U1, U2, TB, TV, V1, V2; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( A != NULL ); + MPI_VALIDATE_RET( N != NULL ); + + if( mbedtls_mpi_cmp_int( N, 1 ) <= 0 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &TA ); mbedtls_mpi_init( &TU ); mbedtls_mpi_init( &U1 ); mbedtls_mpi_init( &U2 ); + mbedtls_mpi_init( &G ); mbedtls_mpi_init( &TB ); mbedtls_mpi_init( &TV ); + mbedtls_mpi_init( &V1 ); mbedtls_mpi_init( &V2 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( &G, A, N ) ); + + if( mbedtls_mpi_cmp_int( &G, 1 ) != 0 ) + { + ret = MBEDTLS_ERR_MPI_NOT_ACCEPTABLE; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &TA, A, N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TU, &TA ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TB, N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TV, N ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &U1, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &U2, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &V1, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &V2, 1 ) ); + + do + { + while( ( TU.p[0] & 1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &TU, 1 ) ); + + if( ( U1.p[0] & 1 ) != 0 || ( U2.p[0] & 1 ) != 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &U1, &U1, &TB ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &U2, &U2, &TA ) ); + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &U1, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &U2, 1 ) ); + } + + while( ( TV.p[0] & 1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &TV, 1 ) ); + + if( ( V1.p[0] & 1 ) != 0 || ( V2.p[0] & 1 ) != 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &V1, &V1, &TB ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &V2, &V2, &TA ) ); + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &V1, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &V2, 1 ) ); + } + + if( mbedtls_mpi_cmp_mpi( &TU, &TV ) >= 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &TU, &TU, &TV ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &U1, &U1, &V1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &U2, &U2, &V2 ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &TV, &TV, &TU ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &V1, &V1, &U1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &V2, &V2, &U2 ) ); + } + } + while( mbedtls_mpi_cmp_int( &TU, 0 ) != 0 ); + + while( mbedtls_mpi_cmp_int( &V1, 0 ) < 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &V1, &V1, N ) ); + + while( mbedtls_mpi_cmp_mpi( &V1, N ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &V1, &V1, N ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( X, &V1 ) ); + +cleanup: + + mbedtls_mpi_free( &TA ); mbedtls_mpi_free( &TU ); mbedtls_mpi_free( &U1 ); mbedtls_mpi_free( &U2 ); + mbedtls_mpi_free( &G ); mbedtls_mpi_free( &TB ); mbedtls_mpi_free( &TV ); + mbedtls_mpi_free( &V1 ); mbedtls_mpi_free( &V2 ); + + return( ret ); +} + +#if defined(MBEDTLS_GENPRIME) + +static const int small_prime[] = +{ + 3, 5, 7, 11, 13, 17, 19, 23, + 29, 31, 37, 41, 43, 47, 53, 59, + 61, 67, 71, 73, 79, 83, 89, 97, + 101, 103, 107, 109, 113, 127, 131, 137, + 139, 149, 151, 157, 163, 167, 173, 179, + 181, 191, 193, 197, 199, 211, 223, 227, + 229, 233, 239, 241, 251, 257, 263, 269, + 271, 277, 281, 283, 293, 307, 311, 313, + 317, 331, 337, 347, 349, 353, 359, 367, + 373, 379, 383, 389, 397, 401, 409, 419, + 421, 431, 433, 439, 443, 449, 457, 461, + 463, 467, 479, 487, 491, 499, 503, 509, + 521, 523, 541, 547, 557, 563, 569, 571, + 577, 587, 593, 599, 601, 607, 613, 617, + 619, 631, 641, 643, 647, 653, 659, 661, + 673, 677, 683, 691, 701, 709, 719, 727, + 733, 739, 743, 751, 757, 761, 769, 773, + 787, 797, 809, 811, 821, 823, 827, 829, + 839, 853, 857, 859, 863, 877, 881, 883, + 887, 907, 911, 919, 929, 937, 941, 947, + 953, 967, 971, 977, 983, 991, 997, -103 +}; + +/* + * Small divisors test (X must be positive) + * + * Return values: + * 0: no small factor (possible prime, more tests needed) + * 1: certain prime + * MBEDTLS_ERR_MPI_NOT_ACCEPTABLE: certain non-prime + * other negative: error + */ +static int mpi_check_small_factors( const mbedtls_mpi *X ) +{ + int ret = 0; + size_t i; + mbedtls_mpi_uint r; + + if( ( X->p[0] & 1 ) == 0 ) + return( MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ); + + for( i = 0; small_prime[i] > 0; i++ ) + { + if( mbedtls_mpi_cmp_int( X, small_prime[i] ) <= 0 ) + return( 1 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_int( &r, X, small_prime[i] ) ); + + if( r == 0 ) + return( MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ); + } + +cleanup: + return( ret ); +} + +/* + * Miller-Rabin pseudo-primality test (HAC 4.24) + */ +static int mpi_miller_rabin( const mbedtls_mpi *X, size_t rounds, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret, count; + size_t i, j, k, s; + mbedtls_mpi W, R, T, A, RR; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( f_rng != NULL ); + + mbedtls_mpi_init( &W ); mbedtls_mpi_init( &R ); + mbedtls_mpi_init( &T ); mbedtls_mpi_init( &A ); + mbedtls_mpi_init( &RR ); + + /* + * W = |X| - 1 + * R = W >> lsb( W ) + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &W, X, 1 ) ); + s = mbedtls_mpi_lsb( &W ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R, &W ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &R, s ) ); + + for( i = 0; i < rounds; i++ ) + { + /* + * pick a random A, 1 < A < |X| - 1 + */ + count = 0; + do { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); + + j = mbedtls_mpi_bitlen( &A ); + k = mbedtls_mpi_bitlen( &W ); + if (j > k) { + A.p[A.n - 1] &= ( (mbedtls_mpi_uint) 1 << ( k - ( A.n - 1 ) * biL - 1 ) ) - 1; + } + + if (count++ > 30) { + ret = MBEDTLS_ERR_MPI_NOT_ACCEPTABLE; + goto cleanup; + } + + } while ( mbedtls_mpi_cmp_mpi( &A, &W ) >= 0 || + mbedtls_mpi_cmp_int( &A, 1 ) <= 0 ); + + /* + * A = A^R mod |X| + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &A, &A, &R, X, &RR ) ); + + if( mbedtls_mpi_cmp_mpi( &A, &W ) == 0 || + mbedtls_mpi_cmp_int( &A, 1 ) == 0 ) + continue; + + j = 1; + while( j < s && mbedtls_mpi_cmp_mpi( &A, &W ) != 0 ) + { + /* + * A = A * A mod |X| + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &A, &A ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &A, &T, X ) ); + + if( mbedtls_mpi_cmp_int( &A, 1 ) == 0 ) + break; + + j++; + } + + /* + * not prime if A != |X| - 1 or A == 1 + */ + if( mbedtls_mpi_cmp_mpi( &A, &W ) != 0 || + mbedtls_mpi_cmp_int( &A, 1 ) == 0 ) + { + ret = MBEDTLS_ERR_MPI_NOT_ACCEPTABLE; + break; + } + } + +cleanup: + mbedtls_mpi_free( &W ); mbedtls_mpi_free( &R ); + mbedtls_mpi_free( &T ); mbedtls_mpi_free( &A ); + mbedtls_mpi_free( &RR ); + + return( ret ); +} + +/* + * Pseudo-primality test: small factors, then Miller-Rabin + */ +int mbedtls_mpi_is_prime_ext( const mbedtls_mpi *X, int rounds, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + mbedtls_mpi XX; + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( f_rng != NULL ); + + XX.s = 1; + XX.n = X->n; + XX.p = X->p; + + if( mbedtls_mpi_cmp_int( &XX, 0 ) == 0 || + mbedtls_mpi_cmp_int( &XX, 1 ) == 0 ) + return( MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ); + + if( mbedtls_mpi_cmp_int( &XX, 2 ) == 0 ) + return( 0 ); + + if( ( ret = mpi_check_small_factors( &XX ) ) != 0 ) + { + if( ret == 1 ) + return( 0 ); + + return( ret ); + } + + return( mpi_miller_rabin( &XX, rounds, f_rng, p_rng ) ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/* + * Pseudo-primality test, error probability 2^-80 + */ +int mbedtls_mpi_is_prime( const mbedtls_mpi *X, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( f_rng != NULL ); + + /* + * In the past our key generation aimed for an error rate of at most + * 2^-80. Since this function is deprecated, aim for the same certainty + * here as well. + */ + return( mbedtls_mpi_is_prime_ext( X, 40, f_rng, p_rng ) ); +} +#endif + +/* + * Prime number generation + * + * To generate an RSA key in a way recommended by FIPS 186-4, both primes must + * be either 1024 bits or 1536 bits long, and flags must contain + * MBEDTLS_MPI_GEN_PRIME_FLAG_LOW_ERR. + */ +int mbedtls_mpi_gen_prime( mbedtls_mpi *X, size_t nbits, int flags, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ +#ifdef MBEDTLS_HAVE_INT64 +// ceil(2^63.5) +#define CEIL_MAXUINT_DIV_SQRT2 0xb504f333f9de6485ULL +#else +// ceil(2^31.5) +#define CEIL_MAXUINT_DIV_SQRT2 0xb504f334U +#endif + int ret = MBEDTLS_ERR_MPI_NOT_ACCEPTABLE; + size_t k, n; + int rounds; + mbedtls_mpi_uint r; + mbedtls_mpi Y; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( f_rng != NULL ); + + if( nbits < 3 || nbits > MBEDTLS_MPI_MAX_BITS ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &Y ); + + n = BITS_TO_LIMBS( nbits ); + + if( ( flags & MBEDTLS_MPI_GEN_PRIME_FLAG_LOW_ERR ) == 0 ) + { + /* + * 2^-80 error probability, number of rounds chosen per HAC, table 4.4 + */ + rounds = ( ( nbits >= 1300 ) ? 2 : ( nbits >= 850 ) ? 3 : + ( nbits >= 650 ) ? 4 : ( nbits >= 350 ) ? 8 : + ( nbits >= 250 ) ? 12 : ( nbits >= 150 ) ? 18 : 27 ); + } + else + { + /* + * 2^-100 error probability, number of rounds computed based on HAC, + * fact 4.48 + */ + rounds = ( ( nbits >= 1450 ) ? 4 : ( nbits >= 1150 ) ? 5 : + ( nbits >= 1000 ) ? 6 : ( nbits >= 850 ) ? 7 : + ( nbits >= 750 ) ? 8 : ( nbits >= 500 ) ? 13 : + ( nbits >= 250 ) ? 28 : ( nbits >= 150 ) ? 40 : 51 ); + } + + while( 1 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( X, n * ciL, f_rng, p_rng ) ); + /* make sure generated number is at least (nbits-1)+0.5 bits (FIPS 186-4 §B.3.3 steps 4.4, 5.5) */ + if( X->p[n-1] < CEIL_MAXUINT_DIV_SQRT2 ) continue; + + k = n * biL; + if( k > nbits ) MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( X, k - nbits ) ); + X->p[0] |= 1; + + if( ( flags & MBEDTLS_MPI_GEN_PRIME_FLAG_DH ) == 0 ) + { + ret = mbedtls_mpi_is_prime_ext( X, rounds, f_rng, p_rng ); + + if( ret != MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ) + goto cleanup; + } + else + { + /* + * An necessary condition for Y and X = 2Y + 1 to be prime + * is X = 2 mod 3 (which is equivalent to Y = 2 mod 3). + * Make sure it is satisfied, while keeping X = 3 mod 4 + */ + + X->p[0] |= 2; + + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_int( &r, X, 3 ) ); + if( r == 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( X, X, 8 ) ); + else if( r == 1 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( X, X, 4 ) ); + + /* Set Y = (X-1) / 2, which is X / 2 because X is odd */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Y, X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &Y, 1 ) ); + + while( 1 ) + { + /* + * First, check small factors for X and Y + * before doing Miller-Rabin on any of them + */ + if( ( ret = mpi_check_small_factors( X ) ) == 0 && + ( ret = mpi_check_small_factors( &Y ) ) == 0 && + ( ret = mpi_miller_rabin( X, rounds, f_rng, p_rng ) ) + == 0 && + ( ret = mpi_miller_rabin( &Y, rounds, f_rng, p_rng ) ) + == 0 ) + goto cleanup; + + if( ret != MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ) + goto cleanup; + + /* + * Next candidates. We want to preserve Y = (X-1) / 2 and + * Y = 1 mod 2 and Y = 2 mod 3 (eq X = 3 mod 4 and X = 2 mod 3) + * so up Y by 6 and X by 12. + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( X, X, 12 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( &Y, &Y, 6 ) ); + } + } + } + +cleanup: + + mbedtls_mpi_free( &Y ); + + return( ret ); +} + +#endif /* MBEDTLS_GENPRIME */ + +#if defined(MBEDTLS_SELF_TEST) + +#define GCD_PAIR_COUNT 3 + +static const int gcd_pairs[GCD_PAIR_COUNT][3] = +{ + { 693, 609, 21 }, + { 1764, 868, 28 }, + { 768454923, 542167814, 1 } +}; + +/* + * Checkup routine + */ +int mbedtls_mpi_self_test( int verbose ) +{ + int ret, i; + mbedtls_mpi A, E, N, X, Y, U, V; + + mbedtls_mpi_init( &A ); mbedtls_mpi_init( &E ); mbedtls_mpi_init( &N ); mbedtls_mpi_init( &X ); + mbedtls_mpi_init( &Y ); mbedtls_mpi_init( &U ); mbedtls_mpi_init( &V ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &A, 16, + "EFE021C2645FD1DC586E69184AF4A31E" \ + "D5F53E93B5F123FA41680867BA110131" \ + "944FE7952E2517337780CB0DB80E61AA" \ + "E7C8DDC6C5C6AADEB34EB38A2F40D5E6" ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &E, 16, + "B2E7EFD37075B9F03FF989C7C5051C20" \ + "34D2A323810251127E7BF8625A4F49A5" \ + "F3E27F4DA8BD59C47D6DAABA4C8127BD" \ + "5B5C25763222FEFCCFC38B832366C29E" ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &N, 16, + "0066A198186C18C10B2F5ED9B522752A" \ + "9830B69916E535C8F047518A889A43A5" \ + "94B6BED27A168D31D4A52F88925AA8F5" ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &X, &A, &N ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &U, 16, + "602AB7ECA597A3D6B56FF9829A5E8B85" \ + "9E857EA95A03512E2BAE7391688D264A" \ + "A5663B0341DB9CCFD2C4C5F421FEC814" \ + "8001B72E848A38CAE1C65F78E56ABDEF" \ + "E12D3C039B8A02D6BE593F0BBBDA56F1" \ + "ECF677152EF804370C1A305CAF3B5BF1" \ + "30879B56C61DE584A0F53A2447A51E" ) ); + + if( verbose != 0 ) + mbedtls_printf( " MPI test #1 (mul_mpi): " ); + + if( mbedtls_mpi_cmp_mpi( &X, &U ) != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + ret = 1; + goto cleanup; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_div_mpi( &X, &Y, &A, &N ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &U, 16, + "256567336059E52CAE22925474705F39A94" ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &V, 16, + "6613F26162223DF488E9CD48CC132C7A" \ + "0AC93C701B001B092E4E5B9F73BCD27B" \ + "9EE50D0657C77F374E903CDFA4C642" ) ); + + if( verbose != 0 ) + mbedtls_printf( " MPI test #2 (div_mpi): " ); + + if( mbedtls_mpi_cmp_mpi( &X, &U ) != 0 || + mbedtls_mpi_cmp_mpi( &Y, &V ) != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + ret = 1; + goto cleanup; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &X, &A, &E, &N, NULL ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &U, 16, + "36E139AEA55215609D2816998ED020BB" \ + "BD96C37890F65171D948E9BC7CBAA4D9" \ + "325D24D6A3C12710F10A09FA08AB87" ) ); + + if( verbose != 0 ) + mbedtls_printf( " MPI test #3 (exp_mod): " ); + + if( mbedtls_mpi_cmp_mpi( &X, &U ) != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + ret = 1; + goto cleanup; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &X, &A, &N ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &U, 16, + "003A0AAEDD7E784FC07D8F9EC6E3BFD5" \ + "C3DBA76456363A10869622EAC2DD84EC" \ + "C5B8A74DAC4D09E03B5E0BE779F2DF61" ) ); + + if( verbose != 0 ) + mbedtls_printf( " MPI test #4 (inv_mod): " ); + + if( mbedtls_mpi_cmp_mpi( &X, &U ) != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + ret = 1; + goto cleanup; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + if( verbose != 0 ) + mbedtls_printf( " MPI test #5 (simple gcd): " ); + + for( i = 0; i < GCD_PAIR_COUNT; i++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &X, gcd_pairs[i][0] ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &Y, gcd_pairs[i][1] ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( &A, &X, &Y ) ); + + if( mbedtls_mpi_cmp_int( &A, gcd_pairs[i][2] ) != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed at %d\n", i ); + + ret = 1; + goto cleanup; + } + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + +cleanup: + + if( ret != 0 && verbose != 0 ) + mbedtls_printf( "Unexpected error, return code = %08X\n", ret ); + + mbedtls_mpi_free( &A ); mbedtls_mpi_free( &E ); mbedtls_mpi_free( &N ); mbedtls_mpi_free( &X ); + mbedtls_mpi_free( &Y ); mbedtls_mpi_free( &U ); mbedtls_mpi_free( &V ); + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_BIGNUM_C */ diff --git a/src/common/mbedtls/library/mbedtls_cipher.c b/src/common/mbedtls/library/mbedtls_cipher.c new file mode 100644 index 0000000000..c1ad6ba636 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_cipher.c @@ -0,0 +1,1171 @@ +/** + * \file cipher.c + * + * \brief Generic cipher wrapper for mbed TLS + * + * \author Adriaan de Jong + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_CIPHER_C) + +#include "mbedtls/cipher.h" +#include "mbedtls/cipher_internal.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#include +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) +#include "mbedtls/chachapoly.h" +#endif + +#if defined(MBEDTLS_GCM_C) +#include "mbedtls/gcm.h" +#endif + +#if defined(MBEDTLS_CCM_C) +#include "mbedtls/ccm.h" +#endif + +#if defined(MBEDTLS_CHACHA20_C) +#include "mbedtls/chacha20.h" +#endif + +#if defined(MBEDTLS_CMAC_C) +#include "mbedtls/cmac.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#define CIPHER_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ) +#define CIPHER_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +/* Compare the contents of two buffers in constant time. + * Returns 0 if the contents are bitwise identical, otherwise returns + * a non-zero value. + * This is currently only used by GCM and ChaCha20+Poly1305. + */ +static int mbedtls_constant_time_memcmp( const void *v1, const void *v2, size_t len ) +{ + const unsigned char *p1 = (const unsigned char*) v1; + const unsigned char *p2 = (const unsigned char*) v2; + size_t i; + unsigned char diff; + + for( diff = 0, i = 0; i < len; i++ ) + diff |= p1[i] ^ p2[i]; + + return( (int)diff ); +} +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +static int supported_init = 0; + +const int *mbedtls_cipher_list( void ) +{ + const mbedtls_cipher_definition_t *def; + int *type; + + if( ! supported_init ) + { + def = mbedtls_cipher_definitions; + type = mbedtls_cipher_supported; + + while( def->type != 0 ) + *type++ = (*def++).type; + + *type = 0; + + supported_init = 1; + } + + return( mbedtls_cipher_supported ); +} + +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_type( const mbedtls_cipher_type_t cipher_type ) +{ + const mbedtls_cipher_definition_t *def; + + for( def = mbedtls_cipher_definitions; def->info != NULL; def++ ) + if( def->type == cipher_type ) + return( def->info ); + + return( NULL ); +} + +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_string( const char *cipher_name ) +{ + const mbedtls_cipher_definition_t *def; + + if( NULL == cipher_name ) + return( NULL ); + + for( def = mbedtls_cipher_definitions; def->info != NULL; def++ ) + if( ! strcmp( def->info->name, cipher_name ) ) + return( def->info ); + + return( NULL ); +} + +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values( const mbedtls_cipher_id_t cipher_id, + int key_bitlen, + const mbedtls_cipher_mode_t mode ) +{ + const mbedtls_cipher_definition_t *def; + + for( def = mbedtls_cipher_definitions; def->info != NULL; def++ ) + if( def->info->base->cipher == cipher_id && + def->info->key_bitlen == (unsigned) key_bitlen && + def->info->mode == mode ) + return( def->info ); + + return( NULL ); +} + +void mbedtls_cipher_init( mbedtls_cipher_context_t *ctx ) +{ + CIPHER_VALIDATE( ctx != NULL ); + memset( ctx, 0, sizeof( mbedtls_cipher_context_t ) ); +} + +void mbedtls_cipher_free( mbedtls_cipher_context_t *ctx ) +{ + if( ctx == NULL ) + return; + +#if defined(MBEDTLS_CMAC_C) + if( ctx->cmac_ctx ) + { + mbedtls_platform_zeroize( ctx->cmac_ctx, + sizeof( mbedtls_cmac_context_t ) ); + mbedtls_free( ctx->cmac_ctx ); + } +#endif + + if( ctx->cipher_ctx ) + ctx->cipher_info->base->ctx_free_func( ctx->cipher_ctx ); + + mbedtls_platform_zeroize( ctx, sizeof(mbedtls_cipher_context_t) ); +} + +int mbedtls_cipher_setup( mbedtls_cipher_context_t *ctx, const mbedtls_cipher_info_t *cipher_info ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + if( cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + memset( ctx, 0, sizeof( mbedtls_cipher_context_t ) ); + + if( NULL == ( ctx->cipher_ctx = cipher_info->base->ctx_alloc_func() ) ) + return( MBEDTLS_ERR_CIPHER_ALLOC_FAILED ); + + ctx->cipher_info = cipher_info; + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) + /* + * Ignore possible errors caused by a cipher mode that doesn't use padding + */ +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) + (void) mbedtls_cipher_set_padding_mode( ctx, MBEDTLS_PADDING_PKCS7 ); +#else + (void) mbedtls_cipher_set_padding_mode( ctx, MBEDTLS_PADDING_NONE ); +#endif +#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ + + return( 0 ); +} + +int mbedtls_cipher_setkey( mbedtls_cipher_context_t *ctx, + const unsigned char *key, + int key_bitlen, + const mbedtls_operation_t operation ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( key != NULL ); + CIPHER_VALIDATE_RET( operation == MBEDTLS_ENCRYPT || + operation == MBEDTLS_DECRYPT ); + if( ctx->cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + if( ( ctx->cipher_info->flags & MBEDTLS_CIPHER_VARIABLE_KEY_LEN ) == 0 && + (int) ctx->cipher_info->key_bitlen != key_bitlen ) + { + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + } + + ctx->key_bitlen = key_bitlen; + ctx->operation = operation; + + /* + * For OFB, CFB and CTR mode always use the encryption key schedule + */ + if( MBEDTLS_ENCRYPT == operation || + MBEDTLS_MODE_CFB == ctx->cipher_info->mode || + MBEDTLS_MODE_OFB == ctx->cipher_info->mode || + MBEDTLS_MODE_CTR == ctx->cipher_info->mode ) + { + return( ctx->cipher_info->base->setkey_enc_func( ctx->cipher_ctx, key, + ctx->key_bitlen ) ); + } + + if( MBEDTLS_DECRYPT == operation ) + return( ctx->cipher_info->base->setkey_dec_func( ctx->cipher_ctx, key, + ctx->key_bitlen ) ); + + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); +} + +int mbedtls_cipher_set_iv( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, + size_t iv_len ) +{ + size_t actual_iv_size; + + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( iv_len == 0 || iv != NULL ); + if( ctx->cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + /* avoid buffer overflow in ctx->iv */ + if( iv_len > MBEDTLS_MAX_IV_LENGTH ) + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); + + if( ( ctx->cipher_info->flags & MBEDTLS_CIPHER_VARIABLE_IV_LEN ) != 0 ) + actual_iv_size = iv_len; + else + { + actual_iv_size = ctx->cipher_info->iv_size; + + /* avoid reading past the end of input buffer */ + if( actual_iv_size > iv_len ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_CHACHA20_C) + if ( ctx->cipher_info->type == MBEDTLS_CIPHER_CHACHA20 ) + { + if ( 0 != mbedtls_chacha20_starts( (mbedtls_chacha20_context*)ctx->cipher_ctx, + iv, + 0U ) ) /* Initial counter value */ + { + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + } + } +#endif + + if ( actual_iv_size != 0 ) + { + memcpy( ctx->iv, iv, actual_iv_size ); + ctx->iv_size = actual_iv_size; + } + + return( 0 ); +} + +int mbedtls_cipher_reset( mbedtls_cipher_context_t *ctx ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + if( ctx->cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + ctx->unprocessed_len = 0; + + return( 0 ); +} + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +int mbedtls_cipher_update_ad( mbedtls_cipher_context_t *ctx, + const unsigned char *ad, size_t ad_len ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); + if( ctx->cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_GCM_C) + if( MBEDTLS_MODE_GCM == ctx->cipher_info->mode ) + { + return( mbedtls_gcm_starts( (mbedtls_gcm_context *) ctx->cipher_ctx, ctx->operation, + ctx->iv, ctx->iv_size, ad, ad_len ) ); + } +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type ) + { + int result; + mbedtls_chachapoly_mode_t mode; + + mode = ( ctx->operation == MBEDTLS_ENCRYPT ) + ? MBEDTLS_CHACHAPOLY_ENCRYPT + : MBEDTLS_CHACHAPOLY_DECRYPT; + + result = mbedtls_chachapoly_starts( (mbedtls_chachapoly_context*) ctx->cipher_ctx, + ctx->iv, + mode ); + if ( result != 0 ) + return( result ); + + return( mbedtls_chachapoly_update_aad( (mbedtls_chachapoly_context*) ctx->cipher_ctx, + ad, ad_len ) ); + } +#endif + + return( 0 ); +} +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +int mbedtls_cipher_update( mbedtls_cipher_context_t *ctx, const unsigned char *input, + size_t ilen, unsigned char *output, size_t *olen ) +{ + int ret; + size_t block_size; + + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); + CIPHER_VALIDATE_RET( output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + if( ctx->cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + *olen = 0; + block_size = mbedtls_cipher_get_block_size( ctx ); + if ( 0 == block_size ) + { + return( MBEDTLS_ERR_CIPHER_INVALID_CONTEXT ); + } + + if( ctx->cipher_info->mode == MBEDTLS_MODE_ECB ) + { + if( ilen != block_size ) + return( MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED ); + + *olen = ilen; + + if( 0 != ( ret = ctx->cipher_info->base->ecb_func( ctx->cipher_ctx, + ctx->operation, input, output ) ) ) + { + return( ret ); + } + + return( 0 ); + } + +#if defined(MBEDTLS_GCM_C) + if( ctx->cipher_info->mode == MBEDTLS_MODE_GCM ) + { + *olen = ilen; + return( mbedtls_gcm_update( (mbedtls_gcm_context *) ctx->cipher_ctx, ilen, input, + output ) ); + } +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + if ( ctx->cipher_info->type == MBEDTLS_CIPHER_CHACHA20_POLY1305 ) + { + *olen = ilen; + return( mbedtls_chachapoly_update( (mbedtls_chachapoly_context*) ctx->cipher_ctx, + ilen, input, output ) ); + } +#endif + + if( input == output && + ( ctx->unprocessed_len != 0 || ilen % block_size ) ) + { + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + if( ctx->cipher_info->mode == MBEDTLS_MODE_CBC ) + { + size_t copy_len = 0; + + /* + * If there is not enough data for a full block, cache it. + */ + if( ( ctx->operation == MBEDTLS_DECRYPT && NULL != ctx->add_padding && + ilen <= block_size - ctx->unprocessed_len ) || + ( ctx->operation == MBEDTLS_DECRYPT && NULL == ctx->add_padding && + ilen < block_size - ctx->unprocessed_len ) || + ( ctx->operation == MBEDTLS_ENCRYPT && + ilen < block_size - ctx->unprocessed_len ) ) + { + memcpy( &( ctx->unprocessed_data[ctx->unprocessed_len] ), input, + ilen ); + + ctx->unprocessed_len += ilen; + return( 0 ); + } + + /* + * Process cached data first + */ + if( 0 != ctx->unprocessed_len ) + { + copy_len = block_size - ctx->unprocessed_len; + + memcpy( &( ctx->unprocessed_data[ctx->unprocessed_len] ), input, + copy_len ); + + if( 0 != ( ret = ctx->cipher_info->base->cbc_func( ctx->cipher_ctx, + ctx->operation, block_size, ctx->iv, + ctx->unprocessed_data, output ) ) ) + { + return( ret ); + } + + *olen += block_size; + output += block_size; + ctx->unprocessed_len = 0; + + input += copy_len; + ilen -= copy_len; + } + + /* + * Cache final, incomplete block + */ + if( 0 != ilen ) + { + /* Encryption: only cache partial blocks + * Decryption w/ padding: always keep at least one whole block + * Decryption w/o padding: only cache partial blocks + */ + copy_len = ilen % block_size; + if( copy_len == 0 && + ctx->operation == MBEDTLS_DECRYPT && + NULL != ctx->add_padding) + { + copy_len = block_size; + } + + memcpy( ctx->unprocessed_data, &( input[ilen - copy_len] ), + copy_len ); + + ctx->unprocessed_len += copy_len; + ilen -= copy_len; + } + + /* + * Process remaining full blocks + */ + if( ilen ) + { + if( 0 != ( ret = ctx->cipher_info->base->cbc_func( ctx->cipher_ctx, + ctx->operation, ilen, ctx->iv, input, output ) ) ) + { + return( ret ); + } + + *olen += ilen; + } + + return( 0 ); + } +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) + if( ctx->cipher_info->mode == MBEDTLS_MODE_CFB ) + { + if( 0 != ( ret = ctx->cipher_info->base->cfb_func( ctx->cipher_ctx, + ctx->operation, ilen, &ctx->unprocessed_len, ctx->iv, + input, output ) ) ) + { + return( ret ); + } + + *olen = ilen; + + return( 0 ); + } +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) + if( ctx->cipher_info->mode == MBEDTLS_MODE_OFB ) + { + if( 0 != ( ret = ctx->cipher_info->base->ofb_func( ctx->cipher_ctx, + ilen, &ctx->unprocessed_len, ctx->iv, input, output ) ) ) + { + return( ret ); + } + + *olen = ilen; + + return( 0 ); + } +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) + if( ctx->cipher_info->mode == MBEDTLS_MODE_CTR ) + { + if( 0 != ( ret = ctx->cipher_info->base->ctr_func( ctx->cipher_ctx, + ilen, &ctx->unprocessed_len, ctx->iv, + ctx->unprocessed_data, input, output ) ) ) + { + return( ret ); + } + + *olen = ilen; + + return( 0 ); + } +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) + if( ctx->cipher_info->mode == MBEDTLS_MODE_XTS ) + { + if( ctx->unprocessed_len > 0 ) { + /* We can only process an entire data unit at a time. */ + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); + } + + ret = ctx->cipher_info->base->xts_func( ctx->cipher_ctx, + ctx->operation, ilen, ctx->iv, input, output ); + if( ret != 0 ) + { + return( ret ); + } + + *olen = ilen; + + return( 0 ); + } +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + if( ctx->cipher_info->mode == MBEDTLS_MODE_STREAM ) + { + if( 0 != ( ret = ctx->cipher_info->base->stream_func( ctx->cipher_ctx, + ilen, input, output ) ) ) + { + return( ret ); + } + + *olen = ilen; + + return( 0 ); + } +#endif /* MBEDTLS_CIPHER_MODE_STREAM */ + + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); +} + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) +/* + * PKCS7 (and PKCS5) padding: fill with ll bytes, with ll = padding_len + */ +static void add_pkcs_padding( unsigned char *output, size_t output_len, + size_t data_len ) +{ + size_t padding_len = output_len - data_len; + unsigned char i; + + for( i = 0; i < padding_len; i++ ) + output[data_len + i] = (unsigned char) padding_len; +} + +static int get_pkcs_padding( unsigned char *input, size_t input_len, + size_t *data_len ) +{ + size_t i, pad_idx; + unsigned char padding_len, bad = 0; + + if( NULL == input || NULL == data_len ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + padding_len = input[input_len - 1]; + *data_len = input_len - padding_len; + + /* Avoid logical || since it results in a branch */ + bad |= padding_len > input_len; + bad |= padding_len == 0; + + /* The number of bytes checked must be independent of padding_len, + * so pick input_len, which is usually 8 or 16 (one block) */ + pad_idx = input_len - padding_len; + for( i = 0; i < input_len; i++ ) + bad |= ( input[i] ^ padding_len ) * ( i >= pad_idx ); + + return( MBEDTLS_ERR_CIPHER_INVALID_PADDING * ( bad != 0 ) ); +} +#endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ + +#if defined(MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS) +/* + * One and zeros padding: fill with 80 00 ... 00 + */ +static void add_one_and_zeros_padding( unsigned char *output, + size_t output_len, size_t data_len ) +{ + size_t padding_len = output_len - data_len; + unsigned char i = 0; + + output[data_len] = 0x80; + for( i = 1; i < padding_len; i++ ) + output[data_len + i] = 0x00; +} + +static int get_one_and_zeros_padding( unsigned char *input, size_t input_len, + size_t *data_len ) +{ + size_t i; + unsigned char done = 0, prev_done, bad; + + if( NULL == input || NULL == data_len ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + bad = 0x80; + *data_len = 0; + for( i = input_len; i > 0; i-- ) + { + prev_done = done; + done |= ( input[i - 1] != 0 ); + *data_len |= ( i - 1 ) * ( done != prev_done ); + bad ^= input[i - 1] * ( done != prev_done ); + } + + return( MBEDTLS_ERR_CIPHER_INVALID_PADDING * ( bad != 0 ) ); + +} +#endif /* MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS */ + +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN) +/* + * Zeros and len padding: fill with 00 ... 00 ll, where ll is padding length + */ +static void add_zeros_and_len_padding( unsigned char *output, + size_t output_len, size_t data_len ) +{ + size_t padding_len = output_len - data_len; + unsigned char i = 0; + + for( i = 1; i < padding_len; i++ ) + output[data_len + i - 1] = 0x00; + output[output_len - 1] = (unsigned char) padding_len; +} + +static int get_zeros_and_len_padding( unsigned char *input, size_t input_len, + size_t *data_len ) +{ + size_t i, pad_idx; + unsigned char padding_len, bad = 0; + + if( NULL == input || NULL == data_len ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + padding_len = input[input_len - 1]; + *data_len = input_len - padding_len; + + /* Avoid logical || since it results in a branch */ + bad |= padding_len > input_len; + bad |= padding_len == 0; + + /* The number of bytes checked must be independent of padding_len */ + pad_idx = input_len - padding_len; + for( i = 0; i < input_len - 1; i++ ) + bad |= input[i] * ( i >= pad_idx ); + + return( MBEDTLS_ERR_CIPHER_INVALID_PADDING * ( bad != 0 ) ); +} +#endif /* MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN */ + +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS) +/* + * Zero padding: fill with 00 ... 00 + */ +static void add_zeros_padding( unsigned char *output, + size_t output_len, size_t data_len ) +{ + size_t i; + + for( i = data_len; i < output_len; i++ ) + output[i] = 0x00; +} + +static int get_zeros_padding( unsigned char *input, size_t input_len, + size_t *data_len ) +{ + size_t i; + unsigned char done = 0, prev_done; + + if( NULL == input || NULL == data_len ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + *data_len = 0; + for( i = input_len; i > 0; i-- ) + { + prev_done = done; + done |= ( input[i-1] != 0 ); + *data_len |= i * ( done != prev_done ); + } + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_PADDING_ZEROS */ + +/* + * No padding: don't pad :) + * + * There is no add_padding function (check for NULL in mbedtls_cipher_finish) + * but a trivial get_padding function + */ +static int get_no_padding( unsigned char *input, size_t input_len, + size_t *data_len ) +{ + if( NULL == input || NULL == data_len ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + *data_len = input_len; + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ + +int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx, + unsigned char *output, size_t *olen ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + if( ctx->cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + *olen = 0; + + if( MBEDTLS_MODE_CFB == ctx->cipher_info->mode || + MBEDTLS_MODE_OFB == ctx->cipher_info->mode || + MBEDTLS_MODE_CTR == ctx->cipher_info->mode || + MBEDTLS_MODE_GCM == ctx->cipher_info->mode || + MBEDTLS_MODE_XTS == ctx->cipher_info->mode || + MBEDTLS_MODE_STREAM == ctx->cipher_info->mode ) + { + return( 0 ); + } + + if ( ( MBEDTLS_CIPHER_CHACHA20 == ctx->cipher_info->type ) || + ( MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type ) ) + { + return( 0 ); + } + + if( MBEDTLS_MODE_ECB == ctx->cipher_info->mode ) + { + if( ctx->unprocessed_len != 0 ) + return( MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED ); + + return( 0 ); + } + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + if( MBEDTLS_MODE_CBC == ctx->cipher_info->mode ) + { + int ret = 0; + + if( MBEDTLS_ENCRYPT == ctx->operation ) + { + /* check for 'no padding' mode */ + if( NULL == ctx->add_padding ) + { + if( 0 != ctx->unprocessed_len ) + return( MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED ); + + return( 0 ); + } + + ctx->add_padding( ctx->unprocessed_data, mbedtls_cipher_get_iv_size( ctx ), + ctx->unprocessed_len ); + } + else if( mbedtls_cipher_get_block_size( ctx ) != ctx->unprocessed_len ) + { + /* + * For decrypt operations, expect a full block, + * or an empty block if no padding + */ + if( NULL == ctx->add_padding && 0 == ctx->unprocessed_len ) + return( 0 ); + + return( MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED ); + } + + /* cipher block */ + if( 0 != ( ret = ctx->cipher_info->base->cbc_func( ctx->cipher_ctx, + ctx->operation, mbedtls_cipher_get_block_size( ctx ), ctx->iv, + ctx->unprocessed_data, output ) ) ) + { + return( ret ); + } + + /* Set output size for decryption */ + if( MBEDTLS_DECRYPT == ctx->operation ) + return( ctx->get_padding( output, mbedtls_cipher_get_block_size( ctx ), + olen ) ); + + /* Set output size for encryption */ + *olen = mbedtls_cipher_get_block_size( ctx ); + return( 0 ); + } +#else + ((void) output); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); +} + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) +int mbedtls_cipher_set_padding_mode( mbedtls_cipher_context_t *ctx, + mbedtls_cipher_padding_t mode ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + + if( NULL == ctx->cipher_info || MBEDTLS_MODE_CBC != ctx->cipher_info->mode ) + { + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + } + + switch( mode ) + { +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) + case MBEDTLS_PADDING_PKCS7: + ctx->add_padding = add_pkcs_padding; + ctx->get_padding = get_pkcs_padding; + break; +#endif +#if defined(MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS) + case MBEDTLS_PADDING_ONE_AND_ZEROS: + ctx->add_padding = add_one_and_zeros_padding; + ctx->get_padding = get_one_and_zeros_padding; + break; +#endif +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN) + case MBEDTLS_PADDING_ZEROS_AND_LEN: + ctx->add_padding = add_zeros_and_len_padding; + ctx->get_padding = get_zeros_and_len_padding; + break; +#endif +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS) + case MBEDTLS_PADDING_ZEROS: + ctx->add_padding = add_zeros_padding; + ctx->get_padding = get_zeros_padding; + break; +#endif + case MBEDTLS_PADDING_NONE: + ctx->add_padding = NULL; + ctx->get_padding = get_no_padding; + break; + + default: + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); + } + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +int mbedtls_cipher_write_tag( mbedtls_cipher_context_t *ctx, + unsigned char *tag, size_t tag_len ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); + if( ctx->cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + if( MBEDTLS_ENCRYPT != ctx->operation ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_GCM_C) + if( MBEDTLS_MODE_GCM == ctx->cipher_info->mode ) + return( mbedtls_gcm_finish( (mbedtls_gcm_context *) ctx->cipher_ctx, + tag, tag_len ) ); +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + if ( MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type ) + { + /* Don't allow truncated MAC for Poly1305 */ + if ( tag_len != 16U ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + return( mbedtls_chachapoly_finish( (mbedtls_chachapoly_context*) ctx->cipher_ctx, + tag ) ); + } +#endif + + return( 0 ); +} + +int mbedtls_cipher_check_tag( mbedtls_cipher_context_t *ctx, + const unsigned char *tag, size_t tag_len ) +{ + unsigned char check_tag[16]; + int ret; + + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); + if( ctx->cipher_info == NULL ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + if( MBEDTLS_DECRYPT != ctx->operation ) + { + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_GCM_C) + if( MBEDTLS_MODE_GCM == ctx->cipher_info->mode ) + { + if( tag_len > sizeof( check_tag ) ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + if( 0 != ( ret = mbedtls_gcm_finish( (mbedtls_gcm_context *) ctx->cipher_ctx, + check_tag, tag_len ) ) ) + { + return( ret ); + } + + /* Check the tag in "constant-time" */ + if( mbedtls_constant_time_memcmp( tag, check_tag, tag_len ) != 0 ) + return( MBEDTLS_ERR_CIPHER_AUTH_FAILED ); + + return( 0 ); + } +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CHACHAPOLY_C) + if ( MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type ) + { + /* Don't allow truncated MAC for Poly1305 */ + if ( tag_len != sizeof( check_tag ) ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + ret = mbedtls_chachapoly_finish( (mbedtls_chachapoly_context*) ctx->cipher_ctx, + check_tag ); + if ( ret != 0 ) + { + return( ret ); + } + + /* Check the tag in "constant-time" */ + if( mbedtls_constant_time_memcmp( tag, check_tag, tag_len ) != 0 ) + return( MBEDTLS_ERR_CIPHER_AUTH_FAILED ); + + return( 0 ); + } +#endif /* MBEDTLS_CHACHAPOLY_C */ + + return( 0 ); +} +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +/* + * Packet-oriented wrapper for non-AEAD modes + */ +int mbedtls_cipher_crypt( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen ) +{ + int ret; + size_t finish_olen; + + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( iv_len == 0 || iv != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); + CIPHER_VALIDATE_RET( output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + + if( ( ret = mbedtls_cipher_set_iv( ctx, iv, iv_len ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_cipher_reset( ctx ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_cipher_update( ctx, input, ilen, output, olen ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_cipher_finish( ctx, output + *olen, &finish_olen ) ) != 0 ) + return( ret ); + + *olen += finish_olen; + + return( 0 ); +} + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) +/* + * Packet-oriented encryption for AEAD modes + */ +int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, + unsigned char *tag, size_t tag_len ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( iv != NULL ); + CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); + CIPHER_VALIDATE_RET( output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); + +#if defined(MBEDTLS_GCM_C) + if( MBEDTLS_MODE_GCM == ctx->cipher_info->mode ) + { + *olen = ilen; + return( mbedtls_gcm_crypt_and_tag( ctx->cipher_ctx, MBEDTLS_GCM_ENCRYPT, ilen, + iv, iv_len, ad, ad_len, input, output, + tag_len, tag ) ); + } +#endif /* MBEDTLS_GCM_C */ +#if defined(MBEDTLS_CCM_C) + if( MBEDTLS_MODE_CCM == ctx->cipher_info->mode ) + { + *olen = ilen; + return( mbedtls_ccm_encrypt_and_tag( ctx->cipher_ctx, ilen, + iv, iv_len, ad, ad_len, input, output, + tag, tag_len ) ); + } +#endif /* MBEDTLS_CCM_C */ +#if defined(MBEDTLS_CHACHAPOLY_C) + if ( MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type ) + { + /* ChachaPoly has fixed length nonce and MAC (tag) */ + if ( ( iv_len != ctx->cipher_info->iv_size ) || + ( tag_len != 16U ) ) + { + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + } + + *olen = ilen; + return( mbedtls_chachapoly_encrypt_and_tag( ctx->cipher_ctx, + ilen, iv, ad, ad_len, input, output, tag ) ); + } +#endif /* MBEDTLS_CHACHAPOLY_C */ + + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); +} + +/* + * Packet-oriented decryption for AEAD modes + */ +int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, + const unsigned char *tag, size_t tag_len ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( iv != NULL ); + CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); + CIPHER_VALIDATE_RET( output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); + +#if defined(MBEDTLS_GCM_C) + if( MBEDTLS_MODE_GCM == ctx->cipher_info->mode ) + { + int ret; + + *olen = ilen; + ret = mbedtls_gcm_auth_decrypt( ctx->cipher_ctx, ilen, + iv, iv_len, ad, ad_len, + tag, tag_len, input, output ); + + if( ret == MBEDTLS_ERR_GCM_AUTH_FAILED ) + ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; + + return( ret ); + } +#endif /* MBEDTLS_GCM_C */ +#if defined(MBEDTLS_CCM_C) + if( MBEDTLS_MODE_CCM == ctx->cipher_info->mode ) + { + int ret; + + *olen = ilen; + ret = mbedtls_ccm_auth_decrypt( ctx->cipher_ctx, ilen, + iv, iv_len, ad, ad_len, + input, output, tag, tag_len ); + + if( ret == MBEDTLS_ERR_CCM_AUTH_FAILED ) + ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; + + return( ret ); + } +#endif /* MBEDTLS_CCM_C */ +#if defined(MBEDTLS_CHACHAPOLY_C) + if ( MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type ) + { + int ret; + + /* ChachaPoly has fixed length nonce and MAC (tag) */ + if ( ( iv_len != ctx->cipher_info->iv_size ) || + ( tag_len != 16U ) ) + { + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + } + + *olen = ilen; + ret = mbedtls_chachapoly_auth_decrypt( ctx->cipher_ctx, ilen, + iv, ad, ad_len, tag, input, output ); + + if( ret == MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED ) + ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; + + return( ret ); + } +#endif /* MBEDTLS_CHACHAPOLY_C */ + + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); +} +#endif /* MBEDTLS_CIPHER_MODE_AEAD */ + +#endif /* MBEDTLS_CIPHER_C */ diff --git a/src/common/mbedtls/library/mbedtls_cipher_wrap.c b/src/common/mbedtls/library/mbedtls_cipher_wrap.c new file mode 100644 index 0000000000..b38dd433ff --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_cipher_wrap.c @@ -0,0 +1,2285 @@ +/** + * \file cipher_wrap.c + * + * \brief Generic cipher wrapper for mbed TLS + * + * \author Adriaan de Jong + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_CIPHER_C) + +#include "mbedtls/cipher_internal.h" + +#if defined(MBEDTLS_CHACHAPOLY_C) +#include "mbedtls/chachapoly.h" +#endif + +#if defined(MBEDTLS_AES_C) +#include "mbedtls/aes.h" +#endif + +#if defined(MBEDTLS_ARC4_C) +#include "mbedtls/arc4.h" +#endif + +#if defined(MBEDTLS_CAMELLIA_C) +#include "mbedtls/camellia.h" +#endif + +#if defined(MBEDTLS_ARIA_C) +#include "mbedtls/aria.h" +#endif + +#if defined(MBEDTLS_DES_C) +#include "mbedtls/des.h" +#endif + +#if defined(MBEDTLS_BLOWFISH_C) +#include "mbedtls/blowfish.h" +#endif + +#if defined(MBEDTLS_CHACHA20_C) +#include "mbedtls/chacha20.h" +#endif + +#if defined(MBEDTLS_GCM_C) +#include "mbedtls/gcm.h" +#endif + +#if defined(MBEDTLS_CCM_C) +#include "mbedtls/ccm.h" +#endif + +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) +#ifndef NVRM +#include +#endif +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#if defined(MBEDTLS_GCM_C) +/* shared by all GCM ciphers */ +static void *gcm_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_gcm_context ) ); + + if( ctx != NULL ) + mbedtls_gcm_init( (mbedtls_gcm_context *) ctx ); + + return( ctx ); +} + +static void gcm_ctx_free( void *ctx ) +{ + mbedtls_gcm_free( ctx ); + mbedtls_free( ctx ); +} +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CCM_C) +/* shared by all CCM ciphers */ +static void *ccm_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_ccm_context ) ); + + if( ctx != NULL ) + mbedtls_ccm_init( (mbedtls_ccm_context *) ctx ); + + return( ctx ); +} + +static void ccm_ctx_free( void *ctx ) +{ + mbedtls_ccm_free( ctx ); + mbedtls_free( ctx ); +} +#endif /* MBEDTLS_CCM_C */ + +#if defined(MBEDTLS_AES_C) + +static int aes_crypt_ecb_wrap( void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_aes_crypt_ecb( (mbedtls_aes_context *) ctx, operation, input, output ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int aes_crypt_cbc_wrap( void *ctx, mbedtls_operation_t operation, size_t length, + unsigned char *iv, const unsigned char *input, unsigned char *output ) +{ + return mbedtls_aes_crypt_cbc( (mbedtls_aes_context *) ctx, operation, length, iv, input, + output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static int aes_crypt_cfb128_wrap( void *ctx, mbedtls_operation_t operation, + size_t length, size_t *iv_off, unsigned char *iv, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_aes_crypt_cfb128( (mbedtls_aes_context *) ctx, operation, length, iv_off, iv, + input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +static int aes_crypt_ofb_wrap( void *ctx, size_t length, size_t *iv_off, + unsigned char *iv, const unsigned char *input, unsigned char *output ) +{ + return mbedtls_aes_crypt_ofb( (mbedtls_aes_context *) ctx, length, iv_off, + iv, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static int aes_crypt_ctr_wrap( void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_aes_crypt_ctr( (mbedtls_aes_context *) ctx, length, nc_off, nonce_counter, + stream_block, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +static int aes_crypt_xts_wrap( void *ctx, mbedtls_operation_t operation, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output ) +{ + mbedtls_aes_xts_context *xts_ctx = ctx; + int mode; + + switch( operation ) + { + case MBEDTLS_ENCRYPT: + mode = MBEDTLS_AES_ENCRYPT; + break; + case MBEDTLS_DECRYPT: + mode = MBEDTLS_AES_DECRYPT; + break; + default: + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return mbedtls_aes_crypt_xts( xts_ctx, mode, length, + data_unit, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +static int aes_setkey_dec_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_aes_setkey_dec( (mbedtls_aes_context *) ctx, key, key_bitlen ); +} + +static int aes_setkey_enc_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_aes_setkey_enc( (mbedtls_aes_context *) ctx, key, key_bitlen ); +} + +static void * aes_ctx_alloc( void ) +{ + mbedtls_aes_context *aes = mbedtls_calloc( 1, sizeof( mbedtls_aes_context ) ); + + if( aes == NULL ) + return( NULL ); + + mbedtls_aes_init( aes ); + + return( aes ); +} + +static void aes_ctx_free( void *ctx ) +{ + mbedtls_aes_free( (mbedtls_aes_context *) ctx ); + mbedtls_free( ctx ); +} + +static const mbedtls_cipher_base_t aes_info = { + MBEDTLS_CIPHER_ID_AES, + aes_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + aes_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + aes_crypt_cfb128_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + aes_crypt_ofb_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + aes_crypt_ctr_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + aes_setkey_enc_wrap, + aes_setkey_dec_wrap, + aes_ctx_alloc, + aes_ctx_free +}; + +static const mbedtls_cipher_info_t aes_128_ecb_info = { + MBEDTLS_CIPHER_AES_128_ECB, + MBEDTLS_MODE_ECB, + 128, + "AES-128-ECB", + 0, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_192_ecb_info = { + MBEDTLS_CIPHER_AES_192_ECB, + MBEDTLS_MODE_ECB, + 192, + "AES-192-ECB", + 0, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_256_ecb_info = { + MBEDTLS_CIPHER_AES_256_ECB, + MBEDTLS_MODE_ECB, + 256, + "AES-256-ECB", + 0, + 0, + 16, + &aes_info +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t aes_128_cbc_info = { + MBEDTLS_CIPHER_AES_128_CBC, + MBEDTLS_MODE_CBC, + 128, + "AES-128-CBC", + 16, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_192_cbc_info = { + MBEDTLS_CIPHER_AES_192_CBC, + MBEDTLS_MODE_CBC, + 192, + "AES-192-CBC", + 16, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_256_cbc_info = { + MBEDTLS_CIPHER_AES_256_CBC, + MBEDTLS_MODE_CBC, + 256, + "AES-256-CBC", + 16, + 0, + 16, + &aes_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static const mbedtls_cipher_info_t aes_128_cfb128_info = { + MBEDTLS_CIPHER_AES_128_CFB128, + MBEDTLS_MODE_CFB, + 128, + "AES-128-CFB128", + 16, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_192_cfb128_info = { + MBEDTLS_CIPHER_AES_192_CFB128, + MBEDTLS_MODE_CFB, + 192, + "AES-192-CFB128", + 16, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_256_cfb128_info = { + MBEDTLS_CIPHER_AES_256_CFB128, + MBEDTLS_MODE_CFB, + 256, + "AES-256-CFB128", + 16, + 0, + 16, + &aes_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +static const mbedtls_cipher_info_t aes_128_ofb_info = { + MBEDTLS_CIPHER_AES_128_OFB, + MBEDTLS_MODE_OFB, + 128, + "AES-128-OFB", + 16, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_192_ofb_info = { + MBEDTLS_CIPHER_AES_192_OFB, + MBEDTLS_MODE_OFB, + 192, + "AES-192-OFB", + 16, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_256_ofb_info = { + MBEDTLS_CIPHER_AES_256_OFB, + MBEDTLS_MODE_OFB, + 256, + "AES-256-OFB", + 16, + 0, + 16, + &aes_info +}; +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static const mbedtls_cipher_info_t aes_128_ctr_info = { + MBEDTLS_CIPHER_AES_128_CTR, + MBEDTLS_MODE_CTR, + 128, + "AES-128-CTR", + 16, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_192_ctr_info = { + MBEDTLS_CIPHER_AES_192_CTR, + MBEDTLS_MODE_CTR, + 192, + "AES-192-CTR", + 16, + 0, + 16, + &aes_info +}; + +static const mbedtls_cipher_info_t aes_256_ctr_info = { + MBEDTLS_CIPHER_AES_256_CTR, + MBEDTLS_MODE_CTR, + 256, + "AES-256-CTR", + 16, + 0, + 16, + &aes_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +static int xts_aes_setkey_enc_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + mbedtls_aes_xts_context *xts_ctx = ctx; + return( mbedtls_aes_xts_setkey_enc( xts_ctx, key, key_bitlen ) ); +} + +static int xts_aes_setkey_dec_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + mbedtls_aes_xts_context *xts_ctx = ctx; + return( mbedtls_aes_xts_setkey_dec( xts_ctx, key, key_bitlen ) ); +} + +static void *xts_aes_ctx_alloc( void ) +{ + mbedtls_aes_xts_context *xts_ctx = mbedtls_calloc( 1, sizeof( *xts_ctx ) ); + + if( xts_ctx != NULL ) + mbedtls_aes_xts_init( xts_ctx ); + + return( xts_ctx ); +} + +static void xts_aes_ctx_free( void *ctx ) +{ + mbedtls_aes_xts_context *xts_ctx = ctx; + + if( xts_ctx == NULL ) + return; + + mbedtls_aes_xts_free( xts_ctx ); + mbedtls_free( xts_ctx ); +} + +static const mbedtls_cipher_base_t xts_aes_info = { + MBEDTLS_CIPHER_ID_AES, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + aes_crypt_xts_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + xts_aes_setkey_enc_wrap, + xts_aes_setkey_dec_wrap, + xts_aes_ctx_alloc, + xts_aes_ctx_free +}; + +static const mbedtls_cipher_info_t aes_128_xts_info = { + MBEDTLS_CIPHER_AES_128_XTS, + MBEDTLS_MODE_XTS, + 256, + "AES-128-XTS", + 16, + 0, + 16, + &xts_aes_info +}; + +static const mbedtls_cipher_info_t aes_256_xts_info = { + MBEDTLS_CIPHER_AES_256_XTS, + MBEDTLS_MODE_XTS, + 512, + "AES-256-XTS", + 16, + 0, + 16, + &xts_aes_info +}; +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#if defined(MBEDTLS_GCM_C) +static int gcm_aes_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_gcm_setkey( (mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_AES, + key, key_bitlen ); +} + +static const mbedtls_cipher_base_t gcm_aes_info = { + MBEDTLS_CIPHER_ID_AES, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + gcm_aes_setkey_wrap, + gcm_aes_setkey_wrap, + gcm_ctx_alloc, + gcm_ctx_free, +}; + +static const mbedtls_cipher_info_t aes_128_gcm_info = { + MBEDTLS_CIPHER_AES_128_GCM, + MBEDTLS_MODE_GCM, + 128, + "AES-128-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_aes_info +}; + +static const mbedtls_cipher_info_t aes_192_gcm_info = { + MBEDTLS_CIPHER_AES_192_GCM, + MBEDTLS_MODE_GCM, + 192, + "AES-192-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_aes_info +}; + +static const mbedtls_cipher_info_t aes_256_gcm_info = { + MBEDTLS_CIPHER_AES_256_GCM, + MBEDTLS_MODE_GCM, + 256, + "AES-256-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_aes_info +}; +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CCM_C) +static int ccm_aes_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_ccm_setkey( (mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_AES, + key, key_bitlen ); +} + +static const mbedtls_cipher_base_t ccm_aes_info = { + MBEDTLS_CIPHER_ID_AES, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + ccm_aes_setkey_wrap, + ccm_aes_setkey_wrap, + ccm_ctx_alloc, + ccm_ctx_free, +}; + +static const mbedtls_cipher_info_t aes_128_ccm_info = { + MBEDTLS_CIPHER_AES_128_CCM, + MBEDTLS_MODE_CCM, + 128, + "AES-128-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_aes_info +}; + +static const mbedtls_cipher_info_t aes_192_ccm_info = { + MBEDTLS_CIPHER_AES_192_CCM, + MBEDTLS_MODE_CCM, + 192, + "AES-192-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_aes_info +}; + +static const mbedtls_cipher_info_t aes_256_ccm_info = { + MBEDTLS_CIPHER_AES_256_CCM, + MBEDTLS_MODE_CCM, + 256, + "AES-256-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_aes_info +}; +#endif /* MBEDTLS_CCM_C */ + +#endif /* MBEDTLS_AES_C */ + +#if defined(MBEDTLS_CAMELLIA_C) + +static int camellia_crypt_ecb_wrap( void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_camellia_crypt_ecb( (mbedtls_camellia_context *) ctx, operation, input, + output ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int camellia_crypt_cbc_wrap( void *ctx, mbedtls_operation_t operation, + size_t length, unsigned char *iv, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_camellia_crypt_cbc( (mbedtls_camellia_context *) ctx, operation, length, iv, + input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static int camellia_crypt_cfb128_wrap( void *ctx, mbedtls_operation_t operation, + size_t length, size_t *iv_off, unsigned char *iv, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_camellia_crypt_cfb128( (mbedtls_camellia_context *) ctx, operation, length, + iv_off, iv, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static int camellia_crypt_ctr_wrap( void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_camellia_crypt_ctr( (mbedtls_camellia_context *) ctx, length, nc_off, + nonce_counter, stream_block, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +static int camellia_setkey_dec_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_camellia_setkey_dec( (mbedtls_camellia_context *) ctx, key, key_bitlen ); +} + +static int camellia_setkey_enc_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_camellia_setkey_enc( (mbedtls_camellia_context *) ctx, key, key_bitlen ); +} + +static void * camellia_ctx_alloc( void ) +{ + mbedtls_camellia_context *ctx; + ctx = mbedtls_calloc( 1, sizeof( mbedtls_camellia_context ) ); + + if( ctx == NULL ) + return( NULL ); + + mbedtls_camellia_init( ctx ); + + return( ctx ); +} + +static void camellia_ctx_free( void *ctx ) +{ + mbedtls_camellia_free( (mbedtls_camellia_context *) ctx ); + mbedtls_free( ctx ); +} + +static const mbedtls_cipher_base_t camellia_info = { + MBEDTLS_CIPHER_ID_CAMELLIA, + camellia_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + camellia_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + camellia_crypt_cfb128_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + camellia_crypt_ctr_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + camellia_setkey_enc_wrap, + camellia_setkey_dec_wrap, + camellia_ctx_alloc, + camellia_ctx_free +}; + +static const mbedtls_cipher_info_t camellia_128_ecb_info = { + MBEDTLS_CIPHER_CAMELLIA_128_ECB, + MBEDTLS_MODE_ECB, + 128, + "CAMELLIA-128-ECB", + 0, + 0, + 16, + &camellia_info +}; + +static const mbedtls_cipher_info_t camellia_192_ecb_info = { + MBEDTLS_CIPHER_CAMELLIA_192_ECB, + MBEDTLS_MODE_ECB, + 192, + "CAMELLIA-192-ECB", + 0, + 0, + 16, + &camellia_info +}; + +static const mbedtls_cipher_info_t camellia_256_ecb_info = { + MBEDTLS_CIPHER_CAMELLIA_256_ECB, + MBEDTLS_MODE_ECB, + 256, + "CAMELLIA-256-ECB", + 0, + 0, + 16, + &camellia_info +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t camellia_128_cbc_info = { + MBEDTLS_CIPHER_CAMELLIA_128_CBC, + MBEDTLS_MODE_CBC, + 128, + "CAMELLIA-128-CBC", + 16, + 0, + 16, + &camellia_info +}; + +static const mbedtls_cipher_info_t camellia_192_cbc_info = { + MBEDTLS_CIPHER_CAMELLIA_192_CBC, + MBEDTLS_MODE_CBC, + 192, + "CAMELLIA-192-CBC", + 16, + 0, + 16, + &camellia_info +}; + +static const mbedtls_cipher_info_t camellia_256_cbc_info = { + MBEDTLS_CIPHER_CAMELLIA_256_CBC, + MBEDTLS_MODE_CBC, + 256, + "CAMELLIA-256-CBC", + 16, + 0, + 16, + &camellia_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static const mbedtls_cipher_info_t camellia_128_cfb128_info = { + MBEDTLS_CIPHER_CAMELLIA_128_CFB128, + MBEDTLS_MODE_CFB, + 128, + "CAMELLIA-128-CFB128", + 16, + 0, + 16, + &camellia_info +}; + +static const mbedtls_cipher_info_t camellia_192_cfb128_info = { + MBEDTLS_CIPHER_CAMELLIA_192_CFB128, + MBEDTLS_MODE_CFB, + 192, + "CAMELLIA-192-CFB128", + 16, + 0, + 16, + &camellia_info +}; + +static const mbedtls_cipher_info_t camellia_256_cfb128_info = { + MBEDTLS_CIPHER_CAMELLIA_256_CFB128, + MBEDTLS_MODE_CFB, + 256, + "CAMELLIA-256-CFB128", + 16, + 0, + 16, + &camellia_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static const mbedtls_cipher_info_t camellia_128_ctr_info = { + MBEDTLS_CIPHER_CAMELLIA_128_CTR, + MBEDTLS_MODE_CTR, + 128, + "CAMELLIA-128-CTR", + 16, + 0, + 16, + &camellia_info +}; + +static const mbedtls_cipher_info_t camellia_192_ctr_info = { + MBEDTLS_CIPHER_CAMELLIA_192_CTR, + MBEDTLS_MODE_CTR, + 192, + "CAMELLIA-192-CTR", + 16, + 0, + 16, + &camellia_info +}; + +static const mbedtls_cipher_info_t camellia_256_ctr_info = { + MBEDTLS_CIPHER_CAMELLIA_256_CTR, + MBEDTLS_MODE_CTR, + 256, + "CAMELLIA-256-CTR", + 16, + 0, + 16, + &camellia_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_GCM_C) +static int gcm_camellia_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_gcm_setkey( (mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_CAMELLIA, + key, key_bitlen ); +} + +static const mbedtls_cipher_base_t gcm_camellia_info = { + MBEDTLS_CIPHER_ID_CAMELLIA, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + gcm_camellia_setkey_wrap, + gcm_camellia_setkey_wrap, + gcm_ctx_alloc, + gcm_ctx_free, +}; + +static const mbedtls_cipher_info_t camellia_128_gcm_info = { + MBEDTLS_CIPHER_CAMELLIA_128_GCM, + MBEDTLS_MODE_GCM, + 128, + "CAMELLIA-128-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_camellia_info +}; + +static const mbedtls_cipher_info_t camellia_192_gcm_info = { + MBEDTLS_CIPHER_CAMELLIA_192_GCM, + MBEDTLS_MODE_GCM, + 192, + "CAMELLIA-192-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_camellia_info +}; + +static const mbedtls_cipher_info_t camellia_256_gcm_info = { + MBEDTLS_CIPHER_CAMELLIA_256_GCM, + MBEDTLS_MODE_GCM, + 256, + "CAMELLIA-256-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_camellia_info +}; +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CCM_C) +static int ccm_camellia_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_ccm_setkey( (mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_CAMELLIA, + key, key_bitlen ); +} + +static const mbedtls_cipher_base_t ccm_camellia_info = { + MBEDTLS_CIPHER_ID_CAMELLIA, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + ccm_camellia_setkey_wrap, + ccm_camellia_setkey_wrap, + ccm_ctx_alloc, + ccm_ctx_free, +}; + +static const mbedtls_cipher_info_t camellia_128_ccm_info = { + MBEDTLS_CIPHER_CAMELLIA_128_CCM, + MBEDTLS_MODE_CCM, + 128, + "CAMELLIA-128-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_camellia_info +}; + +static const mbedtls_cipher_info_t camellia_192_ccm_info = { + MBEDTLS_CIPHER_CAMELLIA_192_CCM, + MBEDTLS_MODE_CCM, + 192, + "CAMELLIA-192-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_camellia_info +}; + +static const mbedtls_cipher_info_t camellia_256_ccm_info = { + MBEDTLS_CIPHER_CAMELLIA_256_CCM, + MBEDTLS_MODE_CCM, + 256, + "CAMELLIA-256-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_camellia_info +}; +#endif /* MBEDTLS_CCM_C */ + +#endif /* MBEDTLS_CAMELLIA_C */ + +#if defined(MBEDTLS_ARIA_C) + +static int aria_crypt_ecb_wrap( void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output ) +{ + (void) operation; + return mbedtls_aria_crypt_ecb( (mbedtls_aria_context *) ctx, input, + output ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int aria_crypt_cbc_wrap( void *ctx, mbedtls_operation_t operation, + size_t length, unsigned char *iv, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_aria_crypt_cbc( (mbedtls_aria_context *) ctx, operation, length, iv, + input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static int aria_crypt_cfb128_wrap( void *ctx, mbedtls_operation_t operation, + size_t length, size_t *iv_off, unsigned char *iv, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_aria_crypt_cfb128( (mbedtls_aria_context *) ctx, operation, length, + iv_off, iv, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static int aria_crypt_ctr_wrap( void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_aria_crypt_ctr( (mbedtls_aria_context *) ctx, length, nc_off, + nonce_counter, stream_block, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +static int aria_setkey_dec_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_aria_setkey_dec( (mbedtls_aria_context *) ctx, key, key_bitlen ); +} + +static int aria_setkey_enc_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_aria_setkey_enc( (mbedtls_aria_context *) ctx, key, key_bitlen ); +} + +static void * aria_ctx_alloc( void ) +{ + mbedtls_aria_context *ctx; + ctx = mbedtls_calloc( 1, sizeof( mbedtls_aria_context ) ); + + if( ctx == NULL ) + return( NULL ); + + mbedtls_aria_init( ctx ); + + return( ctx ); +} + +static void aria_ctx_free( void *ctx ) +{ + mbedtls_aria_free( (mbedtls_aria_context *) ctx ); + mbedtls_free( ctx ); +} + +static const mbedtls_cipher_base_t aria_info = { + MBEDTLS_CIPHER_ID_ARIA, + aria_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + aria_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + aria_crypt_cfb128_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + aria_crypt_ctr_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + aria_setkey_enc_wrap, + aria_setkey_dec_wrap, + aria_ctx_alloc, + aria_ctx_free +}; + +static const mbedtls_cipher_info_t aria_128_ecb_info = { + MBEDTLS_CIPHER_ARIA_128_ECB, + MBEDTLS_MODE_ECB, + 128, + "ARIA-128-ECB", + 0, + 0, + 16, + &aria_info +}; + +static const mbedtls_cipher_info_t aria_192_ecb_info = { + MBEDTLS_CIPHER_ARIA_192_ECB, + MBEDTLS_MODE_ECB, + 192, + "ARIA-192-ECB", + 0, + 0, + 16, + &aria_info +}; + +static const mbedtls_cipher_info_t aria_256_ecb_info = { + MBEDTLS_CIPHER_ARIA_256_ECB, + MBEDTLS_MODE_ECB, + 256, + "ARIA-256-ECB", + 0, + 0, + 16, + &aria_info +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t aria_128_cbc_info = { + MBEDTLS_CIPHER_ARIA_128_CBC, + MBEDTLS_MODE_CBC, + 128, + "ARIA-128-CBC", + 16, + 0, + 16, + &aria_info +}; + +static const mbedtls_cipher_info_t aria_192_cbc_info = { + MBEDTLS_CIPHER_ARIA_192_CBC, + MBEDTLS_MODE_CBC, + 192, + "ARIA-192-CBC", + 16, + 0, + 16, + &aria_info +}; + +static const mbedtls_cipher_info_t aria_256_cbc_info = { + MBEDTLS_CIPHER_ARIA_256_CBC, + MBEDTLS_MODE_CBC, + 256, + "ARIA-256-CBC", + 16, + 0, + 16, + &aria_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static const mbedtls_cipher_info_t aria_128_cfb128_info = { + MBEDTLS_CIPHER_ARIA_128_CFB128, + MBEDTLS_MODE_CFB, + 128, + "ARIA-128-CFB128", + 16, + 0, + 16, + &aria_info +}; + +static const mbedtls_cipher_info_t aria_192_cfb128_info = { + MBEDTLS_CIPHER_ARIA_192_CFB128, + MBEDTLS_MODE_CFB, + 192, + "ARIA-192-CFB128", + 16, + 0, + 16, + &aria_info +}; + +static const mbedtls_cipher_info_t aria_256_cfb128_info = { + MBEDTLS_CIPHER_ARIA_256_CFB128, + MBEDTLS_MODE_CFB, + 256, + "ARIA-256-CFB128", + 16, + 0, + 16, + &aria_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static const mbedtls_cipher_info_t aria_128_ctr_info = { + MBEDTLS_CIPHER_ARIA_128_CTR, + MBEDTLS_MODE_CTR, + 128, + "ARIA-128-CTR", + 16, + 0, + 16, + &aria_info +}; + +static const mbedtls_cipher_info_t aria_192_ctr_info = { + MBEDTLS_CIPHER_ARIA_192_CTR, + MBEDTLS_MODE_CTR, + 192, + "ARIA-192-CTR", + 16, + 0, + 16, + &aria_info +}; + +static const mbedtls_cipher_info_t aria_256_ctr_info = { + MBEDTLS_CIPHER_ARIA_256_CTR, + MBEDTLS_MODE_CTR, + 256, + "ARIA-256-CTR", + 16, + 0, + 16, + &aria_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_GCM_C) +static int gcm_aria_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_gcm_setkey( (mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_ARIA, + key, key_bitlen ); +} + +static const mbedtls_cipher_base_t gcm_aria_info = { + MBEDTLS_CIPHER_ID_ARIA, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + gcm_aria_setkey_wrap, + gcm_aria_setkey_wrap, + gcm_ctx_alloc, + gcm_ctx_free, +}; + +static const mbedtls_cipher_info_t aria_128_gcm_info = { + MBEDTLS_CIPHER_ARIA_128_GCM, + MBEDTLS_MODE_GCM, + 128, + "ARIA-128-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_aria_info +}; + +static const mbedtls_cipher_info_t aria_192_gcm_info = { + MBEDTLS_CIPHER_ARIA_192_GCM, + MBEDTLS_MODE_GCM, + 192, + "ARIA-192-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_aria_info +}; + +static const mbedtls_cipher_info_t aria_256_gcm_info = { + MBEDTLS_CIPHER_ARIA_256_GCM, + MBEDTLS_MODE_GCM, + 256, + "ARIA-256-GCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &gcm_aria_info +}; +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CCM_C) +static int ccm_aria_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_ccm_setkey( (mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_ARIA, + key, key_bitlen ); +} + +static const mbedtls_cipher_base_t ccm_aria_info = { + MBEDTLS_CIPHER_ID_ARIA, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + ccm_aria_setkey_wrap, + ccm_aria_setkey_wrap, + ccm_ctx_alloc, + ccm_ctx_free, +}; + +static const mbedtls_cipher_info_t aria_128_ccm_info = { + MBEDTLS_CIPHER_ARIA_128_CCM, + MBEDTLS_MODE_CCM, + 128, + "ARIA-128-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_aria_info +}; + +static const mbedtls_cipher_info_t aria_192_ccm_info = { + MBEDTLS_CIPHER_ARIA_192_CCM, + MBEDTLS_MODE_CCM, + 192, + "ARIA-192-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_aria_info +}; + +static const mbedtls_cipher_info_t aria_256_ccm_info = { + MBEDTLS_CIPHER_ARIA_256_CCM, + MBEDTLS_MODE_CCM, + 256, + "ARIA-256-CCM", + 12, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + 16, + &ccm_aria_info +}; +#endif /* MBEDTLS_CCM_C */ + +#endif /* MBEDTLS_ARIA_C */ + +#if defined(MBEDTLS_DES_C) + +static int des_crypt_ecb_wrap( void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output ) +{ + ((void) operation); + return mbedtls_des_crypt_ecb( (mbedtls_des_context *) ctx, input, output ); +} + +static int des3_crypt_ecb_wrap( void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output ) +{ + ((void) operation); + return mbedtls_des3_crypt_ecb( (mbedtls_des3_context *) ctx, input, output ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int des_crypt_cbc_wrap( void *ctx, mbedtls_operation_t operation, size_t length, + unsigned char *iv, const unsigned char *input, unsigned char *output ) +{ + return mbedtls_des_crypt_cbc( (mbedtls_des_context *) ctx, operation, length, iv, input, + output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int des3_crypt_cbc_wrap( void *ctx, mbedtls_operation_t operation, size_t length, + unsigned char *iv, const unsigned char *input, unsigned char *output ) +{ + return mbedtls_des3_crypt_cbc( (mbedtls_des3_context *) ctx, operation, length, iv, input, + output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +static int des_setkey_dec_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + ((void) key_bitlen); + + return mbedtls_des_setkey_dec( (mbedtls_des_context *) ctx, key ); +} + +static int des_setkey_enc_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + ((void) key_bitlen); + + return mbedtls_des_setkey_enc( (mbedtls_des_context *) ctx, key ); +} + +static int des3_set2key_dec_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + ((void) key_bitlen); + + return mbedtls_des3_set2key_dec( (mbedtls_des3_context *) ctx, key ); +} + +static int des3_set2key_enc_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + ((void) key_bitlen); + + return mbedtls_des3_set2key_enc( (mbedtls_des3_context *) ctx, key ); +} + +static int des3_set3key_dec_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + ((void) key_bitlen); + + return mbedtls_des3_set3key_dec( (mbedtls_des3_context *) ctx, key ); +} + +static int des3_set3key_enc_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + ((void) key_bitlen); + + return mbedtls_des3_set3key_enc( (mbedtls_des3_context *) ctx, key ); +} + +static void * des_ctx_alloc( void ) +{ + mbedtls_des_context *des = mbedtls_calloc( 1, sizeof( mbedtls_des_context ) ); + + if( des == NULL ) + return( NULL ); + + mbedtls_des_init( des ); + + return( des ); +} + +static void des_ctx_free( void *ctx ) +{ + mbedtls_des_free( (mbedtls_des_context *) ctx ); + mbedtls_free( ctx ); +} + +static void * des3_ctx_alloc( void ) +{ + mbedtls_des3_context *des3; + des3 = mbedtls_calloc( 1, sizeof( mbedtls_des3_context ) ); + + if( des3 == NULL ) + return( NULL ); + + mbedtls_des3_init( des3 ); + + return( des3 ); +} + +static void des3_ctx_free( void *ctx ) +{ + mbedtls_des3_free( (mbedtls_des3_context *) ctx ); + mbedtls_free( ctx ); +} + +static const mbedtls_cipher_base_t des_info = { + MBEDTLS_CIPHER_ID_DES, + des_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + des_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + des_setkey_enc_wrap, + des_setkey_dec_wrap, + des_ctx_alloc, + des_ctx_free +}; + +static const mbedtls_cipher_info_t des_ecb_info = { + MBEDTLS_CIPHER_DES_ECB, + MBEDTLS_MODE_ECB, + MBEDTLS_KEY_LENGTH_DES, + "DES-ECB", + 0, + 0, + 8, + &des_info +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t des_cbc_info = { + MBEDTLS_CIPHER_DES_CBC, + MBEDTLS_MODE_CBC, + MBEDTLS_KEY_LENGTH_DES, + "DES-CBC", + 8, + 0, + 8, + &des_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +static const mbedtls_cipher_base_t des_ede_info = { + MBEDTLS_CIPHER_ID_DES, + des3_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + des3_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + des3_set2key_enc_wrap, + des3_set2key_dec_wrap, + des3_ctx_alloc, + des3_ctx_free +}; + +static const mbedtls_cipher_info_t des_ede_ecb_info = { + MBEDTLS_CIPHER_DES_EDE_ECB, + MBEDTLS_MODE_ECB, + MBEDTLS_KEY_LENGTH_DES_EDE, + "DES-EDE-ECB", + 0, + 0, + 8, + &des_ede_info +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t des_ede_cbc_info = { + MBEDTLS_CIPHER_DES_EDE_CBC, + MBEDTLS_MODE_CBC, + MBEDTLS_KEY_LENGTH_DES_EDE, + "DES-EDE-CBC", + 8, + 0, + 8, + &des_ede_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +static const mbedtls_cipher_base_t des_ede3_info = { + MBEDTLS_CIPHER_ID_3DES, + des3_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + des3_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + des3_set3key_enc_wrap, + des3_set3key_dec_wrap, + des3_ctx_alloc, + des3_ctx_free +}; + +static const mbedtls_cipher_info_t des_ede3_ecb_info = { + MBEDTLS_CIPHER_DES_EDE3_ECB, + MBEDTLS_MODE_ECB, + MBEDTLS_KEY_LENGTH_DES_EDE3, + "DES-EDE3-ECB", + 0, + 0, + 8, + &des_ede3_info +}; +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t des_ede3_cbc_info = { + MBEDTLS_CIPHER_DES_EDE3_CBC, + MBEDTLS_MODE_CBC, + MBEDTLS_KEY_LENGTH_DES_EDE3, + "DES-EDE3-CBC", + 8, + 0, + 8, + &des_ede3_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ +#endif /* MBEDTLS_DES_C */ + +#if defined(MBEDTLS_BLOWFISH_C) + +static int blowfish_crypt_ecb_wrap( void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_blowfish_crypt_ecb( (mbedtls_blowfish_context *) ctx, operation, input, + output ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int blowfish_crypt_cbc_wrap( void *ctx, mbedtls_operation_t operation, + size_t length, unsigned char *iv, const unsigned char *input, + unsigned char *output ) +{ + return mbedtls_blowfish_crypt_cbc( (mbedtls_blowfish_context *) ctx, operation, length, iv, + input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static int blowfish_crypt_cfb64_wrap( void *ctx, mbedtls_operation_t operation, + size_t length, size_t *iv_off, unsigned char *iv, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_blowfish_crypt_cfb64( (mbedtls_blowfish_context *) ctx, operation, length, + iv_off, iv, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static int blowfish_crypt_ctr_wrap( void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output ) +{ + return mbedtls_blowfish_crypt_ctr( (mbedtls_blowfish_context *) ctx, length, nc_off, + nonce_counter, stream_block, input, output ); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +static int blowfish_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + return mbedtls_blowfish_setkey( (mbedtls_blowfish_context *) ctx, key, key_bitlen ); +} + +static void * blowfish_ctx_alloc( void ) +{ + mbedtls_blowfish_context *ctx; + ctx = mbedtls_calloc( 1, sizeof( mbedtls_blowfish_context ) ); + + if( ctx == NULL ) + return( NULL ); + + mbedtls_blowfish_init( ctx ); + + return( ctx ); +} + +static void blowfish_ctx_free( void *ctx ) +{ + mbedtls_blowfish_free( (mbedtls_blowfish_context *) ctx ); + mbedtls_free( ctx ); +} + +static const mbedtls_cipher_base_t blowfish_info = { + MBEDTLS_CIPHER_ID_BLOWFISH, + blowfish_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + blowfish_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + blowfish_crypt_cfb64_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + blowfish_crypt_ctr_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + blowfish_setkey_wrap, + blowfish_setkey_wrap, + blowfish_ctx_alloc, + blowfish_ctx_free +}; + +static const mbedtls_cipher_info_t blowfish_ecb_info = { + MBEDTLS_CIPHER_BLOWFISH_ECB, + MBEDTLS_MODE_ECB, + 128, + "BLOWFISH-ECB", + 0, + MBEDTLS_CIPHER_VARIABLE_KEY_LEN, + 8, + &blowfish_info +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t blowfish_cbc_info = { + MBEDTLS_CIPHER_BLOWFISH_CBC, + MBEDTLS_MODE_CBC, + 128, + "BLOWFISH-CBC", + 8, + MBEDTLS_CIPHER_VARIABLE_KEY_LEN, + 8, + &blowfish_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static const mbedtls_cipher_info_t blowfish_cfb64_info = { + MBEDTLS_CIPHER_BLOWFISH_CFB64, + MBEDTLS_MODE_CFB, + 128, + "BLOWFISH-CFB64", + 8, + MBEDTLS_CIPHER_VARIABLE_KEY_LEN, + 8, + &blowfish_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static const mbedtls_cipher_info_t blowfish_ctr_info = { + MBEDTLS_CIPHER_BLOWFISH_CTR, + MBEDTLS_MODE_CTR, + 128, + "BLOWFISH-CTR", + 8, + MBEDTLS_CIPHER_VARIABLE_KEY_LEN, + 8, + &blowfish_info +}; +#endif /* MBEDTLS_CIPHER_MODE_CTR */ +#endif /* MBEDTLS_BLOWFISH_C */ + +#if defined(MBEDTLS_ARC4_C) +static int arc4_crypt_stream_wrap( void *ctx, size_t length, + const unsigned char *input, + unsigned char *output ) +{ + return( mbedtls_arc4_crypt( (mbedtls_arc4_context *) ctx, length, input, output ) ); +} + +static int arc4_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + /* we get key_bitlen in bits, arc4 expects it in bytes */ + if( key_bitlen % 8 != 0 ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + mbedtls_arc4_setup( (mbedtls_arc4_context *) ctx, key, key_bitlen / 8 ); + return( 0 ); +} + +static void * arc4_ctx_alloc( void ) +{ + mbedtls_arc4_context *ctx; + ctx = mbedtls_calloc( 1, sizeof( mbedtls_arc4_context ) ); + + if( ctx == NULL ) + return( NULL ); + + mbedtls_arc4_init( ctx ); + + return( ctx ); +} + +static void arc4_ctx_free( void *ctx ) +{ + mbedtls_arc4_free( (mbedtls_arc4_context *) ctx ); + mbedtls_free( ctx ); +} + +static const mbedtls_cipher_base_t arc4_base_info = { + MBEDTLS_CIPHER_ID_ARC4, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + arc4_crypt_stream_wrap, +#endif + arc4_setkey_wrap, + arc4_setkey_wrap, + arc4_ctx_alloc, + arc4_ctx_free +}; + +static const mbedtls_cipher_info_t arc4_128_info = { + MBEDTLS_CIPHER_ARC4_128, + MBEDTLS_MODE_STREAM, + 128, + "ARC4-128", + 0, + 0, + 1, + &arc4_base_info +}; +#endif /* MBEDTLS_ARC4_C */ + +#if defined(MBEDTLS_CHACHA20_C) + +static int chacha20_setkey_wrap( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + if( key_bitlen != 256U ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + if ( 0 != mbedtls_chacha20_setkey( (mbedtls_chacha20_context*)ctx, key ) ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + return( 0 ); +} + +static int chacha20_stream_wrap( void *ctx, size_t length, + const unsigned char *input, + unsigned char *output ) +{ + int ret; + + ret = mbedtls_chacha20_update( ctx, length, input, output ); + if( ret == MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + return( ret ); +} + +static void * chacha20_ctx_alloc( void ) +{ + mbedtls_chacha20_context *ctx; + ctx = mbedtls_calloc( 1, sizeof( mbedtls_chacha20_context ) ); + + if( ctx == NULL ) + return( NULL ); + + mbedtls_chacha20_init( ctx ); + + return( ctx ); +} + +static void chacha20_ctx_free( void *ctx ) +{ + mbedtls_chacha20_free( (mbedtls_chacha20_context *) ctx ); + mbedtls_free( ctx ); +} + +static const mbedtls_cipher_base_t chacha20_base_info = { + MBEDTLS_CIPHER_ID_CHACHA20, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + chacha20_stream_wrap, +#endif + chacha20_setkey_wrap, + chacha20_setkey_wrap, + chacha20_ctx_alloc, + chacha20_ctx_free +}; +static const mbedtls_cipher_info_t chacha20_info = { + MBEDTLS_CIPHER_CHACHA20, + MBEDTLS_MODE_STREAM, + 256, + "CHACHA20", + 12, + 0, + 1, + &chacha20_base_info +}; +#endif /* MBEDTLS_CHACHA20_C */ + +#if defined(MBEDTLS_CHACHAPOLY_C) + +static int chachapoly_setkey_wrap( void *ctx, + const unsigned char *key, + unsigned int key_bitlen ) +{ + if( key_bitlen != 256U ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + if ( 0 != mbedtls_chachapoly_setkey( (mbedtls_chachapoly_context*)ctx, key ) ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + return( 0 ); +} + +static void * chachapoly_ctx_alloc( void ) +{ + mbedtls_chachapoly_context *ctx; + ctx = mbedtls_calloc( 1, sizeof( mbedtls_chachapoly_context ) ); + + if( ctx == NULL ) + return( NULL ); + + mbedtls_chachapoly_init( ctx ); + + return( ctx ); +} + +static void chachapoly_ctx_free( void *ctx ) +{ + mbedtls_chachapoly_free( (mbedtls_chachapoly_context *) ctx ); + mbedtls_free( ctx ); +} + +static const mbedtls_cipher_base_t chachapoly_base_info = { + MBEDTLS_CIPHER_ID_CHACHA20, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + chachapoly_setkey_wrap, + chachapoly_setkey_wrap, + chachapoly_ctx_alloc, + chachapoly_ctx_free +}; +static const mbedtls_cipher_info_t chachapoly_info = { + MBEDTLS_CIPHER_CHACHA20_POLY1305, + MBEDTLS_MODE_CHACHAPOLY, + 256, + "CHACHA20-POLY1305", + 12, + 0, + 1, + &chachapoly_base_info +}; +#endif /* MBEDTLS_CHACHAPOLY_C */ + +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) +static int null_crypt_stream( void *ctx, size_t length, + const unsigned char *input, + unsigned char *output ) +{ + ((void) ctx); + memmove( output, input, length ); + return( 0 ); +} + +static int null_setkey( void *ctx, const unsigned char *key, + unsigned int key_bitlen ) +{ + ((void) ctx); + ((void) key); + ((void) key_bitlen); + + return( 0 ); +} + +static void * null_ctx_alloc( void ) +{ + return( (void *) 1 ); +} + +static void null_ctx_free( void *ctx ) +{ + ((void) ctx); +} + +static const mbedtls_cipher_base_t null_base_info = { + MBEDTLS_CIPHER_ID_NULL, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + null_crypt_stream, +#endif + null_setkey, + null_setkey, + null_ctx_alloc, + null_ctx_free +}; + +static const mbedtls_cipher_info_t null_cipher_info = { + MBEDTLS_CIPHER_NULL, + MBEDTLS_MODE_STREAM, + 0, + "NULL", + 0, + 0, + 1, + &null_base_info +}; +#endif /* defined(MBEDTLS_CIPHER_NULL_CIPHER) */ + +const mbedtls_cipher_definition_t mbedtls_cipher_definitions[] = +{ +#if defined(MBEDTLS_AES_C) + { MBEDTLS_CIPHER_AES_128_ECB, &aes_128_ecb_info }, + { MBEDTLS_CIPHER_AES_192_ECB, &aes_192_ecb_info }, + { MBEDTLS_CIPHER_AES_256_ECB, &aes_256_ecb_info }, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_AES_128_CBC, &aes_128_cbc_info }, + { MBEDTLS_CIPHER_AES_192_CBC, &aes_192_cbc_info }, + { MBEDTLS_CIPHER_AES_256_CBC, &aes_256_cbc_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + { MBEDTLS_CIPHER_AES_128_CFB128, &aes_128_cfb128_info }, + { MBEDTLS_CIPHER_AES_192_CFB128, &aes_192_cfb128_info }, + { MBEDTLS_CIPHER_AES_256_CFB128, &aes_256_cfb128_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + { MBEDTLS_CIPHER_AES_128_OFB, &aes_128_ofb_info }, + { MBEDTLS_CIPHER_AES_192_OFB, &aes_192_ofb_info }, + { MBEDTLS_CIPHER_AES_256_OFB, &aes_256_ofb_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + { MBEDTLS_CIPHER_AES_128_CTR, &aes_128_ctr_info }, + { MBEDTLS_CIPHER_AES_192_CTR, &aes_192_ctr_info }, + { MBEDTLS_CIPHER_AES_256_CTR, &aes_256_ctr_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + { MBEDTLS_CIPHER_AES_128_XTS, &aes_128_xts_info }, + { MBEDTLS_CIPHER_AES_256_XTS, &aes_256_xts_info }, +#endif +#if defined(MBEDTLS_GCM_C) + { MBEDTLS_CIPHER_AES_128_GCM, &aes_128_gcm_info }, + { MBEDTLS_CIPHER_AES_192_GCM, &aes_192_gcm_info }, + { MBEDTLS_CIPHER_AES_256_GCM, &aes_256_gcm_info }, +#endif +#if defined(MBEDTLS_CCM_C) + { MBEDTLS_CIPHER_AES_128_CCM, &aes_128_ccm_info }, + { MBEDTLS_CIPHER_AES_192_CCM, &aes_192_ccm_info }, + { MBEDTLS_CIPHER_AES_256_CCM, &aes_256_ccm_info }, +#endif +#endif /* MBEDTLS_AES_C */ + +#if defined(MBEDTLS_ARC4_C) + { MBEDTLS_CIPHER_ARC4_128, &arc4_128_info }, +#endif + +#if defined(MBEDTLS_BLOWFISH_C) + { MBEDTLS_CIPHER_BLOWFISH_ECB, &blowfish_ecb_info }, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_BLOWFISH_CBC, &blowfish_cbc_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + { MBEDTLS_CIPHER_BLOWFISH_CFB64, &blowfish_cfb64_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + { MBEDTLS_CIPHER_BLOWFISH_CTR, &blowfish_ctr_info }, +#endif +#endif /* MBEDTLS_BLOWFISH_C */ + +#if defined(MBEDTLS_CAMELLIA_C) + { MBEDTLS_CIPHER_CAMELLIA_128_ECB, &camellia_128_ecb_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_ECB, &camellia_192_ecb_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_ECB, &camellia_256_ecb_info }, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_CAMELLIA_128_CBC, &camellia_128_cbc_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CBC, &camellia_192_cbc_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CBC, &camellia_256_cbc_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + { MBEDTLS_CIPHER_CAMELLIA_128_CFB128, &camellia_128_cfb128_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CFB128, &camellia_192_cfb128_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CFB128, &camellia_256_cfb128_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + { MBEDTLS_CIPHER_CAMELLIA_128_CTR, &camellia_128_ctr_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CTR, &camellia_192_ctr_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CTR, &camellia_256_ctr_info }, +#endif +#if defined(MBEDTLS_GCM_C) + { MBEDTLS_CIPHER_CAMELLIA_128_GCM, &camellia_128_gcm_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_GCM, &camellia_192_gcm_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_GCM, &camellia_256_gcm_info }, +#endif +#if defined(MBEDTLS_CCM_C) + { MBEDTLS_CIPHER_CAMELLIA_128_CCM, &camellia_128_ccm_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CCM, &camellia_192_ccm_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CCM, &camellia_256_ccm_info }, +#endif +#endif /* MBEDTLS_CAMELLIA_C */ + +#if defined(MBEDTLS_ARIA_C) + { MBEDTLS_CIPHER_ARIA_128_ECB, &aria_128_ecb_info }, + { MBEDTLS_CIPHER_ARIA_192_ECB, &aria_192_ecb_info }, + { MBEDTLS_CIPHER_ARIA_256_ECB, &aria_256_ecb_info }, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_ARIA_128_CBC, &aria_128_cbc_info }, + { MBEDTLS_CIPHER_ARIA_192_CBC, &aria_192_cbc_info }, + { MBEDTLS_CIPHER_ARIA_256_CBC, &aria_256_cbc_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + { MBEDTLS_CIPHER_ARIA_128_CFB128, &aria_128_cfb128_info }, + { MBEDTLS_CIPHER_ARIA_192_CFB128, &aria_192_cfb128_info }, + { MBEDTLS_CIPHER_ARIA_256_CFB128, &aria_256_cfb128_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + { MBEDTLS_CIPHER_ARIA_128_CTR, &aria_128_ctr_info }, + { MBEDTLS_CIPHER_ARIA_192_CTR, &aria_192_ctr_info }, + { MBEDTLS_CIPHER_ARIA_256_CTR, &aria_256_ctr_info }, +#endif +#if defined(MBEDTLS_GCM_C) + { MBEDTLS_CIPHER_ARIA_128_GCM, &aria_128_gcm_info }, + { MBEDTLS_CIPHER_ARIA_192_GCM, &aria_192_gcm_info }, + { MBEDTLS_CIPHER_ARIA_256_GCM, &aria_256_gcm_info }, +#endif +#if defined(MBEDTLS_CCM_C) + { MBEDTLS_CIPHER_ARIA_128_CCM, &aria_128_ccm_info }, + { MBEDTLS_CIPHER_ARIA_192_CCM, &aria_192_ccm_info }, + { MBEDTLS_CIPHER_ARIA_256_CCM, &aria_256_ccm_info }, +#endif +#endif /* MBEDTLS_ARIA_C */ + +#if defined(MBEDTLS_DES_C) + { MBEDTLS_CIPHER_DES_ECB, &des_ecb_info }, + { MBEDTLS_CIPHER_DES_EDE_ECB, &des_ede_ecb_info }, + { MBEDTLS_CIPHER_DES_EDE3_ECB, &des_ede3_ecb_info }, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_DES_CBC, &des_cbc_info }, + { MBEDTLS_CIPHER_DES_EDE_CBC, &des_ede_cbc_info }, + { MBEDTLS_CIPHER_DES_EDE3_CBC, &des_ede3_cbc_info }, +#endif +#endif /* MBEDTLS_DES_C */ + +#if defined(MBEDTLS_CHACHA20_C) + { MBEDTLS_CIPHER_CHACHA20, &chacha20_info }, +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + { MBEDTLS_CIPHER_CHACHA20_POLY1305, &chachapoly_info }, +#endif + +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) + { MBEDTLS_CIPHER_NULL, &null_cipher_info }, +#endif /* MBEDTLS_CIPHER_NULL_CIPHER */ + + { MBEDTLS_CIPHER_NONE, NULL } +}; + +#define NUM_CIPHERS sizeof mbedtls_cipher_definitions / sizeof mbedtls_cipher_definitions[0] +int mbedtls_cipher_supported[NUM_CIPHERS]; + +#endif /* MBEDTLS_CIPHER_C */ diff --git a/src/common/mbedtls/library/mbedtls_ecdh.c b/src/common/mbedtls/library/mbedtls_ecdh.c new file mode 100644 index 0000000000..1850bf47ab --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_ecdh.c @@ -0,0 +1,689 @@ +/* + * Elliptic curve Diffie-Hellman + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +/* + * References: + * + * SEC1 https://www.secg.org/index.php?action=secg,docs_secg + * RFC 4492 + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECDH_C) + +#include "mbedtls/ecdh.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#endif + +/* Parameter validation macros based on platform_util.h */ +#define ECDH_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECDH_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) +typedef mbedtls_ecdh_context mbedtls_ecdh_context_mbed; +#endif + +static mbedtls_ecp_group_id mbedtls_ecdh_grp_id( + const mbedtls_ecdh_context *ctx ) +{ +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ctx->grp.id ); +#else + return( ctx->grp_id ); +#endif +} + +#if !defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) +/* + * Generate public key (restartable version) + * + * Note: this internal function relies on its caller preserving the value of + * the output parameter 'd' across continuation calls. This would not be + * acceptable for a public function but is OK here as we control call sites. + */ +static int ecdh_gen_public_restartable( mbedtls_ecp_group *grp, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + + /* If multiplication is in progress, we already generated a privkey */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx == NULL || rs_ctx->rsm == NULL ) +#endif + MBEDTLS_MPI_CHK( mbedtls_ecp_gen_privkey( grp, d, f_rng, p_rng ) ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, Q, d, &grp->G, + f_rng, p_rng, rs_ctx ) ); + +cleanup: + return( ret ); +} + +/* + * Generate public key + */ +int mbedtls_ecdh_gen_public( mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECDH_VALIDATE_RET( grp != NULL ); + ECDH_VALIDATE_RET( d != NULL ); + ECDH_VALIDATE_RET( Q != NULL ); + ECDH_VALIDATE_RET( f_rng != NULL ); + return( ecdh_gen_public_restartable( grp, d, Q, f_rng, p_rng, NULL ) ); +} +#endif /* !MBEDTLS_ECDH_GEN_PUBLIC_ALT */ + +#if !defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) +/* + * Compute shared secret (SEC1 3.3.1) + */ +static int ecdh_compute_shared_restartable( mbedtls_ecp_group *grp, + mbedtls_mpi *z, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_ecp_point P; + + mbedtls_ecp_point_init( &P ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, &P, d, Q, + f_rng, p_rng, rs_ctx ) ); + + if( mbedtls_ecp_is_zero( &P ) ) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( z, &P.X ) ); + +cleanup: + mbedtls_ecp_point_free( &P ); + + return( ret ); +} + +/* + * Compute shared secret (SEC1 3.3.1) + */ +int mbedtls_ecdh_compute_shared( mbedtls_ecp_group *grp, mbedtls_mpi *z, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECDH_VALIDATE_RET( grp != NULL ); + ECDH_VALIDATE_RET( Q != NULL ); + ECDH_VALIDATE_RET( d != NULL ); + ECDH_VALIDATE_RET( z != NULL ); + return( ecdh_compute_shared_restartable( grp, z, Q, d, + f_rng, p_rng, NULL ) ); +} +#endif /* !MBEDTLS_ECDH_COMPUTE_SHARED_ALT */ + +static void ecdh_init_internal( mbedtls_ecdh_context_mbed *ctx ) +{ + mbedtls_ecp_group_init( &ctx->grp ); + mbedtls_mpi_init( &ctx->d ); + mbedtls_ecp_point_init( &ctx->Q ); + mbedtls_ecp_point_init( &ctx->Qp ); + mbedtls_mpi_init( &ctx->z ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_init( &ctx->rs ); +#endif +} + +/* + * Initialize context + */ +void mbedtls_ecdh_init( mbedtls_ecdh_context *ctx ) +{ + ECDH_VALIDATE( ctx != NULL ); + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + ecdh_init_internal( ctx ); + mbedtls_ecp_point_init( &ctx->Vi ); + mbedtls_ecp_point_init( &ctx->Vf ); + mbedtls_mpi_init( &ctx->_d ); +#else + memset( ctx, 0, sizeof( mbedtls_ecdh_context ) ); + + ctx->var = MBEDTLS_ECDH_VARIANT_NONE; +#endif + ctx->point_format = MBEDTLS_ECP_PF_UNCOMPRESSED; +#if defined(MBEDTLS_ECP_RESTARTABLE) + ctx->restart_enabled = 0; +#endif +} + +static int ecdh_setup_internal( mbedtls_ecdh_context_mbed *ctx, + mbedtls_ecp_group_id grp_id ) +{ + int ret; + + ret = mbedtls_ecp_group_load( &ctx->grp, grp_id ); + if( ret != 0 ) + { + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + } + + return( 0 ); +} + +/* + * Setup context + */ +int mbedtls_ecdh_setup( mbedtls_ecdh_context *ctx, mbedtls_ecp_group_id grp_id ) +{ + ECDH_VALIDATE_RET( ctx != NULL ); + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_setup_internal( ctx, grp_id ) ); +#else + switch( grp_id ) + { + default: + ctx->point_format = MBEDTLS_ECP_PF_UNCOMPRESSED; + ctx->var = MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0; + ctx->grp_id = grp_id; + ecdh_init_internal( &ctx->ctx.mbed_ecdh ); + return( ecdh_setup_internal( &ctx->ctx.mbed_ecdh, grp_id ) ); + } +#endif +} + +static void ecdh_free_internal( mbedtls_ecdh_context_mbed *ctx ) +{ + mbedtls_ecp_group_free( &ctx->grp ); + mbedtls_mpi_free( &ctx->d ); + mbedtls_ecp_point_free( &ctx->Q ); + mbedtls_ecp_point_free( &ctx->Qp ); + mbedtls_mpi_free( &ctx->z ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_free( &ctx->rs ); +#endif +} + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Enable restartable operations for context + */ +void mbedtls_ecdh_enable_restart( mbedtls_ecdh_context *ctx ) +{ + ECDH_VALIDATE( ctx != NULL ); + + ctx->restart_enabled = 1; +} +#endif + +/* + * Free context + */ +void mbedtls_ecdh_free( mbedtls_ecdh_context *ctx ) +{ + if( ctx == NULL ) + return; + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + mbedtls_ecp_point_free( &ctx->Vi ); + mbedtls_ecp_point_free( &ctx->Vf ); + mbedtls_mpi_free( &ctx->_d ); + ecdh_free_internal( ctx ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + ecdh_free_internal( &ctx->ctx.mbed_ecdh ); + break; + default: + break; + } + + ctx->point_format = MBEDTLS_ECP_PF_UNCOMPRESSED; + ctx->var = MBEDTLS_ECDH_VARIANT_NONE; + ctx->grp_id = MBEDTLS_ECP_DP_NONE; +#endif +} + +static int ecdh_make_params_internal( mbedtls_ecdh_context_mbed *ctx, + size_t *olen, int point_format, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, + unsigned char *, + size_t), + void *p_rng, + int restart_enabled ) +{ + int ret; + size_t grp_len, pt_len; +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_ctx *rs_ctx = NULL; +#endif + + if( ctx->grp.pbits == 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( restart_enabled ) + rs_ctx = &ctx->rs; +#else + (void) restart_enabled; +#endif + + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ( ret = ecdh_gen_public_restartable( &ctx->grp, &ctx->d, &ctx->Q, + f_rng, p_rng, rs_ctx ) ) != 0 ) + return( ret ); +#else + if( ( ret = mbedtls_ecdh_gen_public( &ctx->grp, &ctx->d, &ctx->Q, + f_rng, p_rng ) ) != 0 ) + return( ret ); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + if( ( ret = mbedtls_ecp_tls_write_group( &ctx->grp, &grp_len, buf, + blen ) ) != 0 ) + return( ret ); + + buf += grp_len; + blen -= grp_len; + + if( ( ret = mbedtls_ecp_tls_write_point( &ctx->grp, &ctx->Q, point_format, + &pt_len, buf, blen ) ) != 0 ) + return( ret ); + + *olen = grp_len + pt_len; + return( 0 ); +} + +/* + * Setup and write the ServerKeyExhange parameters (RFC 4492) + * struct { + * ECParameters curve_params; + * ECPoint public; + * } ServerECDHParams; + */ +int mbedtls_ecdh_make_params( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int restart_enabled = 0; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( olen != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + ECDH_VALIDATE_RET( f_rng != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + restart_enabled = ctx->restart_enabled; +#else + (void) restart_enabled; +#endif + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_make_params_internal( ctx, olen, ctx->point_format, buf, blen, + f_rng, p_rng, restart_enabled ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_make_params_internal( &ctx->ctx.mbed_ecdh, olen, + ctx->point_format, buf, blen, + f_rng, p_rng, + restart_enabled ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +static int ecdh_read_params_internal( mbedtls_ecdh_context_mbed *ctx, + const unsigned char **buf, + const unsigned char *end ) +{ + return( mbedtls_ecp_tls_read_point( &ctx->grp, &ctx->Qp, buf, + end - *buf ) ); +} + +/* + * Read the ServerKeyExhange parameters (RFC 4492) + * struct { + * ECParameters curve_params; + * ECPoint public; + * } ServerECDHParams; + */ +int mbedtls_ecdh_read_params( mbedtls_ecdh_context *ctx, + const unsigned char **buf, + const unsigned char *end ) +{ + int ret; + mbedtls_ecp_group_id grp_id; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + ECDH_VALIDATE_RET( *buf != NULL ); + ECDH_VALIDATE_RET( end != NULL ); + + if( ( ret = mbedtls_ecp_tls_read_group_id( &grp_id, buf, end - *buf ) ) + != 0 ) + return( ret ); + + if( ( ret = mbedtls_ecdh_setup( ctx, grp_id ) ) != 0 ) + return( ret ); + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_read_params_internal( ctx, buf, end ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_read_params_internal( &ctx->ctx.mbed_ecdh, + buf, end ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +static int ecdh_get_params_internal( mbedtls_ecdh_context_mbed *ctx, + const mbedtls_ecp_keypair *key, + mbedtls_ecdh_side side ) +{ + int ret; + + /* If it's not our key, just import the public part as Qp */ + if( side == MBEDTLS_ECDH_THEIRS ) + return( mbedtls_ecp_copy( &ctx->Qp, &key->Q ) ); + + /* Our key: import public (as Q) and private parts */ + if( side != MBEDTLS_ECDH_OURS ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + if( ( ret = mbedtls_ecp_copy( &ctx->Q, &key->Q ) ) != 0 || + ( ret = mbedtls_mpi_copy( &ctx->d, &key->d ) ) != 0 ) + return( ret ); + + return( 0 ); +} + +/* + * Get parameters from a keypair + */ +int mbedtls_ecdh_get_params( mbedtls_ecdh_context *ctx, + const mbedtls_ecp_keypair *key, + mbedtls_ecdh_side side ) +{ + int ret; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( key != NULL ); + ECDH_VALIDATE_RET( side == MBEDTLS_ECDH_OURS || + side == MBEDTLS_ECDH_THEIRS ); + + if( mbedtls_ecdh_grp_id( ctx ) == MBEDTLS_ECP_DP_NONE ) + { + /* This is the first call to get_params(). Set up the context + * for use with the group. */ + if( ( ret = mbedtls_ecdh_setup( ctx, key->grp.id ) ) != 0 ) + return( ret ); + } + else + { + /* This is not the first call to get_params(). Check that the + * current key's group is the same as the context's, which was set + * from the first key's group. */ + if( mbedtls_ecdh_grp_id( ctx ) != key->grp.id ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_get_params_internal( ctx, key, side ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_get_params_internal( &ctx->ctx.mbed_ecdh, + key, side ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +static int ecdh_make_public_internal( mbedtls_ecdh_context_mbed *ctx, + size_t *olen, int point_format, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, + unsigned char *, + size_t), + void *p_rng, + int restart_enabled ) +{ + int ret; +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_ctx *rs_ctx = NULL; +#endif + + if( ctx->grp.pbits == 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( restart_enabled ) + rs_ctx = &ctx->rs; +#else + (void) restart_enabled; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ( ret = ecdh_gen_public_restartable( &ctx->grp, &ctx->d, &ctx->Q, + f_rng, p_rng, rs_ctx ) ) != 0 ) + return( ret ); +#else + if( ( ret = mbedtls_ecdh_gen_public( &ctx->grp, &ctx->d, &ctx->Q, + f_rng, p_rng ) ) != 0 ) + return( ret ); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + return mbedtls_ecp_tls_write_point( &ctx->grp, &ctx->Q, point_format, olen, + buf, blen ); +} + +/* + * Setup and export the client public value + */ +int mbedtls_ecdh_make_public( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int restart_enabled = 0; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( olen != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + ECDH_VALIDATE_RET( f_rng != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + restart_enabled = ctx->restart_enabled; +#endif + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_make_public_internal( ctx, olen, ctx->point_format, buf, blen, + f_rng, p_rng, restart_enabled ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_make_public_internal( &ctx->ctx.mbed_ecdh, olen, + ctx->point_format, buf, blen, + f_rng, p_rng, + restart_enabled ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +static int ecdh_read_public_internal( mbedtls_ecdh_context_mbed *ctx, + const unsigned char *buf, size_t blen ) +{ + int ret; + const unsigned char *p = buf; + + if( ( ret = mbedtls_ecp_tls_read_point( &ctx->grp, &ctx->Qp, &p, + blen ) ) != 0 ) + return( ret ); + + if( (size_t)( p - buf ) != blen ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + return( 0 ); +} + +/* + * Parse and import the client's public value + */ +int mbedtls_ecdh_read_public( mbedtls_ecdh_context *ctx, + const unsigned char *buf, size_t blen ) +{ + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_read_public_internal( ctx, buf, blen ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_read_public_internal( &ctx->ctx.mbed_ecdh, + buf, blen ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +static int ecdh_calc_secret_internal( mbedtls_ecdh_context_mbed *ctx, + size_t *olen, unsigned char *buf, + size_t blen, + int (*f_rng)(void *, + unsigned char *, + size_t), + void *p_rng, + int restart_enabled ) +{ + int ret; +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_ctx *rs_ctx = NULL; +#endif + + if( ctx == NULL || ctx->grp.pbits == 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( restart_enabled ) + rs_ctx = &ctx->rs; +#else + (void) restart_enabled; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ( ret = ecdh_compute_shared_restartable( &ctx->grp, &ctx->z, &ctx->Qp, + &ctx->d, f_rng, p_rng, + rs_ctx ) ) != 0 ) + { + return( ret ); + } +#else + if( ( ret = mbedtls_ecdh_compute_shared( &ctx->grp, &ctx->z, &ctx->Qp, + &ctx->d, f_rng, p_rng ) ) != 0 ) + { + return( ret ); + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + if( mbedtls_mpi_size( &ctx->z ) > blen ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + *olen = ctx->grp.pbits / 8 + ( ( ctx->grp.pbits % 8 ) != 0 ); + return mbedtls_mpi_write_binary( &ctx->z, buf, *olen ); +} + +/* + * Derive and export the shared secret + */ +int mbedtls_ecdh_calc_secret( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int restart_enabled = 0; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( olen != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + restart_enabled = ctx->restart_enabled; +#endif + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_calc_secret_internal( ctx, olen, buf, blen, f_rng, p_rng, + restart_enabled ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_calc_secret_internal( &ctx->ctx.mbed_ecdh, olen, buf, + blen, f_rng, p_rng, + restart_enabled ) ); + default: + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } +#endif +} + +#endif /* MBEDTLS_ECDH_C */ diff --git a/src/common/mbedtls/library/mbedtls_ecdsa.c b/src/common/mbedtls/library/mbedtls_ecdsa.c new file mode 100644 index 0000000000..2291413cd1 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_ecdsa.c @@ -0,0 +1,1012 @@ +/* + * Elliptic curve DSA + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +/* + * References: + * + * SEC1 https://www.secg.org/index.php?action=secg,docs_secg + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECDSA_C) + +#include "mbedtls/ecdsa.h" +#include "mbedtls/asn1write.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +#include "mbedtls/hmac_drbg.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#include "mbedtls/platform_util.h" + +/* Parameter validation macros based on platform_util.h */ +#define ECDSA_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECDSA_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_ECP_RESTARTABLE) + +/* + * Sub-context for ecdsa_verify() + */ +struct mbedtls_ecdsa_restart_ver +{ + mbedtls_mpi u1, u2; /* intermediate values */ + enum { /* what to do next? */ + ecdsa_ver_init = 0, /* getting started */ + ecdsa_ver_muladd, /* muladd step */ + } state; +}; + +/* + * Init verify restart sub-context + */ +static void ecdsa_restart_ver_init( mbedtls_ecdsa_restart_ver_ctx *ctx ) +{ + mbedtls_mpi_init( &ctx->u1 ); + mbedtls_mpi_init( &ctx->u2 ); + ctx->state = ecdsa_ver_init; +} + +/* + * Free the components of a verify restart sub-context + */ +static void ecdsa_restart_ver_free( mbedtls_ecdsa_restart_ver_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_mpi_free( &ctx->u1 ); + mbedtls_mpi_free( &ctx->u2 ); + + ecdsa_restart_ver_init( ctx ); +} + +/* + * Sub-context for ecdsa_sign() + */ +struct mbedtls_ecdsa_restart_sig +{ + int sign_tries; + int key_tries; + mbedtls_mpi k; /* per-signature random */ + mbedtls_mpi r; /* r value */ + enum { /* what to do next? */ + ecdsa_sig_init = 0, /* getting started */ + ecdsa_sig_mul, /* doing ecp_mul() */ + ecdsa_sig_modn, /* mod N computations */ + } state; +}; + +/* + * Init verify sign sub-context + */ +static void ecdsa_restart_sig_init( mbedtls_ecdsa_restart_sig_ctx *ctx ) +{ + ctx->sign_tries = 0; + ctx->key_tries = 0; + mbedtls_mpi_init( &ctx->k ); + mbedtls_mpi_init( &ctx->r ); + ctx->state = ecdsa_sig_init; +} + +/* + * Free the components of a sign restart sub-context + */ +static void ecdsa_restart_sig_free( mbedtls_ecdsa_restart_sig_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_mpi_free( &ctx->k ); + mbedtls_mpi_free( &ctx->r ); +} + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +/* + * Sub-context for ecdsa_sign_det() + */ +struct mbedtls_ecdsa_restart_det +{ + mbedtls_hmac_drbg_context rng_ctx; /* DRBG state */ + enum { /* what to do next? */ + ecdsa_det_init = 0, /* getting started */ + ecdsa_det_sign, /* make signature */ + } state; +}; + +/* + * Init verify sign_det sub-context + */ +static void ecdsa_restart_det_init( mbedtls_ecdsa_restart_det_ctx *ctx ) +{ + mbedtls_hmac_drbg_init( &ctx->rng_ctx ); + ctx->state = ecdsa_det_init; +} + +/* + * Free the components of a sign_det restart sub-context + */ +static void ecdsa_restart_det_free( mbedtls_ecdsa_restart_det_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_hmac_drbg_free( &ctx->rng_ctx ); + + ecdsa_restart_det_init( ctx ); +} +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +#define ECDSA_RS_ECP ( rs_ctx == NULL ? NULL : &rs_ctx->ecp ) + +/* Utility macro for checking and updating ops budget */ +#define ECDSA_BUDGET( ops ) \ + MBEDTLS_MPI_CHK( mbedtls_ecp_check_budget( grp, ECDSA_RS_ECP, ops ) ); + +/* Call this when entering a function that needs its own sub-context */ +#define ECDSA_RS_ENTER( SUB ) do { \ + /* reset ops count for this call if top-level */ \ + if( rs_ctx != NULL && rs_ctx->ecp.depth++ == 0 ) \ + rs_ctx->ecp.ops_done = 0; \ + \ + /* set up our own sub-context if needed */ \ + if( mbedtls_ecp_restart_is_enabled() && \ + rs_ctx != NULL && rs_ctx->SUB == NULL ) \ + { \ + rs_ctx->SUB = mbedtls_calloc( 1, sizeof( *rs_ctx->SUB ) ); \ + if( rs_ctx->SUB == NULL ) \ + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); \ + \ + ecdsa_restart_## SUB ##_init( rs_ctx->SUB ); \ + } \ +} while( 0 ) + +/* Call this when leaving a function that needs its own sub-context */ +#define ECDSA_RS_LEAVE( SUB ) do { \ + /* clear our sub-context when not in progress (done or error) */ \ + if( rs_ctx != NULL && rs_ctx->SUB != NULL && \ + ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) \ + { \ + ecdsa_restart_## SUB ##_free( rs_ctx->SUB ); \ + mbedtls_free( rs_ctx->SUB ); \ + rs_ctx->SUB = NULL; \ + } \ + \ + if( rs_ctx != NULL ) \ + rs_ctx->ecp.depth--; \ +} while( 0 ) + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +#define ECDSA_RS_ECP NULL + +#define ECDSA_BUDGET( ops ) /* no-op; for compatibility */ + +#define ECDSA_RS_ENTER( SUB ) (void) rs_ctx +#define ECDSA_RS_LEAVE( SUB ) (void) rs_ctx + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) || \ + !defined(MBEDTLS_ECDSA_SIGN_ALT) || \ + !defined(MBEDTLS_ECDSA_VERIFY_ALT) +/* + * Derive a suitable integer for group grp from a buffer of length len + * SEC1 4.1.3 step 5 aka SEC1 4.1.4 step 3 + */ +static int derive_mpi( const mbedtls_ecp_group *grp, mbedtls_mpi *x, + const unsigned char *buf, size_t blen ) +{ + int ret; + size_t n_size = ( grp->nbits + 7 ) / 8; + size_t use_size = blen > n_size ? n_size : blen; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( x, buf, use_size ) ); + if( use_size * 8 > grp->nbits ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( x, use_size * 8 - grp->nbits ) ); + + /* While at it, reduce modulo N */ + if( mbedtls_mpi_cmp_mpi( x, &grp->N ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( x, x, &grp->N ) ); + +cleanup: + return( ret ); +} +#endif /* ECDSA_DETERMINISTIC || !ECDSA_SIGN_ALT || !ECDSA_VERIFY_ALT */ + +#if !defined(MBEDTLS_ECDSA_SIGN_ALT) +/* + * Compute ECDSA signature of a hashed message (SEC1 4.1.3) + * Obviously, compared to SEC1 4.1.3, we skip step 4 (hash message) + */ +static int ecdsa_sign_restartable( mbedtls_ecp_group *grp, + mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + int (*f_rng_blind)(void *, unsigned char *, size_t), + void *p_rng_blind, + mbedtls_ecdsa_restart_ctx *rs_ctx ) +{ + int ret, key_tries, sign_tries; + int *p_sign_tries = &sign_tries, *p_key_tries = &key_tries; + mbedtls_ecp_point R; + mbedtls_mpi k, e, t; + mbedtls_mpi *pk = &k, *pr = r; + + /* Fail cleanly on curves such as Curve25519 that can't be used for ECDSA */ + if( grp->N.p == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* Make sure d is in range 1..n-1 */ + if( mbedtls_mpi_cmp_int( d, 1 ) < 0 || mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + mbedtls_ecp_point_init( &R ); + mbedtls_mpi_init( &k ); mbedtls_mpi_init( &e ); mbedtls_mpi_init( &t ); + + ECDSA_RS_ENTER( sig ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->sig != NULL ) + { + /* redirect to our context */ + p_sign_tries = &rs_ctx->sig->sign_tries; + p_key_tries = &rs_ctx->sig->key_tries; + pk = &rs_ctx->sig->k; + pr = &rs_ctx->sig->r; + + /* jump to current step */ + if( rs_ctx->sig->state == ecdsa_sig_mul ) + goto mul; + if( rs_ctx->sig->state == ecdsa_sig_modn ) + goto modn; + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + *p_sign_tries = 0; + do + { + if( (*p_sign_tries)++ > 10 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + + /* + * Steps 1-3: generate a suitable ephemeral keypair + * and set r = xR mod n + */ + *p_key_tries = 0; + do + { + if( (*p_key_tries)++ > 10 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_ecp_gen_privkey( grp, pk, f_rng, p_rng ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->sig != NULL ) + rs_ctx->sig->state = ecdsa_sig_mul; + +mul: +#endif + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, &R, pk, &grp->G, + f_rng_blind, + p_rng_blind, + ECDSA_RS_ECP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( pr, &R.X, &grp->N ) ); + } + while( mbedtls_mpi_cmp_int( pr, 0 ) == 0 ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->sig != NULL ) + rs_ctx->sig->state = ecdsa_sig_modn; + +modn: +#endif + /* + * Accounting for everything up to the end of the loop + * (step 6, but checking now avoids saving e and t) + */ + ECDSA_BUDGET( MBEDTLS_ECP_OPS_INV + 4 ); + + /* + * Step 5: derive MPI from hashed message + */ + MBEDTLS_MPI_CHK( derive_mpi( grp, &e, buf, blen ) ); + + /* + * Generate a random value to blind inv_mod in next step, + * avoiding a potential timing leak. + */ + MBEDTLS_MPI_CHK( mbedtls_ecp_gen_privkey( grp, &t, f_rng_blind, + p_rng_blind ) ); + + /* + * Step 6: compute s = (e + r * d) / k = t (e + rd) / (kt) mod n + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( s, pr, d ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &e, &e, s ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &e, &e, &t ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( pk, pk, &t ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( pk, pk, &grp->N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( s, pk, &grp->N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( s, s, &e ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( s, s, &grp->N ) ); + } + while( mbedtls_mpi_cmp_int( s, 0 ) == 0 ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->sig != NULL ) + mbedtls_mpi_copy( r, pr ); +#endif + +cleanup: + mbedtls_ecp_point_free( &R ); + mbedtls_mpi_free( &k ); mbedtls_mpi_free( &e ); mbedtls_mpi_free( &t ); + + ECDSA_RS_LEAVE( sig ); + + return( ret ); +} + +/* + * Compute ECDSA signature of a hashed message + */ +int mbedtls_ecdsa_sign( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + ECDSA_VALIDATE_RET( grp != NULL ); + ECDSA_VALIDATE_RET( r != NULL ); + ECDSA_VALIDATE_RET( s != NULL ); + ECDSA_VALIDATE_RET( d != NULL ); + ECDSA_VALIDATE_RET( f_rng != NULL ); + ECDSA_VALIDATE_RET( buf != NULL || blen == 0 ); + + /* Use the same RNG for both blinding and ephemeral key generation */ + return( ecdsa_sign_restartable( grp, r, s, d, buf, blen, + f_rng, p_rng, f_rng, p_rng, NULL ) ); +} +#endif /* !MBEDTLS_ECDSA_SIGN_ALT */ + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +/* + * Deterministic signature wrapper + */ +static int ecdsa_sign_det_restartable( mbedtls_ecp_group *grp, + mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + mbedtls_md_type_t md_alg, + int (*f_rng_blind)(void *, unsigned char *, size_t), + void *p_rng_blind, + mbedtls_ecdsa_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_hmac_drbg_context rng_ctx; + mbedtls_hmac_drbg_context *p_rng = &rng_ctx; + unsigned char data[2 * MBEDTLS_ECP_MAX_BYTES]; + size_t grp_len = ( grp->nbits + 7 ) / 8; + const mbedtls_md_info_t *md_info; + mbedtls_mpi h; + + if( ( md_info = mbedtls_md_info_from_type( md_alg ) ) == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &h ); + mbedtls_hmac_drbg_init( &rng_ctx ); + + ECDSA_RS_ENTER( det ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->det != NULL ) + { + /* redirect to our context */ + p_rng = &rs_ctx->det->rng_ctx; + + /* jump to current step */ + if( rs_ctx->det->state == ecdsa_det_sign ) + goto sign; + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + /* Use private key and message hash (reduced) to initialize HMAC_DRBG */ + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( d, data, grp_len ) ); + MBEDTLS_MPI_CHK( derive_mpi( grp, &h, buf, blen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &h, data + grp_len, grp_len ) ); + mbedtls_hmac_drbg_seed_buf( p_rng, md_info, data, 2 * grp_len ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->det != NULL ) + rs_ctx->det->state = ecdsa_det_sign; + +sign: +#endif +#if defined(MBEDTLS_ECDSA_SIGN_ALT) + ret = mbedtls_ecdsa_sign( grp, r, s, d, buf, blen, + mbedtls_hmac_drbg_random, p_rng ); +#else + if( f_rng_blind != NULL ) + ret = ecdsa_sign_restartable( grp, r, s, d, buf, blen, + mbedtls_hmac_drbg_random, p_rng, + f_rng_blind, p_rng_blind, rs_ctx ); + else + { + mbedtls_hmac_drbg_context *p_rng_blind_det; + +#if !defined(MBEDTLS_ECP_RESTARTABLE) + /* + * To avoid reusing rng_ctx and risking incorrect behavior we seed a + * second HMAC-DRBG with the same seed. We also apply a label to avoid + * reusing the bits of the ephemeral key for blinding and eliminate the + * risk that they leak this way. + */ + const char* blind_label = "BLINDING CONTEXT"; + mbedtls_hmac_drbg_context rng_ctx_blind; + + mbedtls_hmac_drbg_init( &rng_ctx_blind ); + p_rng_blind_det = &rng_ctx_blind; + + mbedtls_hmac_drbg_seed_buf( p_rng_blind_det, md_info, + data, 2 * grp_len ); + ret = mbedtls_hmac_drbg_update_ret( p_rng_blind_det, + (const unsigned char*) blind_label, + strlen( blind_label ) ); + if( ret != 0 ) + { + mbedtls_hmac_drbg_free( &rng_ctx_blind ); + goto cleanup; + } +#else + /* + * In the case of restartable computations we would either need to store + * the second RNG in the restart context too or set it up at every + * restart. The first option would penalize the correct application of + * the function and the second would defeat the purpose of the + * restartable feature. + * + * Therefore in this case we reuse the original RNG. This comes with the + * price that the resulting signature might not be a valid deterministic + * ECDSA signature with a very low probability (same magnitude as + * successfully guessing the private key). However even then it is still + * a valid ECDSA signature. + */ + p_rng_blind_det = p_rng; +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + /* + * Since the output of the RNGs is always the same for the same key and + * message, this limits the efficiency of blinding and leaks information + * through side channels. After mbedtls_ecdsa_sign_det() is removed NULL + * won't be a valid value for f_rng_blind anymore. Therefore it should + * be checked by the caller and this branch and check can be removed. + */ + ret = ecdsa_sign_restartable( grp, r, s, d, buf, blen, + mbedtls_hmac_drbg_random, p_rng, + mbedtls_hmac_drbg_random, p_rng_blind_det, + rs_ctx ); + +#if !defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_hmac_drbg_free( &rng_ctx_blind ); +#endif + } +#endif /* MBEDTLS_ECDSA_SIGN_ALT */ + +cleanup: + mbedtls_hmac_drbg_free( &rng_ctx ); + mbedtls_mpi_free( &h ); + + ECDSA_RS_LEAVE( det ); + + return( ret ); +} + +/* + * Deterministic signature wrappers + */ +int mbedtls_ecdsa_sign_det( mbedtls_ecp_group *grp, mbedtls_mpi *r, + mbedtls_mpi *s, const mbedtls_mpi *d, + const unsigned char *buf, size_t blen, + mbedtls_md_type_t md_alg ) +{ + ECDSA_VALIDATE_RET( grp != NULL ); + ECDSA_VALIDATE_RET( r != NULL ); + ECDSA_VALIDATE_RET( s != NULL ); + ECDSA_VALIDATE_RET( d != NULL ); + ECDSA_VALIDATE_RET( buf != NULL || blen == 0 ); + + return( ecdsa_sign_det_restartable( grp, r, s, d, buf, blen, md_alg, + NULL, NULL, NULL ) ); +} + +int mbedtls_ecdsa_sign_det_ext( mbedtls_ecp_group *grp, mbedtls_mpi *r, + mbedtls_mpi *s, const mbedtls_mpi *d, + const unsigned char *buf, size_t blen, + mbedtls_md_type_t md_alg, + int (*f_rng_blind)(void *, unsigned char *, + size_t), + void *p_rng_blind ) +{ + ECDSA_VALIDATE_RET( grp != NULL ); + ECDSA_VALIDATE_RET( r != NULL ); + ECDSA_VALIDATE_RET( s != NULL ); + ECDSA_VALIDATE_RET( d != NULL ); + ECDSA_VALIDATE_RET( buf != NULL || blen == 0 ); + ECDSA_VALIDATE_RET( f_rng_blind != NULL ); + + return( ecdsa_sign_det_restartable( grp, r, s, d, buf, blen, md_alg, + f_rng_blind, p_rng_blind, NULL ) ); +} +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +#if !defined(MBEDTLS_ECDSA_VERIFY_ALT) +/* + * Verify ECDSA signature of hashed message (SEC1 4.1.4) + * Obviously, compared to SEC1 4.1.3, we skip step 2 (hash message) + */ +static int ecdsa_verify_restartable( mbedtls_ecp_group *grp, + const unsigned char *buf, size_t blen, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *r, const mbedtls_mpi *s, + mbedtls_ecdsa_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_mpi e, s_inv, u1, u2; + mbedtls_ecp_point R; + mbedtls_mpi *pu1 = &u1, *pu2 = &u2; + + mbedtls_ecp_point_init( &R ); + mbedtls_mpi_init( &e ); mbedtls_mpi_init( &s_inv ); + mbedtls_mpi_init( &u1 ); mbedtls_mpi_init( &u2 ); + + /* Fail cleanly on curves such as Curve25519 that can't be used for ECDSA */ + if( grp->N.p == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + ECDSA_RS_ENTER( ver ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ver != NULL ) + { + /* redirect to our context */ + pu1 = &rs_ctx->ver->u1; + pu2 = &rs_ctx->ver->u2; + + /* jump to current step */ + if( rs_ctx->ver->state == ecdsa_ver_muladd ) + goto muladd; + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + /* + * Step 1: make sure r and s are in range 1..n-1 + */ + if( mbedtls_mpi_cmp_int( r, 1 ) < 0 || mbedtls_mpi_cmp_mpi( r, &grp->N ) >= 0 || + mbedtls_mpi_cmp_int( s, 1 ) < 0 || mbedtls_mpi_cmp_mpi( s, &grp->N ) >= 0 ) + { + ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; + goto cleanup; + } + + /* + * Step 3: derive MPI from hashed message + */ + MBEDTLS_MPI_CHK( derive_mpi( grp, &e, buf, blen ) ); + + /* + * Step 4: u1 = e / s mod n, u2 = r / s mod n + */ + ECDSA_BUDGET( MBEDTLS_ECP_OPS_CHK + MBEDTLS_ECP_OPS_INV + 2 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &s_inv, s, &grp->N ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( pu1, &e, &s_inv ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( pu1, pu1, &grp->N ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( pu2, r, &s_inv ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( pu2, pu2, &grp->N ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ver != NULL ) + rs_ctx->ver->state = ecdsa_ver_muladd; + +muladd: +#endif + /* + * Step 5: R = u1 G + u2 Q + */ + MBEDTLS_MPI_CHK( mbedtls_ecp_muladd_restartable( grp, + &R, pu1, &grp->G, pu2, Q, ECDSA_RS_ECP ) ); + + if( mbedtls_ecp_is_zero( &R ) ) + { + ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; + goto cleanup; + } + + /* + * Step 6: convert xR to an integer (no-op) + * Step 7: reduce xR mod n (gives v) + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &R.X, &R.X, &grp->N ) ); + + /* + * Step 8: check if v (that is, R.X) is equal to r + */ + if( mbedtls_mpi_cmp_mpi( &R.X, r ) != 0 ) + { + ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; + goto cleanup; + } + +cleanup: + mbedtls_ecp_point_free( &R ); + mbedtls_mpi_free( &e ); mbedtls_mpi_free( &s_inv ); + mbedtls_mpi_free( &u1 ); mbedtls_mpi_free( &u2 ); + + ECDSA_RS_LEAVE( ver ); + + return( ret ); +} + +/* + * Verify ECDSA signature of hashed message + */ +int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp, + const unsigned char *buf, size_t blen, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *r, + const mbedtls_mpi *s) +{ + ECDSA_VALIDATE_RET( grp != NULL ); + ECDSA_VALIDATE_RET( Q != NULL ); + ECDSA_VALIDATE_RET( r != NULL ); + ECDSA_VALIDATE_RET( s != NULL ); + ECDSA_VALIDATE_RET( buf != NULL || blen == 0 ); + + return( ecdsa_verify_restartable( grp, buf, blen, Q, r, s, NULL ) ); +} +#endif /* !MBEDTLS_ECDSA_VERIFY_ALT */ + +/* + * Convert a signature (given by context) to ASN.1 + */ +static int ecdsa_signature_to_asn1( const mbedtls_mpi *r, const mbedtls_mpi *s, + unsigned char *sig, size_t *slen ) +{ + int ret; + unsigned char buf[MBEDTLS_ECDSA_MAX_LEN]; + unsigned char *p = buf + sizeof( buf ); + size_t len = 0; + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_mpi( &p, buf, s ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_mpi( &p, buf, r ) ); + + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( &p, buf, len ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( &p, buf, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ); + + memcpy( sig, p, len ); + *slen = len; + + return( 0 ); +} + +/* + * Compute and write signature + */ +int mbedtls_ecdsa_write_signature_restartable( mbedtls_ecdsa_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hlen, + unsigned char *sig, size_t *slen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecdsa_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_mpi r, s; + ECDSA_VALIDATE_RET( ctx != NULL ); + ECDSA_VALIDATE_RET( hash != NULL ); + ECDSA_VALIDATE_RET( sig != NULL ); + ECDSA_VALIDATE_RET( slen != NULL ); + + mbedtls_mpi_init( &r ); + mbedtls_mpi_init( &s ); + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) + MBEDTLS_MPI_CHK( ecdsa_sign_det_restartable( &ctx->grp, &r, &s, &ctx->d, + hash, hlen, md_alg, f_rng, + p_rng, rs_ctx ) ); +#else + (void) md_alg; + +#if defined(MBEDTLS_ECDSA_SIGN_ALT) + (void) rs_ctx; + + MBEDTLS_MPI_CHK( mbedtls_ecdsa_sign( &ctx->grp, &r, &s, &ctx->d, + hash, hlen, f_rng, p_rng ) ); +#else + /* Use the same RNG for both blinding and ephemeral key generation */ + MBEDTLS_MPI_CHK( ecdsa_sign_restartable( &ctx->grp, &r, &s, &ctx->d, + hash, hlen, f_rng, p_rng, f_rng, + p_rng, rs_ctx ) ); +#endif /* MBEDTLS_ECDSA_SIGN_ALT */ +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + + MBEDTLS_MPI_CHK( ecdsa_signature_to_asn1( &r, &s, sig, slen ) ); + +cleanup: + mbedtls_mpi_free( &r ); + mbedtls_mpi_free( &s ); + + return( ret ); +} + +/* + * Compute and write signature + */ +int mbedtls_ecdsa_write_signature( mbedtls_ecdsa_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hlen, + unsigned char *sig, size_t *slen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECDSA_VALIDATE_RET( ctx != NULL ); + ECDSA_VALIDATE_RET( hash != NULL ); + ECDSA_VALIDATE_RET( sig != NULL ); + ECDSA_VALIDATE_RET( slen != NULL ); + return( mbedtls_ecdsa_write_signature_restartable( + ctx, md_alg, hash, hlen, sig, slen, f_rng, p_rng, NULL ) ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) && \ + defined(MBEDTLS_ECDSA_DETERMINISTIC) +int mbedtls_ecdsa_write_signature_det( mbedtls_ecdsa_context *ctx, + const unsigned char *hash, size_t hlen, + unsigned char *sig, size_t *slen, + mbedtls_md_type_t md_alg ) +{ + ECDSA_VALIDATE_RET( ctx != NULL ); + ECDSA_VALIDATE_RET( hash != NULL ); + ECDSA_VALIDATE_RET( sig != NULL ); + ECDSA_VALIDATE_RET( slen != NULL ); + return( mbedtls_ecdsa_write_signature( ctx, md_alg, hash, hlen, sig, slen, + NULL, NULL ) ); +} +#endif + +/* + * Read and check signature + */ +int mbedtls_ecdsa_read_signature( mbedtls_ecdsa_context *ctx, + const unsigned char *hash, size_t hlen, + const unsigned char *sig, size_t slen ) +{ + ECDSA_VALIDATE_RET( ctx != NULL ); + ECDSA_VALIDATE_RET( hash != NULL ); + ECDSA_VALIDATE_RET( sig != NULL ); + return( mbedtls_ecdsa_read_signature_restartable( + ctx, hash, hlen, sig, slen, NULL ) ); +} + +/* + * Restartable read and check signature + */ +int mbedtls_ecdsa_read_signature_restartable( mbedtls_ecdsa_context *ctx, + const unsigned char *hash, size_t hlen, + const unsigned char *sig, size_t slen, + mbedtls_ecdsa_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char *p = (unsigned char *) sig; + const unsigned char *end = sig + slen; + size_t len; + mbedtls_mpi r, s; + ECDSA_VALIDATE_RET( ctx != NULL ); + ECDSA_VALIDATE_RET( hash != NULL ); + ECDSA_VALIDATE_RET( sig != NULL ); + + mbedtls_mpi_init( &r ); + mbedtls_mpi_init( &s ); + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + ret += MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + + if( p + len != end ) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH; + goto cleanup; + } + + if( ( ret = mbedtls_asn1_get_mpi( &p, end, &r ) ) != 0 || + ( ret = mbedtls_asn1_get_mpi( &p, end, &s ) ) != 0 ) + { + ret += MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } +#if defined(MBEDTLS_ECDSA_VERIFY_ALT) + (void) rs_ctx; + + if( ( ret = mbedtls_ecdsa_verify( &ctx->grp, hash, hlen, + &ctx->Q, &r, &s ) ) != 0 ) + goto cleanup; +#else + if( ( ret = ecdsa_verify_restartable( &ctx->grp, hash, hlen, + &ctx->Q, &r, &s, rs_ctx ) ) != 0 ) + goto cleanup; +#endif /* MBEDTLS_ECDSA_VERIFY_ALT */ + + /* At this point we know that the buffer starts with a valid signature. + * Return 0 if the buffer just contains the signature, and a specific + * error code if the valid signature is followed by more data. */ + if( p != end ) + ret = MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH; + +cleanup: + mbedtls_mpi_free( &r ); + mbedtls_mpi_free( &s ); + + return( ret ); +} + +#if !defined(MBEDTLS_ECDSA_GENKEY_ALT) +/* + * Generate key pair + */ +int mbedtls_ecdsa_genkey( mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret = 0; + ECDSA_VALIDATE_RET( ctx != NULL ); + ECDSA_VALIDATE_RET( f_rng != NULL ); + + ret = mbedtls_ecp_group_load( &ctx->grp, gid ); + if( ret != 0 ) + return( ret ); + + return( mbedtls_ecp_gen_keypair( &ctx->grp, &ctx->d, + &ctx->Q, f_rng, p_rng ) ); +} +#endif /* !MBEDTLS_ECDSA_GENKEY_ALT */ + +/* + * Set context from an mbedtls_ecp_keypair + */ +int mbedtls_ecdsa_from_keypair( mbedtls_ecdsa_context *ctx, const mbedtls_ecp_keypair *key ) +{ + int ret; + ECDSA_VALIDATE_RET( ctx != NULL ); + ECDSA_VALIDATE_RET( key != NULL ); + + if( ( ret = mbedtls_ecp_group_copy( &ctx->grp, &key->grp ) ) != 0 || + ( ret = mbedtls_mpi_copy( &ctx->d, &key->d ) ) != 0 || + ( ret = mbedtls_ecp_copy( &ctx->Q, &key->Q ) ) != 0 ) + { + mbedtls_ecdsa_free( ctx ); + } + + return( ret ); +} + +/* + * Initialize context + */ +void mbedtls_ecdsa_init( mbedtls_ecdsa_context *ctx ) +{ + ECDSA_VALIDATE( ctx != NULL ); + + mbedtls_ecp_keypair_init( ctx ); +} + +/* + * Free context + */ +void mbedtls_ecdsa_free( mbedtls_ecdsa_context *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_ecp_keypair_free( ctx ); +} + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Initialize a restart context + */ +void mbedtls_ecdsa_restart_init( mbedtls_ecdsa_restart_ctx *ctx ) +{ + ECDSA_VALIDATE( ctx != NULL ); + + mbedtls_ecp_restart_init( &ctx->ecp ); + + ctx->ver = NULL; + ctx->sig = NULL; +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) + ctx->det = NULL; +#endif +} + +/* + * Free the components of a restart context + */ +void mbedtls_ecdsa_restart_free( mbedtls_ecdsa_restart_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_ecp_restart_free( &ctx->ecp ); + + ecdsa_restart_ver_free( ctx->ver ); + mbedtls_free( ctx->ver ); + ctx->ver = NULL; + + ecdsa_restart_sig_free( ctx->sig ); + mbedtls_free( ctx->sig ); + ctx->sig = NULL; + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) + ecdsa_restart_det_free( ctx->det ); + mbedtls_free( ctx->det ); + ctx->det = NULL; +#endif +} +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +#endif /* MBEDTLS_ECDSA_C */ diff --git a/src/common/mbedtls/library/mbedtls_ecp.c b/src/common/mbedtls/library/mbedtls_ecp.c new file mode 100644 index 0000000000..12b55ac2bd --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_ecp.c @@ -0,0 +1,3559 @@ +/* + * Elliptic curves over GF(p): generic functions + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +/* + * References: + * + * SEC1 https://www.secg.org/index.php?action=secg,docs_secg + * GECC = Guide to Elliptic Curve Cryptography - Hankerson, Menezes, Vanstone + * FIPS 186-3 https://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf + * RFC 4492 for the related TLS structures and constants + * RFC 7748 for the Curve448 and Curve25519 curve definitions + * + * [Curve25519] https://cr.yp.to/ecdh/curve25519-20060209.pdf + * + * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis + * for elliptic curve cryptosystems. In : Cryptographic Hardware and + * Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302. + * + * + * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to + * render ECC resistant against Side Channel Attacks. IACR Cryptology + * ePrint Archive, 2004, vol. 2004, p. 342. + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +/** + * \brief Function level alternative implementation. + * + * The MBEDTLS_ECP_INTERNAL_ALT macro enables alternative implementations to + * replace certain functions in this module. The alternative implementations are + * typically hardware accelerators and need to activate the hardware before the + * computation starts and deactivate it after it finishes. The + * mbedtls_internal_ecp_init() and mbedtls_internal_ecp_free() functions serve + * this purpose. + * + * To preserve the correct functionality the following conditions must hold: + * + * - The alternative implementation must be activated by + * mbedtls_internal_ecp_init() before any of the replaceable functions is + * called. + * - mbedtls_internal_ecp_free() must \b only be called when the alternative + * implementation is activated. + * - mbedtls_internal_ecp_init() must \b not be called when the alternative + * implementation is activated. + * - Public functions must not return while the alternative implementation is + * activated. + * - Replaceable functions are guarded by \c MBEDTLS_ECP_XXX_ALT macros and + * before calling them an \code if( mbedtls_internal_ecp_grp_capable( grp ) ) + * \endcode ensures that the alternative implementation supports the current + * group. + */ +#if defined(MBEDTLS_ECP_INTERNAL_ALT) +#endif + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#ifndef NVRM +#include "mbedtls/threading.h" +#endif +#include "mbedtls/platform_util.h" +#include "mbedtls/bn_mul.h" + +#ifndef NVRM +#include +#endif + +#if !defined(MBEDTLS_ECP_ALT) + +/* Parameter validation macros based on platform_util.h */ +#define ECP_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECP_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#include "mbedtls/ecp_internal.h" + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) +#if defined(MBEDTLS_HMAC_DRBG_C) +#include "mbedtls/hmac_drbg.h" +#elif defined(MBEDTLS_CTR_DRBG_C) +#include "mbedtls/ctr_drbg.h" +#elif defined(MBEDTLS_SHA512_C) +#include "mbedtls/sha512.h" +#elif defined(MBEDTLS_SHA256_C) +#include "mbedtls/sha256.h" +#else +#error "Invalid configuration detected. Include check_config.h to ensure that the configuration is valid." +#endif +#endif /* MBEDTLS_ECP_NO_INTERNAL_RNG */ + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +#if defined(MBEDTLS_SELF_TEST) +/* + * Counts of point addition and doubling, and field multiplications. + * Used to test resistance of point multiplication to simple timing attacks. + */ +static unsigned long add_count, dbl_count, mul_count; +#endif + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) +/* + * Currently ecp_mul() takes a RNG function as an argument, used for + * side-channel protection, but it can be NULL. The initial reasoning was + * that people will pass non-NULL RNG when they care about side-channels, but + * unfortunately we have some APIs that call ecp_mul() with a NULL RNG, with + * no opportunity for the user to do anything about it. + * + * The obvious strategies for addressing that include: + * - change those APIs so that they take RNG arguments; + * - require a global RNG to be available to all crypto modules. + * + * Unfortunately those would break compatibility. So what we do instead is + * have our own internal DRBG instance, seeded from the secret scalar. + * + * The following is a light-weight abstraction layer for doing that with + * HMAC_DRBG (first choice) or CTR_DRBG. + */ + +#if defined(MBEDTLS_HMAC_DRBG_C) + +/* DRBG context type */ +typedef mbedtls_hmac_drbg_context ecp_drbg_context; + +/* DRBG context init */ +static inline void ecp_drbg_init( ecp_drbg_context *ctx ) +{ + mbedtls_hmac_drbg_init( ctx ); +} + +/* DRBG context free */ +static inline void ecp_drbg_free( ecp_drbg_context *ctx ) +{ + mbedtls_hmac_drbg_free( ctx ); +} + +/* DRBG function */ +static inline int ecp_drbg_random( void *p_rng, + unsigned char *output, size_t output_len ) +{ + return( mbedtls_hmac_drbg_random( p_rng, output, output_len ) ); +} + +/* DRBG context seeding */ +static int ecp_drbg_seed( ecp_drbg_context *ctx, + const mbedtls_mpi *secret, size_t secret_len ) +{ + int ret; + unsigned char secret_bytes[MBEDTLS_ECP_MAX_BYTES]; + /* The list starts with strong hashes */ + const mbedtls_md_type_t md_type = mbedtls_md_list()[0]; + const mbedtls_md_info_t *md_info = mbedtls_md_info_from_type( md_type ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( secret, + secret_bytes, secret_len ) ); + + ret = mbedtls_hmac_drbg_seed_buf( ctx, md_info, secret_bytes, secret_len ); + +cleanup: + mbedtls_platform_zeroize( secret_bytes, secret_len ); + + return( ret ); +} + +#elif defined(MBEDTLS_CTR_DRBG_C) + +/* DRBG context type */ +typedef mbedtls_ctr_drbg_context ecp_drbg_context; + +/* DRBG context init */ +static inline void ecp_drbg_init( ecp_drbg_context *ctx ) +{ + mbedtls_ctr_drbg_init( ctx ); +} + +/* DRBG context free */ +static inline void ecp_drbg_free( ecp_drbg_context *ctx ) +{ + mbedtls_ctr_drbg_free( ctx ); +} + +/* DRBG function */ +static inline int ecp_drbg_random( void *p_rng, + unsigned char *output, size_t output_len ) +{ + return( mbedtls_ctr_drbg_random( p_rng, output, output_len ) ); +} + +/* + * Since CTR_DRBG doesn't have a seed_buf() function the way HMAC_DRBG does, + * we need to pass an entropy function when seeding. So we use a dummy + * function for that, and pass the actual entropy as customisation string. + * (During seeding of CTR_DRBG the entropy input and customisation string are + * concatenated before being used to update the secret state.) + */ +static int ecp_ctr_drbg_null_entropy(void *ctx, unsigned char *out, size_t len) +{ + (void) ctx; + memset( out, 0, len ); + return( 0 ); +} + +/* DRBG context seeding */ +static int ecp_drbg_seed( ecp_drbg_context *ctx, + const mbedtls_mpi *secret, size_t secret_len ) +{ + int ret; + unsigned char secret_bytes[MBEDTLS_ECP_MAX_BYTES]; + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( secret, + secret_bytes, secret_len ) ); + + ret = mbedtls_ctr_drbg_seed( ctx, ecp_ctr_drbg_null_entropy, NULL, + secret_bytes, secret_len ); + +cleanup: + mbedtls_platform_zeroize( secret_bytes, secret_len ); + + return( ret ); +} + +#elif defined(MBEDTLS_SHA512_C) || defined(MBEDTLS_SHA256_C) + +/* This will be used in the self-test function */ +#define ECP_ONE_STEP_KDF + +/* + * We need to expand secret data (the scalar) into a longer stream of bytes. + * + * We'll use the One-Step KDF from NIST SP 800-56C, with option 1 (H is a hash + * function) and empty FixedInfo. (Though we'll make it fit the DRBG API for + * convenience, this is not a full-fledged DRBG, but we don't need one here.) + * + * We need a basic hash abstraction layer to use whatever SHA-2 is available. + */ +#if defined(MBEDTLS_SHA512_C) + +#define HASH_FUNC( in, ilen, out ) mbedtls_sha512_ret( in, ilen, out, 0 ); +#define HASH_BLOCK_BYTES ( 512 / 8 ) + +#elif defined(MBEDTLS_SHA256_C) + +#define HASH_FUNC( in, ilen, out ) mbedtls_sha256_ret( in, ilen, out, 0 ); +#define HASH_BLOCK_BYTES ( 256 / 8 ) + +#endif /* SHA512/SHA256 abstraction */ + +/* + * State consists of a 32-bit counter plus the secret value. + * + * We stored them concatenated in a single buffer as that's what will get + * passed to the hash function. + */ +typedef struct { + size_t total_len; + uint8_t buf[4 + MBEDTLS_ECP_MAX_BYTES]; +} ecp_drbg_context; + +static void ecp_drbg_init( ecp_drbg_context *ctx ) +{ + memset( ctx, 0, sizeof( ecp_drbg_context ) ); +} + +static void ecp_drbg_free( ecp_drbg_context *ctx ) +{ + mbedtls_platform_zeroize( ctx, sizeof( ecp_drbg_context ) ); +} + +static int ecp_drbg_seed( ecp_drbg_context *ctx, + const mbedtls_mpi *secret, size_t secret_len ) +{ + ctx->total_len = 4 + secret_len; + memset( ctx->buf, 0, 4); + return( mbedtls_mpi_write_binary( secret, ctx->buf + 4, secret_len ) ); +} + +static int ecp_drbg_random( void *p_rng, unsigned char *output, size_t output_len ) +{ + ecp_drbg_context *ctx = p_rng; + int ret; + size_t len_done = 0; + uint8_t tmp[HASH_BLOCK_BYTES]; + + while( len_done < output_len ) + { + uint8_t use_len; + + /* This function is only called for coordinate randomisation, which + * happens only twice in a scalar multiplication. Each time needs a + * random value in the range [2, p-1], and gets it by drawing len(p) + * bytes from this function, and retrying up to 10 times if unlucky. + * + * So for the largest curve, each scalar multiplication draws at most + * 20 * 66 bytes. The minimum block size is 32 (SHA-256), so with + * rounding that means a most 20 * 3 blocks. + * + * Since we don't need to draw more that 255 blocks, don't bother + * with carry propagation and just return an error instead. We can + * change that it we even need to draw more blinding values. + */ + ctx->buf[3] += 1; + if( ctx->buf[3] == 0 ) + return( MBEDTLS_ERR_ECP_RANDOM_FAILED ); + + ret = HASH_FUNC( ctx->buf, ctx->total_len, tmp ); + if( ret != 0 ) + return( ret ); + + if( output_len - len_done > HASH_BLOCK_BYTES ) + use_len = HASH_BLOCK_BYTES; + else + use_len = output_len - len_done; + + memcpy( output + len_done, tmp, use_len ); + len_done += use_len; + } + + mbedtls_platform_zeroize( tmp, sizeof( tmp ) ); + + return( 0 ); +} + +#else /* DRBG/SHA modules */ +#error "Invalid configuration detected. Include check_config.h to ensure that the configuration is valid." +#endif /* DRBG/SHA modules */ +#endif /* MBEDTLS_ECP_NO_INTERNAL_RNG */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Maximum number of "basic operations" to be done in a row. + * + * Default value 0 means that ECC operations will not yield. + * Note that regardless of the value of ecp_max_ops, always at + * least one step is performed before yielding. + * + * Setting ecp_max_ops=1 can be suitable for testing purposes + * as it will interrupt computation at all possible points. + */ +static unsigned ecp_max_ops = 0; + +/* + * Set ecp_max_ops + */ +void mbedtls_ecp_set_max_ops( unsigned max_ops ) +{ + ecp_max_ops = max_ops; +} + +/* + * Check if restart is enabled + */ +int mbedtls_ecp_restart_is_enabled( void ) +{ + return( ecp_max_ops != 0 ); +} + +/* + * Restart sub-context for ecp_mul_comb() + */ +struct mbedtls_ecp_restart_mul +{ + mbedtls_ecp_point R; /* current intermediate result */ + size_t i; /* current index in various loops, 0 outside */ + mbedtls_ecp_point *T; /* table for precomputed points */ + unsigned char T_size; /* number of points in table T */ + enum { /* what were we doing last time we returned? */ + ecp_rsm_init = 0, /* nothing so far, dummy initial state */ + ecp_rsm_pre_dbl, /* precompute 2^n multiples */ + ecp_rsm_pre_norm_dbl, /* normalize precomputed 2^n multiples */ + ecp_rsm_pre_add, /* precompute remaining points by adding */ + ecp_rsm_pre_norm_add, /* normalize all precomputed points */ + ecp_rsm_comb_core, /* ecp_mul_comb_core() */ + ecp_rsm_final_norm, /* do the final normalization */ + } state; +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_context drbg_ctx; + unsigned char drbg_seeded; +#endif +}; + +/* + * Init restart_mul sub-context + */ +static void ecp_restart_rsm_init( mbedtls_ecp_restart_mul_ctx *ctx ) +{ + mbedtls_ecp_point_init( &ctx->R ); + ctx->i = 0; + ctx->T = NULL; + ctx->T_size = 0; + ctx->state = ecp_rsm_init; +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_init( &ctx->drbg_ctx ); + ctx->drbg_seeded = 0; +#endif +} + +/* + * Free the components of a restart_mul sub-context + */ +static void ecp_restart_rsm_free( mbedtls_ecp_restart_mul_ctx *ctx ) +{ + unsigned char i; + + if( ctx == NULL ) + return; + + mbedtls_ecp_point_free( &ctx->R ); + + if( ctx->T != NULL ) + { + for( i = 0; i < ctx->T_size; i++ ) + mbedtls_ecp_point_free( ctx->T + i ); + mbedtls_free( ctx->T ); + } + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_free( &ctx->drbg_ctx ); +#endif + + ecp_restart_rsm_init( ctx ); +} + +/* + * Restart context for ecp_muladd() + */ +struct mbedtls_ecp_restart_muladd +{ + mbedtls_ecp_point mP; /* mP value */ + mbedtls_ecp_point R; /* R intermediate result */ + enum { /* what should we do next? */ + ecp_rsma_mul1 = 0, /* first multiplication */ + ecp_rsma_mul2, /* second multiplication */ + ecp_rsma_add, /* addition */ + ecp_rsma_norm, /* normalization */ + } state; +}; + +/* + * Init restart_muladd sub-context + */ +static void ecp_restart_ma_init( mbedtls_ecp_restart_muladd_ctx *ctx ) +{ + mbedtls_ecp_point_init( &ctx->mP ); + mbedtls_ecp_point_init( &ctx->R ); + ctx->state = ecp_rsma_mul1; +} + +/* + * Free the components of a restart_muladd sub-context + */ +static void ecp_restart_ma_free( mbedtls_ecp_restart_muladd_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_ecp_point_free( &ctx->mP ); + mbedtls_ecp_point_free( &ctx->R ); + + ecp_restart_ma_init( ctx ); +} + +/* + * Initialize a restart context + */ +void mbedtls_ecp_restart_init( mbedtls_ecp_restart_ctx *ctx ) +{ + ECP_VALIDATE( ctx != NULL ); + ctx->ops_done = 0; + ctx->depth = 0; + ctx->rsm = NULL; + ctx->ma = NULL; +} + +/* + * Free the components of a restart context + */ +void mbedtls_ecp_restart_free( mbedtls_ecp_restart_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + ecp_restart_rsm_free( ctx->rsm ); + mbedtls_free( ctx->rsm ); + + ecp_restart_ma_free( ctx->ma ); + mbedtls_free( ctx->ma ); + + mbedtls_ecp_restart_init( ctx ); +} + +/* + * Check if we can do the next step + */ +int mbedtls_ecp_check_budget( const mbedtls_ecp_group *grp, + mbedtls_ecp_restart_ctx *rs_ctx, + unsigned ops ) +{ + ECP_VALIDATE_RET( grp != NULL ); + + if( rs_ctx != NULL && ecp_max_ops != 0 ) + { + /* scale depending on curve size: the chosen reference is 256-bit, + * and multiplication is quadratic. Round to the closest integer. */ + if( grp->pbits >= 512 ) + ops *= 4; + else if( grp->pbits >= 384 ) + ops *= 2; + + /* Avoid infinite loops: always allow first step. + * Because of that, however, it's not generally true + * that ops_done <= ecp_max_ops, so the check + * ops_done > ecp_max_ops below is mandatory. */ + if( ( rs_ctx->ops_done != 0 ) && + ( rs_ctx->ops_done > ecp_max_ops || + ops > ecp_max_ops - rs_ctx->ops_done ) ) + { + return( MBEDTLS_ERR_ECP_IN_PROGRESS ); + } + + /* update running count */ + rs_ctx->ops_done += ops; + } + + return( 0 ); +} + +/* Call this when entering a function that needs its own sub-context */ +#define ECP_RS_ENTER( SUB ) do { \ + /* reset ops count for this call if top-level */ \ + if( rs_ctx != NULL && rs_ctx->depth++ == 0 ) \ + rs_ctx->ops_done = 0; \ + \ + /* set up our own sub-context if needed */ \ + if( mbedtls_ecp_restart_is_enabled() && \ + rs_ctx != NULL && rs_ctx->SUB == NULL ) \ + { \ + rs_ctx->SUB = mbedtls_calloc( 1, sizeof( *rs_ctx->SUB ) ); \ + if( rs_ctx->SUB == NULL ) \ + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); \ + \ + ecp_restart_## SUB ##_init( rs_ctx->SUB ); \ + } \ +} while( 0 ) + +/* Call this when leaving a function that needs its own sub-context */ +#define ECP_RS_LEAVE( SUB ) do { \ + /* clear our sub-context when not in progress (done or error) */ \ + if( rs_ctx != NULL && rs_ctx->SUB != NULL && \ + ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) \ + { \ + ecp_restart_## SUB ##_free( rs_ctx->SUB ); \ + mbedtls_free( rs_ctx->SUB ); \ + rs_ctx->SUB = NULL; \ + } \ + \ + if( rs_ctx != NULL ) \ + rs_ctx->depth--; \ +} while( 0 ) + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +#define ECP_RS_ENTER( sub ) (void) rs_ctx; +#define ECP_RS_LEAVE( sub ) (void) rs_ctx; + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#define ECP_SHORTWEIERSTRASS +#endif + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) || \ + defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#define ECP_MONTGOMERY +#endif + +/* + * Curve types: internal for now, might be exposed later + */ +typedef enum +{ + ECP_TYPE_NONE = 0, + ECP_TYPE_SHORT_WEIERSTRASS, /* y^2 = x^3 + a x + b */ + ECP_TYPE_MONTGOMERY, /* y^2 = x^3 + a x^2 + x */ +} ecp_curve_type; + +/* + * List of supported curves: + * - internal ID + * - TLS NamedCurve ID (RFC 4492 sec. 5.1.1, RFC 7071 sec. 2) + * - size in bits + * - readable name + * + * Curves are listed in order: largest curves first, and for a given size, + * fastest curves first. This provides the default order for the SSL module. + * + * Reminder: update profiles in x509_crt.c when adding a new curves! + */ +static const mbedtls_ecp_curve_info ecp_supported_curves[] = +{ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + { MBEDTLS_ECP_DP_SECP521R1, 25, 521, "secp521r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + { MBEDTLS_ECP_DP_BP512R1, 28, 512, "brainpoolP512r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + { MBEDTLS_ECP_DP_SECP384R1, 24, 384, "secp384r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + { MBEDTLS_ECP_DP_BP384R1, 27, 384, "brainpoolP384r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + { MBEDTLS_ECP_DP_SECP256R1, 23, 256, "secp256r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + { MBEDTLS_ECP_DP_SECP256K1, 22, 256, "secp256k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + { MBEDTLS_ECP_DP_BP256R1, 26, 256, "brainpoolP256r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + { MBEDTLS_ECP_DP_SECP224R1, 21, 224, "secp224r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + { MBEDTLS_ECP_DP_SECP224K1, 20, 224, "secp224k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + { MBEDTLS_ECP_DP_SECP192R1, 19, 192, "secp192r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + { MBEDTLS_ECP_DP_SECP192K1, 18, 192, "secp192k1" }, +#endif + { MBEDTLS_ECP_DP_NONE, 0, 0, NULL }, +}; + +#define ECP_NB_CURVES sizeof( ecp_supported_curves ) / \ + sizeof( ecp_supported_curves[0] ) + +static mbedtls_ecp_group_id ecp_supported_grp_id[ECP_NB_CURVES]; + +/* + * List of supported curves and associated info + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list( void ) +{ + return( ecp_supported_curves ); +} + +/* + * List of supported curves, group ID only + */ +const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list( void ) +{ + static int init_done = 0; + + if( ! init_done ) + { + size_t i = 0; + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + ecp_supported_grp_id[i++] = curve_info->grp_id; + } + ecp_supported_grp_id[i] = MBEDTLS_ECP_DP_NONE; + + init_done = 1; + } + + return( ecp_supported_grp_id ); +} + +/* + * Get the curve info for the internal identifier + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id( mbedtls_ecp_group_id grp_id ) +{ + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( curve_info->grp_id == grp_id ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the curve info from the TLS identifier + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id( uint16_t tls_id ) +{ + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( curve_info->tls_id == tls_id ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the curve info from the name + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name( const char *name ) +{ + const mbedtls_ecp_curve_info *curve_info; + + if( name == NULL ) + return( NULL ); + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( strcmp( curve_info->name, name ) == 0 ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the type of a curve + */ +static inline ecp_curve_type ecp_get_type( const mbedtls_ecp_group *grp ) +{ + if( grp->G.X.p == NULL ) + return( ECP_TYPE_NONE ); + + if( grp->G.Y.p == NULL ) + return( ECP_TYPE_MONTGOMERY ); + else + return( ECP_TYPE_SHORT_WEIERSTRASS ); +} + +/* + * Initialize (the components of) a point + */ +void mbedtls_ecp_point_init( mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE( pt != NULL ); + + mbedtls_mpi_init( &pt->X ); + mbedtls_mpi_init( &pt->Y ); + mbedtls_mpi_init( &pt->Z ); +} + +/* + * Initialize (the components of) a group + */ +void mbedtls_ecp_group_init( mbedtls_ecp_group *grp ) +{ + ECP_VALIDATE( grp != NULL ); + + grp->id = MBEDTLS_ECP_DP_NONE; + mbedtls_mpi_init( &grp->P ); + mbedtls_mpi_init( &grp->A ); + mbedtls_mpi_init( &grp->B ); + mbedtls_ecp_point_init( &grp->G ); + mbedtls_mpi_init( &grp->N ); + grp->pbits = 0; + grp->nbits = 0; + grp->h = 0; + grp->modp = NULL; + grp->t_pre = NULL; + grp->t_post = NULL; + grp->t_data = NULL; + grp->T = NULL; + grp->T_size = 0; +} + +/* + * Initialize (the components of) a key pair + */ +void mbedtls_ecp_keypair_init( mbedtls_ecp_keypair *key ) +{ + ECP_VALIDATE( key != NULL ); + + mbedtls_ecp_group_init( &key->grp ); + mbedtls_mpi_init( &key->d ); + mbedtls_ecp_point_init( &key->Q ); +} + +/* + * Unallocate (the components of) a point + */ +void mbedtls_ecp_point_free( mbedtls_ecp_point *pt ) +{ + if( pt == NULL ) + return; + + mbedtls_mpi_free( &( pt->X ) ); + mbedtls_mpi_free( &( pt->Y ) ); + mbedtls_mpi_free( &( pt->Z ) ); +} + +/* + * Unallocate (the components of) a group + */ +void mbedtls_ecp_group_free( mbedtls_ecp_group *grp ) +{ + size_t i; + + if( grp == NULL ) + return; + + if( grp->h != 1 ) + { + mbedtls_mpi_free( &grp->P ); + mbedtls_mpi_free( &grp->A ); + mbedtls_mpi_free( &grp->B ); + mbedtls_ecp_point_free( &grp->G ); + mbedtls_mpi_free( &grp->N ); + } + + if( grp->T != NULL ) + { + for( i = 0; i < grp->T_size; i++ ) + mbedtls_ecp_point_free( &grp->T[i] ); + mbedtls_free( grp->T ); + } + + mbedtls_platform_zeroize( grp, sizeof( mbedtls_ecp_group ) ); +} + +/* + * Unallocate (the components of) a key pair + */ +void mbedtls_ecp_keypair_free( mbedtls_ecp_keypair *key ) +{ + if( key == NULL ) + return; + + mbedtls_ecp_group_free( &key->grp ); + mbedtls_mpi_free( &key->d ); + mbedtls_ecp_point_free( &key->Q ); +} + +/* + * Copy the contents of a point + */ +int mbedtls_ecp_copy( mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret; + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->X, &Q->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->Y, &Q->Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->Z, &Q->Z ) ); + +cleanup: + return( ret ); +} + +/* + * Copy the contents of a group object + */ +int mbedtls_ecp_group_copy( mbedtls_ecp_group *dst, const mbedtls_ecp_group *src ) +{ + ECP_VALIDATE_RET( dst != NULL ); + ECP_VALIDATE_RET( src != NULL ); + + return( mbedtls_ecp_group_load( dst, src->id ) ); +} + +/* + * Set point to zero + */ +int mbedtls_ecp_set_zero( mbedtls_ecp_point *pt ) +{ + int ret; + ECP_VALIDATE_RET( pt != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->X , 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Y , 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z , 0 ) ); + +cleanup: + return( ret ); +} + +/* + * Tell if a point is zero + */ +int mbedtls_ecp_is_zero( mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE_RET( pt != NULL ); + + return( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ); +} + +/* + * Compare two points lazily + */ +int mbedtls_ecp_point_cmp( const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q ) +{ + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + if( mbedtls_mpi_cmp_mpi( &P->X, &Q->X ) == 0 && + mbedtls_mpi_cmp_mpi( &P->Y, &Q->Y ) == 0 && + mbedtls_mpi_cmp_mpi( &P->Z, &Q->Z ) == 0 ) + { + return( 0 ); + } + + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Import a non-zero point from ASCII strings + */ +int mbedtls_ecp_point_read_string( mbedtls_ecp_point *P, int radix, + const char *x, const char *y ) +{ + int ret; + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( x != NULL ); + ECP_VALIDATE_RET( y != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &P->X, radix, x ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &P->Y, radix, y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &P->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Export a point into unsigned binary data (SEC1 2.3.3) + */ +int mbedtls_ecp_point_write_binary( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *P, + int format, size_t *olen, + unsigned char *buf, size_t buflen ) +{ + int ret = 0; + size_t plen; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( format == MBEDTLS_ECP_PF_UNCOMPRESSED || + format == MBEDTLS_ECP_PF_COMPRESSED ); + + /* + * Common case: P == 0 + */ + if( mbedtls_mpi_cmp_int( &P->Z, 0 ) == 0 ) + { + if( buflen < 1 ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x00; + *olen = 1; + + return( 0 ); + } + + plen = mbedtls_mpi_size( &grp->P ); + + if( format == MBEDTLS_ECP_PF_UNCOMPRESSED ) + { + *olen = 2 * plen + 1; + + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x04; + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->X, buf + 1, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->Y, buf + 1 + plen, plen ) ); + } + else if( format == MBEDTLS_ECP_PF_COMPRESSED ) + { + *olen = plen + 1; + + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x02 + mbedtls_mpi_get_bit( &P->Y, 0 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->X, buf + 1, plen ) ); + } + +cleanup: + return( ret ); +} + +/* + * Import a point from unsigned binary data (SEC1 2.3.4) + */ +int mbedtls_ecp_point_read_binary( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char *buf, size_t ilen ) +{ + int ret; + size_t plen; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + + if( ilen < 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + if( buf[0] == 0x00 ) + { + if( ilen == 1 ) + return( mbedtls_ecp_set_zero( pt ) ); + else + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + plen = mbedtls_mpi_size( &grp->P ); + + if( buf[0] != 0x04 ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + if( ilen != 2 * plen + 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &pt->X, buf + 1, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &pt->Y, buf + 1 + plen, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Import a point from a TLS ECPoint record (RFC 4492) + * struct { + * opaque point <1..2^8-1>; + * } ECPoint; + */ +int mbedtls_ecp_tls_read_point( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char **buf, size_t buf_len ) +{ + unsigned char data_len; + const unsigned char *buf_start; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + /* + * We must have at least two bytes (1 for length, at least one for data) + */ + if( buf_len < 2 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + data_len = *(*buf)++; + if( data_len < 1 || data_len > buf_len - 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * Save buffer start for read_binary and update buf + */ + buf_start = *buf; + *buf += data_len; + + return( mbedtls_ecp_point_read_binary( grp, pt, buf_start, data_len ) ); +} + +/* + * Export a point as a TLS ECPoint record (RFC 4492) + * struct { + * opaque point <1..2^8-1>; + * } ECPoint; + */ +int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt, + int format, size_t *olen, + unsigned char *buf, size_t blen ) +{ + int ret; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( format == MBEDTLS_ECP_PF_UNCOMPRESSED || + format == MBEDTLS_ECP_PF_COMPRESSED ); + + /* + * buffer length must be at least one, for our length byte + */ + if( blen < 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + if( ( ret = mbedtls_ecp_point_write_binary( grp, pt, format, + olen, buf + 1, blen - 1) ) != 0 ) + return( ret ); + + /* + * write length to the first byte and update total length + */ + buf[0] = (unsigned char) *olen; + ++*olen; + + return( 0 ); +} + +/* + * Set a group from an ECParameters record (RFC 4492) + */ +int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp, + const unsigned char **buf, size_t len ) +{ + int ret; + mbedtls_ecp_group_id grp_id; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + if( ( ret = mbedtls_ecp_tls_read_group_id( &grp_id, buf, len ) ) != 0 ) + return( ret ); + + return( mbedtls_ecp_group_load( grp, grp_id ) ); +} + +/* + * Read a group id from an ECParameters record (RFC 4492) and convert it to + * mbedtls_ecp_group_id. + */ +int mbedtls_ecp_tls_read_group_id( mbedtls_ecp_group_id *grp, + const unsigned char **buf, size_t len ) +{ + uint16_t tls_id; + const mbedtls_ecp_curve_info *curve_info; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + /* + * We expect at least three bytes (see below) + */ + if( len < 3 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * First byte is curve_type; only named_curve is handled + */ + if( *(*buf)++ != MBEDTLS_ECP_TLS_NAMED_CURVE ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * Next two bytes are the namedcurve value + */ + tls_id = *(*buf)++; + tls_id <<= 8; + tls_id |= *(*buf)++; + + if( ( curve_info = mbedtls_ecp_curve_info_from_tls_id( tls_id ) ) == NULL ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + *grp = curve_info->grp_id; + + return( 0 ); +} + +/* + * Write the ECParameters record corresponding to a group (RFC 4492) + */ +int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp, size_t *olen, + unsigned char *buf, size_t blen ) +{ + const mbedtls_ecp_curve_info *curve_info; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + + if( ( curve_info = mbedtls_ecp_curve_info_from_grp_id( grp->id ) ) == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * We are going to write 3 bytes (see below) + */ + *olen = 3; + if( blen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + /* + * First byte is curve_type, always named_curve + */ + *buf++ = MBEDTLS_ECP_TLS_NAMED_CURVE; + + /* + * Next two bytes are the namedcurve value + */ + buf[0] = curve_info->tls_id >> 8; + buf[1] = curve_info->tls_id & 0xFF; + + return( 0 ); +} + +/* + * Wrapper around fast quasi-modp functions, with fall-back to mbedtls_mpi_mod_mpi. + * See the documentation of struct mbedtls_ecp_group. + * + * This function is in the critial loop for mbedtls_ecp_mul, so pay attention to perf. + */ +static int ecp_modp( mbedtls_mpi *N, const mbedtls_ecp_group *grp ) +{ + int ret; + + if( grp->modp == NULL ) + return( mbedtls_mpi_mod_mpi( N, N, &grp->P ) ); + + /* N->s < 0 is a much faster test, which fails only if N is 0 */ + if( ( N->s < 0 && mbedtls_mpi_cmp_int( N, 0 ) != 0 ) || + mbedtls_mpi_bitlen( N ) > 2 * grp->pbits ) + { + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + MBEDTLS_MPI_CHK( grp->modp( N ) ); + + /* N->s < 0 is a much faster test, which fails only if N is 0 */ + while( N->s < 0 && mbedtls_mpi_cmp_int( N, 0 ) != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &grp->P ) ); + + while( mbedtls_mpi_cmp_mpi( N, &grp->P ) >= 0 ) + /* we known P, N and the result are positive */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( N, N, &grp->P ) ); + +cleanup: + return( ret ); +} + +/* + * Fast mod-p functions expect their argument to be in the 0..p^2 range. + * + * In order to guarantee that, we need to ensure that operands of + * mbedtls_mpi_mul_mpi are in the 0..p range. So, after each operation we will + * bring the result back to this range. + * + * The following macros are shortcuts for doing that. + */ + +/* + * Reduce a mbedtls_mpi mod p in-place, general case, to use after mbedtls_mpi_mul_mpi + */ +#if defined(MBEDTLS_SELF_TEST) +#define INC_MUL_COUNT mul_count++; +#else +#define INC_MUL_COUNT +#endif + +#define MOD_MUL( N ) \ + do \ + { \ + MBEDTLS_MPI_CHK( ecp_modp( &(N), grp ) ); \ + INC_MUL_COUNT \ + } while( 0 ) + +/* + * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_sub_mpi + * N->s < 0 is a very fast test, which fails only if N is 0 + */ +#define MOD_SUB( N ) \ + while( (N).s < 0 && mbedtls_mpi_cmp_int( &(N), 0 ) != 0 ) \ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &(N), &(N), &grp->P ) ) + +/* + * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_add_mpi and mbedtls_mpi_mul_int. + * We known P, N and the result are positive, so sub_abs is correct, and + * a bit faster. + */ +#define MOD_ADD( N ) \ + while( mbedtls_mpi_cmp_mpi( &(N), &grp->P ) >= 0 ) \ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( &(N), &(N), &grp->P ) ) + +#if defined(ECP_SHORTWEIERSTRASS) +/* + * For curves in short Weierstrass form, we do all the internal operations in + * Jacobian coordinates. + * + * For multiplication, we'll use a comb method with coutermeasueres against + * SPA, hence timing attacks. + */ + +/* + * Normalize jacobian coordinates so that Z == 0 || Z == 1 (GECC 3.2.1) + * Cost: 1N := 1I + 3M + 1S + */ +static int ecp_normalize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt ) +{ + int ret; + mbedtls_mpi Zi, ZZi; + + if( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ) + return( 0 ); + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_jac( grp, pt ) ); +#endif /* MBEDTLS_ECP_NORMALIZE_JAC_ALT */ + + mbedtls_mpi_init( &Zi ); mbedtls_mpi_init( &ZZi ); + + /* + * X = X / Z^2 mod p + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &Zi, &pt->Z, &grp->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ZZi, &Zi, &Zi ) ); MOD_MUL( ZZi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->X, &pt->X, &ZZi ) ); MOD_MUL( pt->X ); + + /* + * Y = Y / Z^3 mod p + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &ZZi ) ); MOD_MUL( pt->Y ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &Zi ) ); MOD_MUL( pt->Y ); + + /* + * Z = 1 + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + +cleanup: + + mbedtls_mpi_free( &Zi ); mbedtls_mpi_free( &ZZi ); + + return( ret ); +} + +/* + * Normalize jacobian coordinates of an array of (pointers to) points, + * using Montgomery's trick to perform only one inversion mod P. + * (See for example Cohen's "A Course in Computational Algebraic Number + * Theory", Algorithm 10.3.4.) + * + * Warning: fails (returning an error) if one of the points is zero! + * This should never happen, see choice of w in ecp_mul_comb(). + * + * Cost: 1N(t) := 1I + (6t - 3)M + 1S + */ +static int ecp_normalize_jac_many( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *T[], size_t T_size ) +{ + int ret; + size_t i; + mbedtls_mpi *c, u, Zi, ZZi; + + if( T_size < 2 ) + return( ecp_normalize_jac( grp, *T ) ); + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_jac_many( grp, T, T_size ) ); +#endif + + if( ( c = mbedtls_calloc( T_size, sizeof( mbedtls_mpi ) ) ) == NULL ) + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); + + for( i = 0; i < T_size; i++ ) + mbedtls_mpi_init( &c[i] ); + + mbedtls_mpi_init( &u ); mbedtls_mpi_init( &Zi ); mbedtls_mpi_init( &ZZi ); + + /* + * c[i] = Z_0 * ... * Z_i + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &c[0], &T[0]->Z ) ); + for( i = 1; i < T_size; i++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &c[i], &c[i-1], &T[i]->Z ) ); + MOD_MUL( c[i] ); + } + + /* + * u = 1 / (Z_0 * ... * Z_n) mod P + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &u, &c[T_size-1], &grp->P ) ); + + for( i = T_size - 1; ; i-- ) + { + /* + * Zi = 1 / Z_i mod p + * u = 1 / (Z_0 * ... * Z_i) mod P + */ + if( i == 0 ) { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Zi, &u ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &Zi, &u, &c[i-1] ) ); MOD_MUL( Zi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &u, &u, &T[i]->Z ) ); MOD_MUL( u ); + } + + /* + * proceed as in normalize() + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ZZi, &Zi, &Zi ) ); MOD_MUL( ZZi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->X, &T[i]->X, &ZZi ) ); MOD_MUL( T[i]->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->Y, &T[i]->Y, &ZZi ) ); MOD_MUL( T[i]->Y ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->Y, &T[i]->Y, &Zi ) ); MOD_MUL( T[i]->Y ); + + /* + * Post-precessing: reclaim some memory by shrinking coordinates + * - not storing Z (always 1) + * - shrinking other coordinates, but still keeping the same number of + * limbs as P, as otherwise it will too likely be regrown too fast. + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shrink( &T[i]->X, grp->P.n ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shrink( &T[i]->Y, grp->P.n ) ); + mbedtls_mpi_free( &T[i]->Z ); + + if( i == 0 ) + break; + } + +cleanup: + + mbedtls_mpi_free( &u ); mbedtls_mpi_free( &Zi ); mbedtls_mpi_free( &ZZi ); + for( i = 0; i < T_size; i++ ) + mbedtls_mpi_free( &c[i] ); + mbedtls_free( c ); + + return( ret ); +} + +/* + * Conditional point inversion: Q -> -Q = (Q.X, -Q.Y, Q.Z) without leak. + * "inv" must be 0 (don't invert) or 1 (invert) or the result will be invalid + */ +static int ecp_safe_invert_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *Q, + unsigned char inv ) +{ + int ret; + unsigned char nonzero; + mbedtls_mpi mQY; + + mbedtls_mpi_init( &mQY ); + + /* Use the fact that -Q.Y mod P = P - Q.Y unless Q.Y == 0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &mQY, &grp->P, &Q->Y ) ); + nonzero = mbedtls_mpi_cmp_int( &Q->Y, 0 ) != 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &Q->Y, &mQY, inv & nonzero ) ); + +cleanup: + mbedtls_mpi_free( &mQY ); + + return( ret ); +} + +/* + * Point doubling R = 2 P, Jacobian coordinates + * + * Based on https://www.hyperelliptic.org/EFD/g1p/auto-shortw-jacobian.html#doubling-dbl-1998-cmo-2 . + * + * We follow the variable naming fairly closely. The formula variations that trade a MUL for a SQR + * (plus a few ADDs) aren't useful as our bignum implementation doesn't distinguish squaring. + * + * Standard optimizations are applied when curve parameter A is one of { 0, -3 }. + * + * Cost: 1D := 3M + 4S (A == 0) + * 4M + 4S (A == -3) + * 3M + 6S + 1a otherwise + */ +static int ecp_double_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point *P ) +{ + int ret; + mbedtls_mpi M, S, T, U; + +#if defined(MBEDTLS_SELF_TEST) + dbl_count++; +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_double_jac( grp, R, P ) ); +#endif /* MBEDTLS_ECP_DOUBLE_JAC_ALT */ + + mbedtls_mpi_init( &M ); mbedtls_mpi_init( &S ); mbedtls_mpi_init( &T ); mbedtls_mpi_init( &U ); + + /* Special case for A = -3 */ + if( grp->A.p == NULL ) + { + /* M = 3(X + Z^2)(X - Z^2) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->Z, &P->Z ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &T, &P->X, &S ) ); MOD_ADD( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &U, &P->X, &S ) ); MOD_SUB( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &T, &U ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &S, 3 ) ); MOD_ADD( M ); + } + else + { + /* M = 3.X^2 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->X, &P->X ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &S, 3 ) ); MOD_ADD( M ); + + /* Optimize away for "koblitz" curves with A = 0 */ + if( mbedtls_mpi_cmp_int( &grp->A, 0 ) != 0 ) + { + /* M += A.Z^4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->Z, &P->Z ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &S, &S ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &T, &grp->A ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &M, &M, &S ) ); MOD_ADD( M ); + } + } + + /* S = 4.X.Y^2 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &P->Y, &P->Y ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &T, 1 ) ); MOD_ADD( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->X, &T ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &S, 1 ) ); MOD_ADD( S ); + + /* U = 8.Y^4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &U, &T, &T ) ); MOD_MUL( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &U, 1 ) ); MOD_ADD( U ); + + /* T = M^2 - 2.S */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &M, &M ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T, &T, &S ) ); MOD_SUB( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T, &T, &S ) ); MOD_SUB( T ); + + /* S = M(S - T) - U */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S, &S, &T ) ); MOD_SUB( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &S, &M ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S, &S, &U ) ); MOD_SUB( S ); + + /* U = 2.Y.Z */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &U, &P->Y, &P->Z ) ); MOD_MUL( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &U, 1 ) ); MOD_ADD( U ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->X, &T ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Y, &S ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Z, &U ) ); + +cleanup: + mbedtls_mpi_free( &M ); mbedtls_mpi_free( &S ); mbedtls_mpi_free( &T ); mbedtls_mpi_free( &U ); + + return( ret ); +} + +/* + * Addition: R = P + Q, mixed affine-Jacobian coordinates (GECC 3.22) + * + * The coordinates of Q must be normalized (= affine), + * but those of P don't need to. R is not normalized. + * + * Special cases: (1) P or Q is zero, (2) R is zero, (3) P == Q. + * None of these cases can happen as intermediate step in ecp_mul_comb(): + * - at each step, P, Q and R are multiples of the base point, the factor + * being less than its order, so none of them is zero; + * - Q is an odd multiple of the base point, P an even multiple, + * due to the choice of precomputed points in the modified comb method. + * So branches for these cases do not leak secret information. + * + * We accept Q->Z being unset (saving memory in tables) as meaning 1. + * + * Cost: 1A := 8M + 3S + */ +static int ecp_add_mixed( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret; + mbedtls_mpi T1, T2, T3, T4, X, Y, Z; + +#if defined(MBEDTLS_SELF_TEST) + add_count++; +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_add_mixed( grp, R, P, Q ) ); +#endif /* MBEDTLS_ECP_ADD_MIXED_ALT */ + + /* + * Trivial cases: P == 0 or Q == 0 (case 1) + */ + if( mbedtls_mpi_cmp_int( &P->Z, 0 ) == 0 ) + return( mbedtls_ecp_copy( R, Q ) ); + + if( Q->Z.p != NULL && mbedtls_mpi_cmp_int( &Q->Z, 0 ) == 0 ) + return( mbedtls_ecp_copy( R, P ) ); + + /* + * Make sure Q coordinates are normalized + */ + if( Q->Z.p != NULL && mbedtls_mpi_cmp_int( &Q->Z, 1 ) != 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &T1 ); mbedtls_mpi_init( &T2 ); mbedtls_mpi_init( &T3 ); mbedtls_mpi_init( &T4 ); + mbedtls_mpi_init( &X ); mbedtls_mpi_init( &Y ); mbedtls_mpi_init( &Z ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T1, &P->Z, &P->Z ) ); MOD_MUL( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T2, &T1, &P->Z ) ); MOD_MUL( T2 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T1, &T1, &Q->X ) ); MOD_MUL( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T2, &T2, &Q->Y ) ); MOD_MUL( T2 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T1, &T1, &P->X ) ); MOD_SUB( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T2, &T2, &P->Y ) ); MOD_SUB( T2 ); + + /* Special cases (2) and (3) */ + if( mbedtls_mpi_cmp_int( &T1, 0 ) == 0 ) + { + if( mbedtls_mpi_cmp_int( &T2, 0 ) == 0 ) + { + ret = ecp_double_jac( grp, R, P ); + goto cleanup; + } + else + { + ret = mbedtls_ecp_set_zero( R ); + goto cleanup; + } + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &Z, &P->Z, &T1 ) ); MOD_MUL( Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T1, &T1 ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T4, &T3, &T1 ) ); MOD_MUL( T4 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T3, &P->X ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T1, &T3, 2 ) ); MOD_ADD( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &X, &T2, &T2 ) ); MOD_MUL( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &T1 ) ); MOD_SUB( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &T4 ) ); MOD_SUB( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T3, &T3, &X ) ); MOD_SUB( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T3, &T2 ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T4, &T4, &P->Y ) ); MOD_MUL( T4 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &Y, &T3, &T4 ) ); MOD_SUB( Y ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->X, &X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Y, &Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Z, &Z ) ); + +cleanup: + + mbedtls_mpi_free( &T1 ); mbedtls_mpi_free( &T2 ); mbedtls_mpi_free( &T3 ); mbedtls_mpi_free( &T4 ); + mbedtls_mpi_free( &X ); mbedtls_mpi_free( &Y ); mbedtls_mpi_free( &Z ); + + return( ret ); +} + +/* + * Randomize jacobian coordinates: + * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_jac(). + * + * This countermeasure was first suggested in [2]. + */ +static int ecp_randomize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + mbedtls_mpi l, ll; + size_t p_size; + int count = 0; + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_randomize_jac( grp, pt, f_rng, p_rng ) ); +#endif /* MBEDTLS_ECP_RANDOMIZE_JAC_ALT */ + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); mbedtls_mpi_init( &ll ); + + /* Generate l such that 1 < l < p */ + do + { + if( count++ > 30 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, ( p_size * 8 ) - grp->pbits ) ); + } + while( ( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ) || + ( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) ); + + /* Z = l * Z */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Z, &pt->Z, &l ) ); MOD_MUL( pt->Z ); + + /* X = l^2 * X */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ll, &l, &l ) ); MOD_MUL( ll ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->X, &pt->X, &ll ) ); MOD_MUL( pt->X ); + + /* Y = l^3 * Y */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ll, &ll, &l ) ); MOD_MUL( ll ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &ll ) ); MOD_MUL( pt->Y ); + +cleanup: + mbedtls_mpi_free( &l ); mbedtls_mpi_free( &ll ); + + return( ret ); +} + +/* + * Check and define parameters used by the comb method (see below for details) + */ +#if MBEDTLS_ECP_WINDOW_SIZE < 2 || MBEDTLS_ECP_WINDOW_SIZE > 7 +#error "MBEDTLS_ECP_WINDOW_SIZE out of bounds" +#endif + +/* d = ceil( n / w ) */ +#define COMB_MAX_D ( MBEDTLS_ECP_MAX_BITS + 1 ) / 2 + +/* number of precomputed points */ +#define COMB_MAX_PRE ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + +/* + * Compute the representation of m that will be used with our comb method. + * + * The basic comb method is described in GECC 3.44 for example. We use a + * modified version that provides resistance to SPA by avoiding zero + * digits in the representation as in [3]. We modify the method further by + * requiring that all K_i be odd, which has the small cost that our + * representation uses one more K_i, due to carries, but saves on the size of + * the precomputed table. + * + * Summary of the comb method and its modifications: + * + * - The goal is to compute m*P for some w*d-bit integer m. + * + * - The basic comb method splits m into the w-bit integers + * x[0] .. x[d-1] where x[i] consists of the bits in m whose + * index has residue i modulo d, and computes m * P as + * S[x[0]] + 2 * S[x[1]] + .. + 2^(d-1) S[x[d-1]], where + * S[i_{w-1} .. i_0] := i_{w-1} 2^{(w-1)d} P + ... + i_1 2^d P + i_0 P. + * + * - If it happens that, say, x[i+1]=0 (=> S[x[i+1]]=0), one can replace the sum by + * .. + 2^{i-1} S[x[i-1]] - 2^i S[x[i]] + 2^{i+1} S[x[i]] + 2^{i+2} S[x[i+2]] .., + * thereby successively converting it into a form where all summands + * are nonzero, at the cost of negative summands. This is the basic idea of [3]. + * + * - More generally, even if x[i+1] != 0, we can first transform the sum as + * .. - 2^i S[x[i]] + 2^{i+1} ( S[x[i]] + S[x[i+1]] ) + 2^{i+2} S[x[i+2]] .., + * and then replace S[x[i]] + S[x[i+1]] = S[x[i] ^ x[i+1]] + 2 S[x[i] & x[i+1]]. + * Performing and iterating this procedure for those x[i] that are even + * (keeping track of carry), we can transform the original sum into one of the form + * S[x'[0]] +- 2 S[x'[1]] +- .. +- 2^{d-1} S[x'[d-1]] + 2^d S[x'[d]] + * with all x'[i] odd. It is therefore only necessary to know S at odd indices, + * which is why we are only computing half of it in the first place in + * ecp_precompute_comb and accessing it with index abs(i) / 2 in ecp_select_comb. + * + * - For the sake of compactness, only the seven low-order bits of x[i] + * are used to represent its absolute value (K_i in the paper), and the msb + * of x[i] encodes the sign (s_i in the paper): it is set if and only if + * if s_i == -1; + * + * Calling conventions: + * - x is an array of size d + 1 + * - w is the size, ie number of teeth, of the comb, and must be between + * 2 and 7 (in practice, between 2 and MBEDTLS_ECP_WINDOW_SIZE) + * - m is the MPI, expected to be odd and such that bitlength(m) <= w * d + * (the result will be incorrect if these assumptions are not satisfied) + */ +static void ecp_comb_recode_core( unsigned char x[], size_t d, + unsigned char w, const mbedtls_mpi *m ) +{ + size_t i, j; + unsigned char c, cc, adjust; + + memset( x, 0, d+1 ); + + /* First get the classical comb values (except for x_d = 0) */ + for( i = 0; i < d; i++ ) + for( j = 0; j < w; j++ ) + x[i] |= mbedtls_mpi_get_bit( m, i + d * j ) << j; + + /* Now make sure x_1 .. x_d are odd */ + c = 0; + for( i = 1; i <= d; i++ ) + { + /* Add carry and update it */ + cc = x[i] & c; + x[i] = x[i] ^ c; + c = cc; + + /* Adjust if needed, avoiding branches */ + adjust = 1 - ( x[i] & 0x01 ); + c |= x[i] & ( x[i-1] * adjust ); + x[i] = x[i] ^ ( x[i-1] * adjust ); + x[i-1] |= adjust << 7; + } +} + +/* + * Precompute points for the adapted comb method + * + * Assumption: T must be able to hold 2^{w - 1} elements. + * + * Operation: If i = i_{w-1} ... i_1 is the binary representation of i, + * sets T[i] = i_{w-1} 2^{(w-1)d} P + ... + i_1 2^d P + P. + * + * Cost: d(w-1) D + (2^{w-1} - 1) A + 1 N(w-1) + 1 N(2^{w-1} - 1) + * + * Note: Even comb values (those where P would be omitted from the + * sum defining T[i] above) are not needed in our adaption + * the comb method. See ecp_comb_recode_core(). + * + * This function currently works in four steps: + * (1) [dbl] Computation of intermediate T[i] for 2-power values of i + * (2) [norm_dbl] Normalization of coordinates of these T[i] + * (3) [add] Computation of all T[i] + * (4) [norm_add] Normalization of all T[i] + * + * Step 1 can be interrupted but not the others; together with the final + * coordinate normalization they are the largest steps done at once, depending + * on the window size. Here are operation counts for P-256: + * + * step (2) (3) (4) + * w = 5 142 165 208 + * w = 4 136 77 160 + * w = 3 130 33 136 + * w = 2 124 11 124 + * + * So if ECC operations are blocking for too long even with a low max_ops + * value, it's useful to set MBEDTLS_ECP_WINDOW_SIZE to a lower value in order + * to minimize maximum blocking time. + */ +static int ecp_precompute_comb( const mbedtls_ecp_group *grp, + mbedtls_ecp_point T[], const mbedtls_ecp_point *P, + unsigned char w, size_t d, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char i; + size_t j = 0; + const unsigned char T_size = 1U << ( w - 1 ); + mbedtls_ecp_point *cur, *TT[COMB_MAX_PRE - 1]; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + if( rs_ctx->rsm->state == ecp_rsm_pre_dbl ) + goto dbl; + if( rs_ctx->rsm->state == ecp_rsm_pre_norm_dbl ) + goto norm_dbl; + if( rs_ctx->rsm->state == ecp_rsm_pre_add ) + goto add; + if( rs_ctx->rsm->state == ecp_rsm_pre_norm_add ) + goto norm_add; + } +#else + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + rs_ctx->rsm->state = ecp_rsm_pre_dbl; + + /* initial state for the loop */ + rs_ctx->rsm->i = 0; + } + +dbl: +#endif + /* + * Set T[0] = P and + * T[2^{l-1}] = 2^{dl} P for l = 1 .. w-1 (this is not the final value) + */ + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &T[0], P ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->i != 0 ) + j = rs_ctx->rsm->i; + else +#endif + j = 0; + + for( ; j < d * ( w - 1 ); j++ ) + { + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_DBL ); + + i = 1U << ( j / d ); + cur = T + i; + + if( j % d == 0 ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( cur, T + ( i >> 1 ) ) ); + + MBEDTLS_MPI_CHK( ecp_double_jac( grp, cur, cur ) ); + } + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_norm_dbl; + +norm_dbl: +#endif + /* + * Normalize current elements in T. As T has holes, + * use an auxiliary array of pointers to elements in T. + */ + j = 0; + for( i = 1; i < T_size; i <<= 1 ) + TT[j++] = T + i; + + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV + 6 * j - 2 ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac_many( grp, TT, j ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_add; + +add: +#endif + /* + * Compute the remaining ones using the minimal number of additions + * Be careful to update T[2^l] only after using it! + */ + MBEDTLS_ECP_BUDGET( ( T_size - 1 ) * MBEDTLS_ECP_OPS_ADD ); + + for( i = 1; i < T_size; i <<= 1 ) + { + j = i; + while( j-- ) + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, &T[i + j], &T[j], &T[i] ) ); + } + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_norm_add; + +norm_add: +#endif + /* + * Normalize final elements in T. Even though there are no holes now, we + * still need the auxiliary array for homogeneity with the previous + * call. Also, skip T[0] which is already normalised, being a copy of P. + */ + for( j = 0; j + 1 < T_size; j++ ) + TT[j] = T + j + 1; + + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV + 6 * j - 2 ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac_many( grp, TT, j ) ); + +cleanup: +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + if( rs_ctx->rsm->state == ecp_rsm_pre_dbl ) + rs_ctx->rsm->i = j; + } +#endif + + return( ret ); +} + +/* + * Select precomputed point: R = sign(i) * T[ abs(i) / 2 ] + * + * See ecp_comb_recode_core() for background + */ +static int ecp_select_comb( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point T[], unsigned char T_size, + unsigned char i ) +{ + int ret; + unsigned char ii, j; + + /* Ignore the "sign" bit and scale down */ + ii = ( i & 0x7Fu ) >> 1; + + /* Read the whole table to thwart cache-based timing attacks */ + for( j = 0; j < T_size; j++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &R->X, &T[j].X, j == ii ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &R->Y, &T[j].Y, j == ii ) ); + } + + /* Safely invert result if i is "negative" */ + MBEDTLS_MPI_CHK( ecp_safe_invert_jac( grp, R, i >> 7 ) ); + +cleanup: + return( ret ); +} + +/* + * Core multiplication algorithm for the (modified) comb method. + * This part is actually common with the basic comb method (GECC 3.44) + * + * Cost: d A + d D + 1 R + */ +static int ecp_mul_comb_core( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point T[], unsigned char T_size, + const unsigned char x[], size_t d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_ecp_point Txi; + size_t i; + + mbedtls_ecp_point_init( &Txi ); + +#if !defined(MBEDTLS_ECP_RESTARTABLE) + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + rs_ctx->rsm->state != ecp_rsm_comb_core ) + { + rs_ctx->rsm->i = 0; + rs_ctx->rsm->state = ecp_rsm_comb_core; + } + + /* new 'if' instead of nested for the sake of the 'else' branch */ + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->i != 0 ) + { + /* restore current index (R already pointing to rs_ctx->rsm->R) */ + i = rs_ctx->rsm->i; + } + else +#endif + { + /* Start with a non-zero point and randomize its coordinates */ + i = d; + MBEDTLS_MPI_CHK( ecp_select_comb( grp, R, T, T_size, x[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 1 ) ); +#if defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng != 0 ) +#endif + MBEDTLS_MPI_CHK( ecp_randomize_jac( grp, R, f_rng, p_rng ) ); + } + + while( i != 0 ) + { + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_DBL + MBEDTLS_ECP_OPS_ADD ); + --i; + + MBEDTLS_MPI_CHK( ecp_double_jac( grp, R, R ) ); + MBEDTLS_MPI_CHK( ecp_select_comb( grp, &Txi, T, T_size, x[i] ) ); + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, R, R, &Txi ) ); + } + +cleanup: + + mbedtls_ecp_point_free( &Txi ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + rs_ctx->rsm->i = i; + /* no need to save R, already pointing to rs_ctx->rsm->R */ + } +#endif + + return( ret ); +} + +/* + * Recode the scalar to get constant-time comb multiplication + * + * As the actual scalar recoding needs an odd scalar as a starting point, + * this wrapper ensures that by replacing m by N - m if necessary, and + * informs the caller that the result of multiplication will be negated. + * + * This works because we only support large prime order for Short Weierstrass + * curves, so N is always odd hence either m or N - m is. + * + * See ecp_comb_recode_core() for background. + */ +static int ecp_comb_recode_scalar( const mbedtls_ecp_group *grp, + const mbedtls_mpi *m, + unsigned char k[COMB_MAX_D + 1], + size_t d, + unsigned char w, + unsigned char *parity_trick ) +{ + int ret; + mbedtls_mpi M, mm; + + mbedtls_mpi_init( &M ); + mbedtls_mpi_init( &mm ); + + /* N is always odd (see above), just make extra sure */ + if( mbedtls_mpi_get_bit( &grp->N, 0 ) != 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* do we need the parity trick? */ + *parity_trick = ( mbedtls_mpi_get_bit( m, 0 ) == 0 ); + + /* execute parity fix in constant time */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &M, m ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &mm, &grp->N, m ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &M, &mm, *parity_trick ) ); + + /* actual scalar recoding */ + ecp_comb_recode_core( k, d, w, &M ); + +cleanup: + mbedtls_mpi_free( &mm ); + mbedtls_mpi_free( &M ); + + return( ret ); +} + +/* + * Perform comb multiplication (for short Weierstrass curves) + * once the auxiliary table has been pre-computed. + * + * Scalar recoding may use a parity trick that makes us compute -m * P, + * if that is the case we'll need to recover m * P at the end. + */ +static int ecp_mul_comb_after_precomp( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *T, + unsigned char T_size, + unsigned char w, + size_t d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char parity_trick; + unsigned char k[COMB_MAX_D + 1]; + mbedtls_ecp_point *RR = R; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + RR = &rs_ctx->rsm->R; + + if( rs_ctx->rsm->state == ecp_rsm_final_norm ) + goto final_norm; + } +#endif + + MBEDTLS_MPI_CHK( ecp_comb_recode_scalar( grp, m, k, d, w, + &parity_trick ) ); + MBEDTLS_MPI_CHK( ecp_mul_comb_core( grp, RR, T, T_size, k, d, + f_rng, p_rng, rs_ctx ) ); + MBEDTLS_MPI_CHK( ecp_safe_invert_jac( grp, RR, parity_trick ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_final_norm; + +final_norm: + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV ); +#endif + /* + * Knowledge of the jacobian coordinates may leak the last few bits of the + * scalar [1], and since our MPI implementation isn't constant-flow, + * inversion (used for coordinate normalization) may leak the full value + * of its input via side-channels [2]. + * + * [1] https://eprint.iacr.org/2003/191 + * [2] https://eprint.iacr.org/2020/055 + * + * Avoid the leak by randomizing coordinates before we normalize them. + */ +#if defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng != 0 ) +#endif + MBEDTLS_MPI_CHK( ecp_randomize_jac( grp, RR, f_rng, p_rng ) ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, RR ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, RR ) ); +#endif + +cleanup: + return( ret ); +} + +/* + * Pick window size based on curve size and whether we optimize for base point + */ +static unsigned char ecp_pick_window_size( const mbedtls_ecp_group *grp, + unsigned char p_eq_g ) +{ + unsigned char w; + + /* + * Minimize the number of multiplications, that is minimize + * 10 * d * w + 18 * 2^(w-1) + 11 * d + 7 * w, with d = ceil( nbits / w ) + * (see costs of the various parts, with 1S = 1M) + */ + w = grp->nbits >= 384 ? 5 : 4; + + /* + * If P == G, pre-compute a bit more, since this may be re-used later. + * Just adding one avoids upping the cost of the first mul too much, + * and the memory cost too. + */ + if( p_eq_g ) + w++; + + /* + * Make sure w is within bounds. + * (The last test is useful only for very small curves in the test suite.) + */ + if( w > MBEDTLS_ECP_WINDOW_SIZE ) + w = MBEDTLS_ECP_WINDOW_SIZE; + if( w >= grp->nbits ) + w = 2; + + return( w ); +} + +/* + * Multiplication using the comb method - for curves in short Weierstrass form + * + * This function is mainly responsible for administrative work: + * - managing the restart context if enabled + * - managing the table of precomputed points (passed between the below two + * functions): allocation, computation, ownership tranfer, freeing. + * + * It delegates the actual arithmetic work to: + * ecp_precompute_comb() and ecp_mul_comb_with_precomp() + * + * See comments on ecp_comb_recode_core() regarding the computation strategy. + */ +static int ecp_mul_comb( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char w, p_eq_g, i; + size_t d; + unsigned char T_size = 0, T_ok = 0; + mbedtls_ecp_point *T = NULL; +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_context drbg_ctx; + + ecp_drbg_init( &drbg_ctx ); +#endif + + ECP_RS_ENTER( rsm ); + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng == NULL ) + { + /* Adjust pointers */ + f_rng = &ecp_drbg_random; +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + p_rng = &rs_ctx->rsm->drbg_ctx; + else +#endif + p_rng = &drbg_ctx; + + /* Initialize internal DRBG if necessary */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx == NULL || rs_ctx->rsm == NULL || + rs_ctx->rsm->drbg_seeded == 0 ) +#endif + { + const size_t m_len = ( grp->nbits + 7 ) / 8; + MBEDTLS_MPI_CHK( ecp_drbg_seed( p_rng, m, m_len ) ); + } +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->drbg_seeded = 1; +#endif + } +#endif /* !MBEDTLS_ECP_NO_INTERNAL_RNG */ + + /* Is P the base point ? */ +#if MBEDTLS_ECP_FIXED_POINT_OPTIM == 1 + p_eq_g = ( mbedtls_mpi_cmp_mpi( &P->Y, &grp->G.Y ) == 0 && + mbedtls_mpi_cmp_mpi( &P->X, &grp->G.X ) == 0 ); +#else + p_eq_g = 0; +#endif + + /* Pick window size and deduce related sizes */ + w = ecp_pick_window_size( grp, p_eq_g ); + T_size = 1U << ( w - 1 ); + d = ( grp->nbits + w - 1 ) / w; + + /* Pre-computed table: do we have it already for the base point? */ + if( p_eq_g && grp->T != NULL ) + { + /* second pointer to the same table, will be deleted on exit */ + T = grp->T; + T_ok = 1; + } + else +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* Pre-computed table: do we have one in progress? complete? */ + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->T != NULL ) + { + /* transfer ownership of T from rsm to local function */ + T = rs_ctx->rsm->T; + rs_ctx->rsm->T = NULL; + rs_ctx->rsm->T_size = 0; + + /* This effectively jumps to the call to mul_comb_after_precomp() */ + T_ok = rs_ctx->rsm->state >= ecp_rsm_comb_core; + } + else +#endif + /* Allocate table if we didn't have any */ + { + T = mbedtls_calloc( T_size, sizeof( mbedtls_ecp_point ) ); + if( T == NULL ) + { + ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + goto cleanup; + } + + for( i = 0; i < T_size; i++ ) + mbedtls_ecp_point_init( &T[i] ); + + T_ok = 0; + } + + /* Compute table (or finish computing it) if not done already */ + if( !T_ok ) + { + MBEDTLS_MPI_CHK( ecp_precompute_comb( grp, T, P, w, d, rs_ctx ) ); + + if( p_eq_g ) + { + /* almost transfer ownership of T to the group, but keep a copy of + * the pointer to use for calling the next function more easily */ + grp->T = T; + grp->T_size = T_size; + } + } + + /* Actual comb multiplication using precomputed points */ + MBEDTLS_MPI_CHK( ecp_mul_comb_after_precomp( grp, R, m, + T, T_size, w, d, + f_rng, p_rng, rs_ctx ) ); + +cleanup: + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_free( &drbg_ctx ); +#endif + + /* does T belong to the group? */ + if( T == grp->T ) + T = NULL; + + /* does T belong to the restart context? */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && ret == MBEDTLS_ERR_ECP_IN_PROGRESS && T != NULL ) + { + /* transfer ownership of T from local function to rsm */ + rs_ctx->rsm->T_size = T_size; + rs_ctx->rsm->T = T; + T = NULL; + } +#endif + + /* did T belong to us? then let's destroy it! */ + if( T != NULL ) + { + for( i = 0; i < T_size; i++ ) + mbedtls_ecp_point_free( &T[i] ); + mbedtls_free( T ); + } + + /* don't free R while in progress in case R == P */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) +#endif + /* prevent caller from using invalid value */ + if( ret != 0 ) + mbedtls_ecp_point_free( R ); + + ECP_RS_LEAVE( rsm ); + + return( ret ); +} + +#endif /* ECP_SHORTWEIERSTRASS */ + +#if defined(ECP_MONTGOMERY) +/* + * For Montgomery curves, we do all the internal arithmetic in projective + * coordinates. Import/export of points uses only the x coordinates, which is + * internaly represented as X / Z. + * + * For scalar multiplication, we'll use a Montgomery ladder. + */ + +/* + * Normalize Montgomery x/z coordinates: X = X/Z, Z = 1 + * Cost: 1M + 1I + */ +static int ecp_normalize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P ) +{ + int ret; + +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_mxz( grp, P ) ); +#endif /* MBEDTLS_ECP_NORMALIZE_MXZ_ALT */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &P->Z, &P->Z, &grp->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->X, &P->X, &P->Z ) ); MOD_MUL( P->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &P->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Randomize projective x/z coordinates: + * (X, Z) -> (l X, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_mxz(). + * + * This countermeasure was first suggested in [2]. + * Cost: 2M + */ +static int ecp_randomize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + mbedtls_mpi l; + size_t p_size; + int count = 0; + +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_randomize_mxz( grp, P, f_rng, p_rng ) ); +#endif /* MBEDTLS_ECP_RANDOMIZE_MXZ_ALT */ + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); + + /* Generate l such that 1 < l < p */ + do + { + if( count++ > 30 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, ( p_size * 8 ) - grp->pbits ) ); + } + while( ( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ) || + ( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->X, &P->X, &l ) ); MOD_MUL( P->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->Z, &P->Z, &l ) ); MOD_MUL( P->Z ); + +cleanup: + mbedtls_mpi_free( &l ); + + return( ret ); +} + +/* + * Double-and-add: R = 2P, S = P + Q, with d = X(P - Q), + * for Montgomery curves in x/z coordinates. + * + * https://www.hyperelliptic.org/EFD/g1p/auto-code/montgom/xz/ladder/mladd-1987-m.op3 + * with + * d = X1 + * P = (X2, Z2) + * Q = (X3, Z3) + * R = (X4, Z4) + * S = (X5, Z5) + * and eliminating temporary variables tO, ..., t4. + * + * Cost: 5M + 4S + */ +static int ecp_double_add_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, mbedtls_ecp_point *S, + const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q, + const mbedtls_mpi *d ) +{ + int ret; + mbedtls_mpi A, AA, B, BB, E, C, D, DA, CB; + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_double_add_mxz( grp, R, S, P, Q, d ) ); +#endif /* MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT */ + + mbedtls_mpi_init( &A ); mbedtls_mpi_init( &AA ); mbedtls_mpi_init( &B ); + mbedtls_mpi_init( &BB ); mbedtls_mpi_init( &E ); mbedtls_mpi_init( &C ); + mbedtls_mpi_init( &D ); mbedtls_mpi_init( &DA ); mbedtls_mpi_init( &CB ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &A, &P->X, &P->Z ) ); MOD_ADD( A ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &AA, &A, &A ) ); MOD_MUL( AA ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &B, &P->X, &P->Z ) ); MOD_SUB( B ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &BB, &B, &B ) ); MOD_MUL( BB ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &E, &AA, &BB ) ); MOD_SUB( E ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &C, &Q->X, &Q->Z ) ); MOD_ADD( C ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &D, &Q->X, &Q->Z ) ); MOD_SUB( D ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &DA, &D, &A ) ); MOD_MUL( DA ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &CB, &C, &B ) ); MOD_MUL( CB ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &S->X, &DA, &CB ) ); MOD_MUL( S->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->X, &S->X, &S->X ) ); MOD_MUL( S->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S->Z, &DA, &CB ) ); MOD_SUB( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->Z, &S->Z, &S->Z ) ); MOD_MUL( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->Z, d, &S->Z ) ); MOD_MUL( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->X, &AA, &BB ) ); MOD_MUL( R->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->Z, &grp->A, &E ) ); MOD_MUL( R->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &R->Z, &BB, &R->Z ) ); MOD_ADD( R->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->Z, &E, &R->Z ) ); MOD_MUL( R->Z ); + +cleanup: + mbedtls_mpi_free( &A ); mbedtls_mpi_free( &AA ); mbedtls_mpi_free( &B ); + mbedtls_mpi_free( &BB ); mbedtls_mpi_free( &E ); mbedtls_mpi_free( &C ); + mbedtls_mpi_free( &D ); mbedtls_mpi_free( &DA ); mbedtls_mpi_free( &CB ); + + return( ret ); +} + +/* + * Multiplication with Montgomery ladder in x/z coordinates, + * for curves in Montgomery form + */ +static int ecp_mul_mxz( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + size_t i; + unsigned char b; + mbedtls_ecp_point RP; + mbedtls_mpi PX; +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_context drbg_ctx; + + ecp_drbg_init( &drbg_ctx ); +#endif + mbedtls_ecp_point_init( &RP ); mbedtls_mpi_init( &PX ); + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng == NULL ) + { + const size_t m_len = ( grp->nbits + 7 ) / 8; + MBEDTLS_MPI_CHK( ecp_drbg_seed( &drbg_ctx, m, m_len ) ); + f_rng = &ecp_drbg_random; + p_rng = &drbg_ctx; + } +#endif /* !MBEDTLS_ECP_NO_INTERNAL_RNG */ + + /* Save PX and read from P before writing to R, in case P == R */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &PX, &P->X ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &RP, P ) ); + + /* Set R to zero in modified x/z coordinates */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->X, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 0 ) ); + mbedtls_mpi_free( &R->Y ); + + /* RP.X might be sligtly larger than P, so reduce it */ + MOD_ADD( RP.X ); + + /* Randomize coordinates of the starting point */ +#if defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng != NULL ) +#endif + MBEDTLS_MPI_CHK( ecp_randomize_mxz( grp, &RP, f_rng, p_rng ) ); + + /* Loop invariant: R = result so far, RP = R + P */ + i = mbedtls_mpi_bitlen( m ); /* one past the (zero-based) most significant bit */ + while( i-- > 0 ) + { + b = mbedtls_mpi_get_bit( m, i ); + /* + * if (b) R = 2R + P else R = 2R, + * which is: + * if (b) double_add( RP, R, RP, R ) + * else double_add( R, RP, R, RP ) + * but using safe conditional swaps to avoid leaks + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->X, &RP.X, b ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->Z, &RP.Z, b ) ); + MBEDTLS_MPI_CHK( ecp_double_add_mxz( grp, R, &RP, R, &RP, &PX ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->X, &RP.X, b ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->Z, &RP.Z, b ) ); + } + + /* + * Knowledge of the projective coordinates may leak the last few bits of the + * scalar [1], and since our MPI implementation isn't constant-flow, + * inversion (used for coordinate normalization) may leak the full value + * of its input via side-channels [2]. + * + * [1] https://eprint.iacr.org/2003/191 + * [2] https://eprint.iacr.org/2020/055 + * + * Avoid the leak by randomizing coordinates before we normalize them. + */ +#if defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng != NULL ) +#endif + MBEDTLS_MPI_CHK( ecp_randomize_mxz( grp, R, f_rng, p_rng ) ); + + MBEDTLS_MPI_CHK( ecp_normalize_mxz( grp, R ) ); + +cleanup: +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_free( &drbg_ctx ); +#endif + + mbedtls_ecp_point_free( &RP ); mbedtls_mpi_free( &PX ); + + return( ret ); +} + +#endif /* ECP_MONTGOMERY */ + +/* + * Restartable multiplication R = m * P + */ +int mbedtls_ecp_mul_restartable( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + char is_grp_capable = 0; +#endif + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* reset ops count for this call if top-level */ + if( rs_ctx != NULL && rs_ctx->depth++ == 0 ) + rs_ctx->ops_done = 0; +#endif + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( ( is_grp_capable = mbedtls_internal_ecp_grp_capable( grp ) ) ) + MBEDTLS_MPI_CHK( mbedtls_internal_ecp_init( grp ) ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* skip argument check when restarting */ + if( rs_ctx == NULL || rs_ctx->rsm == NULL ) +#endif + { + /* check_privkey is free */ + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_CHK ); + + /* Common sanity checks */ + MBEDTLS_MPI_CHK( mbedtls_ecp_check_privkey( grp, m ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_check_pubkey( grp, P ) ); + } + + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; +#if defined(ECP_MONTGOMERY) + if( ecp_get_type( grp ) == ECP_TYPE_MONTGOMERY ) + MBEDTLS_MPI_CHK( ecp_mul_mxz( grp, R, m, P, f_rng, p_rng ) ); +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( ecp_get_type( grp ) == ECP_TYPE_SHORT_WEIERSTRASS ) + MBEDTLS_MPI_CHK( ecp_mul_comb( grp, R, m, P, f_rng, p_rng, rs_ctx ) ); +#endif + +cleanup: + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( is_grp_capable ) + mbedtls_internal_ecp_free( grp ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL ) + rs_ctx->depth--; +#endif + + return( ret ); +} + +/* + * Multiplication R = m * P + */ +int mbedtls_ecp_mul( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + return( mbedtls_ecp_mul_restartable( grp, R, m, P, f_rng, p_rng, NULL ) ); +} + +#if defined(ECP_SHORTWEIERSTRASS) +/* + * Check that an affine point is valid as a public key, + * short weierstrass curves (SEC1 3.2.3.1) + */ +static int ecp_check_pubkey_sw( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) +{ + int ret; + mbedtls_mpi YY, RHS; + + /* pt coordinates must be normalized for our checks */ + if( mbedtls_mpi_cmp_int( &pt->X, 0 ) < 0 || + mbedtls_mpi_cmp_int( &pt->Y, 0 ) < 0 || + mbedtls_mpi_cmp_mpi( &pt->X, &grp->P ) >= 0 || + mbedtls_mpi_cmp_mpi( &pt->Y, &grp->P ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + mbedtls_mpi_init( &YY ); mbedtls_mpi_init( &RHS ); + + /* + * YY = Y^2 + * RHS = X (X^2 + A) + B = X^3 + A X + B + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &YY, &pt->Y, &pt->Y ) ); MOD_MUL( YY ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &RHS, &pt->X, &pt->X ) ); MOD_MUL( RHS ); + + /* Special case for A = -3 */ + if( grp->A.p == NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &RHS, &RHS, 3 ) ); MOD_SUB( RHS ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &RHS, &RHS, &grp->A ) ); MOD_ADD( RHS ); + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &RHS, &RHS, &pt->X ) ); MOD_MUL( RHS ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &RHS, &RHS, &grp->B ) ); MOD_ADD( RHS ); + + if( mbedtls_mpi_cmp_mpi( &YY, &RHS ) != 0 ) + ret = MBEDTLS_ERR_ECP_INVALID_KEY; + +cleanup: + + mbedtls_mpi_free( &YY ); mbedtls_mpi_free( &RHS ); + + return( ret ); +} +#endif /* ECP_SHORTWEIERSTRASS */ + +/* + * R = m * P with shortcuts for m == 1 and m == -1 + * NOT constant-time - ONLY for short Weierstrass! + */ +static int mbedtls_ecp_mul_shortcuts( mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + + if( mbedtls_mpi_cmp_int( m, 1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, P ) ); + } + else if( mbedtls_mpi_cmp_int( m, -1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, P ) ); + if( mbedtls_mpi_cmp_int( &R->Y, 0 ) != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &R->Y, &grp->P, &R->Y ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, R, m, P, + NULL, NULL, rs_ctx ) ); + } + +cleanup: + return( ret ); +} + +/* + * Restartable linear combination + * NOT constant-time + */ +int mbedtls_ecp_muladd_restartable( + mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_ecp_point mP; + mbedtls_ecp_point *pmP = &mP; + mbedtls_ecp_point *pR = R; +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + char is_grp_capable = 0; +#endif + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( n != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + if( ecp_get_type( grp ) != ECP_TYPE_SHORT_WEIERSTRASS ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + mbedtls_ecp_point_init( &mP ); + + ECP_RS_ENTER( ma ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + { + /* redirect intermediate results to restart context */ + pmP = &rs_ctx->ma->mP; + pR = &rs_ctx->ma->R; + + /* jump to next operation */ + if( rs_ctx->ma->state == ecp_rsma_mul2 ) + goto mul2; + if( rs_ctx->ma->state == ecp_rsma_add ) + goto add; + if( rs_ctx->ma->state == ecp_rsma_norm ) + goto norm; + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_shortcuts( grp, pmP, m, P, rs_ctx ) ); +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_mul2; + +mul2: +#endif + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_shortcuts( grp, pR, n, Q, rs_ctx ) ); + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( ( is_grp_capable = mbedtls_internal_ecp_grp_capable( grp ) ) ) + MBEDTLS_MPI_CHK( mbedtls_internal_ecp_init( grp ) ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_add; + +add: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_ADD ); + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, pR, pmP, pR ) ); +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_norm; + +norm: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV ); + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, pR ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, pR ) ); +#endif + +cleanup: +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( is_grp_capable ) + mbedtls_internal_ecp_free( grp ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + + mbedtls_ecp_point_free( &mP ); + + ECP_RS_LEAVE( ma ); + + return( ret ); +} + +/* + * Linear combination + * NOT constant-time + */ +int mbedtls_ecp_muladd( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( n != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + return( mbedtls_ecp_muladd_restartable( grp, R, m, P, n, Q, NULL ) ); +} + +#if defined(ECP_MONTGOMERY) +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +#define ECP_MPI_INIT(s, n, p) {s, (n), (mbedtls_mpi_uint *)(p)} +#define ECP_MPI_INIT_ARRAY(x) \ + ECP_MPI_INIT(1, sizeof(x) / sizeof(mbedtls_mpi_uint), x) +/* + * Constants for the two points other than 0, 1, -1 (mod p) in + * https://cr.yp.to/ecdh.html#validate + * See ecp_check_pubkey_x25519(). + */ +static const mbedtls_mpi_uint x25519_bad_point_1[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xe0, 0xeb, 0x7a, 0x7c, 0x3b, 0x41, 0xb8, 0xae ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x16, 0x56, 0xe3, 0xfa, 0xf1, 0x9f, 0xc4, 0x6a ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xda, 0x09, 0x8d, 0xeb, 0x9c, 0x32, 0xb1, 0xfd ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x86, 0x62, 0x05, 0x16, 0x5f, 0x49, 0xb8, 0x00 ), +}; +static const mbedtls_mpi_uint x25519_bad_point_2[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x5f, 0x9c, 0x95, 0xbc, 0xa3, 0x50, 0x8c, 0x24 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xb1, 0xd0, 0xb1, 0x55, 0x9c, 0x83, 0xef, 0x5b ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x04, 0x44, 0x5c, 0xc4, 0x58, 0x1c, 0x8e, 0x86 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xd8, 0x22, 0x4e, 0xdd, 0xd0, 0x9f, 0x11, 0x57 ), +}; +static const mbedtls_mpi ecp_x25519_bad_point_1 = ECP_MPI_INIT_ARRAY( + x25519_bad_point_1 ); +static const mbedtls_mpi ecp_x25519_bad_point_2 = ECP_MPI_INIT_ARRAY( + x25519_bad_point_2 ); +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +/* + * Check that the input point is not one of the low-order points. + * This is recommended by the "May the Fourth" paper: + * https://eprint.iacr.org/2017/806.pdf + * Those points are never sent by an honest peer. + */ +static int ecp_check_bad_points_mx( const mbedtls_mpi *X, const mbedtls_mpi *P, + const mbedtls_ecp_group_id grp_id ) +{ + int ret; + mbedtls_mpi XmP; + + mbedtls_mpi_init( &XmP ); + + /* Reduce X mod P so that we only need to check values less than P. + * We know X < 2^256 so we can proceed by subtraction. */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &XmP, X ) ); + while( mbedtls_mpi_cmp_mpi( &XmP, P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &XmP, &XmP, P ) ); + + /* Check against the known bad values that are less than P. For Curve448 + * these are 0, 1 and -1. For Curve25519 we check the values less than P + * from the following list: https://cr.yp.to/ecdh.html#validate */ + if( mbedtls_mpi_cmp_int( &XmP, 1 ) <= 0 ) /* takes care of 0 and 1 */ + { + ret = MBEDTLS_ERR_ECP_INVALID_KEY; + goto cleanup; + } + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + if( grp_id == MBEDTLS_ECP_DP_CURVE25519 ) + { + if( mbedtls_mpi_cmp_mpi( &XmP, &ecp_x25519_bad_point_1 ) == 0 ) + { + ret = MBEDTLS_ERR_ECP_INVALID_KEY; + goto cleanup; + } + + if( mbedtls_mpi_cmp_mpi( &XmP, &ecp_x25519_bad_point_2 ) == 0 ) + { + ret = MBEDTLS_ERR_ECP_INVALID_KEY; + goto cleanup; + } + } +#else + (void) grp_id; +#endif + + /* Final check: check if XmP + 1 is P (final because it changes XmP!) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( &XmP, &XmP, 1 ) ); + if( mbedtls_mpi_cmp_mpi( &XmP, P ) == 0 ) + { + ret = MBEDTLS_ERR_ECP_INVALID_KEY; + goto cleanup; + } + + ret = 0; + +cleanup: + mbedtls_mpi_free( &XmP ); + + return( ret ); +} + +/* + * Check validity of a public key for Montgomery curves with x-only schemes + */ +static int ecp_check_pubkey_mx( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) +{ + /* [Curve25519 p. 5] Just check X is the correct number of bytes */ + /* Allow any public value, if it's too big then we'll just reduce it mod p + * (RFC 7748 sec. 5 para. 3). */ + if( mbedtls_mpi_size( &pt->X ) > ( grp->nbits + 7 ) / 8 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + /* Implicit in all standards (as they don't consider negative numbers): + * X must be non-negative. This is normally ensured by the way it's + * encoded for transmission, but let's be extra sure. */ + if( mbedtls_mpi_cmp_int( &pt->X, 0 ) < 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + return( ecp_check_bad_points_mx( &pt->X, &grp->P, grp->id ) ); +} +#endif /* ECP_MONTGOMERY */ + +/* + * Check that a point is valid as a public key + */ +int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + + /* Must use affine coordinates */ + if( mbedtls_mpi_cmp_int( &pt->Z, 1 ) != 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + +#if defined(ECP_MONTGOMERY) + if( ecp_get_type( grp ) == ECP_TYPE_MONTGOMERY ) + return( ecp_check_pubkey_mx( grp, pt ) ); +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( ecp_get_type( grp ) == ECP_TYPE_SHORT_WEIERSTRASS ) + return( ecp_check_pubkey_sw( grp, pt ) ); +#endif + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Check that an mbedtls_mpi is valid as a private key + */ +int mbedtls_ecp_check_privkey( const mbedtls_ecp_group *grp, + const mbedtls_mpi *d ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + +#if defined(ECP_MONTGOMERY) + if( ecp_get_type( grp ) == ECP_TYPE_MONTGOMERY ) + { + /* see RFC 7748 sec. 5 para. 5 */ + if( mbedtls_mpi_get_bit( d, 0 ) != 0 || + mbedtls_mpi_get_bit( d, 1 ) != 0 || + mbedtls_mpi_bitlen( d ) - 1 != grp->nbits ) /* mbedtls_mpi_bitlen is one-based! */ + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + /* see [Curve25519] page 5 */ + if( grp->nbits == 254 && mbedtls_mpi_get_bit( d, 2 ) != 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + return( 0 ); + } +#endif /* ECP_MONTGOMERY */ +#if defined(ECP_SHORTWEIERSTRASS) + if( ecp_get_type( grp ) == ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* see SEC1 3.2 */ + if( mbedtls_mpi_cmp_int( d, 1 ) < 0 || + mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + else + return( 0 ); + } +#endif /* ECP_SHORTWEIERSTRASS */ + + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Generate a private key + */ +int mbedtls_ecp_gen_privkey( const mbedtls_ecp_group *grp, + mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + size_t n_size; +#if defined(ECP_SHORTWEIERSTRASS) + mbedtls_mpi one; + + mbedtls_mpi_init( &one ); +#endif + + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + n_size = ( grp->nbits + 7 ) / 8; + +#if defined(ECP_MONTGOMERY) + if( ecp_get_type( grp ) == ECP_TYPE_MONTGOMERY ) + { + /* [M225] page 5 */ + size_t b; + + do { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( d, n_size, f_rng, p_rng ) ); + } while( mbedtls_mpi_bitlen( d ) == 0); + + /* Make sure the most significant bit is nbits */ + b = mbedtls_mpi_bitlen( d ) - 1; /* mbedtls_mpi_bitlen is one-based */ + if( b > grp->nbits ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( d, b - grp->nbits ) ); + else + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, grp->nbits, 1 ) ); + + /* Make sure the last two bits are unset for Curve448, three bits for + Curve25519 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 0, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 1, 0 ) ); + if( grp->nbits == 254 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 2, 0 ) ); + } + } +#endif /* ECP_MONTGOMERY */ + +#if defined(ECP_SHORTWEIERSTRASS) + if( ecp_get_type( grp ) == ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* SEC1 3.2.1: Generate d such that 1 <= n < N */ + int count = 0; + unsigned lt_lower = 1, lt_upper = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &one, grp->N.n ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &one, 1 ) ); + + /* + * Match the procedure given in RFC 6979 (deterministic ECDSA): + * - use the same byte ordering; + * - keep the leftmost nbits bits of the generated octet string; + * - try until result is in the desired range. + * This also avoids any biais, which is especially important for ECDSA. + */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( d, n_size, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( d, 8 * n_size - grp->nbits ) ); + + /* + * Each try has at worst a probability 1/2 of failing (the msb has + * a probability 1/2 of being 0, and then the result will be < N), + * so after 30 tries failure probability is a most 2**(-30). + * + * For most curves, 1 try is enough with overwhelming probability, + * since N starts with a lot of 1s in binary, but some curves + * such as secp224k1 are actually very close to the worst case. + */ + if( ++count > 30 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_lt_mpi_ct( d, &grp->N, <_upper ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lt_mpi_ct( d, &one, <_lower ) ); + } + while( lt_lower != 0 || lt_upper == 0 ); + } +#endif /* ECP_SHORTWEIERSTRASS */ + +cleanup: +#if defined(ECP_SHORTWEIERSTRASS) + mbedtls_mpi_free( &one ); +#endif + return( ret ); +} + +/* + * Generate a keypair with configurable base point + */ +int mbedtls_ecp_gen_keypair_base( mbedtls_ecp_group *grp, + const mbedtls_ecp_point *G, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( G != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_gen_privkey( grp, d, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( grp, Q, d, G, f_rng, p_rng ) ); + +cleanup: + return( ret ); +} + +/* + * Generate key pair, wrapper for conventional base point + */ +int mbedtls_ecp_gen_keypair( mbedtls_ecp_group *grp, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + return( mbedtls_ecp_gen_keypair_base( grp, &grp->G, d, Q, f_rng, p_rng ) ); +} + +/* + * Generate a keypair, prettier wrapper + */ +int mbedtls_ecp_gen_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + ECP_VALIDATE_RET( key != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + if( ( ret = mbedtls_ecp_group_load( &key->grp, grp_id ) ) != 0 ) + return( ret ); + + return( mbedtls_ecp_gen_keypair( &key->grp, &key->d, &key->Q, f_rng, p_rng ) ); +} + +/* + * Check a public-private key pair + */ +int mbedtls_ecp_check_pub_priv( const mbedtls_ecp_keypair *pub, const mbedtls_ecp_keypair *prv ) +{ + int ret; + mbedtls_ecp_point Q; + mbedtls_ecp_group grp; + ECP_VALIDATE_RET( pub != NULL ); + ECP_VALIDATE_RET( prv != NULL ); + + if( pub->grp.id == MBEDTLS_ECP_DP_NONE || + pub->grp.id != prv->grp.id || + mbedtls_mpi_cmp_mpi( &pub->Q.X, &prv->Q.X ) || + mbedtls_mpi_cmp_mpi( &pub->Q.Y, &prv->Q.Y ) || + mbedtls_mpi_cmp_mpi( &pub->Q.Z, &prv->Q.Z ) ) + { + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + mbedtls_ecp_point_init( &Q ); + mbedtls_ecp_group_init( &grp ); + + /* mbedtls_ecp_mul() needs a non-const group... */ + mbedtls_ecp_group_copy( &grp, &prv->grp ); + + /* Also checks d is valid */ + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &Q, &prv->d, &prv->grp.G, NULL, NULL ) ); + + if( mbedtls_mpi_cmp_mpi( &Q.X, &prv->Q.X ) || + mbedtls_mpi_cmp_mpi( &Q.Y, &prv->Q.Y ) || + mbedtls_mpi_cmp_mpi( &Q.Z, &prv->Q.Z ) ) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + +cleanup: + mbedtls_ecp_point_free( &Q ); + mbedtls_ecp_group_free( &grp ); + + return( ret ); +} + +#if defined(MBEDTLS_SELF_TEST) + +#if defined(ECP_ONE_STEP_KDF) +/* + * There are no test vectors from NIST for the One-Step KDF in SP 800-56C, + * but unofficial ones can be found at: + * https://github.com/patrickfav/singlestep-kdf/wiki/NIST-SP-800-56C-Rev1:-Non-Official-Test-Vectors + * + * We only use the ones with empty fixedInfo, and for brevity's sake, only + * 40-bytes output (with SHA-256 that's more than one block, and with SHA-512 + * less than one block). + */ +#if defined(MBEDTLS_SHA512_C) + +static const uint8_t test_kdf_z[16] = { + 0x3b, 0xa9, 0x79, 0xe9, 0xbc, 0x5e, 0x3e, 0xc7, + 0x61, 0x30, 0x36, 0xb6, 0xf5, 0x1c, 0xd5, 0xaa, +}; +static const uint8_t test_kdf_out[40] = { + 0x3e, 0xf6, 0xda, 0xf9, 0x51, 0x60, 0x70, 0x5f, + 0xdf, 0x21, 0xcd, 0xab, 0xac, 0x25, 0x7b, 0x05, + 0xfe, 0xc1, 0xab, 0x7c, 0xc9, 0x68, 0x43, 0x25, + 0x8a, 0xfc, 0x40, 0x6e, 0x5b, 0xf7, 0x98, 0x27, + 0x10, 0xfa, 0x7b, 0x93, 0x52, 0xd4, 0x16, 0xaa, +}; + +#elif defined(MBEDTLS_SHA256_C) + +static const uint8_t test_kdf_z[16] = { + 0xc8, 0x3e, 0x35, 0x8e, 0x99, 0xa6, 0x89, 0xc6, + 0x7d, 0xb4, 0xfe, 0x39, 0xcf, 0x8f, 0x26, 0xe1, +}; +static const uint8_t test_kdf_out[40] = { + 0x7d, 0xf6, 0x41, 0xf8, 0x3c, 0x47, 0xdc, 0x28, + 0x5f, 0x7f, 0xaa, 0xde, 0x05, 0x64, 0xd6, 0x25, + 0x00, 0x6a, 0x47, 0xd9, 0x1e, 0xa4, 0xa0, 0x8c, + 0xd7, 0xf7, 0x0c, 0x99, 0xaa, 0xa0, 0x72, 0x66, + 0x69, 0x0e, 0x25, 0xaa, 0xa1, 0x63, 0x14, 0x79, +}; + +#endif + +static int ecp_kdf_self_test( void ) +{ + int ret; + ecp_drbg_context kdf_ctx; + mbedtls_mpi scalar; + uint8_t out[sizeof( test_kdf_out )]; + + ecp_drbg_init( &kdf_ctx ); + mbedtls_mpi_init( &scalar ); + memset( out, 0, sizeof( out ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &scalar, + test_kdf_z, sizeof( test_kdf_z ) ) ); + + MBEDTLS_MPI_CHK( ecp_drbg_seed( &kdf_ctx, + &scalar, sizeof( test_kdf_z ) ) ); + + MBEDTLS_MPI_CHK( ecp_drbg_random( &kdf_ctx, out, sizeof( out ) ) ); + + if( memcmp( out, test_kdf_out, sizeof( out ) ) != 0 ) + ret = -1; + +cleanup: + ecp_drbg_free( &kdf_ctx ); + mbedtls_mpi_free( &scalar ); + + return( ret ); +} +#endif /* ECP_ONE_STEP_KDF */ + +/* + * Checkup routine + */ +int mbedtls_ecp_self_test( int verbose ) +{ + int ret; + size_t i; + mbedtls_ecp_group grp; + mbedtls_ecp_point R, P; + mbedtls_mpi m; + unsigned long add_c_prev, dbl_c_prev, mul_c_prev; + /* exponents especially adapted for secp192r1 */ + const char *exponents[] = + { + "000000000000000000000000000000000000000000000001", /* one */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22830", /* N - 1 */ + "5EA6F389A38B8BC81E767753B15AA5569E1782E30ABE7D25", /* random */ + "400000000000000000000000000000000000000000000000", /* one and zeros */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* all ones */ + "555555555555555555555555555555555555555555555555", /* 101010... */ + }; + + mbedtls_ecp_group_init( &grp ); + mbedtls_ecp_point_init( &R ); + mbedtls_ecp_point_init( &P ); + mbedtls_mpi_init( &m ); + + /* Use secp192r1 if available, or any available curve */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, MBEDTLS_ECP_DP_SECP192R1 ) ); +#else + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, mbedtls_ecp_curve_list()->grp_id ) ); +#endif + + if( verbose != 0 ) + mbedtls_printf( " ECP test #1 (constant op_count, base point G): " ); + + /* Do a dummy multiplication first to trigger precomputation */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &m, 2 ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &P, &m, &grp.G, NULL, NULL ) ); + + add_count = 0; + dbl_count = 0; + mul_count = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[0] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &grp.G, NULL, NULL ) ); + + for( i = 1; i < sizeof( exponents ) / sizeof( exponents[0] ); i++ ) + { + add_c_prev = add_count; + dbl_c_prev = dbl_count; + mul_c_prev = mul_count; + add_count = 0; + dbl_count = 0; + mul_count = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &grp.G, NULL, NULL ) ); + + if( add_count != add_c_prev || + dbl_count != dbl_c_prev || + mul_count != mul_c_prev ) + { + if( verbose != 0 ) + mbedtls_printf( "failed (%u)\n", (unsigned int) i ); + + ret = 1; + goto cleanup; + } + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + if( verbose != 0 ) + mbedtls_printf( " ECP test #2 (constant op_count, other point): " ); + /* We computed P = 2G last time, use it */ + + add_count = 0; + dbl_count = 0; + mul_count = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[0] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &P, NULL, NULL ) ); + + for( i = 1; i < sizeof( exponents ) / sizeof( exponents[0] ); i++ ) + { + add_c_prev = add_count; + dbl_c_prev = dbl_count; + mul_c_prev = mul_count; + add_count = 0; + dbl_count = 0; + mul_count = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &P, NULL, NULL ) ); + + if( add_count != add_c_prev || + dbl_count != dbl_c_prev || + mul_count != mul_c_prev ) + { + if( verbose != 0 ) + mbedtls_printf( "failed (%u)\n", (unsigned int) i ); + + ret = 1; + goto cleanup; + } + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + +#if defined(ECP_ONE_STEP_KDF) + if( verbose != 0 ) + mbedtls_printf( " ECP test #3 (internal KDF): " ); + + ret = ecp_kdf_self_test(); + if( ret != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + ret = 1; + goto cleanup; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); +#endif /* ECP_ONE_STEP_KDF */ + +cleanup: + + if( ret < 0 && verbose != 0 ) + mbedtls_printf( "Unexpected error, return code = %08X\n", ret ); + + mbedtls_ecp_group_free( &grp ); + mbedtls_ecp_point_free( &R ); + mbedtls_ecp_point_free( &P ); + mbedtls_mpi_free( &m ); + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* !MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/src/common/mbedtls/library/mbedtls_ecp_curves.c b/src/common/mbedtls/library/mbedtls_ecp_curves.c new file mode 100644 index 0000000000..17ce08b95b --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_ecp_curves.c @@ -0,0 +1,1472 @@ +/* + * Elliptic curves over GF(p): curve-specific data and functions + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/bn_mul.h" + +#ifndef NVRM +#include +#endif + +#if !defined(MBEDTLS_ECP_ALT) + +/* Parameter validation macros based on platform_util.h */ +#define ECP_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECP_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +#define ECP_MPI_INIT(s, n, p) {s, (n), (mbedtls_mpi_uint *)(p)} + +#define ECP_MPI_INIT_ARRAY(x) \ + ECP_MPI_INIT(1, sizeof(x) / sizeof(mbedtls_mpi_uint), x) + +/* + * Note: the constants are in little-endian order + * to be directly usable in MPIs + */ + +/* + * Domain parameters for secp192r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +static const mbedtls_mpi_uint secp192r1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192r1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xB1, 0xB9, 0x46, 0xC1, 0xEC, 0xDE, 0xB8, 0xFE ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x49, 0x30, 0x24, 0x72, 0xAB, 0xE9, 0xA7, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE7, 0x80, 0x9C, 0xE5, 0x19, 0x05, 0x21, 0x64 ), +}; +static const mbedtls_mpi_uint secp192r1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x12, 0x10, 0xFF, 0x82, 0xFD, 0x0A, 0xFF, 0xF4 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x88, 0xA1, 0x43, 0xEB, 0x20, 0xBF, 0x7C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF6, 0x90, 0x30, 0xB0, 0x0E, 0xA8, 0x8D, 0x18 ), +}; +static const mbedtls_mpi_uint secp192r1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x11, 0x48, 0x79, 0x1E, 0xA1, 0x77, 0xF9, 0x73 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD5, 0xCD, 0x24, 0x6B, 0xED, 0x11, 0x10, 0x63 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x78, 0xDA, 0xC8, 0xFF, 0x95, 0x2B, 0x19, 0x07 ), +}; +static const mbedtls_mpi_uint secp192r1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +/* + * Domain parameters for secp224r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +static const mbedtls_mpi_uint secp224r1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp224r1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C ), + MBEDTLS_BYTES_TO_T_UINT_4( 0x85, 0x0A, 0x05, 0xB4 ), +}; +static const mbedtls_mpi_uint secp224r1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B ), + MBEDTLS_BYTES_TO_T_UINT_4( 0xBD, 0x0C, 0x0E, 0xB7 ), +}; +static const mbedtls_mpi_uint secp224r1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5 ), + MBEDTLS_BYTES_TO_T_UINT_4( 0x88, 0x63, 0x37, 0xBD ), +}; +static const mbedtls_mpi_uint secp224r1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +/* + * Domain parameters for secp256r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +static const mbedtls_mpi_uint secp256r1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256r1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x4B, 0x60, 0xD2, 0x27, 0x3E, 0x3C, 0xCE, 0x3B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF6, 0xB0, 0x53, 0xCC, 0xB0, 0x06, 0x1D, 0x65 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBC, 0x86, 0x98, 0x76, 0x55, 0xBD, 0xEB, 0xB3 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE7, 0x93, 0x3A, 0xAA, 0xD8, 0x35, 0xC6, 0x5A ), +}; +static const mbedtls_mpi_uint secp256r1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x96, 0xC2, 0x98, 0xD8, 0x45, 0x39, 0xA1, 0xF4 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA0, 0x33, 0xEB, 0x2D, 0x81, 0x7D, 0x03, 0x77 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF2, 0x40, 0xA4, 0x63, 0xE5, 0xE6, 0xBC, 0xF8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x47, 0x42, 0x2C, 0xE1, 0xF2, 0xD1, 0x17, 0x6B ), +}; +static const mbedtls_mpi_uint secp256r1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xF5, 0x51, 0xBF, 0x37, 0x68, 0x40, 0xB6, 0xCB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCE, 0x5E, 0x31, 0x6B, 0x57, 0x33, 0xCE, 0x2B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x16, 0x9E, 0x0F, 0x7C, 0x4A, 0xEB, 0xE7, 0x8E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9B, 0x7F, 0x1A, 0xFE, 0xE2, 0x42, 0xE3, 0x4F ), +}; +static const mbedtls_mpi_uint secp256r1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x51, 0x25, 0x63, 0xFC, 0xC2, 0xCA, 0xB9, 0xF3 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x84, 0x9E, 0x17, 0xA7, 0xAD, 0xFA, 0xE6, 0xBC ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +/* + * Domain parameters for secp384r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +static const mbedtls_mpi_uint secp384r1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp384r1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xEF, 0x2A, 0xEC, 0xD3, 0xED, 0xC8, 0x85, 0x2A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9D, 0xD1, 0x2E, 0x8A, 0x8D, 0x39, 0x56, 0xC6 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5A, 0x87, 0x13, 0x50, 0x8F, 0x08, 0x14, 0x03 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x12, 0x41, 0x81, 0xFE, 0x6E, 0x9C, 0x1D, 0x18 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x19, 0x2D, 0xF8, 0xE3, 0x6B, 0x05, 0x8E, 0x98 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE4, 0xE7, 0x3E, 0xE2, 0xA7, 0x2F, 0x31, 0xB3 ), +}; +static const mbedtls_mpi_uint secp384r1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xB7, 0x0A, 0x76, 0x72, 0x38, 0x5E, 0x54, 0x3A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6C, 0x29, 0x55, 0xBF, 0x5D, 0xF2, 0x02, 0x55 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x38, 0x2A, 0x54, 0x82, 0xE0, 0x41, 0xF7, 0x59 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x98, 0x9B, 0xA7, 0x8B, 0x62, 0x3B, 0x1D, 0x6E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x74, 0xAD, 0x20, 0xF3, 0x1E, 0xC7, 0xB1, 0x8E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x37, 0x05, 0x8B, 0xBE, 0x22, 0xCA, 0x87, 0xAA ), +}; +static const mbedtls_mpi_uint secp384r1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x5F, 0x0E, 0xEA, 0x90, 0x7C, 0x1D, 0x43, 0x7A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9D, 0x81, 0x7E, 0x1D, 0xCE, 0xB1, 0x60, 0x0A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC0, 0xB8, 0xF0, 0xB5, 0x13, 0x31, 0xDA, 0xE9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7C, 0x14, 0x9A, 0x28, 0xBD, 0x1D, 0xF4, 0xF8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x29, 0xDC, 0x92, 0x92, 0xBF, 0x98, 0x9E, 0x5D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6F, 0x2C, 0x26, 0x96, 0x4A, 0xDE, 0x17, 0x36 ), +}; +static const mbedtls_mpi_uint secp384r1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x73, 0x29, 0xC5, 0xCC, 0x6A, 0x19, 0xEC, 0xEC ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7A, 0xA7, 0xB0, 0x48, 0xB2, 0x0D, 0x1A, 0x58 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDF, 0x2D, 0x37, 0xF4, 0x81, 0x4D, 0x63, 0xC7 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +/* + * Domain parameters for secp521r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +static const mbedtls_mpi_uint secp521r1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_2( 0xFF, 0x01 ), +}; +static const mbedtls_mpi_uint secp521r1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x3F, 0x50, 0x6B, 0xD4, 0x1F, 0x45, 0xEF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF1, 0x34, 0x2C, 0x3D, 0x88, 0xDF, 0x73, 0x35 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x07, 0xBF, 0xB1, 0x3B, 0xBD, 0xC0, 0x52, 0x16 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7B, 0x93, 0x7E, 0xEC, 0x51, 0x39, 0x19, 0x56 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE1, 0x09, 0xF1, 0x8E, 0x91, 0x89, 0xB4, 0xB8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF3, 0x15, 0xB3, 0x99, 0x5B, 0x72, 0xDA, 0xA2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xEE, 0x40, 0x85, 0xB6, 0xA0, 0x21, 0x9A, 0x92 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x1F, 0x9A, 0x1C, 0x8E, 0x61, 0xB9, 0x3E, 0x95 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x51, 0x00 ), +}; +static const mbedtls_mpi_uint secp521r1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x66, 0xBD, 0xE5, 0xC2, 0x31, 0x7E, 0x7E, 0xF9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x9B, 0x42, 0x6A, 0x85, 0xC1, 0xB3, 0x48, 0x33 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDE, 0xA8, 0xFF, 0xA2, 0x27, 0xC1, 0x1D, 0xFE ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x59, 0xE7, 0xEF, 0x77, 0x5E, 0x4B, 0xA1 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBA, 0x3D, 0x4D, 0x6B, 0x60, 0xAF, 0x28, 0xF8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x21, 0xB5, 0x3F, 0x05, 0x39, 0x81, 0x64, 0x9C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x42, 0xB4, 0x95, 0x23, 0x66, 0xCB, 0x3E, 0x9E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCD, 0xE9, 0x04, 0x04, 0xB7, 0x06, 0x8E, 0x85 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0xC6, 0x00 ), +}; +static const mbedtls_mpi_uint secp521r1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x50, 0x66, 0xD1, 0x9F, 0x76, 0x94, 0xBE, 0x88 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x40, 0xC2, 0x72, 0xA2, 0x86, 0x70, 0x3C, 0x35 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x61, 0x07, 0xAD, 0x3F, 0x01, 0xB9, 0x50, 0xC5 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x40, 0x26, 0xF4, 0x5E, 0x99, 0x72, 0xEE, 0x97 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x2C, 0x66, 0x3E, 0x27, 0x17, 0xBD, 0xAF, 0x17 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x68, 0x44, 0x9B, 0x57, 0x49, 0x44, 0xF5, 0x98 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD9, 0x1B, 0x7D, 0x2C, 0xB4, 0x5F, 0x8A, 0x5C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x04, 0xC0, 0x3B, 0x9A, 0x78, 0x6A, 0x29, 0x39 ), + MBEDTLS_BYTES_TO_T_UINT_2( 0x18, 0x01 ), +}; +static const mbedtls_mpi_uint secp521r1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x09, 0x64, 0x38, 0x91, 0x1E, 0xB7, 0x6F, 0xBB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAE, 0x47, 0x9C, 0x89, 0xB8, 0xC9, 0xB5, 0x3B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD0, 0xA5, 0x09, 0xF7, 0x48, 0x01, 0xCC, 0x7F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6B, 0x96, 0x2F, 0xBF, 0x83, 0x87, 0x86, 0x51 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_2( 0xFF, 0x01 ), +}; +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +static const mbedtls_mpi_uint secp192k1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x37, 0xEE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192k1_a[] = { + MBEDTLS_BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp192k1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_2( 0x03, 0x00 ), +}; +static const mbedtls_mpi_uint secp192k1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x7D, 0x6C, 0xE0, 0xEA, 0xB1, 0xD1, 0xA5, 0x1D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x34, 0xF4, 0xB7, 0x80, 0x02, 0x7D, 0xB0, 0x26 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAE, 0xE9, 0x57, 0xC0, 0x0E, 0xF1, 0x4F, 0xDB ), +}; +static const mbedtls_mpi_uint secp192k1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x9D, 0x2F, 0x5E, 0xD9, 0x88, 0xAA, 0x82, 0x40 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x34, 0x86, 0xBE, 0x15, 0xD0, 0x63, 0x41, 0x84 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA7, 0x28, 0x56, 0x9C, 0x6D, 0x2F, 0x2F, 0x9B ), +}; +static const mbedtls_mpi_uint secp192k1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x8D, 0xFD, 0xDE, 0x74, 0x6A, 0x46, 0x69, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x17, 0xFC, 0xF2, 0x26, 0xFE, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +static const mbedtls_mpi_uint secp224k1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x6D, 0xE5, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp224k1_a[] = { + MBEDTLS_BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp224k1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_2( 0x05, 0x00 ), +}; +static const mbedtls_mpi_uint secp224k1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x5C, 0xA4, 0xB7, 0xB6, 0x0E, 0x65, 0x7E, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA9, 0x75, 0x70, 0xE4, 0xE9, 0x67, 0xA4, 0x69 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA1, 0x28, 0xFC, 0x30, 0xDF, 0x99, 0xF0, 0x4D ), + MBEDTLS_BYTES_TO_T_UINT_4( 0x33, 0x5B, 0x45, 0xA1 ), +}; +static const mbedtls_mpi_uint secp224k1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xA5, 0x61, 0x6D, 0x55, 0xDB, 0x4B, 0xCA, 0xE2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x59, 0xBD, 0xB0, 0xC0, 0xF7, 0x19, 0xE3, 0xF7 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD6, 0xFB, 0xCA, 0x82, 0x42, 0x34, 0xBA, 0x7F ), + MBEDTLS_BYTES_TO_T_UINT_4( 0xED, 0x9F, 0x08, 0x7E ), +}; +static const mbedtls_mpi_uint secp224k1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xF7, 0xB1, 0x9F, 0x76, 0x71, 0xA9, 0xF0, 0xCA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x84, 0x61, 0xEC, 0xD2, 0xE8, 0xDC, 0x01, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ), +}; +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +static const mbedtls_mpi_uint secp256k1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x2F, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256k1_a[] = { + MBEDTLS_BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp256k1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_2( 0x07, 0x00 ), +}; +static const mbedtls_mpi_uint secp256k1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x98, 0x17, 0xF8, 0x16, 0x5B, 0x81, 0xF2, 0x59 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD9, 0x28, 0xCE, 0x2D, 0xDB, 0xFC, 0x9B, 0x02 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x07, 0x0B, 0x87, 0xCE, 0x95, 0x62, 0xA0, 0x55 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAC, 0xBB, 0xDC, 0xF9, 0x7E, 0x66, 0xBE, 0x79 ), +}; +static const mbedtls_mpi_uint secp256k1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xB8, 0xD4, 0x10, 0xFB, 0x8F, 0xD0, 0x47, 0x9C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x19, 0x54, 0x85, 0xA6, 0x48, 0xB4, 0x17, 0xFD ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA8, 0x08, 0x11, 0x0E, 0xFC, 0xFB, 0xA4, 0x5D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x65, 0xC4, 0xA3, 0x26, 0x77, 0xDA, 0x3A, 0x48 ), +}; +static const mbedtls_mpi_uint secp256k1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x41, 0x41, 0x36, 0xD0, 0x8C, 0x5E, 0xD2, 0xBF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x3B, 0xA0, 0x48, 0xAF, 0xE6, 0xDC, 0xAE, 0xBA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +/* + * Domain parameters for brainpoolP256r1 (RFC 5639 3.4) + */ +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP256r1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_a[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), +}; +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +/* + * Domain parameters for brainpoolP384r1 (RFC 5639 3.6) + */ +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP384r1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_a[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), +}; +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +/* + * Domain parameters for brainpoolP512r1 (RFC 5639 3.7) + */ +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP512r1_p[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_a[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78 ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_b[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_gx[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81 ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_gy[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_n[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + MBEDTLS_BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), +}; +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +/* + * Create an MPI from embedded constants + * (assumes len is an exact multiple of sizeof mbedtls_mpi_uint) + */ +static inline void ecp_mpi_load( mbedtls_mpi *X, const mbedtls_mpi_uint *p, size_t len ) +{ + X->s = 1; + X->n = len / sizeof( mbedtls_mpi_uint ); + X->p = (mbedtls_mpi_uint *) p; +} + +/* + * Set an MPI to static value 1 + */ +static inline void ecp_mpi_set1( mbedtls_mpi *X ) +{ + static mbedtls_mpi_uint one[] = { 1 }; + X->s = 1; + X->n = 1; + X->p = one; +} + +/* + * Make group available from embedded constants + */ +static int ecp_group_load( mbedtls_ecp_group *grp, + const mbedtls_mpi_uint *p, size_t plen, + const mbedtls_mpi_uint *a, size_t alen, + const mbedtls_mpi_uint *b, size_t blen, + const mbedtls_mpi_uint *gx, size_t gxlen, + const mbedtls_mpi_uint *gy, size_t gylen, + const mbedtls_mpi_uint *n, size_t nlen) +{ + ecp_mpi_load( &grp->P, p, plen ); + if( a != NULL ) + ecp_mpi_load( &grp->A, a, alen ); + ecp_mpi_load( &grp->B, b, blen ); + ecp_mpi_load( &grp->N, n, nlen ); + + ecp_mpi_load( &grp->G.X, gx, gxlen ); + ecp_mpi_load( &grp->G.Y, gy, gylen ); + ecp_mpi_set1( &grp->G.Z ); + + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + grp->nbits = mbedtls_mpi_bitlen( &grp->N ); + + grp->h = 1; + + return( 0 ); +} + +#if defined(MBEDTLS_ECP_NIST_OPTIM) +/* Forward declarations */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +static int ecp_mod_p192( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +static int ecp_mod_p224( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +static int ecp_mod_p256( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +static int ecp_mod_p384( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +static int ecp_mod_p521( mbedtls_mpi * ); +#endif + +#define NIST_MODP( P ) grp->modp = ecp_mod_ ## P; +#else +#define NIST_MODP( P ) +#endif /* MBEDTLS_ECP_NIST_OPTIM */ + +/* Additional forward declarations */ +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +static int ecp_mod_p255( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +static int ecp_mod_p448( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +static int ecp_mod_p192k1( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +static int ecp_mod_p224k1( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +static int ecp_mod_p256k1( mbedtls_mpi * ); +#endif + +#define LOAD_GROUP_A( G ) ecp_group_load( grp, \ + G ## _p, sizeof( G ## _p ), \ + G ## _a, sizeof( G ## _a ), \ + G ## _b, sizeof( G ## _b ), \ + G ## _gx, sizeof( G ## _gx ), \ + G ## _gy, sizeof( G ## _gy ), \ + G ## _n, sizeof( G ## _n ) ) + +#define LOAD_GROUP( G ) ecp_group_load( grp, \ + G ## _p, sizeof( G ## _p ), \ + NULL, 0, \ + G ## _b, sizeof( G ## _b ), \ + G ## _gx, sizeof( G ## _gx ), \ + G ## _gy, sizeof( G ## _gy ), \ + G ## _n, sizeof( G ## _n ) ) + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +/* Constants used by ecp_use_curve25519() */ +static const mbedtls_mpi_sint curve25519_a24 = 0x01DB42; +static const unsigned char curve25519_part_of_n[] = { + 0x14, 0xDE, 0xF9, 0xDE, 0xA2, 0xF7, 0x9C, 0xD6, + 0x58, 0x12, 0x63, 0x1A, 0x5C, 0xF5, 0xD3, 0xED, +}; + +/* + * Specialized function for creating the Curve25519 group + */ +static int ecp_use_curve25519( mbedtls_ecp_group *grp ) +{ + int ret; + + /* Actually ( A + 2 ) / 4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->A, curve25519_a24 ) ); + + /* P = 2^255 - 19 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 255 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 19 ) ); + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + /* N = 2^252 + 27742317777372353535851937790883648493 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &grp->N, + curve25519_part_of_n, sizeof( curve25519_part_of_n ) ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &grp->N, 252, 1 ) ); + + /* Y intentionally not set, since we use x/z coordinates. + * This is used as a marker to identify Montgomery curves! */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.X, 9 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.Z, 1 ) ); + mbedtls_mpi_free( &grp->G.Y ); + + /* Actually, the required msb for private keys */ + grp->nbits = 254; + +cleanup: + if( ret != 0 ) + mbedtls_ecp_group_free( grp ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +/* Constants used by ecp_use_curve448() */ +static const mbedtls_mpi_sint curve448_a24 = 0x98AA; +static const unsigned char curve448_part_of_n[] = { + 0x83, 0x35, 0xDC, 0x16, 0x3B, 0xB1, 0x24, + 0xB6, 0x51, 0x29, 0xC9, 0x6F, 0xDE, 0x93, + 0x3D, 0x8D, 0x72, 0x3A, 0x70, 0xAA, 0xDC, + 0x87, 0x3D, 0x6D, 0x54, 0xA7, 0xBB, 0x0D, +}; + +/* + * Specialized function for creating the Curve448 group + */ +static int ecp_use_curve448( mbedtls_ecp_group *grp ) +{ + mbedtls_mpi Ns; + int ret; + + mbedtls_mpi_init( &Ns ); + + /* Actually ( A + 2 ) / 4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->A, curve448_a24 ) ); + + /* P = 2^448 - 2^224 - 1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 1 ) ); + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + /* Y intentionally not set, since we use x/z coordinates. + * This is used as a marker to identify Montgomery curves! */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.X, 5 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.Z, 1 ) ); + mbedtls_mpi_free( &grp->G.Y ); + + /* N = 2^446 - 13818066809895115352007386748515426880336692474882178609894547503885 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &grp->N, 446, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &Ns, + curve448_part_of_n, sizeof( curve448_part_of_n ) ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &grp->N, &grp->N, &Ns ) ); + + /* Actually, the required msb for private keys */ + grp->nbits = 447; + +cleanup: + mbedtls_mpi_free( &Ns ); + if( ret != 0 ) + mbedtls_ecp_group_free( grp ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +/* + * Set a group using well-known domain parameters + */ +int mbedtls_ecp_group_load( mbedtls_ecp_group *grp, mbedtls_ecp_group_id id ) +{ + ECP_VALIDATE_RET( grp != NULL ); + mbedtls_ecp_group_free( grp ); + + grp->id = id; + + switch( id ) + { +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + case MBEDTLS_ECP_DP_SECP192R1: + NIST_MODP( p192 ); + return( LOAD_GROUP( secp192r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + case MBEDTLS_ECP_DP_SECP224R1: + NIST_MODP( p224 ); + return( LOAD_GROUP( secp224r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + case MBEDTLS_ECP_DP_SECP256R1: + NIST_MODP( p256 ); + return( LOAD_GROUP( secp256r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + case MBEDTLS_ECP_DP_SECP384R1: + NIST_MODP( p384 ); + return( LOAD_GROUP( secp384r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + case MBEDTLS_ECP_DP_SECP521R1: + NIST_MODP( p521 ); + return( LOAD_GROUP( secp521r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + case MBEDTLS_ECP_DP_SECP192K1: + grp->modp = ecp_mod_p192k1; + return( LOAD_GROUP_A( secp192k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + case MBEDTLS_ECP_DP_SECP224K1: + grp->modp = ecp_mod_p224k1; + return( LOAD_GROUP_A( secp224k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + case MBEDTLS_ECP_DP_SECP256K1: + grp->modp = ecp_mod_p256k1; + return( LOAD_GROUP_A( secp256k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + case MBEDTLS_ECP_DP_BP256R1: + return( LOAD_GROUP_A( brainpoolP256r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + case MBEDTLS_ECP_DP_BP384R1: + return( LOAD_GROUP_A( brainpoolP384r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + case MBEDTLS_ECP_DP_BP512R1: + return( LOAD_GROUP_A( brainpoolP512r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + case MBEDTLS_ECP_DP_CURVE25519: + grp->modp = ecp_mod_p255; + return( ecp_use_curve25519( grp ) ); +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + case MBEDTLS_ECP_DP_CURVE448: + grp->modp = ecp_mod_p448; + return( ecp_use_curve448( grp ) ); +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + + default: + mbedtls_ecp_group_free( grp ); + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + } +} + +#if defined(MBEDTLS_ECP_NIST_OPTIM) +/* + * Fast reduction modulo the primes used by the NIST curves. + * + * These functions are critical for speed, but not needed for correct + * operations. So, we make the choice to heavily rely on the internals of our + * bignum library, which creates a tight coupling between these functions and + * our MPI implementation. However, the coupling between the ECP module and + * MPI remains loose, since these functions can be deactivated at will. + */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +/* + * Compared to the way things are presented in FIPS 186-3 D.2, + * we proceed in columns, from right (least significant chunk) to left, + * adding chunks to N in place, and keeping a carry for the next chunk. + * This avoids moving things around in memory, and uselessly adding zeros, + * compared to the more straightforward, line-oriented approach. + * + * For this prime we need to handle data in chunks of 64 bits. + * Since this is always a multiple of our basic mbedtls_mpi_uint, we can + * use a mbedtls_mpi_uint * to designate such a chunk, and small loops to handle it. + */ + +/* Add 64-bit chunks (dst += src) and update carry */ +static inline void add64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *src, mbedtls_mpi_uint *carry ) +{ + unsigned char i; + mbedtls_mpi_uint c = 0; + for( i = 0; i < 8 / sizeof( mbedtls_mpi_uint ); i++, dst++, src++ ) + { + *dst += c; c = ( *dst < c ); + *dst += *src; c += ( *dst < *src ); + } + *carry += c; +} + +/* Add carry to a 64-bit chunk and update carry */ +static inline void carry64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *carry ) +{ + unsigned char i; + for( i = 0; i < 8 / sizeof( mbedtls_mpi_uint ); i++, dst++ ) + { + *dst += *carry; + *carry = ( *dst < *carry ); + } +} + +#define WIDTH 8 / sizeof( mbedtls_mpi_uint ) +#define A( i ) N->p + (i) * WIDTH +#define ADD( i ) add64( p, A( i ), &c ) +#define NEXT p += WIDTH; carry64( p, &c ) +#define LAST p += WIDTH; *p = c; while( ++p < end ) *p = 0 + +/* + * Fast quasi-reduction modulo p192 (FIPS 186-3 D.2.1) + */ +static int ecp_mod_p192( mbedtls_mpi *N ) +{ + int ret; + mbedtls_mpi_uint c = 0; + mbedtls_mpi_uint *p, *end; + + /* Make sure we have enough blocks so that A(5) is legal */ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( N, 6 * WIDTH ) ); + + p = N->p; + end = p + N->n; + + ADD( 3 ); ADD( 5 ); NEXT; // A0 += A3 + A5 + ADD( 3 ); ADD( 4 ); ADD( 5 ); NEXT; // A1 += A3 + A4 + A5 + ADD( 4 ); ADD( 5 ); LAST; // A2 += A4 + A5 + +cleanup: + return( ret ); +} + +#undef WIDTH +#undef A +#undef ADD +#undef NEXT +#undef LAST +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +/* + * The reader is advised to first understand ecp_mod_p192() since the same + * general structure is used here, but with additional complications: + * (1) chunks of 32 bits, and (2) subtractions. + */ + +/* + * For these primes, we need to handle data in chunks of 32 bits. + * This makes it more complicated if we use 64 bits limbs in MPI, + * which prevents us from using a uniform access method as for p192. + * + * So, we define a mini abstraction layer to access 32 bit chunks, + * load them in 'cur' for work, and store them back from 'cur' when done. + * + * While at it, also define the size of N in terms of 32-bit chunks. + */ +#define LOAD32 cur = A( i ); + +#if defined(MBEDTLS_HAVE_INT32) /* 32 bit */ + +#define MAX32 N->n +#define A( j ) N->p[j] +#define STORE32 N->p[i] = cur; + +#else /* 64-bit */ + +#define MAX32 N->n * 2 +#define A( j ) (j) % 2 ? (uint32_t)( N->p[(j)/2] >> 32 ) : \ + (uint32_t)( N->p[(j)/2] ) +#define STORE32 \ + if( i % 2 ) { \ + N->p[i/2] &= 0x00000000FFFFFFFF; \ + N->p[i/2] |= ((mbedtls_mpi_uint) cur) << 32; \ + } else { \ + N->p[i/2] &= 0xFFFFFFFF00000000; \ + N->p[i/2] |= (mbedtls_mpi_uint) cur; \ + } + +#endif /* sizeof( mbedtls_mpi_uint ) */ + +/* + * Helpers for addition and subtraction of chunks, with signed carry. + */ +static inline void add32( uint32_t *dst, uint32_t src, signed char *carry ) +{ + *dst += src; + *carry += ( *dst < src ); +} + +static inline void sub32( uint32_t *dst, uint32_t src, signed char *carry ) +{ + *carry -= ( *dst < src ); + *dst -= src; +} + +#define ADD( j ) add32( &cur, A( j ), &c ); +#define SUB( j ) sub32( &cur, A( j ), &c ); + +/* + * Helpers for the main 'loop' + * (see fix_negative for the motivation of C) + */ +#define INIT( b ) \ + int ret; \ + signed char c = 0, cc; \ + uint32_t cur; \ + size_t i = 0, bits = (b); \ + mbedtls_mpi C; \ + mbedtls_mpi_uint Cp[ (b) / 8 / sizeof( mbedtls_mpi_uint) + 1 ]; \ + \ + C.s = 1; \ + C.n = (b) / 8 / sizeof( mbedtls_mpi_uint) + 1; \ + C.p = Cp; \ + memset( Cp, 0, C.n * sizeof( mbedtls_mpi_uint ) ); \ + \ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( N, (b) * 2 / 8 / \ + sizeof( mbedtls_mpi_uint ) ) ); \ + LOAD32; + +#define NEXT \ + STORE32; i++; LOAD32; \ + cc = c; c = 0; \ + if( cc < 0 ) \ + sub32( &cur, -cc, &c ); \ + else \ + add32( &cur, cc, &c ); \ + +#define LAST \ + STORE32; i++; \ + cur = c > 0 ? c : 0; STORE32; \ + cur = 0; while( ++i < MAX32 ) { STORE32; } \ + if( c < 0 ) MBEDTLS_MPI_CHK( fix_negative( N, c, &C, bits ) ); + +/* + * If the result is negative, we get it in the form + * c * 2^bits + N, with c negative and N positive shorter than 'bits' + */ +static inline int fix_negative( mbedtls_mpi *N, signed char c, mbedtls_mpi *C, size_t bits ) +{ + int ret; + + /* C = - c * 2^bits */ +#if !defined(MBEDTLS_HAVE_INT64) + ((void) bits); +#else + if( bits == 224 ) + C->p[ C->n - 1 ] = ((mbedtls_mpi_uint) -c) << 32; + else +#endif + C->p[ C->n - 1 ] = (mbedtls_mpi_uint) -c; + + /* N = - ( C - N ) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( N, C, N ) ); + N->s = -1; + +cleanup: + + return( ret ); +} + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +/* + * Fast quasi-reduction modulo p224 (FIPS 186-3 D.2.2) + */ +static int ecp_mod_p224( mbedtls_mpi *N ) +{ + INIT( 224 ); + + SUB( 7 ); SUB( 11 ); NEXT; // A0 += -A7 - A11 + SUB( 8 ); SUB( 12 ); NEXT; // A1 += -A8 - A12 + SUB( 9 ); SUB( 13 ); NEXT; // A2 += -A9 - A13 + SUB( 10 ); ADD( 7 ); ADD( 11 ); NEXT; // A3 += -A10 + A7 + A11 + SUB( 11 ); ADD( 8 ); ADD( 12 ); NEXT; // A4 += -A11 + A8 + A12 + SUB( 12 ); ADD( 9 ); ADD( 13 ); NEXT; // A5 += -A12 + A9 + A13 + SUB( 13 ); ADD( 10 ); LAST; // A6 += -A13 + A10 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +/* + * Fast quasi-reduction modulo p256 (FIPS 186-3 D.2.3) + */ +static int ecp_mod_p256( mbedtls_mpi *N ) +{ + INIT( 256 ); + + ADD( 8 ); ADD( 9 ); + SUB( 11 ); SUB( 12 ); SUB( 13 ); SUB( 14 ); NEXT; // A0 + + ADD( 9 ); ADD( 10 ); + SUB( 12 ); SUB( 13 ); SUB( 14 ); SUB( 15 ); NEXT; // A1 + + ADD( 10 ); ADD( 11 ); + SUB( 13 ); SUB( 14 ); SUB( 15 ); NEXT; // A2 + + ADD( 11 ); ADD( 11 ); ADD( 12 ); ADD( 12 ); ADD( 13 ); + SUB( 15 ); SUB( 8 ); SUB( 9 ); NEXT; // A3 + + ADD( 12 ); ADD( 12 ); ADD( 13 ); ADD( 13 ); ADD( 14 ); + SUB( 9 ); SUB( 10 ); NEXT; // A4 + + ADD( 13 ); ADD( 13 ); ADD( 14 ); ADD( 14 ); ADD( 15 ); + SUB( 10 ); SUB( 11 ); NEXT; // A5 + + ADD( 14 ); ADD( 14 ); ADD( 15 ); ADD( 15 ); ADD( 14 ); ADD( 13 ); + SUB( 8 ); SUB( 9 ); NEXT; // A6 + + ADD( 15 ); ADD( 15 ); ADD( 15 ); ADD( 8 ); + SUB( 10 ); SUB( 11 ); SUB( 12 ); SUB( 13 ); LAST; // A7 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +/* + * Fast quasi-reduction modulo p384 (FIPS 186-3 D.2.4) + */ +static int ecp_mod_p384( mbedtls_mpi *N ) +{ + INIT( 384 ); + + ADD( 12 ); ADD( 21 ); ADD( 20 ); + SUB( 23 ); NEXT; // A0 + + ADD( 13 ); ADD( 22 ); ADD( 23 ); + SUB( 12 ); SUB( 20 ); NEXT; // A2 + + ADD( 14 ); ADD( 23 ); + SUB( 13 ); SUB( 21 ); NEXT; // A2 + + ADD( 15 ); ADD( 12 ); ADD( 20 ); ADD( 21 ); + SUB( 14 ); SUB( 22 ); SUB( 23 ); NEXT; // A3 + + ADD( 21 ); ADD( 21 ); ADD( 16 ); ADD( 13 ); ADD( 12 ); ADD( 20 ); ADD( 22 ); + SUB( 15 ); SUB( 23 ); SUB( 23 ); NEXT; // A4 + + ADD( 22 ); ADD( 22 ); ADD( 17 ); ADD( 14 ); ADD( 13 ); ADD( 21 ); ADD( 23 ); + SUB( 16 ); NEXT; // A5 + + ADD( 23 ); ADD( 23 ); ADD( 18 ); ADD( 15 ); ADD( 14 ); ADD( 22 ); + SUB( 17 ); NEXT; // A6 + + ADD( 19 ); ADD( 16 ); ADD( 15 ); ADD( 23 ); + SUB( 18 ); NEXT; // A7 + + ADD( 20 ); ADD( 17 ); ADD( 16 ); + SUB( 19 ); NEXT; // A8 + + ADD( 21 ); ADD( 18 ); ADD( 17 ); + SUB( 20 ); NEXT; // A9 + + ADD( 22 ); ADD( 19 ); ADD( 18 ); + SUB( 21 ); NEXT; // A10 + + ADD( 23 ); ADD( 20 ); ADD( 19 ); + SUB( 22 ); LAST; // A11 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#undef A +#undef LOAD32 +#undef STORE32 +#undef MAX32 +#undef INIT +#undef NEXT +#undef LAST + +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED || + MBEDTLS_ECP_DP_SECP256R1_ENABLED || + MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +/* + * Here we have an actual Mersenne prime, so things are more straightforward. + * However, chunks are aligned on a 'weird' boundary (521 bits). + */ + +/* Size of p521 in terms of mbedtls_mpi_uint */ +#define P521_WIDTH ( 521 / 8 / sizeof( mbedtls_mpi_uint ) + 1 ) + +/* Bits to keep in the most significant mbedtls_mpi_uint */ +#define P521_MASK 0x01FF + +/* + * Fast quasi-reduction modulo p521 (FIPS 186-3 D.2.5) + * Write N as A1 + 2^521 A0, return A0 + A1 + */ +static int ecp_mod_p521( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P521_WIDTH + 1]; + /* Worst case for the size of M is when mbedtls_mpi_uint is 16 bits: + * we need to hold bits 513 to 1056, which is 34 limbs, that is + * P521_WIDTH + 1. Otherwise P521_WIDTH is enough. */ + + if( N->n < P521_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P521_WIDTH - 1 ); + if( M.n > P521_WIDTH + 1 ) + M.n = P521_WIDTH + 1; + M.p = Mp; + memcpy( Mp, N->p + P521_WIDTH - 1, M.n * sizeof( mbedtls_mpi_uint ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, 521 % ( 8 * sizeof( mbedtls_mpi_uint ) ) ) ); + + /* N = A0 */ + N->p[P521_WIDTH - 1] &= P521_MASK; + for( i = P521_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} + +#undef P521_WIDTH +#undef P521_MASK +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#endif /* MBEDTLS_ECP_NIST_OPTIM */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + +/* Size of p255 in terms of mbedtls_mpi_uint */ +#define P255_WIDTH ( 255 / 8 / sizeof( mbedtls_mpi_uint ) + 1 ) + +/* + * Fast quasi-reduction modulo p255 = 2^255 - 19 + * Write N as A0 + 2^255 A1, return A0 + 19 * A1 + */ +static int ecp_mod_p255( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P255_WIDTH + 2]; + + if( N->n < P255_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P255_WIDTH - 1 ); + if( M.n > P255_WIDTH + 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + M.p = Mp; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + P255_WIDTH - 1, M.n * sizeof( mbedtls_mpi_uint ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, 255 % ( 8 * sizeof( mbedtls_mpi_uint ) ) ) ); + M.n++; /* Make room for multiplication by 19 */ + + /* N = A0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( N, 255, 0 ) ); + for( i = P255_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + 19 * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &M, 19 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + +/* Size of p448 in terms of mbedtls_mpi_uint */ +#define P448_WIDTH ( 448 / 8 / sizeof( mbedtls_mpi_uint ) ) + +/* Number of limbs fully occupied by 2^224 (max), and limbs used by it (min) */ +#define DIV_ROUND_UP( X, Y ) ( ( ( X ) + ( Y ) - 1 ) / ( Y ) ) +#define P224_WIDTH_MIN ( 28 / sizeof( mbedtls_mpi_uint ) ) +#define P224_WIDTH_MAX DIV_ROUND_UP( 28, sizeof( mbedtls_mpi_uint ) ) +#define P224_UNUSED_BITS ( ( P224_WIDTH_MAX * sizeof( mbedtls_mpi_uint ) * 8 ) - 224 ) + +/* + * Fast quasi-reduction modulo p448 = 2^448 - 2^224 - 1 + * Write N as A0 + 2^448 A1 and A1 as B0 + 2^224 B1, and return + * A0 + A1 + B1 + (B0 + B1) * 2^224. This is different to the reference + * implementation of Curve448, which uses its own special 56-bit limbs rather + * than a generic bignum library. We could squeeze some extra speed out on + * 32-bit machines by splitting N up into 32-bit limbs and doing the + * arithmetic using the limbs directly as we do for the NIST primes above, + * but for 64-bit targets it should use half the number of operations if we do + * the reduction with 224-bit limbs, since mpi_add_mpi will then use 64-bit adds. + */ +static int ecp_mod_p448( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M, Q; + mbedtls_mpi_uint Mp[P448_WIDTH + 1], Qp[P448_WIDTH]; + + if( N->n <= P448_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P448_WIDTH ); + if( M.n > P448_WIDTH ) + /* Shouldn't be called with N larger than 2^896! */ + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + M.p = Mp; + memset( Mp, 0, sizeof( Mp ) ); + memcpy( Mp, N->p + P448_WIDTH, M.n * sizeof( mbedtls_mpi_uint ) ); + + /* N = A0 */ + for( i = P448_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N += A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &M ) ); + + /* Q = B1, N += B1 */ + Q = M; + Q.p = Qp; + memcpy( Qp, Mp, sizeof( Qp ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &Q, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &Q ) ); + + /* M = (B0 + B1) * 2^224, N += M */ + if( sizeof( mbedtls_mpi_uint ) > 4 ) + Mp[P224_WIDTH_MIN] &= ( (mbedtls_mpi_uint)-1 ) >> ( P224_UNUSED_BITS ); + for( i = P224_WIDTH_MAX; i < M.n; ++i ) + Mp[i] = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &M, &M, &Q ) ); + M.n = P448_WIDTH + 1; /* Make room for shifted carry bit from the addition */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &M, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* + * Fast quasi-reduction modulo P = 2^s - R, + * with R about 33 bits, used by the Koblitz curves. + * + * Write N as A0 + 2^224 A1, return A0 + R * A1. + * Actually do two passes, since R is big. + */ +#define P_KOBLITZ_MAX ( 256 / 8 / sizeof( mbedtls_mpi_uint ) ) // Max limbs in P +#define P_KOBLITZ_R ( 8 / sizeof( mbedtls_mpi_uint ) ) // Limbs in R +static inline int ecp_mod_koblitz( mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p_limbs, + size_t adjust, size_t shift, mbedtls_mpi_uint mask ) +{ + int ret; + size_t i; + mbedtls_mpi M, R; + mbedtls_mpi_uint Mp[P_KOBLITZ_MAX + P_KOBLITZ_R + 1]; + + if( N->n < p_limbs ) + return( 0 ); + + /* Init R */ + R.s = 1; + R.p = Rp; + R.n = P_KOBLITZ_R; + + /* Common setup for M */ + M.s = 1; + M.p = Mp; + + /* M = A1 */ + M.n = N->n - ( p_limbs - adjust ); + if( M.n > p_limbs + adjust ) + M.n = p_limbs + adjust; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + p_limbs - adjust, M.n * sizeof( mbedtls_mpi_uint ) ); + if( shift != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, shift ) ); + M.n += R.n; /* Make room for multiplication by R */ + + /* N = A0 */ + if( mask != 0 ) + N->p[p_limbs - 1] &= mask; + for( i = p_limbs; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + R * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &M, &M, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + + /* Second pass */ + + /* M = A1 */ + M.n = N->n - ( p_limbs - adjust ); + if( M.n > p_limbs + adjust ) + M.n = p_limbs + adjust; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + p_limbs - adjust, M.n * sizeof( mbedtls_mpi_uint ) ); + if( shift != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, shift ) ); + M.n += R.n; /* Make room for multiplication by R */ + + /* N = A0 */ + if( mask != 0 ) + N->p[p_limbs - 1] &= mask; + for( i = p_limbs; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + R * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &M, &M, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED) || + MBEDTLS_ECP_DP_SECP224K1_ENABLED) || + MBEDTLS_ECP_DP_SECP256K1_ENABLED) */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +/* + * Fast quasi-reduction modulo p192k1 = 2^192 - R, + * with R = 2^32 + 2^12 + 2^8 + 2^7 + 2^6 + 2^3 + 1 = 0x0100001119 + */ +static int ecp_mod_p192k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xC9, 0x11, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00 ) }; + + return( ecp_mod_koblitz( N, Rp, 192 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, + 0 ) ); +} +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +/* + * Fast quasi-reduction modulo p224k1 = 2^224 - R, + * with R = 2^32 + 2^12 + 2^11 + 2^9 + 2^7 + 2^4 + 2 + 1 = 0x0100001A93 + */ +static int ecp_mod_p224k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0x93, 0x1A, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00 ) }; + +#if defined(MBEDTLS_HAVE_INT64) + return( ecp_mod_koblitz( N, Rp, 4, 1, 32, 0xFFFFFFFF ) ); +#else + return( ecp_mod_koblitz( N, Rp, 224 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, + 0 ) ); +#endif +} + +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* + * Fast quasi-reduction modulo p256k1 = 2^256 - R, + * with R = 2^32 + 2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1 = 0x01000003D1 + */ +static int ecp_mod_p256k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + MBEDTLS_BYTES_TO_T_UINT_8( 0xD1, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00 ) }; + return( ecp_mod_koblitz( N, Rp, 256 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, + 0 ) ); +} +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#endif /* !MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/src/common/mbedtls/library/mbedtls_gcm.c b/src/common/mbedtls/library/mbedtls_gcm.c new file mode 100644 index 0000000000..0c9f241dc8 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_gcm.c @@ -0,0 +1,1007 @@ +/* + * NIST SP800-38D compliant GCM implementation + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +/* + * https://csrc.nist.gov/publications/nistpubs/800-38D/SP-800-38D.pdf + * + * See also: + * [MGV] https://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf + * + * We use the algorithm described as Shoup's method with 4-bit tables in + * [MGV] 4.1, pp. 12-13, to enhance speed without using too much memory. + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_GCM_C) + +#include "mbedtls/gcm.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_AESNI_C) +#include "mbedtls/aesni.h" +#endif + +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#if !defined(MBEDTLS_PLATFORM_C) +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ + +#if !defined(MBEDTLS_GCM_ALT) + +/* Parameter validation macros */ +#define GCM_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_GCM_BAD_INPUT ) +#define GCM_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +/* + * 32-bit integer manipulation macros (big endian) + */ +#ifndef GET_UINT32_BE +#define GET_UINT32_BE(n,b,i) \ +{ \ + (n) = ( (uint32_t) (b)[(i) ] << 24 ) \ + | ( (uint32_t) (b)[(i) + 1] << 16 ) \ + | ( (uint32_t) (b)[(i) + 2] << 8 ) \ + | ( (uint32_t) (b)[(i) + 3] ); \ +} +#endif + +#ifndef PUT_UINT32_BE +#define PUT_UINT32_BE(n,b,i) \ +{ \ + (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ +} +#endif + +/* + * Initialize a context + */ +void mbedtls_gcm_init( mbedtls_gcm_context *ctx ) +{ + GCM_VALIDATE( ctx != NULL ); + memset( ctx, 0, sizeof( mbedtls_gcm_context ) ); +} + +/* + * Precompute small multiples of H, that is set + * HH[i] || HL[i] = H times i, + * where i is seen as a field element as in [MGV], ie high-order bits + * correspond to low powers of P. The result is stored in the same way, that + * is the high-order bit of HH corresponds to P^0 and the low-order bit of HL + * corresponds to P^127. + */ +static int gcm_gen_table( mbedtls_gcm_context *ctx ) +{ + int ret, i, j; + uint64_t hi, lo; + uint64_t vl, vh; + unsigned char h[16]; + size_t olen = 0; + + memset( h, 0, 16 ); + if( ( ret = mbedtls_cipher_update( &ctx->cipher_ctx, h, 16, h, &olen ) ) != 0 ) + return( ret ); + + /* pack h as two 64-bits ints, big-endian */ + GET_UINT32_BE( hi, h, 0 ); + GET_UINT32_BE( lo, h, 4 ); + vh = (uint64_t) hi << 32 | lo; + + GET_UINT32_BE( hi, h, 8 ); + GET_UINT32_BE( lo, h, 12 ); + vl = (uint64_t) hi << 32 | lo; + + /* 8 = 1000 corresponds to 1 in GF(2^128) */ + ctx->HL[8] = vl; + ctx->HH[8] = vh; + +#if defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_HAVE_X86_64) + /* With CLMUL support, we need only h, not the rest of the table */ + if( mbedtls_aesni_has_support( MBEDTLS_AESNI_CLMUL ) ) + return( 0 ); +#endif + + /* 0 corresponds to 0 in GF(2^128) */ + ctx->HH[0] = 0; + ctx->HL[0] = 0; + + for( i = 4; i > 0; i >>= 1 ) + { + uint32_t T = ( vl & 1 ) * 0xe1000000U; + vl = ( vh << 63 ) | ( vl >> 1 ); + vh = ( vh >> 1 ) ^ ( (uint64_t) T << 32); + + ctx->HL[i] = vl; + ctx->HH[i] = vh; + } + + for( i = 2; i <= 8; i *= 2 ) + { + uint64_t *HiL = ctx->HL + i, *HiH = ctx->HH + i; + vh = *HiH; + vl = *HiL; + for( j = 1; j < i; j++ ) + { + HiH[j] = vh ^ ctx->HH[j]; + HiL[j] = vl ^ ctx->HL[j]; + } + } + + return( 0 ); +} + +int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ) +{ + int ret; + const mbedtls_cipher_info_t *cipher_info; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( key != NULL ); + GCM_VALIDATE_RET( keybits == 128 || keybits == 192 || keybits == 256 ); + + cipher_info = mbedtls_cipher_info_from_values( cipher, keybits, MBEDTLS_MODE_ECB ); + if( cipher_info == NULL ) + return( MBEDTLS_ERR_GCM_BAD_INPUT ); + + if( cipher_info->block_size != 16 ) + return( MBEDTLS_ERR_GCM_BAD_INPUT ); + + mbedtls_cipher_free( &ctx->cipher_ctx ); + + if( ( ret = mbedtls_cipher_setup( &ctx->cipher_ctx, cipher_info ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_cipher_setkey( &ctx->cipher_ctx, key, keybits, + MBEDTLS_ENCRYPT ) ) != 0 ) + { + return( ret ); + } + + if( ( ret = gcm_gen_table( ctx ) ) != 0 ) + return( ret ); + + return( 0 ); +} + +/* + * Shoup's method for multiplication use this table with + * last4[x] = x times P^128 + * where x and last4[x] are seen as elements of GF(2^128) as in [MGV] + */ +static const uint64_t last4[16] = +{ + 0x0000, 0x1c20, 0x3840, 0x2460, + 0x7080, 0x6ca0, 0x48c0, 0x54e0, + 0xe100, 0xfd20, 0xd940, 0xc560, + 0x9180, 0x8da0, 0xa9c0, 0xb5e0 +}; + +/* + * Sets output to x times H using the precomputed tables. + * x and output are seen as elements of GF(2^128) as in [MGV]. + */ +static void gcm_mult( mbedtls_gcm_context *ctx, const unsigned char x[16], + unsigned char output[16] ) +{ + int i = 0; + unsigned char lo, hi, rem; + uint64_t zh, zl; + +#if defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_HAVE_X86_64) + if( mbedtls_aesni_has_support( MBEDTLS_AESNI_CLMUL ) ) { + unsigned char h[16]; + + PUT_UINT32_BE( ctx->HH[8] >> 32, h, 0 ); + PUT_UINT32_BE( ctx->HH[8], h, 4 ); + PUT_UINT32_BE( ctx->HL[8] >> 32, h, 8 ); + PUT_UINT32_BE( ctx->HL[8], h, 12 ); + + mbedtls_aesni_gcm_mult( output, x, h ); + return; + } +#endif /* MBEDTLS_AESNI_C && MBEDTLS_HAVE_X86_64 */ + + lo = x[15] & 0xf; + + zh = ctx->HH[lo]; + zl = ctx->HL[lo]; + + for( i = 15; i >= 0; i-- ) + { + lo = x[i] & 0xf; + hi = x[i] >> 4; + + if( i != 15 ) + { + rem = (unsigned char) zl & 0xf; + zl = ( zh << 60 ) | ( zl >> 4 ); + zh = ( zh >> 4 ); + zh ^= (uint64_t) last4[rem] << 48; + zh ^= ctx->HH[lo]; + zl ^= ctx->HL[lo]; + + } + + rem = (unsigned char) zl & 0xf; + zl = ( zh << 60 ) | ( zl >> 4 ); + zh = ( zh >> 4 ); + zh ^= (uint64_t) last4[rem] << 48; + zh ^= ctx->HH[hi]; + zl ^= ctx->HL[hi]; + } + + PUT_UINT32_BE( zh >> 32, output, 0 ); + PUT_UINT32_BE( zh, output, 4 ); + PUT_UINT32_BE( zl >> 32, output, 8 ); + PUT_UINT32_BE( zl, output, 12 ); +} + +int mbedtls_gcm_starts( mbedtls_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len ) +{ + int ret; + unsigned char work_buf[16]; + size_t i; + const unsigned char *p; + size_t use_len, olen = 0; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( iv != NULL ); + GCM_VALIDATE_RET( add_len == 0 || add != NULL ); + + /* IV and AD are limited to 2^64 bits, so 2^61 bytes */ + /* IV is not allowed to be zero length */ + if( iv_len == 0 || + ( (uint64_t) iv_len ) >> 61 != 0 || + ( (uint64_t) add_len ) >> 61 != 0 ) + { + return( MBEDTLS_ERR_GCM_BAD_INPUT ); + } + + memset( ctx->y, 0x00, sizeof(ctx->y) ); + memset( ctx->buf, 0x00, sizeof(ctx->buf) ); + + ctx->mode = mode; + ctx->len = 0; + ctx->add_len = 0; + + if( iv_len == 12 ) + { + memcpy( ctx->y, iv, iv_len ); + ctx->y[15] = 1; + } + else + { + memset( work_buf, 0x00, 16 ); + PUT_UINT32_BE( iv_len * 8, work_buf, 12 ); + + p = iv; + while( iv_len > 0 ) + { + use_len = ( iv_len < 16 ) ? iv_len : 16; + + for( i = 0; i < use_len; i++ ) + ctx->y[i] ^= p[i]; + + gcm_mult( ctx, ctx->y, ctx->y ); + + iv_len -= use_len; + p += use_len; + } + + for( i = 0; i < 16; i++ ) + ctx->y[i] ^= work_buf[i]; + + gcm_mult( ctx, ctx->y, ctx->y ); + } + + if( ( ret = mbedtls_cipher_update( &ctx->cipher_ctx, ctx->y, 16, ctx->base_ectr, + &olen ) ) != 0 ) + { + return( ret ); + } + + ctx->add_len = add_len; + p = add; + while( add_len > 0 ) + { + use_len = ( add_len < 16 ) ? add_len : 16; + + for( i = 0; i < use_len; i++ ) + ctx->buf[i] ^= p[i]; + + gcm_mult( ctx, ctx->buf, ctx->buf ); + + add_len -= use_len; + p += use_len; + } + + return( 0 ); +} + +int mbedtls_gcm_update( mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *input, + unsigned char *output ) +{ + int ret; + unsigned char ectr[16]; + size_t i; + const unsigned char *p; + unsigned char *out_p = output; + size_t use_len, olen = 0; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( length == 0 || input != NULL ); + GCM_VALIDATE_RET( length == 0 || output != NULL ); + + if( output > input && (size_t) ( output - input ) < length ) + return( MBEDTLS_ERR_GCM_BAD_INPUT ); + + /* Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes + * Also check for possible overflow */ + if( ctx->len + length < ctx->len || + (uint64_t) ctx->len + length > 0xFFFFFFFE0ull ) + { + return( MBEDTLS_ERR_GCM_BAD_INPUT ); + } + + ctx->len += length; + + p = input; + while( length > 0 ) + { + use_len = ( length < 16 ) ? length : 16; + + for( i = 16; i > 12; i-- ) + if( ++ctx->y[i - 1] != 0 ) + break; + + if( ( ret = mbedtls_cipher_update( &ctx->cipher_ctx, ctx->y, 16, ectr, + &olen ) ) != 0 ) + { + return( ret ); + } + + for( i = 0; i < use_len; i++ ) + { + if( ctx->mode == MBEDTLS_GCM_DECRYPT ) + ctx->buf[i] ^= p[i]; + out_p[i] = ectr[i] ^ p[i]; + if( ctx->mode == MBEDTLS_GCM_ENCRYPT ) + ctx->buf[i] ^= out_p[i]; + } + + gcm_mult( ctx, ctx->buf, ctx->buf ); + + length -= use_len; + p += use_len; + out_p += use_len; + } + + return( 0 ); +} + +int mbedtls_gcm_finish( mbedtls_gcm_context *ctx, + unsigned char *tag, + size_t tag_len ) +{ + unsigned char work_buf[16]; + size_t i; + uint64_t orig_len; + uint64_t orig_add_len; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( tag != NULL ); + + orig_len = ctx->len * 8; + orig_add_len = ctx->add_len * 8; + + if( tag_len > 16 || tag_len < 4 ) + return( MBEDTLS_ERR_GCM_BAD_INPUT ); + + memcpy( tag, ctx->base_ectr, tag_len ); + + if( orig_len || orig_add_len ) + { + memset( work_buf, 0x00, 16 ); + + PUT_UINT32_BE( ( orig_add_len >> 32 ), work_buf, 0 ); + PUT_UINT32_BE( ( orig_add_len ), work_buf, 4 ); + PUT_UINT32_BE( ( orig_len >> 32 ), work_buf, 8 ); + PUT_UINT32_BE( ( orig_len ), work_buf, 12 ); + + for( i = 0; i < 16; i++ ) + ctx->buf[i] ^= work_buf[i]; + + gcm_mult( ctx, ctx->buf, ctx->buf ); + + for( i = 0; i < tag_len; i++ ) + tag[i] ^= ctx->buf[i]; + } + + return( 0 ); +} + +int mbedtls_gcm_crypt_and_tag( mbedtls_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ) +{ + int ret; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( iv != NULL ); + GCM_VALIDATE_RET( add_len == 0 || add != NULL ); + GCM_VALIDATE_RET( length == 0 || input != NULL ); + GCM_VALIDATE_RET( length == 0 || output != NULL ); + GCM_VALIDATE_RET( tag != NULL ); + + if( ( ret = mbedtls_gcm_starts( ctx, mode, iv, iv_len, add, add_len ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_gcm_update( ctx, length, input, output ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_gcm_finish( ctx, tag, tag_len ) ) != 0 ) + return( ret ); + + return( 0 ); +} + +int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ) +{ + int ret; + unsigned char check_tag[16]; + size_t i; + int diff; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( iv != NULL ); + GCM_VALIDATE_RET( add_len == 0 || add != NULL ); + GCM_VALIDATE_RET( tag != NULL ); + GCM_VALIDATE_RET( length == 0 || input != NULL ); + GCM_VALIDATE_RET( length == 0 || output != NULL ); + + if( ( ret = mbedtls_gcm_crypt_and_tag( ctx, MBEDTLS_GCM_DECRYPT, length, + iv, iv_len, add, add_len, + input, output, tag_len, check_tag ) ) != 0 ) + { + return( ret ); + } + + /* Check tag in "constant-time" */ + for( diff = 0, i = 0; i < tag_len; i++ ) + diff |= tag[i] ^ check_tag[i]; + + if( diff != 0 ) + { + mbedtls_platform_zeroize( output, length ); + return( MBEDTLS_ERR_GCM_AUTH_FAILED ); + } + + return( 0 ); +} + +void mbedtls_gcm_free( mbedtls_gcm_context *ctx ) +{ + if( ctx == NULL ) + return; + mbedtls_cipher_free( &ctx->cipher_ctx ); + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_gcm_context ) ); +} + +#endif /* !MBEDTLS_GCM_ALT */ + +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +/* + * AES-GCM test vectors from: + * + * https://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip + */ +#define MAX_TESTS 6 + +static const int key_index[MAX_TESTS] = + { 0, 0, 1, 1, 1, 1 }; + +static const unsigned char key[MAX_TESTS][32] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c, + 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08, + 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c, + 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 }, +}; + +static const size_t iv_len[MAX_TESTS] = + { 12, 12, 12, 12, 8, 60 }; + +static const int iv_index[MAX_TESTS] = + { 0, 0, 1, 1, 1, 2 }; + +static const unsigned char iv[MAX_TESTS][64] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 }, + { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad, + 0xde, 0xca, 0xf8, 0x88 }, + { 0x93, 0x13, 0x22, 0x5d, 0xf8, 0x84, 0x06, 0xe5, + 0x55, 0x90, 0x9c, 0x5a, 0xff, 0x52, 0x69, 0xaa, + 0x6a, 0x7a, 0x95, 0x38, 0x53, 0x4f, 0x7d, 0xa1, + 0xe4, 0xc3, 0x03, 0xd2, 0xa3, 0x18, 0xa7, 0x28, + 0xc3, 0xc0, 0xc9, 0x51, 0x56, 0x80, 0x95, 0x39, + 0xfc, 0xf0, 0xe2, 0x42, 0x9a, 0x6b, 0x52, 0x54, + 0x16, 0xae, 0xdb, 0xf5, 0xa0, 0xde, 0x6a, 0x57, + 0xa6, 0x37, 0xb3, 0x9b }, +}; + +static const size_t add_len[MAX_TESTS] = + { 0, 0, 0, 20, 20, 20 }; + +static const int add_index[MAX_TESTS] = + { 0, 0, 0, 1, 1, 1 }; + +static const unsigned char additional[MAX_TESTS][64] = +{ + { 0x00 }, + { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, + 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, + 0xab, 0xad, 0xda, 0xd2 }, +}; + +static const size_t pt_len[MAX_TESTS] = + { 0, 16, 64, 60, 60, 60 }; + +static const int pt_index[MAX_TESTS] = + { 0, 0, 1, 1, 1, 1 }; + +static const unsigned char pt[MAX_TESTS][64] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, + 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, + 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda, + 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72, + 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, + 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, + 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, + 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 }, +}; + +static const unsigned char ct[MAX_TESTS * 3][64] = +{ + { 0x00 }, + { 0x03, 0x88, 0xda, 0xce, 0x60, 0xb6, 0xa3, 0x92, + 0xf3, 0x28, 0xc2, 0xb9, 0x71, 0xb2, 0xfe, 0x78 }, + { 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24, + 0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c, + 0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0, + 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e, + 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c, + 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05, + 0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97, + 0x3d, 0x58, 0xe0, 0x91, 0x47, 0x3f, 0x59, 0x85 }, + { 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24, + 0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c, + 0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0, + 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e, + 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c, + 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05, + 0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97, + 0x3d, 0x58, 0xe0, 0x91 }, + { 0x61, 0x35, 0x3b, 0x4c, 0x28, 0x06, 0x93, 0x4a, + 0x77, 0x7f, 0xf5, 0x1f, 0xa2, 0x2a, 0x47, 0x55, + 0x69, 0x9b, 0x2a, 0x71, 0x4f, 0xcd, 0xc6, 0xf8, + 0x37, 0x66, 0xe5, 0xf9, 0x7b, 0x6c, 0x74, 0x23, + 0x73, 0x80, 0x69, 0x00, 0xe4, 0x9f, 0x24, 0xb2, + 0x2b, 0x09, 0x75, 0x44, 0xd4, 0x89, 0x6b, 0x42, + 0x49, 0x89, 0xb5, 0xe1, 0xeb, 0xac, 0x0f, 0x07, + 0xc2, 0x3f, 0x45, 0x98 }, + { 0x8c, 0xe2, 0x49, 0x98, 0x62, 0x56, 0x15, 0xb6, + 0x03, 0xa0, 0x33, 0xac, 0xa1, 0x3f, 0xb8, 0x94, + 0xbe, 0x91, 0x12, 0xa5, 0xc3, 0xa2, 0x11, 0xa8, + 0xba, 0x26, 0x2a, 0x3c, 0xca, 0x7e, 0x2c, 0xa7, + 0x01, 0xe4, 0xa9, 0xa4, 0xfb, 0xa4, 0x3c, 0x90, + 0xcc, 0xdc, 0xb2, 0x81, 0xd4, 0x8c, 0x7c, 0x6f, + 0xd6, 0x28, 0x75, 0xd2, 0xac, 0xa4, 0x17, 0x03, + 0x4c, 0x34, 0xae, 0xe5 }, + { 0x00 }, + { 0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41, + 0x1c, 0x26, 0x7e, 0x43, 0x84, 0xb0, 0xf6, 0x00 }, + { 0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41, + 0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57, + 0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84, + 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c, + 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25, + 0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47, + 0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9, + 0xcc, 0xda, 0x27, 0x10, 0xac, 0xad, 0xe2, 0x56 }, + { 0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41, + 0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57, + 0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84, + 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c, + 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25, + 0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47, + 0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9, + 0xcc, 0xda, 0x27, 0x10 }, + { 0x0f, 0x10, 0xf5, 0x99, 0xae, 0x14, 0xa1, 0x54, + 0xed, 0x24, 0xb3, 0x6e, 0x25, 0x32, 0x4d, 0xb8, + 0xc5, 0x66, 0x63, 0x2e, 0xf2, 0xbb, 0xb3, 0x4f, + 0x83, 0x47, 0x28, 0x0f, 0xc4, 0x50, 0x70, 0x57, + 0xfd, 0xdc, 0x29, 0xdf, 0x9a, 0x47, 0x1f, 0x75, + 0xc6, 0x65, 0x41, 0xd4, 0xd4, 0xda, 0xd1, 0xc9, + 0xe9, 0x3a, 0x19, 0xa5, 0x8e, 0x8b, 0x47, 0x3f, + 0xa0, 0xf0, 0x62, 0xf7 }, + { 0xd2, 0x7e, 0x88, 0x68, 0x1c, 0xe3, 0x24, 0x3c, + 0x48, 0x30, 0x16, 0x5a, 0x8f, 0xdc, 0xf9, 0xff, + 0x1d, 0xe9, 0xa1, 0xd8, 0xe6, 0xb4, 0x47, 0xef, + 0x6e, 0xf7, 0xb7, 0x98, 0x28, 0x66, 0x6e, 0x45, + 0x81, 0xe7, 0x90, 0x12, 0xaf, 0x34, 0xdd, 0xd9, + 0xe2, 0xf0, 0x37, 0x58, 0x9b, 0x29, 0x2d, 0xb3, + 0xe6, 0x7c, 0x03, 0x67, 0x45, 0xfa, 0x22, 0xe7, + 0xe9, 0xb7, 0x37, 0x3b }, + { 0x00 }, + { 0xce, 0xa7, 0x40, 0x3d, 0x4d, 0x60, 0x6b, 0x6e, + 0x07, 0x4e, 0xc5, 0xd3, 0xba, 0xf3, 0x9d, 0x18 }, + { 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, + 0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d, + 0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9, + 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa, + 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d, + 0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38, + 0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a, + 0xbc, 0xc9, 0xf6, 0x62, 0x89, 0x80, 0x15, 0xad }, + { 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, + 0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d, + 0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9, + 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa, + 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d, + 0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38, + 0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a, + 0xbc, 0xc9, 0xf6, 0x62 }, + { 0xc3, 0x76, 0x2d, 0xf1, 0xca, 0x78, 0x7d, 0x32, + 0xae, 0x47, 0xc1, 0x3b, 0xf1, 0x98, 0x44, 0xcb, + 0xaf, 0x1a, 0xe1, 0x4d, 0x0b, 0x97, 0x6a, 0xfa, + 0xc5, 0x2f, 0xf7, 0xd7, 0x9b, 0xba, 0x9d, 0xe0, + 0xfe, 0xb5, 0x82, 0xd3, 0x39, 0x34, 0xa4, 0xf0, + 0x95, 0x4c, 0xc2, 0x36, 0x3b, 0xc7, 0x3f, 0x78, + 0x62, 0xac, 0x43, 0x0e, 0x64, 0xab, 0xe4, 0x99, + 0xf4, 0x7c, 0x9b, 0x1f }, + { 0x5a, 0x8d, 0xef, 0x2f, 0x0c, 0x9e, 0x53, 0xf1, + 0xf7, 0x5d, 0x78, 0x53, 0x65, 0x9e, 0x2a, 0x20, + 0xee, 0xb2, 0xb2, 0x2a, 0xaf, 0xde, 0x64, 0x19, + 0xa0, 0x58, 0xab, 0x4f, 0x6f, 0x74, 0x6b, 0xf4, + 0x0f, 0xc0, 0xc3, 0xb7, 0x80, 0xf2, 0x44, 0x45, + 0x2d, 0xa3, 0xeb, 0xf1, 0xc5, 0xd8, 0x2c, 0xde, + 0xa2, 0x41, 0x89, 0x97, 0x20, 0x0e, 0xf8, 0x2e, + 0x44, 0xae, 0x7e, 0x3f }, +}; + +static const unsigned char tag[MAX_TESTS * 3][16] = +{ + { 0x58, 0xe2, 0xfc, 0xce, 0xfa, 0x7e, 0x30, 0x61, + 0x36, 0x7f, 0x1d, 0x57, 0xa4, 0xe7, 0x45, 0x5a }, + { 0xab, 0x6e, 0x47, 0xd4, 0x2c, 0xec, 0x13, 0xbd, + 0xf5, 0x3a, 0x67, 0xb2, 0x12, 0x57, 0xbd, 0xdf }, + { 0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6, + 0x2c, 0xf3, 0x5a, 0xbd, 0x2b, 0xa6, 0xfa, 0xb4 }, + { 0x5b, 0xc9, 0x4f, 0xbc, 0x32, 0x21, 0xa5, 0xdb, + 0x94, 0xfa, 0xe9, 0x5a, 0xe7, 0x12, 0x1a, 0x47 }, + { 0x36, 0x12, 0xd2, 0xe7, 0x9e, 0x3b, 0x07, 0x85, + 0x56, 0x1b, 0xe1, 0x4a, 0xac, 0xa2, 0xfc, 0xcb }, + { 0x61, 0x9c, 0xc5, 0xae, 0xff, 0xfe, 0x0b, 0xfa, + 0x46, 0x2a, 0xf4, 0x3c, 0x16, 0x99, 0xd0, 0x50 }, + { 0xcd, 0x33, 0xb2, 0x8a, 0xc7, 0x73, 0xf7, 0x4b, + 0xa0, 0x0e, 0xd1, 0xf3, 0x12, 0x57, 0x24, 0x35 }, + { 0x2f, 0xf5, 0x8d, 0x80, 0x03, 0x39, 0x27, 0xab, + 0x8e, 0xf4, 0xd4, 0x58, 0x75, 0x14, 0xf0, 0xfb }, + { 0x99, 0x24, 0xa7, 0xc8, 0x58, 0x73, 0x36, 0xbf, + 0xb1, 0x18, 0x02, 0x4d, 0xb8, 0x67, 0x4a, 0x14 }, + { 0x25, 0x19, 0x49, 0x8e, 0x80, 0xf1, 0x47, 0x8f, + 0x37, 0xba, 0x55, 0xbd, 0x6d, 0x27, 0x61, 0x8c }, + { 0x65, 0xdc, 0xc5, 0x7f, 0xcf, 0x62, 0x3a, 0x24, + 0x09, 0x4f, 0xcc, 0xa4, 0x0d, 0x35, 0x33, 0xf8 }, + { 0xdc, 0xf5, 0x66, 0xff, 0x29, 0x1c, 0x25, 0xbb, + 0xb8, 0x56, 0x8f, 0xc3, 0xd3, 0x76, 0xa6, 0xd9 }, + { 0x53, 0x0f, 0x8a, 0xfb, 0xc7, 0x45, 0x36, 0xb9, + 0xa9, 0x63, 0xb4, 0xf1, 0xc4, 0xcb, 0x73, 0x8b }, + { 0xd0, 0xd1, 0xc8, 0xa7, 0x99, 0x99, 0x6b, 0xf0, + 0x26, 0x5b, 0x98, 0xb5, 0xd4, 0x8a, 0xb9, 0x19 }, + { 0xb0, 0x94, 0xda, 0xc5, 0xd9, 0x34, 0x71, 0xbd, + 0xec, 0x1a, 0x50, 0x22, 0x70, 0xe3, 0xcc, 0x6c }, + { 0x76, 0xfc, 0x6e, 0xce, 0x0f, 0x4e, 0x17, 0x68, + 0xcd, 0xdf, 0x88, 0x53, 0xbb, 0x2d, 0x55, 0x1b }, + { 0x3a, 0x33, 0x7d, 0xbf, 0x46, 0xa7, 0x92, 0xc4, + 0x5e, 0x45, 0x49, 0x13, 0xfe, 0x2e, 0xa8, 0xf2 }, + { 0xa4, 0x4a, 0x82, 0x66, 0xee, 0x1c, 0x8e, 0xb0, + 0xc8, 0xb5, 0xd4, 0xcf, 0x5a, 0xe9, 0xf1, 0x9a }, +}; + +int mbedtls_gcm_self_test( int verbose ) +{ + mbedtls_gcm_context ctx; + unsigned char buf[64]; + unsigned char tag_buf[16]; + int i, j, ret; + mbedtls_cipher_id_t cipher = MBEDTLS_CIPHER_ID_AES; + + for( j = 0; j < 3; j++ ) + { + int key_len = 128 + 64 * j; + + for( i = 0; i < MAX_TESTS; i++ ) + { + mbedtls_gcm_init( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( " AES-GCM-%3d #%d (%s): ", + key_len, i, "enc" ); + + ret = mbedtls_gcm_setkey( &ctx, cipher, key[key_index[i]], + key_len ); + /* + * AES-192 is an optional feature that may be unavailable when + * there is an alternative underlying implementation i.e. when + * MBEDTLS_AES_ALT is defined. + */ + if( ret == MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED && key_len == 192 ) + { + mbedtls_printf( "skipped\n" ); + break; + } + else if( ret != 0 ) + { + goto exit; + } + + ret = mbedtls_gcm_crypt_and_tag( &ctx, MBEDTLS_GCM_ENCRYPT, + pt_len[i], + iv[iv_index[i]], iv_len[i], + additional[add_index[i]], add_len[i], + pt[pt_index[i]], buf, 16, tag_buf ); + if( ret != 0 ) + goto exit; + + if ( memcmp( buf, ct[j * 6 + i], pt_len[i] ) != 0 || + memcmp( tag_buf, tag[j * 6 + i], 16 ) != 0 ) + { + ret = 1; + goto exit; + } + + mbedtls_gcm_free( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + mbedtls_gcm_init( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( " AES-GCM-%3d #%d (%s): ", + key_len, i, "dec" ); + + ret = mbedtls_gcm_setkey( &ctx, cipher, key[key_index[i]], + key_len ); + if( ret != 0 ) + goto exit; + + ret = mbedtls_gcm_crypt_and_tag( &ctx, MBEDTLS_GCM_DECRYPT, + pt_len[i], + iv[iv_index[i]], iv_len[i], + additional[add_index[i]], add_len[i], + ct[j * 6 + i], buf, 16, tag_buf ); + + if( ret != 0 ) + goto exit; + + if( memcmp( buf, pt[pt_index[i]], pt_len[i] ) != 0 || + memcmp( tag_buf, tag[j * 6 + i], 16 ) != 0 ) + { + ret = 1; + goto exit; + } + + mbedtls_gcm_free( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + mbedtls_gcm_init( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( " AES-GCM-%3d #%d split (%s): ", + key_len, i, "enc" ); + + ret = mbedtls_gcm_setkey( &ctx, cipher, key[key_index[i]], + key_len ); + if( ret != 0 ) + goto exit; + + ret = mbedtls_gcm_starts( &ctx, MBEDTLS_GCM_ENCRYPT, + iv[iv_index[i]], iv_len[i], + additional[add_index[i]], add_len[i] ); + if( ret != 0 ) + goto exit; + + if( pt_len[i] > 32 ) + { + size_t rest_len = pt_len[i] - 32; + ret = mbedtls_gcm_update( &ctx, 32, pt[pt_index[i]], buf ); + if( ret != 0 ) + goto exit; + + ret = mbedtls_gcm_update( &ctx, rest_len, pt[pt_index[i]] + 32, + buf + 32 ); + if( ret != 0 ) + goto exit; + } + else + { + ret = mbedtls_gcm_update( &ctx, pt_len[i], pt[pt_index[i]], buf ); + if( ret != 0 ) + goto exit; + } + + ret = mbedtls_gcm_finish( &ctx, tag_buf, 16 ); + if( ret != 0 ) + goto exit; + + if( memcmp( buf, ct[j * 6 + i], pt_len[i] ) != 0 || + memcmp( tag_buf, tag[j * 6 + i], 16 ) != 0 ) + { + ret = 1; + goto exit; + } + + mbedtls_gcm_free( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + mbedtls_gcm_init( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( " AES-GCM-%3d #%d split (%s): ", + key_len, i, "dec" ); + + ret = mbedtls_gcm_setkey( &ctx, cipher, key[key_index[i]], + key_len ); + if( ret != 0 ) + goto exit; + + ret = mbedtls_gcm_starts( &ctx, MBEDTLS_GCM_DECRYPT, + iv[iv_index[i]], iv_len[i], + additional[add_index[i]], add_len[i] ); + if( ret != 0 ) + goto exit; + + if( pt_len[i] > 32 ) + { + size_t rest_len = pt_len[i] - 32; + ret = mbedtls_gcm_update( &ctx, 32, ct[j * 6 + i], buf ); + if( ret != 0 ) + goto exit; + + ret = mbedtls_gcm_update( &ctx, rest_len, ct[j * 6 + i] + 32, + buf + 32 ); + if( ret != 0 ) + goto exit; + } + else + { + ret = mbedtls_gcm_update( &ctx, pt_len[i], ct[j * 6 + i], + buf ); + if( ret != 0 ) + goto exit; + } + + ret = mbedtls_gcm_finish( &ctx, tag_buf, 16 ); + if( ret != 0 ) + goto exit; + + if( memcmp( buf, pt[pt_index[i]], pt_len[i] ) != 0 || + memcmp( tag_buf, tag[j * 6 + i], 16 ) != 0 ) + { + ret = 1; + goto exit; + } + + mbedtls_gcm_free( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + ret = 0; + +exit: + if( ret != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + mbedtls_gcm_free( &ctx ); + } + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ + +#endif /* MBEDTLS_GCM_C */ diff --git a/src/common/mbedtls/library/mbedtls_hkdf.c b/src/common/mbedtls/library/mbedtls_hkdf.c new file mode 100644 index 0000000000..99b1d5043b --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_hkdf.c @@ -0,0 +1,205 @@ +/* + * HKDF implementation -- RFC 5869 + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_HKDF_C) + +#ifndef NVRM +#include +#endif +#include "mbedtls/hkdf.h" +#include "mbedtls/platform_util.h" + +int mbedtls_hkdf( const mbedtls_md_info_t *md, const unsigned char *salt, + size_t salt_len, const unsigned char *ikm, size_t ikm_len, + const unsigned char *info, size_t info_len, + unsigned char *okm, size_t okm_len ) +{ + int ret; + unsigned char prk[MBEDTLS_MD_MAX_SIZE]; + + ret = mbedtls_hkdf_extract( md, salt, salt_len, ikm, ikm_len, prk ); + + if( ret == 0 ) + { + ret = mbedtls_hkdf_expand( md, prk, mbedtls_md_get_size( md ), + info, info_len, okm, okm_len ); + } + + mbedtls_platform_zeroize( prk, sizeof( prk ) ); + + return( ret ); +} + +int mbedtls_hkdf_extract( const mbedtls_md_info_t *md, + const unsigned char *salt, size_t salt_len, + const unsigned char *ikm, size_t ikm_len, + unsigned char *prk ) +{ + unsigned char null_salt[MBEDTLS_MD_MAX_SIZE] = { '\0' }; + + if( salt == NULL ) + { + size_t hash_len; + + if( salt_len != 0 ) + { + return MBEDTLS_ERR_HKDF_BAD_INPUT_DATA; + } + + hash_len = mbedtls_md_get_size( md ); + + if( hash_len == 0 ) + { + return MBEDTLS_ERR_HKDF_BAD_INPUT_DATA; + } + + salt = null_salt; + salt_len = hash_len; + } + + return( mbedtls_md_hmac( md, salt, salt_len, ikm, ikm_len, prk ) ); +} + +int mbedtls_hkdf_expand( const mbedtls_md_info_t *md, const unsigned char *prk, + size_t prk_len, const unsigned char *info, + size_t info_len, unsigned char *okm, size_t okm_len ) +{ + size_t hash_len; + size_t where = 0; + size_t n; + size_t t_len = 0; + size_t i; + int ret = 0; + mbedtls_md_context_t ctx; + unsigned char t[MBEDTLS_MD_MAX_SIZE]; + + if( okm == NULL ) + { + return( MBEDTLS_ERR_HKDF_BAD_INPUT_DATA ); + } + + hash_len = mbedtls_md_get_size( md ); + + if( prk_len < hash_len || hash_len == 0 ) + { + return( MBEDTLS_ERR_HKDF_BAD_INPUT_DATA ); + } + + if( info == NULL ) + { + info = (const unsigned char *) ""; + info_len = 0; + } + + n = okm_len / hash_len; + + if( (okm_len % hash_len) != 0 ) + { + n++; + } + + /* + * Per RFC 5869 Section 2.3, okm_len must not exceed + * 255 times the hash length + */ + if( n > 255 ) + { + return( MBEDTLS_ERR_HKDF_BAD_INPUT_DATA ); + } + + mbedtls_md_init( &ctx ); + + if( (ret = mbedtls_md_setup( &ctx, md, 1) ) != 0 ) + { + goto exit; + } + + /* + * Compute T = T(1) | T(2) | T(3) | ... | T(N) + * Where T(N) is defined in RFC 5869 Section 2.3 + */ + for( i = 1; i <= n; i++ ) + { + size_t num_to_copy; + unsigned char c = i & 0xff; + + ret = mbedtls_md_hmac_starts( &ctx, prk, prk_len ); + if( ret != 0 ) + { + goto exit; + } + + ret = mbedtls_md_hmac_update( &ctx, t, t_len ); + if( ret != 0 ) + { + goto exit; + } + + ret = mbedtls_md_hmac_update( &ctx, info, info_len ); + if( ret != 0 ) + { + goto exit; + } + + /* The constant concatenated to the end of each T(n) is a single octet. + * */ + ret = mbedtls_md_hmac_update( &ctx, &c, 1 ); + if( ret != 0 ) + { + goto exit; + } + + ret = mbedtls_md_hmac_finish( &ctx, t ); + if( ret != 0 ) + { + goto exit; + } + + num_to_copy = i != n ? hash_len : okm_len - where; + memcpy( okm + where, t, num_to_copy ); + where += hash_len; + t_len = hash_len; + } + +exit: + mbedtls_md_free( &ctx ); + mbedtls_platform_zeroize( t, sizeof( t ) ); + + return( ret ); +} + +#endif /* MBEDTLS_HKDF_C */ diff --git a/src/common/mbedtls/library/mbedtls_md.c b/src/common/mbedtls/library/mbedtls_md.c new file mode 100644 index 0000000000..6824f36fb8 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_md.c @@ -0,0 +1,488 @@ +/** + * \file mbedtls_md.c + * + * \brief Generic message digest wrapper for mbed TLS + * + * \author Adriaan de Jong + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_MD_C) + +#include "mbedtls/md.h" +#include "mbedtls/md_internal.h" +#include "mbedtls/platform_util.h" + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_FS_IO) +#include +#endif + +/* + * Reminder: update profiles in x509_crt.c when adding a new hash! + */ +static const int supported_digests[] = { + +#if defined(MBEDTLS_SHA512_C) + MBEDTLS_MD_SHA512, + MBEDTLS_MD_SHA384, +#endif + +#if defined(MBEDTLS_SHA256_C) + MBEDTLS_MD_SHA256, + MBEDTLS_MD_SHA224, +#endif + +#if defined(MBEDTLS_SHA1_C) + MBEDTLS_MD_SHA1, +#endif + +#if defined(MBEDTLS_RIPEMD160_C) + MBEDTLS_MD_RIPEMD160, +#endif + +#if defined(MBEDTLS_MD5_C) + MBEDTLS_MD_MD5, +#endif + +#if defined(MBEDTLS_MD4_C) + MBEDTLS_MD_MD4, +#endif + +#if defined(MBEDTLS_MD2_C) + MBEDTLS_MD_MD2, +#endif + + MBEDTLS_MD_NONE +}; + +const int *mbedtls_md_list( void ) +{ + return( supported_digests ); +} + +const mbedtls_md_info_t *mbedtls_md_info_from_string( const char *md_name ) +{ + if( NULL == md_name ) + return( NULL ); + + /* Get the appropriate digest information */ +#if defined(MBEDTLS_MD2_C) + if( !strcmp( "MD2", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_MD2 ); +#endif +#if defined(MBEDTLS_MD4_C) + if( !strcmp( "MD4", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_MD4 ); +#endif +#if defined(MBEDTLS_MD5_C) + if( !strcmp( "MD5", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_MD5 ); +#endif +#if defined(MBEDTLS_RIPEMD160_C) + if( !strcmp( "RIPEMD160", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_RIPEMD160 ); +#endif +#if defined(MBEDTLS_SHA1_C) + if( !strcmp( "SHA1", md_name ) || !strcmp( "SHA", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_SHA1 ); +#endif +#if defined(MBEDTLS_SHA256_C) + if( !strcmp( "SHA224", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_SHA224 ); + if( !strcmp( "SHA256", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_SHA256 ); +#endif +#if defined(MBEDTLS_SHA512_C) + if( !strcmp( "SHA384", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_SHA384 ); + if( !strcmp( "SHA512", md_name ) ) + return mbedtls_md_info_from_type( MBEDTLS_MD_SHA512 ); +#endif + return( NULL ); +} + +const mbedtls_md_info_t *mbedtls_md_info_from_type( mbedtls_md_type_t md_type ) +{ + switch( md_type ) + { +#if defined(MBEDTLS_MD2_C) + case MBEDTLS_MD_MD2: + return( &mbedtls_md2_info ); +#endif +#if defined(MBEDTLS_MD4_C) + case MBEDTLS_MD_MD4: + return( &mbedtls_md4_info ); +#endif +#if defined(MBEDTLS_MD5_C) + case MBEDTLS_MD_MD5: + return( &mbedtls_md5_info ); +#endif +#if defined(MBEDTLS_RIPEMD160_C) + case MBEDTLS_MD_RIPEMD160: + return( &mbedtls_ripemd160_info ); +#endif +#if defined(MBEDTLS_SHA1_C) + case MBEDTLS_MD_SHA1: + return( &mbedtls_sha1_info ); +#endif +#if defined(MBEDTLS_SHA256_C) + case MBEDTLS_MD_SHA224: + return( &mbedtls_sha224_info ); + case MBEDTLS_MD_SHA256: + return( &mbedtls_sha256_info ); +#endif +#if defined(MBEDTLS_SHA512_C) + case MBEDTLS_MD_SHA384: + return( &mbedtls_sha384_info ); + case MBEDTLS_MD_SHA512: + return( &mbedtls_sha512_info ); +#endif + default: + return( NULL ); + } +} + +void mbedtls_md_init( mbedtls_md_context_t *ctx ) +{ + memset( ctx, 0, sizeof( mbedtls_md_context_t ) ); +} + +void mbedtls_md_free( mbedtls_md_context_t *ctx ) +{ + if( ctx == NULL || ctx->md_info == NULL ) + return; + + if( ctx->md_ctx != NULL ) + ctx->md_info->ctx_free_func( ctx->md_ctx ); + + if( ctx->hmac_ctx != NULL ) + { + mbedtls_platform_zeroize( ctx->hmac_ctx, + 2 * ctx->md_info->block_size ); + mbedtls_free( ctx->hmac_ctx ); + } + + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_md_context_t ) ); +} + +int mbedtls_md_clone( mbedtls_md_context_t *dst, + const mbedtls_md_context_t *src ) +{ + if( dst == NULL || dst->md_info == NULL || + src == NULL || src->md_info == NULL || + dst->md_info != src->md_info ) + { + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + } + + dst->md_info->clone_func( dst->md_ctx, src->md_ctx ); + + return( 0 ); +} + +#if ! defined(MBEDTLS_DEPRECATED_REMOVED) +int mbedtls_md_init_ctx( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info ) +{ + return mbedtls_md_setup( ctx, md_info, 1 ); +} +#endif + +int mbedtls_md_setup( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info, int hmac ) +{ + if( md_info == NULL || ctx == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + if( ( ctx->md_ctx = md_info->ctx_alloc_func() ) == NULL ) + return( MBEDTLS_ERR_MD_ALLOC_FAILED ); + + if( hmac != 0 ) + { + ctx->hmac_ctx = mbedtls_calloc( 2, md_info->block_size ); + if( ctx->hmac_ctx == NULL ) + { + md_info->ctx_free_func( ctx->md_ctx ); + return( MBEDTLS_ERR_MD_ALLOC_FAILED ); + } + } + + ctx->md_info = md_info; + + return( 0 ); +} + +int mbedtls_md_starts( mbedtls_md_context_t *ctx ) +{ + if( ctx == NULL || ctx->md_info == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + return( ctx->md_info->starts_func( ctx->md_ctx ) ); +} + +int mbedtls_md_update( mbedtls_md_context_t *ctx, const unsigned char *input, size_t ilen ) +{ + if( ctx == NULL || ctx->md_info == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + return( ctx->md_info->update_func( ctx->md_ctx, input, ilen ) ); +} + +int mbedtls_md_finish( mbedtls_md_context_t *ctx, unsigned char *output ) +{ + if( ctx == NULL || ctx->md_info == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + return( ctx->md_info->finish_func( ctx->md_ctx, output ) ); +} + +int mbedtls_md( const mbedtls_md_info_t *md_info, const unsigned char *input, size_t ilen, + unsigned char *output ) +{ + if( md_info == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + return( md_info->digest_func( input, ilen, output ) ); +} + +#if defined(MBEDTLS_FS_IO) +int mbedtls_md_file( const mbedtls_md_info_t *md_info, const char *path, unsigned char *output ) +{ + int ret; + FILE *f; + size_t n; + mbedtls_md_context_t ctx; + unsigned char buf[1024]; + + if( md_info == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + if( ( f = fopen( path, "rb" ) ) == NULL ) + return( MBEDTLS_ERR_MD_FILE_IO_ERROR ); + + mbedtls_md_init( &ctx ); + + if( ( ret = mbedtls_md_setup( &ctx, md_info, 0 ) ) != 0 ) + goto cleanup; + + if( ( ret = md_info->starts_func( ctx.md_ctx ) ) != 0 ) + goto cleanup; + + while( ( n = fread( buf, 1, sizeof( buf ), f ) ) > 0 ) + if( ( ret = md_info->update_func( ctx.md_ctx, buf, n ) ) != 0 ) + goto cleanup; + + if( ferror( f ) != 0 ) + ret = MBEDTLS_ERR_MD_FILE_IO_ERROR; + else + ret = md_info->finish_func( ctx.md_ctx, output ); + +cleanup: + mbedtls_platform_zeroize( buf, sizeof( buf ) ); + fclose( f ); + mbedtls_md_free( &ctx ); + + return( ret ); +} +#endif /* MBEDTLS_FS_IO */ + +int mbedtls_md_hmac_starts( mbedtls_md_context_t *ctx, const unsigned char *key, size_t keylen ) +{ + int ret; + unsigned char sum[MBEDTLS_MD_MAX_SIZE]; + unsigned char *ipad, *opad; + size_t i; + + if( ctx == NULL || ctx->md_info == NULL || ctx->hmac_ctx == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + if( keylen > (size_t) ctx->md_info->block_size ) + { + if( ( ret = ctx->md_info->starts_func( ctx->md_ctx ) ) != 0 ) + goto cleanup; + if( ( ret = ctx->md_info->update_func( ctx->md_ctx, key, keylen ) ) != 0 ) + goto cleanup; + if( ( ret = ctx->md_info->finish_func( ctx->md_ctx, sum ) ) != 0 ) + goto cleanup; + + keylen = ctx->md_info->size; + key = sum; + } + + ipad = (unsigned char *) ctx->hmac_ctx; + opad = (unsigned char *) ctx->hmac_ctx + ctx->md_info->block_size; + + memset( ipad, 0x36, ctx->md_info->block_size ); + memset( opad, 0x5C, ctx->md_info->block_size ); + + for( i = 0; i < keylen; i++ ) + { + ipad[i] = (unsigned char)( ipad[i] ^ key[i] ); + opad[i] = (unsigned char)( opad[i] ^ key[i] ); + } + + if( ( ret = ctx->md_info->starts_func( ctx->md_ctx ) ) != 0 ) + goto cleanup; + if( ( ret = ctx->md_info->update_func( ctx->md_ctx, ipad, + ctx->md_info->block_size ) ) != 0 ) + goto cleanup; + +cleanup: + mbedtls_platform_zeroize( sum, sizeof( sum ) ); + + return( ret ); +} + +int mbedtls_md_hmac_update( mbedtls_md_context_t *ctx, const unsigned char *input, size_t ilen ) +{ + if( ctx == NULL || ctx->md_info == NULL || ctx->hmac_ctx == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + return( ctx->md_info->update_func( ctx->md_ctx, input, ilen ) ); +} + +int mbedtls_md_hmac_finish( mbedtls_md_context_t *ctx, unsigned char *output ) +{ + int ret; + unsigned char tmp[MBEDTLS_MD_MAX_SIZE]; + unsigned char *opad; + + if( ctx == NULL || ctx->md_info == NULL || ctx->hmac_ctx == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + opad = (unsigned char *) ctx->hmac_ctx + ctx->md_info->block_size; + + if( ( ret = ctx->md_info->finish_func( ctx->md_ctx, tmp ) ) != 0 ) + return( ret ); + if( ( ret = ctx->md_info->starts_func( ctx->md_ctx ) ) != 0 ) + return( ret ); + if( ( ret = ctx->md_info->update_func( ctx->md_ctx, opad, + ctx->md_info->block_size ) ) != 0 ) + return( ret ); + if( ( ret = ctx->md_info->update_func( ctx->md_ctx, tmp, + ctx->md_info->size ) ) != 0 ) + return( ret ); + return( ctx->md_info->finish_func( ctx->md_ctx, output ) ); +} + +int mbedtls_md_hmac_reset( mbedtls_md_context_t *ctx ) +{ + int ret; + unsigned char *ipad; + + if( ctx == NULL || ctx->md_info == NULL || ctx->hmac_ctx == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + ipad = (unsigned char *) ctx->hmac_ctx; + + if( ( ret = ctx->md_info->starts_func( ctx->md_ctx ) ) != 0 ) + return( ret ); + return( ctx->md_info->update_func( ctx->md_ctx, ipad, + ctx->md_info->block_size ) ); +} + +int mbedtls_md_hmac( const mbedtls_md_info_t *md_info, + const unsigned char *key, size_t keylen, + const unsigned char *input, size_t ilen, + unsigned char *output ) +{ + mbedtls_md_context_t ctx; + int ret; + + if( md_info == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + mbedtls_md_init( &ctx ); + + if( ( ret = mbedtls_md_setup( &ctx, md_info, 1 ) ) != 0 ) + goto cleanup; + + if( ( ret = mbedtls_md_hmac_starts( &ctx, key, keylen ) ) != 0 ) + goto cleanup; + if( ( ret = mbedtls_md_hmac_update( &ctx, input, ilen ) ) != 0 ) + goto cleanup; + if( ( ret = mbedtls_md_hmac_finish( &ctx, output ) ) != 0 ) + goto cleanup; + +cleanup: + mbedtls_md_free( &ctx ); + + return( ret ); +} + +int mbedtls_md_process( mbedtls_md_context_t *ctx, const unsigned char *data ) +{ + if( ctx == NULL || ctx->md_info == NULL ) + return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); + + return( ctx->md_info->process_func( ctx->md_ctx, data ) ); +} + +unsigned char mbedtls_md_get_size( const mbedtls_md_info_t *md_info ) +{ + if( md_info == NULL ) + return( 0 ); + + return md_info->size; +} + +mbedtls_md_type_t mbedtls_md_get_type( const mbedtls_md_info_t *md_info ) +{ + if( md_info == NULL ) + return( MBEDTLS_MD_NONE ); + + return md_info->type; +} + +const char *mbedtls_md_get_name( const mbedtls_md_info_t *md_info ) +{ + if( md_info == NULL ) + return( NULL ); + + return md_info->name; +} + +#endif /* MBEDTLS_MD_C */ diff --git a/src/common/mbedtls/library/mbedtls_md_wrap.c b/src/common/mbedtls/library/mbedtls_md_wrap.c new file mode 100644 index 0000000000..72d97c5d4b --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_md_wrap.c @@ -0,0 +1,597 @@ +/** + * \file md_wrap.c + * + * \brief Generic message digest wrapper for mbed TLS + * + * \author Adriaan de Jong + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_MD_C) + +#include "mbedtls/md_internal.h" + +#if defined(MBEDTLS_MD2_C) +#include "mbedtls/md2.h" +#endif + +#if defined(MBEDTLS_MD4_C) +#include "mbedtls/md4.h" +#endif + +#if defined(MBEDTLS_MD5_C) +#include "mbedtls/md5.h" +#endif + +#if defined(MBEDTLS_RIPEMD160_C) +#include "mbedtls/ripemd160.h" +#endif + +#if defined(MBEDTLS_SHA1_C) +#include "mbedtls/sha1.h" +#endif + +#if defined(MBEDTLS_SHA256_C) +#include "mbedtls/sha256.h" +#endif + +#if defined(MBEDTLS_SHA512_C) +#include "mbedtls/sha512.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#if defined(MBEDTLS_MD2_C) + +static int md2_starts_wrap( void *ctx ) +{ + return( mbedtls_md2_starts_ret( (mbedtls_md2_context *) ctx ) ); +} + +static int md2_update_wrap( void *ctx, const unsigned char *input, + size_t ilen ) +{ + return( mbedtls_md2_update_ret( (mbedtls_md2_context *) ctx, input, ilen ) ); +} + +static int md2_finish_wrap( void *ctx, unsigned char *output ) +{ + return( mbedtls_md2_finish_ret( (mbedtls_md2_context *) ctx, output ) ); +} + +static void *md2_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_md2_context ) ); + + if( ctx != NULL ) + mbedtls_md2_init( (mbedtls_md2_context *) ctx ); + + return( ctx ); +} + +static void md2_ctx_free( void *ctx ) +{ + mbedtls_md2_free( (mbedtls_md2_context *) ctx ); + mbedtls_free( ctx ); +} + +static void md2_clone_wrap( void *dst, const void *src ) +{ + mbedtls_md2_clone( (mbedtls_md2_context *) dst, + (const mbedtls_md2_context *) src ); +} + +static int md2_process_wrap( void *ctx, const unsigned char *data ) +{ + ((void) data); + + return( mbedtls_internal_md2_process( (mbedtls_md2_context *) ctx ) ); +} + +const mbedtls_md_info_t mbedtls_md2_info = { + MBEDTLS_MD_MD2, + "MD2", + 16, + 16, + md2_starts_wrap, + md2_update_wrap, + md2_finish_wrap, + mbedtls_md2_ret, + md2_ctx_alloc, + md2_ctx_free, + md2_clone_wrap, + md2_process_wrap, +}; + +#endif /* MBEDTLS_MD2_C */ + +#if defined(MBEDTLS_MD4_C) + +static int md4_starts_wrap( void *ctx ) +{ + return( mbedtls_md4_starts_ret( (mbedtls_md4_context *) ctx ) ); +} + +static int md4_update_wrap( void *ctx, const unsigned char *input, + size_t ilen ) +{ + return( mbedtls_md4_update_ret( (mbedtls_md4_context *) ctx, input, ilen ) ); +} + +static int md4_finish_wrap( void *ctx, unsigned char *output ) +{ + return( mbedtls_md4_finish_ret( (mbedtls_md4_context *) ctx, output ) ); +} + +static void *md4_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_md4_context ) ); + + if( ctx != NULL ) + mbedtls_md4_init( (mbedtls_md4_context *) ctx ); + + return( ctx ); +} + +static void md4_ctx_free( void *ctx ) +{ + mbedtls_md4_free( (mbedtls_md4_context *) ctx ); + mbedtls_free( ctx ); +} + +static void md4_clone_wrap( void *dst, const void *src ) +{ + mbedtls_md4_clone( (mbedtls_md4_context *) dst, + (const mbedtls_md4_context *) src ); +} + +static int md4_process_wrap( void *ctx, const unsigned char *data ) +{ + return( mbedtls_internal_md4_process( (mbedtls_md4_context *) ctx, data ) ); +} + +const mbedtls_md_info_t mbedtls_md4_info = { + MBEDTLS_MD_MD4, + "MD4", + 16, + 64, + md4_starts_wrap, + md4_update_wrap, + md4_finish_wrap, + mbedtls_md4_ret, + md4_ctx_alloc, + md4_ctx_free, + md4_clone_wrap, + md4_process_wrap, +}; + +#endif /* MBEDTLS_MD4_C */ + +#if defined(MBEDTLS_MD5_C) + +static int md5_starts_wrap( void *ctx ) +{ + return( mbedtls_md5_starts_ret( (mbedtls_md5_context *) ctx ) ); +} + +static int md5_update_wrap( void *ctx, const unsigned char *input, + size_t ilen ) +{ + return( mbedtls_md5_update_ret( (mbedtls_md5_context *) ctx, input, ilen ) ); +} + +static int md5_finish_wrap( void *ctx, unsigned char *output ) +{ + return( mbedtls_md5_finish_ret( (mbedtls_md5_context *) ctx, output ) ); +} + +static void *md5_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_md5_context ) ); + + if( ctx != NULL ) + mbedtls_md5_init( (mbedtls_md5_context *) ctx ); + + return( ctx ); +} + +static void md5_ctx_free( void *ctx ) +{ + mbedtls_md5_free( (mbedtls_md5_context *) ctx ); + mbedtls_free( ctx ); +} + +static void md5_clone_wrap( void *dst, const void *src ) +{ + mbedtls_md5_clone( (mbedtls_md5_context *) dst, + (const mbedtls_md5_context *) src ); +} + +static int md5_process_wrap( void *ctx, const unsigned char *data ) +{ + return( mbedtls_internal_md5_process( (mbedtls_md5_context *) ctx, data ) ); +} + +const mbedtls_md_info_t mbedtls_md5_info = { + MBEDTLS_MD_MD5, + "MD5", + 16, + 64, + md5_starts_wrap, + md5_update_wrap, + md5_finish_wrap, + mbedtls_md5_ret, + md5_ctx_alloc, + md5_ctx_free, + md5_clone_wrap, + md5_process_wrap, +}; + +#endif /* MBEDTLS_MD5_C */ + +#if defined(MBEDTLS_RIPEMD160_C) + +static int ripemd160_starts_wrap( void *ctx ) +{ + return( mbedtls_ripemd160_starts_ret( (mbedtls_ripemd160_context *) ctx ) ); +} + +static int ripemd160_update_wrap( void *ctx, const unsigned char *input, + size_t ilen ) +{ + return( mbedtls_ripemd160_update_ret( (mbedtls_ripemd160_context *) ctx, + input, ilen ) ); +} + +static int ripemd160_finish_wrap( void *ctx, unsigned char *output ) +{ + return( mbedtls_ripemd160_finish_ret( (mbedtls_ripemd160_context *) ctx, + output ) ); +} + +static void *ripemd160_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_ripemd160_context ) ); + + if( ctx != NULL ) + mbedtls_ripemd160_init( (mbedtls_ripemd160_context *) ctx ); + + return( ctx ); +} + +static void ripemd160_ctx_free( void *ctx ) +{ + mbedtls_ripemd160_free( (mbedtls_ripemd160_context *) ctx ); + mbedtls_free( ctx ); +} + +static void ripemd160_clone_wrap( void *dst, const void *src ) +{ + mbedtls_ripemd160_clone( (mbedtls_ripemd160_context *) dst, + (const mbedtls_ripemd160_context *) src ); +} + +static int ripemd160_process_wrap( void *ctx, const unsigned char *data ) +{ + return( mbedtls_internal_ripemd160_process( + (mbedtls_ripemd160_context *) ctx, data ) ); +} + +const mbedtls_md_info_t mbedtls_ripemd160_info = { + MBEDTLS_MD_RIPEMD160, + "RIPEMD160", + 20, + 64, + ripemd160_starts_wrap, + ripemd160_update_wrap, + ripemd160_finish_wrap, + mbedtls_ripemd160_ret, + ripemd160_ctx_alloc, + ripemd160_ctx_free, + ripemd160_clone_wrap, + ripemd160_process_wrap, +}; + +#endif /* MBEDTLS_RIPEMD160_C */ + +#if defined(MBEDTLS_SHA1_C) + +static int sha1_starts_wrap( void *ctx ) +{ + return( mbedtls_sha1_starts_ret( (mbedtls_sha1_context *) ctx ) ); +} + +static int sha1_update_wrap( void *ctx, const unsigned char *input, + size_t ilen ) +{ + return( mbedtls_sha1_update_ret( (mbedtls_sha1_context *) ctx, + input, ilen ) ); +} + +static int sha1_finish_wrap( void *ctx, unsigned char *output ) +{ + return( mbedtls_sha1_finish_ret( (mbedtls_sha1_context *) ctx, output ) ); +} + +static void *sha1_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_sha1_context ) ); + + if( ctx != NULL ) + mbedtls_sha1_init( (mbedtls_sha1_context *) ctx ); + + return( ctx ); +} + +static void sha1_clone_wrap( void *dst, const void *src ) +{ + mbedtls_sha1_clone( (mbedtls_sha1_context *) dst, + (const mbedtls_sha1_context *) src ); +} + +static void sha1_ctx_free( void *ctx ) +{ + mbedtls_sha1_free( (mbedtls_sha1_context *) ctx ); + mbedtls_free( ctx ); +} + +static int sha1_process_wrap( void *ctx, const unsigned char *data ) +{ + return( mbedtls_internal_sha1_process( (mbedtls_sha1_context *) ctx, + data ) ); +} + +const mbedtls_md_info_t mbedtls_sha1_info = { + MBEDTLS_MD_SHA1, + "SHA1", + 20, + 64, + sha1_starts_wrap, + sha1_update_wrap, + sha1_finish_wrap, + mbedtls_sha1_ret, + sha1_ctx_alloc, + sha1_ctx_free, + sha1_clone_wrap, + sha1_process_wrap, +}; + +#endif /* MBEDTLS_SHA1_C */ + +/* + * Wrappers for generic message digests + */ +#if defined(MBEDTLS_SHA256_C) + +static int sha224_starts_wrap( void *ctx ) +{ + return( mbedtls_sha256_starts_ret( (mbedtls_sha256_context *) ctx, 1 ) ); +} + +static int sha224_update_wrap( void *ctx, const unsigned char *input, + size_t ilen ) +{ + return( mbedtls_sha256_update_ret( (mbedtls_sha256_context *) ctx, + input, ilen ) ); +} + +static int sha224_finish_wrap( void *ctx, unsigned char *output ) +{ + return( mbedtls_sha256_finish_ret( (mbedtls_sha256_context *) ctx, + output ) ); +} + +static int sha224_wrap( const unsigned char *input, size_t ilen, + unsigned char *output ) +{ + return( mbedtls_sha256_ret( input, ilen, output, 1 ) ); +} + +static void *sha224_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_sha256_context ) ); + + if( ctx != NULL ) + mbedtls_sha256_init( (mbedtls_sha256_context *) ctx ); + + return( ctx ); +} + +static void sha224_ctx_free( void *ctx ) +{ + mbedtls_sha256_free( (mbedtls_sha256_context *) ctx ); + mbedtls_free( ctx ); +} + +static void sha224_clone_wrap( void *dst, const void *src ) +{ + mbedtls_sha256_clone( (mbedtls_sha256_context *) dst, + (const mbedtls_sha256_context *) src ); +} + +static int sha224_process_wrap( void *ctx, const unsigned char *data ) +{ + return( mbedtls_internal_sha256_process( (mbedtls_sha256_context *) ctx, + data ) ); +} + +const mbedtls_md_info_t mbedtls_sha224_info = { + MBEDTLS_MD_SHA224, + "SHA224", + 28, + 64, + sha224_starts_wrap, + sha224_update_wrap, + sha224_finish_wrap, + sha224_wrap, + sha224_ctx_alloc, + sha224_ctx_free, + sha224_clone_wrap, + sha224_process_wrap, +}; + +static int sha256_starts_wrap( void *ctx ) +{ + return( mbedtls_sha256_starts_ret( (mbedtls_sha256_context *) ctx, 0 ) ); +} + +static int sha256_wrap( const unsigned char *input, size_t ilen, + unsigned char *output ) +{ + return( mbedtls_sha256_ret( input, ilen, output, 0 ) ); +} + +const mbedtls_md_info_t mbedtls_sha256_info = { + MBEDTLS_MD_SHA256, + "SHA256", + 32, + 64, + sha256_starts_wrap, + sha224_update_wrap, + sha224_finish_wrap, + sha256_wrap, + sha224_ctx_alloc, + sha224_ctx_free, + sha224_clone_wrap, + sha224_process_wrap, +}; + +#endif /* MBEDTLS_SHA256_C */ + +#if defined(MBEDTLS_SHA512_C) + +static int sha384_starts_wrap( void *ctx ) +{ + return( mbedtls_sha512_starts_ret( (mbedtls_sha512_context *) ctx, 1 ) ); +} + +static int sha384_update_wrap( void *ctx, const unsigned char *input, + size_t ilen ) +{ + return( mbedtls_sha512_update_ret( (mbedtls_sha512_context *) ctx, + input, ilen ) ); +} + +static int sha384_finish_wrap( void *ctx, unsigned char *output ) +{ + return( mbedtls_sha512_finish_ret( (mbedtls_sha512_context *) ctx, + output ) ); +} + +static int sha384_wrap( const unsigned char *input, size_t ilen, + unsigned char *output ) +{ + return( mbedtls_sha512_ret( input, ilen, output, 1 ) ); +} + +static void *sha384_ctx_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_sha512_context ) ); + + if( ctx != NULL ) + mbedtls_sha512_init( (mbedtls_sha512_context *) ctx ); + + return( ctx ); +} + +static void sha384_ctx_free( void *ctx ) +{ + mbedtls_sha512_free( (mbedtls_sha512_context *) ctx ); + mbedtls_free( ctx ); +} + +static void sha384_clone_wrap( void *dst, const void *src ) +{ + mbedtls_sha512_clone( (mbedtls_sha512_context *) dst, + (const mbedtls_sha512_context *) src ); +} + +static int sha384_process_wrap( void *ctx, const unsigned char *data ) +{ + return( mbedtls_internal_sha512_process( (mbedtls_sha512_context *) ctx, + data ) ); +} + +const mbedtls_md_info_t mbedtls_sha384_info = { + MBEDTLS_MD_SHA384, + "SHA384", + 48, + 128, + sha384_starts_wrap, + sha384_update_wrap, + sha384_finish_wrap, + sha384_wrap, + sha384_ctx_alloc, + sha384_ctx_free, + sha384_clone_wrap, + sha384_process_wrap, +}; + +static int sha512_starts_wrap( void *ctx ) +{ + return( mbedtls_sha512_starts_ret( (mbedtls_sha512_context *) ctx, 0 ) ); +} + +static int sha512_wrap( const unsigned char *input, size_t ilen, + unsigned char *output ) +{ + return( mbedtls_sha512_ret( input, ilen, output, 0 ) ); +} + +const mbedtls_md_info_t mbedtls_sha512_info = { + MBEDTLS_MD_SHA512, + "SHA512", + 64, + 128, + sha512_starts_wrap, + sha384_update_wrap, + sha384_finish_wrap, + sha512_wrap, + sha384_ctx_alloc, + sha384_ctx_free, + sha384_clone_wrap, + sha384_process_wrap, +}; + +#endif /* MBEDTLS_SHA512_C */ + +#endif /* MBEDTLS_MD_C */ diff --git a/src/common/mbedtls/library/mbedtls_oid.c b/src/common/mbedtls/library/mbedtls_oid.c new file mode 100644 index 0000000000..fbec7b2049 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_oid.c @@ -0,0 +1,771 @@ +/** + * \file oid.c + * + * \brief Object Identifier (OID) database + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_OID_C) + +#include "mbedtls/oid.h" +#include "mbedtls/rsa.h" + +#ifndef NVRM +#include +#include +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#define mbedtls_snprintf snprintf +#endif + +#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C) +#include "mbedtls/x509.h" +#endif + +/* + * Macro to automatically add the size of #define'd OIDs + */ +#define ADD_LEN(s) s, MBEDTLS_OID_SIZE(s) + +/* + * Macro to generate an internal function for oid_XXX_from_asn1() (used by + * the other functions) + */ +#define FN_OID_TYPED_FROM_ASN1( TYPE_T, NAME, LIST ) \ + static const TYPE_T * oid_ ## NAME ## _from_asn1( \ + const mbedtls_asn1_buf *oid ) \ + { \ + const TYPE_T *p = (LIST); \ + const mbedtls_oid_descriptor_t *cur = \ + (const mbedtls_oid_descriptor_t *) p; \ + if( p == NULL || oid == NULL ) return( NULL ); \ + while( cur->asn1 != NULL ) { \ + if( cur->asn1_len == oid->len && \ + memcmp( cur->asn1, oid->p, oid->len ) == 0 ) { \ + return( p ); \ + } \ + p++; \ + cur = (const mbedtls_oid_descriptor_t *) p; \ + } \ + return( NULL ); \ + } + +/* + * Macro to generate a function for retrieving a single attribute from the + * descriptor of an mbedtls_oid_descriptor_t wrapper. + */ +#define FN_OID_GET_DESCRIPTOR_ATTR1(FN_NAME, TYPE_T, TYPE_NAME, ATTR1_TYPE, ATTR1) \ +int FN_NAME( const mbedtls_asn1_buf *oid, ATTR1_TYPE * ATTR1 ) \ +{ \ + const TYPE_T *data = oid_ ## TYPE_NAME ## _from_asn1( oid ); \ + if( data == NULL ) return( MBEDTLS_ERR_OID_NOT_FOUND ); \ + *ATTR1 = data->descriptor.ATTR1; \ + return( 0 ); \ +} + +/* + * Macro to generate a function for retrieving a single attribute from an + * mbedtls_oid_descriptor_t wrapper. + */ +#define FN_OID_GET_ATTR1(FN_NAME, TYPE_T, TYPE_NAME, ATTR1_TYPE, ATTR1) \ +int FN_NAME( const mbedtls_asn1_buf *oid, ATTR1_TYPE * ATTR1 ) \ +{ \ + const TYPE_T *data = oid_ ## TYPE_NAME ## _from_asn1( oid ); \ + if( data == NULL ) return( MBEDTLS_ERR_OID_NOT_FOUND ); \ + *ATTR1 = data->ATTR1; \ + return( 0 ); \ +} + +/* + * Macro to generate a function for retrieving two attributes from an + * mbedtls_oid_descriptor_t wrapper. + */ +#define FN_OID_GET_ATTR2(FN_NAME, TYPE_T, TYPE_NAME, ATTR1_TYPE, ATTR1, \ + ATTR2_TYPE, ATTR2) \ +int FN_NAME( const mbedtls_asn1_buf *oid, ATTR1_TYPE * ATTR1, \ + ATTR2_TYPE * ATTR2 ) \ +{ \ + const TYPE_T *data = oid_ ## TYPE_NAME ## _from_asn1( oid ); \ + if( data == NULL ) return( MBEDTLS_ERR_OID_NOT_FOUND ); \ + *(ATTR1) = data->ATTR1; \ + *(ATTR2) = data->ATTR2; \ + return( 0 ); \ +} + +/* + * Macro to generate a function for retrieving the OID based on a single + * attribute from a mbedtls_oid_descriptor_t wrapper. + */ +#define FN_OID_GET_OID_BY_ATTR1(FN_NAME, TYPE_T, LIST, ATTR1_TYPE, ATTR1) \ +int FN_NAME( ATTR1_TYPE ATTR1, const char **oid, size_t *olen ) \ +{ \ + const TYPE_T *cur = (LIST); \ + while( cur->descriptor.asn1 != NULL ) { \ + if( cur->ATTR1 == (ATTR1) ) { \ + *oid = cur->descriptor.asn1; \ + *olen = cur->descriptor.asn1_len; \ + return( 0 ); \ + } \ + cur++; \ + } \ + return( MBEDTLS_ERR_OID_NOT_FOUND ); \ +} + +/* + * Macro to generate a function for retrieving the OID based on two + * attributes from a mbedtls_oid_descriptor_t wrapper. + */ +#define FN_OID_GET_OID_BY_ATTR2(FN_NAME, TYPE_T, LIST, ATTR1_TYPE, ATTR1, \ + ATTR2_TYPE, ATTR2) \ +int FN_NAME( ATTR1_TYPE ATTR1, ATTR2_TYPE ATTR2, const char **oid , \ + size_t *olen ) \ +{ \ + const TYPE_T *cur = (LIST); \ + while( cur->descriptor.asn1 != NULL ) { \ + if( cur->ATTR1 == (ATTR1) && cur->ATTR2 == (ATTR2) ) { \ + *oid = cur->descriptor.asn1; \ + *olen = cur->descriptor.asn1_len; \ + return( 0 ); \ + } \ + cur++; \ + } \ + return( MBEDTLS_ERR_OID_NOT_FOUND ); \ +} + +#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C) +/* + * For X520 attribute types + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + const char *short_name; +} oid_x520_attr_t; + +static const oid_x520_attr_t oid_x520_attr_type[] = +{ + { + { ADD_LEN( MBEDTLS_OID_AT_CN ), "id-at-commonName", "Common Name" }, + "CN", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_COUNTRY ), "id-at-countryName", "Country" }, + "C", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_LOCALITY ), "id-at-locality", "Locality" }, + "L", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_STATE ), "id-at-state", "State" }, + "ST", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_ORGANIZATION ),"id-at-organizationName", "Organization" }, + "O", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_ORG_UNIT ), "id-at-organizationalUnitName", "Org Unit" }, + "OU", + }, + { + { ADD_LEN( MBEDTLS_OID_PKCS9_EMAIL ), "emailAddress", "E-mail address" }, + "emailAddress", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_SERIAL_NUMBER ),"id-at-serialNumber", "Serial number" }, + "serialNumber", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_POSTAL_ADDRESS ),"id-at-postalAddress", "Postal address" }, + "postalAddress", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_POSTAL_CODE ), "id-at-postalCode", "Postal code" }, + "postalCode", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_SUR_NAME ), "id-at-surName", "Surname" }, + "SN", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_GIVEN_NAME ), "id-at-givenName", "Given name" }, + "GN", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_INITIALS ), "id-at-initials", "Initials" }, + "initials", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_GENERATION_QUALIFIER ), "id-at-generationQualifier", "Generation qualifier" }, + "generationQualifier", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_TITLE ), "id-at-title", "Title" }, + "title", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_DN_QUALIFIER ),"id-at-dnQualifier", "Distinguished Name qualifier" }, + "dnQualifier", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_PSEUDONYM ), "id-at-pseudonym", "Pseudonym" }, + "pseudonym", + }, + { + { ADD_LEN( MBEDTLS_OID_DOMAIN_COMPONENT ), "id-domainComponent", "Domain component" }, + "DC", + }, + { + { ADD_LEN( MBEDTLS_OID_AT_UNIQUE_IDENTIFIER ), "id-at-uniqueIdentifier", "Unique Identifier" }, + "uniqueIdentifier", + }, + { + { NULL, 0, NULL, NULL }, + NULL, + } +}; + +FN_OID_TYPED_FROM_ASN1(oid_x520_attr_t, x520_attr, oid_x520_attr_type) +FN_OID_GET_ATTR1(mbedtls_oid_get_attr_short_name, oid_x520_attr_t, x520_attr, const char *, short_name) + +/* + * For X509 extensions + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + int ext_type; +} oid_x509_ext_t; + +static const oid_x509_ext_t oid_x509_ext[] = +{ + { + { ADD_LEN( MBEDTLS_OID_BASIC_CONSTRAINTS ), "id-ce-basicConstraints", "Basic Constraints" }, + MBEDTLS_X509_EXT_BASIC_CONSTRAINTS, + }, + { + { ADD_LEN( MBEDTLS_OID_KEY_USAGE ), "id-ce-keyUsage", "Key Usage" }, + MBEDTLS_X509_EXT_KEY_USAGE, + }, + { + { ADD_LEN( MBEDTLS_OID_EXTENDED_KEY_USAGE ), "id-ce-extKeyUsage", "Extended Key Usage" }, + MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE, + }, + { + { ADD_LEN( MBEDTLS_OID_SUBJECT_ALT_NAME ), "id-ce-subjectAltName", "Subject Alt Name" }, + MBEDTLS_X509_EXT_SUBJECT_ALT_NAME, + }, + { + { ADD_LEN( MBEDTLS_OID_NS_CERT_TYPE ), "id-netscape-certtype", "Netscape Certificate Type" }, + MBEDTLS_X509_EXT_NS_CERT_TYPE, + }, + { + { NULL, 0, NULL, NULL }, + 0, + }, +}; + +FN_OID_TYPED_FROM_ASN1(oid_x509_ext_t, x509_ext, oid_x509_ext) +FN_OID_GET_ATTR1(mbedtls_oid_get_x509_ext_type, oid_x509_ext_t, x509_ext, int, ext_type) + +static const mbedtls_oid_descriptor_t oid_ext_key_usage[] = +{ + { ADD_LEN( MBEDTLS_OID_SERVER_AUTH ), "id-kp-serverAuth", "TLS Web Server Authentication" }, + { ADD_LEN( MBEDTLS_OID_CLIENT_AUTH ), "id-kp-clientAuth", "TLS Web Client Authentication" }, + { ADD_LEN( MBEDTLS_OID_CODE_SIGNING ), "id-kp-codeSigning", "Code Signing" }, + { ADD_LEN( MBEDTLS_OID_EMAIL_PROTECTION ), "id-kp-emailProtection", "E-mail Protection" }, + { ADD_LEN( MBEDTLS_OID_TIME_STAMPING ), "id-kp-timeStamping", "Time Stamping" }, + { ADD_LEN( MBEDTLS_OID_OCSP_SIGNING ), "id-kp-OCSPSigning", "OCSP Signing" }, + { NULL, 0, NULL, NULL }, +}; + +FN_OID_TYPED_FROM_ASN1(mbedtls_oid_descriptor_t, ext_key_usage, oid_ext_key_usage) +FN_OID_GET_ATTR1(mbedtls_oid_get_extended_key_usage, mbedtls_oid_descriptor_t, ext_key_usage, const char *, description) +#endif /* MBEDTLS_X509_USE_C || MBEDTLS_X509_CREATE_C */ + +#if defined(MBEDTLS_MD_C) +/* + * For SignatureAlgorithmIdentifier + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + mbedtls_md_type_t md_alg; + mbedtls_pk_type_t pk_alg; +} oid_sig_alg_t; + +static const oid_sig_alg_t oid_sig_alg[] = +{ +#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_MD2_C) + { + { ADD_LEN( MBEDTLS_OID_PKCS1_MD2 ), "md2WithRSAEncryption", "RSA with MD2" }, + MBEDTLS_MD_MD2, MBEDTLS_PK_RSA, + }, +#endif /* MBEDTLS_MD2_C */ +#if defined(MBEDTLS_MD4_C) + { + { ADD_LEN( MBEDTLS_OID_PKCS1_MD4 ), "md4WithRSAEncryption", "RSA with MD4" }, + MBEDTLS_MD_MD4, MBEDTLS_PK_RSA, + }, +#endif /* MBEDTLS_MD4_C */ +#if defined(MBEDTLS_MD5_C) + { + { ADD_LEN( MBEDTLS_OID_PKCS1_MD5 ), "md5WithRSAEncryption", "RSA with MD5" }, + MBEDTLS_MD_MD5, MBEDTLS_PK_RSA, + }, +#endif /* MBEDTLS_MD5_C */ +#if defined(MBEDTLS_SHA1_C) + { + { ADD_LEN( MBEDTLS_OID_PKCS1_SHA1 ), "sha-1WithRSAEncryption", "RSA with SHA1" }, + MBEDTLS_MD_SHA1, MBEDTLS_PK_RSA, + }, +#endif /* MBEDTLS_SHA1_C */ +#if defined(MBEDTLS_SHA256_C) + { + { ADD_LEN( MBEDTLS_OID_PKCS1_SHA224 ), "sha224WithRSAEncryption", "RSA with SHA-224" }, + MBEDTLS_MD_SHA224, MBEDTLS_PK_RSA, + }, + { + { ADD_LEN( MBEDTLS_OID_PKCS1_SHA256 ), "sha256WithRSAEncryption", "RSA with SHA-256" }, + MBEDTLS_MD_SHA256, MBEDTLS_PK_RSA, + }, +#endif /* MBEDTLS_SHA256_C */ +#if defined(MBEDTLS_SHA512_C) + { + { ADD_LEN( MBEDTLS_OID_PKCS1_SHA384 ), "sha384WithRSAEncryption", "RSA with SHA-384" }, + MBEDTLS_MD_SHA384, MBEDTLS_PK_RSA, + }, + { + { ADD_LEN( MBEDTLS_OID_PKCS1_SHA512 ), "sha512WithRSAEncryption", "RSA with SHA-512" }, + MBEDTLS_MD_SHA512, MBEDTLS_PK_RSA, + }, +#endif /* MBEDTLS_SHA512_C */ +#if defined(MBEDTLS_SHA1_C) + { + { ADD_LEN( MBEDTLS_OID_RSA_SHA_OBS ), "sha-1WithRSAEncryption", "RSA with SHA1" }, + MBEDTLS_MD_SHA1, MBEDTLS_PK_RSA, + }, +#endif /* MBEDTLS_SHA1_C */ +#endif /* MBEDTLS_RSA_C */ +#if defined(MBEDTLS_ECDSA_C) +#if defined(MBEDTLS_SHA1_C) + { + { ADD_LEN( MBEDTLS_OID_ECDSA_SHA1 ), "ecdsa-with-SHA1", "ECDSA with SHA1" }, + MBEDTLS_MD_SHA1, MBEDTLS_PK_ECDSA, + }, +#endif /* MBEDTLS_SHA1_C */ +#if defined(MBEDTLS_SHA256_C) + { + { ADD_LEN( MBEDTLS_OID_ECDSA_SHA224 ), "ecdsa-with-SHA224", "ECDSA with SHA224" }, + MBEDTLS_MD_SHA224, MBEDTLS_PK_ECDSA, + }, + { + { ADD_LEN( MBEDTLS_OID_ECDSA_SHA256 ), "ecdsa-with-SHA256", "ECDSA with SHA256" }, + MBEDTLS_MD_SHA256, MBEDTLS_PK_ECDSA, + }, +#endif /* MBEDTLS_SHA256_C */ +#if defined(MBEDTLS_SHA512_C) + { + { ADD_LEN( MBEDTLS_OID_ECDSA_SHA384 ), "ecdsa-with-SHA384", "ECDSA with SHA384" }, + MBEDTLS_MD_SHA384, MBEDTLS_PK_ECDSA, + }, + { + { ADD_LEN( MBEDTLS_OID_ECDSA_SHA512 ), "ecdsa-with-SHA512", "ECDSA with SHA512" }, + MBEDTLS_MD_SHA512, MBEDTLS_PK_ECDSA, + }, +#endif /* MBEDTLS_SHA512_C */ +#endif /* MBEDTLS_ECDSA_C */ +#if defined(MBEDTLS_RSA_C) + { + { ADD_LEN( MBEDTLS_OID_RSASSA_PSS ), "RSASSA-PSS", "RSASSA-PSS" }, + MBEDTLS_MD_NONE, MBEDTLS_PK_RSASSA_PSS, + }, +#endif /* MBEDTLS_RSA_C */ + { + { NULL, 0, NULL, NULL }, + MBEDTLS_MD_NONE, MBEDTLS_PK_NONE, + }, +}; + +FN_OID_TYPED_FROM_ASN1(oid_sig_alg_t, sig_alg, oid_sig_alg) +FN_OID_GET_DESCRIPTOR_ATTR1(mbedtls_oid_get_sig_alg_desc, oid_sig_alg_t, sig_alg, const char *, description) +FN_OID_GET_ATTR2(mbedtls_oid_get_sig_alg, oid_sig_alg_t, sig_alg, mbedtls_md_type_t, md_alg, mbedtls_pk_type_t, pk_alg) +FN_OID_GET_OID_BY_ATTR2(mbedtls_oid_get_oid_by_sig_alg, oid_sig_alg_t, oid_sig_alg, mbedtls_pk_type_t, pk_alg, mbedtls_md_type_t, md_alg) +#endif /* MBEDTLS_MD_C */ + +/* + * For PublicKeyInfo (PKCS1, RFC 5480) + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + mbedtls_pk_type_t pk_alg; +} oid_pk_alg_t; + +static const oid_pk_alg_t oid_pk_alg[] = +{ + { + { ADD_LEN( MBEDTLS_OID_PKCS1_RSA ), "rsaEncryption", "RSA" }, + MBEDTLS_PK_RSA, + }, + { + { ADD_LEN( MBEDTLS_OID_EC_ALG_UNRESTRICTED ), "id-ecPublicKey", "Generic EC key" }, + MBEDTLS_PK_ECKEY, + }, + { + { ADD_LEN( MBEDTLS_OID_EC_ALG_ECDH ), "id-ecDH", "EC key for ECDH" }, + MBEDTLS_PK_ECKEY_DH, + }, + { + { NULL, 0, NULL, NULL }, + MBEDTLS_PK_NONE, + }, +}; + +FN_OID_TYPED_FROM_ASN1(oid_pk_alg_t, pk_alg, oid_pk_alg) +FN_OID_GET_ATTR1(mbedtls_oid_get_pk_alg, oid_pk_alg_t, pk_alg, mbedtls_pk_type_t, pk_alg) +FN_OID_GET_OID_BY_ATTR1(mbedtls_oid_get_oid_by_pk_alg, oid_pk_alg_t, oid_pk_alg, mbedtls_pk_type_t, pk_alg) + +#if defined(MBEDTLS_ECP_C) +/* + * For namedCurve (RFC 5480) + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + mbedtls_ecp_group_id grp_id; +} oid_ecp_grp_t; + +static const oid_ecp_grp_t oid_ecp_grp[] = +{ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_SECP192R1 ), "secp192r1", "secp192r1" }, + MBEDTLS_ECP_DP_SECP192R1, + }, +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_SECP224R1 ), "secp224r1", "secp224r1" }, + MBEDTLS_ECP_DP_SECP224R1, + }, +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_SECP256R1 ), "secp256r1", "secp256r1" }, + MBEDTLS_ECP_DP_SECP256R1, + }, +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_SECP384R1 ), "secp384r1", "secp384r1" }, + MBEDTLS_ECP_DP_SECP384R1, + }, +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_SECP521R1 ), "secp521r1", "secp521r1" }, + MBEDTLS_ECP_DP_SECP521R1, + }, +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_SECP192K1 ), "secp192k1", "secp192k1" }, + MBEDTLS_ECP_DP_SECP192K1, + }, +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_SECP224K1 ), "secp224k1", "secp224k1" }, + MBEDTLS_ECP_DP_SECP224K1, + }, +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_SECP256K1 ), "secp256k1", "secp256k1" }, + MBEDTLS_ECP_DP_SECP256K1, + }, +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_BP256R1 ), "brainpoolP256r1","brainpool256r1" }, + MBEDTLS_ECP_DP_BP256R1, + }, +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_BP384R1 ), "brainpoolP384r1","brainpool384r1" }, + MBEDTLS_ECP_DP_BP384R1, + }, +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + { + { ADD_LEN( MBEDTLS_OID_EC_GRP_BP512R1 ), "brainpoolP512r1","brainpool512r1" }, + MBEDTLS_ECP_DP_BP512R1, + }, +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + { + { NULL, 0, NULL, NULL }, + MBEDTLS_ECP_DP_NONE, + }, +}; + +FN_OID_TYPED_FROM_ASN1(oid_ecp_grp_t, grp_id, oid_ecp_grp) +FN_OID_GET_ATTR1(mbedtls_oid_get_ec_grp, oid_ecp_grp_t, grp_id, mbedtls_ecp_group_id, grp_id) +FN_OID_GET_OID_BY_ATTR1(mbedtls_oid_get_oid_by_ec_grp, oid_ecp_grp_t, oid_ecp_grp, mbedtls_ecp_group_id, grp_id) +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_CIPHER_C) +/* + * For PKCS#5 PBES2 encryption algorithm + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + mbedtls_cipher_type_t cipher_alg; +} oid_cipher_alg_t; + +static const oid_cipher_alg_t oid_cipher_alg[] = +{ + { + { ADD_LEN( MBEDTLS_OID_DES_CBC ), "desCBC", "DES-CBC" }, + MBEDTLS_CIPHER_DES_CBC, + }, + { + { ADD_LEN( MBEDTLS_OID_DES_EDE3_CBC ), "des-ede3-cbc", "DES-EDE3-CBC" }, + MBEDTLS_CIPHER_DES_EDE3_CBC, + }, + { + { NULL, 0, NULL, NULL }, + MBEDTLS_CIPHER_NONE, + }, +}; + +FN_OID_TYPED_FROM_ASN1(oid_cipher_alg_t, cipher_alg, oid_cipher_alg) +FN_OID_GET_ATTR1(mbedtls_oid_get_cipher_alg, oid_cipher_alg_t, cipher_alg, mbedtls_cipher_type_t, cipher_alg) +#endif /* MBEDTLS_CIPHER_C */ + +#if defined(MBEDTLS_MD_C) +/* + * For digestAlgorithm + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + mbedtls_md_type_t md_alg; +} oid_md_alg_t; + +static const oid_md_alg_t oid_md_alg[] = +{ +#if defined(MBEDTLS_MD2_C) + { + { ADD_LEN( MBEDTLS_OID_DIGEST_ALG_MD2 ), "id-md2", "MD2" }, + MBEDTLS_MD_MD2, + }, +#endif /* MBEDTLS_MD2_C */ +#if defined(MBEDTLS_MD4_C) + { + { ADD_LEN( MBEDTLS_OID_DIGEST_ALG_MD4 ), "id-md4", "MD4" }, + MBEDTLS_MD_MD4, + }, +#endif /* MBEDTLS_MD4_C */ +#if defined(MBEDTLS_MD5_C) + { + { ADD_LEN( MBEDTLS_OID_DIGEST_ALG_MD5 ), "id-md5", "MD5" }, + MBEDTLS_MD_MD5, + }, +#endif /* MBEDTLS_MD5_C */ +#if defined(MBEDTLS_SHA1_C) + { + { ADD_LEN( MBEDTLS_OID_DIGEST_ALG_SHA1 ), "id-sha1", "SHA-1" }, + MBEDTLS_MD_SHA1, + }, +#endif /* MBEDTLS_SHA1_C */ +#if defined(MBEDTLS_SHA256_C) + { + { ADD_LEN( MBEDTLS_OID_DIGEST_ALG_SHA224 ), "id-sha224", "SHA-224" }, + MBEDTLS_MD_SHA224, + }, + { + { ADD_LEN( MBEDTLS_OID_DIGEST_ALG_SHA256 ), "id-sha256", "SHA-256" }, + MBEDTLS_MD_SHA256, + }, +#endif /* MBEDTLS_SHA256_C */ +#if defined(MBEDTLS_SHA512_C) + { + { ADD_LEN( MBEDTLS_OID_DIGEST_ALG_SHA384 ), "id-sha384", "SHA-384" }, + MBEDTLS_MD_SHA384, + }, + { + { ADD_LEN( MBEDTLS_OID_DIGEST_ALG_SHA512 ), "id-sha512", "SHA-512" }, + MBEDTLS_MD_SHA512, + }, +#endif /* MBEDTLS_SHA512_C */ + { + { NULL, 0, NULL, NULL }, + MBEDTLS_MD_NONE, + }, +}; + +FN_OID_TYPED_FROM_ASN1(oid_md_alg_t, md_alg, oid_md_alg) +FN_OID_GET_ATTR1(mbedtls_oid_get_md_alg, oid_md_alg_t, md_alg, mbedtls_md_type_t, md_alg) +FN_OID_GET_OID_BY_ATTR1(mbedtls_oid_get_oid_by_md, oid_md_alg_t, oid_md_alg, mbedtls_md_type_t, md_alg) + +/* + * For HMAC digestAlgorithm + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + mbedtls_md_type_t md_hmac; +} oid_md_hmac_t; + +static const oid_md_hmac_t oid_md_hmac[] = +{ +#if defined(MBEDTLS_SHA1_C) + { + { ADD_LEN( MBEDTLS_OID_HMAC_SHA1 ), "hmacSHA1", "HMAC-SHA-1" }, + MBEDTLS_MD_SHA1, + }, +#endif /* MBEDTLS_SHA1_C */ +#if defined(MBEDTLS_SHA256_C) + { + { ADD_LEN( MBEDTLS_OID_HMAC_SHA224 ), "hmacSHA224", "HMAC-SHA-224" }, + MBEDTLS_MD_SHA224, + }, + { + { ADD_LEN( MBEDTLS_OID_HMAC_SHA256 ), "hmacSHA256", "HMAC-SHA-256" }, + MBEDTLS_MD_SHA256, + }, +#endif /* MBEDTLS_SHA256_C */ +#if defined(MBEDTLS_SHA512_C) + { + { ADD_LEN( MBEDTLS_OID_HMAC_SHA384 ), "hmacSHA384", "HMAC-SHA-384" }, + MBEDTLS_MD_SHA384, + }, + { + { ADD_LEN( MBEDTLS_OID_HMAC_SHA512 ), "hmacSHA512", "HMAC-SHA-512" }, + MBEDTLS_MD_SHA512, + }, +#endif /* MBEDTLS_SHA512_C */ + { + { NULL, 0, NULL, NULL }, + MBEDTLS_MD_NONE, + }, +}; + +FN_OID_TYPED_FROM_ASN1(oid_md_hmac_t, md_hmac, oid_md_hmac) +FN_OID_GET_ATTR1(mbedtls_oid_get_md_hmac, oid_md_hmac_t, md_hmac, mbedtls_md_type_t, md_hmac) +#endif /* MBEDTLS_MD_C */ + +#if defined(MBEDTLS_PKCS12_C) +/* + * For PKCS#12 PBEs + */ +typedef struct { + mbedtls_oid_descriptor_t descriptor; + mbedtls_md_type_t md_alg; + mbedtls_cipher_type_t cipher_alg; +} oid_pkcs12_pbe_alg_t; + +static const oid_pkcs12_pbe_alg_t oid_pkcs12_pbe_alg[] = +{ + { + { ADD_LEN( MBEDTLS_OID_PKCS12_PBE_SHA1_DES3_EDE_CBC ), "pbeWithSHAAnd3-KeyTripleDES-CBC", "PBE with SHA1 and 3-Key 3DES" }, + MBEDTLS_MD_SHA1, MBEDTLS_CIPHER_DES_EDE3_CBC, + }, + { + { ADD_LEN( MBEDTLS_OID_PKCS12_PBE_SHA1_DES2_EDE_CBC ), "pbeWithSHAAnd2-KeyTripleDES-CBC", "PBE with SHA1 and 2-Key 3DES" }, + MBEDTLS_MD_SHA1, MBEDTLS_CIPHER_DES_EDE_CBC, + }, + { + { NULL, 0, NULL, NULL }, + MBEDTLS_MD_NONE, MBEDTLS_CIPHER_NONE, + }, +}; + +FN_OID_TYPED_FROM_ASN1(oid_pkcs12_pbe_alg_t, pkcs12_pbe_alg, oid_pkcs12_pbe_alg) +FN_OID_GET_ATTR2(mbedtls_oid_get_pkcs12_pbe_alg, oid_pkcs12_pbe_alg_t, pkcs12_pbe_alg, mbedtls_md_type_t, md_alg, mbedtls_cipher_type_t, cipher_alg) +#endif /* MBEDTLS_PKCS12_C */ + +#define OID_SAFE_SNPRINTF \ + do { \ + if( ret < 0 || (size_t) ret >= n ) \ + return( MBEDTLS_ERR_OID_BUF_TOO_SMALL ); \ + \ + n -= (size_t) ret; \ + p += (size_t) ret; \ + } while( 0 ) + +/* Return the x.y.z.... style numeric string for the given OID */ +int mbedtls_oid_get_numeric_string( char *buf, size_t size, + const mbedtls_asn1_buf *oid ) +{ + int ret; + size_t i, n; + unsigned int value; + char *p; + + p = buf; + n = size; + + /* First byte contains first two dots */ + if( oid->len > 0 ) + { + ret = mbedtls_snprintf( p, n, "%d.%d", oid->p[0] / 40, oid->p[0] % 40 ); + OID_SAFE_SNPRINTF; + } + + value = 0; + for( i = 1; i < oid->len; i++ ) + { + /* Prevent overflow in value. */ + if( ( ( value << 7 ) >> 7 ) != value ) + return( MBEDTLS_ERR_OID_BUF_TOO_SMALL ); + + value <<= 7; + value += oid->p[i] & 0x7F; + + if( !( oid->p[i] & 0x80 ) ) + { + /* Last byte */ + ret = mbedtls_snprintf( p, n, ".%d", value ); + OID_SAFE_SNPRINTF; + value = 0; + } + } + + return( (int) ( size - n ) ); +} + +#endif /* MBEDTLS_OID_C */ diff --git a/src/common/mbedtls/library/mbedtls_pem.c b/src/common/mbedtls/library/mbedtls_pem.c new file mode 100644 index 0000000000..eb35fbf1a3 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_pem.c @@ -0,0 +1,507 @@ +/* + * Privacy Enhanced Mail (PEM) decoding + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) || defined(MBEDTLS_PEM_WRITE_C) + +#include "mbedtls/pem.h" +#include "mbedtls/base64.h" +#include "mbedtls/des.h" +#include "mbedtls/aes.h" +#include "mbedtls/md5.h" +#include "mbedtls/cipher.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) +void mbedtls_pem_init( mbedtls_pem_context *ctx ) +{ + memset( ctx, 0, sizeof( mbedtls_pem_context ) ); +} + +#if defined(MBEDTLS_MD5_C) && defined(MBEDTLS_CIPHER_MODE_CBC) && \ + ( defined(MBEDTLS_DES_C) || defined(MBEDTLS_AES_C) ) +/* + * Read a 16-byte hex string and convert it to binary + */ +static int pem_get_iv( const unsigned char *s, unsigned char *iv, + size_t iv_len ) +{ + size_t i, j, k; + + memset( iv, 0, iv_len ); + + for( i = 0; i < iv_len * 2; i++, s++ ) + { + if( *s >= '0' && *s <= '9' ) j = *s - '0'; else + if( *s >= 'A' && *s <= 'F' ) j = *s - '7'; else + if( *s >= 'a' && *s <= 'f' ) j = *s - 'W'; else + return( MBEDTLS_ERR_PEM_INVALID_ENC_IV ); + + k = ( ( i & 1 ) != 0 ) ? j : j << 4; + + iv[i >> 1] = (unsigned char)( iv[i >> 1] | k ); + } + + return( 0 ); +} + +static int pem_pbkdf1( unsigned char *key, size_t keylen, + unsigned char *iv, + const unsigned char *pwd, size_t pwdlen ) +{ + mbedtls_md5_context md5_ctx; + unsigned char md5sum[16]; + size_t use_len; + int ret; + + mbedtls_md5_init( &md5_ctx ); + + /* + * key[ 0..15] = MD5(pwd || IV) + */ + if( ( ret = mbedtls_md5_starts_ret( &md5_ctx ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md5_update_ret( &md5_ctx, pwd, pwdlen ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md5_update_ret( &md5_ctx, iv, 8 ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md5_finish_ret( &md5_ctx, md5sum ) ) != 0 ) + goto exit; + + if( keylen <= 16 ) + { + memcpy( key, md5sum, keylen ); + goto exit; + } + + memcpy( key, md5sum, 16 ); + + /* + * key[16..23] = MD5(key[ 0..15] || pwd || IV]) + */ + if( ( ret = mbedtls_md5_starts_ret( &md5_ctx ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md5_update_ret( &md5_ctx, md5sum, 16 ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md5_update_ret( &md5_ctx, pwd, pwdlen ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md5_update_ret( &md5_ctx, iv, 8 ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md5_finish_ret( &md5_ctx, md5sum ) ) != 0 ) + goto exit; + + use_len = 16; + if( keylen < 32 ) + use_len = keylen - 16; + + memcpy( key + 16, md5sum, use_len ); + +exit: + mbedtls_md5_free( &md5_ctx ); + mbedtls_platform_zeroize( md5sum, 16 ); + + return( ret ); +} + +#if defined(MBEDTLS_DES_C) +/* + * Decrypt with DES-CBC, using PBKDF1 for key derivation + */ +static int pem_des_decrypt( unsigned char des_iv[8], + unsigned char *buf, size_t buflen, + const unsigned char *pwd, size_t pwdlen ) +{ + mbedtls_des_context des_ctx; + unsigned char des_key[8]; + int ret; + + mbedtls_des_init( &des_ctx ); + + if( ( ret = pem_pbkdf1( des_key, 8, des_iv, pwd, pwdlen ) ) != 0 ) + goto exit; + + if( ( ret = mbedtls_des_setkey_dec( &des_ctx, des_key ) ) != 0 ) + goto exit; + ret = mbedtls_des_crypt_cbc( &des_ctx, MBEDTLS_DES_DECRYPT, buflen, + des_iv, buf, buf ); + +exit: + mbedtls_des_free( &des_ctx ); + mbedtls_platform_zeroize( des_key, 8 ); + + return( ret ); +} + +/* + * Decrypt with 3DES-CBC, using PBKDF1 for key derivation + */ +static int pem_des3_decrypt( unsigned char des3_iv[8], + unsigned char *buf, size_t buflen, + const unsigned char *pwd, size_t pwdlen ) +{ + mbedtls_des3_context des3_ctx; + unsigned char des3_key[24]; + int ret; + + mbedtls_des3_init( &des3_ctx ); + + if( ( ret = pem_pbkdf1( des3_key, 24, des3_iv, pwd, pwdlen ) ) != 0 ) + goto exit; + + if( ( ret = mbedtls_des3_set3key_dec( &des3_ctx, des3_key ) ) != 0 ) + goto exit; + ret = mbedtls_des3_crypt_cbc( &des3_ctx, MBEDTLS_DES_DECRYPT, buflen, + des3_iv, buf, buf ); + +exit: + mbedtls_des3_free( &des3_ctx ); + mbedtls_platform_zeroize( des3_key, 24 ); + + return( ret ); +} +#endif /* MBEDTLS_DES_C */ + +#if defined(MBEDTLS_AES_C) +/* + * Decrypt with AES-XXX-CBC, using PBKDF1 for key derivation + */ +static int pem_aes_decrypt( unsigned char aes_iv[16], unsigned int keylen, + unsigned char *buf, size_t buflen, + const unsigned char *pwd, size_t pwdlen ) +{ + mbedtls_aes_context aes_ctx; + unsigned char aes_key[32]; + int ret; + + mbedtls_aes_init( &aes_ctx ); + + if( ( ret = pem_pbkdf1( aes_key, keylen, aes_iv, pwd, pwdlen ) ) != 0 ) + goto exit; + + if( ( ret = mbedtls_aes_setkey_dec( &aes_ctx, aes_key, keylen * 8 ) ) != 0 ) + goto exit; + ret = mbedtls_aes_crypt_cbc( &aes_ctx, MBEDTLS_AES_DECRYPT, buflen, + aes_iv, buf, buf ); + +exit: + mbedtls_aes_free( &aes_ctx ); + mbedtls_platform_zeroize( aes_key, keylen ); + + return( ret ); +} +#endif /* MBEDTLS_AES_C */ + +#endif /* MBEDTLS_MD5_C && MBEDTLS_CIPHER_MODE_CBC && + ( MBEDTLS_AES_C || MBEDTLS_DES_C ) */ + +int mbedtls_pem_read_buffer( mbedtls_pem_context *ctx, const char *header, const char *footer, + const unsigned char *data, const unsigned char *pwd, + size_t pwdlen, size_t *use_len ) +{ + int ret, enc; + size_t len; + unsigned char *buf; + const unsigned char *s1, *s2, *end; +#if defined(MBEDTLS_MD5_C) && defined(MBEDTLS_CIPHER_MODE_CBC) && \ + ( defined(MBEDTLS_DES_C) || defined(MBEDTLS_AES_C) ) + unsigned char pem_iv[16]; + mbedtls_cipher_type_t enc_alg = MBEDTLS_CIPHER_NONE; +#else + ((void) pwd); + ((void) pwdlen); +#endif /* MBEDTLS_MD5_C && MBEDTLS_CIPHER_MODE_CBC && + ( MBEDTLS_AES_C || MBEDTLS_DES_C ) */ + + if( ctx == NULL ) + return( MBEDTLS_ERR_PEM_BAD_INPUT_DATA ); + + s1 = (unsigned char *) strstr( (const char *) data, header ); + + if( s1 == NULL ) + return( MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ); + + s2 = (unsigned char *) strstr( (const char *) data, footer ); + + if( s2 == NULL || s2 <= s1 ) + return( MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ); + + s1 += strlen( header ); + if( *s1 == ' ' ) s1++; + if( *s1 == '\r' ) s1++; + if( *s1 == '\n' ) s1++; + else return( MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ); + + end = s2; + end += strlen( footer ); + if( *end == ' ' ) end++; + if( *end == '\r' ) end++; + if( *end == '\n' ) end++; + *use_len = end - data; + + enc = 0; + + if( s2 - s1 >= 22 && memcmp( s1, "Proc-Type: 4,ENCRYPTED", 22 ) == 0 ) + { +#if defined(MBEDTLS_MD5_C) && defined(MBEDTLS_CIPHER_MODE_CBC) && \ + ( defined(MBEDTLS_DES_C) || defined(MBEDTLS_AES_C) ) + enc++; + + s1 += 22; + if( *s1 == '\r' ) s1++; + if( *s1 == '\n' ) s1++; + else return( MBEDTLS_ERR_PEM_INVALID_DATA ); + + +#if defined(MBEDTLS_DES_C) + if( s2 - s1 >= 23 && memcmp( s1, "DEK-Info: DES-EDE3-CBC,", 23 ) == 0 ) + { + enc_alg = MBEDTLS_CIPHER_DES_EDE3_CBC; + + s1 += 23; + if( s2 - s1 < 16 || pem_get_iv( s1, pem_iv, 8 ) != 0 ) + return( MBEDTLS_ERR_PEM_INVALID_ENC_IV ); + + s1 += 16; + } + else if( s2 - s1 >= 18 && memcmp( s1, "DEK-Info: DES-CBC,", 18 ) == 0 ) + { + enc_alg = MBEDTLS_CIPHER_DES_CBC; + + s1 += 18; + if( s2 - s1 < 16 || pem_get_iv( s1, pem_iv, 8) != 0 ) + return( MBEDTLS_ERR_PEM_INVALID_ENC_IV ); + + s1 += 16; + } +#endif /* MBEDTLS_DES_C */ + +#if defined(MBEDTLS_AES_C) + if( s2 - s1 >= 14 && memcmp( s1, "DEK-Info: AES-", 14 ) == 0 ) + { + if( s2 - s1 < 22 ) + return( MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG ); + else if( memcmp( s1, "DEK-Info: AES-128-CBC,", 22 ) == 0 ) + enc_alg = MBEDTLS_CIPHER_AES_128_CBC; + else if( memcmp( s1, "DEK-Info: AES-192-CBC,", 22 ) == 0 ) + enc_alg = MBEDTLS_CIPHER_AES_192_CBC; + else if( memcmp( s1, "DEK-Info: AES-256-CBC,", 22 ) == 0 ) + enc_alg = MBEDTLS_CIPHER_AES_256_CBC; + else + return( MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG ); + + s1 += 22; + if( s2 - s1 < 32 || pem_get_iv( s1, pem_iv, 16 ) != 0 ) + return( MBEDTLS_ERR_PEM_INVALID_ENC_IV ); + + s1 += 32; + } +#endif /* MBEDTLS_AES_C */ + + if( enc_alg == MBEDTLS_CIPHER_NONE ) + return( MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG ); + + if( *s1 == '\r' ) s1++; + if( *s1 == '\n' ) s1++; + else return( MBEDTLS_ERR_PEM_INVALID_DATA ); +#else + return( MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE ); +#endif /* MBEDTLS_MD5_C && MBEDTLS_CIPHER_MODE_CBC && + ( MBEDTLS_AES_C || MBEDTLS_DES_C ) */ + } + + if( s1 >= s2 ) + return( MBEDTLS_ERR_PEM_INVALID_DATA ); + + ret = mbedtls_base64_decode( NULL, 0, &len, s1, s2 - s1 ); + + if( ret == MBEDTLS_ERR_BASE64_INVALID_CHARACTER ) + return( MBEDTLS_ERR_PEM_INVALID_DATA + ret ); + + if( ( buf = mbedtls_calloc( 1, len ) ) == NULL ) + return( MBEDTLS_ERR_PEM_ALLOC_FAILED ); + + if( ( ret = mbedtls_base64_decode( buf, len, &len, s1, s2 - s1 ) ) != 0 ) + { + mbedtls_platform_zeroize( buf, len ); + mbedtls_free( buf ); + return( MBEDTLS_ERR_PEM_INVALID_DATA + ret ); + } + + if( enc != 0 ) + { +#if defined(MBEDTLS_MD5_C) && defined(MBEDTLS_CIPHER_MODE_CBC) && \ + ( defined(MBEDTLS_DES_C) || defined(MBEDTLS_AES_C) ) + if( pwd == NULL ) + { + mbedtls_platform_zeroize( buf, len ); + mbedtls_free( buf ); + return( MBEDTLS_ERR_PEM_PASSWORD_REQUIRED ); + } + + ret = 0; + +#if defined(MBEDTLS_DES_C) + if( enc_alg == MBEDTLS_CIPHER_DES_EDE3_CBC ) + ret = pem_des3_decrypt( pem_iv, buf, len, pwd, pwdlen ); + else if( enc_alg == MBEDTLS_CIPHER_DES_CBC ) + ret = pem_des_decrypt( pem_iv, buf, len, pwd, pwdlen ); +#endif /* MBEDTLS_DES_C */ + +#if defined(MBEDTLS_AES_C) + if( enc_alg == MBEDTLS_CIPHER_AES_128_CBC ) + ret = pem_aes_decrypt( pem_iv, 16, buf, len, pwd, pwdlen ); + else if( enc_alg == MBEDTLS_CIPHER_AES_192_CBC ) + ret = pem_aes_decrypt( pem_iv, 24, buf, len, pwd, pwdlen ); + else if( enc_alg == MBEDTLS_CIPHER_AES_256_CBC ) + ret = pem_aes_decrypt( pem_iv, 32, buf, len, pwd, pwdlen ); +#endif /* MBEDTLS_AES_C */ + + if( ret != 0 ) + { + mbedtls_free( buf ); + return( ret ); + } + + /* + * The result will be ASN.1 starting with a SEQUENCE tag, with 1 to 3 + * length bytes (allow 4 to be sure) in all known use cases. + * + * Use that as a heuristic to try to detect password mismatches. + */ + if( len <= 2 || buf[0] != 0x30 || buf[1] > 0x83 ) + { + mbedtls_platform_zeroize( buf, len ); + mbedtls_free( buf ); + return( MBEDTLS_ERR_PEM_PASSWORD_MISMATCH ); + } +#else + mbedtls_platform_zeroize( buf, len ); + mbedtls_free( buf ); + return( MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE ); +#endif /* MBEDTLS_MD5_C && MBEDTLS_CIPHER_MODE_CBC && + ( MBEDTLS_AES_C || MBEDTLS_DES_C ) */ + } + + ctx->buf = buf; + ctx->buflen = len; + + return( 0 ); +} + +void mbedtls_pem_free( mbedtls_pem_context *ctx ) +{ + if ( ctx->buf != NULL ) + { + mbedtls_platform_zeroize( ctx->buf, ctx->buflen ); + mbedtls_free( ctx->buf ); + } + mbedtls_free( ctx->info ); + + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_pem_context ) ); +} +#endif /* MBEDTLS_PEM_PARSE_C */ + +#if defined(MBEDTLS_PEM_WRITE_C) +int mbedtls_pem_write_buffer( const char *header, const char *footer, + const unsigned char *der_data, size_t der_len, + unsigned char *buf, size_t buf_len, size_t *olen ) +{ + int ret; + unsigned char *encode_buf = NULL, *c, *p = buf; + size_t len = 0, use_len, add_len = 0; + + mbedtls_base64_encode( NULL, 0, &use_len, der_data, der_len ); + add_len = strlen( header ) + strlen( footer ) + ( use_len / 64 ) + 1; + + if( use_len + add_len > buf_len ) + { + *olen = use_len + add_len; + return( MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL ); + } + + if( use_len != 0 && + ( ( encode_buf = mbedtls_calloc( 1, use_len ) ) == NULL ) ) + return( MBEDTLS_ERR_PEM_ALLOC_FAILED ); + + if( ( ret = mbedtls_base64_encode( encode_buf, use_len, &use_len, der_data, + der_len ) ) != 0 ) + { + mbedtls_free( encode_buf ); + return( ret ); + } + + memcpy( p, header, strlen( header ) ); + p += strlen( header ); + c = encode_buf; + + while( use_len ) + { + len = ( use_len > 64 ) ? 64 : use_len; + memcpy( p, c, len ); + use_len -= len; + p += len; + c += len; + *p++ = '\n'; + } + + memcpy( p, footer, strlen( footer ) ); + p += strlen( footer ); + + *p++ = '\0'; + *olen = p - buf; + + /* Clean any remaining data previously written to the buffer */ + memset( buf + *olen, 0, buf_len - *olen ); + + mbedtls_free( encode_buf ); + return( 0 ); +} +#endif /* MBEDTLS_PEM_WRITE_C */ +#endif /* MBEDTLS_PEM_PARSE_C || MBEDTLS_PEM_WRITE_C */ + diff --git a/src/common/mbedtls/library/mbedtls_pk.c b/src/common/mbedtls/library/mbedtls_pk.c new file mode 100644 index 0000000000..74758439fb --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_pk.c @@ -0,0 +1,560 @@ +/* + * Public Key abstraction layer + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_PK_C) +#include "mbedtls/pk.h" +#include "mbedtls/pk_internal.h" + +#include "mbedtls/platform_util.h" + +#if defined(MBEDTLS_RSA_C) +#include "mbedtls/rsa.h" +#endif +#if defined(MBEDTLS_ECP_C) +#include "mbedtls/ecp.h" +#endif +#if defined(MBEDTLS_ECDSA_C) +#include "mbedtls/ecdsa.h" +#endif + +#include +#include + +/* Parameter validation macros based on platform_util.h */ +#define PK_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_PK_BAD_INPUT_DATA ) +#define PK_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +/* + * Initialise a mbedtls_pk_context + */ +void mbedtls_pk_init( mbedtls_pk_context *ctx ) +{ + PK_VALIDATE( ctx != NULL ); + + ctx->pk_info = NULL; + ctx->pk_ctx = NULL; +} + +/* + * Free (the components of) a mbedtls_pk_context + */ +void mbedtls_pk_free( mbedtls_pk_context *ctx ) +{ + if( ctx == NULL ) + return; + + if ( ctx->pk_info != NULL ) + ctx->pk_info->ctx_free_func( ctx->pk_ctx ); + + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_pk_context ) ); +} + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Initialize a restart context + */ +void mbedtls_pk_restart_init( mbedtls_pk_restart_ctx *ctx ) +{ + PK_VALIDATE( ctx != NULL ); + ctx->pk_info = NULL; + ctx->rs_ctx = NULL; +} + +/* + * Free the components of a restart context + */ +void mbedtls_pk_restart_free( mbedtls_pk_restart_ctx *ctx ) +{ + if( ctx == NULL || ctx->pk_info == NULL || + ctx->pk_info->rs_free_func == NULL ) + { + return; + } + + ctx->pk_info->rs_free_func( ctx->rs_ctx ); + + ctx->pk_info = NULL; + ctx->rs_ctx = NULL; +} +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +/* + * Get pk_info structure from type + */ +const mbedtls_pk_info_t * mbedtls_pk_info_from_type( mbedtls_pk_type_t pk_type ) +{ + switch( pk_type ) { +#if defined(MBEDTLS_RSA_C) + case MBEDTLS_PK_RSA: + return( &mbedtls_rsa_info ); +#endif +#if defined(MBEDTLS_ECP_C) + case MBEDTLS_PK_ECKEY: + return( &mbedtls_eckey_info ); + case MBEDTLS_PK_ECKEY_DH: + return( &mbedtls_eckeydh_info ); +#endif +#if defined(MBEDTLS_ECDSA_C) + case MBEDTLS_PK_ECDSA: + return( &mbedtls_ecdsa_info ); +#endif + /* MBEDTLS_PK_RSA_ALT omitted on purpose */ + default: + return( NULL ); + } +} + +/* + * Initialise context + */ +int mbedtls_pk_setup( mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info ) +{ + PK_VALIDATE_RET( ctx != NULL ); + if( info == NULL || ctx->pk_info != NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + if( ( ctx->pk_ctx = info->ctx_alloc_func() ) == NULL ) + return( MBEDTLS_ERR_PK_ALLOC_FAILED ); + + ctx->pk_info = info; + + return( 0 ); +} + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +/* + * Initialize an RSA-alt context + */ +int mbedtls_pk_setup_rsa_alt( mbedtls_pk_context *ctx, void * key, + mbedtls_pk_rsa_alt_decrypt_func decrypt_func, + mbedtls_pk_rsa_alt_sign_func sign_func, + mbedtls_pk_rsa_alt_key_len_func key_len_func ) +{ + mbedtls_rsa_alt_context *rsa_alt; + const mbedtls_pk_info_t *info = &mbedtls_rsa_alt_info; + + PK_VALIDATE_RET( ctx != NULL ); + if( ctx->pk_info != NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + if( ( ctx->pk_ctx = info->ctx_alloc_func() ) == NULL ) + return( MBEDTLS_ERR_PK_ALLOC_FAILED ); + + ctx->pk_info = info; + + rsa_alt = (mbedtls_rsa_alt_context *) ctx->pk_ctx; + + rsa_alt->key = key; + rsa_alt->decrypt_func = decrypt_func; + rsa_alt->sign_func = sign_func; + rsa_alt->key_len_func = key_len_func; + + return( 0 ); +} +#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ + +/* + * Tell if a PK can do the operations of the given type + */ +int mbedtls_pk_can_do( const mbedtls_pk_context *ctx, mbedtls_pk_type_t type ) +{ + /* A context with null pk_info is not set up yet and can't do anything. + * For backward compatibility, also accept NULL instead of a context + * pointer. */ + if( ctx == NULL || ctx->pk_info == NULL ) + return( 0 ); + + return( ctx->pk_info->can_do( type ) ); +} + +/* + * Helper for mbedtls_pk_sign and mbedtls_pk_verify + */ +static inline int pk_hashlen_helper( mbedtls_md_type_t md_alg, size_t *hash_len ) +{ + const mbedtls_md_info_t *md_info; + + if( *hash_len != 0 && md_alg == MBEDTLS_MD_NONE ) + return( 0 ); + + if( ( md_info = mbedtls_md_info_from_type( md_alg ) ) == NULL ) + return( -1 ); + + if ( *hash_len != 0 && *hash_len < mbedtls_md_get_size( md_info ) ) + return ( -1 ); + + *hash_len = mbedtls_md_get_size( md_info ); + return( 0 ); +} + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Helper to set up a restart context if needed + */ +static int pk_restart_setup( mbedtls_pk_restart_ctx *ctx, + const mbedtls_pk_info_t *info ) +{ + /* Don't do anything if already set up or invalid */ + if( ctx == NULL || ctx->pk_info != NULL ) + return( 0 ); + + /* Should never happen when we're called */ + if( info->rs_alloc_func == NULL || info->rs_free_func == NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + if( ( ctx->rs_ctx = info->rs_alloc_func() ) == NULL ) + return( MBEDTLS_ERR_PK_ALLOC_FAILED ); + + ctx->pk_info = info; + + return( 0 ); +} +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +/* + * Verify a signature (restartable) + */ +int mbedtls_pk_verify_restartable( mbedtls_pk_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len, + mbedtls_pk_restart_ctx *rs_ctx ) +{ + PK_VALIDATE_RET( ctx != NULL ); + PK_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && hash_len == 0 ) || + hash != NULL ); + PK_VALIDATE_RET( sig != NULL ); + + if( ctx->pk_info == NULL || + pk_hashlen_helper( md_alg, &hash_len ) != 0 ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /* optimization: use non-restartable version if restart disabled */ + if( rs_ctx != NULL && + mbedtls_ecp_restart_is_enabled() && + ctx->pk_info->verify_rs_func != NULL ) + { + int ret; + + if( ( ret = pk_restart_setup( rs_ctx, ctx->pk_info ) ) != 0 ) + return( ret ); + + ret = ctx->pk_info->verify_rs_func( ctx->pk_ctx, + md_alg, hash, hash_len, sig, sig_len, rs_ctx->rs_ctx ); + + if( ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) + mbedtls_pk_restart_free( rs_ctx ); + + return( ret ); + } +#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + (void) rs_ctx; +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + + if( ctx->pk_info->verify_func == NULL ) + return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); + + return( ctx->pk_info->verify_func( ctx->pk_ctx, md_alg, hash, hash_len, + sig, sig_len ) ); +} + +/* + * Verify a signature + */ +int mbedtls_pk_verify( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ) +{ + return( mbedtls_pk_verify_restartable( ctx, md_alg, hash, hash_len, + sig, sig_len, NULL ) ); +} + +/* + * Verify a signature with options + */ +int mbedtls_pk_verify_ext( mbedtls_pk_type_t type, const void *options, + mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ) +{ + PK_VALIDATE_RET( ctx != NULL ); + PK_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && hash_len == 0 ) || + hash != NULL ); + PK_VALIDATE_RET( sig != NULL ); + + if( ctx->pk_info == NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + if( ! mbedtls_pk_can_do( ctx, type ) ) + return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); + + if( type == MBEDTLS_PK_RSASSA_PSS ) + { +#if defined(MBEDTLS_RSA_C) && defined(MBEDTLS_PKCS1_V21) + int ret; + const mbedtls_pk_rsassa_pss_options *pss_opts; + +#if SIZE_MAX > UINT_MAX + if( md_alg == MBEDTLS_MD_NONE && UINT_MAX < hash_len ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); +#endif /* SIZE_MAX > UINT_MAX */ + + if( options == NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + pss_opts = (const mbedtls_pk_rsassa_pss_options *) options; + + if( sig_len < mbedtls_pk_get_len( ctx ) ) + return( MBEDTLS_ERR_RSA_VERIFY_FAILED ); + + ret = mbedtls_rsa_rsassa_pss_verify_ext( mbedtls_pk_rsa( *ctx ), + NULL, NULL, MBEDTLS_RSA_PUBLIC, + md_alg, (unsigned int) hash_len, hash, + pss_opts->mgf1_hash_id, + pss_opts->expected_salt_len, + sig ); + if( ret != 0 ) + return( ret ); + + if( sig_len > mbedtls_pk_get_len( ctx ) ) + return( MBEDTLS_ERR_PK_SIG_LEN_MISMATCH ); + + return( 0 ); +#else + return( MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE ); +#endif /* MBEDTLS_RSA_C && MBEDTLS_PKCS1_V21 */ + } + + /* General case: no options */ + if( options != NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + return( mbedtls_pk_verify( ctx, md_alg, hash, hash_len, sig, sig_len ) ); +} + +/* + * Make a signature (restartable) + */ +int mbedtls_pk_sign_restartable( mbedtls_pk_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_pk_restart_ctx *rs_ctx ) +{ + PK_VALIDATE_RET( ctx != NULL ); + PK_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && hash_len == 0 ) || + hash != NULL ); + PK_VALIDATE_RET( sig != NULL ); + + if( ctx->pk_info == NULL || + pk_hashlen_helper( md_alg, &hash_len ) != 0 ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /* optimization: use non-restartable version if restart disabled */ + if( rs_ctx != NULL && + mbedtls_ecp_restart_is_enabled() && + ctx->pk_info->sign_rs_func != NULL ) + { + int ret; + + if( ( ret = pk_restart_setup( rs_ctx, ctx->pk_info ) ) != 0 ) + return( ret ); + + ret = ctx->pk_info->sign_rs_func( ctx->pk_ctx, md_alg, + hash, hash_len, sig, sig_len, f_rng, p_rng, rs_ctx->rs_ctx ); + + if( ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) + mbedtls_pk_restart_free( rs_ctx ); + + return( ret ); + } +#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + (void) rs_ctx; +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + + if( ctx->pk_info->sign_func == NULL ) + return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); + + return( ctx->pk_info->sign_func( ctx->pk_ctx, md_alg, hash, hash_len, + sig, sig_len, f_rng, p_rng ) ); +} + +/* + * Make a signature + */ +int mbedtls_pk_sign( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + return( mbedtls_pk_sign_restartable( ctx, md_alg, hash, hash_len, + sig, sig_len, f_rng, p_rng, NULL ) ); +} + +/* + * Decrypt message + */ +int mbedtls_pk_decrypt( mbedtls_pk_context *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + PK_VALIDATE_RET( ctx != NULL ); + PK_VALIDATE_RET( input != NULL || ilen == 0 ); + PK_VALIDATE_RET( output != NULL || osize == 0 ); + PK_VALIDATE_RET( olen != NULL ); + + if( ctx->pk_info == NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + if( ctx->pk_info->decrypt_func == NULL ) + return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); + + return( ctx->pk_info->decrypt_func( ctx->pk_ctx, input, ilen, + output, olen, osize, f_rng, p_rng ) ); +} + +/* + * Encrypt message + */ +int mbedtls_pk_encrypt( mbedtls_pk_context *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + PK_VALIDATE_RET( ctx != NULL ); + PK_VALIDATE_RET( input != NULL || ilen == 0 ); + PK_VALIDATE_RET( output != NULL || osize == 0 ); + PK_VALIDATE_RET( olen != NULL ); + + if( ctx->pk_info == NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + if( ctx->pk_info->encrypt_func == NULL ) + return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); + + return( ctx->pk_info->encrypt_func( ctx->pk_ctx, input, ilen, + output, olen, osize, f_rng, p_rng ) ); +} + +/* + * Check public-private key pair + */ +int mbedtls_pk_check_pair( const mbedtls_pk_context *pub, const mbedtls_pk_context *prv ) +{ + PK_VALIDATE_RET( pub != NULL ); + PK_VALIDATE_RET( prv != NULL ); + + if( pub->pk_info == NULL || + prv->pk_info == NULL || + prv->pk_info->check_pair_func == NULL ) + { + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + } + + if( prv->pk_info->type == MBEDTLS_PK_RSA_ALT ) + { + if( pub->pk_info->type != MBEDTLS_PK_RSA ) + return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); + } + else + { + if( pub->pk_info != prv->pk_info ) + return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); + } + + return( prv->pk_info->check_pair_func( pub->pk_ctx, prv->pk_ctx ) ); +} + +/* + * Get key size in bits + */ +size_t mbedtls_pk_get_bitlen( const mbedtls_pk_context *ctx ) +{ + /* For backward compatibility, accept NULL or a context that + * isn't set up yet, and return a fake value that should be safe. */ + if( ctx == NULL || ctx->pk_info == NULL ) + return( 0 ); + + return( ctx->pk_info->get_bitlen( ctx->pk_ctx ) ); +} + +/* + * Export debug information + */ +int mbedtls_pk_debug( const mbedtls_pk_context *ctx, mbedtls_pk_debug_item *items ) +{ + PK_VALIDATE_RET( ctx != NULL ); + if( ctx->pk_info == NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + if( ctx->pk_info->debug_func == NULL ) + return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); + + ctx->pk_info->debug_func( ctx->pk_ctx, items ); + return( 0 ); +} + +/* + * Access the PK type name + */ +const char *mbedtls_pk_get_name( const mbedtls_pk_context *ctx ) +{ + if( ctx == NULL || ctx->pk_info == NULL ) + return( "invalid PK" ); + + return( ctx->pk_info->name ); +} + +/* + * Access the PK type + */ +mbedtls_pk_type_t mbedtls_pk_get_type( const mbedtls_pk_context *ctx ) +{ + if( ctx == NULL || ctx->pk_info == NULL ) + return( MBEDTLS_PK_NONE ); + + return( ctx->pk_info->type ); +} + +#endif /* MBEDTLS_PK_C */ diff --git a/src/common/mbedtls/library/mbedtls_pk_wrap.c b/src/common/mbedtls/library/mbedtls_pk_wrap.c new file mode 100644 index 0000000000..c1e84f6f6f --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_pk_wrap.c @@ -0,0 +1,732 @@ +/* + * Public Key abstraction layer: wrapper functions + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_PK_C) +#include "mbedtls/pk_internal.h" + +/* Even if RSA not activated, for the sake of RSA-alt */ +#include "mbedtls/rsa.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_ECP_C) +#include "mbedtls/ecp.h" +#endif + +#if defined(MBEDTLS_ECDSA_C) +#include "mbedtls/ecdsa.h" +#endif + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +#include "mbedtls/platform_util.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#include +#include + +#if defined(MBEDTLS_RSA_C) +static int rsa_can_do( mbedtls_pk_type_t type ) +{ + return( type == MBEDTLS_PK_RSA || + type == MBEDTLS_PK_RSASSA_PSS ); +} + +static size_t rsa_get_bitlen( const void *ctx ) +{ + const mbedtls_rsa_context * rsa = (const mbedtls_rsa_context *) ctx; + return( 8 * mbedtls_rsa_get_len( rsa ) ); +} + +static int rsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ) +{ + int ret; + mbedtls_rsa_context * rsa = (mbedtls_rsa_context *) ctx; + size_t rsa_len = mbedtls_rsa_get_len( rsa ); + +#if SIZE_MAX > UINT_MAX + if( md_alg == MBEDTLS_MD_NONE && UINT_MAX < hash_len ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); +#endif /* SIZE_MAX > UINT_MAX */ + + if( sig_len < rsa_len ) + return( MBEDTLS_ERR_RSA_VERIFY_FAILED ); + + if( ( ret = mbedtls_rsa_pkcs1_verify( rsa, NULL, NULL, + MBEDTLS_RSA_PUBLIC, md_alg, + (unsigned int) hash_len, hash, sig ) ) != 0 ) + return( ret ); + + /* The buffer contains a valid signature followed by extra data. + * We have a special error code for that so that so that callers can + * use mbedtls_pk_verify() to check "Does the buffer start with a + * valid signature?" and not just "Does the buffer contain a valid + * signature?". */ + if( sig_len > rsa_len ) + return( MBEDTLS_ERR_PK_SIG_LEN_MISMATCH ); + + return( 0 ); +} + +static int rsa_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + mbedtls_rsa_context * rsa = (mbedtls_rsa_context *) ctx; + +#if SIZE_MAX > UINT_MAX + if( md_alg == MBEDTLS_MD_NONE && UINT_MAX < hash_len ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); +#endif /* SIZE_MAX > UINT_MAX */ + + *sig_len = mbedtls_rsa_get_len( rsa ); + + return( mbedtls_rsa_pkcs1_sign( rsa, f_rng, p_rng, MBEDTLS_RSA_PRIVATE, + md_alg, (unsigned int) hash_len, hash, sig ) ); +} + +static int rsa_decrypt_wrap( void *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + mbedtls_rsa_context * rsa = (mbedtls_rsa_context *) ctx; + + if( ilen != mbedtls_rsa_get_len( rsa ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + return( mbedtls_rsa_pkcs1_decrypt( rsa, f_rng, p_rng, + MBEDTLS_RSA_PRIVATE, olen, input, output, osize ) ); +} + +static int rsa_encrypt_wrap( void *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + mbedtls_rsa_context * rsa = (mbedtls_rsa_context *) ctx; + *olen = mbedtls_rsa_get_len( rsa ); + + if( *olen > osize ) + return( MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE ); + + return( mbedtls_rsa_pkcs1_encrypt( rsa, f_rng, p_rng, MBEDTLS_RSA_PUBLIC, + ilen, input, output ) ); +} + +static int rsa_check_pair_wrap( const void *pub, const void *prv ) +{ + return( mbedtls_rsa_check_pub_priv( (const mbedtls_rsa_context *) pub, + (const mbedtls_rsa_context *) prv ) ); +} + +static void *rsa_alloc_wrap( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_rsa_context ) ); + + if( ctx != NULL ) + mbedtls_rsa_init( (mbedtls_rsa_context *) ctx, 0, 0 ); + + return( ctx ); +} + +static void rsa_free_wrap( void *ctx ) +{ + mbedtls_rsa_free( (mbedtls_rsa_context *) ctx ); + mbedtls_free( ctx ); +} + +static void rsa_debug( const void *ctx, mbedtls_pk_debug_item *items ) +{ + items->type = MBEDTLS_PK_DEBUG_MPI; + items->name = "rsa.N"; + items->value = &( ((mbedtls_rsa_context *) ctx)->N ); + + items++; + + items->type = MBEDTLS_PK_DEBUG_MPI; + items->name = "rsa.E"; + items->value = &( ((mbedtls_rsa_context *) ctx)->E ); +} + +const mbedtls_pk_info_t mbedtls_rsa_info = { + MBEDTLS_PK_RSA, + "RSA", + rsa_get_bitlen, + rsa_can_do, + rsa_verify_wrap, + rsa_sign_wrap, +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + NULL, + NULL, +#endif + rsa_decrypt_wrap, + rsa_encrypt_wrap, + rsa_check_pair_wrap, + rsa_alloc_wrap, + rsa_free_wrap, +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + NULL, + NULL, +#endif + rsa_debug, +}; +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_ECP_C) +/* + * Generic EC key + */ +static int eckey_can_do( mbedtls_pk_type_t type ) +{ + return( type == MBEDTLS_PK_ECKEY || + type == MBEDTLS_PK_ECKEY_DH || + type == MBEDTLS_PK_ECDSA ); +} + +static size_t eckey_get_bitlen( const void *ctx ) +{ + return( ((mbedtls_ecp_keypair *) ctx)->grp.pbits ); +} + +#if defined(MBEDTLS_ECDSA_C) +/* Forward declarations */ +static int ecdsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ); + +static int ecdsa_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); + +static int eckey_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ) +{ + int ret; + mbedtls_ecdsa_context ecdsa; + + mbedtls_ecdsa_init( &ecdsa ); + + if( ( ret = mbedtls_ecdsa_from_keypair( &ecdsa, ctx ) ) == 0 ) + ret = ecdsa_verify_wrap( &ecdsa, md_alg, hash, hash_len, sig, sig_len ); + + mbedtls_ecdsa_free( &ecdsa ); + + return( ret ); +} + +static int eckey_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + mbedtls_ecdsa_context ecdsa; + + mbedtls_ecdsa_init( &ecdsa ); + + if( ( ret = mbedtls_ecdsa_from_keypair( &ecdsa, ctx ) ) == 0 ) + ret = ecdsa_sign_wrap( &ecdsa, md_alg, hash, hash_len, sig, sig_len, + f_rng, p_rng ); + + mbedtls_ecdsa_free( &ecdsa ); + + return( ret ); +} + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/* Forward declarations */ +static int ecdsa_verify_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len, + void *rs_ctx ); + +static int ecdsa_sign_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + void *rs_ctx ); + +/* + * Restart context for ECDSA operations with ECKEY context + * + * We need to store an actual ECDSA context, as we need to pass the same to + * the underlying ecdsa function, so we can't create it on the fly every time. + */ +typedef struct +{ + mbedtls_ecdsa_restart_ctx ecdsa_rs; + mbedtls_ecdsa_context ecdsa_ctx; +} eckey_restart_ctx; + +static void *eckey_rs_alloc( void ) +{ + eckey_restart_ctx *rs_ctx; + + void *ctx = mbedtls_calloc( 1, sizeof( eckey_restart_ctx ) ); + + if( ctx != NULL ) + { + rs_ctx = ctx; + mbedtls_ecdsa_restart_init( &rs_ctx->ecdsa_rs ); + mbedtls_ecdsa_init( &rs_ctx->ecdsa_ctx ); + } + + return( ctx ); +} + +static void eckey_rs_free( void *ctx ) +{ + eckey_restart_ctx *rs_ctx; + + if( ctx == NULL) + return; + + rs_ctx = ctx; + mbedtls_ecdsa_restart_free( &rs_ctx->ecdsa_rs ); + mbedtls_ecdsa_free( &rs_ctx->ecdsa_ctx ); + + mbedtls_free( ctx ); +} + +static int eckey_verify_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len, + void *rs_ctx ) +{ + int ret; + eckey_restart_ctx *rs = rs_ctx; + + /* Should never happen */ + if( rs == NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + /* set up our own sub-context if needed (that is, on first run) */ + if( rs->ecdsa_ctx.grp.pbits == 0 ) + MBEDTLS_MPI_CHK( mbedtls_ecdsa_from_keypair( &rs->ecdsa_ctx, ctx ) ); + + MBEDTLS_MPI_CHK( ecdsa_verify_rs_wrap( &rs->ecdsa_ctx, + md_alg, hash, hash_len, + sig, sig_len, &rs->ecdsa_rs ) ); + +cleanup: + return( ret ); +} + +static int eckey_sign_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + void *rs_ctx ) +{ + int ret; + eckey_restart_ctx *rs = rs_ctx; + + /* Should never happen */ + if( rs == NULL ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); + + /* set up our own sub-context if needed (that is, on first run) */ + if( rs->ecdsa_ctx.grp.pbits == 0 ) + MBEDTLS_MPI_CHK( mbedtls_ecdsa_from_keypair( &rs->ecdsa_ctx, ctx ) ); + + MBEDTLS_MPI_CHK( ecdsa_sign_rs_wrap( &rs->ecdsa_ctx, md_alg, + hash, hash_len, sig, sig_len, + f_rng, p_rng, &rs->ecdsa_rs ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_RESTARTABLE */ +#endif /* MBEDTLS_ECDSA_C */ + +static int eckey_check_pair( const void *pub, const void *prv ) +{ + return( mbedtls_ecp_check_pub_priv( (const mbedtls_ecp_keypair *) pub, + (const mbedtls_ecp_keypair *) prv ) ); +} + +static void *eckey_alloc_wrap( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_ecp_keypair ) ); + + if( ctx != NULL ) + mbedtls_ecp_keypair_init( ctx ); + + return( ctx ); +} + +static void eckey_free_wrap( void *ctx ) +{ + mbedtls_ecp_keypair_free( (mbedtls_ecp_keypair *) ctx ); + mbedtls_free( ctx ); +} + +static void eckey_debug( const void *ctx, mbedtls_pk_debug_item *items ) +{ + items->type = MBEDTLS_PK_DEBUG_ECP; + items->name = "eckey.Q"; + items->value = &( ((mbedtls_ecp_keypair *) ctx)->Q ); +} + +const mbedtls_pk_info_t mbedtls_eckey_info = { + MBEDTLS_PK_ECKEY, + "EC", + eckey_get_bitlen, + eckey_can_do, +#if defined(MBEDTLS_ECDSA_C) + eckey_verify_wrap, + eckey_sign_wrap, +#if defined(MBEDTLS_ECP_RESTARTABLE) + eckey_verify_rs_wrap, + eckey_sign_rs_wrap, +#endif +#else /* MBEDTLS_ECDSA_C */ + NULL, + NULL, +#endif /* MBEDTLS_ECDSA_C */ + NULL, + NULL, + eckey_check_pair, + eckey_alloc_wrap, + eckey_free_wrap, +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + eckey_rs_alloc, + eckey_rs_free, +#endif + eckey_debug, +}; + +/* + * EC key restricted to ECDH + */ +static int eckeydh_can_do( mbedtls_pk_type_t type ) +{ + return( type == MBEDTLS_PK_ECKEY || + type == MBEDTLS_PK_ECKEY_DH ); +} + +const mbedtls_pk_info_t mbedtls_eckeydh_info = { + MBEDTLS_PK_ECKEY_DH, + "EC_DH", + eckey_get_bitlen, /* Same underlying key structure */ + eckeydh_can_do, + NULL, + NULL, +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + NULL, + NULL, +#endif + NULL, + NULL, + eckey_check_pair, + eckey_alloc_wrap, /* Same underlying key structure */ + eckey_free_wrap, /* Same underlying key structure */ +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + NULL, + NULL, +#endif + eckey_debug, /* Same underlying key structure */ +}; +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_ECDSA_C) +static int ecdsa_can_do( mbedtls_pk_type_t type ) +{ + return( type == MBEDTLS_PK_ECDSA ); +} + +static int ecdsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len ) +{ + int ret; + ((void) md_alg); + + ret = mbedtls_ecdsa_read_signature( (mbedtls_ecdsa_context *) ctx, + hash, hash_len, sig, sig_len ); + + if( ret == MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH ) + return( MBEDTLS_ERR_PK_SIG_LEN_MISMATCH ); + + return( ret ); +} + +static int ecdsa_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + return( mbedtls_ecdsa_write_signature( (mbedtls_ecdsa_context *) ctx, + md_alg, hash, hash_len, sig, sig_len, f_rng, p_rng ) ); +} + +#if defined(MBEDTLS_ECP_RESTARTABLE) +static int ecdsa_verify_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len, + void *rs_ctx ) +{ + int ret; + ((void) md_alg); + + ret = mbedtls_ecdsa_read_signature_restartable( + (mbedtls_ecdsa_context *) ctx, + hash, hash_len, sig, sig_len, + (mbedtls_ecdsa_restart_ctx *) rs_ctx ); + + if( ret == MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH ) + return( MBEDTLS_ERR_PK_SIG_LEN_MISMATCH ); + + return( ret ); +} + +static int ecdsa_sign_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + void *rs_ctx ) +{ + return( mbedtls_ecdsa_write_signature_restartable( + (mbedtls_ecdsa_context *) ctx, + md_alg, hash, hash_len, sig, sig_len, f_rng, p_rng, + (mbedtls_ecdsa_restart_ctx *) rs_ctx ) ); + +} +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +static void *ecdsa_alloc_wrap( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_ecdsa_context ) ); + + if( ctx != NULL ) + mbedtls_ecdsa_init( (mbedtls_ecdsa_context *) ctx ); + + return( ctx ); +} + +static void ecdsa_free_wrap( void *ctx ) +{ + mbedtls_ecdsa_free( (mbedtls_ecdsa_context *) ctx ); + mbedtls_free( ctx ); +} + +#if defined(MBEDTLS_ECP_RESTARTABLE) +static void *ecdsa_rs_alloc( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_ecdsa_restart_ctx ) ); + + if( ctx != NULL ) + mbedtls_ecdsa_restart_init( ctx ); + + return( ctx ); +} + +static void ecdsa_rs_free( void *ctx ) +{ + mbedtls_ecdsa_restart_free( ctx ); + mbedtls_free( ctx ); +} +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +const mbedtls_pk_info_t mbedtls_ecdsa_info = { + MBEDTLS_PK_ECDSA, + "ECDSA", + eckey_get_bitlen, /* Compatible key structures */ + ecdsa_can_do, + ecdsa_verify_wrap, + ecdsa_sign_wrap, +#if defined(MBEDTLS_ECP_RESTARTABLE) + ecdsa_verify_rs_wrap, + ecdsa_sign_rs_wrap, +#endif + NULL, + NULL, + eckey_check_pair, /* Compatible key structures */ + ecdsa_alloc_wrap, + ecdsa_free_wrap, +#if defined(MBEDTLS_ECP_RESTARTABLE) + ecdsa_rs_alloc, + ecdsa_rs_free, +#endif + eckey_debug, /* Compatible key structures */ +}; +#endif /* MBEDTLS_ECDSA_C */ + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +/* + * Support for alternative RSA-private implementations + */ + +static int rsa_alt_can_do( mbedtls_pk_type_t type ) +{ + return( type == MBEDTLS_PK_RSA ); +} + +static size_t rsa_alt_get_bitlen( const void *ctx ) +{ + const mbedtls_rsa_alt_context *rsa_alt = (const mbedtls_rsa_alt_context *) ctx; + + return( 8 * rsa_alt->key_len_func( rsa_alt->key ) ); +} + +static int rsa_alt_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + mbedtls_rsa_alt_context *rsa_alt = (mbedtls_rsa_alt_context *) ctx; + +#if SIZE_MAX > UINT_MAX + if( UINT_MAX < hash_len ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); +#endif /* SIZE_MAX > UINT_MAX */ + + *sig_len = rsa_alt->key_len_func( rsa_alt->key ); + + return( rsa_alt->sign_func( rsa_alt->key, f_rng, p_rng, MBEDTLS_RSA_PRIVATE, + md_alg, (unsigned int) hash_len, hash, sig ) ); +} + +static int rsa_alt_decrypt_wrap( void *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + mbedtls_rsa_alt_context *rsa_alt = (mbedtls_rsa_alt_context *) ctx; + + ((void) f_rng); + ((void) p_rng); + + if( ilen != rsa_alt->key_len_func( rsa_alt->key ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + return( rsa_alt->decrypt_func( rsa_alt->key, + MBEDTLS_RSA_PRIVATE, olen, input, output, osize ) ); +} + +#if defined(MBEDTLS_RSA_C) +static int rsa_alt_check_pair( const void *pub, const void *prv ) +{ + unsigned char sig[MBEDTLS_MPI_MAX_SIZE]; + unsigned char hash[32]; + size_t sig_len = 0; + int ret; + + if( rsa_alt_get_bitlen( prv ) != rsa_get_bitlen( pub ) ) + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + + memset( hash, 0x2a, sizeof( hash ) ); + + if( ( ret = rsa_alt_sign_wrap( (void *) prv, MBEDTLS_MD_NONE, + hash, sizeof( hash ), + sig, &sig_len, NULL, NULL ) ) != 0 ) + { + return( ret ); + } + + if( rsa_verify_wrap( (void *) pub, MBEDTLS_MD_NONE, + hash, sizeof( hash ), sig, sig_len ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + return( 0 ); +} +#endif /* MBEDTLS_RSA_C */ + +static void *rsa_alt_alloc_wrap( void ) +{ + void *ctx = mbedtls_calloc( 1, sizeof( mbedtls_rsa_alt_context ) ); + + if( ctx != NULL ) + memset( ctx, 0, sizeof( mbedtls_rsa_alt_context ) ); + + return( ctx ); +} + +static void rsa_alt_free_wrap( void *ctx ) +{ + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_rsa_alt_context ) ); + mbedtls_free( ctx ); +} + +const mbedtls_pk_info_t mbedtls_rsa_alt_info = { + MBEDTLS_PK_RSA_ALT, + "RSA-alt", + rsa_alt_get_bitlen, + rsa_alt_can_do, + NULL, + rsa_alt_sign_wrap, +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + NULL, + NULL, +#endif + rsa_alt_decrypt_wrap, + NULL, +#if defined(MBEDTLS_RSA_C) + rsa_alt_check_pair, +#else + NULL, +#endif + rsa_alt_alloc_wrap, + rsa_alt_free_wrap, +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + NULL, + NULL, +#endif + NULL, +}; + +#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ + +#endif /* MBEDTLS_PK_C */ diff --git a/src/common/mbedtls/library/mbedtls_pkparse.c b/src/common/mbedtls/library/mbedtls_pkparse.c new file mode 100644 index 0000000000..878ee201a4 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_pkparse.c @@ -0,0 +1,1551 @@ +/* + * Public Key layer for parsing key files and structures + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_PK_PARSE_C) + +#include "mbedtls/pk.h" +#include "mbedtls/asn1.h" +#include "mbedtls/oid.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_RSA_C) +#include "mbedtls/rsa.h" +#endif +#if defined(MBEDTLS_ECP_C) +#include "mbedtls/ecp.h" +#endif +#if defined(MBEDTLS_ECDSA_C) +#include "mbedtls/ecdsa.h" +#endif +#if defined(MBEDTLS_PEM_PARSE_C) +#include "mbedtls/pem.h" +#endif +#if defined(MBEDTLS_PKCS5_C) +#include "mbedtls/pkcs5.h" +#endif +#if defined(MBEDTLS_PKCS12_C) +#include "mbedtls/pkcs12.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +/* Parameter validation macros based on platform_util.h */ +#define PK_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_PK_BAD_INPUT_DATA ) +#define PK_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_FS_IO) +/* + * Load all data from a file into a given buffer. + * + * The file is expected to contain either PEM or DER encoded data. + * A terminating null byte is always appended. It is included in the announced + * length only if the data looks like it is PEM encoded. + */ +int mbedtls_pk_load_file( const char *path, unsigned char **buf, size_t *n ) +{ + FILE *f; + long size; + + PK_VALIDATE_RET( path != NULL ); + PK_VALIDATE_RET( buf != NULL ); + PK_VALIDATE_RET( n != NULL ); + + if( ( f = fopen( path, "rb" ) ) == NULL ) + return( MBEDTLS_ERR_PK_FILE_IO_ERROR ); + + fseek( f, 0, SEEK_END ); + if( ( size = ftell( f ) ) == -1 ) + { + fclose( f ); + return( MBEDTLS_ERR_PK_FILE_IO_ERROR ); + } + fseek( f, 0, SEEK_SET ); + + *n = (size_t) size; + + if( *n + 1 == 0 || + ( *buf = mbedtls_calloc( 1, *n + 1 ) ) == NULL ) + { + fclose( f ); + return( MBEDTLS_ERR_PK_ALLOC_FAILED ); + } + + if( fread( *buf, 1, *n, f ) != *n ) + { + fclose( f ); + + mbedtls_platform_zeroize( *buf, *n ); + mbedtls_free( *buf ); + + return( MBEDTLS_ERR_PK_FILE_IO_ERROR ); + } + + fclose( f ); + + (*buf)[*n] = '\0'; + + if( strstr( (const char *) *buf, "-----BEGIN " ) != NULL ) + ++*n; + + return( 0 ); +} + +/* + * Load and parse a private key + */ +int mbedtls_pk_parse_keyfile( mbedtls_pk_context *ctx, + const char *path, const char *pwd ) +{ + int ret; + size_t n; + unsigned char *buf; + + PK_VALIDATE_RET( ctx != NULL ); + PK_VALIDATE_RET( path != NULL ); + + if( ( ret = mbedtls_pk_load_file( path, &buf, &n ) ) != 0 ) + return( ret ); + + if( pwd == NULL ) + ret = mbedtls_pk_parse_key( ctx, buf, n, NULL, 0 ); + else + ret = mbedtls_pk_parse_key( ctx, buf, n, + (const unsigned char *) pwd, strlen( pwd ) ); + + mbedtls_platform_zeroize( buf, n ); + mbedtls_free( buf ); + + return( ret ); +} + +/* + * Load and parse a public key + */ +int mbedtls_pk_parse_public_keyfile( mbedtls_pk_context *ctx, const char *path ) +{ + int ret; + size_t n; + unsigned char *buf; + + PK_VALIDATE_RET( ctx != NULL ); + PK_VALIDATE_RET( path != NULL ); + + if( ( ret = mbedtls_pk_load_file( path, &buf, &n ) ) != 0 ) + return( ret ); + + ret = mbedtls_pk_parse_public_key( ctx, buf, n ); + + mbedtls_platform_zeroize( buf, n ); + mbedtls_free( buf ); + + return( ret ); +} +#endif /* MBEDTLS_FS_IO */ + +#if defined(MBEDTLS_ECP_C) +/* Minimally parse an ECParameters buffer to and mbedtls_asn1_buf + * + * ECParameters ::= CHOICE { + * namedCurve OBJECT IDENTIFIER + * specifiedCurve SpecifiedECDomain -- = SEQUENCE { ... } + * -- implicitCurve NULL + * } + */ +static int pk_get_ecparams( unsigned char **p, const unsigned char *end, + mbedtls_asn1_buf *params ) +{ + int ret; + + if ( end - *p < 1 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + /* Tag may be either OID or SEQUENCE */ + params->tag = **p; + if( params->tag != MBEDTLS_ASN1_OID +#if defined(MBEDTLS_PK_PARSE_EC_EXTENDED) + && params->tag != ( MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) +#endif + ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + } + + if( ( ret = mbedtls_asn1_get_tag( p, end, ¶ms->len, params->tag ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + params->p = *p; + *p += params->len; + + if( *p != end ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +#if defined(MBEDTLS_PK_PARSE_EC_EXTENDED) +/* + * Parse a SpecifiedECDomain (SEC 1 C.2) and (mostly) fill the group with it. + * WARNING: the resulting group should only be used with + * pk_group_id_from_specified(), since its base point may not be set correctly + * if it was encoded compressed. + * + * SpecifiedECDomain ::= SEQUENCE { + * version SpecifiedECDomainVersion(ecdpVer1 | ecdpVer2 | ecdpVer3, ...), + * fieldID FieldID {{FieldTypes}}, + * curve Curve, + * base ECPoint, + * order INTEGER, + * cofactor INTEGER OPTIONAL, + * hash HashAlgorithm OPTIONAL, + * ... + * } + * + * We only support prime-field as field type, and ignore hash and cofactor. + */ +static int pk_group_from_specified( const mbedtls_asn1_buf *params, mbedtls_ecp_group *grp ) +{ + int ret; + unsigned char *p = params->p; + const unsigned char * const end = params->p + params->len; + const unsigned char *end_field, *end_curve; + size_t len; + int ver; + + /* SpecifiedECDomainVersion ::= INTEGER { 1, 2, 3 } */ + if( ( ret = mbedtls_asn1_get_int( &p, end, &ver ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + if( ver < 1 || ver > 3 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); + + /* + * FieldID { FIELD-ID:IOSet } ::= SEQUENCE { -- Finite field + * fieldType FIELD-ID.&id({IOSet}), + * parameters FIELD-ID.&Type({IOSet}{@fieldType}) + * } + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( ret ); + + end_field = p + len; + + /* + * FIELD-ID ::= TYPE-IDENTIFIER + * FieldTypes FIELD-ID ::= { + * { Prime-p IDENTIFIED BY prime-field } | + * { Characteristic-two IDENTIFIED BY characteristic-two-field } + * } + * prime-field OBJECT IDENTIFIER ::= { id-fieldType 1 } + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end_field, &len, MBEDTLS_ASN1_OID ) ) != 0 ) + return( ret ); + + if( len != MBEDTLS_OID_SIZE( MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD ) || + memcmp( p, MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD, len ) != 0 ) + { + return( MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE ); + } + + p += len; + + /* Prime-p ::= INTEGER -- Field of size p. */ + if( ( ret = mbedtls_asn1_get_mpi( &p, end_field, &grp->P ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + if( p != end_field ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + /* + * Curve ::= SEQUENCE { + * a FieldElement, + * b FieldElement, + * seed BIT STRING OPTIONAL + * -- Shall be present if used in SpecifiedECDomain + * -- with version equal to ecdpVer2 or ecdpVer3 + * } + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( ret ); + + end_curve = p + len; + + /* + * FieldElement ::= OCTET STRING + * containing an integer in the case of a prime field + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end_curve, &len, MBEDTLS_ASN1_OCTET_STRING ) ) != 0 || + ( ret = mbedtls_mpi_read_binary( &grp->A, p, len ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + p += len; + + if( ( ret = mbedtls_asn1_get_tag( &p, end_curve, &len, MBEDTLS_ASN1_OCTET_STRING ) ) != 0 || + ( ret = mbedtls_mpi_read_binary( &grp->B, p, len ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + p += len; + + /* Ignore seed BIT STRING OPTIONAL */ + if( ( ret = mbedtls_asn1_get_tag( &p, end_curve, &len, MBEDTLS_ASN1_BIT_STRING ) ) == 0 ) + p += len; + + if( p != end_curve ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + /* + * ECPoint ::= OCTET STRING + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, MBEDTLS_ASN1_OCTET_STRING ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + if( ( ret = mbedtls_ecp_point_read_binary( grp, &grp->G, + ( const unsigned char *) p, len ) ) != 0 ) + { + /* + * If we can't read the point because it's compressed, cheat by + * reading only the X coordinate and the parity bit of Y. + */ + if( ret != MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE || + ( p[0] != 0x02 && p[0] != 0x03 ) || + len != mbedtls_mpi_size( &grp->P ) + 1 || + mbedtls_mpi_read_binary( &grp->G.X, p + 1, len - 1 ) != 0 || + mbedtls_mpi_lset( &grp->G.Y, p[0] - 2 ) != 0 || + mbedtls_mpi_lset( &grp->G.Z, 1 ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); + } + } + + p += len; + + /* + * order INTEGER + */ + if( ( ret = mbedtls_asn1_get_mpi( &p, end, &grp->N ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + grp->nbits = mbedtls_mpi_bitlen( &grp->N ); + + /* + * Allow optional elements by purposefully not enforcing p == end here. + */ + + return( 0 ); +} + +/* + * Find the group id associated with an (almost filled) group as generated by + * pk_group_from_specified(), or return an error if unknown. + */ +static int pk_group_id_from_group( const mbedtls_ecp_group *grp, mbedtls_ecp_group_id *grp_id ) +{ + int ret = 0; + mbedtls_ecp_group ref; + const mbedtls_ecp_group_id *id; + + mbedtls_ecp_group_init( &ref ); + + for( id = mbedtls_ecp_grp_id_list(); *id != MBEDTLS_ECP_DP_NONE; id++ ) + { + /* Load the group associated to that id */ + mbedtls_ecp_group_free( &ref ); + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &ref, *id ) ); + + /* Compare to the group we were given, starting with easy tests */ + if( grp->pbits == ref.pbits && grp->nbits == ref.nbits && + mbedtls_mpi_cmp_mpi( &grp->P, &ref.P ) == 0 && + mbedtls_mpi_cmp_mpi( &grp->A, &ref.A ) == 0 && + mbedtls_mpi_cmp_mpi( &grp->B, &ref.B ) == 0 && + mbedtls_mpi_cmp_mpi( &grp->N, &ref.N ) == 0 && + mbedtls_mpi_cmp_mpi( &grp->G.X, &ref.G.X ) == 0 && + mbedtls_mpi_cmp_mpi( &grp->G.Z, &ref.G.Z ) == 0 && + /* For Y we may only know the parity bit, so compare only that */ + mbedtls_mpi_get_bit( &grp->G.Y, 0 ) == mbedtls_mpi_get_bit( &ref.G.Y, 0 ) ) + { + break; + } + + } + +cleanup: + mbedtls_ecp_group_free( &ref ); + + *grp_id = *id; + + if( ret == 0 && *id == MBEDTLS_ECP_DP_NONE ) + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + + return( ret ); +} + +/* + * Parse a SpecifiedECDomain (SEC 1 C.2) and find the associated group ID + */ +static int pk_group_id_from_specified( const mbedtls_asn1_buf *params, + mbedtls_ecp_group_id *grp_id ) +{ + int ret; + mbedtls_ecp_group grp; + + mbedtls_ecp_group_init( &grp ); + + if( ( ret = pk_group_from_specified( params, &grp ) ) != 0 ) + goto cleanup; + + ret = pk_group_id_from_group( &grp, grp_id ); + +cleanup: + mbedtls_ecp_group_free( &grp ); + + return( ret ); +} +#endif /* MBEDTLS_PK_PARSE_EC_EXTENDED */ + +/* + * Use EC parameters to initialise an EC group + * + * ECParameters ::= CHOICE { + * namedCurve OBJECT IDENTIFIER + * specifiedCurve SpecifiedECDomain -- = SEQUENCE { ... } + * -- implicitCurve NULL + */ +static int pk_use_ecparams( const mbedtls_asn1_buf *params, mbedtls_ecp_group *grp ) +{ + int ret; + mbedtls_ecp_group_id grp_id; + + if( params->tag == MBEDTLS_ASN1_OID ) + { + if( mbedtls_oid_get_ec_grp( params, &grp_id ) != 0 ) + return( MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE ); + } + else + { +#if defined(MBEDTLS_PK_PARSE_EC_EXTENDED) + if( ( ret = pk_group_id_from_specified( params, &grp_id ) ) != 0 ) + return( ret ); +#else + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); +#endif + } + + /* + * grp may already be initilialized; if so, make sure IDs match + */ + if( grp->id != MBEDTLS_ECP_DP_NONE && grp->id != grp_id ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); + + if( ( ret = mbedtls_ecp_group_load( grp, grp_id ) ) != 0 ) + return( ret ); + + return( 0 ); +} + +/* + * EC public key is an EC point + * + * The caller is responsible for clearing the structure upon failure if + * desired. Take care to pass along the possible ECP_FEATURE_UNAVAILABLE + * return code of mbedtls_ecp_point_read_binary() and leave p in a usable state. + */ +static int pk_get_ecpubkey( unsigned char **p, const unsigned char *end, + mbedtls_ecp_keypair *key ) +{ + int ret; + + if( ( ret = mbedtls_ecp_point_read_binary( &key->grp, &key->Q, + (const unsigned char *) *p, end - *p ) ) == 0 ) + { + ret = mbedtls_ecp_check_pubkey( &key->grp, &key->Q ); + } + + /* + * We know mbedtls_ecp_point_read_binary consumed all bytes or failed + */ + *p = (unsigned char *) end; + + return( ret ); +} +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_RSA_C) +/* + * RSAPublicKey ::= SEQUENCE { + * modulus INTEGER, -- n + * publicExponent INTEGER -- e + * } + */ +static int pk_get_rsapubkey( unsigned char **p, + const unsigned char *end, + mbedtls_rsa_context *rsa ) +{ + int ret; + size_t len; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY + ret ); + + if( *p + len != end ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + /* Import N */ + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY + ret ); + + if( ( ret = mbedtls_rsa_import_raw( rsa, *p, len, NULL, 0, NULL, 0, + NULL, 0, NULL, 0 ) ) != 0 ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY ); + + *p += len; + + /* Import E */ + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY + ret ); + + if( ( ret = mbedtls_rsa_import_raw( rsa, NULL, 0, NULL, 0, NULL, 0, + NULL, 0, *p, len ) ) != 0 ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY ); + + *p += len; + + if( mbedtls_rsa_complete( rsa ) != 0 || + mbedtls_rsa_check_pubkey( rsa ) != 0 ) + { + return( MBEDTLS_ERR_PK_INVALID_PUBKEY ); + } + + if( *p != end ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} +#endif /* MBEDTLS_RSA_C */ + +/* Get a PK algorithm identifier + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL } + */ +static int pk_get_pk_alg( unsigned char **p, + const unsigned char *end, + mbedtls_pk_type_t *pk_alg, mbedtls_asn1_buf *params ) +{ + int ret; + mbedtls_asn1_buf alg_oid; + + memset( params, 0, sizeof(mbedtls_asn1_buf) ); + + if( ( ret = mbedtls_asn1_get_alg( p, end, &alg_oid, params ) ) != 0 ) + return( MBEDTLS_ERR_PK_INVALID_ALG + ret ); + + if( mbedtls_oid_get_pk_alg( &alg_oid, pk_alg ) != 0 ) + return( MBEDTLS_ERR_PK_UNKNOWN_PK_ALG ); + + /* + * No parameters with RSA (only for EC) + */ + if( *pk_alg == MBEDTLS_PK_RSA && + ( ( params->tag != MBEDTLS_ASN1_NULL && params->tag != 0 ) || + params->len != 0 ) ) + { + return( MBEDTLS_ERR_PK_INVALID_ALG ); + } + + return( 0 ); +} + +/* + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING } + */ +int mbedtls_pk_parse_subpubkey( unsigned char **p, const unsigned char *end, + mbedtls_pk_context *pk ) +{ + int ret; + size_t len; + mbedtls_asn1_buf alg_params; + mbedtls_pk_type_t pk_alg = MBEDTLS_PK_NONE; + const mbedtls_pk_info_t *pk_info; + + PK_VALIDATE_RET( p != NULL ); + PK_VALIDATE_RET( *p != NULL ); + PK_VALIDATE_RET( end != NULL ); + PK_VALIDATE_RET( pk != NULL ); + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + end = *p + len; + + if( ( ret = pk_get_pk_alg( p, end, &pk_alg, &alg_params ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_asn1_get_bitstring_null( p, end, &len ) ) != 0 ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY + ret ); + + if( *p + len != end ) + return( MBEDTLS_ERR_PK_INVALID_PUBKEY + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + if( ( pk_info = mbedtls_pk_info_from_type( pk_alg ) ) == NULL ) + return( MBEDTLS_ERR_PK_UNKNOWN_PK_ALG ); + + if( ( ret = mbedtls_pk_setup( pk, pk_info ) ) != 0 ) + return( ret ); + +#if defined(MBEDTLS_RSA_C) + if( pk_alg == MBEDTLS_PK_RSA ) + { + ret = pk_get_rsapubkey( p, end, mbedtls_pk_rsa( *pk ) ); + } else +#endif /* MBEDTLS_RSA_C */ +#if defined(MBEDTLS_ECP_C) + if( pk_alg == MBEDTLS_PK_ECKEY_DH || pk_alg == MBEDTLS_PK_ECKEY ) + { + ret = pk_use_ecparams( &alg_params, &mbedtls_pk_ec( *pk )->grp ); + if( ret == 0 ) + ret = pk_get_ecpubkey( p, end, mbedtls_pk_ec( *pk ) ); + } else +#endif /* MBEDTLS_ECP_C */ + ret = MBEDTLS_ERR_PK_UNKNOWN_PK_ALG; + + if( ret == 0 && *p != end ) + ret = MBEDTLS_ERR_PK_INVALID_PUBKEY + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH; + + if( ret != 0 ) + mbedtls_pk_free( pk ); + + return( ret ); +} + +#if defined(MBEDTLS_RSA_C) +/* + * Wrapper around mbedtls_asn1_get_mpi() that rejects zero. + * + * The value zero is: + * - never a valid value for an RSA parameter + * - interpreted as "omitted, please reconstruct" by mbedtls_rsa_complete(). + * + * Since values can't be omitted in PKCS#1, passing a zero value to + * rsa_complete() would be incorrect, so reject zero values early. + */ +static int asn1_get_nonzero_mpi( unsigned char **p, + const unsigned char *end, + mbedtls_mpi *X ) +{ + int ret; + + ret = mbedtls_asn1_get_mpi( p, end, X ); + if( ret != 0 ) + return( ret ); + + if( mbedtls_mpi_cmp_int( X, 0 ) == 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); + + return( 0 ); +} + +/* + * Parse a PKCS#1 encoded private RSA key + */ +static int pk_parse_key_pkcs1_der( mbedtls_rsa_context *rsa, + const unsigned char *key, + size_t keylen ) +{ + int ret, version; + size_t len; + unsigned char *p, *end; + + mbedtls_mpi T; + mbedtls_mpi_init( &T ); + + p = (unsigned char *) key; + end = p + keylen; + + /* + * This function parses the RSAPrivateKey (PKCS#1) + * + * RSAPrivateKey ::= SEQUENCE { + * version Version, + * modulus INTEGER, -- n + * publicExponent INTEGER, -- e + * privateExponent INTEGER, -- d + * prime1 INTEGER, -- p + * prime2 INTEGER, -- q + * exponent1 INTEGER, -- d mod (p-1) + * exponent2 INTEGER, -- d mod (q-1) + * coefficient INTEGER, -- (inverse of q) mod p + * otherPrimeInfos OtherPrimeInfos OPTIONAL + * } + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + end = p + len; + + if( ( ret = mbedtls_asn1_get_int( &p, end, &version ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + if( version != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_VERSION ); + } + + /* Import N */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, &T, NULL, NULL, + NULL, NULL ) ) != 0 ) + goto cleanup; + + /* Import E */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, NULL, NULL, NULL, + NULL, &T ) ) != 0 ) + goto cleanup; + + /* Import D */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, NULL, NULL, NULL, + &T, NULL ) ) != 0 ) + goto cleanup; + + /* Import P */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, NULL, &T, NULL, + NULL, NULL ) ) != 0 ) + goto cleanup; + + /* Import Q */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, NULL, NULL, &T, + NULL, NULL ) ) != 0 ) + goto cleanup; + +#if !defined(MBEDTLS_RSA_NO_CRT) && !defined(MBEDTLS_RSA_ALT) + /* + * The RSA CRT parameters DP, DQ and QP are nominally redundant, in + * that they can be easily recomputed from D, P and Q. However by + * parsing them from the PKCS1 structure it is possible to avoid + * recalculating them which both reduces the overhead of loading + * RSA private keys into memory and also avoids side channels which + * can arise when computing those values, since all of D, P, and Q + * are secret. See https://eprint.iacr.org/2020/055 for a + * description of one such attack. + */ + + /* Import DP */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_mpi_copy( &rsa->DP, &T ) ) != 0 ) + goto cleanup; + + /* Import DQ */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_mpi_copy( &rsa->DQ, &T ) ) != 0 ) + goto cleanup; + + /* Import QP */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_mpi_copy( &rsa->QP, &T ) ) != 0 ) + goto cleanup; + +#else + /* Verify existance of the CRT params */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 ) + goto cleanup; +#endif + + /* rsa_complete() doesn't complete anything with the default + * implementation but is still called: + * - for the benefit of alternative implementation that may want to + * pre-compute stuff beyond what's provided (eg Montgomery factors) + * - as is also sanity-checks the key + * + * Furthermore, we also check the public part for consistency with + * mbedtls_pk_parse_pubkey(), as it includes size minima for example. + */ + if( ( ret = mbedtls_rsa_complete( rsa ) ) != 0 || + ( ret = mbedtls_rsa_check_pubkey( rsa ) ) != 0 ) + { + goto cleanup; + } + + if( p != end ) + { + ret = MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ; + } + +cleanup: + + mbedtls_mpi_free( &T ); + + if( ret != 0 ) + { + /* Wrap error code if it's coming from a lower level */ + if( ( ret & 0xff80 ) == 0 ) + ret = MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret; + else + ret = MBEDTLS_ERR_PK_KEY_INVALID_FORMAT; + + mbedtls_rsa_free( rsa ); + } + + return( ret ); +} +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_ECP_C) +/* + * Parse a SEC1 encoded private EC key + */ +static int pk_parse_key_sec1_der( mbedtls_ecp_keypair *eck, + const unsigned char *key, + size_t keylen ) +{ + int ret; + int version, pubkey_done; + size_t len; + mbedtls_asn1_buf params; + unsigned char *p = (unsigned char *) key; + unsigned char *end = p + keylen; + unsigned char *end2; + + /* + * RFC 5915, or SEC1 Appendix C.4 + * + * ECPrivateKey ::= SEQUENCE { + * version INTEGER { ecPrivkeyVer1(1) } (ecPrivkeyVer1), + * privateKey OCTET STRING, + * parameters [0] ECParameters {{ NamedCurve }} OPTIONAL, + * publicKey [1] BIT STRING OPTIONAL + * } + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + end = p + len; + + if( ( ret = mbedtls_asn1_get_int( &p, end, &version ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + if( version != 1 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_VERSION ); + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, MBEDTLS_ASN1_OCTET_STRING ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + if( ( ret = mbedtls_mpi_read_binary( &eck->d, p, len ) ) != 0 ) + { + mbedtls_ecp_keypair_free( eck ); + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + p += len; + + pubkey_done = 0; + if( p != end ) + { + /* + * Is 'parameters' present? + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | 0 ) ) == 0 ) + { + if( ( ret = pk_get_ecparams( &p, p + len, ¶ms) ) != 0 || + ( ret = pk_use_ecparams( ¶ms, &eck->grp ) ) != 0 ) + { + mbedtls_ecp_keypair_free( eck ); + return( ret ); + } + } + else if( ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + { + mbedtls_ecp_keypair_free( eck ); + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + } + + if( p != end ) + { + /* + * Is 'publickey' present? If not, or if we can't read it (eg because it + * is compressed), create it from the private key. + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | 1 ) ) == 0 ) + { + end2 = p + len; + + if( ( ret = mbedtls_asn1_get_bitstring_null( &p, end2, &len ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + if( p + len != end2 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + if( ( ret = pk_get_ecpubkey( &p, end2, eck ) ) == 0 ) + pubkey_done = 1; + else + { + /* + * The only acceptable failure mode of pk_get_ecpubkey() above + * is if the point format is not recognized. + */ + if( ret != MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); + } + } + else if( ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + { + mbedtls_ecp_keypair_free( eck ); + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + } + + if( ! pubkey_done && + ( ret = mbedtls_ecp_mul( &eck->grp, &eck->Q, &eck->d, &eck->grp.G, + NULL, NULL ) ) != 0 ) + { + mbedtls_ecp_keypair_free( eck ); + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + if( ( ret = mbedtls_ecp_check_privkey( &eck->grp, &eck->d ) ) != 0 ) + { + mbedtls_ecp_keypair_free( eck ); + return( ret ); + } + + return( 0 ); +} +#endif /* MBEDTLS_ECP_C */ + +/* + * Parse an unencrypted PKCS#8 encoded private key + * + * Notes: + * + * - This function does not own the key buffer. It is the + * responsibility of the caller to take care of zeroizing + * and freeing it after use. + * + * - The function is responsible for freeing the provided + * PK context on failure. + * + */ +static int pk_parse_key_pkcs8_unencrypted_der( + mbedtls_pk_context *pk, + const unsigned char* key, + size_t keylen ) +{ + int ret, version; + size_t len; + mbedtls_asn1_buf params; + unsigned char *p = (unsigned char *) key; + unsigned char *end = p + keylen; + mbedtls_pk_type_t pk_alg = MBEDTLS_PK_NONE; + const mbedtls_pk_info_t *pk_info; + + /* + * This function parses the PrivateKeyInfo object (PKCS#8 v1.2 = RFC 5208) + * + * PrivateKeyInfo ::= SEQUENCE { + * version Version, + * privateKeyAlgorithm PrivateKeyAlgorithmIdentifier, + * privateKey PrivateKey, + * attributes [0] IMPLICIT Attributes OPTIONAL } + * + * Version ::= INTEGER + * PrivateKeyAlgorithmIdentifier ::= AlgorithmIdentifier + * PrivateKey ::= OCTET STRING + * + * The PrivateKey OCTET STRING is a SEC1 ECPrivateKey + */ + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + end = p + len; + + if( ( ret = mbedtls_asn1_get_int( &p, end, &version ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + if( version != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_VERSION + ret ); + + if( ( ret = pk_get_pk_alg( &p, end, &pk_alg, ¶ms ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, MBEDTLS_ASN1_OCTET_STRING ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + if( len < 1 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + if( ( pk_info = mbedtls_pk_info_from_type( pk_alg ) ) == NULL ) + return( MBEDTLS_ERR_PK_UNKNOWN_PK_ALG ); + + if( ( ret = mbedtls_pk_setup( pk, pk_info ) ) != 0 ) + return( ret ); + +#if defined(MBEDTLS_RSA_C) + if( pk_alg == MBEDTLS_PK_RSA ) + { + if( ( ret = pk_parse_key_pkcs1_der( mbedtls_pk_rsa( *pk ), p, len ) ) != 0 ) + { + mbedtls_pk_free( pk ); + return( ret ); + } + } else +#endif /* MBEDTLS_RSA_C */ +#if defined(MBEDTLS_ECP_C) + if( pk_alg == MBEDTLS_PK_ECKEY || pk_alg == MBEDTLS_PK_ECKEY_DH ) + { + if( ( ret = pk_use_ecparams( ¶ms, &mbedtls_pk_ec( *pk )->grp ) ) != 0 || + ( ret = pk_parse_key_sec1_der( mbedtls_pk_ec( *pk ), p, len ) ) != 0 ) + { + mbedtls_pk_free( pk ); + return( ret ); + } + } else +#endif /* MBEDTLS_ECP_C */ + return( MBEDTLS_ERR_PK_UNKNOWN_PK_ALG ); + + return( 0 ); +} + +/* + * Parse an encrypted PKCS#8 encoded private key + * + * To save space, the decryption happens in-place on the given key buffer. + * Also, while this function may modify the keybuffer, it doesn't own it, + * and instead it is the responsibility of the caller to zeroize and properly + * free it after use. + * + */ +#if defined(MBEDTLS_PKCS12_C) || defined(MBEDTLS_PKCS5_C) +static int pk_parse_key_pkcs8_encrypted_der( + mbedtls_pk_context *pk, + unsigned char *key, size_t keylen, + const unsigned char *pwd, size_t pwdlen ) +{ + int ret, decrypted = 0; + size_t len; + unsigned char *buf; + unsigned char *p, *end; + mbedtls_asn1_buf pbe_alg_oid, pbe_params; +#if defined(MBEDTLS_PKCS12_C) + mbedtls_cipher_type_t cipher_alg; + mbedtls_md_type_t md_alg; +#endif + + p = key; + end = p + keylen; + + if( pwdlen == 0 ) + return( MBEDTLS_ERR_PK_PASSWORD_REQUIRED ); + + /* + * This function parses the EncryptedPrivateKeyInfo object (PKCS#8) + * + * EncryptedPrivateKeyInfo ::= SEQUENCE { + * encryptionAlgorithm EncryptionAlgorithmIdentifier, + * encryptedData EncryptedData + * } + * + * EncryptionAlgorithmIdentifier ::= AlgorithmIdentifier + * + * EncryptedData ::= OCTET STRING + * + * The EncryptedData OCTET STRING is a PKCS#8 PrivateKeyInfo + * + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + } + + end = p + len; + + if( ( ret = mbedtls_asn1_get_alg( &p, end, &pbe_alg_oid, &pbe_params ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, MBEDTLS_ASN1_OCTET_STRING ) ) != 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + ret ); + + buf = p; + + /* + * Decrypt EncryptedData with appropriate PBE + */ +#if defined(MBEDTLS_PKCS12_C) + if( mbedtls_oid_get_pkcs12_pbe_alg( &pbe_alg_oid, &md_alg, &cipher_alg ) == 0 ) + { + if( ( ret = mbedtls_pkcs12_pbe( &pbe_params, MBEDTLS_PKCS12_PBE_DECRYPT, + cipher_alg, md_alg, + pwd, pwdlen, p, len, buf ) ) != 0 ) + { + if( ret == MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH ) + return( MBEDTLS_ERR_PK_PASSWORD_MISMATCH ); + + return( ret ); + } + + decrypted = 1; + } + else if( MBEDTLS_OID_CMP( MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_128, &pbe_alg_oid ) == 0 ) + { + if( ( ret = mbedtls_pkcs12_pbe_sha1_rc4_128( &pbe_params, + MBEDTLS_PKCS12_PBE_DECRYPT, + pwd, pwdlen, + p, len, buf ) ) != 0 ) + { + return( ret ); + } + + // Best guess for password mismatch when using RC4. If first tag is + // not MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE + // + if( *buf != ( MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) + return( MBEDTLS_ERR_PK_PASSWORD_MISMATCH ); + + decrypted = 1; + } + else +#endif /* MBEDTLS_PKCS12_C */ +#if defined(MBEDTLS_PKCS5_C) + if( MBEDTLS_OID_CMP( MBEDTLS_OID_PKCS5_PBES2, &pbe_alg_oid ) == 0 ) + { + if( ( ret = mbedtls_pkcs5_pbes2( &pbe_params, MBEDTLS_PKCS5_DECRYPT, pwd, pwdlen, + p, len, buf ) ) != 0 ) + { + if( ret == MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH ) + return( MBEDTLS_ERR_PK_PASSWORD_MISMATCH ); + + return( ret ); + } + + decrypted = 1; + } + else +#endif /* MBEDTLS_PKCS5_C */ + { + ((void) pwd); + } + + if( decrypted == 0 ) + return( MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE ); + + return( pk_parse_key_pkcs8_unencrypted_der( pk, buf, len ) ); +} +#endif /* MBEDTLS_PKCS12_C || MBEDTLS_PKCS5_C */ + +/* + * Parse a private key + */ +int mbedtls_pk_parse_key( mbedtls_pk_context *pk, + const unsigned char *key, size_t keylen, + const unsigned char *pwd, size_t pwdlen ) +{ + int ret; + const mbedtls_pk_info_t *pk_info; +#if defined(MBEDTLS_PEM_PARSE_C) + size_t len; + mbedtls_pem_context pem; +#endif + + PK_VALIDATE_RET( pk != NULL ); + if( keylen == 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); + PK_VALIDATE_RET( key != NULL ); + +#if defined(MBEDTLS_PEM_PARSE_C) + mbedtls_pem_init( &pem ); + +#if defined(MBEDTLS_RSA_C) + /* Avoid calling mbedtls_pem_read_buffer() on non-null-terminated string */ + if( key[keylen - 1] != '\0' ) + ret = MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT; + else + ret = mbedtls_pem_read_buffer( &pem, + "-----BEGIN RSA PRIVATE KEY-----", + "-----END RSA PRIVATE KEY-----", + key, pwd, pwdlen, &len ); + + if( ret == 0 ) + { + pk_info = mbedtls_pk_info_from_type( MBEDTLS_PK_RSA ); + if( ( ret = mbedtls_pk_setup( pk, pk_info ) ) != 0 || + ( ret = pk_parse_key_pkcs1_der( mbedtls_pk_rsa( *pk ), + pem.buf, pem.buflen ) ) != 0 ) + { + mbedtls_pk_free( pk ); + } + + mbedtls_pem_free( &pem ); + return( ret ); + } + else if( ret == MBEDTLS_ERR_PEM_PASSWORD_MISMATCH ) + return( MBEDTLS_ERR_PK_PASSWORD_MISMATCH ); + else if( ret == MBEDTLS_ERR_PEM_PASSWORD_REQUIRED ) + return( MBEDTLS_ERR_PK_PASSWORD_REQUIRED ); + else if( ret != MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ) + return( ret ); +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_ECP_C) + /* Avoid calling mbedtls_pem_read_buffer() on non-null-terminated string */ + if( key[keylen - 1] != '\0' ) + ret = MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT; + else + ret = mbedtls_pem_read_buffer( &pem, + "-----BEGIN EC PRIVATE KEY-----", + "-----END EC PRIVATE KEY-----", + key, pwd, pwdlen, &len ); + if( ret == 0 ) + { + pk_info = mbedtls_pk_info_from_type( MBEDTLS_PK_ECKEY ); + + if( ( ret = mbedtls_pk_setup( pk, pk_info ) ) != 0 || + ( ret = pk_parse_key_sec1_der( mbedtls_pk_ec( *pk ), + pem.buf, pem.buflen ) ) != 0 ) + { + mbedtls_pk_free( pk ); + } + + mbedtls_pem_free( &pem ); + return( ret ); + } + else if( ret == MBEDTLS_ERR_PEM_PASSWORD_MISMATCH ) + return( MBEDTLS_ERR_PK_PASSWORD_MISMATCH ); + else if( ret == MBEDTLS_ERR_PEM_PASSWORD_REQUIRED ) + return( MBEDTLS_ERR_PK_PASSWORD_REQUIRED ); + else if( ret != MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ) + return( ret ); +#endif /* MBEDTLS_ECP_C */ + + /* Avoid calling mbedtls_pem_read_buffer() on non-null-terminated string */ + if( key[keylen - 1] != '\0' ) + ret = MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT; + else + ret = mbedtls_pem_read_buffer( &pem, + "-----BEGIN PRIVATE KEY-----", + "-----END PRIVATE KEY-----", + key, NULL, 0, &len ); + if( ret == 0 ) + { + if( ( ret = pk_parse_key_pkcs8_unencrypted_der( pk, + pem.buf, pem.buflen ) ) != 0 ) + { + mbedtls_pk_free( pk ); + } + + mbedtls_pem_free( &pem ); + return( ret ); + } + else if( ret != MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ) + return( ret ); + +#if defined(MBEDTLS_PKCS12_C) || defined(MBEDTLS_PKCS5_C) + /* Avoid calling mbedtls_pem_read_buffer() on non-null-terminated string */ + if( key[keylen - 1] != '\0' ) + ret = MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT; + else + ret = mbedtls_pem_read_buffer( &pem, + "-----BEGIN ENCRYPTED PRIVATE KEY-----", + "-----END ENCRYPTED PRIVATE KEY-----", + key, NULL, 0, &len ); + if( ret == 0 ) + { + if( ( ret = pk_parse_key_pkcs8_encrypted_der( pk, + pem.buf, pem.buflen, + pwd, pwdlen ) ) != 0 ) + { + mbedtls_pk_free( pk ); + } + + mbedtls_pem_free( &pem ); + return( ret ); + } + else if( ret != MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ) + return( ret ); +#endif /* MBEDTLS_PKCS12_C || MBEDTLS_PKCS5_C */ +#else + ((void) pwd); + ((void) pwdlen); +#endif /* MBEDTLS_PEM_PARSE_C */ + + /* + * At this point we only know it's not a PEM formatted key. Could be any + * of the known DER encoded private key formats + * + * We try the different DER format parsers to see if one passes without + * error + */ +#if defined(MBEDTLS_PKCS12_C) || defined(MBEDTLS_PKCS5_C) + { + unsigned char *key_copy; + + if( ( key_copy = mbedtls_calloc( 1, keylen ) ) == NULL ) + return( MBEDTLS_ERR_PK_ALLOC_FAILED ); + + memcpy( key_copy, key, keylen ); + + ret = pk_parse_key_pkcs8_encrypted_der( pk, key_copy, keylen, + pwd, pwdlen ); + + mbedtls_platform_zeroize( key_copy, keylen ); + mbedtls_free( key_copy ); + } + + if( ret == 0 ) + return( 0 ); + + mbedtls_pk_free( pk ); + mbedtls_pk_init( pk ); + + if( ret == MBEDTLS_ERR_PK_PASSWORD_MISMATCH ) + { + return( ret ); + } +#endif /* MBEDTLS_PKCS12_C || MBEDTLS_PKCS5_C */ + + if( ( ret = pk_parse_key_pkcs8_unencrypted_der( pk, key, keylen ) ) == 0 ) + return( 0 ); + + mbedtls_pk_free( pk ); + mbedtls_pk_init( pk ); + +#if defined(MBEDTLS_RSA_C) + + pk_info = mbedtls_pk_info_from_type( MBEDTLS_PK_RSA ); + if( mbedtls_pk_setup( pk, pk_info ) == 0 && + pk_parse_key_pkcs1_der( mbedtls_pk_rsa( *pk ), key, keylen ) == 0 ) + { + return( 0 ); + } + + mbedtls_pk_free( pk ); + mbedtls_pk_init( pk ); +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_ECP_C) + pk_info = mbedtls_pk_info_from_type( MBEDTLS_PK_ECKEY ); + if( mbedtls_pk_setup( pk, pk_info ) == 0 && + pk_parse_key_sec1_der( mbedtls_pk_ec( *pk ), + key, keylen ) == 0 ) + { + return( 0 ); + } + mbedtls_pk_free( pk ); +#endif /* MBEDTLS_ECP_C */ + + /* If MBEDTLS_RSA_C is defined but MBEDTLS_ECP_C isn't, + * it is ok to leave the PK context initialized but not + * freed: It is the caller's responsibility to call pk_init() + * before calling this function, and to call pk_free() + * when it fails. If MBEDTLS_ECP_C is defined but MBEDTLS_RSA_C + * isn't, this leads to mbedtls_pk_free() being called + * twice, once here and once by the caller, but this is + * also ok and in line with the mbedtls_pk_free() calls + * on failed PEM parsing attempts. */ + + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); +} + +/* + * Parse a public key + */ +int mbedtls_pk_parse_public_key( mbedtls_pk_context *ctx, + const unsigned char *key, size_t keylen ) +{ + int ret; + unsigned char *p; +#if defined(MBEDTLS_RSA_C) + const mbedtls_pk_info_t *pk_info; +#endif +#if defined(MBEDTLS_PEM_PARSE_C) + size_t len; + mbedtls_pem_context pem; +#endif + + PK_VALIDATE_RET( ctx != NULL ); + if( keylen == 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); + PK_VALIDATE_RET( key != NULL || keylen == 0 ); + +#if defined(MBEDTLS_PEM_PARSE_C) + mbedtls_pem_init( &pem ); +#if defined(MBEDTLS_RSA_C) + /* Avoid calling mbedtls_pem_read_buffer() on non-null-terminated string */ + if( key[keylen - 1] != '\0' ) + ret = MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT; + else + ret = mbedtls_pem_read_buffer( &pem, + "-----BEGIN RSA PUBLIC KEY-----", + "-----END RSA PUBLIC KEY-----", + key, NULL, 0, &len ); + + if( ret == 0 ) + { + p = pem.buf; + if( ( pk_info = mbedtls_pk_info_from_type( MBEDTLS_PK_RSA ) ) == NULL ) + return( MBEDTLS_ERR_PK_UNKNOWN_PK_ALG ); + + if( ( ret = mbedtls_pk_setup( ctx, pk_info ) ) != 0 ) + return( ret ); + + if ( ( ret = pk_get_rsapubkey( &p, p + pem.buflen, mbedtls_pk_rsa( *ctx ) ) ) != 0 ) + mbedtls_pk_free( ctx ); + + mbedtls_pem_free( &pem ); + return( ret ); + } + else if( ret != MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ) + { + mbedtls_pem_free( &pem ); + return( ret ); + } +#endif /* MBEDTLS_RSA_C */ + + /* Avoid calling mbedtls_pem_read_buffer() on non-null-terminated string */ + if( key[keylen - 1] != '\0' ) + ret = MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT; + else + ret = mbedtls_pem_read_buffer( &pem, + "-----BEGIN PUBLIC KEY-----", + "-----END PUBLIC KEY-----", + key, NULL, 0, &len ); + + if( ret == 0 ) + { + /* + * Was PEM encoded + */ + p = pem.buf; + + ret = mbedtls_pk_parse_subpubkey( &p, p + pem.buflen, ctx ); + mbedtls_pem_free( &pem ); + return( ret ); + } + else if( ret != MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ) + { + mbedtls_pem_free( &pem ); + return( ret ); + } + mbedtls_pem_free( &pem ); +#endif /* MBEDTLS_PEM_PARSE_C */ + +#if defined(MBEDTLS_RSA_C) + if( ( pk_info = mbedtls_pk_info_from_type( MBEDTLS_PK_RSA ) ) == NULL ) + return( MBEDTLS_ERR_PK_UNKNOWN_PK_ALG ); + + if( ( ret = mbedtls_pk_setup( ctx, pk_info ) ) != 0 ) + return( ret ); + + p = (unsigned char *)key; + ret = pk_get_rsapubkey( &p, p + keylen, mbedtls_pk_rsa( *ctx ) ); + if( ret == 0 ) + { + return( ret ); + } + mbedtls_pk_free( ctx ); + if( ret != ( MBEDTLS_ERR_PK_INVALID_PUBKEY + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) ) + { + return( ret ); + } +#endif /* MBEDTLS_RSA_C */ + p = (unsigned char *) key; + + ret = mbedtls_pk_parse_subpubkey( &p, p + keylen, ctx ); + + return( ret ); +} + +#endif /* MBEDTLS_PK_PARSE_C */ diff --git a/src/common/mbedtls/library/mbedtls_sha256.c b/src/common/mbedtls/library/mbedtls_sha256.c new file mode 100644 index 0000000000..7772606b27 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_sha256.c @@ -0,0 +1,626 @@ +/* + * FIPS-180-2 compliant SHA-256 implementation + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +/* + * The SHA-256 Secure Hash Standard was published by NIST in 2002. + * + * https://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SHA256_C) + +#include "mbedtls/sha256.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_SELF_TEST) +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST */ + +#define SHA256_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_SHA256_BAD_INPUT_DATA ) +#define SHA256_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if !defined(MBEDTLS_SHA256_ALT) + +/* + * 32-bit integer manipulation macros (big endian) + */ +#ifndef GET_UINT32_BE +#define GET_UINT32_BE(n,b,i) \ +do { \ + (n) = ( (uint32_t) (b)[(i) ] << 24 ) \ + | ( (uint32_t) (b)[(i) + 1] << 16 ) \ + | ( (uint32_t) (b)[(i) + 2] << 8 ) \ + | ( (uint32_t) (b)[(i) + 3] ); \ +} while( 0 ) +#endif + +#ifndef PUT_UINT32_BE +#define PUT_UINT32_BE(n,b,i) \ +do { \ + (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ +} while( 0 ) +#endif + +void mbedtls_sha256_init( mbedtls_sha256_context *ctx ) +{ + SHA256_VALIDATE( ctx != NULL ); + + memset( ctx, 0, sizeof( mbedtls_sha256_context ) ); +} + +void mbedtls_sha256_free( mbedtls_sha256_context *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_sha256_context ) ); +} + +void mbedtls_sha256_clone( mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src ) +{ + SHA256_VALIDATE( dst != NULL ); + SHA256_VALIDATE( src != NULL ); + + *dst = *src; +} + +/* + * SHA-256 context setup + */ +int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ) +{ + SHA256_VALIDATE_RET( ctx != NULL ); + SHA256_VALIDATE_RET( is224 == 0 || is224 == 1 ); + + ctx->total[0] = 0; + ctx->total[1] = 0; + + if( is224 == 0 ) + { + /* SHA-256 */ + ctx->state[0] = 0x6A09E667; + ctx->state[1] = 0xBB67AE85; + ctx->state[2] = 0x3C6EF372; + ctx->state[3] = 0xA54FF53A; + ctx->state[4] = 0x510E527F; + ctx->state[5] = 0x9B05688C; + ctx->state[6] = 0x1F83D9AB; + ctx->state[7] = 0x5BE0CD19; + } + else + { + /* SHA-224 */ + ctx->state[0] = 0xC1059ED8; + ctx->state[1] = 0x367CD507; + ctx->state[2] = 0x3070DD17; + ctx->state[3] = 0xF70E5939; + ctx->state[4] = 0xFFC00B31; + ctx->state[5] = 0x68581511; + ctx->state[6] = 0x64F98FA7; + ctx->state[7] = 0xBEFA4FA4; + } + + ctx->is224 = is224; + + return( 0 ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, + int is224 ) +{ + mbedtls_sha256_starts_ret( ctx, is224 ); +} +#endif + +#if !defined(MBEDTLS_SHA256_PROCESS_ALT) +static const uint32_t K[] = +{ + 0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5, + 0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5, + 0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3, + 0x72BE5D74, 0x80DEB1FE, 0x9BDC06A7, 0xC19BF174, + 0xE49B69C1, 0xEFBE4786, 0x0FC19DC6, 0x240CA1CC, + 0x2DE92C6F, 0x4A7484AA, 0x5CB0A9DC, 0x76F988DA, + 0x983E5152, 0xA831C66D, 0xB00327C8, 0xBF597FC7, + 0xC6E00BF3, 0xD5A79147, 0x06CA6351, 0x14292967, + 0x27B70A85, 0x2E1B2138, 0x4D2C6DFC, 0x53380D13, + 0x650A7354, 0x766A0ABB, 0x81C2C92E, 0x92722C85, + 0xA2BFE8A1, 0xA81A664B, 0xC24B8B70, 0xC76C51A3, + 0xD192E819, 0xD6990624, 0xF40E3585, 0x106AA070, + 0x19A4C116, 0x1E376C08, 0x2748774C, 0x34B0BCB5, + 0x391C0CB3, 0x4ED8AA4A, 0x5B9CCA4F, 0x682E6FF3, + 0x748F82EE, 0x78A5636F, 0x84C87814, 0x8CC70208, + 0x90BEFFFA, 0xA4506CEB, 0xBEF9A3F7, 0xC67178F2, +}; + +#define SHR(x,n) (((x) & 0xFFFFFFFF) >> (n)) +#define ROTR(x,n) (SHR(x,n) | ((x) << (32 - (n)))) + +#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3)) +#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10)) + +#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22)) +#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25)) + +#define F0(x,y,z) (((x) & (y)) | ((z) & ((x) | (y)))) +#define F1(x,y,z) ((z) ^ ((x) & ((y) ^ (z)))) + +#define R(t) \ + ( \ + local.W[t] = S1(local.W[(t) - 2]) + local.W[(t) - 7] + \ + S0(local.W[(t) - 15]) + local.W[(t) - 16] \ + ) + +#define P(a,b,c,d,e,f,g,h,x,K) \ + do \ + { \ + local.temp1 = (h) + S3(e) + F1((e),(f),(g)) + (K) + (x); \ + local.temp2 = S2(a) + F0((a),(b),(c)); \ + (d) += local.temp1; (h) = local.temp1 + local.temp2; \ + } while( 0 ) + +int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, + const unsigned char data[64] ) +{ + struct + { + uint32_t temp1, temp2, W[64]; + uint32_t A[8]; + } local; + + unsigned int i; + + SHA256_VALIDATE_RET( ctx != NULL ); + SHA256_VALIDATE_RET( (const unsigned char *)data != NULL ); + + for( i = 0; i < 8; i++ ) + local.A[i] = ctx->state[i]; + +#if defined(MBEDTLS_SHA256_SMALLER) + for( i = 0; i < 64; i++ ) + { + if( i < 16 ) + GET_UINT32_BE( local.W[i], data, 4 * i ); + else + R( i ); + + P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], local.W[i], K[i] ); + + local.temp1 = local.A[7]; local.A[7] = local.A[6]; + local.A[6] = local.A[5]; local.A[5] = local.A[4]; + local.A[4] = local.A[3]; local.A[3] = local.A[2]; + local.A[2] = local.A[1]; local.A[1] = local.A[0]; + local.A[0] = local.temp1; + } +#else /* MBEDTLS_SHA256_SMALLER */ + for( i = 0; i < 16; i++ ) + GET_UINT32_BE( local.W[i], data, 4 * i ); + + for( i = 0; i < 16; i += 8 ) + { + P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], local.W[i+0], K[i+0] ); + P( local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], + local.A[4], local.A[5], local.A[6], local.W[i+1], K[i+1] ); + P( local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], + local.A[3], local.A[4], local.A[5], local.W[i+2], K[i+2] ); + P( local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], + local.A[2], local.A[3], local.A[4], local.W[i+3], K[i+3] ); + P( local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], + local.A[1], local.A[2], local.A[3], local.W[i+4], K[i+4] ); + P( local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], + local.A[0], local.A[1], local.A[2], local.W[i+5], K[i+5] ); + P( local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], + local.A[7], local.A[0], local.A[1], local.W[i+6], K[i+6] ); + P( local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], + local.A[6], local.A[7], local.A[0], local.W[i+7], K[i+7] ); + } + + for( i = 16; i < 64; i += 8 ) + { + P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], R(i+0), K[i+0] ); + P( local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], + local.A[4], local.A[5], local.A[6], R(i+1), K[i+1] ); + P( local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], + local.A[3], local.A[4], local.A[5], R(i+2), K[i+2] ); + P( local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], + local.A[2], local.A[3], local.A[4], R(i+3), K[i+3] ); + P( local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], + local.A[1], local.A[2], local.A[3], R(i+4), K[i+4] ); + P( local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], + local.A[0], local.A[1], local.A[2], R(i+5), K[i+5] ); + P( local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], + local.A[7], local.A[0], local.A[1], R(i+6), K[i+6] ); + P( local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], + local.A[6], local.A[7], local.A[0], R(i+7), K[i+7] ); + } +#endif /* MBEDTLS_SHA256_SMALLER */ + + for( i = 0; i < 8; i++ ) + ctx->state[i] += local.A[i]; + + /* Zeroise buffers and variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &local, sizeof( local ) ); + + return( 0 ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256_process( mbedtls_sha256_context *ctx, + const unsigned char data[64] ) +{ + mbedtls_internal_sha256_process( ctx, data ); +} +#endif +#endif /* !MBEDTLS_SHA256_PROCESS_ALT */ + +/* + * SHA-256 process buffer + */ +int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + int ret; + size_t fill; + uint32_t left; + + SHA256_VALIDATE_RET( ctx != NULL ); + SHA256_VALIDATE_RET( ilen == 0 || input != NULL ); + + if( ilen == 0 ) + return( 0 ); + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += (uint32_t) ilen; + ctx->total[0] &= 0xFFFFFFFF; + + if( ctx->total[0] < (uint32_t) ilen ) + ctx->total[1]++; + + if( left && ilen >= fill ) + { + memcpy( (void *) (ctx->buffer + left), input, fill ); + + if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 ) + return( ret ); + + input += fill; + ilen -= fill; + left = 0; + } + + while( ilen >= 64 ) + { + if( ( ret = mbedtls_internal_sha256_process( ctx, input ) ) != 0 ) + return( ret ); + + input += 64; + ilen -= 64; + } + + if( ilen > 0 ) + memcpy( (void *) (ctx->buffer + left), input, ilen ); + + return( 0 ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256_update( mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + mbedtls_sha256_update_ret( ctx, input, ilen ); +} +#endif + +/* + * SHA-256 final digest + */ +int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, + unsigned char output[32] ) +{ + int ret; + uint32_t used; + uint32_t high, low; + + SHA256_VALIDATE_RET( ctx != NULL ); + SHA256_VALIDATE_RET( (unsigned char *)output != NULL ); + + /* + * Add padding: 0x80 then 0x00 until 8 bytes remain for the length + */ + used = ctx->total[0] & 0x3F; + + ctx->buffer[used++] = 0x80; + + if( used <= 56 ) + { + /* Enough room for padding + length in current block */ + memset( ctx->buffer + used, 0, 56 - used ); + } + else + { + /* We'll need an extra block */ + memset( ctx->buffer + used, 0, 64 - used ); + + if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 ) + return( ret ); + + memset( ctx->buffer, 0, 56 ); + } + + /* + * Add message length + */ + high = ( ctx->total[0] >> 29 ) + | ( ctx->total[1] << 3 ); + low = ( ctx->total[0] << 3 ); + + PUT_UINT32_BE( high, ctx->buffer, 56 ); + PUT_UINT32_BE( low, ctx->buffer, 60 ); + + if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 ) + return( ret ); + + /* + * Output final state + */ + PUT_UINT32_BE( ctx->state[0], output, 0 ); + PUT_UINT32_BE( ctx->state[1], output, 4 ); + PUT_UINT32_BE( ctx->state[2], output, 8 ); + PUT_UINT32_BE( ctx->state[3], output, 12 ); + PUT_UINT32_BE( ctx->state[4], output, 16 ); + PUT_UINT32_BE( ctx->state[5], output, 20 ); + PUT_UINT32_BE( ctx->state[6], output, 24 ); + + if( ctx->is224 == 0 ) + PUT_UINT32_BE( ctx->state[7], output, 28 ); + + return( 0 ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, + unsigned char output[32] ) +{ + mbedtls_sha256_finish_ret( ctx, output ); +} +#endif + +#endif /* !MBEDTLS_SHA256_ALT */ + +/* + * output = SHA-256( input buffer ) + */ +int mbedtls_sha256_ret( const unsigned char *input, + size_t ilen, + unsigned char output[32], + int is224 ) +{ + int ret; + mbedtls_sha256_context ctx; + + SHA256_VALIDATE_RET( is224 == 0 || is224 == 1 ); + SHA256_VALIDATE_RET( ilen == 0 || input != NULL ); + SHA256_VALIDATE_RET( (unsigned char *)output != NULL ); + + mbedtls_sha256_init( &ctx ); + + if( ( ret = mbedtls_sha256_starts_ret( &ctx, is224 ) ) != 0 ) + goto exit; + + if( ( ret = mbedtls_sha256_update_ret( &ctx, input, ilen ) ) != 0 ) + goto exit; + + if( ( ret = mbedtls_sha256_finish_ret( &ctx, output ) ) != 0 ) + goto exit; + +exit: + mbedtls_sha256_free( &ctx ); + + return( ret ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha256( const unsigned char *input, + size_t ilen, + unsigned char output[32], + int is224 ) +{ + mbedtls_sha256_ret( input, ilen, output, is224 ); +} +#endif + +#if defined(MBEDTLS_SELF_TEST) +/* + * FIPS-180-2 test vectors + */ +static const unsigned char sha256_test_buf[3][57] = +{ + { "abc" }, + { "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" }, + { "" } +}; + +static const size_t sha256_test_buflen[3] = +{ + 3, 56, 1000 +}; + +static const unsigned char sha256_test_sum[6][32] = +{ + /* + * SHA-224 test vectors + */ + { 0x23, 0x09, 0x7D, 0x22, 0x34, 0x05, 0xD8, 0x22, + 0x86, 0x42, 0xA4, 0x77, 0xBD, 0xA2, 0x55, 0xB3, + 0x2A, 0xAD, 0xBC, 0xE4, 0xBD, 0xA0, 0xB3, 0xF7, + 0xE3, 0x6C, 0x9D, 0xA7 }, + { 0x75, 0x38, 0x8B, 0x16, 0x51, 0x27, 0x76, 0xCC, + 0x5D, 0xBA, 0x5D, 0xA1, 0xFD, 0x89, 0x01, 0x50, + 0xB0, 0xC6, 0x45, 0x5C, 0xB4, 0xF5, 0x8B, 0x19, + 0x52, 0x52, 0x25, 0x25 }, + { 0x20, 0x79, 0x46, 0x55, 0x98, 0x0C, 0x91, 0xD8, + 0xBB, 0xB4, 0xC1, 0xEA, 0x97, 0x61, 0x8A, 0x4B, + 0xF0, 0x3F, 0x42, 0x58, 0x19, 0x48, 0xB2, 0xEE, + 0x4E, 0xE7, 0xAD, 0x67 }, + + /* + * SHA-256 test vectors + */ + { 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, + 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, + 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, + 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD }, + { 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8, + 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39, + 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67, + 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 }, + { 0xCD, 0xC7, 0x6E, 0x5C, 0x99, 0x14, 0xFB, 0x92, + 0x81, 0xA1, 0xC7, 0xE2, 0x84, 0xD7, 0x3E, 0x67, + 0xF1, 0x80, 0x9A, 0x48, 0xA4, 0x97, 0x20, 0x0E, + 0x04, 0x6D, 0x39, 0xCC, 0xC7, 0x11, 0x2C, 0xD0 } +}; + +/* + * Checkup routine + */ +int mbedtls_sha256_self_test( int verbose ) +{ + int i, j, k, buflen, ret = 0; + unsigned char *buf; + unsigned char sha256sum[32]; + mbedtls_sha256_context ctx; + + buf = mbedtls_calloc( 1024, sizeof(unsigned char) ); + if( NULL == buf ) + { + if( verbose != 0 ) + mbedtls_printf( "Buffer allocation failed\n" ); + + return( 1 ); + } + + mbedtls_sha256_init( &ctx ); + + for( i = 0; i < 6; i++ ) + { + j = i % 3; + k = i < 3; + + if( verbose != 0 ) + mbedtls_printf( " SHA-%d test #%d: ", 256 - k * 32, j + 1 ); + + if( ( ret = mbedtls_sha256_starts_ret( &ctx, k ) ) != 0 ) + goto fail; + + if( j == 2 ) + { + memset( buf, 'a', buflen = 1000 ); + + for( j = 0; j < 1000; j++ ) + { + ret = mbedtls_sha256_update_ret( &ctx, buf, buflen ); + if( ret != 0 ) + goto fail; + } + + } + else + { + ret = mbedtls_sha256_update_ret( &ctx, sha256_test_buf[j], + sha256_test_buflen[j] ); + if( ret != 0 ) + goto fail; + } + + if( ( ret = mbedtls_sha256_finish_ret( &ctx, sha256sum ) ) != 0 ) + goto fail; + + + if( memcmp( sha256sum, sha256_test_sum[i], 32 - k * 4 ) != 0 ) + { + ret = 1; + goto fail; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + goto exit; + +fail: + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + +exit: + mbedtls_sha256_free( &ctx ); + mbedtls_free( buf ); + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_SHA256_C */ diff --git a/src/common/mbedtls/library/mbedtls_sha512.c b/src/common/mbedtls/library/mbedtls_sha512.c new file mode 100644 index 0000000000..3d9aa0a656 --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_sha512.c @@ -0,0 +1,663 @@ +/* + * FIPS-180-2 compliant SHA-384/512 implementation + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +/* + * The SHA-512 Secure Hash Standard was published by NIST in 2002. + * + * https://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SHA512_C) + +#include "mbedtls/sha512.h" +#include "mbedtls/platform_util.h" + +#if defined(_MSC_VER) || defined(__WATCOMC__) + #define UL64(x) x##ui64 +#else + #define UL64(x) x##ULL +#endif + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_SELF_TEST) +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST */ + +#define SHA512_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_SHA512_BAD_INPUT_DATA ) +#define SHA512_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if !defined(MBEDTLS_SHA512_ALT) + +/* + * 64-bit integer manipulation macros (big endian) + */ +#ifndef GET_UINT64_BE +#define GET_UINT64_BE(n,b,i) \ +{ \ + (n) = ( (uint64_t) (b)[(i) ] << 56 ) \ + | ( (uint64_t) (b)[(i) + 1] << 48 ) \ + | ( (uint64_t) (b)[(i) + 2] << 40 ) \ + | ( (uint64_t) (b)[(i) + 3] << 32 ) \ + | ( (uint64_t) (b)[(i) + 4] << 24 ) \ + | ( (uint64_t) (b)[(i) + 5] << 16 ) \ + | ( (uint64_t) (b)[(i) + 6] << 8 ) \ + | ( (uint64_t) (b)[(i) + 7] ); \ +} +#endif /* GET_UINT64_BE */ + +#ifndef PUT_UINT64_BE +#define PUT_UINT64_BE(n,b,i) \ +{ \ + (b)[(i) ] = (unsigned char) ( (n) >> 56 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 48 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 40 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) >> 32 ); \ + (b)[(i) + 4] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 5] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 6] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 7] = (unsigned char) ( (n) ); \ +} +#endif /* PUT_UINT64_BE */ + +void mbedtls_sha512_init( mbedtls_sha512_context *ctx ) +{ + SHA512_VALIDATE( ctx != NULL ); + + memset( ctx, 0, sizeof( mbedtls_sha512_context ) ); +} + +void mbedtls_sha512_free( mbedtls_sha512_context *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_sha512_context ) ); +} + +void mbedtls_sha512_clone( mbedtls_sha512_context *dst, + const mbedtls_sha512_context *src ) +{ + SHA512_VALIDATE( dst != NULL ); + SHA512_VALIDATE( src != NULL ); + + *dst = *src; +} + +/* + * SHA-512 context setup + */ +int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384 ) +{ + SHA512_VALIDATE_RET( ctx != NULL ); + SHA512_VALIDATE_RET( is384 == 0 || is384 == 1 ); + + ctx->total[0] = 0; + ctx->total[1] = 0; + + if( is384 == 0 ) + { + /* SHA-512 */ + ctx->state[0] = UL64(0x6A09E667F3BCC908); + ctx->state[1] = UL64(0xBB67AE8584CAA73B); + ctx->state[2] = UL64(0x3C6EF372FE94F82B); + ctx->state[3] = UL64(0xA54FF53A5F1D36F1); + ctx->state[4] = UL64(0x510E527FADE682D1); + ctx->state[5] = UL64(0x9B05688C2B3E6C1F); + ctx->state[6] = UL64(0x1F83D9ABFB41BD6B); + ctx->state[7] = UL64(0x5BE0CD19137E2179); + } + else + { + /* SHA-384 */ + ctx->state[0] = UL64(0xCBBB9D5DC1059ED8); + ctx->state[1] = UL64(0x629A292A367CD507); + ctx->state[2] = UL64(0x9159015A3070DD17); + ctx->state[3] = UL64(0x152FECD8F70E5939); + ctx->state[4] = UL64(0x67332667FFC00B31); + ctx->state[5] = UL64(0x8EB44A8768581511); + ctx->state[6] = UL64(0xDB0C2E0D64F98FA7); + ctx->state[7] = UL64(0x47B5481DBEFA4FA4); + } + + ctx->is384 = is384; + + return( 0 ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, + int is384 ) +{ + mbedtls_sha512_starts_ret( ctx, is384 ); +} +#endif + +#if !defined(MBEDTLS_SHA512_PROCESS_ALT) + +/* + * Round constants + */ +static const uint64_t K[80] = +{ + UL64(0x428A2F98D728AE22), UL64(0x7137449123EF65CD), + UL64(0xB5C0FBCFEC4D3B2F), UL64(0xE9B5DBA58189DBBC), + UL64(0x3956C25BF348B538), UL64(0x59F111F1B605D019), + UL64(0x923F82A4AF194F9B), UL64(0xAB1C5ED5DA6D8118), + UL64(0xD807AA98A3030242), UL64(0x12835B0145706FBE), + UL64(0x243185BE4EE4B28C), UL64(0x550C7DC3D5FFB4E2), + UL64(0x72BE5D74F27B896F), UL64(0x80DEB1FE3B1696B1), + UL64(0x9BDC06A725C71235), UL64(0xC19BF174CF692694), + UL64(0xE49B69C19EF14AD2), UL64(0xEFBE4786384F25E3), + UL64(0x0FC19DC68B8CD5B5), UL64(0x240CA1CC77AC9C65), + UL64(0x2DE92C6F592B0275), UL64(0x4A7484AA6EA6E483), + UL64(0x5CB0A9DCBD41FBD4), UL64(0x76F988DA831153B5), + UL64(0x983E5152EE66DFAB), UL64(0xA831C66D2DB43210), + UL64(0xB00327C898FB213F), UL64(0xBF597FC7BEEF0EE4), + UL64(0xC6E00BF33DA88FC2), UL64(0xD5A79147930AA725), + UL64(0x06CA6351E003826F), UL64(0x142929670A0E6E70), + UL64(0x27B70A8546D22FFC), UL64(0x2E1B21385C26C926), + UL64(0x4D2C6DFC5AC42AED), UL64(0x53380D139D95B3DF), + UL64(0x650A73548BAF63DE), UL64(0x766A0ABB3C77B2A8), + UL64(0x81C2C92E47EDAEE6), UL64(0x92722C851482353B), + UL64(0xA2BFE8A14CF10364), UL64(0xA81A664BBC423001), + UL64(0xC24B8B70D0F89791), UL64(0xC76C51A30654BE30), + UL64(0xD192E819D6EF5218), UL64(0xD69906245565A910), + UL64(0xF40E35855771202A), UL64(0x106AA07032BBD1B8), + UL64(0x19A4C116B8D2D0C8), UL64(0x1E376C085141AB53), + UL64(0x2748774CDF8EEB99), UL64(0x34B0BCB5E19B48A8), + UL64(0x391C0CB3C5C95A63), UL64(0x4ED8AA4AE3418ACB), + UL64(0x5B9CCA4F7763E373), UL64(0x682E6FF3D6B2B8A3), + UL64(0x748F82EE5DEFB2FC), UL64(0x78A5636F43172F60), + UL64(0x84C87814A1F0AB72), UL64(0x8CC702081A6439EC), + UL64(0x90BEFFFA23631E28), UL64(0xA4506CEBDE82BDE9), + UL64(0xBEF9A3F7B2C67915), UL64(0xC67178F2E372532B), + UL64(0xCA273ECEEA26619C), UL64(0xD186B8C721C0C207), + UL64(0xEADA7DD6CDE0EB1E), UL64(0xF57D4F7FEE6ED178), + UL64(0x06F067AA72176FBA), UL64(0x0A637DC5A2C898A6), + UL64(0x113F9804BEF90DAE), UL64(0x1B710B35131C471B), + UL64(0x28DB77F523047D84), UL64(0x32CAAB7B40C72493), + UL64(0x3C9EBE0A15C9BEBC), UL64(0x431D67C49C100D4C), + UL64(0x4CC5D4BECB3E42B6), UL64(0x597F299CFC657E2A), + UL64(0x5FCB6FAB3AD6FAEC), UL64(0x6C44198C4A475817) +}; + +int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx, + const unsigned char data[128] ) +{ + int i; + struct + { + uint64_t temp1, temp2, W[80]; + uint64_t A, B, C, D, E, F, G, H; + } local; + + SHA512_VALIDATE_RET( ctx != NULL ); + SHA512_VALIDATE_RET( (const unsigned char *)data != NULL ); + +#define SHR(x,n) ((x) >> (n)) +#define ROTR(x,n) (SHR((x),(n)) | ((x) << (64 - (n)))) + +#define S0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x, 7)) +#define S1(x) (ROTR(x,19) ^ ROTR(x,61) ^ SHR(x, 6)) + +#define S2(x) (ROTR(x,28) ^ ROTR(x,34) ^ ROTR(x,39)) +#define S3(x) (ROTR(x,14) ^ ROTR(x,18) ^ ROTR(x,41)) + +#define F0(x,y,z) (((x) & (y)) | ((z) & ((x) | (y)))) +#define F1(x,y,z) ((z) ^ ((x) & ((y) ^ (z)))) + +#define P(a,b,c,d,e,f,g,h,x,K) \ + do \ + { \ + local.temp1 = (h) + S3(e) + F1((e),(f),(g)) + (K) + (x); \ + local.temp2 = S2(a) + F0((a),(b),(c)); \ + (d) += local.temp1; (h) = local.temp1 + local.temp2; \ + } while( 0 ) + + for( i = 0; i < 16; i++ ) + { + GET_UINT64_BE( local.W[i], data, i << 3 ); + } + + for( ; i < 80; i++ ) + { + local.W[i] = S1(local.W[i - 2]) + local.W[i - 7] + + S0(local.W[i - 15]) + local.W[i - 16]; + } + + local.A = ctx->state[0]; + local.B = ctx->state[1]; + local.C = ctx->state[2]; + local.D = ctx->state[3]; + local.E = ctx->state[4]; + local.F = ctx->state[5]; + local.G = ctx->state[6]; + local.H = ctx->state[7]; + i = 0; + + do + { + P( local.A, local.B, local.C, local.D, local.E, + local.F, local.G, local.H, local.W[i], K[i] ); i++; + P( local.H, local.A, local.B, local.C, local.D, + local.E, local.F, local.G, local.W[i], K[i] ); i++; + P( local.G, local.H, local.A, local.B, local.C, + local.D, local.E, local.F, local.W[i], K[i] ); i++; + P( local.F, local.G, local.H, local.A, local.B, + local.C, local.D, local.E, local.W[i], K[i] ); i++; + P( local.E, local.F, local.G, local.H, local.A, + local.B, local.C, local.D, local.W[i], K[i] ); i++; + P( local.D, local.E, local.F, local.G, local.H, + local.A, local.B, local.C, local.W[i], K[i] ); i++; + P( local.C, local.D, local.E, local.F, local.G, + local.H, local.A, local.B, local.W[i], K[i] ); i++; + P( local.B, local.C, local.D, local.E, local.F, + local.G, local.H, local.A, local.W[i], K[i] ); i++; + } + while( i < 80 ); + + ctx->state[0] += local.A; + ctx->state[1] += local.B; + ctx->state[2] += local.C; + ctx->state[3] += local.D; + ctx->state[4] += local.E; + ctx->state[5] += local.F; + ctx->state[6] += local.G; + ctx->state[7] += local.H; + + /* Zeroise buffers and variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &local, sizeof( local ) ); + + return( 0 ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512_process( mbedtls_sha512_context *ctx, + const unsigned char data[128] ) +{ + mbedtls_internal_sha512_process( ctx, data ); +} +#endif +#endif /* !MBEDTLS_SHA512_PROCESS_ALT */ + +/* + * SHA-512 process buffer + */ +int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + int ret; + size_t fill; + unsigned int left; + + SHA512_VALIDATE_RET( ctx != NULL ); + SHA512_VALIDATE_RET( ilen == 0 || input != NULL ); + + if( ilen == 0 ) + return( 0 ); + + left = (unsigned int) (ctx->total[0] & 0x7F); + fill = 128 - left; + + ctx->total[0] += (uint64_t) ilen; + + if( ctx->total[0] < (uint64_t) ilen ) + ctx->total[1]++; + + if( left && ilen >= fill ) + { + memcpy( (void *) (ctx->buffer + left), input, fill ); + + if( ( ret = mbedtls_internal_sha512_process( ctx, ctx->buffer ) ) != 0 ) + return( ret ); + + input += fill; + ilen -= fill; + left = 0; + } + + while( ilen >= 128 ) + { + if( ( ret = mbedtls_internal_sha512_process( ctx, input ) ) != 0 ) + return( ret ); + + input += 128; + ilen -= 128; + } + + if( ilen > 0 ) + memcpy( (void *) (ctx->buffer + left), input, ilen ); + + return( 0 ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512_update( mbedtls_sha512_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + mbedtls_sha512_update_ret( ctx, input, ilen ); +} +#endif + +/* + * SHA-512 final digest + */ +int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, + unsigned char output[64] ) +{ + int ret; + unsigned used; + uint64_t high, low; + + SHA512_VALIDATE_RET( ctx != NULL ); + SHA512_VALIDATE_RET( (unsigned char *)output != NULL ); + + /* + * Add padding: 0x80 then 0x00 until 16 bytes remain for the length + */ + used = ctx->total[0] & 0x7F; + + ctx->buffer[used++] = 0x80; + + if( used <= 112 ) + { + /* Enough room for padding + length in current block */ + memset( ctx->buffer + used, 0, 112 - used ); + } + else + { + /* We'll need an extra block */ + memset( ctx->buffer + used, 0, 128 - used ); + + if( ( ret = mbedtls_internal_sha512_process( ctx, ctx->buffer ) ) != 0 ) + return( ret ); + + memset( ctx->buffer, 0, 112 ); + } + + /* + * Add message length + */ + high = ( ctx->total[0] >> 61 ) + | ( ctx->total[1] << 3 ); + low = ( ctx->total[0] << 3 ); + + PUT_UINT64_BE( high, ctx->buffer, 112 ); + PUT_UINT64_BE( low, ctx->buffer, 120 ); + + if( ( ret = mbedtls_internal_sha512_process( ctx, ctx->buffer ) ) != 0 ) + return( ret ); + + /* + * Output final state + */ + PUT_UINT64_BE( ctx->state[0], output, 0 ); + PUT_UINT64_BE( ctx->state[1], output, 8 ); + PUT_UINT64_BE( ctx->state[2], output, 16 ); + PUT_UINT64_BE( ctx->state[3], output, 24 ); + PUT_UINT64_BE( ctx->state[4], output, 32 ); + PUT_UINT64_BE( ctx->state[5], output, 40 ); + + if( ctx->is384 == 0 ) + { + PUT_UINT64_BE( ctx->state[6], output, 48 ); + PUT_UINT64_BE( ctx->state[7], output, 56 ); + } + + return( 0 ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, + unsigned char output[64] ) +{ + mbedtls_sha512_finish_ret( ctx, output ); +} +#endif + +#endif /* !MBEDTLS_SHA512_ALT */ + +/* + * output = SHA-512( input buffer ) + */ +int mbedtls_sha512_ret( const unsigned char *input, + size_t ilen, + unsigned char output[64], + int is384 ) +{ + int ret; + mbedtls_sha512_context ctx; + + SHA512_VALIDATE_RET( is384 == 0 || is384 == 1 ); + SHA512_VALIDATE_RET( ilen == 0 || input != NULL ); + SHA512_VALIDATE_RET( (unsigned char *)output != NULL ); + + mbedtls_sha512_init( &ctx ); + + if( ( ret = mbedtls_sha512_starts_ret( &ctx, is384 ) ) != 0 ) + goto exit; + + if( ( ret = mbedtls_sha512_update_ret( &ctx, input, ilen ) ) != 0 ) + goto exit; + + if( ( ret = mbedtls_sha512_finish_ret( &ctx, output ) ) != 0 ) + goto exit; + +exit: + mbedtls_sha512_free( &ctx ); + + return( ret ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_sha512( const unsigned char *input, + size_t ilen, + unsigned char output[64], + int is384 ) +{ + mbedtls_sha512_ret( input, ilen, output, is384 ); +} +#endif + +#if defined(MBEDTLS_SELF_TEST) + +/* + * FIPS-180-2 test vectors + */ +static const unsigned char sha512_test_buf[3][113] = +{ + { "abc" }, + { "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn" + "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" }, + { "" } +}; + +static const size_t sha512_test_buflen[3] = +{ + 3, 112, 1000 +}; + +static const unsigned char sha512_test_sum[6][64] = +{ + /* + * SHA-384 test vectors + */ + { 0xCB, 0x00, 0x75, 0x3F, 0x45, 0xA3, 0x5E, 0x8B, + 0xB5, 0xA0, 0x3D, 0x69, 0x9A, 0xC6, 0x50, 0x07, + 0x27, 0x2C, 0x32, 0xAB, 0x0E, 0xDE, 0xD1, 0x63, + 0x1A, 0x8B, 0x60, 0x5A, 0x43, 0xFF, 0x5B, 0xED, + 0x80, 0x86, 0x07, 0x2B, 0xA1, 0xE7, 0xCC, 0x23, + 0x58, 0xBA, 0xEC, 0xA1, 0x34, 0xC8, 0x25, 0xA7 }, + { 0x09, 0x33, 0x0C, 0x33, 0xF7, 0x11, 0x47, 0xE8, + 0x3D, 0x19, 0x2F, 0xC7, 0x82, 0xCD, 0x1B, 0x47, + 0x53, 0x11, 0x1B, 0x17, 0x3B, 0x3B, 0x05, 0xD2, + 0x2F, 0xA0, 0x80, 0x86, 0xE3, 0xB0, 0xF7, 0x12, + 0xFC, 0xC7, 0xC7, 0x1A, 0x55, 0x7E, 0x2D, 0xB9, + 0x66, 0xC3, 0xE9, 0xFA, 0x91, 0x74, 0x60, 0x39 }, + { 0x9D, 0x0E, 0x18, 0x09, 0x71, 0x64, 0x74, 0xCB, + 0x08, 0x6E, 0x83, 0x4E, 0x31, 0x0A, 0x4A, 0x1C, + 0xED, 0x14, 0x9E, 0x9C, 0x00, 0xF2, 0x48, 0x52, + 0x79, 0x72, 0xCE, 0xC5, 0x70, 0x4C, 0x2A, 0x5B, + 0x07, 0xB8, 0xB3, 0xDC, 0x38, 0xEC, 0xC4, 0xEB, + 0xAE, 0x97, 0xDD, 0xD8, 0x7F, 0x3D, 0x89, 0x85 }, + + /* + * SHA-512 test vectors + */ + { 0xDD, 0xAF, 0x35, 0xA1, 0x93, 0x61, 0x7A, 0xBA, + 0xCC, 0x41, 0x73, 0x49, 0xAE, 0x20, 0x41, 0x31, + 0x12, 0xE6, 0xFA, 0x4E, 0x89, 0xA9, 0x7E, 0xA2, + 0x0A, 0x9E, 0xEE, 0xE6, 0x4B, 0x55, 0xD3, 0x9A, + 0x21, 0x92, 0x99, 0x2A, 0x27, 0x4F, 0xC1, 0xA8, + 0x36, 0xBA, 0x3C, 0x23, 0xA3, 0xFE, 0xEB, 0xBD, + 0x45, 0x4D, 0x44, 0x23, 0x64, 0x3C, 0xE8, 0x0E, + 0x2A, 0x9A, 0xC9, 0x4F, 0xA5, 0x4C, 0xA4, 0x9F }, + { 0x8E, 0x95, 0x9B, 0x75, 0xDA, 0xE3, 0x13, 0xDA, + 0x8C, 0xF4, 0xF7, 0x28, 0x14, 0xFC, 0x14, 0x3F, + 0x8F, 0x77, 0x79, 0xC6, 0xEB, 0x9F, 0x7F, 0xA1, + 0x72, 0x99, 0xAE, 0xAD, 0xB6, 0x88, 0x90, 0x18, + 0x50, 0x1D, 0x28, 0x9E, 0x49, 0x00, 0xF7, 0xE4, + 0x33, 0x1B, 0x99, 0xDE, 0xC4, 0xB5, 0x43, 0x3A, + 0xC7, 0xD3, 0x29, 0xEE, 0xB6, 0xDD, 0x26, 0x54, + 0x5E, 0x96, 0xE5, 0x5B, 0x87, 0x4B, 0xE9, 0x09 }, + { 0xE7, 0x18, 0x48, 0x3D, 0x0C, 0xE7, 0x69, 0x64, + 0x4E, 0x2E, 0x42, 0xC7, 0xBC, 0x15, 0xB4, 0x63, + 0x8E, 0x1F, 0x98, 0xB1, 0x3B, 0x20, 0x44, 0x28, + 0x56, 0x32, 0xA8, 0x03, 0xAF, 0xA9, 0x73, 0xEB, + 0xDE, 0x0F, 0xF2, 0x44, 0x87, 0x7E, 0xA6, 0x0A, + 0x4C, 0xB0, 0x43, 0x2C, 0xE5, 0x77, 0xC3, 0x1B, + 0xEB, 0x00, 0x9C, 0x5C, 0x2C, 0x49, 0xAA, 0x2E, + 0x4E, 0xAD, 0xB2, 0x17, 0xAD, 0x8C, 0xC0, 0x9B } +}; + +/* + * Checkup routine + */ +int mbedtls_sha512_self_test( int verbose ) +{ + int i, j, k, buflen, ret = 0; + unsigned char *buf; + unsigned char sha512sum[64]; + mbedtls_sha512_context ctx; + + buf = mbedtls_calloc( 1024, sizeof(unsigned char) ); + if( NULL == buf ) + { + if( verbose != 0 ) + mbedtls_printf( "Buffer allocation failed\n" ); + + return( 1 ); + } + + mbedtls_sha512_init( &ctx ); + + for( i = 0; i < 6; i++ ) + { + j = i % 3; + k = i < 3; + + if( verbose != 0 ) + mbedtls_printf( " SHA-%d test #%d: ", 512 - k * 128, j + 1 ); + + if( ( ret = mbedtls_sha512_starts_ret( &ctx, k ) ) != 0 ) + goto fail; + + if( j == 2 ) + { + memset( buf, 'a', buflen = 1000 ); + + for( j = 0; j < 1000; j++ ) + { + ret = mbedtls_sha512_update_ret( &ctx, buf, buflen ); + if( ret != 0 ) + goto fail; + } + } + else + { + ret = mbedtls_sha512_update_ret( &ctx, sha512_test_buf[j], + sha512_test_buflen[j] ); + if( ret != 0 ) + goto fail; + } + + if( ( ret = mbedtls_sha512_finish_ret( &ctx, sha512sum ) ) != 0 ) + goto fail; + + if( memcmp( sha512sum, sha512_test_sum[i], 64 - k * 16 ) != 0 ) + { + ret = 1; + goto fail; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + } + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + goto exit; + +fail: + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + +exit: + mbedtls_sha512_free( &ctx ); + mbedtls_free( buf ); + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_SHA512_C */ diff --git a/src/common/mbedtls/library/mbedtls_x509.c b/src/common/mbedtls/library/mbedtls_x509.c new file mode 100644 index 0000000000..bec73bf53d --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_x509.c @@ -0,0 +1,1085 @@ +/* + * X.509 common functions for parsing and verification + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +/* + * The ITU-T X.509 standard defines a certificate format for PKI. + * + * https://www.ietf.org/rfc/rfc5280.txt (Certificates and CRLs) + * https://www.ietf.org/rfc/rfc3279.txt (Alg IDs for CRLs) + * https://www.ietf.org/rfc/rfc2986.txt (CSRs, aka PKCS#10) + * + * https://www.itu.int/ITU-T/studygroups/com17/languages/X.680-0207.pdf + * https://www.itu.int/ITU-T/studygroups/com17/languages/X.690-0207.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_X509_USE_C) + +#include "mbedtls/x509.h" +#include "mbedtls/asn1.h" +#include "mbedtls/oid.h" + +#ifndef NVRM +#include +#include +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) +#include "mbedtls/pem.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_free free +#define mbedtls_calloc calloc +#define mbedtls_printf printf +#define mbedtls_snprintf snprintf +#endif + +#if defined(MBEDTLS_HAVE_TIME) +#include "mbedtls/platform_time.h" +#endif +#if defined(MBEDTLS_HAVE_TIME_DATE) +#include "mbedtls/platform_util.h" +#include +#endif + +#define CHECK(code) if( ( ret = ( code ) ) != 0 ){ return( ret ); } +#define CHECK_RANGE(min, max, val) \ + do \ + { \ + if( ( val ) < ( min ) || ( val ) > ( max ) ) \ + { \ + return( ret ); \ + } \ + } while( 0 ) + +/* + * CertificateSerialNumber ::= INTEGER + */ +int mbedtls_x509_get_serial( unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *serial ) +{ + int ret; + + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_X509_INVALID_SERIAL + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + if( **p != ( MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_PRIMITIVE | 2 ) && + **p != MBEDTLS_ASN1_INTEGER ) + return( MBEDTLS_ERR_X509_INVALID_SERIAL + + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + + serial->tag = *(*p)++; + + if( ( ret = mbedtls_asn1_get_len( p, end, &serial->len ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_SERIAL + ret ); + + serial->p = *p; + *p += serial->len; + + return( 0 ); +} + +/* Get an algorithm identifier without parameters (eg for signatures) + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL } + */ +int mbedtls_x509_get_alg_null( unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *alg ) +{ + int ret; + + if( ( ret = mbedtls_asn1_get_alg_null( p, end, alg ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + return( 0 ); +} + +/* + * Parse an algorithm identifier with (optional) parameters + */ +int mbedtls_x509_get_alg( unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *alg, mbedtls_x509_buf *params ) +{ + int ret; + + if( ( ret = mbedtls_asn1_get_alg( p, end, alg, params ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + return( 0 ); +} + +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) +/* + * HashAlgorithm ::= AlgorithmIdentifier + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL } + * + * For HashAlgorithm, parameters MUST be NULL or absent. + */ +static int x509_get_hash_alg( const mbedtls_x509_buf *alg, mbedtls_md_type_t *md_alg ) +{ + int ret; + unsigned char *p; + const unsigned char *end; + mbedtls_x509_buf md_oid; + size_t len; + + /* Make sure we got a SEQUENCE and setup bounds */ + if( alg->tag != ( MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + + p = (unsigned char *) alg->p; + end = p + alg->len; + + if( p >= end ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + /* Parse md_oid */ + md_oid.tag = *p; + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &md_oid.len, MBEDTLS_ASN1_OID ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + md_oid.p = p; + p += md_oid.len; + + /* Get md_alg from md_oid */ + if( ( ret = mbedtls_oid_get_md_alg( &md_oid, md_alg ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + /* Make sure params is absent of NULL */ + if( p == end ) + return( 0 ); + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, MBEDTLS_ASN1_NULL ) ) != 0 || len != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + if( p != end ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +/* + * RSASSA-PSS-params ::= SEQUENCE { + * hashAlgorithm [0] HashAlgorithm DEFAULT sha1Identifier, + * maskGenAlgorithm [1] MaskGenAlgorithm DEFAULT mgf1SHA1Identifier, + * saltLength [2] INTEGER DEFAULT 20, + * trailerField [3] INTEGER DEFAULT 1 } + * -- Note that the tags in this Sequence are explicit. + * + * RFC 4055 (which defines use of RSASSA-PSS in PKIX) states that the value + * of trailerField MUST be 1, and PKCS#1 v2.2 doesn't even define any other + * option. Enfore this at parsing time. + */ +int mbedtls_x509_get_rsassa_pss_params( const mbedtls_x509_buf *params, + mbedtls_md_type_t *md_alg, mbedtls_md_type_t *mgf_md, + int *salt_len ) +{ + int ret; + unsigned char *p; + const unsigned char *end, *end2; + size_t len; + mbedtls_x509_buf alg_id, alg_params; + + /* First set everything to defaults */ + *md_alg = MBEDTLS_MD_SHA1; + *mgf_md = MBEDTLS_MD_SHA1; + *salt_len = 20; + + /* Make sure params is a SEQUENCE and setup bounds */ + if( params->tag != ( MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + + p = (unsigned char *) params->p; + end = p + params->len; + + if( p == end ) + return( 0 ); + + /* + * HashAlgorithm + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | 0 ) ) == 0 ) + { + end2 = p + len; + + /* HashAlgorithm ::= AlgorithmIdentifier (without parameters) */ + if( ( ret = mbedtls_x509_get_alg_null( &p, end2, &alg_id ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_oid_get_md_alg( &alg_id, md_alg ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + if( p != end2 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + } + else if( ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + if( p == end ) + return( 0 ); + + /* + * MaskGenAlgorithm + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | 1 ) ) == 0 ) + { + end2 = p + len; + + /* MaskGenAlgorithm ::= AlgorithmIdentifier (params = HashAlgorithm) */ + if( ( ret = mbedtls_x509_get_alg( &p, end2, &alg_id, &alg_params ) ) != 0 ) + return( ret ); + + /* Only MFG1 is recognised for now */ + if( MBEDTLS_OID_CMP( MBEDTLS_OID_MGF1, &alg_id ) != 0 ) + return( MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE + + MBEDTLS_ERR_OID_NOT_FOUND ); + + /* Parse HashAlgorithm */ + if( ( ret = x509_get_hash_alg( &alg_params, mgf_md ) ) != 0 ) + return( ret ); + + if( p != end2 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + } + else if( ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + if( p == end ) + return( 0 ); + + /* + * salt_len + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | 2 ) ) == 0 ) + { + end2 = p + len; + + if( ( ret = mbedtls_asn1_get_int( &p, end2, salt_len ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + if( p != end2 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + } + else if( ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + if( p == end ) + return( 0 ); + + /* + * trailer_field (if present, must be 1) + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | 3 ) ) == 0 ) + { + int trailer_field; + + end2 = p + len; + + if( ( ret = mbedtls_asn1_get_int( &p, end2, &trailer_field ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + if( p != end2 ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + if( trailer_field != 1 ) + return( MBEDTLS_ERR_X509_INVALID_ALG ); + } + else if( ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); + + if( p != end ) + return( MBEDTLS_ERR_X509_INVALID_ALG + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} +#endif /* MBEDTLS_X509_RSASSA_PSS_SUPPORT */ + +/* + * AttributeTypeAndValue ::= SEQUENCE { + * type AttributeType, + * value AttributeValue } + * + * AttributeType ::= OBJECT IDENTIFIER + * + * AttributeValue ::= ANY DEFINED BY AttributeType + */ +static int x509_get_attr_type_value( unsigned char **p, + const unsigned char *end, + mbedtls_x509_name *cur ) +{ + int ret; + size_t len; + mbedtls_x509_buf *oid; + mbedtls_x509_buf *val; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_NAME + ret ); + + end = *p + len; + + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_X509_INVALID_NAME + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + oid = &cur->oid; + oid->tag = **p; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &oid->len, MBEDTLS_ASN1_OID ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_NAME + ret ); + + oid->p = *p; + *p += oid->len; + + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_X509_INVALID_NAME + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + if( **p != MBEDTLS_ASN1_BMP_STRING && **p != MBEDTLS_ASN1_UTF8_STRING && + **p != MBEDTLS_ASN1_T61_STRING && **p != MBEDTLS_ASN1_PRINTABLE_STRING && + **p != MBEDTLS_ASN1_IA5_STRING && **p != MBEDTLS_ASN1_UNIVERSAL_STRING && + **p != MBEDTLS_ASN1_BIT_STRING ) + return( MBEDTLS_ERR_X509_INVALID_NAME + + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + + val = &cur->val; + val->tag = *(*p)++; + + if( ( ret = mbedtls_asn1_get_len( p, end, &val->len ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_NAME + ret ); + + val->p = *p; + *p += val->len; + + if( *p != end ) + { + return( MBEDTLS_ERR_X509_INVALID_NAME + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + } + + cur->next = NULL; + + return( 0 ); +} + +/* + * Name ::= CHOICE { -- only one possibility for now -- + * rdnSequence RDNSequence } + * + * RDNSequence ::= SEQUENCE OF RelativeDistinguishedName + * + * RelativeDistinguishedName ::= + * SET OF AttributeTypeAndValue + * + * AttributeTypeAndValue ::= SEQUENCE { + * type AttributeType, + * value AttributeValue } + * + * AttributeType ::= OBJECT IDENTIFIER + * + * AttributeValue ::= ANY DEFINED BY AttributeType + * + * The data structure is optimized for the common case where each RDN has only + * one element, which is represented as a list of AttributeTypeAndValue. + * For the general case we still use a flat list, but we mark elements of the + * same set so that they are "merged" together in the functions that consume + * this list, eg mbedtls_x509_dn_gets(). + */ +int mbedtls_x509_get_name( unsigned char **p, const unsigned char *end, + mbedtls_x509_name *cur ) +{ + int ret; + size_t set_len; + const unsigned char *end_set; + + /* don't use recursion, we'd risk stack overflow if not optimized */ + while( 1 ) + { + /* + * parse SET + */ + if( ( ret = mbedtls_asn1_get_tag( p, end, &set_len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SET ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_NAME + ret ); + + end_set = *p + set_len; + + while( 1 ) + { + if( ( ret = x509_get_attr_type_value( p, end_set, cur ) ) != 0 ) + return( ret ); + + if( *p == end_set ) + break; + + /* Mark this item as being no the only one in a set */ + cur->next_merged = 1; + + cur->next = mbedtls_calloc( 1, sizeof( mbedtls_x509_name ) ); + + if( cur->next == NULL ) + return( MBEDTLS_ERR_X509_ALLOC_FAILED ); + + cur = cur->next; + } + + /* + * continue until end of SEQUENCE is reached + */ + if( *p == end ) + return( 0 ); + + cur->next = mbedtls_calloc( 1, sizeof( mbedtls_x509_name ) ); + + if( cur->next == NULL ) + return( MBEDTLS_ERR_X509_ALLOC_FAILED ); + + cur = cur->next; + } +} + +static int x509_parse_int( unsigned char **p, size_t n, int *res ) +{ + *res = 0; + + for( ; n > 0; --n ) + { + if( ( **p < '0') || ( **p > '9' ) ) + return ( MBEDTLS_ERR_X509_INVALID_DATE ); + + *res *= 10; + *res += ( *(*p)++ - '0' ); + } + + return( 0 ); +} + +static int x509_date_is_valid(const mbedtls_x509_time *t ) +{ + int ret = MBEDTLS_ERR_X509_INVALID_DATE; + int month_len; + + CHECK_RANGE( 0, 9999, t->year ); + CHECK_RANGE( 0, 23, t->hour ); + CHECK_RANGE( 0, 59, t->min ); + CHECK_RANGE( 0, 59, t->sec ); + + switch( t->mon ) + { + case 1: case 3: case 5: case 7: case 8: case 10: case 12: + month_len = 31; + break; + case 4: case 6: case 9: case 11: + month_len = 30; + break; + case 2: + if( ( !( t->year % 4 ) && t->year % 100 ) || + !( t->year % 400 ) ) + month_len = 29; + else + month_len = 28; + break; + default: + return( ret ); + } + CHECK_RANGE( 1, month_len, t->day ); + + return( 0 ); +} + +/* + * Parse an ASN1_UTC_TIME (yearlen=2) or ASN1_GENERALIZED_TIME (yearlen=4) + * field. + */ +static int x509_parse_time( unsigned char **p, size_t len, size_t yearlen, + mbedtls_x509_time *tm ) +{ + int ret; + + /* + * Minimum length is 10 or 12 depending on yearlen + */ + if ( len < yearlen + 8 ) + return ( MBEDTLS_ERR_X509_INVALID_DATE ); + len -= yearlen + 8; + + /* + * Parse year, month, day, hour, minute + */ + CHECK( x509_parse_int( p, yearlen, &tm->year ) ); + if ( 2 == yearlen ) + { + if ( tm->year < 50 ) + tm->year += 100; + + tm->year += 1900; + } + + CHECK( x509_parse_int( p, 2, &tm->mon ) ); + CHECK( x509_parse_int( p, 2, &tm->day ) ); + CHECK( x509_parse_int( p, 2, &tm->hour ) ); + CHECK( x509_parse_int( p, 2, &tm->min ) ); + + /* + * Parse seconds if present + */ + if ( len >= 2 ) + { + CHECK( x509_parse_int( p, 2, &tm->sec ) ); + len -= 2; + } + else + return ( MBEDTLS_ERR_X509_INVALID_DATE ); + + /* + * Parse trailing 'Z' if present + */ + if ( 1 == len && 'Z' == **p ) + { + (*p)++; + len--; + } + + /* + * We should have parsed all characters at this point + */ + if ( 0 != len ) + return ( MBEDTLS_ERR_X509_INVALID_DATE ); + + CHECK( x509_date_is_valid( tm ) ); + + return ( 0 ); +} + +/* + * Time ::= CHOICE { + * utcTime UTCTime, + * generalTime GeneralizedTime } + */ +int mbedtls_x509_get_time( unsigned char **p, const unsigned char *end, + mbedtls_x509_time *tm ) +{ + int ret; + size_t len, year_len; + unsigned char tag; + + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_X509_INVALID_DATE + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + tag = **p; + + if( tag == MBEDTLS_ASN1_UTC_TIME ) + year_len = 2; + else if( tag == MBEDTLS_ASN1_GENERALIZED_TIME ) + year_len = 4; + else + return( MBEDTLS_ERR_X509_INVALID_DATE + + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + + (*p)++; + ret = mbedtls_asn1_get_len( p, end, &len ); + + if( ret != 0 ) + return( MBEDTLS_ERR_X509_INVALID_DATE + ret ); + + return x509_parse_time( p, len, year_len, tm ); +} + +int mbedtls_x509_get_sig( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *sig ) +{ + int ret; + size_t len; + int tag_type; + + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_X509_INVALID_SIGNATURE + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + tag_type = **p; + + if( ( ret = mbedtls_asn1_get_bitstring_null( p, end, &len ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_SIGNATURE + ret ); + + sig->tag = tag_type; + sig->len = len; + sig->p = *p; + + *p += len; + + return( 0 ); +} + +/* + * Get signature algorithm from alg OID and optional parameters + */ +int mbedtls_x509_get_sig_alg( const mbedtls_x509_buf *sig_oid, const mbedtls_x509_buf *sig_params, + mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg, + void **sig_opts ) +{ + int ret; + + if( *sig_opts != NULL ) + return( MBEDTLS_ERR_X509_BAD_INPUT_DATA ); + + if( ( ret = mbedtls_oid_get_sig_alg( sig_oid, md_alg, pk_alg ) ) != 0 ) + return( MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG + ret ); + +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) + if( *pk_alg == MBEDTLS_PK_RSASSA_PSS ) + { + mbedtls_pk_rsassa_pss_options *pss_opts; + + pss_opts = mbedtls_calloc( 1, sizeof( mbedtls_pk_rsassa_pss_options ) ); + if( pss_opts == NULL ) + return( MBEDTLS_ERR_X509_ALLOC_FAILED ); + + ret = mbedtls_x509_get_rsassa_pss_params( sig_params, + md_alg, + &pss_opts->mgf1_hash_id, + &pss_opts->expected_salt_len ); + if( ret != 0 ) + { + mbedtls_free( pss_opts ); + return( ret ); + } + + *sig_opts = (void *) pss_opts; + } + else +#endif /* MBEDTLS_X509_RSASSA_PSS_SUPPORT */ + { + /* Make sure parameters are absent or NULL */ + if( ( sig_params->tag != MBEDTLS_ASN1_NULL && sig_params->tag != 0 ) || + sig_params->len != 0 ) + return( MBEDTLS_ERR_X509_INVALID_ALG ); + } + + return( 0 ); +} + +/* + * X.509 Extensions (No parsing of extensions, pointer should + * be either manually updated or extensions should be parsed!) + */ +int mbedtls_x509_get_ext( unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *ext, int tag ) +{ + int ret; + size_t len; + + /* Extension structure use EXPLICIT tagging. That is, the actual + * `Extensions` structure is wrapped by a tag-length pair using + * the respective context-specific tag. */ + ret = mbedtls_asn1_get_tag( p, end, &ext->len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | tag ); + if( ret != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + ext->tag = MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | tag; + ext->p = *p; + end = *p + ext->len; + + /* + * Extensions ::= SEQUENCE SIZE (1..MAX) OF Extension + */ + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + if( end != *p + len ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +/* + * Store the name in printable form into buf; no more + * than size characters will be written + */ +int mbedtls_x509_dn_gets( char *buf, size_t size, const mbedtls_x509_name *dn ) +{ + int ret; + size_t i, n; + unsigned char c, merge = 0; + const mbedtls_x509_name *name; + const char *short_name = NULL; + char s[MBEDTLS_X509_MAX_DN_NAME_SIZE], *p; + + memset( s, 0, sizeof( s ) ); + + name = dn; + p = buf; + n = size; + + while( name != NULL ) + { + if( !name->oid.p ) + { + name = name->next; + continue; + } + + if( name != dn ) + { + ret = mbedtls_snprintf( p, n, merge ? " + " : ", " ); + MBEDTLS_X509_SAFE_SNPRINTF; + } + + ret = mbedtls_oid_get_attr_short_name( &name->oid, &short_name ); + + if( ret == 0 ) + ret = mbedtls_snprintf( p, n, "%s=", short_name ); + else + ret = mbedtls_snprintf( p, n, "\?\?=" ); + MBEDTLS_X509_SAFE_SNPRINTF; + + for( i = 0; i < name->val.len; i++ ) + { + if( i >= sizeof( s ) - 1 ) + break; + + c = name->val.p[i]; + if( c < 32 || c == 127 || ( c > 128 && c < 160 ) ) + s[i] = '?'; + else s[i] = c; + } + s[i] = '\0'; + ret = mbedtls_snprintf( p, n, "%s", s ); + MBEDTLS_X509_SAFE_SNPRINTF; + + merge = name->next_merged; + name = name->next; + } + + return( (int) ( size - n ) ); +} + +/* + * Store the serial in printable form into buf; no more + * than size characters will be written + */ +int mbedtls_x509_serial_gets( char *buf, size_t size, const mbedtls_x509_buf *serial ) +{ + int ret; + size_t i, n, nr; + char *p; + + p = buf; + n = size; + + nr = ( serial->len <= 32 ) + ? serial->len : 28; + + for( i = 0; i < nr; i++ ) + { + if( i == 0 && nr > 1 && serial->p[i] == 0x0 ) + continue; + + ret = mbedtls_snprintf( p, n, "%02X%s", + serial->p[i], ( i < nr - 1 ) ? ":" : "" ); + MBEDTLS_X509_SAFE_SNPRINTF; + } + + if( nr != serial->len ) + { + ret = mbedtls_snprintf( p, n, "...." ); + MBEDTLS_X509_SAFE_SNPRINTF; + } + + return( (int) ( size - n ) ); +} + +/* + * Helper for writing signature algorithms + */ +int mbedtls_x509_sig_alg_gets( char *buf, size_t size, const mbedtls_x509_buf *sig_oid, + mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg, + const void *sig_opts ) +{ + int ret; + char *p = buf; + size_t n = size; + const char *desc = NULL; + + ret = mbedtls_oid_get_sig_alg_desc( sig_oid, &desc ); + if( ret != 0 ) + ret = mbedtls_snprintf( p, n, "???" ); + else + ret = mbedtls_snprintf( p, n, "%s", desc ); + MBEDTLS_X509_SAFE_SNPRINTF; + +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) + if( pk_alg == MBEDTLS_PK_RSASSA_PSS ) + { + const mbedtls_pk_rsassa_pss_options *pss_opts; + const mbedtls_md_info_t *md_info, *mgf_md_info; + + pss_opts = (const mbedtls_pk_rsassa_pss_options *) sig_opts; + + md_info = mbedtls_md_info_from_type( md_alg ); + mgf_md_info = mbedtls_md_info_from_type( pss_opts->mgf1_hash_id ); + + ret = mbedtls_snprintf( p, n, " (%s, MGF1-%s, 0x%02X)", + md_info ? mbedtls_md_get_name( md_info ) : "???", + mgf_md_info ? mbedtls_md_get_name( mgf_md_info ) : "???", + pss_opts->expected_salt_len ); + MBEDTLS_X509_SAFE_SNPRINTF; + } +#else + ((void) pk_alg); + ((void) md_alg); + ((void) sig_opts); +#endif /* MBEDTLS_X509_RSASSA_PSS_SUPPORT */ + + return( (int)( size - n ) ); +} + +/* + * Helper for writing "RSA key size", "EC key size", etc + */ +int mbedtls_x509_key_size_helper( char *buf, size_t buf_size, const char *name ) +{ + char *p = buf; + size_t n = buf_size; + int ret; + + ret = mbedtls_snprintf( p, n, "%s key size", name ); + MBEDTLS_X509_SAFE_SNPRINTF; + + return( 0 ); +} + +#if defined(MBEDTLS_HAVE_TIME_DATE) +/* + * Set the time structure to the current time. + * Return 0 on success, non-zero on failure. + */ +static int x509_get_current_time( mbedtls_x509_time *now ) +{ + struct tm *lt, tm_buf; + mbedtls_time_t tt; + int ret = 0; + + tt = mbedtls_time( NULL ); + lt = mbedtls_platform_gmtime_r( &tt, &tm_buf ); + + if( lt == NULL ) + ret = -1; + else + { + now->year = lt->tm_year + 1900; + now->mon = lt->tm_mon + 1; + now->day = lt->tm_mday; + now->hour = lt->tm_hour; + now->min = lt->tm_min; + now->sec = lt->tm_sec; + } + + return( ret ); +} + +/* + * Return 0 if before <= after, 1 otherwise + */ +static int x509_check_time( const mbedtls_x509_time *before, const mbedtls_x509_time *after ) +{ + if( before->year > after->year ) + return( 1 ); + + if( before->year == after->year && + before->mon > after->mon ) + return( 1 ); + + if( before->year == after->year && + before->mon == after->mon && + before->day > after->day ) + return( 1 ); + + if( before->year == after->year && + before->mon == after->mon && + before->day == after->day && + before->hour > after->hour ) + return( 1 ); + + if( before->year == after->year && + before->mon == after->mon && + before->day == after->day && + before->hour == after->hour && + before->min > after->min ) + return( 1 ); + + if( before->year == after->year && + before->mon == after->mon && + before->day == after->day && + before->hour == after->hour && + before->min == after->min && + before->sec > after->sec ) + return( 1 ); + + return( 0 ); +} + +int mbedtls_x509_time_is_past( const mbedtls_x509_time *to ) +{ + mbedtls_x509_time now; + + if( x509_get_current_time( &now ) != 0 ) + return( 1 ); + + return( x509_check_time( &now, to ) ); +} + +int mbedtls_x509_time_is_future( const mbedtls_x509_time *from ) +{ + mbedtls_x509_time now; + + if( x509_get_current_time( &now ) != 0 ) + return( 1 ); + + return( x509_check_time( from, &now ) ); +} + +#else /* MBEDTLS_HAVE_TIME_DATE */ + +int mbedtls_x509_time_is_past( const mbedtls_x509_time *to ) +{ + ((void) to); + return( 0 ); +} + +int mbedtls_x509_time_is_future( const mbedtls_x509_time *from ) +{ + ((void) from); + return( 0 ); +} +#endif /* MBEDTLS_HAVE_TIME_DATE */ + +#if defined(MBEDTLS_SELF_TEST) + +#include "mbedtls/x509_crt.h" +#include "mbedtls/certs.h" + +/* + * Checkup routine + */ +int mbedtls_x509_self_test( int verbose ) +{ + int ret = 0; +#if defined(MBEDTLS_CERTS_C) && defined(MBEDTLS_SHA256_C) + uint32_t flags; + mbedtls_x509_crt cacert; + mbedtls_x509_crt clicert; + + if( verbose != 0 ) + mbedtls_printf( " X.509 certificate load: " ); + + mbedtls_x509_crt_init( &cacert ); + mbedtls_x509_crt_init( &clicert ); + + ret = mbedtls_x509_crt_parse( &clicert, (const unsigned char *) mbedtls_test_cli_crt, + mbedtls_test_cli_crt_len ); + if( ret != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + goto cleanup; + } + + ret = mbedtls_x509_crt_parse( &cacert, (const unsigned char *) mbedtls_test_ca_crt, + mbedtls_test_ca_crt_len ); + if( ret != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + goto cleanup; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n X.509 signature verify: "); + + ret = mbedtls_x509_crt_verify( &clicert, &cacert, NULL, NULL, &flags, NULL, NULL ); + if( ret != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n" ); + + goto cleanup; + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n\n"); + +cleanup: + mbedtls_x509_crt_free( &cacert ); + mbedtls_x509_crt_free( &clicert ); +#else + ((void) verbose); +#endif /* MBEDTLS_CERTS_C && MBEDTLS_SHA256_C */ + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_X509_USE_C */ diff --git a/src/common/mbedtls/library/mbedtls_x509_crt.c b/src/common/mbedtls/library/mbedtls_x509_crt.c new file mode 100644 index 0000000000..719aadc9fe --- /dev/null +++ b/src/common/mbedtls/library/mbedtls_x509_crt.c @@ -0,0 +1,2681 @@ +/* + * X.509 certificate parsing and verification + */ +// +// Copyright The Mbed TLS Contributors +// NVIDIA_EDIT: This version of MbedTLS is dual-licensed - NVIDIA +// receives it under the GPL-2.0 license - these headers are updated +// accordingly. +// +// SPDX-License-Identifier: GPL-2.0 +// +// This file is provided under the GNU General Public License v2.0. +// +// ********** +// GNU General Public License v2.0: +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// ********** +// +/* + * The ITU-T X.509 standard defines a certificate format for PKI. + * + * https://www.ietf.org/rfc/rfc5280.txt (Certificates and CRLs) + * https://www.ietf.org/rfc/rfc3279.txt (Alg IDs for CRLs) + * https://www.ietf.org/rfc/rfc2986.txt (CSRs, aka PKCS#10) + * + * https://www.itu.int/ITU-T/studygroups/com17/languages/X.680-0207.pdf + * https://www.itu.int/ITU-T/studygroups/com17/languages/X.690-0207.pdf + * + * [SIRO] https://cabforum.org/wp-content/uploads/Chunghwatelecom201503cabforumV4.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + +#include "mbedtls/x509_crt.h" +#include "mbedtls/oid.h" +#include "mbedtls/platform_util.h" + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) +#include "mbedtls/pem.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_free free +#define mbedtls_calloc calloc +#define mbedtls_snprintf snprintf +#endif + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + +#ifndef NVRM +#include +#endif + +#if defined(MBEDTLS_FS_IO) +#include +#include +#include +#include +#endif + +/* + * Item in a verification chain: cert and flags for it + */ +typedef struct { + mbedtls_x509_crt *crt; + uint32_t flags; +} x509_crt_verify_chain_item; + +/* + * Max size of verification chain: end-entity + intermediates + trusted root + */ +#define X509_MAX_VERIFY_CHAIN_SIZE ( MBEDTLS_X509_MAX_INTERMEDIATE_CA + 2 ) + +/* Default profile. Do not remove items unless there are serious security + * concerns. */ +const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default = +{ +#if defined(MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES) + /* Allow SHA-1 (weak, but still safe in controlled environments) */ + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA1 ) | +#endif + /* Only SHA-2 hashes */ + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA224 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA256 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA384 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA512 ), + 0xFFFFFFF, /* Any PK alg */ + 0xFFFFFFF, /* Any curve */ + 2048, +}; + +/* + * Next-default profile + */ +const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_next = +{ + /* Hashes from SHA-256 and above */ + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA256 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA384 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA512 ), + 0xFFFFFFF, /* Any PK alg */ +#if defined(MBEDTLS_ECP_C) + /* Curves at or above 128-bit security level */ + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_SECP256R1 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_SECP384R1 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_SECP521R1 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_BP256R1 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_BP384R1 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_BP512R1 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_SECP256K1 ), +#else + 0, +#endif + 2048, +}; + +/* + * NSA Suite B Profile + */ +const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_suiteb = +{ + /* Only SHA-256 and 384 */ + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA256 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA384 ), + /* Only ECDSA */ + MBEDTLS_X509_ID_FLAG( MBEDTLS_PK_ECDSA ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_PK_ECKEY ), +#if defined(MBEDTLS_ECP_C) + /* Only NIST P-256 and P-384 */ + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_SECP256R1 ) | + MBEDTLS_X509_ID_FLAG( MBEDTLS_ECP_DP_SECP384R1 ), +#else + 0, +#endif + 0, +}; + +/* + * Check md_alg against profile + * Return 0 if md_alg is acceptable for this profile, -1 otherwise + */ +static int x509_profile_check_md_alg( const mbedtls_x509_crt_profile *profile, + mbedtls_md_type_t md_alg ) +{ + if( md_alg == MBEDTLS_MD_NONE ) + return( -1 ); + + if( ( profile->allowed_mds & MBEDTLS_X509_ID_FLAG( md_alg ) ) != 0 ) + return( 0 ); + + return( -1 ); +} + +/* + * Check pk_alg against profile + * Return 0 if pk_alg is acceptable for this profile, -1 otherwise + */ +static int x509_profile_check_pk_alg( const mbedtls_x509_crt_profile *profile, + mbedtls_pk_type_t pk_alg ) +{ + if( pk_alg == MBEDTLS_PK_NONE ) + return( -1 ); + + if( ( profile->allowed_pks & MBEDTLS_X509_ID_FLAG( pk_alg ) ) != 0 ) + return( 0 ); + + return( -1 ); +} + +/* + * Check key against profile + * Return 0 if pk is acceptable for this profile, -1 otherwise + */ +static int x509_profile_check_key( const mbedtls_x509_crt_profile *profile, + const mbedtls_pk_context *pk ) +{ + const mbedtls_pk_type_t pk_alg = mbedtls_pk_get_type( pk ); + +#if defined(MBEDTLS_RSA_C) + if( pk_alg == MBEDTLS_PK_RSA || pk_alg == MBEDTLS_PK_RSASSA_PSS ) + { + if( mbedtls_pk_get_bitlen( pk ) >= profile->rsa_min_bitlen ) + return( 0 ); + + return( -1 ); + } +#endif + +#if defined(MBEDTLS_ECP_C) + if( pk_alg == MBEDTLS_PK_ECDSA || + pk_alg == MBEDTLS_PK_ECKEY || + pk_alg == MBEDTLS_PK_ECKEY_DH ) + { + const mbedtls_ecp_group_id gid = mbedtls_pk_ec( *pk )->grp.id; + + if( gid == MBEDTLS_ECP_DP_NONE ) + return( -1 ); + + if( ( profile->allowed_curves & MBEDTLS_X509_ID_FLAG( gid ) ) != 0 ) + return( 0 ); + + return( -1 ); + } +#endif + + return( -1 ); +} + +/* + * Like memcmp, but case-insensitive and always returns -1 if different + */ +static int x509_memcasecmp( const void *s1, const void *s2, size_t len ) +{ + size_t i; + unsigned char diff; + const unsigned char *n1 = s1, *n2 = s2; + + for( i = 0; i < len; i++ ) + { + diff = n1[i] ^ n2[i]; + + if( diff == 0 ) + continue; + + if( diff == 32 && + ( ( n1[i] >= 'a' && n1[i] <= 'z' ) || + ( n1[i] >= 'A' && n1[i] <= 'Z' ) ) ) + { + continue; + } + + return( -1 ); + } + + return( 0 ); +} + +/* + * Return 0 if name matches wildcard, -1 otherwise + */ +static int x509_check_wildcard( const char *cn, const mbedtls_x509_buf *name ) +{ + size_t i; + size_t cn_idx = 0, cn_len = strlen( cn ); + + /* We can't have a match if there is no wildcard to match */ + if( name->len < 3 || name->p[0] != '*' || name->p[1] != '.' ) + return( -1 ); + + for( i = 0; i < cn_len; ++i ) + { + if( cn[i] == '.' ) + { + cn_idx = i; + break; + } + } + + if( cn_idx == 0 ) + return( -1 ); + + if( cn_len - cn_idx == name->len - 1 && + x509_memcasecmp( name->p + 1, cn + cn_idx, name->len - 1 ) == 0 ) + { + return( 0 ); + } + + return( -1 ); +} + +/* + * Compare two X.509 strings, case-insensitive, and allowing for some encoding + * variations (but not all). + * + * Return 0 if equal, -1 otherwise. + */ +static int x509_string_cmp( const mbedtls_x509_buf *a, const mbedtls_x509_buf *b ) +{ + if( a->tag == b->tag && + a->len == b->len && + memcmp( a->p, b->p, b->len ) == 0 ) + { + return( 0 ); + } + + if( ( a->tag == MBEDTLS_ASN1_UTF8_STRING || a->tag == MBEDTLS_ASN1_PRINTABLE_STRING ) && + ( b->tag == MBEDTLS_ASN1_UTF8_STRING || b->tag == MBEDTLS_ASN1_PRINTABLE_STRING ) && + a->len == b->len && + x509_memcasecmp( a->p, b->p, b->len ) == 0 ) + { + return( 0 ); + } + + return( -1 ); +} + +/* + * Compare two X.509 Names (aka rdnSequence). + * + * See RFC 5280 section 7.1, though we don't implement the whole algorithm: + * we sometimes return unequal when the full algorithm would return equal, + * but never the other way. (In particular, we don't do Unicode normalisation + * or space folding.) + * + * Return 0 if equal, -1 otherwise. + */ +static int x509_name_cmp( const mbedtls_x509_name *a, const mbedtls_x509_name *b ) +{ + /* Avoid recursion, it might not be optimised by the compiler */ + while( a != NULL || b != NULL ) + { + if( a == NULL || b == NULL ) + return( -1 ); + + /* type */ + if( a->oid.tag != b->oid.tag || + a->oid.len != b->oid.len || + memcmp( a->oid.p, b->oid.p, b->oid.len ) != 0 ) + { + return( -1 ); + } + + /* value */ + if( x509_string_cmp( &a->val, &b->val ) != 0 ) + return( -1 ); + + /* structure of the list of sets */ + if( a->next_merged != b->next_merged ) + return( -1 ); + + a = a->next; + b = b->next; + } + + /* a == NULL == b */ + return( 0 ); +} + +/* + * Reset (init or clear) a verify_chain + */ +static void x509_crt_verify_chain_reset( + mbedtls_x509_crt_verify_chain *ver_chain ) +{ + size_t i; + + for( i = 0; i < MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE; i++ ) + { + ver_chain->items[i].crt = NULL; + ver_chain->items[i].flags = (uint32_t) -1; + } + + ver_chain->len = 0; +} + +/* + * Version ::= INTEGER { v1(0), v2(1), v3(2) } + */ +static int x509_get_version( unsigned char **p, + const unsigned char *end, + int *ver ) +{ + int ret; + size_t len; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | 0 ) ) != 0 ) + { + if( ret == MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + { + *ver = 0; + return( 0 ); + } + + return( MBEDTLS_ERR_X509_INVALID_FORMAT + ret ); + } + + end = *p + len; + + if( ( ret = mbedtls_asn1_get_int( p, end, ver ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_VERSION + ret ); + + if( *p != end ) + return( MBEDTLS_ERR_X509_INVALID_VERSION + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +/* + * Validity ::= SEQUENCE { + * notBefore Time, + * notAfter Time } + */ +static int x509_get_dates( unsigned char **p, + const unsigned char *end, + mbedtls_x509_time *from, + mbedtls_x509_time *to ) +{ + int ret; + size_t len; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_DATE + ret ); + + end = *p + len; + + if( ( ret = mbedtls_x509_get_time( p, end, from ) ) != 0 ) + return( ret ); + + if( ( ret = mbedtls_x509_get_time( p, end, to ) ) != 0 ) + return( ret ); + + if( *p != end ) + return( MBEDTLS_ERR_X509_INVALID_DATE + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +/* + * X.509 v2/v3 unique identifier (not parsed) + */ +static int x509_get_uid( unsigned char **p, + const unsigned char *end, + mbedtls_x509_buf *uid, int n ) +{ + int ret; + + if( *p == end ) + return( 0 ); + + uid->tag = **p; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &uid->len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | n ) ) != 0 ) + { + if( ret == MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + return( 0 ); + + return( MBEDTLS_ERR_X509_INVALID_FORMAT + ret ); + } + + uid->p = *p; + *p += uid->len; + + return( 0 ); +} + +static int x509_get_basic_constraints( unsigned char **p, + const unsigned char *end, + int *ca_istrue, + int *max_pathlen ) +{ + int ret; + size_t len; + + /* + * BasicConstraints ::= SEQUENCE { + * cA BOOLEAN DEFAULT FALSE, + * pathLenConstraint INTEGER (0..MAX) OPTIONAL } + */ + *ca_istrue = 0; /* DEFAULT FALSE */ + *max_pathlen = 0; /* endless */ + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + if( *p == end ) + return( 0 ); + + if( ( ret = mbedtls_asn1_get_bool( p, end, ca_istrue ) ) != 0 ) + { + if( ret == MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) + ret = mbedtls_asn1_get_int( p, end, ca_istrue ); + + if( ret != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + if( *ca_istrue != 0 ) + *ca_istrue = 1; + } + + if( *p == end ) + return( 0 ); + + if( ( ret = mbedtls_asn1_get_int( p, end, max_pathlen ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + if( *p != end ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + /* Do not accept max_pathlen equal to INT_MAX to avoid a signed integer + * overflow, which is an undefined behavior. */ + if( *max_pathlen == INT_MAX ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_INVALID_LENGTH ); + + (*max_pathlen)++; + + return( 0 ); +} + +static int x509_get_ns_cert_type( unsigned char **p, + const unsigned char *end, + unsigned char *ns_cert_type) +{ + int ret; + mbedtls_x509_bitstring bs = { 0, 0, NULL }; + + if( ( ret = mbedtls_asn1_get_bitstring( p, end, &bs ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + if( bs.len != 1 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_INVALID_LENGTH ); + + /* Get actual bitstring */ + *ns_cert_type = *bs.p; + return( 0 ); +} + +static int x509_get_key_usage( unsigned char **p, + const unsigned char *end, + unsigned int *key_usage) +{ + int ret; + size_t i; + mbedtls_x509_bitstring bs = { 0, 0, NULL }; + + if( ( ret = mbedtls_asn1_get_bitstring( p, end, &bs ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + if( bs.len < 1 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_INVALID_LENGTH ); + + /* Get actual bitstring */ + *key_usage = 0; + for( i = 0; i < bs.len && i < sizeof( unsigned int ); i++ ) + { + *key_usage |= (unsigned int) bs.p[i] << (8*i); + } + + return( 0 ); +} + +/* + * ExtKeyUsageSyntax ::= SEQUENCE SIZE (1..MAX) OF KeyPurposeId + * + * KeyPurposeId ::= OBJECT IDENTIFIER + */ +static int x509_get_ext_key_usage( unsigned char **p, + const unsigned char *end, + mbedtls_x509_sequence *ext_key_usage) +{ + int ret; + + if( ( ret = mbedtls_asn1_get_sequence_of( p, end, ext_key_usage, MBEDTLS_ASN1_OID ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + /* Sequence length must be >= 1 */ + if( ext_key_usage->buf.p == NULL ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_INVALID_LENGTH ); + + return( 0 ); +} + +/* + * SubjectAltName ::= GeneralNames + * + * GeneralNames ::= SEQUENCE SIZE (1..MAX) OF GeneralName + * + * GeneralName ::= CHOICE { + * otherName [0] OtherName, + * rfc822Name [1] IA5String, + * dNSName [2] IA5String, + * x400Address [3] ORAddress, + * directoryName [4] Name, + * ediPartyName [5] EDIPartyName, + * uniformResourceIdentifier [6] IA5String, + * iPAddress [7] OCTET STRING, + * registeredID [8] OBJECT IDENTIFIER } + * + * OtherName ::= SEQUENCE { + * type-id OBJECT IDENTIFIER, + * value [0] EXPLICIT ANY DEFINED BY type-id } + * + * EDIPartyName ::= SEQUENCE { + * nameAssigner [0] DirectoryString OPTIONAL, + * partyName [1] DirectoryString } + * + * NOTE: we only parse and use dNSName at this point. + */ +static int x509_get_subject_alt_name( unsigned char **p, + const unsigned char *end, + mbedtls_x509_sequence *subject_alt_name ) +{ + int ret; + size_t len, tag_len; + mbedtls_asn1_buf *buf; + unsigned char tag; + mbedtls_asn1_sequence *cur = subject_alt_name; + + /* Get main sequence tag */ + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + if( *p + len != end ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + while( *p < end ) + { + if( ( end - *p ) < 1 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_OUT_OF_DATA ); + + tag = **p; + (*p)++; + if( ( ret = mbedtls_asn1_get_len( p, end, &tag_len ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + if( ( tag & MBEDTLS_ASN1_TAG_CLASS_MASK ) != + MBEDTLS_ASN1_CONTEXT_SPECIFIC ) + { + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + } + + /* Skip everything but DNS name */ + if( tag != ( MBEDTLS_ASN1_CONTEXT_SPECIFIC | 2 ) ) + { + *p += tag_len; + continue; + } + + /* Allocate and assign next pointer */ + if( cur->buf.p != NULL ) + { + if( cur->next != NULL ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS ); + + cur->next = mbedtls_calloc( 1, sizeof( mbedtls_asn1_sequence ) ); + + if( cur->next == NULL ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_ALLOC_FAILED ); + + cur = cur->next; + } + + buf = &(cur->buf); + buf->tag = tag; + buf->p = *p; + buf->len = tag_len; + *p += buf->len; + } + + /* Set final sequence entry's next pointer to NULL */ + cur->next = NULL; + + if( *p != end ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +/* + * X.509 v3 extensions + * + */ +static int x509_get_crt_ext( unsigned char **p, + const unsigned char *end, + mbedtls_x509_crt *crt ) +{ + int ret; + size_t len; + unsigned char *end_ext_data, *end_ext_octet; + + if( *p == end ) + return( 0 ); + + if( ( ret = mbedtls_x509_get_ext( p, end, &crt->v3_ext, 3 ) ) != 0 ) + return( ret ); + + end = crt->v3_ext.p + crt->v3_ext.len; + while( *p < end ) + { + /* + * Extension ::= SEQUENCE { + * extnID OBJECT IDENTIFIER, + * critical BOOLEAN DEFAULT FALSE, + * extnValue OCTET STRING } + */ + mbedtls_x509_buf extn_oid = {0, 0, NULL}; + int is_critical = 0; /* DEFAULT FALSE */ + int ext_type = 0; + + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + end_ext_data = *p + len; + + /* Get extension ID */ + if( ( ret = mbedtls_asn1_get_tag( p, end_ext_data, &extn_oid.len, + MBEDTLS_ASN1_OID ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + extn_oid.tag = MBEDTLS_ASN1_OID; + extn_oid.p = *p; + *p += extn_oid.len; + + /* Get optional critical */ + if( ( ret = mbedtls_asn1_get_bool( p, end_ext_data, &is_critical ) ) != 0 && + ( ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ) ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + /* Data should be octet string type */ + if( ( ret = mbedtls_asn1_get_tag( p, end_ext_data, &len, + MBEDTLS_ASN1_OCTET_STRING ) ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); + + end_ext_octet = *p + len; + + if( end_ext_octet != end_ext_data ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + /* + * Detect supported extensions + */ + ret = mbedtls_oid_get_x509_ext_type( &extn_oid, &ext_type ); + + if( ret != 0 ) + { + /* No parser found, skip extension */ + *p = end_ext_octet; + +#if !defined(MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION) + if( is_critical ) + { + /* Data is marked as critical: fail */ + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + } +#endif + continue; + } + + /* Forbid repeated extensions */ + if( ( crt->ext_types & ext_type ) != 0 ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS ); + + crt->ext_types |= ext_type; + + switch( ext_type ) + { + case MBEDTLS_X509_EXT_BASIC_CONSTRAINTS: + /* Parse basic constraints */ + if( ( ret = x509_get_basic_constraints( p, end_ext_octet, + &crt->ca_istrue, &crt->max_pathlen ) ) != 0 ) + return( ret ); + break; + + case MBEDTLS_X509_EXT_KEY_USAGE: + /* Parse key usage */ + if( ( ret = x509_get_key_usage( p, end_ext_octet, + &crt->key_usage ) ) != 0 ) + return( ret ); + break; + + case MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE: + /* Parse extended key usage */ + if( ( ret = x509_get_ext_key_usage( p, end_ext_octet, + &crt->ext_key_usage ) ) != 0 ) + return( ret ); + break; + + case MBEDTLS_X509_EXT_SUBJECT_ALT_NAME: + /* Parse subject alt name */ + if( ( ret = x509_get_subject_alt_name( p, end_ext_octet, + &crt->subject_alt_names ) ) != 0 ) + return( ret ); + break; + + case MBEDTLS_X509_EXT_NS_CERT_TYPE: + /* Parse netscape certificate type */ + if( ( ret = x509_get_ns_cert_type( p, end_ext_octet, + &crt->ns_cert_type ) ) != 0 ) + return( ret ); + break; + + default: + return( MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE ); + } + } + + if( *p != end ) + return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + return( 0 ); +} + +/* + * Parse and fill a single X.509 certificate in DER format + */ +static int x509_crt_parse_der_core( mbedtls_x509_crt *crt, const unsigned char *buf, + size_t buflen ) +{ + int ret; + size_t len; + unsigned char *p, *end, *crt_end; + mbedtls_x509_buf sig_params1, sig_params2, sig_oid2; + + memset( &sig_params1, 0, sizeof( mbedtls_x509_buf ) ); + memset( &sig_params2, 0, sizeof( mbedtls_x509_buf ) ); + memset( &sig_oid2, 0, sizeof( mbedtls_x509_buf ) ); + + /* + * Check for valid input + */ + if( crt == NULL || buf == NULL ) + return( MBEDTLS_ERR_X509_BAD_INPUT_DATA ); + + // Use the original buffer until we figure out actual length + p = (unsigned char*) buf; + len = buflen; + end = p + len; + + /* + * Certificate ::= SEQUENCE { + * tbsCertificate TBSCertificate, + * signatureAlgorithm AlgorithmIdentifier, + * signatureValue BIT STRING } + */ + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_INVALID_FORMAT ); + } + + if( len > (size_t) ( end - p ) ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + } + crt_end = p + len; + + // Create and populate a new buffer for the raw field + crt->raw.len = crt_end - buf; + crt->raw.p = p = mbedtls_calloc( 1, crt->raw.len ); + if( p == NULL ) + return( MBEDTLS_ERR_X509_ALLOC_FAILED ); + + memcpy( p, buf, crt->raw.len ); + + // Direct pointers to the new buffer + p += crt->raw.len - len; + end = crt_end = p + len; + + /* + * TBSCertificate ::= SEQUENCE { + */ + crt->tbs.p = p; + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_INVALID_FORMAT + ret ); + } + + end = p + len; + crt->tbs.len = end - crt->tbs.p; + + /* + * Version ::= INTEGER { v1(0), v2(1), v3(2) } + * + * CertificateSerialNumber ::= INTEGER + * + * signature AlgorithmIdentifier + */ + if( ( ret = x509_get_version( &p, end, &crt->version ) ) != 0 || + ( ret = mbedtls_x509_get_serial( &p, end, &crt->serial ) ) != 0 || + ( ret = mbedtls_x509_get_alg( &p, end, &crt->sig_oid, + &sig_params1 ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + + if( crt->version < 0 || crt->version > 2 ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_UNKNOWN_VERSION ); + } + + crt->version++; + + if( ( ret = mbedtls_x509_get_sig_alg( &crt->sig_oid, &sig_params1, + &crt->sig_md, &crt->sig_pk, + &crt->sig_opts ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + + /* + * issuer Name + */ + crt->issuer_raw.p = p; + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_INVALID_FORMAT + ret ); + } + + if( ( ret = mbedtls_x509_get_name( &p, p + len, &crt->issuer ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + + crt->issuer_raw.len = p - crt->issuer_raw.p; + + /* + * Validity ::= SEQUENCE { + * notBefore Time, + * notAfter Time } + * + */ + if( ( ret = x509_get_dates( &p, end, &crt->valid_from, + &crt->valid_to ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + + /* + * subject Name + */ + crt->subject_raw.p = p; + + if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_INVALID_FORMAT + ret ); + } + + if( len && ( ret = mbedtls_x509_get_name( &p, p + len, &crt->subject ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + + crt->subject_raw.len = p - crt->subject_raw.p; + + /* + * SubjectPublicKeyInfo + */ + if( ( ret = mbedtls_pk_parse_subpubkey( &p, end, &crt->pk ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + + /* + * issuerUniqueID [1] IMPLICIT UniqueIdentifier OPTIONAL, + * -- If present, version shall be v2 or v3 + * subjectUniqueID [2] IMPLICIT UniqueIdentifier OPTIONAL, + * -- If present, version shall be v2 or v3 + * extensions [3] EXPLICIT Extensions OPTIONAL + * -- If present, version shall be v3 + */ + if( crt->version == 2 || crt->version == 3 ) + { + ret = x509_get_uid( &p, end, &crt->issuer_id, 1 ); + if( ret != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + } + + if( crt->version == 2 || crt->version == 3 ) + { + ret = x509_get_uid( &p, end, &crt->subject_id, 2 ); + if( ret != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + } + +#if !defined(MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3) + if( crt->version == 3 ) +#endif + { + ret = x509_get_crt_ext( &p, end, crt ); + if( ret != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + } + + if( p != end ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + } + + end = crt_end; + + /* + * } + * -- end of TBSCertificate + * + * signatureAlgorithm AlgorithmIdentifier, + * signatureValue BIT STRING + */ + if( ( ret = mbedtls_x509_get_alg( &p, end, &sig_oid2, &sig_params2 ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + + if( crt->sig_oid.len != sig_oid2.len || + memcmp( crt->sig_oid.p, sig_oid2.p, crt->sig_oid.len ) != 0 || + sig_params1.tag != sig_params2.tag || + sig_params1.len != sig_params2.len || + ( sig_params1.len != 0 && + memcmp( sig_params1.p, sig_params2.p, sig_params1.len ) != 0 ) ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_SIG_MISMATCH ); + } + + if( ( ret = mbedtls_x509_get_sig( &p, end, &crt->sig ) ) != 0 ) + { + mbedtls_x509_crt_free( crt ); + return( ret ); + } + + if( p != end ) + { + mbedtls_x509_crt_free( crt ); + return( MBEDTLS_ERR_X509_INVALID_FORMAT + + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + } + + return( 0 ); +} + +/* + * Parse one X.509 certificate in DER format from a buffer and add them to a + * chained list + */ +int mbedtls_x509_crt_parse_der( mbedtls_x509_crt *chain, const unsigned char *buf, + size_t buflen ) +{ + int ret; + mbedtls_x509_crt *crt = chain, *prev = NULL; + + /* + * Check for valid input + */ + if( crt == NULL || buf == NULL ) + return( MBEDTLS_ERR_X509_BAD_INPUT_DATA ); + + while( crt->version != 0 && crt->next != NULL ) + { + prev = crt; + crt = crt->next; + } + + /* + * Add new certificate on the end of the chain if needed. + */ + if( crt->version != 0 && crt->next == NULL ) + { + crt->next = mbedtls_calloc( 1, sizeof( mbedtls_x509_crt ) ); + + if( crt->next == NULL ) + return( MBEDTLS_ERR_X509_ALLOC_FAILED ); + + prev = crt; + mbedtls_x509_crt_init( crt->next ); + crt = crt->next; + } + + if( ( ret = x509_crt_parse_der_core( crt, buf, buflen ) ) != 0 ) + { + if( prev ) + prev->next = NULL; + + if( crt != chain ) + mbedtls_free( crt ); + + return( ret ); + } + + return( 0 ); +} + +/* + * Parse one or more PEM certificates from a buffer and add them to the chained + * list + */ +int mbedtls_x509_crt_parse( mbedtls_x509_crt *chain, const unsigned char *buf, size_t buflen ) +{ +#if defined(MBEDTLS_PEM_PARSE_C) + int success = 0, first_error = 0, total_failed = 0; + int buf_format = MBEDTLS_X509_FORMAT_DER; +#endif + + /* + * Check for valid input + */ + if( chain == NULL || buf == NULL ) + return( MBEDTLS_ERR_X509_BAD_INPUT_DATA ); + + /* + * Determine buffer content. Buffer contains either one DER certificate or + * one or more PEM certificates. + */ +#if defined(MBEDTLS_PEM_PARSE_C) + if( buflen != 0 && buf[buflen - 1] == '\0' && + strstr( (const char *) buf, "-----BEGIN CERTIFICATE-----" ) != NULL ) + { + buf_format = MBEDTLS_X509_FORMAT_PEM; + } + + if( buf_format == MBEDTLS_X509_FORMAT_DER ) + return mbedtls_x509_crt_parse_der( chain, buf, buflen ); +#else + return mbedtls_x509_crt_parse_der( chain, buf, buflen ); +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) + if( buf_format == MBEDTLS_X509_FORMAT_PEM ) + { + int ret; + mbedtls_pem_context pem; + + /* 1 rather than 0 since the terminating NULL byte is counted in */ + while( buflen > 1 ) + { + size_t use_len; + mbedtls_pem_init( &pem ); + + /* If we get there, we know the string is null-terminated */ + ret = mbedtls_pem_read_buffer( &pem, + "-----BEGIN CERTIFICATE-----", + "-----END CERTIFICATE-----", + buf, NULL, 0, &use_len ); + + if( ret == 0 ) + { + /* + * Was PEM encoded + */ + buflen -= use_len; + buf += use_len; + } + else if( ret == MBEDTLS_ERR_PEM_BAD_INPUT_DATA ) + { + return( ret ); + } + else if( ret != MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT ) + { + mbedtls_pem_free( &pem ); + + /* + * PEM header and footer were found + */ + buflen -= use_len; + buf += use_len; + + if( first_error == 0 ) + first_error = ret; + + total_failed++; + continue; + } + else + break; + + ret = mbedtls_x509_crt_parse_der( chain, pem.buf, pem.buflen ); + + mbedtls_pem_free( &pem ); + + if( ret != 0 ) + { + /* + * Quit parsing on a memory error + */ + if( ret == MBEDTLS_ERR_X509_ALLOC_FAILED ) + return( ret ); + + if( first_error == 0 ) + first_error = ret; + + total_failed++; + continue; + } + + success = 1; + } + } + + if( success ) + return( total_failed ); + else if( first_error ) + return( first_error ); + else + return( MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT ); +#endif /* MBEDTLS_PEM_PARSE_C */ +} + +#if defined(MBEDTLS_FS_IO) +/* + * Load one or more certificates and add them to the chained list + */ +int mbedtls_x509_crt_parse_file( mbedtls_x509_crt *chain, const char *path ) +{ + int ret; + size_t n; + unsigned char *buf; + + if( ( ret = mbedtls_pk_load_file( path, &buf, &n ) ) != 0 ) + return( ret ); + + ret = mbedtls_x509_crt_parse( chain, buf, n ); + + mbedtls_platform_zeroize( buf, n ); + mbedtls_free( buf ); + + return( ret ); +} + +int mbedtls_x509_crt_parse_path( mbedtls_x509_crt *chain, const char *path ) +{ + int ret = 0; + int t_ret; + int snp_ret; + struct stat sb; + struct dirent *entry; + char entry_name[MBEDTLS_X509_MAX_FILE_PATH_LEN]; + DIR *dir = opendir( path ); + + if( dir == NULL ) + return( MBEDTLS_ERR_X509_FILE_IO_ERROR ); + +#if defined(MBEDTLS_THREADING_C) + if( ( ret = mbedtls_mutex_lock( &mbedtls_threading_readdir_mutex ) ) != 0 ) + { + closedir( dir ); + return( ret ); + } +#endif /* MBEDTLS_THREADING_C */ + + while( ( entry = readdir( dir ) ) != NULL ) + { + snp_ret = mbedtls_snprintf( entry_name, sizeof entry_name, + "%s/%s", path, entry->d_name ); + + if( snp_ret < 0 || (size_t)snp_ret >= sizeof entry_name ) + { + ret = MBEDTLS_ERR_X509_BUFFER_TOO_SMALL; + goto cleanup; + } + else if( stat( entry_name, &sb ) == -1 ) + { + ret = MBEDTLS_ERR_X509_FILE_IO_ERROR; + goto cleanup; + } + + if( !S_ISREG( sb.st_mode ) ) + continue; + + // Ignore parse errors + // + t_ret = mbedtls_x509_crt_parse_file( chain, entry_name ); + if( t_ret < 0 ) + ret++; + else + ret += t_ret; + } + +cleanup: + closedir( dir ); + +#if defined(MBEDTLS_THREADING_C) + if( mbedtls_mutex_unlock( &mbedtls_threading_readdir_mutex ) != 0 ) + ret = MBEDTLS_ERR_THREADING_MUTEX_ERROR; +#endif /* MBEDTLS_THREADING_C */ + + return( ret ); +} +#endif /* MBEDTLS_FS_IO */ + +static int x509_info_subject_alt_name( char **buf, size_t *size, + const mbedtls_x509_sequence *subject_alt_name ) +{ + size_t i; + size_t n = *size; + char *p = *buf; + const mbedtls_x509_sequence *cur = subject_alt_name; + const char *sep = ""; + size_t sep_len = 0; + + while( cur != NULL ) + { + if( cur->buf.len + sep_len >= n ) + { + *p = '\0'; + return( MBEDTLS_ERR_X509_BUFFER_TOO_SMALL ); + } + + n -= cur->buf.len + sep_len; + for( i = 0; i < sep_len; i++ ) + *p++ = sep[i]; + for( i = 0; i < cur->buf.len; i++ ) + *p++ = cur->buf.p[i]; + + sep = ", "; + sep_len = 2; + + cur = cur->next; + } + + *p = '\0'; + + *size = n; + *buf = p; + + return( 0 ); +} + +#define PRINT_ITEM(i) \ + { \ + ret = mbedtls_snprintf( p, n, "%s" i, sep ); \ + MBEDTLS_X509_SAFE_SNPRINTF; \ + sep = ", "; \ + } + +#define CERT_TYPE(type,name) \ + if( ns_cert_type & (type) ) \ + PRINT_ITEM( name ); + +static int x509_info_cert_type( char **buf, size_t *size, + unsigned char ns_cert_type ) +{ + int ret; + size_t n = *size; + char *p = *buf; + const char *sep = ""; + + CERT_TYPE( MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT, "SSL Client" ); + CERT_TYPE( MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER, "SSL Server" ); + CERT_TYPE( MBEDTLS_X509_NS_CERT_TYPE_EMAIL, "Email" ); + CERT_TYPE( MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING, "Object Signing" ); + CERT_TYPE( MBEDTLS_X509_NS_CERT_TYPE_RESERVED, "Reserved" ); + CERT_TYPE( MBEDTLS_X509_NS_CERT_TYPE_SSL_CA, "SSL CA" ); + CERT_TYPE( MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA, "Email CA" ); + CERT_TYPE( MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA, "Object Signing CA" ); + + *size = n; + *buf = p; + + return( 0 ); +} + +#define KEY_USAGE(code,name) \ + if( key_usage & (code) ) \ + PRINT_ITEM( name ); + +static int x509_info_key_usage( char **buf, size_t *size, + unsigned int key_usage ) +{ + int ret; + size_t n = *size; + char *p = *buf; + const char *sep = ""; + + KEY_USAGE( MBEDTLS_X509_KU_DIGITAL_SIGNATURE, "Digital Signature" ); + KEY_USAGE( MBEDTLS_X509_KU_NON_REPUDIATION, "Non Repudiation" ); + KEY_USAGE( MBEDTLS_X509_KU_KEY_ENCIPHERMENT, "Key Encipherment" ); + KEY_USAGE( MBEDTLS_X509_KU_DATA_ENCIPHERMENT, "Data Encipherment" ); + KEY_USAGE( MBEDTLS_X509_KU_KEY_AGREEMENT, "Key Agreement" ); + KEY_USAGE( MBEDTLS_X509_KU_KEY_CERT_SIGN, "Key Cert Sign" ); + KEY_USAGE( MBEDTLS_X509_KU_CRL_SIGN, "CRL Sign" ); + KEY_USAGE( MBEDTLS_X509_KU_ENCIPHER_ONLY, "Encipher Only" ); + KEY_USAGE( MBEDTLS_X509_KU_DECIPHER_ONLY, "Decipher Only" ); + + *size = n; + *buf = p; + + return( 0 ); +} + +static int x509_info_ext_key_usage( char **buf, size_t *size, + const mbedtls_x509_sequence *extended_key_usage ) +{ + int ret; + const char *desc; + size_t n = *size; + char *p = *buf; + const mbedtls_x509_sequence *cur = extended_key_usage; + const char *sep = ""; + + while( cur != NULL ) + { + if( mbedtls_oid_get_extended_key_usage( &cur->buf, &desc ) != 0 ) + desc = "???"; + + ret = mbedtls_snprintf( p, n, "%s%s", sep, desc ); + MBEDTLS_X509_SAFE_SNPRINTF; + + sep = ", "; + + cur = cur->next; + } + + *size = n; + *buf = p; + + return( 0 ); +} + +/* + * Return an informational string about the certificate. + */ +#define BEFORE_COLON 18 +#define BC "18" +int mbedtls_x509_crt_info( char *buf, size_t size, const char *prefix, + const mbedtls_x509_crt *crt ) +{ + int ret; + size_t n; + char *p; + char key_size_str[BEFORE_COLON]; + + p = buf; + n = size; + + if( NULL == crt ) + { + ret = mbedtls_snprintf( p, n, "\nCertificate is uninitialised!\n" ); + MBEDTLS_X509_SAFE_SNPRINTF; + + return( (int) ( size - n ) ); + } + + ret = mbedtls_snprintf( p, n, "%scert. version : %d\n", + prefix, crt->version ); + MBEDTLS_X509_SAFE_SNPRINTF; + ret = mbedtls_snprintf( p, n, "%sserial number : ", + prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + + ret = mbedtls_x509_serial_gets( p, n, &crt->serial ); + MBEDTLS_X509_SAFE_SNPRINTF; + + ret = mbedtls_snprintf( p, n, "\n%sissuer name : ", prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + ret = mbedtls_x509_dn_gets( p, n, &crt->issuer ); + MBEDTLS_X509_SAFE_SNPRINTF; + + ret = mbedtls_snprintf( p, n, "\n%ssubject name : ", prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + ret = mbedtls_x509_dn_gets( p, n, &crt->subject ); + MBEDTLS_X509_SAFE_SNPRINTF; + + ret = mbedtls_snprintf( p, n, "\n%sissued on : " \ + "%04d-%02d-%02d %02d:%02d:%02d", prefix, + crt->valid_from.year, crt->valid_from.mon, + crt->valid_from.day, crt->valid_from.hour, + crt->valid_from.min, crt->valid_from.sec ); + MBEDTLS_X509_SAFE_SNPRINTF; + + ret = mbedtls_snprintf( p, n, "\n%sexpires on : " \ + "%04d-%02d-%02d %02d:%02d:%02d", prefix, + crt->valid_to.year, crt->valid_to.mon, + crt->valid_to.day, crt->valid_to.hour, + crt->valid_to.min, crt->valid_to.sec ); + MBEDTLS_X509_SAFE_SNPRINTF; + + ret = mbedtls_snprintf( p, n, "\n%ssigned using : ", prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + + ret = mbedtls_x509_sig_alg_gets( p, n, &crt->sig_oid, crt->sig_pk, + crt->sig_md, crt->sig_opts ); + MBEDTLS_X509_SAFE_SNPRINTF; + + /* Key size */ + if( ( ret = mbedtls_x509_key_size_helper( key_size_str, BEFORE_COLON, + mbedtls_pk_get_name( &crt->pk ) ) ) != 0 ) + { + return( ret ); + } + + ret = mbedtls_snprintf( p, n, "\n%s%-" BC "s: %d bits", prefix, key_size_str, + (int) mbedtls_pk_get_bitlen( &crt->pk ) ); + MBEDTLS_X509_SAFE_SNPRINTF; + + /* + * Optional extensions + */ + + if( crt->ext_types & MBEDTLS_X509_EXT_BASIC_CONSTRAINTS ) + { + ret = mbedtls_snprintf( p, n, "\n%sbasic constraints : CA=%s", prefix, + crt->ca_istrue ? "true" : "false" ); + MBEDTLS_X509_SAFE_SNPRINTF; + + if( crt->max_pathlen > 0 ) + { + ret = mbedtls_snprintf( p, n, ", max_pathlen=%d", crt->max_pathlen - 1 ); + MBEDTLS_X509_SAFE_SNPRINTF; + } + } + + if( crt->ext_types & MBEDTLS_X509_EXT_SUBJECT_ALT_NAME ) + { + ret = mbedtls_snprintf( p, n, "\n%ssubject alt name : ", prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + + if( ( ret = x509_info_subject_alt_name( &p, &n, + &crt->subject_alt_names ) ) != 0 ) + return( ret ); + } + + if( crt->ext_types & MBEDTLS_X509_EXT_NS_CERT_TYPE ) + { + ret = mbedtls_snprintf( p, n, "\n%scert. type : ", prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + + if( ( ret = x509_info_cert_type( &p, &n, crt->ns_cert_type ) ) != 0 ) + return( ret ); + } + + if( crt->ext_types & MBEDTLS_X509_EXT_KEY_USAGE ) + { + ret = mbedtls_snprintf( p, n, "\n%skey usage : ", prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + + if( ( ret = x509_info_key_usage( &p, &n, crt->key_usage ) ) != 0 ) + return( ret ); + } + + if( crt->ext_types & MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE ) + { + ret = mbedtls_snprintf( p, n, "\n%sext key usage : ", prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + + if( ( ret = x509_info_ext_key_usage( &p, &n, + &crt->ext_key_usage ) ) != 0 ) + return( ret ); + } + + ret = mbedtls_snprintf( p, n, "\n" ); + MBEDTLS_X509_SAFE_SNPRINTF; + + return( (int) ( size - n ) ); +} + +struct x509_crt_verify_string { + int code; + const char *string; +}; + +static const struct x509_crt_verify_string x509_crt_verify_strings[] = { + { MBEDTLS_X509_BADCERT_EXPIRED, "The certificate validity has expired" }, + { MBEDTLS_X509_BADCERT_REVOKED, "The certificate has been revoked (is on a CRL)" }, + { MBEDTLS_X509_BADCERT_CN_MISMATCH, "The certificate Common Name (CN) does not match with the expected CN" }, + { MBEDTLS_X509_BADCERT_NOT_TRUSTED, "The certificate is not correctly signed by the trusted CA" }, + { MBEDTLS_X509_BADCRL_NOT_TRUSTED, "The CRL is not correctly signed by the trusted CA" }, + { MBEDTLS_X509_BADCRL_EXPIRED, "The CRL is expired" }, + { MBEDTLS_X509_BADCERT_MISSING, "Certificate was missing" }, + { MBEDTLS_X509_BADCERT_SKIP_VERIFY, "Certificate verification was skipped" }, + { MBEDTLS_X509_BADCERT_OTHER, "Other reason (can be used by verify callback)" }, + { MBEDTLS_X509_BADCERT_FUTURE, "The certificate validity starts in the future" }, + { MBEDTLS_X509_BADCRL_FUTURE, "The CRL is from the future" }, + { MBEDTLS_X509_BADCERT_KEY_USAGE, "Usage does not match the keyUsage extension" }, + { MBEDTLS_X509_BADCERT_EXT_KEY_USAGE, "Usage does not match the extendedKeyUsage extension" }, + { MBEDTLS_X509_BADCERT_NS_CERT_TYPE, "Usage does not match the nsCertType extension" }, + { MBEDTLS_X509_BADCERT_BAD_MD, "The certificate is signed with an unacceptable hash." }, + { MBEDTLS_X509_BADCERT_BAD_PK, "The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA)." }, + { MBEDTLS_X509_BADCERT_BAD_KEY, "The certificate is signed with an unacceptable key (eg bad curve, RSA too short)." }, + { MBEDTLS_X509_BADCRL_BAD_MD, "The CRL is signed with an unacceptable hash." }, + { MBEDTLS_X509_BADCRL_BAD_PK, "The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA)." }, + { MBEDTLS_X509_BADCRL_BAD_KEY, "The CRL is signed with an unacceptable key (eg bad curve, RSA too short)." }, + { 0, NULL } +}; + +int mbedtls_x509_crt_verify_info( char *buf, size_t size, const char *prefix, + uint32_t flags ) +{ + int ret; + const struct x509_crt_verify_string *cur; + char *p = buf; + size_t n = size; + + for( cur = x509_crt_verify_strings; cur->string != NULL ; cur++ ) + { + if( ( flags & cur->code ) == 0 ) + continue; + + ret = mbedtls_snprintf( p, n, "%s%s\n", prefix, cur->string ); + MBEDTLS_X509_SAFE_SNPRINTF; + flags ^= cur->code; + } + + if( flags != 0 ) + { + ret = mbedtls_snprintf( p, n, "%sUnknown reason " + "(this should not happen)\n", prefix ); + MBEDTLS_X509_SAFE_SNPRINTF; + } + + return( (int) ( size - n ) ); +} + +#if defined(MBEDTLS_X509_CHECK_KEY_USAGE) +int mbedtls_x509_crt_check_key_usage( const mbedtls_x509_crt *crt, + unsigned int usage ) +{ + unsigned int usage_must, usage_may; + unsigned int may_mask = MBEDTLS_X509_KU_ENCIPHER_ONLY + | MBEDTLS_X509_KU_DECIPHER_ONLY; + + if( ( crt->ext_types & MBEDTLS_X509_EXT_KEY_USAGE ) == 0 ) + return( 0 ); + + usage_must = usage & ~may_mask; + + if( ( ( crt->key_usage & ~may_mask ) & usage_must ) != usage_must ) + return( MBEDTLS_ERR_X509_BAD_INPUT_DATA ); + + usage_may = usage & may_mask; + + if( ( ( crt->key_usage & may_mask ) | usage_may ) != usage_may ) + return( MBEDTLS_ERR_X509_BAD_INPUT_DATA ); + + return( 0 ); +} +#endif + +#if defined(MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE) +int mbedtls_x509_crt_check_extended_key_usage( const mbedtls_x509_crt *crt, + const char *usage_oid, + size_t usage_len ) +{ + const mbedtls_x509_sequence *cur; + + /* Extension is not mandatory, absent means no restriction */ + if( ( crt->ext_types & MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE ) == 0 ) + return( 0 ); + + /* + * Look for the requested usage (or wildcard ANY) in our list + */ + for( cur = &crt->ext_key_usage; cur != NULL; cur = cur->next ) + { + const mbedtls_x509_buf *cur_oid = &cur->buf; + + if( cur_oid->len == usage_len && + memcmp( cur_oid->p, usage_oid, usage_len ) == 0 ) + { + return( 0 ); + } + + if( MBEDTLS_OID_CMP( MBEDTLS_OID_ANY_EXTENDED_KEY_USAGE, cur_oid ) == 0 ) + return( 0 ); + } + + return( MBEDTLS_ERR_X509_BAD_INPUT_DATA ); +} +#endif /* MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE */ + +#if defined(MBEDTLS_X509_CRL_PARSE_C) +/* + * Return 1 if the certificate is revoked, or 0 otherwise. + */ +int mbedtls_x509_crt_is_revoked( const mbedtls_x509_crt *crt, const mbedtls_x509_crl *crl ) +{ + const mbedtls_x509_crl_entry *cur = &crl->entry; + + while( cur != NULL && cur->serial.len != 0 ) + { + if( crt->serial.len == cur->serial.len && + memcmp( crt->serial.p, cur->serial.p, crt->serial.len ) == 0 ) + { + return( 1 ); + } + + cur = cur->next; + } + + return( 0 ); +} + +/* + * Check that the given certificate is not revoked according to the CRL. + * Skip validation if no CRL for the given CA is present. + */ +static int x509_crt_verifycrl( mbedtls_x509_crt *crt, mbedtls_x509_crt *ca, + mbedtls_x509_crl *crl_list, + const mbedtls_x509_crt_profile *profile ) +{ + int flags = 0; + unsigned char hash[MBEDTLS_MD_MAX_SIZE]; + const mbedtls_md_info_t *md_info; + + if( ca == NULL ) + return( flags ); + + while( crl_list != NULL ) + { + if( crl_list->version == 0 || + x509_name_cmp( &crl_list->issuer, &ca->subject ) != 0 ) + { + crl_list = crl_list->next; + continue; + } + + /* + * Check if the CA is configured to sign CRLs + */ +#if defined(MBEDTLS_X509_CHECK_KEY_USAGE) + if( mbedtls_x509_crt_check_key_usage( ca, + MBEDTLS_X509_KU_CRL_SIGN ) != 0 ) + { + flags |= MBEDTLS_X509_BADCRL_NOT_TRUSTED; + break; + } +#endif + + /* + * Check if CRL is correctly signed by the trusted CA + */ + if( x509_profile_check_md_alg( profile, crl_list->sig_md ) != 0 ) + flags |= MBEDTLS_X509_BADCRL_BAD_MD; + + if( x509_profile_check_pk_alg( profile, crl_list->sig_pk ) != 0 ) + flags |= MBEDTLS_X509_BADCRL_BAD_PK; + + md_info = mbedtls_md_info_from_type( crl_list->sig_md ); + if( mbedtls_md( md_info, crl_list->tbs.p, crl_list->tbs.len, hash ) != 0 ) + { + /* Note: this can't happen except after an internal error */ + flags |= MBEDTLS_X509_BADCRL_NOT_TRUSTED; + break; + } + + if( x509_profile_check_key( profile, &ca->pk ) != 0 ) + flags |= MBEDTLS_X509_BADCERT_BAD_KEY; + + if( mbedtls_pk_verify_ext( crl_list->sig_pk, crl_list->sig_opts, &ca->pk, + crl_list->sig_md, hash, mbedtls_md_get_size( md_info ), + crl_list->sig.p, crl_list->sig.len ) != 0 ) + { + flags |= MBEDTLS_X509_BADCRL_NOT_TRUSTED; + break; + } + + /* + * Check for validity of CRL (Do not drop out) + */ + if( mbedtls_x509_time_is_past( &crl_list->next_update ) ) + flags |= MBEDTLS_X509_BADCRL_EXPIRED; + + if( mbedtls_x509_time_is_future( &crl_list->this_update ) ) + flags |= MBEDTLS_X509_BADCRL_FUTURE; + + /* + * Check if certificate is revoked + */ + if( mbedtls_x509_crt_is_revoked( crt, crl_list ) ) + { + flags |= MBEDTLS_X509_BADCERT_REVOKED; + break; + } + + crl_list = crl_list->next; + } + + return( flags ); +} +#endif /* MBEDTLS_X509_CRL_PARSE_C */ + +/* + * Check the signature of a certificate by its parent + */ +static int x509_crt_check_signature( const mbedtls_x509_crt *child, + mbedtls_x509_crt *parent, + mbedtls_x509_crt_restart_ctx *rs_ctx ) +{ + const mbedtls_md_info_t *md_info; + unsigned char hash[MBEDTLS_MD_MAX_SIZE]; + + md_info = mbedtls_md_info_from_type( child->sig_md ); + if( mbedtls_md( md_info, child->tbs.p, child->tbs.len, hash ) != 0 ) + { + /* Note: this can't happen except after an internal error */ + return( -1 ); + } + + /* Skip expensive computation on obvious mismatch */ + if( ! mbedtls_pk_can_do( &parent->pk, child->sig_pk ) ) + return( -1 ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && child->sig_pk == MBEDTLS_PK_ECDSA ) + { + return( mbedtls_pk_verify_restartable( &parent->pk, + child->sig_md, hash, mbedtls_md_get_size( md_info ), + child->sig.p, child->sig.len, &rs_ctx->pk ) ); + } +#else + (void) rs_ctx; +#endif + + return( mbedtls_pk_verify_ext( child->sig_pk, child->sig_opts, &parent->pk, + child->sig_md, hash, mbedtls_md_get_size( md_info ), + child->sig.p, child->sig.len ) ); +} + +/* + * Check if 'parent' is a suitable parent (signing CA) for 'child'. + * Return 0 if yes, -1 if not. + * + * top means parent is a locally-trusted certificate + */ +static int x509_crt_check_parent( const mbedtls_x509_crt *child, + const mbedtls_x509_crt *parent, + int top ) +{ + int need_ca_bit; + + /* Parent must be the issuer */ + if( x509_name_cmp( &child->issuer, &parent->subject ) != 0 ) + return( -1 ); + + /* Parent must have the basicConstraints CA bit set as a general rule */ + need_ca_bit = 1; + + /* Exception: v1/v2 certificates that are locally trusted. */ + if( top && parent->version < 3 ) + need_ca_bit = 0; + + if( need_ca_bit && ! parent->ca_istrue ) + return( -1 ); + +#if defined(MBEDTLS_X509_CHECK_KEY_USAGE) + if( need_ca_bit && + mbedtls_x509_crt_check_key_usage( parent, MBEDTLS_X509_KU_KEY_CERT_SIGN ) != 0 ) + { + return( -1 ); + } +#endif + + return( 0 ); +} + +/* + * Find a suitable parent for child in candidates, or return NULL. + * + * Here suitable is defined as: + * 1. subject name matches child's issuer + * 2. if necessary, the CA bit is set and key usage allows signing certs + * 3. for trusted roots, the signature is correct + * (for intermediates, the signature is checked and the result reported) + * 4. pathlen constraints are satisfied + * + * If there's a suitable candidate which is also time-valid, return the first + * such. Otherwise, return the first suitable candidate (or NULL if there is + * none). + * + * The rationale for this rule is that someone could have a list of trusted + * roots with two versions on the same root with different validity periods. + * (At least one user reported having such a list and wanted it to just work.) + * The reason we don't just require time-validity is that generally there is + * only one version, and if it's expired we want the flags to state that + * rather than NOT_TRUSTED, as would be the case if we required it here. + * + * The rationale for rule 3 (signature for trusted roots) is that users might + * have two versions of the same CA with different keys in their list, and the + * way we select the correct one is by checking the signature (as we don't + * rely on key identifier extensions). (This is one way users might choose to + * handle key rollover, another relies on self-issued certs, see [SIRO].) + * + * Arguments: + * - [in] child: certificate for which we're looking for a parent + * - [in] candidates: chained list of potential parents + * - [out] r_parent: parent found (or NULL) + * - [out] r_signature_is_good: 1 if child signature by parent is valid, or 0 + * - [in] top: 1 if candidates consists of trusted roots, ie we're at the top + * of the chain, 0 otherwise + * - [in] path_cnt: number of intermediates seen so far + * - [in] self_cnt: number of self-signed intermediates seen so far + * (will never be greater than path_cnt) + * - [in-out] rs_ctx: context for restarting operations + * + * Return value: + * - 0 on success + * - MBEDTLS_ERR_ECP_IN_PROGRESS otherwise + */ +static int x509_crt_find_parent_in( + mbedtls_x509_crt *child, + mbedtls_x509_crt *candidates, + mbedtls_x509_crt **r_parent, + int *r_signature_is_good, + int top, + unsigned path_cnt, + unsigned self_cnt, + mbedtls_x509_crt_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_x509_crt *parent, *fallback_parent; + int signature_is_good, fallback_signature_is_good; + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /* did we have something in progress? */ + if( rs_ctx != NULL && rs_ctx->parent != NULL ) + { + /* restore saved state */ + parent = rs_ctx->parent; + fallback_parent = rs_ctx->fallback_parent; + fallback_signature_is_good = rs_ctx->fallback_signature_is_good; + + /* clear saved state */ + rs_ctx->parent = NULL; + rs_ctx->fallback_parent = NULL; + rs_ctx->fallback_signature_is_good = 0; + + /* resume where we left */ + goto check_signature; + } +#endif + + fallback_parent = NULL; + fallback_signature_is_good = 0; + + for( parent = candidates; parent != NULL; parent = parent->next ) + { + /* basic parenting skills (name, CA bit, key usage) */ + if( x509_crt_check_parent( child, parent, top ) != 0 ) + continue; + + /* +1 because stored max_pathlen is 1 higher that the actual value */ + if( parent->max_pathlen > 0 && + (size_t) parent->max_pathlen < 1 + path_cnt - self_cnt ) + { + continue; + } + + /* Signature */ +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +check_signature: +#endif + ret = x509_crt_check_signature( child, parent, rs_ctx ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + /* save state */ + rs_ctx->parent = parent; + rs_ctx->fallback_parent = fallback_parent; + rs_ctx->fallback_signature_is_good = fallback_signature_is_good; + + return( ret ); + } +#else + (void) ret; +#endif + + signature_is_good = ret == 0; + if( top && ! signature_is_good ) + continue; + + /* optional time check */ + if( mbedtls_x509_time_is_past( &parent->valid_to ) || + mbedtls_x509_time_is_future( &parent->valid_from ) ) + { + if( fallback_parent == NULL ) + { + fallback_parent = parent; + fallback_signature_is_good = signature_is_good; + } + + continue; + } + + *r_parent = parent; + *r_signature_is_good = signature_is_good; + + break; + } + + if( parent == NULL ) + { + *r_parent = fallback_parent; + *r_signature_is_good = fallback_signature_is_good; + } + + return( 0 ); +} + +/* + * Find a parent in trusted CAs or the provided chain, or return NULL. + * + * Searches in trusted CAs first, and return the first suitable parent found + * (see find_parent_in() for definition of suitable). + * + * Arguments: + * - [in] child: certificate for which we're looking for a parent, followed + * by a chain of possible intermediates + * - [in] trust_ca: list of locally trusted certificates + * - [out] parent: parent found (or NULL) + * - [out] parent_is_trusted: 1 if returned `parent` is trusted, or 0 + * - [out] signature_is_good: 1 if child signature by parent is valid, or 0 + * - [in] path_cnt: number of links in the chain so far (EE -> ... -> child) + * - [in] self_cnt: number of self-signed certs in the chain so far + * (will always be no greater than path_cnt) + * - [in-out] rs_ctx: context for restarting operations + * + * Return value: + * - 0 on success + * - MBEDTLS_ERR_ECP_IN_PROGRESS otherwise + */ +static int x509_crt_find_parent( + mbedtls_x509_crt *child, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crt **parent, + int *parent_is_trusted, + int *signature_is_good, + unsigned path_cnt, + unsigned self_cnt, + mbedtls_x509_crt_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_x509_crt *search_list; + + *parent_is_trusted = 1; + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /* restore then clear saved state if we have some stored */ + if( rs_ctx != NULL && rs_ctx->parent_is_trusted != -1 ) + { + *parent_is_trusted = rs_ctx->parent_is_trusted; + rs_ctx->parent_is_trusted = -1; + } +#endif + + while( 1 ) { + search_list = *parent_is_trusted ? trust_ca : child->next; + + ret = x509_crt_find_parent_in( child, search_list, + parent, signature_is_good, + *parent_is_trusted, + path_cnt, self_cnt, rs_ctx ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + /* save state */ + rs_ctx->parent_is_trusted = *parent_is_trusted; + return( ret ); + } +#else + (void) ret; +#endif + + /* stop here if found or already in second iteration */ + if( *parent != NULL || *parent_is_trusted == 0 ) + break; + + /* prepare second iteration */ + *parent_is_trusted = 0; + } + + /* extra precaution against mistakes in the caller */ + if( *parent == NULL ) + { + *parent_is_trusted = 0; + *signature_is_good = 0; + } + + return( 0 ); +} + +/* + * Check if an end-entity certificate is locally trusted + * + * Currently we require such certificates to be self-signed (actually only + * check for self-issued as self-signatures are not checked) + */ +static int x509_crt_check_ee_locally_trusted( + mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca ) +{ + mbedtls_x509_crt *cur; + + /* must be self-issued */ + if( x509_name_cmp( &crt->issuer, &crt->subject ) != 0 ) + return( -1 ); + + /* look for an exact match with trusted cert */ + for( cur = trust_ca; cur != NULL; cur = cur->next ) + { + if( crt->raw.len == cur->raw.len && + memcmp( crt->raw.p, cur->raw.p, crt->raw.len ) == 0 ) + { + return( 0 ); + } + } + + /* too bad */ + return( -1 ); +} + +/* + * Build and verify a certificate chain + * + * Given a peer-provided list of certificates EE, C1, ..., Cn and + * a list of trusted certs R1, ... Rp, try to build and verify a chain + * EE, Ci1, ... Ciq [, Rj] + * such that every cert in the chain is a child of the next one, + * jumping to a trusted root as early as possible. + * + * Verify that chain and return it with flags for all issues found. + * + * Special cases: + * - EE == Rj -> return a one-element list containing it + * - EE, Ci1, ..., Ciq cannot be continued with a trusted root + * -> return that chain with NOT_TRUSTED set on Ciq + * + * Tests for (aspects of) this function should include at least: + * - trusted EE + * - EE -> trusted root + * - EE -> intermediate CA -> trusted root + * - if relevant: EE untrusted + * - if relevant: EE -> intermediate, untrusted + * with the aspect under test checked at each relevant level (EE, int, root). + * For some aspects longer chains are required, but usually length 2 is + * enough (but length 1 is not in general). + * + * Arguments: + * - [in] crt: the cert list EE, C1, ..., Cn + * - [in] trust_ca: the trusted list R1, ..., Rp + * - [in] ca_crl, profile: as in verify_with_profile() + * - [out] ver_chain: the built and verified chain + * Only valid when return value is 0, may contain garbage otherwise! + * Restart note: need not be the same when calling again to resume. + * - [in-out] rs_ctx: context for restarting operations + * + * Return value: + * - non-zero if the chain could not be fully built and examined + * - 0 is the chain was successfully built and examined, + * even if it was found to be invalid + */ +static int x509_crt_verify_chain( + mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const mbedtls_x509_crt_profile *profile, + mbedtls_x509_crt_verify_chain *ver_chain, + mbedtls_x509_crt_restart_ctx *rs_ctx ) +{ + /* Don't initialize any of those variables here, so that the compiler can + * catch potential issues with jumping ahead when restarting */ + int ret; + uint32_t *flags; + mbedtls_x509_crt_verify_chain_item *cur; + mbedtls_x509_crt *child; + mbedtls_x509_crt *parent; + int parent_is_trusted; + int child_is_trusted; + int signature_is_good; + unsigned self_cnt; + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /* resume if we had an operation in progress */ + if( rs_ctx != NULL && rs_ctx->in_progress == x509_crt_rs_find_parent ) + { + /* restore saved state */ + *ver_chain = rs_ctx->ver_chain; /* struct copy */ + self_cnt = rs_ctx->self_cnt; + + /* restore derived state */ + cur = &ver_chain->items[ver_chain->len - 1]; + child = cur->crt; + flags = &cur->flags; + + goto find_parent; + } +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + + child = crt; + self_cnt = 0; + parent_is_trusted = 0; + child_is_trusted = 0; + + while( 1 ) { + /* Add certificate to the verification chain */ + cur = &ver_chain->items[ver_chain->len]; + cur->crt = child; + cur->flags = 0; + ver_chain->len++; + flags = &cur->flags; + + /* Check time-validity (all certificates) */ + if( mbedtls_x509_time_is_past( &child->valid_to ) ) + *flags |= MBEDTLS_X509_BADCERT_EXPIRED; + + if( mbedtls_x509_time_is_future( &child->valid_from ) ) + *flags |= MBEDTLS_X509_BADCERT_FUTURE; + + /* Stop here for trusted roots (but not for trusted EE certs) */ + if( child_is_trusted ) + return( 0 ); + + /* Check signature algorithm: MD & PK algs */ + if( x509_profile_check_md_alg( profile, child->sig_md ) != 0 ) + *flags |= MBEDTLS_X509_BADCERT_BAD_MD; + + if( x509_profile_check_pk_alg( profile, child->sig_pk ) != 0 ) + *flags |= MBEDTLS_X509_BADCERT_BAD_PK; + + /* Special case: EE certs that are locally trusted */ + if( ver_chain->len == 1 && + x509_crt_check_ee_locally_trusted( child, trust_ca ) == 0 ) + { + return( 0 ); + } + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +find_parent: +#endif + /* Look for a parent in trusted CAs or up the chain */ + ret = x509_crt_find_parent( child, trust_ca, &parent, + &parent_is_trusted, &signature_is_good, + ver_chain->len - 1, self_cnt, rs_ctx ); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + /* save state */ + rs_ctx->in_progress = x509_crt_rs_find_parent; + rs_ctx->self_cnt = self_cnt; + rs_ctx->ver_chain = *ver_chain; /* struct copy */ + + return( ret ); + } +#else + (void) ret; +#endif + + /* No parent? We're done here */ + if( parent == NULL ) + { + *flags |= MBEDTLS_X509_BADCERT_NOT_TRUSTED; + return( 0 ); + } + + /* Count intermediate self-issued (not necessarily self-signed) certs. + * These can occur with some strategies for key rollover, see [SIRO], + * and should be excluded from max_pathlen checks. */ + if( ver_chain->len != 1 && + x509_name_cmp( &child->issuer, &child->subject ) == 0 ) + { + self_cnt++; + } + + /* path_cnt is 0 for the first intermediate CA, + * and if parent is trusted it's not an intermediate CA */ + if( ! parent_is_trusted && + ver_chain->len > MBEDTLS_X509_MAX_INTERMEDIATE_CA ) + { + /* return immediately to avoid overflow the chain array */ + return( MBEDTLS_ERR_X509_FATAL_ERROR ); + } + + /* signature was checked while searching parent */ + if( ! signature_is_good ) + *flags |= MBEDTLS_X509_BADCERT_NOT_TRUSTED; + + /* check size of signing key */ + if( x509_profile_check_key( profile, &parent->pk ) != 0 ) + *flags |= MBEDTLS_X509_BADCERT_BAD_KEY; + +#if defined(MBEDTLS_X509_CRL_PARSE_C) + /* Check trusted CA's CRL for the given crt */ + *flags |= x509_crt_verifycrl( child, parent, ca_crl, profile ); +#else + (void) ca_crl; +#endif + + /* prepare for next iteration */ + child = parent; + parent = NULL; + child_is_trusted = parent_is_trusted; + signature_is_good = 0; + } +} + +/* + * Check for CN match + */ +static int x509_crt_check_cn( const mbedtls_x509_buf *name, + const char *cn, size_t cn_len ) +{ + /* try exact match */ + if( name->len == cn_len && + x509_memcasecmp( cn, name->p, cn_len ) == 0 ) + { + return( 0 ); + } + + /* try wildcard match */ + if( x509_check_wildcard( cn, name ) == 0 ) + { + return( 0 ); + } + + return( -1 ); +} + +/* + * Verify the requested CN - only call this if cn is not NULL! + */ +static void x509_crt_verify_name( const mbedtls_x509_crt *crt, + const char *cn, + uint32_t *flags ) +{ + const mbedtls_x509_name *name; + const mbedtls_x509_sequence *cur; + size_t cn_len = strlen( cn ); + + if( crt->ext_types & MBEDTLS_X509_EXT_SUBJECT_ALT_NAME ) + { + for( cur = &crt->subject_alt_names; cur != NULL; cur = cur->next ) + { + if( x509_crt_check_cn( &cur->buf, cn, cn_len ) == 0 ) + break; + } + + if( cur == NULL ) + *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH; + } + else + { + for( name = &crt->subject; name != NULL; name = name->next ) + { + if( MBEDTLS_OID_CMP( MBEDTLS_OID_AT_CN, &name->oid ) == 0 && + x509_crt_check_cn( &name->val, cn, cn_len ) == 0 ) + { + break; + } + } + + if( name == NULL ) + *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH; + } +} + +/* + * Merge the flags for all certs in the chain, after calling callback + */ +static int x509_crt_merge_flags_with_cb( + uint32_t *flags, + const mbedtls_x509_crt_verify_chain *ver_chain, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy ) +{ + int ret; + unsigned i; + uint32_t cur_flags; + const mbedtls_x509_crt_verify_chain_item *cur; + + for( i = ver_chain->len; i != 0; --i ) + { + cur = &ver_chain->items[i-1]; + cur_flags = cur->flags; + + if( NULL != f_vrfy ) + if( ( ret = f_vrfy( p_vrfy, cur->crt, (int) i-1, &cur_flags ) ) != 0 ) + return( ret ); + + *flags |= cur_flags; + } + + return( 0 ); +} + +/* + * Verify the certificate validity (default profile, not restartable) + */ +int mbedtls_x509_crt_verify( mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy ) +{ + return( mbedtls_x509_crt_verify_restartable( crt, trust_ca, ca_crl, + &mbedtls_x509_crt_profile_default, cn, flags, + f_vrfy, p_vrfy, NULL ) ); +} + +/* + * Verify the certificate validity (user-chosen profile, not restartable) + */ +int mbedtls_x509_crt_verify_with_profile( mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const mbedtls_x509_crt_profile *profile, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy ) +{ + return( mbedtls_x509_crt_verify_restartable( crt, trust_ca, ca_crl, + profile, cn, flags, f_vrfy, p_vrfy, NULL ) ); +} + +/* + * Verify the certificate validity, with profile, restartable version + * + * This function: + * - checks the requested CN (if any) + * - checks the type and size of the EE cert's key, + * as that isn't done as part of chain building/verification currently + * - builds and verifies the chain + * - then calls the callback and merges the flags + */ +int mbedtls_x509_crt_verify_restartable( mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const mbedtls_x509_crt_profile *profile, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy, + mbedtls_x509_crt_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_pk_type_t pk_type; + mbedtls_x509_crt_verify_chain ver_chain; + uint32_t ee_flags; + + *flags = 0; + ee_flags = 0; + x509_crt_verify_chain_reset( &ver_chain ); + + if( profile == NULL ) + { + ret = MBEDTLS_ERR_X509_BAD_INPUT_DATA; + goto exit; + } + + /* check name if requested */ + if( cn != NULL ) + x509_crt_verify_name( crt, cn, &ee_flags ); + + /* Check the type and size of the key */ + pk_type = mbedtls_pk_get_type( &crt->pk ); + + if( x509_profile_check_pk_alg( profile, pk_type ) != 0 ) + ee_flags |= MBEDTLS_X509_BADCERT_BAD_PK; + + if( x509_profile_check_key( profile, &crt->pk ) != 0 ) + ee_flags |= MBEDTLS_X509_BADCERT_BAD_KEY; + + /* Check the chain */ + ret = x509_crt_verify_chain( crt, trust_ca, ca_crl, profile, + &ver_chain, rs_ctx ); + + if( ret != 0 ) + goto exit; + + /* Merge end-entity flags */ + ver_chain.items[0].flags |= ee_flags; + + /* Build final flags, calling callback on the way if any */ + ret = x509_crt_merge_flags_with_cb( flags, &ver_chain, f_vrfy, p_vrfy ); + +exit: +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) + mbedtls_x509_crt_restart_free( rs_ctx ); +#endif + + /* prevent misuse of the vrfy callback - VERIFY_FAILED would be ignored by + * the SSL module for authmode optional, but non-zero return from the + * callback means a fatal error so it shouldn't be ignored */ + if( ret == MBEDTLS_ERR_X509_CERT_VERIFY_FAILED ) + ret = MBEDTLS_ERR_X509_FATAL_ERROR; + + if( ret != 0 ) + { + *flags = (uint32_t) -1; + return( ret ); + } + + if( *flags != 0 ) + return( MBEDTLS_ERR_X509_CERT_VERIFY_FAILED ); + + return( 0 ); +} + +/* + * Initialize a certificate chain + */ +void mbedtls_x509_crt_init( mbedtls_x509_crt *crt ) +{ + memset( crt, 0, sizeof(mbedtls_x509_crt) ); +} + +/* + * Unallocate all certificate data + */ +void mbedtls_x509_crt_free( mbedtls_x509_crt *crt ) +{ + mbedtls_x509_crt *cert_cur = crt; + mbedtls_x509_crt *cert_prv; + mbedtls_x509_name *name_cur; + mbedtls_x509_name *name_prv; + mbedtls_x509_sequence *seq_cur; + mbedtls_x509_sequence *seq_prv; + + if( crt == NULL ) + return; + + do + { + mbedtls_pk_free( &cert_cur->pk ); + +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) + mbedtls_free( cert_cur->sig_opts ); +#endif + + name_cur = cert_cur->issuer.next; + while( name_cur != NULL ) + { + name_prv = name_cur; + name_cur = name_cur->next; + mbedtls_platform_zeroize( name_prv, sizeof( mbedtls_x509_name ) ); + mbedtls_free( name_prv ); + } + + name_cur = cert_cur->subject.next; + while( name_cur != NULL ) + { + name_prv = name_cur; + name_cur = name_cur->next; + mbedtls_platform_zeroize( name_prv, sizeof( mbedtls_x509_name ) ); + mbedtls_free( name_prv ); + } + + seq_cur = cert_cur->ext_key_usage.next; + while( seq_cur != NULL ) + { + seq_prv = seq_cur; + seq_cur = seq_cur->next; + mbedtls_platform_zeroize( seq_prv, + sizeof( mbedtls_x509_sequence ) ); + mbedtls_free( seq_prv ); + } + + seq_cur = cert_cur->subject_alt_names.next; + while( seq_cur != NULL ) + { + seq_prv = seq_cur; + seq_cur = seq_cur->next; + mbedtls_platform_zeroize( seq_prv, + sizeof( mbedtls_x509_sequence ) ); + mbedtls_free( seq_prv ); + } + + if( cert_cur->raw.p != NULL ) + { + mbedtls_platform_zeroize( cert_cur->raw.p, cert_cur->raw.len ); + mbedtls_free( cert_cur->raw.p ); + } + + cert_cur = cert_cur->next; + } + while( cert_cur != NULL ); + + cert_cur = crt; + do + { + cert_prv = cert_cur; + cert_cur = cert_cur->next; + + mbedtls_platform_zeroize( cert_prv, sizeof( mbedtls_x509_crt ) ); + if( cert_prv != crt ) + mbedtls_free( cert_prv ); + } + while( cert_cur != NULL ); +} + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Initialize a restart context + */ +void mbedtls_x509_crt_restart_init( mbedtls_x509_crt_restart_ctx *ctx ) +{ + mbedtls_pk_restart_init( &ctx->pk ); + + ctx->parent = NULL; + ctx->fallback_parent = NULL; + ctx->fallback_signature_is_good = 0; + + ctx->parent_is_trusted = -1; + + ctx->in_progress = x509_crt_rs_none; + ctx->self_cnt = 0; + x509_crt_verify_chain_reset( &ctx->ver_chain ); +} + +/* + * Free the components of a restart context + */ +void mbedtls_x509_crt_restart_free( mbedtls_x509_crt_restart_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_pk_restart_free( &ctx->pk ); + mbedtls_x509_crt_restart_init( ctx ); +} +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +#endif /* MBEDTLS_X509_CRT_PARSE_C */ diff --git a/src/common/mbedtls/nvidia/nvrm_mbedtls_config.h b/src/common/mbedtls/nvidia/nvrm_mbedtls_config.h new file mode 100644 index 0000000000..b685d397ee --- /dev/null +++ b/src/common/mbedtls/nvidia/nvrm_mbedtls_config.h @@ -0,0 +1,219 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +// +// This file provides custom configuration options for MbedTLS. It is included +// via the MBEDTLS_USER_CONFIG_FILE macro, which means it supplements the +// MbedTLS default "config.h" file. Therefore, in this file, we modify defaults +// as set by config.h, rather than edit them directly. +// +// These configurations were originally tuned specifically for libspdm on RM, +// so the defines may need to be modified if more functionality is desired. +// +// NOTE: Since RM cannot include freestanding headers like stdlib.h and string.h, +// we have removed or hijacked their inclusion and provided replacement +// definitions at the bottom of this file. +// + +#ifndef _NVRM_MBEDTLS_CONFIG_H_ +#define _NVRM_MBEDTLS_CONFIG_H_ + +// First, disable all features that we are not using. +#undef MBEDTLS_HAVE_TIME +#undef MBEDTLS_HAVE_TIME_DATE +#undef MBEDTLS_CIPHER_MODE_CBC +#undef MBEDTLS_CIPHER_MODE_CFB +#undef MBEDTLS_CIPHER_MODE_OFB +#undef MBEDTLS_CIPHER_MODE_XTS +#undef MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS +#undef MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN +#undef MBEDTLS_CIPHER_PADDING_ZEROS +#undef MBEDTLS_ECP_DP_SECP192R1_ENABLED +#undef MBEDTLS_ECP_DP_SECP224R1_ENABLED +#undef MBEDTLS_ECP_DP_SECP521R1_ENABLED +#undef MBEDTLS_ECP_DP_SECP192K1_ENABLED +#undef MBEDTLS_ECP_DP_SECP224K1_ENABLED +#undef MBEDTLS_ECP_DP_SECP256K1_ENABLED +#undef MBEDTLS_ECP_DP_BP256R1_ENABLED +#undef MBEDTLS_ECP_DP_BP384R1_ENABLED +#undef MBEDTLS_ECP_DP_BP512R1_ENABLED +#undef MBEDTLS_ECP_DP_CURVE25519_ENABLED +#undef MBEDTLS_ECP_DP_CURVE448_ENABLED +#undef MBEDTLS_ECP_NIST_OPTIM +#undef MBEDTLS_ECDSA_DETERMINISTIC +#undef MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_RSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED +#undef MBEDTLS_PK_PARSE_EC_EXTENDED +#undef MBEDTLS_GENPRIME +#undef MBEDTLS_FS_IO +#undef MBEDTLS_MPI_WINDOWS_SIZE +#undef MBEDTLS_PK_RSA_ALT_SUPPORT +#undef MBEDTLS_PKCS1_V15 +#undef MBEDTLS_PKCS1_V21 +#undef MBEDTLS_SELF_TEST +#undef MBEDTLS_SSL_ALL_ALERT_MESSAGES +#undef MBEDTLS_SSL_ENCRYPT_THEN_MAC +#undef MBEDTLS_SSL_EXTENDED_MASTER_SECRET +#undef MBEDTLS_SSL_FALLBACK_SCSV +#undef MBEDTLS_SSL_CBC_RECORD_SPLITTING +#undef MBEDTLS_SSL_RENEGOTIATION +#undef MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +#undef MBEDTLS_SSL_PROTO_TLS1 +#undef MBEDTLS_SSL_PROTO_TLS1_1 +#undef MBEDTLS_SSL_PROTO_TLS1_2 +#undef MBEDTLS_SSL_PROTO_DTLS +#undef MBEDTLS_SSL_ALPN +#undef MBEDTLS_SSL_DTLS_ANTI_REPLAY +#undef MBEDTLS_SSL_DTLS_HELLO_VERIFY +#undef MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +#undef MBEDTLS_SSL_DTLS_BADMAC_LIMIT +#undef MBEDTLS_SSL_SESSION_TICKETS +#undef MBEDTLS_SSL_EXPORT_KEYS +#undef MBEDTLS_SSL_SERVER_NAME_INDICATION +#undef MBEDTLS_SSL_TRUNCATED_HMAC +#undef MBEDTLS_X509_CHECK_KEY_USAGE +#undef MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE +#undef MBEDTLS_X509_RSASSA_PSS_SUPPORT +#undef MBEDTLS_AESNI_C +#undef MBEDTLS_ARC4_C +#undef MBEDTLS_BLOWFISH_C +#undef MBEDTLS_CAMELLIA_C +#undef MBEDTLS_CCM_C +#undef MBEDTLS_CERTS_C +#undef MBEDTLS_CHACHA20_C +#undef MBEDTLS_CHACHAPOLY_C +#undef MBEDTLS_CTR_DRBG_C +#undef MBEDTLS_DEBUG_C +#undef MBEDTLS_DES_C +#undef MBEDTLS_DHM_C +#undef MBEDTLS_ENTROPY_C +#undef MBEDTLS_ERROR_C +#undef MBEDTLS_HMAC_DRBG_C +#undef MBEDTLS_MD5_C +#undef MBEDTLS_NET_C +#undef MBEDTLS_PADLOCK_C +#undef MBEDTLS_PEM_PARSE_C +#undef MBEDTLS_PK_WRITE_C +#undef MBEDTLS_PKCS5_C +#undef MBEDTLS_PKCS12_C +#undef MBEDTLS_POLY1305_C +#undef MBEDTLS_RIPEMD160_C +#undef MBEDTLS_RSA_C +#undef MBEDTLS_SHA1_C +#undef MBEDTLS_SSL_CACHE_C +#undef MBEDTLS_SSL_COOKIE_C +#undef MBEDTLS_SSL_TICKET_C +#undef MBEDTLS_SSL_CLI_C +#undef MBEDTLS_SSL_SRV_C +#undef MBEDTLS_SSL_TLS_C +#undef MBEDTLS_TIMING_C +#undef MBEDTLS_X509_CSR_PARSE_C +#undef MBEDTLS_X509_CREATE_C +#undef MBEDTLS_X509_CRT_WRITE_C +#undef MBEDTLS_X509_CSR_WRITE_C +#undef MBEDTLS_XTEA_C + +// +// The commented out '#undef's below are features set by MbedTLS's config.h +// that we want to keep enabled. Listed here for tracking purposes. +// +//#undef MBEDTLS_ECP_DP_SECP256R1_ENABLED +//#undef MBEDTLS_ECP_DP_SECP384R1_ENABLED +//#undef MBEDTLS_ASN1_WRITE_C +//#undef MBEDTLS_BASE64_C +//#undef MBEDTLS_BIGNUM_C +//#undef MBEDTLS_ECDH_C +//#undef MBEDTLS_ECDSA_C +//#undef MBEDTLS_ECP_C +//#undef MBEDTLS_HKDF_C +//#undef MBEDTLS_OID_C +//#undef MBEDTLS_PEM_WRITE_C +//#undef MBEDTLS_PK_C +//#undef MBEDTLS_SHA512_C +//#undef MBEDTLS_X509_USE_C +//#undef MBEDTLS_X509_CRT_PARSE_C +//#undef MBEDTLS_X509_CRL_PARSE_C + +// Explicitly define any features we need that aren't already set. +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_PK_PARSE_C + +// Kernel doesn't have 128bit division. +#define MBEDTLS_NO_UDBL_DIVISION + +// Define for hopeful perf boost due to better memory layout. +#define MBEDTLS_AES_ROM_TABLES + +// Stack size is too large with default window size +#define MBEDTLS_MPI_WINDOW_SIZE 1 + +// +// Use custom memory allocation. These functions will be provided +// by libspdm wrappers around NvPort implementations. +// +#define MBEDTLS_PLATFORM_MEMORY +#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS +#define MBEDTLS_PLATFORM_ZEROIZE_ALT +#define MBEDTLS_PLATFORM_SNPRINTF_ALT +#define MBEDTLS_PLATFORM_STD_SNPRINTF mbedtls_snprintf + +// +// These changes are all WARs for system headers, required for Linux RM builds. +// We prevent their inclusion in MbedTLS source, either via editing MbedTLS +// source, or hijacking their compile guards before they are included. +// We provide definitions of any required macros, types, or functions manually. +// + +// WARs for limits.h +#if !defined(_GCC_LIMITS_H_) +#define _GCC_LIMITS_H_ +#define INT_MAX +2147483647 +#endif // _GCC_LIMITS_H_ + +// WAR to waive self-test in check_config.h. +#define CHAR_BIT 8U + +// Include stdint.h directly here to avoid missing dependencies. +#include + +// WARs for string.h - we will use NvPort functions in their place. +#include "nvport/nvport.h" + +#define memcmp(str1, str2, n) portMemCmp((str1), (str2), (NvLength)(n)) +#define memcpy(dest, src, n) portMemCopy((dest), (NvLength)(n), (src), (NvLength)(n)) +#define memset(str, c, n) portMemSet((str), (NvU8)(c), (NvLength)(n)) +#define memmove(dest, src, n) portMemMove((dest), (NvLength)(n), (src), (NvLength)(n)) +#define strlen(str) portStringLength(str) + +// NvPort implementation doesn't have max length parameter, so set arbitrary number. +#define strcmp(str1, str2) portStringCompare ((str1), (str2), (0x1000)) + +#endif // _NVRM_MBEDTLS_CONFIG_H_ diff --git a/src/common/mbedtls/nvidia/nvrm_platform.c b/src/common/mbedtls/nvidia/nvrm_platform.c new file mode 100644 index 0000000000..edfd8cdcb5 --- /dev/null +++ b/src/common/mbedtls/nvidia/nvrm_platform.c @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +// File provides RM implementations of platform utilities needed by MbedTLS. + +#include "mbedtls/config.h" +#include "os/os.h" +#include "stddef.h" + +void +mbedtls_platform_zeroize +( + void *buf, + size_t len +) +{ + portMemSet(buf, 0, (NvLength)len); +} + +void * +mbedtls_calloc +( + size_t n, + size_t size +) +{ + NvLength bytes; + void *ptr; + + bytes = (NvLength)(n * size); + ptr = portMemAllocNonPaged(bytes); + if (ptr == NULL) + { + return ptr; + } + + portMemSet(ptr, 0, bytes); + + return ptr; +} + +void +mbedtls_free +( + void *ptr +) +{ + // portMemFree handles NULL. + portMemFree(ptr); +} + +// +// MbedTLS requires snprintf function pointer - since we don't currently need, +// define empty function to be called when snprintf is needed. +// +int nvrmSnPrintf +( + char *s, + size_t n, + const char *format, + ... +) +{ + return 0; +} + +int (*mbedtls_snprintf)(char *s, size_t n, const char *format, ...) = nvrmSnPrintf; diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.c b/src/common/modeset/hdmipacket/nvhdmipkt.c index f544d0790a..42033621e0 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt.c @@ -315,7 +315,8 @@ NvHdmi_QueryFRLConfig(NvHdmiPkt_Handle libHandle, } // if there is no FRL capability reported fail this call - if (pSinkCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE) + if ((pSrcCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE) || + (pSinkCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE)) { return NVHDMIPKT_FAIL; } diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c index ae29ff3d3a..86ac625e6f 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c @@ -573,12 +573,13 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis, packetLen == 0 || pPacketIn == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE) { result = NVHDMIPKT_INVALID_ARG; + NvHdmiPkt_Print(pThis, "Invalid arg"); goto hdmiPacketWrite9171_exit; } if ((result = validateInputPacketLength(pktType9171, packetLen, pPacketIn)) != NVHDMIPKT_SUCCESS) { - NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect"); + NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect %d", packetLen); NvHdmiPkt_Assert(0); goto hdmiPacketWrite9171_exit; } diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_C671.c b/src/common/modeset/hdmipacket/nvhdmipkt_C671.c index 8385565911..ffc6e3f55d 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_C671.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_C671.c @@ -460,6 +460,7 @@ static NvBool evaluateIsDSCPossible(NVHDMIPKT_CLASS *pThis, #endif // NVHDMIPKT_RM_CALLS_INTERNAL { bIsDSCPossible = pGetHdmiFrlCapacityComputationParams->dsc.bIsDSCPossible; + *pFRLParams = pGetHdmiFrlCapacityComputationParams->input; } pThis->callback.free(pThis->cbHandle, pGetHdmiFrlCapacityComputationParams); diff --git a/src/common/modeset/timing/displayid20.h b/src/common/modeset/timing/displayid20.h index 951f382567..1bfcace0f5 100644 --- a/src/common/modeset/timing/displayid20.h +++ b/src/common/modeset/timing/displayid20.h @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -275,7 +275,7 @@ typedef struct _tagDISPLAYID_2_0_TIMING_7_BLOCK #define DISPLAYID_2_0_TIMING_DSC_PASSTHRU_TIMING 1 -// the following fields apply to Timing Descriptors 7 (Not all of them are +// the following fields apply to Timing 7 Descriptors (Not all of them are // used per descriptor, but the format is the same #define DISPLAYID_2_0_TIMING_ASPECT_RATIO_1_1 0 #define DISPLAYID_2_0_TIMING_ASPECT_RATIO_5_4 1 @@ -308,29 +308,15 @@ typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK_HEADER NvU8 data_bytes; // Values range from 1(0x01) to 248(0xF8) } DISPLAYID_2_0_TIMING_8_BLOCK_HEADER; -typedef struct _tagDISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE -{ - NvU8 timing_code; -} DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE; - -typedef struct _tagDISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE -{ - NvU8 timing_code[2]; -} DISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE; - #define DISPLAYID_2_0_TIMING_8_MAX_CODES 248 typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK { DISPLAYID_2_0_TIMING_8_BLOCK_HEADER header; - - union - { - DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE timing_code_1[DISPLAYID_2_0_TIMING_8_MAX_CODES]; - DISPLAYID_2_0_TIMING_8_TWO_BYTE_CODE timing_code_2[DISPLAYID_2_0_TIMING_8_MAX_CODES / 2]; - }; + NvU8 timingCode[DISPLAYID_2_0_TIMING_8_MAX_CODES]; } DISPLAYID_2_0_TIMING_8_BLOCK; +// the following fields apply to Timing 8 Descriptors #define DISPLAYID_2_0_TIMING_CODE_DMT 0 #define DISPLAYID_2_0_TIMING_CODE_CTA_VIC 1 #define DISPLAYID_2_0_TIMING_CODE_HDMI_VIC 2 @@ -353,6 +339,7 @@ typedef struct _TAG_DISPLAYID_2_0_TIMING_9_DESCRIPTOR NvU8 refresh_rate; // 1 Hz to 256 Hz } DISPLAYID_2_0_TIMING_9_DESCRIPTOR; +// the following fields apply to Timing 9/10 Descriptors #define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD 0 #define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1 1 #define DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2 2 @@ -384,8 +371,8 @@ typedef struct _DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR { struct { NvU8 timing_formula :3; - NvU8 early_vsync :1; - NvU8 rr1000div1001_or_hblank :1; + NvU8 early_vsync :1; + NvU8 rr1000div1001_or_hblank :1; NvU8 stereo_support :2; NvU8 ycc420_support :1; } options; diff --git a/src/common/modeset/timing/nvt_displayid20.c b/src/common/modeset/timing/nvt_displayid20.c index 83ab4e1cb8..c97b9e88fc 100644 --- a/src/common/modeset/timing/nvt_displayid20.c +++ b/src/common/modeset/timing/nvt_displayid20.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -61,7 +61,6 @@ static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER // Helper function static NVT_STATUS getPrimaryUseCase(NvU8 product_type, NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE *primary_use_case); -static NVT_STATUS parseDisplayId20Timing7Descriptor(const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 revision, NvU8 count); static NVT_STATUS parseDisplayId20Timing9Descriptor(const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 count); static NvU32 greatestCommonDenominator(NvU32 x, NvU32 y); static NvU8 getExistedTimingSeqNumber(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, enum NVT_TIMING_TYPE); @@ -625,6 +624,7 @@ parseDisplayId20Timing7( return NVT_STATUS_ERR; } + revision = pTiming7Block->header.revision; descriptorCount = pDataBlock->data_bytes / (sizeof(DISPLAYID_2_0_TIMING_7_DESCRIPTOR) + pTiming7Block->header.payload_bytes_len); if (descriptorCount < 1 || descriptorCount > DISPLAYID_2_0_TIMING_7_MAX_DESCRIPTORS) @@ -641,8 +641,36 @@ parseDisplayId20Timing7( for (i = 0; i < descriptorCount; i++) { NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); - if (parseDisplayId20Timing7Descriptor(&pTiming7Block->descriptors[i], &newTiming, revision, startSeqNumber+i) == NVT_STATUS_SUCCESS) + if (parseDisplayId20Timing7Descriptor(&pTiming7Block->descriptors[i], &newTiming, startSeqNumber+i) == NVT_STATUS_SUCCESS) { + newTiming.etc.flag |= (revision >= DISPLAYID_2_0_TYPE7_DSC_PASSTHRU_REVISION && pTiming7Block->header.dsc_passthrough == 1) ? + NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU : + 0; + + if (revision >= DISPLAYID_2_0_TYPE7_YCC420_SUPPORT_REVISION) + { + newTiming.etc.flag |= pTiming7Block->descriptors[i].options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0; + + if (pTiming7Block->descriptors[i].options.is_preferred_or_ycc420) // YCC 420 support + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, 1, 1, 0, 1); + } + } + else + { + newTiming.etc.flag |= pTiming7Block->descriptors[i].options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0; + } + + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type7:#%2d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)((newTiming.interlaced ? 2 : 1)*newTiming.VVisible), + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; + if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming)) { break; @@ -667,80 +695,50 @@ parseDisplayId20Timing8( NVT_STATUS status = NVT_STATUS_SUCCESS; const DISPLAYID_2_0_TIMING_8_BLOCK *pTiming8Block = NULL; NVT_TIMING newTiming; - NvU8 codeType = DISPLAYID_2_0_TIMING_CODE_RSERVED; + NvU8 codeCount = 0; NvU8 startSeqNumber = 0; NvU8 i; pTiming8Block = (const DISPLAYID_2_0_TIMING_8_BLOCK *)pDataBlock; + codeCount = pDataBlock->data_bytes; - // 1-byte descriptor timing code - if (pTiming8Block->header.timing_code_size == DISPLAYID_2_0_TIMING_CODE_SIZE_1_BYTE) + if (codeCount == 0) { - if (pDataBlock->data_bytes % sizeof(DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE) != 0) - { - return NVT_STATUS_ERR; - } + nvt_assert(0 && "No available byte code!"); + return NVT_STATUS_SUCCESS; + } - codeCount = pDataBlock->data_bytes / sizeof(DISPLAYID_2_0_TIMING_8_ONE_BYTE_CODE); - if (codeCount < 1 || codeCount > DISPLAYID_2_0_TIMING_8_MAX_CODES) - { - return NVT_STATUS_ERR; - } + if (codeCount > DISPLAYID_2_0_TIMING_8_MAX_CODES) + { + nvt_assert(0 && "one byte code is out of range!"); + return NVT_STATUS_SUCCESS; + } - codeType = pTiming8Block->header.timing_code_type; + if (pDisplayIdInfo != NULL) + { + startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_8); + } - if (pDisplayIdInfo != NULL) - { - startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_8); - } + for (i = 0; i < codeCount; i++) + { + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); - for (i = 0; i < codeCount; i++) + if (parseDisplayId20Timing8Descriptor(&pTiming8Block->timingCode, &newTiming, + pTiming8Block->header.timing_code_type, + pTiming8Block->header.timing_code_size, i, startSeqNumber+i) == NVT_STATUS_SUCCESS) { - NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); - - if (codeType == DISPLAYID_2_0_TIMING_CODE_DMT) - { - if (NvTiming_EnumDMT((NvU32)(pTiming8Block->timing_code_1[i].timing_code), - &newTiming) != NVT_STATUS_SUCCESS) - { - if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; - break; - } - } - else if (codeType == DISPLAYID_2_0_TIMING_CODE_CTA_VIC) - { - if (NvTiming_EnumCEA861bTiming((NvU32)(pTiming8Block->timing_code_1[i].timing_code), - &newTiming) != NVT_STATUS_SUCCESS) - { - if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; - break; - } - } - else if (codeType == DISPLAYID_2_0_TIMING_CODE_HDMI_VIC) - { - if (NvTiming_EnumHdmiVsdbExtendedTiming((NvU32)(pTiming8Block->timing_code_1[i].timing_code), - &newTiming) != NVT_STATUS_SUCCESS) - { - if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; - break; - } - } - else - { - // RESERVED - break; - } - - newTiming.etc.flag |= ((pTiming8Block->header.revision >= 1) && pTiming8Block->header.is_support_yuv420) ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0; - newTiming.etc.status = NVT_STATUS_DISPLAYID_8N(++startSeqNumber); + newTiming.etc.flag |= ((pTiming8Block->header.revision == 1) && pTiming8Block->header.is_support_yuv420) ? + NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : + 0; NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type8:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), - (int)newTiming.HVisible, (int)newTiming.VVisible, - (int)newTiming.etc.rrx1k/1000, (int)newTiming.etc.rrx1k%1000, - (newTiming.interlaced ? "I":"P")); + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming)) { @@ -748,11 +746,6 @@ parseDisplayId20Timing8( } } } - else - { - nvt_assert(0); - // TODO : 2-byte descriptor timing code did not define yet in DID20. - } return status; } @@ -859,11 +852,11 @@ parseDisplayId20Timing10( for (i = 0; i < descriptorCount; i++) { - startSeqNumber += i; NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pTiming10Block->descriptors[i*eachOfDescriptorsSize], &newTiming, - pTiming10Block->header.payload_bytes_len)) + pTiming10Block->header.payload_bytes_len, + startSeqNumber+i)) { p6bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *)&pTiming10Block->descriptors[i*eachOfDescriptorsSize]; @@ -894,8 +887,8 @@ parseDisplayId20Timing10( (newTiming.interlaced ? "I":"P")); } - newTiming.etc.status = NVT_STATUS_DISPLAYID_10N(++startSeqNumber); newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming)) { @@ -1417,9 +1410,9 @@ parseDisplayId20CtaData( parseCea861Hdr10PlusDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); // CEA861-F at 7.5.12 section about VFPDB block. - if (p861Info->total_vfpdb > 0) + if (p861Info->total_svr > 0) { - parse861bShortPreferredTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + parseCta861NativeOrPreferredTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); } return status; @@ -1532,16 +1525,19 @@ assignNextAvailableDisplayId20Timing( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing7Descriptor( - const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor, + const void *pVoidDescriptor, NVT_TIMING *pTiming, - NvU8 revision, NvU8 count) { NVT_STATUS status = NVT_STATUS_SUCCESS; NvU32 gdc = 0; + const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor = NULL; + + pDescriptor = (const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *)pVoidDescriptor; + // pclk is in 10Khz // pixel_clock is in kHz pTiming->pclk = ((pDescriptor->pixel_clock[2] << 16 | @@ -1636,36 +1632,63 @@ parseDisplayId20Timing7Descriptor( pTiming->etc.rrx1k = NvTiming_CalcRRx1k(pTiming->pclk, pTiming->interlaced, pTiming->HTotal, - pTiming->VTotal); + pTiming->VTotal); - pTiming->etc.flag |= (revision >= DISPLAYID_2_0_TYPE7_DSC_PASSTHRU_REVISION ) ? NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU : 0; + pTiming->etc.status = NVT_STATUS_DISPLAYID_7N(++count); - if (revision >= DISPLAYID_2_0_TYPE7_YCC420_SUPPORT_REVISION) - { - pTiming->etc.flag |= pDescriptor->options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0; + return status; +} + +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS +parseDisplayId20Timing8Descriptor( + const void *pVoidDescriptor, + NVT_TIMING *pTiming, + NvU8 codeType, + NvU8 codeSize, + NvU8 idx, + NvU8 count) +{ + NVT_STATUS status = NVT_STATUS_SUCCESS; + + const NvU8 *pTimingCode = (const NvU8 *)pVoidDescriptor; + const NvU16 *pTiming2ByteCode = (const NvU16 *)pVoidDescriptor; - if (pDescriptor->options.is_preferred_or_ycc420) // YCC 420 support + if (codeSize == DISPLAYID_2_0_TIMING_CODE_SIZE_1_BYTE) + { + switch (codeType) + { + case DISPLAYID_2_0_TIMING_CODE_DMT: //single-byte DMT ID Codes + status = NvTiming_EnumDMT((NvU32)(pTimingCode[idx]), pTiming); + break; + case DISPLAYID_2_0_TIMING_CODE_CTA_VIC: + status = NvTiming_EnumCEA861bTiming((NvU32)(pTimingCode[idx]), pTiming); + break; + case DISPLAYID_2_0_TIMING_CODE_HDMI_VIC: + status = NvTiming_EnumHdmiVsdbExtendedTiming((NvU32)(pTimingCode[idx]), pTiming); + break; + default: { - UPDATE_BPC_FOR_COLORFORMAT(pTiming->etc.yuv420, 0, 1, 1, 1, 0, 1); + nvt_assert(0 && "RESERVED timing code type"); + status = NVT_STATUS_ERR; + } + break; } } - else + else if (codeSize == DISPLAYID_2_0_TIMING_CODE_SIZE_2_BYTE) { - pTiming->etc.flag |= pDescriptor->options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0; + // Standard two-byte codes + if (codeType == DISPLAYID_2_0_TIMING_CODE_DMT) + { + status = NvTiming_EnumStdTwoBytesCode((NvU16)pTiming2ByteCode[idx], pTiming); + } } - pTiming->etc.status = NVT_STATUS_DISPLAYID_7N(++count); - - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type7:#%2d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)((pTiming->interlaced ? 2 : 1)*pTiming->VVisible), - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0'; - - pTiming->etc.rep = 0x1; + if (status == NVT_STATUS_SUCCESS) + { + pTiming->etc.status = NVT_STATUS_DISPLAYID_8N(++count); + return status; + } return status; } @@ -1733,6 +1756,7 @@ parseDisplayId20Timing9Descriptor( } } pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0'; + pTiming->etc.rep = 0x1; return status; } @@ -1742,7 +1766,8 @@ NVT_STATUS parseDisplayId20Timing10Descriptor( const void *pDescriptor, NVT_TIMING *pTiming, - NvU8 payloadBytes) + NvU8 payloadBytes, + NvU8 count) { NVT_STATUS status = NVT_STATUS_SUCCESS; const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR* p6bytesDescriptor = NULL; @@ -1810,7 +1835,11 @@ parseDisplayId20Timing10Descriptor( break; } - if (status == NVT_STATUS_SUCCESS) return status; + if (status == NVT_STATUS_SUCCESS) + { + pTiming->etc.status = NVT_STATUS_DISPLAYID_10N(++count); + return status; + } return status; } diff --git a/src/common/modeset/timing/nvt_dmt.c b/src/common/modeset/timing/nvt_dmt.c index d644d37eb0..acb9b9782f 100644 --- a/src/common/modeset/timing/nvt_dmt.c +++ b/src/common/modeset/timing/nvt_dmt.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -34,7 +34,7 @@ PUSH_SEGMENTS -// DMT table +// DMT table 2-1 // Macro to declare a TIMING initializer for given parameters without border #define DMT_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rr,pclk,id) \ {hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',NVT_PROGRESSIVE,pclk,{0,rr,set_rrx1k(pclk,ht,vt),0,0x1,{0},{0},{0},{0},NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT,id),"VESA DMT"}} @@ -192,6 +192,43 @@ NVT_STATUS NvTiming_EnumDMT(NvU32 dmtId, NVT_TIMING *pT) return NVT_STATUS_ERR; } +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS NvTiming_EnumStdTwoBytesCode(NvU16 std2ByteCode, NVT_TIMING *pT) +{ + NvU32 aspect, width, height, rr; + + if ((pT == NULL) || (std2ByteCode == 0)) + { + return NVT_STATUS_ERR; + } + + // The value in the EDID = (Horizontal active pixels/8) - 31 + width = (std2ByteCode & 0x0FF) + 31; + width <<= 3; + rr = ((std2ByteCode >> 8) & 0x3F) + 60; // bits 5->0 + + // get the height + aspect = ((std2ByteCode >> 8) & 0xC0); // aspect ratio at bit 7:6 + + if (aspect == 0x00) height = width * 5 / 8; // 16:10 + else if (aspect == 0x40) height = width * 3 / 4; // 4:3 + else if (aspect == 0x80) height = width * 4 / 5; // 5:4 + else height = width * 9 / 16; // 16:9 + + // try to get the timing from DMT or DMT_RB + if (NvTiming_CalcDMT(width, height, rr, 0, pT) == NVT_STATUS_SUCCESS) + { + return NVT_STATUS_SUCCESS; + } + // try to get the timing from DMT_RB2 + else if (NvTiming_CalcDMT_RB2(width, height, rr, 0, pT) == NVT_STATUS_SUCCESS) + { + return NVT_STATUS_SUCCESS; + } + + return NVT_STATUS_ERR; +} + CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS NvTiming_CalcDMT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT) { @@ -269,4 +306,42 @@ NVT_STATUS NvTiming_CalcDMT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, return NVT_STATUS_ERR; } +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS NvTiming_CalcDMT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT) +{ + NVT_TIMING *p = (NVT_TIMING *)DMT; + + if (pT == NULL) + return NVT_STATUS_ERR; + + if (width == 0 || height == 0 || rr == 0) + return NVT_STATUS_ERR; + + // no interlaced DMT timing + if ((flag & NVT_PVT_INTERLACED_MASK) != 0) + return NVT_STATUS_ERR; + + while (p->HVisible != 0 && p->VVisible != 0) + { + // select only reduced-bandwidth timing. + if (NVT_GET_TIMING_STATUS_TYPE(p->etc.status) == NVT_TYPE_DMT_RB_2) + { + if ((NvU32)p->HVisible == width && + (NvU32)p->VVisible == height && + (NvU32)p->etc.rr == rr) + { + NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING)); + *pT = *p; + pT->etc.rrx1k = axb_div_c((NvU32)pT->pclk, (NvU32)10000*(NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal); + NVT_SNPRINTF((char *)pT->etc.name, 40, "DMT-RB2:%dx%dx%dHz",width, height, rr); + pT->etc.name[39] = '\0'; + pT->etc.rgb444.bpc.bpc8 = 1; + return NVT_STATUS_SUCCESS; + } + } + p ++; + } + return NVT_STATUS_ERR; +} + POP_SEGMENTS diff --git a/src/common/modeset/timing/nvt_edid.c b/src/common/modeset/timing/nvt_edid.c index f2f57616b3..681b3104ae 100644 --- a/src/common/modeset/timing/nvt_edid.c +++ b/src/common/modeset/timing/nvt_edid.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -1079,15 +1079,17 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID // add the detailed timings in 18-byte long display descriptor parse861ExtDetailedTiming(pExt, p861Info->basic_caps, pInfo); - if (p861Info->revision >= NVT_CTA861_REV_H && p861Info->total_did_type10db != 0) + if (p861Info->revision >= NVT_CTA861_REV_H) { - parseCta861DIDType10VideoTimingDataBlock(p861Info, pInfo); + if (p861Info->total_did_type7db != 0) parseCta861DIDType7VideoTimingDataBlock(p861Info, pInfo); + if (p861Info->total_did_type8db != 0) parseCta861DIDType8VideoTimingDataBlock(p861Info, pInfo); + if (p861Info->total_did_type10db != 0) parseCta861DIDType10VideoTimingDataBlock(p861Info, pInfo); } // CEA861-F at 7.5.12 section about VFPDB block. - if (p861Info->revision >= NVT_CEA861_REV_F && p861Info->total_vfpdb != 0) + if (p861Info->revision >= NVT_CEA861_REV_F && (p861Info->total_svr != 0 || p861Info->valid.NVRDB == 1)) { - parse861bShortPreferredTiming(p861Info, pInfo, FROM_CTA861_EXTENSION); + parseCta861NativeOrPreferredTiming(p861Info, pInfo, FROM_CTA861_EXTENSION); } k++; @@ -1175,6 +1177,27 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID // find out the total established timings - base EDID and then the LDDs parseEdidEstablishedTiming(pInfo); + // remove the T8VTDB timing if it co-existed in standard or established timings + if (pInfo->ext861.revision >= NVT_CTA861_REV_H && pInfo->ext861.total_did_type8db != 0 && pInfo->total_timings > 1) + { + for (i = 0; i < pInfo->total_timings; i++) + { + if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == NVT_TYPE_CTA861_DID_T8) + { + if (isMatchedStandardTiming(pInfo, &pInfo->timing[i]) || isMatchedEstablishedTiming(pInfo, &pInfo->timing[i])) + { + for (j = i; j < pInfo->total_timings - 1; j++) + { + // remove the entry by moving the next entry up. + pInfo->timing[j] = pInfo->timing[j+1]; + } + NVMISC_MEMSET(&pInfo->timing[pInfo->total_timings-1], 0, sizeof(NVT_TIMING)); + pInfo->total_timings--; i--; + } + } + } + } + getEdidHDM1_4bVsdbTiming(pInfo); // Assert if no timings were found (due to a bad EDID) or if we mistakenly @@ -1286,7 +1309,38 @@ void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo) } } } +} + +CODE_SEGMENT(PAGE_DD_CODE) +NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT) +{ + NvU32 j; + for (j = 0; j < pInfo->total_timings; j++) + { + if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_STD && + NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT)) + { + return NV_TRUE; + } + } + return NV_FALSE; +} + +CODE_SEGMENT(PAGE_DD_CODE) +NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT) +{ + NvU32 j; + + for (j = 0; j < pInfo->total_timings; j++) + { + if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_EST && + NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT)) + { + return NV_TRUE; + } + } + return NV_FALSE; } CODE_SEGMENT(PAGE_DD_CODE) @@ -1390,7 +1444,7 @@ CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k) { NvU32 i, j; - NvU32 preferred_cea, preferred_displayid_dtd, preferred_dtd1, dtd1, map0, map1, map2, map3, map4, ceaIndex, max, cvt; + NvU32 native_cta, preferred_cta, preferred_displayid_dtd, preferred_dtd1, dtd1, map0, map1, map2, map3, map4, ceaIndex, max, cvt; NVT_TIMING *pEdidTiming; NVT_EDID_DD_RANGE_CVT *pCVT = NULL; NVT_TIMING cvtTiming; @@ -1406,7 +1460,9 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f // the timing mapping index : // - // preferred_cea - the "prefer SVD" in CEA-861-F (i.e. A Sink that prefers a Video Format that is not listed as an SVD in Video Data Block, but instead listed in YCBCR 4:2:0 VDB) + // native_cta - the "native resoluiotn of the sink" in the CTA861.6 A Source shall override any other native video resolution indicators + // if the Source supports NVRDB and the NVRDB was found in the E-EDID + // preferred_cta - the "prefer SVD" in CTA-861-F (i.e. A Sink that prefers a Video Format that is not listed as an SVD in Video Data Block, but instead listed in YCBCR 4:2:0 VDB) // preferred_displayid_dtd - the "prefer detailed timing of DispalyID" extension // preferred_dtd1 - the first deatiled timing and PTM flag is enable // dtd1 - the first detailed timing @@ -1416,7 +1472,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f // map3 - the "closest" match to the panel's native timing (i.e. the first DTD timing or the short 861B/C/D timings with "native" flag). // map4 - the "closest" match with the same refresh rate // max - the timing with the max visible area - preferred_cea = preferred_displayid_dtd = preferred_dtd1 = dtd1 = map0 = map1 = map2 = map3 = map4 = ceaIndex = pEdidInfo->total_timings; + native_cta = preferred_cta = preferred_displayid_dtd = preferred_dtd1 = dtd1 = map0 = map1 = map2 = map3 = map4 = ceaIndex = pEdidInfo->total_timings; max = cvt = 0; for (i = 0; i < pEdidInfo->total_timings; i++) { @@ -1440,7 +1496,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f map0 = i; } - if ( (NVT_PREFERRED_TIMING_IS_CEA(pEdidTiming[i].etc.flag)) || + if ( (NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag)) || ((0 == (flag & NVT_FLAG_EDID_861_ST)) && NVT_PREFERRED_TIMING_IS_DTD1(pEdidTiming[i].etc.flag, pEdidTiming[i].etc.status)) || (NVT_PREFERRED_TIMING_IS_DISPLAYID(pEdidTiming[i].etc.flag)) || (NVT_IS_NATIVE_TIMING(pEdidTiming[i].etc.status))) @@ -1479,10 +1535,14 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f } // find out the preferred timing just in case of cea_vfpdb is existed - if (preferred_cea == pEdidInfo->total_timings && - NVT_PREFERRED_TIMING_IS_CEA(pEdidTiming[i].etc.flag)) + if (native_cta == pEdidInfo->total_timings && NVT_NATIVE_TIMING_IS_CTA(pEdidTiming[i].etc.flag)) + { + native_cta = i; + } + + if (preferred_cta == pEdidInfo->total_timings && NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag)) { - preferred_cea = i; + preferred_cta = i; } // find out the preferred timing just in case @@ -1741,7 +1801,8 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f if (flag & NVT_FLAG_NV_PREFERRED_TIMING) { *pT = (preferred_displayid_dtd != pEdidInfo->total_timings) ? pEdidTiming[preferred_displayid_dtd] : - (preferred_cea != pEdidInfo->total_timings) ? pEdidTiming[preferred_cea] : + (native_cta != pEdidInfo->total_timings) ? pEdidTiming[native_cta] : + (preferred_cta != pEdidInfo->total_timings) ? pEdidTiming[preferred_cta] : (preferred_dtd1 != pEdidInfo->total_timings) ? pEdidTiming[preferred_dtd1] : pEdidTiming[dtd1]; // what if DTD1 itself is filtered out, in such case dtd1 index points to an invalid timing[]? @@ -1998,7 +2059,7 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal { ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION); return ret; - } + } // check block 0 checksum value if (!isChecksumValid(pEdid)) @@ -2313,7 +2374,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) } else if (ctaBlockTag == NVT_CEA861_TAG_EXTENDED_FLAG) { - if (*pData_collection == NVT_CEA861_EXT_TAG_HF_EEODB) + if (*pData_collection == NVT_CTA861_EXT_TAG_HF_EEODB) { if ((p->bVersionNumber != 0x01) || (p->bRevisionNumber != 0x03)) { @@ -2334,7 +2395,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) else pData_collection += ctaPayload; } - else if (ctaBlockTag == NVT_CEA861_TAG_RSVD || ctaBlockTag == NVT_CEA861_TAG_RSVD1) + else if (ctaBlockTag == NVT_CEA861_TAG_RSVD) { ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_TAG); pData_collection += ctaPayload; diff --git a/src/common/modeset/timing/nvt_edidext_861.c b/src/common/modeset/timing/nvt_edidext_861.c index 766f3739b1..ee16907d38 100644 --- a/src/common/modeset/timing/nvt_edidext_861.c +++ b/src/common/modeset/timing/nvt_edidext_861.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -371,10 +371,36 @@ static const HDMI3DDETAILS HDMI_MANDATORY_3D_FORMATS[] = {20, NVT_HDMI_3D_SUPPORTED_SIDEBYSIDEHALF_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH} // 1920 x 1080i @ 50 Hz }; static NvU32 MAX_HDMI_MANDATORY_3D_FORMAT = sizeof(HDMI_MANDATORY_3D_FORMATS) / sizeof(HDMI_MANDATORY_3D_FORMATS[0]); - static const NVT_VIDEO_INFOFRAME DEFAULT_VIDEO_INFOFRAME = {/*header*/2,2,13, /*byte1*/0, /*byte2*/0x8, /*byte3*/0, /*byte4*/0, /*byte5*/0, /*byte6~13*/0,0,0,0,0,0,0,0}; static const NVT_AUDIO_INFOFRAME DEFAULT_AUDIO_INFOFRAME = {/*header*/4,1,10, /*byte1*/0, /*byte2*/0, /*byte3*/0, /*byte*/0, /*byte5*/0, /*byte6~10*/0,0,0,0,0}; -static const NVT_VENDOR_SPECIFIC_INFOFRAME DEFAULT_VENDOR_SPECIFIC_INFOFRAME = {/*header*/{0x01,1,6}, {/*byte1*/3, /*byte2*/0x0c, /*byte3*/0, /*byte4*/0, /*byte5*/0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}}; + +CODE_SEGMENT(PAGE_DD_CODE) +static NvU8 +getExistedCTATimingSeqNumber( + NVT_EDID_INFO *pInfo, + enum NVT_TIMING_TYPE timingType) +{ + NvU8 count = 0; + NvU8 i = 0; + + switch (timingType) + { + case NVT_TYPE_CTA861_DID_T7: + case NVT_TYPE_CTA861_DID_T8: + case NVT_TYPE_CTA861_DID_T10: + break; + default: + return count; + } + + for (i = 0; i< pInfo->total_timings; i++) + { + if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == timingType) + ++count; + } + + return count; +} // parse the 861 detailed timing info CODE_SEGMENT(PAGE_DD_CODE) @@ -397,7 +423,7 @@ void parse861ExtDetailedTiming(NvU8 *pEdidExt, // Get all detailed timings in CEA ext block pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pEdidExt[pEIA861->offset]; - while((NvU8 *)pDTD + sizeof(DETAILEDTIMINGDESCRIPTOR) < (pEdidExt + sizeof(EDIDV1STRUC) - 1) && + while((NvU8 *)pDTD + sizeof(DETAILEDTIMINGDESCRIPTOR) < (pEdidExt + sizeof(EDIDV1STRUC)) && pDTD->wDTPixelClock != 0) { NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); @@ -687,25 +713,28 @@ void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, } } -// Currently, we only focus on the particular application in CEA861-F spec described +// Currently, the SVR both used in the NVRDB and VFPDB. // "One particular application is a Sink that prefers a Video Format that is not listed as an SVD in a VDB // but instead listed in a YCBCR 4:2:0 Video Data Block" CODE_SEGMENT(PAGE_DD_CODE) -void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, - void *pRawInfo, - NVT_CTA861_ORIGIN flag) +void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, + void *pRawInfo, + NVT_CTA861_ORIGIN flag) { NvU32 isMatch,i,j = 0; NVT_TIMING preferTiming; NVT_EDID_INFO *pInfo = NULL; NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL; + NvU8 nativeSvr = 0; NvU8 *pSvr = pExt861->svr_vfpdb; - NvU8 totalSvr = pExt861->total_vfpdb; + NvU8 totalSvr = pExt861->total_svr; NvU8 kth = 0; NvU8 extKth = 0; NvU8 DTDCount = 0; NvU8 extDTDCount = 0; + NvU8 DIDT7Count = 0; + NvU8 DIDT10Count = 0; if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) { @@ -723,29 +752,38 @@ void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, // finding all the DTD in Base 0 or CTA861 if (flag == FROM_CTA861_EXTENSION) { + // get the NVRDB, from the spec this native resolution has more high priority than others + if (pExt861->valid.NVRDB == 1) + { + nativeSvr = pExt861->native_video_resolution_db.native_svr; + totalSvr = 1; + } + for (j = 0; j < pInfo->total_timings; j++) { - if (NVT_IS_DTD(pInfo->timing[j].etc.status)) - { - DTDCount++; - } - else if (NVT_IS_EXT_DTD(pInfo->timing[j].etc.status)) - { - extDTDCount++; - } + if (NVT_IS_DTD(pInfo->timing[j].etc.status)) DTDCount++; + else if (NVT_IS_EXT_DTD(pInfo->timing[j].etc.status)) extDTDCount++; + else if (NVT_IS_CTA861_DID_T7(pInfo->timing[j].etc.status)) DIDT7Count++; + else if (NVT_IS_CTA861_DID_T10(pInfo->timing[j].etc.status)) DIDT10Count++; } } - // TODO : this only handle single SVR right now + // this only handle single SVR right now for (i = 0; i < totalSvr; i++) { - NvU8 svr = pSvr[i]; + NvU8 svr = 0; NvU8 vic = 0; - if (svr == 0 || svr == 128 || (svr >= 161 && svr <= 192) || svr == 255) - continue; + if (pExt861->valid.NVRDB == 1) + svr = nativeSvr; + else + svr = pSvr[i]; + + // Reserved + if (svr == 0 || svr == 128 || (svr >= 176 && svr <= 192) || svr == 255) + continue; - // Kth 18bytes DTD in the EDID + // Interpret as the Kth 18-byte DTD, where K = SVR - 128 (for K = 1 to 16) in both base0 and CTA block if (svr >= 129 && svr <= 144) { kth = svr - 128; @@ -756,39 +794,81 @@ void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, { if (kth <= DTDCount) { - if (NVT_IS_DTDn(pInfo->timing[j].etc.status, kth)) - { - pInfo->timing[j].etc.flag |= NVT_FLAG_CEA_PREFERRED_TIMING; + if (NVT_IS_DTDn(pInfo->timing[j].etc.status, kth)) break; - } } else { extKth = kth - DTDCount; - if (NVT_IS_EXT_DTDn(pInfo->timing[j].etc.status, extKth)) - { - pInfo->timing[j].etc.flag |= NVT_FLAG_CEA_PREFERRED_TIMING; + if (NVT_IS_EXT_DTDn(pInfo->timing[j].etc.status, extKth)) break; - } } } + + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; } } else if (svr >= 145 && svr <= 160) { - // TODO : Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor, - // where N = SVR – 144 (for N = 1 to 16) + // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor + // where N = SVR – 144 (for N = 1 to 16) + kth = svr - 144; + + if (flag == FROM_CTA861_EXTENSION) + { + for (j = 0; j < pInfo->total_timings; j++) + { + if (kth <= DIDT7Count) // pick the Nth 20-byte first + { + if (NVT_IS_CTA861_DID_T7n(pInfo->timing[j].etc.status, kth)) + break; + } + else + { + extKth = kth - DIDT7Count; // pick the T10 CVT-based timing then + if (NVT_IS_CTA861_DID_T10n(pInfo->timing[j].etc.status, extKth)) + break; + } + } + + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; + } + } + else if (svr >= 161 && svr <= 175) + { + // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N + // where N = SVR - 160 (for N = 1 to 15) break; } else if (svr == 254) { - // TODO : Interpret as the timing format indicated by the first code of the first T8VTDB + // Interpret as the timing format indicated by the first code of the first T8VTDB + if (flag == FROM_CTA861_EXTENSION) + { + for (j = 0; j < pInfo->total_timings; j++) + { + if (NVT_IS_CTA861_DID_T8_1(pInfo->timing[j].etc.status)) + { + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; + break; + } + } + } break; } else // assign corresponding CEA format's timing from pre-defined CE timing table, EIA861B { // ( SVR >= 1 and SVR <= 127) and (SVR >= 193 and SVR <= 253) - vic = NVT_GET_CTA_8BIT_VIC(svr); + vic = NVT_GET_CTA_8BIT_VIC(svr); preferTiming = EIA861B[vic-1]; if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) @@ -798,19 +878,25 @@ void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, isMatch = NvTiming_IsTimingExactEqual(&pInfo->timing[j], &preferTiming); if (isMatch && (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_861ST)) { - pInfo->timing[j].etc.flag |= NVT_FLAG_CEA_PREFERRED_TIMING; + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; break; } } } else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) - { + { for (j = 0; j < pDisplayID20->total_timings; j++) { isMatch = NvTiming_IsTimingExactEqual(&pDisplayID20->timing[j], &preferTiming); if (isMatch && (NVT_GET_TIMING_STATUS_TYPE(pDisplayID20->timing[j].etc.status) == NVT_TYPE_EDID_861ST)) { - pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CEA_PREFERRED_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; + if (pExt861->valid.NVRDB == 1) + pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; + else + pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; break; } } @@ -1294,7 +1380,9 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, NvU32 vendor_index = 0; NvU32 yuv420vdb_index = 0; NvU32 yuv420cmdb_index = 0; - NvU32 didT10_index = 0; + NvU8 didT7_index = 0; + NvU8 didT8_index = 0; + NvU8 didT10_index = 0; NvU8 svr_index = 0; NvU32 ieee_id = 0; NvU32 tag, ext_tag, payload; @@ -1309,7 +1397,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, /*don't allow data colleciton totally size larger than [127 - 5 (tag, revision, offset, describing native video format, checksum)]*/ if ((i + payload > size) || (i + payload > 122)) { - return NVT_STATUS_ERR; + break; } // move the pointer to the payload section or extended Tag Code i++; @@ -1324,7 +1412,6 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, case NVT_CEA861_TAG_SPEAKER_ALLOC: case NVT_CEA861_TAG_VESA_DTC: case NVT_CEA861_TAG_RSVD: - case NVT_CEA861_TAG_RSVD1: break; case NVT_CEA861_TAG_VENDOR: if (payload < 3) return NVT_STATUS_ERR; @@ -1341,11 +1428,35 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, else if (ext_tag == NVT_CEA861_EXT_TAG_HDR_STATIC_METADATA && payload < 3) return NVT_STATUS_ERR; else if (ext_tag == NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO && payload < 4) return NVT_STATUS_ERR; else if (ext_tag == NVT_CTA861_EXT_TAG_SCDB && payload < 7) return NVT_STATUS_ERR; - else if (ext_tag == NVT_CEA861_EXT_TAG_HF_EEODB && payload != 2) return NVT_STATUS_ERR; - else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X) + else if (ext_tag == NVT_CTA861_EXT_TAG_HF_EEODB && payload != 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VII && payload <= 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VIII && payload <= 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X && payload <= 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_NATIVE_VIDEO_RESOLUTION) { - if (((p[i+1] & 0x70) >> 4 == 0) && (payload-2) % 6) return NVT_STATUS_ERR; - if (((p[i+1] & 0x70) >> 4 == 1) && (payload-2) % 7) return NVT_STATUS_ERR; + if (payload != 2 && payload != 3 && payload != 7) return NVT_STATUS_ERR; + } + + if (payload > 2) + { + if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VII) + { + if ((payload-2) != 20) return NVT_STATUS_ERR; // only support 20-bytes + if ((p[i+1] & 0x7) != 2) return NVT_STATUS_ERR; // Block Revision shall be 2 + if ((p[i+1] & 0x70) >> 4 != 0) return NVT_STATUS_ERR; // Not allow extra byte + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VIII) + { + if ((payload-2) < 1) return NVT_STATUS_ERR; // minimum one code supported + if ((p[i+1] & 0x7) != 1) return NVT_STATUS_ERR; // Block Revision shall be 1 + if ((p[i+1] & 0xC0) >> 6 != 0) return NVT_STATUS_ERR; // Not allow others than DMT Timing + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X) + { + if ((p[i+1] & 0x7) != 0) return NVT_STATUS_ERR; // Block Revision shall be 0 + if (((p[i+1] & 0x70) >> 4 == 0) && (payload-2) % 6) return NVT_STATUS_ERR; // supported 6-bytes descriptors + if (((p[i+1] & 0x70) >> 4 == 1) && (payload-2) % 7) return NVT_STATUS_ERR; // supported 7-bytes descriptors + } } } break; @@ -1459,7 +1570,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, else if (ext_tag == NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE && payload >= 2) { // when present, indicates the order of preference for selected Video Formats listed as DTDs and/or SVDs throughout Block 0 and the CTA Extensions of the - // order of SVD preferred modes shall take precedence over preferred modes defined elsewhere in the EDID/CEA861 blocks + // order of SVD preferred modes shall take precedence over preferred modes defined elsewhere in the EDID/CEA861 blocks // exclude the extended tag i++; payload--; @@ -1468,7 +1579,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, { p861info->svr_vfpdb[svr_index] = p[i]; } - p861info->total_vfpdb = svr_index; + p861info->total_svr = svr_index; } else if (ext_tag == NVT_CEA861_EXT_TAG_YCBCR420_VIDEO && payload >= 2) { @@ -1566,11 +1677,83 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, i += payload; } } - else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X && ((payload-2) % 6 == 0 || (payload-2) % 7 == 0)) + else if (ext_tag == NVT_CTA861_EXT_TAG_NATIVE_VIDEO_RESOLUTION) { + if (payload != 2 && payload != 3 && payload != 7) break; + + i++; payload--; + p861info->native_video_resolution_db.native_svr = p[i]; + p861info->valid.NVRDB = 1; + i++; payload--; + if (payload != 0) + { + p861info->native_video_resolution_db.option.img_size = p[i] & 0x01; + p861info->native_video_resolution_db.option.sz_prec = (p[i] & 0x80) >> 7; - p861info->did_type10_data_block[didT10_index].version.revision = p[i] & 0x7; + i++; payload--; + if (p861info->native_video_resolution_db.option.img_size == 1) + { + for (j = 0; j< payload; j++, i++) + { + p861info->native_video_resolution_db.image_size[j] = p[i]; + } + } + } + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VII) + { + if( payload != 22) break; + + i++; payload--; + p861info->did_type7_data_block[didT7_index].version.revision = p[i] & 0x07; + p861info->did_type7_data_block[didT7_index].version.dsc_pt = (p[i] & 0x08) >> 3; + p861info->did_type7_data_block[didT7_index].version.t7_m = (p[i] & 0x70) >> 4; + + //do not consider Byte 3 + i++; payload--; + + p861info->did_type7_data_block[didT7_index].total_descriptors = + (NvU8)(payload / (NVT_CTA861_DID_TYPE7_DESCRIPTORS_LENGTH + p861info->did_type7_data_block[didT7_index].version.t7_m)); + + for (j = 0; j < payload; j++, i++) + { + p861info->did_type7_data_block[didT7_index].payload[j] = p[i]; + } + // next type7 data block if it exists + p861info->total_did_type7db = ++didT7_index; + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_VIII) + { + if (payload <= 2) break; + + i++; payload--; + p861info->did_type8_data_block[didT8_index].version.revision = p[i] & 0x07; + p861info->did_type8_data_block[didT8_index].version.tcs = (p[i] & 0x08) >> 3; + p861info->did_type8_data_block[didT8_index].version.t8y420 = (p[i] & 0x20) >> 5; + p861info->did_type8_data_block[didT8_index].version.code_type = (p[i] & 0xC0) >> 6; + + //do not consider Byte 3 + i++; payload--; + + if (p861info->did_type8_data_block[didT8_index].version.tcs == 0) + p861info->did_type8_data_block[didT8_index].total_descriptors = (NvU8)payload; + else if (p861info->did_type8_data_block[didT8_index].version.tcs == 1) + p861info->did_type8_data_block[didT8_index].total_descriptors = (NvU8)(payload / 2); + + for (j = 0; j < payload; j++, i++) + { + p861info->did_type8_data_block[didT8_index].payload[j] = p[i]; + } + // next type7 data block if it exists + p861info->total_did_type8db = ++didT8_index; + } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X) + { + if (payload < 8 || ((payload-2) % 6 != 0 && (payload-2) % 7 != 0)) break; + + i++; payload--; + p861info->did_type10_data_block[didT10_index].version.revision = p[i] & 0x07; p861info->did_type10_data_block[didT10_index].version.t10_m = (p[i] & 0x70) >> 4; // do not consider Byte 3 @@ -1586,8 +1769,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, p861info->did_type10_data_block[didT10_index].payload[j] = p[i]; } // next type10 data block if it exists - p861info->total_did_type10db++; - didT10_index++; + p861info->total_did_type10db = ++didT10_index; } else if(ext_tag == NVT_CTA861_EXT_TAG_SCDB && payload >= 7) // sizeof(HDMI Forum Sink Capability Data Block) ranges between 7 to 31 bytes { @@ -1606,7 +1788,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, p861info->hfscdbSize = MIN(payload - 3, NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH); p861info->valid.SCDB = 1; } - else if (ext_tag == NVT_CEA861_EXT_TAG_HF_EEODB && payload == 2) + else if (ext_tag == NVT_CTA861_EXT_TAG_HF_EEODB && payload == 2) { // Skip over extended tag i++; payload--; @@ -1629,7 +1811,10 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, } } - p861info->total_vsdb = (NvU8)vendor_index; + if (p861info) + { + p861info->total_vsdb = (NvU8)vendor_index; + } return NVT_STATUS_SUCCESS; } @@ -1895,8 +2080,9 @@ NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_ // "NVT_VIDEO_INFOFRAME" / "VIDEO_INFOFRAME" / "DEFAULT_VIDEO_INFOFRAME" / "NVM_DISP_STATE" etc.. // to accept the new ACE0-3 bits supported in the future. Right now no any sink to support this. // - // Based on the latest CTA-861-G-Errata.pdf file, we need to do following logic to get the correct CTA861 version - // When Y2 = 0, the following algorithm shall be used for AVI InfoFrame version selection: + // Based on the latest CTA-861-H.pdf file, we need to do following logic to get the correct CTA861 version + // When Y=7, the IDO defines the C, EC and ACE fields, it shall use AVI InfoFrame Version 4. + // When Y < 7, the following algorithm shall be used for AVI InfoFrame version selection: // if (C=3 and EC=7) // Sources shall use AVI InfoFrame Version 4. // Else if (VIC>=128) @@ -1907,7 +2093,11 @@ NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_ // if (pCtrl) { - if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) <= NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE) // this shall be as 0 always. + if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED) + { + pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; + } + else if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) < NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED) { if ((nvt_get_bits(pInfoFrame->byte2, NVT_VIDEO_INFOFRAME_BYTE2_C1C0_MASK, NVT_VIDEO_INFOFRAME_BYTE2_C1C0_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE2_C1C0_EXT_COLORIMETRY) && //EC2-0 is based on the 7.5.5 at CTA861-G which DCI-P3 bit defined or notat byte4 @@ -1935,7 +2125,7 @@ NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_ if (pInfoFrame->version == NVT_VIDEO_INFOFRAME_VERSION_2) { - nvt_nvu8_set_bits(pInfoFrame->byte4, 0, NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_MASK, NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->byte4, 0, NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_MASK, NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_SHIFT); } else if (pInfoFrame->version == NVT_VIDEO_INFOFRAME_VERSION_1) { @@ -2160,7 +2350,7 @@ NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, N NvU8 HDMIFormat; // parameter check - if (pEdidInfo == NULL || pInfoFrame == NULL) + if (pEdidInfo == NULL || pInfoFrame == NULL || pCtrl == NULL) { return NVT_STATUS_INVALID_PARAMETER; } @@ -2173,104 +2363,129 @@ NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, N // initialize the infoframe buffer - *pInfoFrame = DEFAULT_VENDOR_SPECIFIC_INFOFRAME; + nvt_nvu8_set_bits(pInfoFrame->Header.type, NVT_HDMI_VS_HB0_VALUE, NVT_HDMI_VS_HB0_MASK, NVT_HDMI_VS_HB0_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Header.version, NVT_HDMI_VS_HB1_VALUE, NVT_HDMI_VS_HB1_MASK, NVT_HDMI_VS_HB1_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Header.length, NVT_HDMI_VS_HB2_VALUE, NVT_HDMI_VS_HB2_MASK, NVT_HDMI_VS_HB2_SHIFT); + + if (pCtrl->HDMIRevision == 14) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_1_4, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_1_4, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_1_4, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT); + } + else if (pCtrl->HDMIRevision >= 20) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_2_0, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_2_0, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_2_0, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT); + } // init the header (mostly done in default Infoframe) pInfoFrame->Header.length = offsetof(NVT_VENDOR_SPECIFIC_INFOFRAME_PAYLOAD, optionalBytes); // construct the desired infoframe contents based on the control - if (pCtrl) - { - // clear all static reserved fields - nvt_nvu8_set_bits(pInfoFrame->Data.byte4, 0, NVT_HDMI_VS_BYTE4_RSVD_MASK, NVT_HDMI_VS_BYTE4_RSVD_SHIFT); + + // clear all static reserved fields + nvt_nvu8_set_bits(pInfoFrame->Data.byte4, 0, NVT_HDMI_VS_BYTE4_RSVD_MASK, NVT_HDMI_VS_BYTE4_RSVD_SHIFT); - // setup the parameters - nvt_nvu8_set_bits(pInfoFrame->Data.byte4, pCtrl->HDMIFormat, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_MASK, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_SHIFT); + // setup the parameters + nvt_nvu8_set_bits(pInfoFrame->Data.byte4, pCtrl->HDMIFormat, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_MASK, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_SHIFT); - // determine what the format is -- if disabled, force the format to NONE. - if (pCtrl->Enable) + // determine what the format is -- if disabled, force the format to NONE. + if (pCtrl->Enable) + { + HDMIFormat = pCtrl->HDMIFormat; + } + else + { + HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE; + } + + switch(HDMIFormat) + { + case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE: { - HDMIFormat = pCtrl->HDMIFormat; + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT); + break; } - else + case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT: { - HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE; + // Note: extended resolution frames are not yet fully supported + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->HDMI_VIC, NVT_HDMI_VS_BYTE5_HDMI_VIC_MASK, NVT_HDMI_VS_BYTE5_HDMI_VIC_SHIFT); + break; } - - switch(HDMIFormat) + case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D: { - case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE: - { - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT); - break; - } - case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT: + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTE5_HDMI_RSVD_MASK, NVT_HDMI_VS_BYTE5_HDMI_RSVD_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->ThreeDStruc, NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK, NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT); + + // side by side half requires additional format data in the infoframe. + if (NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEHALF == pCtrl->ThreeDStruc) { - // Note: extended resolution frames are not yet fully supported - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->HDMI_VIC, NVT_HDMI_VS_BYTE5_HDMI_VIC_MASK, NVT_HDMI_VS_BYTE5_HDMI_VIC_SHIFT); - break; + nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], pCtrl->ThreeDDetail, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SHIFT); + optIdx++; } - case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D: + if (pCtrl->MetadataPresent) { - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTE5_HDMI_RSVD_MASK, NVT_HDMI_VS_BYTE5_HDMI_RSVD_SHIFT); - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->ThreeDStruc, NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK, NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); - // side by side half requires additional format data in the infoframe. - if (NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEHALF == pCtrl->ThreeDStruc) + switch(pCtrl->MetadataType) { - nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], pCtrl->ThreeDDetail, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SHIFT); - optIdx++; - } - if (pCtrl->MetadataPresent) - { - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); - - switch(pCtrl->MetadataType) + case NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX: { - case NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX: + if (sizeof(pCtrl->Metadata) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX && + sizeof(pInfoFrame->Data.optionalBytes) - (optIdx + 1) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX) { - if (sizeof(pCtrl->Metadata) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX && - sizeof(pInfoFrame->Data.optionalBytes) - (optIdx + 1) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX) - { - nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_SHIFT); - nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_SHIFT); - ++optIdx; + nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_SHIFT); + ++optIdx; - NVMISC_MEMCPY(pCtrl->Metadata, &pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX); - optIdx += NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX; - } - else - { - // not enough data in the control struct or not enough room in the infoframe -- BOTH compile time issues!! - // ignore metadata. - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); - } - break; + NVMISC_MEMCPY(pCtrl->Metadata, &pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX); + optIdx += NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX; } - default: + else { - // unrecognised metadata, recover the best we can. - // note -- can not copy whatever is there because type implies length. + // not enough data in the control struct or not enough room in the infoframe -- BOTH compile time issues!! + // ignore metadata. nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); - RetCode = NVT_STATUS_ERR; } + break; + } + default: + { + // unrecognised metadata, recover the best we can. + // note -- can not copy whatever is there because type implies length. + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); + RetCode = NVT_STATUS_ERR; } - - } - else - { - nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); } - break; + } + else + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT); + } + break; } - // clear last byte of infoframe (reserved per spec). - pInfoFrame->Header.length += optIdx + 1; - for (; optIdx < sizeof(pInfoFrame->Data.optionalBytes); ++optIdx) - { - nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTENv_RSVD, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT); - } + + } + + if (pCtrl->ALLMEnable == 1) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_ALLM_MODE_EN, NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK, NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT); + } + else if (pCtrl->ALLMEnable == 0) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_ALLM_MODE_DIS, NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK, NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT); } + + // clear last byte of infoframe (reserved per spec). + pInfoFrame->Header.length += optIdx + 1; + for (; optIdx < sizeof(pInfoFrame->Data.optionalBytes); ++optIdx) + { + nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTENv_RSVD, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT); + } + return RetCode; } @@ -2294,6 +2509,13 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe( pInfoFrame->Header.firstLast = NVT_EMP_HEADER_FIRST_LAST; pInfoFrame->Header.sequenceIndex = 0x00; + if (pCtrl->EnableQMS) + { + nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_EMP_BYTE1_SYNC_ENABLE, + NVT_HDMI_EMP_BYTE1_SYNC_MASK, + NVT_HDMI_EMP_BYTE1_SYNC_SHIFT); + } + nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_EMP_BYTE1_VFR_ENABLE, NVT_HDMI_EMP_BYTE1_VFR_MASK, NVT_HDMI_EMP_BYTE1_VFR_SHIFT); @@ -2302,7 +2524,7 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe( NVT_HDMI_EMP_BYTE1_NEW_MASK, NVT_HDMI_EMP_BYTE1_NEW_SHIFT); - if (!pCtrl->EnableVRR) + if (!pCtrl->EnableVRR && !pCtrl->EnableQMS) { nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_EMP_BYTE1_END_ENABLE, NVT_HDMI_EMP_BYTE1_END_MASK, @@ -2318,7 +2540,7 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe( NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK, NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT); - nvt_nvu8_set_bits(pInfoFrame->Data.byte7, (pCtrl->EnableVRR ? 4 : 0), + nvt_nvu8_set_bits(pInfoFrame->Data.byte7, ((pCtrl->EnableVRR || pCtrl->EnableQMS) ? 4 : 0), NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK, NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT); @@ -2329,6 +2551,16 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe( NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK, NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT); } + else if (pCtrl->EnableQMS) + { + nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], 1, + NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK, + NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT); + nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], + NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_ENABLE, + NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK, + NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_SHIFT); + } if (pCtrl->ITTiming) { @@ -2363,6 +2595,67 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe( return RetCode; } +// Construct Adaptive Sync SDP +CODE_SEGMENT(PAGE_DD_CODE) +void NvTiming_ConstructAdaptiveSyncSDP( + const NVT_ADAPTIVE_SYNC_SDP_CTRL *pCtrl, + NVT_ADAPTIVE_SYNC_SDP *pSdp) +{ + if (!pCtrl || !pSdp) + { + return; + } + + // Initialize the infoframe + NVMISC_MEMSET(pSdp, 0, sizeof(*pSdp)); + + // Construct an infoframe to enable or disable Adaptive Sync SDP + pSdp->header.type = NVT_DP_ADAPTIVE_SYNC_SDP_PACKET_TYPE; + pSdp->header.version = NVT_DP_ADAPTIVE_SYNC_SDP_VERSION; + pSdp->header.length = NVT_DP_ADAPTIVE_SYNC_SDP_LENGTH; + + // Payload + if (pCtrl->bFixedVTotal) + { + nvt_nvu8_set_bits(pSdp->payload.db0, NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_REACHED, + NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT); + if (pCtrl->targetRefreshRate) + { + nvt_nvu8_set_bits(pSdp->payload.db3, pCtrl->targetRefreshRate & 0xff, + NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_SHIFT); + + nvt_nvu8_set_bits(pSdp->payload.db4, pCtrl->targetRefreshRate & 0x1, + NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_SHIFT); + } + } + else + { + nvt_nvu8_set_bits(pSdp->payload.db0, NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_VARIABLE, + NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT); + } + + if (pCtrl->minVTotal) + { + nvt_nvu8_set_bits(pSdp->payload.db1, pCtrl->minVTotal & 0xff, + NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_SHIFT); + nvt_nvu8_set_bits(pSdp->payload.db2, (pCtrl->minVTotal & 0xff00) >> 8, + NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_SHIFT); + } + + if (pCtrl->bRefreshRateDivider) + { + nvt_nvu8_set_bits(pSdp->payload.db4, NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_ENABLE, + NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_SHIFT); + } +} + // Enumerate Psf Timing CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS NvTiming_EnumNvPsfTiming(NvU32 nvPsfFormat, NVT_TIMING *pT) @@ -2990,6 +3283,7 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo) pHdmiInfo->cnmvrr = pHdmiForum->CNMVRR; pHdmiInfo->cinemaVrr = pHdmiForum->CinemaVRR; pHdmiInfo->m_delta = pHdmiForum->M_delta; + pHdmiInfo->qms = pHdmiForum->QMS; pHdmiInfo->fapa_end_extended = pHdmiForum->FAPA_End_Extended; // sixth byte @@ -3018,7 +3312,9 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo) pHdmiInfo->dsc_All_bpp = pHdmiForum->DSC_All_bpp; pHdmiInfo->dsc_Native_420 = pHdmiForum->DSC_Native_420; pHdmiInfo->dsc_1p2 = pHdmiForum->DSC_1p2; - + pHdmiInfo->qms_tfr_min = pHdmiForum->QMS_TFR_min; + pHdmiInfo->qms_tfr_max = pHdmiForum->QMS_TFR_max; + // ninth byte if (!remainingSize--) { @@ -3065,9 +3361,10 @@ void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo NVT_HDR10PLUS_INFO *pHdr10PlusInfo = NULL; if (pExt861 == NULL || pRawInfo == NULL) - { return; - } + + if(pExt861->vsvdb.ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID) + return; if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) { @@ -3084,26 +3381,153 @@ void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo return; } - if(pExt861->vsvdb.ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID) - { - return; - } - NVMISC_MEMSET(pHdr10PlusInfo, 0, sizeof(NVT_HDR10PLUS_INFO)); if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_HDR10PLUS_INFO)) - { return; - } NVMISC_MEMCPY(pHdr10PlusInfo, &pExt861->vsvdb.vendor_data, sizeof(NVT_HDR10PLUS_INFO)); } +CODE_SEGMENT(PAGE_DD_CODE) +void parseCta861DIDType7VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo) +{ + NvU8 i = 0; + NvU8 t7db_idx = 0; + NvU8 startSeqNum = 0; + + NVT_TIMING newTiming; + NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo; + const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pT7Descriptor = NULL; + NvU8 eachOfDescSize = sizeof(DISPLAYID_2_0_TIMING_7_DESCRIPTOR); + + for (t7db_idx = 0; t7db_idx < pExt861->total_did_type7db; t7db_idx++) + { + // 20 bytes + eachOfDescSize += pExt861->did_type7_data_block[t7db_idx].version.t7_m; + + if (pExt861->did_type7_data_block[t7db_idx].total_descriptors != NVT_CTA861_DID_TYPE7_DESCRIPTORS_MAX) + { + nvt_assert(0 && "payload descriptor invalid. expect T7VTDB only 1 descriptor"); + continue; + } + + if (pExt861->did_type7_data_block[t7db_idx].version.revision != 2 ) + { + nvt_assert(0 && "The revision supported by CTA-861 is not 2"); + } + + startSeqNum = getExistedCTATimingSeqNumber(pInfo, NVT_TYPE_CTA861_DID_T7); + + for (i = 0; i < pExt861->did_type7_data_block[i].total_descriptors; i++) + { + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); + if (NVT_STATUS_SUCCESS == parseDisplayId20Timing7Descriptor(&pExt861->did_type7_data_block[t7db_idx].payload[i*eachOfDescSize], + &newTiming, + startSeqNum+i)) + { + // T7VTDB shall not be used with video timing that can be expressed in an 18-byte DTD + if (newTiming.HVisible < 4096 && newTiming.VVisible < 4096 && newTiming.pclk < 65536) + { + nvt_assert(0 && "The timing can be expressed in an 18-byte DTD"); + continue; + } + + pT7Descriptor = (const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *) + &pExt861->did_type7_data_block[t7db_idx].payload[i*eachOfDescSize]; + + if (pT7Descriptor->options.is_preferred_or_ycc420 == 1 && newTiming.pclk > NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN) + { + newTiming.etc.yuv420.bpcs = 0; + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, + pInfo->hdmiForumInfo.dc_30bit_420, + pInfo->hdmiForumInfo.dc_36bit_420, 0, + pInfo->hdmiForumInfo.dc_48bit_420); + } + + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-T7:#%3d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + newTiming.etc.status = NVT_STATUS_CTA861_DID_T7N(NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status)); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; + + if (!assignNextAvailableTiming(pInfo, &newTiming)) + { + break; + } + } + } + } +} + +CODE_SEGMENT(PAGE_DD_CODE) +void parseCta861DIDType8VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo) +{ + NvU8 i = 0; + NvU8 t8db_idx = 0; + NvU8 startSeqNum = 0; + NvU8 codeSize = 0; + NvU8 codeType = 0; + + NVT_TIMING newTiming; + NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo; + + for (t8db_idx = 0; t8db_idx < pExt861->total_did_type8db; t8db_idx++) + { + codeType = pExt861->did_type8_data_block[t8db_idx].version.code_type; + codeSize = pExt861->did_type8_data_block[t8db_idx].version.tcs; + + if (codeType != 0 /*DMT*/) + { + nvt_assert(0 && "Not DMT code type!"); + continue; + } + + startSeqNum = getExistedCTATimingSeqNumber(pInfo, NVT_TYPE_CTA861_DID_T8); + + for (i=0; i < pExt861->did_type8_data_block[t8db_idx].total_descriptors; i++) + { + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); + + if (parseDisplayId20Timing8Descriptor(pExt861->did_type8_data_block[t8db_idx].payload, + &newTiming, codeType, codeSize, i, startSeqNum + i) == NVT_STATUS_SUCCESS) + { + if (pExt861->did_type8_data_block[t8db_idx].version.t8y420 == 1 && newTiming.pclk > NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN) + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, + pInfo->hdmiForumInfo.dc_30bit_420, + pInfo->hdmiForumInfo.dc_36bit_420, 0, + pInfo->hdmiForumInfo.dc_48bit_420); + } + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-T8:#%3d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + newTiming.etc.status = NVT_STATUS_CTA861_DID_T8N(NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status)); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; + + if (!assignNextAvailableTiming(pInfo, &newTiming)) + { + break; + } + } + } + } +} + CODE_SEGMENT(PAGE_DD_CODE) void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo) { NvU8 i = 0; NvU8 t10db_idx = 0; + NvU8 startSeqNum = 0; NVT_TIMING newTiming; NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo; @@ -3112,27 +3536,29 @@ void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, voi for (t10db_idx = 0; t10db_idx < pExt861->total_did_type10db; t10db_idx++) { + startSeqNum = getExistedCTATimingSeqNumber(pInfo, NVT_TYPE_CTA861_DID_T10); + // 6 or 7 bytes length - eachOfDescriptorsSize = sizeof(DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR) + pExt861->did_type10_data_block[t10db_idx].version.t10_m; + eachOfDescriptorsSize += pExt861->did_type10_data_block[t10db_idx].version.t10_m; for (i = 0; i < pExt861->did_type10_data_block[t10db_idx].total_descriptors; i++) { if (pExt861->did_type10_data_block[t10db_idx].total_descriptors < NVT_CTA861_DID_TYPE10_DESCRIPTORS_MIN || pExt861->did_type10_data_block[t10db_idx].total_descriptors > NVT_CTA861_DID_TYPE10_DESCRIPTORS_MAX) { - nvt_assert(0 && "payload descriptor invalid. expect minimum 1 descriptor, maximum 4 descriptors"); + nvt_assert(0 && "payload descriptor invalid. expect T10VTDB has minimum 1 descriptor, maximum 4 descriptors"); continue; } NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pExt861->did_type10_data_block[t10db_idx].payload[i*eachOfDescriptorsSize], &newTiming, - pExt861->did_type10_data_block[t10db_idx].version.t10_m)) + pExt861->did_type10_data_block[t10db_idx].version.t10_m, startSeqNum+i)) { p6bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *) &pExt861->did_type10_data_block[t10db_idx].payload[i*eachOfDescriptorsSize]; - if (p6bytesDescriptor->options.ycc420_support) + if (p6bytesDescriptor->options.ycc420_support && newTiming.pclk > NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN) { UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, pInfo->hdmiForumInfo.dc_30bit_420, @@ -3161,9 +3587,9 @@ void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, voi (int)newTiming.etc.rrx1k%1000, (newTiming.interlaced ? "I":"P")); } - newTiming.etc.status = NVT_STATUS_DISPLAYID_10N(i+1); - newTiming.etc.flag |= NVT_FLAG_DISPLAYID_T10_TIMING; + newTiming.etc.status = NVT_STATUS_CTA861_DID_T10N(NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status)); newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + newTiming.etc.rep = 0x1; if (!assignNextAvailableTiming(pInfo, &newTiming)) { @@ -3176,8 +3602,6 @@ void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, voi } } } - - return; } POP_SEGMENTS diff --git a/src/common/modeset/timing/nvt_edidext_displayid.c b/src/common/modeset/timing/nvt_edidext_displayid.c index 7862d848af..2063537958 100644 --- a/src/common/modeset/timing/nvt_edidext_displayid.c +++ b/src/common/modeset/timing/nvt_edidext_displayid.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -1372,9 +1372,9 @@ static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo) // yuv420-only video parse861bShortYuv420Timing(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK); // CEA861-F at 7.5.12 section about VFPDB block. - if (p861info->total_vfpdb != 0) + if (p861info->total_svr != 0) { - parse861bShortPreferredTiming(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK); + parseCta861NativeOrPreferredTiming(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK); } return NVT_STATUS_SUCCESS; diff --git a/src/common/modeset/timing/nvtiming.h b/src/common/modeset/timing/nvtiming.h index f0bc762f7d..dc7d142108 100644 --- a/src/common/modeset/timing/nvtiming.h +++ b/src/common/modeset/timing/nvtiming.h @@ -1,6 +1,6 @@ //**************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -278,17 +278,17 @@ typedef enum NVT_TIMING_TYPE NVT_TYPE_CVT_RB, // CVT timing with reduced blanking NVT_TYPE_CUST, // Customized timing NVT_TYPE_EDID_DTD, // EDID detailed timing - NVT_TYPE_EDID_STD, // EDID standard timing + NVT_TYPE_EDID_STD, // = 10 EDID standard timing NVT_TYPE_EDID_EST, // EDID established timing NVT_TYPE_EDID_CVT, // EDID defined CVT timing (EDID 1.4) - NVT_TYPE_EDID_861ST, // EDID defined CEA/EIA 861 timing (in the EDID 861 extension) + NVT_TYPE_EDID_861ST, // EDID defined CEA/EIA 861 timing (in the CTA861 extension) NVT_TYPE_NV_PREDEFINED, // NV pre-defined timings (PsF timings) NVT_TYPE_DMT_RB, // DMT timing with reduced blanking NVT_TYPE_EDID_EXT_DTD, // EDID detailed timing in the extension NVT_TYPE_SDTV, // SDTV timing (including NTSC, PAL etc) NVT_TYPE_HDTV, // HDTV timing (480p,480i,720p, 1080i etc) NVT_TYPE_SMPTE, // deprecated ? still used by drivers\unix\nvkms\src\nvkms-dpy.c - NVT_TYPE_EDID_VTB_EXT, // EDID defined VTB extension timing + NVT_TYPE_EDID_VTB_EXT, // = 20 EDID defined VTB extension timing NVT_TYPE_EDID_VTB_EXT_STD, // EDID defined VTB extension standard timing NVT_TYPE_EDID_VTB_EXT_DTD, // EDID defined VTB extension detailed timing NVT_TYPE_EDID_VTB_EXT_CVT, // EDID defined VTB extension cvt timing @@ -298,13 +298,16 @@ typedef enum NVT_TIMING_TYPE NVT_TYPE_HDMI_EXT, // EDID defined HDMI extended resolution timing (UHDTV - 4k, 8k etc.) NVT_TYPE_CUST_AUTO, // Customized timing generated automatically by NVCPL NVT_TYPE_CUST_MANUAL, // Customized timing entered manually by user - NVT_TYPE_CVT_RB_2, // CVT timing with reduced blanking V2 + NVT_TYPE_CVT_RB_2, // = 30 CVT timing with reduced blanking V2 NVT_TYPE_DMT_RB_2, // DMT timing with reduced blanking V2 NVT_TYPE_DISPLAYID_7, // DisplayID 2.0 detailed timing - Type VII NVT_TYPE_DISPLAYID_8, // DisplayID 2.0 enumerated timing - Type VIII NVT_TYPE_DISPLAYID_9, // DisplayID 2.0 formula-based timing - Type IX NVT_TYPE_DISPLAYID_10, // DisplayID 2.0 formula-based timing - Type X NVT_TYPE_CVT_RB_3, // CVT timing with reduced blanking V3 + NVT_TYPE_CTA861_DID_T7, // EDID defined CTA861 DisplayID Type VII timing (in the CTA861 extension) + NVT_TYPE_CTA861_DID_T8, // EDID defined CTA861 DisplayID Type VIII timing (in the CTA861 extension) + NVT_TYPE_CTA861_DID_T10 // EDID defined CTA861 DisplayID Type X timing (in the CTA861 extension) }NVT_TIMING_TYPE; // // 5. the timing sequence number like the TV format and EIA861B predefined timing format @@ -424,7 +427,9 @@ typedef enum NVT_TV_FORMAT #define NVT_STATUS_DISPLAYID_9N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_9, n) #define NVT_STATUS_DISPLAYID_10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_10, n) #define NVT_STATUS_HDMI_EXTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_HDMI_EXT, n) - +#define NVT_STATUS_CTA861_DID_T7N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T7, n) +#define NVT_STATUS_CTA861_DID_T8N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T8, n) +#define NVT_STATUS_CTA861_DID_T10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T10, n) //******************************** // CEA/EIA 861 related EDID info @@ -456,7 +461,7 @@ typedef enum NVT_TV_FORMAT #define NVT_CEA861_SHORT_DESCRIPTOR_TAG_MASK 0xE0 #define NVT_CEA861_SHORT_DESCRIPTOR_TAG_SHIFT 5 // -// the descriptor type tags +// the CTA Tag Codes #define NVT_CEA861_TAG_RSVD 0 // reserved block #define NVT_CEA861_TAG_NONE 0 // reserved block #define NVT_CEA861_TAG_AUDIO 1 // Audio Data Block @@ -476,33 +481,34 @@ typedef enum NVT_TV_FORMAT #define NVT_CEA861_EXT_TAG_COLORIMETRY 5 // Colorimetry Data Block #define NVT_CEA861_EXT_TAG_HDR_STATIC_METADATA 6 // HDR Static Metadata Data Block CEA861.3 HDR extension for HDMI 2.0a #define NVT_CTA861_EXT_TAG_HDR_DYNAMIC_METADATA 7 // CTA861-H HDR Dynamic Metadata Data Block -#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MIN 8 // 8...12 : Reserved for video-related blocks +#define NVT_CTA861_EXT_TAG_NATIVE_VIDEO_RESOLUTION 8 // CTA861.6 Native Video Resolution Data Block +#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MIN 9 // 9...12 : Reserved for video-related blocks #define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MAX 12 #define NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE 13 // CEA861F Video Format Preference Data Block #define NVT_CEA861_EXT_TAG_YCBCR420_VIDEO 14 // CEA861F YCBCR 4:2:0 Video Data Block #define NVT_CEA861_EXT_TAG_YCBCR420_CAP 15 // CEA861F YCBCR 4:2:0 Capability Map Data Block #define NVT_CEA861_EXT_TAG_MISC_AUDIO 16 // CEA Miscellaneous Audio Fields #define NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_AUDIO 17 // Vendor-Specific Audio Data Block -#define NVT_CEA861_EXT_TAG_HDMI_AUDIO 18 // Reserved for HDMI Audio Data Block +#define NVT_CTA861_EXT_TAG_HDMI_AUDIO 18 // Reserved for HDMI Audio Data Block #define NVT_CTA861_EXT_TAG_ROOM_CONFIGURATION 19 // CTA861-H Room Configuration Data Block #define NVT_CTA861_EXT_TAG_SPEACKER_LOCATION 20 // CTA861-H Speaker Location Data Block #define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MIN 21 // 21...31 : Reserved for audio-related blocks #define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MAX 31 #define NVT_CEA861_EXT_TAG_INFOFRAME 32 // Infoframe Data Block -#define NVT_CEA861_EXT_TAG_RSVD 33 // Reserved +#define NVT_CTA861_EXT_TAG_RSVD 33 // Reserved #define NVT_CTA861_EXT_TAG_DID_TYPE_VII 34 // DisplayID Type VII Video Timing Data Block #define NVT_CTA861_EXT_TAG_DID_TYPE_VIII 35 // DisplayID Type VIII Video Timing Data Block #define NVT_CTA861_EXT_TAG_RSVD_MIN_1 36 // 36...41 : Reserved for general #define NVT_CTA861_EXT_TAG_RSVD_MAX_1 41 #define NVT_CTA861_EXT_TAG_DID_TYPE_X 42 // DisplayID Type X Video Timing Data Block #define NVT_CTA861_EXT_TAG_RSVD_MIN_2 43 // 43...119 : Reserved for general -#define NVT_CEA861_EXT_TAG_RSVD_MAX_2 119 -#define NVT_CEA861_EXT_TAG_HF_EEODB 120 // HDMI Forum Edid Extension Override Data Block +#define NVT_CTA861_EXT_TAG_RSVD_MAX_2 119 +#define NVT_CTA861_EXT_TAG_HF_EEODB 120 // HDMI Forum Edid Extension Override Data Block #define NVT_CTA861_EXT_TAG_SCDB 121 // 0x79 == Tag for Sink Capability Data Block -#define NVT_CEA861_EXT_TAG_HDMI_RSVD_MIN 122 // 122...127 : Reserved for HDMI -#define NVT_CEA861_EXT_TAG_HDMI_RSVD_MAX 127 -#define NVT_CEA861_EXT_TAG_RSVD_MIN_3 128 // 128...255 : Reserved for general -#define NVT_CEA861_EXT_TAG_RSVD_MAX_3 255 +#define NVT_CTA861_EXT_TAG_HDMI_RSVD_MIN 122 // 122...127 : Reserved for HDMI +#define NVT_CTA861_EXT_TAG_HDMI_RSVD_MAX 127 +#define NVT_CTA861_EXT_TAG_RSVD_MIN_3 128 // 128...255 : Reserved for general +#define NVT_CTA861_EXT_TAG_RSVD_MAX_3 255 // //the extended tag payload size; the size includes the extended tag code #define NVT_CEA861_EXT_VIDEO_CAP_SD_SIZE 2 @@ -1008,8 +1014,10 @@ typedef struct tagNVT_HDR10PLUS_INFO #define NVT_CEA861_COLORIMETRY_BT2020YCC 0x40 // BT2020 Y'CbCr capable #define NVT_CEA861_COLORIMETRY_BT2020RGB 0x80 // BT2020 RGB capable // Colorimetry capabilities - byte 4 -#define NVT_CEA861_COLORIMETRY_DCI_P3 0x80 // DCI-P3 - +#define NVT_CEA861_COLORIMETRY_defaultRGB 0x10 // based on the default chromaticity in Basic Display Parameters and Feature Block +#define NVT_CEA861_COLORIMETRY_sRGB 0x20 // IEC 61966-2-1 +#define NVT_CEA861_COLORIMETRY_ICtCp 0x40 // ITU-R BT.2100 ICtCp +#define NVT_CEA861_COLORIMETRY_ST2113RGB 0x80 // SMPTE ST 2113 R'G'B' // // gamut-related metadata capabilities - byte 4 #define NVT_CEA861_GAMUT_METADATA_MASK 0x8F // the colorimetry or gamut-related metadata block mask @@ -1121,14 +1129,58 @@ typedef struct tagNVT_2BYTES NvU8 byte2; } NVT_2BYTES; +#pragma pack(1) +#define NVT_CTA861_DID_MAX_DATA_BLOCK 4 +//*********************** +// DisplayID VII Video Timing Data Block (T7VDB) +//*********************** +#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_MIN 1 +#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_MAX 1 +#define NVT_CTA861_DID_TYPE7_DESCRIPTORS_LENGTH 20 + +typedef struct tagDID_TYPE7_DATA +{ + struct { + NvU8 revision : 3; + NvU8 dsc_pt : 1; + NvU8 t7_m : 3; + NvU8 F37 : 1; + } version; + + NvU8 total_descriptors; + NvU8 payload[29]; // t7_m=0 so only 20byte used +} DID_TYPE7_DATA; + //*********************** -// DisplayID 10 Timing Data Block +// DisplayID VIII Video Timing Data Block (T8VDB) +//*********************** +#define NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTOR 1 +#define NVT_CTA861_DID_TYPE8_TWO_BYTE_DESCRIPTOR 2 +#define NVT_CTA861_DID_TYPE8_DESCRIPTORS_MIN 1 +#define NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTORS_MAX 28 +#define NVT_CTA861_DID_TYPE8_TWO_BYTE_DESCRIPTORS_MAX 14 + +typedef struct tagDID_TYPE8_DATA +{ + struct { + NvU8 revision : 3; + NvU8 tcs : 1; + NvU8 F34 : 1; + NvU8 t8y420 : 1; + NvU8 code_type : 2; + } version; + + NvU8 total_descriptors; + NvU8 payload[NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTORS_MAX]; // used one_byte descriptor length +} DID_TYPE8_DATA; + +//*********************** +// DisplayID X Video Timing Data Block (T10VDB) //*********************** #define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MIN 1 #define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MAX 4 -#define NVT_CTA861_DID_TYPE10_MAX_DATA_BLOCK 4 -typedef struct DID_TYPE10_DATA +typedef struct tagDID_TYPE10_DATA { struct { NvU8 revision : 3; @@ -1138,11 +1190,34 @@ typedef struct DID_TYPE10_DATA } version; NvU8 total_descriptors; - NvU8 payload[28]; // given the 7bytes * 4 space } DID_TYPE10_DATA; -// See CEA-861E, Table 42, 43 Extended Tags; indicates that the corresponding CEA extended data block value is valid, e.g. if colorimetry is set, then NVT_EDID_CEA861_INFO::colorimetry is valid +//*********************** +// Native Video Resolution Data Block (NVRDB) +//*********************** +typedef struct tagNATIVE_VIDEO_RESOLUTION_DATA +{ + NvU8 native_svr; + + struct { + NvU8 img_size : 1; + NvU8 f41 : 1; + NvU8 f42 : 1; + NvU8 f43 : 1; + NvU8 f44 : 1; + NvU8 f45 : 1; + NvU8 f46 : 1; + NvU8 sz_prec : 1; + } option; + + NvU8 image_size[4]; +} NATIVE_VIDEO_RESOLUTION_DATA; + +#pragma pack() + +// See CEA-861E, Table 42, 43 Extended Tags; indicates that the corresponding CEA extended data block value is valid, +// e.g. if colorimetry is set, then NVT_EDID_CEA861_INFO::colorimetry is valid typedef struct tagNVT_VALID_EXTENDED_BLOCKS { NvU32 VCDB : 1; @@ -1158,6 +1233,7 @@ typedef struct tagNVT_VALID_EXTENDED_BLOCKS NvU32 HF_EEODB : 1; NvU32 nvda_vsdb : 1; NvU32 msft_vsdb : 1; + NvU32 NVRDB : 1; } NVT_VALID_EXTENDED_BLOCKS; //************************* @@ -1223,9 +1299,12 @@ typedef struct tagEDID_CEA861_INFO NVT_5BYTES hdr_static_metadata; // VFPDB extended block. See CEA861-H, Section 7.5.12 Video Format Preference Data Block - NvU8 total_vfpdb; + NvU8 total_svr; NvU8 svr_vfpdb[NVT_CEA861_VFPDB_MAX_DESCRIPTOR]; // svr of preferred video formats + // NVRDB extended block. see CTA861.6, Section 7.5.18 Native Video Resolution Data Block + NATIVE_VIDEO_RESOLUTION_DATA native_video_resolution_db; + // Y420VDB extended block. See CEA861-F, Section 7.5.10 YCBCR 4:2:0 Video Data Block NvU8 total_y420vdb; NvU8 svd_y420vdb[NVT_CEA861_Y420VDB_MAX_DESCRIPTOR]; // svd of video formats that only support YCbCr 4:2:0 @@ -1238,9 +1317,17 @@ typedef struct tagEDID_CEA861_INFO NvU32 hfscdbSize; NvU8 hfscdb[NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH]; - // DID Type X Video extended block, see CTA861-H, section 3.5.17.3 DisplayID Type X Video Timing Data Block - NvU8 total_did_type10db; - DID_TYPE10_DATA did_type10_data_block[NVT_CTA861_DID_TYPE10_MAX_DATA_BLOCK]; + // DID Type VII Video extended block, see 7.5.17.1 in CTA861-H + NvU8 total_did_type7db; + DID_TYPE7_DATA did_type7_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK]; + + // DID Type VIII Video extended block, see 7.5.17.2 in CTA861-H + NvU8 total_did_type8db; + DID_TYPE8_DATA did_type8_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK]; + + // DID Type X Video extended block, see 7.5.17.3 in CTA861-H + NvU8 total_did_type10db; + DID_TYPE10_DATA did_type10_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK]; NvU8 hfeeodb; // HDMI Forum Edid Extension Override Data Block. } NVT_EDID_CEA861_INFO; @@ -2153,12 +2240,14 @@ typedef struct tagNVT_HDMI_FORUM_INFO NvU8 cnmvrr : 1; NvU8 cinemaVrr : 1; NvU8 m_delta : 1; + NvU8 qms : 1; NvU8 fapa_end_extended : 1; - NvU8 rsvd : 1; NvU16 vrr_min : 6; NvU16 vrr_max : 10; + NvU8 qms_tfr_min : 1; + NvU8 qms_tfr_max : 1; NvU16 dsc_MaxSlices : 6; NvU16 dsc_MaxPclkPerSliceMHz : 10; @@ -2804,6 +2893,7 @@ typedef struct tagNVT_VIDEO_INFOFRAME_CTRL NvU16 left_bar; NvU16 right_bar; }NVT_VIDEO_INFOFRAME_CTRL; + // typedef struct tagNVT_AUDIO_INFOFRAME_CTRL { @@ -2818,14 +2908,16 @@ typedef struct tagNVT_AUDIO_INFOFRAME_CTRL typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_CTRL { - NvU32 Enable; - NvU8 HDMIFormat; - NvU8 HDMI_VIC; - NvU8 ThreeDStruc; - NvU8 ThreeDDetail; - NvU8 MetadataPresent; - NvU8 MetadataType; - NvU8 Metadata[8]; // type determines length + NvU32 Enable; + NvU8 HDMIRevision; + NvU8 HDMIFormat; + NvU8 HDMI_VIC; + NvBool ALLMEnable; + NvU8 ThreeDStruc; + NvU8 ThreeDDetail; + NvU8 MetadataPresent; + NvU8 MetadataType; + NvU8 Metadata[8]; // type determines length } NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL; #define NVT_3D_METADTATA_TYPE_PARALAX 0x00 @@ -2841,8 +2933,17 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL NvU32 BaseVFP; NvU32 ReducedBlanking; NvU32 BaseRefreshRate; + NvU32 EnableQMS; } NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL; +typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL +{ + NvU32 minVTotal; + NvU32 targetRefreshRate; + NvBool bFixedVTotal; + NvBool bRefreshRateDivider; +}NVT_ADAPTIVE_SYNC_SDP_CTRL; + //*********************************** // the actual Auido/Video Infoframe //*********************************** @@ -2915,7 +3016,6 @@ typedef struct tagNVT_VIDEO_INFOFRAME NvU8 left_bar_high; NvU8 right_bar_low; NvU8 right_bar_high; - }NVT_VIDEO_INFOFRAME; // #define NVT_VIDEO_INFOFRAME_VERSION_1 1 @@ -2949,8 +3049,9 @@ typedef struct tagNVT_VIDEO_INFOFRAME #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_RGB 0 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr422 1 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr444 2 -#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420 3 -#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE 3 // nvlEscape still uses this lline 4266 +#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420 3 +#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE 3 // nvlEscape still uses this line 4266 +#define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED 7 // CEA-861-F - Unix still used this one #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_MASK 0x60 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_SHIFT 0x5 @@ -3069,14 +3170,17 @@ typedef struct tagNVT_VIDEO_INFOFRAME #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_MASK 0xFF #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_SHIFT 0 // -#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_V4_MASK 0xF0 -#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_V4_SHIFT 4 -#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_0 0 -#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_1 1 -// #define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_MASK 0x0F #define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_SHIFT 0 // +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_MASK 0xF0 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_SHIFT 4 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_P3D65RGB 0 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_P3DCIRGB 1 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_BT2100_ICtCp 2 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_sRGB 3 +#define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_defaultRGB 4 +// #define NVT_VIDEO_INFOFRAME_CONTENT_VIDEO 0 #define NVT_VIDEO_INFOFRAME_CONTENT_GRAPHICS 1 #define NVT_VIDEO_INFOFRAME_CONTENT_PHOTO 2 @@ -3474,6 +3578,33 @@ typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME // #define NVT_HDMI_VS_INFOFRAME_VERSION_1 1 +#define NVT_HDMI_VS_HB0_MASK 0xFF +#define NVT_HDMI_VS_HB0_SHIFT 0x00 +#define NVT_HDMI_VS_HB0_VALUE 0x01 + +#define NVT_HDMI_VS_HB1_MASK 0xFF +#define NVT_HDMI_VS_HB1_SHIFT 0x00 +#define NVT_HDMI_VS_HB1_VALUE 0x01 + +#define NVT_HDMI_VS_HB2_MASK 0xFF +#define NVT_HDMI_VS_HB2_SHIFT 0x00 +#define NVT_HDMI_VS_HB2_VALUE 0x06 + +#define NVT_HDMI_VS_BYTE1_OUI_MASK 0xff +#define NVT_HDMI_VS_BYTE1_OUI_SHIFT 0x00 +#define NVT_HDMI_VS_BYTE1_OUI_VER_1_4 0x03 +#define NVT_HDMI_VS_BYTE1_OUI_VER_2_0 0xD8 + +#define NVT_HDMI_VS_BYTE2_OUI_MASK 0xff +#define NVT_HDMI_VS_BYTE2_OUI_SHIFT 0x00 +#define NVT_HDMI_VS_BYTE2_OUI_VER_1_4 0x0C +#define NVT_HDMI_VS_BYTE2_OUI_VER_2_0 0x5D + +#define NVT_HDMI_VS_BYTE3_OUI_MASK 0xff +#define NVT_HDMI_VS_BYTE3_OUI_SHIFT 0x00 +#define NVT_HDMI_VS_BYTE3_OUI_VER_1_4 0x00 +#define NVT_HDMI_VS_BYTE3_OUI_VER_2_0 0xC4 + // #define NVT_HDMI_VS_BYTE4_RSVD_MASK 0x1f #define NVT_HDMI_VS_BYTE4_RSVD_SHIFT 0x00 @@ -3500,6 +3631,10 @@ typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME #define NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT 0x03 #define NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES 0x00 // HDMI Metadata is not present #define NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES 0x01 // HDMI Metadata is present +#define NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK 0x02 // ALLM is field of length 1 bit at Bit Number 1 +#define NVT_HDMI_VS_BYTE5_ALLM_MODE_DIS 0x00 +#define NVT_HDMI_VS_BYTE5_ALLM_MODE_EN 0x01 +#define NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT 0x01 // ALLM is byte5 bit position 1, so shift 1 bit #define NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK 0xf0 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT 0x04 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_NA 0xfe @@ -3566,83 +3701,184 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME NVT_EXTENDED_METADATA_PACKET_INFOFRAME_PAYLOAD Data; } NVT_EXTENDED_METADATA_PACKET_INFOFRAME; -#define NVT_HDMI_EMP_BYTE1_RSVD_MASK 0x01 -#define NVT_HDMI_EMP_BYTE1_RSVD_SHIFT 0 +#define NVT_HDMI_EMP_BYTE1_RSVD_MASK 0x01 +#define NVT_HDMI_EMP_BYTE1_RSVD_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE1_SYNC_MASK 0x02 +#define NVT_HDMI_EMP_BYTE1_SYNC_SHIFT 1 +#define NVT_HDMI_EMP_BYTE1_SYNC_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_SYNC_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE1_VFR_MASK 0x04 +#define NVT_HDMI_EMP_BYTE1_VFR_SHIFT 2 +#define NVT_HDMI_EMP_BYTE1_VFR_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_VFR_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE1_AFR_MASK 0x08 +#define NVT_HDMI_EMP_BYTE1_AFR_SHIFT 3 +#define NVT_HDMI_EMP_BYTE1_AFR_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_AFR_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_MASK 0x30 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_SHIFT 4 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_PSEUDO_STATIC 0 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_DYNAMIC 1 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_UNIQUE 2 +#define NVT_HDMI_EMP_BYTE1_DS_TYPE_RSVD 3 + +#define NVT_HDMI_EMP_BYTE1_END_MASK 0x40 +#define NVT_HDMI_EMP_BYTE1_END_SHIFT 6 +#define NVT_HDMI_EMP_BYTE1_END_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_END_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE1_NEW_MASK 0x80 +#define NVT_HDMI_EMP_BYTE1_NEW_SHIFT 7 +#define NVT_HDMI_EMP_BYTE1_NEW_DISABLE 0 +#define NVT_HDMI_EMP_BYTE1_NEW_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE2_RSVD_MASK 0xff +#define NVT_HDMI_EMP_BYTE2_RSVD_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_MASK 0xff +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SHIFT 0 +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VENDOR_SPECIFIC 0 +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SPEC_DEFINED 1 +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_CTA_DEFINED 2 +#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VESA_DEFINED 3 + +#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK 0x01 +#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0 +#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0 +#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1 +#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK 0x01 +#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT 1 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK 0x01 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_SHIFT 2 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_DISABLE 0 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_MASK 0xff +#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE8_MD2_RB_MASK 0x04 +#define NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT 2 +#define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0 +#define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1 + +#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03 +#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0 + +#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_MASK 0xff +#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_PACKET_TYPE 0x22 +#define NVT_DP_ADAPTIVE_SYNC_SDP_VERSION 0x2 +#define NVT_DP_ADAPTIVE_SYNC_SDP_LENGTH 0x9 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_MASK 0x3 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_VARIABLE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_FIXED 1 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_NOT_REACHED 2 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_REACHED 3 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_MASK 0x4 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SHIFT 2 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_ENABLED 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_DISABLED 1 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_MASK 0x8 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_SHIFT 3 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_NO_UPDATE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_UPDATE 1 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_RSVD_MASK 0xf0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_RSVD_SHIFT 4 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK 0x01 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_SHIFT 0 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_MASK 0x1c +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_SHIFT 2 + +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_MASK 0x20 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_SHIFT 5 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_DISABLE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_ENABLE 1 -#define NVT_HDMI_EMP_BYTE1_SYNC_MASK 0x02 -#define NVT_HDMI_EMP_BYTE1_SYNC_SHIFT 1 -#define NVT_HDMI_EMP_BYTE1_SYNC_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_SYNC_ENABLE 1 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_MASK 0x40 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_SHIFT 6 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_DISABLE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_ENABLE 1 -#define NVT_HDMI_EMP_BYTE1_VFR_MASK 0x04 -#define NVT_HDMI_EMP_BYTE1_VFR_SHIFT 2 -#define NVT_HDMI_EMP_BYTE1_VFR_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_VFR_ENABLE 1 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_MASK 0x80 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_SHIFT 7 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_DISABLE 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_ENABLE 1 -#define NVT_HDMI_EMP_BYTE1_AFR_MASK 0x08 -#define NVT_HDMI_EMP_BYTE1_AFR_SHIFT 3 -#define NVT_HDMI_EMP_BYTE1_AFR_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_AFR_ENABLE 1 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB5_DURATION_INCREASE_CONSTRAINT_LSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB5_DURATION_INCREASE_CONSTRAINT_LSB_SHIFT 0 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_MASK 0x30 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_SHIFT 4 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_PSEUDO_STATIC 0 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_DYNAMIC 1 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_UNIQUE 2 -#define NVT_HDMI_EMP_BYTE1_DS_TYPE_RSVD 3 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB6_DURATION_INCREASE_CONSTRAINT_MSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB6_DURATION_INCREASE_CONSTRAINT_MSB_SHIFT 0 -#define NVT_HDMI_EMP_BYTE1_END_MASK 0x40 -#define NVT_HDMI_EMP_BYTE1_END_SHIFT 6 -#define NVT_HDMI_EMP_BYTE1_END_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_END_ENABLE 1 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_SHIFT 0 -#define NVT_HDMI_EMP_BYTE1_NEW_MASK 0x80 -#define NVT_HDMI_EMP_BYTE1_NEW_SHIFT 7 -#define NVT_HDMI_EMP_BYTE1_NEW_DISABLE 0 -#define NVT_HDMI_EMP_BYTE1_NEW_ENABLE 1 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_SHIFT 0 -#define NVT_HDMI_EMP_BYTE2_RSVD_MASK 0xff -#define NVT_HDMI_EMP_BYTE2_RSVD_SHIFT 0 +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_BYTE2_MASK 0xff +#define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_BYTE2_SHIFT 0 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_MASK 0xff -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SHIFT 0 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VENDOR_SPECIFIC 0 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SPEC_DEFINED 1 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_CTA_DEFINED 2 -#define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VESA_DEFINED 3 - -#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK 0x01 -#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0 -#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0 -#define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1 - -#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_MASK 0xff -#define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_SHIFT 0 - -#define NVT_HDMI_EMP_BYTE8_MD2_RB_MASK 0x04 -#define NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT 2 -#define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0 -#define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1 - -#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03 -#define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0 +typedef struct tagNVT_ADAPTIVE_SYNC_SDP_HEADER +{ + NvU8 hb0; + NvU8 type; + NvU8 version; + NvU8 length; +}NVT_ADAPTIVE_SYNC_SDP_HEADER; -#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_MASK 0xff -#define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_SHIFT 0 +typedef struct tagNVT_ADAPTIVE_SYNC_SDP_PAYLOAD +{ + NvU8 db0; // operatingMode + NvU8 db1; // minVTotalLSB + NvU8 db2; // minVTotalMSB + NvU8 db3; // targetRefreshRateLSB + NvU8 db4; // targetRefreshRateMSB, rsvd, targetRRDivider, frameInc/Dec Config + NvU8 db5; // frameDurationIncMs + NvU8 db6; // frameDurationDecreaseMs + NvU8 db7; // coastingVTotalPrLSB + NvU8 db8; // coastingVTotalPrMSB + NvU8 rsvd[23]; +}NVT_ADAPTIVE_SYNC_SDP_PAYLOAD; +typedef struct tagADAPTIVE_SYNC_SDP +{ + NVT_ADAPTIVE_SYNC_SDP_HEADER header; + NVT_ADAPTIVE_SYNC_SDP_PAYLOAD payload; +}NVT_ADAPTIVE_SYNC_SDP; // the Vendor-Specific-Data-Block header typedef struct tagNVT_CEA861_VSDB_HEADER @@ -3814,7 +4050,7 @@ typedef struct tagNVT_HDMI_FORUM_VSDB_PAYLOAD NvU8 CNMVRR : 1; NvU8 CinemaVRR : 1; NvU8 M_delta : 1; - NvU8 Rsvd_2 : 1; + NvU8 QMS : 1; NvU8 FAPA_End_Extended : 1; // sixth byte @@ -3827,7 +4063,8 @@ typedef struct tagNVT_HDMI_FORUM_VSDB_PAYLOAD NvU8 DSC_12bpc : 1; NvU8 DSC_16bpc : 1; NvU8 DSC_All_bpp : 1; - NvU8 Rsvd_3 : 2; + NvU8 QMS_TFR_min : 1; + NvU8 QMS_TFR_max : 1; NvU8 DSC_Native_420 : 1; NvU8 DSC_1p2 : 1; // ninth byte @@ -5344,13 +5581,11 @@ typedef enum #define NVT_FLAG_NV_PREFERRED_TIMING 0x00040000 #define NVT_FLAG_DTD1_PREFERRED_TIMING 0x00080000 #define NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING 0x00100000 -#define NVT_FLAG_CEA_PREFERRED_TIMING 0x00200000 +#define NVT_FLAG_CTA_PREFERRED_TIMING 0x00200000 #define NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU 0x00400000 #define NVT_FLAG_DISPLAYID_2_0_TIMING 0x00800000 // this one for the CTA861 embedded in DID20 #define NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated -#define NVT_FLAG_DISPLAYID_T7_TIMING 0x02000000 -#define NVT_FLAG_DISPLAYID_T8_TIMING 0x04000000 -#define NVT_FLAG_DISPLAYID_T10_TIMING 0x08000000 +#define NVT_FLAG_CTA_NATIVE_TIMING 0x02000000 // NVRDB defined #define NVT_FLAG_INTERLACED_MASK (NVT_FLAG_INTERLACED_TIMING | NVT_FLAG_INTERLACED_TIMING2) @@ -5377,8 +5612,10 @@ NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT // DMT timing calculation NVT_STATUS NvTiming_EnumDMT(NvU32 dmtId, NVT_TIMING *pT); +NVT_STATUS NvTiming_EnumStdTwoBytesCode(NvU16 std2ByteCodes, NVT_TIMING *pT); NVT_STATUS NvTiming_CalcDMT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); NVT_STATUS NvTiming_CalcDMT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); +NVT_STATUS NvTiming_CalcDMT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); // CVT timing calculation NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT); @@ -5427,9 +5664,7 @@ NvU32 NvTiming_DisplayID2ValidationMask(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, NVT_STATUS NvTiming_DisplayID2ValidationDataBlocks(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, NvBool bIsStrongValidation); NVT_STATUS NvTiming_Get18ByteLongDescriptorIndex(NVT_EDID_INFO *pEdidInfo, NvU8 tag, NvU32 *dtdIndex); -NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo, - NvU8 *pProductName, - const NvU32 productNameLength); +NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo, NvU8 *pProductName, const NvU32 productNameLength); NvU32 NvTiming_CalculateEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidsize); NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion); NVT_STATUS NvTiming_CalculateEDIDLimits(NVT_EDID_INFO *pEdidInfo, NVT_EDID_RANGE_LIMIT *pLimit); @@ -5442,17 +5677,18 @@ NvU32 a_div_b(NvU32 a, NvU32 b); NvU32 calculateCRC32(NvU8* pBuf, NvU32 bufsize); void patchChecksum(NvU8* pBuf); NvBool isChecksumValid(NvU8* pBuf); - NvU32 RRx1kToPclk (NVT_TIMING *pT); NVT_STATUS NvTiming_ComposeCustTimingString(NVT_TIMING *pT); -// Infoframe composer -NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_VIDEO_INFOFRAME_CTRL *pCtrl); -NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_INFOFRAME_CTRL *pCtrl, NVT_VIDEO_INFOFRAME *pContext, NVT_VIDEO_INFOFRAME *p); -NVT_STATUS NvTiming_ConstructAudioInfoframe(NVT_AUDIO_INFOFRAME_CTRL *pCtrl, NVT_AUDIO_INFOFRAME *pContext, NVT_AUDIO_INFOFRAME *p); -NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL *pCtrl, NVT_VENDOR_SPECIFIC_INFOFRAME *p); -NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL *pCtrl, NVT_EXTENDED_METADATA_PACKET_INFOFRAME *p); +// Infoframe/SDP composer +NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_VIDEO_INFOFRAME_CTRL *pCtrl); +NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_INFOFRAME_CTRL *pCtrl, NVT_VIDEO_INFOFRAME *pContext, NVT_VIDEO_INFOFRAME *p); +NVT_STATUS NvTiming_ConstructAudioInfoframe(NVT_AUDIO_INFOFRAME_CTRL *pCtrl, NVT_AUDIO_INFOFRAME *pContext, NVT_AUDIO_INFOFRAME *p); +NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL *pCtrl, NVT_VENDOR_SPECIFIC_INFOFRAME *p); +NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL *pCtrl, NVT_EXTENDED_METADATA_PACKET_INFOFRAME *p); +void NvTiming_ConstructAdaptiveSyncSDP(const NVT_ADAPTIVE_SYNC_SDP_CTRL *pCtrl, NVT_ADAPTIVE_SYNC_SDP *p); + // Get specific timing from parsed EDID NVT_STATUS NvTiming_GetDTD1Timing (NVT_EDID_INFO * pEdidInfo, NVT_TIMING * pT); @@ -5460,15 +5696,22 @@ NVT_STATUS NvTiming_GetDTD1Timing (NVT_EDID_INFO * pEdidInfo, NVT_TIMING * pT); #define NVT_IS_DTD(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_DTD) #define NVT_IS_EXT_DTD(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_EXT_DTD) #define NVT_IS_CTA861(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_861ST) +#define NVT_IS_CTA861_DID_T7(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T7) +#define NVT_IS_CTA861_DID_T8(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T8) +#define NVT_IS_CTA861_DID_T10(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T10) -#define NVT_IS_DTD1(d) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1)) -#define NVT_IS_DTDn(d, n) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) -#define NVT_IS_EXT_DTDn(d, n) ((NVT_IS_EXT_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_DTD1(d) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1)) +#define NVT_IS_DTDn(d, n) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_EXT_DTDn(d, n) ((NVT_IS_EXT_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_CTA861_DID_T7n(d, n) ((NVT_IS_CTA861_DID_T7((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_CTA861_DID_T8_1(d) ((NVT_IS_CTA861_DID_T8((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1)) +#define NVT_IS_CTA861_DID_T10n(d, n) ((NVT_IS_CTA861_DID_T10((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) #define NVT_DID20_TIMING_IS_CTA861(flag, status) ((NVT_IS_CTA861((status))) && (0 != (NVT_FLAG_DISPLAYID_2_0_TIMING & (flag)))) #define NVT_PREFERRED_TIMING_IS_DTD1(flag, status) ((NVT_IS_DTD1((status))) && (0 != (NVT_FLAG_DTD1_PREFERRED_TIMING & (flag)))) #define NVT_PREFERRED_TIMING_IS_DISPLAYID(flag) (0 != (NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING & flag)) -#define NVT_PREFERRED_TIMING_IS_CEA(flag) (0 != (NVT_FLAG_CEA_PREFERRED_TIMING & flag)) +#define NVT_PREFERRED_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_PREFERRED_TIMING & flag)) +#define NVT_NATIVE_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_NATIVE_TIMING & flag)) #ifdef __cplusplus } diff --git a/src/common/modeset/timing/nvtiming_pvt.h b/src/common/modeset/timing/nvtiming_pvt.h index ef553aa296..37ffa9f084 100644 --- a/src/common/modeset/timing/nvtiming_pvt.h +++ b/src/common/modeset/timing/nvtiming_pvt.h @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -68,7 +68,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *pEdid, NvU32 size, NVT_EDID_CEA861_INF void parse861ExtDetailedTiming(NvU8 *pEdidExt, NvU8 basicCaps, NVT_EDID_INFO *pInfo); void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); -void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861HfScdb(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861HfEeodb(NVT_EDID_CEA861_INFO *pExt861, NvU32 *pTotalEdidExtensions); @@ -81,8 +81,12 @@ void parseEdidNvidiaVSDBBlock(VSDB_DATA *pVsdb, NVDA_VSDB_PARSED_INFO *vsd void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCta861DIDType7VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); +void parseCta861DIDType8VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); NvBool isMatchedCTA861Timing(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); +NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); +NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); NvU32 isHdmi3DStereoType(NvU8 StereoStructureType); NvU32 getCEA861TimingAspectRatio(NvU32 vic); void SetActiveSpaceForHDMI3DStereo(const NVT_TIMING *pTiming, NVT_EXT_TIMING *pExtTiming); @@ -96,7 +100,9 @@ NVT_STATUS getDisplayIdEDIDExtInfo(NvU8* pEdid, NvU32 edidSize, NVT_EDID_INFO* p NVT_STATUS parseDisplayIdBlock(NvU8* pBlock, NvU8 max_length, NvU8* pLength, NVT_EDID_INFO* pEdidInfo); NVT_STATUS getDisplayId20EDIDExtInfo(NvU8* pDisplayid, NvU32 edidSize, NVT_EDID_INFO* pEdidInfo); NVT_STATUS parseDisplayId20EDIDExtDataBlocks(NvU8* pDataBlock, NvU8 remainSectionLength, NvU8* pCurrentDBLength, NVT_EDID_INFO* pEdidInfo); -NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadBytes); +NVT_STATUS parseDisplayId20Timing7Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 count); +NVT_STATUS parseDisplayId20Timing8Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 codeType, NvU8 codeSize, NvU8 index, NvU8 count); +NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadBytes, NvU8 count); void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); void updateColorFormatForDisplayId20ExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); NvBool assignNextAvailableDisplayId20Timing(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming); diff --git a/src/common/nvlink/inband/interface/nvlink_inband_msg.h b/src/common/nvlink/inband/interface/nvlink_inband_msg.h index ab08017fe2..f58c390edb 100644 --- a/src/common/nvlink/inband/interface/nvlink_inband_msg.h +++ b/src/common/nvlink/inband/interface/nvlink_inband_msg.h @@ -76,6 +76,12 @@ typedef struct /* Add more caps as need in the future */ +#define NVLINK_INBAND_BW_MODE_FULL 0 +#define NVLINK_INBAND_BW_MODE_OFF 1 +#define NVLINK_INBAND_BW_MODE_MIN 2 +#define NVLINK_INBAND_BW_MODE_HALF 3 +#define NVLINK_INBAND_BW_MODE_3QUARTER 4 + typedef struct { NvU64 pciInfo; /* Encoded as Domain(63:32):Bus(15:8):Device(0:7). (debug only) */ @@ -85,7 +91,8 @@ typedef struct NvU64 enabledLinkMask; /* GPU's currently enabled NvLink mask info. (debug only) */ NvU32 gpuCapMask; /* GPU capabilities, one of NVLINK_INBAND_GPU_PROBE_CAPS */ - NvU8 reserved[32]; /* For future use. Must be initialized to zero */ + NvU8 bwMode; /* NVLink bandwidth mode, one of NVLINK_INBAND_BW_MODE */ + NvU8 reserved[31]; /* For future use. Must be initialized to zero */ } nvlink_inband_gpu_probe_req_t; typedef struct @@ -96,6 +103,9 @@ typedef struct #define NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1 NVBIT64(0) #define NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1 NVBIT64(1) +#define NVLINK_INBAND_FM_CAPS_BW_MODE_MIN NVBIT64(2) +#define NVLINK_INBAND_FM_CAPS_BW_MODE_HALF NVBIT64(3) +#define NVLINK_INBAND_FM_CAPS_BW_MODE_3QUARTER NVBIT64(4) typedef struct { @@ -108,7 +118,8 @@ typedef struct NvU64 gpaAddressRange; /* GPU GPA address range */ NvU64 flaAddress; /* FLA starting address for the GPU */ NvU64 flaAddressRange; /* GPU FLA address range */ - NvU8 reserved[32]; /* For future use. Must be initialized to zero */ + NvU32 linkMaskToBeReduced; /* bit mask of unused NVLink ports for P2P */ + NvU8 reserved[28]; /* For future use. Must be initialized to zero */ } nvlink_inband_gpu_probe_rsp_t; typedef struct diff --git a/src/common/nvlink/interface/nvlink.h b/src/common/nvlink/interface/nvlink.h index 3415fe0c98..59e76cd2ee 100644 --- a/src/common/nvlink/interface/nvlink.h +++ b/src/common/nvlink/interface/nvlink.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2014-2022 NVidia Corporation + Copyright (c) 2014-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -120,6 +120,12 @@ struct nvlink_device NvU32 numLinksPerIoctrl; NvU32 numActiveLinksPerIoctrl; + // + // boolean indicating if a given device + // is a reduced nvlink config + // + NvBool bReducedNvlinkConfig; + // Client private information void *pDevInfo; }; @@ -397,6 +403,10 @@ NvBool nvlink_lib_is_initialized(void); */ NvBool nvlink_lib_is_device_list_empty(void); +/* + * Get if a device registerd to the nvlink corelib has a reduced nvlink config + */ +NvBool nvlink_lib_is_registerd_device_with_reduced_config(void); /************************************************************************************************/ /************************** NVLink library driver-side interface ********************************/ @@ -456,15 +466,11 @@ NvlStatus nvlink_lib_set_link_master(nvlink_link *link); */ NvlStatus nvlink_lib_get_link_master(nvlink_link *link, nvlink_link **master); -/* - * Set the training state for the given link as non-ALI or ALI - */ -NvlStatus nvlink_lib_is_link_using_ALI(nvlink_link *link, NvBool *usingALI); - /* * Set the training state for the given link as non-ALI or ALI */ NvlStatus nvlink_lib_link_set_training_mode(nvlink_link *link, NvBool enableALI); + /************************************************************************************************/ /*************************** NVLink topology discovery functions ********************************/ /************************************************************************************************/ diff --git a/src/common/nvlink/interface/nvlink_lib_ctrl.h b/src/common/nvlink/interface/nvlink_lib_ctrl.h index 1a481c69dd..22a7061d1d 100644 --- a/src/common/nvlink/interface/nvlink_lib_ctrl.h +++ b/src/common/nvlink/interface/nvlink_lib_ctrl.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVidia Corporation + Copyright (c) 2016-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -154,7 +154,7 @@ typedef enum nvlink_link_mode_enable_pm, nvlink_link_mode_disable_pm, nvlink_link_mode_traffic_setup, - nvlink_link_mode_contain + nvlink_link_mode_contain, } nvlink_link_mode; /* sublink tx modes */ diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c index 611a475ac3..ad5a9cc9fc 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2020 NVidia Corporation + Copyright (c) 2017-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -297,7 +297,6 @@ nvlink_core_get_endpoint_state NvU64 state = NVLINK_LINKSTATE_INVALID; NvU64 dlState = NVLINK_LINKSTATE_INVALID; NvU64 tlState = NVLINK_LINKSTATE_INVALID; - if ((link == NULL) || (linkState == NULL)) { return; @@ -309,7 +308,7 @@ nvlink_core_get_endpoint_state // unless the corresponding HAL/Callbacks are not registered, which can // happen during early development cycle. Adding an assert to catch that // in debug builds. - // + // status = link->link_handlers->get_dl_link_mode(link, &dlState); nvlink_assert(status == NVL_SUCCESS); diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c index 13591e33d8..521cfbb0aa 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2020 NVidia Corporation + Copyright (c) 2017-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -3614,15 +3614,12 @@ nvlink_lib_ctrl_get_device_link_states for (i = 0; i < numLinks; ++i) { - // Check RxDet status of the link and repopulate as necessary - nvlink_core_get_rx_detect(&links[i], 1, 0); - // Get the endpoint states of the link nvlink_core_get_endpoint_state(links[i], &(params->endStates[i])); NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, - "%s: link 0x%x -- rxDet status 0x%x, linkMode 0x%x,\n", - __FUNCTION__, i, links[i]->bRxDetected, params->endStates[i].linkMode)); + "%s: link 0x%x -- linkMode 0x%x,\n", + __FUNCTION__, i, params->endStates[i].linkMode)); } diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c index 261f6399a9..633c0a3123 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c @@ -384,70 +384,3 @@ nvlink_lib_link_set_training_mode return status; } - -/** - * Get whether the link is using ALI for training. - * - * @param[in] link NVLink Link pointer - * @param[out] usingAli Boolean on whether ALI training is being used - * - * return NVL_SUCCESS if getting the variable is successful - */ -NvlStatus -nvlink_lib_is_link_using_ALI -( - nvlink_link *link, - NvBool *usingALI -) -{ - NvlStatus status = NVL_SUCCESS; - usingALI = NV_FALSE; - - if (link == NULL) - { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: Bad link pointer specified.\n", - __FUNCTION__)); - return NVL_ERR_GENERIC; - } - - // Acquire the top-level lock - status = nvlink_lib_top_lock_acquire(); - if (status != NVL_SUCCESS) - { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: Failed to acquire top-level lock\n", - __FUNCTION__)); - - return status; - } - - // Acquire the per-link lock - status = nvlink_lib_link_locks_acquire(&link, 1); - if (status != NVL_SUCCESS) - { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: Failed to acquire per-link locks\n", - __FUNCTION__)); - - // Release the top-level lock - nvlink_lib_top_lock_release(); - - return status; - } - - // - // All the required per-link locks are successfully acquired - // The connection list traversal is also complete now - // Release the top level-lock - // - nvlink_lib_top_lock_release(); - - // TODO: Add Getter for per-link enableALI state variable - - // Release the per-link lock - nvlink_lib_link_locks_release(&link, 1); - - return status; -} - diff --git a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c index d3517f945f..52c50c597e 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation + Copyright (c) 2019-2023 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -127,8 +127,8 @@ nvlink_lib_unload(void) } // Release and free top-level lock - nvlink_lib_top_lock_release(); - nvlink_lib_top_lock_free(); + nvlink_lib_top_lock_release(); + nvlink_lib_top_lock_free(); } return NVL_SUCCESS; @@ -160,3 +160,40 @@ nvlink_lib_is_device_list_empty(void) return isEmpty; } +/* + * Get if a device registerd to the nvlink corelib has a reduced nvlink config + * + * return NV_TRUE if there is a device registered to the core library that is a reduced + * nvlink config device + */ +NvBool +nvlink_lib_is_registerd_device_with_reduced_config(void) +{ + NvlStatus lock_status = NVL_SUCCESS; + nvlink_device *dev = NULL; + + // Acquire top-level lock + lock_status = nvlink_lib_top_lock_acquire(); + if (lock_status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire top-level lock\n", + __FUNCTION__)); + + return NV_FALSE; + } + + FOR_EACH_DEVICE_REGISTERED(dev, nvlinkLibCtx.nv_devicelist_head, node) + { + if (dev->bReducedNvlinkConfig == NV_TRUE) + { + return NV_TRUE; + } + } + + // Release and free top-level lock + nvlink_lib_top_lock_release(); + nvlink_lib_top_lock_free(); + + return NV_FALSE; +} diff --git a/src/common/nvswitch/common/inc/soe/soeifcore.h b/src/common/nvswitch/common/inc/soe/soeifcore.h index 621cb279ea..354b20d829 100644 --- a/src/common/nvswitch/common/inc/soe/soeifcore.h +++ b/src/common/nvswitch/common/inc/soe/soeifcore.h @@ -24,6 +24,8 @@ #ifndef _SOECORE_H_ #define _SOECORE_H_ +#define SOE_CORE_BIOS_SIZE_LS10 0x100000 // 1 MB + /*! * @file soeifutil.h * @brief SOE CORE Command Queue @@ -81,6 +83,21 @@ enum * Init PLM2 protected registers */ RM_SOE_CORE_CMD_INIT_L2_STATE, + + /*! + * Read Power + */ + RM_SOE_CORE_CMD_GET_POWER_VALUES, + + /*! + * Set NPORT interrupts + */ + RM_SOE_CORE_CMD_SET_NPORT_INTRS, + + /*! + * Disable NPORT fatal interrupt + */ + RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR, }; // Timeout for SOE reset callback function @@ -152,6 +169,41 @@ typedef struct NvU8 cmdType; } RM_SOE_CORE_CMD_L2_STATE; +typedef struct +{ + NvU8 cmdType; +} RM_SOE_CORE_CMD_GET_POWER; + +typedef struct +{ + NvU8 cmdType; + NvU32 nport; + NvBool bEnable; +} RM_SOE_CORE_CMD_NPORT_INTRS; + +typedef struct +{ + NvU8 cmdType; + NvU32 nport; + NvU32 nportIntrEnable; + NvU8 nportIntrType; +} RM_SOE_CORE_CMD_NPORT_FATAL_INTR; + +/*! + * NPORT Interrupt Types + */ +enum +{ + RM_SOE_CORE_NPORT_ROUTE_INTERRUPT, + RM_SOE_CORE_NPORT_INGRESS_INTERRUPT, + RM_SOE_CORE_NPORT_EGRESS_0_INTERRUPT, + RM_SOE_CORE_NPORT_EGRESS_1_INTERRUPT, + RM_SOE_CORE_NPORT_TSTATE_INTERRUPT, + RM_SOE_CORE_NPORT_SOURCETRACK_INTERRUPT, + RM_SOE_CORE_NPORT_MULTICAST_INTERRUPT, + RM_SOE_CORE_NPORT_REDUCTION_INTERRUPT +}; + typedef union { NvU8 cmdType; @@ -163,9 +215,11 @@ typedef union RM_SOE_CORE_CMD_NPORT_TPROD_STATE nportTprodState; RM_SOE_CORE_CMD_GET_VOLTAGE getVoltage; RM_SOE_CORE_CMD_L2_STATE l2State; + RM_SOE_CORE_CMD_GET_POWER getPower; + RM_SOE_CORE_CMD_NPORT_INTRS nportIntrs; + RM_SOE_CORE_CMD_NPORT_FATAL_INTR nportDisableIntr; } RM_SOE_CORE_CMD; - typedef struct { NvU8 msgType; @@ -175,9 +229,19 @@ typedef struct NvU32 hvdd_mv; } RM_SOE_CORE_MSG_GET_VOLTAGE; +typedef struct +{ + NvU8 msgType; + NvU8 flcnStatus; + NvU32 vdd_w; + NvU32 dvdd_w; + NvU32 hvdd_w; +} RM_SOE_CORE_MSG_GET_POWER; + typedef union { NvU8 msgType; RM_SOE_CORE_MSG_GET_VOLTAGE getVoltage; + RM_SOE_CORE_MSG_GET_POWER getPower; } RM_SOE_CORE_MSG; #endif // _SOECORE_H_ diff --git a/src/common/nvswitch/common/inc/soe/soeiftherm.h b/src/common/nvswitch/common/inc/soe/soeiftherm.h index 58dea84529..1478ed4ee1 100644 --- a/src/common/nvswitch/common/inc/soe/soeiftherm.h +++ b/src/common/nvswitch/common/inc/soe/soeiftherm.h @@ -75,6 +75,7 @@ enum { RM_SOE_THERM_MSG_ID_SLOWDOWN_STATUS, RM_SOE_THERM_MSG_ID_SHUTDOWN_STATUS, + RM_SOE_THERM_MSG_ID_ACK_FORCE_SLOWDOWN, }; /*! @@ -102,6 +103,7 @@ typedef struct NvBool bSlowdown; NvTemp maxTemperature; NvTemp warnThreshold; + NvBool bLinksL1Status; struct { diff --git a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h index 5b54d67c15..7234bb3114 100644 --- a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h +++ b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h @@ -751,6 +751,19 @@ typedef struct NvU32 hvdd_mv; } NVSWITCH_CTRL_GET_VOLTAGE_PARAMS; +/* + * CTRL_NVSWITCH_GET_POWER + * + * Zero(0) indicates that a measurement is not available + * on the current platform. + */ +typedef struct +{ + NvU32 vdd_w; + NvU32 dvdd_w; + NvU32 hvdd_w; +} NVSWITCH_GET_POWER_PARAMS; + /* * CTRL_NVSWITCH_GET_ERRORS * @@ -1283,6 +1296,9 @@ typedef enum nvswitch_pri_error_instance NVSWITCH_PPRIV_WRITE_PRT } NVSWITCH_PRI_ERROR_INSTANCE; +#define NVSWITCH_ERROR_MAX_DESCRPTION_LEN 70 +#define NVSWITCH_RAW_ERROR_DATA_SIZE 16 + typedef struct nvswitch_error { NvU32 error_value; /* NVSWITCH_ERR_* */ @@ -1291,6 +1307,9 @@ typedef struct nvswitch_error NvU32 subinstance; /* Used for lane# or similar */ NV_DECLARE_ALIGNED(NvU64 time, 8); /* Platform time (nsec) */ NvBool error_resolved; /* If an error is correctable, set to true. */ + NvU32 error_data[NVSWITCH_RAW_ERROR_DATA_SIZE]; /* Data from NVSWITCH_REPORT_DATA */ + NvU32 error_data_size; /* Size of error_data */ + NvU8 error_description[NVSWITCH_ERROR_MAX_DESCRPTION_LEN]; /* Short description of error */ } NVSWITCH_ERROR; #define NVSWITCH_ERROR_COUNT_SIZE 64 @@ -3534,6 +3553,15 @@ typedef struct #define NVSWITCH_CTRL_I2C_MESSAGE_LENGTH_MAX 256 +typedef enum +{ + NVSWITCH_I2C_ACQUIRER_NONE = 0, + NVSWITCH_I2C_ACQUIRER_UNKNOWN, + NVSWITCH_I2C_ACQUIRER_IOCTL, // e.g. MODS + NVSWITCH_I2C_ACQUIRER_EXTERNAL, // e.g. Linux Direct + +} NVSWITCH_I2C_ACQUIRER; + /* * CTRL_NVSWITCH_I2C_INDEXED * @@ -3817,7 +3845,9 @@ typedef struct #define CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 0x52 #define CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 0x53 #define CTRL_NVSWITCH_GET_VOLTAGE 0x54 -#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x55 +#define CTRL_NVSWITCH_RESERVED_11 0x55 +#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x56 +#define CTRL_NVSWITCH_GET_POWER 0x57 #ifdef __cplusplus } diff --git a/src/common/nvswitch/kernel/bios_nvswitch.c b/src/common/nvswitch/kernel/bios_nvswitch.c index de238e0884..cecc5624c1 100644 --- a/src/common/nvswitch/kernel/bios_nvswitch.c +++ b/src/common/nvswitch/kernel/bios_nvswitch.c @@ -29,6 +29,7 @@ #include "flcn/flcn_nvswitch.h" #include "rmflcncmdif_nvswitch.h" +#include "haldef_nvswitch.h" static NvlStatus _nvswitch_core_bios_read @@ -48,7 +49,6 @@ _nvswitch_core_bios_read RM_SOE_CORE_CMD_BIOS *pParams = &cmd.cmd.core.bios; NvU64 dmaHandle = 0; NvU8 *pReadBuffer = NULL; - NvU32 spiReadCnt = 0; NvU32 offset = 0; NvU32 bufferSize = (reqSize < SOE_DMA_MAX_SIZE) ? SOE_DMA_MAX_SIZE : MAX_READ_SIZE; @@ -134,7 +134,6 @@ _nvswitch_core_bios_read } offset += pParams->sizeInBytes; - spiReadCnt++; } nvswitch_os_unmap_dma_region(device->os_handle, pReadBuffer, dmaHandle, @@ -203,7 +202,7 @@ nvswitch_bios_get_image return NVL_SUCCESS; } - status = nvswitch_bios_read_size(device, &biosSize); + status = device->hal.nvswitch_get_bios_size(device, &biosSize); if (status != NVL_SUCCESS || biosSize == 0) { NVSWITCH_PRINT(device, ERROR, diff --git a/src/common/nvswitch/kernel/error_nvswitch.c b/src/common/nvswitch/kernel/error_nvswitch.c index e1c6aba915..2b97a56a9e 100644 --- a/src/common/nvswitch/kernel/error_nvswitch.c +++ b/src/common/nvswitch/kernel/error_nvswitch.c @@ -153,14 +153,21 @@ nvswitch_record_error NvBool error_resolved, void *data, NvU32 data_size, - NvU32 line + NvU32 line, + const char *description ) { NvU32 idx_error; + NvU32 description_len = (NvU32)nvswitch_os_strlen(description) - 2; //take out leading and trailing quotation NVSWITCH_ASSERT(errors != NULL); NVSWITCH_ASSERT(data_size <= sizeof(errors->error_log[idx_error].data)); + if (description_len > NVSWITCH_ERROR_MAX_DESCRPTION_LEN) + { + description_len = NVSWITCH_ERROR_MAX_DESCRPTION_LEN; + } + // If no error log has been created, don't log it. if ((errors->error_log_size != 0) && (errors->error_log != NULL)) { @@ -192,6 +199,8 @@ nvswitch_record_error errors->error_log[idx_error].severity = severity; errors->error_log[idx_error].error_resolved = error_resolved; errors->error_log[idx_error].line = line; + errors->error_log[idx_error].data_size = data_size; + nvswitch_os_memcpy(&errors->error_log[idx_error].description, description + 1, description_len); // Log tracking info errors->error_log[idx_error].timer_count = nvswitch_hw_counter_read_counter(device); @@ -265,6 +274,7 @@ nvswitch_get_error error_entry->timer_count = ((device == NULL) ? 0 : nvswitch_hw_counter_read_counter(device)); error_entry->time = nvswitch_os_get_platform_time(); + error_entry->data_size = 0; } else { @@ -545,6 +555,13 @@ nvswitch_ctrl_get_errors p->error[p->errorCount].subinstance = error.subinstance; p->error[p->errorCount].time = error.time; p->error[p->errorCount].error_resolved = error.error_resolved; + p->error[p->errorCount].error_data_size = error.data_size; + if (error.data_size > 0) + { + nvswitch_os_memcpy(p->error[p->errorCount].error_data, error.data.raw.data, error.data_size); + } + nvswitch_os_memcpy(p->error[p->errorCount].error_description, error.description, sizeof(error.description)); + p->errorCount++; index++; } diff --git a/src/common/nvswitch/kernel/inc/common_nvswitch.h b/src/common/nvswitch/kernel/inc/common_nvswitch.h index f7f66f698f..370dc28748 100644 --- a/src/common/nvswitch/kernel/inc/common_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/common_nvswitch.h @@ -132,13 +132,13 @@ void nvswitch_assert_log NvU32 line ); -#define NVSWITCH_ASSERT(_cond) \ +#define NVSWITCH_ASSERT(_cond) \ ((void)((!(_cond)) ? nvswitch_assert_log(__FUNCTION__, __FILE__, __LINE__) : 0)) #else void nvswitch_assert_log(void); -#define NVSWITCH_ASSERT(_cond) \ +#define NVSWITCH_ASSERT(_cond) \ ((void)((!(_cond)) ? nvswitch_assert_log() : 0)) #endif @@ -469,7 +469,8 @@ nvswitch_record_error NvBool error_resolved, void *data, NvU32 data_size, - NvU32 line + NvU32 line, + const char *description ); void @@ -579,5 +580,6 @@ NvlStatus nvswitch_set_training_mode(nvswitch_device *device); NvBool nvswitch_is_link_in_reset(nvswitch_device *device, nvlink_link *link); void nvswitch_apply_recal_settings(nvswitch_device *device, nvlink_link *link); void nvswitch_init_buffer_ready(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); - +NvBool nvswitch_does_link_need_termination_enabled(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_link_termination_setup(nvswitch_device *device, nvlink_link* link); #endif //_COMMON_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/error_nvswitch.h b/src/common/nvswitch/kernel/inc/error_nvswitch.h index 1cefd94e98..3c57133004 100644 --- a/src/common/nvswitch/kernel/inc/error_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/error_nvswitch.h @@ -99,6 +99,8 @@ typedef struct NvU64 timer_count; // NvSwitch timer count NvU64 time; // Platform time, in ns NvU32 line; + NvU32 data_size; // Size of data + NvU8 description[NVSWITCH_ERROR_MAX_DESCRPTION_LEN]; // Short description of error type union { @@ -135,9 +137,9 @@ typedef struct NVSWITCH_ERROR_SEVERITY_FATAL, \ _errresolved, \ NULL, 0, \ - __LINE__) + __LINE__, NULL) -#define NVSWITCH_LOG_FATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata) \ +#define NVSWITCH_LOG_FATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata, ...) \ nvswitch_record_error( \ _device, \ &(_device->log_FATAL_ERRORS), \ @@ -147,8 +149,7 @@ typedef struct NVSWITCH_ERROR_SEVERITY_FATAL, \ _errresolved, \ _errdata, sizeof(*_errdata), \ - __LINE__) - + __LINE__, #__VA_ARGS__) #define NVSWITCH_LOG_NONFATAL(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved) \ nvswitch_record_error( \ @@ -160,9 +161,9 @@ typedef struct NVSWITCH_ERROR_SEVERITY_NONFATAL, \ _errresolved, \ NULL, 0, \ - __LINE__) + __LINE__, NULL) -#define NVSWITCH_LOG_NONFATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata) \ +#define NVSWITCH_LOG_NONFATAL_DATA(_device, _errsrc, _errtype, _instance, _subinstance, _errresolved, _errdata, ...) \ nvswitch_record_error( \ _device, \ &(_device->log_NONFATAL_ERRORS), \ @@ -172,7 +173,7 @@ typedef struct NVSWITCH_ERROR_SEVERITY_NONFATAL, \ _errresolved, \ _errdata, sizeof(*_errdata), \ - __LINE__) + __LINE__, #__VA_ARGS__) #define NVSWITCH_NVLINK_ARCH_ERROR_NONE 0 #define NVSWITCH_NVLINK_ARCH_ERROR_GENERIC 1 diff --git a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h index 1fce5962bd..d1294124c3 100644 --- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h @@ -122,6 +122,8 @@ _op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_inforom_supported, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_spi_supported, (nvswitch_device *device), _arch) \ + _op(NvBool, nvswitch_is_bios_supported, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_get_bios_size, (nvswitch_device *device, NvU32 *pSize), _arch) \ _op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_post_init_device_setup, (nvswitch_device *device), _arch) \ _op(void, nvswitch_post_init_blacklist_device_setup, (nvswitch_device *device), _arch) \ @@ -229,6 +231,9 @@ _op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_therm_read_voltage, (nvswitch_device *device, NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info), _arch) \ _op(void, nvswitch_soe_init_l2_state, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_ctrl_therm_read_power, (nvswitch_device *device, NVSWITCH_GET_POWER_PARAMS *info), _arch) \ + _op(NvBool, nvswitch_does_link_need_termination_enabled, (nvswitch_device *device, nvlink_link *link), _arch) \ + _op(NvlStatus, nvswitch_link_termination_setup, (nvswitch_device *device, nvlink_link *link), _arch) \ #define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \ _op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \ diff --git a/src/common/nvswitch/kernel/inc/intr_nvswitch.h b/src/common/nvswitch/kernel/inc/intr_nvswitch.h index c6331735ad..5b4a5e52d2 100644 --- a/src/common/nvswitch/kernel/inc/intr_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/intr_nvswitch.h @@ -90,7 +90,7 @@ NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR ## _logenum, \ "Non-fatal, Link %02d %s%s\n", link, _str, NVSWITCH_FIRST()); \ NVSWITCH_LOG_NONFATAL_DATA(device, _HW, _logenum, \ - link, 0, NV_FALSE, &report); \ + link, 0, NV_FALSE, &report, _str); \ if (nvswitch_lib_notify_client_events(device, \ NVSWITCH_DEVICE_EVENT_NONFATAL) != NVL_SUCCESS) \ { \ @@ -106,7 +106,7 @@ NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR ## _logenum, \ "Fatal, Link %02d %s%s\n", link, _str, NVSWITCH_FIRST()); \ NVSWITCH_LOG_FATAL_DATA(device, _HW, _logenum, \ - link, 0, NV_FALSE, &report); \ + link, 0, NV_FALSE, &report, _str); \ nvswitch_set_fatal_error(device, device_fatal, link); \ if (nvswitch_lib_notify_client_events(device, \ NVSWITCH_DEVICE_EVENT_FATAL) != NVL_SUCCESS) \ @@ -122,7 +122,7 @@ NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR ## _logenum, \ "Non-fatal, %s, instance=%d, chiplet=%d\n", _str, instance, chiplet); \ NVSWITCH_LOG_NONFATAL_DATA(device, _HW, _logenum, \ - instance, chiplet, NV_FALSE, &err_data); \ + instance, chiplet, NV_FALSE, &err_data, _str); \ if (nvswitch_lib_notify_client_events(device, \ NVSWITCH_DEVICE_EVENT_NONFATAL) != NVL_SUCCESS) \ { \ @@ -137,7 +137,7 @@ NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR ## _logenum, \ "Fatal, %s, instance=%d, chiplet=%d\n", _str, instance, chiplet); \ NVSWITCH_LOG_FATAL_DATA(device, _HW, _logenum, \ - instance, chiplet, NV_FALSE, &err_data); \ + instance, chiplet, NV_FALSE, &err_data, _str); \ nvswitch_set_fatal_error(device, device_fatal, 0); \ if (nvswitch_lib_notify_client_events(device, \ NVSWITCH_DEVICE_EVENT_FATAL) != NVL_SUCCESS) \ diff --git a/src/common/nvswitch/kernel/inc/lr10/lr10.h b/src/common/nvswitch/kernel/inc/lr10/lr10.h index b156426dbc..f958122848 100644 --- a/src/common/nvswitch/kernel/inc/lr10/lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/lr10.h @@ -569,8 +569,25 @@ typedef struct // Ganged Link table NvU64 *ganged_link_table; + + // + // Mask of links on the LR10 device connected to a disabled + // remote link + // + NvU64 disabledRemoteEndLinkMask; + + // + // Bool indicating if disabledRemoteEndLinkMask + // has been cached previously + // + NvBool bDisabledRemoteEndLinkMaskCached; } lr10_device; +typedef struct { + NvU32 switchPhysicalId; + NvU64 linkMask; +} lr10_links_connected_to_disabled_remote_end; + #define NVSWITCH_GET_CHIP_DEVICE_LR10(_device) \ ( \ ((_device)->chip_id == NV_PSMC_BOOT_42_CHIP_ID_LR10) ? \ @@ -643,8 +660,8 @@ NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_lr10(nvswitch_device *device, NVS NvlStatus nvswitch_service_nvldl_fatal_link_lr10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link); NvlStatus nvswitch_ctrl_inband_send_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p); NvlStatus nvswitch_ctrl_inband_read_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p); -void nvswitch_send_inband_nack_lr10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); -NvU32 nvswitch_get_max_persistent_message_count_lr10(nvswitch_device *device); +void nvswitch_send_inband_nack_lr10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); +NvU32 nvswitch_get_max_persistent_message_count_lr10(nvswitch_device *device); NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link, NvBool bSync); NvlStatus nvswitch_service_minion_link_lr10(nvswitch_device *device, NvU32 nvliptInstance); void nvswitch_apply_recal_settings_lr10(nvswitch_device *device, nvlink_link *link); @@ -660,5 +677,7 @@ NvlStatus nvswitch_launch_ALI_lr10(nvswitch_device *device); NvlStatus nvswitch_reset_and_train_link_lr10(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_ctrl_get_bios_info_lr10(nvswitch_device *device, NVSWITCH_GET_BIOS_INFO_PARAMS *p); +NvBool nvswitch_does_link_need_termination_enabled_lr10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_link_termination_setup_lr10(nvswitch_device *device, nvlink_link* link); #endif //_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/lr10/minion_production_ucode_lr10_dbg.h b/src/common/nvswitch/kernel/inc/lr10/minion_production_ucode_lr10_dbg.h index 505838c172..412eabbd9c 100644 --- a/src/common/nvswitch/kernel/inc/lr10/minion_production_ucode_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/lr10/minion_production_ucode_lr10_dbg.h @@ -33,7 +33,7 @@ #define _MINION_UCODE_LR10_DBG_H_ const NvU32 minion_ucode_data_lr10_dbg[] = { - 0x004000d0, 0x0004fe00, 0xc47ea4bd, 0x02f8006b, 0x4908a4b6, 0x9afa0830, 0x00b6b000, 0x090bfcf0, + 0x004000d0, 0x0004fe00, 0xa47ea4bd, 0x02f8006b, 0x4908a4b6, 0x9afa0830, 0x00b6b000, 0x090bfcf0, 0x029fbb02, 0xfa08104f, 0xb4b300f9, 0x02f80600, 0x010a00f8, 0x107eb4bd, 0x00f80000, 0xb4bd020a, 0x0000107e, 0x060a00f8, 0x107eb4bd, 0x00f80000, 0x000000df, 0x08bc4940, 0x89009ffa, 0xb6010060, 0xa9bc0fa4, 0x0000d9a0, 0xa9fd0080, 0x0000d905, 0xa9fa4000, 0x40004f01, 0xfa08bc49, 0x00f8009f, @@ -108,15 +108,15 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0x989a3c00, 0x56009433, 0x0101a08f, 0xbc0fa994, 0x00df909f, 0xfd008000, 0x99ce059f, 0x02448f00, 0xe8fabc00, 0xbce899c7, 0x9ebba9f9, 0x6199e702, 0x0796b003, 0x09050df4, 0x01c48e07, 0x03af9400, 0xbcf0f9bc, 0x999098ef, 0xf9e9bc01, 0x00ff9eb3, 0x89010f0e, 0x3c000254, 0x00f8a99f, 0x00026c89, - 0xb3989abc, 0xbd080290, 0x7e00f8a4, 0xec001acb, 0xf803e8aa, 0xb202f900, 0x1acb7ea0, 0x03e84c00, - 0xd4bdabb2, 0xe712a4b6, 0x7e01eebb, 0x89007272, 0xbc000500, 0x94b39890, 0xa0890c01, 0xc53e0000, + 0xb3989abc, 0xbd080290, 0x7e00f8a4, 0xec001aad, 0xf803e8aa, 0xb202f900, 0x1aad7ea0, 0x03e84c00, + 0xd4bdabb2, 0xe712a4b6, 0x7e01eebb, 0x8900725e, 0xbc000500, 0x94b39890, 0xa0890c01, 0xc53e0000, 0x10890009, 0x90bc0005, 0x0294b398, 0x0090890c, 0x09c53e00, 0x0190b300, 0xb2bfb20c, 0x09da3eae, - 0x00988900, 0x989cbf00, 0x677e019d, 0xb9940071, 0x10a5b610, 0xff10bf95, 0xa889a59a, 0x9cbf0000, - 0xb2019998, 0x10c5b6fb, 0xb6109d95, 0x9cff1094, 0x71677ec5, 0x10a99500, 0xfd10ba94, 0x01fb05a9, + 0x00988900, 0x989cbf00, 0x537e019d, 0xb9940071, 0x10a5b610, 0xff10bf95, 0xa889a59a, 0x9cbf0000, + 0xb2019998, 0x10c5b6fb, 0xb6109d95, 0x9cff1094, 0x71537ec5, 0x10a99500, 0xfd10ba94, 0x01fb05a9, 0x0002dc89, 0xf9989abc, 0xb3a0b202, 0x7e380194, 0x330006a9, 0xb23000a0, 0x04287e0a, 0x00a43300, 0x7e0ab226, 0x33000434, 0xb21c00a4, 0x09757e0a, 0x027c8900, 0x9890bc00, 0x0d0294b3, 0x3e02a5b6, 0xbd000a45, 0x8901fba4, 0xf9002784, 0xf89a3c22, 0x0002dc89, 0xb2989abc, 0x01f630a0, 0xb00b1cf0, - 0x2cf00196, 0x17537e0b, 0x025c8900, 0xc890bc00, 0x0003c489, 0x89f890bc, 0xbc000a34, 0x2489e890, + 0x2cf00196, 0x17397e0b, 0x025c8900, 0xc890bc00, 0x0003c489, 0x89f890bc, 0xbc000a34, 0x2489e890, 0x90bc000a, 0x0a1489d8, 0x9890bc00, 0xb61e14b6, 0xa4b61d24, 0xffc4f11f, 0x0ff4f0ff, 0xf005acfd, 0xf4b601e4, 0x13e4b614, 0xf005affd, 0xaefd01d4, 0x0194f005, 0xb612d4b6, 0xadfd1094, 0x05a9fd05, 0xfd05a1fd, 0x21fb05a2, 0x0002dc89, 0xf9989abc, 0xb2cfb252, 0x0190b3a4, 0x3e94bd0a, 0x89000af2, @@ -161,8 +161,8 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0x000e6480, 0xeb019d33, 0x207c8902, 0x0f4b9401, 0xd9b0b9bc, 0x00800000, 0xce05b9fd, 0x04bc00bb, 0xffffdca8, 0xbcfd7fff, 0x0d4f3e04, 0x0ec48f00, 0x0e948000, 0x0ea48200, 0x0eb48500, 0x01943300, 0x0f41946a, 0x01328c8e, 0x800000d9, 0x101ebc00, 0xce0519fd, 0xf4bc0011, 0xff1bc4a8, 0x7e00ff4c, - 0xc4005fd5, 0x04bcffa3, 0xe81bc7a8, 0x7e00ff4c, 0xb2005fd5, 0xa824bca0, 0x4cf01bc7, 0x04b600ff, - 0x5fd57e08, 0xbca2b200, 0x1b95a854, 0x00ff4c18, 0x7e0503fd, 0xb6005fd5, 0xa4b61024, 0x0502fd18, + 0xc4005fb5, 0x04bcffa3, 0xe81bc7a8, 0x7e00ff4c, 0xb2005fb5, 0xa824bca0, 0x4cf01bc7, 0x04b600ff, + 0x5fb57e08, 0xbca2b200, 0x1b95a854, 0x00ff4c18, 0x7e0503fd, 0xb6005fb5, 0xa4b61024, 0x0502fd18, 0x3ea50aff, 0xbc0012f7, 0x04bc98f4, 0xf854bcd8, 0xf0e824bc, 0xd4b6ff94, 0x18f4b608, 0xfdffe4f0, 0xd4f1059f, 0xe4b6ffff, 0x059efd10, 0x3ea59dff, 0x800012f7, 0x33001014, 0x0218019d, 0x8f0f4994, 0xbc012028, 0x9d3e909f, 0x24800010, 0x9d330010, 0x94020101, 0x288e0f49, 0x9ebc0130, 0x0000df90, @@ -194,261 +194,260 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0x03c9c404, 0xfd0394b6, 0xaffa05f9, 0x01b43301, 0x01944f1d, 0xc700a9ce, 0x9ca63399, 0x920e0bf4, 0xf4b301ff, 0x180af200, 0xa4bd00f8, 0x908900f8, 0xa4b60170, 0xa0a9bc0f, 0x800000d9, 0x05a9fd00, 0xdf00a9ce, 0x80000000, 0xfa059ffd, 0xfc0f01a9, 0xc4049ffd, 0x9ffd03cf, 0x01a9fa05, 0x1d01b433, - 0xce01944f, 0x99c700a9, 0xf49ca630, 0xff920e0b, 0x00f4b301, 0xf8190af2, 0xf8a4bd00, 0x70908900, - 0x0fa4b601, 0xd9a0a9bc, 0x00800000, 0xce05a9fd, 0xffdf00a9, 0xfd7fffff, 0xa9fa049f, 0x8f00f801, - 0xf9017090, 0x0fa99412, 0x9fbca1b2, 0x0000df90, 0x9ffd0080, 0x0099ce05, 0x000000df, 0xfd1a0002, - 0x0bf4049f, 0xbd010b20, 0x13a77ec4, 0xb3a0b200, 0xb21300a4, 0x143d7e1a, 0x89020f00, 0xbc00026c, - 0x0ab2199f, 0x02f911fb, 0x020c010b, 0xee7ea0b2, 0x0ab20013, 0x010c010b, 0x0013a77e, 0x0d00a4b3, - 0x6c89010f, 0x9fbc0002, 0x8f01fb09, 0x94017090, 0x9fbc0fa9, 0x0000df90, 0x9fff0080, 0x00d9ced5, - 0xffffffdf, 0x049ffdfe, 0x8e01d9fa, 0xbf00030c, 0xbb010fe9, 0xf9fd04fa, 0x08844905, 0x99cfefa0, - 0xff94f100, 0x0099b9ff, 0x0f059ffd, 0xf49fa6ff, 0x248f221b, 0xd9ce00f4, 0x1999c700, 0xb301ff92, - 0xb30c00f0, 0x3ef30190, 0x0a001531, 0x0190b317, 0xf8a4bd06, 0x030c8900, 0x099fbf00, 0xe49abc01, - 0xf494efff, 0xfefd060b, 0x030c8906, 0xf89fa000, 0x030c8e00, 0x09efbf00, 0x049abb01, 0xa0059ffd, - 0xf900f8e9, 0x03b4f012, 0x940fa4b6, 0x44890cbd, 0xb4b60128, 0xa0a9bc04, 0x00d1e4bd, 0x00008000, - 0xcfff4ccf, 0xcef5a1ff, 0x90fd00f9, 0x059bfd04, 0xfd049cfd, 0xf9fa059d, 0x01ee9001, 0xb340aa90, - 0xfbe504e4, 0x8912f911, 0x3c000c0c, 0xa0b2989a, 0x9933380a, 0x8900cc01, 0x3c0002fc, 0x9c89f890, - 0x90bc0002, 0x300e0ae8, 0x9cf001f6, 0x02e6b00b, 0xf00bfcf0, 0x9ffd01f6, 0xa51bf504, 0x03288900, - 0x98903c00, 0x9933120a, 0x94009801, 0x1c890f0d, 0x00dc0100, 0xbc008000, 0xdcffd0d9, 0x00cecec5, - 0x0002cc89, 0xdf9890bc, 0x8fffffff, 0xf004effd, 0x94b60794, 0x05e9fd1c, 0xdf01cefa, 0x00800000, - 0x2804ddb8, 0xf5dfff00, 0xf100f9ce, 0xfa081895, 0x00d901f9, 0x90008000, 0x894e18dd, 0x05d9fd00, - 0x9200dfce, 0xf9c701ee, 0x0194b303, 0x04f9c712, 0x0b0194b3, 0xb307f1c7, 0xb30c0110, 0x3e2100e0, - 0xb3001640, 0xb21900e0, 0x7e020b0a, 0x89001563, 0xbd0002dc, 0x0991bca4, 0x00167e3e, 0x11fb200a, - 0x01004489, 0xbc0fa4b6, 0x00d9a0a9, 0xb6008f00, 0xc4b60cb4, 0xffb4f104, 0xffc4f0ff, 0xf005b9fd, - 0xbcfd03d4, 0x02d4b605, 0x800000d9, 0x05bdfd00, 0xfa05a9fd, 0xa9ce01ab, 0x01ee9200, 0x0800e4b3, - 0x00f8040a, 0xb30394f0, 0x0aef0190, 0x0094b305, 0xf8a4bd06, 0x20948900, 0x0fa4b601, 0xbc0fb4f0, - 0x00d9a0a9, 0xfd008000, 0xabfa05a9, 0x04834f01, 0xb600a9ce, 0x0bf41f95, 0xf8a4bd07, 0x01ff9200, - 0xf000f4b3, 0x00f82d0a, 0x01004089, 0xbc0fa4b6, 0x0089a0a9, 0xb4b60f00, 0x03c4f004, 0xb6ffb4f0, - 0xb9fd02c4, 0x0000d905, 0xbcfd0080, 0x05a9fd05, 0x0901abfa, 0x17453e01, 0x00a9ce00, 0xf40394f0, - 0xdd92100b, 0x00d4b301, 0xb3240af4, 0xbd060094, 0x8900f8a4, 0xbc00028c, 0x96b0989a, 0x0bacf003, - 0x408900f8, 0xa4b60100, 0xa0a9bc0f, 0x800000d9, 0x05a9fd00, 0xf000aace, 0xacf003a4, 0xd900f80b, - 0x00800000, 0xb602aa90, 0xa9fd0fa4, 0x00aace05, 0xf8ffa4f0, 0x08b4b600, 0x0002ec89, 0xffffb4f1, - 0xbc04b5f0, 0x00f8a99b, 0x01284089, 0x800000df, 0x0fa4b600, 0xffa0a9bc, 0x99ce95af, 0x00aab800, - 0xaffd0001, 0xffff8f05, 0x049ffdfe, 0x0400008f, 0x8f059ffd, 0xf0f7ffff, 0x9ffd01b4, 0x13b4b604, - 0x0201008f, 0xfd05bffd, 0xabfa05b9, 0x8900f801, 0xdf012840, 0x00800000, 0xbc0fa4b6, 0xafffa0a9, - 0x0099ce95, 0x0100aab8, 0x05affd00, 0x9ffdfe0f, 0x0295f004, 0xf801a9fa, 0xbd02f900, 0x7ea0b2b4, - 0xb20017a8, 0x17ef7e0a, 0x8901fb00, 0xbc00029c, 0xb4b3a99b, 0x0f0f0f02, 0x0002ac89, 0xf8a99fbc, - 0x02ac8e00, 0x03b4b300, 0x2b8c8f20, 0x0fa99401, 0xdf909fbc, 0x00800000, 0xce059ffd, 0x99c70099, - 0x18673e68, 0xbc94bd00, 0x00f8a9e9, 0x00025889, 0x00f89a20, 0x00025889, 0x00f89a3f, 0x0002fc89, - 0x30989a3c, 0xacf00196, 0x0f00f80b, 0x03008901, 0xa99f3c00, 0x2089f43d, 0x9f3c0005, 0x0f00f8a9, - 0x03048901, 0xa99f3c00, 0x010f00f8, 0x00030889, 0xf8a99f3c, 0x03148900, 0xa99bbc00, 0x148900f8, - 0x9abc0003, 0x4767d9f8, 0xf9a68932, 0xf80bacf0, 0x89f43d00, 0x3c000324, 0xf4bda99f, 0x0002bc89, - 0xf8a99fbc, 0x03248900, 0xa89a3c00, 0x048900f8, 0xa4b60169, 0x0000df0f, 0xa9bc0080, 0xf5afffa0, - 0xde00f9ce, 0x7fffffff, 0xfa049efd, 0x00d901f9, 0xb8008000, 0x0207e0aa, 0xce05a9fd, 0xffdf00a9, - 0xfd7fffff, 0xa9fa049f, 0x8900f801, 0xb6016124, 0xa9bc0fa4, 0x0000d9a0, 0xa9fd0080, 0x00a9ce05, - 0xffffffdf, 0x049ffd7f, 0xf801a9fa, 0x21088900, 0x0fa4b601, 0x800000df, 0xa0a9bc00, 0xcef5afff, - 0x95f100f9, 0xf9fa03ff, 0x0000d901, 0xaa900080, 0x05a9fd40, 0x0f00a9ce, 0x049ffdc0, 0xf0ff3f4f, - 0x9ffd1295, 0x4095f004, 0xf801a9fa, 0x08044900, 0x8d0099ce, 0xde017600, 0x00800000, 0xbc0fa4b6, - 0x008da0ad, 0xaefffe8a, 0xa0adbcf5, 0x3300ffce, 0xe44b0394, 0x738000f9, 0x8f430090, 0xbc01284c, - 0xaeffa0af, 0x0099ce95, 0xb8dfff4f, 0x000100aa, 0xff049ffd, 0xe9fae5ae, 0x0000de01, 0xaa920080, - 0x95aeffe8, 0xb80099ce, 0x000100af, 0xde05fefd, 0xefffffff, 0xfa049efd, 0x00f801f9, 0x044942f9, - 0x0099ce08, 0x0176008d, 0xde0fa394, 0x00800000, 0x8d303dbc, 0xfffe8a00, 0x3dbcf53e, 0x00ffce30, - 0xa9039d33, 0x00f9e400, 0x00997380, 0x4c8f00a0, 0x3fbc0128, 0x254eff40, 0x890020ce, 0xbc01294c, - 0xef093039, 0xfd153eff, 0x10fa0409, 0x02704a01, 0x200005f1, 0x00044c7e, 0xd90110fa, 0x00800000, - 0xffe83392, 0x00ce0539, 0x0031b800, 0x19fd0001, 0xffffd905, 0x09fdbfff, 0x0000d904, 0x09fd1000, - 0x0110fa05, 0x4c7e0f0a, 0x00d90004, 0xfd400000, 0x10fa0509, 0x7e0f0a01, 0xd900044c, 0xbfffffff, - 0xfa0409fd, 0x0f0a0110, 0x00044c7e, 0xbd0022ce, 0x1025f0f4, 0x800000de, 0x954eff00, 0x900192fa, - 0x449001ff, 0x04f4b340, 0x7e41fbf4, 0xb3003afd, 0xb31004a0, 0xb31a07a0, 0x3e0f00a0, 0xda001af4, - 0x01896402, 0x80da00f8, 0xf802faf0, 0x9f88da00, 0x00f8032a, 0xadbeefda, 0xf900f8de, 0x7ea1b222, - 0x33000440, 0x00c001ad, 0x287e1ab2, 0xad330004, 0xb200b501, 0x04347e1a, 0x01ad3300, 0x8c8900aa, - 0x10940130, 0x0009bc0f, 0x800000d9, 0x009b4f00, 0x89e509ff, 0xbcfecf74, 0xe9ce0009, 0x01ff9200, - 0x0f00f4b3, 0x01023209, 0x3e0391b0, 0xb6001b58, 0x90b31f95, 0x24bde801, 0x01005089, 0x09bc1ab2, - 0x5b517e00, 0x7e1ab200, 0xb2006472, 0x5fe37e1a, 0x7e1ab200, 0xb20062f3, 0x63477e1a, 0x7e1ab200, - 0xd90063ae, 0x00800000, 0xce9509ff, 0x94f00099, 0x0c0bf430, 0x2889010f, 0x9f3c0003, 0x4767df19, - 0x14898932, 0x9fbc0003, 0x0024b319, 0x3ea4bd0a, 0xb4001bb6, 0x010f03a0, 0x00032489, 0x3e199f3c, - 0x0a001bc5, 0x8921fb13, 0xbc00028c, 0x22f9989a, 0x90b3a0b2, 0xa4bd0a03, 0x001c873e, 0xd57eb4bd, - 0x0ab20016, 0xc4bd060b, 0x020202dd, 0x05dc4e02, 0x0005e67e, 0x9300adb3, 0x05dc4100, 0x020202d2, - 0xb2070b02, 0x050b7e0a, 0x01119200, 0x667e0ab2, 0xa2a60005, 0xb2751bf4, 0x057d7e0a, 0x00a4b300, - 0xbd0ab26c, 0x0d040cb4, 0x07d04e01, 0x0016807e, 0x5700a4b3, 0x060b0ab2, 0x02ddc4bd, 0x4e010101, - 0xe67e05dc, 0xa4b30005, 0xdc414100, 0x0102d205, 0x070b0101, 0x0b7e0ab2, 0x11920005, 0x7e0ab201, - 0xa6000566, 0x2d1bf4a2, 0x7d7e0ab2, 0xa4b30005, 0x0ab22400, 0xd57e0e0b, 0xa4b30016, 0x020f0d00, - 0x00027c89, 0xfb099fbc, 0x001db321, 0x213eff78, 0x14b3001c, 0x2f0ac000, 0x001c873e, 0xb4bd32f9, - 0xd57ea1b2, 0x1ab20016, 0xc4bd060b, 0x020202dd, 0x09c44e02, 0x0005e67e, 0xa4b3a2b2, 0xc4402c00, - 0x0202d309, 0x070b0202, 0x0b7e1ab2, 0x00920005, 0x7e1ab201, 0xa6000566, 0x111bf4a3, 0x7d7e1ab2, - 0xa4b30005, 0x2ab20800, 0x04b331fb, 0x2e02dc00, 0x001ce63e, 0x00028c89, 0xf9989abc, 0xb3a1b222, - 0xbd0a0390, 0x1d7f3e04, 0x7eb4bd00, 0xb20016d5, 0x00a4b3a0, 0x0b1ab26e, 0xddc4bd06, 0x02020202, - 0x7e09c44e, 0xb20005e6, 0x00a4b3a0, 0x09c44056, 0x020202d2, 0xb2070b02, 0x050b7e1a, 0x01009200, - 0x667e1ab2, 0xa2a60005, 0xb23b1bf4, 0x057d7e1a, 0x00a4b300, 0xbd1ab232, 0x0dc4bdb4, 0x07d04e01, - 0x0016807e, 0xa4b3a0b2, 0x010f1900, 0x00027c89, 0x9fbc1ab2, 0x089b7e19, 0x7e1ab200, 0xb20008fd, - 0xb321fb0a, 0x00b20004, 0x1d7f3e2e, 0x001c8900, 0x9432f901, 0x09bc0fa0, 0x0000d900, 0xa1b20080, - 0x893509ff, 0xbcfeffe4, 0x32ce0009, 0x02cc8900, 0x5c2fc700, 0x7ea99fbc, 0x33003ab8, 0x890f00a4, - 0xbc0002bc, 0x90b39891, 0xf4bd1900, 0x0002bc89, 0x9fbc1ab2, 0x7e020b19, 0x3e00182b, 0x8e001e71, - 0x3f000258, 0x33300ae9, 0x008c009d, 0x0002dc89, 0x09f891bc, 0x0ae92001, 0x01f0b30c, 0x89010f7a, - 0xbc00029c, 0x00df199f, 0xd9400000, 0x8fffffff, 0xfd9429ff, 0x39fa059f, 0x00688901, 0x0000df01, - 0x09bc0080, 0xf50fff00, 0xde00f9ce, 0x40000000, 0xfa059efd, 0x00df01f9, 0x90008000, 0x0fff4400, - 0x00f9cef5, 0xfdcfff4e, 0xf9fa049e, 0x0000d901, 0x0eb80080, 0xfd0022e8, 0xe9ce05e9, 0xffffdf00, - 0x9ffd7fff, 0x01e9fa04, 0xfd01ff90, 0xe9fa059f, 0xfba4bd01, 0x028c8931, 0xbcf4bd00, 0x9c89a99f, - 0x9fbc0002, 0x02bc89a9, 0xa99fbc00, 0x00025c89, 0x89a99fbc, 0xbc0002dc, 0x7c89a99f, 0x9fbc0002, - 0x026c89a9, 0xbc010e00, 0xac89a99e, 0x9fbc0002, 0x02ec89a9, 0xbc02f900, 0xfc89a99f, 0x9e3c0002, - 0x030089a9, 0xa99f3c00, 0x00030489, 0x89a99f3c, 0x3c000308, 0x2489a99f, 0x9f3c0003, 0x032889a9, - 0x3ca0b200, 0x357ea99f, 0x0ab20015, 0x0039c27e, 0x2d7e0ab2, 0x01fb0029, 0x0002dc89, 0xf9989abc, - 0x01a2b222, 0x029db325, 0xbc8901f4, 0xa0940166, 0xbc050f0f, 0x00d90009, 0xff008000, 0x9ffa9509, - 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, - 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, - 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, - 0xd9019ffa, 0x00800000, 0x096800b8, 0x9509ff02, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, - 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, - 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, - 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d101, 0x00b80080, 0x8f00177c, - 0xfffe8af8, 0x0fbc9501, 0x0099ce00, 0xf40194f0, 0x04895f1b, 0x09bc0175, 0x5b127e00, 0x7e2ab200, - 0xb2006630, 0x1e757e2a, 0x7e2ab200, 0xb200070d, 0x07e87e2a, 0xf501ff00, 0xf000f9ce, 0xf9fa0195, - 0x0000df01, 0x00b80080, 0xff021540, 0x99ce950f, 0x0000b800, 0x0fff0010, 0x0099ce95, 0xfe983c89, - 0x080000b8, 0xf50fff02, 0xce0009bc, 0x2ab200f9, 0x0014a67e, 0xadb3a1b2, 0xb2008300, 0x14cb7e2a, - 0xb3a1b200, 0xb27600a4, 0x7e010b2a, 0xb20032ac, 0x00a4b3a1, 0x75048f68, 0x8afc8901, 0x000fbcfe, - 0x800000de, 0xe50eff00, 0xce0009bc, 0xfe0f00e9, 0xfa049ffd, 0x2ab201e9, 0x003b2d7e, 0x1f00a433, - 0x0176088f, 0x8f000fbc, 0xd9fe89f8, 0x00800000, 0xbc9509ff, 0x010f000f, 0xb2019ffa, 0x3b367e2a, - 0x00a43300, 0x76548918, 0xbc010f01, 0x00d90009, 0xff008000, 0x9ffa9509, 0xfb1ab201, 0x7ea4bd21, - 0xbd001e75, 0x3b057ea4, 0x7e010a00, 0x0a001e75, 0x3b057e01, 0x7e020a00, 0x0a001e75, 0x3b057e02, - 0x7e030a00, 0x0a001e75, 0x3b057e03, 0x89f43d00, 0x20000310, 0xb200f89f, 0x01cfc4ad, 0xfa08c049, - 0xbe4f009f, 0x01c0b373, 0x4e030f06, 0xe9cf08c0, 0x0899c700, 0x0bf49ca6, 0x01ff9227, 0xf200f4b3, - 0xf001c6b0, 0x1d090bfc, 0x33a29fbc, 0xb21401b4, 0xb2040bac, 0x02617eda, 0xf8a4bd00, 0xf8a4bd00, - 0x02dc8900, 0x989abc00, 0x110f02f9, 0x94b3a0b2, 0x010b6802, 0x377e010c, 0x0d940021, 0x2820890f, - 0x0000df01, 0xd9bc0080, 0xf5dfffd0, 0x4e00f9ce, 0x9efdfdfe, 0x01f9fa04, 0x800000d9, 0x18dd9000, - 0xfd50b74e, 0xd9ce05d9, 0x209fc600, 0xc70194f0, 0x90b305ff, 0xf4bd0600, 0xb301ee92, 0xb30800e0, - 0xb2e700f0, 0xbd010b0a, 0x21377ec4, 0x89f4bd00, 0xbc0002bc, 0xfab2099f, 0x22f901fb, 0xc1b2b2b2, - 0x947ea0b2, 0x2209003a, 0x8a00ad33, 0x0314b300, 0x028c8f3c, 0x0124b300, 0x0018892b, 0x09f1bc01, - 0xbc0f0f94, 0x00d9f0f9, 0xfd008000, 0xf9ce05f9, 0xffffde00, 0x9efddfff, 0x01f9fa04, 0x0022593e, - 0xf9bc0209, 0x22593e09, 0x028c8900, 0xbc010f00, 0x0209099f, 0x0bf42fa6, 0x00ac893c, 0x0f0d9401, - 0xd9d0d9bc, 0x00800000, 0xce05d9fd, 0x26b000d9, 0x0bfcf000, 0x9401f4f0, 0xf4b602fc, 0xfdf70e03, - 0x9ffd049e, 0xfdfb0f05, 0x9cfd049f, 0x01d9fa05, 0x9ab294bd, 0x8c8921fb, 0x9abc0002, 0xb202f998, - 0x019992a0, 0xf40196b0, 0xdc893e0d, 0x9abc0002, 0x0194b398, 0x03f27e34, 0x01a43300, 0x7e0ab20e, - 0x3e001cf4, 0xb20022cd, 0x1c9c7e0a, 0x00a4b300, 0x7e0ab21a, 0xbd00177f, 0xb2acb2b4, 0x21fa7e0a, - 0x22e73e00, 0xfba4bd00, 0x0c32f901, 0xb2a2b207, 0x4e030db3, 0x807e07d0, 0xa1b20016, 0x3600a4b3, - 0x9207d040, 0x34b30100, 0x2ab20e00, 0x0003d87e, 0x00231a3e, 0xbe7e2ab2, 0xa6b00003, 0x0b9cf007, - 0x0c0000b3, 0xdf009033, 0x0023323e, 0x06009433, 0x1ab20601, 0xdc8931fb, 0x9abc0002, 0xb212f998, - 0x0299b3a1, 0xa87e016b, 0xa4f00003, 0x04a0b3ff, 0x02a0b314, 0x0b1ab210, 0x0d030c04, 0x17087e6e, - 0xbd1ab200, 0x22e97eb4, 0x0b1ab200, 0x22e97e01, 0x284c8900, 0x0f109401, 0x800000de, 0x0009bc00, - 0xce950eff, 0xef0f0099, 0x010000b8, 0x049ffd00, 0xf1e50eff, 0xfa200095, 0x00de01e9, 0x92008000, - 0x0effe800, 0x0099ce95, 0x00b8fd0f, 0xfd000100, 0x0eff049f, 0x0195f0e5, 0x0b01e9fa, 0xb2020c01, - 0x13ee7e1a, 0x0000d900, 0x00b80080, 0x4e000728, 0x09ff0106, 0x0000dab5, 0x00b81000, 0xff020ff4, - 0x6889c509, 0x09bcfedf, 0x00b9ce00, 0xc700cdce, 0x9afd749f, 0x0e0bf404, 0x0b00f4b3, 0x3e1fd995, - 0xbd002405, 0x01ee9294, 0x0800e0b3, 0xdd009033, 0x7e01384a, 0xb200044c, 0x7e030b1a, 0x89001563, - 0xb2012820, 0x0009bc1a, 0x010c010b, 0x0021377e, 0x800000df, 0xf50fff00, 0x4e00f9ce, 0x9efdf3e5, - 0x01f9fa04, 0x800000d9, 0x180f9000, 0xff50b74c, 0xedcee5f9, 0x18d9c400, 0xc6101bf4, 0x9bc740d9, - 0x82d9c406, 0x06009033, 0xcc92b4bd, 0x00c0b301, 0x00b03308, 0xb2b4bde1, 0x17a87e1a, 0xbd010b00, - 0x7e1ab2c4, 0xb2002137, 0x39ac7e1a, 0x7e1ab200, 0x890039b7, 0x0f0002dc, 0x199fbc02, 0x00027c89, + 0xce01944f, 0x99c700a9, 0xf49ca630, 0xff920e0b, 0x00f4b301, 0xf8190af2, 0xf8a4bd00, 0x70908f00, + 0x9412f901, 0xa1b20fa9, 0xdf909fbc, 0x00800000, 0xce059fff, 0x00df0009, 0x0e020000, 0x049ffd1a, + 0x0b280bf4, 0x7ec4bd01, 0xb20013a7, 0x00a4b3ae, 0x0009ce1b, 0xffffffdf, 0x049ffd7f, 0x0f0109fa, + 0x026c8902, 0x199fbc00, 0x11fbeab2, 0x010b02f9, 0xa0b2020c, 0x0013ee7e, 0x010b0ab2, 0xa77e010c, + 0xa4b30013, 0x010f0d00, 0x00026c89, 0xfb099fbc, 0x70908f01, 0x0fa99401, 0xdf909fbc, 0x00800000, + 0xced59fff, 0xffdf00d9, 0xfdfeffff, 0xd9fa049f, 0x030c8e01, 0x0fe9bf00, 0x04fabb01, 0x4905f9fd, + 0xefa00884, 0xf10099cf, 0xb9ffff94, 0x9ffd0099, 0xa6ff0f05, 0x221bf49f, 0x00f4248f, 0xc700d9ce, + 0xff921999, 0x00f0b301, 0x0190b30c, 0x15173ef3, 0xb3170a00, 0xbd060190, 0x8900f8a4, 0xbf00030c, + 0xbc01099f, 0xefffe49a, 0x060bf494, 0x8906fefd, 0xa000030c, 0x8e00f89f, 0xbf00030c, 0xbb0109ef, + 0x9ffd049a, 0xf8e9a005, 0xf012f900, 0xa4b603b4, 0x0cbd940f, 0x01284489, 0xbc04b4b6, 0xe4bda0a9, + 0x800000d1, 0x4ccf0000, 0xa1ffcfff, 0x00f9cef5, 0xfd0490fd, 0x9cfd059b, 0x059dfd04, 0x9001f9fa, + 0xaa9001ee, 0x04e4b340, 0xf911fbe5, 0x0c0c8912, 0x989a3c00, 0x380aa0b2, 0xcc019933, 0x02fc8900, + 0xf8903c00, 0x00029c89, 0x0ae890bc, 0x01f6300e, 0xb00b9cf0, 0xfcf002e6, 0x01f6f00b, 0xf5049ffd, + 0x8900a51b, 0x3c000328, 0x120a9890, 0x98019933, 0x0f0d9400, 0x01001c89, 0x800000dc, 0xd0d9bc00, + 0xcec5dcff, 0xcc8900ce, 0x90bc0002, 0xffffdf98, 0xeffd8fff, 0x0794f004, 0xfd1c94b6, 0xcefa05e9, + 0x0000df01, 0xddb80080, 0xff002804, 0xf9cef5df, 0x1895f100, 0x01f9fa08, 0x800000d9, 0x18dd9000, + 0xfd00894e, 0xdfce05d9, 0x01ee9200, 0xb303f9c7, 0xc7120194, 0x94b304f9, 0xf1c70b01, 0x0110b307, + 0x00e0b30c, 0x16263e21, 0x00e0b300, 0x0b0ab219, 0x15497e02, 0x02dc8900, 0xbca4bd00, 0x643e0991, + 0x200a0016, 0x448911fb, 0xa4b60100, 0xa0a9bc0f, 0x8f0000d9, 0x0cb4b600, 0xf104c4b6, 0xf0ffffb4, + 0xb9fdffc4, 0x03d4f005, 0xb605bcfd, 0x00d902d4, 0xfd008000, 0xa9fd05bd, 0x01abfa05, 0x9200a9ce, + 0xe4b301ee, 0x040a0800, 0x94f000f8, 0x0190b303, 0xb3050aef, 0xbd060094, 0x8900f8a4, 0xb6012094, + 0xb4f00fa4, 0xa0a9bc0f, 0x800000d9, 0x05a9fd00, 0x4f01abfa, 0xa9ce0483, 0x1f95b600, 0xbd070bf4, + 0x9200f8a4, 0xf4b301ff, 0x2d0af000, 0x408900f8, 0xa4b60100, 0xa0a9bc0f, 0x0f000089, 0xf004b4b6, + 0xb4f003c4, 0x02c4b6ff, 0xd905b9fd, 0x00800000, 0xfd05bcfd, 0xabfa05a9, 0x3e010901, 0xce00172b, + 0x94f000a9, 0x100bf403, 0xb301dd92, 0x0af400d4, 0x0094b324, 0xf8a4bd06, 0x028c8900, 0x989abc00, + 0xf00396b0, 0x00f80bac, 0x01004089, 0xbc0fa4b6, 0x00d9a0a9, 0xfd008000, 0xaace05a9, 0x03a4f000, + 0xf80bacf0, 0x0000d900, 0xaa900080, 0x0fa4b602, 0xce05a9fd, 0xa4f000aa, 0xb600f8ff, 0xec8908b4, + 0xb4f10002, 0xb5f0ffff, 0xa99bbc04, 0x408900f8, 0x00df0128, 0xb6008000, 0xa9bc0fa4, 0x95afffa0, + 0xb80099ce, 0x000100aa, 0x8f05affd, 0xfdfeffff, 0x008f049f, 0x9ffd0400, 0xffff8f05, 0x049ffdf7, + 0x0201008f, 0xfa059ffd, 0x00f801a9, 0xa0b212f9, 0x8e7eb1b2, 0x40890017, 0xc08f0128, 0x04b6fed7, + 0x0009bc0f, 0x800000d9, 0x9509ff00, 0xce000fbc, 0xfe0f0099, 0xc5049ffd, 0x14b3029f, 0x9fc50701, + 0x29408986, 0x0009bc01, 0x800000d9, 0x9509ff00, 0xfb019ffa, 0x029c8911, 0xa99bbc00, 0x0f02b4b3, + 0xac890f0f, 0x9fbc0002, 0x8e00f8a9, 0xb30002ac, 0x8f2003b4, 0x94012b8c, 0x9fbc0fa9, 0x0000df90, + 0x9ffd0080, 0x0099ce05, 0x3e6899c7, 0xbd001851, 0xa9e9bc94, 0x588900f8, 0x9a200002, 0xfc8900f8, + 0x9a3c0002, 0x01963098, 0xf80bacf0, 0x89010f00, 0x3c000300, 0xf43da99f, 0x00052089, 0xf8a99f3c, + 0x89010f00, 0x3c000304, 0x00f8a99f, 0x0889010f, 0x9f3c0003, 0x8900f8a9, 0xbc000314, 0x00f8a99b, + 0x00031489, 0xd9f89abc, 0x89324767, 0xacf0f9a6, 0x3d00f80b, 0x032489f4, 0xa99f3c00, 0xbc89f4bd, + 0x9fbc0002, 0x8900f8a9, 0x3c000324, 0x00f8a89a, 0x01690489, 0xdf0fa4b6, 0x00800000, 0xffa0a9bc, + 0xf9cef5af, 0xffffde00, 0x9efd7fff, 0x01f9fa04, 0x800000d9, 0xe0aab800, 0xa9fd0207, 0x00a9ce05, + 0xffffffdf, 0x049ffd7f, 0xf801a9fa, 0x61248900, 0x0fa4b601, 0xd9a0a9bc, 0x00800000, 0xce05a9fd, + 0xffdf00a9, 0xfd7fffff, 0xa9fa049f, 0x8900f801, 0xb6012108, 0x00df0fa4, 0xbc008000, 0xafffa0a9, + 0x00f9cef5, 0x03ff95f1, 0xd901f9fa, 0x00800000, 0xfd40aa90, 0xa9ce05a9, 0xfdc00f00, 0x3f4f049f, + 0x1295f0ff, 0xf0049ffd, 0xa9fa4095, 0x4900f801, 0x99ce0804, 0x76008d00, 0x0000de01, 0xa4b60080, + 0xa0adbc0f, 0xfe8a008d, 0xbcf5aeff, 0xffcea0ad, 0x03943300, 0x00f9e44b, 0x00907380, 0x284c8f43, + 0xa0afbc01, 0xce95aeff, 0xff4f0099, 0x00aab8df, 0x9ffd0001, 0xe5aeff04, 0xde01e9fa, 0x00800000, + 0xffe8aa92, 0x99ce95ae, 0x00afb800, 0xfefd0001, 0xffffde05, 0x9efdefff, 0x01f9fa04, 0x42f900f8, + 0xce080449, 0x008d0099, 0xa3940176, 0x0000de0f, 0x3dbc0080, 0x8a008d30, 0xf53efffe, 0xce303dbc, + 0x9d3300ff, 0xe400a903, 0x738000f9, 0x00a00099, 0x01284c8f, 0xff403fbc, 0x20ce254e, 0x294c8900, + 0x3039bc01, 0x3effef09, 0x0409fd15, 0x4a0110fa, 0x05f10270, 0x4c7e2000, 0x10fa0004, 0x0000d901, + 0x33920080, 0x0539ffe8, 0xb80000ce, 0x00010031, 0xd90519fd, 0xbfffffff, 0xd90409fd, 0x10000000, + 0xfa0509fd, 0x0f0a0110, 0x00044c7e, 0x000000d9, 0x0509fd40, 0x0a0110fa, 0x044c7e0f, 0xffffd900, + 0x09fdbfff, 0x0110fa04, 0x4c7e0f0a, 0x22ce0004, 0xf0f4bd00, 0x00de1025, 0xff008000, 0x92fa954e, + 0x01ff9001, 0xb3404490, 0xfbf404f4, 0x3add7e41, 0x04a0b300, 0x07a0b310, 0x00a0b31a, 0x1ad63e0f, + 0x6402da00, 0x00f80189, 0xfaf080da, 0xda00f802, 0x032a9f88, 0xefda00f8, 0xf8deadbe, 0xb222f900, + 0x04407ea1, 0x01ad3300, 0x1ab200c0, 0x0004287e, 0xb501ad33, 0x7e1ab200, 0x33000434, 0x00aa01ad, + 0x01308c89, 0xbc0f1094, 0x00d90009, 0x4f008000, 0x09ff009b, 0xcf7489e5, 0x0009bcfe, 0x9200e9ce, + 0xf4b301ff, 0x32090f00, 0x91b00102, 0x1b3a3e03, 0x1f95b600, 0xe80190b3, 0x508924bd, 0x1ab20100, + 0x7e0009bc, 0xb2005b31, 0x64527e1a, 0x7e1ab200, 0xb2005fc3, 0x62d37e1a, 0x7e1ab200, 0xb2006327, + 0x638e7e1a, 0x0000d900, 0x09ff0080, 0x0099ce95, 0xf43094f0, 0x010f0c0b, 0x00032889, 0xdf199f3c, + 0x89324767, 0x00031489, 0xb3199fbc, 0xbd0a0024, 0x1b983ea4, 0x03a0b400, 0x2489010f, 0x9f3c0003, + 0x1ba73e19, 0xfb130a00, 0x028c8921, 0x989abc00, 0xa0b222f9, 0x0a0390b3, 0x693ea4bd, 0xb4bd001c, + 0x0016bb7e, 0x060b0ab2, 0x02ddc4bd, 0x4e020202, 0xe67e05dc, 0xadb30005, 0x41009300, 0x02d205dc, + 0x0b020202, 0x7e0ab207, 0x9200050b, 0x0ab20111, 0x0005667e, 0x1bf4a2a6, 0x7e0ab275, 0xb300057d, + 0xb26c00a4, 0x0cb4bd0a, 0x4e010d04, 0x667e07d0, 0xa4b30016, 0x0ab25700, 0xc4bd060b, 0x010102dd, + 0x05dc4e01, 0x0005e67e, 0x4100a4b3, 0xd205dc41, 0x01010102, 0x0ab2070b, 0x00050b7e, 0xb2011192, + 0x05667e0a, 0xf4a2a600, 0x0ab22d1b, 0x00057d7e, 0x2400a4b3, 0x0e0b0ab2, 0x0016bb7e, 0x0d00a4b3, + 0x7c89020f, 0x9fbc0002, 0xb321fb09, 0xff78001d, 0x001c033e, 0xc00014b3, 0x693e2f0a, 0x32f9001c, + 0xa1b2b4bd, 0x0016bb7e, 0x060b1ab2, 0x02ddc4bd, 0x4e020202, 0xe67e09c4, 0xa2b20005, 0x2c00a4b3, + 0xd309c440, 0x02020202, 0x1ab2070b, 0x00050b7e, 0xb2010092, 0x05667e1a, 0xf4a3a600, 0x1ab2111b, + 0x00057d7e, 0x0800a4b3, 0x31fb2ab2, 0xdc0004b3, 0xc83e2e02, 0x8c89001c, 0x9abc0002, 0xb222f998, + 0x0390b3a1, 0x3e04bd0a, 0xbd001d61, 0x16bb7eb4, 0xb3a0b200, 0xb26e00a4, 0xbd060b1a, 0x0202ddc4, + 0xc44e0202, 0x05e67e09, 0xb3a0b200, 0x405600a4, 0x02d209c4, 0x0b020202, 0x7e1ab207, 0x9200050b, + 0x1ab20100, 0x0005667e, 0x1bf4a2a6, 0x7e1ab23b, 0xb300057d, 0xb23200a4, 0xbdb4bd1a, 0x4e010dc4, + 0x667e07d0, 0xa0b20016, 0x1900a4b3, 0x7c89010f, 0x1ab20002, 0x7e199fbc, 0xb200089b, 0x08fd7e1a, + 0xfb0ab200, 0x0004b321, 0x3e2e00b2, 0x89001d61, 0xf901001c, 0x0fa09432, 0xd90009bc, 0x00800000, + 0x09ffa1b2, 0xffe48935, 0x0009bcfe, 0x890032ce, 0xc70002cc, 0x9fbc5c2f, 0x3a987ea9, 0x00a43300, + 0x02bc890f, 0x9891bc00, 0x190090b3, 0xbc89f4bd, 0x1ab20002, 0x0b199fbc, 0x18157e02, 0x1e533e00, + 0x02588e00, 0x0ae93f00, 0x009d3330, 0xdc89008c, 0x91bc0002, 0x200109f8, 0xb30c0ae9, 0x0f7a01f0, + 0x029c8901, 0x199fbc00, 0x000000df, 0xffffd940, 0x29ff8fff, 0x059ffd94, 0x890139fa, 0xdf010068, + 0x00800000, 0xff0009bc, 0xf9cef50f, 0x0000de00, 0x9efd4000, 0x01f9fa05, 0x800000df, 0x44009000, + 0xcef50fff, 0xff4e00f9, 0x049efdcf, 0xd901f9fa, 0x00800000, 0x22e80eb8, 0x05e9fd00, 0xdf00e9ce, + 0x7fffffff, 0xfa049ffd, 0xff9001e9, 0x059ffd01, 0xbd01e9fa, 0x8931fba4, 0xbd00028c, 0xa99fbcf4, + 0x00029c89, 0x89a99fbc, 0xbc0002bc, 0x5c89a99f, 0x9fbc0002, 0x02dc89a9, 0xa99fbc00, 0x00027c89, + 0x89a99fbc, 0x0e00026c, 0xa99ebc01, 0x0002ac89, 0x89a99fbc, 0xf90002ec, 0xa99fbc02, 0x0002fc89, + 0x89a99e3c, 0x3c000300, 0x0489a99f, 0x9f3c0003, 0x030889a9, 0xa99f3c00, 0x00032489, 0x89a99f3c, + 0xb2000328, 0xa99f3ca0, 0x00151b7e, 0xa27e0ab2, 0x0ab20039, 0x00290d7e, 0xdc8901fb, 0x9abc0002, + 0xb222f998, 0xb32501a2, 0x01f4029d, 0x0166bc89, 0x0f0fa094, 0x0009bc05, 0x800000d9, 0x9509ff00, + 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, + 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, + 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, + 0x9ffa9509, 0x0000d901, 0x00b80080, 0xff020968, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, + 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, + 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, + 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd1019ffa, 0x00800000, 0x177c00b8, + 0x8af88f00, 0x9501fffe, 0xce000fbc, 0x94f00099, 0x5f1bf401, 0x01750489, 0x7e0009bc, 0xb2005af2, + 0x66107e2a, 0x7e2ab200, 0xb2001e57, 0x070d7e2a, 0x7e2ab200, 0xff0007e8, 0xf9cef501, 0x0195f000, + 0xdf01f9fa, 0x00800000, 0x154000b8, 0x950fff02, 0xb80099ce, 0x00100000, 0xce950fff, 0x3c890099, + 0x00b8fe98, 0xff020800, 0x09bcf50f, 0x00f9ce00, 0x8c7e2ab2, 0xa1b20014, 0x8300adb3, 0x7e2ab200, + 0xb20014b1, 0x00a4b3a1, 0x0b2ab276, 0x328c7e01, 0xb3a1b200, 0x8f6800a4, 0x89017504, 0xbcfe8afc, + 0x00de000f, 0xff008000, 0x09bce50e, 0x00e9ce00, 0x9ffdfe0f, 0x01e9fa04, 0x0d7e2ab2, 0xa433003b, + 0x088f1f00, 0x0fbc0176, 0x89f88f00, 0x0000d9fe, 0x09ff0080, 0x000fbc95, 0x9ffa010f, 0x7e2ab201, + 0x33003b16, 0x891800a4, 0x0f017654, 0x0009bc01, 0x800000d9, 0x9509ff00, 0xb2019ffa, 0xbd21fb1a, + 0x1e577ea4, 0x7ea4bd00, 0x0a003ae5, 0x1e577e01, 0x7e010a00, 0x0a003ae5, 0x1e577e02, 0x7e020a00, + 0x0a003ae5, 0x1e577e03, 0x7e030a00, 0x3d003ae5, 0x031089f4, 0xf89f2000, 0xc4adb200, 0xc04901cf, + 0x009ffa08, 0xb373be4f, 0x0f0601c0, 0x08c04e03, 0xc700e9cf, 0x9ca60899, 0x92270bf4, 0xf4b301ff, + 0xc6b0f200, 0x0bfcf001, 0x9fbc1d09, 0x01b433a2, 0x0bacb214, 0x7edab204, 0xbd000261, 0xbd00f8a4, + 0x8900f8a4, 0xbc0002dc, 0x02f9989a, 0xa0b2110f, 0x680294b3, 0x010c010b, 0x0021197e, 0x890f0d94, + 0xdf012820, 0x00800000, 0xffd0d9bc, 0xf9cef5df, 0xfdfe4e00, 0xfa049efd, 0x00d901f9, 0x90008000, + 0xb74e18dd, 0x05d9fd50, 0xc600d9ce, 0x94f0209f, 0x05ffc701, 0x060090b3, 0xee92f4bd, 0x00e0b301, + 0x00f0b308, 0x0b0ab2e7, 0x7ec4bd01, 0xbd002119, 0x02bc89f4, 0x099fbc00, 0x01fbfab2, 0xb2b222f9, + 0xa0b2c1b2, 0x003a747e, 0xad332209, 0xb3008a00, 0x8f3c0314, 0xb300028c, 0x892b0124, 0xbc010018, + 0x0f9409f1, 0xf0f9bc0f, 0x800000d9, 0x05f9fd00, 0xde00f9ce, 0xdfffffff, 0xfa049efd, 0x3b3e01f9, + 0x02090022, 0x3e09f9bc, 0x8900223b, 0x0f00028c, 0x099fbc01, 0x2fa60209, 0x893c0bf4, 0x940100ac, + 0xd9bc0f0d, 0x0000d9d0, 0xd9fd0080, 0x00d9ce05, 0xf00026b0, 0xf4f00bfc, 0x02fc9401, 0x0e03f4b6, + 0x049efdf7, 0x0f059ffd, 0x049ffdfb, 0xfa059cfd, 0x94bd01d9, 0x21fb9ab2, 0x00028c89, 0xf9989abc, + 0x92a0b202, 0x96b00199, 0x3e0df401, 0x0002dc89, 0xb3989abc, 0x7e340194, 0x330003f2, 0xb20e01a4, + 0x1cd67e0a, 0x22af3e00, 0x7e0ab200, 0xb3001c7e, 0xb21a00a4, 0x17657e0a, 0xb2b4bd00, 0x7e0ab2ac, + 0x3e0021dc, 0xbd0022c9, 0xf901fba4, 0xb2070c32, 0x0db3b2a2, 0x07d04e03, 0x0016667e, 0xa4b3a1b2, + 0xd0403600, 0x01009207, 0x0e0034b3, 0xd87e2ab2, 0xfc3e0003, 0x2ab20022, 0x0003be7e, 0xf007a6b0, + 0x00b30b9c, 0x90330c00, 0x143edf00, 0x94330023, 0x06010600, 0x31fb1ab2, 0x0002dc89, 0xf9989abc, + 0xb3a1b212, 0x01690299, 0x0003a87e, 0xb3ffa4f0, 0xb31404a0, 0xb21002a0, 0x0c040b1a, 0x7e6e0d03, + 0xb20016ee, 0x7eb4bd1a, 0xb20022cb, 0x7e010b1a, 0x890022cb, 0x9401284c, 0x00de0f10, 0xbc008000, + 0x0eff0009, 0x0099ce95, 0x00b8ef0f, 0xfd000100, 0x0eff049f, 0x0095f1e5, 0x01e9fa20, 0x800000de, + 0xe8009200, 0xce950eff, 0xfd0f0099, 0x010000b8, 0x049ffd00, 0xf0e50eff, 0xe9fa0195, 0x0c010b01, + 0x7e1ab202, 0xd90013ee, 0x00800000, 0x072800b8, 0x01064e00, 0xdab509ff, 0x10000000, 0x0ff400b8, + 0xc509ff02, 0xfedf6889, 0xce0009bc, 0xcdce00b9, 0x749fc700, 0xf4049afd, 0xf4b30e0b, 0xd9950b00, + 0x23e73e1f, 0x9294bd00, 0xe0b301ee, 0x90330800, 0x384add00, 0x044c7e01, 0x0b1ab200, 0x15497e03, + 0x28208900, 0xbc1ab201, 0x010b0009, 0x197e010c, 0x00df0021, 0xff008000, 0xf9cef50f, 0xf3e54e00, + 0xfa049efd, 0x00d901f9, 0x90008000, 0xb74c180f, 0xe5f9ff50, 0xc400edce, 0x1bf418d9, 0x40d9c610, + 0xc4069bc7, 0x903382d9, 0xb4bd0600, 0xb301cc92, 0x330800c0, 0xb2e100b0, 0x178e7e1a, 0xbd010b00, + 0x7e1ab2c4, 0xb2002119, 0x398c7e1a, 0x7e1ab200, 0x89003997, 0x0f0002dc, 0x199fbc02, 0x00027c89, 0x9ebce4bd, 0x026c8919, 0x199ebc00, 0x6c8f11fb, 0x02f90100, 0xb20fa994, 0x909fbca0, 0x00dfe4bd, 0xff008000, 0xfefaf59f, 0x0000df01, 0x99920080, 0x059ffd04, 0x9ffaf4bd, 0x0c040b01, 0x7e370d01, - 0xb2001708, 0x23367e0a, 0x8f01fb00, 0xf901006c, 0x0fa99402, 0x9fbca0b2, 0xdfe4bd90, 0x00800000, - 0xfaf59fff, 0x00df01fe, 0x92008000, 0x9ffd0499, 0xfaf4bd05, 0xee7e019f, 0x0ab20018, 0x0022967e, - 0x367e0ab2, 0x01fb0023, 0xa1b242f9, 0x0069307e, 0x00395089, 0x3398913c, 0x94380194, 0x70890f1e, + 0xb20016ee, 0x23187e0a, 0x8f01fb00, 0xf901006c, 0x0fa99402, 0x9fbca0b2, 0xdfe4bd90, 0x00800000, + 0xfaf59fff, 0x00df01fe, 0x92008000, 0x9ffd0499, 0xfaf4bd05, 0xd07e019f, 0x0ab20018, 0x0022787e, + 0x187e0ab2, 0x01fb0023, 0xa1b242f9, 0x00686c7e, 0x00395089, 0x3398913c, 0x94380194, 0x70890f1e, 0xd4bd0128, 0xdae0e9bc, 0x00800000, 0xffffffdb, 0x0000dcc0, 0xeaff1c00, 0x00f9cef5, 0xfd049bfd, 0xf9fa059c, 0x01dd9001, 0xb340ee90, 0x89eb04d4, 0x94012840, 0x09bc0f10, 0x0000d900, 0x09ff0080, 0x004fce45, 0x010000b8, 0x3509ff00, 0xfed6c089, 0xd90009bc, 0x3fffffff, 0xfa04f9fd, 0x1ab2013f, - 0x003ad07e, 0x1ab2abb2, 0x005cc37e, 0xadb3a2b2, 0x8900a300, 0x3c000324, 0x94339891, 0x1ab20a01, - 0x005ba67e, 0x01282089, 0xd90009bc, 0x00800000, 0xced509ff, 0x95f100d9, 0xd9fa0201, 0x180f9001, + 0x003ab07e, 0x1ab2abb2, 0x005ca37e, 0xadb3a2b2, 0x8900a300, 0x3c000324, 0x94339891, 0x1ab20a01, + 0x005b867e, 0x01282089, 0xd90009bc, 0x00800000, 0xced509ff, 0x95f100d9, 0xd9fa0201, 0x180f9001, 0x800000d9, 0xc5f9ff00, 0xce00c84f, 0xff9200ce, 0x01e9c401, 0x0b0194b3, 0xb305e9c7, 0xb30c0190, - 0x3e4a00f0, 0xb30025eb, 0xce4200f0, 0xff8f0049, 0x9ffdf9fe, 0x0139fa04, 0xf100d9ce, 0xfa040295, - 0xc84f01d9, 0x00cece00, 0xc701ff92, 0x94b301e9, 0xe9c70b01, 0x0190b306, 0x00f0b30c, 0x26253e16, - 0x00f4b300, 0x264f3e10, 0x3e370200, 0x02002651, 0xfb2ab221, 0xb252f941, 0xfc30f4a1, 0x003afd7e, - 0x1ab2a4b2, 0x003ad97e, 0x1ab2a3b2, 0x003b127e, 0x00031089, 0xa2b2993f, 0x92019933, 0x3800de00, - 0xe9ce0080, 0xffffdf00, 0x9ffd3fff, 0x01e9fa04, 0x217e1ab2, 0x00d50068, 0x94008000, 0x14890f10, - 0x09bc0171, 0x0505fd00, 0xb20000ce, 0x3aeb7e1a, 0x08884900, 0xb60099cf, 0x0bc41d95, 0x0091b0ff, - 0x3db24cb2, 0xe17e2eb2, 0xa4b3005e, 0x0c896800, 0x913c000c, 0x33390a98, 0x895b0190, 0x3c000c10, + 0x3e4a00f0, 0xb30025cb, 0xce4200f0, 0xff8f0049, 0x9ffdf9fe, 0x0139fa04, 0xf100d9ce, 0xfa040295, + 0xc84f01d9, 0x00cece00, 0xc701ff92, 0x94b301e9, 0xe9c70b01, 0x0190b306, 0x00f0b30c, 0x26053e16, + 0x00f4b300, 0x262f3e10, 0x3e370200, 0x02002631, 0xfb2ab221, 0xb252f941, 0xfc30f4a1, 0x003add7e, + 0x1ab2a4b2, 0x003ab97e, 0x1ab2a3b2, 0x003af27e, 0x00031089, 0xa2b2993f, 0x92019933, 0x3800de00, + 0xe9ce0080, 0xffffdf00, 0x9ffd3fff, 0x01e9fa04, 0x487e1ab2, 0x00d50069, 0x94008000, 0x14890f10, + 0x09bc0171, 0x0505fd00, 0xb20000ce, 0x3acb7e1a, 0x08884900, 0xb60099cf, 0x0bc41d95, 0x0091b0ff, + 0x3db24cb2, 0xc17e2eb2, 0xa4b3005e, 0x0c896800, 0x913c000c, 0x33390a98, 0x895b0190, 0x3c000c10, 0x94339891, 0x04de2001, 0xce008038, 0xff8f00e9, 0x95fde0ff, 0x049ffd05, 0x0a00008f, 0xfa059ffd, 0x010f01e9, 0x00031089, 0x90899f20, 0x1f940170, 0xf0f9bc0f, 0x800000d9, 0x05f9fd00, 0xde00f9ce, - 0x01000000, 0xfa059efd, 0x1ab201f9, 0x0015357e, 0x30f4a4bd, 0xf951fb04, 0x73108942, 0x0fa19401, + 0x01000000, 0xfa059efd, 0x1ab201f9, 0x00151b7e, 0x30f4a4bd, 0xf951fb04, 0x73108942, 0x0fa19401, 0x19bca0b2, 0x0000df10, 0x1fff0080, 0x00f9cef5, 0xfa0295f0, 0x588901f9, 0x11b8fe8b, 0xdf000198, - 0x00800000, 0xbcf51fff, 0xf9ce1019, 0xe495f000, 0x7e01f9fa, 0xb20067ab, 0x69047e0a, 0x7e0ab200, - 0xb3003aeb, 0xb22e02a4, 0x69e27e0a, 0x7e0ab200, 0xb3003af4, 0xb20a02a4, 0x698a7e0a, 0x7e0ab200, - 0xb3003af4, 0xb23e03a4, 0x683e7e0a, 0x27e13e00, 0x7e0ab200, 0xb3003aeb, 0xb22a03a4, 0x686a7e0a, - 0x7e0ab200, 0xb3003af4, 0xb20a03a4, 0x68c87e0a, 0x7e0ab200, 0xb3003af4, 0xb20a02a4, 0x68807e0a, - 0x7e0ab200, 0xb3003af4, 0xb20e04a0, 0x3af47e0a, 0x05a4b300, 0x7e0ab20a, 0x8900689c, 0xbc016900, - 0x00d91019, 0xff008000, 0x42ce4519, 0x001fb800, 0xf9ff0208, 0x0031ce35, 0x9d7e0ab2, 0xa033003a, - 0xf7091000, 0xfd1015f0, 0x363e0429, 0xef090028, 0xfd0825f0, 0x0ab20419, 0x003aa67e, 0x1000a033, - 0x15f0ef09, 0x0429fd01, 0x0028543e, 0x25f0fe09, 0x0419fd10, 0xaf7e0ab2, 0xa033003a, 0xfd091000, - 0xff021ec5, 0x723ef429, 0xfd090028, 0xff022fc5, 0x4ffae419, 0x013efa01, 0x2489f43d, 0x9f3c0003, - 0xf941fb09, 0x7ea1b222, 0xb2006a03, 0x3ae27e1a, 0x03a0b300, 0x3874890f, 0x98913c00, 0x0a019433, - 0x7f7e1ab2, 0x1ab20067, 0x003b1b7e, 0x0a00a033, 0x4e7e1ab2, 0x74890069, 0x913c0038, 0x00903398, - 0x7e1ab20a, 0x8900194d, 0x94010068, 0x00df0f10, 0xbc400000, 0x00d90009, 0xff008000, 0x9ffa9509, + 0x00800000, 0xbcf51fff, 0xf9ce1019, 0xe495f000, 0x7e01f9fa, 0xb20068b6, 0x688a7e0a, 0x7e0ab200, + 0xb3003acb, 0xb22e02a4, 0x684b7e0a, 0x7e0ab200, 0xb3003ad4, 0xb20a02a4, 0x692c7e0a, 0x7e0ab200, + 0xb3003ad4, 0xb23e03a4, 0x675f7e0a, 0x27c13e00, 0x7e0ab200, 0xb3003acb, 0xb22a03a4, 0x69a17e0a, + 0x7e0ab200, 0xb3003ad4, 0xb20a03a4, 0x69657e0a, 0x7e0ab200, 0xb3003ad4, 0xb20a02a4, 0x68037e0a, + 0x7e0ab200, 0xb3003ad4, 0xb20e04a0, 0x3ad47e0a, 0x05a4b300, 0x7e0ab20a, 0x890069b7, 0xbc016900, + 0x00d91019, 0xff008000, 0x42ce4519, 0x001fb800, 0xf9ff0208, 0x0031ce35, 0x7d7e0ab2, 0xa033003a, + 0xf7091000, 0xfd1015f0, 0x163e0429, 0xef090028, 0xfd0825f0, 0x0ab20419, 0x003a867e, 0x1000a033, + 0x15f0ef09, 0x0429fd01, 0x0028343e, 0x25f0fe09, 0x0419fd10, 0x8f7e0ab2, 0xa033003a, 0xfd091000, + 0xff021ec5, 0x523ef429, 0xfd090028, 0xff022fc5, 0x4ffae419, 0x013efa01, 0x2489f43d, 0x9f3c0003, + 0xf941fb09, 0x7ea1b222, 0xb20069e3, 0x3ac27e1a, 0x03a0b300, 0x3874890f, 0x98913c00, 0x0a019433, + 0x1f7e1ab2, 0x1ab20068, 0x003afb7e, 0x0a00a033, 0xc77e1ab2, 0x74890067, 0x913c0038, 0x00903398, + 0x7e1ab20a, 0x8900192f, 0x94010068, 0x00df0f10, 0xbc400000, 0x00d90009, 0xff008000, 0x9ffa9509, 0xff948f01, 0x040090fe, 0x800000d9, 0x9509ff00, 0xdf000fbc, 0x11000000, 0x89019ffa, 0x3c000324, - 0x24332891, 0x50892901, 0x1ab20100, 0x7e0009bc, 0xd9006502, 0x00800000, 0xce9509ff, 0x94f00099, + 0x24332891, 0x50892901, 0x1ab20100, 0x7e0009bc, 0xd90064e2, 0x00800000, 0xce9509ff, 0x94f00099, 0x0a0bf430, 0x00032889, 0xfb19923c, 0x02af9421, 0xbb05a994, 0x2c8f029f, 0xe4bd0003, 0xbd909fbc, 0x909fa0f4, 0x999001ee, 0x07e4b304, 0x039c89f8, 0xa99fbc00, 0x0003ac89, 0x89a99fbc, 0x3c0003bc, 0xc489a99f, 0x9fbc0003, 0x8900f8a9, 0x3c0003bc, 0x260f989a, 0x4f009033, 0x0003ac8e, 0xb0f8eabc, - 0x0cf406f6, 0x01f9901d, 0x94a9e9bc, 0x9abb03a9, 0x909fbc02, 0x00032c8f, 0x3ef8f9bc, 0x940029b6, + 0x0cf406f6, 0x01f9901d, 0x94a9e9bc, 0x9abb03a9, 0x909fbc02, 0x00032c8f, 0x3ef8f9bc, 0x94002996, 0xaf9402a9, 0x02f9bb05, 0x00032c89, 0xbff0f9bc, 0xbc0109ff, 0xa9b8a9e9, 0xb6000248, 0x9ffa0294, 0xb2f4bd01, 0xb800f8fa, 0x000248a9, 0xce0294b6, 0x9c8f009d, 0xfabc0003, 0x06e6b0e8, 0x90360cf4, 0xf9bc01e9, 0x03af94a9, 0xbc02fabb, 0x2c8ef0fe, 0xedbc0003, 0x03c08ff9, 0x0794b300, 0x3c01090b, 0x00f8a9f9, 0xf93c943d, 0x89f4bda9, 0xbc0003c4, 0x00f8a99f, 0x0003bc89, 0xf8a99b3c, 0x02a99400, - 0xaf9422f9, 0x12f9bc05, 0x00032c89, 0x981019bc, 0xa2b20510, 0x003b517e, 0x0bf40aa6, 0x3ea43d09, - 0x98002a57, 0x2ab20610, 0x003b5a7e, 0x9cf00aa6, 0x0196f00b, 0xfb019ac6, 0x02a99421, 0xaf9422f9, - 0x12f9bc05, 0x00032c89, 0x981019bc, 0xa2b20310, 0x003b3f7e, 0x0bf40aa6, 0x3ea43d09, 0x98002a93, - 0x2ab20410, 0x003b487e, 0x9cf00aa6, 0x0196f00b, 0xfb019ac6, 0xb212f921, 0x2a597ea0, 0xb2a13200, - 0x2a1d7e0a, 0x02099400, 0xbb050f94, 0x2c8902f9, 0xf9bc0003, 0x0ef9bff0, 0x0694b309, 0x00163028, + 0xaf9422f9, 0x12f9bc05, 0x00032c89, 0x981019bc, 0xa2b20510, 0x003b317e, 0x0bf40aa6, 0x3ea43d09, + 0x98002a37, 0x2ab20610, 0x003b3a7e, 0x9cf00aa6, 0x0196f00b, 0xfb019ac6, 0x02a99421, 0xaf9422f9, + 0x12f9bc05, 0x00032c89, 0x981019bc, 0xa2b20310, 0x003b1f7e, 0x0bf40aa6, 0x3ea43d09, 0x98002a73, + 0x2ab20410, 0x003b287e, 0x9cf00aa6, 0x0196f00b, 0xfb019ac6, 0xb212f921, 0x2a397ea0, 0xb2a13200, + 0x29fd7e0a, 0x02099400, 0xbb050f94, 0x2c8902f9, 0xf9bc0003, 0x0ef9bff0, 0x0694b309, 0x00163028, 0x300bfcf0, 0x9cf000a6, 0x00f0330b, 0x33030e0a, 0x0e120094, 0x00f43301, 0x33020e0c, 0x0e060094, 0x89eab20f, 0xbc0003c4, 0x11fb099e, 0x9402af94, 0x9fbb05a9, 0x032c8f02, 0x909fbc00, 0x9fa0060f, 0x01287089, 0xac9432f9, 0xbca1b20f, 0xb4bdc0c9, 0x0d03a994, 0x229abc01, 0x800000d3, 0x032c8000, 0x95c3ff00, 0xc70099ce, 0x9fc7509e, 0x0ae4b668, 0xb63f94f0, 0x2dbc06f4, 0x05f9fda0, 0xfd01b9c4, - 0xfe9405fe, 0x0094b310, 0xa90fbc0b, 0x002b5c3e, 0x90980abc, 0xe9ff01dd, 0xa909bc95, 0x9001bb90, - 0xb4b340cc, 0x1ab2bf04, 0x003b3f7e, 0x8f021994, 0x9400032c, 0x09bb0510, 0x000fbc02, 0xb2030ab5, - 0x3b487e1a, 0x040ab500, 0x517e1ab2, 0x0ab5003b, 0x7e1ab205, 0x89003b5a, 0xbd00039c, 0x199fbcf4, + 0xfe9405fe, 0x0094b310, 0xa90fbc0b, 0x002b3c3e, 0x90980abc, 0xe9ff01dd, 0xa909bc95, 0x9001bb90, + 0xb4b340cc, 0x1ab2bf04, 0x003b1f7e, 0x8f021994, 0x9400032c, 0x09bb0510, 0x000fbc02, 0xb2030ab5, + 0x3b287e1a, 0x040ab500, 0x317e1ab2, 0x0ab5003b, 0x7e1ab205, 0x89003b3a, 0xbd00039c, 0x199fbcf4, 0x0003ac89, 0xbc060ab5, 0x010f199f, 0x0003bc89, 0xfb199f3c, 0x27888931, 0xb299bf00, 0x0094b3af, - 0x3b688925, 0xb399bf00, 0xa6100194, 0x089cf0ab, 0x3e0196f0, 0x3d002bfb, 0xf4fba6a4, 0x010a2b0d, + 0x3b688925, 0xb399bf00, 0xa6100194, 0x089cf0ab, 0x3e0196f0, 0x3d002bdb, 0xf4fba6a4, 0x010a2b0d, 0x90b300f8, 0xa43d0801, 0x688900f8, 0x99bf003b, 0x0f0194b3, 0xfba6a43d, 0x320e0cf4, 0xa600f89a, 0x089cf0ab, 0x00f89a32, 0x0038d089, 0xa4b6e4bd, 0xa0abbc02, 0x89a99ebc, 0xbc002910, 0x3089a99e, 0x010d003a, 0x89a99dbc, 0x8f003b80, 0xbc00ffff, 0x6c89a99f, 0x9d3c003b, 0x3bd089a9, 0xa99e3c00, 0x00369089, 0x89a99ebc, 0xbc0037e8, 0x3089a99e, 0x9ebc0038, 0xf900f8a9, 0x02b99402, 0xae94d0b2, 0x04bd9404, 0xb006af94, 0x1df400c6, 0xf0efbc1d, 0x8e909dbc, 0xbc003550, 0xcfc4909f, 0x909ebc1f, - 0x3e20f5f0, 0xbc002c9d, 0x9dbcf0ef, 0x35508e90, 0x909fbc00, 0xbc01cfb9, 0xf4f0909e, 0x019fb51f, + 0x3e20f5f0, 0xbc002c7d, 0x9dbcf0ef, 0x35508e90, 0x909fbc00, 0xbc01cfb9, 0xf4f0909e, 0x019fb51f, 0x9404b994, 0xbf9406ad, 0xf0f9bc02, 0xbc04a994, 0xf9bc909d, 0x355089f0, 0x010eb900, 0xf0f0f9bc, - 0x94bd0fe4, 0xb502feb5, 0x01fb03f9, 0xb1b232f9, 0x087ea0b2, 0x2889002c, 0x050d003a, 0x94899da0, + 0x94bd0fe4, 0xb502feb5, 0x01fb03f9, 0xb1b232f9, 0xe87ea0b2, 0x2889002b, 0x050d003a, 0x94899da0, 0x0ab20039, 0x04b6140f, 0x0001bc02, 0x89099fbc, 0xa000382c, 0x3760899d, 0xbcf4bd00, 0xd889099f, 0xf10e0039, 0x89099ebc, 0x8200278c, 0xbc003710, 0x1bb2099e, 0x003b2883, 0xbc092ebc, 0xecb2093e, - 0x577eedb2, 0x20bc002c, 0x3830bcf8, 0x00387889, 0x890993bc, 0xbc003954, 0x31fb099f, 0x8e20a9c4, - 0xf4003a2c, 0xa9c40a0b, 0x2d503e1f, 0x01a9b900, 0xbfb9e9a0, 0x3c208901, 0xf89fa000, 0x9832f900, - 0xc19802c2, 0xb2b3b201, 0x2c087ea0, 0xb21ab200, 0x2d3c7e2b, 0x3c208900, 0x3a2c8f00, 0xbf9ebf00, + 0x377eedb2, 0x20bc002c, 0x3830bcf8, 0x00387889, 0x890993bc, 0xbc003954, 0x31fb099f, 0x8e20a9c4, + 0xf4003a2c, 0xa9c40a0b, 0x2d303e1f, 0x01a9b900, 0xbfb9e9a0, 0x3c208901, 0xf89fa000, 0x9832f900, + 0xc19802c2, 0xb2b3b201, 0x2be87ea0, 0xb21ab200, 0x2d1c7e2b, 0x3c208900, 0x3a2c8f00, 0xbf9ebf00, 0x387889ff, 0x0204b600, 0xbc0003bc, 0x5489099f, 0x9ebc0039, 0x9431fb09, 0x9bbc02a9, 0x37a489c0, 0xf89cbc00, 0x0036d089, 0x89e89cbc, 0x0d003a28, 0x899da001, 0xf4003994, 0x22f9ec30, 0xfa90a1b2, 0xc99abc02, 0x00371089, 0x9202e090, 0x9ebc02ee, 0x382c89c9, 0x92b2b200, 0x288b02ff, 0x9da0003b, 0x89c9bfbc, 0xbc003760, 0x1609c990, 0xf416f6b0, 0xeb090c1c, 0x1ff4f9a6, 0xbcea0908, 0xe6b0c9b9, - 0x0f1ef400, 0xbd021994, 0x9092bce4, 0x002e1f3e, 0xe9a6f209, 0x94121ff4, 0xf10e0219, 0x8f9092bc, - 0xbc003710, 0xa6b099fe, 0x0f1df416, 0x0e021994, 0x9092bc16, 0x002e473e, 0xa9a6eb09, 0x94121ff4, - 0xea0e0219, 0x8f9092bc, 0xbc003994, 0x06b099fe, 0x0f1ef400, 0xbd021994, 0x9092bce4, 0x002e6f3e, + 0x0f1ef400, 0xbd021994, 0x9092bce4, 0x002dff3e, 0xe9a6f209, 0x94121ff4, 0xf10e0219, 0x8f9092bc, + 0xbc003710, 0xa6b099fe, 0x0f1df416, 0x0e021994, 0x9092bc16, 0x002e273e, 0xa9a6eb09, 0x94121ff4, + 0xea0e0219, 0x8f9092bc, 0xbc003994, 0x06b099fe, 0x0f1ef400, 0xbd021994, 0x9092bce4, 0x002e4f3e, 0x09a6f209, 0x94121ff4, 0xf10e0219, 0x8f9092bc, 0xbc003760, 0x1f9499fe, 0x3b288902, 0xf0f2bc00, 0x89e89fbc, 0xbc003710, 0xd889089f, 0x9ebc0039, 0x278c89f9, 0xbc1ab200, 0xecb2f990, 0x0db22bb2, - 0x002c577e, 0x94042994, 0x2f94061e, 0xf0f9bc02, 0xbc041994, 0xf9bc909e, 0x355089f0, 0xf0f9bc00, + 0x002c377e, 0x94042994, 0x2f94061e, 0xf0f9bc02, 0xbc041994, 0xf9bc909e, 0x355089f0, 0xf0f9bc00, 0x4dfef9bf, 0x0cdd9001, 0xd9a01ab2, 0xb201f998, 0xb5dcb22b, 0xf99801d9, 0x02d9b502, 0xb503f998, - 0xff9803d9, 0x04dfb504, 0x002d5d7e, 0x891425fb, 0xb6003878, 0xabbc02a4, 0xa99cbca0, 0x00395489, + 0xff9803d9, 0x04dfb504, 0x002d3d7e, 0x891425fb, 0xb6003878, 0xabbc02a4, 0xa99cbca0, 0x00395489, 0xf8a99dbc, 0x02a99400, 0x9bbc42f9, 0x387889f0, 0x289fbc00, 0x0036908e, 0xf40026b0, 0x29c40d1d, - 0x2095f01f, 0x002f2e3e, 0xf00129b9, 0xe9bc1f94, 0x02a994f9, 0x89e09bbc, 0xbc003954, 0x3089489e, + 0x2095f01f, 0x002f0e3e, 0xf00129b9, 0xe9bc1f94, 0x02a994f9, 0x89e09bbc, 0xbc003954, 0x3089489e, 0xe88f0038, 0x9cbc0037, 0x0149b9e9, 0xbc0f94f0, 0xff89e9f9, 0xc9a600ff, 0x89650bf4, 0xbc003b6c, - 0xd93fd0e9, 0x8fffc0c4, 0x33003b80, 0x3d0f0194, 0xe9f0bc94, 0x853ed920, 0xfebc002f, 0xf409a698, - 0xf0bc060d, 0x02a994e9, 0x003a3083, 0xbc109bbc, 0x0ab2b831, 0x002bb57e, 0x2500a033, 0x2ab20bb2, - 0x0076ce7e, 0x0038d089, 0x9abc0bb2, 0x7e4ab219, 0x890076ce, 0xbc002910, 0x9abc1930, 0x8941fb19, + 0xd93fd0e9, 0x8fffc0c4, 0x33003b80, 0x3d0f0194, 0xe9f0bc94, 0x653ed920, 0xfebc002f, 0xf409a698, + 0xf0bc060d, 0x02a994e9, 0x003a3083, 0xbc109bbc, 0x0ab2b831, 0x002b957e, 0x2500a033, 0x2ab20bb2, + 0x0076ba7e, 0x0038d089, 0x9abc0bb2, 0x7e4ab219, 0x890076ba, 0xbc002910, 0x9abc1930, 0x8941fb19, 0x94003690, 0xfbbc02af, 0xa89fbcf0, 0x0037e889, 0x89e89fbc, 0xbc003830, 0xa4f0989f, 0x0fe4f03f, 0xb618a4b6, 0x94f110e4, 0xaefdffff, 0x05a9fd05, 0x808900f8, 0xa4b6003b, 0xa0abbc02, 0xf1a89abc, - 0xf8ef00a5, 0x00a6b000, 0x7e091df4, 0xf800768d, 0x08a4b600, 0x00768d7e, 0xf808a7b6, 0x00a6b000, - 0xb6121df4, 0x8d7e08a4, 0xaa900076, 0x08a7b6ff, 0x8d7e00f8, 0x00f80076, 0x7e08a4b6, 0x9000768d, + 0xf8ef00a5, 0x00a6b000, 0x7e091df4, 0xf8007679, 0x08a4b600, 0x0076797e, 0xf808a7b6, 0x00a6b000, + 0xb6121df4, 0x797e08a4, 0xaa900076, 0x08a7b6ff, 0x797e00f8, 0x00f80076, 0x7e08a4b6, 0x90007679, 0xa7b67faa, 0x8900f808, 0xbf0037a0, 0xb342f999, 0x94230090, 0x308f02a0, 0xd08e003a, 0xa4820038, - 0x10830037, 0xd0840029, 0x94b30036, 0xab3e6002, 0x30890030, 0xa094003a, 0x000bbc02, 0x891890bc, - 0xbc0038d0, 0x1bb2a890, 0x0030057e, 0x0037a489, 0x89099abc, 0xbc002910, 0x1bb2a890, 0x0030057e, - 0x0036d089, 0x3e099abc, 0xbc0030e8, 0xf0bc000b, 0xa8e0bc18, 0x1d7e1bb2, 0x2abc0030, 0xa830bc09, - 0x1d7e1bb2, 0xe53e0030, 0x0bbc0030, 0x18f0bc00, 0xb2a8e0bc, 0x30387e1b, 0x092abc00, 0xb2a830bc, - 0x30387e1b, 0x094abc00, 0x42f941fb, 0xb202e398, 0xb4b2b2a1, 0x40340690, 0x01e0981c, 0x18f4cda6, - 0x7e9cb237, 0xb2002f05, 0x7e3bb20a, 0x89002d3c, 0x8e003c20, 0xbf003a2c, 0x89eebf9d, 0x94003878, - 0xa43d021f, 0xbcf0f2bc, 0x5489f99e, 0x9dbc0039, 0x31683ef9, 0x7e9cb200, 0xb2002f05, 0x7e2bb21a, - 0x0a003047, 0xf44a2601, 0xa48f211b, 0x19940037, 0x9092bc02, 0x8fc8f9bc, 0xbc0036d0, 0x1ab2d8f9, - 0x577e2bb2, 0x4a32002c, 0xa99441fb, 0x8f42f902, 0xbc003bd0, 0x0fbc009b, 0xb2993f90, 0xb2b4b2a3, + 0x10830037, 0xd0840029, 0x94b30036, 0x8b3e6002, 0x30890030, 0xa094003a, 0x000bbc02, 0x891890bc, + 0xbc0038d0, 0x1bb2a890, 0x002fe57e, 0x0037a489, 0x89099abc, 0xbc002910, 0x1bb2a890, 0x002fe57e, + 0x0036d089, 0x3e099abc, 0xbc0030c8, 0xf0bc000b, 0xa8e0bc18, 0xfd7e1bb2, 0x2abc002f, 0xa830bc09, + 0xfd7e1bb2, 0xc53e002f, 0x0bbc0030, 0x18f0bc00, 0xb2a8e0bc, 0x30187e1b, 0x092abc00, 0xb2a830bc, + 0x30187e1b, 0x094abc00, 0x42f941fb, 0xb202e398, 0xb4b2b2a1, 0x40340690, 0x01e0981c, 0x18f4cda6, + 0x7e9cb237, 0xb2002ee5, 0x7e3bb20a, 0x89002d1c, 0x8e003c20, 0xbf003a2c, 0x89eebf9d, 0x94003878, + 0xa43d021f, 0xbcf0f2bc, 0x5489f99e, 0x9dbc0039, 0x31483ef9, 0x7e9cb200, 0xb2002ee5, 0x7e2bb21a, + 0x0a003027, 0xf44a2601, 0xa48f211b, 0x19940037, 0x9092bc02, 0x8fc8f9bc, 0xbc0036d0, 0x1ab2d8f9, + 0x377e2bb2, 0x4a32002c, 0xa99441fb, 0x8f42f902, 0xbc003bd0, 0x0fbc009b, 0xb2993f90, 0xb2b4b2a3, 0x009d33c1, 0xd88d00c3, 0x94890039, 0xd0bc0039, 0x9890bce8, 0x1ff4e9a6, 0x278c8926, 0xf890bc00, - 0x00376089, 0xa69890bc, 0x131cf4f9, 0x003a2889, 0xe9bc99bf, 0x09d9bc90, 0x0031e33e, 0x00278c8b, + 0x00376089, 0xa69890bc, 0x131cf4f9, 0x003a2889, 0xe9bc99bf, 0x09d9bc90, 0x0031c33e, 0x00278c8b, 0x00382c89, 0xbf023e94, 0xe0e4bc9c, 0x003b288d, 0xbcf8bebc, 0xd889d8de, 0xfcbc0039, 0xe99dbcf0, - 0xb2e9bfbc, 0xb23ab21c, 0x2f057e4b, 0x02399400, 0x0039d880, 0x812094bc, 0xbc00278c, 0x12bcc802, - 0xb23ab2d8, 0x2c577e4b, 0xe802bc00, 0x89d812bc, 0xbc003994, 0x7889f892, 0x9ebc0038, 0x39548929, + 0xb2e9bfbc, 0xb23ab21c, 0x2ee57e4b, 0x02399400, 0x0039d880, 0x812094bc, 0xbc00278c, 0x12bcc802, + 0xb23ab2d8, 0x2c377e4b, 0xe802bc00, 0x89d812bc, 0xbc003994, 0x7889f892, 0x9ebc0038, 0x39548929, 0x299dbc00, 0x1ef4efa6, 0x37608946, 0x9892bc00, 0x1ef4d9a6, 0x3bd0893a, 0x2029bc00, 0x29200109, - 0x00326c3e, 0x002f057e, 0x4bb23ab2, 0x0030477e, 0x0037a489, 0x89c890bc, 0xbc0036d0, 0x3ab2d890, - 0x577e4bb2, 0x010a002c, 0x00326e3e, 0x41fba43d, 0xb604bf94, 0xbfbc02b4, 0x35508fb0, 0x06ae9400, + 0x00324c3e, 0x002ee57e, 0x4bb23ab2, 0x0030277e, 0x0037a489, 0x89c890bc, 0xbc0036d0, 0x3ab2d890, + 0x377e4bb2, 0x010a002c, 0x00324e3e, 0x41fba43d, 0xb604bf94, 0xbfbc02b4, 0x35508fb0, 0x06ae9400, 0xbc04a4b6, 0xbabca0ae, 0xb0bfbcb0, 0x9ab2bfbf, 0xbf989fa0, 0x019fb501, 0xb502bf98, 0xbf98029f, 0x039fb503, 0xb504bb98, 0x00f8049b, 0x01738089, 0xbc0fa4b6, 0x00d9a0a9, 0xfd008000, 0xa9ce05a9, 0xfdfe0f00, 0xbfc4049f, 0x059ffd01, 0x4f01a9fa, 0xa9ce50b7, 0x0199c700, 0xa601ff92, 0x0b9cf09b, - 0x0c00f0b3, 0xee009033, 0x0032f23e, 0x90331b0a, 0xa4bd0600, 0xf08900f8, 0x9abc0004, 0xb3aeb2f8, + 0x0c00f0b3, 0xee009033, 0x0032d23e, 0x90331b0a, 0xa4bd0600, 0xf08900f8, 0x9abc0004, 0xb3aeb2f8, 0x0a2b00f0, 0xf4faa601, 0x2089431b, 0x9ebc0004, 0xf0020a98, 0x99920394, 0x0196b002, 0x892e0cf4, 0xbd002784, 0xe99f3ca4, 0x208900f8, 0x9abc0004, 0x0394f098, 0x0b0190b3, 0x9aa6030a, 0x3d0e1bf4, 0x278489f4, 0x3ca4bd00, 0x00f8e99f, 0x00042089, 0x89f89abc, 0xbc000500, 0xaeb2d89a, 0xb302f995, - 0xb03001d0, 0x08f401d6, 0xb3010a0d, 0x3e5c03d4, 0xf00033ab, 0x040a0194, 0x8f4f0bf4, 0x3d003950, - 0xe9f93c94, 0x00290c8f, 0x3ee9f93c, 0xf00033a7, 0x050a0294, 0x3d330bf4, 0x39508f94, 0xe9f93c00, + 0xb03001d0, 0x08f401d6, 0xb3010a0d, 0x3e5c03d4, 0xf000338b, 0x040a0194, 0x8f4f0bf4, 0x3d003950, + 0xe9f93c94, 0x00290c8f, 0x3ee9f93c, 0xf0003387, 0x050a0294, 0x3d330bf4, 0x39508f94, 0xe9f93c00, 0x00290c89, 0xbde99d3c, 0xf000f8a4, 0x060a0894, 0x0f170bf4, 0x39508901, 0x3ca4bd00, 0xf43de99f, 0x00290c89, 0xf8e99f3c, 0x04208900, 0xf89abc00, 0x00051089, 0xb2e89abc, 0x07f995ad, 0x1901e0b3, - 0xf401e6b0, 0x010a2608, 0x2c02e4b3, 0x0a0494f0, 0x33fa3e07, 0x0294f000, 0x90b3080a, 0x50891a00, + 0xf401e6b0, 0x010a2608, 0x2c02e4b3, 0x0a0494f0, 0x33da3e07, 0x0294f000, 0x90b3080a, 0x50891a00, 0xa4bd0037, 0xf8d99ebc, 0x89f4bd00, 0xbc003750, 0xa4bda99f, 0x208e00f8, 0xea3c0005, 0x33afb298, 0xbd080094, 0x8900f8a4, 0xbc000420, 0x0e0a989a, 0xf44094f0, 0x01090a0b, 0xe93ca4bd, 0x8900f8f9, 0xbc000420, 0x2489e89a, 0x9abc0005, 0xc7090df8, 0xefff4aee, 0xf49fa694, 0x94890c1b, 0xd4bd000a, @@ -474,24 +473,24 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0xf003b4f0, 0xf4b61ff4, 0x0f94f017, 0xb607e4f0, 0xe4b60294, 0x059bfd07, 0xfd07d4f0, 0xd4b6059e, 0xffc4f00a, 0xb6059dfd, 0x9cfd0fc4, 0x059ffd05, 0x0176848f, 0xbc0fa4b6, 0x00dfa0af, 0xfd008000, 0xa9fa05af, 0x8900f801, 0xb6010004, 0xa9bc0fa4, 0x0000d9a0, 0xa9fd0080, 0x00aace05, 0xc7080049, - 0xa0b35caa, 0xa6b04202, 0x140cf402, 0xa0b32009, 0x00493600, 0x01a4b301, 0x37643e2d, 0x04a0b300, - 0x40004915, 0xf404a6b0, 0xa4b31d08, 0x5a3e1805, 0x00890037, 0x643e0200, 0x00890037, 0x643e1000, + 0xa0b35caa, 0xa6b04202, 0x140cf402, 0xa0b32009, 0x00493600, 0x01a4b301, 0x37443e2d, 0x04a0b300, + 0x40004915, 0xf404a6b0, 0xa4b31d08, 0x3a3e1805, 0x00890037, 0x443e0200, 0x00890037, 0x443e1000, 0x94bd0037, 0x00f89ab2, 0x1489010f, 0x9fbc000a, 0xf8a4bda9, 0xb662f900, 0x60890fa4, 0xc2320128, 0xbd00a9bc, 0x109990c4, 0x800000d6, 0xa0a9bc00, 0xff44c005, 0xffff83f0, 0x01bf98f8, 0x9802bd98, - 0x243303b1, 0xa6ff0b00, 0x37b03ee5, 0xe506ff00, 0xf000e9ce, 0x95fd3ff4, 0x059ffd04, 0xb60fdfc4, + 0x243303b1, 0xa6ff0b00, 0x37903ee5, 0xe506ff00, 0xf000e9ce, 0x95fd3ff4, 0x059ffd04, 0xb60fdfc4, 0x94fd08f4, 0x059ffd04, 0xfd071fc4, 0xf4b60493, 0x059ffd10, 0x9001e9fa, 0xaa9001cc, 0x14bb9040, 0xb3400090, 0xfbb604c4, 0x02af9461, 0x003a988e, 0xbcf0fbbc, 0x52f9d8ef, 0x001a588e, 0xdf94a2b2, 0x899ab204, 0xb2003950, 0x58923cb4, 0xd99434bd, 0xbc14bd02, 0x04bd909f, 0xbdf09ebc, 0x17d88eb4, - 0xbc030c00, 0x5b3e909e, 0x54330038, 0x93981600, 0x03919804, 0x98029098, 0x9cbf019b, 0x00384e3e, + 0xbc030c00, 0x3b3e909e, 0x54330038, 0x93981600, 0x03919804, 0x98029098, 0x9cbf019b, 0x00382e3e, 0xf398fcbf, 0x03f19804, 0x9802f098, 0xdd9001fb, 0x14999001, 0xb314ff90, 0x0e1100c0, 0x00503320, 0xa6010e06, 0xc508f4de, 0x8f022994, 0xbc003a98, 0xfdbc9094, 0x04a3b599, 0xb503a1b5, 0xabb502a0, 0xfbaca001, 0x00188f51, 0x0fa99401, 0xdf909fbc, 0x00800000, 0xcee59fff, 0x848900ef, 0x9a3c0027, - 0x01943398, 0x0000d910, 0xf9ff4000, 0x38b93e95, 0xffffd900, 0xf9ffbfff, 0x01e9fa94, 0x02f900f8, + 0x01943398, 0x0000d910, 0xf9ff4000, 0x38993e95, 0xffffd900, 0xf9ffbfff, 0x01e9fa94, 0x02f900f8, 0x800000df, 0x0fa99400, 0x0100188e, 0xff909ebc, 0x0cce059f, 0xf899b800, 0x9fff002d, 0x00beceb5, 0x0ffc99b8, 0xd59fff00, 0x8900dfce, 0x3c003950, 0x9433989a, 0x00d91601, 0xf0100000, 0xf5f010e5, - 0x95c9ff10, 0x0039183e, 0xf9fdef09, 0x04e9fd04, 0xffffffd9, 0x94c9ffef, 0xfa0109fa, 0xdffa01be, + 0x95c9ff10, 0x0038f83e, 0xf9fdef09, 0x04e9fd04, 0xffffffd9, 0x94c9ffef, 0xfa0109fa, 0xdffa01be, 0x8f01fb01, 0x94010018, 0x9fbc0fa9, 0x0000df90, 0x9fff0080, 0x00efcee5, 0x00290c89, 0x33989a3c, - 0x09100194, 0x94f9ffe0, 0x3e0895f0, 0x09003954, 0x94f9ffe0, 0xf801e9fa, 0x0fae9400, 0x01001889, + 0x09100194, 0x94f9ffe0, 0x3e0895f0, 0x09003934, 0x94f9ffe0, 0xf801e9fa, 0x0fae9400, 0x01001889, 0x800000dd, 0xe0e9bc00, 0xced5edff, 0x508900df, 0x9abc0037, 0xffffd9c8, 0xf9fdf3ff, 0x03c4f004, 0xfd1ac994, 0xdffa05f9, 0x0000d901, 0xeeb80080, 0xfd002fe8, 0xe9ce05e9, 0xffffdf00, 0xc4b6ff3f, 0x049ffd16, 0xfa059cfd, 0x00f801e9, 0x1489f4bd, 0x9fbc000a, 0xbd00f8a9, 0x0a2489f4, 0xa99fbc00, @@ -508,283 +507,283 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0xf89abf00, 0xbeefdf00, 0xec89dead, 0x9fa00003, 0x008900f8, 0x9abc0005, 0x8900f8a8, 0xbc003750, 0x96b0989a, 0x0bacf000, 0xf801a6f0, 0x0ba48900, 0xa89a3c00, 0xa88900f8, 0x9a3c000b, 0x8900f8a8, 0xbc000440, 0x00f8a89a, 0x00045089, 0xf8a89abc, 0x04608900, 0xa89abc00, 0x708900f8, 0x9abc0004, - 0x8900f8a8, 0xbc000614, 0xb4b3a99b, 0xbdb21109, 0x020bc4bd, 0x3e0dac4e, 0xb2003b84, 0x0bc4bdbd, + 0x8900f8a8, 0xbc000614, 0xb4b3a99b, 0xbdb21109, 0x020bc4bd, 0x3e0dac4e, 0xb2003b64, 0x0bc4bdbd, 0x09c44e02, 0x0005e67e, 0xafb200f8, 0x5933b0b3, 0xf433b6b0, 0xb0b3130c, 0xb0b32430, 0xb4b31831, - 0xc93e6e0c, 0xb0b3003b, 0xb4b35634, 0xd83e6236, 0x4489003b, 0xdc3e000a, 0x4089003b, 0x9abc0004, - 0x045089c8, 0x3bf03e00, 0x0a648900, 0xc89abc00, 0x000a5489, 0x003bf03e, 0x000ae489, 0xbdd89fbc, - 0x3bf33ec4, 0x0ab48900, 0xc89abc00, 0x000ac489, 0x4ed89fbc, 0xe67e09c4, 0x00f80005, 0x000ad489, + 0xa93e6e0c, 0xb0b3003b, 0xb4b35634, 0xb83e6236, 0x4489003b, 0xbc3e000a, 0x4089003b, 0x9abc0004, + 0x045089c8, 0x3bd03e00, 0x0a648900, 0xc89abc00, 0x000a5489, 0x003bd03e, 0x000ae489, 0xbdd89fbc, + 0x3bd33ec4, 0x0ab48900, 0xc89abc00, 0x000ac489, 0x4ed89fbc, 0xe67e09c4, 0x00f80005, 0x000ad489, 0xbdd89abc, 0x09c44ec4, 0x0005e67e, 0xe48900f8, 0x9abc0006, 0xb262f9f8, 0x00f0b3a3, 0xa6010a10, - 0x8b1bf5fa, 0x3c503e00, 0x39508900, 0x989a3c00, 0x14019033, 0x001acb7e, 0x7fd9010f, 0xa60206cc, - 0x050cf4a9, 0x0802f4bd, 0x1d00f0b3, 0x003c633e, 0x00395089, 0x3398933c, 0x020c0194, 0x3ef4bd08, - 0x02003c65, 0x01f9c404, 0x940f3094, 0x14bd1794, 0x01287089, 0x800000d6, 0x0009bc00, 0x7fffffd5, + 0x8b1bf5fa, 0x3c303e00, 0x39508900, 0x989a3c00, 0x14019033, 0x001aad7e, 0x7fd9010f, 0xa60206cc, + 0x050cf4a9, 0x0802f4bd, 0x1d00f0b3, 0x003c433e, 0x00395089, 0x3398933c, 0x020c0194, 0x3ef4bd08, + 0x02003c45, 0x01f9c404, 0x940f3094, 0x14bd1794, 0x01287089, 0x800000d6, 0x0009bc00, 0x7fffffd5, 0xf506ffff, 0xfd00f9ce, 0x94fd0495, 0x01f9fa05, 0x21bc060b, 0x400090d4, 0xb2081190, 0x4ec4bd3a, 0xe67e09c4, 0x14b30005, 0xa4bddb20, 0x30f461fb, 0xb282f9c4, 0xf830f4a2, 0xa701b9b3, 0x01b6b000, - 0xb31108f4, 0x02f002b9, 0xcd04bdb3, 0x3d5f3e03, 0x38b88900, 0x3c010f00, 0xa994a99f, 0x04ae9406, + 0xb31108f4, 0x02f002b9, 0xcd04bdb3, 0x3d3f3e03, 0x38b88900, 0x3c010f00, 0xa994a99f, 0x04ae9406, 0x8930e9bc, 0xb20027cc, 0x3039bce5, 0x0039208f, 0x00391089, 0xd0b2c6b2, 0xbc505fbc, 0x14bd40e9, 0xe8870708, 0x508e0003, 0xe23c0039, 0x01943398, 0xb501a016, 0x08b50101, 0x0301b502, 0x3e0401b5, - 0x0f003d35, 0xb5010904, 0x0fb50101, 0x0301b502, 0xa00409b5, 0x98723c01, 0x0e019433, 0x3bb20ab2, - 0xe87e140c, 0x6ebf0076, 0x90143390, 0x00900466, 0x904ea014, 0x45a60444, 0x3eae1bf4, 0x890040a3, + 0x0f003d15, 0xb5010904, 0x0fb50101, 0x0301b502, 0xa00409b5, 0x98723c01, 0x0e019433, 0x3bb20ab2, + 0xd47e140c, 0x6ebf0076, 0x90143390, 0x00900466, 0x904ea014, 0x45a60444, 0x3eae1bf4, 0x89004083, 0x3c003950, 0x200f9892, 0x330ef1b0, 0x09090090, 0x0e91b001, 0x8f042e94, 0xbc003a98, 0xc089f0ef, 0xf1b00038, 0x022f9413, 0xb090f9bc, 0x22bc1191, 0x9092bc90, 0xb00694b6, 0x88890d91, 0xf9bc003a, 0x3b808980, 0x90e9bc00, 0x890f91b0, 0xbc003910, 0x44fe90e9, 0x1091b001, 0xd889d1b2, 0xc1b0003a, - 0x70f9bc12, 0xe88f34bd, 0x4490003a, 0x60efbc54, 0x9d33893f, 0xb2009500, 0xb22ab249, 0x37e97e3b, + 0x70f9bc12, 0xe88f34bd, 0x4490003a, 0x60efbc54, 0x9d33893f, 0xb2009500, 0xb22ab249, 0x37c97e3b, 0xb449bf00, 0x3bb20ed0, 0x19a02ab2, 0xb5014e98, 0x4f98011e, 0xb54eb202, 0x4998021f, 0x0319b503, 0xbf044f98, 0x041fb519, 0xf0b449a0, 0x01199813, 0x49b5fcbf, 0x021f9801, 0x98024fb5, 0x49b50319, - 0x1290b403, 0xb5041f98, 0x99bf044f, 0x003a808f, 0x3c0091b0, 0xf130f8f2, 0x30ea7e04, 0xbf3bb200, - 0xb28a2060, 0x2fbf7e2a, 0x0de0b400, 0x8f010990, 0xa0002950, 0x9033bc69, 0xb69093bc, 0xe9bc0494, + 0x1290b403, 0xb5041f98, 0x99bf044f, 0x003a808f, 0x3c0091b0, 0xf130f8f2, 0x30ca7e04, 0xbf3bb200, + 0xb28a2060, 0x2f9f7e2a, 0x0de0b400, 0x8f010990, 0xa0002950, 0x9033bc69, 0xb69093bc, 0xe9bc0494, 0x9090bc90, 0x3f99fabc, 0x015d3385, 0x80890105, 0x923c003a, 0x000d3308, 0xe0b400be, 0x33e93f11, - 0xb23b0194, 0x7e3bb22a, 0xb4002d97, 0x49b211f0, 0x3bb22ab2, 0x707ef020, 0x49bf0032, 0x4e9819a0, - 0x011eb501, 0xb5024f98, 0x4998021f, 0x0319b503, 0xb5044e98, 0x1d3e041e, 0x793f003f, 0x61009433, - 0xb212f0b4, 0xbf2ab23b, 0x316a7efc, 0x2049b200, 0xb23bb27a, 0x32707e2a, 0xb249bf00, 0xa03bb22a, - 0x014e9819, 0x98011eb5, 0x1fb5024f, 0x03499802, 0x980319b5, 0x1eb5044e, 0x7e60bf04, 0xbc002fbf, + 0xb23b0194, 0x7e3bb22a, 0xb4002d77, 0x49b211f0, 0x3bb22ab2, 0x507ef020, 0x49bf0032, 0x4e9819a0, + 0x011eb501, 0xb5024f98, 0x4998021f, 0x0319b503, 0xb5044e98, 0xfd3e041e, 0x793f003e, 0x61009433, + 0xb212f0b4, 0xbf2ab23b, 0x314a7efc, 0x2049b200, 0xb23bb27a, 0x32507e2a, 0xb249bf00, 0xa03bb22a, + 0x014e9819, 0x98011eb5, 0x1fb5024f, 0x03499802, 0x980319b5, 0x1eb5044e, 0x7e60bf04, 0xbc002f9f, 0x508e9033, 0x0f900029, 0xb46fa001, 0x93bc0df0, 0x0494b690, 0xbc90f9bc, 0xeabc9090, 0x337f3f99, - 0xb44f01f4, 0xe9bf0fe0, 0x0038b88e, 0x3e29ef3c, 0xb2003f65, 0xb22ab249, 0x32707e3b, 0xa049bf00, + 0xb44f01f4, 0xe9bf0fe0, 0x0038b88e, 0x3e29ef3c, 0xb2003f45, 0xb22ab249, 0x32507e3b, 0xa049bf00, 0x014e9819, 0x98011eb5, 0x1fb5024f, 0x03499802, 0xb50ff0b4, 0x4e980319, 0x041eb504, 0xb88ef9bf, 0xe53c0038, 0x10f0b429, 0xef0095f1, 0x90b4f9a0, 0x10e0b40f, 0x9011f0b4, 0x99900133, 0x04ee9004, 0xb00f91b0, 0x90b410e1, 0x13e0b412, 0xb001ff90, 0x999011f1, 0x04ee9004, 0xb01291b0, 0x889013e1, - 0x14119001, 0x90017790, 0x3db30466, 0x3efe2604, 0x8f0040a3, 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0x099ebc01, 0x0009f489, 0xfb099fbc, - 0xac30f401, 0xa1b232f9, 0x0018e57e, 0x0037e48f, 0x3398f13c, 0x00bf009d, 0xf93c0109, 0xf5a92619, - 0xb200861b, 0x65ef7e1a, 0x0f109400, 0x01287089, 0x09bc24bd, 0x0000d300, 0x03ff0080, 0x0099ce95, + 0xc71cfd95, 0x9fbc78ff, 0x07848909, 0x099dbc00, 0x0047ff3e, 0x0009e489, 0xbd02ac94, 0xc0c9bcd4, + 0x0044ca7e, 0x0009e489, 0x89f890bc, 0xc7000a04, 0xf4f002fe, 0x099ebc01, 0x0009f489, 0xfb099fbc, + 0xac30f401, 0xa1b232f9, 0x0018c77e, 0x0037e48f, 0x3398f13c, 0x00bf009d, 0xf93c0109, 0xf5a92619, + 0xb200861b, 0x65cf7e1a, 0x0f109400, 0x01287089, 0x09bc24bd, 0x0000d300, 0x03ff0080, 0x0099ce95, 0x93fd040d, 0x40009004, 0x060094b3, 0xd2bb080d, 0x901ab204, 0x060b0822, 0xc44ec4bd, 0x05e67e09, - 0x2024b300, 0xbd020bd9, 0xfe1ab2d4, 0x00900140, 0x7e0cb260, 0x4b0044ea, 0x1ab2030a, 0x003b637e, - 0x010f0bbf, 0x0038b889, 0x0f199f3c, 0x3bc08901, 0x199fbc00, 0x030abeb3, 0xbd1ab23e, 0x48f77ec4, - 0x48f43e00, 0x06d48900, 0xb891bc00, 0xb20140fe, 0x1000901a, 0xf97e0cb2, 0x1ab20041, 0xc43d0bb2, - 0x0037757e, 0x0b0b1ab2, 0x248d010c, 0x087e00f4, 0xa4bd0017, 0xb35435fb, 0x5b010aba, 0x010ab6b1, - 0xb3140cf4, 0xb3490ab0, 0x280109ba, 0x1709b4b3, 0x0049273e, 0x0309bab3, 0x0abab32b, 0xbab35803, - 0x0a190209, 0xb200f801, 0x52847ecb, 0xb200f800, 0x4eb37ecb, 0xb200f800, 0x49b67ecb, 0x0f00f800, - 0x0a148901, 0xa99fbc00, 0x00495d3e, 0x0048217e, 0xd48900f8, 0x9a3c0039, 0x00903398, 0xf8a4bd08, - 0x3be08900, 0x04ab9400, 0x7eb0b9bc, 0xf8005419, 0x43cd7e00, 0xf400f800, 0x22f9fc30, 0xc1b2b0b2, - 0xcbb2a2b2, 0x003b637e, 0x290000b3, 0x40fe020b, 0x902ab201, 0xd4bd0c00, 0xea7e0cb2, 0x0bbf0044, - 0x1bf4b1a6, 0xbd2ab20f, 0x48f77ec4, 0x49b33e00, 0xfba4bd00, 0x300b0425, 0xf9e830f4, 0xf4a0b252, - 0x0c7eec30, 0x0ab20045, 0x0c7e0c0b, 0x0ab20045, 0x0035c37e, 0x00093489, 0x929890bc, 0x96b00499, - 0x090cf401, 0xa67e0ab2, 0x0ab20069, 0x0c7e310b, 0x74890045, 0x90bc0006, 0x04c089f8, 0x9890bc00, - 0x0bf4f9a6, 0x0b0ab213, 0x7e080c19, 0x0a000261, 0x4ead3e08, 0x06848900, 0xe890bc00, 0x00050089, - 0xa69890bc, 0x130bf4e9, 0x190b0ab2, 0x617e090c, 0x090a0002, 0x004ead3e, 0x00069489, 0x89f890bc, - 0xbc000510, 0xf9a69890, 0xb2130bf4, 0x0c190b0a, 0x02617e0a, 0x3e0a0a00, 0xb3004ead, 0xb31800f0, - 0xb21401e4, 0x0c190b0a, 0x02617e0b, 0x3e0b0a00, 0xb2004ead, 0x7e360b0a, 0x8900450c, 0xbc0009f4, + 0x2024b300, 0xbd020bd9, 0xfe1ab2d4, 0x00900140, 0x7e0cb260, 0x4b0044ca, 0x1ab2030a, 0x003b437e, + 0x010f0bbf, 0x0038b889, 0x0f199f3c, 0x3bc08901, 0x199fbc00, 0x030abeb3, 0xbd1ab23e, 0x48d77ec4, + 0x48d43e00, 0x06d48900, 0xb891bc00, 0xb20140fe, 0x1000901a, 0xd97e0cb2, 0x1ab20041, 0xc43d0bb2, + 0x0037557e, 0x0b0b1ab2, 0x248d010c, 0xee7e00f4, 0xa4bd0016, 0xb35435fb, 0x5b010aba, 0x010ab6b1, + 0xb3140cf4, 0xb3490ab0, 0x280109ba, 0x1709b4b3, 0x0049073e, 0x0309bab3, 0x0abab32b, 0xbab35803, + 0x0a190209, 0xb200f801, 0x52647ecb, 0xb200f800, 0x4e937ecb, 0xb200f800, 0x49967ecb, 0x0f00f800, + 0x0a148901, 0xa99fbc00, 0x00493d3e, 0x0048017e, 0xd48900f8, 0x9a3c0039, 0x00903398, 0xf8a4bd08, + 0x3be08900, 0x04ab9400, 0x7eb0b9bc, 0xf80053f9, 0x43ad7e00, 0xf400f800, 0x22f9fc30, 0xc1b2b0b2, + 0xcbb2a2b2, 0x003b437e, 0x290000b3, 0x40fe020b, 0x902ab201, 0xd4bd0c00, 0xca7e0cb2, 0x0bbf0044, + 0x1bf4b1a6, 0xbd2ab20f, 0x48d77ec4, 0x49933e00, 0xfba4bd00, 0x300b0425, 0xf9e830f4, 0xf4a0b252, + 0xec7eec30, 0x0ab20044, 0xec7e0c0b, 0x0ab20044, 0x0035a37e, 0x00093489, 0x929890bc, 0x96b00499, + 0x090cf401, 0x8b7e0ab2, 0x0ab20067, 0xec7e310b, 0x74890044, 0x90bc0006, 0x04c089f8, 0x9890bc00, + 0x0bf4f9a6, 0x0b0ab213, 0x7e080c19, 0x0a000261, 0x4e8d3e08, 0x06848900, 0xe890bc00, 0x00050089, + 0xa69890bc, 0x130bf4e9, 0x190b0ab2, 0x617e090c, 0x090a0002, 0x004e8d3e, 0x00069489, 0x89f890bc, + 0xbc000510, 0xf9a69890, 0xb2130bf4, 0x0c190b0a, 0x02617e0a, 0x3e0a0a00, 0xb3004e8d, 0xb31800f0, + 0xb21401e4, 0x0c190b0a, 0x02617e0b, 0x3e0b0a00, 0xb2004e8d, 0x7e360b0a, 0x890044ec, 0xbc0009f4, 0x94b39890, 0x010f0d00, 0x0003d489, 0x89099f3c, 0xbc000a04, 0x94b39890, 0x010f0d00, 0x0003d889, - 0xb2099f3c, 0x36357e0a, 0x05c48900, 0x05748f00, 0x9890bc00, 0xfdf8f0bc, 0x1bf4049f, 0x89010f0c, + 0xb2099f3c, 0x36157e0a, 0x05c48900, 0x05748f00, 0x9890bc00, 0xfdf8f0bc, 0x1bf4049f, 0x89010f0c, 0x3c0003dc, 0xd489099f, 0x848f0005, 0x90bc0005, 0xf8f0bc98, 0xf4049ffd, 0x010f0c1b, 0x0003e089, 0x89099f3c, 0x8f0005e4, 0xbc000594, 0xf0bc9890, 0x049ffdf8, 0x0f0c1bf4, 0x03e48901, 0x099f3c00, - 0x330b0ab2, 0x00450c7e, 0x000a9489, 0x89f890bc, 0xbc000884, 0x0109e890, 0xbbfff4f0, 0xf9fd049e, - 0x131bf404, 0x190b0ab2, 0x617e0d0c, 0x0d0a0002, 0x004ead3e, 0x01309c89, 0x8f0f0194, 0xbcfecf64, + 0x330b0ab2, 0x0044ec7e, 0x000a9489, 0x89f890bc, 0xbc000884, 0x0109e890, 0xbbfff4f0, 0xf9fd049e, + 0x131bf404, 0x190b0ab2, 0x617e0d0c, 0x0d0a0002, 0x004e8d3e, 0x01309c89, 0x8f0f0194, 0xbcfecf64, 0x00d91019, 0xff008000, 0x1fbc4519, 0x004fce10, 0x000af489, 0xd9e890bc, 0x7fffffff, 0xb004f9fd, 0x9cf000e6, 0x1f94b60b, 0xfa05f9fd, 0x3489014f, 0x90bc0007, 0x074489e8, 0xf890bc00, 0x00079489, 0x90d890bc, 0xffbc01ee, 0x909fbc90, 0xbb039992, 0x348904e9, 0x9ebc0008, 0xf4eda609, 0x0ab21318, - 0x100c190b, 0x0002617e, 0xad3e100a, 0x5489004e, 0x90bc0007, 0x076489e8, 0xf890bc00, 0x0007c489, + 0x100c190b, 0x0002617e, 0x8d3e100a, 0x5489004e, 0x90bc0007, 0x076489e8, 0xf890bc00, 0x0007c489, 0x90d890bc, 0xff9001ee, 0x08448201, 0x90ffbc00, 0xbb909fbc, 0x2ebc04e9, 0xf4eda609, 0x0ab21318, - 0x110c190b, 0x0002617e, 0xad3e110a, 0x0ab2004e, 0x001acb7e, 0xbdd820bc, 0x0191b094, 0x090091b0, + 0x110c190b, 0x0002617e, 0x8d3e110a, 0x0ab2004e, 0x001aad7e, 0xbdd820bc, 0x0191b094, 0x090091b0, 0x05a5950b, 0xfe0143fe, 0x33900142, 0x34229038, 0xb00291b0, 0x21b00331, 0xb20ab204, 0xbdc4bd5b, - 0x41197ee4, 0x00adb300, 0x34890288, 0xcc8f0120, 0x19bcfedf, 0x0000dc10, 0x1cff0080, 0x101fbcc5, + 0x40f97ee4, 0x00adb300, 0x34890288, 0xcc8f0120, 0x19bcfedf, 0x0000dc10, 0x1cff0080, 0x101fbcc5, 0xbf00c9ce, 0xb82dbf3e, 0x002833ff, 0xb6049ffd, 0xd4f10be4, 0xe4f107ff, 0x004fffff, 0x059efdf8, 0xfd049ffd, 0xc9fa059d, 0x08448901, 0xd890bc00, 0x91b094bd, 0x00c84901, 0x090091b0, 0x0143fe0b, - 0x900142fe, 0x22903033, 0x0291b02c, 0xb00331b0, 0x0ab20421, 0xc4bd5bb2, 0x197ee4bd, 0xadb30041, + 0x900142fe, 0x22903033, 0x0291b02c, 0xb00331b0, 0x0ab20421, 0xc4bd5bb2, 0xf97ee4bd, 0xadb30040, 0xce020f00, 0x3ebf0049, 0xff8f2dbf, 0x9ffdff07, 0x0be4b604, 0x07ffd4f1, 0xffffe4f1, 0xfdf8004f, 0x9ffd059e, 0x059dfd04, 0x890149fa, 0xd40130ac, 0x00800000, 0x8f1019bc, 0xfffecf54, 0x1fbc9514, 0x0099ce10, 0x0008448f, 0xc7d8f0bc, 0x99e78d9f, 0x9fbb0142, 0x0191b004, 0xb000c849, 0x0b090091, - 0xfe0143fe, 0x33900142, 0x3c229040, 0xb00291b0, 0x21b00331, 0xb20ab204, 0xbdc4bd5b, 0x41197ee4, + 0xfe0143fe, 0x33900142, 0x3c229040, 0xb00291b0, 0x21b00331, 0xb20ab204, 0xbdc4bd5b, 0x40f97ee4, 0x00adb300, 0xa889018c, 0x588f0130, 0x19bcfecf, 0xa514ff10, 0xce101fbc, 0x3ebf00af, 0xac892dbf, 0xfcc7000b, 0x099cbc8d, 0x000bbc89, 0x0142fbe7, 0x89099bbc, 0xf0fc1fff, 0xf9fd1fe4, 0x0de4b604, - 0xfde00349, 0xd4f105fe, 0xf9fd07ff, 0x02d4b604, 0xfa05fdfd, 0x340b01af, 0x0c7e0ab2, 0x74890045, + 0xfde00349, 0xd4f105fe, 0xf9fd07ff, 0x02d4b604, 0xfa05fdfd, 0x340b01af, 0xec7e0ab2, 0x74890044, 0x90bc0007, 0x078489e8, 0x9890bc00, 0x0007f48f, 0x90f8f0bc, 0x999001ee, 0x0294b601, 0x89d4e9bc, - 0xbc000814, 0xdfa6099d, 0xb21318f4, 0x0c190b0a, 0x02617e12, 0x3e120a00, 0x94004ead, 0x248f0202, - 0x2fbc0008, 0xb25bb290, 0x0091b00a, 0xe4bdc4bd, 0x0040ab7e, 0xd900adb3, 0x00048900, 0x1019bc01, + 0xbc000814, 0xdfa6099d, 0xb21318f4, 0x0c190b0a, 0x02617e12, 0x3e120a00, 0x94004e8d, 0x248f0202, + 0x2fbc0008, 0xb25bb290, 0x0091b00a, 0xe4bdc4bd, 0x00408b7e, 0xd900adb3, 0x00048900, 0x1019bc01, 0x800000d9, 0xa519ff00, 0x8900aece, 0xbc000824, 0xf0b3f890, 0xf4f11500, 0x004907ff, 0x94e9fff8, - 0x3e059ffd, 0xd9004e0f, 0x80000000, 0xfa95e9ff, 0xa48901a9, 0x90bc0006, 0x0aa489e8, 0xf890bc00, - 0x9ebb0109, 0xfff4f104, 0x04f9fdff, 0xb2131bf4, 0x0c190b0a, 0x02617e06, 0x3e060a00, 0x89004ead, + 0x3e059ffd, 0xd9004def, 0x80000000, 0xfa95e9ff, 0xa48901a9, 0x90bc0006, 0x0aa489e8, 0xf890bc00, + 0x9ebb0109, 0xfff4f104, 0x04f9fdff, 0xb2131bf4, 0x0c190b0a, 0x02617e06, 0x3e060a00, 0x89004e8d, 0xbc0006d4, 0xe4b3099e, 0x80890b01, 0x9e3c003a, 0x06b48909, 0xd890bc00, 0x000aa489, 0x8f9890bc, 0xde010000, 0x00ff0000, 0xfd04fdbb, 0x9ffd049e, 0x131bf404, 0x190b0ab2, 0x617e070c, 0x070a0002, - 0x004ead3e, 0x0006e489, 0x9dbc0ab2, 0x36967e09, 0x06c48f00, 0xbc0ab200, 0x030bc02f, 0xea7ed4bd, - 0x0ab20044, 0x094c010b, 0x49777e03, 0x1430f400, 0x891855fb, 0xbc0004c0, 0xf089f89a, 0x9abc0004, + 0x004e8d3e, 0x0006e489, 0x9dbc0ab2, 0x36767e09, 0x06c48f00, 0xbc0ab200, 0x030bc02f, 0xca7ed4bd, + 0x0ab20044, 0x094c010b, 0x49577e03, 0x1430f400, 0x891855fb, 0xbc0004c0, 0xf089f89a, 0x9abc0004, 0x050089d8, 0xe89abc00, 0x00051089, 0xf0989abc, 0xf4f001d4, 0x0fe4f003, 0xb60f94f0, 0xe4b61094, - 0x04f4b608, 0xfd05fdfd, 0xf9fd05fe, 0x0a448905, 0xbc22f900, 0xa0b2a99f, 0x310bb2b2, 0x003b8a7e, - 0x300b0ab2, 0x003b8a7e, 0x00049089, 0x89d890bc, 0xbc0004b0, 0xa089e890, 0x90bc0004, 0x048089f8, + 0x04f4b608, 0xfd05fdfd, 0xf9fd05fe, 0x0a448905, 0xbc22f900, 0xa0b2a99f, 0x310bb2b2, 0x003b6a7e, + 0x300b0ab2, 0x003b6a7e, 0x00049089, 0x89d890bc, 0xbc0004b0, 0xa089e890, 0x90bc0004, 0x048089f8, 0x9890bc00, 0xb618dc94, 0xf4f108f4, 0x94f0ffff, 0x05f9fdff, 0x000a6489, 0xb608d5b6, 0xedfd1ae4, - 0x099ebc05, 0x2e000089, 0x8905f9fd, 0xfd000a54, 0x0ab205fc, 0x0b099fbc, 0x3b8a7e0c, 0x05f48900, + 0x099ebc05, 0x2f000089, 0x8905f9fd, 0xfd000a54, 0x0ab205fc, 0x0b099fbc, 0x3b6a7e0c, 0x05f48900, 0xf890bc00, 0x0005a489, 0x89d890bc, 0xbc000604, 0xb489e890, 0x90bc0005, 0x04fdfd98, 0xb201fdc4, 0x04e9fd0a, 0x000b8489, 0x8f099fbc, 0xc4000b94, 0xfebc01e9, 0x0294b609, 0x000ae48f, 0x0b059dfd, - 0x09f9bc36, 0x003b8a7e, 0x00087489, 0x89f890bc, 0xbc000524, 0xf9fd9890, 0x131bf404, 0x190b0ab2, - 0x617e030c, 0x030a0002, 0x0052823e, 0xf404f9c4, 0x020f090b, 0x004fe03e, 0xf402fec4, 0x010f100b, - 0x000af489, 0x3e099fbc, 0xc4004ff8, 0x0bf401f9, 0x0af4890a, 0x099ebc00, 0x00055489, 0x000af48f, + 0x09f9bc36, 0x003b6a7e, 0x00087489, 0x89f890bc, 0xbc000524, 0xf9fd9890, 0x131bf404, 0x190b0ab2, + 0x617e030c, 0x030a0002, 0x0052623e, 0xf404f9c4, 0x020f090b, 0x004fc03e, 0xf402fec4, 0x010f100b, + 0x000af489, 0x3e099fbc, 0xc4004fd8, 0x0bf401f9, 0x0af4890a, 0x099ebc00, 0x00055489, 0x000af48f, 0xbc1890bc, 0x6489f8f0, 0x90bc0005, 0x085489a8, 0xb890bc00, 0x00086489, 0x89c890bc, 0xbc000ab4, 0xaf90099f, 0x90ffbc01, 0x90909fbc, 0xd9bb011d, 0x07c48904, 0x01ce9000, 0xbc099dbc, 0x9ebc90ee, 0x01bf9090, 0x8904f9bb, 0xbc0007d4, 0x548e099f, 0x4489000b, 0xfda6000b, 0xbc0d0df4, 0xecbc099b, - 0x506b3e09, 0x0991bc00, 0x8909eabc, 0xbc000714, 0x2489b890, 0x90bc0007, 0x079489e8, 0xbc030f00, + 0x504b3e09, 0x0991bc00, 0x8909eabc, 0xbc000714, 0x2489b890, 0x90bc0007, 0x079489e8, 0xbc030f00, 0xeebc099f, 0x909ebc90, 0x90039992, 0xf9bb01bf, 0x07a48904, 0x099fbc00, 0x000b348d, 0x000b248c, - 0xf403f6b0, 0xdebc0d0d, 0x09cbbc09, 0x0050ba3e, 0xd9bc0109, 0xbc020909, 0x448f09c9, 0xf0bc000b, + 0xf403f6b0, 0xdebc0d0d, 0x09cbbc09, 0x00509a3e, 0xd9bc0109, 0xbc020909, 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0x90330099, 0xf4bd0a03, 0x0057db3e, 0x890fffc7, 0xbc017650, + 0xfa0195f0, 0x8f3e01e9, 0x01090057, 0x89a9d93c, 0x8f017600, 0xbcfe8a00, 0x00d95059, 0xff008000, + 0x5fbc9559, 0x009fce50, 0xce080449, 0x90330099, 0xf4bd0a03, 0x0057bb3e, 0x890fffc7, 0xbc017650, 0x74895059, 0x9f3c0038, 0x0000d949, 0xb08f0080, 0x59fffe89, 0x505fbce5, 0x8d00e9ce, 0xc4000ba8, - 0x1bf4019f, 0x49df3c10, 0xfa0195f0, 0x173e01e9, 0x01090058, 0xb249d93c, 0x18e57e4a, 0x01a43300, - 0x064ab219, 0x18be7e16, 0x00a93300, 0x4ab202a9, 0xb57eb4bd, 0x0cd90018, 0xce008020, 0xdc8f0099, + 0x1bf4019f, 0x49df3c10, 0xfa0195f0, 0xf73e01e9, 0x01090057, 0xb249d93c, 0x18c77e4a, 0x01a43300, + 0x064ab219, 0x18a07e16, 0x00a93300, 0x4ab202a9, 0x977eb4bd, 0x0cd90018, 0xce008020, 0xdc8f0099, 0x9e95000b, 0x1a9dc70c, 0xc749febc, 0xfc89769f, 0x9fbc000b, 0x0bec8949, 0x499dbc00, 0x000c0c8e, - 0x1600d4b3, 0x8e49ed3c, 0xb3000c10, 0x3c1400f0, 0x843e49ed, 0x943d0058, 0x000c108f, 0x0949f93c, - 0x49e93c01, 0x010b4ab2, 0x0032ac7e, 0xadb3a6b2, 0x89024400, 0xbc017380, 0x00d95059, 0xff008000, - 0x8089f559, 0x59bcfe8c, 0xce94bd50, 0x999000fe, 0x3294b301, 0xbd4ab2fa, 0x32ac7eb4, 0xb3a6b200, + 0x1600d4b3, 0x8e49ed3c, 0xb3000c10, 0x3c1400f0, 0x643e49ed, 0x943d0058, 0x000c108f, 0x0949f93c, + 0x49e93c01, 0x010b4ab2, 0x00328c7e, 0xadb3a6b2, 0x89024400, 0xbc017380, 0x00d95059, 0xff008000, + 0x8089f559, 0x59bcfe8c, 0xce94bd50, 0x999000fe, 0x3294b301, 0xbd4ab2fa, 0x328c7eb4, 0xb3a6b200, 0x021300ad, 0x0174a88f, 0xdf505fbc, 0x00800000, 0xcef55fff, 0x95f100f9, 0xf9fa0100, 0x89f48f01, 0x6455b8fe, 0x00d90001, 0xff008000, 0x5fbc9559, 0x0099ce50, 0x0003ec8b, 0x008fbdbf, 0x9cc70004, 0x49f9bce8, 0x8f039ec4, 0xc70004c0, 0xfebc2499, 0x04d08f49, 0x49f9bc00, 0x0004e089, 0xd9499cbc, 0xdeadbeef, 0x1bf4d9a6, 0x89bca005, 0xbf0003ec, 0xbeefd99f, 0xf9a6dead, 0x89190bf4, 0xbc0004e0, - 0x9fa69894, 0xb20d0bf4, 0x0c180b4a, 0x59eb3e0f, 0x76188900, 0x0000d701, 0x59bc0080, 0xf557ff50, + 0x9fa69894, 0xb20d0bf4, 0x0c180b4a, 0x59cb3e0f, 0x76188900, 0x0000d701, 0x59bc0080, 0xf557ff50, 0x8900ffce, 0x900003f0, 0x9fbc6855, 0xe557ff49, 0xfe898089, 0xce5059bc, 0x208900ee, 0x9ebc0004, 0x04f08949, 0x01fdc400, 0x89499dbc, 0xc7000500, 0x9cbc21fc, 0x05108949, 0x26fbc700, 0x89499bbc, 0xc7000520, 0x9a3c03fa, 0x05248949, 0x48f0c700, 0x894990bc, 0xc7000534, 0x91bcebf1, 0x05448949, - 0x93f2c700, 0x894992bc, 0x95000554, 0xffc71cf3, 0x499fbc78, 0x00056489, 0x93bc4ab2, 0x32f67e49, - 0xb3acb200, 0xb21200a0, 0x7e180b4a, 0x06000261, 0x5ad23e1f, 0x7e4ab200, 0xb200334c, 0x00a4b3ac, - 0x7e4ab2ea, 0xb20033c9, 0x00a4b3ac, 0x7e4ab2de, 0xb2003416, 0x00a4b3ac, 0x7e4ab2d2, 0xb2003885, - 0x38be7e4a, 0x7e4ab200, 0xb2003923, 0x39597e4a, 0x7e4ab200, 0xb200343f, 0x00a4b3ac, 0x7e4ab2ae, - 0xb2003467, 0x00a4b3ac, 0x0a9489a2, 0xc894bc00, 0x000a8489, 0x0bd894bc, 0x7e4ab223, 0xb2000494, - 0x348e7e4a, 0xb3acb200, 0xb28000a4, 0x34b67e4a, 0xb3acb200, 0xff7400ad, 0x000aa489, 0xbdd894bc, - 0xb2240bc4, 0x04947e4a, 0x7e4ab200, 0xb20056df, 0x00adb3ac, 0x248fff56, 0x5fbc0176, 0x9557ff50, - 0x8f0099ce, 0xbc000bcc, 0x94f049f9, 0x1f0bf401, 0x0003c089, 0x3308943c, 0xb2150104, 0x18e57e4a, - 0x00a43300, 0x03e8890b, 0x49903c00, 0x617e4ab2, 0x6ab20056, 0xdb8f71fb, 0x440902e7, 0xf8009ffa, + 0x93f2c700, 0x894992bc, 0x95000554, 0xffc71cf3, 0x499fbc78, 0x00056489, 0x93bc4ab2, 0x32d67e49, + 0xb3acb200, 0xb21200a0, 0x7e180b4a, 0x06000261, 0x5ab23e1f, 0x7e4ab200, 0xb200332c, 0x00a4b3ac, + 0x7e4ab2ea, 0xb20033a9, 0x00a4b3ac, 0x7e4ab2de, 0xb20033f6, 0x00a4b3ac, 0x7e4ab2d2, 0xb2003865, + 0x389e7e4a, 0x7e4ab200, 0xb2003903, 0x39397e4a, 0x7e4ab200, 0xb200341f, 0x00a4b3ac, 0x7e4ab2ae, + 0xb2003447, 0x00a4b3ac, 0x0a9489a2, 0xc894bc00, 0x000a8489, 0x0bd894bc, 0x7e4ab223, 0xb2000494, + 0x346e7e4a, 0xb3acb200, 0xb28000a4, 0x34967e4a, 0xb3acb200, 0xff7400ad, 0x000aa489, 0xbdd894bc, + 0xb2240bc4, 0x04947e4a, 0x7e4ab200, 0xb20056bf, 0x00adb3ac, 0x248fff56, 0x5fbc0176, 0x9557ff50, + 0x8f0099ce, 0xbc000bcc, 0x94f049f9, 0x1f0bf401, 0x0003c089, 0x3308943c, 0xb2150104, 0x18c77e4a, + 0x00a43300, 0x03e8890b, 0x49903c00, 0x417e4ab2, 0x6ab20056, 0xdb8f71fb, 0x440902e7, 0xf8009ffa, 0x02b5b600, 0x0c02a0b3, 0x1803a0b3, 0x00f8a4bd, 0x09f0bbbc, 0xf0fbbc40, 0xc4079fbb, 0x00f8079a, 0x89f0bbbc, 0xbc492492, 0x9fbbf0fb, 0x079ac407, 0xa99400f8, 0xb6e4bd07, 0xd4bd04a4, 0x3ea0a9bc, - 0xa0005b36, 0x01ff909d, 0xb3049990, 0x90f809f4, 0xe0b301ee, 0xef941d04, 0x02e99405, 0x8f909fbc, - 0xbc000c14, 0x9fbc909a, 0x3ef4bd90, 0xf8005b23, 0x9452f900, 0xa99404af, 0xbda3b207, 0x40f9bc24, - 0x001ffc85, 0x005b893e, 0x3ab20b7f, 0x00902cb2, 0x00b3f006, 0x0012f97e, 0x11901aa0, 0xf405a604, + 0xa0005b16, 0x01ff909d, 0xb3049990, 0x90f809f4, 0xe0b301ee, 0xef941d04, 0x02e99405, 0x8f909fbc, + 0xbc000c14, 0x9fbc909a, 0x3ef4bd90, 0xf8005b03, 0x9452f900, 0xa99404af, 0xbda3b207, 0x40f9bc24, + 0x001ffc85, 0x005b693e, 0x3ab20b7f, 0x00902cb2, 0x00b3f006, 0x0012f97e, 0x11901aa0, 0xf405a604, 0x2290e91b, 0x0420b301, 0x0229941f, 0xbc052f94, 0xc680909f, 0x94bc001f, 0x0c148910, 0x1019bc00, - 0x005b683e, 0x62f951fb, 0x9404af94, 0xa4b207a9, 0xf9bc14bd, 0x1ffe8650, 0x5bfd3e00, 0xb2207f00, + 0x005b483e, 0x62f951fb, 0x9404af94, 0xa4b207a9, 0xf9bc14bd, 0x1ffe8650, 0x5bdd3e00, 0xb2207f00, 0xe44ab21c, 0x7effff0b, 0x580012f9, 0x3cbf0129, 0xe4062290, 0xf0ffff0b, 0x9cff0093, 0x0099b9c4, 0x9004a9fd, 0xacff0433, 0xb21db2c5, 0x13357e4a, 0xf426a600, 0x1190ca1b, 0x0410b301, 0x0219941f, - 0xbc051f94, 0xc882909f, 0x95bc001f, 0x0c148930, 0x3039bc00, 0x005bbd3e, 0x82f961fb, 0xc464bfc7, + 0xbc051f94, 0xc882909f, 0x95bc001f, 0x0c148930, 0x3039bc00, 0x005b9d3e, 0x82f961fb, 0xc464bfc7, 0xb9c70fb2, 0xc7a1b232, 0xf79474b8, 0x0496940c, 0x9404f594, 0x04bd0824, 0xb248b3c7, 0x02294b0c, 0xf97e1ab2, 0xf8090012, 0x09c4a9ff, 0x4b0db2cf, 0x1ab20229, 0xfdc53cff, 0xc6fd04c9, 0x13357e05, 0x4b0cb200, 0x1ab2022a, 0x0012f97e, 0xa9fff009, 0xff0f49c4, 0xfdc52cff, 0xff4904c9, 0xc55cfff0, 0x8904c9fd, 0xb2ff0fff, 0x022a4b0d, 0xc4fd1ab2, 0x04c9fd05, 0x7e05c7fd, 0xb2001335, 0x022b4b0c, 0xf97e1ab2, 0xf0090012, 0xa9ff0db2, 0x010090c4, 0xb2c58cff, 0x022b4b1a, 0x0013357e, 0x7f040db3, - 0xf981fbff, 0xb3a2b242, 0xb31304b0, 0x0a5d07b0, 0x00bdb323, 0x013e020e, 0x5680005d, 0x1e81001d, - 0x0b7f001e, 0xb2010c58, 0x0400902a, 0xf000b3f0, 0x040d00c3, 0x0013357e, 0x1bf401a6, 0x5d4b3ee8, + 0xf981fbff, 0xb3a2b242, 0xb31304b0, 0x0a5d07b0, 0x00bdb323, 0xe13e020e, 0x5680005c, 0x1e81001d, + 0x0b7f001e, 0xb2010c58, 0x0400902a, 0xf000b3f0, 0x040d00c3, 0x0013357e, 0x1bf401a6, 0x5d2b3ee8, 0x1c5a8000, 0x1d568100, 0x580b7f00, 0x2ab2010c, 0xf0040090, 0xc3f000b3, 0x7e040d00, 0xa6001335, - 0xe81bf401, 0x005d4b3e, 0x001e1e80, 0x001eea81, 0x0c580b7f, 0x902ab201, 0xb3f00400, 0x00c3f000, + 0xe81bf401, 0x005d2b3e, 0x001e1e80, 0x001eea81, 0x0c580b7f, 0x902ab201, 0xb3f00400, 0x00c3f000, 0x357e040d, 0x01a60013, 0x89e81bf4, 0x3c002784, 0x94339892, 0x04bd2901, 0x0cb2fe01, 0x2ab2130b, - 0x0012f97e, 0xa1ff0db2, 0x010090c4, 0xb201c5f0, 0x7e130b2a, 0xb3001335, 0xb2e30404, 0x3b1b7e2a, + 0x0012f97e, 0xa1ff0db2, 0x010090c4, 0xb201c5f0, 0x7e130b2a, 0xb3001335, 0xb2e30404, 0x3afb7e2a, 0x01a43300, 0xbd240b62, 0x7e2ab2c4, 0x000012f9, 0xffd4bdcf, 0x240bc4a0, 0x357e2ab2, 0x240b0013, 0x2ab2010c, 0x0012f97e, 0xa0ff010d, 0xb2240bc4, 0x13357e2a, 0x0c240b00, 0x7e2ab202, 0x0d0012f9, 0xc4a0ff02, 0x2ab2240b, 0x0013357e, 0x030c240b, 0xf97e2ab2, 0x240b0012, 0x0dc4a0ff, 0x7e2ab203, - 0xb2001335, 0x3ae27e2a, 0x03a4b300, 0x4b2ab212, 0xcb4c00b9, 0x7e040d00, 0x89001335, 0x3c000300, + 0xb2001335, 0x3ac27e2a, 0x03a4b300, 0x4b2ab212, 0xcb4c00b9, 0x7e040d00, 0x89001335, 0x3c000300, 0x94339892, 0xb4837701, 0x347f001f, 0x1cb214bd, 0xffff4be4, 0xf97e2ab2, 0x3c580012, 0x013f5802, 0x4be41db2, 0xc9e4ffff, 0x99b9ffff, 0x04a9fd00, 0xf004cffd, 0xacff00c3, 0x7e2ab2c5, 0x58001335, 0x1cb20330, 0x0be42ab2, 0xf97effff, 0x39580012, 0x043c5805, 0x0be41db2, 0x1190ffff, 0xc49cff01, @@ -793,62 +792,62 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0x7e02644b, 0xb3001335, 0x89e10404, 0x3c000308, 0x94339892, 0x04bd2b01, 0x0cb2ce01, 0xb202644b, 0x12f97e2a, 0xff0db200, 0x0090c4a1, 0x11c5f001, 0x644b2ab2, 0x13357e02, 0x0404b300, 0xfba4bde1, 0xb232f941, 0x0ab3b2a2, 0x01d9b331, 0xc99400da, 0x90e9bc08, 0x040196b1, 0xb1140cf4, 0xf4040096, - 0x96b05e18, 0x0c0cf401, 0x005f3a3e, 0x07039ab3, 0x3e230a0b, 0x80005fc3, 0x81001ba0, 0x7f001bf4, - 0x010b580a, 0xf0040090, 0xb3f000a3, 0x13677e00, 0xf401a600, 0x7c3eec1b, 0xa880005f, 0xfc81001a, - 0x0a7f001a, 0x90010b58, 0xa3f00400, 0x00b3f000, 0x0013677e, 0x1bf401a6, 0x5f7c3eec, 0x1afc8000, + 0x96b05e18, 0x0c0cf401, 0x005f1a3e, 0x07039ab3, 0x3e230a0b, 0x80005fa3, 0x81001ba0, 0x7f001bf4, + 0x010b580a, 0xf0040090, 0xb3f000a3, 0x13677e00, 0xf401a600, 0x5c3eec1b, 0xa880005f, 0xfc81001a, + 0x0a7f001a, 0x90010b58, 0xa3f00400, 0x00b3f000, 0x0013677e, 0x1bf401a6, 0x5f5c3eec, 0x1afc8000, 0x1b508100, 0x580a7f00, 0x0090010b, 0x00a3f004, 0x7e00b3f0, 0xa6001367, 0xec1bf401, 0x4a05b0b4, - 0xb4f000f7, 0x10b5f007, 0x0013677e, 0x3bb22ab2, 0x005ae17e, 0x1b01a0b3, 0x2902a4b3, 0x867e090a, - 0x3f490013, 0xb4a9ffff, 0x3e80b5f0, 0x0a005fbb, 0x13867e09, 0xff3f4900, 0x0ab4a9ff, 0x13677e09, + 0xb4f000f7, 0x10b5f007, 0x0013677e, 0x3bb22ab2, 0x005ac17e, 0x1b01a0b3, 0x2902a4b3, 0x867e090a, + 0x3f490013, 0xb4a9ffff, 0x3e80b5f0, 0x0a005f9b, 0x13867e09, 0xff3f4900, 0x0ab4a9ff, 0x13677e09, 0xfba4bd00, 0xf0bca631, 0xbabc0b9c, 0x1f94b6b0, 0xf8a59bff, 0xb0babc00, 0xcba6cab2, 0xb2050df4, 0xf900f8ba, 0x008c8952, 0x0000d001, 0xa5940080, 0xbca4b20f, 0x50ff5059, 0x00bbceb5, 0x000e5481, - 0xf1a81abc, 0x4c03ffb4, 0x55b803ff, 0x7e001ff0, 0xff005fc5, 0x1abcb550, 0x00bbce49, 0x000e6481, - 0xdca814bc, 0x7fffffff, 0xb804bcfd, 0x00020c55, 0x005fc57e, 0xbcb550ff, 0xbbce491a, 0x0e748100, - 0xa814bc00, 0x8c10b5b6, 0xb800ffff, 0x00100055, 0x005fc57e, 0xbcb550ff, 0xbbce491a, 0x0e848100, - 0xa814bc00, 0x8c00b3f0, 0x9000ffff, 0xc57e0455, 0x50ff005f, 0xcd748905, 0x491abcfe, 0xce5059bc, + 0xf1a81abc, 0x4c03ffb4, 0x55b803ff, 0x7e001ff0, 0xff005fa5, 0x1abcb550, 0x00bbce49, 0x000e6481, + 0xdca814bc, 0x7fffffff, 0xb804bcfd, 0x00020c55, 0x005fa57e, 0xbcb550ff, 0xbbce491a, 0x0e748100, + 0xa814bc00, 0x8c10b5b6, 0xb800ffff, 0x00100055, 0x005fa57e, 0xbcb550ff, 0xbbce491a, 0x0e848100, + 0xa814bc00, 0x8c00b3f0, 0x9000ffff, 0xa57e0455, 0x50ff005f, 0xcd748905, 0x491abcfe, 0xce5059bc, 0x9489000d, 0x94bc000e, 0xe8d9c7f8, 0xb1e09fbc, 0xf400fee6, 0xff4e060d, 0x0ea48900, 0xf894bc00, 0x000e9489, 0xc7499ebc, 0x9fbcf0d9, 0xfee6b1e0, 0x060df400, 0x8900ff4e, 0xbc000eb4, 0xa489f894, 0x9ebc000e, 0x18d99549, 0xb1e09fbc, 0xf400fee6, 0xff4e060d, 0x0ec48900, 0xf894bc00, 0x000eb489, 0xc4499ebc, 0x9fbcffd9, 0xfef6b1f0, 0x060df400, 0x8900ff4f, 0xd3013294, 0x00800000, 0x895059bc, 0xff000ec4, 0x9fbcb553, 0x00bbce49, 0x000ed480, 0xf0a804bc, 0xff8c00b3, 0x55b800ff, 0x7e000104, - 0xff005fc5, 0x0abcb553, 0x00bbce49, 0x000ee481, 0xd0a814bc, 0x00ffffff, 0xb204b0fd, 0x5fc57e0c, - 0x04559000, 0xff491abc, 0xbbceb553, 0x0ef48100, 0xa814bc00, 0xb204b0fd, 0x0455900c, 0x005fc57e, - 0xbcb553ff, 0xbbce491a, 0x0f048100, 0xa814bc00, 0xb204b0fd, 0x0455900c, 0x005fc57e, 0xbcb553ff, - 0xbbce491a, 0x0f148100, 0xa814bc00, 0xb204b0fd, 0x9055b80c, 0xc57e0203, 0x53ff005f, 0x491abcb5, - 0x8000bbce, 0xbc000f24, 0xbbc7a804, 0x7c55b8e8, 0xff4c022e, 0x5fc57e00, 0x490abc00, 0xce0553ff, - 0x34810000, 0x14bc000f, 0x100b95a8, 0x00ffff8c, 0x000f4482, 0x005fc57e, 0xbc491abc, 0x0be4a824, - 0xff8cffff, 0x559000ff, 0x5fc57e04, 0xb553ff00, 0xce492abc, 0x548000bb, 0x04bc000f, 0x00b3f0a8, - 0x8c045590, 0x7e00ffff, 0xbc005fc5, 0x53ff490a, 0x0000ce05, 0x000f6481, 0x95a814bc, 0xff4c180b, - 0x0f748200, 0x5fc57e00, 0x491abc00, 0xc4a824bc, 0xff4cff0b, 0x0f848100, 0x5fc57e00, 0x492abc00, - 0xc7a814bc, 0xff4ce80b, 0x0f948200, 0x5fc57e00, 0x491abc00, 0xc7a824bc, 0x5590f00b, 0x00ff4c04, - 0x7e0553ff, 0xbc005fc5, 0x00ce492a, 0x0fa48100, 0xa814bc00, 0x8c100b95, 0x8200ffff, 0x7e000fb4, - 0xbc005fc5, 0x24bc491a, 0xff0be4a8, 0xffff8cff, 0x04509000, 0x005fc57e, 0xbc0503fd, 0x00ce492a, - 0x0fc48100, 0xa814bc00, 0x4ce80bc7, 0xd48200ff, 0xc57e000f, 0x1abc005f, 0xa824bc49, 0x4cff0bc4, - 0xe48300ff, 0xc57e000f, 0x2abc005f, 0xa834bc49, 0x4cf00bc7, 0xf48100ff, 0xc57e000f, 0x3abc005f, - 0xa814bc49, 0x4c180b95, 0xc57e00ff, 0x1abc005f, 0x8f51fb49, 0xdb010050, 0x00800000, 0xbc0fa994, + 0xff005fa5, 0x0abcb553, 0x00bbce49, 0x000ee481, 0xd0a814bc, 0x00ffffff, 0xb204b0fd, 0x5fa57e0c, + 0x04559000, 0xff491abc, 0xbbceb553, 0x0ef48100, 0xa814bc00, 0xb204b0fd, 0x0455900c, 0x005fa57e, + 0xbcb553ff, 0xbbce491a, 0x0f048100, 0xa814bc00, 0xb204b0fd, 0x0455900c, 0x005fa57e, 0xbcb553ff, + 0xbbce491a, 0x0f148100, 0xa814bc00, 0xb204b0fd, 0x9055b80c, 0xa57e0203, 0x53ff005f, 0x491abcb5, + 0x8000bbce, 0xbc000f24, 0xbbc7a804, 0x7c55b8e8, 0xff4c022e, 0x5fa57e00, 0x490abc00, 0xce0553ff, + 0x34810000, 0x14bc000f, 0x100b95a8, 0x00ffff8c, 0x000f4482, 0x005fa57e, 0xbc491abc, 0x0be4a824, + 0xff8cffff, 0x559000ff, 0x5fa57e04, 0xb553ff00, 0xce492abc, 0x548000bb, 0x04bc000f, 0x00b3f0a8, + 0x8c045590, 0x7e00ffff, 0xbc005fa5, 0x53ff490a, 0x0000ce05, 0x000f6481, 0x95a814bc, 0xff4c180b, + 0x0f748200, 0x5fa57e00, 0x491abc00, 0xc4a824bc, 0xff4cff0b, 0x0f848100, 0x5fa57e00, 0x492abc00, + 0xc7a814bc, 0xff4ce80b, 0x0f948200, 0x5fa57e00, 0x491abc00, 0xc7a824bc, 0x5590f00b, 0x00ff4c04, + 0x7e0553ff, 0xbc005fa5, 0x00ce492a, 0x0fa48100, 0xa814bc00, 0x8c100b95, 0x8200ffff, 0x7e000fb4, + 0xbc005fa5, 0x24bc491a, 0xff0be4a8, 0xffff8cff, 0x04509000, 0x005fa57e, 0xbc0503fd, 0x00ce492a, + 0x0fc48100, 0xa814bc00, 0x4ce80bc7, 0xd48200ff, 0xa57e000f, 0x1abc005f, 0xa824bc49, 0x4cff0bc4, + 0xe48300ff, 0xa57e000f, 0x2abc005f, 0xa834bc49, 0x4cf00bc7, 0xf48100ff, 0xa57e000f, 0x3abc005f, + 0xa814bc49, 0x4c180b95, 0xa57e00ff, 0x1abc005f, 0x8f51fb49, 0xdb010050, 0x00800000, 0xbc0fa994, 0x9bff909f, 0x00ffcef5, 0x0010048c, 0xb8d8cabc, 0x001fd899, 0xfde59bff, 0xcfbc05fd, 0x00eecea9, 0x0010148d, 0xb8f8dabc, 0x00100099, 0xfd059bfd, 0xdebc05ef, 0x0099cea9, 0x0010248e, 0xfdf8eabc, 0xe9bc059f, 0x8f00f8a9, 0x94013068, 0x9fbc0fa9, 0x0000df90, 0x9ffd0080, 0x009ece05, 0x0010348d, 0xc4f8dabc, 0x9fa63fe9, 0xb20518f4, 0x10448cf9, 0xf8cabc00, 0xc7a9d9bc, 0x9fa6a8e9, 0xb20518f4, 0x10548bf9, 0xf8babc00, 0xc7a9c9bc, 0x9fa6b0e9, 0xb20518f4, 0x10648df9, 0xf8dabc00, 0xc7a9b9bc, 0x9fa6b8e9, 0xb20518f4, 0xa9d9bcf9, 0x408f00f8, 0x00d90130, 0x94008000, 0xefbc0fae, 0xf5e9ffe0, - 0x9200fcce, 0xe9ff18ee, 0xcfd889b5, 0xe0e9bcfe, 0xc400bdce, 0x0bf402d9, 0x68cfc70a, 0x0063e73e, - 0x00107489, 0x89f89abc, 0xbc001074, 0xd9c4a99f, 0x0a0bf420, 0x3e78cfc7, 0x89006402, 0xbc001084, - 0x8489f89a, 0x9fbc0010, 0x10d9c4a9, 0xc70a0bf4, 0x1d3e70cf, 0x94890064, 0x9abc0010, 0x304489f8, + 0x9200fcce, 0xe9ff18ee, 0xcfd889b5, 0xe0e9bcfe, 0xc400bdce, 0x0bf402d9, 0x68cfc70a, 0x0063c73e, + 0x00107489, 0x89f89abc, 0xbc001074, 0xd9c4a99f, 0x0a0bf420, 0x3e78cfc7, 0x890063e2, 0xbc001084, + 0x8489f89a, 0x9fbc0010, 0x10d9c4a9, 0xc70a0bf4, 0xfd3e70cf, 0x94890063, 0x9abc0010, 0x304489f8, 0xe0e9bc01, 0x00109489, 0xd9a99fbc, 0x00800000, 0xce95e9ff, 0xbdce009f, 0x80d9c400, 0x0b009033, - 0x3e70fec7, 0x8900644e, 0xbc0010a4, 0xa489e89a, 0x9ebc0010, 0x40d9c4a9, 0xc70a0bf4, 0x693e78ff, - 0xb4890064, 0x9abc0010, 0x10b489f8, 0xa99fbc00, 0x12f900f8, 0xb2015c4b, 0x76ce7ea0, 0x11048900, + 0x3e70fec7, 0x8900642e, 0xbc0010a4, 0xa489e89a, 0x9ebc0010, 0x40d9c4a9, 0xc70a0bf4, 0x493e78ff, + 0xb4890064, 0x9abc0010, 0x10b489f8, 0xa99fbc00, 0x12f900f8, 0xb2015c4b, 0x76ba7ea0, 0x11048900, 0x0f0d9400, 0x8fa0a9bc, 0x89001674, 0xd1010000, 0x00800000, 0x8be0d9bc, 0xbf0017d0, 0x0000dcf9, 0xe9bc0080, 0x0591fd90, 0xa00099ce, 0x04ff90a9, 0xa604aa90, 0xe61bf4fb, 0x01300089, 0xffd0d9bc, 0x99ce95dc, 0x10c48f00, 0x30ddb800, 0xf9bc0002, 0x95dcff09, 0x8f0099ce, 0x900010d4, 0xf9bc50dd, 0xe5dcff09, 0x8f00eece, 0xb80010e4, 0x0230f0d9, 0xfd09febc, 0x99ce059c, 0x10f48f00, 0x09f9bc00, - 0x12f911fb, 0xb2015c4b, 0x76ce7ea0, 0x11048900, 0x0f0c9400, 0x8ea0a9bc, 0x89001674, 0xd1010000, + 0x12f911fb, 0xb2015c4b, 0x76ba7ea0, 0x11048900, 0x0f0c9400, 0x8ea0a9bc, 0x89001674, 0xd1010000, 0x00800000, 0x8bd0c9bc, 0xbf0017ac, 0xbcafbfe9, 0x91fd90d9, 0x019ffa05, 0x9004ee90, 0xeba604aa, 0x89eb1bf4, 0xdd013000, 0x00800000, 0xffc0c9bc, 0xdeced5cd, 0x10c48900, 0xf890bc00, 0x000000d9, 0x04e9fd42, 0xffffffd9, 0x04f9fdbd, 0xfa05effd, 0x00dd01de, 0xb8008000, 0x000230cc, 0xced5cdff, 0xd48900de, 0x90bc0010, 0xffff89f8, 0x04e9fde4, 0x1b000089, 0xfd04f9fd, 0xdefa05ef, 0x0000dd01, 0xcc900080, 0xd5cdff50, 0x8900dece, 0xbc0010e4, 0xf00f9890, 0xfd0fe4f0, 0xe9fd049f, 0x01defa05, 0x800000d9, 0xf0cdb800, 0xd9fd0230, 0x00dece05, 0x0010f489, 0xd9f890bc, 0x0fffffff, 0xd904e9fd, - 0xf0000000, 0xfd04f9fd, 0xdefa05ef, 0x8911fb01, 0xf9010000, 0x015c4b02, 0xbc0fa094, 0xce7e0009, + 0xf0000000, 0xfd04f9fd, 0xdefa05ef, 0x8911fb01, 0xf9010000, 0x015c4b02, 0xbc0fa094, 0xba7e0009, 0x3c890076, 0xac8e0012, 0xa9bc0017, 0x0000dca0, 0xd08d0080, 0xe9bf0017, 0x09bcafbf, 0x059cfd90, 0x90019ffa, 0xaa9004ee, 0xf4eda604, 0x01fbeb1b, 0x000e548e, 0xe9bc94bd, 0x0e648ea9, 0xa9e9bc00, 0x000e748e, 0x8ea9e9bc, 0xbc000e84, 0x948ea9e9, 0xe9bc000e, 0x0ea48ea9, 0xa9e9bc00, 0x000eb48e, @@ -860,131 +859,132 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0xa9e9bc00, 0x0010348e, 0x8ea9e9bc, 0xbc001044, 0x548ea9e9, 0xe9bc0010, 0x10648ea9, 0xa9e9bc00, 0x0010748e, 0x8ea9e9bc, 0xbc001084, 0x948ea9e9, 0xe9bc0010, 0x10a48ea9, 0xa9e9bc00, 0x0010b48e, 0x8ea9e9bc, 0xbc0010c4, 0xd48ea9e9, 0xe9bc0010, 0x10e48ea9, 0xa9e9bc00, 0x0010f48e, 0xbc015c4b, - 0xce7ea9e9, 0x04890076, 0xf4bd0011, 0xbda0a9bc, 0x90afa094, 0xaa900199, 0x5794b304, 0xb600f8f8, + 0xba7ea9e9, 0x04890076, 0xf4bd0011, 0xbda0a9bc, 0x90afa094, 0xaa900199, 0x5794b304, 0xb600f8f8, + 0xf88c0fa4, 0x288b0023, 0xcfbf0024, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, 0xf9fa059d, + 0x0ccc9001, 0x1bf4cba6, 0x8f00f8e4, 0xbf0021b8, 0x0fa4b6fe, 0xcee0aebc, 0xfd9800e9, 0x02ff9801, + 0xfd049ffd, 0xe9fa059d, 0x21b88f01, 0x03f99800, 0xcea0a9bc, 0xfe9800a9, 0x05ff9804, 0xfd049ffd, + 0xa9fa059e, 0x8f00f801, 0xbf002104, 0x0fa4b6fe, 0xcee0aebc, 0xfd9800e9, 0x02ff9801, 0xfd049ffd, + 0xe9fa059d, 0x21048f01, 0x03f99800, 0xcea0a9bc, 0xfe9800a9, 0x05ff9804, 0xfd049ffd, 0xa9fa059e, + 0xd900f801, 0x00816128, 0xbc0fa4b6, 0xa9cea0a9, 0xf0004f00, 0xf0049ffd, 0xa9fa6495, 0xb600f801, 0x348c0fa4, 0xb88b0021, 0xcfbf0021, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, 0xf9fa059d, - 0x0ccc9001, 0x1bf4cba6, 0x8f00f8e4, 0xbf0021d0, 0x00d9cefd, 0x9801fe98, 0x9ffd02ff, 0x059efd04, - 0x8f01d9fa, 0x980021d0, 0xd9ce03fd, 0x04fe9800, 0xfd05ff98, 0x9efd049f, 0x01d9fa05, 0x0021d08f, - 0xce06fd98, 0xfe9800d9, 0x08ff9807, 0xfd049ffd, 0xd9fa059e, 0x21f48c01, 0x0fa4b600, 0x0023688b, - 0xafbccfbf, 0x00f9cef0, 0x9802ce98, 0x9efd01cd, 0x059dfd04, 0x9001f9fa, 0xcba60ccc, 0xf8e41bf4, - 0x3814de00, 0xe9ce0080, 0xffffdf00, 0x9ffd00ff, 0x0000df04, 0x9ffd0600, 0x01e9fa05, 0xa4b600f8, - 0x23f88c0f, 0x24288b00, 0xbccfbf00, 0xf9cef0af, 0x02ce9800, 0xfd01cd98, 0x9dfd049e, 0x01f9fa05, - 0xa60ccc90, 0xe41bf4cb, 0x88d900f8, 0xce008020, 0x004e009f, 0x04fefdff, 0xfa59f5f0, 0x00f8019f, - 0x816128d9, 0x0fa4b600, 0xcea0a9bc, 0x004f00a9, 0x049ffdf0, 0xfa6495f0, 0x00f801a9, 0x8c0fa4b6, - 0x8b002434, 0xbf002464, 0xf0afbccf, 0x9800f9ce, 0xcd9802ce, 0x049efd01, 0xfa059dfd, 0xcc9001f9, - 0xf4cba60c, 0x00f8e41b, 0x0024648f, 0xa4b6febf, 0xe0aebc0f, 0x9800e9ce, 0xff9801fd, 0x049ffd02, - 0xfa059dfd, 0x648f01e9, 0xf9980024, 0xa0a9bc03, 0x9800a9ce, 0xff9804fe, 0x049ffd05, 0xfa059efd, - 0x00f801a9, 0x8c0fa4b6, 0x8b002368, 0xbf0023e0, 0xf0afbccf, 0x9800f9ce, 0xcd9802ce, 0x049efd01, - 0xfa059dfd, 0xcc9001f9, 0xf4cba60c, 0x00f8e41b, 0x812828d9, 0x0fa4b600, 0xcea0a9bc, 0xff8f00a9, - 0x9ffdff00, 0x0095f104, 0x01a9fa68, 0x048f00f8, 0xfebf0021, 0xbc0fa4b6, 0xe9cee0ae, 0x01fd9800, - 0xfd02ff98, 0x9dfd049f, 0x01e9fa05, 0x0021048f, 0xbc03f998, 0xa9cea0a9, 0x04fe9800, 0xfd05ff98, - 0x9efd049f, 0x01a9fa05, 0x28d900f8, 0xb6008161, 0xa9bc0fa4, 0x00a9cea0, 0xfdf0004f, 0x95f0049f, - 0x01a9fa6c, 0xb88f00f8, 0xfebf0021, 0xbc0fa4b6, 0xe9cee0ae, 0x01fd9800, 0xfd02ff98, 0x9dfd049f, - 0x01e9fa05, 0x0021b88f, 0xbc03f998, 0xa9cea0a9, 0x04fe9800, 0xfd05ff98, 0x9efd049f, 0x01a9fa05, - 0x8cd900f8, 0xb600816a, 0xa9bc0fa4, 0x00a9cea0, 0xf8ffff8f, 0x8f049ffd, 0xfd070000, 0xa9fa059f, - 0xb600f801, 0xfc8c0fa4, 0x048b001f, 0xcfbf0021, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, + 0x0ccc9001, 0x1bf4cba6, 0xd900f8e4, 0x00816a8c, 0xbc0fa4b6, 0xa9cea0a9, 0xffff8f00, 0x049ffdf8, + 0x0700008f, 0xfa059ffd, 0x00f801a9, 0x812828d9, 0x0fa4b600, 0xcea0a9bc, 0xff8f00a9, 0x9ffdff00, + 0x0095f104, 0x01a9fa68, 0xa4b600f8, 0x23688c0f, 0x23e08b00, 0xbccfbf00, 0xf9cef0af, 0x02ce9800, + 0xfd01cd98, 0x9dfd049e, 0x01f9fa05, 0xa60ccc90, 0xe41bf4cb, 0xd08f00f8, 0xfdbf0021, 0x9800d9ce, + 0xff9801fe, 0x049ffd02, 0xfa059efd, 0xd08f01d9, 0xfd980021, 0x00d9ce03, 0x9804fe98, 0x9ffd05ff, + 0x059efd04, 0x8f01d9fa, 0x980021d0, 0xd9ce06fd, 0x07fe9800, 0xfd08ff98, 0x9efd049f, 0x01d9fa05, + 0x0021f48c, 0x8b0fa4b6, 0xbf002368, 0xf0afbccf, 0x9800f9ce, 0xcd9802ce, 0x049efd01, 0xfa059dfd, + 0xcc9001f9, 0xf4cba60c, 0x00f8e41b, 0x816128d9, 0x0fa4b600, 0xcea0a9bc, 0x004f00a9, 0x049ffdf0, + 0xfa6c95f0, 0x00f801a9, 0x803814de, 0x00e9ce00, 0xffffffdf, 0x049ffd00, 0x000000df, 0x059ffd06, + 0xf801e9fa, 0x24648f00, 0xb6febf00, 0xaebc0fa4, 0x00e9cee0, 0x9801fd98, 0x9ffd02ff, 0x059dfd04, + 0x8f01e9fa, 0x98002464, 0xa9bc03f9, 0x00a9cea0, 0x9804fe98, 0x9ffd05ff, 0x059efd04, 0xf801a9fa, + 0x2088d900, 0x9fce0080, 0xff004e00, 0xf004fefd, 0x9ffa59f5, 0xb600f801, 0x348c0fa4, 0x648b0024, + 0xcfbf0024, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, 0xf9fa059d, 0x0ccc9001, 0x1bf4cba6, + 0xb600f8e4, 0xfc8c0fa4, 0x048b001f, 0xcfbf0021, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, 0xf9fa059d, 0x0ccc9001, 0x1bf4cba6, 0x8f00f8e4, 0xbf0017d0, 0x019990f9, 0x00f8f9a0, 0xa0f990f9, - 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006cfb7e, 0xe8fee0fc, 0xfef0fc00, + 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006cdb7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, - 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006ddf7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, + 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006dbf7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, - 0xe0f9018e, 0x00708c7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, - 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006d8e7e, + 0xe0f9018e, 0x0070787e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, + 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006d6e7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, - 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006cad7e, 0xe8fee0fc, 0xfef0fc00, + 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006c8d7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, - 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006c5f7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, + 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006c3f7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, - 0xe0f9018e, 0x006a2f7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, - 0x00f801f8, 0x0017d489, 0x9433993f, 0x0a0a0c01, 0x107eb4bd, 0x46890000, 0x93fe0000, 0x492e0f00, - 0x9ffa0080, 0x5ad67e00, 0x08004900, 0x8f0099cf, 0xfd010000, 0x0bf4049f, 0x02af7e0e, 0x00468900, - 0x0093fe00, 0x00021b7e, 0x0020fd7e, 0x006a748a, 0x0000e17e, 0x006aac8a, 0x0000f97e, 0x006ae48a, - 0x0001117e, 0x006a3c8a, 0x0001297e, 0x006b1c8a, 0x0001417e, 0x006b548a, 0x0001597e, 0x006b8c8a, - 0x0001717e, 0x0001897e, 0x0004627e, 0x00022c7e, 0xd489010f, 0x9f200017, 0x3e0028f4, 0xf9006c58, - 0x08404912, 0xc70099cf, 0x1ab27491, 0x0002407e, 0x1000a433, 0x010b090a, 0x0000107e, 0x006cab3e, + 0xe0f9018e, 0x006a0f7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, + 0x00f801f8, 0x0017d489, 0x9433993f, 0x0a0a0c01, 0x107eb4bd, 0x46890000, 0x93fe0000, 0x492f0f00, + 0x9ffa0080, 0x5ab67e00, 0x08004900, 0x8f0099cf, 0xfd010000, 0x0bf4049f, 0x02af7e0e, 0x00468900, + 0x0093fe00, 0x00021b7e, 0x0020df7e, 0x006a548a, 0x0000e17e, 0x006a8c8a, 0x0000f97e, 0x006ac48a, + 0x0001117e, 0x006a1c8a, 0x0001297e, 0x006afc8a, 0x0001417e, 0x006b348a, 0x0001597e, 0x006b6c8a, + 0x0001717e, 0x0001897e, 0x0004627e, 0x00022c7e, 0xd489010f, 0x9f200017, 0x3e0028f4, 0xf9006c38, + 0x08404912, 0xc70099cf, 0x1ab27491, 0x0002407e, 0x1000a433, 0x010b090a, 0x0000107e, 0x006c8b3e, 0x02a010b8, 0x0204b600, 0xe4000bce, 0xb2ffffbc, 0xf0bbc71a, 0x000ac87e, 0x02b019b8, 0x0294b600, 0xd9009afa, 0x80000000, 0xfb0109fa, 0x4912f911, 0x99cf0840, 0x7091c700, 0x407e1ab2, 0xa4330002, - 0x080a1000, 0x107e010b, 0xf93e0000, 0x10b8006c, 0xb6000260, 0x0bce0204, 0xffbce400, 0xc71ab2ff, + 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0x09b3006f, 0xb1015b60, 0xf4006006, 0x09b3190c, 0xb1013b43, - 0xf5004306, 0xb3012808, 0x019f580d, 0x00701f3e, 0x4d7009b3, 0x7109b301, 0x0db30152, 0x3e018c61, - 0xb2007033, 0x25287e1a, 0x6fdc3e00, 0x0b1ab200, 0x7ec4bd01, 0x3e000261, 0xb2007061, 0x15a57e1a, - 0x6fdc3e00, 0x7e1ab200, 0x3e002883, 0xb2007061, 0x18197e1a, 0x70613e00, 0x7e1ab200, 0x3e002737, - 0xb2007061, 0x26557e1a, 0x6fdc3e00, 0x7e1ab200, 0x3e0024eb, 0xb2007061, 0x21817e1a, 0x6fdc3e00, - 0x7e1ab200, 0x3e005773, 0xb2006fdc, 0x53b47e1a, 0x6fdc3e00, 0x7e1ab200, 0x3e0052d0, 0xb2006fdc, - 0x177f7e1a, 0xb2010b00, 0x7e1ab2ac, 0x3e0021fa, 0xb2006fdc, 0x22967e1a, 0x6fdc3e00, 0x7e1ab200, - 0x3e00145f, 0x0b006fdc, 0x0c1ab201, 0x13a77e01, 0xb3abb200, 0x009e00ad, 0xcb7e1ab2, 0xdc3e0014, - 0x1ab2006f, 0x0018d17e, 0x0070613e, 0xfb7e1ab2, 0xdc3e001a, 0x1ab2006f, 0x00296b7e, 0xa9b3abb2, - 0x3e008300, 0xb2007051, 0x29c77e1a, 0x70613e00, 0x08b04b00, 0xb200bbcf, 0x5c1a7e1a, 0x70613e00, - 0x7e1ab200, 0x3e00188b, 0xb2007061, 0x189f7e1a, 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0x7e1ab200, 0xb2000050, 0x0c020b1a, - 0x02617e15, 0xf421fb00, 0x82f9e030, 0xffffc1e4, 0xb210c295, 0xffa0e4c5, 0x10a395ff, 0x48fea4b2, - 0x0147fe01, 0x903c8890, 0x8bb53477, 0x017db501, 0x0bb27ca0, 0x1ab28aa0, 0x0076ce7e, 0xa6b20bb2, - 0xce7e2ab2, 0x3bb20076, 0x1ab2a0b2, 0x0076ce7e, 0xa1b23bb2, 0xce7e2ab2, 0x10bc0076, 0x10699500, - 0x09bcadb2, 0xf410a600, 0x00890a0d, 0xd9bc0100, 0x017b98d0, 0xffff69e4, 0xfe100f94, 0xf9bc014e, - 0x24ee90f0, 0xa0100995, 0x90d9bcef, 0xbf01e9b5, 0x01ed98ec, 0x41fe4ab2, 0x2c119001, 0xa0011db5, - 0x76ce7e1c, 0x018b9800, 0x5ab2a0b2, 0x0076ce7e, 0xbc011b98, 0x1abf000a, 0xfbb00bbc, 0x30f42085, - 0x00c0b3f0, 0x014ffe33, 0xb508ff90, 0xfaa001fb, 0x9cbb2009, 0x0096b002, 0xbc211df4, 0xb9bcf5ac, - 0x014afe94, 0xbc059ffd, 0xa9a0f5bc, 0x9801afb5, 0xaabf01ab, 0xf81030f4, 0x014afe00, 0xbd019fb9, - 0xf5bfbc94, 0xa001a9b5, 0x01ab98af, 0x543eaabf, 0x30f40072, 0xfe82f9e4, 0x49fe014f, 0x30ff9001, - 0xb5389990, 0xfca001fd, 0xa0019bb5, 0xb2c2b29a, 0x00ddb3a6, 0xcba600bb, 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0x73ae3e20, 0xb2100900, 0x73ae3e9d, 0xb2100900, 0x72b23e9d, 0x01449200, 0x3e0002bc, - 0x9200730e, 0x02bc0144, 0x73fc3e00, 0xb2a9b200, 0x00a6b0af, 0xb22b1ef4, 0x00b6b0ba, 0xff131ef4, - 0xb9ffacfa, 0x051ef496, 0xaab900f8, 0xb900f801, 0xfaff01ba, 0x96b9ffac, 0x3ef01ff4, 0xb90076aa, - 0xbab201af, 0xf400b6b0, 0xaf3ed81f, 0xaf950076, 0x10b99510, 0xff91a9ff, 0xbffda0ba, 0xb0b9bc01, - 0xbc10b4b6, 0x00f8a0ba, 0x1400c0b3, 0xb93c94bd, 0x99af3cf8, 0xa6019990, 0xf51bf49c, 0x02f800f8, + 0x0a1000a4, 0x7e010b05, 0x3e000010, 0x8f006dbd, 0x94010060, 0x9fbc0f09, 0x0000df90, 0x9ffd0080, + 0x0091ce05, 0x000000d9, 0x9419ff11, 0xb2090bf4, 0x248e7e0a, 0xb20ab200, 0x00807e1b, 0xf911fb00, + 0x08404922, 0xc40099cf, 0x1ab20f91, 0x0002407e, 0x1200a433, 0x010b040a, 0x107e24bd, 0x4d3e0000, + 0x19b80070, 0xb6000240, 0x92cf0294, 0xff20c400, 0xff0209b3, 0x7e1ab200, 0x0b00038e, 0x00a9330b, + 0x09b30244, 0xb0011712, 0x0cf41206, 0x0709b369, 0x06b00122, 0x2e0cf407, 0xe50309b3, 0x0306b000, + 0xb3130cf4, 0x00c20109, 0xf50106b0, 0x3e00c40c, 0xb300704d, 0x00de0509, 0xf50506b0, 0x3e00ea0c, + 0xb3006f07, 0x01140e09, 0xf40e06b0, 0x09b3180c, 0xb000f50c, 0x0cf50c06, 0x0db300f7, 0x3e021808, + 0xb3006f39, 0x010f1009, 0xf51006b0, 0x3e011b0c, 0xb3006f61, 0x017a4109, 0x004106b1, 0xb3340cf4, + 0x01401809, 0xf41806b0, 0x09b3160c, 0xb3011015, 0x01261709, 0xde140db3, 0x6f903e01, 0x2109b300, + 0x09b30136, 0xb3013b40, 0x01cb200d, 0x006fc93e, 0x656009b3, 0x6006b101, 0x190cf400, 0x454309b3, + 0x4306b101, 0x3208f500, 0x580db301, 0x0b3e01a9, 0x09b30070, 0xb3015770, 0x015c7109, 0x96610db3, + 0x701f3e01, 0x7e1ab200, 0x3e002508, 0xb2006f67, 0xbd010b1a, 0x02617ec4, 0x704d3e00, 0x7e1ab200, + 0x3e00158b, 0xb2006f67, 0x28637e1a, 0x704d3e00, 0xbd1ab200, 0x6f1d3eb4, 0x0b1ab200, 0x17cc7e01, + 0x704d3e00, 0x7e1ab200, 0x3e002717, 0xb200704d, 0x26357e1a, 0x6f673e00, 0x7e1ab200, 0x3e0024cb, + 0xb200704d, 0x21637e1a, 0x6f673e00, 0x7e1ab200, 0x3e005753, 0xb2006f67, 0x53947e1a, 0x6f673e00, + 0x7e1ab200, 0xb20052b0, 0x00a9b3ab, 0x3d3e00e4, 0x1ab20070, 0x0017657e, 0xacb2010b, 0xdc7e1ab2, + 0x673e0021, 0x1ab2006f, 0x0022787e, 0x006f673e, 0x3d7e1ab2, 0x673e0014, 0x010b006f, 0x010c1ab2, + 0x0013a77e, 0xadb3abb2, 0xb2009700, 0x14b17e1a, 0x6f673e00, 0x7e1ab200, 0x3e0018b3, 0xb200704d, + 0x1add7e1a, 0x6f673e00, 0x7e1ab200, 0x3e00294b, 0xb2006f67, 0x29a77e1a, 0x704d3e00, 0x08b04b00, + 0xb200bbcf, 0x5bfa7e1a, 0x704d3e00, 0x7e1ab200, 0x3e00186d, 0xb200704d, 0x18817e1a, 0x704d3e00, + 0x7e1ab200, 0x3e00188c, 0xb200704d, 0x1d6f7e1a, 0x6f673e00, 0x7e1ab200, 0x3e0019de, 0xb200704d, + 0x196f7e1a, 0x704d3e00, 0x7e1ab200, 0x3e00084d, 0xb200704d, 0x07c77e1a, 0x704d3e00, 0x04b0b300, + 0x7e1ab210, 0x0e00177b, 0x704f3e01, 0xb8e4bd00, 0x0002401d, 0xffffffdf, 0x1ee4b6bf, 0xd902d4b6, + 0x80000000, 0xfd9529ff, 0xe9fd049f, 0x00defa05, 0x100b21fb, 0x0070413e, 0x404922f9, 0x0099cf08, + 0xb26491c7, 0x02407e1a, 0x00a43300, 0x0b030a10, 0x00107e01, 0x71513e00, 0x7e1ab200, 0xb20001e7, + 0x0ca0b3a0, 0x0ca6b062, 0xb3130cf4, 0xb32002a0, 0xb33803a0, 0x3e5e00a0, 0xb3007141, 0xb36811a0, + 0xb36e12a0, 0x3e7e0da4, 0xb200711b, 0x1ba97e1a, 0xb2a2b200, 0x00507e1a, 0x0020b300, 0xb21ab278, + 0x3e2cb20b, 0xb200714d, 0x1cd67e1a, 0xb2a0b200, 0x00507e1a, 0x0000b300, 0xb21ab25c, 0x3e020b0c, + 0xb200714d, 0x7e020b1a, 0x3d001815, 0x18567ea4, 0x7e1ab200, 0x3e000050, 0xb2007151, 0x3e030b1a, + 0xb2007107, 0x554f7e1a, 0x71333e00, 0x7e1ab200, 0xb20055b5, 0x00a0b3ac, 0x0b1ab21c, 0x714d3e19, + 0x7e1ab200, 0xb2000050, 0x0c020b1a, 0x02617e15, 0xf421fb00, 0x82f9e030, 0xffffc1e4, 0xb210c295, + 0xffa0e4c5, 0x10a395ff, 0x48fea4b2, 0x0147fe01, 0x903c8890, 0x8bb53477, 0x017db501, 0x0bb27ca0, + 0x1ab28aa0, 0x0076ba7e, 0xa6b20bb2, 0xba7e2ab2, 0x3bb20076, 0x1ab2a0b2, 0x0076ba7e, 0xa1b23bb2, + 0xba7e2ab2, 0x10bc0076, 0x10699500, 0x09bcadb2, 0xf410a600, 0x00890a0d, 0xd9bc0100, 0x017b98d0, + 0xffff69e4, 0xfe100f94, 0xf9bc014e, 0x24ee90f0, 0xa0100995, 0x90d9bcef, 0xbf01e9b5, 0x01ed98ec, + 0x41fe4ab2, 0x2c119001, 0xa0011db5, 0x76ba7e1c, 0x018b9800, 0x5ab2a0b2, 0x0076ba7e, 0xbc011b98, + 0x1abf000a, 0xfbb00bbc, 0x30f42085, 0x00c0b3f0, 0x014ffe33, 0xb508ff90, 0xfaa001fb, 0x9cbb2009, + 0x0096b002, 0xbc211df4, 0xb9bcf5ac, 0x014afe94, 0xbc059ffd, 0xa9a0f5bc, 0x9801afb5, 0xaabf01ab, + 0xf81030f4, 0x014afe00, 0xbd019fb9, 0xf5bfbc94, 0xa001a9b5, 0x01ab98af, 0x403eaabf, 0x30f40072, + 0xfe82f9e4, 0x49fe014f, 0x30ff9001, 0xb5389990, 0xfca001fd, 0xa0019bb5, 0xb2c2b29a, 0x00ddb3a6, + 0xcba600bb, 0x00f70df5, 0x00ffff89, 0x0cf5c9a6, 0xc6b1037a, 0x0df500ff, 0x080903af, 0x29bc180d, + 0x24888fe5, 0x98fe3c00, 0xbbff94f0, 0xd0b302d9, 0xbdbc1800, 0xbb2009f4, 0x9dbb042d, 0x9569bc02, + 0xff046dbb, 0x2195b59f, 0xff25e410, 0x4cb1ffff, 0xb20db1ff, 0x7e5bb24a, 0xb60076ba, 0x69951004, + 0x0509fd10, 0x0df4a0a6, 0x01449214, 0xa60002bc, 0x090cf420, 0x0cf5a0a6, 0x0abb036f, 0xff5bb202, + 0x3ab23c01, 0x0076ba7e, 0xe40d01ff, 0xb6ffff69, 0x09fd1004, 0xf4a0a605, 0x3392160d, 0x0002bc01, + 0x0cf420a6, 0xf4a0a60b, 0x3392060d, 0x10499401, 0x39ffb4bd, 0x1c85fba5, 0x0cf5dba6, 0xff8900ec, + 0xd9a600ff, 0x00e90cf5, 0x00ffd6b1, 0x02f10df5, 0x180c0809, 0x8fe5d9bc, 0x3c002488, 0x94f098fe, + 0x72c9bcff, 0xed007db3, 0xf4dba600, 0x26a60908, 0x00b60cf5, 0xb4bd010a, 0xb31c85fb, 0x090900c4, + 0x0092cc01, 0x00ffff89, 0x0cf529a6, 0x26b101c7, 0x0df500ff, 0x080902bb, 0x29bc180d, 0x24888fe5, + 0x98fe3c00, 0xbcff94f0, 0x4db342d9, 0xbc01cb00, 0x239502b2, 0xff25e410, 0xff0107ff, 0x5bb24c03, + 0xba7e4ab2, 0x03ff0076, 0x1069950d, 0xfd1004b6, 0xa0a60509, 0x92140df4, 0x02bc0144, 0xf420a600, + 0xa0a6090c, 0x028b0cf5, 0xb2020abb, 0x1c03ff5b, 0xba7e1ab2, 0x03ff0076, 0xff69e40d, 0x1004b6ff, + 0xa60509fd, 0x160df4a0, 0xbc011192, 0x20a60002, 0xa60b0cf4, 0x060df4a0, 0x94011192, 0x7bb21049, + 0xfba519ff, 0xa4bd1c85, 0x85fbb4bd, 0xffffd91c, 0xd9a600ff, 0x02010df5, 0x888f1809, 0xd9bc0024, + 0x98fe3ce5, 0x94f0080c, 0x72c9bcff, 0x1d0079b3, 0x9427bcff, 0xbbe4b7bc, 0x91b004d7, 0xbb200909, + 0xb9bc0297, 0xf569bc05, 0xff9529bc, 0x9dff85fe, 0x10439545, 0xffff41e4, 0xb25c03ff, 0x7e5ab21b, + 0xff0076ba, 0x89950d03, 0x1004b610, 0xa60509fd, 0x190df4a0, 0xbc015592, 0x40a60004, 0xa60e0cf4, + 0x090df4a0, 0xbc015592, 0x0abb0004, 0xff1bb202, 0x2ab22c03, 0x0076ba7e, 0xe40d03ff, 0xb6ffff89, + 0x09fd1004, 0xf4a0a605, 0x2292190d, 0x0004bc01, 0x0cf440a6, 0xf4a0a60e, 0x04bc090d, 0x01229200, + 0xb40910b4, 0x59940930, 0x820abc10, 0xf14529ff, 0xe4ffff14, 0xb2ffff40, 0x7e0ab21b, 0xb60076ba, + 0xa5b21035, 0x0ab23bb2, 0x0076ba7e, 0x42951bb2, 0xb2a0b210, 0x76ba7e2a, 0xb23bb200, 0x7e2ab2a1, + 0xbc0076ba, 0x59950010, 0x0009bc10, 0x0df410a6, 0x0000890a, 0xa0a9bc01, 0xbc100995, 0x8aa6a0a9, + 0x00ed08f5, 0x0bf58aa6, 0x4ab200d4, 0x85fbb4bd, 0xffffd91c, 0x29a600ff, 0x00fd0df5, 0x888f1809, + 0x29bc0024, 0x98fe3ce5, 0x94f0080d, 0x42d9bcff, 0x3f0049b3, 0xf4b4bcfe, 0x04bb2000, 0x9560bc02, + 0xbc0424bb, 0x239505b0, 0x859fff10, 0xe47c03ff, 0xb2ffff25, 0x7e5bb27a, 0xff0076ba, 0x89950d03, + 0x1004b610, 0xa60590ff, 0x190df4a0, 0xbc017792, 0x20a60002, 0xa60e0cf4, 0x090df4a0, 0xbc017792, + 0x0abb0002, 0xff5bb202, 0x1ab21c03, 0x0076ba7e, 0xe40d03ff, 0xb6ffff89, 0x09fd1004, 0xf4a0a605, + 0x1192190d, 0x0002bc01, 0x0cf420a6, 0xf4a0a60e, 0x1192090d, 0x0002bc01, 0xbb107994, 0x0abb0464, + 0x7519ff02, 0x0073bb3e, 0xffffffd9, 0xf4c9a600, 0x18094e0d, 0x9e3e080d, 0x0f940072, 0xff5ee410, + 0x9467bcff, 0xa6f0febc, 0x2118f59f, 0x014a92ff, 0x85fbb4bd, 0xb210091c, 0x73543e9c, 0x0c94bd00, + 0x73543e20, 0x0d94bd00, 0x729e3e20, 0x0d94bd00, 0x739a3e20, 0xb2100900, 0x739a3e9d, 0xb2100900, + 0x729e3e9d, 0x01449200, 0x3e0002bc, 0x920072fa, 0x02bc0144, 0x73e83e00, 0xb2a9b200, 0x00a6b0af, + 0xb22b1ef4, 0x00b6b0ba, 0xff131ef4, 0xb9ffacfa, 0x051ef496, 0xaab900f8, 0xb900f801, 0xfaff01ba, + 0x96b9ffac, 0x3ef01ff4, 0xb9007696, 0xbab201af, 0xf400b6b0, 0x9b3ed81f, 0xaf950076, 0x10b99510, + 0xff91a9ff, 0xbffda0ba, 0xb0b9bc01, 0xbc10b4b6, 0x00f8a0ba, 0x1400c0b3, 0xb93c94bd, 0x99af3cf8, + 0xa6019990, 0xf51bf49c, 0x02f800f8, 0x0202f802, 0xf80202f8, 0x02f80202, 0x0202f802, 0xf80202f8, 0xf2e8911a, 0xefac17e9, 0xd5510687, 0xd8570622, 0xb47df343, 0x56dd5387, 0xd8db62f9, 0xff7f6fe1, 0xa6d47a0f, 0xc564fcac, 0xa3fdd2f7, 0x2a44d4c6, 0xff16ae95, 0x77c19e61, 0x70c69a2a, 0xb18bf04b, 0x3db93bbe, 0xce16b53b, 0xea324a27, 0xccb6435e, 0x5e27377e, 0xfbb2b5bc, 0x2a467f22, 0xbde9aa37, @@ -1057,11 +1057,11 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0xcc0bf79a, 0xdc2be884, 0x53b46a1f, 0xdfd60169, 0x470bb491, 0xcc1920d2, 0xfd3ac52e, 0x5683fa01, 0xdf63a241, 0x6f08a80c, 0xf39a3b3c, 0xcd722471, 0xcc0bf79a, 0xdc2be884, 0x53b46a1f, 0xdfd60169, 0x470bb491, 0xcc1920d2, 0xfd3ac52e, 0x5683fa01, 0xdf63a241, 0x6f08a80c, 0xf39a3b3c, 0xcd722471, - 0x00000002, 0x0000002e, 0x00000000, 0x00000000, 0x206e614a, 0x32203031, 0x20323230, 0x333a3930, - 0x32323a36, 0x00580020, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000002, 0x0000002f, 0x00000000, 0x00000000, 0x20727041, 0x32203832, 0x20333230, 0x323a3032, + 0x35323a35, 0x00580020, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x3fd26956, 0x6674ff70, 0xcc87316f, 0x440b2953, 0x50c0ef2d, 0x3f8fcfb3, 0xc5fef1a0, 0x7404d2c2, - 0x620d246e, 0xac97f8b8, 0xfbe1a191, 0x508703bc, 0x0000e38e, 0x00000000, 0x0000f5c2, 0x00000000, + 0x3fd26956, 0x6674ff70, 0xcc87316f, 0x440b2953, 0x100a7c7b, 0x96c0b74a, 0xf665aa1d, 0xc5ba1dd8, + 0xadf421a9, 0x118771c9, 0x9222e575, 0xaf1f02bd, 0x0000e38e, 0x00000000, 0x0000f5c2, 0x00000000, 0x0000fc0f, 0x00000000, 0x007a0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1361,7 +1361,7 @@ const NvU32 minion_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000010, 0x00000000, 0x7c010001, 0x04100c13, 0x00000293, 0x0000002c, 0x00000018, 0x00007272, + 0x00000010, 0x00000000, 0x7c010001, 0x04100c13, 0x00000293, 0x0000002c, 0x00000018, 0x0000725e, 0x0000041b, 0x00000304, 0x04200e00, 0x00000002, 0x0980440e, 0x0b820a81, 0x0d840c83, 0x0f860e85, 0x11881087, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1591,3 +1591,4 @@ const NvU32 minion_ucode_header_lr10_dbg[] = { const NvU32 minion_ucode_data_size_lr10_dbg = 12096; #endif // _MINION_UCODE_LR10_DBG_H_ + diff --git a/src/common/nvswitch/kernel/inc/lr10/minion_production_ucode_lr10_prod.h b/src/common/nvswitch/kernel/inc/lr10/minion_production_ucode_lr10_prod.h index 7126039b27..512e870779 100644 --- a/src/common/nvswitch/kernel/inc/lr10/minion_production_ucode_lr10_prod.h +++ b/src/common/nvswitch/kernel/inc/lr10/minion_production_ucode_lr10_prod.h @@ -33,7 +33,7 @@ #define _MINION_UCODE_LR10_PROD_H_ const NvU32 minion_ucode_data_lr10_prod[] = { - 0x004000d0, 0x0004fe00, 0xc47ea4bd, 0x02f8006b, 0x4908a4b6, 0x9afa0830, 0x00b6b000, 0x090bfcf0, + 0x004000d0, 0x0004fe00, 0xa47ea4bd, 0x02f8006b, 0x4908a4b6, 0x9afa0830, 0x00b6b000, 0x090bfcf0, 0x029fbb02, 0xfa08104f, 0xb4b300f9, 0x02f80600, 0x010a00f8, 0x107eb4bd, 0x00f80000, 0xb4bd020a, 0x0000107e, 0x060a00f8, 0x107eb4bd, 0x00f80000, 0x000000df, 0x08bc4940, 0x89009ffa, 0xb6010060, 0xa9bc0fa4, 0x0000d9a0, 0xa9fd0080, 0x0000d905, 0xa9fa4000, 0x40004f01, 0xfa08bc49, 0x00f8009f, @@ -108,15 +108,15 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0x989a3c00, 0x56009433, 0x0101a08f, 0xbc0fa994, 0x00df909f, 0xfd008000, 0x99ce059f, 0x02448f00, 0xe8fabc00, 0xbce899c7, 0x9ebba9f9, 0x6199e702, 0x0796b003, 0x09050df4, 0x01c48e07, 0x03af9400, 0xbcf0f9bc, 0x999098ef, 0xf9e9bc01, 0x00ff9eb3, 0x89010f0e, 0x3c000254, 0x00f8a99f, 0x00026c89, - 0xb3989abc, 0xbd080290, 0x7e00f8a4, 0xec001acb, 0xf803e8aa, 0xb202f900, 0x1acb7ea0, 0x03e84c00, - 0xd4bdabb2, 0xe712a4b6, 0x7e01eebb, 0x89007272, 0xbc000500, 0x94b39890, 0xa0890c01, 0xc53e0000, + 0xb3989abc, 0xbd080290, 0x7e00f8a4, 0xec001aad, 0xf803e8aa, 0xb202f900, 0x1aad7ea0, 0x03e84c00, + 0xd4bdabb2, 0xe712a4b6, 0x7e01eebb, 0x8900725e, 0xbc000500, 0x94b39890, 0xa0890c01, 0xc53e0000, 0x10890009, 0x90bc0005, 0x0294b398, 0x0090890c, 0x09c53e00, 0x0190b300, 0xb2bfb20c, 0x09da3eae, - 0x00988900, 0x989cbf00, 0x677e019d, 0xb9940071, 0x10a5b610, 0xff10bf95, 0xa889a59a, 0x9cbf0000, - 0xb2019998, 0x10c5b6fb, 0xb6109d95, 0x9cff1094, 0x71677ec5, 0x10a99500, 0xfd10ba94, 0x01fb05a9, + 0x00988900, 0x989cbf00, 0x537e019d, 0xb9940071, 0x10a5b610, 0xff10bf95, 0xa889a59a, 0x9cbf0000, + 0xb2019998, 0x10c5b6fb, 0xb6109d95, 0x9cff1094, 0x71537ec5, 0x10a99500, 0xfd10ba94, 0x01fb05a9, 0x0002dc89, 0xf9989abc, 0xb3a0b202, 0x7e380194, 0x330006a9, 0xb23000a0, 0x04287e0a, 0x00a43300, 0x7e0ab226, 0x33000434, 0xb21c00a4, 0x09757e0a, 0x027c8900, 0x9890bc00, 0x0d0294b3, 0x3e02a5b6, 0xbd000a45, 0x8901fba4, 0xf9002784, 0xf89a3c22, 0x0002dc89, 0xb2989abc, 0x01f630a0, 0xb00b1cf0, - 0x2cf00196, 0x17537e0b, 0x025c8900, 0xc890bc00, 0x0003c489, 0x89f890bc, 0xbc000a34, 0x2489e890, + 0x2cf00196, 0x17397e0b, 0x025c8900, 0xc890bc00, 0x0003c489, 0x89f890bc, 0xbc000a34, 0x2489e890, 0x90bc000a, 0x0a1489d8, 0x9890bc00, 0xb61e14b6, 0xa4b61d24, 0xffc4f11f, 0x0ff4f0ff, 0xf005acfd, 0xf4b601e4, 0x13e4b614, 0xf005affd, 0xaefd01d4, 0x0194f005, 0xb612d4b6, 0xadfd1094, 0x05a9fd05, 0xfd05a1fd, 0x21fb05a2, 0x0002dc89, 0xf9989abc, 0xb2cfb252, 0x0190b3a4, 0x3e94bd0a, 0x89000af2, @@ -161,8 +161,8 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0x000e6480, 0xeb019d33, 0x207c8902, 0x0f4b9401, 0xd9b0b9bc, 0x00800000, 0xce05b9fd, 0x04bc00bb, 0xffffdca8, 0xbcfd7fff, 0x0d4f3e04, 0x0ec48f00, 0x0e948000, 0x0ea48200, 0x0eb48500, 0x01943300, 0x0f41946a, 0x01328c8e, 0x800000d9, 0x101ebc00, 0xce0519fd, 0xf4bc0011, 0xff1bc4a8, 0x7e00ff4c, - 0xc4005fd5, 0x04bcffa3, 0xe81bc7a8, 0x7e00ff4c, 0xb2005fd5, 0xa824bca0, 0x4cf01bc7, 0x04b600ff, - 0x5fd57e08, 0xbca2b200, 0x1b95a854, 0x00ff4c18, 0x7e0503fd, 0xb6005fd5, 0xa4b61024, 0x0502fd18, + 0xc4005fb5, 0x04bcffa3, 0xe81bc7a8, 0x7e00ff4c, 0xb2005fb5, 0xa824bca0, 0x4cf01bc7, 0x04b600ff, + 0x5fb57e08, 0xbca2b200, 0x1b95a854, 0x00ff4c18, 0x7e0503fd, 0xb6005fb5, 0xa4b61024, 0x0502fd18, 0x3ea50aff, 0xbc0012f7, 0x04bc98f4, 0xf854bcd8, 0xf0e824bc, 0xd4b6ff94, 0x18f4b608, 0xfdffe4f0, 0xd4f1059f, 0xe4b6ffff, 0x059efd10, 0x3ea59dff, 0x800012f7, 0x33001014, 0x0218019d, 0x8f0f4994, 0xbc012028, 0x9d3e909f, 0x24800010, 0x9d330010, 0x94020101, 0x288e0f49, 0x9ebc0130, 0x0000df90, @@ -194,261 +194,260 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0x03c9c404, 0xfd0394b6, 0xaffa05f9, 0x01b43301, 0x01944f1d, 0xc700a9ce, 0x9ca63399, 0x920e0bf4, 0xf4b301ff, 0x180af200, 0xa4bd00f8, 0x908900f8, 0xa4b60170, 0xa0a9bc0f, 0x800000d9, 0x05a9fd00, 0xdf00a9ce, 0x80000000, 0xfa059ffd, 0xfc0f01a9, 0xc4049ffd, 0x9ffd03cf, 0x01a9fa05, 0x1d01b433, - 0xce01944f, 0x99c700a9, 0xf49ca630, 0xff920e0b, 0x00f4b301, 0xf8190af2, 0xf8a4bd00, 0x70908900, - 0x0fa4b601, 0xd9a0a9bc, 0x00800000, 0xce05a9fd, 0xffdf00a9, 0xfd7fffff, 0xa9fa049f, 0x8f00f801, - 0xf9017090, 0x0fa99412, 0x9fbca1b2, 0x0000df90, 0x9ffd0080, 0x0099ce05, 0x000000df, 0xfd1a0002, - 0x0bf4049f, 0xbd010b20, 0x13a77ec4, 0xb3a0b200, 0xb21300a4, 0x143d7e1a, 0x89020f00, 0xbc00026c, - 0x0ab2199f, 0x02f911fb, 0x020c010b, 0xee7ea0b2, 0x0ab20013, 0x010c010b, 0x0013a77e, 0x0d00a4b3, - 0x6c89010f, 0x9fbc0002, 0x8f01fb09, 0x94017090, 0x9fbc0fa9, 0x0000df90, 0x9fff0080, 0x00d9ced5, - 0xffffffdf, 0x049ffdfe, 0x8e01d9fa, 0xbf00030c, 0xbb010fe9, 0xf9fd04fa, 0x08844905, 0x99cfefa0, - 0xff94f100, 0x0099b9ff, 0x0f059ffd, 0xf49fa6ff, 0x248f221b, 0xd9ce00f4, 0x1999c700, 0xb301ff92, - 0xb30c00f0, 0x3ef30190, 0x0a001531, 0x0190b317, 0xf8a4bd06, 0x030c8900, 0x099fbf00, 0xe49abc01, - 0xf494efff, 0xfefd060b, 0x030c8906, 0xf89fa000, 0x030c8e00, 0x09efbf00, 0x049abb01, 0xa0059ffd, - 0xf900f8e9, 0x03b4f012, 0x940fa4b6, 0x44890cbd, 0xb4b60128, 0xa0a9bc04, 0x00d1e4bd, 0x00008000, - 0xcfff4ccf, 0xcef5a1ff, 0x90fd00f9, 0x059bfd04, 0xfd049cfd, 0xf9fa059d, 0x01ee9001, 0xb340aa90, - 0xfbe504e4, 0x8912f911, 0x3c000c0c, 0xa0b2989a, 0x9933380a, 0x8900cc01, 0x3c0002fc, 0x9c89f890, - 0x90bc0002, 0x300e0ae8, 0x9cf001f6, 0x02e6b00b, 0xf00bfcf0, 0x9ffd01f6, 0xa51bf504, 0x03288900, - 0x98903c00, 0x9933120a, 0x94009801, 0x1c890f0d, 0x00dc0100, 0xbc008000, 0xdcffd0d9, 0x00cecec5, - 0x0002cc89, 0xdf9890bc, 0x8fffffff, 0xf004effd, 0x94b60794, 0x05e9fd1c, 0xdf01cefa, 0x00800000, - 0x2804ddb8, 0xf5dfff00, 0xf100f9ce, 0xfa081895, 0x00d901f9, 0x90008000, 0x894e18dd, 0x05d9fd00, - 0x9200dfce, 0xf9c701ee, 0x0194b303, 0x04f9c712, 0x0b0194b3, 0xb307f1c7, 0xb30c0110, 0x3e2100e0, - 0xb3001640, 0xb21900e0, 0x7e020b0a, 0x89001563, 0xbd0002dc, 0x0991bca4, 0x00167e3e, 0x11fb200a, - 0x01004489, 0xbc0fa4b6, 0x00d9a0a9, 0xb6008f00, 0xc4b60cb4, 0xffb4f104, 0xffc4f0ff, 0xf005b9fd, - 0xbcfd03d4, 0x02d4b605, 0x800000d9, 0x05bdfd00, 0xfa05a9fd, 0xa9ce01ab, 0x01ee9200, 0x0800e4b3, - 0x00f8040a, 0xb30394f0, 0x0aef0190, 0x0094b305, 0xf8a4bd06, 0x20948900, 0x0fa4b601, 0xbc0fb4f0, - 0x00d9a0a9, 0xfd008000, 0xabfa05a9, 0x04834f01, 0xb600a9ce, 0x0bf41f95, 0xf8a4bd07, 0x01ff9200, - 0xf000f4b3, 0x00f82d0a, 0x01004089, 0xbc0fa4b6, 0x0089a0a9, 0xb4b60f00, 0x03c4f004, 0xb6ffb4f0, - 0xb9fd02c4, 0x0000d905, 0xbcfd0080, 0x05a9fd05, 0x0901abfa, 0x17453e01, 0x00a9ce00, 0xf40394f0, - 0xdd92100b, 0x00d4b301, 0xb3240af4, 0xbd060094, 0x8900f8a4, 0xbc00028c, 0x96b0989a, 0x0bacf003, - 0x408900f8, 0xa4b60100, 0xa0a9bc0f, 0x800000d9, 0x05a9fd00, 0xf000aace, 0xacf003a4, 0xd900f80b, - 0x00800000, 0xb602aa90, 0xa9fd0fa4, 0x00aace05, 0xf8ffa4f0, 0x08b4b600, 0x0002ec89, 0xffffb4f1, - 0xbc04b5f0, 0x00f8a99b, 0x01284089, 0x800000df, 0x0fa4b600, 0xffa0a9bc, 0x99ce95af, 0x00aab800, - 0xaffd0001, 0xffff8f05, 0x049ffdfe, 0x0400008f, 0x8f059ffd, 0xf0f7ffff, 0x9ffd01b4, 0x13b4b604, - 0x0201008f, 0xfd05bffd, 0xabfa05b9, 0x8900f801, 0xdf012840, 0x00800000, 0xbc0fa4b6, 0xafffa0a9, - 0x0099ce95, 0x0100aab8, 0x05affd00, 0x9ffdfe0f, 0x0295f004, 0xf801a9fa, 0xbd02f900, 0x7ea0b2b4, - 0xb20017a8, 0x17ef7e0a, 0x8901fb00, 0xbc00029c, 0xb4b3a99b, 0x0f0f0f02, 0x0002ac89, 0xf8a99fbc, - 0x02ac8e00, 0x03b4b300, 0x2b8c8f20, 0x0fa99401, 0xdf909fbc, 0x00800000, 0xce059ffd, 0x99c70099, - 0x18673e68, 0xbc94bd00, 0x00f8a9e9, 0x00025889, 0x00f89a20, 0x00025889, 0x00f89a3f, 0x0002fc89, - 0x30989a3c, 0xacf00196, 0x0f00f80b, 0x03008901, 0xa99f3c00, 0x2089f43d, 0x9f3c0005, 0x0f00f8a9, - 0x03048901, 0xa99f3c00, 0x010f00f8, 0x00030889, 0xf8a99f3c, 0x03148900, 0xa99bbc00, 0x148900f8, - 0x9abc0003, 0x4767d9f8, 0xf9a68932, 0xf80bacf0, 0x89f43d00, 0x3c000324, 0xf4bda99f, 0x0002bc89, - 0xf8a99fbc, 0x03248900, 0xa89a3c00, 0x048900f8, 0xa4b60169, 0x0000df0f, 0xa9bc0080, 0xf5afffa0, - 0xde00f9ce, 0x7fffffff, 0xfa049efd, 0x00d901f9, 0xb8008000, 0x0207e0aa, 0xce05a9fd, 0xffdf00a9, - 0xfd7fffff, 0xa9fa049f, 0x8900f801, 0xb6016124, 0xa9bc0fa4, 0x0000d9a0, 0xa9fd0080, 0x00a9ce05, - 0xffffffdf, 0x049ffd7f, 0xf801a9fa, 0x21088900, 0x0fa4b601, 0x800000df, 0xa0a9bc00, 0xcef5afff, - 0x95f100f9, 0xf9fa03ff, 0x0000d901, 0xaa900080, 0x05a9fd40, 0x0f00a9ce, 0x049ffdc0, 0xf0ff3f4f, - 0x9ffd1295, 0x4095f004, 0xf801a9fa, 0x08044900, 0x8d0099ce, 0xde017600, 0x00800000, 0xbc0fa4b6, - 0x008da0ad, 0xaefffe8a, 0xa0adbcf5, 0x3300ffce, 0xe44b0394, 0x738000f9, 0x8f430090, 0xbc01284c, - 0xaeffa0af, 0x0099ce95, 0xb8dfff4f, 0x000100aa, 0xff049ffd, 0xe9fae5ae, 0x0000de01, 0xaa920080, - 0x95aeffe8, 0xb80099ce, 0x000100af, 0xde05fefd, 0xefffffff, 0xfa049efd, 0x00f801f9, 0x044942f9, - 0x0099ce08, 0x0176008d, 0xde0fa394, 0x00800000, 0x8d303dbc, 0xfffe8a00, 0x3dbcf53e, 0x00ffce30, - 0xa9039d33, 0x00f9e400, 0x00997380, 0x4c8f00a0, 0x3fbc0128, 0x254eff40, 0x890020ce, 0xbc01294c, - 0xef093039, 0xfd153eff, 0x10fa0409, 0x02704a01, 0x200005f1, 0x00044c7e, 0xd90110fa, 0x00800000, - 0xffe83392, 0x00ce0539, 0x0031b800, 0x19fd0001, 0xffffd905, 0x09fdbfff, 0x0000d904, 0x09fd1000, - 0x0110fa05, 0x4c7e0f0a, 0x00d90004, 0xfd400000, 0x10fa0509, 0x7e0f0a01, 0xd900044c, 0xbfffffff, - 0xfa0409fd, 0x0f0a0110, 0x00044c7e, 0xbd0022ce, 0x1025f0f4, 0x800000de, 0x954eff00, 0x900192fa, - 0x449001ff, 0x04f4b340, 0x7e41fbf4, 0xb3003afd, 0xb31004a0, 0xb31a07a0, 0x3e0f00a0, 0xda001af4, - 0x01896402, 0x80da00f8, 0xf802faf0, 0x9f88da00, 0x00f8032a, 0xadbeefda, 0xf900f8de, 0x7ea1b222, - 0x33000440, 0x00c001ad, 0x287e1ab2, 0xad330004, 0xb200b501, 0x04347e1a, 0x01ad3300, 0x8c8900aa, - 0x10940130, 0x0009bc0f, 0x800000d9, 0x009b4f00, 0x89e509ff, 0xbcfecf74, 0xe9ce0009, 0x01ff9200, - 0x0f00f4b3, 0x01023209, 0x3e0391b0, 0xb6001b58, 0x90b31f95, 0x24bde801, 0x01005089, 0x09bc1ab2, - 0x5b517e00, 0x7e1ab200, 0xb2006472, 0x5fe37e1a, 0x7e1ab200, 0xb20062f3, 0x63477e1a, 0x7e1ab200, - 0xd90063ae, 0x00800000, 0xce9509ff, 0x94f00099, 0x0c0bf430, 0x2889010f, 0x9f3c0003, 0x4767df19, - 0x14898932, 0x9fbc0003, 0x0024b319, 0x3ea4bd0a, 0xb4001bb6, 0x010f03a0, 0x00032489, 0x3e199f3c, - 0x0a001bc5, 0x8921fb13, 0xbc00028c, 0x22f9989a, 0x90b3a0b2, 0xa4bd0a03, 0x001c873e, 0xd57eb4bd, - 0x0ab20016, 0xc4bd060b, 0x020202dd, 0x05dc4e02, 0x0005e67e, 0x9300adb3, 0x05dc4100, 0x020202d2, - 0xb2070b02, 0x050b7e0a, 0x01119200, 0x667e0ab2, 0xa2a60005, 0xb2751bf4, 0x057d7e0a, 0x00a4b300, - 0xbd0ab26c, 0x0d040cb4, 0x07d04e01, 0x0016807e, 0x5700a4b3, 0x060b0ab2, 0x02ddc4bd, 0x4e010101, - 0xe67e05dc, 0xa4b30005, 0xdc414100, 0x0102d205, 0x070b0101, 0x0b7e0ab2, 0x11920005, 0x7e0ab201, - 0xa6000566, 0x2d1bf4a2, 0x7d7e0ab2, 0xa4b30005, 0x0ab22400, 0xd57e0e0b, 0xa4b30016, 0x020f0d00, - 0x00027c89, 0xfb099fbc, 0x001db321, 0x213eff78, 0x14b3001c, 0x2f0ac000, 0x001c873e, 0xb4bd32f9, - 0xd57ea1b2, 0x1ab20016, 0xc4bd060b, 0x020202dd, 0x09c44e02, 0x0005e67e, 0xa4b3a2b2, 0xc4402c00, - 0x0202d309, 0x070b0202, 0x0b7e1ab2, 0x00920005, 0x7e1ab201, 0xa6000566, 0x111bf4a3, 0x7d7e1ab2, - 0xa4b30005, 0x2ab20800, 0x04b331fb, 0x2e02dc00, 0x001ce63e, 0x00028c89, 0xf9989abc, 0xb3a1b222, - 0xbd0a0390, 0x1d7f3e04, 0x7eb4bd00, 0xb20016d5, 0x00a4b3a0, 0x0b1ab26e, 0xddc4bd06, 0x02020202, - 0x7e09c44e, 0xb20005e6, 0x00a4b3a0, 0x09c44056, 0x020202d2, 0xb2070b02, 0x050b7e1a, 0x01009200, - 0x667e1ab2, 0xa2a60005, 0xb23b1bf4, 0x057d7e1a, 0x00a4b300, 0xbd1ab232, 0x0dc4bdb4, 0x07d04e01, - 0x0016807e, 0xa4b3a0b2, 0x010f1900, 0x00027c89, 0x9fbc1ab2, 0x089b7e19, 0x7e1ab200, 0xb20008fd, - 0xb321fb0a, 0x00b20004, 0x1d7f3e2e, 0x001c8900, 0x9432f901, 0x09bc0fa0, 0x0000d900, 0xa1b20080, - 0x893509ff, 0xbcfeffe4, 0x32ce0009, 0x02cc8900, 0x5c2fc700, 0x7ea99fbc, 0x33003ab8, 0x890f00a4, - 0xbc0002bc, 0x90b39891, 0xf4bd1900, 0x0002bc89, 0x9fbc1ab2, 0x7e020b19, 0x3e00182b, 0x8e001e71, - 0x3f000258, 0x33300ae9, 0x008c009d, 0x0002dc89, 0x09f891bc, 0x0ae92001, 0x01f0b30c, 0x89010f7a, - 0xbc00029c, 0x00df199f, 0xd9400000, 0x8fffffff, 0xfd9429ff, 0x39fa059f, 0x00688901, 0x0000df01, - 0x09bc0080, 0xf50fff00, 0xde00f9ce, 0x40000000, 0xfa059efd, 0x00df01f9, 0x90008000, 0x0fff4400, - 0x00f9cef5, 0xfdcfff4e, 0xf9fa049e, 0x0000d901, 0x0eb80080, 0xfd0022e8, 0xe9ce05e9, 0xffffdf00, - 0x9ffd7fff, 0x01e9fa04, 0xfd01ff90, 0xe9fa059f, 0xfba4bd01, 0x028c8931, 0xbcf4bd00, 0x9c89a99f, - 0x9fbc0002, 0x02bc89a9, 0xa99fbc00, 0x00025c89, 0x89a99fbc, 0xbc0002dc, 0x7c89a99f, 0x9fbc0002, - 0x026c89a9, 0xbc010e00, 0xac89a99e, 0x9fbc0002, 0x02ec89a9, 0xbc02f900, 0xfc89a99f, 0x9e3c0002, - 0x030089a9, 0xa99f3c00, 0x00030489, 0x89a99f3c, 0x3c000308, 0x2489a99f, 0x9f3c0003, 0x032889a9, - 0x3ca0b200, 0x357ea99f, 0x0ab20015, 0x0039c27e, 0x2d7e0ab2, 0x01fb0029, 0x0002dc89, 0xf9989abc, - 0x01a2b222, 0x029db325, 0xbc8901f4, 0xa0940166, 0xbc050f0f, 0x00d90009, 0xff008000, 0x9ffa9509, - 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, - 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, - 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, - 0xd9019ffa, 0x00800000, 0x096800b8, 0x9509ff02, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, - 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, - 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, - 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d101, 0x00b80080, 0x8f00177c, - 0xfffe8af8, 0x0fbc9501, 0x0099ce00, 0xf40194f0, 0x04895f1b, 0x09bc0175, 0x5b127e00, 0x7e2ab200, - 0xb2006630, 0x1e757e2a, 0x7e2ab200, 0xb200070d, 0x07e87e2a, 0xf501ff00, 0xf000f9ce, 0xf9fa0195, - 0x0000df01, 0x00b80080, 0xff021540, 0x99ce950f, 0x0000b800, 0x0fff0010, 0x0099ce95, 0xfe983c89, - 0x080000b8, 0xf50fff02, 0xce0009bc, 0x2ab200f9, 0x0014a67e, 0xadb3a1b2, 0xb2008300, 0x14cb7e2a, - 0xb3a1b200, 0xb27600a4, 0x7e010b2a, 0xb20032ac, 0x00a4b3a1, 0x75048f68, 0x8afc8901, 0x000fbcfe, - 0x800000de, 0xe50eff00, 0xce0009bc, 0xfe0f00e9, 0xfa049ffd, 0x2ab201e9, 0x003b2d7e, 0x1f00a433, - 0x0176088f, 0x8f000fbc, 0xd9fe89f8, 0x00800000, 0xbc9509ff, 0x010f000f, 0xb2019ffa, 0x3b367e2a, - 0x00a43300, 0x76548918, 0xbc010f01, 0x00d90009, 0xff008000, 0x9ffa9509, 0xfb1ab201, 0x7ea4bd21, - 0xbd001e75, 0x3b057ea4, 0x7e010a00, 0x0a001e75, 0x3b057e01, 0x7e020a00, 0x0a001e75, 0x3b057e02, - 0x7e030a00, 0x0a001e75, 0x3b057e03, 0x89f43d00, 0x20000310, 0xb200f89f, 0x01cfc4ad, 0xfa08c049, - 0xbe4f009f, 0x01c0b373, 0x4e030f06, 0xe9cf08c0, 0x0899c700, 0x0bf49ca6, 0x01ff9227, 0xf200f4b3, - 0xf001c6b0, 0x1d090bfc, 0x33a29fbc, 0xb21401b4, 0xb2040bac, 0x02617eda, 0xf8a4bd00, 0xf8a4bd00, - 0x02dc8900, 0x989abc00, 0x110f02f9, 0x94b3a0b2, 0x010b6802, 0x377e010c, 0x0d940021, 0x2820890f, - 0x0000df01, 0xd9bc0080, 0xf5dfffd0, 0x4e00f9ce, 0x9efdfdfe, 0x01f9fa04, 0x800000d9, 0x18dd9000, - 0xfd50b74e, 0xd9ce05d9, 0x209fc600, 0xc70194f0, 0x90b305ff, 0xf4bd0600, 0xb301ee92, 0xb30800e0, - 0xb2e700f0, 0xbd010b0a, 0x21377ec4, 0x89f4bd00, 0xbc0002bc, 0xfab2099f, 0x22f901fb, 0xc1b2b2b2, - 0x947ea0b2, 0x2209003a, 0x8a00ad33, 0x0314b300, 0x028c8f3c, 0x0124b300, 0x0018892b, 0x09f1bc01, - 0xbc0f0f94, 0x00d9f0f9, 0xfd008000, 0xf9ce05f9, 0xffffde00, 0x9efddfff, 0x01f9fa04, 0x0022593e, - 0xf9bc0209, 0x22593e09, 0x028c8900, 0xbc010f00, 0x0209099f, 0x0bf42fa6, 0x00ac893c, 0x0f0d9401, - 0xd9d0d9bc, 0x00800000, 0xce05d9fd, 0x26b000d9, 0x0bfcf000, 0x9401f4f0, 0xf4b602fc, 0xfdf70e03, - 0x9ffd049e, 0xfdfb0f05, 0x9cfd049f, 0x01d9fa05, 0x9ab294bd, 0x8c8921fb, 0x9abc0002, 0xb202f998, - 0x019992a0, 0xf40196b0, 0xdc893e0d, 0x9abc0002, 0x0194b398, 0x03f27e34, 0x01a43300, 0x7e0ab20e, - 0x3e001cf4, 0xb20022cd, 0x1c9c7e0a, 0x00a4b300, 0x7e0ab21a, 0xbd00177f, 0xb2acb2b4, 0x21fa7e0a, - 0x22e73e00, 0xfba4bd00, 0x0c32f901, 0xb2a2b207, 0x4e030db3, 0x807e07d0, 0xa1b20016, 0x3600a4b3, - 0x9207d040, 0x34b30100, 0x2ab20e00, 0x0003d87e, 0x00231a3e, 0xbe7e2ab2, 0xa6b00003, 0x0b9cf007, - 0x0c0000b3, 0xdf009033, 0x0023323e, 0x06009433, 0x1ab20601, 0xdc8931fb, 0x9abc0002, 0xb212f998, - 0x0299b3a1, 0xa87e016b, 0xa4f00003, 0x04a0b3ff, 0x02a0b314, 0x0b1ab210, 0x0d030c04, 0x17087e6e, - 0xbd1ab200, 0x22e97eb4, 0x0b1ab200, 0x22e97e01, 0x284c8900, 0x0f109401, 0x800000de, 0x0009bc00, - 0xce950eff, 0xef0f0099, 0x010000b8, 0x049ffd00, 0xf1e50eff, 0xfa200095, 0x00de01e9, 0x92008000, - 0x0effe800, 0x0099ce95, 0x00b8fd0f, 0xfd000100, 0x0eff049f, 0x0195f0e5, 0x0b01e9fa, 0xb2020c01, - 0x13ee7e1a, 0x0000d900, 0x00b80080, 0x4e000728, 0x09ff0106, 0x0000dab5, 0x00b81000, 0xff020ff4, - 0x6889c509, 0x09bcfedf, 0x00b9ce00, 0xc700cdce, 0x9afd749f, 0x0e0bf404, 0x0b00f4b3, 0x3e1fd995, - 0xbd002405, 0x01ee9294, 0x0800e0b3, 0xdd009033, 0x7e01384a, 0xb200044c, 0x7e030b1a, 0x89001563, - 0xb2012820, 0x0009bc1a, 0x010c010b, 0x0021377e, 0x800000df, 0xf50fff00, 0x4e00f9ce, 0x9efdf3e5, - 0x01f9fa04, 0x800000d9, 0x180f9000, 0xff50b74c, 0xedcee5f9, 0x18d9c400, 0xc6101bf4, 0x9bc740d9, - 0x82d9c406, 0x06009033, 0xcc92b4bd, 0x00c0b301, 0x00b03308, 0xb2b4bde1, 0x17a87e1a, 0xbd010b00, - 0x7e1ab2c4, 0xb2002137, 0x39ac7e1a, 0x7e1ab200, 0x890039b7, 0x0f0002dc, 0x199fbc02, 0x00027c89, + 0xce01944f, 0x99c700a9, 0xf49ca630, 0xff920e0b, 0x00f4b301, 0xf8190af2, 0xf8a4bd00, 0x70908f00, + 0x9412f901, 0xa1b20fa9, 0xdf909fbc, 0x00800000, 0xce059fff, 0x00df0009, 0x0e020000, 0x049ffd1a, + 0x0b280bf4, 0x7ec4bd01, 0xb20013a7, 0x00a4b3ae, 0x0009ce1b, 0xffffffdf, 0x049ffd7f, 0x0f0109fa, + 0x026c8902, 0x199fbc00, 0x11fbeab2, 0x010b02f9, 0xa0b2020c, 0x0013ee7e, 0x010b0ab2, 0xa77e010c, + 0xa4b30013, 0x010f0d00, 0x00026c89, 0xfb099fbc, 0x70908f01, 0x0fa99401, 0xdf909fbc, 0x00800000, + 0xced59fff, 0xffdf00d9, 0xfdfeffff, 0xd9fa049f, 0x030c8e01, 0x0fe9bf00, 0x04fabb01, 0x4905f9fd, + 0xefa00884, 0xf10099cf, 0xb9ffff94, 0x9ffd0099, 0xa6ff0f05, 0x221bf49f, 0x00f4248f, 0xc700d9ce, + 0xff921999, 0x00f0b301, 0x0190b30c, 0x15173ef3, 0xb3170a00, 0xbd060190, 0x8900f8a4, 0xbf00030c, + 0xbc01099f, 0xefffe49a, 0x060bf494, 0x8906fefd, 0xa000030c, 0x8e00f89f, 0xbf00030c, 0xbb0109ef, + 0x9ffd049a, 0xf8e9a005, 0xf012f900, 0xa4b603b4, 0x0cbd940f, 0x01284489, 0xbc04b4b6, 0xe4bda0a9, + 0x800000d1, 0x4ccf0000, 0xa1ffcfff, 0x00f9cef5, 0xfd0490fd, 0x9cfd059b, 0x059dfd04, 0x9001f9fa, + 0xaa9001ee, 0x04e4b340, 0xf911fbe5, 0x0c0c8912, 0x989a3c00, 0x380aa0b2, 0xcc019933, 0x02fc8900, + 0xf8903c00, 0x00029c89, 0x0ae890bc, 0x01f6300e, 0xb00b9cf0, 0xfcf002e6, 0x01f6f00b, 0xf5049ffd, + 0x8900a51b, 0x3c000328, 0x120a9890, 0x98019933, 0x0f0d9400, 0x01001c89, 0x800000dc, 0xd0d9bc00, + 0xcec5dcff, 0xcc8900ce, 0x90bc0002, 0xffffdf98, 0xeffd8fff, 0x0794f004, 0xfd1c94b6, 0xcefa05e9, + 0x0000df01, 0xddb80080, 0xff002804, 0xf9cef5df, 0x1895f100, 0x01f9fa08, 0x800000d9, 0x18dd9000, + 0xfd00894e, 0xdfce05d9, 0x01ee9200, 0xb303f9c7, 0xc7120194, 0x94b304f9, 0xf1c70b01, 0x0110b307, + 0x00e0b30c, 0x16263e21, 0x00e0b300, 0x0b0ab219, 0x15497e02, 0x02dc8900, 0xbca4bd00, 0x643e0991, + 0x200a0016, 0x448911fb, 0xa4b60100, 0xa0a9bc0f, 0x8f0000d9, 0x0cb4b600, 0xf104c4b6, 0xf0ffffb4, + 0xb9fdffc4, 0x03d4f005, 0xb605bcfd, 0x00d902d4, 0xfd008000, 0xa9fd05bd, 0x01abfa05, 0x9200a9ce, + 0xe4b301ee, 0x040a0800, 0x94f000f8, 0x0190b303, 0xb3050aef, 0xbd060094, 0x8900f8a4, 0xb6012094, + 0xb4f00fa4, 0xa0a9bc0f, 0x800000d9, 0x05a9fd00, 0x4f01abfa, 0xa9ce0483, 0x1f95b600, 0xbd070bf4, + 0x9200f8a4, 0xf4b301ff, 0x2d0af000, 0x408900f8, 0xa4b60100, 0xa0a9bc0f, 0x0f000089, 0xf004b4b6, + 0xb4f003c4, 0x02c4b6ff, 0xd905b9fd, 0x00800000, 0xfd05bcfd, 0xabfa05a9, 0x3e010901, 0xce00172b, + 0x94f000a9, 0x100bf403, 0xb301dd92, 0x0af400d4, 0x0094b324, 0xf8a4bd06, 0x028c8900, 0x989abc00, + 0xf00396b0, 0x00f80bac, 0x01004089, 0xbc0fa4b6, 0x00d9a0a9, 0xfd008000, 0xaace05a9, 0x03a4f000, + 0xf80bacf0, 0x0000d900, 0xaa900080, 0x0fa4b602, 0xce05a9fd, 0xa4f000aa, 0xb600f8ff, 0xec8908b4, + 0xb4f10002, 0xb5f0ffff, 0xa99bbc04, 0x408900f8, 0x00df0128, 0xb6008000, 0xa9bc0fa4, 0x95afffa0, + 0xb80099ce, 0x000100aa, 0x8f05affd, 0xfdfeffff, 0x008f049f, 0x9ffd0400, 0xffff8f05, 0x049ffdf7, + 0x0201008f, 0xfa059ffd, 0x00f801a9, 0xa0b212f9, 0x8e7eb1b2, 0x40890017, 0xc08f0128, 0x04b6fed7, + 0x0009bc0f, 0x800000d9, 0x9509ff00, 0xce000fbc, 0xfe0f0099, 0xc5049ffd, 0x14b3029f, 0x9fc50701, + 0x29408986, 0x0009bc01, 0x800000d9, 0x9509ff00, 0xfb019ffa, 0x029c8911, 0xa99bbc00, 0x0f02b4b3, + 0xac890f0f, 0x9fbc0002, 0x8e00f8a9, 0xb30002ac, 0x8f2003b4, 0x94012b8c, 0x9fbc0fa9, 0x0000df90, + 0x9ffd0080, 0x0099ce05, 0x3e6899c7, 0xbd001851, 0xa9e9bc94, 0x588900f8, 0x9a200002, 0xfc8900f8, + 0x9a3c0002, 0x01963098, 0xf80bacf0, 0x89010f00, 0x3c000300, 0xf43da99f, 0x00052089, 0xf8a99f3c, + 0x89010f00, 0x3c000304, 0x00f8a99f, 0x0889010f, 0x9f3c0003, 0x8900f8a9, 0xbc000314, 0x00f8a99b, + 0x00031489, 0xd9f89abc, 0x89324767, 0xacf0f9a6, 0x3d00f80b, 0x032489f4, 0xa99f3c00, 0xbc89f4bd, + 0x9fbc0002, 0x8900f8a9, 0x3c000324, 0x00f8a89a, 0x01690489, 0xdf0fa4b6, 0x00800000, 0xffa0a9bc, + 0xf9cef5af, 0xffffde00, 0x9efd7fff, 0x01f9fa04, 0x800000d9, 0xe0aab800, 0xa9fd0207, 0x00a9ce05, + 0xffffffdf, 0x049ffd7f, 0xf801a9fa, 0x61248900, 0x0fa4b601, 0xd9a0a9bc, 0x00800000, 0xce05a9fd, + 0xffdf00a9, 0xfd7fffff, 0xa9fa049f, 0x8900f801, 0xb6012108, 0x00df0fa4, 0xbc008000, 0xafffa0a9, + 0x00f9cef5, 0x03ff95f1, 0xd901f9fa, 0x00800000, 0xfd40aa90, 0xa9ce05a9, 0xfdc00f00, 0x3f4f049f, + 0x1295f0ff, 0xf0049ffd, 0xa9fa4095, 0x4900f801, 0x99ce0804, 0x76008d00, 0x0000de01, 0xa4b60080, + 0xa0adbc0f, 0xfe8a008d, 0xbcf5aeff, 0xffcea0ad, 0x03943300, 0x00f9e44b, 0x00907380, 0x284c8f43, + 0xa0afbc01, 0xce95aeff, 0xff4f0099, 0x00aab8df, 0x9ffd0001, 0xe5aeff04, 0xde01e9fa, 0x00800000, + 0xffe8aa92, 0x99ce95ae, 0x00afb800, 0xfefd0001, 0xffffde05, 0x9efdefff, 0x01f9fa04, 0x42f900f8, + 0xce080449, 0x008d0099, 0xa3940176, 0x0000de0f, 0x3dbc0080, 0x8a008d30, 0xf53efffe, 0xce303dbc, + 0x9d3300ff, 0xe400a903, 0x738000f9, 0x00a00099, 0x01284c8f, 0xff403fbc, 0x20ce254e, 0x294c8900, + 0x3039bc01, 0x3effef09, 0x0409fd15, 0x4a0110fa, 0x05f10270, 0x4c7e2000, 0x10fa0004, 0x0000d901, + 0x33920080, 0x0539ffe8, 0xb80000ce, 0x00010031, 0xd90519fd, 0xbfffffff, 0xd90409fd, 0x10000000, + 0xfa0509fd, 0x0f0a0110, 0x00044c7e, 0x000000d9, 0x0509fd40, 0x0a0110fa, 0x044c7e0f, 0xffffd900, + 0x09fdbfff, 0x0110fa04, 0x4c7e0f0a, 0x22ce0004, 0xf0f4bd00, 0x00de1025, 0xff008000, 0x92fa954e, + 0x01ff9001, 0xb3404490, 0xfbf404f4, 0x3add7e41, 0x04a0b300, 0x07a0b310, 0x00a0b31a, 0x1ad63e0f, + 0x6402da00, 0x00f80189, 0xfaf080da, 0xda00f802, 0x032a9f88, 0xefda00f8, 0xf8deadbe, 0xb222f900, + 0x04407ea1, 0x01ad3300, 0x1ab200c0, 0x0004287e, 0xb501ad33, 0x7e1ab200, 0x33000434, 0x00aa01ad, + 0x01308c89, 0xbc0f1094, 0x00d90009, 0x4f008000, 0x09ff009b, 0xcf7489e5, 0x0009bcfe, 0x9200e9ce, + 0xf4b301ff, 0x32090f00, 0x91b00102, 0x1b3a3e03, 0x1f95b600, 0xe80190b3, 0x508924bd, 0x1ab20100, + 0x7e0009bc, 0xb2005b31, 0x64527e1a, 0x7e1ab200, 0xb2005fc3, 0x62d37e1a, 0x7e1ab200, 0xb2006327, + 0x638e7e1a, 0x0000d900, 0x09ff0080, 0x0099ce95, 0xf43094f0, 0x010f0c0b, 0x00032889, 0xdf199f3c, + 0x89324767, 0x00031489, 0xb3199fbc, 0xbd0a0024, 0x1b983ea4, 0x03a0b400, 0x2489010f, 0x9f3c0003, + 0x1ba73e19, 0xfb130a00, 0x028c8921, 0x989abc00, 0xa0b222f9, 0x0a0390b3, 0x693ea4bd, 0xb4bd001c, + 0x0016bb7e, 0x060b0ab2, 0x02ddc4bd, 0x4e020202, 0xe67e05dc, 0xadb30005, 0x41009300, 0x02d205dc, + 0x0b020202, 0x7e0ab207, 0x9200050b, 0x0ab20111, 0x0005667e, 0x1bf4a2a6, 0x7e0ab275, 0xb300057d, + 0xb26c00a4, 0x0cb4bd0a, 0x4e010d04, 0x667e07d0, 0xa4b30016, 0x0ab25700, 0xc4bd060b, 0x010102dd, + 0x05dc4e01, 0x0005e67e, 0x4100a4b3, 0xd205dc41, 0x01010102, 0x0ab2070b, 0x00050b7e, 0xb2011192, + 0x05667e0a, 0xf4a2a600, 0x0ab22d1b, 0x00057d7e, 0x2400a4b3, 0x0e0b0ab2, 0x0016bb7e, 0x0d00a4b3, + 0x7c89020f, 0x9fbc0002, 0xb321fb09, 0xff78001d, 0x001c033e, 0xc00014b3, 0x693e2f0a, 0x32f9001c, + 0xa1b2b4bd, 0x0016bb7e, 0x060b1ab2, 0x02ddc4bd, 0x4e020202, 0xe67e09c4, 0xa2b20005, 0x2c00a4b3, + 0xd309c440, 0x02020202, 0x1ab2070b, 0x00050b7e, 0xb2010092, 0x05667e1a, 0xf4a3a600, 0x1ab2111b, + 0x00057d7e, 0x0800a4b3, 0x31fb2ab2, 0xdc0004b3, 0xc83e2e02, 0x8c89001c, 0x9abc0002, 0xb222f998, + 0x0390b3a1, 0x3e04bd0a, 0xbd001d61, 0x16bb7eb4, 0xb3a0b200, 0xb26e00a4, 0xbd060b1a, 0x0202ddc4, + 0xc44e0202, 0x05e67e09, 0xb3a0b200, 0x405600a4, 0x02d209c4, 0x0b020202, 0x7e1ab207, 0x9200050b, + 0x1ab20100, 0x0005667e, 0x1bf4a2a6, 0x7e1ab23b, 0xb300057d, 0xb23200a4, 0xbdb4bd1a, 0x4e010dc4, + 0x667e07d0, 0xa0b20016, 0x1900a4b3, 0x7c89010f, 0x1ab20002, 0x7e199fbc, 0xb200089b, 0x08fd7e1a, + 0xfb0ab200, 0x0004b321, 0x3e2e00b2, 0x89001d61, 0xf901001c, 0x0fa09432, 0xd90009bc, 0x00800000, + 0x09ffa1b2, 0xffe48935, 0x0009bcfe, 0x890032ce, 0xc70002cc, 0x9fbc5c2f, 0x3a987ea9, 0x00a43300, + 0x02bc890f, 0x9891bc00, 0x190090b3, 0xbc89f4bd, 0x1ab20002, 0x0b199fbc, 0x18157e02, 0x1e533e00, + 0x02588e00, 0x0ae93f00, 0x009d3330, 0xdc89008c, 0x91bc0002, 0x200109f8, 0xb30c0ae9, 0x0f7a01f0, + 0x029c8901, 0x199fbc00, 0x000000df, 0xffffd940, 0x29ff8fff, 0x059ffd94, 0x890139fa, 0xdf010068, + 0x00800000, 0xff0009bc, 0xf9cef50f, 0x0000de00, 0x9efd4000, 0x01f9fa05, 0x800000df, 0x44009000, + 0xcef50fff, 0xff4e00f9, 0x049efdcf, 0xd901f9fa, 0x00800000, 0x22e80eb8, 0x05e9fd00, 0xdf00e9ce, + 0x7fffffff, 0xfa049ffd, 0xff9001e9, 0x059ffd01, 0xbd01e9fa, 0x8931fba4, 0xbd00028c, 0xa99fbcf4, + 0x00029c89, 0x89a99fbc, 0xbc0002bc, 0x5c89a99f, 0x9fbc0002, 0x02dc89a9, 0xa99fbc00, 0x00027c89, + 0x89a99fbc, 0x0e00026c, 0xa99ebc01, 0x0002ac89, 0x89a99fbc, 0xf90002ec, 0xa99fbc02, 0x0002fc89, + 0x89a99e3c, 0x3c000300, 0x0489a99f, 0x9f3c0003, 0x030889a9, 0xa99f3c00, 0x00032489, 0x89a99f3c, + 0xb2000328, 0xa99f3ca0, 0x00151b7e, 0xa27e0ab2, 0x0ab20039, 0x00290d7e, 0xdc8901fb, 0x9abc0002, + 0xb222f998, 0xb32501a2, 0x01f4029d, 0x0166bc89, 0x0f0fa094, 0x0009bc05, 0x800000d9, 0x9509ff00, + 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, + 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, + 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, 0xff040090, + 0x9ffa9509, 0x0000d901, 0x00b80080, 0xff020968, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, + 0xd9019ffa, 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, + 0x00800000, 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd9019ffa, 0x00800000, + 0xff040090, 0x9ffa9509, 0x0000d901, 0x00900080, 0x9509ff04, 0xd1019ffa, 0x00800000, 0x177c00b8, + 0x8af88f00, 0x9501fffe, 0xce000fbc, 0x94f00099, 0x5f1bf401, 0x01750489, 0x7e0009bc, 0xb2005af2, + 0x66107e2a, 0x7e2ab200, 0xb2001e57, 0x070d7e2a, 0x7e2ab200, 0xff0007e8, 0xf9cef501, 0x0195f000, + 0xdf01f9fa, 0x00800000, 0x154000b8, 0x950fff02, 0xb80099ce, 0x00100000, 0xce950fff, 0x3c890099, + 0x00b8fe98, 0xff020800, 0x09bcf50f, 0x00f9ce00, 0x8c7e2ab2, 0xa1b20014, 0x8300adb3, 0x7e2ab200, + 0xb20014b1, 0x00a4b3a1, 0x0b2ab276, 0x328c7e01, 0xb3a1b200, 0x8f6800a4, 0x89017504, 0xbcfe8afc, + 0x00de000f, 0xff008000, 0x09bce50e, 0x00e9ce00, 0x9ffdfe0f, 0x01e9fa04, 0x0d7e2ab2, 0xa433003b, + 0x088f1f00, 0x0fbc0176, 0x89f88f00, 0x0000d9fe, 0x09ff0080, 0x000fbc95, 0x9ffa010f, 0x7e2ab201, + 0x33003b16, 0x891800a4, 0x0f017654, 0x0009bc01, 0x800000d9, 0x9509ff00, 0xb2019ffa, 0xbd21fb1a, + 0x1e577ea4, 0x7ea4bd00, 0x0a003ae5, 0x1e577e01, 0x7e010a00, 0x0a003ae5, 0x1e577e02, 0x7e020a00, + 0x0a003ae5, 0x1e577e03, 0x7e030a00, 0x3d003ae5, 0x031089f4, 0xf89f2000, 0xc4adb200, 0xc04901cf, + 0x009ffa08, 0xb373be4f, 0x0f0601c0, 0x08c04e03, 0xc700e9cf, 0x9ca60899, 0x92270bf4, 0xf4b301ff, + 0xc6b0f200, 0x0bfcf001, 0x9fbc1d09, 0x01b433a2, 0x0bacb214, 0x7edab204, 0xbd000261, 0xbd00f8a4, + 0x8900f8a4, 0xbc0002dc, 0x02f9989a, 0xa0b2110f, 0x680294b3, 0x010c010b, 0x0021197e, 0x890f0d94, + 0xdf012820, 0x00800000, 0xffd0d9bc, 0xf9cef5df, 0xfdfe4e00, 0xfa049efd, 0x00d901f9, 0x90008000, + 0xb74e18dd, 0x05d9fd50, 0xc600d9ce, 0x94f0209f, 0x05ffc701, 0x060090b3, 0xee92f4bd, 0x00e0b301, + 0x00f0b308, 0x0b0ab2e7, 0x7ec4bd01, 0xbd002119, 0x02bc89f4, 0x099fbc00, 0x01fbfab2, 0xb2b222f9, + 0xa0b2c1b2, 0x003a747e, 0xad332209, 0xb3008a00, 0x8f3c0314, 0xb300028c, 0x892b0124, 0xbc010018, + 0x0f9409f1, 0xf0f9bc0f, 0x800000d9, 0x05f9fd00, 0xde00f9ce, 0xdfffffff, 0xfa049efd, 0x3b3e01f9, + 0x02090022, 0x3e09f9bc, 0x8900223b, 0x0f00028c, 0x099fbc01, 0x2fa60209, 0x893c0bf4, 0x940100ac, + 0xd9bc0f0d, 0x0000d9d0, 0xd9fd0080, 0x00d9ce05, 0xf00026b0, 0xf4f00bfc, 0x02fc9401, 0x0e03f4b6, + 0x049efdf7, 0x0f059ffd, 0x049ffdfb, 0xfa059cfd, 0x94bd01d9, 0x21fb9ab2, 0x00028c89, 0xf9989abc, + 0x92a0b202, 0x96b00199, 0x3e0df401, 0x0002dc89, 0xb3989abc, 0x7e340194, 0x330003f2, 0xb20e01a4, + 0x1cd67e0a, 0x22af3e00, 0x7e0ab200, 0xb3001c7e, 0xb21a00a4, 0x17657e0a, 0xb2b4bd00, 0x7e0ab2ac, + 0x3e0021dc, 0xbd0022c9, 0xf901fba4, 0xb2070c32, 0x0db3b2a2, 0x07d04e03, 0x0016667e, 0xa4b3a1b2, + 0xd0403600, 0x01009207, 0x0e0034b3, 0xd87e2ab2, 0xfc3e0003, 0x2ab20022, 0x0003be7e, 0xf007a6b0, + 0x00b30b9c, 0x90330c00, 0x143edf00, 0x94330023, 0x06010600, 0x31fb1ab2, 0x0002dc89, 0xf9989abc, + 0xb3a1b212, 0x01690299, 0x0003a87e, 0xb3ffa4f0, 0xb31404a0, 0xb21002a0, 0x0c040b1a, 0x7e6e0d03, + 0xb20016ee, 0x7eb4bd1a, 0xb20022cb, 0x7e010b1a, 0x890022cb, 0x9401284c, 0x00de0f10, 0xbc008000, + 0x0eff0009, 0x0099ce95, 0x00b8ef0f, 0xfd000100, 0x0eff049f, 0x0095f1e5, 0x01e9fa20, 0x800000de, + 0xe8009200, 0xce950eff, 0xfd0f0099, 0x010000b8, 0x049ffd00, 0xf0e50eff, 0xe9fa0195, 0x0c010b01, + 0x7e1ab202, 0xd90013ee, 0x00800000, 0x072800b8, 0x01064e00, 0xdab509ff, 0x10000000, 0x0ff400b8, + 0xc509ff02, 0xfedf6889, 0xce0009bc, 0xcdce00b9, 0x749fc700, 0xf4049afd, 0xf4b30e0b, 0xd9950b00, + 0x23e73e1f, 0x9294bd00, 0xe0b301ee, 0x90330800, 0x384add00, 0x044c7e01, 0x0b1ab200, 0x15497e03, + 0x28208900, 0xbc1ab201, 0x010b0009, 0x197e010c, 0x00df0021, 0xff008000, 0xf9cef50f, 0xf3e54e00, + 0xfa049efd, 0x00d901f9, 0x90008000, 0xb74c180f, 0xe5f9ff50, 0xc400edce, 0x1bf418d9, 0x40d9c610, + 0xc4069bc7, 0x903382d9, 0xb4bd0600, 0xb301cc92, 0x330800c0, 0xb2e100b0, 0x178e7e1a, 0xbd010b00, + 0x7e1ab2c4, 0xb2002119, 0x398c7e1a, 0x7e1ab200, 0x89003997, 0x0f0002dc, 0x199fbc02, 0x00027c89, 0x9ebce4bd, 0x026c8919, 0x199ebc00, 0x6c8f11fb, 0x02f90100, 0xb20fa994, 0x909fbca0, 0x00dfe4bd, 0xff008000, 0xfefaf59f, 0x0000df01, 0x99920080, 0x059ffd04, 0x9ffaf4bd, 0x0c040b01, 0x7e370d01, - 0xb2001708, 0x23367e0a, 0x8f01fb00, 0xf901006c, 0x0fa99402, 0x9fbca0b2, 0xdfe4bd90, 0x00800000, - 0xfaf59fff, 0x00df01fe, 0x92008000, 0x9ffd0499, 0xfaf4bd05, 0xee7e019f, 0x0ab20018, 0x0022967e, - 0x367e0ab2, 0x01fb0023, 0xa1b242f9, 0x0069307e, 0x00395089, 0x3398913c, 0x94380194, 0x70890f1e, + 0xb20016ee, 0x23187e0a, 0x8f01fb00, 0xf901006c, 0x0fa99402, 0x9fbca0b2, 0xdfe4bd90, 0x00800000, + 0xfaf59fff, 0x00df01fe, 0x92008000, 0x9ffd0499, 0xfaf4bd05, 0xd07e019f, 0x0ab20018, 0x0022787e, + 0x187e0ab2, 0x01fb0023, 0xa1b242f9, 0x00686c7e, 0x00395089, 0x3398913c, 0x94380194, 0x70890f1e, 0xd4bd0128, 0xdae0e9bc, 0x00800000, 0xffffffdb, 0x0000dcc0, 0xeaff1c00, 0x00f9cef5, 0xfd049bfd, 0xf9fa059c, 0x01dd9001, 0xb340ee90, 0x89eb04d4, 0x94012840, 0x09bc0f10, 0x0000d900, 0x09ff0080, 0x004fce45, 0x010000b8, 0x3509ff00, 0xfed6c089, 0xd90009bc, 0x3fffffff, 0xfa04f9fd, 0x1ab2013f, - 0x003ad07e, 0x1ab2abb2, 0x005cc37e, 0xadb3a2b2, 0x8900a300, 0x3c000324, 0x94339891, 0x1ab20a01, - 0x005ba67e, 0x01282089, 0xd90009bc, 0x00800000, 0xced509ff, 0x95f100d9, 0xd9fa0201, 0x180f9001, + 0x003ab07e, 0x1ab2abb2, 0x005ca37e, 0xadb3a2b2, 0x8900a300, 0x3c000324, 0x94339891, 0x1ab20a01, + 0x005b867e, 0x01282089, 0xd90009bc, 0x00800000, 0xced509ff, 0x95f100d9, 0xd9fa0201, 0x180f9001, 0x800000d9, 0xc5f9ff00, 0xce00c84f, 0xff9200ce, 0x01e9c401, 0x0b0194b3, 0xb305e9c7, 0xb30c0190, - 0x3e4a00f0, 0xb30025eb, 0xce4200f0, 0xff8f0049, 0x9ffdf9fe, 0x0139fa04, 0xf100d9ce, 0xfa040295, - 0xc84f01d9, 0x00cece00, 0xc701ff92, 0x94b301e9, 0xe9c70b01, 0x0190b306, 0x00f0b30c, 0x26253e16, - 0x00f4b300, 0x264f3e10, 0x3e370200, 0x02002651, 0xfb2ab221, 0xb252f941, 0xfc30f4a1, 0x003afd7e, - 0x1ab2a4b2, 0x003ad97e, 0x1ab2a3b2, 0x003b127e, 0x00031089, 0xa2b2993f, 0x92019933, 0x3800de00, - 0xe9ce0080, 0xffffdf00, 0x9ffd3fff, 0x01e9fa04, 0x217e1ab2, 0x00d50068, 0x94008000, 0x14890f10, - 0x09bc0171, 0x0505fd00, 0xb20000ce, 0x3aeb7e1a, 0x08884900, 0xb60099cf, 0x0bc41d95, 0x0091b0ff, - 0x3db24cb2, 0xe17e2eb2, 0xa4b3005e, 0x0c896800, 0x913c000c, 0x33390a98, 0x895b0190, 0x3c000c10, + 0x3e4a00f0, 0xb30025cb, 0xce4200f0, 0xff8f0049, 0x9ffdf9fe, 0x0139fa04, 0xf100d9ce, 0xfa040295, + 0xc84f01d9, 0x00cece00, 0xc701ff92, 0x94b301e9, 0xe9c70b01, 0x0190b306, 0x00f0b30c, 0x26053e16, + 0x00f4b300, 0x262f3e10, 0x3e370200, 0x02002631, 0xfb2ab221, 0xb252f941, 0xfc30f4a1, 0x003add7e, + 0x1ab2a4b2, 0x003ab97e, 0x1ab2a3b2, 0x003af27e, 0x00031089, 0xa2b2993f, 0x92019933, 0x3800de00, + 0xe9ce0080, 0xffffdf00, 0x9ffd3fff, 0x01e9fa04, 0x487e1ab2, 0x00d50069, 0x94008000, 0x14890f10, + 0x09bc0171, 0x0505fd00, 0xb20000ce, 0x3acb7e1a, 0x08884900, 0xb60099cf, 0x0bc41d95, 0x0091b0ff, + 0x3db24cb2, 0xc17e2eb2, 0xa4b3005e, 0x0c896800, 0x913c000c, 0x33390a98, 0x895b0190, 0x3c000c10, 0x94339891, 0x04de2001, 0xce008038, 0xff8f00e9, 0x95fde0ff, 0x049ffd05, 0x0a00008f, 0xfa059ffd, 0x010f01e9, 0x00031089, 0x90899f20, 0x1f940170, 0xf0f9bc0f, 0x800000d9, 0x05f9fd00, 0xde00f9ce, - 0x01000000, 0xfa059efd, 0x1ab201f9, 0x0015357e, 0x30f4a4bd, 0xf951fb04, 0x73108942, 0x0fa19401, + 0x01000000, 0xfa059efd, 0x1ab201f9, 0x00151b7e, 0x30f4a4bd, 0xf951fb04, 0x73108942, 0x0fa19401, 0x19bca0b2, 0x0000df10, 0x1fff0080, 0x00f9cef5, 0xfa0295f0, 0x588901f9, 0x11b8fe8b, 0xdf000198, - 0x00800000, 0xbcf51fff, 0xf9ce1019, 0xe495f000, 0x7e01f9fa, 0xb20067ab, 0x69047e0a, 0x7e0ab200, - 0xb3003aeb, 0xb22e02a4, 0x69e27e0a, 0x7e0ab200, 0xb3003af4, 0xb20a02a4, 0x698a7e0a, 0x7e0ab200, - 0xb3003af4, 0xb23e03a4, 0x683e7e0a, 0x27e13e00, 0x7e0ab200, 0xb3003aeb, 0xb22a03a4, 0x686a7e0a, - 0x7e0ab200, 0xb3003af4, 0xb20a03a4, 0x68c87e0a, 0x7e0ab200, 0xb3003af4, 0xb20a02a4, 0x68807e0a, - 0x7e0ab200, 0xb3003af4, 0xb20e04a0, 0x3af47e0a, 0x05a4b300, 0x7e0ab20a, 0x8900689c, 0xbc016900, - 0x00d91019, 0xff008000, 0x42ce4519, 0x001fb800, 0xf9ff0208, 0x0031ce35, 0x9d7e0ab2, 0xa033003a, - 0xf7091000, 0xfd1015f0, 0x363e0429, 0xef090028, 0xfd0825f0, 0x0ab20419, 0x003aa67e, 0x1000a033, - 0x15f0ef09, 0x0429fd01, 0x0028543e, 0x25f0fe09, 0x0419fd10, 0xaf7e0ab2, 0xa033003a, 0xfd091000, - 0xff021ec5, 0x723ef429, 0xfd090028, 0xff022fc5, 0x4ffae419, 0x013efa01, 0x2489f43d, 0x9f3c0003, - 0xf941fb09, 0x7ea1b222, 0xb2006a03, 0x3ae27e1a, 0x03a0b300, 0x3874890f, 0x98913c00, 0x0a019433, - 0x7f7e1ab2, 0x1ab20067, 0x003b1b7e, 0x0a00a033, 0x4e7e1ab2, 0x74890069, 0x913c0038, 0x00903398, - 0x7e1ab20a, 0x8900194d, 0x94010068, 0x00df0f10, 0xbc400000, 0x00d90009, 0xff008000, 0x9ffa9509, + 0x00800000, 0xbcf51fff, 0xf9ce1019, 0xe495f000, 0x7e01f9fa, 0xb20068b6, 0x688a7e0a, 0x7e0ab200, + 0xb3003acb, 0xb22e02a4, 0x684b7e0a, 0x7e0ab200, 0xb3003ad4, 0xb20a02a4, 0x692c7e0a, 0x7e0ab200, + 0xb3003ad4, 0xb23e03a4, 0x675f7e0a, 0x27c13e00, 0x7e0ab200, 0xb3003acb, 0xb22a03a4, 0x69a17e0a, + 0x7e0ab200, 0xb3003ad4, 0xb20a03a4, 0x69657e0a, 0x7e0ab200, 0xb3003ad4, 0xb20a02a4, 0x68037e0a, + 0x7e0ab200, 0xb3003ad4, 0xb20e04a0, 0x3ad47e0a, 0x05a4b300, 0x7e0ab20a, 0x890069b7, 0xbc016900, + 0x00d91019, 0xff008000, 0x42ce4519, 0x001fb800, 0xf9ff0208, 0x0031ce35, 0x7d7e0ab2, 0xa033003a, + 0xf7091000, 0xfd1015f0, 0x163e0429, 0xef090028, 0xfd0825f0, 0x0ab20419, 0x003a867e, 0x1000a033, + 0x15f0ef09, 0x0429fd01, 0x0028343e, 0x25f0fe09, 0x0419fd10, 0x8f7e0ab2, 0xa033003a, 0xfd091000, + 0xff021ec5, 0x523ef429, 0xfd090028, 0xff022fc5, 0x4ffae419, 0x013efa01, 0x2489f43d, 0x9f3c0003, + 0xf941fb09, 0x7ea1b222, 0xb20069e3, 0x3ac27e1a, 0x03a0b300, 0x3874890f, 0x98913c00, 0x0a019433, + 0x1f7e1ab2, 0x1ab20068, 0x003afb7e, 0x0a00a033, 0xc77e1ab2, 0x74890067, 0x913c0038, 0x00903398, + 0x7e1ab20a, 0x8900192f, 0x94010068, 0x00df0f10, 0xbc400000, 0x00d90009, 0xff008000, 0x9ffa9509, 0xff948f01, 0x040090fe, 0x800000d9, 0x9509ff00, 0xdf000fbc, 0x11000000, 0x89019ffa, 0x3c000324, - 0x24332891, 0x50892901, 0x1ab20100, 0x7e0009bc, 0xd9006502, 0x00800000, 0xce9509ff, 0x94f00099, + 0x24332891, 0x50892901, 0x1ab20100, 0x7e0009bc, 0xd90064e2, 0x00800000, 0xce9509ff, 0x94f00099, 0x0a0bf430, 0x00032889, 0xfb19923c, 0x02af9421, 0xbb05a994, 0x2c8f029f, 0xe4bd0003, 0xbd909fbc, 0x909fa0f4, 0x999001ee, 0x07e4b304, 0x039c89f8, 0xa99fbc00, 0x0003ac89, 0x89a99fbc, 0x3c0003bc, 0xc489a99f, 0x9fbc0003, 0x8900f8a9, 0x3c0003bc, 0x260f989a, 0x4f009033, 0x0003ac8e, 0xb0f8eabc, - 0x0cf406f6, 0x01f9901d, 0x94a9e9bc, 0x9abb03a9, 0x909fbc02, 0x00032c8f, 0x3ef8f9bc, 0x940029b6, + 0x0cf406f6, 0x01f9901d, 0x94a9e9bc, 0x9abb03a9, 0x909fbc02, 0x00032c8f, 0x3ef8f9bc, 0x94002996, 0xaf9402a9, 0x02f9bb05, 0x00032c89, 0xbff0f9bc, 0xbc0109ff, 0xa9b8a9e9, 0xb6000248, 0x9ffa0294, 0xb2f4bd01, 0xb800f8fa, 0x000248a9, 0xce0294b6, 0x9c8f009d, 0xfabc0003, 0x06e6b0e8, 0x90360cf4, 0xf9bc01e9, 0x03af94a9, 0xbc02fabb, 0x2c8ef0fe, 0xedbc0003, 0x03c08ff9, 0x0794b300, 0x3c01090b, 0x00f8a9f9, 0xf93c943d, 0x89f4bda9, 0xbc0003c4, 0x00f8a99f, 0x0003bc89, 0xf8a99b3c, 0x02a99400, - 0xaf9422f9, 0x12f9bc05, 0x00032c89, 0x981019bc, 0xa2b20510, 0x003b517e, 0x0bf40aa6, 0x3ea43d09, - 0x98002a57, 0x2ab20610, 0x003b5a7e, 0x9cf00aa6, 0x0196f00b, 0xfb019ac6, 0x02a99421, 0xaf9422f9, - 0x12f9bc05, 0x00032c89, 0x981019bc, 0xa2b20310, 0x003b3f7e, 0x0bf40aa6, 0x3ea43d09, 0x98002a93, - 0x2ab20410, 0x003b487e, 0x9cf00aa6, 0x0196f00b, 0xfb019ac6, 0xb212f921, 0x2a597ea0, 0xb2a13200, - 0x2a1d7e0a, 0x02099400, 0xbb050f94, 0x2c8902f9, 0xf9bc0003, 0x0ef9bff0, 0x0694b309, 0x00163028, + 0xaf9422f9, 0x12f9bc05, 0x00032c89, 0x981019bc, 0xa2b20510, 0x003b317e, 0x0bf40aa6, 0x3ea43d09, + 0x98002a37, 0x2ab20610, 0x003b3a7e, 0x9cf00aa6, 0x0196f00b, 0xfb019ac6, 0x02a99421, 0xaf9422f9, + 0x12f9bc05, 0x00032c89, 0x981019bc, 0xa2b20310, 0x003b1f7e, 0x0bf40aa6, 0x3ea43d09, 0x98002a73, + 0x2ab20410, 0x003b287e, 0x9cf00aa6, 0x0196f00b, 0xfb019ac6, 0xb212f921, 0x2a397ea0, 0xb2a13200, + 0x29fd7e0a, 0x02099400, 0xbb050f94, 0x2c8902f9, 0xf9bc0003, 0x0ef9bff0, 0x0694b309, 0x00163028, 0x300bfcf0, 0x9cf000a6, 0x00f0330b, 0x33030e0a, 0x0e120094, 0x00f43301, 0x33020e0c, 0x0e060094, 0x89eab20f, 0xbc0003c4, 0x11fb099e, 0x9402af94, 0x9fbb05a9, 0x032c8f02, 0x909fbc00, 0x9fa0060f, 0x01287089, 0xac9432f9, 0xbca1b20f, 0xb4bdc0c9, 0x0d03a994, 0x229abc01, 0x800000d3, 0x032c8000, 0x95c3ff00, 0xc70099ce, 0x9fc7509e, 0x0ae4b668, 0xb63f94f0, 0x2dbc06f4, 0x05f9fda0, 0xfd01b9c4, - 0xfe9405fe, 0x0094b310, 0xa90fbc0b, 0x002b5c3e, 0x90980abc, 0xe9ff01dd, 0xa909bc95, 0x9001bb90, - 0xb4b340cc, 0x1ab2bf04, 0x003b3f7e, 0x8f021994, 0x9400032c, 0x09bb0510, 0x000fbc02, 0xb2030ab5, - 0x3b487e1a, 0x040ab500, 0x517e1ab2, 0x0ab5003b, 0x7e1ab205, 0x89003b5a, 0xbd00039c, 0x199fbcf4, + 0xfe9405fe, 0x0094b310, 0xa90fbc0b, 0x002b3c3e, 0x90980abc, 0xe9ff01dd, 0xa909bc95, 0x9001bb90, + 0xb4b340cc, 0x1ab2bf04, 0x003b1f7e, 0x8f021994, 0x9400032c, 0x09bb0510, 0x000fbc02, 0xb2030ab5, + 0x3b287e1a, 0x040ab500, 0x317e1ab2, 0x0ab5003b, 0x7e1ab205, 0x89003b3a, 0xbd00039c, 0x199fbcf4, 0x0003ac89, 0xbc060ab5, 0x010f199f, 0x0003bc89, 0xfb199f3c, 0x27888931, 0xb299bf00, 0x0094b3af, - 0x3b688925, 0xb399bf00, 0xa6100194, 0x089cf0ab, 0x3e0196f0, 0x3d002bfb, 0xf4fba6a4, 0x010a2b0d, + 0x3b688925, 0xb399bf00, 0xa6100194, 0x089cf0ab, 0x3e0196f0, 0x3d002bdb, 0xf4fba6a4, 0x010a2b0d, 0x90b300f8, 0xa43d0801, 0x688900f8, 0x99bf003b, 0x0f0194b3, 0xfba6a43d, 0x320e0cf4, 0xa600f89a, 0x089cf0ab, 0x00f89a32, 0x0038d089, 0xa4b6e4bd, 0xa0abbc02, 0x89a99ebc, 0xbc002910, 0x3089a99e, 0x010d003a, 0x89a99dbc, 0x8f003b80, 0xbc00ffff, 0x6c89a99f, 0x9d3c003b, 0x3bd089a9, 0xa99e3c00, 0x00369089, 0x89a99ebc, 0xbc0037e8, 0x3089a99e, 0x9ebc0038, 0xf900f8a9, 0x02b99402, 0xae94d0b2, 0x04bd9404, 0xb006af94, 0x1df400c6, 0xf0efbc1d, 0x8e909dbc, 0xbc003550, 0xcfc4909f, 0x909ebc1f, - 0x3e20f5f0, 0xbc002c9d, 0x9dbcf0ef, 0x35508e90, 0x909fbc00, 0xbc01cfb9, 0xf4f0909e, 0x019fb51f, + 0x3e20f5f0, 0xbc002c7d, 0x9dbcf0ef, 0x35508e90, 0x909fbc00, 0xbc01cfb9, 0xf4f0909e, 0x019fb51f, 0x9404b994, 0xbf9406ad, 0xf0f9bc02, 0xbc04a994, 0xf9bc909d, 0x355089f0, 0x010eb900, 0xf0f0f9bc, - 0x94bd0fe4, 0xb502feb5, 0x01fb03f9, 0xb1b232f9, 0x087ea0b2, 0x2889002c, 0x050d003a, 0x94899da0, + 0x94bd0fe4, 0xb502feb5, 0x01fb03f9, 0xb1b232f9, 0xe87ea0b2, 0x2889002b, 0x050d003a, 0x94899da0, 0x0ab20039, 0x04b6140f, 0x0001bc02, 0x89099fbc, 0xa000382c, 0x3760899d, 0xbcf4bd00, 0xd889099f, 0xf10e0039, 0x89099ebc, 0x8200278c, 0xbc003710, 0x1bb2099e, 0x003b2883, 0xbc092ebc, 0xecb2093e, - 0x577eedb2, 0x20bc002c, 0x3830bcf8, 0x00387889, 0x890993bc, 0xbc003954, 0x31fb099f, 0x8e20a9c4, - 0xf4003a2c, 0xa9c40a0b, 0x2d503e1f, 0x01a9b900, 0xbfb9e9a0, 0x3c208901, 0xf89fa000, 0x9832f900, - 0xc19802c2, 0xb2b3b201, 0x2c087ea0, 0xb21ab200, 0x2d3c7e2b, 0x3c208900, 0x3a2c8f00, 0xbf9ebf00, + 0x377eedb2, 0x20bc002c, 0x3830bcf8, 0x00387889, 0x890993bc, 0xbc003954, 0x31fb099f, 0x8e20a9c4, + 0xf4003a2c, 0xa9c40a0b, 0x2d303e1f, 0x01a9b900, 0xbfb9e9a0, 0x3c208901, 0xf89fa000, 0x9832f900, + 0xc19802c2, 0xb2b3b201, 0x2be87ea0, 0xb21ab200, 0x2d1c7e2b, 0x3c208900, 0x3a2c8f00, 0xbf9ebf00, 0x387889ff, 0x0204b600, 0xbc0003bc, 0x5489099f, 0x9ebc0039, 0x9431fb09, 0x9bbc02a9, 0x37a489c0, 0xf89cbc00, 0x0036d089, 0x89e89cbc, 0x0d003a28, 0x899da001, 0xf4003994, 0x22f9ec30, 0xfa90a1b2, 0xc99abc02, 0x00371089, 0x9202e090, 0x9ebc02ee, 0x382c89c9, 0x92b2b200, 0x288b02ff, 0x9da0003b, 0x89c9bfbc, 0xbc003760, 0x1609c990, 0xf416f6b0, 0xeb090c1c, 0x1ff4f9a6, 0xbcea0908, 0xe6b0c9b9, - 0x0f1ef400, 0xbd021994, 0x9092bce4, 0x002e1f3e, 0xe9a6f209, 0x94121ff4, 0xf10e0219, 0x8f9092bc, - 0xbc003710, 0xa6b099fe, 0x0f1df416, 0x0e021994, 0x9092bc16, 0x002e473e, 0xa9a6eb09, 0x94121ff4, - 0xea0e0219, 0x8f9092bc, 0xbc003994, 0x06b099fe, 0x0f1ef400, 0xbd021994, 0x9092bce4, 0x002e6f3e, + 0x0f1ef400, 0xbd021994, 0x9092bce4, 0x002dff3e, 0xe9a6f209, 0x94121ff4, 0xf10e0219, 0x8f9092bc, + 0xbc003710, 0xa6b099fe, 0x0f1df416, 0x0e021994, 0x9092bc16, 0x002e273e, 0xa9a6eb09, 0x94121ff4, + 0xea0e0219, 0x8f9092bc, 0xbc003994, 0x06b099fe, 0x0f1ef400, 0xbd021994, 0x9092bce4, 0x002e4f3e, 0x09a6f209, 0x94121ff4, 0xf10e0219, 0x8f9092bc, 0xbc003760, 0x1f9499fe, 0x3b288902, 0xf0f2bc00, 0x89e89fbc, 0xbc003710, 0xd889089f, 0x9ebc0039, 0x278c89f9, 0xbc1ab200, 0xecb2f990, 0x0db22bb2, - 0x002c577e, 0x94042994, 0x2f94061e, 0xf0f9bc02, 0xbc041994, 0xf9bc909e, 0x355089f0, 0xf0f9bc00, + 0x002c377e, 0x94042994, 0x2f94061e, 0xf0f9bc02, 0xbc041994, 0xf9bc909e, 0x355089f0, 0xf0f9bc00, 0x4dfef9bf, 0x0cdd9001, 0xd9a01ab2, 0xb201f998, 0xb5dcb22b, 0xf99801d9, 0x02d9b502, 0xb503f998, - 0xff9803d9, 0x04dfb504, 0x002d5d7e, 0x891425fb, 0xb6003878, 0xabbc02a4, 0xa99cbca0, 0x00395489, + 0xff9803d9, 0x04dfb504, 0x002d3d7e, 0x891425fb, 0xb6003878, 0xabbc02a4, 0xa99cbca0, 0x00395489, 0xf8a99dbc, 0x02a99400, 0x9bbc42f9, 0x387889f0, 0x289fbc00, 0x0036908e, 0xf40026b0, 0x29c40d1d, - 0x2095f01f, 0x002f2e3e, 0xf00129b9, 0xe9bc1f94, 0x02a994f9, 0x89e09bbc, 0xbc003954, 0x3089489e, + 0x2095f01f, 0x002f0e3e, 0xf00129b9, 0xe9bc1f94, 0x02a994f9, 0x89e09bbc, 0xbc003954, 0x3089489e, 0xe88f0038, 0x9cbc0037, 0x0149b9e9, 0xbc0f94f0, 0xff89e9f9, 0xc9a600ff, 0x89650bf4, 0xbc003b6c, - 0xd93fd0e9, 0x8fffc0c4, 0x33003b80, 0x3d0f0194, 0xe9f0bc94, 0x853ed920, 0xfebc002f, 0xf409a698, - 0xf0bc060d, 0x02a994e9, 0x003a3083, 0xbc109bbc, 0x0ab2b831, 0x002bb57e, 0x2500a033, 0x2ab20bb2, - 0x0076ce7e, 0x0038d089, 0x9abc0bb2, 0x7e4ab219, 0x890076ce, 0xbc002910, 0x9abc1930, 0x8941fb19, + 0xd93fd0e9, 0x8fffc0c4, 0x33003b80, 0x3d0f0194, 0xe9f0bc94, 0x653ed920, 0xfebc002f, 0xf409a698, + 0xf0bc060d, 0x02a994e9, 0x003a3083, 0xbc109bbc, 0x0ab2b831, 0x002b957e, 0x2500a033, 0x2ab20bb2, + 0x0076ba7e, 0x0038d089, 0x9abc0bb2, 0x7e4ab219, 0x890076ba, 0xbc002910, 0x9abc1930, 0x8941fb19, 0x94003690, 0xfbbc02af, 0xa89fbcf0, 0x0037e889, 0x89e89fbc, 0xbc003830, 0xa4f0989f, 0x0fe4f03f, 0xb618a4b6, 0x94f110e4, 0xaefdffff, 0x05a9fd05, 0x808900f8, 0xa4b6003b, 0xa0abbc02, 0xf1a89abc, - 0xf8ef00a5, 0x00a6b000, 0x7e091df4, 0xf800768d, 0x08a4b600, 0x00768d7e, 0xf808a7b6, 0x00a6b000, - 0xb6121df4, 0x8d7e08a4, 0xaa900076, 0x08a7b6ff, 0x8d7e00f8, 0x00f80076, 0x7e08a4b6, 0x9000768d, + 0xf8ef00a5, 0x00a6b000, 0x7e091df4, 0xf8007679, 0x08a4b600, 0x0076797e, 0xf808a7b6, 0x00a6b000, + 0xb6121df4, 0x797e08a4, 0xaa900076, 0x08a7b6ff, 0x797e00f8, 0x00f80076, 0x7e08a4b6, 0x90007679, 0xa7b67faa, 0x8900f808, 0xbf0037a0, 0xb342f999, 0x94230090, 0x308f02a0, 0xd08e003a, 0xa4820038, - 0x10830037, 0xd0840029, 0x94b30036, 0xab3e6002, 0x30890030, 0xa094003a, 0x000bbc02, 0x891890bc, - 0xbc0038d0, 0x1bb2a890, 0x0030057e, 0x0037a489, 0x89099abc, 0xbc002910, 0x1bb2a890, 0x0030057e, - 0x0036d089, 0x3e099abc, 0xbc0030e8, 0xf0bc000b, 0xa8e0bc18, 0x1d7e1bb2, 0x2abc0030, 0xa830bc09, - 0x1d7e1bb2, 0xe53e0030, 0x0bbc0030, 0x18f0bc00, 0xb2a8e0bc, 0x30387e1b, 0x092abc00, 0xb2a830bc, - 0x30387e1b, 0x094abc00, 0x42f941fb, 0xb202e398, 0xb4b2b2a1, 0x40340690, 0x01e0981c, 0x18f4cda6, - 0x7e9cb237, 0xb2002f05, 0x7e3bb20a, 0x89002d3c, 0x8e003c20, 0xbf003a2c, 0x89eebf9d, 0x94003878, - 0xa43d021f, 0xbcf0f2bc, 0x5489f99e, 0x9dbc0039, 0x31683ef9, 0x7e9cb200, 0xb2002f05, 0x7e2bb21a, - 0x0a003047, 0xf44a2601, 0xa48f211b, 0x19940037, 0x9092bc02, 0x8fc8f9bc, 0xbc0036d0, 0x1ab2d8f9, - 0x577e2bb2, 0x4a32002c, 0xa99441fb, 0x8f42f902, 0xbc003bd0, 0x0fbc009b, 0xb2993f90, 0xb2b4b2a3, + 0x10830037, 0xd0840029, 0x94b30036, 0x8b3e6002, 0x30890030, 0xa094003a, 0x000bbc02, 0x891890bc, + 0xbc0038d0, 0x1bb2a890, 0x002fe57e, 0x0037a489, 0x89099abc, 0xbc002910, 0x1bb2a890, 0x002fe57e, + 0x0036d089, 0x3e099abc, 0xbc0030c8, 0xf0bc000b, 0xa8e0bc18, 0xfd7e1bb2, 0x2abc002f, 0xa830bc09, + 0xfd7e1bb2, 0xc53e002f, 0x0bbc0030, 0x18f0bc00, 0xb2a8e0bc, 0x30187e1b, 0x092abc00, 0xb2a830bc, + 0x30187e1b, 0x094abc00, 0x42f941fb, 0xb202e398, 0xb4b2b2a1, 0x40340690, 0x01e0981c, 0x18f4cda6, + 0x7e9cb237, 0xb2002ee5, 0x7e3bb20a, 0x89002d1c, 0x8e003c20, 0xbf003a2c, 0x89eebf9d, 0x94003878, + 0xa43d021f, 0xbcf0f2bc, 0x5489f99e, 0x9dbc0039, 0x31483ef9, 0x7e9cb200, 0xb2002ee5, 0x7e2bb21a, + 0x0a003027, 0xf44a2601, 0xa48f211b, 0x19940037, 0x9092bc02, 0x8fc8f9bc, 0xbc0036d0, 0x1ab2d8f9, + 0x377e2bb2, 0x4a32002c, 0xa99441fb, 0x8f42f902, 0xbc003bd0, 0x0fbc009b, 0xb2993f90, 0xb2b4b2a3, 0x009d33c1, 0xd88d00c3, 0x94890039, 0xd0bc0039, 0x9890bce8, 0x1ff4e9a6, 0x278c8926, 0xf890bc00, - 0x00376089, 0xa69890bc, 0x131cf4f9, 0x003a2889, 0xe9bc99bf, 0x09d9bc90, 0x0031e33e, 0x00278c8b, + 0x00376089, 0xa69890bc, 0x131cf4f9, 0x003a2889, 0xe9bc99bf, 0x09d9bc90, 0x0031c33e, 0x00278c8b, 0x00382c89, 0xbf023e94, 0xe0e4bc9c, 0x003b288d, 0xbcf8bebc, 0xd889d8de, 0xfcbc0039, 0xe99dbcf0, - 0xb2e9bfbc, 0xb23ab21c, 0x2f057e4b, 0x02399400, 0x0039d880, 0x812094bc, 0xbc00278c, 0x12bcc802, - 0xb23ab2d8, 0x2c577e4b, 0xe802bc00, 0x89d812bc, 0xbc003994, 0x7889f892, 0x9ebc0038, 0x39548929, + 0xb2e9bfbc, 0xb23ab21c, 0x2ee57e4b, 0x02399400, 0x0039d880, 0x812094bc, 0xbc00278c, 0x12bcc802, + 0xb23ab2d8, 0x2c377e4b, 0xe802bc00, 0x89d812bc, 0xbc003994, 0x7889f892, 0x9ebc0038, 0x39548929, 0x299dbc00, 0x1ef4efa6, 0x37608946, 0x9892bc00, 0x1ef4d9a6, 0x3bd0893a, 0x2029bc00, 0x29200109, - 0x00326c3e, 0x002f057e, 0x4bb23ab2, 0x0030477e, 0x0037a489, 0x89c890bc, 0xbc0036d0, 0x3ab2d890, - 0x577e4bb2, 0x010a002c, 0x00326e3e, 0x41fba43d, 0xb604bf94, 0xbfbc02b4, 0x35508fb0, 0x06ae9400, + 0x00324c3e, 0x002ee57e, 0x4bb23ab2, 0x0030277e, 0x0037a489, 0x89c890bc, 0xbc0036d0, 0x3ab2d890, + 0x377e4bb2, 0x010a002c, 0x00324e3e, 0x41fba43d, 0xb604bf94, 0xbfbc02b4, 0x35508fb0, 0x06ae9400, 0xbc04a4b6, 0xbabca0ae, 0xb0bfbcb0, 0x9ab2bfbf, 0xbf989fa0, 0x019fb501, 0xb502bf98, 0xbf98029f, 0x039fb503, 0xb504bb98, 0x00f8049b, 0x01738089, 0xbc0fa4b6, 0x00d9a0a9, 0xfd008000, 0xa9ce05a9, 0xfdfe0f00, 0xbfc4049f, 0x059ffd01, 0x4f01a9fa, 0xa9ce50b7, 0x0199c700, 0xa601ff92, 0x0b9cf09b, - 0x0c00f0b3, 0xee009033, 0x0032f23e, 0x90331b0a, 0xa4bd0600, 0xf08900f8, 0x9abc0004, 0xb3aeb2f8, + 0x0c00f0b3, 0xee009033, 0x0032d23e, 0x90331b0a, 0xa4bd0600, 0xf08900f8, 0x9abc0004, 0xb3aeb2f8, 0x0a2b00f0, 0xf4faa601, 0x2089431b, 0x9ebc0004, 0xf0020a98, 0x99920394, 0x0196b002, 0x892e0cf4, 0xbd002784, 0xe99f3ca4, 0x208900f8, 0x9abc0004, 0x0394f098, 0x0b0190b3, 0x9aa6030a, 0x3d0e1bf4, 0x278489f4, 0x3ca4bd00, 0x00f8e99f, 0x00042089, 0x89f89abc, 0xbc000500, 0xaeb2d89a, 0xb302f995, - 0xb03001d0, 0x08f401d6, 0xb3010a0d, 0x3e5c03d4, 0xf00033ab, 0x040a0194, 0x8f4f0bf4, 0x3d003950, - 0xe9f93c94, 0x00290c8f, 0x3ee9f93c, 0xf00033a7, 0x050a0294, 0x3d330bf4, 0x39508f94, 0xe9f93c00, + 0xb03001d0, 0x08f401d6, 0xb3010a0d, 0x3e5c03d4, 0xf000338b, 0x040a0194, 0x8f4f0bf4, 0x3d003950, + 0xe9f93c94, 0x00290c8f, 0x3ee9f93c, 0xf0003387, 0x050a0294, 0x3d330bf4, 0x39508f94, 0xe9f93c00, 0x00290c89, 0xbde99d3c, 0xf000f8a4, 0x060a0894, 0x0f170bf4, 0x39508901, 0x3ca4bd00, 0xf43de99f, 0x00290c89, 0xf8e99f3c, 0x04208900, 0xf89abc00, 0x00051089, 0xb2e89abc, 0x07f995ad, 0x1901e0b3, - 0xf401e6b0, 0x010a2608, 0x2c02e4b3, 0x0a0494f0, 0x33fa3e07, 0x0294f000, 0x90b3080a, 0x50891a00, + 0xf401e6b0, 0x010a2608, 0x2c02e4b3, 0x0a0494f0, 0x33da3e07, 0x0294f000, 0x90b3080a, 0x50891a00, 0xa4bd0037, 0xf8d99ebc, 0x89f4bd00, 0xbc003750, 0xa4bda99f, 0x208e00f8, 0xea3c0005, 0x33afb298, 0xbd080094, 0x8900f8a4, 0xbc000420, 0x0e0a989a, 0xf44094f0, 0x01090a0b, 0xe93ca4bd, 0x8900f8f9, 0xbc000420, 0x2489e89a, 0x9abc0005, 0xc7090df8, 0xefff4aee, 0xf49fa694, 0x94890c1b, 0xd4bd000a, @@ -474,24 +473,24 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0xf003b4f0, 0xf4b61ff4, 0x0f94f017, 0xb607e4f0, 0xe4b60294, 0x059bfd07, 0xfd07d4f0, 0xd4b6059e, 0xffc4f00a, 0xb6059dfd, 0x9cfd0fc4, 0x059ffd05, 0x0176848f, 0xbc0fa4b6, 0x00dfa0af, 0xfd008000, 0xa9fa05af, 0x8900f801, 0xb6010004, 0xa9bc0fa4, 0x0000d9a0, 0xa9fd0080, 0x00aace05, 0xc7080049, - 0xa0b35caa, 0xa6b04202, 0x140cf402, 0xa0b32009, 0x00493600, 0x01a4b301, 0x37643e2d, 0x04a0b300, - 0x40004915, 0xf404a6b0, 0xa4b31d08, 0x5a3e1805, 0x00890037, 0x643e0200, 0x00890037, 0x643e1000, + 0xa0b35caa, 0xa6b04202, 0x140cf402, 0xa0b32009, 0x00493600, 0x01a4b301, 0x37443e2d, 0x04a0b300, + 0x40004915, 0xf404a6b0, 0xa4b31d08, 0x3a3e1805, 0x00890037, 0x443e0200, 0x00890037, 0x443e1000, 0x94bd0037, 0x00f89ab2, 0x1489010f, 0x9fbc000a, 0xf8a4bda9, 0xb662f900, 0x60890fa4, 0xc2320128, 0xbd00a9bc, 0x109990c4, 0x800000d6, 0xa0a9bc00, 0xff44c005, 0xffff83f0, 0x01bf98f8, 0x9802bd98, - 0x243303b1, 0xa6ff0b00, 0x37b03ee5, 0xe506ff00, 0xf000e9ce, 0x95fd3ff4, 0x059ffd04, 0xb60fdfc4, + 0x243303b1, 0xa6ff0b00, 0x37903ee5, 0xe506ff00, 0xf000e9ce, 0x95fd3ff4, 0x059ffd04, 0xb60fdfc4, 0x94fd08f4, 0x059ffd04, 0xfd071fc4, 0xf4b60493, 0x059ffd10, 0x9001e9fa, 0xaa9001cc, 0x14bb9040, 0xb3400090, 0xfbb604c4, 0x02af9461, 0x003a988e, 0xbcf0fbbc, 0x52f9d8ef, 0x001a588e, 0xdf94a2b2, 0x899ab204, 0xb2003950, 0x58923cb4, 0xd99434bd, 0xbc14bd02, 0x04bd909f, 0xbdf09ebc, 0x17d88eb4, - 0xbc030c00, 0x5b3e909e, 0x54330038, 0x93981600, 0x03919804, 0x98029098, 0x9cbf019b, 0x00384e3e, + 0xbc030c00, 0x3b3e909e, 0x54330038, 0x93981600, 0x03919804, 0x98029098, 0x9cbf019b, 0x00382e3e, 0xf398fcbf, 0x03f19804, 0x9802f098, 0xdd9001fb, 0x14999001, 0xb314ff90, 0x0e1100c0, 0x00503320, 0xa6010e06, 0xc508f4de, 0x8f022994, 0xbc003a98, 0xfdbc9094, 0x04a3b599, 0xb503a1b5, 0xabb502a0, 0xfbaca001, 0x00188f51, 0x0fa99401, 0xdf909fbc, 0x00800000, 0xcee59fff, 0x848900ef, 0x9a3c0027, - 0x01943398, 0x0000d910, 0xf9ff4000, 0x38b93e95, 0xffffd900, 0xf9ffbfff, 0x01e9fa94, 0x02f900f8, + 0x01943398, 0x0000d910, 0xf9ff4000, 0x38993e95, 0xffffd900, 0xf9ffbfff, 0x01e9fa94, 0x02f900f8, 0x800000df, 0x0fa99400, 0x0100188e, 0xff909ebc, 0x0cce059f, 0xf899b800, 0x9fff002d, 0x00beceb5, 0x0ffc99b8, 0xd59fff00, 0x8900dfce, 0x3c003950, 0x9433989a, 0x00d91601, 0xf0100000, 0xf5f010e5, - 0x95c9ff10, 0x0039183e, 0xf9fdef09, 0x04e9fd04, 0xffffffd9, 0x94c9ffef, 0xfa0109fa, 0xdffa01be, + 0x95c9ff10, 0x0038f83e, 0xf9fdef09, 0x04e9fd04, 0xffffffd9, 0x94c9ffef, 0xfa0109fa, 0xdffa01be, 0x8f01fb01, 0x94010018, 0x9fbc0fa9, 0x0000df90, 0x9fff0080, 0x00efcee5, 0x00290c89, 0x33989a3c, - 0x09100194, 0x94f9ffe0, 0x3e0895f0, 0x09003954, 0x94f9ffe0, 0xf801e9fa, 0x0fae9400, 0x01001889, + 0x09100194, 0x94f9ffe0, 0x3e0895f0, 0x09003934, 0x94f9ffe0, 0xf801e9fa, 0x0fae9400, 0x01001889, 0x800000dd, 0xe0e9bc00, 0xced5edff, 0x508900df, 0x9abc0037, 0xffffd9c8, 0xf9fdf3ff, 0x03c4f004, 0xfd1ac994, 0xdffa05f9, 0x0000d901, 0xeeb80080, 0xfd002fe8, 0xe9ce05e9, 0xffffdf00, 0xc4b6ff3f, 0x049ffd16, 0xfa059cfd, 0x00f801e9, 0x1489f4bd, 0x9fbc000a, 0xbd00f8a9, 0x0a2489f4, 0xa99fbc00, @@ -508,283 +507,283 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0xf89abf00, 0xbeefdf00, 0xec89dead, 0x9fa00003, 0x008900f8, 0x9abc0005, 0x8900f8a8, 0xbc003750, 0x96b0989a, 0x0bacf000, 0xf801a6f0, 0x0ba48900, 0xa89a3c00, 0xa88900f8, 0x9a3c000b, 0x8900f8a8, 0xbc000440, 0x00f8a89a, 0x00045089, 0xf8a89abc, 0x04608900, 0xa89abc00, 0x708900f8, 0x9abc0004, - 0x8900f8a8, 0xbc000614, 0xb4b3a99b, 0xbdb21109, 0x020bc4bd, 0x3e0dac4e, 0xb2003b84, 0x0bc4bdbd, + 0x8900f8a8, 0xbc000614, 0xb4b3a99b, 0xbdb21109, 0x020bc4bd, 0x3e0dac4e, 0xb2003b64, 0x0bc4bdbd, 0x09c44e02, 0x0005e67e, 0xafb200f8, 0x5933b0b3, 0xf433b6b0, 0xb0b3130c, 0xb0b32430, 0xb4b31831, - 0xc93e6e0c, 0xb0b3003b, 0xb4b35634, 0xd83e6236, 0x4489003b, 0xdc3e000a, 0x4089003b, 0x9abc0004, - 0x045089c8, 0x3bf03e00, 0x0a648900, 0xc89abc00, 0x000a5489, 0x003bf03e, 0x000ae489, 0xbdd89fbc, - 0x3bf33ec4, 0x0ab48900, 0xc89abc00, 0x000ac489, 0x4ed89fbc, 0xe67e09c4, 0x00f80005, 0x000ad489, + 0xa93e6e0c, 0xb0b3003b, 0xb4b35634, 0xb83e6236, 0x4489003b, 0xbc3e000a, 0x4089003b, 0x9abc0004, + 0x045089c8, 0x3bd03e00, 0x0a648900, 0xc89abc00, 0x000a5489, 0x003bd03e, 0x000ae489, 0xbdd89fbc, + 0x3bd33ec4, 0x0ab48900, 0xc89abc00, 0x000ac489, 0x4ed89fbc, 0xe67e09c4, 0x00f80005, 0x000ad489, 0xbdd89abc, 0x09c44ec4, 0x0005e67e, 0xe48900f8, 0x9abc0006, 0xb262f9f8, 0x00f0b3a3, 0xa6010a10, - 0x8b1bf5fa, 0x3c503e00, 0x39508900, 0x989a3c00, 0x14019033, 0x001acb7e, 0x7fd9010f, 0xa60206cc, - 0x050cf4a9, 0x0802f4bd, 0x1d00f0b3, 0x003c633e, 0x00395089, 0x3398933c, 0x020c0194, 0x3ef4bd08, - 0x02003c65, 0x01f9c404, 0x940f3094, 0x14bd1794, 0x01287089, 0x800000d6, 0x0009bc00, 0x7fffffd5, + 0x8b1bf5fa, 0x3c303e00, 0x39508900, 0x989a3c00, 0x14019033, 0x001aad7e, 0x7fd9010f, 0xa60206cc, + 0x050cf4a9, 0x0802f4bd, 0x1d00f0b3, 0x003c433e, 0x00395089, 0x3398933c, 0x020c0194, 0x3ef4bd08, + 0x02003c45, 0x01f9c404, 0x940f3094, 0x14bd1794, 0x01287089, 0x800000d6, 0x0009bc00, 0x7fffffd5, 0xf506ffff, 0xfd00f9ce, 0x94fd0495, 0x01f9fa05, 0x21bc060b, 0x400090d4, 0xb2081190, 0x4ec4bd3a, 0xe67e09c4, 0x14b30005, 0xa4bddb20, 0x30f461fb, 0xb282f9c4, 0xf830f4a2, 0xa701b9b3, 0x01b6b000, - 0xb31108f4, 0x02f002b9, 0xcd04bdb3, 0x3d5f3e03, 0x38b88900, 0x3c010f00, 0xa994a99f, 0x04ae9406, + 0xb31108f4, 0x02f002b9, 0xcd04bdb3, 0x3d3f3e03, 0x38b88900, 0x3c010f00, 0xa994a99f, 0x04ae9406, 0x8930e9bc, 0xb20027cc, 0x3039bce5, 0x0039208f, 0x00391089, 0xd0b2c6b2, 0xbc505fbc, 0x14bd40e9, 0xe8870708, 0x508e0003, 0xe23c0039, 0x01943398, 0xb501a016, 0x08b50101, 0x0301b502, 0x3e0401b5, - 0x0f003d35, 0xb5010904, 0x0fb50101, 0x0301b502, 0xa00409b5, 0x98723c01, 0x0e019433, 0x3bb20ab2, - 0xe87e140c, 0x6ebf0076, 0x90143390, 0x00900466, 0x904ea014, 0x45a60444, 0x3eae1bf4, 0x890040a3, + 0x0f003d15, 0xb5010904, 0x0fb50101, 0x0301b502, 0xa00409b5, 0x98723c01, 0x0e019433, 0x3bb20ab2, + 0xd47e140c, 0x6ebf0076, 0x90143390, 0x00900466, 0x904ea014, 0x45a60444, 0x3eae1bf4, 0x89004083, 0x3c003950, 0x200f9892, 0x330ef1b0, 0x09090090, 0x0e91b001, 0x8f042e94, 0xbc003a98, 0xc089f0ef, 0xf1b00038, 0x022f9413, 0xb090f9bc, 0x22bc1191, 0x9092bc90, 0xb00694b6, 0x88890d91, 0xf9bc003a, 0x3b808980, 0x90e9bc00, 0x890f91b0, 0xbc003910, 0x44fe90e9, 0x1091b001, 0xd889d1b2, 0xc1b0003a, - 0x70f9bc12, 0xe88f34bd, 0x4490003a, 0x60efbc54, 0x9d33893f, 0xb2009500, 0xb22ab249, 0x37e97e3b, + 0x70f9bc12, 0xe88f34bd, 0x4490003a, 0x60efbc54, 0x9d33893f, 0xb2009500, 0xb22ab249, 0x37c97e3b, 0xb449bf00, 0x3bb20ed0, 0x19a02ab2, 0xb5014e98, 0x4f98011e, 0xb54eb202, 0x4998021f, 0x0319b503, 0xbf044f98, 0x041fb519, 0xf0b449a0, 0x01199813, 0x49b5fcbf, 0x021f9801, 0x98024fb5, 0x49b50319, - 0x1290b403, 0xb5041f98, 0x99bf044f, 0x003a808f, 0x3c0091b0, 0xf130f8f2, 0x30ea7e04, 0xbf3bb200, - 0xb28a2060, 0x2fbf7e2a, 0x0de0b400, 0x8f010990, 0xa0002950, 0x9033bc69, 0xb69093bc, 0xe9bc0494, + 0x1290b403, 0xb5041f98, 0x99bf044f, 0x003a808f, 0x3c0091b0, 0xf130f8f2, 0x30ca7e04, 0xbf3bb200, + 0xb28a2060, 0x2f9f7e2a, 0x0de0b400, 0x8f010990, 0xa0002950, 0x9033bc69, 0xb69093bc, 0xe9bc0494, 0x9090bc90, 0x3f99fabc, 0x015d3385, 0x80890105, 0x923c003a, 0x000d3308, 0xe0b400be, 0x33e93f11, - 0xb23b0194, 0x7e3bb22a, 0xb4002d97, 0x49b211f0, 0x3bb22ab2, 0x707ef020, 0x49bf0032, 0x4e9819a0, - 0x011eb501, 0xb5024f98, 0x4998021f, 0x0319b503, 0xb5044e98, 0x1d3e041e, 0x793f003f, 0x61009433, - 0xb212f0b4, 0xbf2ab23b, 0x316a7efc, 0x2049b200, 0xb23bb27a, 0x32707e2a, 0xb249bf00, 0xa03bb22a, - 0x014e9819, 0x98011eb5, 0x1fb5024f, 0x03499802, 0x980319b5, 0x1eb5044e, 0x7e60bf04, 0xbc002fbf, + 0xb23b0194, 0x7e3bb22a, 0xb4002d77, 0x49b211f0, 0x3bb22ab2, 0x507ef020, 0x49bf0032, 0x4e9819a0, + 0x011eb501, 0xb5024f98, 0x4998021f, 0x0319b503, 0xb5044e98, 0xfd3e041e, 0x793f003e, 0x61009433, + 0xb212f0b4, 0xbf2ab23b, 0x314a7efc, 0x2049b200, 0xb23bb27a, 0x32507e2a, 0xb249bf00, 0xa03bb22a, + 0x014e9819, 0x98011eb5, 0x1fb5024f, 0x03499802, 0x980319b5, 0x1eb5044e, 0x7e60bf04, 0xbc002f9f, 0x508e9033, 0x0f900029, 0xb46fa001, 0x93bc0df0, 0x0494b690, 0xbc90f9bc, 0xeabc9090, 0x337f3f99, - 0xb44f01f4, 0xe9bf0fe0, 0x0038b88e, 0x3e29ef3c, 0xb2003f65, 0xb22ab249, 0x32707e3b, 0xa049bf00, + 0xb44f01f4, 0xe9bf0fe0, 0x0038b88e, 0x3e29ef3c, 0xb2003f45, 0xb22ab249, 0x32507e3b, 0xa049bf00, 0x014e9819, 0x98011eb5, 0x1fb5024f, 0x03499802, 0xb50ff0b4, 0x4e980319, 0x041eb504, 0xb88ef9bf, 0xe53c0038, 0x10f0b429, 0xef0095f1, 0x90b4f9a0, 0x10e0b40f, 0x9011f0b4, 0x99900133, 0x04ee9004, 0xb00f91b0, 0x90b410e1, 0x13e0b412, 0xb001ff90, 0x999011f1, 0x04ee9004, 0xb01291b0, 0x889013e1, - 0x14119001, 0x90017790, 0x3db30466, 0x3efe2604, 0x8f0040a3, 0x94003910, 0xae9404a9, 0x809fbc02, + 0x14119001, 0x90017790, 0x3db30466, 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0x0037e48f, 0x3398f13c, 0x00bf009d, 0xf93c0109, 0xf5a92619, - 0xb200861b, 0x65ef7e1a, 0x0f109400, 0x01287089, 0x09bc24bd, 0x0000d300, 0x03ff0080, 0x0099ce95, + 0xc71cfd95, 0x9fbc78ff, 0x07848909, 0x099dbc00, 0x0047ff3e, 0x0009e489, 0xbd02ac94, 0xc0c9bcd4, + 0x0044ca7e, 0x0009e489, 0x89f890bc, 0xc7000a04, 0xf4f002fe, 0x099ebc01, 0x0009f489, 0xfb099fbc, + 0xac30f401, 0xa1b232f9, 0x0018c77e, 0x0037e48f, 0x3398f13c, 0x00bf009d, 0xf93c0109, 0xf5a92619, + 0xb200861b, 0x65cf7e1a, 0x0f109400, 0x01287089, 0x09bc24bd, 0x0000d300, 0x03ff0080, 0x0099ce95, 0x93fd040d, 0x40009004, 0x060094b3, 0xd2bb080d, 0x901ab204, 0x060b0822, 0xc44ec4bd, 0x05e67e09, - 0x2024b300, 0xbd020bd9, 0xfe1ab2d4, 0x00900140, 0x7e0cb260, 0x4b0044ea, 0x1ab2030a, 0x003b637e, - 0x010f0bbf, 0x0038b889, 0x0f199f3c, 0x3bc08901, 0x199fbc00, 0x030abeb3, 0xbd1ab23e, 0x48f77ec4, - 0x48f43e00, 0x06d48900, 0xb891bc00, 0xb20140fe, 0x1000901a, 0xf97e0cb2, 0x1ab20041, 0xc43d0bb2, - 0x0037757e, 0x0b0b1ab2, 0x248d010c, 0x087e00f4, 0xa4bd0017, 0xb35435fb, 0x5b010aba, 0x010ab6b1, - 0xb3140cf4, 0xb3490ab0, 0x280109ba, 0x1709b4b3, 0x0049273e, 0x0309bab3, 0x0abab32b, 0xbab35803, - 0x0a190209, 0xb200f801, 0x52847ecb, 0xb200f800, 0x4eb37ecb, 0xb200f800, 0x49b67ecb, 0x0f00f800, - 0x0a148901, 0xa99fbc00, 0x00495d3e, 0x0048217e, 0xd48900f8, 0x9a3c0039, 0x00903398, 0xf8a4bd08, - 0x3be08900, 0x04ab9400, 0x7eb0b9bc, 0xf8005419, 0x43cd7e00, 0xf400f800, 0x22f9fc30, 0xc1b2b0b2, - 0xcbb2a2b2, 0x003b637e, 0x290000b3, 0x40fe020b, 0x902ab201, 0xd4bd0c00, 0xea7e0cb2, 0x0bbf0044, - 0x1bf4b1a6, 0xbd2ab20f, 0x48f77ec4, 0x49b33e00, 0xfba4bd00, 0x300b0425, 0xf9e830f4, 0xf4a0b252, - 0x0c7eec30, 0x0ab20045, 0x0c7e0c0b, 0x0ab20045, 0x0035c37e, 0x00093489, 0x929890bc, 0x96b00499, - 0x090cf401, 0xa67e0ab2, 0x0ab20069, 0x0c7e310b, 0x74890045, 0x90bc0006, 0x04c089f8, 0x9890bc00, - 0x0bf4f9a6, 0x0b0ab213, 0x7e080c19, 0x0a000261, 0x4ead3e08, 0x06848900, 0xe890bc00, 0x00050089, - 0xa69890bc, 0x130bf4e9, 0x190b0ab2, 0x617e090c, 0x090a0002, 0x004ead3e, 0x00069489, 0x89f890bc, - 0xbc000510, 0xf9a69890, 0xb2130bf4, 0x0c190b0a, 0x02617e0a, 0x3e0a0a00, 0xb3004ead, 0xb31800f0, - 0xb21401e4, 0x0c190b0a, 0x02617e0b, 0x3e0b0a00, 0xb2004ead, 0x7e360b0a, 0x8900450c, 0xbc0009f4, + 0x2024b300, 0xbd020bd9, 0xfe1ab2d4, 0x00900140, 0x7e0cb260, 0x4b0044ca, 0x1ab2030a, 0x003b437e, + 0x010f0bbf, 0x0038b889, 0x0f199f3c, 0x3bc08901, 0x199fbc00, 0x030abeb3, 0xbd1ab23e, 0x48d77ec4, + 0x48d43e00, 0x06d48900, 0xb891bc00, 0xb20140fe, 0x1000901a, 0xd97e0cb2, 0x1ab20041, 0xc43d0bb2, + 0x0037557e, 0x0b0b1ab2, 0x248d010c, 0xee7e00f4, 0xa4bd0016, 0xb35435fb, 0x5b010aba, 0x010ab6b1, + 0xb3140cf4, 0xb3490ab0, 0x280109ba, 0x1709b4b3, 0x0049073e, 0x0309bab3, 0x0abab32b, 0xbab35803, + 0x0a190209, 0xb200f801, 0x52647ecb, 0xb200f800, 0x4e937ecb, 0xb200f800, 0x49967ecb, 0x0f00f800, + 0x0a148901, 0xa99fbc00, 0x00493d3e, 0x0048017e, 0xd48900f8, 0x9a3c0039, 0x00903398, 0xf8a4bd08, + 0x3be08900, 0x04ab9400, 0x7eb0b9bc, 0xf80053f9, 0x43ad7e00, 0xf400f800, 0x22f9fc30, 0xc1b2b0b2, + 0xcbb2a2b2, 0x003b437e, 0x290000b3, 0x40fe020b, 0x902ab201, 0xd4bd0c00, 0xca7e0cb2, 0x0bbf0044, + 0x1bf4b1a6, 0xbd2ab20f, 0x48d77ec4, 0x49933e00, 0xfba4bd00, 0x300b0425, 0xf9e830f4, 0xf4a0b252, + 0xec7eec30, 0x0ab20044, 0xec7e0c0b, 0x0ab20044, 0x0035a37e, 0x00093489, 0x929890bc, 0x96b00499, + 0x090cf401, 0x8b7e0ab2, 0x0ab20067, 0xec7e310b, 0x74890044, 0x90bc0006, 0x04c089f8, 0x9890bc00, + 0x0bf4f9a6, 0x0b0ab213, 0x7e080c19, 0x0a000261, 0x4e8d3e08, 0x06848900, 0xe890bc00, 0x00050089, + 0xa69890bc, 0x130bf4e9, 0x190b0ab2, 0x617e090c, 0x090a0002, 0x004e8d3e, 0x00069489, 0x89f890bc, + 0xbc000510, 0xf9a69890, 0xb2130bf4, 0x0c190b0a, 0x02617e0a, 0x3e0a0a00, 0xb3004e8d, 0xb31800f0, + 0xb21401e4, 0x0c190b0a, 0x02617e0b, 0x3e0b0a00, 0xb2004e8d, 0x7e360b0a, 0x890044ec, 0xbc0009f4, 0x94b39890, 0x010f0d00, 0x0003d489, 0x89099f3c, 0xbc000a04, 0x94b39890, 0x010f0d00, 0x0003d889, - 0xb2099f3c, 0x36357e0a, 0x05c48900, 0x05748f00, 0x9890bc00, 0xfdf8f0bc, 0x1bf4049f, 0x89010f0c, + 0xb2099f3c, 0x36157e0a, 0x05c48900, 0x05748f00, 0x9890bc00, 0xfdf8f0bc, 0x1bf4049f, 0x89010f0c, 0x3c0003dc, 0xd489099f, 0x848f0005, 0x90bc0005, 0xf8f0bc98, 0xf4049ffd, 0x010f0c1b, 0x0003e089, 0x89099f3c, 0x8f0005e4, 0xbc000594, 0xf0bc9890, 0x049ffdf8, 0x0f0c1bf4, 0x03e48901, 0x099f3c00, - 0x330b0ab2, 0x00450c7e, 0x000a9489, 0x89f890bc, 0xbc000884, 0x0109e890, 0xbbfff4f0, 0xf9fd049e, - 0x131bf404, 0x190b0ab2, 0x617e0d0c, 0x0d0a0002, 0x004ead3e, 0x01309c89, 0x8f0f0194, 0xbcfecf64, + 0x330b0ab2, 0x0044ec7e, 0x000a9489, 0x89f890bc, 0xbc000884, 0x0109e890, 0xbbfff4f0, 0xf9fd049e, + 0x131bf404, 0x190b0ab2, 0x617e0d0c, 0x0d0a0002, 0x004e8d3e, 0x01309c89, 0x8f0f0194, 0xbcfecf64, 0x00d91019, 0xff008000, 0x1fbc4519, 0x004fce10, 0x000af489, 0xd9e890bc, 0x7fffffff, 0xb004f9fd, 0x9cf000e6, 0x1f94b60b, 0xfa05f9fd, 0x3489014f, 0x90bc0007, 0x074489e8, 0xf890bc00, 0x00079489, 0x90d890bc, 0xffbc01ee, 0x909fbc90, 0xbb039992, 0x348904e9, 0x9ebc0008, 0xf4eda609, 0x0ab21318, - 0x100c190b, 0x0002617e, 0xad3e100a, 0x5489004e, 0x90bc0007, 0x076489e8, 0xf890bc00, 0x0007c489, + 0x100c190b, 0x0002617e, 0x8d3e100a, 0x5489004e, 0x90bc0007, 0x076489e8, 0xf890bc00, 0x0007c489, 0x90d890bc, 0xff9001ee, 0x08448201, 0x90ffbc00, 0xbb909fbc, 0x2ebc04e9, 0xf4eda609, 0x0ab21318, - 0x110c190b, 0x0002617e, 0xad3e110a, 0x0ab2004e, 0x001acb7e, 0xbdd820bc, 0x0191b094, 0x090091b0, + 0x110c190b, 0x0002617e, 0x8d3e110a, 0x0ab2004e, 0x001aad7e, 0xbdd820bc, 0x0191b094, 0x090091b0, 0x05a5950b, 0xfe0143fe, 0x33900142, 0x34229038, 0xb00291b0, 0x21b00331, 0xb20ab204, 0xbdc4bd5b, - 0x41197ee4, 0x00adb300, 0x34890288, 0xcc8f0120, 0x19bcfedf, 0x0000dc10, 0x1cff0080, 0x101fbcc5, + 0x40f97ee4, 0x00adb300, 0x34890288, 0xcc8f0120, 0x19bcfedf, 0x0000dc10, 0x1cff0080, 0x101fbcc5, 0xbf00c9ce, 0xb82dbf3e, 0x002833ff, 0xb6049ffd, 0xd4f10be4, 0xe4f107ff, 0x004fffff, 0x059efdf8, 0xfd049ffd, 0xc9fa059d, 0x08448901, 0xd890bc00, 0x91b094bd, 0x00c84901, 0x090091b0, 0x0143fe0b, - 0x900142fe, 0x22903033, 0x0291b02c, 0xb00331b0, 0x0ab20421, 0xc4bd5bb2, 0x197ee4bd, 0xadb30041, + 0x900142fe, 0x22903033, 0x0291b02c, 0xb00331b0, 0x0ab20421, 0xc4bd5bb2, 0xf97ee4bd, 0xadb30040, 0xce020f00, 0x3ebf0049, 0xff8f2dbf, 0x9ffdff07, 0x0be4b604, 0x07ffd4f1, 0xffffe4f1, 0xfdf8004f, 0x9ffd059e, 0x059dfd04, 0x890149fa, 0xd40130ac, 0x00800000, 0x8f1019bc, 0xfffecf54, 0x1fbc9514, 0x0099ce10, 0x0008448f, 0xc7d8f0bc, 0x99e78d9f, 0x9fbb0142, 0x0191b004, 0xb000c849, 0x0b090091, - 0xfe0143fe, 0x33900142, 0x3c229040, 0xb00291b0, 0x21b00331, 0xb20ab204, 0xbdc4bd5b, 0x41197ee4, + 0xfe0143fe, 0x33900142, 0x3c229040, 0xb00291b0, 0x21b00331, 0xb20ab204, 0xbdc4bd5b, 0x40f97ee4, 0x00adb300, 0xa889018c, 0x588f0130, 0x19bcfecf, 0xa514ff10, 0xce101fbc, 0x3ebf00af, 0xac892dbf, 0xfcc7000b, 0x099cbc8d, 0x000bbc89, 0x0142fbe7, 0x89099bbc, 0xf0fc1fff, 0xf9fd1fe4, 0x0de4b604, - 0xfde00349, 0xd4f105fe, 0xf9fd07ff, 0x02d4b604, 0xfa05fdfd, 0x340b01af, 0x0c7e0ab2, 0x74890045, + 0xfde00349, 0xd4f105fe, 0xf9fd07ff, 0x02d4b604, 0xfa05fdfd, 0x340b01af, 0xec7e0ab2, 0x74890044, 0x90bc0007, 0x078489e8, 0x9890bc00, 0x0007f48f, 0x90f8f0bc, 0x999001ee, 0x0294b601, 0x89d4e9bc, - 0xbc000814, 0xdfa6099d, 0xb21318f4, 0x0c190b0a, 0x02617e12, 0x3e120a00, 0x94004ead, 0x248f0202, - 0x2fbc0008, 0xb25bb290, 0x0091b00a, 0xe4bdc4bd, 0x0040ab7e, 0xd900adb3, 0x00048900, 0x1019bc01, + 0xbc000814, 0xdfa6099d, 0xb21318f4, 0x0c190b0a, 0x02617e12, 0x3e120a00, 0x94004e8d, 0x248f0202, + 0x2fbc0008, 0xb25bb290, 0x0091b00a, 0xe4bdc4bd, 0x00408b7e, 0xd900adb3, 0x00048900, 0x1019bc01, 0x800000d9, 0xa519ff00, 0x8900aece, 0xbc000824, 0xf0b3f890, 0xf4f11500, 0x004907ff, 0x94e9fff8, - 0x3e059ffd, 0xd9004e0f, 0x80000000, 0xfa95e9ff, 0xa48901a9, 0x90bc0006, 0x0aa489e8, 0xf890bc00, - 0x9ebb0109, 0xfff4f104, 0x04f9fdff, 0xb2131bf4, 0x0c190b0a, 0x02617e06, 0x3e060a00, 0x89004ead, + 0x3e059ffd, 0xd9004def, 0x80000000, 0xfa95e9ff, 0xa48901a9, 0x90bc0006, 0x0aa489e8, 0xf890bc00, + 0x9ebb0109, 0xfff4f104, 0x04f9fdff, 0xb2131bf4, 0x0c190b0a, 0x02617e06, 0x3e060a00, 0x89004e8d, 0xbc0006d4, 0xe4b3099e, 0x80890b01, 0x9e3c003a, 0x06b48909, 0xd890bc00, 0x000aa489, 0x8f9890bc, 0xde010000, 0x00ff0000, 0xfd04fdbb, 0x9ffd049e, 0x131bf404, 0x190b0ab2, 0x617e070c, 0x070a0002, - 0x004ead3e, 0x0006e489, 0x9dbc0ab2, 0x36967e09, 0x06c48f00, 0xbc0ab200, 0x030bc02f, 0xea7ed4bd, - 0x0ab20044, 0x094c010b, 0x49777e03, 0x1430f400, 0x891855fb, 0xbc0004c0, 0xf089f89a, 0x9abc0004, + 0x004e8d3e, 0x0006e489, 0x9dbc0ab2, 0x36767e09, 0x06c48f00, 0xbc0ab200, 0x030bc02f, 0xca7ed4bd, + 0x0ab20044, 0x094c010b, 0x49577e03, 0x1430f400, 0x891855fb, 0xbc0004c0, 0xf089f89a, 0x9abc0004, 0x050089d8, 0xe89abc00, 0x00051089, 0xf0989abc, 0xf4f001d4, 0x0fe4f003, 0xb60f94f0, 0xe4b61094, - 0x04f4b608, 0xfd05fdfd, 0xf9fd05fe, 0x0a448905, 0xbc22f900, 0xa0b2a99f, 0x310bb2b2, 0x003b8a7e, - 0x300b0ab2, 0x003b8a7e, 0x00049089, 0x89d890bc, 0xbc0004b0, 0xa089e890, 0x90bc0004, 0x048089f8, + 0x04f4b608, 0xfd05fdfd, 0xf9fd05fe, 0x0a448905, 0xbc22f900, 0xa0b2a99f, 0x310bb2b2, 0x003b6a7e, + 0x300b0ab2, 0x003b6a7e, 0x00049089, 0x89d890bc, 0xbc0004b0, 0xa089e890, 0x90bc0004, 0x048089f8, 0x9890bc00, 0xb618dc94, 0xf4f108f4, 0x94f0ffff, 0x05f9fdff, 0x000a6489, 0xb608d5b6, 0xedfd1ae4, - 0x099ebc05, 0x2e000089, 0x8905f9fd, 0xfd000a54, 0x0ab205fc, 0x0b099fbc, 0x3b8a7e0c, 0x05f48900, + 0x099ebc05, 0x2f000089, 0x8905f9fd, 0xfd000a54, 0x0ab205fc, 0x0b099fbc, 0x3b6a7e0c, 0x05f48900, 0xf890bc00, 0x0005a489, 0x89d890bc, 0xbc000604, 0xb489e890, 0x90bc0005, 0x04fdfd98, 0xb201fdc4, 0x04e9fd0a, 0x000b8489, 0x8f099fbc, 0xc4000b94, 0xfebc01e9, 0x0294b609, 0x000ae48f, 0x0b059dfd, - 0x09f9bc36, 0x003b8a7e, 0x00087489, 0x89f890bc, 0xbc000524, 0xf9fd9890, 0x131bf404, 0x190b0ab2, - 0x617e030c, 0x030a0002, 0x0052823e, 0xf404f9c4, 0x020f090b, 0x004fe03e, 0xf402fec4, 0x010f100b, - 0x000af489, 0x3e099fbc, 0xc4004ff8, 0x0bf401f9, 0x0af4890a, 0x099ebc00, 0x00055489, 0x000af48f, + 0x09f9bc36, 0x003b6a7e, 0x00087489, 0x89f890bc, 0xbc000524, 0xf9fd9890, 0x131bf404, 0x190b0ab2, + 0x617e030c, 0x030a0002, 0x0052623e, 0xf404f9c4, 0x020f090b, 0x004fc03e, 0xf402fec4, 0x010f100b, + 0x000af489, 0x3e099fbc, 0xc4004fd8, 0x0bf401f9, 0x0af4890a, 0x099ebc00, 0x00055489, 0x000af48f, 0xbc1890bc, 0x6489f8f0, 0x90bc0005, 0x085489a8, 0xb890bc00, 0x00086489, 0x89c890bc, 0xbc000ab4, 0xaf90099f, 0x90ffbc01, 0x90909fbc, 0xd9bb011d, 0x07c48904, 0x01ce9000, 0xbc099dbc, 0x9ebc90ee, 0x01bf9090, 0x8904f9bb, 0xbc0007d4, 0x548e099f, 0x4489000b, 0xfda6000b, 0xbc0d0df4, 0xecbc099b, - 0x506b3e09, 0x0991bc00, 0x8909eabc, 0xbc000714, 0x2489b890, 0x90bc0007, 0x079489e8, 0xbc030f00, + 0x504b3e09, 0x0991bc00, 0x8909eabc, 0xbc000714, 0x2489b890, 0x90bc0007, 0x079489e8, 0xbc030f00, 0xeebc099f, 0x909ebc90, 0x90039992, 0xf9bb01bf, 0x07a48904, 0x099fbc00, 0x000b348d, 0x000b248c, - 0xf403f6b0, 0xdebc0d0d, 0x09cbbc09, 0x0050ba3e, 0xd9bc0109, 0xbc020909, 0x448f09c9, 0xf0bc000b, + 0xf403f6b0, 0xdebc0d0d, 0x09cbbc09, 0x00509a3e, 0xd9bc0109, 0xbc020909, 0x448f09c9, 0xf0bc000b, 0x0b248fe8, 0xd8f0bc00, 0x000b348f, 0x89f8f0bc, 0xbc000b54, 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0xf9c40051, 0x0e0bf401, + 0x000b0489, 0x3e099ebc, 0xc4005143, 0x020f04f9, 0xb2df1bf4, 0x0c190b0a, 0x02617e0f, 0x3e0f0a00, + 0x89005262, 0x3c0003e8, 0x94339890, 0xf4bd0d01, 0x000b0489, 0x89099fbc, 0xbc0008d4, 0x4489f890, + 0x90bc0005, 0x94f9ff98, 0xb2131bf4, 0x0c190b0a, 0x02617e05, 0x3e050a00, 0xc4005262, 0x0bf4029f, + 0x3e010f09, 0xf000518d, 0x0bf40194, 0x0b148947, 0x099fbc00, 0x0008e489, 0x89b890bc, 0xbc0008f4, 0xf489c890, 0x008e0007, 0x9ebc0300, 0x01c99009, 0x900294b6, 0xf9bb01bf, 0x08048904, 0x099fbc00, - 0x000b748d, 0x000b648a, 0x0df4fea6, 0x52013e21, 0x0b0ab200, 0x7e0e0c19, 0x0a000261, 0x52823e0e, - 0x09dcbc00, 0x3e09abbc, 0x09005215, 0x09d9bc03, 0xa9bc0209, 0x0b648f09, 0xe8f0bc00, 0x000b048f, + 0x000b748d, 0x000b648a, 0x0df4fea6, 0x51e13e21, 0x0b0ab200, 0x7e0e0c19, 0x0a000261, 0x52623e0e, + 0x09dcbc00, 0x3e09abbc, 0x090051f5, 0x09d9bc03, 0xa9bc0209, 0x0b648f09, 0xe8f0bc00, 0x000b048f, 0x8fd8f0bc, 0xbc000b14, 0x7489f8f0, 0x90bc000b, 0x18e4b698, 0xb210f4b6, 0x1c94b60a, 0xfd059efd, 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0xbc000614, 0x9fb3989a, 0x00bd0309, 0x0100ac89, 0xbc0fad94, 0x00d9d0d9, 0xff008000, 0x5489e5d9, 0xd9bcfeff, 0x00efced0, 0x04000089, 0xf494f9ff, 0xff890d0b, 0xf9fffbff, 0x01e9fa94, 0x01309c89, 0xd9bcf43d, 0x38b889d0, 0x199f3c00, 0x800000df, 0xf5dfff00, 0xde00f9ce, 0x40000000, 0xfa059efd, 0xe4bd01f9, 0x0838ddb8, 0x0000db02, 0x00dc0080, 0xff080000, 0xf9cef5db, 0x059cfd00, - 0x9001f9fa, 0xdd9001ee, 0x04e4b340, 0xbd020bee, 0xfe1ab2d4, 0x00900140, 0x7e0cb208, 0xb20044ea, - 0x7e0a0b1a, 0xbf003b63, 0x0a04b300, 0x7e1ab224, 0xb2000050, 0xbd0bb21a, 0x48f77ec4, 0xb3030900, - 0x3e0e00a0, 0x090053af, 0x53af3e1e, 0xb294bd00, 0x0415fb9a, 0x0100ac8f, 0xf40fa994, 0x9fbcfc30, + 0x9001f9fa, 0xdd9001ee, 0x04e4b340, 0xbd020bee, 0xfe1ab2d4, 0x00900140, 0x7e0cb208, 0xb20044ca, + 0x7e0a0b1a, 0xbf003b43, 0x0a04b300, 0x7e1ab224, 0xb2000050, 0xbd0bb21a, 0x48d77ec4, 0xb3030900, + 0x3e0e00a0, 0x0900538f, 0x538f3e1e, 0xb294bd00, 0x0415fb9a, 0x0100ac8f, 0xf40fa994, 0x9fbcfc30, 0xdf12f990, 0x00800000, 0x9fffa1b2, 0x00efcee5, 0x02000089, 0xf494f9ff, 0xff890d0b, 0xf9fffdff, - 0x01e9fa94, 0xd4bd020b, 0x40fe1ab2, 0x08009001, 0xea7e0cb2, 0x090b0044, 0x637e1ab2, 0x0bbf003b, - 0x1209b4b3, 0xc4bd1ab2, 0x0048f77e, 0xa4b30309, 0x94bd0600, 0x15fb9ab2, 0x38b88904, 0xac30f400, - 0x9a3c32f9, 0x89a1b2f8, 0xb2000614, 0x089abcbc, 0x1300f433, 0x0f0a04b3, 0x7e010a4b, 0x3e003b63, - 0xb3005490, 0x4d010a0e, 0x0006d489, 0x0fb891bc, 0x39d48901, 0x0143fe00, 0x90199f3c, 0x1ab21033, - 0xae7e3db2, 0xa2b2003c, 0x0200adb3, 0x38b88901, 0x98913c00, 0x1c009433, 0xc43d3bb2, 0x757e1ab2, - 0x1ab20037, 0x010c0b0b, 0x00f4248d, 0x0017087e, 0x0038b889, 0x3398913c, 0x00d10099, 0x030a0bb3, - 0x40fe00cc, 0x901ab201, 0x0bb21000, 0x003c0e7e, 0xadb3a2b2, 0xb200b800, 0x3d1ab20b, 0x37757ec4, + 0x01e9fa94, 0xd4bd020b, 0x40fe1ab2, 0x08009001, 0xca7e0cb2, 0x090b0044, 0x437e1ab2, 0x0bbf003b, + 0x1209b4b3, 0xc4bd1ab2, 0x0048d77e, 0xa4b30309, 0x94bd0600, 0x15fb9ab2, 0x38b88904, 0xac30f400, + 0x9a3c32f9, 0x89a1b2f8, 0xb2000614, 0x089abcbc, 0x1300f433, 0x0f0a04b3, 0x7e010a4b, 0x3e003b43, + 0xb3005470, 0x4d010a0e, 0x0006d489, 0x0fb891bc, 0x39d48901, 0x0143fe00, 0x90199f3c, 0x1ab21033, + 0x8e7e3db2, 0xa2b2003c, 0x0200adb3, 0x38b88901, 0x98913c00, 0x1c009433, 0xc43d3bb2, 0x557e1ab2, + 0x1ab20037, 0x010c0b0b, 0x00f4248d, 0x0016ee7e, 0x0038b889, 0x3398913c, 0x00d10099, 0x030a0bb3, + 0x40fe00cc, 0x901ab201, 0x0bb21000, 0x003bee7e, 0xadb3a2b2, 0xb200b800, 0x3d1ab20b, 0x37557ec4, 0x00048900, 0x0f1f9401, 0xd9f0f9bc, 0x00800000, 0xce05f9fd, 0x004e00f9, 0x049efdf8, 0x0901f9fa, 0x3bc08f01, 0xbc9ab200, 0x108919f9, 0xf0b20039, 0x94041e94, 0xff8b041f, 0xf9bc00ff, 0x0a348cf0, 0x39208900, 0xbcd4bd00, 0xf9bfe0e9, 0xa604ff90, 0x091bf49b, 0xbc19cabc, 0xfea6190d, 0x89ee1bf4, - 0xbc003bc0, 0x90b39891, 0x4bfe1200, 0x901ab201, 0x010c10bb, 0x0037757e, 0xd4bd020b, 0x40fe1ab2, - 0x60009001, 0xea7e0cb2, 0x0a4b0044, 0x7e1ab203, 0xbf003b63, 0x0abeb30b, 0x1ab21503, 0xf77ec4bd, - 0xa2b20048, 0x00556a3e, 0x2ab224bd, 0x0b5435fb, 0xf4d4bd02, 0x22f9fc30, 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0x89a9d93c, 0x8f017600, 0xbcfe8a00, 0x00d95059, 0xff008000, + 0x5fbc9559, 0x009fce50, 0xce080449, 0x90330099, 0xf4bd0a03, 0x0057bb3e, 0x890fffc7, 0xbc017650, 0x74895059, 0x9f3c0038, 0x0000d949, 0xb08f0080, 0x59fffe89, 0x505fbce5, 0x8d00e9ce, 0xc4000ba8, - 0x1bf4019f, 0x49df3c10, 0xfa0195f0, 0x173e01e9, 0x01090058, 0xb249d93c, 0x18e57e4a, 0x01a43300, - 0x064ab219, 0x18be7e16, 0x00a93300, 0x4ab202a9, 0xb57eb4bd, 0x0cd90018, 0xce008020, 0xdc8f0099, + 0x1bf4019f, 0x49df3c10, 0xfa0195f0, 0xf73e01e9, 0x01090057, 0xb249d93c, 0x18c77e4a, 0x01a43300, + 0x064ab219, 0x18a07e16, 0x00a93300, 0x4ab202a9, 0x977eb4bd, 0x0cd90018, 0xce008020, 0xdc8f0099, 0x9e95000b, 0x1a9dc70c, 0xc749febc, 0xfc89769f, 0x9fbc000b, 0x0bec8949, 0x499dbc00, 0x000c0c8e, - 0x1600d4b3, 0x8e49ed3c, 0xb3000c10, 0x3c1400f0, 0x843e49ed, 0x943d0058, 0x000c108f, 0x0949f93c, - 0x49e93c01, 0x010b4ab2, 0x0032ac7e, 0xadb3a6b2, 0x89024400, 0xbc017380, 0x00d95059, 0xff008000, - 0x8089f559, 0x59bcfe8c, 0xce94bd50, 0x999000fe, 0x3294b301, 0xbd4ab2fa, 0x32ac7eb4, 0xb3a6b200, + 0x1600d4b3, 0x8e49ed3c, 0xb3000c10, 0x3c1400f0, 0x643e49ed, 0x943d0058, 0x000c108f, 0x0949f93c, + 0x49e93c01, 0x010b4ab2, 0x00328c7e, 0xadb3a6b2, 0x89024400, 0xbc017380, 0x00d95059, 0xff008000, + 0x8089f559, 0x59bcfe8c, 0xce94bd50, 0x999000fe, 0x3294b301, 0xbd4ab2fa, 0x328c7eb4, 0xb3a6b200, 0x021300ad, 0x0174a88f, 0xdf505fbc, 0x00800000, 0xcef55fff, 0x95f100f9, 0xf9fa0100, 0x89f48f01, 0x6455b8fe, 0x00d90001, 0xff008000, 0x5fbc9559, 0x0099ce50, 0x0003ec8b, 0x008fbdbf, 0x9cc70004, 0x49f9bce8, 0x8f039ec4, 0xc70004c0, 0xfebc2499, 0x04d08f49, 0x49f9bc00, 0x0004e089, 0xd9499cbc, 0xdeadbeef, 0x1bf4d9a6, 0x89bca005, 0xbf0003ec, 0xbeefd99f, 0xf9a6dead, 0x89190bf4, 0xbc0004e0, - 0x9fa69894, 0xb20d0bf4, 0x0c180b4a, 0x59eb3e0f, 0x76188900, 0x0000d701, 0x59bc0080, 0xf557ff50, + 0x9fa69894, 0xb20d0bf4, 0x0c180b4a, 0x59cb3e0f, 0x76188900, 0x0000d701, 0x59bc0080, 0xf557ff50, 0x8900ffce, 0x900003f0, 0x9fbc6855, 0xe557ff49, 0xfe898089, 0xce5059bc, 0x208900ee, 0x9ebc0004, 0x04f08949, 0x01fdc400, 0x89499dbc, 0xc7000500, 0x9cbc21fc, 0x05108949, 0x26fbc700, 0x89499bbc, 0xc7000520, 0x9a3c03fa, 0x05248949, 0x48f0c700, 0x894990bc, 0xc7000534, 0x91bcebf1, 0x05448949, - 0x93f2c700, 0x894992bc, 0x95000554, 0xffc71cf3, 0x499fbc78, 0x00056489, 0x93bc4ab2, 0x32f67e49, - 0xb3acb200, 0xb21200a0, 0x7e180b4a, 0x06000261, 0x5ad23e1f, 0x7e4ab200, 0xb200334c, 0x00a4b3ac, - 0x7e4ab2ea, 0xb20033c9, 0x00a4b3ac, 0x7e4ab2de, 0xb2003416, 0x00a4b3ac, 0x7e4ab2d2, 0xb2003885, - 0x38be7e4a, 0x7e4ab200, 0xb2003923, 0x39597e4a, 0x7e4ab200, 0xb200343f, 0x00a4b3ac, 0x7e4ab2ae, - 0xb2003467, 0x00a4b3ac, 0x0a9489a2, 0xc894bc00, 0x000a8489, 0x0bd894bc, 0x7e4ab223, 0xb2000494, - 0x348e7e4a, 0xb3acb200, 0xb28000a4, 0x34b67e4a, 0xb3acb200, 0xff7400ad, 0x000aa489, 0xbdd894bc, - 0xb2240bc4, 0x04947e4a, 0x7e4ab200, 0xb20056df, 0x00adb3ac, 0x248fff56, 0x5fbc0176, 0x9557ff50, - 0x8f0099ce, 0xbc000bcc, 0x94f049f9, 0x1f0bf401, 0x0003c089, 0x3308943c, 0xb2150104, 0x18e57e4a, - 0x00a43300, 0x03e8890b, 0x49903c00, 0x617e4ab2, 0x6ab20056, 0xdb8f71fb, 0x440902e7, 0xf8009ffa, + 0x93f2c700, 0x894992bc, 0x95000554, 0xffc71cf3, 0x499fbc78, 0x00056489, 0x93bc4ab2, 0x32d67e49, + 0xb3acb200, 0xb21200a0, 0x7e180b4a, 0x06000261, 0x5ab23e1f, 0x7e4ab200, 0xb200332c, 0x00a4b3ac, + 0x7e4ab2ea, 0xb20033a9, 0x00a4b3ac, 0x7e4ab2de, 0xb20033f6, 0x00a4b3ac, 0x7e4ab2d2, 0xb2003865, + 0x389e7e4a, 0x7e4ab200, 0xb2003903, 0x39397e4a, 0x7e4ab200, 0xb200341f, 0x00a4b3ac, 0x7e4ab2ae, + 0xb2003447, 0x00a4b3ac, 0x0a9489a2, 0xc894bc00, 0x000a8489, 0x0bd894bc, 0x7e4ab223, 0xb2000494, + 0x346e7e4a, 0xb3acb200, 0xb28000a4, 0x34967e4a, 0xb3acb200, 0xff7400ad, 0x000aa489, 0xbdd894bc, + 0xb2240bc4, 0x04947e4a, 0x7e4ab200, 0xb20056bf, 0x00adb3ac, 0x248fff56, 0x5fbc0176, 0x9557ff50, + 0x8f0099ce, 0xbc000bcc, 0x94f049f9, 0x1f0bf401, 0x0003c089, 0x3308943c, 0xb2150104, 0x18c77e4a, + 0x00a43300, 0x03e8890b, 0x49903c00, 0x417e4ab2, 0x6ab20056, 0xdb8f71fb, 0x440902e7, 0xf8009ffa, 0x02b5b600, 0x0c02a0b3, 0x1803a0b3, 0x00f8a4bd, 0x09f0bbbc, 0xf0fbbc40, 0xc4079fbb, 0x00f8079a, 0x89f0bbbc, 0xbc492492, 0x9fbbf0fb, 0x079ac407, 0xa99400f8, 0xb6e4bd07, 0xd4bd04a4, 0x3ea0a9bc, - 0xa0005b36, 0x01ff909d, 0xb3049990, 0x90f809f4, 0xe0b301ee, 0xef941d04, 0x02e99405, 0x8f909fbc, - 0xbc000c14, 0x9fbc909a, 0x3ef4bd90, 0xf8005b23, 0x9452f900, 0xa99404af, 0xbda3b207, 0x40f9bc24, - 0x001ffc85, 0x005b893e, 0x3ab20b7f, 0x00902cb2, 0x00b3f006, 0x0012f97e, 0x11901aa0, 0xf405a604, + 0xa0005b16, 0x01ff909d, 0xb3049990, 0x90f809f4, 0xe0b301ee, 0xef941d04, 0x02e99405, 0x8f909fbc, + 0xbc000c14, 0x9fbc909a, 0x3ef4bd90, 0xf8005b03, 0x9452f900, 0xa99404af, 0xbda3b207, 0x40f9bc24, + 0x001ffc85, 0x005b693e, 0x3ab20b7f, 0x00902cb2, 0x00b3f006, 0x0012f97e, 0x11901aa0, 0xf405a604, 0x2290e91b, 0x0420b301, 0x0229941f, 0xbc052f94, 0xc680909f, 0x94bc001f, 0x0c148910, 0x1019bc00, - 0x005b683e, 0x62f951fb, 0x9404af94, 0xa4b207a9, 0xf9bc14bd, 0x1ffe8650, 0x5bfd3e00, 0xb2207f00, + 0x005b483e, 0x62f951fb, 0x9404af94, 0xa4b207a9, 0xf9bc14bd, 0x1ffe8650, 0x5bdd3e00, 0xb2207f00, 0xe44ab21c, 0x7effff0b, 0x580012f9, 0x3cbf0129, 0xe4062290, 0xf0ffff0b, 0x9cff0093, 0x0099b9c4, 0x9004a9fd, 0xacff0433, 0xb21db2c5, 0x13357e4a, 0xf426a600, 0x1190ca1b, 0x0410b301, 0x0219941f, - 0xbc051f94, 0xc882909f, 0x95bc001f, 0x0c148930, 0x3039bc00, 0x005bbd3e, 0x82f961fb, 0xc464bfc7, + 0xbc051f94, 0xc882909f, 0x95bc001f, 0x0c148930, 0x3039bc00, 0x005b9d3e, 0x82f961fb, 0xc464bfc7, 0xb9c70fb2, 0xc7a1b232, 0xf79474b8, 0x0496940c, 0x9404f594, 0x04bd0824, 0xb248b3c7, 0x02294b0c, 0xf97e1ab2, 0xf8090012, 0x09c4a9ff, 0x4b0db2cf, 0x1ab20229, 0xfdc53cff, 0xc6fd04c9, 0x13357e05, 0x4b0cb200, 0x1ab2022a, 0x0012f97e, 0xa9fff009, 0xff0f49c4, 0xfdc52cff, 0xff4904c9, 0xc55cfff0, 0x8904c9fd, 0xb2ff0fff, 0x022a4b0d, 0xc4fd1ab2, 0x04c9fd05, 0x7e05c7fd, 0xb2001335, 0x022b4b0c, 0xf97e1ab2, 0xf0090012, 0xa9ff0db2, 0x010090c4, 0xb2c58cff, 0x022b4b1a, 0x0013357e, 0x7f040db3, - 0xf981fbff, 0xb3a2b242, 0xb31304b0, 0x0a5d07b0, 0x00bdb323, 0x013e020e, 0x5680005d, 0x1e81001d, - 0x0b7f001e, 0xb2010c58, 0x0400902a, 0xf000b3f0, 0x040d00c3, 0x0013357e, 0x1bf401a6, 0x5d4b3ee8, + 0xf981fbff, 0xb3a2b242, 0xb31304b0, 0x0a5d07b0, 0x00bdb323, 0xe13e020e, 0x5680005c, 0x1e81001d, + 0x0b7f001e, 0xb2010c58, 0x0400902a, 0xf000b3f0, 0x040d00c3, 0x0013357e, 0x1bf401a6, 0x5d2b3ee8, 0x1c5a8000, 0x1d568100, 0x580b7f00, 0x2ab2010c, 0xf0040090, 0xc3f000b3, 0x7e040d00, 0xa6001335, - 0xe81bf401, 0x005d4b3e, 0x001e1e80, 0x001eea81, 0x0c580b7f, 0x902ab201, 0xb3f00400, 0x00c3f000, + 0xe81bf401, 0x005d2b3e, 0x001e1e80, 0x001eea81, 0x0c580b7f, 0x902ab201, 0xb3f00400, 0x00c3f000, 0x357e040d, 0x01a60013, 0x89e81bf4, 0x3c002784, 0x94339892, 0x04bd2901, 0x0cb2fe01, 0x2ab2130b, - 0x0012f97e, 0xa1ff0db2, 0x010090c4, 0xb201c5f0, 0x7e130b2a, 0xb3001335, 0xb2e30404, 0x3b1b7e2a, + 0x0012f97e, 0xa1ff0db2, 0x010090c4, 0xb201c5f0, 0x7e130b2a, 0xb3001335, 0xb2e30404, 0x3afb7e2a, 0x01a43300, 0xbd240b62, 0x7e2ab2c4, 0x000012f9, 0xffd4bdcf, 0x240bc4a0, 0x357e2ab2, 0x240b0013, 0x2ab2010c, 0x0012f97e, 0xa0ff010d, 0xb2240bc4, 0x13357e2a, 0x0c240b00, 0x7e2ab202, 0x0d0012f9, 0xc4a0ff02, 0x2ab2240b, 0x0013357e, 0x030c240b, 0xf97e2ab2, 0x240b0012, 0x0dc4a0ff, 0x7e2ab203, - 0xb2001335, 0x3ae27e2a, 0x03a4b300, 0x4b2ab212, 0xcb4c00b9, 0x7e040d00, 0x89001335, 0x3c000300, + 0xb2001335, 0x3ac27e2a, 0x03a4b300, 0x4b2ab212, 0xcb4c00b9, 0x7e040d00, 0x89001335, 0x3c000300, 0x94339892, 0xb4837701, 0x347f001f, 0x1cb214bd, 0xffff4be4, 0xf97e2ab2, 0x3c580012, 0x013f5802, 0x4be41db2, 0xc9e4ffff, 0x99b9ffff, 0x04a9fd00, 0xf004cffd, 0xacff00c3, 0x7e2ab2c5, 0x58001335, 0x1cb20330, 0x0be42ab2, 0xf97effff, 0x39580012, 0x043c5805, 0x0be41db2, 0x1190ffff, 0xc49cff01, @@ -793,62 +792,62 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0x7e02644b, 0xb3001335, 0x89e10404, 0x3c000308, 0x94339892, 0x04bd2b01, 0x0cb2ce01, 0xb202644b, 0x12f97e2a, 0xff0db200, 0x0090c4a1, 0x11c5f001, 0x644b2ab2, 0x13357e02, 0x0404b300, 0xfba4bde1, 0xb232f941, 0x0ab3b2a2, 0x01d9b331, 0xc99400da, 0x90e9bc08, 0x040196b1, 0xb1140cf4, 0xf4040096, - 0x96b05e18, 0x0c0cf401, 0x005f3a3e, 0x07039ab3, 0x3e230a0b, 0x80005fc3, 0x81001ba0, 0x7f001bf4, - 0x010b580a, 0xf0040090, 0xb3f000a3, 0x13677e00, 0xf401a600, 0x7c3eec1b, 0xa880005f, 0xfc81001a, - 0x0a7f001a, 0x90010b58, 0xa3f00400, 0x00b3f000, 0x0013677e, 0x1bf401a6, 0x5f7c3eec, 0x1afc8000, + 0x96b05e18, 0x0c0cf401, 0x005f1a3e, 0x07039ab3, 0x3e230a0b, 0x80005fa3, 0x81001ba0, 0x7f001bf4, + 0x010b580a, 0xf0040090, 0xb3f000a3, 0x13677e00, 0xf401a600, 0x5c3eec1b, 0xa880005f, 0xfc81001a, + 0x0a7f001a, 0x90010b58, 0xa3f00400, 0x00b3f000, 0x0013677e, 0x1bf401a6, 0x5f5c3eec, 0x1afc8000, 0x1b508100, 0x580a7f00, 0x0090010b, 0x00a3f004, 0x7e00b3f0, 0xa6001367, 0xec1bf401, 0x4a05b0b4, - 0xb4f000f7, 0x10b5f007, 0x0013677e, 0x3bb22ab2, 0x005ae17e, 0x1b01a0b3, 0x2902a4b3, 0x867e090a, - 0x3f490013, 0xb4a9ffff, 0x3e80b5f0, 0x0a005fbb, 0x13867e09, 0xff3f4900, 0x0ab4a9ff, 0x13677e09, + 0xb4f000f7, 0x10b5f007, 0x0013677e, 0x3bb22ab2, 0x005ac17e, 0x1b01a0b3, 0x2902a4b3, 0x867e090a, + 0x3f490013, 0xb4a9ffff, 0x3e80b5f0, 0x0a005f9b, 0x13867e09, 0xff3f4900, 0x0ab4a9ff, 0x13677e09, 0xfba4bd00, 0xf0bca631, 0xbabc0b9c, 0x1f94b6b0, 0xf8a59bff, 0xb0babc00, 0xcba6cab2, 0xb2050df4, 0xf900f8ba, 0x008c8952, 0x0000d001, 0xa5940080, 0xbca4b20f, 0x50ff5059, 0x00bbceb5, 0x000e5481, - 0xf1a81abc, 0x4c03ffb4, 0x55b803ff, 0x7e001ff0, 0xff005fc5, 0x1abcb550, 0x00bbce49, 0x000e6481, - 0xdca814bc, 0x7fffffff, 0xb804bcfd, 0x00020c55, 0x005fc57e, 0xbcb550ff, 0xbbce491a, 0x0e748100, - 0xa814bc00, 0x8c10b5b6, 0xb800ffff, 0x00100055, 0x005fc57e, 0xbcb550ff, 0xbbce491a, 0x0e848100, - 0xa814bc00, 0x8c00b3f0, 0x9000ffff, 0xc57e0455, 0x50ff005f, 0xcd748905, 0x491abcfe, 0xce5059bc, + 0xf1a81abc, 0x4c03ffb4, 0x55b803ff, 0x7e001ff0, 0xff005fa5, 0x1abcb550, 0x00bbce49, 0x000e6481, + 0xdca814bc, 0x7fffffff, 0xb804bcfd, 0x00020c55, 0x005fa57e, 0xbcb550ff, 0xbbce491a, 0x0e748100, + 0xa814bc00, 0x8c10b5b6, 0xb800ffff, 0x00100055, 0x005fa57e, 0xbcb550ff, 0xbbce491a, 0x0e848100, + 0xa814bc00, 0x8c00b3f0, 0x9000ffff, 0xa57e0455, 0x50ff005f, 0xcd748905, 0x491abcfe, 0xce5059bc, 0x9489000d, 0x94bc000e, 0xe8d9c7f8, 0xb1e09fbc, 0xf400fee6, 0xff4e060d, 0x0ea48900, 0xf894bc00, 0x000e9489, 0xc7499ebc, 0x9fbcf0d9, 0xfee6b1e0, 0x060df400, 0x8900ff4e, 0xbc000eb4, 0xa489f894, 0x9ebc000e, 0x18d99549, 0xb1e09fbc, 0xf400fee6, 0xff4e060d, 0x0ec48900, 0xf894bc00, 0x000eb489, 0xc4499ebc, 0x9fbcffd9, 0xfef6b1f0, 0x060df400, 0x8900ff4f, 0xd3013294, 0x00800000, 0x895059bc, 0xff000ec4, 0x9fbcb553, 0x00bbce49, 0x000ed480, 0xf0a804bc, 0xff8c00b3, 0x55b800ff, 0x7e000104, - 0xff005fc5, 0x0abcb553, 0x00bbce49, 0x000ee481, 0xd0a814bc, 0x00ffffff, 0xb204b0fd, 0x5fc57e0c, - 0x04559000, 0xff491abc, 0xbbceb553, 0x0ef48100, 0xa814bc00, 0xb204b0fd, 0x0455900c, 0x005fc57e, - 0xbcb553ff, 0xbbce491a, 0x0f048100, 0xa814bc00, 0xb204b0fd, 0x0455900c, 0x005fc57e, 0xbcb553ff, - 0xbbce491a, 0x0f148100, 0xa814bc00, 0xb204b0fd, 0x9055b80c, 0xc57e0203, 0x53ff005f, 0x491abcb5, - 0x8000bbce, 0xbc000f24, 0xbbc7a804, 0x7c55b8e8, 0xff4c022e, 0x5fc57e00, 0x490abc00, 0xce0553ff, - 0x34810000, 0x14bc000f, 0x100b95a8, 0x00ffff8c, 0x000f4482, 0x005fc57e, 0xbc491abc, 0x0be4a824, - 0xff8cffff, 0x559000ff, 0x5fc57e04, 0xb553ff00, 0xce492abc, 0x548000bb, 0x04bc000f, 0x00b3f0a8, - 0x8c045590, 0x7e00ffff, 0xbc005fc5, 0x53ff490a, 0x0000ce05, 0x000f6481, 0x95a814bc, 0xff4c180b, - 0x0f748200, 0x5fc57e00, 0x491abc00, 0xc4a824bc, 0xff4cff0b, 0x0f848100, 0x5fc57e00, 0x492abc00, - 0xc7a814bc, 0xff4ce80b, 0x0f948200, 0x5fc57e00, 0x491abc00, 0xc7a824bc, 0x5590f00b, 0x00ff4c04, - 0x7e0553ff, 0xbc005fc5, 0x00ce492a, 0x0fa48100, 0xa814bc00, 0x8c100b95, 0x8200ffff, 0x7e000fb4, - 0xbc005fc5, 0x24bc491a, 0xff0be4a8, 0xffff8cff, 0x04509000, 0x005fc57e, 0xbc0503fd, 0x00ce492a, - 0x0fc48100, 0xa814bc00, 0x4ce80bc7, 0xd48200ff, 0xc57e000f, 0x1abc005f, 0xa824bc49, 0x4cff0bc4, - 0xe48300ff, 0xc57e000f, 0x2abc005f, 0xa834bc49, 0x4cf00bc7, 0xf48100ff, 0xc57e000f, 0x3abc005f, - 0xa814bc49, 0x4c180b95, 0xc57e00ff, 0x1abc005f, 0x8f51fb49, 0xdb010050, 0x00800000, 0xbc0fa994, + 0xff005fa5, 0x0abcb553, 0x00bbce49, 0x000ee481, 0xd0a814bc, 0x00ffffff, 0xb204b0fd, 0x5fa57e0c, + 0x04559000, 0xff491abc, 0xbbceb553, 0x0ef48100, 0xa814bc00, 0xb204b0fd, 0x0455900c, 0x005fa57e, + 0xbcb553ff, 0xbbce491a, 0x0f048100, 0xa814bc00, 0xb204b0fd, 0x0455900c, 0x005fa57e, 0xbcb553ff, + 0xbbce491a, 0x0f148100, 0xa814bc00, 0xb204b0fd, 0x9055b80c, 0xa57e0203, 0x53ff005f, 0x491abcb5, + 0x8000bbce, 0xbc000f24, 0xbbc7a804, 0x7c55b8e8, 0xff4c022e, 0x5fa57e00, 0x490abc00, 0xce0553ff, + 0x34810000, 0x14bc000f, 0x100b95a8, 0x00ffff8c, 0x000f4482, 0x005fa57e, 0xbc491abc, 0x0be4a824, + 0xff8cffff, 0x559000ff, 0x5fa57e04, 0xb553ff00, 0xce492abc, 0x548000bb, 0x04bc000f, 0x00b3f0a8, + 0x8c045590, 0x7e00ffff, 0xbc005fa5, 0x53ff490a, 0x0000ce05, 0x000f6481, 0x95a814bc, 0xff4c180b, + 0x0f748200, 0x5fa57e00, 0x491abc00, 0xc4a824bc, 0xff4cff0b, 0x0f848100, 0x5fa57e00, 0x492abc00, + 0xc7a814bc, 0xff4ce80b, 0x0f948200, 0x5fa57e00, 0x491abc00, 0xc7a824bc, 0x5590f00b, 0x00ff4c04, + 0x7e0553ff, 0xbc005fa5, 0x00ce492a, 0x0fa48100, 0xa814bc00, 0x8c100b95, 0x8200ffff, 0x7e000fb4, + 0xbc005fa5, 0x24bc491a, 0xff0be4a8, 0xffff8cff, 0x04509000, 0x005fa57e, 0xbc0503fd, 0x00ce492a, + 0x0fc48100, 0xa814bc00, 0x4ce80bc7, 0xd48200ff, 0xa57e000f, 0x1abc005f, 0xa824bc49, 0x4cff0bc4, + 0xe48300ff, 0xa57e000f, 0x2abc005f, 0xa834bc49, 0x4cf00bc7, 0xf48100ff, 0xa57e000f, 0x3abc005f, + 0xa814bc49, 0x4c180b95, 0xa57e00ff, 0x1abc005f, 0x8f51fb49, 0xdb010050, 0x00800000, 0xbc0fa994, 0x9bff909f, 0x00ffcef5, 0x0010048c, 0xb8d8cabc, 0x001fd899, 0xfde59bff, 0xcfbc05fd, 0x00eecea9, 0x0010148d, 0xb8f8dabc, 0x00100099, 0xfd059bfd, 0xdebc05ef, 0x0099cea9, 0x0010248e, 0xfdf8eabc, 0xe9bc059f, 0x8f00f8a9, 0x94013068, 0x9fbc0fa9, 0x0000df90, 0x9ffd0080, 0x009ece05, 0x0010348d, 0xc4f8dabc, 0x9fa63fe9, 0xb20518f4, 0x10448cf9, 0xf8cabc00, 0xc7a9d9bc, 0x9fa6a8e9, 0xb20518f4, 0x10548bf9, 0xf8babc00, 0xc7a9c9bc, 0x9fa6b0e9, 0xb20518f4, 0x10648df9, 0xf8dabc00, 0xc7a9b9bc, 0x9fa6b8e9, 0xb20518f4, 0xa9d9bcf9, 0x408f00f8, 0x00d90130, 0x94008000, 0xefbc0fae, 0xf5e9ffe0, - 0x9200fcce, 0xe9ff18ee, 0xcfd889b5, 0xe0e9bcfe, 0xc400bdce, 0x0bf402d9, 0x68cfc70a, 0x0063e73e, - 0x00107489, 0x89f89abc, 0xbc001074, 0xd9c4a99f, 0x0a0bf420, 0x3e78cfc7, 0x89006402, 0xbc001084, - 0x8489f89a, 0x9fbc0010, 0x10d9c4a9, 0xc70a0bf4, 0x1d3e70cf, 0x94890064, 0x9abc0010, 0x304489f8, + 0x9200fcce, 0xe9ff18ee, 0xcfd889b5, 0xe0e9bcfe, 0xc400bdce, 0x0bf402d9, 0x68cfc70a, 0x0063c73e, + 0x00107489, 0x89f89abc, 0xbc001074, 0xd9c4a99f, 0x0a0bf420, 0x3e78cfc7, 0x890063e2, 0xbc001084, + 0x8489f89a, 0x9fbc0010, 0x10d9c4a9, 0xc70a0bf4, 0xfd3e70cf, 0x94890063, 0x9abc0010, 0x304489f8, 0xe0e9bc01, 0x00109489, 0xd9a99fbc, 0x00800000, 0xce95e9ff, 0xbdce009f, 0x80d9c400, 0x0b009033, - 0x3e70fec7, 0x8900644e, 0xbc0010a4, 0xa489e89a, 0x9ebc0010, 0x40d9c4a9, 0xc70a0bf4, 0x693e78ff, - 0xb4890064, 0x9abc0010, 0x10b489f8, 0xa99fbc00, 0x12f900f8, 0xb2015c4b, 0x76ce7ea0, 0x11048900, + 0x3e70fec7, 0x8900642e, 0xbc0010a4, 0xa489e89a, 0x9ebc0010, 0x40d9c4a9, 0xc70a0bf4, 0x493e78ff, + 0xb4890064, 0x9abc0010, 0x10b489f8, 0xa99fbc00, 0x12f900f8, 0xb2015c4b, 0x76ba7ea0, 0x11048900, 0x0f0d9400, 0x8fa0a9bc, 0x89001674, 0xd1010000, 0x00800000, 0x8be0d9bc, 0xbf0017d0, 0x0000dcf9, 0xe9bc0080, 0x0591fd90, 0xa00099ce, 0x04ff90a9, 0xa604aa90, 0xe61bf4fb, 0x01300089, 0xffd0d9bc, 0x99ce95dc, 0x10c48f00, 0x30ddb800, 0xf9bc0002, 0x95dcff09, 0x8f0099ce, 0x900010d4, 0xf9bc50dd, 0xe5dcff09, 0x8f00eece, 0xb80010e4, 0x0230f0d9, 0xfd09febc, 0x99ce059c, 0x10f48f00, 0x09f9bc00, - 0x12f911fb, 0xb2015c4b, 0x76ce7ea0, 0x11048900, 0x0f0c9400, 0x8ea0a9bc, 0x89001674, 0xd1010000, + 0x12f911fb, 0xb2015c4b, 0x76ba7ea0, 0x11048900, 0x0f0c9400, 0x8ea0a9bc, 0x89001674, 0xd1010000, 0x00800000, 0x8bd0c9bc, 0xbf0017ac, 0xbcafbfe9, 0x91fd90d9, 0x019ffa05, 0x9004ee90, 0xeba604aa, 0x89eb1bf4, 0xdd013000, 0x00800000, 0xffc0c9bc, 0xdeced5cd, 0x10c48900, 0xf890bc00, 0x000000d9, 0x04e9fd42, 0xffffffd9, 0x04f9fdbd, 0xfa05effd, 0x00dd01de, 0xb8008000, 0x000230cc, 0xced5cdff, 0xd48900de, 0x90bc0010, 0xffff89f8, 0x04e9fde4, 0x1b000089, 0xfd04f9fd, 0xdefa05ef, 0x0000dd01, 0xcc900080, 0xd5cdff50, 0x8900dece, 0xbc0010e4, 0xf00f9890, 0xfd0fe4f0, 0xe9fd049f, 0x01defa05, 0x800000d9, 0xf0cdb800, 0xd9fd0230, 0x00dece05, 0x0010f489, 0xd9f890bc, 0x0fffffff, 0xd904e9fd, - 0xf0000000, 0xfd04f9fd, 0xdefa05ef, 0x8911fb01, 0xf9010000, 0x015c4b02, 0xbc0fa094, 0xce7e0009, + 0xf0000000, 0xfd04f9fd, 0xdefa05ef, 0x8911fb01, 0xf9010000, 0x015c4b02, 0xbc0fa094, 0xba7e0009, 0x3c890076, 0xac8e0012, 0xa9bc0017, 0x0000dca0, 0xd08d0080, 0xe9bf0017, 0x09bcafbf, 0x059cfd90, 0x90019ffa, 0xaa9004ee, 0xf4eda604, 0x01fbeb1b, 0x000e548e, 0xe9bc94bd, 0x0e648ea9, 0xa9e9bc00, 0x000e748e, 0x8ea9e9bc, 0xbc000e84, 0x948ea9e9, 0xe9bc000e, 0x0ea48ea9, 0xa9e9bc00, 0x000eb48e, @@ -860,131 +859,132 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0xa9e9bc00, 0x0010348e, 0x8ea9e9bc, 0xbc001044, 0x548ea9e9, 0xe9bc0010, 0x10648ea9, 0xa9e9bc00, 0x0010748e, 0x8ea9e9bc, 0xbc001084, 0x948ea9e9, 0xe9bc0010, 0x10a48ea9, 0xa9e9bc00, 0x0010b48e, 0x8ea9e9bc, 0xbc0010c4, 0xd48ea9e9, 0xe9bc0010, 0x10e48ea9, 0xa9e9bc00, 0x0010f48e, 0xbc015c4b, - 0xce7ea9e9, 0x04890076, 0xf4bd0011, 0xbda0a9bc, 0x90afa094, 0xaa900199, 0x5794b304, 0xb600f8f8, + 0xba7ea9e9, 0x04890076, 0xf4bd0011, 0xbda0a9bc, 0x90afa094, 0xaa900199, 0x5794b304, 0xb600f8f8, + 0xf88c0fa4, 0x288b0023, 0xcfbf0024, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, 0xf9fa059d, + 0x0ccc9001, 0x1bf4cba6, 0x8f00f8e4, 0xbf0021b8, 0x0fa4b6fe, 0xcee0aebc, 0xfd9800e9, 0x02ff9801, + 0xfd049ffd, 0xe9fa059d, 0x21b88f01, 0x03f99800, 0xcea0a9bc, 0xfe9800a9, 0x05ff9804, 0xfd049ffd, + 0xa9fa059e, 0x8f00f801, 0xbf002104, 0x0fa4b6fe, 0xcee0aebc, 0xfd9800e9, 0x02ff9801, 0xfd049ffd, + 0xe9fa059d, 0x21048f01, 0x03f99800, 0xcea0a9bc, 0xfe9800a9, 0x05ff9804, 0xfd049ffd, 0xa9fa059e, + 0xd900f801, 0x00816128, 0xbc0fa4b6, 0xa9cea0a9, 0xf0004f00, 0xf0049ffd, 0xa9fa6495, 0xb600f801, 0x348c0fa4, 0xb88b0021, 0xcfbf0021, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, 0xf9fa059d, - 0x0ccc9001, 0x1bf4cba6, 0x8f00f8e4, 0xbf0021d0, 0x00d9cefd, 0x9801fe98, 0x9ffd02ff, 0x059efd04, - 0x8f01d9fa, 0x980021d0, 0xd9ce03fd, 0x04fe9800, 0xfd05ff98, 0x9efd049f, 0x01d9fa05, 0x0021d08f, - 0xce06fd98, 0xfe9800d9, 0x08ff9807, 0xfd049ffd, 0xd9fa059e, 0x21f48c01, 0x0fa4b600, 0x0023688b, - 0xafbccfbf, 0x00f9cef0, 0x9802ce98, 0x9efd01cd, 0x059dfd04, 0x9001f9fa, 0xcba60ccc, 0xf8e41bf4, - 0x3814de00, 0xe9ce0080, 0xffffdf00, 0x9ffd00ff, 0x0000df04, 0x9ffd0600, 0x01e9fa05, 0xa4b600f8, - 0x23f88c0f, 0x24288b00, 0xbccfbf00, 0xf9cef0af, 0x02ce9800, 0xfd01cd98, 0x9dfd049e, 0x01f9fa05, - 0xa60ccc90, 0xe41bf4cb, 0x88d900f8, 0xce008020, 0x004e009f, 0x04fefdff, 0xfa59f5f0, 0x00f8019f, - 0x816128d9, 0x0fa4b600, 0xcea0a9bc, 0x004f00a9, 0x049ffdf0, 0xfa6495f0, 0x00f801a9, 0x8c0fa4b6, - 0x8b002434, 0xbf002464, 0xf0afbccf, 0x9800f9ce, 0xcd9802ce, 0x049efd01, 0xfa059dfd, 0xcc9001f9, - 0xf4cba60c, 0x00f8e41b, 0x0024648f, 0xa4b6febf, 0xe0aebc0f, 0x9800e9ce, 0xff9801fd, 0x049ffd02, - 0xfa059dfd, 0x648f01e9, 0xf9980024, 0xa0a9bc03, 0x9800a9ce, 0xff9804fe, 0x049ffd05, 0xfa059efd, - 0x00f801a9, 0x8c0fa4b6, 0x8b002368, 0xbf0023e0, 0xf0afbccf, 0x9800f9ce, 0xcd9802ce, 0x049efd01, - 0xfa059dfd, 0xcc9001f9, 0xf4cba60c, 0x00f8e41b, 0x812828d9, 0x0fa4b600, 0xcea0a9bc, 0xff8f00a9, - 0x9ffdff00, 0x0095f104, 0x01a9fa68, 0x048f00f8, 0xfebf0021, 0xbc0fa4b6, 0xe9cee0ae, 0x01fd9800, - 0xfd02ff98, 0x9dfd049f, 0x01e9fa05, 0x0021048f, 0xbc03f998, 0xa9cea0a9, 0x04fe9800, 0xfd05ff98, - 0x9efd049f, 0x01a9fa05, 0x28d900f8, 0xb6008161, 0xa9bc0fa4, 0x00a9cea0, 0xfdf0004f, 0x95f0049f, - 0x01a9fa6c, 0xb88f00f8, 0xfebf0021, 0xbc0fa4b6, 0xe9cee0ae, 0x01fd9800, 0xfd02ff98, 0x9dfd049f, - 0x01e9fa05, 0x0021b88f, 0xbc03f998, 0xa9cea0a9, 0x04fe9800, 0xfd05ff98, 0x9efd049f, 0x01a9fa05, - 0x8cd900f8, 0xb600816a, 0xa9bc0fa4, 0x00a9cea0, 0xf8ffff8f, 0x8f049ffd, 0xfd070000, 0xa9fa059f, - 0xb600f801, 0xfc8c0fa4, 0x048b001f, 0xcfbf0021, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, + 0x0ccc9001, 0x1bf4cba6, 0xd900f8e4, 0x00816a8c, 0xbc0fa4b6, 0xa9cea0a9, 0xffff8f00, 0x049ffdf8, + 0x0700008f, 0xfa059ffd, 0x00f801a9, 0x812828d9, 0x0fa4b600, 0xcea0a9bc, 0xff8f00a9, 0x9ffdff00, + 0x0095f104, 0x01a9fa68, 0xa4b600f8, 0x23688c0f, 0x23e08b00, 0xbccfbf00, 0xf9cef0af, 0x02ce9800, + 0xfd01cd98, 0x9dfd049e, 0x01f9fa05, 0xa60ccc90, 0xe41bf4cb, 0xd08f00f8, 0xfdbf0021, 0x9800d9ce, + 0xff9801fe, 0x049ffd02, 0xfa059efd, 0xd08f01d9, 0xfd980021, 0x00d9ce03, 0x9804fe98, 0x9ffd05ff, + 0x059efd04, 0x8f01d9fa, 0x980021d0, 0xd9ce06fd, 0x07fe9800, 0xfd08ff98, 0x9efd049f, 0x01d9fa05, + 0x0021f48c, 0x8b0fa4b6, 0xbf002368, 0xf0afbccf, 0x9800f9ce, 0xcd9802ce, 0x049efd01, 0xfa059dfd, + 0xcc9001f9, 0xf4cba60c, 0x00f8e41b, 0x816128d9, 0x0fa4b600, 0xcea0a9bc, 0x004f00a9, 0x049ffdf0, + 0xfa6c95f0, 0x00f801a9, 0x803814de, 0x00e9ce00, 0xffffffdf, 0x049ffd00, 0x000000df, 0x059ffd06, + 0xf801e9fa, 0x24648f00, 0xb6febf00, 0xaebc0fa4, 0x00e9cee0, 0x9801fd98, 0x9ffd02ff, 0x059dfd04, + 0x8f01e9fa, 0x98002464, 0xa9bc03f9, 0x00a9cea0, 0x9804fe98, 0x9ffd05ff, 0x059efd04, 0xf801a9fa, + 0x2088d900, 0x9fce0080, 0xff004e00, 0xf004fefd, 0x9ffa59f5, 0xb600f801, 0x348c0fa4, 0x648b0024, + 0xcfbf0024, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, 0xf9fa059d, 0x0ccc9001, 0x1bf4cba6, + 0xb600f8e4, 0xfc8c0fa4, 0x048b001f, 0xcfbf0021, 0xcef0afbc, 0xce9800f9, 0x01cd9802, 0xfd049efd, 0xf9fa059d, 0x0ccc9001, 0x1bf4cba6, 0x8f00f8e4, 0xbf0017d0, 0x019990f9, 0x00f8f9a0, 0xa0f990f9, - 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006cfb7e, 0xe8fee0fc, 0xfef0fc00, + 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006cdb7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, - 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006ddf7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, + 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006dbf7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, - 0xe0f9018e, 0x00708c7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, - 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006d8e7e, + 0xe0f9018e, 0x0070787e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, + 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006d6e7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, - 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006cad7e, 0xe8fee0fc, 0xfef0fc00, + 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006c8d7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, - 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006c5f7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, + 0x9ffef0f9, 0xfef0f901, 0xe0f9018e, 0x006c3f7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, 0x00f801f8, 0xa0f990f9, 0xc0f9b0f9, 0xe0f9d0f9, 0x9ffef0f9, 0xfef0f901, - 0xe0f9018e, 0x006a2f7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, - 0x00f801f8, 0x0017d489, 0x9433993f, 0x0a0a0c01, 0x107eb4bd, 0x46890000, 0x93fe0000, 0x492e0f00, - 0x9ffa0080, 0x5ad67e00, 0x08004900, 0x8f0099cf, 0xfd010000, 0x0bf4049f, 0x02af7e0e, 0x00468900, - 0x0093fe00, 0x00021b7e, 0x0020fd7e, 0x006a748a, 0x0000e17e, 0x006aac8a, 0x0000f97e, 0x006ae48a, - 0x0001117e, 0x006a3c8a, 0x0001297e, 0x006b1c8a, 0x0001417e, 0x006b548a, 0x0001597e, 0x006b8c8a, - 0x0001717e, 0x0001897e, 0x0004627e, 0x00022c7e, 0xd489010f, 0x9f200017, 0x3e0028f4, 0xf9006c58, - 0x08404912, 0xc70099cf, 0x1ab27491, 0x0002407e, 0x1000a433, 0x010b090a, 0x0000107e, 0x006cab3e, + 0xe0f9018e, 0x006a0f7e, 0xe8fee0fc, 0xfef0fc00, 0xf0fc00f9, 0xd0fce0fc, 0xb0fcc0fc, 0x90fca0fc, + 0x00f801f8, 0x0017d489, 0x9433993f, 0x0a0a0c01, 0x107eb4bd, 0x46890000, 0x93fe0000, 0x492f0f00, + 0x9ffa0080, 0x5ab67e00, 0x08004900, 0x8f0099cf, 0xfd010000, 0x0bf4049f, 0x02af7e0e, 0x00468900, + 0x0093fe00, 0x00021b7e, 0x0020df7e, 0x006a548a, 0x0000e17e, 0x006a8c8a, 0x0000f97e, 0x006ac48a, + 0x0001117e, 0x006a1c8a, 0x0001297e, 0x006afc8a, 0x0001417e, 0x006b348a, 0x0001597e, 0x006b6c8a, + 0x0001717e, 0x0001897e, 0x0004627e, 0x00022c7e, 0xd489010f, 0x9f200017, 0x3e0028f4, 0xf9006c38, + 0x08404912, 0xc70099cf, 0x1ab27491, 0x0002407e, 0x1000a433, 0x010b090a, 0x0000107e, 0x006c8b3e, 0x02a010b8, 0x0204b600, 0xe4000bce, 0xb2ffffbc, 0xf0bbc71a, 0x000ac87e, 0x02b019b8, 0x0294b600, 0xd9009afa, 0x80000000, 0xfb0109fa, 0x4912f911, 0x99cf0840, 0x7091c700, 0x407e1ab2, 0xa4330002, - 0x080a1000, 0x107e010b, 0xf93e0000, 0x10b8006c, 0xb6000260, 0x0bce0204, 0xffbce400, 0xc71ab2ff, + 0x080a1000, 0x107e010b, 0xd93e0000, 0x10b8006c, 0xb6000260, 0x0bce0204, 0xffbce400, 0xc71ab2ff, 0xc87ef0bb, 0x19b8000a, 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0x8f006ddd, 0x94010060, 0x9fbc0f09, 0x0000df90, 0x9ffd0080, - 0x0091ce05, 0x000000d9, 0x9419ff11, 0xb2090bf4, 0x24ae7e0a, 0xb20ab200, 0x00807e1b, 0xf911fb00, - 0x08404922, 0xc40099cf, 0x1ab20f91, 0x0002407e, 0x1200a433, 0x010b040a, 0x107e24bd, 0x613e0000, - 0x19b80070, 0xb6000240, 0x92cf0294, 0xff20c400, 0xfd0209b3, 0x7e1ab200, 0x0b00038e, 0x00a9330b, - 0x09b30238, 0xb0017111, 0x0cf41106, 0x0609b367, 0x06b0010c, 0x2c0cf406, 0xd50209b3, 0x0206b000, - 0xb3110cf4, 0x021e0009, 0x3e010db3, 0x6f033e02, 0x0409b300, 0x06b000d4, 0xd60cf504, 0x6f1b3e00, - 0x0d09b300, 0x06b00100, 0x180cf40d, 0xe10809b3, 0x0806b000, 0x00cf08f5, 0x0e0c0db3, 0x6f573e02, - 0x0f09b300, 0x06b000f4, 0xf60cf50f, 0x6f6b3e00, 0x4109b300, 0x06b10170, 0x0cf40041, 0x1809b334, - 0x06b0012f, 0x160cf418, 0xff1509b3, 0x1709b300, 0x0db30115, 0x3e01d414, 0xb3006f9d, 0x012c2109, - 0x314009b3, 0x200db301, 0xd63e01c1, 0x09b3006f, 0xb1015b60, 0xf4006006, 0x09b3190c, 0xb1013b43, - 0xf5004306, 0xb3012808, 0x019f580d, 0x00701f3e, 0x4d7009b3, 0x7109b301, 0x0db30152, 0x3e018c61, - 0xb2007033, 0x25287e1a, 0x6fdc3e00, 0x0b1ab200, 0x7ec4bd01, 0x3e000261, 0xb2007061, 0x15a57e1a, - 0x6fdc3e00, 0x7e1ab200, 0x3e002883, 0xb2007061, 0x18197e1a, 0x70613e00, 0x7e1ab200, 0x3e002737, - 0xb2007061, 0x26557e1a, 0x6fdc3e00, 0x7e1ab200, 0x3e0024eb, 0xb2007061, 0x21817e1a, 0x6fdc3e00, - 0x7e1ab200, 0x3e005773, 0xb2006fdc, 0x53b47e1a, 0x6fdc3e00, 0x7e1ab200, 0x3e0052d0, 0xb2006fdc, - 0x177f7e1a, 0xb2010b00, 0x7e1ab2ac, 0x3e0021fa, 0xb2006fdc, 0x22967e1a, 0x6fdc3e00, 0x7e1ab200, - 0x3e00145f, 0x0b006fdc, 0x0c1ab201, 0x13a77e01, 0xb3abb200, 0x009e00ad, 0xcb7e1ab2, 0xdc3e0014, - 0x1ab2006f, 0x0018d17e, 0x0070613e, 0xfb7e1ab2, 0xdc3e001a, 0x1ab2006f, 0x00296b7e, 0xa9b3abb2, - 0x3e008300, 0xb2007051, 0x29c77e1a, 0x70613e00, 0x08b04b00, 0xb200bbcf, 0x5c1a7e1a, 0x70613e00, - 0x7e1ab200, 0x3e00188b, 0xb2007061, 0x189f7e1a, 0x70613e00, 0x7e1ab200, 0x3e0018aa, 0xb2007061, - 0x1d8d7e1a, 0x6fdc3e00, 0x7e1ab200, 0x3e0019fc, 0xb2007061, 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0x10a395ff, 0x48fea4b2, - 0x0147fe01, 0x903c8890, 0x8bb53477, 0x017db501, 0x0bb27ca0, 0x1ab28aa0, 0x0076ce7e, 0xa6b20bb2, - 0xce7e2ab2, 0x3bb20076, 0x1ab2a0b2, 0x0076ce7e, 0xa1b23bb2, 0xce7e2ab2, 0x10bc0076, 0x10699500, - 0x09bcadb2, 0xf410a600, 0x00890a0d, 0xd9bc0100, 0x017b98d0, 0xffff69e4, 0xfe100f94, 0xf9bc014e, - 0x24ee90f0, 0xa0100995, 0x90d9bcef, 0xbf01e9b5, 0x01ed98ec, 0x41fe4ab2, 0x2c119001, 0xa0011db5, - 0x76ce7e1c, 0x018b9800, 0x5ab2a0b2, 0x0076ce7e, 0xbc011b98, 0x1abf000a, 0xfbb00bbc, 0x30f42085, - 0x00c0b3f0, 0x014ffe33, 0xb508ff90, 0xfaa001fb, 0x9cbb2009, 0x0096b002, 0xbc211df4, 0xb9bcf5ac, - 0x014afe94, 0xbc059ffd, 0xa9a0f5bc, 0x9801afb5, 0xaabf01ab, 0xf81030f4, 0x014afe00, 0xbd019fb9, - 0xf5bfbc94, 0xa001a9b5, 0x01ab98af, 0x543eaabf, 0x30f40072, 0xfe82f9e4, 0x49fe014f, 0x30ff9001, - 0xb5389990, 0xfca001fd, 0xa0019bb5, 0xb2c2b29a, 0x00ddb3a6, 0xcba600bb, 0x00f70df5, 0x00ffff89, - 0x0cf5c9a6, 0xc6b1037a, 0x0df500ff, 0x080903af, 0x29bc180d, 0x24888fe5, 0x98fe3c00, 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0x73fc3e00, 0xb2a9b200, 0x00a6b0af, 0xb22b1ef4, 0x00b6b0ba, 0xff131ef4, - 0xb9ffacfa, 0x051ef496, 0xaab900f8, 0xb900f801, 0xfaff01ba, 0x96b9ffac, 0x3ef01ff4, 0xb90076aa, - 0xbab201af, 0xf400b6b0, 0xaf3ed81f, 0xaf950076, 0x10b99510, 0xff91a9ff, 0xbffda0ba, 0xb0b9bc01, - 0xbc10b4b6, 0x00f8a0ba, 0x1400c0b3, 0xb93c94bd, 0x99af3cf8, 0xa6019990, 0xf51bf49c, 0x02f800f8, + 0x0a1000a4, 0x7e010b05, 0x3e000010, 0x8f006dbd, 0x94010060, 0x9fbc0f09, 0x0000df90, 0x9ffd0080, + 0x0091ce05, 0x000000d9, 0x9419ff11, 0xb2090bf4, 0x248e7e0a, 0xb20ab200, 0x00807e1b, 0xf911fb00, + 0x08404922, 0xc40099cf, 0x1ab20f91, 0x0002407e, 0x1200a433, 0x010b040a, 0x107e24bd, 0x4d3e0000, + 0x19b80070, 0xb6000240, 0x92cf0294, 0xff20c400, 0xff0209b3, 0x7e1ab200, 0x0b00038e, 0x00a9330b, + 0x09b30244, 0xb0011712, 0x0cf41206, 0x0709b369, 0x06b00122, 0x2e0cf407, 0xe50309b3, 0x0306b000, + 0xb3130cf4, 0x00c20109, 0xf50106b0, 0x3e00c40c, 0xb300704d, 0x00de0509, 0xf50506b0, 0x3e00ea0c, + 0xb3006f07, 0x01140e09, 0xf40e06b0, 0x09b3180c, 0xb000f50c, 0x0cf50c06, 0x0db300f7, 0x3e021808, + 0xb3006f39, 0x010f1009, 0xf51006b0, 0x3e011b0c, 0xb3006f61, 0x017a4109, 0x004106b1, 0xb3340cf4, + 0x01401809, 0xf41806b0, 0x09b3160c, 0xb3011015, 0x01261709, 0xde140db3, 0x6f903e01, 0x2109b300, + 0x09b30136, 0xb3013b40, 0x01cb200d, 0x006fc93e, 0x656009b3, 0x6006b101, 0x190cf400, 0x454309b3, + 0x4306b101, 0x3208f500, 0x580db301, 0x0b3e01a9, 0x09b30070, 0xb3015770, 0x015c7109, 0x96610db3, + 0x701f3e01, 0x7e1ab200, 0x3e002508, 0xb2006f67, 0xbd010b1a, 0x02617ec4, 0x704d3e00, 0x7e1ab200, + 0x3e00158b, 0xb2006f67, 0x28637e1a, 0x704d3e00, 0xbd1ab200, 0x6f1d3eb4, 0x0b1ab200, 0x17cc7e01, + 0x704d3e00, 0x7e1ab200, 0x3e002717, 0xb200704d, 0x26357e1a, 0x6f673e00, 0x7e1ab200, 0x3e0024cb, + 0xb200704d, 0x21637e1a, 0x6f673e00, 0x7e1ab200, 0x3e005753, 0xb2006f67, 0x53947e1a, 0x6f673e00, + 0x7e1ab200, 0xb20052b0, 0x00a9b3ab, 0x3d3e00e4, 0x1ab20070, 0x0017657e, 0xacb2010b, 0xdc7e1ab2, + 0x673e0021, 0x1ab2006f, 0x0022787e, 0x006f673e, 0x3d7e1ab2, 0x673e0014, 0x010b006f, 0x010c1ab2, + 0x0013a77e, 0xadb3abb2, 0xb2009700, 0x14b17e1a, 0x6f673e00, 0x7e1ab200, 0x3e0018b3, 0xb200704d, + 0x1add7e1a, 0x6f673e00, 0x7e1ab200, 0x3e00294b, 0xb2006f67, 0x29a77e1a, 0x704d3e00, 0x08b04b00, + 0xb200bbcf, 0x5bfa7e1a, 0x704d3e00, 0x7e1ab200, 0x3e00186d, 0xb200704d, 0x18817e1a, 0x704d3e00, + 0x7e1ab200, 0x3e00188c, 0xb200704d, 0x1d6f7e1a, 0x6f673e00, 0x7e1ab200, 0x3e0019de, 0xb200704d, + 0x196f7e1a, 0x704d3e00, 0x7e1ab200, 0x3e00084d, 0xb200704d, 0x07c77e1a, 0x704d3e00, 0x04b0b300, + 0x7e1ab210, 0x0e00177b, 0x704f3e01, 0xb8e4bd00, 0x0002401d, 0xffffffdf, 0x1ee4b6bf, 0xd902d4b6, + 0x80000000, 0xfd9529ff, 0xe9fd049f, 0x00defa05, 0x100b21fb, 0x0070413e, 0x404922f9, 0x0099cf08, + 0xb26491c7, 0x02407e1a, 0x00a43300, 0x0b030a10, 0x00107e01, 0x71513e00, 0x7e1ab200, 0xb20001e7, + 0x0ca0b3a0, 0x0ca6b062, 0xb3130cf4, 0xb32002a0, 0xb33803a0, 0x3e5e00a0, 0xb3007141, 0xb36811a0, + 0xb36e12a0, 0x3e7e0da4, 0xb200711b, 0x1ba97e1a, 0xb2a2b200, 0x00507e1a, 0x0020b300, 0xb21ab278, + 0x3e2cb20b, 0xb200714d, 0x1cd67e1a, 0xb2a0b200, 0x00507e1a, 0x0000b300, 0xb21ab25c, 0x3e020b0c, + 0xb200714d, 0x7e020b1a, 0x3d001815, 0x18567ea4, 0x7e1ab200, 0x3e000050, 0xb2007151, 0x3e030b1a, + 0xb2007107, 0x554f7e1a, 0x71333e00, 0x7e1ab200, 0xb20055b5, 0x00a0b3ac, 0x0b1ab21c, 0x714d3e19, + 0x7e1ab200, 0xb2000050, 0x0c020b1a, 0x02617e15, 0xf421fb00, 0x82f9e030, 0xffffc1e4, 0xb210c295, + 0xffa0e4c5, 0x10a395ff, 0x48fea4b2, 0x0147fe01, 0x903c8890, 0x8bb53477, 0x017db501, 0x0bb27ca0, + 0x1ab28aa0, 0x0076ba7e, 0xa6b20bb2, 0xba7e2ab2, 0x3bb20076, 0x1ab2a0b2, 0x0076ba7e, 0xa1b23bb2, + 0xba7e2ab2, 0x10bc0076, 0x10699500, 0x09bcadb2, 0xf410a600, 0x00890a0d, 0xd9bc0100, 0x017b98d0, + 0xffff69e4, 0xfe100f94, 0xf9bc014e, 0x24ee90f0, 0xa0100995, 0x90d9bcef, 0xbf01e9b5, 0x01ed98ec, + 0x41fe4ab2, 0x2c119001, 0xa0011db5, 0x76ba7e1c, 0x018b9800, 0x5ab2a0b2, 0x0076ba7e, 0xbc011b98, + 0x1abf000a, 0xfbb00bbc, 0x30f42085, 0x00c0b3f0, 0x014ffe33, 0xb508ff90, 0xfaa001fb, 0x9cbb2009, + 0x0096b002, 0xbc211df4, 0xb9bcf5ac, 0x014afe94, 0xbc059ffd, 0xa9a0f5bc, 0x9801afb5, 0xaabf01ab, + 0xf81030f4, 0x014afe00, 0xbd019fb9, 0xf5bfbc94, 0xa001a9b5, 0x01ab98af, 0x403eaabf, 0x30f40072, + 0xfe82f9e4, 0x49fe014f, 0x30ff9001, 0xb5389990, 0xfca001fd, 0xa0019bb5, 0xb2c2b29a, 0x00ddb3a6, + 0xcba600bb, 0x00f70df5, 0x00ffff89, 0x0cf5c9a6, 0xc6b1037a, 0x0df500ff, 0x080903af, 0x29bc180d, + 0x24888fe5, 0x98fe3c00, 0xbbff94f0, 0xd0b302d9, 0xbdbc1800, 0xbb2009f4, 0x9dbb042d, 0x9569bc02, + 0xff046dbb, 0x2195b59f, 0xff25e410, 0x4cb1ffff, 0xb20db1ff, 0x7e5bb24a, 0xb60076ba, 0x69951004, + 0x0509fd10, 0x0df4a0a6, 0x01449214, 0xa60002bc, 0x090cf420, 0x0cf5a0a6, 0x0abb036f, 0xff5bb202, + 0x3ab23c01, 0x0076ba7e, 0xe40d01ff, 0xb6ffff69, 0x09fd1004, 0xf4a0a605, 0x3392160d, 0x0002bc01, + 0x0cf420a6, 0xf4a0a60b, 0x3392060d, 0x10499401, 0x39ffb4bd, 0x1c85fba5, 0x0cf5dba6, 0xff8900ec, + 0xd9a600ff, 0x00e90cf5, 0x00ffd6b1, 0x02f10df5, 0x180c0809, 0x8fe5d9bc, 0x3c002488, 0x94f098fe, + 0x72c9bcff, 0xed007db3, 0xf4dba600, 0x26a60908, 0x00b60cf5, 0xb4bd010a, 0xb31c85fb, 0x090900c4, + 0x0092cc01, 0x00ffff89, 0x0cf529a6, 0x26b101c7, 0x0df500ff, 0x080902bb, 0x29bc180d, 0x24888fe5, + 0x98fe3c00, 0xbcff94f0, 0x4db342d9, 0xbc01cb00, 0x239502b2, 0xff25e410, 0xff0107ff, 0x5bb24c03, + 0xba7e4ab2, 0x03ff0076, 0x1069950d, 0xfd1004b6, 0xa0a60509, 0x92140df4, 0x02bc0144, 0xf420a600, + 0xa0a6090c, 0x028b0cf5, 0xb2020abb, 0x1c03ff5b, 0xba7e1ab2, 0x03ff0076, 0xff69e40d, 0x1004b6ff, + 0xa60509fd, 0x160df4a0, 0xbc011192, 0x20a60002, 0xa60b0cf4, 0x060df4a0, 0x94011192, 0x7bb21049, + 0xfba519ff, 0xa4bd1c85, 0x85fbb4bd, 0xffffd91c, 0xd9a600ff, 0x02010df5, 0x888f1809, 0xd9bc0024, + 0x98fe3ce5, 0x94f0080c, 0x72c9bcff, 0x1d0079b3, 0x9427bcff, 0xbbe4b7bc, 0x91b004d7, 0xbb200909, + 0xb9bc0297, 0xf569bc05, 0xff9529bc, 0x9dff85fe, 0x10439545, 0xffff41e4, 0xb25c03ff, 0x7e5ab21b, + 0xff0076ba, 0x89950d03, 0x1004b610, 0xa60509fd, 0x190df4a0, 0xbc015592, 0x40a60004, 0xa60e0cf4, + 0x090df4a0, 0xbc015592, 0x0abb0004, 0xff1bb202, 0x2ab22c03, 0x0076ba7e, 0xe40d03ff, 0xb6ffff89, + 0x09fd1004, 0xf4a0a605, 0x2292190d, 0x0004bc01, 0x0cf440a6, 0xf4a0a60e, 0x04bc090d, 0x01229200, + 0xb40910b4, 0x59940930, 0x820abc10, 0xf14529ff, 0xe4ffff14, 0xb2ffff40, 0x7e0ab21b, 0xb60076ba, + 0xa5b21035, 0x0ab23bb2, 0x0076ba7e, 0x42951bb2, 0xb2a0b210, 0x76ba7e2a, 0xb23bb200, 0x7e2ab2a1, + 0xbc0076ba, 0x59950010, 0x0009bc10, 0x0df410a6, 0x0000890a, 0xa0a9bc01, 0xbc100995, 0x8aa6a0a9, + 0x00ed08f5, 0x0bf58aa6, 0x4ab200d4, 0x85fbb4bd, 0xffffd91c, 0x29a600ff, 0x00fd0df5, 0x888f1809, + 0x29bc0024, 0x98fe3ce5, 0x94f0080d, 0x42d9bcff, 0x3f0049b3, 0xf4b4bcfe, 0x04bb2000, 0x9560bc02, + 0xbc0424bb, 0x239505b0, 0x859fff10, 0xe47c03ff, 0xb2ffff25, 0x7e5bb27a, 0xff0076ba, 0x89950d03, + 0x1004b610, 0xa60590ff, 0x190df4a0, 0xbc017792, 0x20a60002, 0xa60e0cf4, 0x090df4a0, 0xbc017792, + 0x0abb0002, 0xff5bb202, 0x1ab21c03, 0x0076ba7e, 0xe40d03ff, 0xb6ffff89, 0x09fd1004, 0xf4a0a605, + 0x1192190d, 0x0002bc01, 0x0cf420a6, 0xf4a0a60e, 0x1192090d, 0x0002bc01, 0xbb107994, 0x0abb0464, + 0x7519ff02, 0x0073bb3e, 0xffffffd9, 0xf4c9a600, 0x18094e0d, 0x9e3e080d, 0x0f940072, 0xff5ee410, + 0x9467bcff, 0xa6f0febc, 0x2118f59f, 0x014a92ff, 0x85fbb4bd, 0xb210091c, 0x73543e9c, 0x0c94bd00, + 0x73543e20, 0x0d94bd00, 0x729e3e20, 0x0d94bd00, 0x739a3e20, 0xb2100900, 0x739a3e9d, 0xb2100900, + 0x729e3e9d, 0x01449200, 0x3e0002bc, 0x920072fa, 0x02bc0144, 0x73e83e00, 0xb2a9b200, 0x00a6b0af, + 0xb22b1ef4, 0x00b6b0ba, 0xff131ef4, 0xb9ffacfa, 0x051ef496, 0xaab900f8, 0xb900f801, 0xfaff01ba, + 0x96b9ffac, 0x3ef01ff4, 0xb9007696, 0xbab201af, 0xf400b6b0, 0x9b3ed81f, 0xaf950076, 0x10b99510, + 0xff91a9ff, 0xbffda0ba, 0xb0b9bc01, 0xbc10b4b6, 0x00f8a0ba, 0x1400c0b3, 0xb93c94bd, 0x99af3cf8, + 0xa6019990, 0xf51bf49c, 0x02f800f8, 0x0202f802, 0xf80202f8, 0x02f80202, 0x0202f802, 0xf80202f8, 0x4c2f2637, 0xfc866c05, 0x254eb903, 0x179baf0f, 0xded1bf8c, 0x949f48e4, 0x95104317, 0xcee888a8, 0x90186199, 0xa8bd1766, 0x6a9d039e, 0x7c88dbe6, 0x3e355a39, 0xe8d1712e, 0xf4b369f0, 0xfdda049f, 0x7d4abea6, 0xdf8fb3c9, 0xae92df60, 0x8f1cb3bc, 0x6b04d605, 0xd1254c24, 0xf17782fd, 0x1cc60d9a, @@ -1057,11 +1057,11 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0x932146aa, 0x368a923f, 0x9fdadd0b, 0x16f2e758, 0x26c61195, 0x1272d745, 0x8894d060, 0xf540e36b, 0x9e2799bc, 0x642f4d4c, 0x648416a0, 0x4d2907eb, 0x932146aa, 0x368a923f, 0x9fdadd0b, 0x16f2e758, 0x26c61195, 0x1272d745, 0x8894d060, 0xf540e36b, 0x9e2799bc, 0x642f4d4c, 0x648416a0, 0x4d2907eb, - 0x00000002, 0x0000002e, 0x00000000, 0x00000000, 0x206e614a, 0x32203031, 0x20323230, 0x333a3930, - 0x32323a36, 0x00580020, 0x00000000, 0x00000000, 0x4bb116ce, 0x005a9e8c, 0xdc8cdfd1, 0x9ca9094d, - 0x39ecb736, 0x777b071c, 0xdac3f5b4, 0xa1bb964c, 0xb0f63b92, 0x340cb1d5, 0xd8a942a6, 0xf466ffab, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x9fa62a39, 0xeafd8b15, 0x4c979bb0, 0xed0365f5, - 0x620d246e, 0xac97f8b8, 0xfbe1a191, 0x508703bc, 0x0000e38e, 0x00000000, 0x0000f5c2, 0x00000000, + 0x00000002, 0x0000002f, 0x00000000, 0x00000000, 0x20727041, 0x32203832, 0x20333230, 0x323a3032, + 0x35323a35, 0x00580020, 0x00000000, 0x00000000, 0x4bb116ce, 0x005a9e8c, 0xdc8cdfd1, 0x9ca9094d, + 0xda7709f9, 0xdf7ab23f, 0x3217b5e2, 0xb61a8b41, 0xc3860933, 0x6f1fc8a0, 0x5c580d32, 0x3df0c6b1, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x292325fd, 0xc840854c, 0xed02136a, 0x8c08e29f, + 0xadf421a9, 0x118771c9, 0x9222e575, 0xaf1f02bd, 0x0000e38e, 0x00000000, 0x0000f5c2, 0x00000000, 0x0000fc0f, 0x00000000, 0x007a0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1361,7 +1361,7 @@ const NvU32 minion_ucode_data_lr10_prod[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000010, 0x00000000, 0x7c010001, 0x04100c13, 0x00000293, 0x0000002c, 0x00000018, 0x00007272, + 0x00000010, 0x00000000, 0x7c010001, 0x04100c13, 0x00000293, 0x0000002c, 0x00000018, 0x0000725e, 0x0000041b, 0x00000304, 0x04200e00, 0x00000002, 0x0980440e, 0x0b820a81, 0x0d840c83, 0x0f860e85, 0x11881087, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1591,3 +1591,4 @@ const NvU32 minion_ucode_header_lr10_prod[] = { const NvU32 minion_ucode_data_size_lr10_prod = 12096; #endif // _MINION_UCODE_LR10_PROD_H_ + diff --git a/src/common/nvswitch/kernel/inc/lr10/therm_lr10.h b/src/common/nvswitch/kernel/inc/lr10/therm_lr10.h index c6d3d68ab9..ea9298fdd7 100644 --- a/src/common/nvswitch/kernel/inc/lr10/therm_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/therm_lr10.h @@ -62,4 +62,11 @@ nvswitch_ctrl_therm_read_voltage_lr10 NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info ); +NvlStatus +nvswitch_ctrl_therm_read_power_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_POWER_PARAMS *info +); + #endif //_THERM_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/ls10.h b/src/common/nvswitch/kernel/inc/ls10/ls10.h index aa93b01488..431ca84765 100644 --- a/src/common/nvswitch/kernel/inc/ls10/ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/ls10.h @@ -186,6 +186,9 @@ #define DMA_ADDR_WIDTH_LS10 64 +#define SOE_VBIOS_VERSION_MASK 0xFF0000 +#define SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR 0x370000 + // // Helpful IO wrappers // @@ -500,10 +503,16 @@ typedef struct NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \ } -#define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS (10 * NVSWITCH_INTERVAL_1SEC_IN_NS) -#define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (10 * NVSWITCH_INTERVAL_1MSEC_IN_NS) +#define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS (12 * NVSWITCH_INTERVAL_1SEC_IN_NS) +#define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (12 * NVSWITCH_INTERVAL_1MSEC_IN_NS) // Struct used for passing around error masks in error handling functions +typedef struct +{ + NvBool bPending; + NvU32 regData; +} MINION_LINK_INTR; + typedef struct { NvU32 dl; @@ -513,17 +522,17 @@ typedef struct NvU32 tlcRx1Injected; NvU32 liptLnk; NvU32 liptLnkInjected; + MINION_LINK_INTR minionLinkIntr; } NVLINK_LINK_ERROR_INFO_ERR_MASKS, *PNVLINK_LINK_ERROR_INFO_ERR_MASKS; typedef struct -{ +{ NvBool bLinkErrorsCallBackEnabled; NvBool bLinkStateCallBackEnabled; + NvBool bResetAndDrainRetry; NVLINK_LINK_ERROR_INFO_ERR_MASKS fatalIntrMask; NVLINK_LINK_ERROR_INFO_ERR_MASKS nonFatalIntrMask; - - NvBool bResetAndDrainRetry; } NVLINK_LINK_ERROR_REPORTING; typedef struct @@ -795,7 +804,6 @@ typedef const struct #define nvswitch_ctrl_get_info_ls10 nvswitch_ctrl_get_info_lr10 #define nvswitch_ctrl_set_switch_port_config_ls10 nvswitch_ctrl_set_switch_port_config_lr10 -#define nvswitch_ctrl_get_fom_values_ls10 nvswitch_ctrl_get_fom_values_lr10 #define nvswitch_ctrl_get_throughput_counters_ls10 nvswitch_ctrl_get_throughput_counters_lr10 #define nvswitch_save_nvlink_seed_data_from_minion_to_inforom_ls10 nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10 @@ -867,7 +875,6 @@ NvlStatus nvswitch_ctrl_get_nvlink_status_ls10(nvswitch_device *device, NVSWITCH NvlStatus nvswitch_ctrl_get_info_lr10(nvswitch_device *device, NVSWITCH_GET_INFO *p); NvlStatus nvswitch_ctrl_set_switch_port_config_lr10(nvswitch_device *device, NVSWITCH_SET_SWITCH_PORT_CONFIG *p); -NvlStatus nvswitch_ctrl_get_fom_values_lr10(nvswitch_device *device, NVSWITCH_GET_FOM_VALUES_PARAMS *p); NvlStatus nvswitch_ctrl_get_throughput_counters_lr10(nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p); void nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10(nvswitch_device *device, NvU32 linkId); void nvswitch_store_seed_data_from_inforom_to_corelib_lr10(nvswitch_device *device); @@ -973,6 +980,7 @@ void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvli void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 link); void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); +void nvswitch_set_dlpl_interrupts_ls10(nvlink_link *link); NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask); void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); @@ -992,9 +1000,6 @@ NvlStatus nvswitch_launch_ALI_ls10(nvswitch_device *device); NvlStatus nvswitch_ctrl_set_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p); NvlStatus nvswitch_ctrl_get_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p); -void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); -NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask); - void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); NvBool nvswitch_is_inforom_supported_ls10(nvswitch_device *device); @@ -1002,6 +1007,8 @@ void nvswitch_set_error_rate_threshold_ls10(nvlink_link *link, NvBool bIsDe void nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink_link *link, NvBool bEnable); NvlStatus nvswitch_reset_and_train_link_ls10(nvswitch_device *device, nvlink_link *link); NvBool nvswitch_are_link_clocks_on_ls10(nvswitch_device *device, nvlink_link *link, NvU32 clocksMask); +NvBool nvswitch_does_link_need_termination_enabled_ls10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_link_termination_setup_ls10(nvswitch_device *device, nvlink_link* link); void nvswitch_get_error_rate_threshold_ls10(nvlink_link *link); #endif //_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h b/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h index 25da73164c..e698a3631f 100644 --- a/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h @@ -24,6 +24,21 @@ #ifndef _MINION_NVLINK_DEFINES_PUBLIC_H_ #define _MINION_NVLINK_DEFINES_PUBLIC_H_ +//PAD REG READ API (Bug 2643883) +#define NV_MINION_UCODE_READUPHYPAD_ADDR 11:0 +#define NV_MINION_UCODE_READUPHYPAD_LANE 15:12 + +//FIELD FOR DEBUG_MISC_i DATA REGISTERS +#define NV_MINION_DEBUG_MISC_0_LINK_STATE 7:0 +#define NV_MINION_DEBUG_MISC_0_ISR_ID 15:8 +#define NV_MINION_DEBUG_MISC_0_OTHER_DATA 31:16 + +// Recal values checks +#define NV_MINION_UCODE_L1_EXIT_MARGIN 100 +#define NV_MINION_UCODE_L1_EXIT_MAX 200 +#define NV_MINION_UCODE_RECOVERY_TIME 250 +#define NV_MINION_UCODE_PEQ_TIME 96 + // SUBCODES for DLCMD FAULT (uses DLCMDFAULR code) - dlCmdFault() - NVLINK_LINK_INT typedef enum _MINION_STATUS { @@ -31,4 +46,6 @@ typedef enum _MINION_STATUS MINION_ALARM_BUSY = 80, } MINION_STATUS; + #define LINKSTATUS_EMERGENCY_SHUTDOWN 0x29 + #define LINKSTATUS_INITPHASE1 0x24 #endif // _MINION_NVLINK_DEFINES_PUBLIC_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h index d018436422..abdc5f3c6d 100644 --- a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,9 +39,16 @@ void nvswitch_cci_soe_callback_ls10(nvswitch_device *device, RM_FLCN_MSG *pGenMs void *pParams, NvU32 seqDesc, NV_STATUS status); NvlStatus nvswitch_set_nport_tprod_state_ls10(nvswitch_device *device, NvU32 nport); void nvswitch_soe_unregister_events_ls10(nvswitch_device *device); +void nvswitch_therm_soe_callback_ls10(nvswitch_device *device, union RM_FLCN_MSG *pMsg, + void *pParams, NvU32 seqDesc, NV_STATUS status); NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device); NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport); NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport); void nvswitch_soe_init_l2_state_ls10(nvswitch_device *device); +void nvswitch_heartbeat_soe_callback_ls10(nvswitch_device *device, RM_FLCN_MSG *pGenMsg, + void *pParams, NvU32 seqDesc, NV_STATUS status); +NvlStatus nvswitch_soe_set_nport_interrupts_ls10(nvswitch_device *device, NvU32 nport, NvBool bEnable); +void nvswitch_soe_disable_nport_fatal_interrupts_ls10(nvswitch_device *device, NvU32 nport, + NvU32 nportIntrEnable, NvU8 nportIntrType); #endif //_SOE_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/therm_ls10.h b/src/common/nvswitch/kernel/inc/ls10/therm_ls10.h index e49d710391..2f11ea8c66 100644 --- a/src/common/nvswitch/kernel/inc/ls10/therm_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/therm_ls10.h @@ -56,4 +56,11 @@ nvswitch_ctrl_therm_read_voltage_ls10 nvswitch_device *device, NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info ); + +NvlStatus +nvswitch_ctrl_therm_read_power_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_POWER_PARAMS *info +); #endif //_THERM_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/pmgr_nvswitch.h b/src/common/nvswitch/kernel/inc/pmgr_nvswitch.h index 7f86d5e4c7..02e2b5e072 100644 --- a/src/common/nvswitch/kernel/inc/pmgr_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/pmgr_nvswitch.h @@ -164,16 +164,6 @@ typedef struct NvBool bBlockProtocol; } NVSWITCH_I2C_HW_CMD, *PNVSWITCH_I2C_HW_CMD; - -typedef enum -{ - NVSWITCH_I2C_ACQUIRER_NONE = 0, - NVSWITCH_I2C_ACQUIRER_UNKNOWN, - NVSWITCH_I2C_ACQUIRER_IOCTL, // e.g. MODS - NVSWITCH_I2C_ACQUIRER_EXTERNAL, // e.g. Linux Direct - -} NVSWITCH_I2C_ACQUIRER; - typedef enum { i2cProfile_Standard, i2cProfile_Fast, diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index bbc53edd82..53f6e82049 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -116,8 +116,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f9881, 0x000f8c82, 0x2abf10bf, 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x78890b18, 0x423e0010, 0x7c89000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, - 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x548f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf000554, + 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x5c8f1132, 0xf9bf0005, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf00055c, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0038a77e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, @@ -179,7 +179,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x31008fff, - 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e001104, + 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00056088, 0x8120597c, 0x3e001104, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0031248f, 0x18909fbc, 0x19180190, @@ -208,7 +208,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0c004d81, 0xcf0b004c, 0xcecf00df, 0x00d9cf00, 0x1bf4f9a6, 0xb5aea0f5, 0x00f801af, 0xcf0b0049, 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, - 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000554, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, + 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x0000055c, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, 0x00289880, 0x8cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3550daf2, 0x50db0000, 0x7e000033, 0x7e0015f6, 0xf7000b68, 0x8cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, @@ -349,7 +349,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x223e02f8, 0xf9cf0027, 0x4c99c700, 0x390090b3, 0xf60190b3, 0x363e02f8, 0xa48f0027, 0x008901ad, 0x9ff601c1, 0xb8f4bd00, 0x00010099, 0xdf009ff6, 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x27363e9f, 0xe400f800, 0xc7ff00bf, 0xaeb2f0b9, - 0xdfd59fff, 0x0000055c, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, + 0xdfd59fff, 0x00000564, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, 0x7501ff58, 0x00f809ef, 0x3f04ff90, 0x009433f9, 0xf8010adf, 0x0aa9b200, 0x00b0b302, 0x3db92008, 0xf900f8a4, 0xb3a0b202, 0x986500a0, 0x90b305a9, 0x0cd95e00, 0xbf000014, 0xe8aab89a, 0x277e0004, 0xa9e7001a, 0x9ab30168, 0xb34c0fff, 0xb6470090, 0xaab314a5, 0xb3400fff, 0x983b00a0, 0x94b6050e, @@ -443,19 +443,19 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xdcdff430, 0xf9000005, 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, - 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06c, 0x00a0b31a, 0x7eb43d1a, 0xb300b104, - 0xbf1200a0, 0x7eff001a, 0x3e00b63e, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, + 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06d, 0x00a0b31a, 0x7eb43d1a, 0xb300b105, + 0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000, 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e, 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50741, 0x352bb201, 0x42b51540, 0xbd92a006, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, 0x980d0090, 0x95f00149, 0x0149b508, 0x000644d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, - 0x95f101f9, 0xf9b54000, 0x299cda01, 0x027e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, + 0x95f101f9, 0xf9b54000, 0x299cda01, 0x037e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, 0xb20091b0, 0xbdb4bd0d, 0x2e70da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, - 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ee7e2b, 0x1fa43300, - 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x0095097e, 0x061fa033, 0xb4bd09f8, 0x097e020a, - 0x9cda0095, 0x7e000029, 0xfe009ab1, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, + 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ef7e2b, 0x1fa43300, + 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x00950a7e, 0x061fa033, 0xb4bd09f8, 0x0a7e020a, + 0x9cda0095, 0x7e000029, 0xfe009ab2, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, 0xd9320204, 0x00000644, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, 0x159f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, 0x033e9824, 0x002a3cd9, 0x2a44df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, @@ -463,8 +463,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, - 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0524de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, - 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b87e, 0x0036063e, 0x1bb20ab2, + 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x052cde3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, + 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b97e, 0x0036063e, 0x1bb20ab2, 0x3e7e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, 0x0000d9be, 0xe9ff4000, 0x6b0bf494, 0x681fa433, 0x900149fe, 0x9dbf4099, 0xbf049992, 0x1ee4339c, 0x0003df42, 0xff89ff00, 0xefff3fff, 0x94d9fff4, 0xff0294b6, 0xc0b3e5f9, 0xe9c50b00, 0x36703e03, @@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, - 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, + 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, @@ -646,7 +646,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x005d0a7e, 0x001404da, 0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7ca, + 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, @@ -662,7 +662,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00, 0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204, 0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014, - 0x95f90e99, 0x1e0a00f8, 0x00b9a17e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, + 0x95f90e99, 0x1e0a00f8, 0x00b9a27e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8, 0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00, 0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000, @@ -751,7 +751,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, 0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01, - 0x4c8900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a09f8, + 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a09f8, 0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, 0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0, 0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00, @@ -859,7 +859,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0xde3e02f8, 0xf9cf0066, 0x4c99c700, 0x3a0090b3, 0xf60190b3, 0xf23e02f8, 0x00d90066, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x006e7e14, 0x0149fe00, 0xbf1c9990, 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0608de00, 0x9fc70000, - 0x1899c710, 0x3515ef35, 0x063e14e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, + 0x1899c710, 0x3516ef35, 0x063e15e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0xf23e9fb2, 0x00890066, 0x99cf01c2, 0x009fe400, 0xff94f120, 0x00fdb33f, 0xc13eff40, 0x448f0066, 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890066a8, 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efec700, 0x8f006681, @@ -1157,371 +1157,371 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2875fb00, 0x00299cd9, 0x15991800, 0xbeb2adb2, 0x0a009033, 0x008b707e, 0x44d900f8, 0xbf000006, 0xb2cab29b, 0xb0bdbcec, 0x000b7e7e, 0x00f81f0a, 0xdff430f4, 0x000005dc, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, - 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xee7e0bb2, 0xa4330094, 0x4bfe551f, - 0x90020a01, 0xee7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, - 0x0f0204b3, 0x009a447e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee509, 0x14999001, 0x19a699bf, - 0x0a150bf4, 0x7e1bb201, 0x33009509, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 0xdf99bf10, + 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xef7e0bb2, 0xa4330094, 0x4bfe551f, + 0x90020a01, 0xef7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, + 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee50a, 0x14999001, 0x19a699bf, + 0x0a150bf4, 0x7e1bb201, 0x3300950a, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 0xdf99bf10, 0xbfffffff, 0xeffd1f0a, 0x0099b904, 0xf09419ff, 0x96f00b9c, 0x1e94b601, 0xa0059efd, 0x8d233e29, 0xfe1f0a00, 0x99900149, 0xd99fbf18, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40c35, 0x05dcdfe4, 0x52f90000, 0x49feffbf, 0x30999001, 0x9fa0a3b2, 0xc5b2afbf, 0xfdc7b4b2, 0x00ddb31d, - 0xfa95075c, 0x10f99508, 0xa132f032, 0xf9339232, 0x3000d515, 0x0cf415f6, 0x05f93346, 0xf63005fb, - 0x1c0cf405, 0x8701f933, 0x301f0a00, 0x08f501f6, 0xf6300739, 0x240cf503, 0x8e283e07, 0x10f93300, - 0xf630041a, 0x0e0cf410, 0xf50df630, 0x3e070e08, 0x33009155, 0x070611fd, 0x00915f3e, 0x421df933, - 0x1df63006, 0x33250cf4, 0x03fa18f9, 0xf418f630, 0xfd330c0c, 0x3e06e717, 0x33009408, 0x01001af9, - 0xd91cfd33, 0x94c53e06, 0x21f93300, 0xf6300262, 0x0c0cf421, 0xc51efd33, 0x8ecd3e06, 0x24f93300, - 0xfd330639, 0x3e06b725, 0xdf009499, 0x0000299c, 0x2614f918, 0x0d18f4a9, 0xbcffa9c4, 0x6e3e98f9, - 0xbda00093, 0x0094303e, 0x1d33080a, 0x7e069d00, 0x330063f7, 0x490a0300, 0xa9fdff00, 0x3e4aa004, - 0x0a009430, 0x04163003, 0x067f0cf5, 0x00299cd9, 0x0e99bf00, 0xbc080a01, 0x99c7f4e1, 0x049ffd98, - 0x06670bf5, 0x0e021033, 0x10041033, 0x843eea32, 0xeab2008e, 0x008e7a3e, 0x4bfea4bd, 0x2cbb9001, - 0x0063b47e, 0x008a847e, 0x3f1fad33, 0x0149fe06, 0xbf2c9990, 0x1fe9959e, 0x0a0190b3, 0xa73ed4bd, - 0x00dd008e, 0xc4ff0000, 0x943380e9, 0xf4bd0a00, 0x008ebe3e, 0xe6b0010f, 0x051ff400, 0xe995ff0f, - 0x95d9ff08, 0xa090f9bc, 0x94c73e49, 0xb29b3200, 0x7e5db24c, 0x3e0077ca, 0x330094c7, 0x305507a0, - 0x0cf407a6, 0x299cd912, 0xa6300000, 0x2b0df402, 0x008f243e, 0xf40ca630, 0x9cd9120c, 0x30000029, - 0x18f409a6, 0x8f473e57, 0x0da03300, 0x33030a61, 0x05b80e1d, 0x008f7a3e, 0xdf019998, 0x04000000, - 0x008f603e, 0xdf019998, 0x08000000, 0x008f603e, 0x00299cd9, 0x02999800, 0x0200008f, 0xf5049ffd, - 0x3e00c61b, 0x98009045, 0x008f0299, 0x9ffd0400, 0xc41bf504, 0x90453e00, 0x02999800, 0x0100008f, - 0xf4049ffd, 0x453e2f1b, 0x9cd90090, 0x8f000029, 0x98400000, 0x873e0299, 0x9cd9008f, 0x98000029, - 0x00df0299, 0xfd008000, 0x1bf5049f, 0x453e00a9, 0x10330090, 0x16307307, 0x1a0cf407, 0x4b021033, - 0xf4021630, 0x1033540c, 0x1d332700, 0x3e048601, 0x30008fd7, 0x0cf40c16, 0x0916300d, 0x3e6518f4, - 0x30009015, 0x0df40e16, 0x94303e6d, 0x7e4ab200, 0x3e00789f, 0x320094c7, 0xb22b321a, 0x7e5db24c, - 0x3e007cca, 0x320094c7, 0xb22b321a, 0x7e5db24c, 0x3e007c3b, 0x320094c7, 0xb22b321a, 0x7e467e4c, - 0x94c73e00, 0xb22b3200, 0x0a5db24c, 0x7ba27e07, 0x94c73e00, 0x32080a00, 0xb24cb22b, 0x7b037e5d, - 0x321a3200, 0xb23cb22b, 0x7e5eb24d, 0x3e007ed3, 0x320094c7, 0xb22b321a, 0xb24db23c, 0x78a77e5e, - 0x94c73e00, 0x3e080a00, 0x0a0094c7, 0x009d3304, 0x9cd9047a, 0x98000029, 0x080a0299, 0x400094f1, - 0x04670bf5, 0xfe0149fe, 0x99900142, 0x1822902c, 0x2da09da0, 0xa0049992, 0x0499929d, 0x99929da0, - 0x929da004, 0x9da00499, 0x85011933, 0x01163000, 0x0a0e08f4, 0x021d3303, 0x213e0432, 0x41fe0091, - 0x0140fe01, 0x902c1190, 0x1ab22800, 0x607e0bb2, 0x19bf0075, 0x43fe00bf, 0x0142fe01, 0x900794f0, - 0x22902433, 0xfe3ab220, 0x2bb20141, 0xf01c1190, 0x1cb20704, 0xfd0404b6, 0x5c7e0509, 0x29bf006a, - 0x1ebf3fbf, 0xb60141fe, 0xf4f00894, 0xff94f1ff, 0x10f4b6ff, 0x9018e4b6, 0x09fd1811, 0xfd1ab205, - 0x0efd050f, 0x6a497e05, 0x91473e00, 0x7e2ab200, 0xb2006a39, 0x7e20bf2a, 0xbf006a29, 0x914d3e29, - 0x0141fe00, 0xb2181190, 0x6a167e1a, 0xbf1ab200, 0x6a037e10, 0xb219bf00, 0xff04f11a, 0x1094b6ff, - 0x7e0590ff, 0xbf0069f0, 0xff94f119, 0xa040a0ff, 0x94303e59, 0x7efab200, 0x3e0095f3, 0x330094c7, - 0x330d00a0, 0x035c01ad, 0x0091ad3e, 0x9033b0bf, 0x94330c01, 0x9d3e2f02, 0x41fe0091, 0x90010a01, - 0x1bb21811, 0x0094ee7e, 0x3f1fad33, 0x091fbf03, 0x9509fffe, 0xa0049fff, 0x91a13e10, 0xff04f100, - 0xb22a3201, 0x95097e0b, 0x94c73e00, 0x7e9a3200, 0x3e0094ee, 0xb20094c7, 0x95227efa, 0x94c73e00, - 0x299cd300, 0x39bf0000, 0x000000df, 0xfd080a20, 0x0bf5049f, 0x030a02f5, 0xef001d33, 0x0140fe02, - 0x90014cfe, 0xcc902800, 0xfe0bb22c, 0x22900142, 0x7e2ab224, 0x7f007347, 0x03967009, 0x940b9cf0, - 0x0e7e0791, 0x30180001, 0x01087e58, 0x00003300, 0x3e1fb20a, 0x7f00924c, 0x00a4732a, 0x3e19b20a, - 0xc500924a, 0xa0734019, 0xa0731403, 0xa4731804, 0x9fe51c02, 0x4c3e0100, 0x9fe50092, 0x4c3e0200, - 0x9fe50092, 0x4c3e0300, 0x9fb20092, 0x900149fe, 0x997f2c99, 0x88049973, 0x04967000, 0x731a0cf4, - 0x70480190, 0x08f40196, 0x02907336, 0x039d734c, 0xce3e00e3, 0x99730092, 0x70009b07, 0x0cf40796, - 0x05907310, 0x069d7369, 0x033e00cb, 0x99730093, 0x73009c08, 0x00bd099d, 0x0093383e, 0xfe07ff89, - 0x3e04f9fd, 0x49009350, 0xf9ffc7ff, 0x0095f194, 0x92bf3e20, 0xc7ff4900, 0xf194f9ff, 0x8f180095, - 0xfdfe3fff, 0x9fe5049f, 0x503e4000, 0xff490093, 0x94f9ffc7, 0x100095f1, 0x0092bf3e, 0xffc7ff49, - 0x95f194f9, 0xf43e0800, 0xff490092, 0x94f9ffc7, 0x100095f1, 0xfe3fff8f, 0xe5049ffd, 0x3e80009f, - 0x49009350, 0xf9ffc7ff, 0x0095f194, 0x931b3e08, 0xc7ff4900, 0xf194f9ff, 0x8f100095, 0xfdfe3fff, - 0x9fe5049f, 0x503ec000, 0xff490093, 0x94f9ffc7, 0x080095f1, 0x0093423e, 0xffc7ff49, 0x95f194f9, - 0xff8f1000, 0x9ffdfe3f, 0x00008f04, 0xf59fff01, 0x00299cd9, 0x50991800, 0x0f009033, 0x02000089, - 0x3e95f9ff, 0x8900936e, 0xfffdffff, 0x49a094f9, 0x0094303e, 0xf514a630, 0xc401480c, 0xd0d9ffaf, - 0xbc000004, 0x9cd9e89f, 0x0a000029, 0x3befc708, 0xc7989fbc, 0x9fbb96ef, 0x0194f005, 0x012b0bf5, - 0xe7ff29c4, 0x54010def, 0x040a029b, 0x18f5bf66, 0xf3f00119, 0xffb9e400, 0xc2f9bcff, 0xf404c6b0, - 0x040c090d, 0x0093ca3e, 0xbae44da0, 0xe9c4ffff, 0x42ebe703, 0x00943301, 0xb0babc12, 0x0029bcd9, - 0x3e4ab200, 0xd90093f3, 0x00000644, 0xbabc99bf, 0xbc4ab2b0, 0x7e7eb09b, 0x303e000b, 0x9b320094, - 0x009aca7e, 0x0094c73e, 0x0f00a033, 0x1d33080a, 0x3e00b101, 0xfe0094c7, 0x00900140, 0x7e0ab224, - 0x3f0072fb, 0x00a54f09, 0x06009433, 0x4fa05a0f, 0xc73e1f0a, 0x9cd90094, 0x18000029, 0x99331599, - 0x33008700, 0x303802a0, 0x0cf402a6, 0x00a0330f, 0x01a43318, 0x946f3e6e, 0x03a03300, 0x04a4332c, - 0x948f3e62, 0x7e3ab200, 0x3e009d81, 0xb20094c7, 0x7ecbb2ba, 0x3e009ffb, 0x320094c7, 0x9d0a7e2a, - 0x94c73e00, 0x7e2a3200, 0x3e00a211, 0x320094c7, 0xa1a57e2a, 0x94c73e00, 0x299cd900, 0x99180000, - 0x00903315, 0x6cfbc724, 0x4db22c32, 0xa4f05eb2, 0x9eab7e0f, 0x94c73e00, 0x3e020a00, 0x0a0094c7, - 0x94c73e03, 0xfe090a00, 0x99900149, 0xd99fbf30, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, - 0xa4f01c55, 0x02a4b6ff, 0x1f0acaa0, 0xaf3200f8, 0xf630040a, 0x120cf402, 0xd9fff4f0, 0x00002a5c, - 0x0af89fbc, 0xf8bfa01f, 0x0aaf3200, 0x02f63004, 0xf0100cf4, 0x5cd9fff4, 0x0a00002a, 0xf99bbc1f, - 0x12f900f8, 0xb210af95, 0x08ae95b1, 0x00299cd0, 0x26ff0900, 0x3d1bf4e9, 0x26490918, 0xb21bf5f9, - 0x4a091800, 0x99331c0a, 0x3000ab01, 0x08f50196, 0x060a00a1, 0x9d029d33, 0x13099800, 0x1f0af43d, - 0x0918b9a0, 0x4a0f3549, 0x35019910, 0xf13e4909, 0x09180095, 0x330a0a4a, 0xd97a0094, 0x00002a5c, - 0xf4f099bf, 0xe899c7ff, 0xbc0694b6, 0xf6b0f0f9, 0x5e0cf43f, 0xe433030a, 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0x070d1806, 0xf0ffe4f0, 0xf4f0ff94, 0x0894b6ff, - 0xfd10f4b6, 0xd4b6059e, 0x05f9fd18, 0xf505dffd, 0x05045e0b, 0x03d6b005, 0x045d0cf5, 0xb3013db5, - 0x490e01d4, 0x39b55000, 0xb1d73e02, 0x080d1800, 0x18090918, 0x0e180a0f, 0xffd4f00b, 0xf0ff94f0, - 0x94b6fff4, 0x10f4b608, 0xb6059dfd, 0xf9fd18e4, 0x05effd05, 0xb2023eb5, 0x7e0bb23a, 0x9800a60b, - 0xff09023a, 0x1bf4a9a6, 0x3e04bd09, 0xb600b5ed, 0x3b9007a5, 0x033ab530, 0x00b6d17e, 0xadb3a5b2, - 0x9803f500, 0xc009033b, 0x90343a90, 0xb9fd3fbb, 0x03b5b604, 0x00b79e7e, 0xadb3a5b2, 0xfe03d900, - 0x48fe0147, 0x40779001, 0x799044bd, 0x3c889001, 0x3e0991b0, 0xbd00b347, 0xb38ea0e4, 0x980f0044, - 0xb4bd0c3a, 0x6a3efe0c, 0x3ab200b2, 0x7cb24bb2, 0x00a5787e, 0xadb3a5b2, 0x3f039d00, 0x0194f079, - 0x98120bf4, 0x4bb20c3a, 0x757eff0c, 0x443e00b6, 0x7ab200b3, 0x00a32f7e, 0x0f00a0b3, 0xb20c3a98, - 0x3efd0c4b, 0x3f00b26a, 0x0294f079, 0x980e1bf4, 0x4bb20c3a, 0x393efd0c, 0xb0b400b3, 0x0c3ab209, - 0x7e8db201, 0xb300a63f, 0x3f5d00a0, 0xbd3fb279, 0x0299c724, 0xb0019990, 0xf5980a91, 0x0054b354, - 0x09b0b439, 0x0c0022bc, 0x0002bc03, 0xb80304b6, 0x00014001, 0xb21031bc, 0xb7987e1a, 0x0030bc00, - 0x014309b8, 0xb5952000, 0xf0b45302, 0x540fb50a, 0x043e81a0, 0x229000b3, 0x18ff9001, 0xbe1424b3, - 0x00b6313e, 0x793f8ebf, 0x18027f58, 0xee98077d, 0x0d3a9803, 0xf00299c7, 0xffcc00f3, 0x1f96cb70, - 0xe6cb4bb2, 0xcb010cd8, 0xf6ebf0d6, 0xe57e01e0, 0x3a9800a2, 0xb24bb20c, 0xb6757e6c, 0xb3a5b200, - 0x02b400ad, 0x98014490, 0x4ba6033b, 0xfeeb08f5, 0xbbbc94bd, 0xb289a0b0, 0xb7b47e8a, 0xb3a5b200, - 0x029400ad, 0x84bd37b2, 0xbc547f98, 0x98bc9088, 0x0394b690, 0x014099b8, 0x9039bc00, 0xb30b91b0, - 0x025300f9, 0xb4033c98, 0xb43d0fa0, 0xccbc24bd, 0x7e44bdc0, 0xb400b78f, 0x623e0f60, 0x3a9800b4, - 0xb02bb20d, 0xf57e0c41, 0xa93300a2, 0x9800b500, 0x4cfe0c3a, 0x902bb201, 0x5e7e38cc, 0xadb300b6, - 0xb4020c00, 0x90b40be0, 0x03ef980e, 0xa6d899c7, 0x8e1bf59f, 0x0d3a9800, 0x010c2bb2, 0x00a2ed7e, - 0xb2014cfe, 0x902bb23a, 0x937e30cc, 0xa4b300a5, 0x3a981306, 0x0c2bb20c, 0xb6757efd, 0xb45f3e00, - 0x00adb300, 0x907401cb, 0x0093f01c, 0xbc9099bc, 0x017f0069, 0xffff19e4, 0x60091bf4, 0xb45f3e02, - 0x0c3a9800, 0xe4014cfe, 0x90ffff1b, 0x5e7e34cc, 0xadb300b6, 0x34019800, 0x90343af0, 0xf4f92636, - 0x0260100d, 0xffff1be4, 0x3e0c3a98, 0x9800b454, 0x2bb20c3a, 0x757efd0c, 0xadb300b6, 0x90017000, - 0x3a980122, 0xf52aa603, 0xb2ff3708, 0x3d6eb264, 0xbdd43db4, 0x3ec4bdf4, 0x7f00b496, 0x009473e9, - 0x3e010d0a, 0x3300b490, 0x0b0600d0, 0x01cc9001, 0x9001ff90, 0xfaa602ee, 0xb3e308f4, 0xb50b00c4, - 0xd23e547c, 0xb93300b5, 0x9800a600, 0x96b00139, 0x300cf402, 0x6db20309, 0xbd5479b5, 0x3ef4bde4, - 0x7f00b4d5, 0x009073d9, 0xe9697c0a, 0x9001ee90, 0xdd9001ff, 0x03399802, 0x08f4f9a6, 0xb54c3ee9, - 0x0194bd00, 0x5479b5f1, 0x1bb224bd, 0x00b5263e, 0x09e4407f, 0x0bf4ffff, 0xa6f10f26, 0x0b1bf4bf, - 0xffff0be4, 0x00b51e3e, 0xe40c3a98, 0x7effff0c, 0xb300b675, 0x00b900ad, 0xffff0be4, 0x229019b2, - 0x02449001, 0x399891b2, 0xf429a603, 0xf109c508, 0x0bf5b9a6, 0x3a9800a0, 0x0a3c980c, 0x00b6757e, - 0x8c00adb3, 0x0a31b500, 0x00b5d23e, 0x94bd6f7f, 0xb501c192, 0xf3f05179, 0xb504bd00, 0x8a3e527f, - 0x4b7f00b5, 0x98014c58, 0x00900c3a, 0x00b3f001, 0x9000c3f0, 0x757e0244, 0xa4b300b6, 0xe0b45200, - 0x01e9980b, 0xb5709990, 0x01a601e9, 0x7cd608f4, 0x3a980860, 0xe4f00c0c, 0x7effff0b, 0xb300b675, - 0xfe2d00a4, 0x0be4014c, 0x3ab2ffff, 0x7e40cc90, 0xb300a578, 0x341900a4, 0x7f984690, 0xff94f051, - 0xb5f0f9bc, 0xd23e517f, 0x030a00b5, 0xdd3ea5b2, 0x889000b5, 0x18779001, 0x90148db3, 0x0149fefd, - 0xbf3c9990, 0xb7487e9a, 0xb5f33e00, 0x3e030500, 0xbd00b5f5, 0xb20bb204, 0xa60b7e3a, 0x0050b300, - 0x0c3a981a, 0xc77e04bd, 0x3a9800b6, 0x0c30b50d, 0x00b7487e, 0xfe0d30b5, 0x99900149, 0xd99fbf50, - 0x000005dc, 0x5ab299bf, 0x0bf4f9a6, 0xb6373e11, 0x3e010500, 0x7e00b5f3, 0xfb003a31, 0x02f93085, - 0xe77ea0b2, 0x0a9800a5, 0xb6c77e0c, 0x0d0a9800, 0x00b7487e, 0x487e0ab2, 0xa4bd00b7, 0xa9bf01fb, - 0x020aafb2, 0x18f4b9a6, 0x01b9900d, 0xbd98f9bc, 0xf8c9a0a4, 0xb2a9bf00, 0xa6020aaf, 0x0b18f4b9, - 0xbd01b990, 0x99fcbca4, 0xb9bf00f8, 0xcab2afb2, 0x08f4c9a6, 0xf8f10a07, 0x02fbb500, 0xfcb5fca0, - 0xbf00f801, 0x02af98a9, 0xa090b9bc, 0xa6fbbfa9, 0x0808f49b, 0xa0029bbb, 0x01a998a9, 0xa9a6aabf, - 0x0a051bf4, 0xb300f8f1, 0x7e0800a0, 0xf800b748, 0xf830f400, 0x0005dcdf, 0xbf32f900, 0x0149feff, - 0xb2149990, 0xb29fa0a0, 0x00a0b3b3, 0xa6fd0242, 0x3a0cf4a2, 0xfe01ab90, 0xb4b60141, 0x10119002, - 0xb47e1ab2, 0xa4b300b7, 0x19bf2700, 0x2cb21db2, 0x90a0e4bd, 0xe990dfbf, 0xbc9eb201, 0x90a699fc, - 0xbff408f4, 0x3e3da0dd, 0x0a00b72d, 0x0149fe02, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, - 0x3a317e07, 0x0835fb00, 0x44da00f8, 0x7e000029, 0x300041c7, 0xacf000a6, 0x01a6f00b, 0xf801aab9, - 0x2944da00, 0x427e0000, 0xa6300041, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x002944da, 0x42d77e00, - 0x00a63000, 0xf00bacf0, 0xaab901a6, 0xf000f801, 0x947effb4, 0x00f8000b, 0x000b7e7e, 0x02f900f8, - 0xa43da0b2, 0x00384c7e, 0xf000a6b0, 0x0aa00b9c, 0x01fb9ab2, 0xa0b202f9, 0x2a7ea43d, 0xa6b00038, - 0x0b9cf000, 0x9ab20aa0, 0x30f401fb, 0x05dcdfe4, 0x82f90000, 0x49feffbf, 0x0145fe01, 0xfe3c9990, - 0x9fa00147, 0x90245590, 0x1cd93477, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x7eff0d2c, 0x330000c1, - 0xb4eb00a4, 0x393f0c30, 0xe20c9433, 0x33043118, 0x330f0010, 0x00b00119, 0x703e043d, 0x3f9800b9, - 0x142cd902, 0x31980000, 0x0a345804, 0x9f3f5fa0, 0x90033998, 0x59b51836, 0xa0ff0901, 0x00f43379, - 0x32f77e18, 0x33a03200, 0x012900ad, 0x2cdf0109, 0x20000014, 0xf01272f9, 0x14bd0043, 0x00b8b03e, - 0xb10241bc, 0xf4010006, 0x0040060d, 0x0b947e01, 0x1424d900, 0x9abf0000, 0xffff2ce4, 0x0db26bb2, - 0x001300de, 0xaf117e00, 0xb37aa000, 0x00d400ad, 0x5c985bbf, 0x041d9001, 0x207c0eb2, 0x1010bc20, - 0x001300da, 0x21367e00, 0x33a03200, 0x00c500ad, 0x004cb4bd, 0x1300da01, 0x14a60000, 0x3ea408f4, - 0x9800b95f, 0x2cd9023f, 0x98000014, 0x32580434, 0x3f5fa00a, 0x0339989f, 0xb5183890, 0xff090159, - 0xf43379a0, 0xf77e1600, 0xa0320032, 0x8400ad33, 0x142cdf00, 0xf1200000, 0xffff26e4, 0x503e24bd, - 0x62bc00b9, 0x0016b112, 0x060df401, 0x7e010041, 0xbf000b94, 0x015c985b, 0xb2042d90, 0x1300da1e, - 0xd07e0000, 0x4ce40020, 0x21bcffff, 0xb2a03220, 0xde1db28b, 0x00001300, 0x3340417c, 0xd93500a4, - 0x00001424, 0x3b7e9abf, 0x7aa000ac, 0x1300a4b3, 0x004cb4bd, 0x1300da01, 0x26a60000, 0xbfa608f4, - 0x015c985b, 0xd4bd7ab2, 0x367e040e, 0xa0320021, 0xb22db034, 0x0f817e3a, 0x000d3300, 0x0130fe71, - 0x30020f3a, 0x331838f1, 0xfe040903, 0x9130014a, 0x3b313039, 0xaa90b4bd, 0x0f717e38, 0xb7ea3e00, - 0xd902f900, 0x00002930, 0x9abfa0b2, 0xde7e640b, 0x10090000, 0x6100a433, 0x02a60089, 0xf1009fcf, - 0xf61000f5, 0x008a009f, 0x004b02a6, 0x4dc4bd10, 0xe4bd2710, 0x00198b7e, 0x1500a433, 0x002930d9, - 0x7e9abf00, 0x0900009b, 0xba153e04, 0x4b0ab200, 0xfc7e03e8, 0x00890016, 0xaab802a4, 0xb6000200, - 0xaa920aa5, 0x009af601, 0xb801114f, 0x00020099, 0x3d009ff6, 0xfb9a3294, 0x00000001, 0x00000000, + 0xfa95075d, 0x10f99508, 0xa132f032, 0xf9339232, 0x3000d515, 0x0cf415f6, 0x05f93346, 0xf63005fc, + 0x1c0cf405, 0x8701f933, 0x301f0a00, 0x08f501f6, 0xf630073a, 0x250cf503, 0x8e283e07, 0x10f93300, + 0xf630041b, 0x0e0cf410, 0xf50df630, 0x3e070f08, 0x33009156, 0x070711fd, 0x0091603e, 0x431df933, + 0x1df63006, 0x33250cf4, 0x03fb18f9, 0xf418f630, 0xfd330c0c, 0x3e06e817, 0x33009409, 0x01011af9, + 0xda1cfd33, 0x94c63e06, 0x21f93300, 0xf6300263, 0x0c0cf421, 0xc61efd33, 0x8ece3e06, 0x24f93300, + 0xfd33063a, 0x3e06b825, 0xdf00949a, 0x0000299c, 0x2614f918, 0x0d18f4a9, 0xbcffa9c4, 0x6f3e98f9, + 0xbda00093, 0x0094313e, 0x1d33080a, 0x7e069e00, 0x330063f7, 0x490a0300, 0xa9fdff00, 0x3e4aa004, + 0x0a009431, 0x09163003, 0x06800cf5, 0x00299cd9, 0x0e99bf00, 0xbc080a01, 0x99e7f4e1, 0x9ffd0133, + 0x670bf504, 0x02103306, 0x0410330e, 0x3eea3210, 0xb2008e85, 0x8e7b3eea, 0xfea4bd00, 0xbb90014b, + 0x63b47e2c, 0x8a847e00, 0x1fad3300, 0x49fe063f, 0x2c999001, 0xe9959ebf, 0x0190b31f, 0x3ed4bd0a, + 0xdd008ea8, 0xff000000, 0x3380e9c4, 0xbd0a0094, 0x8ebf3ef4, 0xb0010f00, 0x1ff400e6, 0x95ff0f05, + 0xd9ff08e9, 0x90f9bc95, 0xc83e49a0, 0x9b320094, 0x5db24cb2, 0x0077ca7e, 0x0094c83e, 0x5507a033, + 0xf407a630, 0x9cd9120c, 0x30000029, 0x0df402a6, 0x8f253e2b, 0x0ca63000, 0xd9120cf4, 0x0000299c, + 0xf409a630, 0x483e5718, 0xa033008f, 0x030a610d, 0xb80e1d33, 0x8f7b3e05, 0x01999800, 0x000000df, + 0x8f613e04, 0x01999800, 0x000000df, 0x8f613e08, 0x299cd900, 0x99980000, 0x00008f02, 0x049ffd02, + 0x00c61bf5, 0x0090463e, 0x8f029998, 0xfd040000, 0x1bf5049f, 0x463e00c4, 0x99980090, 0x00008f02, + 0x049ffd01, 0x3e2f1bf4, 0xd9009046, 0x0000299c, 0x4000008f, 0x3e029998, 0xd9008f88, 0x0000299c, + 0xdf029998, 0x00800000, 0xf5049ffd, 0x3e00a91b, 0x33009046, 0x30730710, 0x0cf40716, 0x0210331a, + 0x0216304b, 0x33540cf4, 0x33270010, 0x0486011d, 0x008fd83e, 0xf40c1630, 0x16300d0c, 0x6518f409, + 0x0090163e, 0xf40e1630, 0x313e6d0d, 0x4ab20094, 0x00789f7e, 0x0094c83e, 0x2b321a32, 0x5db24cb2, + 0x007cca7e, 0x0094c83e, 0x2b321a32, 0x5db24cb2, 0x007c3b7e, 0x0094c83e, 0x2b321a32, 0x467e4cb2, + 0xc83e007e, 0x2b320094, 0x5db24cb2, 0xa27e070a, 0xc83e007b, 0x080a0094, 0x4cb22b32, 0x037e5db2, + 0x1a32007b, 0x3cb22b32, 0x5eb24db2, 0x007ed37e, 0x0094c83e, 0x2b321a32, 0x4db23cb2, 0xa77e5eb2, + 0xc83e0078, 0x080a0094, 0x0094c83e, 0x9d33040a, 0xd9047a00, 0x0000299c, 0x0a029998, 0x0094f108, + 0x670bf540, 0x0149fe04, 0x900142fe, 0x22902c99, 0xa09da018, 0x0499922d, 0x99929da0, 0x929da004, + 0x9da00499, 0xa0049992, 0x0119339d, 0x16300085, 0x0e08f401, 0x1d33030a, 0x3e043202, 0xfe009122, + 0x40fe0141, 0x2c119001, 0xb2280090, 0x7e0bb21a, 0xbf007560, 0xfe00bf19, 0x42fe0143, 0x0794f001, + 0x90243390, 0x3ab22022, 0xb20141fe, 0x1c11902b, 0xb20704f0, 0x0404b61c, 0x7e0509fd, 0xbf006a5c, + 0xbf3fbf29, 0x0141fe1e, 0xf00894b6, 0x94f1fff4, 0xf4b6ffff, 0x18e4b610, 0xfd181190, 0x1ab20509, + 0xfd050ffd, 0x497e050e, 0x483e006a, 0x2ab20091, 0x006a397e, 0x20bf2ab2, 0x006a297e, 0x4e3e29bf, + 0x41fe0091, 0x18119001, 0x167e1ab2, 0x1ab2006a, 0x037e10bf, 0x19bf006a, 0x04f11ab2, 0x94b6ffff, + 0x0590ff10, 0x0069f07e, 0x94f119bf, 0x40a0ffff, 0x313e59a0, 0xfab20094, 0x0095f47e, 0x0094c83e, + 0x0d00a033, 0x5c01ad33, 0x91ae3e03, 0x33b0bf00, 0x330c0190, 0x3e2f0294, 0xfe00919e, 0x010a0141, + 0xb2181190, 0x94ef7e1b, 0x1fad3300, 0x1fbf033f, 0x09fffe09, 0x049fff95, 0xa23e10a0, 0x04f10091, + 0x2a3203ff, 0x0a7e0bb2, 0xc83e0095, 0x9a320094, 0x0094ef7e, 0x0094c83e, 0x237efab2, 0xc83e0095, + 0x9cd30094, 0xbf000029, 0x0000df39, 0x080a2000, 0xf5049ffd, 0x0a02f50b, 0x001d3303, 0x40fe02ef, + 0x014cfe01, 0x90280090, 0x0bb22ccc, 0x900142fe, 0x2ab22422, 0x0073477e, 0x9670097f, 0x0b9cf003, + 0x7e079194, 0x1800010e, 0x087e5830, 0x00330001, 0x1fb20a00, 0x00924d3e, 0xa4732a7f, 0x19b20a00, + 0x00924b3e, 0x734019c5, 0x731403a0, 0x731804a0, 0xe51c02a4, 0x3e01009f, 0xe500924d, 0x3e02009f, + 0xe500924d, 0x3e03009f, 0xb200924d, 0x0149fe9f, 0x7f2c9990, 0x04997399, 0x96700088, 0x1a0cf404, + 0x48019073, 0xf4019670, 0x90733608, 0x9d734c02, 0x3e00e303, 0x730092cf, 0x009b0799, 0xf4079670, + 0x9073100c, 0x9d736905, 0x3e00cb06, 0x73009304, 0x009c0899, 0xbd099d73, 0x93393e00, 0x07ff8900, + 0x04f9fdfe, 0x0093513e, 0xffc7ff49, 0x95f194f9, 0xc03e2000, 0xff490092, 0x94f9ffc7, 0x180095f1, + 0xfe3fff8f, 0xe5049ffd, 0x3e40009f, 0x49009351, 0xf9ffc7ff, 0x0095f194, 0x92c03e10, 0xc7ff4900, + 0xf194f9ff, 0x3e080095, 0x490092f5, 0xf9ffc7ff, 0x0095f194, 0x3fff8f10, 0x049ffdfe, 0x80009fe5, + 0x0093513e, 0xffc7ff49, 0x95f194f9, 0x1c3e0800, 0xff490093, 0x94f9ffc7, 0x100095f1, 0xfe3fff8f, + 0xe5049ffd, 0x3ec0009f, 0x49009351, 0xf9ffc7ff, 0x0095f194, 0x93433e08, 0xc7ff4900, 0xf194f9ff, + 0x8f100095, 0xfdfe3fff, 0x008f049f, 0x9fff0100, 0x299cd9f5, 0x99180000, 0x00903350, 0x0000890f, + 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x16a63000, 0x01480cf5, 0xd9ffafc4, + 0x000004d0, 0xd9e89fbc, 0x0000299c, 0xefc7080a, 0x989fbc3b, 0xbb96efc7, 0x94f0059f, 0x2b0bf501, + 0xff29c401, 0x010defe7, 0x0a029b54, 0xf5bf6604, 0xf0011918, 0xb9e400f3, 0xf9bcffff, 0x04c6b0c2, + 0x0c090df4, 0x93cb3e04, 0xe44da000, 0xc4ffffba, 0xebe703e9, 0x94330142, 0xbabc1200, 0x29bcd9b0, + 0x4ab20000, 0x0093f43e, 0x000644d9, 0xbc99bf00, 0x4ab2b0ba, 0x7eb09bbc, 0x3e000b7e, 0x32009431, + 0x9acb7e9b, 0x94c83e00, 0x00a03300, 0x33080a0f, 0x00b1011d, 0x0094c83e, 0x900140fe, 0x0ab22400, + 0x0072fb7e, 0xa54f093f, 0x00943300, 0xa05a0f06, 0x3e1f0a4f, 0xd90094c8, 0x0000299c, 0x33159918, + 0x00870099, 0x3802a033, 0xf402a630, 0xa0330f0c, 0xa4331800, 0x703e6e01, 0xa0330094, 0xa4332c03, + 0x903e6204, 0x3ab20094, 0x009d827e, 0x0094c83e, 0xcbb2bab2, 0x009ffc7e, 0x0094c83e, 0x0b7e2a32, + 0xc83e009d, 0x2a320094, 0x00a2127e, 0x0094c83e, 0xa67e2a32, 0xc83e00a1, 0x9cd90094, 0x18000029, + 0x90331599, 0xfbc72400, 0xb22c326c, 0xf05eb24d, 0xac7e0fa4, 0xc83e009e, 0x020a0094, 0x0094c83e, + 0xc83e030a, 0x090a0094, 0x900149fe, 0x9fbf3099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, + 0xf01c55fb, 0xa4b6ffa4, 0x0acaa002, 0x3200f81f, 0x30040aaf, 0x0cf402f6, 0xfff4f012, 0x002a5cd9, + 0xf89fbc00, 0xbfa01f0a, 0xaf3200f8, 0xf630040a, 0x100cf402, 0xd9fff4f0, 0x00002a5c, 0x9bbc1f0a, + 0xf900f8f9, 0x10af9512, 0xae95b1b2, 0x299cd008, 0xff090000, 0x1bf4e926, 0x4909183d, 0x1bf5f926, + 0x091800b2, 0x331c0a4a, 0x00ab0199, 0xf5019630, 0x0a00a108, 0x029d3306, 0x0998009d, 0x0af43d13, + 0x18b9a01f, 0x0f354909, 0x0199104a, 0x3e490935, 0x180095f2, 0x0a0a4a09, 0x7a009433, 0x002a5cd9, + 0xf099bf00, 0x99c7fff4, 0x0694b6e8, 0xb0f0f9bc, 0x0cf43ff6, 0x33030a5e, 0x905b0ce4, 0x96b104f9, + 0x0cf40040, 0x02f9944e, 0x002a68df, 0x909fbc00, 0x9a589f7f, 0x73080d01, 0x981b02f4, 0x290d0409, + 0x338094f0, 0x7e0f0090, 0x0900754b, 0x35d43d01, 0x9cdf5009, 0x18000029, 0xd9c449fe, 0x13f9b5ff, + 0xf9350209, 0xffe4f04a, 0x1ea01c0a, 0x0095f23e, 0x11fb040a, 0xadb222f9, 0xa0c7b2b2, 0xb0bbbfe8, + 0x0cf53f06, 0xbcc400cc, 0xffaec4ff, 0x0d0fe4b3, 0xc6b0050a, 0xbb0cf53f, 0x2a5cd900, 0x99bf0000, + 0xc7ff9fc4, 0xf194e899, 0x0694b606, 0x2c0ee0b3, 0x440fe0b3, 0xedb31f0a, 0x7c009a0d, 0x96719009, + 0x0cf500ff, 0x9fe4008c, 0x68d9ffff, 0xbc00002a, 0x2fa0f89f, 0x00966e3e, 0x7190017c, 0xf400ff96, + 0x9fe46f0c, 0x68d9ffff, 0xbc00002a, 0x1f0af99b, 0x0096d03e, 0x0af0c9bc, 0xf0d9c705, 0x9002fb94, + 0x9c940199, 0xe0cbbc02, 0x1000e6b1, 0xbc440cf4, 0x030a9001, 0xbc0294b6, 0xf6b1f0c9, 0x0cf41000, + 0xf49ba632, 0x9ea60808, 0xa62008f4, 0x080df4b9, 0x08f4bfa6, 0x2a68df16, 0x9fbc0000, 0xb0bfbca0, + 0x000b7e7e, 0x00966e3e, 0xd03e040a, 0x030a0096, 0xc9b221fb, 0x0fffa6b1, 0xbc2b0cf4, 0x96b1909a, + 0x0cf41000, 0x2a68de21, 0xaebc0000, 0x00d03390, 0x3e9ab20a, 0xb20096fb, 0x7e9bb2ba, 0x0a000b7e, + 0x0a00f81f, 0xf400f804, 0xdcdfe430, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0a0b220, 0xf0d1b29f, + 0xedb2ffb4, 0xb40aa0b4, 0x09c40be0, 0xf49ba607, 0x0fc7751b, 0x0149fe2f, 0xa0089990, 0x029eb59d, + 0xbc019ab5, 0x94bdb89f, 0x90014ffe, 0xf9a014ff, 0xb501fcb5, 0x09c702f1, 0xbcbabf23, 0x0fc7c8f9, + 0x8a09c785, 0xf0e09f3c, 0x0dc71ff4, 0x05cfbb91, 0xb990d93c, 0xd4f000ee, 0x1fe4f01f, 0xbc0099b9, + 0x94f0e0ef, 0xbcff0f1f, 0xf9bc909d, 0x05febb95, 0xfd049dbb, 0x99b904fc, 0x04fdbb00, 0xfd049afd, + 0xb9a0059f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41c15fb, + 0xdcd9f430, 0xf9000005, 0xb299bf82, 0x014ffed1, 0xa02cff90, 0x92dd3ff9, 0x1f0003ff, 0xf0351709, + 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000530db, 0x7e240c00, 0x09000b7e, 0x200a3209, + 0x98823e19, 0x30030a00, 0x0cf409d6, 0x0147fe78, 0xb2ffc4c4, 0x90043df8, 0x793e2477, 0x09c40098, + 0x947bb2ff, 0x040c0292, 0x3da026bc, 0x96d27ed4, 0x1fa43300, 0xc47fbf6b, 0x94a607f9, 0xc75e18f4, + 0x991223f9, 0x01963001, 0xc7520cf4, 0xe9c42ffe, 0xc8893cff, 0xc78afdc7, 0xd93c85f9, 0xf49c2690, + 0xe0333b0c, 0xf9c73803, 0x909d3c91, 0x0cf49c26, 0x9052bc2c, 0xa0010010, 0x26193f9f, 0xa108f409, + 0x49fe1f0a, 0x2c999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xb23e230b, 0x0d0a0098, 0x0fc439bf, + 0x0000deff, 0x9efdff00, 0x05f9fd04, 0x823e3fa0, 0x317e0098, 0x85fb003a, 0xa830f40c, 0x0005dcd9, + 0xbf82f900, 0xf830f499, 0x4ffea7b2, 0x80ff9001, 0xaabff9a0, 0xb00eb1b0, 0xa6c70dc1, 0x01691268, + 0xf5039630, 0xc7013b0c, 0x96306ca9, 0x310cf50a, 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0xf9a699bf, 0x7e070bf4, 0xf4003a31, + 0x85fb0830, 0xf430f458, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xfe109990, 0x9fa00141, 0x4a0c1190, + 0x040b00b8, 0x307e1cb2, 0xa433008c, 0x40fe2b1f, 0x00b44a01, 0x0b080090, 0x7e0cb204, 0x33008c30, + 0xbf161fa4, 0xa60fbf19, 0x0b9cf09f, 0x320196f0, 0x9a973e9a, 0xfea43d00, 0x99900149, 0xd99fbf10, + 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0xa9980c15, 0x90afb204, 0x010b59ac, 0x4a2095f0, + 0xf9b50090, 0x8c307e04, 0xf400f800, 0xdcd99030, 0xf9000005, 0xfe99bf52, 0xff90014f, 0xa0030e84, + 0x00ad33f9, 0x9cd90105, 0x18000029, 0x99335999, 0x3200f600, 0x014cfeba, 0xcc90b4bd, 0x94e37e20, + 0x33ae3200, 0x00e31fad, 0x4a0144fe, 0x449000b8, 0xb2040b1c, 0x8c307e4c, 0x33ae3200, 0x00cb1fad, + 0x4a0140fe, 0x009000b4, 0xb2040b18, 0x8c307e0c, 0x33ae3200, 0x00b31fad, 0x4abf09bf, 0x0bf5a9a6, + 0xaa9000a6, 0x0140febc, 0x0090010b, 0x7e0cb227, 0x32008c30, 0x1fad33ae, 0x093f0091, 0xb20142fe, + 0x28229043, 0x45ff94f0, 0x91541000, 0x9baa3e02, 0xe43abf00, 0xbcffff1b, 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0x013e04bd, 0x2a9800ac, 0xb003bc0c, 0x00904cb2, 0xb6767e01, + 0x0b90b400, 0x08f409a6, 0x032f98ec, 0xb59039bc, 0x9fa60929, 0xbd0808f4, 0x0929b594, 0x49fea4bd, + 0x60999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x30f4003a, 0x3885fb08, 0xd9cc30f4, + 0x000005dc, 0x99bf82f9, 0xfef830f4, 0xff90014f, 0xb0f9a05c, 0xc8b20be1, 0xa3b2d6b2, 0x8400b9b3, + 0x00e9b302, 0xaf18027f, 0x0141fe2c, 0x119094bd, 0x0019a054, 0x00f93303, 0xc43d026d, 0x407e1db2, + 0xa0b200a6, 0x5e00adb3, 0xbc17bf02, 0x7998f068, 0xf59fa601, 0x98024d08, 0x94b30479, 0x05000a01, + 0x00aee23e, 0x3e0069b3, 0x027f9802, 0xf9a6f009, 0x022a0bf5, 0xea7e3ab2, 0xa2b200a5, 0x1e00a9b3, + 0x0c3c9802, 0x40fe7bb2, 0x34009001, 0x287e0ab2, 0x0ab200a6, 0xcc0570b5, 0xc17e708b, 0xa0b200a6, + 0xe900adb3, 0x0d00b401, 0x01a6f001, 0x01ce0bf5, 0x01d00cf5, 0x804cb43d, 0x7e2ab200, 0xbf00b790, + 0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894, + 0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999, + 0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff, + 0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c, + 0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c, + 0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0, + 0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00, + 0x90335b90, 0x3ab21100, 0x00a9d97e, 0xadb3a0b2, 0xb400db00, 0x40b40d00, 0x014ffe11, 0xb250ff90, + 0x070d942e, 0x4101f1b0, 0x3ab20080, 0x4cb2010b, 0x7e0011b0, 0xb200a5e4, 0xb22cb20b, 0x014dfe3a, + 0x7e4cdd90, 0xb400a4be, 0xa0b214e0, 0x3ab21cb2, 0x0db2b4bd, 0x00a5e67e, 0x91000db3, 0x13b0b400, + 0x90014afe, 0x5d7e34aa, 0x3a9800a9, 0x0db0b40c, 0x90014cfe, 0x5f7e48cc, 0xa0b200b6, 0x6d00a4b3, + 0x011290b4, 0xf491a6f0, 0x4e98321b, 0x70efcd01, 0x0600f4b3, 0x2918700f, 0xff94f006, 0xbb909ebc, + 0x49b5029f, 0xae993e01, 0xb20bb200, 0x7e2cb23a, 0xb200a43f, 0x00a4b3a0, 0x0265bb34, 0x90014afe, + 0xaa7e34aa, 0x60b300a6, 0x90b42000, 0x8085bc0b, 0xb09095bc, 0xe53e0b91, 0x020000ac, 0x00aec93e, + 0xc93e0300, 0x00b400ae, 0xb23ab20c, 0xa60c7e2b, 0xb594bd00, 0xe23e0579, 0x030000ae, 0x00aee23e, + 0x49fe0200, 0x5c999001, 0xdcd99fbf, 0xbf000005, 0xa60ab299, 0x170bf4f9, 0x00af083e, 0x33062918, + 0xfe4f009d, 0x00aec03e, 0x003a317e, 0xfb0830f4, 0x30f43485, 0x05dcdfdc, 0x82f90000, 0x30f4ffbf, + 0x0149fef8, 0xa04c9990, 0x0bb1b09f, 0xd4b2c2b2, 0xa5b2e6b2, 0x1700b9b3, 0x00e9b301, 0x94bd0112, + 0x3d0141fe, 0x481190c4, 0x1db219a0, 0x00a6407e, 0xadb3a0b2, 0xbf00fb00, 0xf042bc19, 0xa6019998, + 0xea08f59f, 0x005ab200, 0xa5ea7e03, 0xb3a3b200, 0x00de00a9, 0x5c981bbf, 0x0140fe0c, 0xb2300090, + 0xa6287e0a, 0xcc0ab200, 0xc17e702b, 0xa8b200a6, 0xad00adb3, 0x7021cd00, 0x420147fe, 0x77900080, + 0xb0383e44, 0x0c00b400, 0x79a094bd, 0x09a6f009, 0x00091bf4, 0xb03f3e02, 0xa6f00900, 0x090df409, + 0x3f3e0300, 0xc0b400b0, 0x0704b60b, 0x0db2e4bd, 0xb4bd5ab2, 0xb00021b0, 0xe47e0171, 0x5abf00a5, + 0x2cb20bb2, 0x797e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xe67e0db2, 0x04b300a5, 0x3ab24500, + 0x117eb4bd, 0xa0b200a4, 0x3700a4b3, 0x01bb7000, 0xf404a602, 0x40b2050d, 0xb2101b90, 0xb03bbc6a, + 0x997e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xaa7e6060, 0x14bd00a6, 0x6d004db3, 0xb280b2ff, + 0x7e3bb25a, 0x3e00a60c, 0x0000b04d, 0x0149fe02, 0xbf4c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60ab2, + 0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005dcd9, 0xbf32f900, 0x014ffe99, 0xb214ff90, + 0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0x9f7e0ab2, 0x09bf00b7, 0x4c0090b3, + 0x4800a4b3, 0x09bf91a0, 0xbf0192b5, 0x1000490f, 0xbf04f9b5, 0xb520090f, 0x09bf05f9, 0xbf0693b5, + 0x3501090f, 0x09bf1cf9, 0xbf2c9a35, 0xb5f0090f, 0x0fbf0af9, 0xb540f990, 0x0fbf0ef9, 0xb5c0f990, + 0x0abf0ff9, 0x00b0ea3e, 0x49fea4bd, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, + 0x35fb003a, 0xd030f408, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2509990, 0x059fa0a3, 0x00a9b302, + 0xb63004fb, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5ea7e, 0x3abfa0b2, 0x804cb4bd, 0x7e0db200, + 0xb200b779, 0x00adb3a5, 0x093f04b1, 0xa24a9d33, 0x01091804, 0x9a469d33, 0x02091804, 0x92469d33, + 0x03091804, 0x8a539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, 0xf0ff94f0, 0x94b6fff4, + 0x10f4b608, 0xb6059efd, 0xf9fd18d4, 0x05dffd05, 0x045e0bf5, 0xd6b00505, 0x5d0cf503, 0x013db504, + 0x0e01d4b3, 0xb5500049, 0xd83e0239, 0x0d1800b1, 0x09091808, 0x180a0f18, 0xd4f00b0e, 0xff94f0ff, + 0xb6fff4f0, 0xf4b60894, 0x059dfd10, 0xfd18e4b6, 0xeffd05f9, 0x023eb505, 0x0bb23ab2, 0x00a60c7e, + 0x09023a98, 0xf4a9a6ff, 0x04bd091b, 0x00b5ee3e, 0x9007a5b6, 0x3ab5303b, 0xb6d27e03, 0xb3a5b200, + 0x03f500ad, 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb79f7e03, 0xb3a5b200, 0x03d900ad, + 0xfe0147fe, 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3483e, 0x8ea0e4bd, 0x0f0044b3, + 0xbd0c3a98, 0x3efe0cb4, 0xb200b26b, 0xb24bb23a, 0xa5797e7c, 0xb3a5b200, 0x039d00ad, 0x94f0793f, + 0x120bf401, 0xb20c3a98, 0x7eff0c4b, 0x3e00b676, 0xb200b345, 0xa3307e7a, 0x00a0b300, 0x0c3a980f, + 0xfd0c4bb2, 0x00b26b3e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, 0xb400b33a, 0x3ab209b0, + 0x8db2010c, 0x00a6407e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, 0x980a91b0, 0x54b354f5, + 0xb0b43900, 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, 0x997e1ab2, 0x30bc00b7, + 0x4309b800, 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b305, 0xff900122, 0x1424b318, + 0xb6323ebe, 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, 0xcc00f3f0, 0x96cb70ff, + 0xcb4bb21f, 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2e6, 0x4bb20c3a, 0x767e6cb2, 0xa5b200b6, + 0xb400adb3, 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, 0xb57e8ab2, 0xa5b200b7, + 0x9400adb3, 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, 0x39bc0001, 0x0b91b090, + 0x5300f9b3, 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b7907e, 0x3e0f60b4, 0x9800b463, + 0x2bb20d3a, 0x7e0c41b0, 0x3300a2f6, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, 0x7e38cc90, 0xb300b65f, + 0x020c00ad, 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, 0x0c2bb20d, 0xa2ee7e01, + 0x014cfe00, 0x2bb23ab2, 0x7e30cc90, 0xb300a594, 0x981306a4, 0x2bb20c3a, 0x767efd0c, 0x603e00b6, + 0xadb300b4, 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, 0x091bf4ff, 0x603e0260, + 0x3a9800b4, 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b65f, 0x019800ad, 0x343af034, 0xf9263690, + 0x60100df4, 0xff1be402, 0x0c3a98ff, 0x00b4553e, 0xb20c3a98, 0x7efd0c2b, 0xb300b676, 0x017000ad, + 0x98012290, 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, 0x00b4973e, 0x9473e97f, + 0x010d0a00, 0x00b4913e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, 0xe308f4fa, 0x0b00c4b3, + 0x3e547cb5, 0x3300b5d3, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, 0x5479b56d, 0xf4bde4bd, + 0x00b4d63e, 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, 0xf4f9a603, 0x4d3ee908, + 0x94bd00b5, 0x79b5f101, 0xb224bd54, 0xb5273e1b, 0xe4407f00, 0xf4ffff09, 0xf10f260b, 0x1bf4bfa6, + 0xff0be40b, 0xb51f3eff, 0x0c3a9800, 0xffff0ce4, 0x00b6767e, 0xb900adb3, 0xff0be400, 0x9019b2ff, + 0x44900122, 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, 0x3c980c3a, 0xb6767e0a, + 0x00adb300, 0x31b5008c, 0xb5d33e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, 0x04bd00f3, 0x3e527fb5, + 0x7f00b58b, 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, 0xb300b676, 0xb45200a4, + 0xe9980be0, 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, 0xffff0be4, 0x00b6767e, + 0x2d00a4b3, 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5797e, 0x1900a4b3, 0x98469034, 0x94f0517f, + 0xf0f9bcff, 0x3e517fb5, 0x0a00b5d3, 0x3ea5b203, 0x9000b5de, 0x77900188, 0x148db318, 0x49fefd90, + 0x3c999001, 0x497e9abf, 0xf43e00b7, 0x030500b5, 0x00b5f63e, 0x0bb204bd, 0x0c7e3ab2, 0x50b300a6, + 0x3a981a00, 0x7e04bd0c, 0x9800b6c8, 0x30b50d3a, 0xb7497e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099, + 0x0005dcd9, 0xb299bf00, 0xf4f9a65a, 0x383e110b, 0x010500b6, 0x00b5f43e, 0x003a317e, 0xf93085fb, + 0x7ea0b202, 0x9800a5e8, 0xc87e0c0a, 0x0a9800b6, 0xb7497e0d, 0x7e0ab200, 0xbd00b749, 0xbf01fba4, + 0x0aafb2a9, 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6, + 0x01b9900b, 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002, + 0x00f801fc, 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01, + 0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7497e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf, + 0x14999001, 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4, + 0x7e1ab210, 0xb300b7b5, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc, + 0xf408f490, 0x3da0ddbf, 0x00b72e3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, + 0x317e070b, 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901, + 0x44da00f8, 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000, + 0xa6300042, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800, + 0x3da0b202, 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a, + 0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, + 0xa00147fe, 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e, + 0xeb00a433, 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b971, + 0x2cd9023f, 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0, + 0xf77e1800, 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, 0xbd0043f0, 0xb8b13e14, + 0x0241bc00, 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, 0xff2ce49a, 0xb26bb2ff, + 0x1300de0d, 0x127e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, 0x7c0eb204, 0x10bc2020, + 0x1300da10, 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, 0xa6000013, 0xa408f414, + 0x00b9603e, 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, 0x18389003, 0x090159b5, + 0x3379a0ff, 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, 0xff26e4f1, 0x3e24bdff, + 0xbc00b951, 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, 0x042d9001, 0x00da1eb2, + 0x7e000013, 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, 0x40417c00, 0x3500a433, + 0x001424d9, 0x7e9abf00, 0xa000ac3c, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, 0xa6000013, 0xa608f426, + 0x5c985bbf, 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, 0x0d33000f, 0x30fe7100, + 0x020f3a01, 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, 0x717e38aa, 0xeb3e000f, + 0x02f900b7, 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, 0xa6008961, 0x009fcf02, + 0x1000f5f1, 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, 0x00a43300, 0x2930d915, + 0x9abf0000, 0x00009b7e, 0x163e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa, + 0x920aa5b6, 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, 0x000001fb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1570,11 +1570,11 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, 0x08400000, 0x08800000, 0x08c300a7, 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, - 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, 0x00209d09, 0x00309d0a, - 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00003b00, 0x46020f1f, - 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, 0x601507ef, 0x801607ef, - 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, 0x7014079d, 0x7015079d, - 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, + 0x12c00000, 0x00000000, 0x00000000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, + 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, + 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, + 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, + 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x1289f13d, 0xdc6acca2, 0x50be285c, 0xd086f67e, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xc901a2e3, 0xd0a96e16, 0x4a0da134, 0xc2405c59, + 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x979b9cb7, 0x7359186e, 0x8b211603, 0x878da8fe, + 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x269562e0, 0x626d8a06, 0xc3df044b, 0x11ecee8e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index 78426d9d23..5c7f533522 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -116,8 +116,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f9881, 0x000f8c82, 0x2abf10bf, 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x78890b18, 0x423e0010, 0x7c89000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, - 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x548f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf000554, + 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x5c8f1132, 0xf9bf0005, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf00055c, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0038a77e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, @@ -179,7 +179,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x31008fff, - 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e001104, + 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00056088, 0x8120597c, 0x3e001104, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0031248f, 0x18909fbc, 0x19180190, @@ -208,7 +208,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0c004d81, 0xcf0b004c, 0xcecf00df, 0x00d9cf00, 0x1bf4f9a6, 0xb5aea0f5, 0x00f801af, 0xcf0b0049, 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, - 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000554, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, + 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x0000055c, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, 0x00289880, 0x8cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3550daf2, 0x50db0000, 0x7e000033, 0x7e0015f6, 0xf7000b68, 0x8cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, @@ -349,7 +349,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x223e02f8, 0xf9cf0027, 0x4c99c700, 0x390090b3, 0xf60190b3, 0x363e02f8, 0xa48f0027, 0x008901ad, 0x9ff601c1, 0xb8f4bd00, 0x00010099, 0xdf009ff6, 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x27363e9f, 0xe400f800, 0xc7ff00bf, 0xaeb2f0b9, - 0xdfd59fff, 0x0000055c, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, + 0xdfd59fff, 0x00000564, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, 0x7501ff58, 0x00f809ef, 0x3f04ff90, 0x009433f9, 0xf8010adf, 0x0aa9b200, 0x00b0b302, 0x3db92008, 0xf900f8a4, 0xb3a0b202, 0x986500a0, 0x90b305a9, 0x0cd95e00, 0xbf000014, 0xe8aab89a, 0x277e0004, 0xa9e7001a, 0x9ab30168, 0xb34c0fff, 0xb6470090, 0xaab314a5, 0xb3400fff, 0x983b00a0, 0x94b6050e, @@ -443,19 +443,19 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xdcdff430, 0xf9000005, 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, - 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06c, 0x00a0b31a, 0x7eb43d1a, 0xb300b104, - 0xbf1200a0, 0x7eff001a, 0x3e00b63e, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, + 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06d, 0x00a0b31a, 0x7eb43d1a, 0xb300b105, + 0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000, 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e, 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50741, 0x352bb201, 0x42b51540, 0xbd92a006, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, 0x980d0090, 0x95f00149, 0x0149b508, 0x000644d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, - 0x95f101f9, 0xf9b54000, 0x299cda01, 0x027e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, + 0x95f101f9, 0xf9b54000, 0x299cda01, 0x037e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, 0xb20091b0, 0xbdb4bd0d, 0x2e70da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, - 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ee7e2b, 0x1fa43300, - 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x0095097e, 0x061fa033, 0xb4bd09f8, 0x097e020a, - 0x9cda0095, 0x7e000029, 0xfe009ab1, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, + 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ef7e2b, 0x1fa43300, + 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x00950a7e, 0x061fa033, 0xb4bd09f8, 0x0a7e020a, + 0x9cda0095, 0x7e000029, 0xfe009ab2, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, 0xd9320204, 0x00000644, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, 0x159f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, 0x033e9824, 0x002a3cd9, 0x2a44df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, @@ -463,8 +463,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, - 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0524de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, - 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b87e, 0x0036063e, 0x1bb20ab2, + 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x052cde3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, + 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b97e, 0x0036063e, 0x1bb20ab2, 0x3e7e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, 0x0000d9be, 0xe9ff4000, 0x6b0bf494, 0x681fa433, 0x900149fe, 0x9dbf4099, 0xbf049992, 0x1ee4339c, 0x0003df42, 0xff89ff00, 0xefff3fff, 0x94d9fff4, 0xff0294b6, 0xc0b3e5f9, 0xe9c50b00, 0x36703e03, @@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, - 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, + 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, @@ -646,7 +646,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x005d0a7e, 0x001404da, 0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7ca, + 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, @@ -662,7 +662,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00, 0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204, 0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014, - 0x95f90e99, 0x1e0a00f8, 0x00b9a17e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, + 0x95f90e99, 0x1e0a00f8, 0x00b9a27e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8, 0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00, 0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000, @@ -751,7 +751,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, 0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01, - 0x4c8900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a09f8, + 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a09f8, 0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, 0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0, 0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00, @@ -859,7 +859,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0xde3e02f8, 0xf9cf0066, 0x4c99c700, 0x3a0090b3, 0xf60190b3, 0xf23e02f8, 0x00d90066, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x006e7e14, 0x0149fe00, 0xbf1c9990, 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0608de00, 0x9fc70000, - 0x1899c710, 0x3515ef35, 0x063e14e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, + 0x1899c710, 0x3516ef35, 0x063e15e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0xf23e9fb2, 0x00890066, 0x99cf01c2, 0x009fe400, 0xff94f120, 0x00fdb33f, 0xc13eff40, 0x448f0066, 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890066a8, 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efec700, 0x8f006681, @@ -1157,371 +1157,371 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2875fb00, 0x00299cd9, 0x15991800, 0xbeb2adb2, 0x0a009033, 0x008b707e, 0x44d900f8, 0xbf000006, 0xb2cab29b, 0xb0bdbcec, 0x000b7e7e, 0x00f81f0a, 0xdff430f4, 0x000005dc, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, - 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xee7e0bb2, 0xa4330094, 0x4bfe551f, - 0x90020a01, 0xee7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, - 0x0f0204b3, 0x009a447e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee509, 0x14999001, 0x19a699bf, - 0x0a150bf4, 0x7e1bb201, 0x33009509, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 0xdf99bf10, + 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xef7e0bb2, 0xa4330094, 0x4bfe551f, + 0x90020a01, 0xef7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, + 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee50a, 0x14999001, 0x19a699bf, + 0x0a150bf4, 0x7e1bb201, 0x3300950a, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 0xdf99bf10, 0xbfffffff, 0xeffd1f0a, 0x0099b904, 0xf09419ff, 0x96f00b9c, 0x1e94b601, 0xa0059efd, 0x8d233e29, 0xfe1f0a00, 0x99900149, 0xd99fbf18, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40c35, 0x05dcdfe4, 0x52f90000, 0x49feffbf, 0x30999001, 0x9fa0a3b2, 0xc5b2afbf, 0xfdc7b4b2, 0x00ddb31d, - 0xfa95075c, 0x10f99508, 0xa132f032, 0xf9339232, 0x3000d515, 0x0cf415f6, 0x05f93346, 0xf63005fb, - 0x1c0cf405, 0x8701f933, 0x301f0a00, 0x08f501f6, 0xf6300739, 0x240cf503, 0x8e283e07, 0x10f93300, - 0xf630041a, 0x0e0cf410, 0xf50df630, 0x3e070e08, 0x33009155, 0x070611fd, 0x00915f3e, 0x421df933, - 0x1df63006, 0x33250cf4, 0x03fa18f9, 0xf418f630, 0xfd330c0c, 0x3e06e717, 0x33009408, 0x01001af9, - 0xd91cfd33, 0x94c53e06, 0x21f93300, 0xf6300262, 0x0c0cf421, 0xc51efd33, 0x8ecd3e06, 0x24f93300, - 0xfd330639, 0x3e06b725, 0xdf009499, 0x0000299c, 0x2614f918, 0x0d18f4a9, 0xbcffa9c4, 0x6e3e98f9, - 0xbda00093, 0x0094303e, 0x1d33080a, 0x7e069d00, 0x330063f7, 0x490a0300, 0xa9fdff00, 0x3e4aa004, - 0x0a009430, 0x04163003, 0x067f0cf5, 0x00299cd9, 0x0e99bf00, 0xbc080a01, 0x99c7f4e1, 0x049ffd98, - 0x06670bf5, 0x0e021033, 0x10041033, 0x843eea32, 0xeab2008e, 0x008e7a3e, 0x4bfea4bd, 0x2cbb9001, - 0x0063b47e, 0x008a847e, 0x3f1fad33, 0x0149fe06, 0xbf2c9990, 0x1fe9959e, 0x0a0190b3, 0xa73ed4bd, - 0x00dd008e, 0xc4ff0000, 0x943380e9, 0xf4bd0a00, 0x008ebe3e, 0xe6b0010f, 0x051ff400, 0xe995ff0f, - 0x95d9ff08, 0xa090f9bc, 0x94c73e49, 0xb29b3200, 0x7e5db24c, 0x3e0077ca, 0x330094c7, 0x305507a0, - 0x0cf407a6, 0x299cd912, 0xa6300000, 0x2b0df402, 0x008f243e, 0xf40ca630, 0x9cd9120c, 0x30000029, - 0x18f409a6, 0x8f473e57, 0x0da03300, 0x33030a61, 0x05b80e1d, 0x008f7a3e, 0xdf019998, 0x04000000, - 0x008f603e, 0xdf019998, 0x08000000, 0x008f603e, 0x00299cd9, 0x02999800, 0x0200008f, 0xf5049ffd, - 0x3e00c61b, 0x98009045, 0x008f0299, 0x9ffd0400, 0xc41bf504, 0x90453e00, 0x02999800, 0x0100008f, - 0xf4049ffd, 0x453e2f1b, 0x9cd90090, 0x8f000029, 0x98400000, 0x873e0299, 0x9cd9008f, 0x98000029, - 0x00df0299, 0xfd008000, 0x1bf5049f, 0x453e00a9, 0x10330090, 0x16307307, 0x1a0cf407, 0x4b021033, - 0xf4021630, 0x1033540c, 0x1d332700, 0x3e048601, 0x30008fd7, 0x0cf40c16, 0x0916300d, 0x3e6518f4, - 0x30009015, 0x0df40e16, 0x94303e6d, 0x7e4ab200, 0x3e00789f, 0x320094c7, 0xb22b321a, 0x7e5db24c, - 0x3e007cca, 0x320094c7, 0xb22b321a, 0x7e5db24c, 0x3e007c3b, 0x320094c7, 0xb22b321a, 0x7e467e4c, - 0x94c73e00, 0xb22b3200, 0x0a5db24c, 0x7ba27e07, 0x94c73e00, 0x32080a00, 0xb24cb22b, 0x7b037e5d, - 0x321a3200, 0xb23cb22b, 0x7e5eb24d, 0x3e007ed3, 0x320094c7, 0xb22b321a, 0xb24db23c, 0x78a77e5e, - 0x94c73e00, 0x3e080a00, 0x0a0094c7, 0x009d3304, 0x9cd9047a, 0x98000029, 0x080a0299, 0x400094f1, - 0x04670bf5, 0xfe0149fe, 0x99900142, 0x1822902c, 0x2da09da0, 0xa0049992, 0x0499929d, 0x99929da0, - 0x929da004, 0x9da00499, 0x85011933, 0x01163000, 0x0a0e08f4, 0x021d3303, 0x213e0432, 0x41fe0091, - 0x0140fe01, 0x902c1190, 0x1ab22800, 0x607e0bb2, 0x19bf0075, 0x43fe00bf, 0x0142fe01, 0x900794f0, - 0x22902433, 0xfe3ab220, 0x2bb20141, 0xf01c1190, 0x1cb20704, 0xfd0404b6, 0x5c7e0509, 0x29bf006a, - 0x1ebf3fbf, 0xb60141fe, 0xf4f00894, 0xff94f1ff, 0x10f4b6ff, 0x9018e4b6, 0x09fd1811, 0xfd1ab205, - 0x0efd050f, 0x6a497e05, 0x91473e00, 0x7e2ab200, 0xb2006a39, 0x7e20bf2a, 0xbf006a29, 0x914d3e29, - 0x0141fe00, 0xb2181190, 0x6a167e1a, 0xbf1ab200, 0x6a037e10, 0xb219bf00, 0xff04f11a, 0x1094b6ff, - 0x7e0590ff, 0xbf0069f0, 0xff94f119, 0xa040a0ff, 0x94303e59, 0x7efab200, 0x3e0095f3, 0x330094c7, - 0x330d00a0, 0x035c01ad, 0x0091ad3e, 0x9033b0bf, 0x94330c01, 0x9d3e2f02, 0x41fe0091, 0x90010a01, - 0x1bb21811, 0x0094ee7e, 0x3f1fad33, 0x091fbf03, 0x9509fffe, 0xa0049fff, 0x91a13e10, 0xff04f100, - 0xb22a3201, 0x95097e0b, 0x94c73e00, 0x7e9a3200, 0x3e0094ee, 0xb20094c7, 0x95227efa, 0x94c73e00, - 0x299cd300, 0x39bf0000, 0x000000df, 0xfd080a20, 0x0bf5049f, 0x030a02f5, 0xef001d33, 0x0140fe02, - 0x90014cfe, 0xcc902800, 0xfe0bb22c, 0x22900142, 0x7e2ab224, 0x7f007347, 0x03967009, 0x940b9cf0, - 0x0e7e0791, 0x30180001, 0x01087e58, 0x00003300, 0x3e1fb20a, 0x7f00924c, 0x00a4732a, 0x3e19b20a, - 0xc500924a, 0xa0734019, 0xa0731403, 0xa4731804, 0x9fe51c02, 0x4c3e0100, 0x9fe50092, 0x4c3e0200, - 0x9fe50092, 0x4c3e0300, 0x9fb20092, 0x900149fe, 0x997f2c99, 0x88049973, 0x04967000, 0x731a0cf4, - 0x70480190, 0x08f40196, 0x02907336, 0x039d734c, 0xce3e00e3, 0x99730092, 0x70009b07, 0x0cf40796, - 0x05907310, 0x069d7369, 0x033e00cb, 0x99730093, 0x73009c08, 0x00bd099d, 0x0093383e, 0xfe07ff89, - 0x3e04f9fd, 0x49009350, 0xf9ffc7ff, 0x0095f194, 0x92bf3e20, 0xc7ff4900, 0xf194f9ff, 0x8f180095, - 0xfdfe3fff, 0x9fe5049f, 0x503e4000, 0xff490093, 0x94f9ffc7, 0x100095f1, 0x0092bf3e, 0xffc7ff49, - 0x95f194f9, 0xf43e0800, 0xff490092, 0x94f9ffc7, 0x100095f1, 0xfe3fff8f, 0xe5049ffd, 0x3e80009f, - 0x49009350, 0xf9ffc7ff, 0x0095f194, 0x931b3e08, 0xc7ff4900, 0xf194f9ff, 0x8f100095, 0xfdfe3fff, - 0x9fe5049f, 0x503ec000, 0xff490093, 0x94f9ffc7, 0x080095f1, 0x0093423e, 0xffc7ff49, 0x95f194f9, - 0xff8f1000, 0x9ffdfe3f, 0x00008f04, 0xf59fff01, 0x00299cd9, 0x50991800, 0x0f009033, 0x02000089, - 0x3e95f9ff, 0x8900936e, 0xfffdffff, 0x49a094f9, 0x0094303e, 0xf514a630, 0xc401480c, 0xd0d9ffaf, - 0xbc000004, 0x9cd9e89f, 0x0a000029, 0x3befc708, 0xc7989fbc, 0x9fbb96ef, 0x0194f005, 0x012b0bf5, - 0xe7ff29c4, 0x54010def, 0x040a029b, 0x18f5bf66, 0xf3f00119, 0xffb9e400, 0xc2f9bcff, 0xf404c6b0, - 0x040c090d, 0x0093ca3e, 0xbae44da0, 0xe9c4ffff, 0x42ebe703, 0x00943301, 0xb0babc12, 0x0029bcd9, - 0x3e4ab200, 0xd90093f3, 0x00000644, 0xbabc99bf, 0xbc4ab2b0, 0x7e7eb09b, 0x303e000b, 0x9b320094, - 0x009aca7e, 0x0094c73e, 0x0f00a033, 0x1d33080a, 0x3e00b101, 0xfe0094c7, 0x00900140, 0x7e0ab224, - 0x3f0072fb, 0x00a54f09, 0x06009433, 0x4fa05a0f, 0xc73e1f0a, 0x9cd90094, 0x18000029, 0x99331599, - 0x33008700, 0x303802a0, 0x0cf402a6, 0x00a0330f, 0x01a43318, 0x946f3e6e, 0x03a03300, 0x04a4332c, - 0x948f3e62, 0x7e3ab200, 0x3e009d81, 0xb20094c7, 0x7ecbb2ba, 0x3e009ffb, 0x320094c7, 0x9d0a7e2a, - 0x94c73e00, 0x7e2a3200, 0x3e00a211, 0x320094c7, 0xa1a57e2a, 0x94c73e00, 0x299cd900, 0x99180000, - 0x00903315, 0x6cfbc724, 0x4db22c32, 0xa4f05eb2, 0x9eab7e0f, 0x94c73e00, 0x3e020a00, 0x0a0094c7, - 0x94c73e03, 0xfe090a00, 0x99900149, 0xd99fbf30, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, - 0xa4f01c55, 0x02a4b6ff, 0x1f0acaa0, 0xaf3200f8, 0xf630040a, 0x120cf402, 0xd9fff4f0, 0x00002a5c, - 0x0af89fbc, 0xf8bfa01f, 0x0aaf3200, 0x02f63004, 0xf0100cf4, 0x5cd9fff4, 0x0a00002a, 0xf99bbc1f, - 0x12f900f8, 0xb210af95, 0x08ae95b1, 0x00299cd0, 0x26ff0900, 0x3d1bf4e9, 0x26490918, 0xb21bf5f9, - 0x4a091800, 0x99331c0a, 0x3000ab01, 0x08f50196, 0x060a00a1, 0x9d029d33, 0x13099800, 0x1f0af43d, - 0x0918b9a0, 0x4a0f3549, 0x35019910, 0xf13e4909, 0x09180095, 0x330a0a4a, 0xd97a0094, 0x00002a5c, - 0xf4f099bf, 0xe899c7ff, 0xbc0694b6, 0xf6b0f0f9, 0x5e0cf43f, 0xe433030a, 0xf9905b0c, 0x4096b104, - 0x4e0cf400, 0xdf02f994, 0x00002a68, 0x7f909fbc, 0x019a589f, 0xf473080d, 0x09981b02, 0xf0290d04, - 0x90338094, 0x4b7e0f00, 0x01090075, 0x0935d43d, 0x299cdf50, 0xfe180000, 0xffd9c449, 0x0913f9b5, - 0x4af93502, 0x0affe4f0, 0x3e1ea01c, 0x0a0095f1, 0xf911fb04, 0xb2adb222, 0xe8a0c7b2, 0x06b0bbbf, - 0xcc0cf53f, 0xffbcc400, 0xb3ffaec4, 0x0a0d0fe4, 0x3fc6b005, 0x00bb0cf5, 0x002a5cd9, 0xc499bf00, - 0x99c7ff9f, 0x06f194e8, 0xb30694b6, 0xb32c0ee0, 0x0a440fe0, 0x0dedb31f, 0x097c009a, 0xff967190, - 0x8c0cf500, 0xff9fe400, 0x2a68d9ff, 0x9fbc0000, 0x3e2fa0f8, 0x7c00966d, 0x96719001, 0x0cf400ff, - 0xff9fe46f, 0x2a68d9ff, 0x9bbc0000, 0x3e1f0af9, 0xbc0096cf, 0x050af0c9, 0x94f0d9c7, 0x999002fb, - 0x029c9401, 0xb1e0cbbc, 0xf41000e6, 0x01bc440c, 0xb6030a90, 0xc9bc0294, 0x00f6b1f0, 0x320cf410, - 0x08f49ba6, 0xf49ea608, 0xb9a62008, 0xa6080df4, 0x1608f4bf, 0x002a68df, 0xa09fbc00, 0x7eb0bfbc, - 0x3e000b7e, 0x0a00966d, 0x96cf3e04, 0xfb030a00, 0xb1c9b221, 0xf40fffa6, 0x9abc2b0c, 0x0096b190, - 0x210cf410, 0x002a68de, 0x90aebc00, 0x0a00d033, 0xfa3e9ab2, 0xbab20096, 0x7e7e9bb2, 0x1f0a000b, - 0x040a00f8, 0x30f400f8, 0x05dcdfe4, 0x12f90000, 0x49feffbf, 0x20999001, 0x9fa0a0b2, 0xb4f0d1b2, - 0xb4edb2ff, 0xe0b40aa0, 0x0709c40b, 0x1bf49ba6, 0x2f0fc775, 0x900149fe, 0x9da00899, 0xb5029eb5, - 0x9fbc019a, 0xfe94bdb8, 0xff90014f, 0xb5f9a014, 0xf1b501fc, 0x2309c702, 0xf9bcbabf, 0x850fc7c8, - 0x3c8a09c7, 0xf4f0e09f, 0x910dc71f, 0x3c05cfbb, 0xeeb990d9, 0x1fd4f000, 0xb91fe4f0, 0xefbc0099, - 0x1f94f0e0, 0x9dbcff0f, 0x95f9bc90, 0xbb05febb, 0xfcfd049d, 0x0099b904, 0xfd04fdbb, 0x9ffd049a, - 0xfeb9a005, 0x99900149, 0xd99fbf20, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f41c15, - 0x05dcd9f4, 0x82f90000, 0xd1b299bf, 0x90014ffe, 0xf9a02cff, 0xff92dd3f, 0x091f0003, 0x01f03517, - 0x2002f035, 0xb2b6b2f9, 0x33a5b2e3, 0xdb1900d4, 0x00000528, 0x7e7e240c, 0x0909000b, 0x19200a32, - 0x0098813e, 0xd630030a, 0x780cf409, 0xc40147fe, 0xf8b2ffc4, 0x7790043d, 0x98783e24, 0xff09c400, - 0x92947bb2, 0xbc040c02, 0xd43da026, 0x0096d17e, 0x6b1fa433, 0xf9c47fbf, 0xf494a607, 0xf9c75e18, - 0x01991223, 0xf4019630, 0xfec7520c, 0xffe9c42f, 0xc7c8893c, 0xf9c78afd, 0x90d93c85, 0x0cf49c26, - 0x03e0333b, 0x91f9c738, 0x26909d3c, 0x2c0cf49c, 0x109052bc, 0x9fa00100, 0x0926193f, 0x0aa108f4, - 0x0149fe1f, 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0x90017000, - 0x3a980122, 0xf52aa603, 0xb2ff3708, 0x3d6eb264, 0xbdd43db4, 0x3ec4bdf4, 0x7f00b496, 0x009473e9, - 0x3e010d0a, 0x3300b490, 0x0b0600d0, 0x01cc9001, 0x9001ff90, 0xfaa602ee, 0xb3e308f4, 0xb50b00c4, - 0xd23e547c, 0xb93300b5, 0x9800a600, 0x96b00139, 0x300cf402, 0x6db20309, 0xbd5479b5, 0x3ef4bde4, - 0x7f00b4d5, 0x009073d9, 0xe9697c0a, 0x9001ee90, 0xdd9001ff, 0x03399802, 0x08f4f9a6, 0xb54c3ee9, - 0x0194bd00, 0x5479b5f1, 0x1bb224bd, 0x00b5263e, 0x09e4407f, 0x0bf4ffff, 0xa6f10f26, 0x0b1bf4bf, - 0xffff0be4, 0x00b51e3e, 0xe40c3a98, 0x7effff0c, 0xb300b675, 0x00b900ad, 0xffff0be4, 0x229019b2, - 0x02449001, 0x399891b2, 0xf429a603, 0xf109c508, 0x0bf5b9a6, 0x3a9800a0, 0x0a3c980c, 0x00b6757e, - 0x8c00adb3, 0x0a31b500, 0x00b5d23e, 0x94bd6f7f, 0xb501c192, 0xf3f05179, 0xb504bd00, 0x8a3e527f, - 0x4b7f00b5, 0x98014c58, 0x00900c3a, 0x00b3f001, 0x9000c3f0, 0x757e0244, 0xa4b300b6, 0xe0b45200, - 0x01e9980b, 0xb5709990, 0x01a601e9, 0x7cd608f4, 0x3a980860, 0xe4f00c0c, 0x7effff0b, 0xb300b675, - 0xfe2d00a4, 0x0be4014c, 0x3ab2ffff, 0x7e40cc90, 0xb300a578, 0x341900a4, 0x7f984690, 0xff94f051, - 0xb5f0f9bc, 0xd23e517f, 0x030a00b5, 0xdd3ea5b2, 0x889000b5, 0x18779001, 0x90148db3, 0x0149fefd, - 0xbf3c9990, 0xb7487e9a, 0xb5f33e00, 0x3e030500, 0xbd00b5f5, 0xb20bb204, 0xa60b7e3a, 0x0050b300, - 0x0c3a981a, 0xc77e04bd, 0x3a9800b6, 0x0c30b50d, 0x00b7487e, 0xfe0d30b5, 0x99900149, 0xd99fbf50, - 0x000005dc, 0x5ab299bf, 0x0bf4f9a6, 0xb6373e11, 0x3e010500, 0x7e00b5f3, 0xfb003a31, 0x02f93085, - 0xe77ea0b2, 0x0a9800a5, 0xb6c77e0c, 0x0d0a9800, 0x00b7487e, 0x487e0ab2, 0xa4bd00b7, 0xa9bf01fb, - 0x020aafb2, 0x18f4b9a6, 0x01b9900d, 0xbd98f9bc, 0xf8c9a0a4, 0xb2a9bf00, 0xa6020aaf, 0x0b18f4b9, - 0xbd01b990, 0x99fcbca4, 0xb9bf00f8, 0xcab2afb2, 0x08f4c9a6, 0xf8f10a07, 0x02fbb500, 0xfcb5fca0, - 0xbf00f801, 0x02af98a9, 0xa090b9bc, 0xa6fbbfa9, 0x0808f49b, 0xa0029bbb, 0x01a998a9, 0xa9a6aabf, - 0x0a051bf4, 0xb300f8f1, 0x7e0800a0, 0xf800b748, 0xf830f400, 0x0005dcdf, 0xbf32f900, 0x0149feff, - 0xb2149990, 0xb29fa0a0, 0x00a0b3b3, 0xa6fd0242, 0x3a0cf4a2, 0xfe01ab90, 0xb4b60141, 0x10119002, - 0xb47e1ab2, 0xa4b300b7, 0x19bf2700, 0x2cb21db2, 0x90a0e4bd, 0xe990dfbf, 0xbc9eb201, 0x90a699fc, - 0xbff408f4, 0x3e3da0dd, 0x0a00b72d, 0x0149fe02, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, - 0x3a317e07, 0x0835fb00, 0x44da00f8, 0x7e000029, 0x300041c7, 0xacf000a6, 0x01a6f00b, 0xf801aab9, - 0x2944da00, 0x427e0000, 0xa6300041, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x002944da, 0x42d77e00, - 0x00a63000, 0xf00bacf0, 0xaab901a6, 0xf000f801, 0x947effb4, 0x00f8000b, 0x000b7e7e, 0x02f900f8, - 0xa43da0b2, 0x00384c7e, 0xf000a6b0, 0x0aa00b9c, 0x01fb9ab2, 0xa0b202f9, 0x2a7ea43d, 0xa6b00038, - 0x0b9cf000, 0x9ab20aa0, 0x30f401fb, 0x05dcdfe4, 0x82f90000, 0x49feffbf, 0x0145fe01, 0xfe3c9990, - 0x9fa00147, 0x90245590, 0x1cd93477, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x7eff0d2c, 0x330000c1, - 0xb4eb00a4, 0x393f0c30, 0xe20c9433, 0x33043118, 0x330f0010, 0x00b00119, 0x703e043d, 0x3f9800b9, - 0x142cd902, 0x31980000, 0x0a345804, 0x9f3f5fa0, 0x90033998, 0x59b51836, 0xa0ff0901, 0x00f43379, - 0x32f77e18, 0x33a03200, 0x012900ad, 0x2cdf0109, 0x20000014, 0xf01272f9, 0x14bd0043, 0x00b8b03e, - 0xb10241bc, 0xf4010006, 0x0040060d, 0x0b947e01, 0x1424d900, 0x9abf0000, 0xffff2ce4, 0x0db26bb2, - 0x001300de, 0xaf117e00, 0xb37aa000, 0x00d400ad, 0x5c985bbf, 0x041d9001, 0x207c0eb2, 0x1010bc20, - 0x001300da, 0x21367e00, 0x33a03200, 0x00c500ad, 0x004cb4bd, 0x1300da01, 0x14a60000, 0x3ea408f4, - 0x9800b95f, 0x2cd9023f, 0x98000014, 0x32580434, 0x3f5fa00a, 0x0339989f, 0xb5183890, 0xff090159, - 0xf43379a0, 0xf77e1600, 0xa0320032, 0x8400ad33, 0x142cdf00, 0xf1200000, 0xffff26e4, 0x503e24bd, - 0x62bc00b9, 0x0016b112, 0x060df401, 0x7e010041, 0xbf000b94, 0x015c985b, 0xb2042d90, 0x1300da1e, - 0xd07e0000, 0x4ce40020, 0x21bcffff, 0xb2a03220, 0xde1db28b, 0x00001300, 0x3340417c, 0xd93500a4, - 0x00001424, 0x3b7e9abf, 0x7aa000ac, 0x1300a4b3, 0x004cb4bd, 0x1300da01, 0x26a60000, 0xbfa608f4, - 0x015c985b, 0xd4bd7ab2, 0x367e040e, 0xa0320021, 0xb22db034, 0x0f817e3a, 0x000d3300, 0x0130fe71, - 0x30020f3a, 0x331838f1, 0xfe040903, 0x9130014a, 0x3b313039, 0xaa90b4bd, 0x0f717e38, 0xb7ea3e00, - 0xd902f900, 0x00002930, 0x9abfa0b2, 0xde7e640b, 0x10090000, 0x6100a433, 0x02a60089, 0xf1009fcf, - 0xf61000f5, 0x008a009f, 0x004b02a6, 0x4dc4bd10, 0xe4bd2710, 0x00198b7e, 0x1500a433, 0x002930d9, - 0x7e9abf00, 0x0900009b, 0xba153e04, 0x4b0ab200, 0xfc7e03e8, 0x00890016, 0xaab802a4, 0xb6000200, - 0xaa920aa5, 0x009af601, 0xb801114f, 0x00020099, 0x3d009ff6, 0xfb9a3294, 0x00000001, 0x00000000, + 0xfa95075d, 0x10f99508, 0xa132f032, 0xf9339232, 0x3000d515, 0x0cf415f6, 0x05f93346, 0xf63005fc, + 0x1c0cf405, 0x8701f933, 0x301f0a00, 0x08f501f6, 0xf630073a, 0x250cf503, 0x8e283e07, 0x10f93300, + 0xf630041b, 0x0e0cf410, 0xf50df630, 0x3e070f08, 0x33009156, 0x070711fd, 0x0091603e, 0x431df933, + 0x1df63006, 0x33250cf4, 0x03fb18f9, 0xf418f630, 0xfd330c0c, 0x3e06e817, 0x33009409, 0x01011af9, + 0xda1cfd33, 0x94c63e06, 0x21f93300, 0xf6300263, 0x0c0cf421, 0xc61efd33, 0x8ece3e06, 0x24f93300, + 0xfd33063a, 0x3e06b825, 0xdf00949a, 0x0000299c, 0x2614f918, 0x0d18f4a9, 0xbcffa9c4, 0x6f3e98f9, + 0xbda00093, 0x0094313e, 0x1d33080a, 0x7e069e00, 0x330063f7, 0x490a0300, 0xa9fdff00, 0x3e4aa004, + 0x0a009431, 0x09163003, 0x06800cf5, 0x00299cd9, 0x0e99bf00, 0xbc080a01, 0x99e7f4e1, 0x9ffd0133, + 0x670bf504, 0x02103306, 0x0410330e, 0x3eea3210, 0xb2008e85, 0x8e7b3eea, 0xfea4bd00, 0xbb90014b, + 0x63b47e2c, 0x8a847e00, 0x1fad3300, 0x49fe063f, 0x2c999001, 0xe9959ebf, 0x0190b31f, 0x3ed4bd0a, + 0xdd008ea8, 0xff000000, 0x3380e9c4, 0xbd0a0094, 0x8ebf3ef4, 0xb0010f00, 0x1ff400e6, 0x95ff0f05, + 0xd9ff08e9, 0x90f9bc95, 0xc83e49a0, 0x9b320094, 0x5db24cb2, 0x0077ca7e, 0x0094c83e, 0x5507a033, + 0xf407a630, 0x9cd9120c, 0x30000029, 0x0df402a6, 0x8f253e2b, 0x0ca63000, 0xd9120cf4, 0x0000299c, + 0xf409a630, 0x483e5718, 0xa033008f, 0x030a610d, 0xb80e1d33, 0x8f7b3e05, 0x01999800, 0x000000df, + 0x8f613e04, 0x01999800, 0x000000df, 0x8f613e08, 0x299cd900, 0x99980000, 0x00008f02, 0x049ffd02, + 0x00c61bf5, 0x0090463e, 0x8f029998, 0xfd040000, 0x1bf5049f, 0x463e00c4, 0x99980090, 0x00008f02, + 0x049ffd01, 0x3e2f1bf4, 0xd9009046, 0x0000299c, 0x4000008f, 0x3e029998, 0xd9008f88, 0x0000299c, + 0xdf029998, 0x00800000, 0xf5049ffd, 0x3e00a91b, 0x33009046, 0x30730710, 0x0cf40716, 0x0210331a, + 0x0216304b, 0x33540cf4, 0x33270010, 0x0486011d, 0x008fd83e, 0xf40c1630, 0x16300d0c, 0x6518f409, + 0x0090163e, 0xf40e1630, 0x313e6d0d, 0x4ab20094, 0x00789f7e, 0x0094c83e, 0x2b321a32, 0x5db24cb2, + 0x007cca7e, 0x0094c83e, 0x2b321a32, 0x5db24cb2, 0x007c3b7e, 0x0094c83e, 0x2b321a32, 0x467e4cb2, + 0xc83e007e, 0x2b320094, 0x5db24cb2, 0xa27e070a, 0xc83e007b, 0x080a0094, 0x4cb22b32, 0x037e5db2, + 0x1a32007b, 0x3cb22b32, 0x5eb24db2, 0x007ed37e, 0x0094c83e, 0x2b321a32, 0x4db23cb2, 0xa77e5eb2, + 0xc83e0078, 0x080a0094, 0x0094c83e, 0x9d33040a, 0xd9047a00, 0x0000299c, 0x0a029998, 0x0094f108, + 0x670bf540, 0x0149fe04, 0x900142fe, 0x22902c99, 0xa09da018, 0x0499922d, 0x99929da0, 0x929da004, + 0x9da00499, 0xa0049992, 0x0119339d, 0x16300085, 0x0e08f401, 0x1d33030a, 0x3e043202, 0xfe009122, + 0x40fe0141, 0x2c119001, 0xb2280090, 0x7e0bb21a, 0xbf007560, 0xfe00bf19, 0x42fe0143, 0x0794f001, + 0x90243390, 0x3ab22022, 0xb20141fe, 0x1c11902b, 0xb20704f0, 0x0404b61c, 0x7e0509fd, 0xbf006a5c, + 0xbf3fbf29, 0x0141fe1e, 0xf00894b6, 0x94f1fff4, 0xf4b6ffff, 0x18e4b610, 0xfd181190, 0x1ab20509, + 0xfd050ffd, 0x497e050e, 0x483e006a, 0x2ab20091, 0x006a397e, 0x20bf2ab2, 0x006a297e, 0x4e3e29bf, + 0x41fe0091, 0x18119001, 0x167e1ab2, 0x1ab2006a, 0x037e10bf, 0x19bf006a, 0x04f11ab2, 0x94b6ffff, + 0x0590ff10, 0x0069f07e, 0x94f119bf, 0x40a0ffff, 0x313e59a0, 0xfab20094, 0x0095f47e, 0x0094c83e, + 0x0d00a033, 0x5c01ad33, 0x91ae3e03, 0x33b0bf00, 0x330c0190, 0x3e2f0294, 0xfe00919e, 0x010a0141, + 0xb2181190, 0x94ef7e1b, 0x1fad3300, 0x1fbf033f, 0x09fffe09, 0x049fff95, 0xa23e10a0, 0x04f10091, + 0x2a3203ff, 0x0a7e0bb2, 0xc83e0095, 0x9a320094, 0x0094ef7e, 0x0094c83e, 0x237efab2, 0xc83e0095, + 0x9cd30094, 0xbf000029, 0x0000df39, 0x080a2000, 0xf5049ffd, 0x0a02f50b, 0x001d3303, 0x40fe02ef, + 0x014cfe01, 0x90280090, 0x0bb22ccc, 0x900142fe, 0x2ab22422, 0x0073477e, 0x9670097f, 0x0b9cf003, + 0x7e079194, 0x1800010e, 0x087e5830, 0x00330001, 0x1fb20a00, 0x00924d3e, 0xa4732a7f, 0x19b20a00, + 0x00924b3e, 0x734019c5, 0x731403a0, 0x731804a0, 0xe51c02a4, 0x3e01009f, 0xe500924d, 0x3e02009f, + 0xe500924d, 0x3e03009f, 0xb200924d, 0x0149fe9f, 0x7f2c9990, 0x04997399, 0x96700088, 0x1a0cf404, + 0x48019073, 0xf4019670, 0x90733608, 0x9d734c02, 0x3e00e303, 0x730092cf, 0x009b0799, 0xf4079670, + 0x9073100c, 0x9d736905, 0x3e00cb06, 0x73009304, 0x009c0899, 0xbd099d73, 0x93393e00, 0x07ff8900, + 0x04f9fdfe, 0x0093513e, 0xffc7ff49, 0x95f194f9, 0xc03e2000, 0xff490092, 0x94f9ffc7, 0x180095f1, + 0xfe3fff8f, 0xe5049ffd, 0x3e40009f, 0x49009351, 0xf9ffc7ff, 0x0095f194, 0x92c03e10, 0xc7ff4900, + 0xf194f9ff, 0x3e080095, 0x490092f5, 0xf9ffc7ff, 0x0095f194, 0x3fff8f10, 0x049ffdfe, 0x80009fe5, + 0x0093513e, 0xffc7ff49, 0x95f194f9, 0x1c3e0800, 0xff490093, 0x94f9ffc7, 0x100095f1, 0xfe3fff8f, + 0xe5049ffd, 0x3ec0009f, 0x49009351, 0xf9ffc7ff, 0x0095f194, 0x93433e08, 0xc7ff4900, 0xf194f9ff, + 0x8f100095, 0xfdfe3fff, 0x008f049f, 0x9fff0100, 0x299cd9f5, 0x99180000, 0x00903350, 0x0000890f, + 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x16a63000, 0x01480cf5, 0xd9ffafc4, + 0x000004d0, 0xd9e89fbc, 0x0000299c, 0xefc7080a, 0x989fbc3b, 0xbb96efc7, 0x94f0059f, 0x2b0bf501, + 0xff29c401, 0x010defe7, 0x0a029b54, 0xf5bf6604, 0xf0011918, 0xb9e400f3, 0xf9bcffff, 0x04c6b0c2, + 0x0c090df4, 0x93cb3e04, 0xe44da000, 0xc4ffffba, 0xebe703e9, 0x94330142, 0xbabc1200, 0x29bcd9b0, + 0x4ab20000, 0x0093f43e, 0x000644d9, 0xbc99bf00, 0x4ab2b0ba, 0x7eb09bbc, 0x3e000b7e, 0x32009431, + 0x9acb7e9b, 0x94c83e00, 0x00a03300, 0x33080a0f, 0x00b1011d, 0x0094c83e, 0x900140fe, 0x0ab22400, + 0x0072fb7e, 0xa54f093f, 0x00943300, 0xa05a0f06, 0x3e1f0a4f, 0xd90094c8, 0x0000299c, 0x33159918, + 0x00870099, 0x3802a033, 0xf402a630, 0xa0330f0c, 0xa4331800, 0x703e6e01, 0xa0330094, 0xa4332c03, + 0x903e6204, 0x3ab20094, 0x009d827e, 0x0094c83e, 0xcbb2bab2, 0x009ffc7e, 0x0094c83e, 0x0b7e2a32, + 0xc83e009d, 0x2a320094, 0x00a2127e, 0x0094c83e, 0xa67e2a32, 0xc83e00a1, 0x9cd90094, 0x18000029, + 0x90331599, 0xfbc72400, 0xb22c326c, 0xf05eb24d, 0xac7e0fa4, 0xc83e009e, 0x020a0094, 0x0094c83e, + 0xc83e030a, 0x090a0094, 0x900149fe, 0x9fbf3099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, + 0xf01c55fb, 0xa4b6ffa4, 0x0acaa002, 0x3200f81f, 0x30040aaf, 0x0cf402f6, 0xfff4f012, 0x002a5cd9, + 0xf89fbc00, 0xbfa01f0a, 0xaf3200f8, 0xf630040a, 0x100cf402, 0xd9fff4f0, 0x00002a5c, 0x9bbc1f0a, + 0xf900f8f9, 0x10af9512, 0xae95b1b2, 0x299cd008, 0xff090000, 0x1bf4e926, 0x4909183d, 0x1bf5f926, + 0x091800b2, 0x331c0a4a, 0x00ab0199, 0xf5019630, 0x0a00a108, 0x029d3306, 0x0998009d, 0x0af43d13, + 0x18b9a01f, 0x0f354909, 0x0199104a, 0x3e490935, 0x180095f2, 0x0a0a4a09, 0x7a009433, 0x002a5cd9, + 0xf099bf00, 0x99c7fff4, 0x0694b6e8, 0xb0f0f9bc, 0x0cf43ff6, 0x33030a5e, 0x905b0ce4, 0x96b104f9, + 0x0cf40040, 0x02f9944e, 0x002a68df, 0x909fbc00, 0x9a589f7f, 0x73080d01, 0x981b02f4, 0x290d0409, + 0x338094f0, 0x7e0f0090, 0x0900754b, 0x35d43d01, 0x9cdf5009, 0x18000029, 0xd9c449fe, 0x13f9b5ff, + 0xf9350209, 0xffe4f04a, 0x1ea01c0a, 0x0095f23e, 0x11fb040a, 0xadb222f9, 0xa0c7b2b2, 0xb0bbbfe8, + 0x0cf53f06, 0xbcc400cc, 0xffaec4ff, 0x0d0fe4b3, 0xc6b0050a, 0xbb0cf53f, 0x2a5cd900, 0x99bf0000, + 0xc7ff9fc4, 0xf194e899, 0x0694b606, 0x2c0ee0b3, 0x440fe0b3, 0xedb31f0a, 0x7c009a0d, 0x96719009, + 0x0cf500ff, 0x9fe4008c, 0x68d9ffff, 0xbc00002a, 0x2fa0f89f, 0x00966e3e, 0x7190017c, 0xf400ff96, + 0x9fe46f0c, 0x68d9ffff, 0xbc00002a, 0x1f0af99b, 0x0096d03e, 0x0af0c9bc, 0xf0d9c705, 0x9002fb94, + 0x9c940199, 0xe0cbbc02, 0x1000e6b1, 0xbc440cf4, 0x030a9001, 0xbc0294b6, 0xf6b1f0c9, 0x0cf41000, + 0xf49ba632, 0x9ea60808, 0xa62008f4, 0x080df4b9, 0x08f4bfa6, 0x2a68df16, 0x9fbc0000, 0xb0bfbca0, + 0x000b7e7e, 0x00966e3e, 0xd03e040a, 0x030a0096, 0xc9b221fb, 0x0fffa6b1, 0xbc2b0cf4, 0x96b1909a, + 0x0cf41000, 0x2a68de21, 0xaebc0000, 0x00d03390, 0x3e9ab20a, 0xb20096fb, 0x7e9bb2ba, 0x0a000b7e, + 0x0a00f81f, 0xf400f804, 0xdcdfe430, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0a0b220, 0xf0d1b29f, + 0xedb2ffb4, 0xb40aa0b4, 0x09c40be0, 0xf49ba607, 0x0fc7751b, 0x0149fe2f, 0xa0089990, 0x029eb59d, + 0xbc019ab5, 0x94bdb89f, 0x90014ffe, 0xf9a014ff, 0xb501fcb5, 0x09c702f1, 0xbcbabf23, 0x0fc7c8f9, + 0x8a09c785, 0xf0e09f3c, 0x0dc71ff4, 0x05cfbb91, 0xb990d93c, 0xd4f000ee, 0x1fe4f01f, 0xbc0099b9, + 0x94f0e0ef, 0xbcff0f1f, 0xf9bc909d, 0x05febb95, 0xfd049dbb, 0x99b904fc, 0x04fdbb00, 0xfd049afd, + 0xb9a0059f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41c15fb, + 0xdcd9f430, 0xf9000005, 0xb299bf82, 0x014ffed1, 0xa02cff90, 0x92dd3ff9, 0x1f0003ff, 0xf0351709, + 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000530db, 0x7e240c00, 0x09000b7e, 0x200a3209, + 0x98823e19, 0x30030a00, 0x0cf409d6, 0x0147fe78, 0xb2ffc4c4, 0x90043df8, 0x793e2477, 0x09c40098, + 0x947bb2ff, 0x040c0292, 0x3da026bc, 0x96d27ed4, 0x1fa43300, 0xc47fbf6b, 0x94a607f9, 0xc75e18f4, + 0x991223f9, 0x01963001, 0xc7520cf4, 0xe9c42ffe, 0xc8893cff, 0xc78afdc7, 0xd93c85f9, 0xf49c2690, + 0xe0333b0c, 0xf9c73803, 0x909d3c91, 0x0cf49c26, 0x9052bc2c, 0xa0010010, 0x26193f9f, 0xa108f409, + 0x49fe1f0a, 0x2c999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xb23e230b, 0x0d0a0098, 0x0fc439bf, + 0x0000deff, 0x9efdff00, 0x05f9fd04, 0x823e3fa0, 0x317e0098, 0x85fb003a, 0xa830f40c, 0x0005dcd9, + 0xbf82f900, 0xf830f499, 0x4ffea7b2, 0x80ff9001, 0xaabff9a0, 0xb00eb1b0, 0xa6c70dc1, 0x01691268, + 0xf5039630, 0xc7013b0c, 0x96306ca9, 0x310cf50a, 0x0141fe01, 0x900140fe, 0x00905711, 0x10a5b650, + 0xb4bd1920, 0xe37e0cb2, 0xad330094, 0xbf011d1f, 0x0142fe09, 0x90ff6bc4, 0xb4b65822, 0xbc2ab204, + 0x6c32b0b9, 0x7eb21db2, 0x0097bf7e, 0x333fa130, 0x00f51fad, 0x080141fe, 0x40119001, 0x1990243d, + 0x0c1e9008, 0x54bd343d, 0xb00c91b0, 0x0e3e0be1, 0x90b4009a, 0x0c1bb214, 0xbcd43d10, 0x4ab24059, + 0x0096d27e, 0xc31fad33, 0x9819bf00, 0xffde011f, 0xfde0ffff, 0x1fb5049e, 0x3319a002, 0x3d0a0020, + 0x99a83e04, 0x0cb0b400, 0xb20bc0b4, 0x8d3e7e1a, 0x321fbf00, 0xffffdea0, 0x09c4e0ff, 0x04fefd1f, + 0xfd1894b6, 0x19a0059f, 0x1bb24ab2, 0x010d100c, 0x0096d27e, 0x731fa433, 0x0a002033, 0x083e0102, + 0x0433009a, 0x043d3f1f, 0x0099f53e, 0x98ff09c4, 0x1d98021c, 0x0de0b403, 0x90014ffe, 0xf9bc58ff, + 0x0e90b4a8, 0x1001e1b0, 0x3b320100, 0xb20091b0, 0x97077e7e, 0x57903400, 0x08f40926, 0x9a083ed2, + 0x3d19bf00, 0x1f929584, 0x90013310, 0x36261055, 0xff4208f5, 0x80331b0a, 0x243e1100, 0x030a009a, + 0x009a273e, 0xfe3fa034, 0x99900149, 0xd99fbf80, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf4003a31, + 0x85fb0830, 0xf430f458, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xfe109990, 0x9fa00141, 0x4a0c1190, + 0x040b00b8, 0x307e1cb2, 0xa433008c, 0x40fe2b1f, 0x00b44a01, 0x0b080090, 0x7e0cb204, 0x33008c30, + 0xbf161fa4, 0xa60fbf19, 0x0b9cf09f, 0x320196f0, 0x9a973e9a, 0xfea43d00, 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0x299cd99f, 0x99980000, 0x0ab2b204, 0x0094f108, 0x360bf440, 0xbd0140fe, 0x0c0090b4, 0x4d7e0ab2, + 0xa433009c, 0x0ab2251f, 0x010c1b32, 0x009c127e, 0x171fa433, 0x90ff19c4, 0x99bc0299, 0x9009bc90, + 0x92f0997f, 0xfe29a00f, 0x99900149, 0xd99fbf30, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, + 0x30f42825, 0x05dcdfd8, 0x62f90000, 0x49feffbf, 0x40999001, 0x9fa0b2b2, 0x00299cd9, 0x04999800, + 0xc3b2a6b2, 0x94f1080b, 0x0bf51000, 0xb4bd00e5, 0x900141fe, 0x1ab21c11, 0x009c4d7e, 0xad33ab32, + 0x0b00d11f, 0x0c1ab2ff, 0x9c127e01, 0x33ab3200, 0x00c01fad, 0x1ab2ff0b, 0x127ec43d, 0xab32009c, + 0xaf1fad33, 0x01145800, 0x29a094bd, 0x109039a0, 0x72157f04, 0x4da47d4c, 0xe4bd8000, 0x323e0101, + 0xc9c4009e, 0x200bf401, 0xfd660f7f, 0xbc0a1df4, 0x273ea41e, 0xfd66009e, 0xbc0d1bf4, 0xa9fd941e, + 0x9e273e05, 0x90df7200, 0xc57601ee, 0x02009001, 0xc473fd72, 0x6ebfd000, 0xc400d3f0, 0xffdfffa9, + 0xb6ff00ff, 0xeffd1094, 0x00008c04, 0x059efdff, 0xfd049cfd, 0x69a0059d, 0x4ee429bf, 0xafc7ffff, + 0x10ed94e8, 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0x030000ae, 0x00aee23e, + 0x49fe0200, 0x5c999001, 0xdcd99fbf, 0xbf000005, 0xa60ab299, 0x170bf4f9, 0x00af083e, 0x33062918, + 0xfe4f009d, 0x00aec03e, 0x003a317e, 0xfb0830f4, 0x30f43485, 0x05dcdfdc, 0x82f90000, 0x30f4ffbf, + 0x0149fef8, 0xa04c9990, 0x0bb1b09f, 0xd4b2c2b2, 0xa5b2e6b2, 0x1700b9b3, 0x00e9b301, 0x94bd0112, + 0x3d0141fe, 0x481190c4, 0x1db219a0, 0x00a6407e, 0xadb3a0b2, 0xbf00fb00, 0xf042bc19, 0xa6019998, + 0xea08f59f, 0x005ab200, 0xa5ea7e03, 0xb3a3b200, 0x00de00a9, 0x5c981bbf, 0x0140fe0c, 0xb2300090, + 0xa6287e0a, 0xcc0ab200, 0xc17e702b, 0xa8b200a6, 0xad00adb3, 0x7021cd00, 0x420147fe, 0x77900080, + 0xb0383e44, 0x0c00b400, 0x79a094bd, 0x09a6f009, 0x00091bf4, 0xb03f3e02, 0xa6f00900, 0x090df409, + 0x3f3e0300, 0xc0b400b0, 0x0704b60b, 0x0db2e4bd, 0xb4bd5ab2, 0xb00021b0, 0xe47e0171, 0x5abf00a5, + 0x2cb20bb2, 0x797e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xe67e0db2, 0x04b300a5, 0x3ab24500, + 0x117eb4bd, 0xa0b200a4, 0x3700a4b3, 0x01bb7000, 0xf404a602, 0x40b2050d, 0xb2101b90, 0xb03bbc6a, + 0x997e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xaa7e6060, 0x14bd00a6, 0x6d004db3, 0xb280b2ff, + 0x7e3bb25a, 0x3e00a60c, 0x0000b04d, 0x0149fe02, 0xbf4c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60ab2, + 0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005dcd9, 0xbf32f900, 0x014ffe99, 0xb214ff90, + 0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0x9f7e0ab2, 0x09bf00b7, 0x4c0090b3, + 0x4800a4b3, 0x09bf91a0, 0xbf0192b5, 0x1000490f, 0xbf04f9b5, 0xb520090f, 0x09bf05f9, 0xbf0693b5, + 0x3501090f, 0x09bf1cf9, 0xbf2c9a35, 0xb5f0090f, 0x0fbf0af9, 0xb540f990, 0x0fbf0ef9, 0xb5c0f990, + 0x0abf0ff9, 0x00b0ea3e, 0x49fea4bd, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, + 0x35fb003a, 0xd030f408, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2509990, 0x059fa0a3, 0x00a9b302, + 0xb63004fb, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5ea7e, 0x3abfa0b2, 0x804cb4bd, 0x7e0db200, + 0xb200b779, 0x00adb3a5, 0x093f04b1, 0xa24a9d33, 0x01091804, 0x9a469d33, 0x02091804, 0x92469d33, + 0x03091804, 0x8a539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, 0xf0ff94f0, 0x94b6fff4, + 0x10f4b608, 0xb6059efd, 0xf9fd18d4, 0x05dffd05, 0x045e0bf5, 0xd6b00505, 0x5d0cf503, 0x013db504, + 0x0e01d4b3, 0xb5500049, 0xd83e0239, 0x0d1800b1, 0x09091808, 0x180a0f18, 0xd4f00b0e, 0xff94f0ff, + 0xb6fff4f0, 0xf4b60894, 0x059dfd10, 0xfd18e4b6, 0xeffd05f9, 0x023eb505, 0x0bb23ab2, 0x00a60c7e, + 0x09023a98, 0xf4a9a6ff, 0x04bd091b, 0x00b5ee3e, 0x9007a5b6, 0x3ab5303b, 0xb6d27e03, 0xb3a5b200, + 0x03f500ad, 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb79f7e03, 0xb3a5b200, 0x03d900ad, + 0xfe0147fe, 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3483e, 0x8ea0e4bd, 0x0f0044b3, + 0xbd0c3a98, 0x3efe0cb4, 0xb200b26b, 0xb24bb23a, 0xa5797e7c, 0xb3a5b200, 0x039d00ad, 0x94f0793f, + 0x120bf401, 0xb20c3a98, 0x7eff0c4b, 0x3e00b676, 0xb200b345, 0xa3307e7a, 0x00a0b300, 0x0c3a980f, + 0xfd0c4bb2, 0x00b26b3e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, 0xb400b33a, 0x3ab209b0, + 0x8db2010c, 0x00a6407e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, 0x980a91b0, 0x54b354f5, + 0xb0b43900, 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, 0x997e1ab2, 0x30bc00b7, + 0x4309b800, 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b305, 0xff900122, 0x1424b318, + 0xb6323ebe, 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, 0xcc00f3f0, 0x96cb70ff, + 0xcb4bb21f, 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2e6, 0x4bb20c3a, 0x767e6cb2, 0xa5b200b6, + 0xb400adb3, 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, 0xb57e8ab2, 0xa5b200b7, + 0x9400adb3, 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, 0x39bc0001, 0x0b91b090, + 0x5300f9b3, 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b7907e, 0x3e0f60b4, 0x9800b463, + 0x2bb20d3a, 0x7e0c41b0, 0x3300a2f6, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, 0x7e38cc90, 0xb300b65f, + 0x020c00ad, 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, 0x0c2bb20d, 0xa2ee7e01, + 0x014cfe00, 0x2bb23ab2, 0x7e30cc90, 0xb300a594, 0x981306a4, 0x2bb20c3a, 0x767efd0c, 0x603e00b6, + 0xadb300b4, 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, 0x091bf4ff, 0x603e0260, + 0x3a9800b4, 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b65f, 0x019800ad, 0x343af034, 0xf9263690, + 0x60100df4, 0xff1be402, 0x0c3a98ff, 0x00b4553e, 0xb20c3a98, 0x7efd0c2b, 0xb300b676, 0x017000ad, + 0x98012290, 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, 0x00b4973e, 0x9473e97f, + 0x010d0a00, 0x00b4913e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, 0xe308f4fa, 0x0b00c4b3, + 0x3e547cb5, 0x3300b5d3, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, 0x5479b56d, 0xf4bde4bd, + 0x00b4d63e, 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, 0xf4f9a603, 0x4d3ee908, + 0x94bd00b5, 0x79b5f101, 0xb224bd54, 0xb5273e1b, 0xe4407f00, 0xf4ffff09, 0xf10f260b, 0x1bf4bfa6, + 0xff0be40b, 0xb51f3eff, 0x0c3a9800, 0xffff0ce4, 0x00b6767e, 0xb900adb3, 0xff0be400, 0x9019b2ff, + 0x44900122, 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, 0x3c980c3a, 0xb6767e0a, + 0x00adb300, 0x31b5008c, 0xb5d33e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, 0x04bd00f3, 0x3e527fb5, + 0x7f00b58b, 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, 0xb300b676, 0xb45200a4, + 0xe9980be0, 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, 0xffff0be4, 0x00b6767e, + 0x2d00a4b3, 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5797e, 0x1900a4b3, 0x98469034, 0x94f0517f, + 0xf0f9bcff, 0x3e517fb5, 0x0a00b5d3, 0x3ea5b203, 0x9000b5de, 0x77900188, 0x148db318, 0x49fefd90, + 0x3c999001, 0x497e9abf, 0xf43e00b7, 0x030500b5, 0x00b5f63e, 0x0bb204bd, 0x0c7e3ab2, 0x50b300a6, + 0x3a981a00, 0x7e04bd0c, 0x9800b6c8, 0x30b50d3a, 0xb7497e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099, + 0x0005dcd9, 0xb299bf00, 0xf4f9a65a, 0x383e110b, 0x010500b6, 0x00b5f43e, 0x003a317e, 0xf93085fb, + 0x7ea0b202, 0x9800a5e8, 0xc87e0c0a, 0x0a9800b6, 0xb7497e0d, 0x7e0ab200, 0xbd00b749, 0xbf01fba4, + 0x0aafb2a9, 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6, + 0x01b9900b, 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002, + 0x00f801fc, 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01, + 0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7497e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf, + 0x14999001, 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4, + 0x7e1ab210, 0xb300b7b5, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc, + 0xf408f490, 0x3da0ddbf, 0x00b72e3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, + 0x317e070b, 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901, + 0x44da00f8, 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000, + 0xa6300042, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800, + 0x3da0b202, 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a, + 0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, + 0xa00147fe, 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e, + 0xeb00a433, 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b971, + 0x2cd9023f, 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0, + 0xf77e1800, 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, 0xbd0043f0, 0xb8b13e14, + 0x0241bc00, 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, 0xff2ce49a, 0xb26bb2ff, + 0x1300de0d, 0x127e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, 0x7c0eb204, 0x10bc2020, + 0x1300da10, 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, 0xa6000013, 0xa408f414, + 0x00b9603e, 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, 0x18389003, 0x090159b5, + 0x3379a0ff, 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, 0xff26e4f1, 0x3e24bdff, + 0xbc00b951, 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, 0x042d9001, 0x00da1eb2, + 0x7e000013, 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, 0x40417c00, 0x3500a433, + 0x001424d9, 0x7e9abf00, 0xa000ac3c, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, 0xa6000013, 0xa608f426, + 0x5c985bbf, 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, 0x0d33000f, 0x30fe7100, + 0x020f3a01, 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, 0x717e38aa, 0xeb3e000f, + 0x02f900b7, 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, 0xa6008961, 0x009fcf02, + 0x1000f5f1, 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, 0x00a43300, 0x2930d915, + 0x9abf0000, 0x00009b7e, 0x163e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa, + 0x920aa5b6, 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, 0x000001fb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1570,11 +1570,11 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, 0x08400000, 0x08800000, 0x08c300a7, 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, - 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, 0x00209d09, 0x00309d0a, - 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00003b00, 0x46020f1f, - 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, 0x601507ef, 0x801607ef, - 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, 0x7014079d, 0x7015079d, - 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, + 0x12c00000, 0x00000000, 0x00000000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, + 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, + 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, + 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, + 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x1289f13d, 0xdc6acca2, 0x50be285c, 0xd086f67e, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xc901a2e3, 0xd0a96e16, 0x4a0da134, 0xc2405c59, + 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x979b9cb7, 0x7359186e, 0x8b211603, 0x878da8fe, + 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x269562e0, 0x626d8a06, 0xc3df044b, 0x11ecee8e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h b/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h index 81419272fd..d482145135 100644 --- a/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/nvswitch/kernel/lr10/link_lr10.c b/src/common/nvswitch/kernel/lr10/link_lr10.c index f0c053cad8..042933a8c8 100644 --- a/src/common/nvswitch/kernel/lr10/link_lr10.c +++ b/src/common/nvswitch/kernel/lr10/link_lr10.c @@ -28,6 +28,7 @@ #include "regkey_nvswitch.h" #include "lr10/lr10.h" #include "lr10/minion_lr10.h" +#include "lr10/pmgr_lr10.h" #include "nvswitch/lr10/dev_nvldl_ip.h" #include "nvswitch/lr10/dev_nvldl_ip_addendum.h" @@ -42,6 +43,45 @@ #include "nvswitch/lr10/dev_nvlipt_ip.h" #include "nvswitch/lr10/dev_nport_ip.h" +#define NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK 8 // This must be incremented if any entries are added to the array below +lr10_links_connected_to_disabled_remote_end nvswitchDisconnetedRemoteLinkMasks[] = +{ + { + 0x8, // switchPhysicalId + 0x56A000500 //linkMask + }, + { + 0x9, // switchPhysicalId + 0x509009900 //linkMask + }, + { + 0xb, // switchPhysicalId + 0x56A000600 //linkMask + }, + { + 0xc, // switchPhysicalId + 0x4A9009400 //linkMask + }, + { + 0x18, // switchPhysicalId + 0x56A000500 //linkMask + }, + { + 0x19, // switchPhysicalId + 0x509009900 //linkMask + }, + { + 0x1b, // switchPhysicalId + 0x56A000600 //linkMask + }, + { + 0x1c, // switchPhysicalId + 0x4A9009400 //linkMask + }, +}; +ct_assert(sizeof(nvswitchDisconnetedRemoteLinkMasks)/sizeof(lr10_links_connected_to_disabled_remote_end) == NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK); + + void nvswitch_setup_link_loopback_mode_lr10 ( @@ -799,6 +839,23 @@ nvswitch_corelib_set_dl_link_mode_lr10 return -NVL_UNBOUND_DEVICE; } + if (nvswitch_does_link_need_termination_enabled(device, link)) + { + + if (mode == NVLINK_LINKSTATE_INITPHASE1) + { + status = nvswitch_link_termination_setup(device, link); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to enable termination on link #%d\n", __FUNCTION__, link->linkNumber); + } + } + + // return SUCCESS to avoid errors being propogated + return NVL_SUCCESS; + } + switch (mode) { case NVLINK_LINKSTATE_SAFE: @@ -872,7 +929,7 @@ nvswitch_corelib_set_dl_link_mode_lr10 NVSWITCH_PRINT(device, ERROR, "%s: link #%d is still in reset, cannot change link state\n", __FUNCTION__, link->linkNumber); - return NVL_ERR_INVALID_STATE; + return -NVL_ERR_INVALID_STATE; } val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _LINK_STATE); @@ -1233,6 +1290,15 @@ nvswitch_corelib_set_tl_link_mode_lr10 return -NVL_UNBOUND_DEVICE; } + if (nvswitch_does_link_need_termination_enabled(device, link)) + { + NVSWITCH_PRINT(device, INFO, + "%s: link #% is connected to a disabled remote end. Skipping TL link mode request!\n", __FUNCTION__, link->linkNumber); + + // return SUCCESS to avoid errors being propogated + return NVL_SUCCESS; + } + switch (mode) { case NVLINK_LINKSTATE_RESET: @@ -1351,6 +1417,15 @@ nvswitch_corelib_set_tx_mode_lr10 return -NVL_UNBOUND_DEVICE; } + if (nvswitch_does_link_need_termination_enabled(device, link)) + { + NVSWITCH_PRINT(device, INFO, + "%s: link #% is connected to a disabled remote end. Skipping TX mode request!\n", __FUNCTION__, link->linkNumber); + + // return SUCCESS to avoid errors being propogated + return NVL_SUCCESS; + } + // check if link is in reset if (nvswitch_is_link_in_reset(device, link)) { @@ -1614,6 +1689,15 @@ nvswitch_corelib_set_rx_mode_lr10 return -NVL_UNBOUND_DEVICE; } + if (nvswitch_does_link_need_termination_enabled(device, link)) + { + NVSWITCH_PRINT(device, INFO, + "%s: link #% is connected to a disabled remote end. Skipping RX mode request!\n", __FUNCTION__, link->linkNumber); + + // return SUCCESS to avoid errors being propogated + return NVL_SUCCESS; + } + // check if link is in reset if (nvswitch_is_link_in_reset(device, link)) { @@ -1824,6 +1908,15 @@ nvswitch_corelib_set_rx_detect_lr10 NvlStatus status; nvswitch_device *device = link->dev->pDevInfo; + if (nvswitch_does_link_need_termination_enabled(device, link)) + { + NVSWITCH_PRINT(device, INFO, + "%s: link #% is connected to a disabled remote end. Skipping RxDet request!\n", __FUNCTION__, link->linkNumber); + + // return SUCCESS to avoid errors being propogated + return NVL_SUCCESS; + } + status = nvswitch_minion_send_command(device, link->linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_TURING_RXDET, 0); @@ -2081,6 +2174,7 @@ nvswitch_setup_link_system_registers_lr10 NvU32 lineRate = 0; NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL; NVSWITCH_BIOS_NVLINK_CONFIG *bios_config; + NvU32 base_entry; bios_config = nvswitch_get_bios_nvlink_config(device); if ((bios_config == NULL) || (bios_config->bit_address == 0)) @@ -2101,14 +2195,17 @@ nvswitch_setup_link_system_registers_lr10 } else { - vbios_link_entry = &bios_config->link_vbios_entry[bios_config->link_base_entry_assigned][link->linkNumber]; + base_entry = bios_config->link_base_entry_assigned; + + vbios_link_entry = &bios_config->link_vbios_entry[base_entry][link->linkNumber]; } + regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL); + // LINE_RATE SYSTEM register if (device->regkeys.nvlink_speed_control != NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_DEFAULT) { - regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, - _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL); lineRate = _nvswitch_get_nvlink_linerate_lr10(device, device->regkeys.nvlink_speed_control); regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, _LINE_RATE, lineRate, regval); @@ -2379,3 +2476,109 @@ nvswitch_reset_and_train_link_lr10 { return NVL_ERR_NOT_IMPLEMENTED; } + +NvBool +nvswitch_does_link_need_termination_enabled_lr10 +( + nvswitch_device *device, + nvlink_link *link +) +{ +#if defined(INCLUDE_NVLINK_LIB) + NvU32 i; + NvU32 physicalId; + lr10_device *chip_device; + + physicalId = nvswitch_read_physical_id(device); + chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); + if (chip_device == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get lr10 chip device!\n", __FUNCTION__); + return NV_FALSE; + } + + // + // If disabledRemoteEndLinkMask has not been cached then + // using the switch's physicalId search nvswitchDisconnetedRemoteLinkMasks + // til a match is found then copy out the linkMask to the chip_device + // Only run this operation if there is a registed device with a reduced + // nvlink config + // + if (chip_device->bDisabledRemoteEndLinkMaskCached == NV_FALSE) + { + chip_device->disabledRemoteEndLinkMask = 0; + if (nvlink_lib_is_registerd_device_with_reduced_config()) + { + for (i = 0; i < NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK; ++i) + { + if (nvswitchDisconnetedRemoteLinkMasks[i].switchPhysicalId == physicalId) + { + chip_device->disabledRemoteEndLinkMask = + nvswitchDisconnetedRemoteLinkMasks[i].linkMask; + break; + } + } + } + + chip_device->bDisabledRemoteEndLinkMaskCached = NV_TRUE; + } + + // return NV_TRUE if the link is inside of disabledRemoteEndLinkMask + return ((BIT64(link->linkNumber) & chip_device->disabledRemoteEndLinkMask) != 0); +#else + return NV_FALSE; +#endif //defined(INCLUDE_NVLINK_LIB) +} + +NvlStatus +nvswitch_link_termination_setup_lr10 +( + nvswitch_device *device, + nvlink_link* link +) +{ + NvlStatus status; + NvU32 linkId = link->linkNumber; + + // Sanity check + if ((link == NULL) || + (linkId >= NVSWITCH_NVLINK_MAX_LINKS) || + !NVSWITCH_IS_LINK_ENG_VALID_LR10(device, NVLDL, linkId)) + { + NVSWITCH_PRINT(device, ERROR, "%s: Link %d is invalid!\n", __FUNCTION__, linkId); + return NVL_BAD_ARGS; + } + + // Sanity check nvlink version + if (link->version != NVLINK_DEVICE_VERSION_30) + { + NVSWITCH_PRINT(device, ERROR, "%s: Link %d: only nvlink version 3.0 can run the termination setup\n", + __FUNCTION__, linkId); + return NVL_BAD_ARGS; + } + + // Send INITPHASE1 to the link + status = nvswitch_minion_send_command_lr10(device, link->linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to send initphase1 to link %d", __FUNCTION__, linkId); + return NVL_ERR_INVALID_STATE; + } + + // Send INITRXTXTERM to the link + nvswitch_minion_send_command_lr10(device, link->linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_INITRXTXTERM, 0); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to send INITRXTXTERM to link %d", __FUNCTION__, linkId); + } + + NVSWITCH_PRINT(device, INFO, + "%s: enabled termination for switchPhysicalId %d link# %d\n", + __FUNCTION__, nvswitch_read_physical_id(device), linkId); + + return NVL_SUCCESS; +} diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index 4349f7185f..1323ea28d2 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -22,6 +22,7 @@ */ #include "common_nvswitch.h" +#include "bios_nvswitch.h" #include "error_nvswitch.h" #include "regkey_nvswitch.h" #include "haldef_nvswitch.h" @@ -3855,7 +3856,7 @@ nvswitch_initialize_device_state_lr10 } else { - NVSWITCH_PRINT(device, ERROR, + NVSWITCH_PRINT(device, WARN, "%s: Skipping SPI init.\n", __FUNCTION__); } @@ -3874,7 +3875,7 @@ nvswitch_initialize_device_state_lr10 } else { - NVSWITCH_PRINT(device, ERROR, + NVSWITCH_PRINT(device, WARN, "%s: Skipping SMBPBI init.\n", __FUNCTION__); } @@ -3981,7 +3982,7 @@ nvswitch_link_lane_reversed_lr10 nvlink_link *link; link = nvswitch_get_link(device, linkId); - if (nvswitch_is_link_in_reset(device, link)) + if ((link == NULL) || nvswitch_is_link_in_reset(device, link)) { return NV_FALSE; } @@ -4579,26 +4580,6 @@ _nvswitch_get_info_revision_minor_ext return (DRF_VAL(_PSMC, _BOOT_42, _MINOR_EXTENDED_REVISION, val)); } -static NvU32 -_nvswitch_get_info_voltage -( - nvswitch_device *device -) -{ - NvU32 voltage = 0; - - return voltage; -} - -static NvBool -_nvswitch_inforom_nvl_supported -( - nvswitch_device *device -) -{ - return NV_FALSE; -} - static NvBool _nvswitch_inforom_bbx_supported ( @@ -4769,7 +4750,7 @@ nvswitch_ctrl_get_info_lr10 p->info[i] = device->switch_pll.vco_freq_khz; break; case NVSWITCH_GET_INFO_INDEX_VOLTAGE_MVOLT: - p->info[i] = _nvswitch_get_info_voltage(device); + retval = -NVL_ERR_NOT_SUPPORTED; break; case NVSWITCH_GET_INFO_INDEX_PHYSICAL_ID: p->info[i] = nvswitch_read_physical_id(device); @@ -6323,7 +6304,6 @@ nvswitch_get_nvlink_ecc_errors_lr10 NvU32 sublinkWidth; link = nvswitch_get_link(device, i); - sublinkWidth = device->hal.nvswitch_get_sublink_width(device, i); if ((link == NULL) || !NVSWITCH_IS_LINK_ENG_VALID_LR10(device, NVLDL, link->linkNumber) || @@ -6332,6 +6312,8 @@ nvswitch_get_nvlink_ecc_errors_lr10 return -NVL_BAD_ARGS; } + sublinkWidth = device->hal.nvswitch_get_sublink_width(device, i); + minion_enabled = nvswitch_is_minion_initialized(device, NVSWITCH_GET_LINK_ENG_INST(device, link->linkNumber, MINION)); @@ -6412,8 +6394,15 @@ nvswitch_ctrl_get_fom_values_lr10 { NvlStatus status; NvU32 statData; + nvlink_link *link; - NVSWITCH_ASSERT(p->linkId < nvswitch_get_num_links(device)); + link = nvswitch_get_link(device, p->linkId); + if (link == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: link #%d invalid\n", + __FUNCTION__, p->linkId); + return -NVL_BAD_ARGS; + } status = nvswitch_minion_get_dl_status(device, p->linkId, NV_NVLSTAT_TR16, 0, &statData); @@ -6728,6 +6717,25 @@ nvswitch_is_spi_supported_lr10 return NV_TRUE; } +NvBool +nvswitch_is_bios_supported_lr10 +( + nvswitch_device *device +) +{ + return nvswitch_is_spi_supported(device); +} + +NvlStatus +nvswitch_get_bios_size_lr10 +( + nvswitch_device *device, + NvU32 *pSize +) +{ + return nvswitch_bios_read_size(device, pSize); +} + NvBool nvswitch_is_smbpbi_supported_lr10 ( @@ -7599,10 +7607,10 @@ nvswitch_parse_bios_image_lr10 NV_STATUS status = NV_OK; // check if spi is supported - if (!nvswitch_is_spi_supported(device)) + if (!nvswitch_is_bios_supported(device)) { NVSWITCH_PRINT(device, ERROR, - "%s: SPI is not supported\n", + "%s: BIOS is not supported\n", __FUNCTION__); return -NVL_ERR_NOT_SUPPORTED; } @@ -7659,7 +7667,7 @@ nvswitch_ctrl_get_sw_info_lr10 switch (p->index[i]) { case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_NVL_SUPPORTED: - p->info[i] = (NvU32)_nvswitch_inforom_nvl_supported(device); + p->info[i] = NV_TRUE; break; case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_BBX_SUPPORTED: p->info[i] = (NvU32)_nvswitch_inforom_bbx_supported(device); diff --git a/src/common/nvswitch/kernel/lr10/therm_lr10.c b/src/common/nvswitch/kernel/lr10/therm_lr10.c index 6e8fc11e4a..1bd9f922e7 100644 --- a/src/common/nvswitch/kernel/lr10/therm_lr10.c +++ b/src/common/nvswitch/kernel/lr10/therm_lr10.c @@ -314,3 +314,13 @@ nvswitch_ctrl_therm_read_voltage_lr10 return -NVL_ERR_NOT_SUPPORTED; } +NvlStatus +nvswitch_ctrl_therm_read_power_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_POWER_PARAMS *info +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c index 3f99ba5f65..5800ccc792 100644 --- a/src/common/nvswitch/kernel/ls10/intr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,9 +24,11 @@ #include "common_nvswitch.h" #include "intr_nvswitch.h" #include "regkey_nvswitch.h" +#include "soe/soe_nvswitch.h" #include "ls10/ls10.h" #include "ls10/minion_ls10.h" +#include "ls10/soe_ls10.h" #include "nvswitch/ls10/dev_ctrl_ip.h" #include "nvswitch/ls10/dev_pri_masterstation_ip.h" @@ -59,6 +61,8 @@ #include "nvswitch/ls10/dev_ctrl_ip_addendum.h" +static void _nvswitch_create_deferred_link_errors_task_ls10(nvswitch_device *device, NvU32 nvlipt_instance, NvU32 link); + static void _nvswitch_construct_ecc_error_event_ls10 ( @@ -113,7 +117,7 @@ _nvswitch_initialize_minion_interrupts intrEn = FLD_SET_DRF_NUM(_MINION, _MINION_INTR_STALL_EN, _LINK, localDiscoveredLinks, intrEn); - { + { // Disable interrupts only if explicitly requested to. Default to enable. if (device->regkeys.minion_intr != NV_SWITCH_REGKEY_MINION_INTERRUPTS_DISABLE) { @@ -258,7 +262,7 @@ _nvswitch_initialize_route_interrupts DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _EXTMCRID_ECC_LIMIT_ERR, _ENABLE) | DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _RAM_ECC_LIMIT_ERR, _ENABLE) | DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _INVALID_MCRID_ERR, _ENABLE); - // NOTE: _MC_TRIGGER_ERR is debug-use only + // NOTE: _MC_TRIGGER_ERR is debug-use only } static void @@ -358,11 +362,11 @@ _nvswitch_initialize_egress_interrupts DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, _ENABLE); chip_device->intr_mask.egress[1].nonfatal = - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, _ENABLE) | - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDSGT_ECC_LIMIT_ERR, _ENABLE) | - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDBUF_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDSGT_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDBUF_ECC_LIMIT_ERR, _ENABLE) | DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, _ENABLE) | DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, _ENABLE) | DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_PARITY_ERR, _ENABLE) | @@ -456,8 +460,8 @@ _nvswitch_initialize_nport_interrupts_ls10 nvswitch_device *device ) { -// Moving this L2 register access to SOE. Refer bug #3747687 -#if 0 +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 NvU32 val; val = @@ -516,7 +520,7 @@ _nvswitch_initialize_nxbar_interrupts_ls10 DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, 1) | DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CDT_PARITY_ERROR, 1); -// Moving this L2 register access to SOE. Refer bug #3747687 +// Moving this L2 register access to SOE. Refer bug #3747687 #if 0 NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, report_fatal); #endif // 0 @@ -532,7 +536,7 @@ _nvswitch_initialize_nxbar_interrupts_ls10 * IRQMASK is used to read in mask of interrupts * IRQDEST is used to read in enabled interrupts that are routed to the HOST * - * IRQSTAT & IRQMASK gives the pending interrupting on this minion + * IRQSTAT & IRQMASK gives the pending interrupting on this minion * * @param[in] device MINION on this device * @param[in] instance MINION instance @@ -561,7 +565,7 @@ nvswitch_minion_service_falcon_interrupts_ls10 return -NVL_NOT_FOUND; } - unhandled = pending; + unhandled = pending; bit = DRF_NUM(_CMINION_FALCON, _IRQSTAT, _WDTMR, 1); if (nvswitch_test_flags(pending, bit)) @@ -761,7 +765,7 @@ _nvswitch_service_priv_ring_ls10 if (pending != 0) { - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_PRIV_ERROR, + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_PRIV_ERROR, "Fatal, Unexpected PRI error\n"); NVSWITCH_LOG_FATAL_DATA(device, _HW, _HW_HOST_PRIV_ERROR, 2, 0, NV_FALSE, &pending); @@ -821,7 +825,7 @@ _nvswitch_collect_nport_error_info_ls10 } while (register_start <= register_end); - + *idx = i; return NVL_SUCCESS; } @@ -1257,8 +1261,16 @@ _nvswitch_service_route_fatal_ls10 // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. if (device->link[link].fatal_error_occurred) { - NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_FATAL_REPORT_EN_0, + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, + report.raw_enable ^ pending, RM_SOE_CORE_NPORT_ROUTE_INTERRUPT); + } + else + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_FATAL_REPORT_EN_0, report.raw_enable ^ pending); + } } if (report.raw_first & report.mask) @@ -1728,8 +1740,16 @@ _nvswitch_service_ingress_fatal_ls10 // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. if (device->link[link].fatal_error_occurred) { - NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FATAL_REPORT_EN_0, + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, + report.raw_enable ^ pending, RM_SOE_CORE_NPORT_INGRESS_INTERRUPT); + } + else + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FATAL_REPORT_EN_0, report.raw_enable ^ pending); + } } if (report.raw_first & report.mask) @@ -2177,7 +2197,7 @@ _nvswitch_service_ingress_nonfatal_ls10 NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FIRST_1, report.raw_first & report.mask); } - + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_0, pending_0); NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_1, pending_1); @@ -2496,8 +2516,16 @@ _nvswitch_service_tstate_fatal_ls10 // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. if (device->link[link].fatal_error_occurred) { - NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_FATAL_REPORT_EN_0, + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, + report.raw_enable ^ pending, RM_SOE_CORE_NPORT_TSTATE_INTERRUPT); + } + else + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_FATAL_REPORT_EN_0, report.raw_enable ^ pending); + } } if (report.raw_first & report.mask) @@ -3144,8 +3172,16 @@ _nvswitch_service_egress_fatal_ls10 // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. if (device->link[link].fatal_error_occurred) { - NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_0, + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, + report.raw_enable ^ pending, RM_SOE_CORE_NPORT_EGRESS_0_INTERRUPT); + } + else + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_0, report.raw_enable ^ pending); + } } if (report.raw_first & report.mask) @@ -3267,8 +3303,16 @@ _nvswitch_service_egress_fatal_ls10 // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. if (device->link[link].fatal_error_occurred) { - NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_1, - report.raw_enable ^ pending); + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, + report.raw_enable ^ pending, RM_SOE_CORE_NPORT_EGRESS_1_INTERRUPT); + } + else + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_1, + report.raw_enable ^ pending); + } } if (report.raw_first & report.mask) @@ -3491,8 +3535,16 @@ _nvswitch_service_sourcetrack_fatal_ls10 // if (device->link[link].fatal_error_occurred) { - NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, + report.raw_enable ^ pending, RM_SOE_CORE_NPORT_SOURCETRACK_INTERRUPT); + } + else + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, report.raw_enable ^ pending); + } } if (report.raw_first & report.mask) @@ -3775,8 +3827,16 @@ _nvswitch_service_multicast_fatal_ls10 // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. if (device->link[link].fatal_error_occurred) { - NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, + report.raw_enable ^ pending, RM_SOE_CORE_NPORT_MULTICAST_INTERRUPT); + } + else + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, report.raw_enable ^ pending); + } } if (report.raw_first & report.mask) @@ -4068,8 +4128,16 @@ _nvswitch_service_reduction_fatal_ls10 // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. if (device->link[link].fatal_error_occurred) { - NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, + report.raw_enable ^ pending, RM_SOE_CORE_NPORT_REDUCTION_INTERRUPT); + } + else + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, report.raw_enable ^ pending); + } } if (report.raw_first & report.mask) @@ -4131,13 +4199,13 @@ _nvswitch_service_npg_fatal_ls10 NvU32 link; pending = NVSWITCH_ENG_RD32(device, NPG, , npg, _NPG, _NPG_INTERRUPT_STATUS); - + if (pending == 0) { return -NVL_NOT_FOUND; } - mask = + mask = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV0_INT_STATUS, _FATAL) | DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV1_INT_STATUS, _FATAL) | DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV2_INT_STATUS, _FATAL) | @@ -4234,7 +4302,7 @@ _nvswitch_service_npg_nonfatal_ls10 return -NVL_NOT_FOUND; } - mask = + mask = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV0_INT_STATUS, _NONFATAL) | DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV1_INT_STATUS, _NONFATAL) | DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV2_INT_STATUS, _NONFATAL) | @@ -4286,10 +4354,11 @@ static NvlStatus _nvswitch_service_nvldl_fatal_ls10 ( nvswitch_device *device, - NvU32 nvlipt_instance + NvU32 nvlipt_instance, + NvU64 intrLinkMask ) { - NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask, runtimeErrorMask = 0; + NvU64 enabledLinkMask, localLinkMask, localIntrLinkMask, runtimeErrorMask = 0; NvU32 i; nvlink_link *link; NvU32 clocksMask = NVSWITCH_PER_LINK_CLOCK_SET(RXCLK) | NVSWITCH_PER_LINK_CLOCK_SET(TXCLK); @@ -4297,11 +4366,22 @@ _nvswitch_service_nvldl_fatal_ls10 NVSWITCH_LINK_TRAINING_ERROR_INFO linkTrainingErrorInfo = { 0 }; NVSWITCH_LINK_RUNTIME_ERROR_INFO linkRuntimeErrorInfo = { 0 }; + // + // The passed in interruptLinkMask should contain a link that is part of the + // given nvlipt instance + // enabledLinkMask = nvswitch_get_enabled_link_mask(device); localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance); - localEnabledLinkMask = enabledLinkMask & localLinkMask; + localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask; - FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask) + if (localIntrLinkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + return -NVL_BAD_ARGS; + } + + FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask) { link = nvswitch_get_link(device, i); if (link == NULL) @@ -4343,7 +4423,7 @@ _nvswitch_service_nvldl_fatal_ls10 NVSWITCH_PRINT(device, ERROR, "%s: NVLDL[0x%x, 0x%llx]: Unable to send Runtime Error bitmask: 0x%llx,\n", __FUNCTION__, - nvlipt_instance, localLinkMask, + nvlipt_instance, localIntrLinkMask, runtimeErrorMask); } @@ -4990,19 +5070,31 @@ NvlStatus _nvswitch_service_nvltlc_fatal_ls10 ( nvswitch_device *device, - NvU32 nvlipt_instance + NvU32 nvlipt_instance, + NvU64 intrLinkMask ) { - NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask; + NvU64 enabledLinkMask, localLinkMask, localIntrLinkMask; NvU32 i; nvlink_link *link; NvlStatus status = -NVL_MORE_PROCESSING_REQUIRED; + // + // The passed in interruptLinkMask should contain a link that is part of the + // given nvlipt instance + // enabledLinkMask = nvswitch_get_enabled_link_mask(device); localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance); - localEnabledLinkMask = enabledLinkMask & localLinkMask; + localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask; - FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask) + if (localIntrLinkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + return -NVL_BAD_ARGS; + } + + FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask) { link = nvswitch_get_link(device, i); if (link == NULL) @@ -5024,7 +5116,7 @@ _nvswitch_service_nvltlc_fatal_ls10 // as the IP's registers are off // if (nvswitch_is_link_in_reset(device, link) || - !nvswitch_are_link_clocks_on_ls10(device, link,NVSWITCH_PER_LINK_CLOCK_SET(NCISOCCLK))); + !nvswitch_are_link_clocks_on_ls10(device, link,NVSWITCH_PER_LINK_CLOCK_SET(NCISOCCLK))) { continue; } @@ -5448,6 +5540,127 @@ _nvswitch_emit_link_errors_nvldl_fatal_link_ls10 error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_UP_FATAL; nvswitch_inforom_nvlink_log_error_event(device, &error_event); } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE); + error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } +} + +static void +_nvswitch_emit_link_errors_minion_fatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 regData; + NvU32 enabledLinks; + NvU32 localLinkIdx = NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + NvU32 bit = BIT(localLinkIdx); + + if (!chip_device->deferredLinkErrors[link].fatalIntrMask.minionLinkIntr.bPending) + { + return; + } + + // Grab the cached interrupt data + regData = chip_device->deferredLinkErrors[link].fatalIntrMask.minionLinkIntr.regData; + + // get all possible interrupting links associated with this minion + report.raw_enable = link; + report.raw_pending = report.raw_enable; + report.mask = report.raw_enable; + report.data[0] = regData; + + switch(DRF_VAL(_MINION, _NVLINK_LINK_INTR, _CODE, regData)) + { + case NV_MINION_NVLINK_LINK_INTR_CODE_NA: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link NA interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link DLCMDFAULT interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link NOINIT interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_LOCAL_CONFIG_ERR: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link Local-Config-Error interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link Negotiation Config Err Interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link BADINIT interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link PMFAIL interrupt", NV_FALSE); + break; + default: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Interrupt code unknown", NV_FALSE); + } + + // Fatal error was hit so disable the interrupt + regData = NVSWITCH_MINION_RD32_LS10(device, nvlipt_instance, _MINION, _MINION_INTR_STALL_EN); + enabledLinks = DRF_VAL(_MINION, _MINION_INTR_STALL_EN, _LINK, regData); + enabledLinks &= ~bit; + regData = DRF_NUM(_MINION, _MINION_INTR_STALL_EN, _LINK, enabledLinks); + NVSWITCH_MINION_LINK_WR32_LS10(device, link, _MINION, _MINION_INTR_STALL_EN, regData); +} + +static void +_nvswitch_emit_link_errors_minion_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 regData; + NvU32 localLinkIdx = NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + NvU32 bit = BIT(localLinkIdx); + + if (!chip_device->deferredLinkErrors[link].nonFatalIntrMask.minionLinkIntr.bPending) + { + return; + } + + // read in the enaled minion interrupts on this minion + regData = NVSWITCH_MINION_RD32_LS10(device, nvlipt_instance, _MINION, _MINION_INTR_STALL_EN); + + // Grab the cached interrupt data + regData = chip_device->deferredLinkErrors[link].nonFatalIntrMask.minionLinkIntr.regData; + + // get all possible interrupting links associated with this minion + report.raw_enable = link; + report.raw_pending = report.raw_enable; + report.mask = report.raw_enable; + report.data[0] = regData; + + switch(DRF_VAL(_MINION, _NVLINK_LINK_INTR, _CODE, regData)) + { + case NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ: + NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link DLREQ interrupt"); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED: + NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link PMDISABLED interrupt"); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link DLCMDFAULT interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ: + NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link TLREQ interrupt"); + break; + } + } static void @@ -5459,7 +5672,7 @@ _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10 { ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; - NvU32 pending, bit; + NvU32 pending, bit, reg; // Only enabled link errors are deffered pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl; @@ -5470,7 +5683,28 @@ _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10 bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 1); if (nvswitch_test_flags(pending, bit)) { - NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate"); + // Disable further interrupts + nvlink_link *nvlink = nvswitch_get_link(device, link); + if (nvlink == NULL) + { + // If we get here, it is a bug. Disable interrupt and assert. + reg = NVSWITCH_LINK_RD32_LS10(device, link, NVLDL, _NVLDL_TOP, _INTR_NONSTALL_EN); + reg = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0, reg); + NVSWITCH_LINK_WR32_LS10(device, link, NVLDL, _NVLDL_TOP, _INTR_NONSTALL_EN, reg); + NVSWITCH_ASSERT(nvlink != NULL); + } + else + { + nvlink->errorThreshold.bInterruptTrigerred = NV_TRUE; + nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink, NV_FALSE); + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate"); + } + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_CRC_COUNTER, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_CRC_COUNTER, "RX CRC Error Rate"); } } @@ -5558,6 +5792,9 @@ _nvswitch_emit_deferred_link_errors_ls10 _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10(device, link); _nvswitch_emit_link_errors_nvltlc_rx_lnk_nonfatal_1_ls10(device, nvlipt_instance, link); _nvswitch_emit_link_errors_nvlipt_lnk_nonfatal_ls10(device, nvlipt_instance, link); + _nvswitch_emit_link_errors_minion_fatal_ls10(device, nvlipt_instance, link); + _nvswitch_emit_link_errors_minion_nonfatal_ls10(device, nvlipt_instance, link); + } static void @@ -5582,11 +5819,11 @@ _nvswitch_deferred_link_state_check_ls10 void *fn_args ) { - NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams = + NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams = (NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS*)fn_args; NvU32 nvlipt_instance = pErrorReportParams->nvlipt_instance; NvU32 link = pErrorReportParams->link; - ls10_device *chip_device; + ls10_device *chip_device; nvlink_link *pLink; NvU64 linkState; @@ -5677,13 +5914,13 @@ _nvswitch_deferred_link_errors_check_ls10 NvU32 nvlipt_instance = pErrorReportParams->nvlipt_instance; NvU32 link = pErrorReportParams->link; ls10_device *chip_device; - NvU32 pending, bit; + NvU32 pending; chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); pending = chip_device->deferredLinkErrors[link].fatalIntrMask.dl; - bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); - if (nvswitch_test_flags(pending, bit)) + if (FLD_TEST_DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1U, pending) || + FLD_TEST_DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1U, pending) ) { nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); } @@ -5726,10 +5963,10 @@ _nvswitch_create_deferred_link_errors_task_ls10 pErrorReportParams->nvlipt_instance = nvlipt_instance; pErrorReportParams->link = link; - status = nvswitch_task_create_args(device, (void*)pErrorReportParams, + status = nvswitch_task_create_args(device, (void*)pErrorReportParams, &_nvswitch_deferred_link_errors_check_ls10, NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS, - NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE | + NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE | NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS); } @@ -5790,7 +6027,7 @@ _nvswitch_service_nvldl_nonfatal_link_ls10 if (nvswitch_test_flags(pending, bit)) { chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl |= bit; - _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); + _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); nvswitch_clear_flags(&unhandled, bit); } @@ -5811,7 +6048,9 @@ _nvswitch_service_nvldl_nonfatal_link_ls10 bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_CRC_COUNTER, 1); if (nvswitch_test_flags(pending, bit)) { - NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_CRC_COUNTER, "RX CRC Counter"); + + chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl |= bit; + _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); nvswitch_clear_flags(&unhandled, bit); // @@ -5843,20 +6082,33 @@ static NvlStatus _nvswitch_service_nvldl_nonfatal_ls10 ( nvswitch_device *device, - NvU32 nvlipt_instance + NvU32 nvlipt_instance, + NvU64 intrLinkMask ) { - NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask; + NvU64 localLinkMask, enabledLinkMask, localIntrLinkMask; NvU32 i; nvlink_link *link; NvlStatus status; NvlStatus return_status = -NVL_NOT_FOUND; NvU32 clocksMask = NVSWITCH_PER_LINK_CLOCK_SET(RXCLK) | NVSWITCH_PER_LINK_CLOCK_SET(TXCLK); - enabledLinkMask = nvswitch_get_enabled_link_mask(device); + + // + // The passed in interruptLinkMask should contain a link that is part of the + // given nvlipt instance + // localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance); - localEnabledLinkMask = enabledLinkMask & localLinkMask; + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask; + + if (localIntrLinkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + return -NVL_BAD_ARGS; + } - FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask) + FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask) { link = nvswitch_get_link(device, i); if (link == NULL) @@ -6200,7 +6452,7 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL; nvswitch_inforom_nvlink_log_error_event(device, &error_event); } - } + } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC3, 1); if (nvswitch_test_flags(pending, bit)) @@ -6288,20 +6540,28 @@ static NvlStatus _nvswitch_service_nvltlc_nonfatal_ls10 ( nvswitch_device *device, - NvU32 nvlipt_instance + NvU32 nvlipt_instance, + NvU64 intrLinkMask ) { - NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask; + NvU64 localLinkMask, enabledLinkMask, localIntrLinkMask; NvU32 i; nvlink_link *link; NvlStatus status; NvlStatus return_status = NVL_SUCCESS; - enabledLinkMask = nvswitch_get_enabled_link_mask(device); localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance); - localEnabledLinkMask = enabledLinkMask & localLinkMask; + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask; + + if (localIntrLinkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + return -NVL_BAD_ARGS; + } - FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask) + FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask) { link = nvswitch_get_link(device, i); if (link == NULL) @@ -6378,6 +6638,13 @@ _nvswitch_service_nvlipt_lnk_status_ls10 bit = DRF_NUM(_NVLIPT_LNK, _INTR_STATUS, _LINKSTATEREQUESTREADYSET, 1); if (nvswitch_test_flags(pending, bit)) { + link = nvswitch_get_link(device, link_id); + if (link == NULL) + { + // If we get here, it's a bug. Assert, then let callers detect unhandled IRQ. + NVSWITCH_ASSERT(link != NULL); + } + nvswitch_clear_flags(&unhandled, bit); if(nvswitch_corelib_get_dl_link_mode_ls10(link, &mode) != NVL_SUCCESS) { @@ -6402,6 +6669,17 @@ _nvswitch_service_nvlipt_lnk_status_ls10 // nvswitch_corelib_training_complete_ls10(link); nvswitch_init_buffer_ready(device, link, NV_TRUE); + link->bRxDetected = NV_TRUE; + } + else if (mode == NVLINK_LINKSTATE_FAULT) + { + // + // If we are here then a previous state transition caused + // the link to FAULT as there is no TL Link state requests + // that explicitly transitions a link to fault. If that is the + // case, set the DL interrupts so any errors can be handled + // + nvswitch_set_dlpl_interrupts_ls10(link); } } @@ -6429,7 +6707,7 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 { ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); nvlink_link *link_info = nvswitch_get_link(device, link); - NvU32 lnkStateRequest, lnkStateStatus; + NvU32 lnkStateRequest, linkState; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; @@ -6465,26 +6743,21 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 if (nvswitch_test_flags(pending, bit)) { // - // Read back LINK_STATE_REQUESTS and LINK_STATE_STATUS registers - // If request == ACTIVE, LINK_STATE_STATUS == ACTIVE_PENDING, request == ERROR - // and there is a pending FAULT_UP interrupt then redo reset_and_drain since the - // last try failed - // + // Read back LINK_STATE_REQUESTS and TOP_LINK_STATE registers + // If request == ACTIVE and TOP_LINK_STATE == FAULT there is a pending + // fault on training so re-run reset_and_drain // Mark that the defered link error mechanism as seeing a reset_and_train re-try so // the deferred task needs to re-create itself instead of continuing with the linkstate // checks // - lnkStateStatus = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber, NVLIPT_LNK, - _NVLIPT_LNK, _CTRL_LINK_STATE_STATUS); + linkState = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber, NVLDL, + _NVLDL, _TOP_LINK_STATE); - lnkStateRequest = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber, + lnkStateRequest = NVSWITCH_LINK_RD32_LS10(device, link, NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_REQUEST); - if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, _ACTIVE, lnkStateRequest) && - !(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _STATUS, _REQUEST_SUCCESSFUL, lnkStateRequest) || - FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _STATUS, _INIT, lnkStateRequest))&& - FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, _ACTIVE_PENDING, lnkStateStatus) && - DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1) & chip_device->deferredLinkErrors[link].fatalIntrMask.dl) + if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, _ACTIVE, lnkStateRequest) && + linkState == NV_NVLDL_TOP_LINK_STATE_STATE_FAULT) { chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_TRUE; device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link)); @@ -6563,77 +6836,81 @@ static NvlStatus _nvswitch_service_nvlipt_link_nonfatal_ls10 ( nvswitch_device *device, - NvU32 instance + NvU32 instance, + NvU64 intrLinkMask ) { - NvU32 i, globalLink, bit, intrLink; - NvU32 interruptingLinks = 0; - NvU32 lnkStatusChangeLinks = 0; - NvlStatus status; - NvU64 link_enable_mask; - - link_enable_mask = ((NvU64)device->regkeys.link_enable_mask2 << 32 | - (NvU64)device->regkeys.link_enable_mask); - for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + NvU32 i, intrLink; + NvU64 localLinkMask, enabledLinkMask, localIntrLinkMask; + NvU64 interruptingLinks = 0; + NvU64 lnkStatusChangeLinks = 0; + NvlStatus status = NVL_SUCCESS; + NvlStatus retStatus = NVL_SUCCESS; + + // + // The passed in interruptLinkMask should contain a link that is part of the + // given nvlipt instance + // + localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(instance); + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask; + + if (localIntrLinkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + return -NVL_BAD_ARGS; + } + + + FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask) { - globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; - if ((NVBIT64(globalLink) & link_enable_mask) == 0) + if (NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT) != instance) { - continue; + NVSWITCH_ASSERT(0); + break; } - intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); + + intrLink = NVSWITCH_LINK_RD32(device, i, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); if(intrLink) { - interruptingLinks |= NVBIT(i); + interruptingLinks |= NVBIT64(i); } - - intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS); + + intrLink = NVSWITCH_LINK_RD32(device, i, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS); if(intrLink) { - lnkStatusChangeLinks |= NVBIT(i); + lnkStatusChangeLinks |= NVBIT64(i); } } + FOR_EACH_INDEX_IN_MASK_END; + - if(lnkStatusChangeLinks) + FOR_EACH_INDEX_IN_MASK(64, i, lnkStatusChangeLinks) { - for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + + if(_nvswitch_service_nvlipt_lnk_status_ls10(device, instance, i) != NVL_SUCCESS) { - bit = NVBIT(i); - globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; - if (nvswitch_test_flags(lnkStatusChangeLinks, bit)) - { - if( _nvswitch_service_nvlipt_lnk_status_ls10(device, instance, globalLink) != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, WARN, "%s: Could not process nvlipt link status interrupt. Continuing. LinkId %d\n", - __FUNCTION__, globalLink); - } - } + NVSWITCH_PRINT(device, WARN, "%s: Could not process nvlipt link status interrupt. Continuing. LinkId %d\n", + __FUNCTION__, i); } } + FOR_EACH_INDEX_IN_MASK_END; - if(interruptingLinks) + FOR_EACH_INDEX_IN_MASK(64, i, interruptingLinks) { - for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + + status = _nvswitch_service_nvlipt_lnk_nonfatal_ls10(device, instance, i); + if (status != NVL_SUCCESS && status != -NVL_NOT_FOUND) { - bit = NVBIT(i); - globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; - if (nvswitch_test_flags(interruptingLinks, bit)) - { - status = _nvswitch_service_nvlipt_lnk_nonfatal_ls10(device, instance, globalLink); - if (status != NVL_SUCCESS && status != -NVL_NOT_FOUND) - { - return -NVL_MORE_PROCESSING_REQUIRED; - } - } + retStatus = -NVL_MORE_PROCESSING_REQUIRED; } - return NVL_SUCCESS; - } - else - { - return -NVL_NOT_FOUND; } + FOR_EACH_INDEX_IN_MASK_END; + + return retStatus; } @@ -6659,7 +6936,7 @@ _nvswitch_service_minion_fatal_ls10 return -NVL_NOT_FOUND; } - unhandled = pending; + unhandled = pending; bit = DRF_NUM(_MINION, _MINION_INTR, _FALCON_STALL, 0x1); if (nvswitch_test_flags(pending, bit)) @@ -6706,11 +6983,27 @@ _nvswitch_service_nvlw_nonfatal_ls10 ) { NvlStatus status[3]; + NvU32 reg; + NvU64 intrLinkMask = 0; - // TODO: @achaudhry invert handling so nvlipt_lnk is first - status[0] = _nvswitch_service_nvldl_nonfatal_ls10(device, instance); - status[1] = _nvswitch_service_nvltlc_nonfatal_ls10(device, instance); - status[2] = _nvswitch_service_nvlipt_link_nonfatal_ls10(device, instance); + reg = NVSWITCH_ENG_RD32_LS10(device, NVLW, instance, _NVLW, _TOP_INTR_1_STATUS); + intrLinkMask = DRF_VAL(_NVLW, _TOP_INTR_1_STATUS, _LINK, reg); + + // + // Shift the mask of interrupting links from the local to the + // NVLW instance to a global mask + // + intrLinkMask = intrLinkMask << (NVSWITCH_LINKS_PER_NVLW_LS10*instance); + + // If there is no pending link interrupts then there is nothing to service + if (intrLinkMask == 0) + { + return NVL_SUCCESS; + } + + status[0] = _nvswitch_service_nvldl_nonfatal_ls10(device, instance, intrLinkMask); + status[1] = _nvswitch_service_nvltlc_nonfatal_ls10(device, instance, intrLinkMask); + status[2] = _nvswitch_service_nvlipt_link_nonfatal_ls10(device, instance, intrLinkMask); if ((status[0] != NVL_SUCCESS) && (status[0] != -NVL_NOT_FOUND) && (status[1] != NVL_SUCCESS) && (status[1] != -NVL_NOT_FOUND) && @@ -6722,7 +7015,6 @@ _nvswitch_service_nvlw_nonfatal_ls10 return NVL_SUCCESS; } -#if 0 static NvlStatus _nvswitch_service_soe_fatal_ls10 ( @@ -6730,14 +7022,13 @@ _nvswitch_service_soe_fatal_ls10 ) { // We only support 1 SOE as of LS10. - if (soeService_HAL(device, (PSOE)device->pSoe) != 0) + if (soeService_HAL(device, (PSOE)device->pSoe) != NVL_SUCCESS) { return -NVL_MORE_PROCESSING_REQUIRED; } return NVL_SUCCESS; } -#endif //0 static NvlStatus _nvswitch_service_nvlipt_lnk_fatal_ls10 @@ -6832,45 +7123,44 @@ static NvlStatus _nvswitch_service_nvlipt_link_fatal_ls10 ( nvswitch_device *device, - NvU32 instance + NvU32 instance, + NvU64 intrLinkMask ) { - NvU32 i, globalLink, bit, intrLink; - NvU32 interruptingLinks = 0; - - //read in error status of current link - for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) - { - globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; + NvU32 i, intrLink; + NvU64 localLinkMask, enabledLinkMask, localIntrLinkMask; + NvlStatus status = NVL_SUCCESS; - intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); + // + // The passed in interruptLinkMask should contain a link that is part of the + // given nvlipt instance + // + localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(instance); + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + localIntrLinkMask = localLinkMask & intrLinkMask & enabledLinkMask; - if(intrLink) - { - interruptingLinks |= NVBIT(i); - } + if (localIntrLinkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: Bad link mask provided for link interrupt servicing!\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + return -NVL_BAD_ARGS; } - if(interruptingLinks) + // read in error status of current link + FOR_EACH_INDEX_IN_MASK(64, i, localIntrLinkMask) { - for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + intrLink = NVSWITCH_LINK_RD32(device, i, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); + if (intrLink != 0) { - bit = NVBIT(i); - globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; - if (nvswitch_test_flags(interruptingLinks, bit)) + if( _nvswitch_service_nvlipt_lnk_fatal_ls10(device, instance, i) != NVL_SUCCESS) { - if( _nvswitch_service_nvlipt_lnk_fatal_ls10(device, instance, globalLink) != NVL_SUCCESS) - { - return -NVL_MORE_PROCESSING_REQUIRED; - } + status = -NVL_MORE_PROCESSING_REQUIRED; } } - return NVL_SUCCESS; - } - else - { - return -NVL_NOT_FOUND; } + FOR_EACH_INDEX_IN_MASK_END; + + return status; } static NvlStatus @@ -6881,21 +7171,46 @@ _nvswitch_service_nvlw_fatal_ls10 ) { NvlStatus status[6]; + NvU64 intrLinkMask = 0; + NvU32 reg; + + reg = NVSWITCH_ENG_RD32_LS10(device, NVLW, instance, _NVLW, _TOP_INTR_0_STATUS); + intrLinkMask = DRF_VAL(_NVLW, _TOP_INTR_0_STATUS, _LINK, reg); + + // + // Shift the mask of interrupting links from the local to the + // NVLW instance to a global mask + // + intrLinkMask = intrLinkMask << (NVSWITCH_LINKS_PER_NVLW_LS10*instance); status[0] = device->hal.nvswitch_service_minion_link(device, instance); - status[1] = _nvswitch_service_nvldl_fatal_ls10(device, instance); - status[2] = _nvswitch_service_nvltlc_fatal_ls10(device, instance); - status[3] = _nvswitch_service_minion_fatal_ls10(device, instance); - status[4] = _nvswitch_service_nvlipt_common_fatal_ls10(device, instance); - status[5] = _nvswitch_service_nvlipt_link_fatal_ls10(device, instance); + status[1] = _nvswitch_service_minion_fatal_ls10(device, instance); + status[2] = _nvswitch_service_nvlipt_common_fatal_ls10(device, instance); + // + // If there is a pending link interrupt on this nvlw instance then service + // those interrupts in the handlers below. Otherwise, mark the status's + // as success as there is nothing to service + // + if (intrLinkMask != 0) + { + status[3] = _nvswitch_service_nvldl_fatal_ls10(device, instance, intrLinkMask); + status[4] = _nvswitch_service_nvltlc_fatal_ls10(device, instance, intrLinkMask); + status[5] = _nvswitch_service_nvlipt_link_fatal_ls10(device, instance, intrLinkMask); + } + else + { + status[3] = NVL_SUCCESS; + status[4] = NVL_SUCCESS; + status[5] = NVL_SUCCESS; + } - if (status[0] != NVL_SUCCESS && - status[1] != NVL_SUCCESS && - status[2] != NVL_SUCCESS && - status[3] != NVL_SUCCESS && - status[4] != NVL_SUCCESS && - status[5] != NVL_SUCCESS) + if (status[0] != NVL_SUCCESS && status[0] != -NVL_NOT_FOUND && + status[1] != NVL_SUCCESS && status[1] != -NVL_NOT_FOUND && + status[2] != NVL_SUCCESS && status[2] != -NVL_NOT_FOUND && + status[3] != NVL_SUCCESS && status[3] != -NVL_NOT_FOUND && + status[4] != NVL_SUCCESS && status[4] != -NVL_NOT_FOUND && + status[5] != NVL_SUCCESS && status[5] != -NVL_NOT_FOUND) { return -NVL_MORE_PROCESSING_REQUIRED; } @@ -6931,6 +7246,7 @@ nvswitch_lib_enable_interrupts_ls10 DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _SEC0_INTR0_0, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1)); @@ -6965,6 +7281,7 @@ nvswitch_lib_disable_interrupts_ls10 DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _SEC0_INTR0_0, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1) | DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1)); @@ -7192,7 +7509,7 @@ nvswitch_lib_service_interrupts_ls10 val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_UNITS); if (val != 0) { - NVSWITCH_PRINT(device, INFO, "%s: UNIT interrupts pending = 0x%x\n", + NVSWITCH_PRINT(device, MMIO, "%s: UNIT interrupts pending = 0x%x\n", __FUNCTION__, val); NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_UNITS_IDX), val); @@ -7236,6 +7553,19 @@ nvswitch_lib_service_interrupts_ls10 return_status = status; } } + if (!IS_RTLSIM(device) && !IS_FMODEL(device)) + { + if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _SEC0_INTR0_0, 1, val)) + { + status = _nvswitch_service_soe_fatal_ls10(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Problem servicing SOE", + __FUNCTION__); + return_status = status; + } + } + } } // step 4 -- retrigger engine interrupts @@ -7312,7 +7642,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); NvU32 pending, bit, unhandled; - NvBool bSkipIntrClear = NV_FALSE; + NvU32 dlDeferredIntrLinkMask = 0; + NvBool bRequireResetAndDrain = NV_FALSE; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; INFOROM_NVLINK_ERROR_EVENT error_event; @@ -7377,15 +7708,6 @@ nvswitch_service_nvldl_fatal_link_ls10 nvswitch_inforom_nvlink_log_error_event(device, &error_event); } - bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); - if (nvswitch_test_flags(pending, bit)) - { - NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE); - nvswitch_clear_flags(&unhandled, bit); - error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL; - nvswitch_inforom_nvlink_log_error_event(device, &error_event); - } - bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_PROTOCOL, 1); if (nvswitch_test_flags(pending, bit)) { @@ -7423,22 +7745,34 @@ nvswitch_service_nvldl_fatal_link_ls10 } // - // Note: LTSSM_FAULT_UP must be the last interrupt serviced in the NVLDL + // Note: LTSSM_FAULT_{UP/DOWN} must be the last interrupt serviced in the NVLDL // Fatal tree. The last step of handling this interrupt is going into the // reset_and_drain flow for the given link which will shutdown and reset // the link. The reset portion will also wipe away any link state including // pending DL interrupts. In order to log all error before wiping that state, // service all other interrupts before this one // - bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); if (nvswitch_test_flags(pending, bit)) { + dlDeferredIntrLinkMask |= bit; + nvswitch_clear_flags(&unhandled, bit); - chip_device->deferredLinkErrors[link].fatalIntrMask.dl |= bit; - _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); + // + // Since reset and drain will reset the link, including clearing + // pending interrupts, skip the clear write below. There are cases + // where link clocks will not be on after reset and drain so there + // maybe PRI errors on writing to the register + // + bRequireResetAndDrain = NV_TRUE; + } + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); + if (nvswitch_test_flags(pending, bit)) + { + dlDeferredIntrLinkMask |= bit; nvswitch_clear_flags(&unhandled, bit); - device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link)); // // Since reset and drain will reset the link, including clearing @@ -7446,7 +7780,31 @@ nvswitch_service_nvldl_fatal_link_ls10 // where link clocks will not be on after reset and drain so there // maybe PRI errors on writing to the register // - bSkipIntrClear = NV_TRUE; + bRequireResetAndDrain = NV_TRUE; + } + + if (bRequireResetAndDrain) + { + // + // If there is a link state callback enabled for this link then + // we hit a consecutive FAULT_UP error. set bResetAndDrainRetry + // so the current callback on completion can create a new + // callback to retry the link state check to account for the added + // delay caused by taking a 2nd fault and having to re-train + // + // If there is no callback enabled then set the error mask + // and create the link errors deferred task. + // + if (chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled) + { + chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_TRUE; + } + else + { + chip_device->deferredLinkErrors[link].fatalIntrMask.dl = dlDeferredIntrLinkMask; + _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); + } + device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link)); } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -7458,9 +7816,9 @@ nvswitch_service_nvldl_fatal_link_ls10 report.raw_enable ^ pending); } - if (!bSkipIntrClear) + if (!bRequireResetAndDrain) { - NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR, pending); + NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR, pending); } if (unhandled != 0) @@ -7484,6 +7842,8 @@ nvswitch_service_minion_link_ls10 NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, unhandled, minionIntr, linkIntr, reg, enabledLinks, bit; NvU32 localLinkIdx, link; + MINION_LINK_INTR minionLinkIntr = { 0 }; + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); // // _MINION_MINION_INTR shows all interrupts currently at the host on this minion @@ -7512,7 +7872,9 @@ nvswitch_service_minion_link_ls10 } unhandled = pending; - + + minionLinkIntr.bPending = NV_TRUE; + FOR_EACH_INDEX_IN_MASK(32, localLinkIdx, pending) { link = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + localLinkIdx; @@ -7520,6 +7882,7 @@ nvswitch_service_minion_link_ls10 // read in the interrupt register for the given link linkIntr = NVSWITCH_MINION_LINK_RD32_LS10(device, link, _MINION, _NVLINK_LINK_INTR(localLinkIdx)); + minionLinkIntr.regData = linkIntr; // _STATE must be set for _CODE to be valid if (!DRF_VAL(_MINION, _NVLINK_LINK_INTR, _STATE, linkIntr)) @@ -7543,7 +7906,15 @@ nvswitch_service_minion_link_ls10 switch(DRF_VAL(_MINION, _NVLINK_LINK_INTR, _CODE, linkIntr)) { case NV_MINION_NVLINK_LINK_INTR_CODE_NA: - NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link NA interrupt", NV_FALSE); + case NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT: + case NV_MINION_NVLINK_LINK_INTR_CODE_LOCAL_CONFIG_ERR: + case NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR: + case NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT: + case NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL: + case NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT: + chip_device->deferredLinkErrors[link].fatalIntrMask.minionLinkIntr = + minionLinkIntr; + _nvswitch_create_deferred_link_errors_task_ls10(device, instance, link); break; case NV_MINION_NVLINK_LINK_INTR_CODE_SWREQ: NVSWITCH_PRINT(device, INFO, @@ -7551,37 +7922,16 @@ nvswitch_service_minion_link_ls10 __FUNCTION__, instance, link); break; case NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ: - NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link DLREQ interrupt"); - break; case NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED: - NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link PMDISABLED interrupt"); - break; - case NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT: - NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link DLCMDFAULT interrupt", NV_FALSE); - break; case NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ: - NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link TLREQ interrupt"); - break; - case NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT: - NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link NOINIT interrupt", NV_FALSE); - break; + chip_device->deferredLinkErrors[link].nonFatalIntrMask.minionLinkIntr = + minionLinkIntr; + _nvswitch_create_deferred_link_errors_task_ls10(device, instance, link); case NV_MINION_NVLINK_LINK_INTR_CODE_NOTIFY: NVSWITCH_PRINT(device, INFO, "%s: Received MINION NOTIFY interrupt on MINION %d : link %d.\n", __FUNCTION__, instance, link); break; - case NV_MINION_NVLINK_LINK_INTR_CODE_LOCAL_CONFIG_ERR: - NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link Local-Config-Error interrupt", NV_FALSE); - break; - case NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR: - NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link Negotiation Config Err Interrupt", NV_FALSE); - break; - case NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT: - NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link BADINIT interrupt", NV_FALSE); - break; - case NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL: - NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link PMFAIL interrupt", NV_FALSE); - break; case NV_MINION_NVLINK_LINK_INTR_CODE_INBAND_BUFFER_AVAILABLE: { NVSWITCH_PRINT(device, INFO, @@ -7589,19 +7939,10 @@ nvswitch_service_minion_link_ls10 nvswitch_minion_receive_inband_data_ls10(device, link); break; } - default: NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Interrupt code unknown", NV_FALSE); } nvswitch_clear_flags(&unhandled, bit); - - // Disable interrupt bit for the given link - fatal error ocurred before - if (device->link[link].fatal_error_occurred) - { - enabledLinks &= ~bit; - reg = DRF_NUM(_MINION, _MINION_INTR_STALL_EN, _LINK, enabledLinks); - NVSWITCH_MINION_LINK_WR32_LS10(device, link, _MINION, _MINION_INTR_STALL_EN, reg); - } } FOR_EACH_INDEX_IN_MASK_END; @@ -7614,4 +7955,3 @@ nvswitch_service_minion_link_ls10 return NVL_SUCCESS; } - diff --git a/src/common/nvswitch/kernel/ls10/link_ls10.c b/src/common/nvswitch/kernel/ls10/link_ls10.c index f98306b95a..bdcae93fa4 100644 --- a/src/common/nvswitch/kernel/ls10/link_ls10.c +++ b/src/common/nvswitch/kernel/ls10/link_ls10.c @@ -121,8 +121,13 @@ nvswitch_init_lpwr_regs_ls10 // IC Enter Threshold if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) { + // // TODO: get from bios. Refer Bug 3626523 for more info. - lpEntryThreshold = 100; + // + // The threshold is measured in 100us unit. So lpEntryThreshold = 1 + // means the threshold is set to 100us in the register. + // + lpEntryThreshold = 1; } else { @@ -505,7 +510,7 @@ nvswitch_reset_persistent_link_hw_state_ls10 NvU32 clocksMask = NVSWITCH_PER_LINK_CLOCK_SET(RXCLK)|NVSWITCH_PER_LINK_CLOCK_SET(TXCLK)| NVSWITCH_PER_LINK_CLOCK_SET(NCISOCCLK); nvlink_link *link = nvswitch_get_link(device, linkNumber); - if (nvswitch_is_link_in_reset(device, link)) + if ((link == NULL) || nvswitch_is_link_in_reset(device, link)) { return; } @@ -1225,11 +1230,13 @@ nvswitch_configure_error_rate_threshold_interrupt_ls10 if (bEnable) { link->errorThreshold.bInterruptTrigerred = NV_FALSE; - intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE); + intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 1, + intrRegVal); } else { - intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _DISABLE); + intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0, + intrRegVal); } NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, @@ -1249,12 +1256,29 @@ nvswitch_init_dlpl_interrupts_ls10 NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR, 0xffffffff); NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_SW2, 0xffffffff); + // Set the interrupt bits + nvswitch_set_dlpl_interrupts_ls10(link); + + // Setup error rate thresholds + nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE); + nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE); +} + +void +nvswitch_set_dlpl_interrupts_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNumber = link->linkNumber; // Stall tree routes to INTR_A which is connected to NVLIPT fatal tree NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_STALL_EN, DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_REPLAY, _DISABLE) | DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_RECOVERY_SHORT, _DISABLE) | DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _LTSSM_FAULT_UP, _ENABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _LTSSM_FAULT_DOWN, _ENABLE) | DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_RAM, _ENABLE) | DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_INTERFACE, _ENABLE) | DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_SUBLINK_CHANGE, _DISABLE) | @@ -1281,9 +1305,6 @@ nvswitch_init_dlpl_interrupts_ls10 DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_CRC_COUNTER, _ENABLE) | DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _LTSSM_PROTOCOL, _DISABLE) | DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _MINION_REQUEST, _DISABLE)); - - nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE); - nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE); } static NvU32 @@ -1433,7 +1454,7 @@ nvswitch_execute_unilateral_link_shutdown_ls10 NvU32 link_state_request; NvU32 link_state; NvU32 stat_data = 0; - NvU32 link_intr_subcode; + NvU32 link_intr_subcode = MINION_OK; if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) { @@ -1470,7 +1491,6 @@ nvswitch_execute_unilateral_link_shutdown_ls10 NV_NVLSTAT_MN00, 0, &stat_data) == NVL_SUCCESS) { link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); - } if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && (link_intr_subcode == MINION_ALARM_BUSY)) @@ -1488,6 +1508,13 @@ nvswitch_execute_unilateral_link_shutdown_ls10 { break; } + } + else + { + // Querying MINION for link_intr_subcode failed so retry + retry_count--; + } + } while (retry_count); @@ -1510,7 +1537,7 @@ nvswitch_reset_and_train_link_ls10 NvU32 link_state_request; NvU32 link_state; NvU32 stat_data; - NvU32 link_intr_subcode; + NvU32 link_intr_subcode = MINION_OK; nvswitch_execute_unilateral_link_shutdown_ls10(link); nvswitch_corelib_clear_link_state_ls10(link); @@ -1537,7 +1564,6 @@ nvswitch_reset_and_train_link_ls10 NV_NVLSTAT_MN00, 0, &stat_data) == NVL_SUCCESS) { link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); - } if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && (link_intr_subcode == MINION_ALARM_BUSY)) @@ -1557,6 +1583,12 @@ nvswitch_reset_and_train_link_ls10 break; } } + else + { + // failed to query minion for the link_intr_subcode so retry + retry_count--; + } + } } while(retry_count); if (status != NVL_SUCCESS) @@ -1625,3 +1657,24 @@ nvswitch_are_link_clocks_on_ls10 return NV_TRUE; } +NvBool +nvswitch_does_link_need_termination_enabled_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + // Not defined for LS10 + return NV_FALSE; +} + +NvlStatus +nvswitch_link_termination_setup_ls10 +( + nvswitch_device *device, + nvlink_link* link +) +{ + // Not supported for LS10 + return -NVL_ERR_NOT_SUPPORTED; +} diff --git a/src/common/nvswitch/kernel/ls10/ls10.c b/src/common/nvswitch/kernel/ls10/ls10.c index 159592615a..728fa4fbcc 100644 --- a/src/common/nvswitch/kernel/ls10/ls10.c +++ b/src/common/nvswitch/kernel/ls10/ls10.c @@ -27,6 +27,7 @@ #include "regkey_nvswitch.h" #include "haldef_nvswitch.h" #include "nvlink_inband_msg.h" +#include "rmsoecmdif.h" #include "ls10/ls10.h" #include "lr10/lr10.h" @@ -63,9 +64,11 @@ #include "nvswitch/ls10/dev_multicasttstate_ip.h" #include "nvswitch/ls10/dev_reductiontstate_ip.h" #include "ls10/minion_nvlink_defines_public_ls10.h" +#include "nvswitch/ls10/dev_pmgr.h" +#include "nvswitch/ls10/dev_timer_ip.h" #define NVSWITCH_IFR_MIN_BIOS_VER_LS10 0x9610170000ull -#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610170000ull +#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610220000ull void * nvswitch_alloc_chipdevice_ls10 @@ -113,7 +116,7 @@ nvswitch_pri_ring_init_ls10 { keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; - command = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); + command = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); if (FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, command)) { break; @@ -914,7 +917,7 @@ nvswitch_ctrl_get_sw_info_ls10 switch (p->index[i]) { case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_NVL_SUPPORTED: - p->info[i] = NV_FALSE; //TODO: Enable once NVL support is present (CTK-4163) + p->info[i] = NV_TRUE; break; case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_BBX_SUPPORTED: p->info[i] = NV_TRUE; @@ -1103,10 +1106,17 @@ nvswitch_link_disable_interrupts_ls10 instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10; localLinkIdx = link % NVSWITCH_LINKS_PER_NVLIPT_LS10; - NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT, - DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x0) | - DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x0) | - DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x0)); + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_set_nport_interrupts_ls10(device, link, NV_FALSE); + } + else + { + NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT, + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x0) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x0) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x0)); + } NVSWITCH_ENG_WR32(device, NVLW, , instance, _NVLW, _LINK_INTR_0_MASK(localLinkIdx), DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x0) | @@ -1138,31 +1148,38 @@ _nvswitch_link_reset_interrupts_ls10 NvU32 eng_instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10; NvU32 localLinkNum = link % NVSWITCH_LINKS_PER_NVLIPT_LS10; - NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT, - DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x1) | - DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x1) | - DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x1)); - - NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_0_MASK(localLinkNum), - DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x1) | - DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) | - DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _CORRECTABLE, 0x0) | - DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x1) | - DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x0)); - - NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_1_MASK(localLinkNum), - DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _FATAL, 0x0) | - DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _NONFATAL, 0x1) | - DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _CORRECTABLE, 0x1) | - DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x0) | - DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x1)); - - NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_2_MASK(localLinkNum), - DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _FATAL, 0x0) | - DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _NONFATAL, 0x0) | - DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _CORRECTABLE, 0x0) | - DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR0, 0x0) | - DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR1, 0x0)); + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_set_nport_interrupts_ls10(device, link, NV_TRUE); + } + else + { + NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT, + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x1) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x1) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x1)); + } + + NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_0_MASK(localLinkNum), + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x1) | + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _CORRECTABLE, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x1) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x0)); + + NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_1_MASK(localLinkNum), + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _NONFATAL, 0x1) | + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _CORRECTABLE, 0x1) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x1)); + + NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_2_MASK(localLinkNum), + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _CORRECTABLE, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR0, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR1, 0x0)); // NVLIPT_LNK regval = NVSWITCH_LINK_RD32_LS10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _INTR_CONTROL_LINK); @@ -1353,10 +1370,15 @@ nvswitch_reset_and_drain_links_ls10 NvU32 link; NvU32 data32; NvU32 retry_count = 3; - NvU32 link_state_request; - NvU32 link_state; - NvU32 stat_data; - NvU32 link_intr_subcode; + NvU32 link_state_request; + NvU32 link_state; + NvU32 stat_data; + NvU32 link_intr_subcode; + NvBool bKeepPolling; + NvBool bIsLinkInEmergencyShutdown; + NvBool bAreDlClocksOn; + NVSWITCH_TIMEOUT timeout; + if (link_mask == 0) { @@ -1425,10 +1447,9 @@ nvswitch_reset_and_drain_links_ls10 if (status != NVL_SUCCESS) { nvswitch_destroy_link(link_info); - return status; } - return -NVL_ERR_INVALID_STATE; + continue; } // @@ -1438,10 +1459,42 @@ nvswitch_reset_and_drain_links_ls10 // // Step 3.0 : - // Prior to starting port reset, perform unilateral shutdown on the - // LS10 side of the link, in case the links are not shutdown. + // Prior to starting port reset, ensure the links is in emergency shutdown // - nvswitch_execute_unilateral_link_shutdown_ls10(link_info); + bIsLinkInEmergencyShutdown = NV_FALSE; + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + do + { + bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + status = nvswitch_minion_get_dl_status(device, link_info->linkNumber, + NV_NVLSTAT_UC01, 0, &stat_data); + + if (status != NVL_SUCCESS) + { + continue; + } + + link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data); + + bIsLinkInEmergencyShutdown = (link_state == LINKSTATUS_EMERGENCY_SHUTDOWN) ? + NV_TRUE:NV_FALSE; + + if (bIsLinkInEmergencyShutdown == NV_TRUE) + { + break; + } + } + while(bKeepPolling); + + if (bIsLinkInEmergencyShutdown == NV_FALSE) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link %d failed to enter emergency shutdown\n", + __FUNCTION__, link); + continue; + } + nvswitch_corelib_clear_link_state_ls10(link_info); // @@ -1483,6 +1536,10 @@ nvswitch_reset_and_drain_links_ls10 { link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); } + else + { + continue; + } if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && (link_intr_subcode == MINION_ALARM_BUSY)) @@ -1515,9 +1572,8 @@ nvswitch_reset_and_drain_links_ls10 if (status != NVL_SUCCESS) { nvswitch_destroy_link(link_info); - return status; } - return status; + continue; } // @@ -1538,12 +1594,15 @@ nvswitch_reset_and_drain_links_ls10 status = nvlink_lib_register_link(device->nvlink_device, link_info); if (status != NVL_SUCCESS) { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to register link: 0x%x with the corelib\n", + __FUNCTION__, link); nvswitch_destroy_link(link_info); - return status; + continue; } // - // Launch ALI training to re-initialize and train the links + // Step 9.0: Launch ALI training to re-initialize and train the links // nvswitch_launch_ALI_link_training(device, link_info); // // Request active, but don't block. FM will come back and check @@ -1558,7 +1617,44 @@ nvswitch_reset_and_drain_links_ls10 NVSWITCH_PRINT(device, ERROR, "%s: TL link state request to active for ALI failed for link: 0x%x\n", __FUNCTION__, link); + continue; + } + + bAreDlClocksOn = NV_FALSE; + nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + do + { + bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + status = nvswitch_minion_get_dl_status(device, link_info->linkNumber, + NV_NVLSTAT_UC01, 0, &stat_data); + + if (status != NVL_SUCCESS) + { + continue; + } + + link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data); + + bAreDlClocksOn = (link_state != LINKSTATUS_INITPHASE1) ? + NV_TRUE:NV_FALSE; + + if (bAreDlClocksOn == NV_TRUE) + { + break; + } } + while(bKeepPolling); + + if (!bAreDlClocksOn) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link: 0x%x doesn't have the TX/RX clocks on, skipping setting DL interrupts!\n", + __FUNCTION__, link); + continue; + } + + nvswitch_set_dlpl_interrupts_ls10(link_info); } FOR_EACH_INDEX_IN_MASK_END; @@ -1575,6 +1671,7 @@ nvswitch_set_nport_port_config_ls10 ) { NvU32 val; + NvlStatus status = NVL_SUCCESS; if (p->requesterLinkID >= NVBIT( DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID) + @@ -1624,156 +1721,162 @@ nvswitch_set_nport_port_config_ls10 if (p->type == CONNECT_TRUNK_SWITCH) { - if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + if (!nvswitch_is_soe_supported(device)) { // Set trunk specific settings (TPROD) on PRE-SILION - // NPORT - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _NPORT, _CTRL); - val = FLD_SET_DRF(_NPORT, _CTRL, _EGDRAINENB, _DISABLE, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _ENEGRESSDBI, _ENABLE, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _ENROUTEDBI, _ENABLE, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _RTDRAINENB, _DISABLE, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _SPARE, _INIT, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _TRUNKLINKENB, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _CTRL, val); - - // EGRESS - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _CTRL); - val = FLD_SET_DRF(_EGRESS, _CTRL, _CTO_ENB, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _CTRL, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _HWRSPERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _URRSPERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _HWRSPERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _URRSPERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _HWRSPERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _INVALIDVCSET_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _URRSPERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PRIVRSPERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); - - // INGRESS - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _INVALIDVCSET, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _READMCREFLECTMEMERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ACLFAIL, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _READMCREFLECTMEMERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, val); - - // SOURCETRACK - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0, val); - - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, val); - } - else - { + // NPORT + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _NPORT, _CTRL); + val = FLD_SET_DRF(_NPORT, _CTRL, _EGDRAINENB, _DISABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _ENEGRESSDBI, _ENABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _ENROUTEDBI, _ENABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _RTDRAINENB, _DISABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _SPARE, _INIT, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _TRUNKLINKENB, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _CTRL, val); + + // EGRESS + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _CTRL); + val = FLD_SET_DRF(_EGRESS, _CTRL, _CTO_ENB, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _CTRL, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PRIVRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); + + // INGRESS + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _READMCREFLECTMEMERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _READMCREFLECTMEMERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, val); + + // SOURCETRACK + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, val); + } + else + { // Set trunk specific settings (TPROD) in SOE - // nvswitch_set_nport_tprod_state_ls10(device, p->portNum); + status = nvswitch_set_nport_tprod_state_ls10(device, p->portNum); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to set NPORT TPROD state\n", + __FUNCTION__); + } } } else @@ -1784,7 +1887,7 @@ nvswitch_set_nport_port_config_ls10 NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE0, NvU64_LO32(p->trunkSrcMask)); NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE1, NvU64_HI32(p->trunkSrcMask)); - return NVL_SUCCESS; + return status; } /* @@ -2567,7 +2670,6 @@ nvswitch_get_nvlink_ecc_errors_ls10 NvU32 sublinkWidth; link = nvswitch_get_link(device, i); - sublinkWidth = device->hal.nvswitch_get_sublink_width(device, i); if ((link == NULL) || !NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber) || @@ -2576,6 +2678,8 @@ nvswitch_get_nvlink_ecc_errors_ls10 return -NVL_BAD_ARGS; } + sublinkWidth = device->hal.nvswitch_get_sublink_width(device, i); + minion_enabled = nvswitch_is_minion_initialized(device, NVSWITCH_GET_LINK_ENG_INST(device, link->linkNumber, MINION)); @@ -2649,6 +2753,48 @@ nvswitch_get_num_links_per_nvlipt_ls10 return NVSWITCH_LINKS_PER_NVLIPT_LS10; } + +NvlStatus +nvswitch_ctrl_get_fom_values_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_FOM_VALUES_PARAMS *p +) +{ + NvlStatus status; + NvU32 statData; + nvlink_link *link; + + link = nvswitch_get_link(device, p->linkId); + if (link == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: link #%d invalid\n", + __FUNCTION__, p->linkId); + return -NVL_BAD_ARGS; + } + + if (nvswitch_is_link_in_reset(device, link)) + { + NVSWITCH_PRINT(device, ERROR, "%s: link #%d is in reset\n", + __FUNCTION__, p->linkId); + return -NVL_ERR_INVALID_STATE; + } + + status = nvswitch_minion_get_dl_status(device, p->linkId, + NV_NVLSTAT_TR16, 0, &statData); + p->figureOfMeritValues[0] = (NvU16) (statData & 0xFFFF); + p->figureOfMeritValues[1] = (NvU16) ((statData >> 16) & 0xFFFF); + + status = nvswitch_minion_get_dl_status(device, p->linkId, + NV_NVLSTAT_TR17, 0, &statData); + p->figureOfMeritValues[2] = (NvU16) (statData & 0xFFFF); + p->figureOfMeritValues[3] = (NvU16) ((statData >> 16) & 0xFFFF); + + p->numLanes = nvswitch_get_sublink_width(device, p->linkId); + + return status; +} + void nvswitch_set_fatal_error_ls10 ( @@ -2798,7 +2944,7 @@ nvswitch_is_inforom_supported_ls10 { NVSWITCH_PRINT(device, INFO, "INFOROM is not supported since SOE is not supported\n"); - return NV_FALSE; + return NV_FALSE; } status = _nvswitch_get_bios_version(device, &version); @@ -2806,8 +2952,8 @@ nvswitch_is_inforom_supported_ls10 { NVSWITCH_PRINT(device, ERROR, "%s: Error getting BIOS version\n", __FUNCTION__); - return NV_FALSE; -} + return NV_FALSE; + } if (version >= NVSWITCH_IFR_MIN_BIOS_VER_LS10) { @@ -2839,6 +2985,41 @@ nvswitch_is_spi_supported_ls10 return NV_FALSE; } +NvBool +nvswitch_is_bios_supported_ls10 +( + nvswitch_device *device +) +{ + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + NVSWITCH_PRINT(device, INFO, + "BIOS is not supported on non-silicon platforms\n"); + return NV_FALSE; + } + + if (!nvswitch_is_soe_supported(device)) + { + NVSWITCH_PRINT(device, INFO, + "BIOS is not supported since SOE is not supported\n"); + return NV_FALSE; + } + + return NV_TRUE; +} + +NvlStatus +nvswitch_get_bios_size_ls10 +( + nvswitch_device *device, + NvU32 *pSize +) +{ + *pSize = SOE_CORE_BIOS_SIZE_LS10; + + return NVL_SUCCESS; +} + /* * @Brief : Check if SMBPBI is supported * @@ -2849,21 +3030,14 @@ nvswitch_is_smbpbi_supported_ls10 nvswitch_device *device ) { + NvU64 version; + NvlStatus status; + if (!nvswitch_is_smbpbi_supported_lr10(device)) { return NV_FALSE; } - // - // Temporary driver WAR to disable SMBPBI on the LS10 NVSwitch driver. - // This should be removed once 3875091 is resolved. - // - return NV_FALSE; - -#if 0 - NvU64 version; - NvlStatus status; - status = _nvswitch_get_bios_version(device, &version); if (status != NVL_SUCCESS) { @@ -2882,7 +3056,6 @@ nvswitch_is_smbpbi_supported_ls10 "SMBPBI is not supported on NVSwitch BIOS version %llx.\n", version); return NV_FALSE; } -#endif } /* @@ -4938,7 +5111,7 @@ nvswitch_launch_ALI_ls10 } nvswitch_launch_ALI_link_training(device, link, NV_FALSE); - } + } FOR_EACH_INDEX_IN_MASK_END; return NVL_SUCCESS; @@ -5065,29 +5238,29 @@ nvswitch_set_training_mode_ls10 { regVal = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, - _CTRL_CAP_LOCAL_LINK_CHANNEL); + _CTRL_CAP_LOCAL_LINK_CHANNEL); - if (!FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CAP_LOCAL_LINK_CHANNEL, _ALI_SUPPORT, _SUPPORTED, regVal)) - { - NVSWITCH_PRINT(device, ERROR, - "%s: ALI training not supported! Non-ALI will be used as the default.\n",__FUNCTION__); + if (!FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CAP_LOCAL_LINK_CHANNEL, _ALI_SUPPORT, _SUPPORTED, regVal)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ALI training not supported! Non-ALI will be used as the default.\n",__FUNCTION__); #ifdef INCLUDE_NVLINK_LIB device->nvlink_device->enableALI = NV_FALSE; #endif - return NVL_SUCCESS; - } + return NVL_SUCCESS; + } #ifdef INCLUDE_NVLINK_LIB device->nvlink_device->enableALI = NV_TRUE; #endif - } + } else { - NVSWITCH_PRINT(device, ERROR, + NVSWITCH_PRINT(device, ERROR, "%s: ALI training not enabled! Non-ALI will be used as the default.\n",__FUNCTION__); #ifdef INCLUDE_NVLINK_LIB - device->nvlink_device->enableALI = NV_FALSE; + device->nvlink_device->enableALI = NV_FALSE; #endif - return NVL_SUCCESS; + return NVL_SUCCESS; } } FOR_EACH_INDEX_IN_MASK_END; @@ -5356,7 +5529,7 @@ nvswitch_ctrl_get_board_part_number_ls10 if (!pInforom->OBD.bValid) { NVSWITCH_PRINT(device, ERROR, "OBD data is not available\n"); - return -NVL_ERR_GENERIC; + return -NVL_ERR_NOT_SUPPORTED; } pOBDObj = &pInforom->OBD.object.v2; diff --git a/src/common/nvswitch/kernel/ls10/minion_ls10.c b/src/common/nvswitch/kernel/ls10/minion_ls10.c index 45da88d6a2..0db7bb7cb4 100644 --- a/src/common/nvswitch/kernel/ls10/minion_ls10.c +++ b/src/common/nvswitch/kernel/ls10/minion_ls10.c @@ -954,14 +954,15 @@ nvswitch_minion_get_ali_debug_registers_ls10 ) { NvU32 localLinkNumber = link->linkNumber % NVSWITCH_LINKS_PER_MINION_LS10; - if (!nvswitch_minion_get_dl_status(device, link->linkNumber, - NV_NVLSTAT_MN00, 0, &(params->dlstatMn00)) == NVL_SUCCESS) + if (nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_MN00, 0, &(params->dlstatMn00)) != NVL_SUCCESS) { NVSWITCH_PRINT(device, INFO,"%s : Failed to poll DLSTAT _MN00 register for (%s):(%d)\n", __FUNCTION__, device->name, link->linkNumber); } - if (!nvswitch_minion_get_dl_status(device, link->linkNumber, NV_NVLSTAT_UC01, 0, &(params->dlstatUc01))) + if (nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_UC01, 0, &(params->dlstatUc01)) != NVL_SUCCESS) { NVSWITCH_PRINT(device, INFO,"%s : Failed to poll DLSTAT UC01 register for (%s):(%d)\n", __FUNCTION__, device->name, link->linkNumber); diff --git a/src/common/nvswitch/kernel/ls10/pmgr_ls10.c b/src/common/nvswitch/kernel/ls10/pmgr_ls10.c index dbe8108c7d..2fa83b9551 100644 --- a/src/common/nvswitch/kernel/ls10/pmgr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/pmgr_ls10.c @@ -301,7 +301,12 @@ nvswitch_ctrl_i2c_indexed_ls10 } return nvswitch_ctrl_i2c_indexed_lr10(device, pParams); } - + + if (pParams->port == NVSWITCH_I2C_PORT_I2CA) + { + pParams->flags = FLD_SET_DRF(SWITCH_CTRL, _I2C_FLAGS, _SPEED_MODE, _100KHZ, pParams->flags); + } + if (pI2c->soeI2CSupported) { return soeI2CAccess_HAL(device, pParams); diff --git a/src/common/nvswitch/kernel/ls10/soe_ls10.c b/src/common/nvswitch/kernel/ls10/soe_ls10.c index 6e43c21a2c..85b2e0923b 100644 --- a/src/common/nvswitch/kernel/ls10/soe_ls10.c +++ b/src/common/nvswitch/kernel/ls10/soe_ls10.c @@ -31,7 +31,6 @@ #include "common_nvswitch.h" #include "ls10/ls10.h" #include "ls10/soe_ls10.h" -#include "lr10/soe_lr10.h" #include "nvswitch/ls10/dev_soe_ip.h" #include "nvswitch/ls10/dev_soe_ip_addendum.h" @@ -344,10 +343,17 @@ nvswitch_set_nport_tprod_state_ls10 NVSWITCH_TIMEOUT timeout; RM_SOE_CORE_CMD_NPORT_TPROD_STATE *nportTprodState; + if (!NVSWITCH_ENG_IS_VALID(device, NPORT, nport)) + { + NVSWITCH_PRINT(device, ERROR, "%s: NPORT #%d invalid\n", + __FUNCTION__, nport); + return -NVL_BAD_ARGS; + } + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_TPROD_STATE); nportTprodState = &cmd.cmd.core.nportTprodState; nportTprodState->nport = nport; @@ -401,7 +407,7 @@ nvswitch_soe_init_l2_state_ls10 nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, L2_STATE); pL2State = &cmd.cmd.core.l2State; pL2State->cmdType = RM_SOE_CORE_CMD_INIT_L2_STATE; @@ -421,6 +427,136 @@ nvswitch_soe_init_l2_state_ls10 } } +/* + * @Brief : Enable/Disable NPORT interrupts + * + * @param[in] device + * @param[in] nport + */ +NvlStatus +nvswitch_soe_set_nport_interrupts_ls10 +( + nvswitch_device *device, + NvU32 nport, + NvBool bEnable +) +{ + FLCN *pFlcn; + NvU32 cmdSeqDesc = 0; + NV_STATUS status; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + RM_SOE_CORE_CMD_NPORT_INTRS *pNportIntrs; + + if (!nvswitch_is_soe_supported(device)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: SOE is not supported\n", + __FUNCTION__); + return -NVL_ERR_INVALID_STATE; + } + + pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_INTRS); + + pNportIntrs = &cmd.cmd.core.nportIntrs; + pNportIntrs->cmdType = RM_SOE_CORE_CMD_SET_NPORT_INTRS; + pNportIntrs->nport = nport; + pNportIntrs->bEnable = bEnable; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to send SET_NPORT_INTRS command to SOE, status 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_GENERIC; + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Disable NPORT Fatal Interrupt in SOE + * + * @param[in] device + * @param[in] nport + * @param[in] nportIntrEnable + * @param[in] nportIntrType + */ +void +nvswitch_soe_disable_nport_fatal_interrupts_ls10 +( + nvswitch_device *device, + NvU32 nport, + NvU32 nportIntrEnable, + NvU8 nportIntrType +) +{ + FLCN *pFlcn; + NvU32 cmdSeqDesc = 0; + NV_STATUS status; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + RM_SOE_CORE_CMD_NPORT_FATAL_INTR *pNportIntrDisable; + NVSWITCH_GET_BIOS_INFO_PARAMS p = { 0 }; + NvlStatus stat; + + stat = device->hal.nvswitch_ctrl_get_bios_info(device, &p); + if ((stat != NVL_SUCCESS) || ((p.version & SOE_VBIOS_VERSION_MASK) < + SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Skipping DISABLE_NPORT_FATAL_INTR command to SOE. Update firmware " + "from .%02X to .%02X\n", + __FUNCTION__, (NvU32)((p.version & SOE_VBIOS_VERSION_MASK) >> 16), + SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR); + return; + } + + if (!nvswitch_is_soe_supported(device)) + { + NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported\n", + __FUNCTION__); + return; + } + + pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_FATAL_INTR); + + pNportIntrDisable = &cmd.cmd.core.nportDisableIntr; + pNportIntrDisable->cmdType = RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR; + pNportIntrDisable->nport = nport; + pNportIntrDisable->nportIntrEnable = nportIntrEnable; + pNportIntrDisable->nportIntrType = nportIntrType; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to send DISABLE_NPORT_FATAL_INTR command to SOE, status 0x%x\n", + __FUNCTION__, status); + } +} /* * @Brief : Init sequence for SOE FSP RISCV image @@ -482,14 +618,6 @@ nvswitch_init_soe_ls10 return status; } - // - // Set TRACEPC to stack mode for better ucode trace - // In Vulcan CR firmware, this is set to reduced mode in the SOE's manifest - // - data = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL); - data = FLD_SET_DRF(_PRISCV, _RISCV_TRACECTL, _MODE, _STACK, data); - flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, data); - // Sanity the command and message queues as a final check if (_nvswitch_soe_send_test_cmd(device) != NV_OK) { @@ -555,7 +683,7 @@ nvswitch_soe_register_event_callbacks_ls10 device, pFlcn, RM_SOE_UNIT_THERM, NULL, - nvswitch_therm_soe_callback_lr10, + nvswitch_therm_soe_callback_ls10, NULL, &pSoe->thermEvtDesc); if (status != NV_OK) diff --git a/src/common/nvswitch/kernel/ls10/therm_ls10.c b/src/common/nvswitch/kernel/ls10/therm_ls10.c index e2c546e203..f642c6d28e 100644 --- a/src/common/nvswitch/kernel/ls10/therm_ls10.c +++ b/src/common/nvswitch/kernel/ls10/therm_ls10.c @@ -361,6 +361,103 @@ nvswitch_monitor_thermal_alert_ls10 return; } +/* + * @brief Callback function to recieve thermal messages from SOE. + */ +void +nvswitch_therm_soe_callback_ls10 +( + nvswitch_device *device, + RM_FLCN_MSG *pGenMsg, + void *pParams, + NvU32 seqDesc, + NV_STATUS status +) +{ + RM_SOE_THERM_MSG_SLOWDOWN_STATUS slowdown_status; + RM_SOE_THERM_MSG_SHUTDOWN_STATUS shutdown_status; + RM_FLCN_MSG_SOE *pMsg = (RM_FLCN_MSG_SOE *)pGenMsg; + NvU32 temperature; + NvU32 threshold; + + switch (pMsg->msg.soeTherm.msgType) + { + case RM_SOE_THERM_MSG_ID_SLOWDOWN_STATUS: + { + slowdown_status = pMsg->msg.soeTherm.slowdown; + if (slowdown_status.bSlowdown) + { + if (slowdown_status.source.bTsense) // TSENSE_THERM_ALERT + { + temperature = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(slowdown_status.maxTemperature); + threshold = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(slowdown_status.warnThreshold); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, + "NVSWITCH Temperature %dC | TSENSE WARN Threshold %dC\n", + temperature, threshold); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, + "Thermal Slowdown Engaged | Temp higher than WARN Threshold\n"); + } + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, + "Thermal Slowdown Engaged | Links Thermal Mode %s\n", (slowdown_status.bLinksL1Status ? "ON" : "OFF")); + + if (slowdown_status.source.bPmgr) // PMGR_THERM_ALERT + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, + "Thermal Slowdown Engaged | PMGR WARN Threshold reached\n"); + } + } + else // REVERT_SLOWDOWN + { + temperature = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(slowdown_status.maxTemperature); + threshold = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(slowdown_status.warnThreshold); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END, + "NVSWITCH Temperature %dC | TSENSE WARN Threshold %dC\n", + temperature, threshold); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END, + "Thermal Slowdown Disengaged | Links Thermal Mode %s\n", (slowdown_status.bLinksL1Status ? "ON" : "OFF")); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END, + "Thermal slowdown Disengaged\n"); + } + break; + } + + case RM_SOE_THERM_MSG_ID_SHUTDOWN_STATUS: + { + shutdown_status = pMsg->msg.soeTherm.shutdown; + if (shutdown_status.source.bTsense) // TSENSE_THERM_SHUTDOWN + { + temperature = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(shutdown_status.maxTemperature); + threshold = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(shutdown_status.overtThreshold); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN, + "NVSWITCH Temperature %dC | OVERT Threshold %dC\n", + temperature, threshold); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN, + "TSENSE OVERT Threshold reached. Shutting Down\n"); + } + + if (shutdown_status.source.bPmgr) // PMGR_THERM_SHUTDOWN + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, + "PMGR OVERT Threshold reached. Shutting Down\n"); + } + break; + } + default: + { + NVSWITCH_PRINT(device, ERROR, "%s Unknown message Id\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + } + } +} + // // nvswitch_therm_read_voltage // @@ -445,3 +542,86 @@ nvswitch_ctrl_therm_read_voltage_ls10 return NVL_SUCCESS; } +// +// nvswitch_therm_read_power +// +// Power is only available on SKUs which have thermal and +// voltage sensors. +// +NvlStatus +nvswitch_ctrl_therm_read_power_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_POWER_PARAMS *pParams +) +{ + FLCN *pFlcn; + NvU32 cmdSeqDesc; + NV_STATUS status; + NvU8 flcnStatus; + RM_FLCN_CMD_SOE cmd; + RM_FLCN_MSG_SOE msg; + RM_SOE_CORE_CMD_GET_POWER *pGetPowerCmd; + NVSWITCH_TIMEOUT timeout; + + if (!nvswitch_is_soe_supported(device)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (pParams == NULL) + { + return -NVL_BAD_ARGS; + } + + pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(pParams, 0, sizeof(NVSWITCH_GET_POWER_PARAMS)); + nvswitch_os_memset(&cmd, 0, sizeof(RM_FLCN_CMD_SOE)); + nvswitch_os_memset(&msg, 0, sizeof(RM_FLCN_MSG_SOE)); + + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, GET_POWER); + + msg.hdr.unitId = RM_SOE_UNIT_CORE; + msg.hdr.size = RM_SOE_MSG_SIZE(CORE, GET_POWER); + + pGetPowerCmd = &cmd.cmd.core.getPower; + pGetPowerCmd->cmdType = RM_SOE_CORE_CMD_GET_POWER_VALUES; + + cmdSeqDesc = 0; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + (PRM_FLCN_MSG)&msg, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to read power 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_INVALID_STATE; + } + + flcnStatus = msg.msg.core.getPower.flcnStatus; + if (flcnStatus != FLCN_OK) + { + if (flcnStatus == FLCN_ERR_MORE_PROCESSING_REQUIRED) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + else + { + return -NVL_ERR_GENERIC; + } + } + + pParams->vdd_w = msg.msg.core.getPower.vdd_w; + pParams->dvdd_w = msg.msg.core.getPower.dvdd_w; + pParams->hvdd_w = msg.msg.core.getPower.hvdd_w; + + return NVL_SUCCESS; +} \ No newline at end of file diff --git a/src/common/nvswitch/kernel/nvswitch.c b/src/common/nvswitch/kernel/nvswitch.c index 2a3af407b4..1c474d8356 100644 --- a/src/common/nvswitch/kernel/nvswitch.c +++ b/src/common/nvswitch/kernel/nvswitch.c @@ -703,6 +703,15 @@ nvswitch_is_spi_supported return device->hal.nvswitch_is_spi_supported(device); } +NvBool +nvswitch_is_bios_supported +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_is_bios_supported(device); +} + NvBool nvswitch_is_smbpbi_supported ( @@ -1626,7 +1635,7 @@ nvswitch_lib_post_init_device return retval; } - if (nvswitch_is_spi_supported(device)) + if (nvswitch_is_bios_supported(device)) { retval = nvswitch_bios_get_image(device); if (retval != NVL_SUCCESS) @@ -1643,7 +1652,7 @@ nvswitch_lib_post_init_device else { NVSWITCH_PRINT(device, ERROR, - "%s: Skipping BIOS parsing since SPI is unsupported.\n", + "%s: Skipping BIOS parsing since BIOS is unsupported.\n", __FUNCTION__); } @@ -3363,6 +3372,26 @@ _nvswitch_ctrl_i2c_smbus_command cmdType, addr, port, cmd, msgLen, pData); } +NvBool +nvswitch_does_link_need_termination_enabled +( + nvswitch_device *device, + nvlink_link *link +) +{ + return device->hal.nvswitch_does_link_need_termination_enabled(device, link); +} + +NvlStatus +nvswitch_link_termination_setup +( + nvswitch_device *device, + nvlink_link* link +) +{ + return device->hal.nvswitch_link_termination_setup(device, link); +} + static NvlStatus _nvswitch_ctrl_get_inforom_nvlink_max_correctable_error_rate ( @@ -4745,6 +4774,16 @@ _nvswitch_ctrl_therm_read_voltage return device->hal.nvswitch_ctrl_therm_read_voltage(device, info); } +static NvlStatus +_nvswitch_ctrl_therm_read_power +( + nvswitch_device *device, + NVSWITCH_GET_POWER_PARAMS *info +) +{ + return device->hal.nvswitch_ctrl_therm_read_power(device, info); +} + NvlStatus nvswitch_lib_ctrl ( @@ -4980,6 +5019,8 @@ nvswitch_lib_ctrl CTRL_NVSWITCH_RESERVED_9); NVSWITCH_DEV_CMD_DISPATCH_RESERVED( CTRL_NVSWITCH_RESERVED_10); + NVSWITCH_DEV_CMD_DISPATCH_RESERVED( + CTRL_NVSWITCH_RESERVED_11); NVSWITCH_DEV_CMD_DISPATCH( CTRL_NVSWITCH_GET_TEMPERATURE_LIMIT, _nvswitch_ctrl_therm_get_temperature_limit, @@ -5084,6 +5125,9 @@ nvswitch_lib_ctrl NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_VOLTAGE, _nvswitch_ctrl_therm_read_voltage, NVSWITCH_CTRL_GET_VOLTAGE_PARAMS); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_POWER, + _nvswitch_ctrl_therm_read_power, + NVSWITCH_GET_POWER_PARAMS); default: nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd); diff --git a/src/common/nvswitch/kernel/smbpbi_nvswitch.c b/src/common/nvswitch/kernel/smbpbi_nvswitch.c index 3816cecbe1..8cefb389df 100644 --- a/src/common/nvswitch/kernel/smbpbi_nvswitch.c +++ b/src/common/nvswitch/kernel/smbpbi_nvswitch.c @@ -90,8 +90,10 @@ nvswitch_smbpbi_post_init if (status == NVL_SUCCESS) { +#if defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS) nvswitch_lib_smbpbi_log_sxid(device, NVSWITCH_ERR_NO_ERROR, "NVSWITCH SMBPBI server is online."); +#endif // defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS) NVSWITCH_PRINT(device, INFO, "%s: SMBPBI POST INIT completed\n", __FUNCTION__); } diff --git a/src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h b/src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h new file mode 100644 index 0000000000..f55c326962 --- /dev/null +++ b/src/common/sdk/nvidia/inc/alloc/alloc_access_counter_buffer.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: alloc/alloc_access_counter_buffer.finn +// + +#include "class/clc365.h" + + +/* + * NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS + * + * Allocation params for ACCESS_COUNTER_NOTIFY_BUFFER. + * This class provides an interface to access counter buffers. + + * accessCounterIndex [IN] + * This parameter specifies index of access counter to which the object should be assigned + * + */ +#define NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS_MESSAGE_ID (0xC365U) + +typedef struct NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS { + NvU32 accessCounterIndex; +} NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS; + diff --git a/src/common/sdk/nvidia/inc/alloc/alloc_channel.h b/src/common/sdk/nvidia/inc/alloc/alloc_channel.h index 4e9620466d..1c4e0c0a22 100644 --- a/src/common/sdk/nvidia/inc/alloc/alloc_channel.h +++ b/src/common/sdk/nvidia/inc/alloc/alloc_channel.h @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: alloc/alloc_channel.finn +// Source file: alloc/alloc_channel.finn // #include "nvlimits.h" @@ -83,6 +83,25 @@ typedef struct NV_MEMORY_DESC_PARAMS { #define NVOS04_FLAGS_VPR_FALSE 0x00000000 #define NVOS04_FLAGS_VPR_TRUE 0x00000001 +/* + * NVOS04_FLAGS_CC_SECURE: + * This flag specifies if channel is intended to be used for + * encryption/decryption of data between SYSMEM <-> VIDMEM. Only CE + * & SEC2 Channels are capable of handling encrypted content and this + * flag will be ignored when CC is disabled or for chips that are not CC + * Capable. + * Reusing VPR index since VPR & CC are mutually exclusive. + * + * NVOS04_FLAGS_CC_SECURE_TRUE: + * The channel will support CC Encryption/Decryption + * + * NVOS04_FLAGS_CC_SECURE_FALSE: + * The channel will not support CC Encryption/Decryption + */ +#define NVOS04_FLAGS_CC_SECURE 2:2 +#define NVOS04_FLAGS_CC_SECURE_FALSE 0x00000000 +#define NVOS04_FLAGS_CC_SECURE_TRUE 0x00000001 + /* @@ -300,8 +319,6 @@ typedef struct NV_CHANNEL_ALLOC_PARAMS { NvU32 subDeviceId; NvHandle hObjectEccError; // ECC error context DMA - - NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); diff --git a/src/common/sdk/nvidia/inc/cc_drv.h b/src/common/sdk/nvidia/inc/cc_drv.h new file mode 100644 index 0000000000..6a0c008a4d --- /dev/null +++ b/src/common/sdk/nvidia/inc/cc_drv.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: cc_drv.finn +// + + + +#include "nvtypes.h" +#include "nvcfg_sdk.h" + +// CLASS NV_CONF_COMPUTE +#define CC_AES_256_GCM_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */ +#define CC_AES_256_GCM_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(CC_AES_256_GCM_IV_SIZE_BYTES / 4)" */ +#define CC_AES_256_GCM_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_AES_256_GCM_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_AES_256_GCM_KEY_SIZE_BYTES / 4)" */ + +#define CC_HMAC_NONCE_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_HMAC_NONCE_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_NONCE_SIZE_BYTES / 4)" */ +#define CC_HMAC_KEY_SIZE_BYTES (0x20U) /* finn: Evaluated from "(256 / 8)" */ +#define CC_HMAC_KEY_SIZE_DWORD (0x8U) /* finn: Evaluated from "(CC_HMAC_KEY_SIZE_BYTES / 4)" */ + +#define APM_AES_128_CTR_IV_SIZE_BYTES (0xcU) /* finn: Evaluated from "(96 / 8)" */ +#define APM_AES_128_CTR_IV_SIZE_DWORD (0x3U) /* finn: Evaluated from "(APM_AES_128_CTR_IV_SIZE_BYTES / 4)" */ +#define APM_AES_128_CTR_KEY_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */ +#define APM_AES_128_CTR_KEY_SIZE_DWORD (0x4U) /* finn: Evaluated from "(APM_AES_128_CTR_KEY_SIZE_BYTES / 4)" */ + +// Type is shared between CC control calls and RMKeyStore +typedef enum ROTATE_IV_TYPE { + ROTATE_IV_ENCRYPT = 0, // Rotate the IV for encryptBundle + ROTATE_IV_DECRYPT = 1, // Rotate the IV for decryptBundle + ROTATE_IV_HMAC = 2, // Rotate the IV for hmacBundle + ROTATE_IV_ALL_VALID = 3, // Rotate the IV for all valid bundles in the KMB +} ROTATE_IV_TYPE; + +typedef struct CC_AES_CRYPTOBUNDLE { + NvU32 iv[CC_AES_256_GCM_IV_SIZE_DWORD]; + NvU32 key[CC_AES_256_GCM_KEY_SIZE_DWORD]; + NvU32 ivMask[CC_AES_256_GCM_IV_SIZE_DWORD]; +} CC_AES_CRYPTOBUNDLE; +typedef struct CC_AES_CRYPTOBUNDLE *PCC_AES_CRYPTOBUNDLE; + +typedef struct CC_HMAC_CRYPTOBUNDLE { + NvU32 nonce[CC_HMAC_NONCE_SIZE_DWORD]; + NvU32 key[CC_HMAC_KEY_SIZE_DWORD]; +} CC_HMAC_CRYPTOBUNDLE; +typedef struct CC_HMAC_CRYPTOBUNDLE *PCC_HMAC_CRYPTOBUNDLE; + +typedef struct CC_KMB { + CC_AES_CRYPTOBUNDLE encryptBundle; // Bundle of encyption material + + union { + CC_HMAC_CRYPTOBUNDLE hmacBundle; // HMAC bundle used for method stream authenticity + CC_AES_CRYPTOBUNDLE decryptBundle; // Bundle of decryption material + }; + NvBool bIsWorkLaunch; // False if decryption parameters are valid +} CC_KMB; +typedef struct CC_KMB *PCC_KMB; + diff --git a/src/common/sdk/nvidia/inc/class/cl0000.h b/src/common/sdk/nvidia/inc/class/cl0000.h index e7fefba706..e8a9b675dd 100644 --- a/src/common/sdk/nvidia/inc/class/cl0000.h +++ b/src/common/sdk/nvidia/inc/class/cl0000.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0000.finn +// Source file: class/cl0000.finn // #include "nvlimits.h" diff --git a/src/common/sdk/nvidia/inc/class/cl0005.h b/src/common/sdk/nvidia/inc/class/cl0005.h index 2d04c34d74..f3f5b534c7 100644 --- a/src/common/sdk/nvidia/inc/class/cl0005.h +++ b/src/common/sdk/nvidia/inc/class/cl0005.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0005.finn +// Source file: class/cl0005.finn // #include "cl0005_notification.h" diff --git a/src/common/sdk/nvidia/inc/class/cl000f.h b/src/common/sdk/nvidia/inc/class/cl000f.h index 7c0d96be3f..3182bec4cd 100644 --- a/src/common/sdk/nvidia/inc/class/cl000f.h +++ b/src/common/sdk/nvidia/inc/class/cl000f.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl000f.finn +// Source file: class/cl000f.finn // #define FABRIC_MANAGER_SESSION (0xfU) /* finn: Evaluated from "NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/nvidia/interface/nv_firmware_types.h b/src/common/sdk/nvidia/inc/class/cl0042.h similarity index 75% rename from src/nvidia/interface/nv_firmware_types.h rename to src/common/sdk/nvidia/inc/class/cl0042.h index 90dd93f1ea..e2a7ab547f 100644 --- a/src/nvidia/interface/nv_firmware_types.h +++ b/src/common/sdk/nvidia/inc/class/cl0042.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,14 +21,19 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef NV_FIRMWARE_TYPES_H -#define NV_FIRMWARE_TYPES_H +#ifndef _cl0042_h_ +#define _cl0042_h_ -typedef enum { - NV_FIRMWARE_MODE_DISABLED = 0, - NV_FIRMWARE_MODE_ENABLED = 1, - NV_FIRMWARE_MODE_DEFAULT = 2, - NV_FIRMWARE_MODE_INVALID = 0xFF -} NvFirmwareMode; +#ifdef __cplusplus +extern "C" { +#endif -#endif // NV_FIRMWARE_TYPES_H +#include "nvtypes.h" + +#define NV_MEMORY_EXTENDED_USER (0x00000042) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0042_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl0050.h b/src/common/sdk/nvidia/inc/class/cl0050.h new file mode 100644 index 0000000000..669ea9912e --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl0050.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0050.finn +// + +#define NV_CE_UTILS (0x50U) /* finn: Evaluated from "NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0050U) + +typedef struct NV0050_ALLOCATION_PARAMETERS { + NvHandle hVaspace; + NV_DECLARE_ALIGNED(NvU64 flags, 8); +} NV0050_ALLOCATION_PARAMETERS; + + +// Whether the CeUtils will allocate everything with RM client or external client +#define NV0050_CEUTILS_FLAGS_EXTERNAL 0:0 +#define NV0050_CEUTILS_FLAGS_EXTERNAL_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_EXTERNAL_TRUE (0x00000001) + +// Whether CeUtils will use virtual copy +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE 1:1 +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_VIRTUAL_MODE_TRUE (0x00000001) + +// Whether the CeUtils is using fifo lite mode. Has to be internal +#define NV0050_CEUTILS_FLAGS_FIFO_LITE 2:2 +#define NV0050_CEUTILS_FLAGS_FIFO_LITE_FALSE (0x00000000) +#define NV0050_CEUTILS_FLAGS_FIFO_LITE_TRUE (0x00000001) diff --git a/src/common/sdk/nvidia/inc/class/cl0060.h b/src/common/sdk/nvidia/inc/class/cl0060.h index 80e3778101..cfa88ff167 100644 --- a/src/common/sdk/nvidia/inc/class/cl0060.h +++ b/src/common/sdk/nvidia/inc/class/cl0060.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0060.finn +// Source file: class/cl0060.finn // #define NV0060_SYNC_GPU_BOOST (0x60U) /* finn: Evaluated from "NV0060_ALLOC_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl0070.h b/src/common/sdk/nvidia/inc/class/cl0070.h index c2a8f4ba7a..95d173efd8 100644 --- a/src/common/sdk/nvidia/inc/class/cl0070.h +++ b/src/common/sdk/nvidia/inc/class/cl0070.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0070.finn +// Source file: class/cl0070.finn // #define NV01_MEMORY_VIRTUAL (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl0080.h b/src/common/sdk/nvidia/inc/class/cl0080.h index 7f4bd59e6a..9e9aad27cc 100644 --- a/src/common/sdk/nvidia/inc/class/cl0080.h +++ b/src/common/sdk/nvidia/inc/class/cl0080.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0080.finn +// Source file: class/cl0080.finn // #include "nvlimits.h" diff --git a/src/common/sdk/nvidia/inc/class/cl0092.h b/src/common/sdk/nvidia/inc/class/cl0092.h index 327e0e47cf..3008277f0d 100644 --- a/src/common/sdk/nvidia/inc/class/cl0092.h +++ b/src/common/sdk/nvidia/inc/class/cl0092.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl0092.finn +// Source file: class/cl0092.finn // #include "class/cl0092_callback.h" diff --git a/src/common/sdk/nvidia/inc/class/cl00c1.h b/src/common/sdk/nvidia/inc/class/cl00c1.h index 73fea05643..d95e4fd0c8 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c1.h +++ b/src/common/sdk/nvidia/inc/class/cl00c1.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00c1.finn +// Source file: class/cl00c1.finn // #include "nvlimits.h" diff --git a/src/common/sdk/nvidia/inc/class/cl00c2.h b/src/common/sdk/nvidia/inc/class/cl00c2.h index a5597c56ea..db3ea0008a 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c2.h +++ b/src/common/sdk/nvidia/inc/class/cl00c2.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00c2.finn +// Source file: class/cl00c2.finn // #define NV01_MEMORY_LOCAL_PHYSICAL (0xc2U) /* finn: Evaluated from "NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl00c3.h b/src/common/sdk/nvidia/inc/class/cl00c3.h index 298e582b88..eb9e1cb5d9 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c3.h +++ b/src/common/sdk/nvidia/inc/class/cl00c3.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00c3.finn +// Source file: class/cl00c3.finn // #define NV01_MEMORY_SYNCPOINT (0xc3U) /* finn: Evaluated from "NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl00da.h b/src/common/sdk/nvidia/inc/class/cl00da.h new file mode 100644 index 0000000000..871f913a3e --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl00da.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00da.finn +// + + + +/* +* NV_SEMAPHORE_SURFACE +* A semaphore surface object contains a GPU-and-CPU-accessible memory region +* containing semaphores, associated monitored fence values, and any other +* related data necessary to implement a circular 32-bit or monotonic 64-bit +* incrementing semaphore primitive and associated event delivery. +*/ +#define NV_SEMAPHORE_SURFACE (0xdaU) /* finn: Evaluated from "NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS_MESSAGE_ID" */ + + /* + * NV_SEMAPHORE_SURFACE_WAIT_VALUE + * The notification index used when registering events with the RM event + * subsystem. RM clients should not need to use this value, as they don't + * allocate events against this class themselves. Rather, they specify an + * OS event when registering a CPU waiter, and semaphore surface takes care + * of creating event objects internally as necessary, similar to the event + * buffer record notification OS event mechanism. + */ +#define NV_SEMAPHORE_SURFACE_WAIT_VALUE (0x00000000) + +/* +* NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS +* +* hSemaphoreMem [IN] +* The handle to the memory used for the semaphore value and, when +* supported, the monitored fence/conditional interrupt value. Must be +* accessible by the GPU corresponding to the parent of the semaphore +* surface, as well as the CPU. +* +* hMaxSubmittedMem [IN] +* The handle to the memory used to track the maximum signal value +* submitted to the GPU for processing for a given semaphore slot in +* hSemaphoreMem. This memory is only accessed by the CPU, but must +* support a CPU mapping that allows the use of 64-bit atomic exchange +* operations. This may be the same memory object as hSemaphoreMem if it is +* possible to create one memory object that supports all the requirements +* for a given GPU and CPU. This handle may be omitted/set to zero on GPUs +* that do not require maximum submitted value tracking. +* +* flags [IN] +* Flags affecting the semaphore surface allocation. Currently, there are +* not valid flags, so this value must be set to zero. +*/ +#define NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS_MESSAGE_ID (0x00DAU) + +typedef struct NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS { + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; + NV_DECLARE_ALIGNED(NvU64 flags, 8); +} NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS; + diff --git a/src/common/sdk/nvidia/inc/class/cl00db.h b/src/common/sdk/nvidia/inc/class/cl00db.h index 91791bdfbf..adb5c4f186 100644 --- a/src/common/sdk/nvidia/inc/class/cl00db.h +++ b/src/common/sdk/nvidia/inc/class/cl00db.h @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00db.finn +// Source file: class/cl00db.finn // #define NV40_DEBUG_BUFFER (0xdbU) /* finn: Evaluated from "NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl00f3.h b/src/common/sdk/nvidia/inc/class/cl00f3.h index 09647c32df..09e60b9a83 100644 --- a/src/common/sdk/nvidia/inc/class/cl00f3.h +++ b/src/common/sdk/nvidia/inc/class/cl00f3.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00f3.finn +// Source file: class/cl00f3.finn // diff --git a/src/common/sdk/nvidia/inc/class/cl00f8.h b/src/common/sdk/nvidia/inc/class/cl00f8.h index 096c46c5b6..2cd38d22b7 100644 --- a/src/common/sdk/nvidia/inc/class/cl00f8.h +++ b/src/common/sdk/nvidia/inc/class/cl00f8.h @@ -27,11 +27,14 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00f8.finn +// Source file: class/cl00f8.finn // +#include "nvcfg_sdk.h" + + /* * Class definition for allocating a contiguous or discontiguous FLA. */ @@ -93,6 +96,8 @@ #define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000 #define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000 + + #define NV00F8_ALLOC_FLAGS_DEFAULT 0 #define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0) #define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1) @@ -106,7 +111,7 @@ typedef struct NV00F8_ALLOCATION_PARAMETERS { NV_DECLARE_ALIGNED(NvU64 alignment, 8); NV_DECLARE_ALIGNED(NvU64 allocSize, 8); - NvU32 pageSize; + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); NvU32 allocFlags; struct { diff --git a/src/common/sdk/nvidia/inc/class/cl00fd.h b/src/common/sdk/nvidia/inc/class/cl00fd.h index 5e80d463eb..062b380bb0 100644 --- a/src/common/sdk/nvidia/inc/class/cl00fd.h +++ b/src/common/sdk/nvidia/inc/class/cl00fd.h @@ -31,7 +31,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00fd.finn +// Source file: class/cl00fd.finn // #define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl00fe.h b/src/common/sdk/nvidia/inc/class/cl00fe.h index 464c1ec9ac..581881b982 100644 --- a/src/common/sdk/nvidia/inc/class/cl00fe.h +++ b/src/common/sdk/nvidia/inc/class/cl00fe.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl00fe.finn +// Source file: class/cl00fe.finn // #define NV_MEMORY_MAPPER (0xfeU) /* finn: Evaluated from "NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl2080.h b/src/common/sdk/nvidia/inc/class/cl2080.h index 32b616f597..a85a662328 100644 --- a/src/common/sdk/nvidia/inc/class/cl2080.h +++ b/src/common/sdk/nvidia/inc/class/cl2080.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl2080.finn +// Source file: class/cl2080.finn // #include "nvlimits.h" diff --git a/src/common/sdk/nvidia/inc/class/cl2080_notification.h b/src/common/sdk/nvidia/inc/class/cl2080_notification.h index 81dff11b51..6b3bec7d49 100644 --- a/src/common/sdk/nvidia/inc/class/cl2080_notification.h +++ b/src/common/sdk/nvidia/inc/class/cl2080_notification.h @@ -202,7 +202,8 @@ extern "C" { #define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176) #define NV2080_NOTIFIERS_NVPCF_EVENTS (177) #define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178) -#define NV2080_NOTIFIERS_MAXCOUNT (179) +#define NV2080_NOTIFIERS_VRR_SET_TIMEOUT (179) +#define NV2080_NOTIFIERS_MAXCOUNT (180) // Indexed GR notifier reference #define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) @@ -497,6 +498,10 @@ typedef struct { NvU32 linkId; } Nv2080NvlinkLnkChangeNotification; +typedef struct { + NvU32 head; +} Nv2080VrrSetTimeoutNotification; + #ifdef __cplusplus }; /* extern "C" */ #endif diff --git a/src/common/sdk/nvidia/inc/class/cl2081.h b/src/common/sdk/nvidia/inc/class/cl2081.h index 05341cac1d..2d1cede2ba 100644 --- a/src/common/sdk/nvidia/inc/class/cl2081.h +++ b/src/common/sdk/nvidia/inc/class/cl2081.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl2081.finn +// Source file: class/cl2081.finn // #define NV2081_BINAPI (0x2081U) /* finn: Evaluated from "NV2081_ALLOC_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl2082.h b/src/common/sdk/nvidia/inc/class/cl2082.h index 0a721f57d8..0846209beb 100644 --- a/src/common/sdk/nvidia/inc/class/cl2082.h +++ b/src/common/sdk/nvidia/inc/class/cl2082.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl2082.finn +// Source file: class/cl2082.finn // #define NV2082_BINAPI_PRIVILEGED (0x2082U) /* finn: Evaluated from "NV2082_ALLOC_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl30f1.h b/src/common/sdk/nvidia/inc/class/cl30f1.h index b7edbd2ea3..ffba5e15a1 100644 --- a/src/common/sdk/nvidia/inc/class/cl30f1.h +++ b/src/common/sdk/nvidia/inc/class/cl30f1.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl30f1.finn +// Source file: class/cl30f1.finn // #include "cl30f1_notification.h" diff --git a/src/common/sdk/nvidia/inc/class/cl503b.h b/src/common/sdk/nvidia/inc/class/cl503b.h index b372f78025..79565a19e9 100644 --- a/src/common/sdk/nvidia/inc/class/cl503b.h +++ b/src/common/sdk/nvidia/inc/class/cl503b.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl503b.finn +// Source file: class/cl503b.finn // #define NV50_P2P (0x503bU) /* finn: Evaluated from "NV503B_ALLOC_PARAMETERS_MESSAGE_ID" */ @@ -37,6 +37,19 @@ #define NV503B_FLAGS_P2P_TYPE_GPA 0 #define NV503B_FLAGS_P2P_TYPE_SPA 1 +/* + * NV503B_BAR1_P2P_DMA_INFO + * + * The DMA information for BAR1 P2P, it is only valid for BAR1 P2P. + * dma_address will be set to NV_U64_MAX and dma_size will be set to 0 + * when the DMA info is not available. + * + */ +typedef struct NV503B_BAR1_P2P_DMA_INFO { + NV_DECLARE_ALIGNED(NvU64 dma_address, 8); + NV_DECLARE_ALIGNED(NvU64 dma_size, 8); +} NV503B_BAR1_P2P_DMA_INFO; + /* NvRmAlloc parameters */ #define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU) @@ -54,4 +67,8 @@ typedef struct NV503B_ALLOC_PARAMETERS { NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area * Must have the same value across the GPUs */ NvU32 flags; /* Flag to indicate types/attib of p2p */ + NvU32 subDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID of SubDevice */ + NvU32 peerSubDeviceEgmPeerIdMask; /* Bit mask of EGM peer ID for PeerSubDevice */ + NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO l2pBar1P2PDmaInfo, 8); /* Bar1 DMA info from local GPU to peer GPU */ + NV_DECLARE_ALIGNED(NV503B_BAR1_P2P_DMA_INFO p2lBar1P2PDmaInfo, 8); /* Bar1 DMA info from peer GPU to local GPU */ } NV503B_ALLOC_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl503c.h b/src/common/sdk/nvidia/inc/class/cl503c.h index 7f28960925..6cfeabf36e 100644 --- a/src/common/sdk/nvidia/inc/class/cl503c.h +++ b/src/common/sdk/nvidia/inc/class/cl503c.h @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl503c.finn +// Source file: class/cl503c.finn // #define NV50_THIRD_PARTY_P2P (0x503cU) /* finn: Evaluated from "NV503C_ALLOC_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl5070.h b/src/common/sdk/nvidia/inc/class/cl5070.h index 6a265519d8..9d165145f1 100644 --- a/src/common/sdk/nvidia/inc/class/cl5070.h +++ b/src/common/sdk/nvidia/inc/class/cl5070.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl5070.finn +// Source file: class/cl5070.finn // #include "cl5070_notification.h" diff --git a/src/common/sdk/nvidia/inc/class/cl5080.h b/src/common/sdk/nvidia/inc/class/cl5080.h index cf059456b9..84117582e8 100644 --- a/src/common/sdk/nvidia/inc/class/cl5080.h +++ b/src/common/sdk/nvidia/inc/class/cl5080.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl5080.finn +// Source file: class/cl5080.finn // #include "cl5080_notification.h" diff --git a/src/common/sdk/nvidia/inc/class/cl83de.h b/src/common/sdk/nvidia/inc/class/cl83de.h index df67debead..6491622d78 100644 --- a/src/common/sdk/nvidia/inc/class/cl83de.h +++ b/src/common/sdk/nvidia/inc/class/cl83de.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl83de.finn +// Source file: class/cl83de.finn // #define GT200_DEBUGGER (0x83deU) /* finn: Evaluated from "NV83DE_ALLOC_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl84a0.h b/src/common/sdk/nvidia/inc/class/cl84a0.h index 1ee51ad760..a1f6d90cb3 100644 --- a/src/common/sdk/nvidia/inc/class/cl84a0.h +++ b/src/common/sdk/nvidia/inc/class/cl84a0.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl84a0.finn +// Source file: class/cl84a0.finn // #include "cl84a0_deprecated.h" diff --git a/src/common/sdk/nvidia/inc/class/cl85b5sw.h b/src/common/sdk/nvidia/inc/class/cl85b5sw.h index 63e1160c00..b741d52591 100644 --- a/src/common/sdk/nvidia/inc/class/cl85b5sw.h +++ b/src/common/sdk/nvidia/inc/class/cl85b5sw.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl85b5sw.finn +// Source file: class/cl85b5sw.finn // #define NV85B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0x85b5U) diff --git a/src/common/sdk/nvidia/inc/class/cl9010.h b/src/common/sdk/nvidia/inc/class/cl9010.h index 722277b89b..ad901c789e 100644 --- a/src/common/sdk/nvidia/inc/class/cl9010.h +++ b/src/common/sdk/nvidia/inc/class/cl9010.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9010.finn +// Source file: class/cl9010.finn // #include "class/cl9010_callback.h" diff --git a/src/common/sdk/nvidia/inc/class/cl9072.h b/src/common/sdk/nvidia/inc/class/cl9072.h index 61e134abb3..0d13a8a173 100644 --- a/src/common/sdk/nvidia/inc/class/cl9072.h +++ b/src/common/sdk/nvidia/inc/class/cl9072.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9072.finn +// Source file: class/cl9072.finn // #include "cl9072_notification.h" diff --git a/src/common/sdk/nvidia/inc/class/cl90cd.h b/src/common/sdk/nvidia/inc/class/cl90cd.h index 6c626a6eab..4c732ebd2a 100644 --- a/src/common/sdk/nvidia/inc/class/cl90cd.h +++ b/src/common/sdk/nvidia/inc/class/cl90cd.h @@ -33,7 +33,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl90cd.finn +// Source file: class/cl90cd.finn // #define NV_EVENT_BUFFER (0x90cdU) /* finn: Evaluated from "NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl9170.h b/src/common/sdk/nvidia/inc/class/cl9170.h index 478125f283..64e520cdeb 100644 --- a/src/common/sdk/nvidia/inc/class/cl9170.h +++ b/src/common/sdk/nvidia/inc/class/cl9170.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9170.finn +// Source file: class/cl9170.finn // #define NV9170_DISPLAY (0x9170U) /* finn: Evaluated from "NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl9270.h b/src/common/sdk/nvidia/inc/class/cl9270.h index de3f498941..2cb750f277 100644 --- a/src/common/sdk/nvidia/inc/class/cl9270.h +++ b/src/common/sdk/nvidia/inc/class/cl9270.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9270.finn +// Source file: class/cl9270.finn // #define NV9270_DISPLAY (0x9270U) /* finn: Evaluated from "NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl9470.h b/src/common/sdk/nvidia/inc/class/cl9470.h index faacb955d6..6b0c829d04 100644 --- a/src/common/sdk/nvidia/inc/class/cl9470.h +++ b/src/common/sdk/nvidia/inc/class/cl9470.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9470.finn +// Source file: class/cl9470.finn // #define NV9470_DISPLAY (0x9470U) /* finn: Evaluated from "NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl9570.h b/src/common/sdk/nvidia/inc/class/cl9570.h index 00e6d7fcd9..3197fd85bf 100644 --- a/src/common/sdk/nvidia/inc/class/cl9570.h +++ b/src/common/sdk/nvidia/inc/class/cl9570.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9570.finn +// Source file: class/cl9570.finn // #define NV9570_DISPLAY (0x9570U) /* finn: Evaluated from "NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl9770.h b/src/common/sdk/nvidia/inc/class/cl9770.h index 914838fc4e..9f14281575 100644 --- a/src/common/sdk/nvidia/inc/class/cl9770.h +++ b/src/common/sdk/nvidia/inc/class/cl9770.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9770.finn +// Source file: class/cl9770.finn // #define NV9770_DISPLAY (0x9770U) /* finn: Evaluated from "NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cl9870.h b/src/common/sdk/nvidia/inc/class/cl9870.h index 44b76598f7..3bf548279e 100644 --- a/src/common/sdk/nvidia/inc/class/cl9870.h +++ b/src/common/sdk/nvidia/inc/class/cl9870.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cl9870.finn +// Source file: class/cl9870.finn // #define NV9870_DISPLAY (0x9870U) /* finn: Evaluated from "NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/cla084.h b/src/common/sdk/nvidia/inc/class/cla084.h index 15752d725e..0dd3ca4f52 100644 --- a/src/common/sdk/nvidia/inc/class/cla084.h +++ b/src/common/sdk/nvidia/inc/class/cla084.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/cla084.finn +// Source file: class/cla084.finn // #include "nv_vgpu_types.h" @@ -50,9 +50,10 @@ * save/restore will not be done in host-RM * vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used * for supporting multiple vGPUs per VM. - * numGuestFbHandles -> number of guest memory handles + * hPluginClient -> handle to the plugin client + * numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient * guestFbHandleList -> handle list to guest memory - * hPluginHeapMemory -> plugin heap memory handle + * hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient * bDeviceProfilingEnabled -> If set to true, profiling is allowed */ #define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U) @@ -69,6 +70,7 @@ typedef struct NVA084_ALLOC_PARAMETERS { NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); NvBool bDisableDefaultSmcExecPartRestore; NvU32 vgpuDeviceInstanceId; + NvHandle hPluginClient; NvU32 numGuestFbHandles; NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS]; NvHandle hPluginHeapMemory; diff --git a/src/common/sdk/nvidia/inc/class/clb069sw.h b/src/common/sdk/nvidia/inc/class/clb069sw.h index 840ac79e5f..37e8ad4e95 100644 --- a/src/common/sdk/nvidia/inc/class/clb069sw.h +++ b/src/common/sdk/nvidia/inc/class/clb069sw.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clb069sw.finn +// Source file: class/clb069sw.finn // #define NVB069_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb069U) diff --git a/src/common/sdk/nvidia/inc/class/clb0b5sw.h b/src/common/sdk/nvidia/inc/class/clb0b5sw.h index ff18931684..06fba1146b 100644 --- a/src/common/sdk/nvidia/inc/class/clb0b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clb0b5sw.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clb0b5sw.finn +// Source file: class/clb0b5sw.finn // diff --git a/src/common/sdk/nvidia/inc/class/clb2cc.h b/src/common/sdk/nvidia/inc/class/clb2cc.h index e539404fec..f3ba26f06d 100644 --- a/src/common/sdk/nvidia/inc/class/clb2cc.h +++ b/src/common/sdk/nvidia/inc/class/clb2cc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clb2cc.finn +// Source file: class/clb2cc.finn // #include "clb0cc.h" diff --git a/src/common/sdk/nvidia/inc/class/clc0b5sw.h b/src/common/sdk/nvidia/inc/class/clc0b5sw.h index dc5bc41331..01ebd0509d 100644 --- a/src/common/sdk/nvidia/inc/class/clc0b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc0b5sw.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc0b5sw.finn +// Source file: class/clc0b5sw.finn // diff --git a/src/common/sdk/nvidia/inc/class/clc1b5sw.h b/src/common/sdk/nvidia/inc/class/clc1b5sw.h index 27af6f2056..08da246ca4 100644 --- a/src/common/sdk/nvidia/inc/class/clc1b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc1b5sw.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc1b5sw.finn +// Source file: class/clc1b5sw.finn // diff --git a/src/common/sdk/nvidia/inc/class/clc370.h b/src/common/sdk/nvidia/inc/class/clc370.h index 4f6bf4b446..762ecf0e2a 100644 --- a/src/common/sdk/nvidia/inc/class/clc370.h +++ b/src/common/sdk/nvidia/inc/class/clc370.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc370.finn +// Source file: class/clc370.finn // #include "clc370_notification.h" diff --git a/src/common/sdk/nvidia/inc/class/clc370_notification.h b/src/common/sdk/nvidia/inc/class/clc370_notification.h index e0c8867313..c94556e981 100644 --- a/src/common/sdk/nvidia/inc/class/clc370_notification.h +++ b/src/common/sdk/nvidia/inc/class/clc370_notification.h @@ -32,8 +32,7 @@ extern "C" { /* event values */ #define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW #define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT -#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0) -#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1) +#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_BEGIN + (0) #define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1) #define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1) diff --git a/src/common/sdk/nvidia/inc/class/clc3b5sw.h b/src/common/sdk/nvidia/inc/class/clc3b5sw.h index b91398493c..518883c65f 100644 --- a/src/common/sdk/nvidia/inc/class/clc3b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc3b5sw.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc3b5sw.finn +// Source file: class/clc3b5sw.finn // diff --git a/src/common/sdk/nvidia/inc/class/clc570.h b/src/common/sdk/nvidia/inc/class/clc570.h index 0e562ab301..461736bde4 100644 --- a/src/common/sdk/nvidia/inc/class/clc570.h +++ b/src/common/sdk/nvidia/inc/class/clc570.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc570.finn +// Source file: class/clc570.finn // #define NVC570_DISPLAY (0xc570U) /* finn: Evaluated from "NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/clc574.h b/src/common/sdk/nvidia/inc/class/clc574.h index 4587c7add9..077a57fa05 100644 --- a/src/common/sdk/nvidia/inc/class/clc574.h +++ b/src/common/sdk/nvidia/inc/class/clc574.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc574.finn +// Source file: class/clc574.finn // #define UVM_CHANNEL_RETAINER (0xc574U) /* finn: Evaluated from "NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/clc58b.h b/src/common/sdk/nvidia/inc/class/clc58b.h index 7dba2c63e7..4972f04c94 100644 --- a/src/common/sdk/nvidia/inc/class/clc58b.h +++ b/src/common/sdk/nvidia/inc/class/clc58b.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc58b.finn +// Source file: class/clc58b.finn // #define TURING_VMMU_A (0xc58bU) /* finn: Evaluated from "TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/clc5b5sw.h b/src/common/sdk/nvidia/inc/class/clc5b5sw.h index 0295824e61..12b3cc00de 100644 --- a/src/common/sdk/nvidia/inc/class/clc5b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc5b5sw.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc5b5sw.finn +// Source file: class/clc5b5sw.finn // diff --git a/src/common/sdk/nvidia/inc/class/clc637.h b/src/common/sdk/nvidia/inc/class/clc637.h index 65bed26620..2f8ec0ce14 100644 --- a/src/common/sdk/nvidia/inc/class/clc637.h +++ b/src/common/sdk/nvidia/inc/class/clc637.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc637.finn +// Source file: class/clc637.finn // #define AMPERE_SMC_PARTITION_REF (0xc637U) /* finn: Evaluated from "NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/clc638.h b/src/common/sdk/nvidia/inc/class/clc638.h index 73b3fda33e..fc038b34b6 100644 --- a/src/common/sdk/nvidia/inc/class/clc638.h +++ b/src/common/sdk/nvidia/inc/class/clc638.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc638.finn +// Source file: class/clc638.finn // #define AMPERE_SMC_EXEC_PARTITION_REF (0xc638U) /* finn: Evaluated from "NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/clc639.h b/src/common/sdk/nvidia/inc/class/clc639.h index d589de7f63..538ede0de1 100644 --- a/src/common/sdk/nvidia/inc/class/clc639.h +++ b/src/common/sdk/nvidia/inc/class/clc639.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc639.finn +// Source file: class/clc639.finn // #define AMPERE_SMC_CONFIG_SESSION (0xc639U) /* finn: Evaluated from "NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/clc640.h b/src/common/sdk/nvidia/inc/class/clc640.h index 214a45cabf..885a5015f7 100644 --- a/src/common/sdk/nvidia/inc/class/clc640.h +++ b/src/common/sdk/nvidia/inc/class/clc640.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc640.finn +// Source file: class/clc640.finn // #define AMPERE_SMC_MONITOR_SESSION (0xc640U) /* finn: Evaluated from "NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/clc670.h b/src/common/sdk/nvidia/inc/class/clc670.h index e46194d6da..482865143e 100644 --- a/src/common/sdk/nvidia/inc/class/clc670.h +++ b/src/common/sdk/nvidia/inc/class/clc670.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc670.finn +// Source file: class/clc670.finn // #define NVC670_DISPLAY (0xc670U) /* finn: Evaluated from "NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/class/clc6b5sw.h b/src/common/sdk/nvidia/inc/class/clc6b5sw.h index 7a928aa66b..2b41bdfcbf 100644 --- a/src/common/sdk/nvidia/inc/class/clc6b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc6b5sw.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc6b5sw.finn +// Source file: class/clc6b5sw.finn // diff --git a/src/common/sdk/nvidia/inc/class/clc770.h b/src/common/sdk/nvidia/inc/class/clc770.h index 4f6691680a..87580e546d 100644 --- a/src/common/sdk/nvidia/inc/class/clc770.h +++ b/src/common/sdk/nvidia/inc/class/clc770.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: class/clc770.finn +// Source file: class/clc770.finn // #define NVC770_DISPLAY (0xc770U) /* finn: Evaluated from "NVC770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h b/src/common/sdk/nvidia/inc/class/clcb33.h similarity index 56% rename from src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h rename to src/common/sdk/nvidia/inc/class/clcb33.h index 100a61262e..c0e19346f5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h +++ b/src/common/sdk/nvidia/inc/class/clcb33.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,35 +23,18 @@ #pragma once +#include + // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080rc.finn +// Source file: class/clcb33.finn // -#include "ctrl/ctrl0080/ctrl0080base.h" - -/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */ +#define NV_CONFIDENTIAL_COMPUTE (0xcb33U) /* finn: Evaluated from "NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS_MESSAGE_ID" */ -/* - * NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK - * - * This command prevents RM from using callbacks when resetting a channel due - * to a page fault. - * - * Possible status return values are: - * NV_OK - */ -#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */ +#define NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS_MESSAGE_ID (0xcb33U) -/* - * NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK - * - * This command permits RM to use callbacks when resetting a channel due - * to a page fault. - * - * Possible status return values are: - * NV_OK - */ -#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */ +typedef struct NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS { + NvHandle hClient; +} NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS; -/* _ctrl0080rc_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clcba2.h b/src/common/sdk/nvidia/inc/class/clcba2.h new file mode 100644 index 0000000000..92326386a1 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clcba2.h @@ -0,0 +1,140 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvtypes.h" + +#ifndef _clcba2_h_ +#define _clcba2_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HOPPER_SEC2_WORK_LAUNCH_A (0x0000CBA2) + +typedef volatile struct _clcba2_tag0 { + NvV32 Reserved00[0x100]; + NvV32 DecryptCopySrcAddrHi; // 0x00000400 - 0x00000403 + NvV32 DecryptCopySrcAddrLo; // 0x00000404 - 0x00000407 + NvV32 DecryptCopyDstAddrHi; // 0x00000408 - 0x0000040B + NvV32 DecryptCopyDstAddrLo; // 0x0000040c - 0x0000040F + NvU32 DecryptCopySize; // 0x00000410 - 0x00000413 + NvU32 DecryptCopyAuthTagAddrHi; // 0x00000414 - 0x00000417 + NvU32 DecryptCopyAuthTagAddrLo; // 0x00000418 - 0x0000041B + NvV32 DigestAddrHi; // 0x0000041C - 0x0000041F + NvV32 DigestAddrLo; // 0x00000420 - 0x00000423 + NvV32 Reserved01[0x7]; + NvV32 SemaphoreA; // 0x00000440 - 0x00000443 + NvV32 SemaphoreB; // 0x00000444 - 0x00000447 + NvV32 SemaphoreSetPayloadLower; // 0x00000448 - 0x0000044B + NvV32 SemaphoreSetPayloadUppper; // 0x0000044C - 0x0000044F + NvV32 SemaphoreD; // 0x00000450 - 0x00000453 + NvU32 Reserved02[0x7]; + NvV32 Execute; // 0x00000470 - 0x00000473 + NvV32 Reserved03[0x23]; +} NVCBA2_HOPPER_SEC2_WORK_LAUNCH_AControlPio; + +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI (0x00000400) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO (0x00000404) +#define NVCBA2_DECRYPT_COPY_SRC_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI (0x00000408) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO (0x0000040c) +#define NVCBA2_DECRYPT_COPY_DST_ADDR_LO_DATA 31:4 +#define NVCBA2_DECRYPT_COPY_SIZE (0x00000410) +#define NVCBA2_DECRYPT_COPY_SIZE_DATA 31:2 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI (0x00000414) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO (0x00000418) +#define NVCBA2_DECRYPT_COPY_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI (0x0000041C) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_HI_DATA 24:0 +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO (0x00000420) +#define NVCBA2_METHOD_STREAM_AUTH_TAG_ADDR_LO_DATA 31:4 +#define NVCBA2_SEMAPHORE_A (0x00000440) +#define NVCBA2_SEMAPHORE_A_UPPER 24:0 +#define NVCBA2_SEMAPHORE_B (0x00000444) +#define NVCBA2_SEMAPHORE_B_LOWER 31:2 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER (0x00000448) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_LOWER_DATA 31:0 +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000044C) +#define NVCBA2_SET_SEMAPHORE_PAYLOAD_UPPER_DATA 31:0 +#define NVCBA2_SEMAPHORE_D (0x00000450) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR 0:0 +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE 1:1 +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_SEMAPHORE_D_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP 2:2 +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_SEMAPHORE_D_TIMESTAMP_ENABLE (0x00000001) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE 3:3 +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE (0x00000470) +#define NVCBA2_EXECUTE_NOTIFY 0:0 +#define NVCBA2_EXECUTE_NOTIFY_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_ON 1:1 +#define NVCBA2_EXECUTE_NOTIFY_ON_END (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_ON_BEGIN (0x00000001) +#define NVCBA2_EXECUTE_FLUSH_DISABLE 2:2 +#define NVCBA2_EXECUTE_FLUSH_DISABLE_FALSE (0x00000000) +#define NVCBA2_EXECUTE_FLUSH_DISABLE_TRUE (0x00000001) +#define NVCBA2_EXECUTE_NOTIFY_INTR 3:3 +#define NVCBA2_EXECUTE_NOTIFY_INTR_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_NOTIFY_INTR_ENABLE (0x00000001) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE 4:4 +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_32_BIT (0x00000000) +#define NVCBA2_EXECUTE_PAYLOAD_SIZE_64_BIT (0x00000001) +#define NVCBA2_EXECUTE_TIMESTAMP 5:5 +#define NVCBA2_EXECUTE_TIMESTAMP_DISABLE (0x00000000) +#define NVCBA2_EXECUTE_TIMESTAMP_ENABLE (0x00000001) + +// Class definitions +#define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024) + +// Errors +#define NVCBA2_ERROR_NONE (0x00000000) +#define NVCBA2_ERROR_DECRYPT_COPY_SRC_ADDR_MISALIGNED_POINTER (0x00000001) +#define NVCBA2_ERROR_DECRYPT_COPY_DEST_ADDR_MISALIGNED_POINTER (0x00000002) +#define NVCBA2_ERROR_DECRYPT_COPY_AUTH_TAG_ADDR_MISALIGNED_POINTER (0x00000003) +#define NVCBA2_ERROR_DECRYPT_COPY_DMA_NACK (0x00000004) +#define NVCBA2_ERROR_DECRYPT_COPY_AUTH_TAG_MISMATCH (0x00000005) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_MISALIGNED_POINTER (0x00000006) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_ADDR_DMA_NACK (0x00000007) +#define NVCBA2_ERROR_METHOD_STREAM_AUTH_TAG_CHECK_FAILURE (0x00000008) +#define NVCBA2_ERROR_MISALIGNED_SIZE (0x00000009) +#define NVCBA2_ERROR_MISSING_METHODS (0x0000000A) +#define NVCBA2_ERROR_SEMAPHORE_RELEASE_DMA_NACK (0x0000000B) +#define NVCBA2_ERROR_DECRYPT_SIZE_MAX_EXCEEDED (0x0000000C) +#define NVCBA2_ERROR_OS_APPLICATION (0x0000000D) +#define NVCBA2_ERROR_INVALID_CTXSW_REQUEST (0x0000000E) +#define NVCBA2_ERROR_BUFFER_OVERFLOW (0x0000000F) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clcba2_h diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h index 89e2219665..6f49405ed5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000base.finn +// Source file: ctrl/ctrl0000/ctrl0000base.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h index a05add6637..6545c7ee8d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000client.finn +// Source file: ctrl/ctrl0000/ctrl0000client.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h index 9b72f207b1..a41da832d9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000diag.finn +// Source file: ctrl/ctrl0000/ctrl0000diag.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h index 1679f841df..a03733d4e1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000event.finn +// Source file: ctrl/ctrl0000/ctrl0000event.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h index f62b504d63..021996719a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000gpu.finn +// Source file: ctrl/ctrl0000/ctrl0000gpu.finn // #include "ctrl/ctrl0000/ctrl0000base.h" @@ -143,7 +143,8 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS { * GPU instance numbers are assigned in bus-probe order beginning with * zero and are limited to one less the number of GPUs in the system. * [out] numaId - * This parameter returns the ID of NUMA node for the specified GPU. + * This parameter returns the ID of NUMA node for the specified GPU or + * the subscribed MIG partition when MIG is enabled. * In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned. * * Possible status values returned are: diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h index 6f8ff132b1..f38c9c3154 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn +// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h index 2df6c426bc..fae2cf92fd 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000gsync.finn +// Source file: ctrl/ctrl0000/ctrl0000gsync.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h index 41a4954f3a..a52be2a374 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000nvd.finn +// Source file: ctrl/ctrl0000/ctrl0000nvd.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h index 9a48202ff8..70ff0eb2ef 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000proc.finn +// Source file: ctrl/ctrl0000/ctrl0000proc.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h index b8e921e4ac..1ca299f80d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn +// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h index c98c725de1..c1ad015ec3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000system.finn +// Source file: ctrl/ctrl0000/ctrl0000system.finn // #include "ctrl/ctrlxxxx.h" @@ -296,8 +296,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { /* Generic types */ #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) - - +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) /* processor capabilities */ #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) @@ -322,47 +321,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { #define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) #define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) -/* feature mask (as opposed to bugs, requirements, etc.) */ -#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */ - -/* - * NV0000_CTRL_CMD_SYSTEM_GET_CAPS - * - * This command returns the set of system capabilities in the - * form of an array of unsigned bytes. System capabilities include - * supported features and required workarounds for the system, - * each represented by a byte offset into the table and a bit - * position within that byte. - * - * capsTblSize - * This parameter specifies the size in bytes of the caps table. - * This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE. - * capsTbl - * This parameter specifies a pointer to the client's caps table buffer - * into which the system caps bits will be transferred by the RM. - * The caps table is an array of unsigned bytes. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_PARAM_STRUCT - * NV_ERR_INVALID_ARGUMENT - */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */ - -typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { - NvU32 capsTblSize; - NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); -} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS; - -/* extract cap bit setting from tbl */ -#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) - -/* caps format is byte_index:bit_mask */ -#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01 - -/* size in bytes of system caps table */ -#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U - /* * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO * @@ -419,13 +377,13 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_OPERATING_SYSTEM */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ /* maximum name string length */ -#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) +#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) /* invalid id */ -#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) +#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) #define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) @@ -1572,9 +1530,11 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { * Please note: as implied above, administrator privileges are * required to modify security settings. */ -#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */ +#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */ #define GPS_MAX_COUNTERS_PER_BLOCK 32U +#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U) + typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { NvU32 objHndl; NvU32 blockId; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h index d55703d657..17c4bdbcfb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000unix.finn +// Source file: ctrl/ctrl0000/ctrl0000unix.finn // #include "ctrl/ctrl0000/ctrl0000base.h" @@ -418,8 +418,7 @@ typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS { #define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1 #define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2 #define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3 - - +#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC 4 #define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h index 671c1a32a5..a8def9dbc1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn +// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn // #include "ctrl/ctrl0000/ctrl0000base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h index 046c931942..44f5279ad2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0002.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0002.finn +// Source file: ctrl/ctrl0002.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h index 91431cee5c..05bb88f3d3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0004.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0004.finn +// Source file: ctrl/ctrl0004.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h index ecabf33505..3f70c7d4eb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl000f.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl000f.finn +// Source file: ctrl/ctrl000f.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h index 60f6684640..257db3af2d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0020.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0020.finn +// Source file: ctrl/ctrl0020.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h b/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h index 880fcc8ca0..0858c065b9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl003e.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl003e.finn +// Source file: ctrl/ctrl003e.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h index 8d9da81ff2..4ccdb8f636 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0041.finn +// Source file: ctrl/ctrl0041.finn // #include "nvos.h" @@ -378,7 +378,7 @@ typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS { #define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U) typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS { - NvU32 pageSize; /* [out] - page size */ + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); /* [out] - page size */ } NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS; /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0050.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0050.h new file mode 100644 index 0000000000..6e56268902 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0050.h @@ -0,0 +1,180 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0050.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV0050_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x0050, NV0050_CTRL_##cat, idx) + +#define NV0050_CTRL_RESERVED (0x00U) +#define NV0050_CTRL_MEMORY (0x01U) + +#define NV0050_CTRL_CMD_NULL (0x5000U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV0050_CTRL_CMD_MEMSET + * + * Memsets a memory allocation and releases a semaphore on completion. + * + * hMemory [IN] + * Memory handle of the memory descriptor that needs to be memset. + * This is only available for verification purposes. + * + * offset [IN] + * Offset into the memory descriptor. + * + * length [IN] + * Length of physical memory to be memset. + * Must be less than or equal to memory size. + * + * pattern [IN] + * The pattern to memset to + * + * flags [IN] + * Can be any of the NV0050_CTRL_MEMSET_FLAGS_* + * DEFAULT + * By default, the memcopy operation will be synchronous and using + * physical copies + * ASYNC + * This flag forces this memset to be asynchronous. + * VIRTUAL + * This flag forces the memset to use Virtual addresses which are + * identity mapped. To use this feature, users need to pass in the + * hVaspace with identity mapped addresses for the entire memory during + * construct. + * + * submittedWorkId [OUT] + * The work submission token users can poll on to wait for work + * completed by CE. Only valid in case of ASYNC mode. + */ + +#define NV0050_CTRL_MEMSET_FLAGS_DEFAULT 0 +#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0) +#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1) + +#define NV0050_CTRL_CMD_MEMSET (0x500101U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8) | NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID" */ + +#define NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0050_CTRL_MEMSET_PARAMS { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NvU32 pattern; + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); +} NV0050_CTRL_MEMSET_PARAMS; + +/* + * NV0050_CTRL_CMD_MEMCOPY + * + * Copies from a source memoryto ssdestination memory and releases a semaphore + * on completion + * + * hDstMemory [IN] + * Memory handle of the memory descriptor to which data will be copied. + * This is only available for verification purposes. + * + * hSrcMemory [IN] + * Memory handle of the memory descriptor from which data will be copied. + * This is only available for verification purposes. + * + * dstOfffset [IN] + * Offset into the destination memory descriptor. + * + * srcOffset [IN] + * Offset into the source memory descriptor. + * + * length [IN] + * Length of physical memory to be copied. + * Must be less than or equal to both destination and source memory size. + * + * flags [IN] + * Can be any of the NV0050_CTRL_MEMCOPY_FLAGS_* + * DEFAULT + * By default, the memcopy operation will be synchronous and using + * physical copies + * ASYNC + * This flag forces this memset to be asynchronous. + * VIRTUAL + * This flag forces the memset to use Virtual addresses which are + * identity mapped. To use this feature, users need to pass in the + * hVaspace with identity mapped addresses for the entire memory during + * construct. + * + * submittedWorkId [OUT] + * The work submission token users can poll on to wait for work + * completed by CE. Only valid in case of ASYNC mode. + */ + +#define NV0050_CTRL_MEMCOPY_FLAGS_DEFAULT 0 +#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(1) +#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(2) + +#define NV0050_CTRL_CMD_MEMCOPY (0x500102U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID)" */ + +#define NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0050_CTRL_MEMCOPY_PARAMS { + NvHandle hDstMemory; + NvHandle hSrcMemory; + NV_DECLARE_ALIGNED(NvU64 dstOffset, 8); + NV_DECLARE_ALIGNED(NvU64 srcOffset, 8); + NV_DECLARE_ALIGNED(NvU64 length, 8); + NV_DECLARE_ALIGNED(NvU64 flags, 8); + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); +} NV0050_CTRL_MEMCOPY_PARAMS; + +/* + * NV0050_CTRL_CMD_CHECK_PROGRESS + * + * Check if a previously submitted work item has been completed by HW. + * + * submittedWorkId [IN] + * The work submission token users can poll on to wait for work + * completed by CE. + * + */ +#define NV0050_CTRL_CHECK_PROGRESS_RESULT_DEFAULT 0 +#define NV0050_CTRL_CHECK_PROGRESS_RESULT_FINISHED NVBIT(1) + +#define NV0050_CTRL_CMD_CHECK_PROGRESS (0x500103U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID)" */ + +#define NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0050_CTRL_CHECK_PROGRESS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8); + NvU32 result; +} NV0050_CTRL_CHECK_PROGRESS_PARAMS; + +/* _ctrl0050_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h index 6b2df39d21..9987bae3d9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073.finn +// Source file: ctrl/ctrl0073.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h index 3712f9f9d2..1f687aafcd 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073base.finn +// Source file: ctrl/ctrl0073/ctrl0073base.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h index 374cbb5b3e..4b39094270 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h @@ -23,11 +23,49 @@ #pragma once +#include + // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073common.finn +// Source file: ctrl/ctrl0073/ctrl0073common.finn // +/* + * DSC caps - + * bDscSupported + * If GPU supports DSC or not + * + * encoderColorFormatMask + * Mask of all color formats for which DSC + * encoding is supported by GPU + * + * lineBufferSizeKB + * Size of line buffer. + * + * rateBufferSizeKB + * Size of rate buffer per slice. + * + * bitsPerPixelPrecision + * Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp + * + * maxNumHztSlices + * Maximum number of horizontal slices supported by DSC encoder + * + * lineBufferBitDepth + * Bit depth used by the GPU to store the reconstructed pixels within + * the line buffer + */ +#define NV0073_CTRL_CMD_DSC_CAP_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS { + NvBool bDscSupported; + NvU32 encoderColorFormatMask; + NvU32 lineBufferSizeKB; + NvU32 rateBufferSizeKB; + NvU32 bitsPerPixelPrecision; + NvU32 maxNumHztSlices; + NvU32 lineBufferBitDepth; +} NV0073_CTRL_CMD_DSC_CAP_PARAMS; /* _ctrl0073common_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h index 207a859109..7195070e39 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -27,10 +27,13 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073dfp.finn +// Source file: ctrl/ctrl0073/ctrl0073dfp.finn // #include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073common.h" + +#include "nvcfg_sdk.h" /* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ @@ -84,8 +87,7 @@ * This specifies whether the displayId is capable of sending * YCBCR444 color format out from the board. * NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH - * This specifies whether the displayId is capable of doing high - * bit-rate (2.7Gbps) or low bit-rate (1.62Gbps) if the DFP is + * This specifies max link rate supported by the displayId, if the DFP is * display port. * NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED * This specifies whether the DFP displayId is allowed to transmit HDMI @@ -105,6 +107,8 @@ * This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode). * NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE * This indicates whether this DFP supports Dynamic MUX + * flags2 + * This parameter returns the extra information specific to this dfp. * * Possible status values returned are: * NV_OK @@ -119,76 +123,77 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 flags; + NvU32 flags2; } NV0073_CTRL_DFP_GET_INFO_PARAMS; /* valid display types */ #define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) -#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) #define NV0073_CTRL_DFP_FLAGS_LANE 5:3 -#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) -#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) -#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) #define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 -#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 -#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 -#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 -#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 -#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 -#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 -#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 -#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 -#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) -#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) #define NV0073_CTRL_DFP_FLAGS_LINK 21:20 -#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 -#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 -#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) -#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) -#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) +#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 -#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) #define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 -#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) -#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) +#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) @@ -569,7 +574,7 @@ typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO { * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable. * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'. * - * Possible status values returned are: + * Possible status values returned are: * NV_OK * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED @@ -1157,40 +1162,31 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { #define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U) typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { - NvU32 subDeviceInstance; - NvU32 displayId; - NvU32 hActive; - NvU32 vActive; - NvU32 hFrontPorch; - NvU32 vFrontPorch; - NvU32 hBackPorch; - NvU32 vBackPorch; - NvU32 hSyncWidth; - NvU32 vSyncWidth; - NvU32 bpp; - NvU32 refresh; - NvU32 pclkHz; - NvU32 numLanes; - NvU32 dscEnable; - NvU32 dscBpp; - NvU32 dscNumSlices; - NvU32 dscDualDsc; - NvU32 dscSliceHeight; - NvU32 dscBlockPrediction; - NvU32 dscDecoderVersionMajor; - NvU32 dscDecoderVersionMinor; - NvBool dscUseCustomPPS; - NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; - - struct { - NvBool bDscSupported; - NvU32 encoderColorFormatMask; - NvU32 lineBufferSizeKB; - NvU32 rateBufferSizeKB; - NvU32 bitsPerPixelPrecision; - NvU32 maxNumHztSlices; - NvU32 lineBufferBitDepth; - } dscEncoderCaps; + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 hActive; + NvU32 vActive; + NvU32 hFrontPorch; + NvU32 vFrontPorch; + NvU32 hBackPorch; + NvU32 vBackPorch; + NvU32 hSyncWidth; + NvU32 vSyncWidth; + NvU32 bpp; + NvU32 refresh; + NvU32 pclkHz; + NvU32 numLanes; + NvU32 dscEnable; + NvU32 dscBpp; + NvU32 dscNumSlices; + NvU32 dscDualDsc; + NvU32 dscSliceHeight; + NvU32 dscBlockPrediction; + NvU32 dscDecoderVersionMajor; + NvU32 dscDecoderVersionMinor; + NvBool dscUseCustomPPS; + NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; + NV0073_CTRL_CMD_DSC_CAP_PARAMS dscEncoderCaps; } NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h index 16da22d179..441b2721f9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -27,10 +27,13 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073dp.finn +// Source file: ctrl/ctrl0073/ctrl0073dp.finn // #include "ctrl/ctrl0073/ctrl0073base.h" +#include "ctrl/ctrl0073/ctrl0073common.h" + +#include "nvcfg_sdk.h" /* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ @@ -1766,29 +1769,7 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS { * bOverrideLinkBw * Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE * - * DSC caps - - * bDscSupported - * If GPU supports DSC or not - * - * encoderColorFormatMask - * Mask of all color formats for which DSC - * encoding is supported by GPU - * - * lineBufferSizeKB - * Size of line buffer. - * - * rateBufferSizeKB - * Size of rate buffer per slice. - * - * bitsPerPixelPrecision - * Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp - * - * maxNumHztSlices - * Maximum number of horizontal slices supported by DSC encoder - * - * lineBufferBitDepth - * Bit depth used by the GPU to store the reconstructed pixels within - * the line buffer + * DSC caps * * Possible status values returned are: * NV_OK @@ -1802,28 +1783,20 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS { #define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { - NvU32 subDeviceInstance; - NvU32 sorIndex; - NvU32 maxLinkRate; - NvU32 dpVersionsSupported; - NvBool bIsMultistreamSupported; - NvBool bIsSCEnabled; - NvBool bHasIncreasedWatermarkLimits; - NvBool bIsPC2Disabled; - NvBool isSingleHeadMSTSupported; - NvBool bFECSupported; - NvBool bIsTrainPhyRepeater; - NvBool bOverrideLinkBw; - - struct { - NvBool bDscSupported; - NvU32 encoderColorFormatMask; - NvU32 lineBufferSizeKB; - NvU32 rateBufferSizeKB; - NvU32 bitsPerPixelPrecision; - NvU32 maxNumHztSlices; - NvU32 lineBufferBitDepth; - } DSC; + NvU32 subDeviceInstance; + NvU32 sorIndex; + NvU32 maxLinkRate; + NvU32 dpVersionsSupported; + NvU32 UHBRSupported; + NvBool bIsMultistreamSupported; + NvBool bIsSCEnabled; + NvBool bHasIncreasedWatermarkLimits; + NvBool bIsPC2Disabled; + NvBool isSingleHeadMSTSupported; + NvBool bFECSupported; + NvBool bIsTrainPhyRepeater; + NvBool bOverrideLinkBw; + NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC; } NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 @@ -1834,7 +1807,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) - #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) @@ -1842,6 +1814,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) + #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h index 1ac3e6fece..04aeead300 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073dpu.finn +// Source file: ctrl/ctrl0073/ctrl0073dpu.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h index a2423a888f..22ce085e9d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h @@ -27,6 +27,104 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073event.finn +// Source file: ctrl/ctrl0073/ctrl0073event.finn // +#include "ctrl/ctrl0073/ctrl0073base.h" + +/* NV04_DISPLAY_COMMON event-related control commands and parameters */ + +/* + * NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated display + * object. This command requires that an instance of NV01_EVENT has been + * previously bound to the associated display object. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * hEvent + * This parameter specifies the handle of the NV01_EVENT instance + * to be bound to the given subDeviceInstance. + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NV0073_NOTIFIERS value (see cl0073.h for more details) and should + * not exceed one less NV0073_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NV0073_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NV0073_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NV0073_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION (0x730301U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 subDeviceInstance; + NvHandle hEvent; + NvU32 event; + NvU32 action; +} NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS; + +/* valid action values */ +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000U) +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U) +#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U) + +/* + * NV0073_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY + * + * hMemory + * This parameter specifies the handle of the memory object + * that identifies the memory address translation for this + * subdevice instance's notification(s). The beginning of the + * translation points to an array of notification data structures. + * The size of the translation must be at least large enough to hold the + * maximum number of notification data structures identified by + * the NV0073_MAX_NOTIFIERS value. + * Legal argument values must be instances of the following classes: + * NV01_NULL + * NV04_MEMORY + * When hMemory specifies the NV01_NULL_OBJECT value then any existing + * memory translation connection is cleared. There must not be any + * pending notifications when this command is issued. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NV0073_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x730303U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS { + NvU32 subDeviceInstance; + NvHandle hMemory; +} NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS; + +#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0U +#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1U +#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2U + +/* _ctrl0073event_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h index b4c3764f92..bc419e1e6b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073internal.finn +// Source file: ctrl/ctrl0073/ctrl0073internal.finn // #include "ctrl/ctrl0073/ctrl0073base.h" @@ -37,4 +37,10 @@ typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS; +#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE (0x730402U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x2U) + +typedef NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS; + /* ctrl0073internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h index 6b34b2460a..aec32e0ab8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073psr.finn +// Source file: ctrl/ctrl0073/ctrl0073psr.finn // #include "ctrl/ctrl0073/ctrl0073base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h index 6b7d8433a3..00698b7da6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073specific.finn +// Source file: ctrl/ctrl0073/ctrl0073specific.finn // #include "ctrl/ctrl0073/ctrl0073base.h" @@ -1274,6 +1274,10 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS { * powerState * This parameter should be one of the valid * NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_* values. + * headIdx + * The head id on which power operation needs to be done. + * bForceMonitorState + * Monitor power state that client wants to force in RM. * * Possible status values returned are: * NV_OK @@ -1285,9 +1289,11 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS { #define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID (0x95U) typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS { - NvU32 subDeviceInstance; - NvU32 displayId; - NvU32 powerState; + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 powerState; + NvU32 headIdx; + NvBool bForceMonitorState; } NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS; #define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_OFF (0x00000000U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h index d1bfd271ee..2270565fd5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073stereo.finn +// Source file: ctrl/ctrl0073/ctrl0073stereo.finn // #include "ctrl/ctrl0073/ctrl0073base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h index 08a06ae723..0c93979fd8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073svp.finn +// Source file: ctrl/ctrl0073/ctrl0073svp.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h index a011bb4f8a..bd3c3ac52c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0073/ctrl0073system.finn +// Source file: ctrl/ctrl0073/ctrl0073system.finn // #include "ctrl/ctrl0073/ctrl0073base.h" @@ -809,6 +809,42 @@ typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS { NvU32 availableInternalDisplaysMask; } NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS; +/* + * NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED + * + * This command is used to notify RM that all subdevices are ready for ACPI + * calls. The caller must make sure that the OS is ready to handle the ACPI + * calls for each ACPI ID. So, this call must be done after the OS has + * initialized all the display ACPI IDs to this subdevice. + * Besides, the ACPI spec provides a function for the display drivers to read + * the EDID directly from the SBIOS for each display's ACPI ID. This function + * is used to override the EDID found from a I2C or DPAux based transaction. + * This command will also attempt to call the ACPI _DDC function to read the + * EDID from the SBIOS for all displayIDs. If an EDID is found from this call, + * the RM will store that new EDID in the EDID buffer of that OD. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID (0x5CU) + +typedef struct NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS { + NvU32 subDeviceInstance; +} NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS; + +#define NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED (0x73015cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID" */ + /* * NV0073_CTRL_SYSTEM_CONNECTOR_INFO @@ -1229,6 +1265,36 @@ typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { +/* +* NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS +* +* This command is used to update information about VRR capable monitors +* subDeviceInstance +* This parameter specifies the subdevice instance within the +* NV04_DISPLAY_COMMON parent device to which the operation should be +* directed.This parameter must specify a value between zero and the +* total number of subdevices within the parent device.This parameter +* should be set to zero for default behavior. +* +* displayId +* DisplayId of the panel for which client wants to add or remove from VRR +* capable monitor list +* +* bAddition +* When set to NV_TRUE, signifies that the vrr monitor is to be added. +* When set to NV_FALSE, signifies that the vrr monitor is to be removed. +* +*/ +#define NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO (0x730185U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bAddition; +} NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS; + /* * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE * @@ -1670,5 +1736,60 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS { NvBool bIsSidebandSrSupported; } NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS; +/* + * NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE + * + * This command is used by client like nvkms to set up the VRR specific + * memory operation in RM such as mapping the client created shared memory + * into RM and reserving a RGline for processing of self-refresh timeout + * related calculations. + * + * Also the expectation is that the client which calls this command with parameter + * bEnable = TRUE, should also call this command with bEnable = FALSE on the + * same head when VRR needs to be disabled. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_GENERIC + */ + +/* + * This is the shared structure that will be used to communicate between + * Physical RM and clients. As of now the access relies on single source of + * truth operation, i.e. only Physical RM writes into the shared location + * and client (nvkms) reads from the same location. + * + * "dataTimeStamp" field is added to capture the timestamp before and after + * updating the flip delay related data fields(all fields except "timeout"). + * This timestamp will be used by clients to determine if the data got updated + * in between by RM while clients were reading it. + * As of now "timeout" field does not have such protection, as access to + * this field is only in response to notification from RM. + */ +typedef struct NV0073_CTRL_RM_VRR_SHARED_DATA { + NvU32 expectedFrameNum; + NvU32 timeout; + NV_DECLARE_ALIGNED(NvU64 flipTimeStamp, 8); + NvBool bCheckFlipTime; + NvBool bFlipTimeAdjustment; + NV_DECLARE_ALIGNED(NvU64 dataTimeStamp, 8); +} NV0073_CTRL_RM_VRR_SHARED_DATA; + +#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE (0x73019eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x9EU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS { + NvU32 subDeviceInstance; + NvBool bEnable; + NvU32 head; + NvU32 height; + NvU32 maxFrameTime; + NvU32 minFrameTime; + NvHandle hMemory; +} NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS; + /* _ctrl0073system_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h index 238c0d611f..1e0c7a93a0 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080.finn +// Source file: ctrl/ctrl0080.finn // @@ -45,7 +45,6 @@ #include "ctrl0080/ctrl0080perf.h" #include "ctrl0080/ctrl0080msenc.h" #include "ctrl0080/ctrl0080bsp.h" -#include "ctrl0080/ctrl0080rc.h" #include "ctrl0080/ctrl0080nvjpg.h" #include "ctrl0080/ctrl0080unix.h" #include "ctrl0080/ctrl0080internal.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h index 4b20dc12c4..7813addc5e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080base.finn +// Source file: ctrl/ctrl0080/ctrl0080base.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h index 2bac0d9a77..6243e21728 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080bif.finn +// Source file: ctrl/ctrl0080/ctrl0080bif.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -69,6 +69,7 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS { #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE 0x4 #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5 #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7 /* * NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR @@ -138,7 +139,7 @@ typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS { } NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS; /* - * NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK + * NV0080_CTRL_BIF_ASPM_FEATURE * * pciePowerControlMask * pciePowerControlIdentifiedKeyOrder diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h index d4911f55ea..fb8e9a0c60 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080bsp.finn +// Source file: ctrl/ctrl0080/ctrl0080bsp.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h index 279151bf34..9b63db0cb9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080cipher.finn +// Source file: ctrl/ctrl0080/ctrl0080cipher.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h index de61930d50..6bead7f36e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080clk.finn +// Source file: ctrl/ctrl0080/ctrl0080clk.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h index dfc7ef9ccc..24f615aec6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080dma.finn +// Source file: ctrl/ctrl0080/ctrl0080dma.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -160,7 +160,7 @@ typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK { #define NV0080_CTRL_CMD_DMA_GET_PTE_INFO (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */ -#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 4U +#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 5U #define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U) @@ -190,7 +190,7 @@ typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS { #define NV0080_CTRL_CMD_DMA_SET_PTE_INFO (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */ -#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 4U +#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 5U #define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU) @@ -356,9 +356,8 @@ typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS { NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS]; NvHandle hVASpace; NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8); - NvU32 hugePageSize; NvU32 vaSpaceId; - NvU32 pageSize512MB; + NV_DECLARE_ALIGNED(NvU64 supportedPageSizeMask, 8); } NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS; /* @@ -429,7 +428,7 @@ typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK { #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U) #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U) -#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 4U +#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 5U #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U) @@ -453,23 +452,6 @@ typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS { #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER 3U #define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH 4U -/* - * NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET - * - * This command invalidates PDB target setting in hardware. - * After execeution of this command PDB target would be in undefined state. - * - * Returns error if the PDB target can not be invalidate. - * - * This call is only supported on chips fermi and later chips. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ - -#define NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET (0x80180bU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | 0xB" */ - /* * NV0080_CTRL_CMD_DMA_INVALIDATE_TLB * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h index 7fcc696f78..f68cd2912a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080fb.finn +// Source file: ctrl/ctrl0080/ctrl0080fb.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -86,6 +86,7 @@ typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS { #define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB 1:0x10 #define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET 1:0x20 // Deprecated #define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 1:0x40 +#define NV0080_CTRL_FB_CAPS_GENERIC_PAGE_KIND 1:0x80 #define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 2:0x01 #define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02 diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h index 823cc0c3aa..0a5e4e0c1d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080fifo.finn +// Source file: ctrl/ctrl0080/ctrl0080fifo.finn // #include "ctrl/ctrl0080/ctrl0080base.h" @@ -91,72 +91,7 @@ typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS { #define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40 /* size in bytes of fifo caps table */ -#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2 - -/* - * NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS - * - * This command enables the GPU to place various scheduling events in the - * off chip event buffer (with optional interrupt) for those GPUs that support - * it. - * - * record - * This parameter specifies a mask of event types to record. - * interrupt - * This parameter specifies a mask of event types for which to interrupt - * the CPU when the event occurs. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_PARAM_STRUCT - * NV_ERR_INVALID_ARGUMENT - */ -#define NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS (0x801703) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x3" */ - -typedef struct NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS { - NvU32 record; - NvU32 interrupt; -} NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS; - -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX 0:0 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX 1:1 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST 2:2 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE 3:3 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT 4:4 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT 5:5 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD 6:6 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX 7:7 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI 8:8 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED 9:9 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC 10:10 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT 11:11 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_ENABLE (0x00000001) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL 11:0 -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_DISABLE (0x00000000) -#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_ENABLE (0x00000fff) +#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2 /* * NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h index 5ce19e5636..58f964e667 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080gpu.finn +// Source file: ctrl/ctrl0080/ctrl0080gpu.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h index 71205d6cfa..4427b2c07c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -27,10 +27,11 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080gr.finn +// Source file: ctrl/ctrl0080/ctrl0080gr.finn // #include "ctrl/ctrl0080/ctrl0080base.h" +#include "nvcfg_sdk.h" typedef struct NV0080_CTRL_GR_ROUTE_INFO { NvU32 flags; @@ -148,14 +149,17 @@ typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO; #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032) -#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000033) + + +#define NV0080_CTRL_GR_INFO_INDEX_DUMMY (0x00000033) +#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034) /* When adding a new INDEX, please update MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size * reflects that. */ -#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000033) -#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x34) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ +#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000034) +#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x35) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ /* * NV0080_CTRL_CMD_GR_GET_INFO diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h index 2a47543ec6..749eeeffae 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080host.finn +// Source file: ctrl/ctrl0080/ctrl0080host.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h index 1fc34f410f..7155f17954 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080internal.finn +// Source file: ctrl/ctrl0080/ctrl0080internal.finn // #include "nvlimits.h" @@ -101,4 +101,30 @@ typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS { NvU8 powerDisconnectedGpuCount; } NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS; +/* + * NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS + * + * This command will RC and disable channels permanently for the given clients. + * + * numClients + * Number of clients + * clientHandles + * List of client handles + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ + +#define NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS (0x802008) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS 200U + +#define NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0x08U) + +typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS { + NvU32 numClients; + NvHandle clientHandles[NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS]; +} NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS; + /* ctrl0080internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h index 60af5a6f73..fc5971c7a7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080msenc.finn +// Source file: ctrl/ctrl0080/ctrl0080msenc.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h index 689fe4bccc..dd3c662a02 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn +// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h index 30010767a8..da58539df1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080perf.finn +// Source file: ctrl/ctrl0080/ctrl0080perf.finn // #define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h index fbbdf73399..1c3838d722 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0080/ctrl0080unix.finn +// Source file: ctrl/ctrl0080/ctrl0080unix.finn // #include "ctrl/ctrl0080/ctrl0080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0090.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0090.h index 83af684274..cded3f8418 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0090.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0090.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0090.finn +// Source file: ctrl/ctrl0090.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00da.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00da.h new file mode 100644 index 0000000000..e0aed23eca --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00da.h @@ -0,0 +1,199 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00da.finn +// + + + +/* NV_SEMAPHORE_SURFACE control commands and parameters */ + +#define NV_SEMAPHORE_SURFACE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00DA, NV00DA_CTRL_##cat, idx) + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY +* Duplicate the memory object(s) bound to the semaphore surface into the RM +* client of the caller. +* +* The handle values are generated and returned by resource manager if the +* client specified a handle value of zero. +* +* If the semaphore surface has a valid max submitted value memory object, but +* the GPU + system do not require separate max submitted value and semaphore +* value surfaces, the handles provided by the client must be equal, and the +* handles returned by resource manager will also be equal. In such cases, the +* client must recognize that both handles correspond to a single reference to +* a single object, and hence the handle must be freed only once by the client. +* +* If the GPU does not require a max submitted value memory object, the handle +* value must be set to zero and the returned handle will always be zero as +* well. +* +* RETURNS: +* NVOS_STATUS_SUCCESS if the memory object(s) were successfully duplicated +* into the calling client. +* NVOS_STATUS_ERROR_INVALID_PARAMETER if any of the rules regarding the +* max submitted value handle value were violated. +* An error code forwarded from NvRmDupObject for any other failures. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY (0xda0001) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS { + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; +} NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL +* Associates a channel with the semaphore surface. All channels which will +* wait on or signal semaphores in a semaphore surface should first register +* with it to ensure proper event delivery and error handling. +* +* engineMask is a bitfield whose contents should be defined by setting bit +* index to '1' if the corresponding engine index will be used. See +* cl2080.h for a list of engine indices. For example, this would indicate +* a channel making use of the engines GR0(graphics/compute), COPY0-COPY9, +* and host: +* +* NvU64 engineMask = (1ULL << NV2080_ENGINE_TYPE_GR0) | +* (1ULL << NV2080_ENGINE_TYPE_COPY0) | +* (1ULL << NV2080_ENGINE_TYPE_COPY1) | +* (1ULL << NV2080_ENGINE_TYPE_COPY2) | +* (1ULL << NV2080_ENGINE_TYPE_COPY3) | +* (1ULL << NV2080_ENGINE_TYPE_COPY4) | +* (1ULL << NV2080_ENGINE_TYPE_COPY5) | +* (1ULL << NV2080_ENGINE_TYPE_COPY6) | +* (1ULL << NV2080_ENGINE_TYPE_COPY7) | +* (1ULL << NV2080_ENGINE_TYPE_COPY8) | +* (1ULL << NV2080_ENGINE_TYPE_COPY9) | +* (1ULL << NV2080_ENGINE_TYPE_HOST); +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL (0xda0002) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID (0x02U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS { + NvHandle hClient; + NvHandle hDevice; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 engineMask, 8); +} NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER +* Ask RM to signal the specified OS event and/or set the semaphore to a new +* value when the value at the specified index is >= a desired value. +* +* index - Specifies the semaphore slot within the surface to which the the wait +* applies. +* waitValue - The value to wait for. +* newValue - Specifies a value to set the semaphore to automatically when the +* specified semaphore slot reaches waitValue. "0" means the semaphore +* value is not altered by this waiter. +* notificationHandle - The OS event (kernel callback or userspace event +* handle) to notify when the value is reached, or 0 if no notification +* is required. +* +* The waiter must specify at least one action. +* +* RETURNS: +* NVOS_STATUS_SUCCESS if the waitValue has not been reached and a waiter was +* successfully registered +* NVOS_STATUS_SUCCESS if the waitValue has been reached, newValue was applied, +* and notificationHandle was 0 (No notification was requested). +* NVOS_STATUS_ERROR_ALREADY_SIGNALLED if the waitValue has been reached and +* newValue was applied if it was not 0, but no notification was registered +* or generated on notificationHandle. Other notifications generated as a +* side effect of newValue being applied, if any, were generated. +* NVOS_STATUS_ERROR_STATE_IN_USE if newValue is not 0 and the specified index +* already has an auto-update value registered. No waiter is registered. +* NVOS_STATUS_ERROR_STATE_IN_USE if the specified notification handle is +* already registered as a waiter for the specified wait_value at the +* specified index. +* already has an auto-update value registered. No waiter is registered. +* NVOS_STATUS_ERROR_* miscelaneous internal errors. No waiter is registered. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER (0xda0003) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS_MESSAGE_ID (0x03U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 waitValue, 8); + NV_DECLARE_ALIGNED(NvU64 newValue, 8); + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); +} NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE +* Modify a semaphore surface semaphore value, awakening any CPU waiters in +* the process. newValue must be >= the current value at the specified index. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE (0xda0004) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS_MESSAGE_ID (0x04U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 newValue, 8); +} NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS; + +/* +* NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER +* Remove a previously registered notification handle from an index + value +* tuple's list of waiters. +* +* index - Specifies the semaphore slot within the surface on which the waiter +* was previously registered. +* waitValue - The value the wait was registered for. +* notificationHandle - The OS event (kernel callback or userspace event +* handle) registered as a waiter. +* +* RETURNS: +* NVOS_STATUS_SUCCESS the waiter was successfully removed from the list of +* pending waiters. +* NVOS_STATUS_ERROR_* miscelaneous internal errors, or the waiter was not +* found in the list of pending waiters. The waiter may have already been +* called, or may be in a list of imminent notifications the RM is +* processing. +*/ +#define NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER (0xda0005) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS_MESSAGE_ID" */ + +#define NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS_MESSAGE_ID (0x05U) + +typedef struct NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS { + NV_DECLARE_ALIGNED(NvU64 index, 8); + NV_DECLARE_ALIGNED(NvU64 waitValue, 8); + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); +} NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS; + +/* _ctrl00da_h_ */ + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h index cb751908e4..ed4595b40d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,10 +27,12 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl00f8.finn +// Source file: ctrl/ctrl00f8.finn // #include "ctrl/ctrlxxxx.h" +#include "ctrl90f1.h" +#include "mmu_fmt_types.h" #define NV00F8_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx) @@ -88,7 +90,7 @@ typedef struct NV_PHYSICAL_MEMORY_ATTRS { typedef struct NV00F8_CTRL_GET_INFO_PARAMS { NV_DECLARE_ALIGNED(NvU64 size, 8); - NvU32 pageSize; + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); NvU32 allocFlags; NV_PHYSICAL_MEMORY_ATTRS physAttrs; } NV00F8_CTRL_GET_INFO_PARAMS; @@ -268,4 +270,47 @@ typedef struct NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS { NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHED_MEM_INFOS], 8); } NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS; +/* + * NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO + * + * Queries page table information for a specific memory fabric address. This + * call is only supported for Verif platforms. This will return the same info + * as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * offset [IN] + * Memory fabric Offset from the base address for which page table + * information is queried. This offset should be aligned to physical page + * size. + * + * numLevels [OUT] + * Number of levels populated. + * + * levels [OUT] + * Per-level information. + * + * pFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * levelFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * sublevelFmt + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * aperture + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + * + * size + * Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS. + */ +#define NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO (0xf80107U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NvU32 numLevels; + NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8); +} NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS; + /* _ctrl00f8_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h index 316aa6e93d..d284fe041b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl00fd.finn +// Source file: ctrl/ctrl00fd.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h index 2be1a04664..6c0b0ceba5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl00fe.finn +// Source file: ctrl/ctrl00fe.finn // #define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0 diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h index 05f19cfcbc..f7f8d6f934 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080.finn +// Source file: ctrl/ctrl2080.finn // @@ -42,6 +42,8 @@ #include "ctrl2080/ctrl2080fb.h" + +#include "ctrl2080/ctrl2080spdm.h" #include "ctrl2080/ctrl2080gr.h" #include "ctrl2080/ctrl2080bus.h" #include "ctrl2080/ctrl2080thermal.h" @@ -72,6 +74,7 @@ #include "ctrl2080/ctrl2080cipher.h" #include "ctrl2080/ctrl2080fla.h" #include "ctrl2080/ctrl2080gsp.h" +#include "ctrl2080/ctrl2080pmu.h" #include "ctrl2080/ctrl2080grmgr.h" @@ -82,3 +85,4 @@ #include "ctrl2080/ctrl2080unix.h" + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h index 322e119a25..d67b0f2c22 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080acr.finn +// Source file: ctrl/ctrl2080/ctrl2080acr.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h index 43a396eae1..758a73a741 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080base.finn +// Source file: ctrl/ctrl2080/ctrl2080base.finn // #include "ctrl/ctrlxxxx.h" @@ -92,6 +92,7 @@ #define NV2080_CTRL_GRMGR (0x38) #define NV2080_CTRL_UCODE_FUZZER (0x39) #define NV2080_CTRL_DMABUF (0x3A) +#define NV2080_CTRL_BIF (0x3B) // per-OS categories start at highest category and work backwards #define NV2080_CTRL_OS_WINDOWS (0x3F) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h index 15ee62c27e..25d3c2c8ed 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080bios.finn +// Source file: ctrl/ctrl2080/ctrl2080bios.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h index 6f69c5c526..95ae0f38c8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn +// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h index caafd7431a..5a11107042 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn +// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h index 4da86e10e1..c7c7391bc5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080bus.finn +// Source file: ctrl/ctrl2080/ctrl2080bus.finn // #include "nvcfg_sdk.h" @@ -1419,6 +1419,11 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS { * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU */ + /* + * in either self-hosted mode or + * externally-hostedmode. + */ + #define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */ @@ -1545,6 +1550,7 @@ typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS { typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS { NvU32 connectionType; NvU32 peerId; + NvBool bEgmPeer; NvBool bSpaAccessOnly; NvBool bUseUuid; NvU32 remoteGpuId; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h index b45627ed52..bf7d9fcbbb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080ce.finn +// Source file: ctrl/ctrl2080/ctrl2080ce.finn // @@ -98,8 +98,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS { #define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80 #define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01 #define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02 - - +#define NV2080_CTRL_CE_CAPS_CE_CC_SECURE 1:0x04 /* * NV2080_CTRL_CE_CAPS_CE_GRCE @@ -133,10 +132,11 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS { * * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL * Set if the CE supports pipelined Block Linear + * + * NV2080_CTRL_CE_CAPS_CE_CC_SECURE + * Set if the CE is capable of encryption/decryption */ - - /* * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK * @@ -298,7 +298,7 @@ typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS { #define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CE_MAX_HSHUBS 5 +#define NV2080_CTRL_CE_MAX_HSHUBS 32 #define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h index 55b9964121..b46acf7618 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080cipher.finn +// Source file: ctrl/ctrl2080/ctrl2080cipher.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h index 20b8f4f9a0..101970a414 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080clk.finn +// Source file: ctrl/ctrl2080/ctrl2080clk.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h index 570987bbfd..2d339faaec 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn +// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h index cd4517f4df..4a380d171b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080dma.finn +// Source file: ctrl/ctrl2080/ctrl2080dma.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h index 982381ffdf..bb4849580c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn +// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h index 7d0fabe24a..d19a2f5c37 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080ecc.finn +// Source file: ctrl/ctrl2080/ctrl2080ecc.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h index 324de6503e..88800d5fc9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080event.finn +// Source file: ctrl/ctrl2080/ctrl2080event.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h index a338bab8e2..dc7be17e36 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fan.finn +// Source file: ctrl/ctrl2080/ctrl2080fan.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h index 76982a19c5..2664849f46 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fb.finn +// Source file: ctrl/ctrl2080/ctrl2080fb.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -419,27 +419,6 @@ typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS { NV2080_CTRL_FB_INFO fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE]; } NV2080_CTRL_FB_GET_INFO_V2_PARAMS; -/* - * NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO - * - * This command returns tile addressing information. - * - * StartAddr - * This parameter returns BAR1 plus the size of the local FB. - * SpaceSize - * This parameter returns the BAR1 aperture size less the size of the - * local FB. - * - * Note that both parameters will contain zero if there is no system tile - * address space. - */ -#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */ - -typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO { - NV_DECLARE_ALIGNED(NvU64 StartAddr, 8); - NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8); -} NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO; - /* * NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET * @@ -537,53 +516,8 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS { } NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS; /* valid flags parameter values */ -#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) -#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) - -/* - * NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED - * - * This command specifies to RM if scanout compaction feature is allowed or - * not in the current configuration. In hybrid mode when dGPU is rendering the - * image, the dGPU blit to the scanout surface happens without mGPU's - * knowledge (directly to system memory), which results in stale compacted - * data resulting in corruption. - * - * This control call can be used to disable the compaction whenever the KMD - * (client) is switching to the pref mode in Hybrid i.e., whenever there is a - * possibility of dGPU doing a blit to mGpu scanout surface. Compaction can - * be enabled when system is back in hybrid power mode as mGpu will be - * rendering the image. - * - * allowCompaction - * This parameter specifies if the display compaction feature is allowed - * or not allowed. - * immediate - * This parameter specifies whether compaction has to be enabled or - * disabled immediately (based on the value of allowCompaction field) or - * during the next modeset. - * - * Possible status values returned are: - * NV_OK - * NVOS_STATUS_INVALID_PARAM_STRUCT - * NVOS_STATUS_NOT_SUPPORTED - * NV_ERR_INVALID_ARGUMENT - */ - -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM - -typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS { - NvU32 allowCompaction; - NvU32 immediate; -} NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS; - -/* valid allowCompaction values */ -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW (0x00000001U) -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW (0x00000000U) - -/* valid immediate values */ -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE (000000001U) -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) /* * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE @@ -628,9 +562,9 @@ typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS { * supports it. Use this call if you want to flush a single allocation and * you have a memory object describing the physical memory. */ -#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU) @@ -1615,239 +1549,6 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS { NvBool upper64KBCompbitSel; } NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS; -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS < Deprecated > - * - * The PS (Performance Path, or Optimized path, or Per Slice version) - * of PutCompBits. - * - * @params[out] NvU32 *fcbits; - * Buffer to receive Fast Clear Bits. - * @params[out] NvU32 *compbits; - * Buffer to receive Compression Bits. - * @params[out] NvU32 *compCacheLine; - * Buffer to receive Comp Cache Line data. - * @params[in] NvU64 dataPhysicalStart; - * Start Address of Data - * @params[in] NvU64 surfaceOffset; - * Offset in the surface - * @params[in] NvU32 comptagLine; - * Compression Tag Line Number - * @params[in] NvU32 ROPTile_offset; - * Offset in the surface of the ROP tile. - * @params[in] NvBool upper64KBCompbitSel; - * Selects Upper or Lower 64K - * @params[in] NvBool getFcBits; - * Indicates if fast clear bits should be returned. - * @params[in] NvP64 derivedParams - * Actually a CompBitDerivedParams structure. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS { - NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); - NV_DECLARE_ALIGNED(NvU32 *compbits, 8); - NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); - NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); - NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); - NvU32 comptagLine; - NvU32 ROPTile_offset; - NvBool upper64KBCompbitSel; - NvBool getFcBits; - NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); -} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS < Deprecated > - * - * The PS (Performance Path, or Optimized path, or Per Slice version) - * of GetCompBits. - * - * @params[in] NvU32 fcbits; - * Buffer with Fast Clear Bits to write. - * @params[in] NvU32 compbits; - * Buffer to receive Compression Bits. - * @params[in] NvBool writeFc - * Indicates of Fast Clear Bits should be written. - * @params[in] NvU32 *compCacheLine; - * Buffer to receive Comp Cache Line data. - * @params[in] NvU64 dataPhysicalStart; - * Start Address of Data - * @params[in] NvU64 surfaceOffset; - * Offset in the surface - * @params[in] NvU32 comptagLine; - * Compression Tag Line Number - * @params[in] NvU32 ROPTile_offset; - * Offset in the surface of the ROP tile. - * @params[in] NvBool upper64KBCompbitSel; - * Selects Upper or Lower 64K - * @params[in] NvP64 derivedParams - * Actually a CompBitDerivedParams structure. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS { - NvU32 fcbits; - NvU32 compbits; - NvBool writeFc; - NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); - NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); - NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); - NvU32 comptagLine; - NvU32 ROPTile_offset; - NvBool upper64KBCompbitSel; - NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); -} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS < Deprecated > - * - * The PS (Performance Path, or Optimized path, or Per Slice version) - * of ReadCompCacheLine. - * - * @paramsNvU32 *compCacheLine; - * Buffer for Comp Cache Line Read - * @paramsNvU32 comptagLine; - * Comp Tag Line Number to read - * @paramsNvU32 partition; - * FB Partition of the desired Comp Cache Line - * @paramsNvU32 slice; - * Slice of the desired Comp Cache Line - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS { - NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); - NvU32 comptagLine; - NvU32 partition; - NvU32 slice; -} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS < Deprecated > - * - * The PS (Performance Path, or Optimized path, or Per Slice version) - * of WriteCompCacheLine. - * - * @params[in] NvU32 *compCacheLine; - * Buffer for Comp Cache Line to Write - * @params[in] NvU32 comptagLine; - * Comp Tag Line Number to Write - * @params[in] NvU32 partition; - * FB Partition of the desired Comp Cache Line - * @params[in] NvU32 slice; - * Slice of the desired Comp Cache Line - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS { - NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); - NvU32 comptagLine; - NvU32 partition; - NvU32 slice; -} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS < Deprecated > - * - * Used by PS (Performance Path, or Optimized path, or Per Slice version) - * to retrieve upper and lower Address of the CompCacheLine. - * - * @params[out] NvU64 *minCPUAddress; - * Minimum (lower bound) of the ComCacheLine. - * @params[out] NvU64 *minCPUAddress; - * Minimum (lower bound) of the ComCacheLine. - * @params[in] NvU32 comptagLine; - * CompTagLine to fetch the bounds of. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS { - NV_DECLARE_ALIGNED(NvU64 *minCPUAddress, 8); - NV_DECLARE_ALIGNED(NvU64 *maxCPUAddress, 8); - NvU32 comptagLine; -} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET < Deprecated > - * - * Used by PS (Performance Path, or Optimized path, or Per Slice version) - * to retrieve partition, slice and ROP Tile Offset of the passed in - * surface location. - * - * @params[out] NvU64 *part; - * Partition in which the target part of the surface resides. - * @params[out] NvU64 *slice; - * Slice in which the target part of the surface resides. - * @params[out] NvU64 *ropTileoffset; - * Offset to the start of the ROP Tile in which the target part of - * the surface resides. - * @params[in] NvU64 *dataPhysicalStart; - * Start address of data for which part/slice/offset is desired. - * @params[in] NvU64 surfaceOffset; - * Byte offset of data for which part/slice/offset is desired. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS { - NV_DECLARE_ALIGNED(NvU64 *part, 8); - NV_DECLARE_ALIGNED(NvU64 *slice, 8); - NV_DECLARE_ALIGNED(NvU64 *ropTileoffset, 8); - NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8); - NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8); -} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS; - -/*! - * NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS < Deprecated > - * - * Used by PS (Performance Path, or Optimized path, or Per Slice version) - * to create a CompBitCopy::CompBitDerivedParams object - * - * @params[out] NvP64 derivedParams - * Actually a CompBitDerivedParams structure. - * @params[in] NvU32 comptagLine; - * Compression Tag Line Number - * @params[in] NvU32 ROPTile_offset; - * Offset in the surface of the ROP tile. - * @params[in] NvBool upper64KBCompbitSel; - * Selects Upper or Lower 64K - * - * Possible status values returned are: - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */ - -typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS { - NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); - NvU32 comptagLine; - NvBool upper64KBCompbitSel; -} NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS; - /*! * NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 < Deprecated > * @@ -2876,8 +2577,9 @@ typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS { /* * NV2080_CTRL_CMD_FB_GET_NUMA_INFO * - * This control command is used by clients to get per-subdevice NUMA memory - * information as assigned by the system. + * This control command is used by clients to get per-subdevice or + * subscribed MIG partition(when MIG is enabled) NUMA memory information as + * assigned by the system. * * numaNodeId[OUT] * - Specifies the NUMA node ID. @@ -2916,4 +2618,37 @@ typedef struct NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS { NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8); } NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS; +/* + * NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT + * + * This control command is used by clients to get NV_SEMAPHORE_SURFACE layout/caps before allocation. + * A semaphore surface can be viewed as an array of independent semaphore entries. + * + * maxSubmittedSemaphoreValueOffset[OUT] + * - An offset of the max submitted value, relative to the semaphore surface entry start, if used. + * Used to emulate 64-bit semaphore values on chips where 64-bit semaphores are not supported. + * + * monitoredFenceThresholdOffset[OUT] + * - An offset of the monitored fence memory, relative to the semaphore surface entry start, if supported. + * + * size[OUT] + * - A size of a single semaphore surface entry. + * + * caps[OUT] + * - A mask of NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_* values. + */ +#define NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT (0x20801352U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED (0x00000001U) +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED (0x00000002U) + +#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID (0x52U) + +typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS { + NV_DECLARE_ALIGNED(NvU64 maxSubmittedSemaphoreValueOffset, 8); + NV_DECLARE_ALIGNED(NvU64 monitoredFenceThresholdOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 caps; +} NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS; + /* _ctrl2080fb_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h index 8f80e72d6d..88cccdf011 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fifo.finn +// Source file: ctrl/ctrl2080/ctrl2080fifo.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h index 3fe89b949b..1f0c86a7b2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fla.finn +// Source file: ctrl/ctrl2080/ctrl2080fla.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h index 3d743b3a14..a75045d1b1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080flcn.finn +// Source file: ctrl/ctrl2080/ctrl2080flcn.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h index 2af63e7643..7ea0b05317 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080fuse.finn +// Source file: ctrl/ctrl2080/ctrl2080fuse.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h index d40e8b6c1b..fd0e3495f3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gpio.finn +// Source file: ctrl/ctrl2080/ctrl2080gpio.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h index e31cd000bf..a56b72c7bf 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gpu.finn +// Source file: ctrl/ctrl2080/ctrl2080gpu.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -103,11 +103,16 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY (0x0000003aU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY (0x0000003bU) + + #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) -#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003fU) +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU) +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000040U) /* valid minor revision extended values */ #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) @@ -198,6 +203,16 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U) +/* valid local EGM supported values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES (0x00000001U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID 31:1 + +/* valid self hosted values */ +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES (0x00000001U) + + /* valid CMP (Crypto Mining Processor) SKU values */ #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U) @@ -208,6 +223,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U) #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U) +/* valid resetless MIG device supported values */ +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U) + /* * NV2080_CTRL_CMD_GPU_GET_INFO * @@ -2585,7 +2604,7 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U -#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8U +#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 20U #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U @@ -2598,6 +2617,7 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF)) #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF)) #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER)) +#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_QUARTER)) #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH)) #define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U) @@ -3264,7 +3284,7 @@ typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO { NvU32 gfxGrCount; NvU32 gpcCount; NvU32 virtualGpcCount; - NvU32 grGpcCount; + NvU32 gfxGpcCount; NvU32 veidCount; NvU32 smCount; NvU32 ceCount; @@ -3322,7 +3342,7 @@ typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS { #define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U) typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS { - NvU32 maxSupportedPageSize; + NV_DECLARE_ALIGNED(NvU64 maxSupportedPageSize, 8); } NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS; @@ -3720,6 +3740,9 @@ typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS { * bEnable [IN] * - Set to NV_TRUE if the GPU partition has been activated. * - Set to NV_FALSE if the GPU partition will be deactivated. + * fabricPartitionId [IN] + * - Set the fabric manager partition ID dring partition activation. + * - Ignored during partition deactivation. * * Possible status values returned are: * NV_OK @@ -3735,6 +3758,7 @@ typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS { typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS { NvU32 gfid; NvBool bEnable; + NvU32 fabricPartitionId; } NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS; /*! @@ -3763,6 +3787,23 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { NvU32 protection; } NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS; +/* + * NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR + * + * @brief This command is similar to NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR + * but will be used to set the EGM fabric base addr associated with the gpu. + * Note: For EGM FLA, we will be making use of the existing control call i.e + * NV2080_CTRL_CMD_FLA_RANGE + * + */ +#define NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR (0x20800199U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x99U) + +typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS { + NV_DECLARE_ALIGNED(NvU64 egmGpaFabricBaseAddr, 8); +} NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS; + /* @@ -3788,7 +3829,7 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { */ #define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xA0U +#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC0U #define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h index 742b21aa4d..2398a0c390 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn +// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h index 2b40775860..86ec9b4792 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gr.finn +// Source file: ctrl/ctrl2080/ctrl2080gr.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -256,6 +256,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC + + +#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY #define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES /* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h index 481b59aaef..609553b2fb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn +// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h index ee04d61a6d..4bb6216580 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080gsp.finn +// Source file: ctrl/ctrl2080/ctrl2080gsp.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -79,4 +79,52 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS { #define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000) #define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001) +/* + * NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS + * + * This command reports the current GSP-RM heap usage statistics. + * + * managedSize + * The total size in bytes of the underlying heap. Note that not all memory + * will be allocatable, due to fragmentation and memory allocator/tracking + * overhead. + * current + * An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to + * GSP-RM heap usage at the time this command is called. + * peak + * An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to + * the "high water mark" of heap usage since GSP-RM was started. + */ +#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT + * + * This record represents a set of heap measurements at a given point in time. + * + * allocatedSize + * Allocated memory size, in bytes. This value does not include overhead used + * by the underlying allocator for padding/metadata, but does include the + * NvPort memory tracking overhead. + * usableSize + * Allocated memory size excluding all metadata, in bytes. This value does + * not include the NvPort memory tracking overhead. + * memTrackOverhead + * Allocated memory size used for NvPort memory tracking. + */ +typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT { + NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8); + NV_DECLARE_ALIGNED(NvU64 usableSize, 8); + NV_DECLARE_ALIGNED(NvU64 memTrackOverhead, 8); + NvU32 allocationCount; +} NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT; + +#define NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 managedSize, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8); + NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8); +} NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS; + // _ctrl2080gsp_h_ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h index f0df6c526f..bc25c808d5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080hshub.finn +// Source file: ctrl/ctrl2080/ctrl2080hshub.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h index b5123cc8cc..99e78c2932 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080i2c.finn +// Source file: ctrl/ctrl2080/ctrl2080i2c.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h index 54a762ab53..ee2ada8108 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080illum.finn +// Source file: ctrl/ctrl2080/ctrl2080illum.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h index cb064784cf..4d64702587 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080internal.finn +// Source file: ctrl/ctrl2080/ctrl2080internal.finn // #include "nvimpshared.h" @@ -38,6 +38,7 @@ #include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */ #include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ #include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ +#include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */ #include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrl90f1.h" #include "ctrl/ctrl30f1.h" @@ -152,6 +153,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { * This command sends access counter buffer pages allocated by CPU-RM * to be setup and enabled in physical RM. * + * accessCounterIndex + * Index of access counter buffer to register. + * * bufferSize * Size of the access counter buffer to register. * @@ -167,6 +171,7 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { #define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { + NvU32 accessCounterIndex; NvU32 bufferSize; NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); } NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; @@ -176,39 +181,19 @@ typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { * * This command requests physical RM to disable the access counter buffer. * - * Possible status values returned are: - * NV_OK - */ -#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1E" */ - -/* - * NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER - * - * This command requests physical RM to service the access counter buffer. + * accessCounterIndex + * Index of access counter buffer to unregister. * * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x21" */ +#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ -/* - * NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE - * - * This command retrieves the access counter buffer size from physical RM. - * - * bufferSize[OUT] - * Size of the access counter buffer. - * - * Possible status values returned are: - * NV_OK - */ -#define NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x29U) +#define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU) -typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS { - NvU32 bufferSize; -} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS; +typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS { + NvU32 accessCounterIndex; +} NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS; #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 @@ -1362,7 +1347,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { NvU32 replayableFaultBufferSize; + NvU32 replayableShadowFaultBufferMetadataSize; NvU32 nonReplayableFaultBufferSize; + NvU32 nonReplayableShadowFaultBufferMetadataSize; } NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; /*! @@ -1848,12 +1835,13 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { */ #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 1500 +#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 3000 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); NvU32 shadowFaultBufferSize; + NvU32 shadowFaultBufferMetadataSize; NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); NvU32 shadowFaultBufferType; NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8); @@ -2288,6 +2276,25 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { NvU8 hshubId; } NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; +/*! + * NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG + * + * Program HSHUB for EGM peer id. + * + * egmPeerId[IN] + * EGM peer id to program in the HSHUB registers. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU) + +typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS { + NvU32 egmPeerId; +} NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS; + /* @@ -2880,6 +2887,8 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { * Handle to SYSMEM memlist object * [in] gspFbAllocsSysOffset * Offset in SYSMEM for GSP's FB Allocations + * [in] bEnteringGcoffState + * Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING * * Possible status values returned are: * NV_OK @@ -2897,6 +2906,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { NvHandle hClient; NvHandle hSysMem; NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8); + NvBool bEnteringGcoffState; } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; /*! @@ -3211,6 +3221,8 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS * * bEnable [IN] * Enable or Reset the settings + * clientLimit [IN] + * Client requested limit * * Possible status values returned are: * NV_OK @@ -3225,6 +3237,7 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { NvBool bEnable; + NvU32 clientLimit; } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; /*! @@ -3467,4 +3480,335 @@ typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS { NvBool gpioDirection; // out } NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS; +/* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA + * + * This command sets up ACPI DDC Edid data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */ + +/* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */ +#define MAX_EDID_SIZE_FROM_SBIOS 512U + +typedef struct NV2080_CTRL_INTERNAL_EDID_DATA { + NvU32 status; + NvU32 acpiId; + NvU32 bufferSize; + NvU8 edidBuffer[MAX_EDID_SIZE_FROM_SBIOS]; +} NV2080_CTRL_INTERNAL_EDID_DATA; + +#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS { + NvU32 tableLen; + NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED + * + * This command intializes display ACPI child devices. + * This command accepts no parameters. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */ + +/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */ + +/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for getting GPU Fabric Probe Internal + * Info from GSP to CPU RM + * + * numProbes[OUT] + * - Number of probe requests sent + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 numProbes, 8); +} NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO + * + * This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS + * from GSP to CPU RM. + * This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for starting GPU Fabric Probe + * + * bwMode[IN] + * - Nvlink Bandwidth mode + */ +#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU8 bwMode; +} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE + * + * This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE + * + * This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE + * + * This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */ + + +/*! + * NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the params for resuming GPU Fabric Probe + * + * bwMode[IN] + * - Nvlink Bandwidth mode + */ +#define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU8 bwMode; +} NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE + * + * This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP. + * This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE + * + * This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP. + * This command accepts no parameters + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get static conf compute info + * + * bIsBar1Trusted: [OUT] + * Is BAR1 trusted to access CPR + * bIsPcieTrusted: [OUT] + * Is PCIE trusted to access CPR + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U) + +typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS { + NvBool bIsBar1Trusted; + NvBool bIsPcieTrusted; +} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS; + + + +/* + * NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP + * + * This command is used by CPU-RM to perform memory operations using GSP + * + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_TIMEOUT_RETRY + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP { + NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0, + NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1, +} NV2080_CTRL_MEMMGR_MEMORY_OP; + +typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO { + /*! + * Base physical address of the surface + */ + NV_DECLARE_ALIGNED(NvU64 baseAddr, 8); + + /*! + * Size of the surface in bytes + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); + + /*! + * Offset in bytes into the surface where read/write must happen + */ + NV_DECLARE_ALIGNED(NvU64 offset, 8); + + /*! + * Aperture where the surface is allocated + */ + NvU32 aperture; + + /*! + * CPU caching attribute of the surface + */ + NvU32 cpuCacheAttrib; +} NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO; + +#define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU) + +typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS { + + /*! + * Source surface info + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8); + + /*! + * Destination surface info + */ + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8); + + /*! + * Size of the data to be transferred + */ + NV_DECLARE_ALIGNED(NvU64 transferSize, 8); + + /*! + * To be set in case of memset + */ + NvU32 value; + + /*! + * Memory op to be performed + */ + NV2080_CTRL_MEMMGR_MEMORY_OP memop; +} NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get local GPU's ATS config + * + * addrSysPhys : [OUT] + * System Physical Address + * addrWidth : [OUT] + * Address width value + * mask : [OUT] + * Mask value + * maskWidth : [OUT] + * Mask width value + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS { + NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); + NvU32 addrWidth; + NvU32 mask; + NvU32 maskWidth; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG + * + * This command is an internal command sent from Kernel RM to Physical RM + * to set peer ATS config using the parameters passed in. + * + * peerId : [IN] + * Peer Id of the peer for which ATS config is to be programmed + * addrSysPhys : [IN] + * System Physical Address + * addrWidth : [IN] + * Address width value + * mask : [IN] + * Mask value + * maskWidth : [IN] + * Mask width value + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU) + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS { + NvU32 peerId; + NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); + NvU32 addrWidth; + NvU32 mask; + NvU32 maskWidth; +} NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO + * + * Get GPU EDPpeak Limit information + * + * limitMin [OUT] + * Minimum allowed limit value on EDPp policy on both AC and DC + * limitRated [OUT] + * Rated/default allowed limit value on EDPp policy on AC + * limitMax [OUT] + * Maximum allowed limit value on EDPp policy on AC + * limitCurr [OUT] + * Current resultant limit effective on EDPp policy on AC and DC + * limitBattRated [OUT] + * Default/rated allowed limit on EDPp policy on DC + * limitBattMax [OUT] + * Maximum allowed limit on EDPp policy on DC + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS { + NvU32 limitMin; + NvU32 limitRated; + NvU32 limitMax; + NvU32 limitCurr; + NvU32 limitBattRated; + NvU32 limitBattMax; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS; + /* ctrl2080internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h index 9a121f97fb..707a2568b3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn +// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h index 2bb1c30333..99973dfc69 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080mc.finn +// Source file: ctrl/ctrl2080/ctrl2080mc.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -79,7 +79,6 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS { #define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170) - /* valid ARCHITECTURE_T23X implementation values */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h index f1e490b100..767c33d056 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080nvd.finn +// Source file: ctrl/ctrl2080/ctrl2080nvd.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h index 913ab8a0dd..a7dc1f8784 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn +// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -2097,6 +2097,7 @@ typedef struct NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS { typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS { NvU32 peerId; NvU32 peerLinkMask; + NvBool bEgmPeer; NvBool bNvswitchConn; } NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS; #define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */ @@ -2972,5 +2973,22 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS { #define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG + * + * This command is to check if a GPU has a reduced nvlink configuration + * + * [out] bReducedNvlinkConfig + * Link number which the sequence should be triggered + */ +#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS { + NvBool bReducedNvlinkConfig; +} NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */ + + /* _ctrl2080nvlink_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h index f87a34f0a0..4873686621 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080perf.finn +// Source file: ctrl/ctrl2080/ctrl2080perf.finn // #include "nvfixedtypes.h" @@ -460,7 +460,7 @@ typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMP #define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72 #define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \ - NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \ + sizeof(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \ NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL /*! diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h index 8eb6c01fb4..137549f34e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn +// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h index 0a3e6b2b81..a0b11908db 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn +// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h index fa476b5dcc..6fcd9ac4c2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn +// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn // diff --git a/kernel-open/common/inc/nv_firmware_types.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h similarity index 78% rename from kernel-open/common/inc/nv_firmware_types.h rename to src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h index 90dd93f1ea..a8860cc88e 100644 --- a/kernel-open/common/inc/nv_firmware_types.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h @@ -1,5 +1,6 @@ + /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,14 +22,20 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef NV_FIRMWARE_TYPES_H -#define NV_FIRMWARE_TYPES_H +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080pmu.finn +// + + -typedef enum { - NV_FIRMWARE_MODE_DISABLED = 0, - NV_FIRMWARE_MODE_ENABLED = 1, - NV_FIRMWARE_MODE_DEFAULT = 2, - NV_FIRMWARE_MODE_INVALID = 0xFF -} NvFirmwareMode; +#include "nvtypes.h" + +/*! + * @file + * + * @brief Enumeration of all PMU RMCTRL identifiers. + */ -#endif // NV_FIRMWARE_TYPES_H diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h index 53cb620a68..ef33336c3b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn +// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h index 2d01ed555d..2f0abcbd40 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h @@ -27,6 +27,97 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080power.finn +// Source file: ctrl/ctrl2080/ctrl2080power.finn // +#include "ctrl/ctrl2080/ctrl2080base.h" + + + +/*! + * @brief GC6 flavor ids + */ +typedef enum NV2080_CTRL_GC6_FLAVOR_ID { + NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = 0, + NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = 1, + + + NV2080_CTRL_GC6_FLAVOR_ID_MAX = 4, +} NV2080_CTRL_GC6_FLAVOR_ID; + +/* + * NV2080_CTRL_CMD_GC6_ENTRY + * + * This command executes the steps of GC6 entry sequence + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED (non-fatal) + * NV_ERR_INVALID_STATE (non-fatal) + * NV_ERR_INVALID_ARGUMENT (non-fatal) + * NV_ERR_NOT_READY (non-fatal) + * NV_ERR_TIMEOUT + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_GC6_ENTRY (0x2080270d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_GC6_ENTRY_PARAMS { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + NvU32 stepMask; + struct { + + + NvBool bIsRTD3Transition; + NvBool bIsRTD3CoreRailPowerCut; + + + NvBool bSkipPstateSanity; + } params; +} NV2080_CTRL_GC6_ENTRY_PARAMS; + +/* + * NV2080_CTRL_CMD_GC6_EXIT + * + * This command executes the steps of GC6 exit sequence + * + * Possible status return values are: + * NV_OK + * NV_ERR_GENERIC + */ +#define NV2080_CTRL_CMD_GC6_EXIT (0x2080270e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_GC6_EXIT_PARAMS { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + struct { + NvBool bIsGpuSelfWake; + NvBool bIsRTD3Transition; + + + NvBool bIsRTD3HotTransition; //output + } params; +} NV2080_CTRL_GC6_EXIT_PARAMS; + +/*! + * @brief GC6 step ids + */ +typedef enum NV2080_CTRL_GC6_STEP_ID { + NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = 0, + NV2080_CTRL_GC6_STEP_ID_GPU_OFF = 1, + NV2080_CTRL_GC6_STEP_ID_MAX = 2, +} NV2080_CTRL_GC6_STEP_ID; + +typedef struct NV2080_CTRL_GC6_FLAVOR_INFO { + NV2080_CTRL_GC6_FLAVOR_ID flavorId; + NvU32 stepMask; +} NV2080_CTRL_GC6_FLAVOR_INFO; + + + +/* _ctrl2080power_h_ */ + + + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h index ed4dd89a3e..86bf7e948f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080rc.finn +// Source file: ctrl/ctrl2080/ctrl2080rc.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h new file mode 100644 index 0000000000..fcd3af8d21 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h @@ -0,0 +1,255 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080spdm.finn +// + + + +/*************************** SPDM COMMANDS ************************************/ + +/*! + * @brief SPDM Command Types + * + */ +#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1) +#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2) +#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3) +#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4) + + +#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF) + + + +#define RSVD7_SIZE 16 + +#define RSVD8_SIZE 2 + +/*! + * Guest RM must send RM_GSP_SPDM_CMD_ID_CC_INIT to GSP-RM before SPDM session start + */ +typedef struct RM_GSP_SPDM_CC_INIT_CTX { + NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc + + NvU8 dmaIdx; // To indicate DMA engine which DMA idx is needed + + NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory. + + NvU32 addrSpace; // The memory type allocated by RM (SYS or FB ...) + + NvU32 regionId; // If memory is in WPR, this is a WPR id. + + NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER) + +} RM_GSP_SPDM_CC_INIT_CTX; +typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX; + +/*! + * Guest RM provides INIT context + */ +typedef struct RM_GSP_SPDM_CMD_CC_INIT { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + RM_GSP_SPDM_CC_INIT_CTX ccInitCtx; +} RM_GSP_SPDM_CMD_CC_INIT; +typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT; + +#define DEINIT_FLAGS_FORCE_CLEAR (0x1) + +/*! + * Guest RM must send RM_GSP_SPDM_CMD_ID_CC_DEINIT to GSP-RM to end a session + */ +typedef struct RM_GSP_SPDM_CC_DEINIT_CTX { + NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc + + NvU32 endpointId; // To indicate SPDM endpoint Id + + NvU32 flags; +} RM_GSP_SPDM_CC_DEINIT_CTX; +typedef struct RM_GSP_SPDM_CC_DEINIT_CTX *PRM_GSP_SPDM_CC_DEINIT_CTX; + +/*! + * Guest RM provides INIT context + */ +typedef struct RM_GSP_SPDM_CMD_CC_DEINIT { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + RM_GSP_SPDM_CC_DEINIT_CTX ccDeinitCtx; +} RM_GSP_SPDM_CMD_CC_DEINIT; +typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT; + +/*! + * RM provides SPDM message request context, include header + corresponding payload + */ + +typedef struct RM_GSP_SPDM_CC_CTRL_CTX { + + NvU32 version; + + NvU32 guestId; // To indicate CC client Id, VM0, VM1 ... etc + + NvU32 endpointId; // To indicate SPDM endpoint Id + + NvU32 ctrlCode; // control code + + NvU32 ctrlParam; // Associated with ctrlCode + +} RM_GSP_SPDM_CC_CTRL_CTX; +typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX; + +/*! + * RM provides the SPDM request info to GSP + */ +typedef struct RM_GSP_SPDM_CMD_CC_CTRL { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + RM_GSP_SPDM_CC_CTRL_CTX ccCtrlCtx; +} RM_GSP_SPDM_CMD_CC_CTRL; +typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL; + +typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + NvU32 rsvd0[2]; + + NvU32 rsvd1; + + char rsvd2[4]; + + char rsvd3[2]; + + char rsvd4[5]; + + char rsvd5[5]; + + char rsvd6[2]; + + char rsvd7[RSVD7_SIZE]; + + NvU32 rsvd8[RSVD8_SIZE]; +} RM_GSP_SPDM_CMD_CC_INIT_RM_DATA; +typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA; + + +/*! + * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives + * getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in + * other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior + * when paired with alignment directives on Linux and Windows. + */ + +/*! + * A union of all SPDM Commands. + */ +typedef union RM_GSP_SPDM_CMD { + NvU8 cmdType; + RM_GSP_SPDM_CMD_CC_INIT ccInit; + RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit; + RM_GSP_SPDM_CMD_CC_CTRL ccCtrl; + RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd; + +} RM_GSP_SPDM_CMD; +typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD; + +/***************************** SPDM MESSAGES *********************************/ + +/*! + * SPDM Message Status + */ + +/*! + * Returns the status for program CE keys to RM + */ +#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1) +#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2) +#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3) +#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4) + + + +/*! + * Returns the Error Status for Invalid Command + */ +#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF) + +/*! + * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives + * getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in + * other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior + * when paired with alignment directives on Linux and Windows. + */ + +/*! + * SPDM message structure. + */ +typedef struct RM_GSP_SPDM_MSG { + NvU8 msgType; + + NvU32 version; + + NvU32 guestId; + + NvU32 endpointId; + + // status returned from GSP message infrastructure. + NvU32 status; + + NvU32 rsvd1; + + NvU32 rsvd2; + + NvU32 rsvd3; + + NvU32 rsvd4; +} RM_GSP_SPDM_MSG; +typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG; + +/* + * NV2080_CTRL_CMD_INTERNAL_SPDM_PARTITION + * + * This command does a partition switch to SPDM partition + * + */ +#define NV2080_CTRL_INTERNAL_SPDM_PARTITION (0x20800ad9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID (0xD9U) + +typedef struct NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS { + NvU8 index; + RM_GSP_SPDM_CMD cmd; + RM_GSP_SPDM_MSG msg; +} NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS; + + + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h index 448723c8c9..0b378d26c6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080spi.finn +// Source file: ctrl/ctrl2080/ctrl2080spi.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h index abe66effab..2ba50105a1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h @@ -25,6 +25,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080thermal.finn +// Source file: ctrl/ctrl2080/ctrl2080thermal.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h index d018e201fb..4d51f6379d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080tmr.finn +// Source file: ctrl/ctrl2080/ctrl2080tmr.finn // #include "ctrl/ctrl2080/ctrl2080base.h" @@ -151,16 +151,32 @@ typedef struct NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE { * for a given CPU clock type. * * cpuClkId - * This parameter specifies the source of the CPU clock. Legal values for - * this parameter include: - * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME - * This clock id will provide real time in microseconds since - * 00:00:00 UTC on January 1, 1970. - * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API - * This clock id will provide time stamp that is constant-rate, high - * precision using platform API that is also available in the user mode. - * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC - * This clock id will provide time stamp using CPU's time stamp counter. + * This parameter specifies the source of the CPU clock. This parameter is + * composed of two fields: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE + * This field specifies source ID of the CPU clock in question. Legal + * values for this parameter include: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME + * This clock id will provide real time in microseconds since + * 00:00:00 UTC on January 1, 1970, as reported by the host OS. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API + * This clock id will provide time stamp that is constant-rate, high + * precision using platform API that is also available in the user + * mode. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC + * This clock id will provide time stamp using CPU's time stamp + * counter. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR + * This field specifies the processor whose clock should be used for the + * source. The control call and cpuClkId parameter remain named for the + * CPU specifically for legacy reasons. Not all processors will support + * all clock sources. Legal values for this parameter include: + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU + * The clock information will be fulfilled by the CPU. This value + * is defined to be 0 so that it is the default for backwards + * compatibility. + * NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP + * The clock information will be fulfilled by the GSP. * * sampleCount * This field specifies the number of clock samples to be taken. @@ -188,10 +204,21 @@ typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE samples[NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES], 8); } NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS; -/* Legal cpuClkId values */ -#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001) -#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002) -#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE 3:0 + +/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE values */ +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME (0x00000001) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC (0x00000002) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API (0x00000003) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS (0x00000004) + +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR 7:4 + +/* Legal NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR values */ +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU (0x00000000) +#define NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP (0x00000001) + + /*! * NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ * @@ -219,7 +246,7 @@ typedef struct NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS { * NV_ERR_INVALID_OPERATION * NV_ERR_INVALID_STATE */ -#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ (0x20800407) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_TIMER_INTERFACE_ID << 8) | NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID" */ /*! * This struct contains bSetMaxFreq flag. diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h index e4995b8a6b..aedb3cef74 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn +// Source file: ctrl/ctrl2080/ctrl2080ucodefuzzer.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h index 782e182c8b..b058211c44 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080unix.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080unix.finn +// Source file: ctrl/ctrl2080/ctrl2080unix.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h index a5a9db11b5..5742c5ed10 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vfe.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080vfe.finn +// Source file: ctrl/ctrl2080/ctrl2080vfe.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h index 12f41e0996..c090e795a6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn +// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn // #include "ctrl/ctrl2080/ctrl2080base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h index eacd59600e..a136214b0e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080volt.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080volt.finn +// Source file: ctrl/ctrl2080/ctrl2080volt.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f.h index b526aa3a48..f54223736b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f.finn +// Source file: ctrl/ctrl208f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h index eb08864fbc..82c65ea1e2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fbase.finn +// Source file: ctrl/ctrl208f/ctrl208fbase.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h index 3499ef99a7..b6cf87c11d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fbif.finn +// Source file: ctrl/ctrl208f/ctrl208fbif.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h index 11fd26e6db..0845699ebd 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbus.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fbus.finn +// Source file: ctrl/ctrl208f/ctrl208fbus.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h index 450d881821..d16a087337 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fclk.h @@ -28,6 +28,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fclk.finn +// Source file: ctrl/ctrl208f/ctrl208fclk.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h index a302d42200..be4d8e4949 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fdma.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fdma.finn +// Source file: ctrl/ctrl208f/ctrl208fdma.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h index 3777829d5b..7f58236d18 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fevent.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fevent.finn +// Source file: ctrl/ctrl208f/ctrl208fevent.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h index ec1691612a..343605bad3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208ffb.finn +// Source file: ctrl/ctrl208f/ctrl208ffb.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" @@ -575,6 +575,9 @@ typedef struct NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS { * remapped from the specified sources will be cleared/removed from the * Inforom RRL object entries list. * + * bForcePurge + * This flag will force purge the RRL object and associated data structures + * * Possbile status values returned are: * NV_OK * NV_ERR_NOT_SUPPORTED @@ -584,7 +587,8 @@ typedef struct NV208F_CTRL_FB_TOGGLE_PHYSICAL_ADDRESS_ECC_ON_OFF_PARAMS { #define NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x15U) typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS { - NvU32 sourceMask; + NvU32 sourceMask; + NvBool bForcePurge; } NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS; /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h index a523160f97..e9abbf4f3d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffbio.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208ffbio.finn +// Source file: ctrl/ctrl208f/ctrl208ffbio.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h index dba64cdcb3..0524fc2748 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208ffifo.finn +// Source file: ctrl/ctrl208f/ctrl208ffifo.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h index dda35bf0b6..5d8f1d81ab 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fgpu.finn +// Source file: ctrl/ctrl208f/ctrl208fgpu.finn // #include "ctrl/ctrl2080/ctrl2080gr.h" /* 208F is partially derivative of 2080 */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h index 357ac1f591..524f2c454b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fgr.finn +// Source file: ctrl/ctrl208f/ctrl208fgr.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h index 2b298e6fbc..2e4964f400 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fmmu.finn +// Source file: ctrl/ctrl208f/ctrl208fmmu.finn // #include "ctrl/ctrl208f/ctrl208fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h index d7ea299acb..7b2a5dde93 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpmgr.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fpmgr.finn +// Source file: ctrl/ctrl208f/ctrl208fpmgr.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h index e225c7bbaa..3e5fd31a54 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl208f/ctrl208fpower.finn +// Source file: ctrl/ctrl208f/ctrl208fpower.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h index 07f0ae9885..a41e40f5a0 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl30f1.finn +// Source file: ctrl/ctrl30f1.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h b/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h index eb9bef58eb..3d2bb0ecc2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl402c.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl402c.finn +// Source file: ctrl/ctrl402c.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h b/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h index e3a9532e5f..33ffad1d0c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl503c.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl503c.finn +// Source file: ctrl/ctrl503c.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h index 22f3fbe3cb..e6a1d038b7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl503c/ctrl503cbase.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl503c/ctrl503cbase.finn +// Source file: ctrl/ctrl503c/ctrl503cbase.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h index 7fd7c369b3..4ff3a45103 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl506f.finn +// Source file: ctrl/ctrl506f.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h index 49297f7ad6..1364253b11 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070base.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070base.finn +// Source file: ctrl/ctrl5070/ctrl5070base.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h index 1916d7fa99..447c8c8046 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070chnc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070chnc.finn +// Source file: ctrl/ctrl5070/ctrl5070chnc.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h index bbfa794d8a..75d7295d9a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070common.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070common.finn +// Source file: ctrl/ctrl5070/ctrl5070common.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h index 5154638830..504c570237 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070event.finn +// Source file: ctrl/ctrl5070/ctrl5070event.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h index 11b79b2806..0f2864a608 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070impoverrides.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070impoverrides.finn +// Source file: ctrl/ctrl5070/ctrl5070impoverrides.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h index 0052168acf..255ce96cf6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070or.finn +// Source file: ctrl/ctrl5070/ctrl5070or.finn // #include "ctrl5070common.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h index a9ce465a0a..40bd67d0a4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070rg.finn +// Source file: ctrl/ctrl5070/ctrl5070rg.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h index 0da723f1ba..a4da5e5468 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070seq.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070seq.finn +// Source file: ctrl/ctrl5070/ctrl5070seq.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h index bbb07e686e..c222907a72 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070system.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070system.finn +// Source file: ctrl/ctrl5070/ctrl5070system.finn // #include "ctrl/ctrl5070/ctrl5070base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h index 6741891c4e..2831174e3d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h @@ -27,6 +27,6 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5070/ctrl5070verif.finn +// Source file: ctrl/ctrl5070/ctrl5070verif.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h index 777bdabc4a..58bd2728f8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5080.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl5080.finn +// Source file: ctrl/ctrl5080.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl83de.h b/src/common/sdk/nvidia/inc/ctrl/ctrl83de.h index 12d792a2a0..5b9b49e07b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl83de.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl83de.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl83de.finn +// Source file: ctrl/ctrl83de.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h index 6ab74be32c..80b69c4b09 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83debase.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl83de/ctrl83debase.finn +// Source file: ctrl/ctrl83de/ctrl83debase.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h index c4c36b0ca4..c798fd705f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl83de/ctrl83dedebug.finn +// Source file: ctrl/ctrl83de/ctrl83dedebug.finn // #include "ctrl/ctrl83de/ctrl83debase.h" @@ -36,7 +36,48 @@ #include "ctrl/ctrl2080/ctrl2080gpu.h" +/* + * NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE + * + * The RmCtrl enables the debug mode for a given context. + * When enabled: + * - The program execution on a SM stops at breakpoints. + * - It allows the user to handle the RC recovery process and + * exceptions. (Yet to be supported) + * - It allows the user to suspend, resume the context. (Yet to be supported) + * + * This command accepts no parameters. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * + */ +#define NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE (0x83de0301) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x1" */ +/* + * NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE + * + * The RmCtrl disables the debug mode for a given context. + * When disabled: + * - The program execution on a SM ignores the breakpoints. + * - RC recovery process and exceptions are handled in the usual way. + * - A request to suspend, resume the context will return error + * NV_ERR_INVALID_COMMAND. + * + * This command accepts no parameters. + * + * Possible return values: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE (0x83de0302) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | 0x2" */ /* * NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h index 43dada9154..e26ce0dc9a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9010.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9010.finn +// Source file: ctrl/ctrl9010.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h index 117b8dda61..4342765fca 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9067.finn +// Source file: ctrl/ctrl9067.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h index 8be99d2205..a2db393618 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl906f.finn +// Source file: ctrl/ctrl906f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h index 8c3cceb4b7..61eb32f05b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9072.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9072.finn +// Source file: ctrl/ctrl9072.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h index 47b8d2f2ac..9970e9f686 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9074.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9074.finn +// Source file: ctrl/ctrl9074.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h index 4aaca210e6..d53413b97b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9096.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl9096.finn +// Source file: ctrl/ctrl9096.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h index fa02e75323..3b12db4bb0 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cc.finn +// Source file: ctrl/ctrl90cc.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h index 707ec03c24..5a6698b69f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccbase.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cc/ctrl90ccbase.finn +// Source file: ctrl/ctrl90cc/ctrl90ccbase.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h index b1013f29de..0abb89aeb9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90cchwpm.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn +// Source file: ctrl/ctrl90cc/ctrl90cchwpm.finn // #include "ctrl/ctrl90cc/ctrl90ccbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h index aa25ceb2c4..58bd91e324 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cc/ctrl90ccpower.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cc/ctrl90ccpower.finn +// Source file: ctrl/ctrl90cc/ctrl90ccpower.finn // #include "ctrl/ctrl90cc/ctrl90ccbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h index 29449abe4c..6113271552 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90cd.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90cd.finn +// Source file: ctrl/ctrl90cd.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h index ad1d9fbe50..c05837d041 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90e6.finn +// Source file: ctrl/ctrl90e6.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h index 00094c1980..1ee51f74ff 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90ec.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90ec.finn +// Source file: ctrl/ctrl90ec.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h index 7bd3b5f205..c98c8cb3de 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl90f1.finn +// Source file: ctrl/ctrl90f1.finn // #include "ctrl/ctrlxxxx.h" @@ -83,6 +83,34 @@ typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS { */ #define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */ +typedef struct NV_CTRL_VASPACE_PAGE_LEVEL { + /*! + * Format of this level. + */ + NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); + + /*! + * Level/Sublevel Formats flattened + */ + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); + NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); + + /*! + * Physical address of this page level instance. + */ + NV_DECLARE_ALIGNED(NvU64 physAddress, 8); + + /*! + * Aperture in which this page level instance resides. + */ + NvU32 aperture; + + /*! + * Size in bytes allocated for this level instance. + */ + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV_CTRL_VASPACE_PAGE_LEVEL; + #define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U) typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { @@ -115,33 +143,7 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { /*! * [out] Per-level information. */ - struct { - /*! - * Format of this level. - */ - NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); - - /*! - * Level/Sublevel Formats flattened - */ - NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); - NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); - - /*! - * Physical address of this page level instance. - */ - NV_DECLARE_ALIGNED(NvU64 physAddress, 8); - - /*! - * Aperture in which this page level instance resides. - */ - NvU32 aperture; - - /*! - * Size in bytes allocated for this level instance. - */ - NV_DECLARE_ALIGNED(NvU64 size, 8); - } levels[GMMU_FMT_MAX_LEVELS]; + NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8); } NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS; /*! diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h index a77df66c21..7526b21467 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06c.finn +// Source file: ctrl/ctrla06c.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f.h index b768326f54..5436cfd707 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f.finn +// Source file: ctrl/ctrla06f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h index 39c977a5a1..0329a0702c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f/ctrla06fbase.finn +// Source file: ctrl/ctrla06f/ctrla06fbase.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h index 245673bbf2..663467b509 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f/ctrla06fevent.finn +// Source file: ctrl/ctrla06f/ctrla06fevent.finn // #include "ctrl/ctrla06f/ctrla06fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h index 32b179170f..41a5b4f1d3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn +// Source file: ctrl/ctrla06f/ctrla06fgpfifo.finn // #include "ctrl/ctrla06f/ctrla06fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h index 83e064dcf2..903a5bb18d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla06f/ctrla06finternal.finn +// Source file: ctrl/ctrla06f/ctrla06finternal.finn // #include "ctrl/ctrla06f/ctrla06fbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h index 29ad3ef535..b259fcd7ab 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h @@ -28,7 +28,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla080.finn +// Source file: ctrl/ctrla080.finn // @@ -643,6 +643,9 @@ typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_FALSE (0x00000000) #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_TRUE (0x00000001) /* UVM supported features */ #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla081.h b/src/common/sdk/nvidia/inc/ctrl/ctrla081.h index e85964d5fa..6f7fb51b45 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla081.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla081.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla081.finn +// Source file: ctrl/ctrla081.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla084.h b/src/common/sdk/nvidia/inc/ctrl/ctrla084.h index 8145c27b1b..d00d8e0259 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla084.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla084.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,10 +27,9 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla084.finn +// Source file: ctrl/ctrla084.finn // -#include "nv_vgpu_types.h" #include "ctrl/ctrlxxxx.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_GPU_MAX_GID_LENGTH #include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES @@ -237,67 +236,6 @@ typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS NvBool bNotifyState; } NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS; -/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE - * - * This command is used to set SRIOV state parameters in RM. - * - * Parameters: - * - * numPluginChannels [IN] - * Number of channels required by plugin - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - */ -#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE (0xa0840108) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID" */ - -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_MAX_PLUGIN_CHANNELS 5 - -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID (0x8U) - -typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS { - NvU32 numPluginChannels; -} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS; - -/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID - * - * This command is used to set/unset VM ID parameters in host vgpu device in RM. - * - * Parameters: - * - * action - * This parameter specifies the desired set guest id action. - * Valid set guest id actions include: - * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_SET - * This action sets the VM ID information in host vgpu device. - * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_UNSET - * This action unsets the VM ID information in host vgpu device. - * vmPid [IN] - * VM process ID - * vmIdType[IN] - * VM ID type whether it's UUID or DOMAIN_ID - * guestVmId[IN] - * VM ID - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - */ -#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID (0xa0840109) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID" */ - -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID (0x9U) - -typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS { - NvU8 action; - NvU32 vmPid; - VM_ID_TYPE vmIdType; - NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); -} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS; - -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000) -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001) - /* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GER_BAR_MAPPING_RANGES * * This command is used to get Bar mapping ranges in RM. @@ -333,4 +271,17 @@ typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS NvBool mitigated[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES]; } NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS; +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_RESTORE_DEFAULT_EXEC_PARTITION + * + * This command restores the vGPU device's default EXEC partition saved in + * KERNEL_HOST_VGPU_DEVICE. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_RESTORE_DEFAULT_EXEC_PARTITION (0xa084010b) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | 0xB" */ + /* _ctrla084_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h b/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h index eceee332d7..f59b0b5f28 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla16f.finn +// Source file: ctrl/ctrla16f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h b/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h index 5e222a48d5..8c3e90fcd9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla26f.finn +// Source file: ctrl/ctrla26f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h index ce73991073..bf31d6466b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb069.finn +// Source file: ctrl/ctrlb069.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h index ddfac2b05d..88906d1ac9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb06f.finn +// Source file: ctrl/ctrlb06f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h index decc79af6e..1148c9a080 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb0cc.finn +// Source file: ctrl/ctrlb0cc.finn // @@ -35,3 +35,363 @@ #include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_GPU_REG_OP #include "ctrlb0cc/ctrlb0ccprofiler.h" #include "ctrlb0cc/ctrlb0ccinternal.h" +#include "ctrlb0cc/ctrlb0ccpower.h" + +/* + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple MAXWELL_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the MAXWELL_PROFILER object is freed or + * the NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS command is called for that + * feature. + * + * Currently, only MAXWELL_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by MAXWELL_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the MAXWELL_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * MAXWELL_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST, the value will be + * one of the following: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES + +typedef NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS NVB0CC_CTRL_PROFILER_REQUEST_CG_CONTROLS_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG 1:0 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG 3:2 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG 7:6 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN 9:8 +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE (0x00000000) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE (0x00000001) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE (0x00000002) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE NVB0CC_CTRL_PROFILER_CG_CONTROL_IGNORE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_DISABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_DISABLE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_ENABLE NVB0CC_CTRL_PROFILER_CG_CONTROL_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED (0x00000000) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED (0x00000001) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED (0x00000002) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED (0x00000003) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FULFILLED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_REJECTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_REQUEST_FAILED NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_IGNORE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _IGNORE) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_DISABLE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _DISABLE) +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_ENABLE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _ENABLE) + +/* + * NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS + * + * This command is deprecated; please us + * NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES. + * + * This command releases the MAXWELL_PROFILER's request for the given clock- + * gating features that was previously created by the + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS command. If the MAXWELL_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS. The RM only reference- + * counts the settings requested by MAXWELL_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * MAXWELL_PROFILER instance. + * + * All outstanding requests made using this MAXWELL_PROFILER object are + * implicitly released when the MAXWELL_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the MAXWELL_PROFILER's reference to. See + * NVB0CC_CTRL_CMD_PROFILER_REQUEST_CG_CONTROLS for valid fields. Valid + * values for each field are: + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_IGNORE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the MAXWELL_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE + * This value indicates that the MAXWELL_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the MAXWELL_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_PROFILER_RELEASE_CG_CONTROLS NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES + +typedef NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS NVB0CC_CTRL_PROFILER_RELEASE_CG_CONTROLS_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_*_IGNORE + */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE (0x00000003) + +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_BLCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_SLCG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ELPG_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_IDLE_SLOWDOWN_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_VAT_RELEASE NVB0CC_CTRL_PROFILER_CG_CONTROL_RELEASE + +/* utility mask for the controlMask parameter for all fields */ +#define NVB0CC_CTRL_PROFILER_CG_CONTROL_MASK_ALL_RELEASE \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, _VAT, _RELEASE) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h index a6d2929f31..54c644119b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccbase.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn +// Source file: ctrl/ctrlb0cc/ctrlb0ccbase.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h index f98a32dda4..533748f6fb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn +// Source file: ctrl/ctrlb0cc/ctrlb0ccinternal.finn // #include "ctrl/ctrlb0cc/ctrlb0ccbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h new file mode 100644 index 0000000000..672aa24e2f --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccpower.h @@ -0,0 +1,402 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlb0cc/ctrlb0ccpower.finn +// + +#include "ctrl/ctrlb0cc/ctrlb0ccbase.h" + +/* + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES + * + * This command attempts to enable or disable various clock-gating features of + * the GPU on behalf of the profiler. If this command is unable to set the + * clock-gating feature state of any of the requested features, this command + * will fail and none of the requested features will be modified. If this + * command fails because one or more clock-gating feature requests were + * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus + * parameter and the fields in the statusMask parameter for the features for + * which the requests were rejected will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED. + * If a given feature is not supported on the GPU, the field for that clock- + * gating feature will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the + * statusMask parameter, but this condition by itself will not cause the + * command to fail. Even if this command fails, the field for clock-gating + * features which would have successfully changed will have the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask + * parameter. + * + * Each of the clock-gating features is reference-counted individually, so + * that multiple MAXWELL_PROFILER objects may request and rely on the same + * settings for the features simultaneously. Each clock-gating feature is + * locked to the requested state until the MAXWELL_PROFILER object is freed or + * the NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that + * feature. + * + * Currently, only MAXWELL_PROFILER requests for power features using this + * command are reference counted. Changes to the power feature settings made + * either by other control commands or the RM itself may interfere with the + * settings requested by MAXWELL_PROFILER instances. + * + * This command will always return NV_OK when given valid + * parameters. If there is any other failure that prevents the clock-gating + * features from being set appropriately, the globalStatus parameter will + * indicate this and the statusMask parameter will indicate which clock-gating + * feature requests failed and why. + * + * controlMask + * This parameter indicates which clock-gating features the request should + * apply to. This parameter has the following fields: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG + * The value of this field indicates whether this request should apply + * to engine-level clock-gating of the GR engine. Valid values for + * this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * This value indicates that the GR engine-level clock-gating + * should be ignored. This will not affect the reference count for + * this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE + * This value indicates that the GR engine-level clock-gating + * should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE + * This value indicates that the GR engine-level clock-gating + * should be enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG + * The value of this field indicates whether this request should apply + * to block-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * This value indicates that block-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE + * This value indicates that block-level clock-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE + * This value indicates that block-level clock-gating should be + * enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG + * The value of this field indicates whether this request should apply + * to second-level clock-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * This value indicates that second-level clock-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE + * This value indicates that second-level clock-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE + * This value indicates that second-level clock-gating should be + * enabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG + * The value of this field indicates whether this request should apply + * to GR engine-level power-gating. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * This value indicates that engine-level power-gating should be + * ignored. This will not affect the reference count for this + * feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE + * This value indicates that engine-level power-gating should be + * disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE + * This value indicates that engine-level power-gating should be + * enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN + * The value of this field indicates whether this request should apply + * to SM idle slowdown. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * This value indicates that SM idle slowdown should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE + * This value indicates that SM idle slowdown should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE + * This value indicates that SM idle slowdown should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT + * The value of this field indicates whether this request should apply + * to VAT. Valid values for this field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that VAT should be ignored. + * This will not affect the reference count for this feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE + * This value indicates that VAT should be disabled. + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE + * This value indicates that VAT should be enabled. + * Note that this field is only temporary to allow reference counting + * restricted to MAXWELL_PROFILER instances, until the time when the + * existing controls for this power feature can be updated to support + * reference counting across all clients and the RM. + * globalStatus + * This parameter returns the overall status of the requests for all + * clock-gating controls. If the value of this parameter is not + * NV_OK, none of the clock-gating controls will be set as + * requested. Possible values for this parameter are: + * NV_OK + * This value indicates that all of the clock-gating control requests + * were either fulfilled or not supported on the hardware. + * NV_ERR_INVALID_REQUEST + * This value indicates that at least one of the clock-gating control + * requests were invalid given the MAXWELL_PROFILER instance's + * outstanding requests. + * NV_ERR_STATE_IN_USE + * This value indicates that at least one of the clock-gating controls + * has already been locked to a conflicting state by another + * MAXWELL_PROFILER instance or the RM itself. + * statusMask + * This parameter returns the status of the request to set each clock- + * gating control specified by the controlMask parameter. The fields are + * identical to those of the controlMask parameter. For each field for + * which the corresponding field in the controlMask parameter has the + * value NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is + * undefined. For each field for which the corresponding field in the + * controlMask parameter has the value + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be + * one of the following: + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED + * This value indicates that the clock-gating feature corresponding to + * the field in question was enabled or disabled according to the + * controlMask parameter, and the reference count for the feature was + * incremented accordingly. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because another conflicting request is + * currently outstanding for the clock-gating feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED + * This value indicates that the clock-gating feature corresponding to + * the field in question was not set to the expected state according + * to the controlMask parameter because the attempt to do so failed + * with an error other than a conflicting request. + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED + * This value indicates that the clock-gating feature corresponding to + * the field in question is not supported on this GPU. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES (0xb0cc0301) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS { + NvU32 globalStatus; + NvU32 controlMask; + NvU32 statusMask; +} NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS; + +/* valid fields for the controlMask and statusMask parameters */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG 1:0 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG 3:2 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG 7:6 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN 9:8 +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT 11:10 + +/* valid values for fields in the controlMask parameter */ +#define NVB0CC_CTRL_POWER_FEATURE_IGNORE (0x00000000) +#define NVB0CC_CTRL_POWER_FEATURE_DISABLE (0x00000001) +#define NVB0CC_CTRL_POWER_FEATURE_ENABLE (0x00000002) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE +/* possible values for fields in the statusMask parameter */ +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED (0x00000000) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED (0x00000001) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED (0x00000002) +#define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED (0x00000003) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED + +/* utility masks for the controlMask parameter for all controls */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) | \ + DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_VAT) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE) +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE) + +/* + * NVB0CC_CTRL_CMD_POWER_RELEASE_FEATUERS + * + * This command releases the MAXWELL_PROFILER's request for the given clock- + * gating features that was previously created by the + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the MAXWELL_PROFILER + * object does not have an outstanding request to one or more of the given + * clock-gating features, those features will be ignored while the other + * feature requests will be released. + * + * After calling this command, the calling client may not rely on the current + * value of any of the released clock-gating features to remain, even if + * several identical requests for the given clock-gating features were made + * using NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference- + * counts the settings requested by MAXWELL_PROFILER instances - it does not + * reference-count multiple identical requests made using the same + * MAXWELL_PROFILER instance. + * + * All outstanding requests made using this MAXWELL_PROFILER object are + * implicitly released when the MAXWELL_PROFILER is freed. + * + * controlMask + * This parameter indicates which clock-gating features the RM should + * release the MAXWELL_PROFILER's reference to. See + * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid + * values for each field are: + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE + * This value indicates that the clock-gating feature associated with + * the field should not be released, even if the MAXWELL_PROFILER has an + * outstanding request for it. This will not affect the reference + * count for the feature. + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE + * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE + * This value indicates that the MAXWELL_PROFILER's outstanding request + * for the clock-gating feature associated with the field should be + * released. This will decrement the reference count for the feature + * if the MAXWELL_PROFILER has an outstanding request for it. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES (0xb0cc0302) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS { + NvU32 controlMask; +} NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS; + +/* + * valid values for the controlMask parameter in addition to + * NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE + */ +#define NVB0CC_CTRL_POWER_FEATURE_RELEASE (0x00000003) + +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE +#define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE + + +/* _ctrlb0ccpower_h_ */ + +/* utility mask for the controlMask parameter for all fields */ +#define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) | \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ + DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h index 0e2685fe0b..74bab8e6d8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn +// Source file: ctrl/ctrlb0cc/ctrlb0ccprofiler.finn // #include "ctrl/ctrlb0cc/ctrlb0ccbase.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h index 8e7aadb6e2..e999a8db31 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc06f.finn +// Source file: ctrl/ctrlc06f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h index fc23e132bc..55afe38d85 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc365.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc365.finn +// Source file: ctrl/ctrlc365.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h index 731db4ad8e..00f63e8cfe 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc369.finn +// Source file: ctrl/ctrlc369.finn // #include "ctrl/ctrlxxxx.h" @@ -80,6 +80,7 @@ typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS { NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); NV_DECLARE_ALIGNED(NvP64 pShadowBufferContext, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferMetadata, 8); NvU32 bufferSize; } NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS; @@ -127,6 +128,7 @@ typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS { typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS { NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); + NV_DECLARE_ALIGNED(NvP64 pShadowBufferMetadata, 8); NvU32 bufferSize; } NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h index c3c4209ce3..979f55c5fb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc36f.finn +// Source file: ctrl/ctrlc36f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h index c132cc07a4..7e4ac399e4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370base.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370base.finn +// Source file: ctrl/ctrlc370/ctrlc370base.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h index 16a263fd47..fa75bbffb0 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370chnc.finn +// Source file: ctrl/ctrlc370/ctrlc370chnc.finn // #include "ctrl/ctrlc370/ctrlc370base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h index ef18c7d895..6cfb57430f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370event.finn +// Source file: ctrl/ctrlc370/ctrlc370event.finn // #include "ctrl/ctrlc370/ctrlc370base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h index 2a4928453e..a7e4a791f3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370rg.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370rg.finn +// Source file: ctrl/ctrlc370/ctrlc370rg.finn // #include "ctrl/ctrlc370/ctrlc370base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h index d891974e56..bb58fae240 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370verif.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc370/ctrlc370verif.finn +// Source file: ctrl/ctrlc370/ctrlc370verif.finn // #include "ctrl/ctrlc370/ctrlc370base.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h index 2d4aea5c57..d8423a238c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372base.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc372/ctrlc372base.finn +// Source file: ctrl/ctrlc372/ctrlc372base.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h index 743663c244..3e2f6e8d10 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc372/ctrlc372chnc.finn +// Source file: ctrl/ctrlc372/ctrlc372chnc.finn // #include "nvdisptypes.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h index c53e217b8e..ef7cc63e14 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc46f.finn +// Source file: ctrl/ctrlc46f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h index a781b1abef..1a226c28ee 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc56f.finn +// Source file: ctrl/ctrlc56f.finn // @@ -40,6 +40,8 @@ #include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */ #include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F +#include "cc_drv.h" + #define NVC56F_CTRL_CMD(cat,idx) \ @@ -160,6 +162,50 @@ typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { NvU32 workSubmitToken; } NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; +/* + * NVC56F_CTRL_CMD_GET_KMB + * + * This command returns the Key Material Bundle (KMB) for the current channel. + * + * kmb [OUT] The KMB for the channel. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC56F_CTRL_CMD_GET_KMB (0xc56f010b) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC56F_CTRL_CMD_GET_KMB_PARAMS_MESSAGE_ID" */ + +#define NVC56F_CTRL_CMD_GET_KMB_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NVC56F_CTRL_CMD_GET_KMB_PARAMS { + CC_KMB kmb; +} NVC56F_CTRL_CMD_GET_KMB_PARAMS; + +/* + * NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV + * + * This command rotates the IVs for secure channels. + * + * rotateIvType [IN] Which IVs to rotate. + * updatedKmb [OUT] Updated KMB after the IV rotation. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV (0xc56f010c) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS_MESSAGE_ID" */ + +#define NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS { + ROTATE_IV_TYPE rotateIvType; + CC_KMB updatedKmb; +} NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS; + /* _ctrlc56f.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h index 07adb74f2b..16c69a74aa 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc637.finn +// Source file: ctrl/ctrlc637.finn // #include "ctrl/ctrlxxxx.h" @@ -311,8 +311,9 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO { } NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO; typedef struct NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS { - NvU32 id; + NvU32 id; NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO info, 8); + NvBool bCreateCap; } NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS; /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h index f9cf5fb190..5e848a9225 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc638.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc638.finn +// Source file: ctrl/ctrlc638.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h index 68687b3001..861935fd97 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc763.finn +// Source file: ctrl/ctrlc763.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h index eeb89236d4..0f2113dd80 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlc86f.finn +// Source file: ctrl/ctrlc86f.finn // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h b/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h new file mode 100644 index 0000000000..2fd409c5dc --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h @@ -0,0 +1,384 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlcb33.finn +// + + + +#include "nvcfg_sdk.h" +#include "ctrl/ctrlxxxx.h" +/* NV_CONF_COMPUTE control commands and parameters */ + +#define NV_CONF_COMPUTE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCB33, NVCB33_CTRL_##cat, idx) + +#define NVCB33_CTRL_RESERVED (0x00) +#define NVCB33_CTRL_CONF_COMPUTE (0x01) + +/* + * NV_CONF_COMPUTE_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible return values: + * NV_OK + */ +#define NV_CONF_COMPUTE_CTRL_CMD_NULL (0xcb330000) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES + * This control call returns overall system and gpu capabilities + * + * Final operating environment depends on a lot of factors: + * APM: Ampere Protected Memory + * HCC: Hopper Confidential Compute + * --------------------------------------------------------------------------- + * SrNo CPU TEE GPU TEE GPU Platform GPU mode SW Status System Env + * --------------------------------------------------------------------------- + * 1 AMD SEV APM/HCC Silicon Production Production Production + * 2 AMD SEV APM/HCC Silicon Production Development Simulation + * 3 APM/HCC Debug Simulation + * 4 Non SEV APM/HCC Simulation + * 5 APM/HCC FMOD/EMU/RTL Simulation + * --------------------------------------------------------------------------- + * + * Prameters: + * cpuCapability: [OUT] + * This indicates if cpu is capable of AMD SEV + * gpusCapability: [OUT] + * This indicates if all gpus in the system support APM/HCC. + * This field doesn't mean APM/HCC is enabled. + * environment: [OUT] + * System environment can be production or simulation + * ccFeature: [OUT] + * Specifies if all gpus in the system have APM/HCC feature enabled + * CC feature can be enabled/disabled using this control call: + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_CC_FEATURE + * devToolsMode: [OUT] + * Dev tools mode is used for debugging/profiling + * Dev tools mode is set at system level and implies that all GPUs in + * the system have this mode enabled/disabled + * + * cpuCapability, gpusCapability & environment are determined by the + * driver and cannot be modified later on + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */ + +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1 + +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2 + +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2 + +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2 + +#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0 +#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1 + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS { + NvU8 cpuCapability; + NvU8 gpusCapability; + NvU8 environment; + NvU8 ccFeature; + NvU8 devToolsMode; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE + * This control call can be used to determine if all GPUs are ready to accept + * work form clients. + * + * bAcceptClientRequest: [OUT] + * NV_TRUE: all gpus accepting client work requests + * NV_FALSE: all gpus blocking client work requests + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE (0xcb330104) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x4" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS { + NvBool bAcceptClientRequest; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE + * This control call can be used to set gpu state to accept client requests + * or to block client requests + * This is a PRIVILEGED control call and can be set via admin tools + * + * bAcceptClientRequest:[IN] + * NV_TRUE: set all gpus state to accept client work requests + * NV_FALSE: set all gpus state to block client work requests + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE (0xcb330105) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x5" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS { + NvBool bAcceptClientRequest; +} NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE + * This control call returns protected and unprotected vidmem size + * + * hSubDevice: [IN] + * subdevice handle for the gpu whose vidmem size is requested + * protectedMemSizeInKb: [OUT] + * total protected memory size in kB + * unprotectedMemSizeInKb: [OUT] + * total unprotected memory size in kB + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE (0xcb330106) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x6" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS { + NvHandle hSubDevice; + NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8); + NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8); +} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE + * This control call updates protected and unprotected vidmem size. + * All memory is protected if APM/HCC is enabled. User can override + * unprotectedMemSizeInKb and that will adjust protectedMemSizeInKb accordingly. + * This is a PRIVILEGED control call and can be set via tools like nvidia-smi. + * Vidmem size can be updated after driver load and before any client FB + * allocations are made. + * + * hSubDevice: [IN] + * subdevice handle for the gpu whose vidmem size is requested + * protectedMemSizeInKb: [OUT] + * total protected memory size in kB + * unprotectedMemSizeInKb: [IN/OUT] + * total unprotected memory size in kB + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INSUFFICIENT_PERMISSIONS + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE (0xcb330107) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x7" */ + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS { + NvHandle hSubDevice; + NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8); + NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8); +} NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS + * This control call returns the max number of AES capable channels SEC2 and CE support. + * + * hSubDevice: [IN] + * subdevice handle for the GPU queried + * numSupportedSec2CCSecureChannels: [OUT] + * Max number of AES capable channels SEC2 supports + * numSupportedCeCCSecureChannels: [OUT] + * Max number of channels CE supports with encrypt/decrypt + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS (0xcb330108) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x8" */ + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS { + NvHandle hSubDevice; + NvU32 numSupportedSec2CCSecureChannels; + NvU32 numSupportedCeCCSecureChannels; +} NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE + * This control call returns the GPU session certificate for the specified GPU. + * The certificate size is the maximum of the certificate size of APM and CC. + * + * hSubDevice: [IN] + * Subdevice handle for the GPU queried + * certChain: [OUT] + * Certificate chain for the GPU queried + * certChainSize: [OUT] + * Actual size of certChain data + * attestationCertChain: [OUT] + * Attestation certificate chain for the GPU queried + * attestationCertChainSize: [OUT] + * Actual size of attestationCertChain data + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE (0xcb330109) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x9" */ + +#define NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE 0x1000 +#define NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE 0x1400 + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS { + NvHandle hSubDevice; + NvU8 certChain[NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE]; + NvU32 certChainSize; + NvU8 attestationCertChain[NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE]; + NvU32 attestationCertChainSize; +} NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS; + + /* + * NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION + * This control call returns the GPU attestation report for the specified GPU. + * The attestation report size is the maximum of the attestation report size of APM and CC. + * + * hSubDevice: [IN] + * Subdevice handle for the GPU queried + * nonce: [IN] + * spdm supports 32 bytes on nonce + * attestationReport: [OUT] + * Attestation report of the GPU queried + * attestationReportSize: [OUT] + * Actual size of the report + * isCecAttestationReportPresent : [OUT] + * Indicates if the next 2 feilds are valid + * cecAttestationReport: [OUT] + * Cec attestation report for the gpu queried + * cecAttestationReportSize: [OUT] + * Actual size of the cec attestation report + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT (0xcb33010a) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xA" */ + +#define NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE 0x2000 +#define NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE 0x1000 +#define NV_CONF_COMPUTE_NONCE_SIZE 0x20 + +#define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS { + NvHandle hSubDevice; + NvU8 nonce[NV_CONF_COMPUTE_NONCE_SIZE]; + NvU8 attestationReport[NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE]; + NvU32 attestationReportSize; + NvBool isCecAttestationReportPresent; + NvU8 cecAttestationReport[NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE]; + NvU32 cecAttestationReportSize; +} NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS + * This control call returns the max number of Conf Compute capable channels SEC2 and CE support. + * + * hSubDevice: [IN] + * subdevice handle for the GPU queried + * maxSec2Channels: [OUT] + * Max number of conf compute capable channels SEC2 supports + * maxCeChannels: [OUT] + * Max number of channels CE supports with encrypt/decrypt + * + * Possible return values: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_CLIENT + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS (0xcb33010b) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xB" */ + +#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS { + NvHandle hSubDevice; + NvU32 maxSec2Channels; + NvU32 maxCeChannels; +} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS; + +/* _ctrlcb33_h_ */ + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h b/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h index 1e47decf97..a034f923f0 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlcbca.finn +// Source file: ctrl/ctrlcbca.finn // #include "ctrl/ctrlxxxx.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h b/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h index 3949b87a15..3daf2358f2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h @@ -27,7 +27,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrlxxxx.finn +// Source file: ctrl/ctrlxxxx.finn // diff --git a/src/common/sdk/nvidia/inc/g_finn_rm_api.h b/src/common/sdk/nvidia/inc/g_finn_rm_api.h index bf74e359fb..7f26fd544f 100644 --- a/src/common/sdk/nvidia/inc/g_finn_rm_api.h +++ b/src/common/sdk/nvidia/inc/g_finn_rm_api.h @@ -40,7 +40,7 @@ * FINN compiler version */ #define FINN_VERSION_MAJOR 1 -#define FINN_VERSION_MINOR 17 +#define FINN_VERSION_MINOR 21 #define FINN_VERSION_PATCH 0 typedef struct FINN_RM_API @@ -58,8 +58,8 @@ typedef struct FINN_RM_API * @brief Private functions not to be called directly */ /**@{*/ -NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char **dst, NvLength dst_size, NvBool seri_up); -NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up); +NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char *dst, NvLength dst_size, NvBool seri_up); +NV_STATUS finnDeserializeInternal_FINN_RM_API(const char *src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up); /**@}*/ @@ -78,12 +78,8 @@ NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_siz * * @param[in] interface FINN interface ID of the param struct. * @param[in] message FINN message ID of the param struct. - * @param[in] api Pointer to the source param struct from which to - * copy the data. - * @param[in, out] dst Double pointer to the destination buffer into - * which to copy the data. *dst will be set to - * *dst + serialized size on success and to the - * location of failed serialization on failure. + * @param[in] api Source param struct from which to copy the data. + * @param[in] dst Destination buffer into which to copy the data. * @param[in] dst_size Maximum size of the destination buffer measured in * `NvU8` units. * @@ -96,13 +92,13 @@ NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_siz * @retval NV_ERR_BUFFER_TOO_SMALL Destination buffer size too small. */ /**@{*/ -static NV_INLINE NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *api, NvU8 **dst, NvLength dst_size) +static NV_INLINE NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *api, NvU8 *dst, NvLength dst_size) { - return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char **) dst, dst_size, NV_TRUE); + return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char *) dst, dst_size, NV_TRUE); } -static NV_INLINE NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *api, NvU8 **dst, NvLength dst_size) +static NV_INLINE NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *api, NvU8 *dst, NvLength dst_size) { - return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char **) dst, dst_size, NV_FALSE); + return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char *) dst, dst_size, NV_FALSE); } /**@}*/ @@ -124,14 +120,10 @@ static NV_INLINE NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message * @warning One of these may be unimplemented depending on platform. If both * are implemented, misuse causes memory corruption and memory leaks. * - * @param[in, out] src Double pointer to the source buffer from which to - * copy the data. *src is set to *src + serialized - * size on success and to the location of failed - * deserialization on failure. + * @param[in] src Source buffer from which to copy the data. * @param[in] src_size Maximum size of the source buffer measured in * `NvU8` units. - * @param[in, out] api Pointer to the destination param struct into which - * to copy the data. + * @param[in, out] api Destination param struct into which to copy the data. * @param[in] api_size Size of the destination param struct measured in * `char` units per `sizeof` operator. * @@ -146,13 +138,13 @@ static NV_INLINE NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message * @retval NV_ERR_LIB_RM_VERSION_MISMATCH Version mismatch. */ /**@{*/ -static NV_INLINE NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *api, NvLength api_size) +static NV_INLINE NV_STATUS FinnRmApiDeserializeDown(NvU8 *src, NvLength src_size, void *api, NvLength api_size) { - return finnDeserializeInternal_FINN_RM_API((const char **) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_FALSE); + return finnDeserializeInternal_FINN_RM_API((const char *) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_FALSE); } -static NV_INLINE NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *api, NvLength api_size) +static NV_INLINE NV_STATUS FinnRmApiDeserializeUp(NvU8 *src, NvLength src_size, void *api, NvLength api_size) { - return finnDeserializeInternal_FINN_RM_API((const char **) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_TRUE); + return finnDeserializeInternal_FINN_RM_API((const char *) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_TRUE); } /**@}*/ @@ -241,6 +233,10 @@ typedef FINN_RM_API FINN_NV01_MEMORY_SYSTEM_MEMORY; typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED; #define FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID (0x4101U) typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY; +#define FINN_NV_CE_UTILS_RESERVED_INTERFACE_ID (0x0050U) +typedef FINN_RM_API FINN_NV_CE_UTILS_RESERVED; +#define FINN_NV_CE_UTILS_UTILS_INTERFACE_ID (0x5001U) +typedef FINN_RM_API FINN_NV_CE_UTILS_UTILS; #define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED; #define FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID (0x7305U) @@ -250,6 +246,8 @@ typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP; #define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP; +#define FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID (0x7303U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_EVENT; #define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL; #define FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID (0x7316U) @@ -289,13 +287,13 @@ typedef FINN_RM_API FINN_NV01_DEVICE_0_NVJPG; #define FINN_NV01_DEVICE_0_PERF_INTERFACE_ID (0x8019U) typedef FINN_RM_API FINN_NV01_DEVICE_0_PERF; -#define FINN_NV01_DEVICE_0_RC_INTERFACE_ID (0x801dU) -typedef FINN_RM_API FINN_NV01_DEVICE_0_RC; #define FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID (0x801eU) typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; #define FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID (0x9001U) typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; +#define FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID (0x00da00U) +typedef FINN_RM_API FINN_NV_SEMAPHORE_SURFACE; #define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) typedef FINN_RM_API FINN_IMEX_SESSION; #define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) @@ -335,6 +333,7 @@ typedef FINN_RM_API FINN_NV_MEMORY_MAPPER; #define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED; + #define FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID (0x208008U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_BIOS; #define FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID (0x208018U) @@ -404,6 +403,9 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVLINK; #define FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID (0x208020U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PERF; +#define FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID (0x208027U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_POWER; + #define FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID (0x208022U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RC; #define FINN_NV20_SUBDEVICE_0_SEC2_INTERFACE_ID (0x208042U) @@ -635,6 +637,8 @@ typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT; typedef FINN_RM_API FINN_MAXWELL_PROFILER_RESERVED; #define FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID (0xb0cc02U) typedef FINN_RM_API FINN_MAXWELL_PROFILER_INTERNAL; +#define FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID (0xb0cc03U) +typedef FINN_RM_API FINN_MAXWELL_PROFILER_POWER; #define FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID (0xb0cc01U) typedef FINN_RM_API FINN_MAXWELL_PROFILER_PROFILER; #define FINN_MAXWELL_PROFILER_CONTEXT_RESERVED_INTERFACE_ID (0xb1cc00U) @@ -730,6 +734,11 @@ typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_GPFIFO; #define FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc86f02U) typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_EVENT; +#define FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID (0xcb3300U) +typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED; +#define FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID (0xcb3301U) +typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE; + #define FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED_INTERFACE_ID (0xcbca00U) typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED; #define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U) diff --git a/src/common/sdk/nvidia/inc/mmu_fmt_types.h b/src/common/sdk/nvidia/inc/mmu_fmt_types.h index ecbe2aaebf..13bb88f123 100644 --- a/src/common/sdk/nvidia/inc/mmu_fmt_types.h +++ b/src/common/sdk/nvidia/inc/mmu_fmt_types.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: mmu_fmt_types.finn +// Source file: mmu_fmt_types.finn // diff --git a/src/common/sdk/nvidia/inc/nv-hypervisor.h b/src/common/sdk/nvidia/inc/nv-hypervisor.h index 422f258b2c..93bcdd6e67 100644 --- a/src/common/sdk/nvidia/inc/nv-hypervisor.h +++ b/src/common/sdk/nvidia/inc/nv-hypervisor.h @@ -41,6 +41,7 @@ typedef enum _HYPERVISOR_TYPE #define CMD_VGPU_VFIO_INJECT_INTERRUPT 1 #define CMD_VGPU_VFIO_REGISTER_MDEV 2 #define CMD_VGPU_VFIO_PRESENT 3 +#define CMD_VFIO_PCI_CORE_PRESENT 4 #define MAX_VF_COUNT_PER_GPU 64 @@ -57,6 +58,7 @@ typedef struct void *waitQueue; void *nv; NvU32 *vgpuTypeIds; + NvU8 **vgpuNames; NvU32 numVgpuTypes; NvU32 domain; NvU8 bus; diff --git a/src/common/sdk/nvidia/inc/nv_vgpu_types.h b/src/common/sdk/nvidia/inc/nv_vgpu_types.h index fae9985954..eea5638835 100644 --- a/src/common/sdk/nvidia/inc/nv_vgpu_types.h +++ b/src/common/sdk/nvidia/inc/nv_vgpu_types.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nv_vgpu_types.finn +// Source file: nv_vgpu_types.finn // diff --git a/src/common/sdk/nvidia/inc/nvdisptypes.h b/src/common/sdk/nvidia/inc/nvdisptypes.h index 90d8ac0156..7ebe391c43 100644 --- a/src/common/sdk/nvidia/inc/nvdisptypes.h +++ b/src/common/sdk/nvidia/inc/nvdisptypes.h @@ -35,7 +35,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nvdisptypes.finn +// Source file: nvdisptypes.finn // diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index 49e3296680..6d8411018b 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 1993-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -118,8 +118,9 @@ #define SPI_PMU_RPC_ERASE_FAIL (124) #define INFOROM_FS_ERROR (125) #define ALI_TRAINING_FAIL (136) -#define ROBUST_CHANNEL_LAST_ERROR (ALI_TRAINING_FAIL) #define NVLINK_FLA_PRIV_ERR (137) +#define ROBUST_CHANNEL_DLA_ERROR (138) +#define ROBUST_CHANNEL_LAST_ERROR (ROBUST_CHANNEL_DLA_ERROR) // Indexed CE reference diff --git a/src/common/sdk/nvidia/inc/nvimpshared.h b/src/common/sdk/nvidia/inc/nvimpshared.h index eb4dc72584..c86d71879a 100644 --- a/src/common/sdk/nvidia/inc/nvimpshared.h +++ b/src/common/sdk/nvidia/inc/nvimpshared.h @@ -35,7 +35,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nvimpshared.finn +// Source file: nvimpshared.finn // diff --git a/src/common/sdk/nvidia/inc/nvlimits.h b/src/common/sdk/nvidia/inc/nvlimits.h index a896adf009..619c749c7e 100644 --- a/src/common/sdk/nvidia/inc/nvlimits.h +++ b/src/common/sdk/nvidia/inc/nvlimits.h @@ -25,7 +25,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: nvlimits.finn +// Source file: nvlimits.finn // diff --git a/src/common/sdk/nvidia/inc/nvos.h b/src/common/sdk/nvidia/inc/nvos.h index 8bb00416cf..beafa59c81 100644 --- a/src/common/sdk/nvidia/inc/nvos.h +++ b/src/common/sdk/nvidia/inc/nvos.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -142,6 +142,7 @@ extern "C" { #define NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION NV_ERR_PRIV_SEC_VIOLATION #define NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE NV_ERR_GPU_IN_DEBUG_MODE +#define NVOS_STATUS_ERROR_ALREADY_SIGNALLED NV_ERR_ALREADY_SIGNALLED /* Note: @@ -243,6 +244,19 @@ typedef struct #define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24 #define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001) +// +// Allow client allocations to go to protected/unprotected video/system memory. +// When Ampere Protected Model aka APM or Confidential Compute is enabled and +// DEFAULT flag is set by client, allocations go to protected memory. When +// protected memory is not enabled, allocations go to unprotected memory. +// If APM or CC is not enabled, it is a bug for a client to set the PROTECTED +// flag to YES +// +#define NVOS02_FLAGS_MEMORY_PROTECTION 26:25 +#define NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT (0x00000000) +#define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED (0x00000001) +#define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED (0x00000002) + // // If _NO_MAP is requested, the RM in supported platforms will not map the // allocated system or IO memory into user space. The client can later map @@ -444,6 +458,7 @@ typedef struct NvHandle hObjectNew; NvV32 hClass; NvP64 pAllocParms NV_ALIGN_BYTES(8); + NvU32 paramsSize; NvV32 status; } NVOS21_PARAMETERS; @@ -459,6 +474,7 @@ typedef struct NvV32 hClass; // [in] class num of new object NvP64 pAllocParms NV_ALIGN_BYTES(8); // [IN] class-specific alloc parameters NvP64 pRightsRequested NV_ALIGN_BYTES(8); // [IN] RS_ACCESS_MASK to request rights, or NULL + NvU32 paramsSize; // [IN] Size of alloc params NvU32 flags; // [IN] flags for FINN serialization NvV32 status; // [OUT] status } NVOS64_PARAMETERS; @@ -1280,6 +1296,18 @@ typedef struct #define NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE 0x00000000 #define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001 +// +// Allow client allocations to go to protected/unprotected video/system memory. +// When Ampere Protected Model aka APM or Confidential Compute is enabled and +// DEFAULT flag is set by client, allocations go to protected memory. When +// protected memory is not enabled, allocations go to unprotected memory. +// If APM or CC is not enabled, it is a bug for a client to set the PROTECTED +// flag to YES +// +#define NVOS32_ATTR2_MEMORY_PROTECTION 26:25 +#define NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT 0x00000000 +#define NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED 0x00000001 +#define NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED 0x00000002 // // Force the allocation to go to guest subheap. // This flag is used by vmiop plugin to allocate from GPA diff --git a/src/common/sdk/nvidia/inc/nvstatuscodes.h b/src/common/sdk/nvidia/inc/nvstatuscodes.h index 517a8cef89..3b11ee9eeb 100644 --- a/src/common/sdk/nvidia/inc/nvstatuscodes.h +++ b/src/common/sdk/nvidia/inc/nvstatuscodes.h @@ -149,6 +149,7 @@ NV_STATUS_CODE(NV_ERR_NVLINK_TRAINING_ERROR, 0x00000077, "Nvlink Train NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error") NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") +NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value") // Warnings: NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") diff --git a/src/common/sdk/nvidia/inc/nvtypes.h b/src/common/sdk/nvidia/inc/nvtypes.h index 53a60f916b..5d3e853e3f 100644 --- a/src/common/sdk/nvidia/inc/nvtypes.h +++ b/src/common/sdk/nvidia/inc/nvtypes.h @@ -507,6 +507,12 @@ typedef struct // place to re-locate these from nvos.h which cannot be included by a number // of builds that need them +#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) + #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) +#else + #define NV_ATTRIBUTE_UNUSED +#endif + #if defined(__GNUC__) #if (__GNUC__ > 3) || \ ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1) && (__GNUC_PATCHLEVEL__ >= 1)) @@ -600,12 +606,6 @@ typedef struct #define NV_FORCERESULTCHECK #endif - #if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER) - #define NV_ATTRIBUTE_UNUSED __attribute__((__unused__)) - #else - #define NV_ATTRIBUTE_UNUSED - #endif - /* * Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at * parameter number 'f' and variadic arguments start at parameter number 'a'. diff --git a/src/common/sdk/nvidia/inc/rs_access.h b/src/common/sdk/nvidia/inc/rs_access.h index 7c71a78020..53ac2d908e 100644 --- a/src/common/sdk/nvidia/inc/rs_access.h +++ b/src/common/sdk/nvidia/inc/rs_access.h @@ -26,7 +26,7 @@ // // This file was generated with FINN, an NVIDIA coding tool. -// Source file: rs_access.finn +// Source file: rs_access.finn // diff --git a/src/common/shared/inc/nvdevid.h b/src/common/shared/inc/nvdevid.h index cce13d03b1..08a32c3f5c 100644 --- a/src/common/shared/inc/nvdevid.h +++ b/src/common/shared/inc/nvdevid.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 200-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 200-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -145,6 +145,7 @@ #define PCI_VENDOR_ID_CADENCE 0x17CD #define PCI_VENDOR_ID_ARM 0x13B5 #define PCI_VENDOR_ID_HYGON 0x1D94 +#define PCI_VENDOR_ID_ALIBABA 0x1DED #define NV_PCI_DEVID_DEVICE 31:16 /* RW--F */ #define NV_PCI_SUBID_DEVICE 31:16 /* RW--F */ @@ -445,6 +446,9 @@ #define FOXCONN_EINSTEIN_64_DEVID 0xA1C1 #define FOXCONN_EINSTEIN_64_SSDEVID 0x7270 +// Lenovo Tomcat Workstation +#define LENOVO_TOMCAT_DEVID 0x1B81 +#define LENOVO_TOMCAT_SSDEVID 0x104e // NVIDIA C51 #define NVIDIA_C51_DEVICE_ID_MIN 0x2F0 @@ -523,10 +527,6 @@ // /////////////////////////////////////////////////////////////////////////////////////////// -// -// When adding a variable to the following enum, please -// add it also to the following chipset_names[]. -// enum { CS_UNKNOWN = 0x0000, CS_UNKNOWN_PCIE = 0x1000 @@ -605,6 +605,7 @@ enum { , CS_NVIDIA_T194 , CS_NVIDIA_T234 , CS_NVIDIA_T23x +, CS_NVIDIA_TH500 , CS_MARVELL_THUNDERX2 , CS_REDHAT_QEMU , CS_AMPERE_EMAG @@ -620,6 +621,8 @@ enum { , CS_HYGON_C86 , CS_PHYTIUM_S2500 , CS_MELLANOX_BLUEFIELD2 +, CS_MELLANOX_BLUEFIELD3 +, CS_ALIBABA_YITIAN , CS_INTEL_1B81 , CS_INTEL_18DC , CS_INTEL_7A04 diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-init.c b/src/common/unix/nvidia-3d/src/nvidia-3d-init.c index 2ea47dee80..dd53f40c86 100644 --- a/src/common/unix/nvidia-3d/src/nvidia-3d-init.c +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-init.c @@ -285,10 +285,13 @@ static NvBool GetSpaVersion( { NV2080_CTRL_GR_INFO_SM_VERSION_8_6, { 8,6 } }, { NV2080_CTRL_GR_INFO_SM_VERSION_8_7, { 8,6 } }, { NV2080_CTRL_GR_INFO_SM_VERSION_8_8, { 8,6 } }, + /* Ada */ { NV2080_CTRL_GR_INFO_SM_VERSION_8_9, { 8,9 } }, + /* Hopper */ { NV2080_CTRL_GR_INFO_SM_VERSION_9_0, { 9,0 } }, + }; const NvU32 smVersion = GetSmVersion(pPushDevice); diff --git a/src/common/unix/nvidia-push/interface/nvidia-push-init.h b/src/common/unix/nvidia-push/interface/nvidia-push-init.h index 7dd0620255..d0988f68dd 100644 --- a/src/common/unix/nvidia-push/interface/nvidia-push-init.h +++ b/src/common/unix/nvidia-push/interface/nvidia-push-init.h @@ -131,6 +131,7 @@ typedef struct _NvPushAllocDeviceParams { NvU32 numClasses; const NvU32 *supportedClasses; + NvPushConfidentialComputeMode confidentialComputeMode; } NvPushAllocDeviceParams; NvBool nvPushAllocDevice( @@ -173,6 +174,13 @@ typedef struct _NvPushAllocChannelParams { */ NvBool ignoreChannelErrors; + /* + * This flag specifies if channel is intended to be used for + * encryption/decryption of data between SYSMEM <-> VIDMEM. Only CE + * & SEC2 Channels are capable of handling encrypted content. + */ + NvBool secureChannel; + /* * DIFR stands for Display Idle Frame Refresh in which a CE is used to * prefetch framebuffer pixels into the GPU's L2 cache. The prefetch diff --git a/src/common/unix/nvidia-push/interface/nvidia-push-types.h b/src/common/unix/nvidia-push/interface/nvidia-push-types.h index 4772ee11d2..4ac201d70c 100644 --- a/src/common/unix/nvidia-push/interface/nvidia-push-types.h +++ b/src/common/unix/nvidia-push/interface/nvidia-push-types.h @@ -69,6 +69,17 @@ typedef union _NvPushChannelUnion #endif } NvPushChannelUnion; +typedef enum _NvPushConfidentialComputeMode { + /* Confidential computing is not in use. */ + NV_PUSH_CONFIDENTIAL_COMPUTE_MODE_NONE, + + /* + * The confidential compute mode of operation is Hopper Confidential + * Compute (HCC). + */ + NV_PUSH_CONFIDENTIAL_COMPUTE_MODE_HCC, +} NvPushConfidentialComputeMode; + typedef struct _NvPushChannelRec NvPushChannelRec; typedef struct _NvPushChannelRec *NvPushChannelPtr; @@ -121,6 +132,8 @@ typedef struct _NvPushDeviceRec { NvPushHal hal; const struct _NvPushImports *pImports; + /* Provided by the host driver */ + NvPushConfidentialComputeMode confidentialComputeMode; } NvPushDeviceRec, *NvPushDevicePtr; diff --git a/src/common/unix/nvidia-push/src/nvidia-push-init.c b/src/common/unix/nvidia-push/src/nvidia-push-init.c index 3262815d8e..db0b4c9afb 100644 --- a/src/common/unix/nvidia-push/src/nvidia-push-init.c +++ b/src/common/unix/nvidia-push/src/nvidia-push-init.c @@ -412,6 +412,9 @@ static NvBool AllocChannelObject( } params.flags = 0; + if (pParams->secureChannel) { + params.flags |= DRF_DEF(OS04, _FLAGS, _CC_SECURE, _TRUE); + } if (pParams->difrPrefetch) { params.flags |= DRF_DEF(OS04, _FLAGS, @@ -1482,6 +1485,8 @@ NvBool nvPushAllocDevice( pDevice->numClasses = pParams->numClasses; pDevice->supportedClasses = pParams->supportedClasses; + pDevice->confidentialComputeMode = pParams->confidentialComputeMode; + for (sd = 0; sd < pParams->numSubDevices; sd++) { pDevice->subDevice[sd].handle = pParams->subDevice[sd].handle; pDevice->subDevice[sd].deviceHandle = pParams->subDevice[sd].deviceHandle; diff --git a/src/common/unix/nvidia-push/src/nvidia-push.c b/src/common/unix/nvidia-push/src/nvidia-push.c index ae19310057..e039fc46f7 100644 --- a/src/common/unix/nvidia-push/src/nvidia-push.c +++ b/src/common/unix/nvidia-push/src/nvidia-push.c @@ -1014,7 +1014,7 @@ static void KeplerReleaseTimelineSemaphore( // Must be done before submitting the semaphore release to ensure the maximum // known-submitted value is never less than the semaphore's current value. - NvTimeSemFermiSetMaxSubmitted(report, val); + NvTimeSemFermiSetMaxSubmittedVal(&report->timer, val); nvPushMethod(p, 0, NVA16F_SEMAPHOREA, 4); nvPushSetMethodDataU64(p, gpuAddress); // NVA16F_SEMAPHOREB @@ -1106,13 +1106,6 @@ NvBool __nvPushGetHal( pHal->caps.extendedBase = TRUE; // otherwise backwards compatible with the Volta DMA HAL // fall through -#if defined(__GNUC__) && __GNUC__ >= 7 - // GCC apparently doesn't think the comment above is sufficient to - // quiet -Wimplicit-fallthrough, when there are preprocessor - // directives between it and the next case. - // This attribute is only supported on gcc 7 and later. - __attribute__ ((fallthrough)); -#endif case AMPERE_CHANNEL_GPFIFO_A: // backwards compatible with the Volta DMA HAL // fall through diff --git a/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c b/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c index e7fe926bfa..b9b5b545b0 100644 --- a/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c @@ -755,11 +755,10 @@ static void libosDwarfBuildTables(LibosDebugResolver *pThis) DwarfStream debugLines = {pThis->debugLineStart, 0, pThis->debugLineEnd - pThis->debugLineStart}; DwarfStream unit; - NvU32 currentUnit = 1; NvU32 unitSize; // Run through the .debug_line elf section to match units to the arange table. - for (currentUnit = 1;; currentUnit++) + while (NV_TRUE) { if (!DWARF_READ(&debugLines, &unitSize) || unitSize >= 0xfffffff0) { @@ -829,11 +828,10 @@ static void dwarfBuildARangeTable(LibosDebugResolver *pThis) // Pad to natural alignment unit.offset = (unit.offset + 15) & ~15; - NvU32 nUnitTupples; NvU64 combAddress = 0; NvU64 combLength = 0; - for (nUnitTupples = 0;; nUnitTupples++) + while (NV_TRUE) { NvU64 address; NvU64 length; @@ -918,7 +916,7 @@ static void dwarfSetARangeTableLineUnit(LibosDebugResolver *pThis, DwarfStream u } // Walk forwards setting the line unit info for all entries with the same arange unit. - for (; (foundUnit == pThis->arangeTable[i].arangeUnit); i++) + for (; foundUnit == pThis->arangeTable[i].arangeUnit; i++) { pThis->arangeTable[i].lineUnitBuffer = unit.buffer; pThis->arangeTable[i].lineUnitSize = unit.size; diff --git a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c index cf0fb6885c..5f6e18c67e 100644 --- a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c @@ -34,6 +34,10 @@ #else // NVRM +#if defined(NVSYM_STANDALONE) +#include "time.h" +#endif + # include # include # include @@ -66,6 +70,8 @@ int logPrintf(const char *, ...); // Forward declaration. TODO: allow libos code #endif // NVRM +#include + #include "nvtypes.h" #include "liblogdecode.h" @@ -484,7 +490,39 @@ static int libos_printf_a( // Prefix every line with GPUn Ucode-task: filename(lineNumber): snprintf( logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, - "T:%llu GPU%u %s-%s: %s(%u): ", pRec->timeStamp, + "T:%llu ", pRec->timeStamp); + logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); + +#if defined(NVSYM_STANDALONE) + { + struct tm tmStruct; + // Libos timestamp is a PTIMER value, which is UNIX time in ns + time_t timeSec = pRec->timeStamp / 1000000000; +#if NVOS_IS_WINDOWS + // "The implementation of localtime_s in Microsoft CRT is incompatible with the + // C standard since it has reversed parameter order and returns errno_t." + errno_t err = localtime_s(&tmStruct, &timeSec); +#else + int err = (localtime_r(&timeSec, &tmStruct) == NULL); +#endif + if (err == 0) + { + snprintf(logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, + "%04d-%02d-%02d %d:%02d:%02d ", + tmStruct.tm_year + 1900, // years since 1900 + tmStruct.tm_mon + 1, // months since January - [0,11] + tmStruct.tm_mday, // day of the month - [1,31] + tmStruct.tm_hour, // hours since midnight - [0,23] + tmStruct.tm_min, // minutes after the hour - [0,59] + tmStruct.tm_sec); // seconds after the minute - [0,59] + logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); + } + } +#endif + + snprintf( + logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, + "GPU%u %s-%s: %s(%u): ", pRec->log->gpuInstance, logDecode->sourceName, pRec->log->taskPrefix, filename, pRec->meta->lineNumber); logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); @@ -1068,10 +1106,14 @@ static void libosExtractLogs_decode(LIBOS_LOG_DECODE *logDecode) // Copy records with highest timestamp. recSize = pLog->record.meta->argumentCount + LIBOS_LOG_DECODE_RECORD_BASE; + // // Skip duplicate records. The same record can be in both wrap and nowrap buffers. + // memcmp LIBOS_LOG_DECODE_RECORD + args starting at LIBOS_LOG_DECODE_RECORD::meta. + // + NvU64 compareSz = recSize - offsetof(LIBOS_LOG_DECODE_RECORD, meta) / sizeof(NvU64); if ((pPrevRec == NULL) || (pPrevRec->log->gpuInstance != pLog->gpuInstance) || - (portMemCmp(&pPrevRec->meta, &pLog->record.meta, (recSize - 1) * sizeof(NvU64)) != 0)) + (portMemCmp(&pPrevRec->meta, &pLog->record.meta, sizeof(NvU64) * compareSz) != 0)) { // Record is not identical to previous record. if (dst < recSize) diff --git a/src/nvidia-modeset/Makefile b/src/nvidia-modeset/Makefile index 9ef3c62e93..6246bb59d1 100644 --- a/src/nvidia-modeset/Makefile +++ b/src/nvidia-modeset/Makefile @@ -105,6 +105,7 @@ CFLAGS += -fno-strict-aliasing CFLAGS += -ffunction-sections CFLAGS += -fdata-sections CFLAGS += -ffreestanding +CFLAGS += -fno-stack-protector CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -Wformat-overflow=2) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -Wformat-truncation=1) diff --git a/src/nvidia-modeset/include/dp/nvdp-connector.h b/src/nvidia-modeset/include/dp/nvdp-connector.h index 70aba5a76a..d44cf86a32 100644 --- a/src/nvidia-modeset/include/dp/nvdp-connector.h +++ b/src/nvidia-modeset/include/dp/nvdp-connector.h @@ -48,7 +48,8 @@ NVDPLibModesetStatePtr nvDPLibCreateModesetState( const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, - NVHwModeTimingsEvo *pTimings); + const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo); void nvDPLibFreeModesetState(NVDPLibModesetStatePtr pDpLibModesetState); @@ -62,7 +63,9 @@ NvBool nvDPLibValidateTimings( const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, - NVHwModeTimingsEvo *pTimings); + const NVHwModeTimingsEvo *pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo); NvBool nvDPEndValidation(NVDispEvoPtr pDispEvo); @@ -71,12 +74,15 @@ NvBool nvDPValidateModeForDpyEvo( const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, - NVHwModeTimingsEvo *pTimings); + const NVHwModeTimingsEvo *pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo); void nvDPPreSetMode(NVDPLibConnectorPtr pDpLibConnector, const NVEvoModesetUpdateState *pModesetUpdateState); -void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector); +void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector, + const NVEvoModesetUpdateState *pModesetUpdateState); void nvDPPause(NVDPLibConnectorPtr pNVDpLibConnector); diff --git a/src/nvidia-modeset/include/dp/nvdp-device.h b/src/nvidia-modeset/include/dp/nvdp-device.h index 93d8a1c309..979aaa20c9 100644 --- a/src/nvidia-modeset/include/dp/nvdp-device.h +++ b/src/nvidia-modeset/include/dp/nvdp-device.h @@ -35,6 +35,7 @@ unsigned int nvDPGetEDIDSize(const NVDpyEvoRec *pDpyEvo); NvBool nvDPGetEDID(const NVDpyEvoRec *pDpyEvo, void *buffer, unsigned int size); void nvDPGetDpyGUID(NVDpyEvoPtr pDpyEvo); void nvDPDpyFree(NVDpyEvoPtr pDpyEvo); +NvBool nvDPDpyIsDscPossible(const NVDpyEvoRec *pDpyEvo); #ifdef __cplusplus }; diff --git a/src/nvidia-modeset/include/nvkms-dpy.h b/src/nvidia-modeset/include/nvkms-dpy.h index 715894f349..4885fb2c1b 100644 --- a/src/nvidia-modeset/include/nvkms-dpy.h +++ b/src/nvidia-modeset/include/nvkms-dpy.h @@ -83,6 +83,8 @@ nvGetDefaultDpyAttributeDigitalSignalValue(const NVConnectorEvoRec *pConnectorEv NVColorFormatInfoRec nvGetColorFormatInfo(const NVDpyEvoRec *pDpyEvo); +NvU32 nvDpyGetPossibleApiHeadsMask(const NVDpyEvoRec *pDpyEvo); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-evo-states.h b/src/nvidia-modeset/include/nvkms-evo-states.h index dcde326d73..8d06c88180 100644 --- a/src/nvidia-modeset/include/nvkms-evo-states.h +++ b/src/nvidia-modeset/include/nvkms-evo-states.h @@ -50,6 +50,8 @@ typedef enum NVEvoLockAction { NV_EVO_REM_FRAME_LOCK_CLIENT, NV_EVO_ENABLE_VRR, NV_EVO_DISABLE_VRR, + NV_EVO_ENABLE_MERGE_MODE, + NV_EVO_DISABLE_MERGE_MODE, NV_EVO_ADD_FRAME_LOCK_REF, NV_EVO_REM_FRAME_LOCK_REF, NV_EVO_ADD_SLI_SECONDARY, @@ -72,6 +74,8 @@ NvBool nvEvoUnRefFrameLockSli(NVDispEvoPtr pDispEvo, /* nvkms-hw-states.c */ +NvBool nvEvoLockHWStateNoChange(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); +NvBool nvEvoLockHWStateMergeMode(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateNoLock(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateLockHeads(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateFrameLockClient(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); diff --git a/src/nvidia-modeset/include/nvkms-evo.h b/src/nvidia-modeset/include/nvkms-evo.h index 5d976f404c..6ef6a79a1c 100644 --- a/src/nvidia-modeset/include/nvkms-evo.h +++ b/src/nvidia-modeset/include/nvkms-evo.h @@ -39,6 +39,7 @@ void nvEvoDetachConnector(NVConnectorEvoRec *pConnectorEvo, const NvU32 head, NVEvoModesetUpdateState *pModesetUpdateState); void nvEvoAttachConnector(NVConnectorEvoRec *pConnectorEvo, const NvU32 head, + const NvU32 isPrimaryHead, NVDPLibModesetStatePtr pDpLibModesetState, NVEvoModesetUpdateState *pModesetUpdateState); void nvEvoUpdateAndKickOff(const NVDispEvoRec *pDispEvo, NvBool sync, @@ -84,6 +85,9 @@ void nvAssignDefaultUsageBounds(const NVDispEvoRec *pDispEvo, void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, const struct NvKmsUsageBounds *b, struct NvKmsUsageBounds *ret); +void nvIntersectUsageBounds(const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b, + struct NvKmsUsageBounds *ret); NvBool UsageBoundsEqual(const struct NvKmsUsageBounds *a, const struct NvKmsUsageBounds *b); NvU64 nvEvoGetFormatsWithEqualOrLowerUsageBound( @@ -125,6 +129,7 @@ void nvSetDitheringEvo( NvBool nvEnableFrameLockEvo(NVDispEvoPtr pDispEvo); NvBool nvDisableFrameLockEvo(NVDispEvoPtr pDispEvo); NvBool nvQueryRasterLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *val); +void nvInvalidateTopologiesEvo(void); NvBool nvSetFlipLockEvo(NVDpyEvoPtr pDpyEvo, NvS64 value); NvBool nvGetFlipLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue); NvBool nvAllowFlipLockEvo(NVDispEvoPtr pDispEvo, NvS64 value); @@ -159,12 +164,15 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo, NvBool nvConstructHwModeTimingsImpCheckEvo( const NVConnectorEvoRec *pConnectorEvo, - NVHwModeTimingsEvoPtr pTimings, + const NVHwModeTimingsEvo *pTimings, + const NvBool enableDsc, + const NvBool b2Heads1Or, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pParams, - NVEvoInfoStringPtr pInfoString, - const int head); + NVHwModeTimingsEvo timings[NVKMS_MAX_HEADS_PER_DISP], + NvU32 *pNumHeads, + NVEvoInfoStringPtr pInfoString); NvBool nvDowngradeColorSpaceAndBpc( const NVColorFormatInfoRec *pSupportedColorFormats, @@ -174,6 +182,8 @@ NvBool nvDowngradeColorSpaceAndBpc( NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo, const struct NvKmsModeValidationParams *pParams); NvBool nvEvoUpdateHwModeTimingsViewPort( @@ -190,6 +200,8 @@ typedef struct _NVValidateImpOneDispHeadParamsRec NvU32 activeRmId; enum nvKmsPixelDepth pixelDepth; NVHwModeTimingsEvoPtr pTimings; + NvBool enableDsc; + NvBool b2Heads1Or; } NVValidateImpOneDispHeadParamsRec; NvBool nvValidateImpOneDisp( @@ -238,7 +250,8 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( const enum NvKmsDpyAttributeColorRangeValue colorRange, NVEvoUpdateState *pUpdateState); -NvBool nvAssignSOREvo(NVConnectorEvoPtr pConnectorEvo, NvU32 sorExcludeMask); +NvBool nvAssignSOREvo(const NVDispEvoRec *pDispEvo, const NvU32 displayId, + const NvBool b2Heads1Or, const NvU32 sorExcludeMask); void nvSetSwapBarrierNotifyEvo(NVDispEvoPtr pDispEvo, NvBool enable, NvBool isPre); @@ -322,6 +335,53 @@ NvBool nvGetDefaultColorSpace( enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, enum NvKmsDpyAttributeColorBpcValue *pColorBpc); +static inline void nvEvoSetFlipOccurredEvent(const NVDispEvoRec *pDispEvo, + const NvU32 head, + const NvU32 layer, + struct nvkms_ref_ptr *ref_ptr, + NVEvoModesetUpdateState + *pModesetUpdate) +{ + nvAssert((head < pDispEvo->pDevEvo->numHeads) && + (layer < pDispEvo->pDevEvo->head[head].numLayers)); + pModesetUpdate->flipOccurredEvent[head].layer[layer].ref_ptr = ref_ptr; + pModesetUpdate->flipOccurredEvent[head].layer[layer].changed = TRUE; +} + +void nvEvoPreModesetRegisterFlipOccurredEvent(NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoModesetUpdateState + *pModesetUpdate); + +void nvEvoPostModesetUnregisterFlipOccurredEvent(NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoModesetUpdateState + *pModesetUpdate); + +void nvEvoLockStateSetMergeMode(NVDispEvoPtr pDispEvo); + +void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState); +void nvEvoEnableMergeModePostModeset(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState); +void nvEvoDisableMergeMode(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState); + +void nvEvoDisableHwYUV420Packer(const NVDispEvoRec *pDispEvo, + const NvU32 head, + NVEvoUpdateState *pUpdateState); + +NvBool nvEvoGetSingleTileHwModeTimings(const NVHwModeTimingsEvo *pSrc, + const NvU32 numTiles, + NVHwModeTimingsEvo *pDst); + +NvBool nvEvoUse2Heads1OR(const NVDpyEvoRec *pDpyEvo, + const NVHwModeTimingsEvo *pTimings, + const struct NvKmsModeValidationParams *pParams); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-evo1.h b/src/nvidia-modeset/include/nvkms-evo1.h index eb9e225eb0..424b00aebf 100644 --- a/src/nvidia-modeset/include/nvkms-evo1.h +++ b/src/nvidia-modeset/include/nvkms-evo1.h @@ -38,7 +38,7 @@ void nvEvo1PrePostIMP(NVDispEvoPtr pDispEvo, NvBool isPre); void nvEvo1SetDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo, const enum nvKmsPixelDepth pixelDepth); NVEvoChannel* nvEvo1AllocateCoreChannel(NVDevEvoRec *pDevEvo); diff --git a/src/nvidia-modeset/include/nvkms-flip-workarea.h b/src/nvidia-modeset/include/nvkms-flip-workarea.h index 0319b28525..55794d34c0 100644 --- a/src/nvidia-modeset/include/nvkms-flip-workarea.h +++ b/src/nvidia-modeset/include/nvkms-flip-workarea.h @@ -65,6 +65,8 @@ struct NvKmsFlipWorkArea { NVProposedFlipStateOneApiHead proposedFlipState; } apiHead[NVKMS_MAX_HEADS_PER_DISP]; } disp[NVKMS_MAX_SUBDEVICES]; + + NVEvoUpdateState updateState; }; #endif /* __NVKMS_FLIP_WORKAREA_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-hdmi.h b/src/nvidia-modeset/include/nvkms-hdmi.h index 33d2499e9f..eaebf5dc3b 100644 --- a/src/nvidia-modeset/include/nvkms-hdmi.h +++ b/src/nvidia-modeset/include/nvkms-hdmi.h @@ -62,8 +62,11 @@ NvBool nvHdmiFrlAssessLink(NVDpyEvoPtr pDpyEvo); NvBool nvHdmiDpySupportsFrl(const NVDpyEvoRec *pDpyEvo); NvBool nvHdmiFrlQueryConfig(const NVDpyEvoRec *pDpyEvo, const NvModeTimings *pModeTimings, - NVHwModeTimingsEvo *pTimings, - const struct NvKmsModeValidationParams *pParams); + const NVHwModeTimingsEvo *pHwTimings, + const NvBool b2Heads1Or, + const struct NvKmsModeValidationParams *pValidationParams, + HDMI_FRL_CONFIG *pConfig, + NVDscInfoEvoRec *pDscInfo); void nvHdmiFrlClearConfig(NVDispEvoRec *pDispEvo, NvU32 activeRmId); void nvHdmiFrlSetConfig(NVDispEvoRec *pDispEvo, NvU32 head); @@ -71,6 +74,16 @@ void nvHdmiDpConstructHeadAudioState(const NvU32 displayId, const NVDpyEvoRec *pDpyEvo, NVDispHeadAudioStateEvoRec *pAudioState); +NvBool nvHdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, + const NVHwModeTimingsEvo *pHwTimings); + +static inline NvBool nvHdmiDpySupportsDsc(const NVDpyEvoRec *pDpyEvo) +{ + return nvDpyIsHdmiEvo(pDpyEvo) && + pDpyEvo->parsedEdid.valid && + pDpyEvo->parsedEdid.info.hdmiForumInfo.dsc_1p2; +} + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-headsurface-priv.h b/src/nvidia-modeset/include/nvkms-headsurface-priv.h index d799466ccf..854c1d5aa0 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface-priv.h +++ b/src/nvidia-modeset/include/nvkms-headsurface-priv.h @@ -481,7 +481,6 @@ static inline void HsIncrementNextIndex( } static inline void HsChangeSurfaceFlipRefCount( - NVDevEvoPtr pDevEvo, NVSurfaceEvoPtr pSurfaceEvo, NvBool increase) { @@ -489,7 +488,7 @@ static inline void HsChangeSurfaceFlipRefCount( if (increase) { nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); } else { - nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); } } } diff --git a/src/nvidia-modeset/include/nvkms-hw-flip.h b/src/nvidia-modeset/include/nvkms-hw-flip.h index 02b7be937f..be3492d581 100644 --- a/src/nvidia-modeset/include/nvkms-hw-flip.h +++ b/src/nvidia-modeset/include/nvkms-hw-flip.h @@ -47,6 +47,7 @@ NvBool nvUpdateFlipEvoHwState( const NvU32 head, const struct NvKmsFlipCommonParams *pParams, const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, NVFlipEvoHwState *pFlipState, NvBool allowVrr); diff --git a/src/nvidia-modeset/include/nvkms-modeset-types.h b/src/nvidia-modeset/include/nvkms-modeset-types.h index 1c2710e417..197f372b32 100644 --- a/src/nvidia-modeset/include/nvkms-modeset-types.h +++ b/src/nvidia-modeset/include/nvkms-modeset-types.h @@ -29,26 +29,36 @@ #include "nvkms-types.h" typedef struct { + NvU32 hwHeadsMask; + struct NvKmsModeValidationParams modeValidationParams; NVHwModeTimingsEvo timings; - NVDpyIdList dpyIdList; - NVConnectorEvoRec *pConnectorEvo; + struct NvKmsPoint viewPortPointIn; NvU32 activeRmId; + NVDpyIdList dpyIdList; + NVAttributesSetEvoRec attributes; struct NvKmsSetLutCommonParams lut; + NVDispStereoParamsEvoRec stereo; + NVDscInfoEvoRec dscInfo; + NVDispHeadInfoFrameStateEvoRec infoFrame; NvU8 allowFlipLockGroup; - NVAttributesSetEvoRec attributes; - struct NvKmsModeValidationParams modeValidationParams; - NvBool changed : 1; - NvBool hs10bpcHint : 1; - NvBool colorSpaceSpecified : 1; - NvBool colorRangeSpecified : 1; + enum NvKmsOutputTf tf; + NvBool colorSpaceSpecified : 1; + NvBool colorRangeSpecified : 1; + NvBool hs10bpcHint : 1; + NvBool changed : 1; +} NVProposedModeSetStateOneApiHead; + +typedef struct { + NvU8 tilePosition; + NVHwModeTimingsEvo timings; + NVConnectorEvoRec *pConnectorEvo; + HDMI_FRL_CONFIG hdmiFrlConfig; NVDPLibModesetStatePtr pDpLibModesetState; NVDispHeadAudioStateEvoRec audio; - NVDispHeadInfoFrameStateEvoRec infoFrame; - enum NvKmsOutputTf tf; - NVDispStereoParamsEvoRec stereo; } NVProposedModeSetHwStateOneHead; typedef struct { + NVProposedModeSetStateOneApiHead apiHead[NVKMS_MAX_HEADS_PER_DISP]; NVProposedModeSetHwStateOneHead head[NVKMS_MAX_HEADS_PER_DISP]; } NVProposedModeSetHwStateOneDisp; @@ -64,4 +74,13 @@ typedef struct { NvBool allowHeadSurfaceInNvKms : 1; } NVProposedModeSetHwState; +static inline void nvAssignHwHeadsMaskProposedApiHead( + NVProposedModeSetStateOneApiHead *pProposedApiHead, + const NvU32 hwHeadsMask) +{ + pProposedApiHead->hwHeadsMask = hwHeadsMask; + pProposedApiHead->attributes.numberOfHardwareHeadsUsed = + nvPopCount32(hwHeadsMask); +} + #endif /* __NVKMS_MODESET_TYPES_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-modeset-workarea.h b/src/nvidia-modeset/include/nvkms-modeset-workarea.h index da492dd33a..832e186718 100644 --- a/src/nvidia-modeset/include/nvkms-modeset-workarea.h +++ b/src/nvidia-modeset/include/nvkms-modeset-workarea.h @@ -31,14 +31,15 @@ typedef struct { struct { NVFlipEvoHwState newState; NVFlipEvoHwState oldState; - NvU32 oldActiveRmId; } head[NVKMS_MAX_HEADS_PER_DISP]; + struct { + NvU32 oldActiveRmId; + } apiHead[NVKMS_MAX_HEADS_PER_DISP]; + NVDpyIdList changedDpyIdList; - NVDpyIdList sorAssignedConnectorsList; NvU32 assignedSorMask; - } sd[NVKMS_MAX_SUBDEVICES]; NVHsConfig hsConfig; NVEvoUpdateState earlyUpdateState; diff --git a/src/nvidia-modeset/include/nvkms-prealloc-types.h b/src/nvidia-modeset/include/nvkms-prealloc-types.h index 0756a440ec..61a99d4f2c 100644 --- a/src/nvidia-modeset/include/nvkms-prealloc-types.h +++ b/src/nvidia-modeset/include/nvkms-prealloc-types.h @@ -37,6 +37,11 @@ enum NVPreallocType { PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS, PREALLOC_TYPE_VALIDATE_PROPOSED_MODESET_HW_STATE, PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS, + PREALLOC_TYPE_VALIDATE_MODE_HDMI_FRL_CONFIG, + PREALLOC_TYPE_VALIDATE_MODE_DSC_INFO, + PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS, + PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS, + PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS, PREALLOC_TYPE_MAX }; diff --git a/src/nvidia-modeset/include/nvkms-private.h b/src/nvidia-modeset/include/nvkms-private.h index 0728fbb926..c337819e0a 100644 --- a/src/nvidia-modeset/include/nvkms-private.h +++ b/src/nvidia-modeset/include/nvkms-private.h @@ -68,6 +68,8 @@ NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDev( struct NvKmsPerOpenDev *pOpenDev); const NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDevConst( const struct NvKmsPerOpenDev *pOpenDev); +NVDevEvoPtr nvGetDevEvoFromOpenDev( + const struct NvKmsPerOpenDev *pOpenDev); void nvKmsServiceNonStallInterrupt(void *dataPtr, NvU32 dataU32); diff --git a/src/nvidia-modeset/include/nvkms-surface.h b/src/nvidia-modeset/include/nvkms-surface.h index 181986e911..0a05242cd2 100644 --- a/src/nvidia-modeset/include/nvkms-surface.h +++ b/src/nvidia-modeset/include/nvkms-surface.h @@ -47,8 +47,7 @@ void nvEvoIncrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo); void nvEvoDecrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo); void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo); -void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo, - NVSurfaceEvoPtr pSurfaceEvo); +void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo); NvBool nvEvoSurfaceRefCntsTooLarge(const NVSurfaceEvoRec *pSurfaceEvo); diff --git a/src/nvidia-modeset/include/nvkms-types.h b/src/nvidia-modeset/include/nvkms-types.h index ab29b4e7f3..d6a39917a9 100644 --- a/src/nvidia-modeset/include/nvkms-types.h +++ b/src/nvidia-modeset/include/nvkms-types.h @@ -150,6 +150,7 @@ typedef struct _NVSurfaceEvoRec NVSurfaceEvoRec, *NVSurfaceEvoPtr; typedef struct _NVDeferredRequestFifoRec *NVDeferredRequestFifoPtr; typedef struct _NVSwapGroupRec *NVSwapGroupPtr; typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; +typedef struct _NVEvoRasterLockTopology *RasterLockTopologyPtr; /* * _NVHs*EvoRec are defined in nvkms-headsurface-priv.h; they are intentionally @@ -183,6 +184,10 @@ typedef struct _NVEvoDma /* Whether this is sysmem, or vidmem accessed through a BAR1 mapping. */ NvBool isBar1Mapping; + struct { + NvU8 vrrNotifierNextSlot; + } vrrNotifierHead[NV_MAX_HEADS]; + void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; } NVEvoDma, *NVEvoDmaPtr; @@ -262,6 +267,7 @@ typedef struct { typedef struct { NvBool usable; + NvU32 maxPClkKHz; NvBool supportsHDMIYUV420HW; NVEvoScalerCaps scalerCaps; } NVEvoHeadCaps; @@ -390,6 +396,12 @@ struct _NVEvoModesetUpdateState { const NVDPLibModesetStateRec *pDpLibModesetState[NVKMS_MAX_HEADS_PER_DISP]; NvBool windowMappingChanged; + struct { + struct _NVEvoModesetUpdateStateOneLayer { + struct nvkms_ref_ptr *ref_ptr; + NvBool changed; + } layer[NVKMS_MAX_LAYERS_PER_HEAD]; + } flipOccurredEvent[NVKMS_MAX_HEADS_PER_DISP]; }; typedef struct { @@ -463,6 +475,7 @@ typedef struct _NVEvoChannel { NVDmaBufferEvoRec pb; NVOS10_EVENT_KERNEL_CALLBACK_EX completionNotifierEventCallback; + const struct nvkms_ref_ptr *completionNotifierEventRefPtr; NvU32 completionNotifierEventHandle; /* @@ -519,6 +532,13 @@ typedef struct _NVEvoHeadControl { NVEvoLockPin flipLockPin; NVEvoLockPin stereoPin; + NvBool mergeMode; + NvBool setLockOffsetX; + + NvU32 stallLockPin; + NvBool useStallLockPin; + NvBool crashLockUnstallMode; + /* * Whether or not this GPU is stereo locked. True if all heads are either * frame or raster locked, and all heads are driving non-interlaced modes. @@ -1273,6 +1293,52 @@ enum nvKmsTimingsProtocol { NVKMS_PROTOCOL_PIOR_EXT_TMDS_ENC, }; +enum NVDscInfoEvoType { + NV_DSC_INFO_EVO_TYPE_DISABLED = 0, + NV_DSC_INFO_EVO_TYPE_HDMI = 1, + NV_DSC_INFO_EVO_TYPE_DP = 3, +}; + +enum NVDscEvoMode { + NV_DSC_EVO_MODE_SINGLE = 0, + NV_DSC_EVO_MODE_DUAL = 1, +}; + +typedef struct _NVDscInfoEvoRec { + union { + /* DisplayPort Display Stream Compression */ + struct { + /* + * The DSC target bits per pixel (bpp) rate value multiplied by 16 that + * is being used by the DSC encoder. + * + * It maps respectively to {pps4[1:0], pps5[7:0]}. + */ + NvU32 bitsPerPixelX16; + + /* + * The DSC picture parameter set (PPS), which the DSC encoder must + * communicate to the decoder. + */ + NvU32 pps[DSC_MAX_PPS_SIZE_DWORD]; + enum NVDscEvoMode dscMode; + } dp; + + struct { + NvU32 bitsPerPixelX16; + NvU32 pps[HDMI_DSC_MAX_PPS_SIZE_DWORD]; + NvU32 dscHActiveBytes; + NvU32 dscHActiveTriBytes; + NvU32 dscHBlankTriBytes; + NvU32 dscTBlankToTTotalRatioX1k; + NvU32 hblankMin; + enum NVDscEvoMode dscMode; + } hdmi; + }; + + enum NVDscInfoEvoType type; +} NVDscInfoEvoRec; + /* * This structure defines all of the values necessary to program mode timings * on EVO hardware. @@ -1321,29 +1387,10 @@ typedef struct _NVHwModeTimingsEvo { struct { /* The vrr type for which this mode is adjusted. */ enum NvKmsDpyVRRType type; + NvU32 timeoutMicroseconds; + NvBool needsSwFramePacing; } vrr; - /* DisplayPort Display Stream Compression */ - struct { - NvBool enable; - - /* - * The DSC target bits per pixel (bpp) rate value multiplied by 16 that - * is being used by the DSC encoder. - * - * It maps respectively to {pps4[1:0], pps5[7:0]}. - */ - NvU32 bitsPerPixelX16; - - /* - * The DSC picture parameter set (PPS), which the DSC encoder must - * communicate to the decoder. - */ - NvU32 pps[DSC_MAX_PPS_SIZE_DWORD]; - } dpDsc; - - HDMI_FRL_CONFIG hdmiFrlConfig; - NVHwModeViewPortEvo viewPort; } NVHwModeTimingsEvo; @@ -1486,14 +1533,6 @@ typedef struct _NVConnectorEvoRec { NvU32 legacyTypeIndex; NvU32 physicalIndex; NvU32 physicalLocation; - NvU32 validHeadMask; - - /* - * [2Heads1OR] XXX Implement the dynamic api-head to hardware-heads mapping - * and remove NVConnectorEvoRec::validApiHeadMask and - * NvKmsQueryConnectorStaticDataReply::headMask. - */ - NvU32 validApiHeadMask; NvU32 dfpInfo; /* DFP info query through NV0073_CTRL_CMD_DFP_GET_INFO */ @@ -1507,8 +1546,10 @@ typedef struct _NVConnectorEvoRec { NvU32 ditherAlgo; /* Hardware heads attached to assigned OR */ NvU32 ownerHeadMask[NV_EVO_MAX_ORS]; - /* ORs mask assigned to this connector */ - NvU32 mask; + /* The mask of secondary ORs assigned to this connector */ + NvU32 secondaryMask; + /* The primary OR assigned to this connector */ + NvU32 primary; } or; NvEldCase audioDevEldCase[NV_MAX_AUDIO_DEVICE_ENTRIES]; @@ -1516,13 +1557,21 @@ typedef struct _NVConnectorEvoRec { NvBool isHdmiEnabled; } NVConnectorEvoRec; +static inline NvU32 nvConnectorGetORMaskEvo(const NVConnectorEvoRec *pConnectorEvo) +{ + if (pConnectorEvo->or.primary != NV_INVALID_OR) { + return NVBIT(pConnectorEvo->or.primary) | pConnectorEvo->or.secondaryMask; + } + return 0x0; +} + static inline NvU32 nvConnectorGetAttachedHeadMaskEvo( const NVConnectorEvoRec *pConnectorEvo) { NvU32 headMask = 0x0; NvU32 orIndex; - FOR_EACH_INDEX_IN_MASK(32, orIndex, pConnectorEvo->or.mask) { + FOR_EACH_INDEX_IN_MASK(32, orIndex, nvConnectorGetORMaskEvo(pConnectorEvo)) { headMask |= pConnectorEvo->or.ownerHeadMask[orIndex]; } FOR_EACH_INDEX_IN_MASK_END; @@ -1532,27 +1581,8 @@ static inline NvU32 nvConnectorGetAttachedHeadMaskEvo( static inline NvBool nvIsConnectorActiveEvo(const NVConnectorEvoRec *pConnectorEvo) { - NvU32 orIndex; - - FOR_EACH_INDEX_IN_MASK(32, orIndex, pConnectorEvo->or.mask) { - if (pConnectorEvo->or.ownerHeadMask[orIndex] != 0x0) { - return TRUE; - } - } FOR_EACH_INDEX_IN_MASK_END; - - return FALSE; -} - -/* - * In case of 2-Heads-1-OR: NV0073_CTRL_CMD_DFP_ASSIGN_SOR assigns 2 SORs, - * lowest SOR index is for primary head. - */ -static inline NvU32 nvEvoConnectorGetPrimaryOr( - const NVConnectorEvoRec *pConnectorEvo) -{ - return (pConnectorEvo->or.mask == 0x0 ? - NV_INVALID_OR : - BIT_IDX_32(LOWESTBIT(pConnectorEvo->or.mask))); + return (pConnectorEvo->or.primary != NV_INVALID_OR) && + (pConnectorEvo->or.ownerHeadMask[pConnectorEvo->or.primary] != 0x0); } typedef struct _NVDpyAttributeCurrentDitheringConfigRec { @@ -1602,6 +1632,8 @@ typedef struct __NVAttributesSetEvoRec { } imageSharpening; enum NvKmsDpyAttributeDigitalSignalValue digitalSignal; + + NvU8 numberOfHardwareHeadsUsed; } NVAttributesSetEvoRec; #define NV_EVO_DEFAULT_ATTRIBUTES_SET \ @@ -1617,8 +1649,19 @@ typedef struct __NVAttributesSetEvoRec { .imageSharpening = { \ .value = NV_EVO_IMAGE_SHARPENING_DEFAULT, \ }, \ + .numberOfHardwareHeadsUsed = 0, \ } +struct NvKmsVrrFramePacingInfo { + /* Whether sw frame pacing is active. */ + NvBool framePacingActive; + + /* Memory handle for vidmem buffer */ + NvHandle memoryHandle; + + /* Shared data to be updated by RM */ + NV0073_CTRL_RM_VRR_SHARED_DATA *pData; +}; typedef struct _NVEldEvoRec { NvU32 size; @@ -1642,11 +1685,21 @@ typedef struct _NVDispHeadInfoFrameStateEvoRec { NvBool hdTimings; } NVDispHeadInfoFrameStateEvoRec; +typedef enum _NVEvoMergeMode { + NV_EVO_MERGE_MODE_DISABLED, + NV_EVO_MERGE_MODE_SETUP, + NV_EVO_MERGE_MODE_PRIMARY, + NV_EVO_MERGE_MODE_SECONDARY, +} NVEvoMergeMode; + /* * This structure stores information about the active per-head display state. */ typedef struct _NVDispHeadStateEvoRec { + struct NvKmsVrrFramePacingInfo vrrFramePacingInfo; + NvU32 displayRate; + /*! Cached, to preserve across modesets. */ struct NvKmsModeValidationParams modeValidationParams; @@ -1685,6 +1738,10 @@ typedef struct _NVDispHeadStateEvoRec { NVHwModeTimingsEvo timings; NVConnectorEvoRec *pConnectorEvo; /* NULL if the head is not active */ + HDMI_FRL_CONFIG hdmiFrlConfig; + + NVDscInfoEvoRec dscInfo; + enum nvKmsPixelDepth pixelDepth; NVDispHeadAudioStateEvoRec audio; @@ -1708,6 +1765,13 @@ typedef struct _NVDispHeadStateEvoRec { * describe the tile presented by this hardware head. */ NvU8 tilePosition; + + NVEvoMergeMode mergeMode; + /* + * XXX[2Heads1OR] Implement per api-head frame pacing and remove + * NVDispEvoRec::mergeModeVrrSecondaryHeadMask. + */ + NvU32 mergeModeVrrSecondaryHeadMask; } NVDispHeadStateEvoRec; typedef struct _NVDispStereoParamsEvoRec { @@ -1865,31 +1929,11 @@ typedef struct _NVDispEvoRec { NvBool dpAuxLoggingEnabled; struct nvkms_backlight_device *backlightDevice; -} NVDispEvoRec; - -/* - * XXX[2Head1OR] Remove nvHardwareHeadToApiHead(), before implementing logic to - * map multiple hardware heads onto the single api head. - */ -static inline NvU32 nvHardwareHeadToApiHead(const NVDevEvoRec *pDevEvo, - const NvU32 head) -{ - /* - * Force a non-identity mapping between hardware heads and api heads, - * to identify bugs in api head handling. - */ - if (head < pDevEvo->numHeads) { - if (!nvkms_force_api_to_hw_head_identity_mappings()) { - return (pDevEvo->numHeads - 1) - head; - } else { - return head; - } - } else { - nvAssert(head == NV_INVALID_HEAD); - return head; - } -} + NvU32 vrrSetTimeoutEventUsageCount; + NVOS10_EVENT_KERNEL_CALLBACK_EX vrrSetTimeoutCallback; + NvU32 vrrSetTimeoutEventHandle; +} NVDispEvoRec; static inline NvU32 GetNextHwHead(NvU32 hwHeadsMask, const NvU32 prevHwHead) { @@ -1910,12 +1954,17 @@ static inline NvU32 GetNextHwHead(NvU32 hwHeadsMask, const NvU32 prevHwHead) FOR_EACH_EVO_HW_HEAD_IN_MASK((__pDispEvo)->apiHeadState[(__apiHead)].hwHeadsMask, \ (__hwHead)) +static inline NvU32 nvGetPrimaryHwHeadFromMask(const NvU32 hwHeadsMask) +{ + return GetNextHwHead(hwHeadsMask, NV_INVALID_HEAD); +} + static inline NvU32 nvGetPrimaryHwHead(const NVDispEvoRec *pDispEvo, const NvU32 apiHead) { return (apiHead != NV_INVALID_HEAD) ? - GetNextHwHead(pDispEvo->apiHeadState[apiHead].hwHeadsMask, - NV_INVALID_HEAD) : NV_INVALID_HEAD; + nvGetPrimaryHwHeadFromMask(pDispEvo->apiHeadState[apiHead].hwHeadsMask) : + NV_INVALID_HEAD; } typedef enum { @@ -2049,8 +2098,9 @@ typedef struct _NVDpyEvoRec { struct { enum NvKmsDpyVRRType type; + NvU32 edidTimeoutMicroseconds; + NvBool needsSwFramePacing; } vrr; - } NVDpyEvoRec; static inline NvBool nvDpyEvoIsDPMST(const NVDpyEvoRec *pDpyEvo) @@ -2621,6 +2671,9 @@ typedef struct { struct NvKmsPerOpen *nvKmsPerOpen; + RasterLockTopologyPtr globalTopologies; + NvU32 numGlobalTopos; + } NVEvoGlobal; extern NVEvoGlobal nvEvoGlobal; @@ -2646,6 +2699,8 @@ typedef struct { struct { /* pTimings == NULL => this head is disabled */ const NVHwModeTimingsEvo *pTimings; + NvBool enableDsc; + NvBool b2Heads1Or; enum nvKmsPixelDepth pixelDepth; const struct NvKmsUsageBounds *pUsage; NvU32 displayId; @@ -2720,6 +2775,8 @@ typedef struct _CRC32NotifierCrcOut { typedef const struct _nv_evo_hal { void (*SetRasterParams) (NVDevEvoPtr pDevEvo, int head, const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, const NVEvoColorRec *pOverscanColor, NVEvoUpdateState *updateState); void (*SetProcAmp) (NVDispEvoPtr pDispEvo, const NvU32 head, @@ -2875,7 +2932,7 @@ typedef const struct _nv_evo_hal { void (*SetDscParams) (const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo, const enum nvKmsPixelDepth pixelDepth); void (*EnableMidFrameAndDWCFWatermark)(NVDevEvoPtr pDevEvo, @@ -2895,6 +2952,11 @@ typedef const struct _nv_evo_hal { const NVEvoScalerCaps* (*GetWindowScalingCaps)(const NVDevEvoRec *pDevEvo); + void (*SetMergeMode)(const NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoMergeMode mode, + NVEvoUpdateState* pUpdateState); + struct { NvU32 supportsNonInterlockedUsageBoundsUpdate :1; NvU32 supportsDisplayRate :1; @@ -2912,6 +2974,7 @@ typedef const struct _nv_evo_hal { NvU32 supportsSynchronizedOverlayPositionUpdate :1; NvU32 supportsVblankSyncObjects :1; NvU32 requiresScalingTapsInBothDimensions :1; + NvU32 supportsMergeMode :1; NvU32 supportedDitheringModes; size_t impStructSize; @@ -2962,6 +3025,15 @@ nvEvoLayerUsageBoundsEqual(const struct NvKmsUsageBounds *a, &b->layer[layer].scaling); } +static inline void nvAssignHwHeadsMaskApiHeadState( + NVDispApiHeadStateEvoRec *pApiHeadState, + const NvU32 hwHeadsMask) +{ + pApiHeadState->hwHeadsMask = hwHeadsMask; + pApiHeadState->attributes.numberOfHardwareHeadsUsed = + nvPopCount32(hwHeadsMask); +} + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-vrr.h b/src/nvidia-modeset/include/nvkms-vrr.h index bb1add984f..e636fb88bf 100644 --- a/src/nvidia-modeset/include/nvkms-vrr.h +++ b/src/nvidia-modeset/include/nvkms-vrr.h @@ -30,6 +30,22 @@ extern "C" { #endif +enum NvKmsDpyVRRType +nvGetAllowedDpyVrrType(const NVDpyEvoRec *pDpyEvo, + const NvModeTimings *pTimings, + enum NvKmsStereoMode stereoMode, + const NvBool allowGsync, + const enum NvKmsAllowAdaptiveSync allowAdaptiveSync); +void nvAdjustHwModeTimingsForVrrEvo(NVHwModeTimingsEvoPtr pTimings, + const enum NvKmsDpyVRRType vrrType, + const NvU32 edidTimeoutMicroseconds, + const NvU32 vrrOverrideMinRefreshRate, + const NvBool needsSwFramePacing); +NvU16 nvPrepareNextVrrNotifier(NVEvoChannelPtr pChannel, NvU32 sd, NvU32 head); +void nvTrackAndDelayFlipForVrrSwFramePacing(NVDispEvoPtr pDispEvo, + const struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo, + NVFlipChannelEvoHwState *pFlip); + void nvAllocVrrEvo(NVDevEvoPtr pDevEvo); void nvFreeVrrEvo(NVDevEvoPtr pDevEvo); void nvDisableVrr(NVDevEvoPtr pDevEvo); diff --git a/src/nvidia-modeset/interface/nvkms-api.h b/src/nvidia-modeset/interface/nvkms-api.h index 56a8498b9e..e1fa905d8f 100644 --- a/src/nvidia-modeset/interface/nvkms-api.h +++ b/src/nvidia-modeset/interface/nvkms-api.h @@ -355,6 +355,7 @@ enum NvKmsModeValidationOverrides { NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS = (1 << 16), NVKMS_MODE_VALIDATION_ALLOW_DP_INTERLACED = (1 << 17), NVKMS_MODE_VALIDATION_NO_INTERLACED_MODES = (1 << 18), + NVKMS_MODE_VALIDATION_MAX_ONE_HARDWARE_HEAD = (1 << 19), }; /*! @@ -1277,9 +1278,6 @@ struct NvKmsQueryConnectorStaticDataReply { NvKmsConnectorSignalFormat signalFormat; NvU32 physicalIndex; NvU32 physicalLocation; - - /* Bitmask of valid heads to drive dpy(s) on this connector. */ - NvU32 headMask; }; struct NvKmsQueryConnectorStaticDataParams { @@ -1343,6 +1341,8 @@ struct NvKmsQueryDpyStaticDataReply { char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH]; NvBool mobileInternal; NvBool isDpMST; + /* Bitmask of valid heads to drive this dpy. */ + NvU32 headMask; }; struct NvKmsQueryDpyStaticDataParams { @@ -1975,6 +1975,7 @@ enum NvKmsSetModeOneDispStatus { NVKMS_SET_MODE_ONE_DISP_STATUS_FAILED_DISPLAY_PORT_BANDWIDTH_CHECK = 3, NVKMS_SET_MODE_ONE_DISP_STATUS_INCOMPATIBLE_DPYS = 4, NVKMS_SET_MODE_ONE_DISP_STATUS_DUPLICATE_DPYS = 5, + NVKMS_SET_MODE_ONE_DISP_STATUS_FAILED_TO_ASSIGN_HARDWARE_HEADS = 6, }; struct NvKmsSetModeOneDispReply { @@ -2551,6 +2552,8 @@ enum NvKmsDpyAttribute { NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE, NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_IS_MULTISTREAM, NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_SINK_IS_AUDIO_CAPABLE, + + NV_KMS_DPY_ATTRIBUTE_NUMBER_OF_HARDWARE_HEADS_USED, }; /*! Values for the NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING attribute. */ diff --git a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h index c76493d748..cf0c2a5902 100644 --- a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h +++ b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h @@ -165,8 +165,6 @@ struct NvKmsKapiConnectorInfo { NvU32 physicalIndex; - NvU32 headMask; - NvKmsConnectorSignalFormat signalFormat; NvKmsConnectorType type; @@ -194,6 +192,7 @@ struct NvKmsKapiStaticDisplayInfo { NvU32 numPossibleClones; NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS]; + NvU32 headMask; }; struct NvKmsKapiSyncpt { @@ -1074,6 +1073,21 @@ struct NvKmsKapiFunctionsTable { NvU64 *pPages ); + /*! + * Check if this memory object can be scanned out for display. + * + * \param [in] device A device allocated using allocateDevice(). + * + * \param [in] memory The memory object to check for display support. + * + * \return NV_TRUE if this memory can be displayed, NV_FALSE if not. + */ + NvBool (*isMemoryValidForDisplay) + ( + const struct NvKmsKapiDevice *device, + const struct NvKmsKapiMemory *memory + ); + /* * Import SGT as a memory handle. * diff --git a/src/nvidia-modeset/kapi/src/nvkms-kapi.c b/src/nvidia-modeset/kapi/src/nvkms-kapi.c index e521be1b3f..52ce05359b 100644 --- a/src/nvidia-modeset/kapi/src/nvkms-kapi.c +++ b/src/nvidia-modeset/kapi/src/nvkms-kapi.c @@ -43,10 +43,13 @@ #include /* NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 */ #include /* NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD */ +#include /* NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM */ #include /* NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES */ +#include /* NV0080_CTRL_CMD_FB_GET_CAPS_V2 */ #include /* NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT */ #include "ctrl/ctrl003e.h" /* NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES */ +#include "ctrl/ctrl0041.h" /* NV0041_CTRL_SURFACE_INFO */ ct_assert(NVKMS_KAPI_LAYER_PRIMARY_IDX == NVKMS_MAIN_LAYER); @@ -113,8 +116,10 @@ static NvBool RmAllocateDevice(struct NvKmsKapiDevice *device) NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS idInfoParams = { }; NV2080_ALLOC_PARAMETERS subdevAllocParams = { 0 }; NV0080_ALLOC_PARAMETERS allocParams = { }; + NV0080_CTRL_FB_GET_CAPS_V2_PARAMS fbCapsParams = { 0 }; NvU32 hRmDevice, hRmSubDevice; + NvBool supportsGenericPageKind; NvU32 ret; /* Allocate RM client */ @@ -228,6 +233,30 @@ static NvBool RmAllocateDevice(struct NvKmsKapiDevice *device) device->hRmSubDevice = hRmSubDevice; + if (device->isSOC) { + /* NVKMS is only used on T23X and later chips, + * which all support generic memory. */ + supportsGenericPageKind = NV_TRUE; + } else { + ret = nvRmApiControl(device->hRmClient, + device->hRmDevice, + NV0080_CTRL_CMD_FB_GET_CAPS_V2, + &fbCapsParams, + sizeof (fbCapsParams)); + if (ret != NVOS_STATUS_SUCCESS) { + nvKmsKapiLogDeviceDebug(device, "Failed to query framebuffer capabilities"); + goto failed; + } + supportsGenericPageKind = + NV0080_CTRL_FB_GET_CAP(fbCapsParams.capsTbl, + NV0080_CTRL_FB_CAPS_GENERIC_PAGE_KIND); + } + + device->caps.genericPageKind = + supportsGenericPageKind ? + 0x06 /* NV_MMU_PTE_KIND_GENERIC_MEMORY */ : + 0xfe /* NV_MMU_PTE_KIND_GENERIC_16BX2 */; + return NV_TRUE; failed: @@ -352,8 +381,10 @@ static NvBool KmsAllocateDevice(struct NvKmsKapiDevice *device) device->caps.maxWidthInPixels = paramsAlloc->reply.maxWidthInPixels; device->caps.maxHeightInPixels = paramsAlloc->reply.maxHeightInPixels; device->caps.maxCursorSizeInPixels = paramsAlloc->reply.maxCursorSize; - device->caps.genericPageKind = paramsAlloc->reply.genericPageKind; device->caps.requiresVrrSemaphores = paramsAlloc->reply.requiresVrrSemaphores; + /* The generic page kind was determined during RM device allocation, + * but it should match what NVKMS reports */ + nvAssert(device->caps.genericPageKind == paramsAlloc->reply.genericPageKind); /* XXX Add LUT support */ @@ -917,6 +948,7 @@ static NvBool GetDeviceResourcesInfo nvkms_memset(info, 0, sizeof(*info)); info->caps.hasVideoMemory = !device->isSOC; + info->caps.genericPageKind = device->caps.genericPageKind; if (device->hKmsDevice == 0x0) { info->caps.pitchAlignment = 0x1; @@ -984,7 +1016,6 @@ static NvBool GetDeviceResourcesInfo info->caps.maxWidthInPixels = device->caps.maxWidthInPixels; info->caps.maxHeightInPixels = device->caps.maxHeightInPixels; info->caps.maxCursorSizeInPixels = device->caps.maxCursorSizeInPixels; - info->caps.genericPageKind = device->caps.genericPageKind; info->caps.pitchAlignment = NV_EVO_PITCH_ALIGNMENT; @@ -1102,8 +1133,6 @@ static NvBool GetConnectorInfo info->physicalIndex = paramsConnector.reply.physicalIndex; - info->headMask = paramsConnector.reply.headMask; - info->signalFormat = paramsConnector.reply.signalFormat; info->type = paramsConnector.reply.type; @@ -1159,7 +1188,7 @@ static NvBool GetStaticDisplayInfo info->dpAddress[sizeof(paramsDpyStatic.reply.dpAddress) - 1] = '\0'; info->internal = paramsDpyStatic.reply.mobileInternal; - + info->headMask = paramsDpyStatic.reply.headMask; done: return status; @@ -1797,6 +1826,57 @@ static NvBool GetMemoryPages return NV_TRUE; } +/* + * Check if the memory we are creating this framebuffer with is valid. We + * cannot scan out sysmem or compressed buffers. + * + * If we cannot use this memory for display it may be resident in sysmem + * or may belong to another GPU. + */ +static NvBool IsMemoryValidForDisplay +( + const struct NvKmsKapiDevice *device, + const struct NvKmsKapiMemory *memory +) +{ + NV_STATUS status; + NV0041_CTRL_SURFACE_INFO surfaceInfo = {}; + NV0041_CTRL_GET_SURFACE_INFO_PARAMS surfaceInfoParams = {}; + + if (device == NULL || memory == NULL) { + return NV_FALSE; + } + + /* + * Don't do these checks on tegra. Tegra has different capabilities. + * Here we always say display is possible so we never fail framebuffer + * creation. + */ + if (device->isSOC) { + return NV_TRUE; + } + + /* Get the type of address space this memory is in, i.e. vidmem or sysmem */ + surfaceInfo.index = NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE; + + surfaceInfoParams.surfaceInfoListSize = 1; + surfaceInfoParams.surfaceInfoList = (NvP64)&surfaceInfo; + + status = nvRmApiControl(device->hRmClient, + memory->hRmHandle, + NV0041_CTRL_CMD_GET_SURFACE_INFO, + &surfaceInfoParams, + sizeof(surfaceInfoParams)); + if (status != NV_OK) { + nvKmsKapiLogDeviceDebug(device, + "Failed to get memory location of RM memory object 0x%x", + memory->hRmHandle); + return NV_FALSE; + } + + return surfaceInfo.data == NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM; +} + static void FreeMemoryPages ( NvU64 *pPages @@ -3238,5 +3318,7 @@ NvBool nvKmsKapiGetFunctionsTableInternal funcsTable->getMemoryPages = GetMemoryPages; funcsTable->freeMemoryPages = FreeMemoryPages; + funcsTable->isMemoryValidForDisplay = IsMemoryValidForDisplay; + return NV_TRUE; } diff --git a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h index bedb7e0751..9e519779a1 100644 --- a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h +++ b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h @@ -40,11 +40,30 @@ #include "nv_stdarg.h" enum NvKmsSyncPtOp { + /* + * Call into Tegra's kernel nvhost driver, and allocate a syncpoint that can + * be exclusively used by the caller. Internally, this operation will call + * get() to set the initial refcount of the syncpoint to 1. + */ NVKMS_SYNCPT_OP_ALLOC, - NVKMS_SYNCPT_OP_GET, + /* + * Decrease the refcount of an already allocated syncpoint. Once the + * refcount drops to 0, the syncpoint will be returned to the free pool that + * nvhost manages, so PUT can also be used to balance out an ALLOC. + */ NVKMS_SYNCPT_OP_PUT, + /* + * Extract syncpt id and thresh from the sync-file file descriptor + */ NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, + /* + * Create dma-fence from syncpt id and thresh value and create sync_file + * file descriptor for the dma-fence handle created. + */ NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, + /* + * read syncpt minimum value of given syncpt + */ NVKMS_SYNCPT_OP_READ_MINVAL, }; @@ -77,7 +96,6 @@ typedef struct { } read_minval; } NvKmsSyncPtOpParams; -NvBool nvkms_force_api_to_hw_head_identity_mappings(void); NvBool nvkms_output_rounding_fix(void); void nvkms_call_rm (void *ops); diff --git a/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp b/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp index 91368b663d..f6fec792ce 100644 --- a/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp @@ -39,6 +39,8 @@ namespace nvkmsDisplayPort { +static void EnableVRR(NVDpyEvoPtr pDpyEvo); + ConnectorEventSink::ConnectorEventSink(NVConnectorEvoPtr pConnectorEvo) : pConnectorEvo(pConnectorEvo) { @@ -221,6 +223,131 @@ static void nvDPAddDeviceToActiveGroup(NVDpyEvoPtr pDpyEvo) } } +static bool DpyHasVRREDID(NVDpyEvoPtr pDpyEvo) +{ + return pDpyEvo->parsedEdid.valid && + pDpyEvo->parsedEdid.info.nvdaVsdbInfo.valid && + // As of this writing, only version 1 is defined. + pDpyEvo->parsedEdid.info.nvdaVsdbInfo.vsdbVersion == 1 && + pDpyEvo->parsedEdid.info.nvdaVsdbInfo.vrrData.v1.supportsVrr; +} + +static void EnableVRR(NVDpyEvoPtr pDpyEvo) +{ + NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; + DisplayPort::Device *device = pDpyEvo->dp.pDpLibDevice->device; + const NvBool dispSupportsVrr = nvDispSupportsVrr(pDispEvo); + + if (pDpyEvo->internal) { + // VRR + notebooks not supported, yet + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + return; + } + + // If the DP library already has the monitor VRR-enabled, then we don't need to + // do it again, but we should still update the minimum refresh rate from the + // EDID if one is available. + const bool alreadyEnabled = device->isVrrMonitorEnabled() && + device->isVrrDriverEnabled(); + + if (DpyHasVRREDID(pDpyEvo) && !alreadyEnabled) { + // Perform VRR enablement whenever the monitor supports VRR, but only + // record it as actually enabled if the rest of the system supports VRR. + // Other state such as the availability of NV_CTRL_GSYNC_ALLOWED is + // keyed off of the presence of a dpy with vrr.type != + // NVKMS_DPY_VRR_TYPE_NONE. + if (device->startVrrEnablement() && dispSupportsVrr) { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_GSYNC; + } else { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + } + + if ((pDpyEvo->vrr.type == NVKMS_DPY_VRR_TYPE_NONE) && dispSupportsVrr) { + nvEvoLogDisp(pDispEvo, EVO_LOG_WARN, + "%s: Failed to initialize G-SYNC", + pDpyEvo->name); + } + } else if (pDispEvo->pDevEvo->caps.supportsDP13 && + device->getIgnoreMSACap()) { + // DP monitors indicate Adaptive-Sync support through the + // MSA_TIMING_PAR_IGNORED bit in the DOWN_STREAM_PORT_COUNT register + // (DP spec 1.4a section 2.2.4.1.1) + if (dispSupportsVrr) { + if (nvDpyIsAdaptiveSyncDefaultlisted(pDpyEvo)) { + pDpyEvo->vrr.type = + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED; + } else { + pDpyEvo->vrr.type = + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED; + } + } else { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + } + + if (pDispEvo->pDevEvo->hal->caps.supportsDisplayRate) { + pDpyEvo->vrr.needsSwFramePacing = dispSupportsVrr; + } + } else { + // Assign pDpyEvo->vrr.type independent of DpyHasVRREDID(), so that if + // the monitor is successfully reenabled by the DP library before it + // calls notifyZombieStateChange(), it'll pick up the correct state. If + // reenablement succeeds, the monitor supports VRR even if we haven't + // read an EDID that says it does yet. + if (alreadyEnabled && dispSupportsVrr) { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_GSYNC; + } else { + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + } + } + + if (pDpyEvo->parsedEdid.valid && nvDpyIsAdaptiveSync(pDpyEvo)) { + // Adaptive-Sync minimum refresh rate is either in DisplayID (Display + // ID spec 1.3 section 4.6 Video Timing Range Limits) or EDID (EDID + // spec 1.4 section 3.10.3.3 Display Range Limits & Additional Timing + // Descriptor Definition) + int minRR = 0; + if (pDpyEvo->parsedEdid.info.ext_displayid.version) { + minRR = pDpyEvo->parsedEdid.info.ext_displayid.range_limits[0].vfreq_min; + } + + if (minRR == 0) { + NvU32 i; + for (i = 0; i < NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR; i++) { + if (pDpyEvo->parsedEdid.info.ldd[i].tag == + NVT_EDID_DISPLAY_DESCRIPTOR_DRL) { + minRR = pDpyEvo->parsedEdid.info.ldd[i].u.range_limit.min_v_rate; + } + } + } + + if (minRR == 0) { + // Adaptive sync does not support self refresh (zero timeout) + nvEvoLogDisp(pDispEvo, EVO_LOG_WARN, + "%s: G-SYNC Compatible: EDID min refresh rate " + "invalid, disabling G-SYNC Compatible.", + pDpyEvo->name); + pDpyEvo->vrr.type = NVKMS_DPY_VRR_TYPE_NONE; + pDpyEvo->vrr.needsSwFramePacing = FALSE; + } else { + pDpyEvo->vrr.edidTimeoutMicroseconds = 1000000 / minRR; + } + } else if (DpyHasVRREDID(pDpyEvo)) { + // Update the minimum refresh rate if a VRR EDID block is present. + const int minRR = + pDpyEvo->parsedEdid.info.nvdaVsdbInfo.vrrData.v1.minRefreshRate; + + if (minRR == 0) { + // Zero indicates that no refreshes are required (i.e. the panel is + // self-refreshing). + pDpyEvo->vrr.edidTimeoutMicroseconds = 0; + } else { + // Round the timeout down. It's better to refresh the panel too soon + // than too late. + pDpyEvo->vrr.edidTimeoutMicroseconds = 1000000 / minRR; + } + } +} + // when we get this event, the DP lib has done link training and the // EDID has been read (by the DP lib) void ConnectorEventSink::newDevice(DisplayPort::Device *device) @@ -395,12 +522,20 @@ void ConnectorEventSink::notifyZombieStateChange(DisplayPort::Device *dev, sendEvent = TRUE; } + // Don't reset VRR enablement here. Though normally NVKMS initiates VRR + // enablement, the DP library needs to initiate VRR re-enablement of a + // zombie device itself before performing link training or else the + // monitor might remain blank if a VRR stream is active when it's + // plugged back in. } else { if (!pDpLibDevice->isPlugged && dev->isPlugged()) { pDpLibDevice->isPlugged = TRUE; sendEvent = TRUE; } + // Determine whether the DP library reenabled VRR on this display. + EnableVRR(pDpyEvo); + nvDPAddDeviceToActiveGroup(pDpyEvo); } @@ -486,6 +621,8 @@ void nvDPLibUpdateDpyLinkConfiguration(NVDpyEvoPtr pDpyEvo) // 27000000. Convert back to NV-CONTROL's defines. linkRate /= 27000000; + nvkmsDisplayPort::EnableVRR(pDpyEvo); + switch (pDpLibDevice->device->getConnectorType()) { case DisplayPort::connectorDisplayPort: connectorType = NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE_DISPLAYPORT; diff --git a/src/nvidia-modeset/src/dp/nvdp-connector.cpp b/src/nvidia-modeset/src/dp/nvdp-connector.cpp index 31744bf93e..cc1055e713 100644 --- a/src/nvidia-modeset/src/dp/nvdp-connector.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-connector.cpp @@ -108,7 +108,10 @@ void nvDPNotifyLongPulse(NVConnectorEvoPtr pConnectorEvo, pNVDpLibConnector->plugged = connected; - if (connected && !nvAssignSOREvo(pConnectorEvo, 0 /* sorExcludeMask */)) { + if (connected && !nvAssignSOREvo(pConnectorEvo->pDispEvo, + nvDpyIdToNvU32(pConnectorEvo->displayId), + FALSE /* b2Heads1Or */, + 0 /* sorExcludeMask */)) { // DPLib takes care of skipping LT on unassigned SOR Display. } @@ -310,7 +313,8 @@ NVDPLibModesetStatePtr nvDPLibCreateModesetState( const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, - NVHwModeTimingsEvo *pTimings) + const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo) { bool found = false; const NVDPLibConnectorRec *pDpLibConnector = NULL; @@ -345,7 +349,7 @@ NVDPLibModesetStatePtr nvDPLibCreateModesetState( colorSpace, colorBpc, &pDpLibModesetState->modesetParams); - if (pTimings->dpDsc.enable) { + if (pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DP) { pDpLibModesetState->modesetParams.modesetInfo.bEnableDsc = true; /* @@ -354,8 +358,22 @@ NVDPLibModesetStatePtr nvDPLibCreateModesetState( * output compressed stream. */ pDpLibModesetState->modesetParams.modesetInfo.depth = - pTimings->dpDsc.bitsPerPixelX16; + pDscInfo->dp.bitsPerPixelX16; + + switch (pDscInfo->dp.dscMode) { + case NV_DSC_EVO_MODE_SINGLE: + pDpLibModesetState->modesetParams.modesetInfo.mode = + DSC_SINGLE; + break; + case NV_DSC_EVO_MODE_DUAL: + pDpLibModesetState->modesetParams.modesetInfo.mode = + DSC_DUAL; + break; + } + } else { + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DISABLED); } + pDpLibModesetState->dpyIdList = dpyIdList; return pDpLibModesetState; @@ -385,7 +403,9 @@ NvBool nvDPLibValidateTimings( const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, - NVHwModeTimingsEvo *pTimings) + const NVHwModeTimingsEvo *pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo) { const NVDpyEvoRec *pDpyEvo; const NVDPLibConnectorRec *pDpLibConnector = NULL; @@ -440,10 +460,21 @@ NvBool nvDPLibValidateTimings( colorBpc, pModesetParams); + if (b2Heads1Or) { + pModesetParams->modesetInfo.mode = DSC_DUAL; + } + dpDscParams.bCheckWithDsc = true; dpDscParams.forceDsc = pModeValidationParams->forceDsc ? DisplayPort::DSC_FORCE_ENABLE : DisplayPort::DSC_DEFAULT; + /* + * 2Heads1Or requires either YUV420 or DSC; if b2Heads1Or is enabled + * but YUV420 is not, force DSC. + */ + if (b2Heads1Or && (pTimings->yuv420Mode != NV_YUV420_MODE_HW)) { + dpDscParams.forceDsc = DisplayPort::DSC_FORCE_ENABLE; + } dpDscParams.bitsPerPixelX16 = pModeValidationParams->dscOverrideBitsPerPixelX16; dpDscParams.pDscOutParams = pDscOutParams; @@ -452,14 +483,30 @@ NvBool nvDPLibValidateTimings( pGroup, *pModesetParams, &dpDscParams); - if (ret) { - pTimings->dpDsc.enable = dpDscParams.bEnableDsc; - pTimings->dpDsc.bitsPerPixelX16 = dpDscParams.bitsPerPixelX16; + if (ret && b2Heads1Or) { + /* + * 2Heads1OR requires either YUV420 or DSC; + * dpDscParams.bEnableDsc is assigned by compoundQueryAttach(). + */ + nvAssert(dpDscParams.bEnableDsc || + (pTimings->yuv420Mode == NV_YUV420_MODE_HW)); + } - ct_assert(sizeof(pTimings->dpDsc.pps) == sizeof(pDscOutParams->PPS)); + if (ret && (pDscInfo != NULL)) { + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); - nvkms_memcpy(pTimings->dpDsc.pps, - pDscOutParams->PPS, sizeof(pTimings->dpDsc.pps)); + if (dpDscParams.bEnableDsc) { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DP; + + pDscInfo->dp.dscMode = b2Heads1Or ? + NV_DSC_EVO_MODE_DUAL : NV_DSC_EVO_MODE_SINGLE; + pDscInfo->dp.bitsPerPixelX16 = dpDscParams.bitsPerPixelX16; + ct_assert(sizeof(pDscInfo->dp.pps) == sizeof(pDscOutParams->PPS)); + nvkms_memcpy(pDscInfo->dp.pps, pDscOutParams->PPS, + sizeof(pDscInfo->dp.pps)); + } else { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DISABLED; + } } done: @@ -498,7 +545,9 @@ NvBool nvDPValidateModeForDpyEvo( const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, - NVHwModeTimingsEvo *pTimings) + const NVHwModeTimingsEvo *pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo) { const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo; @@ -515,7 +564,9 @@ NvBool nvDPValidateModeForDpyEvo( colorSpace, colorBpc, pModeValidationParams, - pTimings); + pTimings, + b2Heads1Or, + pDscInfo); connector->endCompoundQuery(); return ret; @@ -628,10 +679,11 @@ void nvDPPreSetMode(NVDPLibConnectorPtr pDpLibConnector, if ((newHeadMask & NVBIT(head)) != 0x0 && (oldHeadMask & NVBIT(head)) == 0x0) { - NotifyAttachBegin(pDpLibConnector, - head, - pModesetUpdateState->pDpLibModesetState[head]); - + if (pModesetUpdateState->pDpLibModesetState[head] != NULL) { + NotifyAttachBegin(pDpLibConnector, + head, + pModesetUpdateState->pDpLibModesetState[head]); + } } else if ((newHeadMask & NVBIT(head)) == 0x0 && (oldHeadMask & NVBIT(head)) != 0x0) { @@ -646,7 +698,8 @@ void nvDPPreSetMode(NVDPLibConnectorPtr pDpLibConnector, * update. The function should be called for each of affected(change in * head-connector attachment) DpLib connectors, before commit. */ -void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector) +void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector, + const NVEvoModesetUpdateState *pModesetUpdateState) { const NVConnectorEvoRec *pConnectorEvo = pDpLibConnector->pConnectorEvo; @@ -660,8 +713,9 @@ void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector) if ((newHeadMask & NVBIT(head)) != 0x0 && (oldHeadMask & NVBIT(head)) == 0x0) { - NotifyAttachEnd(pDpLibConnector, head); - + if (pModesetUpdateState->pDpLibModesetState[head] != NULL) { + NotifyAttachEnd(pDpLibConnector, head); + } } else if ((newHeadMask & NVBIT(head)) == 0x0 && (oldHeadMask & NVBIT(head)) != 0x0) { @@ -713,7 +767,7 @@ void nvDPPause(NVDPLibConnectorPtr pNVDpLibConnector) params.dpLink = pConnectorEvo->or.protocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A ? 0 : 1; - params.sorIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + params.sorIndex = pConnectorEvo->or.primary; NvU32 ret = nvRmApiControl( nvEvoGlobal.clientHandle, @@ -748,7 +802,7 @@ void nvDPPause(NVDPLibConnectorPtr pNVDpLibConnector) */ static NvU32 GetFirmwareHead(NVConnectorEvoPtr pConnectorEvo) { - NvU32 orIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + NvU32 orIndex = pConnectorEvo->or.primary; if (orIndex == NV_INVALID_OR || pConnectorEvo->or.ownerHeadMask[orIndex] == 0) { @@ -769,7 +823,8 @@ static bool ConnectorIsSharedWithActiveOR(NVConnectorEvoPtr pConnectorEvo) FOR_ALL_EVO_CONNECTORS(pOtherConnectorEvo, pDispEvo) { if (pOtherConnectorEvo != pConnectorEvo && nvIsConnectorActiveEvo(pOtherConnectorEvo) && - (pOtherConnectorEvo->or.mask & pConnectorEvo->or.mask) != 0x0) { + (pOtherConnectorEvo->or.primary == pConnectorEvo->or.primary)) { + nvAssert(pOtherConnectorEvo->or.primary != NV_INVALID_OR); return true; } } @@ -817,7 +872,10 @@ NvBool nvDPResume(NVDPLibConnectorPtr pNVDpLibConnector, NvBool plugged) pNVDpLibConnector->plugged = plugged; if (plugged && !pNVDpLibConnector->headInFirmware) { - NvBool ret = nvAssignSOREvo(pConnectorEvo, 0 /* sorExcludeMask */); + NvBool ret = nvAssignSOREvo(pDispEvo, + nvDpyIdToNvU32(pConnectorEvo->displayId), + FALSE /* b2Heads1Or */, + 0 /* sorExcludeMask */); nvAssert(ret); if (!ret) { diff --git a/src/nvidia-modeset/src/dp/nvdp-device.cpp b/src/nvidia-modeset/src/dp/nvdp-device.cpp index e24e7a211f..7bb79cd0c3 100644 --- a/src/nvidia-modeset/src/dp/nvdp-device.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-device.cpp @@ -146,3 +146,12 @@ void nvDPDpyFree(NVDpyEvoPtr pDpyEvo) pDpyEvo->pConnectorEvo->pDpLibConnector->evtSink->lostDevice(device); } + +NvBool nvDPDpyIsDscPossible(const NVDpyEvoRec *pDpyEvo) +{ + if (!nvDpyUsesDPLib(pDpyEvo) || + (pDpyEvo->dp.pDpLibDevice == NULL)) { + return FALSE; + } + return pDpyEvo->dp.pDpLibDevice->device->isDSCPossible(); +} diff --git a/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp b/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp index 74e89b8cbd..d4fa13503f 100644 --- a/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp @@ -110,7 +110,7 @@ NvU32 EvoInterface::getDisplayId() NvU32 EvoInterface::getSorIndex() { - return nvEvoConnectorGetPrimaryOr(pConnectorEvo); + return pConnectorEvo->or.primary; } NvU32 EvoInterface::getLinkIndex() diff --git a/src/nvidia-modeset/src/g_nvkms-evo-states.c b/src/nvidia-modeset/src/g_nvkms-evo-states.c index e8ae3db225..9c6c633a3f 100644 --- a/src/nvidia-modeset/src/g_nvkms-evo-states.c +++ b/src/nvidia-modeset/src/g_nvkms-evo-states.c @@ -50,6 +50,8 @@ static NvBool EvoLockStateLockHeadsFrameLockServerManyHeads(NVDispEvoPtr, NVEvoS static NvBool EvoLockStateLockHeadsFrameLockServerManyHeadsPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateLockHeadsFrameLockServerPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateLockHeadsPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); +static NvBool EvoLockStateMergeMode(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); +static NvBool EvoLockStateMergeModeVrr(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateNoLock(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliLastSecondary(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliLastSecondaryFrameLockClient(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); @@ -1407,6 +1409,59 @@ static NvBool EvoLockStateLockHeadsPlusRef( } } +static NvBool EvoLockStateMergeMode( + NVDispEvoPtr pDispEvo, + NVEvoSubDevPtr pEvoSubDev, + NVEvoLockAction action, + const NvU32 *pHeads +) +{ + NvBool queryOnly = pHeads == NULL; + + switch (action) { + + case NV_EVO_DISABLE_MERGE_MODE: + if (!queryOnly) { + nvEvoLockHWStateNoLock(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateNoLock; + } + return TRUE; + + case NV_EVO_ENABLE_VRR: + if (!queryOnly) { + nvEvoLockHWStateNoChange(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateMergeModeVrr; + } + return TRUE; + + default: + return FALSE; + } +} + +static NvBool EvoLockStateMergeModeVrr( + NVDispEvoPtr pDispEvo, + NVEvoSubDevPtr pEvoSubDev, + NVEvoLockAction action, + const NvU32 *pHeads +) +{ + NvBool queryOnly = pHeads == NULL; + + switch (action) { + + case NV_EVO_DISABLE_VRR: + if (!queryOnly) { + nvEvoLockHWStateMergeMode(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateMergeMode; + } + return TRUE; + + default: + return FALSE; + } +} + static NvBool EvoLockStateNoLock( NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, @@ -1467,6 +1522,13 @@ static NvBool EvoLockStateNoLock( } return TRUE; + case NV_EVO_ENABLE_MERGE_MODE: + if (!queryOnly) { + nvEvoLockHWStateMergeMode(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateMergeMode; + } + return TRUE; + default: return FALSE; } diff --git a/src/nvidia-modeset/src/nvkms-attributes.c b/src/nvidia-modeset/src/nvkms-attributes.c index 8275603488..9505c1344b 100644 --- a/src/nvidia-modeset/src/nvkms-attributes.c +++ b/src/nvidia-modeset/src/nvkms-attributes.c @@ -1085,16 +1085,85 @@ static NvBool GetStereoEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue) static NvBool GetVrrMinRefreshRate(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue) { - return FALSE; + NvU32 timeoutMicroseconds; + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NvU32 head; + + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { + return FALSE; + } + + head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); + nvAssert(head != NV_INVALID_HEAD); + timeoutMicroseconds = + pDispEvo->headState[head].timings.vrr.timeoutMicroseconds; +#if defined(DEBUG) + { + NvU32 h; + FOR_EACH_EVO_HW_HEAD(pDispEvo, pDpyEvo->apiHead, h) { + nvAssert(timeoutMicroseconds == + pDispEvo->headState[h].timings.vrr.timeoutMicroseconds); + } + } +#endif + + *pValue = timeoutMicroseconds ? (1000000 / timeoutMicroseconds) : 0; + + return TRUE; } static NvBool GetVrrMinRefreshRateValidValues( const NVDpyEvoRec *pDpyEvo, struct NvKmsAttributeValidValuesCommonReply *pValidValues) { - return FALSE; + NvU32 minMinRefreshRate, maxMinRefreshRate; + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NvU32 head; + + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { + return FALSE; + } + + head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); + nvAssert(head != NV_INVALID_HEAD); + nvGetDpyMinRefreshRateValidValues(&pDispEvo->headState[head].timings, + pDpyEvo->vrr.type, + pDpyEvo->vrr.edidTimeoutMicroseconds, + &minMinRefreshRate, + &maxMinRefreshRate); +#if defined(DEBUG) + { + NvU32 h; + FOR_EACH_EVO_HW_HEAD(pDispEvo, pDpyEvo->apiHead, h) { + NvU32 tmpMinMinRefreshRate, tmpMaxMinRefreshRate; + + nvGetDpyMinRefreshRateValidValues(&pDispEvo->headState[h].timings, + pDpyEvo->vrr.type, + pDpyEvo->vrr.edidTimeoutMicroseconds, + &tmpMinMinRefreshRate, + &tmpMaxMinRefreshRate); + + nvAssert(tmpMinMinRefreshRate == minMinRefreshRate); + nvAssert(tmpMaxMinRefreshRate == maxMinRefreshRate); + } + } +#endif + + nvAssert(pValidValues->type == NV_KMS_ATTRIBUTE_TYPE_RANGE); + + pValidValues->u.range.min = minMinRefreshRate; + pValidValues->u.range.max = maxMinRefreshRate; + + return TRUE; } +static NvBool GetNumberOfHardwareHeadsUsed( + const NVDpyEvoRec *pDpyEvo, + NvS64 *pNumHwHeadsUsed) +{ + *pNumHwHeadsUsed = pDpyEvo->currentAttributes.numberOfHardwareHeadsUsed; + return TRUE; +} static const struct { NvBool (*set)(NVDpyEvoPtr pDpyEvo, NvS64 value); NvBool (*get)(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue); @@ -1283,6 +1352,12 @@ static const struct { .getValidValues = GetVrrMinRefreshRateValidValues, .type = NV_KMS_ATTRIBUTE_TYPE_RANGE, }, + [NV_KMS_DPY_ATTRIBUTE_NUMBER_OF_HARDWARE_HEADS_USED] = { + .set = NULL, + .get = GetNumberOfHardwareHeadsUsed, + .getValidValues = NULL, + .type = NV_KMS_ATTRIBUTE_TYPE_INTEGER, + }, }; /*! diff --git a/src/nvidia-modeset/src/nvkms-console-restore.c b/src/nvidia-modeset/src/nvkms-console-restore.c index 9d2069988e..bb9d96695f 100644 --- a/src/nvidia-modeset/src/nvkms-console-restore.c +++ b/src/nvidia-modeset/src/nvkms-console-restore.c @@ -51,7 +51,9 @@ static NvBool FindMode(NVDpyEvoPtr pDpyEvo, params.request.dpyId = pDpyEvo->id; params.request.modeIndex = index++; - params.request.modeValidation.overrides = NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS; + params.request.modeValidation.overrides = + NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS | + NVKMS_MODE_VALIDATION_MAX_ONE_HARDWARE_HEAD; nvValidateModeIndex(pDpyEvo, ¶ms.request, ¶ms.reply); @@ -229,7 +231,7 @@ static NvU32 PickApiHead(const NVDpyEvoRec *pDpyEvo, const NvU32 availableApiHeadsMask) { const NvU32 possibleApiHeads = availableApiHeadsMask & - pDpyEvo->pConnectorEvo->validApiHeadMask; + nvDpyGetPossibleApiHeadsMask(pDpyEvo); const NvU32 activeApiHeadsMask = GetActiveApiHeadMask(pDpyEvo->pDispEvo); @@ -279,7 +281,8 @@ static NvBool InitModeOneHeadRequest( pRequestHead->dpyIdList = nvAddDpyIdToEmptyDpyIdList(pDpyEvo->id); pRequestHead->modeValidationParams.overrides = - NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS; + NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS | + NVKMS_MODE_VALIDATION_MAX_ONE_HARDWARE_HEAD; if (pOverrideViewPortSizeIn != NULL) { pRequestHead->viewPortSizeIn = *pOverrideViewPortSizeIn; } else { diff --git a/src/nvidia-modeset/src/nvkms-cursor.c b/src/nvidia-modeset/src/nvkms-cursor.c index aee9eadf4c..a766c46679 100644 --- a/src/nvidia-modeset/src/nvkms-cursor.c +++ b/src/nvidia-modeset/src/nvkms-cursor.c @@ -118,7 +118,7 @@ SetCursorImageOneHead(NVDispEvoPtr pDispEvo, } if (pSurfaceEvoOld) { - nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvoOld); + nvEvoDecrementSurfaceRefCnts(pSurfaceEvoOld); } pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo = pSurfaceEvoNew; @@ -285,20 +285,35 @@ void nvMoveCursor(NVDispEvoPtr pDispEvo, const NvU32 apiHead, NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; - NvU32 head; + NvU16 hwViewportInWidth; + NvU32 head, headCount; /* XXX NVKMS TODO: validate x,y against current viewport in? */ nvAssert(apiHead != NV_INVALID_HEAD); + headCount = 0; FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; const NvU32 sd = pDispEvo->displayOwner; - pDevEvo->gpus[sd].headState[head].cursor.x = pParams->x; + if (headCount == 0) { + hwViewportInWidth = pTimings->viewPort.in.width; + } else { + nvAssert(hwViewportInWidth == pTimings->viewPort.in.width); + } + + pDevEvo->gpus[sd].headState[head].cursor.x = + pParams->x - (hwViewportInWidth * pHeadState->tilePosition); pDevEvo->gpus[sd].headState[head].cursor.y = pParams->y; nvEvoMoveCursorInternal(pDispEvo, - head, pParams->x, pParams->y); + head, + pDevEvo->gpus[sd].headState[head].cursor.x, + pDevEvo->gpus[sd].headState[head].cursor.y); + + headCount++; } } diff --git a/src/nvidia-modeset/src/nvkms-dpy.c b/src/nvidia-modeset/src/nvkms-dpy.c index e4f1b983dc..34e1ded898 100644 --- a/src/nvidia-modeset/src/nvkms-dpy.c +++ b/src/nvidia-modeset/src/nvkms-dpy.c @@ -654,7 +654,7 @@ void nvDpyProbeMaxPixelClock(NVDpyEvoPtr pDpyEvo) if (pDevEvo->gpus != NULL) { NVEvoSorCaps *sorCaps = pDevEvo->gpus[displayOwner].capabilities.sor; - NvU32 orIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + NvU32 orIndex = pConnectorEvo->or.primary; if (NV0073_CTRL_SYSTEM_GET_CAP(pDevEvo->commonCapsBits, NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED)) { @@ -682,7 +682,10 @@ void nvDpyProbeMaxPixelClock(NVDpyEvoPtr pDpyEvo) * those driving heads, we don't need to exclude RM from * selecting any SOR, so an sorExcludeMask of 0 is appropriate. */ - if (nvAssignSOREvo(pConnectorEvo, 0) && + if (nvAssignSOREvo(pDispEvo, + nvDpyIdToNvU32(pConnectorEvo->displayId), + FALSE /* b2Heads1Or */, + 0 /* sorExcludeMask */) && nvHdmiFrlAssessLink(pDpyEvo)) { /* * Note that although we "assessed" the link above, the @@ -1438,6 +1441,11 @@ static void LogEdid(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString) case NVT_TYPE_DISPLAYID_9: case NVT_TYPE_DISPLAYID_10: case NVT_TYPE_CVT_RB_3: + /* + * XXX temporarily disable the warning so that additional + * NVT_TYPEs_ can be added to nvtiming.h. Bug 3849339. + */ + default: break; } break; @@ -2893,6 +2901,7 @@ void nvDpyUpdateCurrentAttributes(NVDpyEvoRec *pDpyEvo) newAttributes.dithering.mode = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE; newAttributes.digitalSignal = nvGetDefaultDpyAttributeDigitalSignalValue(pDpyEvo->pConnectorEvo); + newAttributes.numberOfHardwareHeadsUsed = 0; } if (newAttributes.colorSpace != @@ -2951,19 +2960,53 @@ void nvDpyUpdateCurrentAttributes(NVDpyEvoRec *pDpyEvo) newAttributes.digitalSignal); } + if (newAttributes.numberOfHardwareHeadsUsed != + pDpyEvo->currentAttributes.numberOfHardwareHeadsUsed) { + nvSendDpyAttributeChangedEventEvo( + pDpyEvo, + NV_KMS_DPY_ATTRIBUTE_NUMBER_OF_HARDWARE_HEADS_USED, + newAttributes.numberOfHardwareHeadsUsed); + } + pDpyEvo->currentAttributes = newAttributes; } // Returns TRUE if this display is capable of Adaptive-Sync NvBool nvDpyIsAdaptiveSync(const NVDpyEvoRec *pDpyEvo) { - return FALSE; + return ((pDpyEvo->vrr.type == + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED) || + (pDpyEvo->vrr.type == + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED)); } // Returns TRUE if this display is in the Adaptive-Sync defaultlist NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVDpyEvoRec *pDpyEvo) { - return FALSE; + NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS params = { }; + NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 ret; + + if (!pDpyEvo->parsedEdid.valid) { + return FALSE; + } + + params.manufacturerID = pDpyEvo->parsedEdid.info.manuf_id; + params.productID = pDpyEvo->parsedEdid.info.product_id; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY, + ¶ms, sizeof(params)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, + "Failed to query default adaptivesync listing for %s", pDpyEvo->name); + return FALSE; + } + + return params.bDefaultAdaptivesync; } static enum NvKmsDpyAttributeColorBpcValue GetYuv422MaxBpc( @@ -3077,3 +3120,34 @@ NVColorFormatInfoRec nvGetColorFormatInfo(const NVDpyEvoRec *pDpyEvo) return colorFormatsInfo; } + +NvU32 nvDpyGetPossibleApiHeadsMask(const NVDpyEvoRec *pDpyEvo) +{ + NvU32 possibleApiHeadMask = 0x0; + NvU32 possibleNumLayers = NVKMS_MAX_LAYERS_PER_HEAD; + const NVDevEvoRec *pDevEvo = pDpyEvo->pDispEvo->pDevEvo; + + /* + * DSI supports only the hardware head-0 assigment, and the + * dp-serializer dpys are bound to the specific hardware head; + * the modeset client can be allowed to choose only those + * api-heads to drive these dpys which has the number of layers + * less than or equal to the number of layers supported by the + * bound hardware heads. + */ + if (pDpyEvo->pConnectorEvo->signalFormat == + NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { + possibleNumLayers = pDevEvo->head[0].numLayers; + } else if (nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)) { + const NvU32 boundHead = pDpyEvo->dp.serializerStreamIndex; + possibleNumLayers = pDevEvo->head[boundHead].numLayers; + } + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (pDevEvo->apiHead[apiHead].numLayers <= possibleNumLayers) { + possibleApiHeadMask |= NVBIT(apiHead); + } + } + + return possibleApiHeadMask; +} diff --git a/src/nvidia-modeset/src/nvkms-evo.c b/src/nvidia-modeset/src/nvkms-evo.c index 8720446c20..3f7a1db5e0 100644 --- a/src/nvidia-modeset/src/nvkms-evo.c +++ b/src/nvidia-modeset/src/nvkms-evo.c @@ -25,6 +25,7 @@ #include "nvkms-evo-states.h" #include "dp/nvdp-connector.h" +#include "dp/nvdp-device.h" #include "nvkms-console-restore.h" #include "nvkms-rm.h" #include "nvkms-dpy.h" @@ -80,13 +81,29 @@ /* * This struct is used to describe a single set of GPUs to lock together by * GetRasterLockTopologies(). - * It is initialized to pDispEvoOrder[i] == NULL, and when filled in NULL is - * used as a terminator. */ -typedef struct { +typedef struct _NVEvoRasterLockTopology { + NvU32 numDisps; NVDispEvoPtr pDispEvoOrder[NVKMS_MAX_SUBDEVICES]; } RasterLockTopology; +/* + * These are used hold additional state for each DispEvo during building of + * topologies. + */ +typedef struct +{ + NVDispEvoPtr pDispEvo; + NvU32 gpuId; + RasterLockTopology *topo; +} DispEntry; + +typedef struct +{ + /* Array of DispEvos and their assigned topologies. */ + NvU32 numDisps; + DispEntry disps[NVKMS_MAX_SUBDEVICES]; +} DispEvoList; static void EvoSetViewportPointIn(NVDispEvoPtr pDispEvo, NvU32 head, NvU16 x, NvU16 y, @@ -94,8 +111,9 @@ static void EvoSetViewportPointIn(NVDispEvoPtr pDispEvo, NvU32 head, static void GetRasterLockPin(NVDispEvoPtr pDispEvo0, NvU32 head0, NVDispEvoPtr pDispEvo1, NvU32 head1, NVEvoLockPin *serverPin, NVEvoLockPin *clientPin); -static NvBool EvoWaitForLock(NVDevEvoPtr pDevEvo, - NvU32 sd, NvU32 head, NvU32 type); +static NvBool EvoWaitForLock(const NVDevEvoRec *pDevEvo, const NvU32 sd, + const NvU32 head, const NvU32 type, + NvU64 *pStartTime); static void EvoUpdateHeadParams(const NVDispEvoRec *pDispEvo, NvU32 head, NVEvoUpdateState *updateState); @@ -123,6 +141,8 @@ NVEvoGlobal nvEvoGlobal = { .debugMemoryAllocationList = NV_LIST_INIT(&nvEvoGlobal.debugMemoryAllocationList), #endif /* DEBUG */ + .globalTopologies = NULL, + .numGlobalTopos = 0 }; /* @@ -248,10 +268,19 @@ void nvEvoDetachConnector(NVConnectorEvoRec *pConnectorEvo, const NvU32 head, const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - const NvU32 orIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + NvU32 orIndex; - nvAssert(orIndex != NV_INVALID_OR); - nvAssert(pConnectorEvo->or.ownerHeadMask[orIndex] & NVBIT(head)); + for (orIndex = 0; + orIndex < ARRAY_LEN(pConnectorEvo->or.ownerHeadMask); orIndex++) { + if ((pConnectorEvo->or.ownerHeadMask[orIndex] & NVBIT(head)) != 0x0) { + break; + } + } + + if (orIndex >= ARRAY_LEN(pConnectorEvo->or.ownerHeadMask)) { + nvAssert(!"Not found attached OR"); + return; + } pConnectorEvo->or.ownerHeadMask[orIndex] &= ~NVBIT(head); @@ -280,8 +309,35 @@ void nvEvoDetachConnector(NVConnectorEvoRec *pConnectorEvo, const NvU32 head, pModesetUpdateState->connectorIds); } +static +NvU32 GetSorIndexToAttachConnector(const NVConnectorEvoRec *pConnectorEvo, + const NvBool isPrimaryHead) +{ + NvU32 orIndex = NV_INVALID_OR; + + nvAssert(isPrimaryHead || + (pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR)); + + if (isPrimaryHead || + (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR)) { + orIndex = pConnectorEvo->or.primary; + } else { + NvU32 i; + + FOR_EACH_INDEX_IN_MASK(32, i, pConnectorEvo->or.secondaryMask) { + if (pConnectorEvo->or.ownerHeadMask[i] == 0x0) { + orIndex = i; + break; + } + } FOR_EACH_INDEX_IN_MASK_END; + } + + return orIndex; +} + void nvEvoAttachConnector(NVConnectorEvoRec *pConnectorEvo, const NvU32 head, + const NvU32 isPrimaryHead, NVDPLibModesetStatePtr pDpLibModesetState, NVEvoModesetUpdateState *pModesetUpdateState) { @@ -290,7 +346,8 @@ void nvEvoAttachConnector(NVConnectorEvoRec *pConnectorEvo, const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - const NvU32 orIndex = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + NvU32 orIndex = + GetSorIndexToAttachConnector(pConnectorEvo, isPrimaryHead); NvU32 i; nvAssert(orIndex != NV_INVALID_OR); @@ -783,6 +840,15 @@ static void SetOverscanColor(NVEvoColorPtr pOverscanColor, NvBool yuv420) #endif } +void nvEvoDisableHwYUV420Packer(const NVDispEvoRec *pDispEvo, + const NvU32 head, + NVEvoUpdateState *pUpdateState) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + pDevEvo->gpus[pDispEvo->displayOwner].headControl[head].hwYuv420 = FALSE; + EvoUpdateHeadParams(pDispEvo, head, pUpdateState); +} + /* * Send the raster timings for the pDpyEvo to EVO. */ @@ -793,6 +859,7 @@ void nvEvoSetTimings(NVDispEvoPtr pDispEvo, NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + const NVDscInfoEvoRec *pDscInfo = &pHeadState->dscInfo; const enum nvKmsPixelDepth pixelDepth = pHeadState->pixelDepth; NVEvoColorRec overscanColor; @@ -801,7 +868,8 @@ void nvEvoSetTimings(NVDispEvoPtr pDispEvo, NV_YUV420_MODE_SW)); pDevEvo->hal->SetRasterParams(pDevEvo, head, - pTimings, &overscanColor, updateState); + pTimings, pHeadState->tilePosition, + pDscInfo, &overscanColor, updateState); // Set the head parameters pDevEvo->gpus[pDispEvo->displayOwner].headControl[head].interlaced = @@ -817,15 +885,14 @@ void nvEvoSetTimings(NVDispEvoPtr pDispEvo, * the HDMI library. */ nvAssert(!((pTimings->yuv420Mode == NV_YUV420_MODE_HW) && - (pTimings->dpDsc.enable || - pTimings->hdmiFrlConfig.dscInfo.bEnableDSC))); + (pDscInfo->type != NV_DSC_INFO_EVO_TYPE_DISABLED))); pDevEvo->gpus[pDispEvo->displayOwner].headControl[head].hwYuv420 = (pTimings->yuv420Mode == NV_YUV420_MODE_HW); EvoUpdateHeadParams(pDispEvo, head, updateState); - pDevEvo->hal->SetDscParams(pDispEvo, head, pTimings, pixelDepth); + pDevEvo->hal->SetDscParams(pDispEvo, head, pDscInfo, pixelDepth); nvPopEvoSubDevMask(pDevEvo); } @@ -837,11 +904,11 @@ void nvEvoSetTimings(NVDispEvoPtr pDispEvo, * This involves incrementing *numTopologies, reallocating the topos array, and * initializing the new entry. */ -static RasterLockTopology *growTopologies(RasterLockTopology *topos, +static RasterLockTopology *GrowTopologies(RasterLockTopology *topos, unsigned int *numTopologies) { RasterLockTopology *newTopos, *topo; - unsigned int i, numTopos; + unsigned int numTopos; numTopos = *numTopologies; @@ -849,26 +916,290 @@ static RasterLockTopology *growTopologies(RasterLockTopology *topos, newTopos = nvRealloc(topos, numTopos * sizeof(RasterLockTopology)); if (!newTopos) { nvFree(topos); + *numTopologies = 0; return NULL; } topo = &newTopos[numTopos - 1]; - - for (i = 0; i < NVKMS_MAX_SUBDEVICES; i++) { - topo->pDispEvoOrder[i] = NULL; - } + topo->numDisps = 0; *numTopologies = numTopos; return newTopos; -} /* growTopologies() */ +} /* GrowTopologies() */ + +static RasterLockTopology *CopyAndAppendTopology(RasterLockTopology *topos, + unsigned int *numTopos, + const RasterLockTopology *source) +{ + RasterLockTopology *dest; + + topos = GrowTopologies(topos, numTopos); + if (topos) { + dest = &topos[*numTopos - 1]; + nvkms_memcpy(dest, source, sizeof(RasterLockTopology)); + } + + return topos; +} + +static void AddDispEvoIntoTopology(RasterLockTopology *topo, NVDispEvoPtr pDispEvo) +{ + NvU32 i; + + /* + * The extent of a topology is the largest number of GPUs that can be + * linked together. + */ + nvAssert(topo->numDisps < NVKMS_MAX_SUBDEVICES); + + /* Caller should keep track of not adding duplicate entries. */ + for (i = 0; i < topo->numDisps; i++) { + nvAssert(topo->pDispEvoOrder[i] != pDispEvo); + } + + /* Add to the end of the array. */ + topo->pDispEvoOrder[topo->numDisps] = pDispEvo; + topo->numDisps++; +} + +static const RasterLockTopology *FindTopologyForDispEvo( + const RasterLockTopology *topos, + unsigned int numTopologies, + const NVDispEvoPtr pDispEvo) +{ + const RasterLockTopology *topo; + NvU32 i; + + for (topo = topos; topo < topos + numTopologies; topo++) { + for (i = 0; i < topo->numDisps; i++) { + if (topo->pDispEvoOrder[i] == pDispEvo) { + return topo; + } + } + } + + return NULL; +} + +static DispEntry *DispEvoListFindDispByGpuId (DispEvoList *list, NvU32 gpuId) +{ + NvU32 i; + + for (i = 0; i < list->numDisps; i++) { + if (list->disps[i].gpuId == gpuId) { + return &list->disps[i]; + } + } + + return NULL; +} + +static void DispEvoListInit(DispEvoList *list) +{ + list->numDisps = 0; +} + +static void DispEvoListAppend(DispEvoList *list, NVDispEvoPtr pDispEvo) +{ + nvAssert(DispEvoListFindDispByGpuId( + list, nvGpuIdOfDispEvo(pDispEvo)) == NULL); + + nvAssert(list->numDisps < ARRAY_LEN(list->disps)); + list->disps[list->numDisps].pDispEvo = pDispEvo; + list->disps[list->numDisps].gpuId = nvGpuIdOfDispEvo(pDispEvo); + list->disps[list->numDisps].topo = NULL; + list->numDisps++; +} + +/* + * Helper function to look up, for a gpuId, the list of connected GPUs in + * NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS. + */ +static NV0000_CTRL_GPU_VIDEO_LINKS *FindLinksForGpuId( + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *vidLinksParams, + NvU32 gpuId) +{ + NvU32 i; + + for (i = 0; i < NV0000_CTRL_GPU_MAX_ATTACHED_GPUS; i++) { + if (vidLinksParams->links[i].gpuId == NV0000_CTRL_GPU_INVALID_ID) { + break; + } + + if (vidLinksParams->links[i].gpuId == gpuId) { + return &vidLinksParams->links[i]; + } + } + + return NULL; +} + +static void BuildTopologyFromVideoLinks(DispEvoList *list, + RasterLockTopology *topo, + NvU32 gpuId, + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *vidLinksParams) +{ + DispEntry *dispEntry; + NV0000_CTRL_GPU_VIDEO_LINKS *links; + NvU32 i; + + /* Find the correct DispEntry for the gpuId. If we can't find one the + * gpuId must be pointing to a DevEvo that was not listed in our + * DevEvoList: ignore these links at this point. */ + dispEntry = DispEvoListFindDispByGpuId(list, gpuId); + if (!dispEntry) { + return; + } + + /* + * Unless we've seen this gpuId already add into current topology and + * try to discover bridged GPUs. + */ + if (!dispEntry->topo) { + /* Assign in the current topology. */ + AddDispEvoIntoTopology(topo, dispEntry->pDispEvo); + dispEntry->topo = topo; + + /* First, get the links for this gpuId. */ + links = FindLinksForGpuId(vidLinksParams, gpuId); + + /* Recurse into connected GPUs. */ + if (links) { + for (i = 0; i < NV0000_CTRL_GPU_MAX_VIDEO_LINKS; i++) { + if (links->connectedGpuIds[i] == NV0000_CTRL_GPU_INVALID_ID) { + break; + } + + BuildTopologyFromVideoLinks(list, + topo, + links->connectedGpuIds[i], + vidLinksParams); + } + } + } +} + +/* + * Stateless (RM SLI/client SLI agnostic) discovery of bridged GPUs: build + * topologies for all non-RM SLI devices based on the found GPU links. + * + * This function and BuildTopologyFromVideoLinks() implement a simple + * algorithm that puts clusters of bridged GPUs into distinct topologies. + * Here's an outline of how we basically generate the final topologies: + * + * 1. Create a DispEvoList array to hold topology state for all the DispEvo + * objects in the system. + * + * 2. Query RM for an array of video links for each GPU. + * + * 3. As long as the DispEvoList contains DispEvos of the given pDevEvo + * without a topology, find the first occurrence of such, create a new + * topology, and populate it by recursively adding the DispEvo and all + * its connected DispEvos into the new topology. + * + * 4. Once all known DispEvos are assigned the result will be a list of + * global RasterLockTopologies, each of which hosts DispEvos that are + * connected together. + * + * The result of this function should be cached once and later used to + * cheaply look up the appropriate, immutable topology for a DispEvo. + * + */ +static RasterLockTopology *GetGpuTopologyStateless(unsigned int *numTopologies) +{ + RasterLockTopology *topos = NULL; + RasterLockTopology *topo; + DispEvoList evoList; + NVDevEvoPtr pCurDev; + NVDispEvoPtr pCurDisp; + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *vidLinksParams; + NvU32 sd; + NvU32 i; + + DispEvoListInit(&evoList); + + /* + * First create an array of DispEntries to hold some state for all the + * DispEvos in the system. + */ + FOR_ALL_EVO_DEVS(pCurDev) { + /* + * Only include non RM SLI devices so as to not clash with multi-GPU + * RM SLI devices. + */ + if (pCurDev->numSubDevices == 1) { + FOR_ALL_EVO_DISPLAYS(pCurDisp, sd, pCurDev) { + DispEvoListAppend(&evoList, pCurDisp); + } + } + } + + /* + * Ask RM about the currently known video links. + */ + vidLinksParams = nvCalloc(1, sizeof(*vidLinksParams)); + if (!vidLinksParams) { + return NULL; + } + + if (nvRmApiControl(nvEvoGlobal.clientHandle, + nvEvoGlobal.clientHandle, + NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS, + vidLinksParams, + sizeof(*vidLinksParams)) == NVOS_STATUS_SUCCESS) { + + for (i = 0; i < evoList.numDisps; i++) { + /* + * Create a new topology starting from the first DispEvo not yet + * assigned into a topology, and all GPUs possibly reachable + * from it through bridges. + * + * TODO: Consider if we should only ever start a new topology + * with a GPU that has only one connection and not two. Then the + * topology's pDispEvoOrder would always start from a "leaf" GPU + * of a linkage graph. But will the GPU links always be linear + * and non-branching? NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS + * makes it possible to represent GPUs with any number of links. + * Either FinishModesetOneTopology() must be able to handle that + * (in which case this is not a concern) or we must be able to + * trust that only 0-2 links will be reported per GPU. + */ + if (evoList.disps[i].topo) { + continue; + } + + topos = GrowTopologies(topos, numTopologies); + if (!topos) { + nvFree(vidLinksParams); + return NULL; + } + + topo = &topos[*numTopologies - 1]; + + BuildTopologyFromVideoLinks(&evoList, + topo, + evoList.disps[i].gpuId, + vidLinksParams); + } + + nvFree(vidLinksParams); + nvAssert(*numTopologies > 0); + return topos; + } + + nvFree(vidLinksParams); + nvFree(topos); + return NULL; +} /* * GetRasterLockTopologies() - Determine which GPUs to consider for locking (or * unlocking) displays. This is one of the following: * 1. SLI video bridge order, if SLI is enabled; - * 2. A single GPU, + * 2. GPUs linked through rasterlock pins, no SLI (like in clientSLI); + * 3. A single GPU, * in that order. * * Note that we still go through the same codepaths for the last degenerate @@ -901,7 +1232,7 @@ static RasterLockTopology *GetRasterLockTopologies(NVDevEvoPtr pDevEvo, if (params.ConnectionCount > 0) { RasterLockTopology *topo; - topos = growTopologies(topos, numTopologies); + topos = GrowTopologies(topos, numTopologies); if (!topos) { return NULL; @@ -927,28 +1258,64 @@ static RasterLockTopology *GetRasterLockTopologies(NVDevEvoPtr pDevEvo, nvAssert(pDevEvo->pDispEvo[sd] != NULL); /* SLI Mosaic. */ - topo->pDispEvoOrder[i] = pDevEvo->pDispEvo[sd]; + AddDispEvoIntoTopology(topo, pDevEvo->pDispEvo[sd]); } } - } else { - /* Single GPU or bridgeless SLI */ - NVDispEvoPtr pDispEvo; - unsigned int sd; + if (*numTopologies > 0) { + return topos; + } + } - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + /* + * Client SLI: Create a RasterLockTopology from pDevEvo's only DispEvo + * and other DispEvos potentially bridged to that. + */ - RasterLockTopology *topo; - topos = growTopologies(topos, numTopologies); + if (pDevEvo->numSubDevices == 1) { + /* Get-or-create cached rasterlock topology for this device. */ + if (!nvEvoGlobal.globalTopologies) { + nvEvoGlobal.globalTopologies = + GetGpuTopologyStateless(&nvEvoGlobal.numGlobalTopos); + } - if (!topos) { - return NULL; + /* Look for a cached topo containing this device's DispEvo. */ + if (nvEvoGlobal.globalTopologies && nvEvoGlobal.numGlobalTopos > 0) { + const RasterLockTopology *foundTopo = + FindTopologyForDispEvo(nvEvoGlobal.globalTopologies, + nvEvoGlobal.numGlobalTopos, + pDevEvo->pDispEvo[0]); + + /* Make a copy of it and add to 'topos'. */ + if (foundTopo) { + topos = CopyAndAppendTopology(topos, numTopologies, foundTopo); } + } - topo = &topos[*numTopologies - 1]; + if (*numTopologies > 0) { + return topos; + } + } + + /* + * Single GPU or bridgeless SLI. We create a topology for each + * individual DispEvo. + */ - topo->pDispEvoOrder[0] = pDispEvo; + NVDispEvoPtr pDispEvo; + unsigned int sd; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + RasterLockTopology *topo; + topos = GrowTopologies(topos, numTopologies); + + if (!topos) { + return NULL; } + + topo = &topos[*numTopologies - 1]; + + AddDispEvoIntoTopology(topo, pDispEvo); } return topos; @@ -1056,13 +1423,9 @@ static void UnlockRasterLockGroup(NVDevEvoPtr pDevEvo) { } for (topo = topos; topo < topos + numTopos; topo++) { - int maxDisps = 0, i; - - for (i = 0; i < NVKMS_MAX_SUBDEVICES && topo->pDispEvoOrder[i]; i++) { - maxDisps = i; - } + int i; - for (i = maxDisps; i >= 0; i--) { + for (i = (int)topo->numDisps - 1; i >= 0; i--) { NVDispEvoPtr pDispEvo = topo->pDispEvoOrder[i]; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 sd = pDispEvo->displayOwner; @@ -1251,6 +1614,55 @@ void nvEvoUpdateSliVideoBridge(NVDevEvoPtr pDevEvo) pDevEvo->sli.bridge.powered = enable; } +void nvEvoLockStateSetMergeMode(NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; + NvU32 activeHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; + NvU32 mergeModeHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; + NvU32 numMergeModeHeads = 0; + NvU32 numActiveHeads = 0; + NvBool needUpdate = FALSE; + + for (NvU32 head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + if (nvHeadIsActive(pDispEvo, head)) { + if (pDispEvo->headState[head].mergeMode != + NV_EVO_MERGE_MODE_DISABLED) { + mergeModeHeads[numMergeModeHeads++] = head; + } + activeHeads[numActiveHeads++] = head; + } + } + mergeModeHeads[numMergeModeHeads] = NV_INVALID_HEAD; + activeHeads[numActiveHeads] = NV_INVALID_HEAD; + + SyncEvoLockState(); + + if (pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, + NV_EVO_DISABLE_MERGE_MODE, NULL)) { + pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, + NV_EVO_DISABLE_MERGE_MODE, activeHeads); + needUpdate = TRUE; + } + + if (numMergeModeHeads > 0) { + nvAssert(pDevEvo->hal->caps.supportsMergeMode); + if (pEvoSubDev->scanLockState(pDispEvo, + pEvoSubDev, + NV_EVO_ENABLE_MERGE_MODE, + mergeModeHeads)) { + needUpdate = TRUE; + } else { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, + "Failed to enable lock state merge mode"); + } + } + + if (needUpdate) { + UpdateEvoLockState(); + } +} + /* * FinishModesetOneTopology() - Set up raster lock between GPUs, if applicable, * for one RasterLockTopology. Called in a loop from nvFinishModesetEvo(). @@ -1267,12 +1679,17 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) NvBool flipLockPossible = TRUE; unsigned int i, j; NvU8 allowFlipLockGroup = 0; + NVDevEvoPtr pDevEvoFlipLockGroup = NULL; + NvBool mergeModeInUse = FALSE; /* - * First, look for devices with VRR enabled. If we find any, go into the - * special VRR framelock mode and don't try to rasterlock any other heads. + * First, look for devices with VRR enabled. If we find any, go into the + * special VRR framelock mode. + * + * If we find devices with VRR or merge mode enabled, don't try to + * rasterlock any other heads. */ - for (i = 0; i < NVKMS_MAX_SUBDEVICES && pDispEvoOrder[i]; i++) { + for (i = 0; i < topo->numDisps; i++) { NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; NvU32 sd = pDispEvo->displayOwner; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -1280,7 +1697,20 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) unsigned int numVrrHeads = 0; NvU32 head; - if (!pDevEvo->gpus || !pDevEvo->vrr.enabled) { + if (!pDevEvo->gpus) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + if (nvHeadIsActive(pDispEvo, head)) { + if (pDispEvo->headState[head].mergeMode != + NV_EVO_MERGE_MODE_DISABLED) { + mergeModeInUse = TRUE; + } + } + } + + if (!pDevEvo->vrr.enabled) { continue; } @@ -1300,7 +1730,7 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) } } - if (vrrInUse) { + if (vrrInUse || mergeModeInUse) { return; } @@ -1311,7 +1741,7 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) * use. For now, only attempt locking if all heads on the device have * compatible timings and consecutive in the video bridge order. */ - for (i = 0; i < NVKMS_MAX_SUBDEVICES && pDispEvoOrder[i]; i++) { + for (i = 0; i < topo->numDisps; i++) { NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 head; @@ -1351,10 +1781,16 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) /* * Only flip lock if all of the heads are in the same * allowFlipLockGroup. + * + * Also, for now, only allow fliplocking if all heads are on + * GPUs with the same pDevEvo (i.e., single GPU or RM-linked + * SLI). */ if (allowFlipLockGroup == 0) { allowFlipLockGroup = pHeadState->allowFlipLockGroup; - } else if (allowFlipLockGroup != pHeadState->allowFlipLockGroup) { + pDevEvoFlipLockGroup = pDevEvo; + } else if (allowFlipLockGroup != pHeadState->allowFlipLockGroup || + pDevEvoFlipLockGroup != pDevEvo) { flipLockPossible = FALSE; } @@ -1383,7 +1819,7 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) * Finally, actually set up locking: go through the video bridge order * setting it up. */ - for (i = 0; i < NVKMS_MAX_SUBDEVICES && pDispEvoOrder[i]; i++) { + for (i = 0; i < topo->numDisps; i++) { NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; NvU32 sd = pDispEvo->displayOwner; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -1544,6 +1980,7 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) for (j = 0; j < usedHeads; j++) { NvU32 tmpHead = head[j]; + NvU64 startTime = 0; NVEvoLockPin pin = nvEvoGetPinForSignal(pDispEvo, &pDevEvo->gpus[sd], @@ -1551,7 +1988,8 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) /* Wait for the raster lock to sync in.. */ if (pin == NV_EVO_LOCK_PIN_ERROR || - !EvoWaitForLock(pDevEvo, sd, tmpHead, EVO_RASTER_LOCK)) { + !EvoWaitForLock(pDevEvo, sd, tmpHead, EVO_RASTER_LOCK, + &startTime)) { flipLockPossible = FALSE; break; } @@ -1586,8 +2024,10 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) * flips in the base channel. */ for (j = 0; j < usedHeads; j++) { + NvU64 startTime = 0; if (flipLockPossible && - !EvoWaitForLock(pDevEvo, sd, head[j], EVO_FLIP_LOCK)) { + !EvoWaitForLock(pDevEvo, sd, head[j], EVO_FLIP_LOCK, + &startTime)) { flipLockPossible = FALSE; break; } @@ -2178,7 +2618,7 @@ static NvBool HeadCanStereoLock(NVDevEvoPtr pDevEvo, int sd, int head) { NVEvoHeadControlPtr pHC = &pDevEvo->gpus[sd].headControlAssy[head]; - return (!pHC->interlaced && + return (!pHC->interlaced && !pHC->mergeMode && ((pHC->serverLock != NV_EVO_NO_LOCK) || (pHC->clientLock != NV_EVO_NO_LOCK))); } @@ -3094,6 +3534,16 @@ NvBool nvQueryRasterLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *val) return TRUE; } +void nvInvalidateTopologiesEvo(void) +{ + if (nvEvoGlobal.globalTopologies) { + nvFree(nvEvoGlobal.globalTopologies); + + nvEvoGlobal.globalTopologies = NULL; + nvEvoGlobal.numGlobalTopos = 0; + } +} + /* * Return the surface format usage bounds that NVKMS will program for the * requested format. @@ -3165,6 +3615,14 @@ NvBool nvUpdateFlipLockEvoOneHead(NVDispEvoPtr pDispEvo, const NvU32 head, NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; + /* + * XXX: [2Heads1OR] If head is locked in the merge mode then its flip-lock + * state can not be changed. + */ + if (pHC->mergeMode) { + return FALSE; + } + if (needsEarlyUpdate) { *needsEarlyUpdate = FALSE; } @@ -3301,9 +3759,12 @@ static void ProhibitFlipLock50(NVDispEvoPtr pDispEvo) NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - NVEvoHeadControlPtr pHC = NULL; - - if (!nvHeadIsActive(pDispEvo, head)) { + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; + /* + * XXX: [2Heads1OR] If head is locked in the merge mode then its flip-lock + * state can not be changed. + */ + if (!nvHeadIsActive(pDispEvo, head) || pHC->mergeMode) { continue; } @@ -3314,8 +3775,6 @@ static void ProhibitFlipLock50(NVDispEvoPtr pDispEvo) continue; } - pHC = &pEvoSubDev->headControl[head]; - if (pHC->flipLock) { needUpdate = TRUE; @@ -3342,14 +3801,16 @@ static void AllowFlipLock50(NVDispEvoPtr pDispEvo) NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - NVEvoHeadControlPtr pHC = NULL; + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; - if (!nvHeadIsActive(pDispEvo, head)) { + /* + * XXX: [2Heads1OR] If head is locked in the merge mode then its flip-lock + * state can not be changed. + */ + if (!nvHeadIsActive(pDispEvo, head) || pHC->mergeMode) { continue; } - pHC = &pEvoSubDev->headControl[head]; - if (!pHC->flipLock && HEAD_MASK_QUERY(pEvoSubDev->flipLockEnabledForSliHeadMask, head)) { @@ -3656,13 +4117,46 @@ static NvBool ValidateConnectorTypes(const NVDevEvoRec *pDevEvo) return TRUE; } +static void UnregisterFlipOccurredEventOneHead(NVDispEvoRec *pDispEvo, + const NvU32 head) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 layer; + + /* XXX NVKMS TODO: need disp-scope in event */ + if (pDispEvo->displayOwner != 0) { + return; + } + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; + + nvAssert((pChannel->completionNotifierEventHandle == 0) || + (pChannel->completionNotifierEventRefPtr != NULL)); + + if (pChannel->completionNotifierEventHandle != 0) { + nvRmApiFree(nvEvoGlobal.clientHandle, + pChannel->pb.channel_handle, + pChannel->completionNotifierEventHandle); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pChannel->completionNotifierEventHandle); + pChannel->completionNotifierEventHandle = 0; + pChannel->completionNotifierEventRefPtr = NULL; + } + } +} + static void ClearApiHeadStateOneDisp(NVDispEvoRec *pDispEvo) { NvU32 apiHead; - NVConnectorEvoRec *pConnectorEvo; - FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { - pConnectorEvo->validApiHeadMask = 0x0; + /* + * Unregister all the flip-occurred event callbacks which are + * registered with the (api-head, layer) pair event data, + * before destroying the api-head states. + */ + for (NvU32 head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + UnregisterFlipOccurredEventOneHead(pDispEvo, head); } for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->apiHeadState); apiHead++) { @@ -3681,57 +4175,13 @@ static void ClearApiHeadStateOneDisp(NVDispEvoRec *pDispEvo) nvkms_memset(pDispEvo->apiHeadState, 0, sizeof(pDispEvo->apiHeadState)); } -static void UnRegisterFlipOccurredEventOneApiHead(NVDevEvoRec *pDevEvo, - const NvU32 apiHead) -{ - const NvU32 dispIndex = 0; /* XXX NVKMS TODO: need disp-scope in event */ - NVDispEvoRec *pDispEvo = pDevEvo->pDispEvo[dispIndex]; - NvU32 layer; - NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); - - if (head == NV_INVALID_HEAD) { - /* This can happen if nvAllocCoreChannelEvo() fails and leaves things - * in a partially-initialized state and nvFreeCoreChannelEvo() is - * called to clean up. */ - return; - } - - /* - * pDevEvo->apiHead[apiHead].numLayers is the number of layer which is - * visible to nvkms clients, and that number should be less than equal to - * pDevEvo->head[head].numLayers. - * - * If (pDevEvo->head[head].numLayers > pDevEvo->apiHead[apiHead].numLayers) - * then the extra per hardware-head layers remains unused and there is no - * need to register the completion notifier callback for those extra per - * hardware-head layers. - */ - nvAssert(pDevEvo->head[head].numLayers >= - pDevEvo->apiHead[apiHead].numLayers); - - for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { - NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; - - if (pChannel->completionNotifierEventHandle != 0) { - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, - pChannel->completionNotifierEventHandle); - pChannel->completionNotifierEventHandle = 0; - } - } -} - static void ClearApiHeadState(NVDevEvoRec *pDevEvo) { - NvU32 apiHead; NvU32 dispIndex; NVDispEvoRec *pDispEvo; nvRmFreeCoreRGSyncpts(pDevEvo); - for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - UnRegisterFlipOccurredEventOneApiHead(pDevEvo, apiHead); - } - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { ClearApiHeadStateOneDisp(pDispEvo); } @@ -3739,16 +4189,19 @@ static void ClearApiHeadState(NVDevEvoRec *pDevEvo) nvkms_memset(pDevEvo->apiHead, 0, sizeof(pDevEvo->apiHead)); } -static NvBool InitApiHeadStateOnceDisp(NVDispEvoRec *pDispEvo) +static NvBool InitApiHeadStateOneDisp(NVDispEvoRec *pDispEvo) { - NvU32 apiHead; - NVConnectorEvoRec *pConnectorEvo; + NvU32 usedApiHeadsMask = 0x0; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; - for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->apiHeadState); apiHead++) { + for (NvU32 apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->apiHeadState); apiHead++) { NvU32 layer; NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + pApiHeadState->activeDpys = nvEmptyDpyIdList(); + pApiHeadState->attributes = NV_EVO_DEFAULT_ATTRIBUTES_SET; + nvListInit(&pApiHeadState->vblankCallbackList); for (layer = 0; layer < ARRAY_LEN(pApiHeadState->flipOccurredEvent); layer++) { @@ -3767,17 +4220,26 @@ static NvBool InitApiHeadStateOnceDisp(NVDispEvoRec *pDispEvo) } } - for (NvU32 head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NvU32 apiHead = nvHardwareHeadToApiHead(pDispEvo->pDevEvo, head); - - pDispEvo->apiHeadState[apiHead].hwHeadsMask = NVBIT(head); - pDispEvo->apiHeadState[apiHead].attributes = - NV_EVO_DEFAULT_ATTRIBUTES_SET; - + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { if (pDispEvo->headState[head].pConnectorEvo != NULL) { + NvU32 apiHead; const NVConnectorEvoRec *pConnectorEvo = pDispEvo->headState[head].pConnectorEvo; + /* Find unused api-head which support the equal number of layers */ + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if ((NVBIT(apiHead) & usedApiHeadsMask) != 0x0) { + continue; + } + + if (pDevEvo->apiHead[apiHead].numLayers == + pDevEvo->head[head].numLayers) { + usedApiHeadsMask |= NVBIT(apiHead); + break; + } + } + nvAssert(apiHead < pDevEvo->numApiHeads); + /* * Use the pDpyEvo for the connector, since we may not have one * for display id if it's a dynamic one. @@ -3788,19 +4250,11 @@ static NvBool InitApiHeadStateOnceDisp(NVDispEvoRec *pDispEvo) nvAssert(pDpyEvo->apiHead == NV_INVALID_HEAD); pDpyEvo->apiHead = apiHead; + nvAssignHwHeadsMaskApiHeadState( + &pDispEvo->apiHeadState[apiHead], + NVBIT(head)); pDispEvo->apiHeadState[apiHead].activeDpys = nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId); - } else { - pDispEvo->apiHeadState[apiHead].activeDpys = nvEmptyDpyIdList(); - } - } - - FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { - NvU32 head; - pConnectorEvo->validApiHeadMask = 0x0; - FOR_EACH_EVO_HW_HEAD_IN_MASK(pConnectorEvo->validHeadMask, head) { - NvU32 apiHead = nvHardwareHeadToApiHead(pDispEvo->pDevEvo, head); - pConnectorEvo->validApiHeadMask |= NVBIT(apiHead); } } @@ -3831,38 +4285,39 @@ static void CompletionNotifierEvent(void *arg, void *pEventDataVoid, 0); /* timeout: schedule the work immediately */ } -static NvBool RegisterFlipOccurredEventOneApiHead(NVDevEvoRec *pDevEvo, - const NvU32 apiHead) +void nvEvoPreModesetRegisterFlipOccurredEvent(NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoModesetUpdateState + *pModesetUpdate) { - const NvU32 dispIndex = 0; /* XXX NVKMS TODO: need disp-scope in event */ - NVDispEvoRec *pDispEvo = pDevEvo->pDispEvo[dispIndex]; + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NvU32 layer; - NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); - nvAssert(head != NV_INVALID_HEAD); - /* - * pDevEvo->apiHead[apiHead].numLayers is the number of layer which is - * visible to nvkms clients, and that number should be less than equal to - * pDevEvo->head[head].numLayers. - * - * If (pDevEvo->head[head].numLayers > pDevEvo->apiHead[apiHead].numLayers) - * then the extra per hardware-head layers remains unused and there is no - * need to register the completion notifier callback for those extra per - * hardware-head layers. - */ - nvAssert(pDevEvo->head[head].numLayers >= - pDevEvo->apiHead[apiHead].numLayers); + /* XXX NVKMS TODO: need disp-scope in event */ + if (pDispEvo->displayOwner != 0) { + return; + } - for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; + const struct _NVEvoModesetUpdateStateOneLayer *pLayer = + &pModesetUpdate->flipOccurredEvent[head].layer[layer]; + + if (!pLayer->changed || + (pLayer->ref_ptr == NULL) || + (pLayer->ref_ptr == pChannel->completionNotifierEventRefPtr)) { + continue; + } + + nvAssert((pChannel->completionNotifierEventHandle == 0) && + (pChannel->completionNotifierEventRefPtr == NULL)); pChannel->completionNotifierEventHandle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); if (!nvRmRegisterCallback(pDevEvo, &pChannel->completionNotifierEventCallback, - pDispEvo->apiHeadState[apiHead]. - flipOccurredEvent[layer].ref_ptr, + pLayer->ref_ptr, pChannel->pb.channel_handle, pChannel->completionNotifierEventHandle, CompletionNotifierEvent, @@ -3870,42 +4325,78 @@ static NvBool RegisterFlipOccurredEventOneApiHead(NVDevEvoRec *pDevEvo, nvFreeUnixRmHandle(&pDevEvo->handleAllocator, pChannel->completionNotifierEventHandle); pChannel->completionNotifierEventHandle = 0; - goto failed; + } else { + pChannel->completionNotifierEventRefPtr = pLayer->ref_ptr; } } +} - return TRUE; +void nvEvoPostModesetUnregisterFlipOccurredEvent(NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoModesetUpdateState + *pModesetUpdate) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 layer; -failed: - UnRegisterFlipOccurredEventOneApiHead(pDevEvo, apiHead); + /* XXX NVKMS TODO: need disp-scope in event */ + if (pDispEvo->displayOwner != 0) { + return; + } - return FALSE; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; + const struct _NVEvoModesetUpdateStateOneLayer *pLayer = + &pModesetUpdate->flipOccurredEvent[head].layer[layer]; + + if (!pLayer->changed || + (pLayer->ref_ptr != NULL) || + (pChannel->completionNotifierEventHandle == 0)) { + + /* + * If the flip occurred event of this layer is updated to get + * enabled (pLayer->ref_ptr != NULL) then that update should have + * been already processed by + * nvEvoPreModesetRegisterFlipOccurredEvent() and + * pChannel->completionNotifierEventRefPtr == pLayer->ref_ptr. + */ + nvAssert(!pLayer->changed || + (pChannel->completionNotifierEventHandle == 0) || + (pChannel->completionNotifierEventRefPtr == + pLayer->ref_ptr)); + continue; + } + + nvRmApiFree(nvEvoGlobal.clientHandle, + pChannel->pb.channel_handle, + pChannel->completionNotifierEventHandle); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pChannel->completionNotifierEventHandle); + pChannel->completionNotifierEventHandle = 0; + pChannel->completionNotifierEventRefPtr = NULL; + } } static NvBool InitApiHeadState(NVDevEvoRec *pDevEvo) { NVDispEvoRec *pDispEvo; NvU32 dispIndex; - NvU32 head; + /* + * For every hardware head, there should be at least one api-head + * which supports the equal number of layer. + */ nvAssert(pDevEvo->numApiHeads == pDevEvo->numHeads); - - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); - pDevEvo->apiHead[apiHead].numLayers = - pDevEvo->head[head].numLayers; + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + pDevEvo->apiHead[head].numLayers = pDevEvo->head[head].numLayers; } FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - if (!InitApiHeadStateOnceDisp(pDispEvo)) { + if (!InitApiHeadStateOneDisp(pDispEvo)) { goto failed; } } - for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - RegisterFlipOccurredEventOneApiHead(pDevEvo, apiHead); - } - nvRmAllocCoreRGSyncpts(pDevEvo); return TRUE; @@ -4108,9 +4599,10 @@ NvBool nvAllocCoreChannelEvo(NVDevEvoPtr pDevEvo) } /*! - * Clear the pConnectorEvo->or.mask tracking. + * Clear the pConnectorEvo->or.primary and pConnectorEvo->or.secondaryMask + * tracking. */ -static void ClearSORAssignmentsOneDisp(NVDispEvoPtr pDispEvo) +static void ClearSORAssignmentsOneDisp(const NVDispEvoRec *pDispEvo) { NVConnectorEvoPtr pConnectorEvo; @@ -4122,14 +4614,16 @@ static void ClearSORAssignmentsOneDisp(NVDispEvoPtr pDispEvo) continue; } - pConnectorEvo->or.mask = 0x0; + pConnectorEvo->or.primary = NV_INVALID_OR; + pConnectorEvo->or.secondaryMask = 0x0; } } /*! - * Update pConnectorEvo->or.mask from the list given to us by RM. + * Update pConnectorEvo->or.primary and pConnectorEvo->or.secondaryMask from + * the list given to us by RM. */ -static void RefreshSORAssignments(NVDispEvoPtr pDispEvo, +static void RefreshSORAssignments(const NVDispEvoRec *pDispEvo, const NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS *pParams) { NVConnectorEvoPtr pConnectorEvo; @@ -4148,22 +4642,38 @@ static void RefreshSORAssignments(NVDispEvoPtr pDispEvo, sorIndex < ARRAY_LEN(pParams->sorAssignList) && sorIndex < ARRAY_LEN(pConnectorEvo->or.ownerHeadMask); sorIndex++) { - if ((pParams->sorAssignList[sorIndex] & displayId) == displayId) { - pConnectorEvo->or.mask |= NVBIT(sorIndex); + if ((pParams->sorAssignListWithTag[sorIndex].displayMask & + displayId) == displayId) { + if ((pParams->sorAssignListWithTag[sorIndex].sorType == + NV0073_CTRL_DFP_SOR_TYPE_SINGLE) || + (pParams->sorAssignListWithTag[sorIndex].sorType == + NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY)) { + pConnectorEvo->or.primary = sorIndex; + } else { + nvAssert(pParams->sorAssignListWithTag[sorIndex].sorType == + NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY); + pConnectorEvo->or.secondaryMask |= NVBIT(sorIndex); + } } } + + nvAssert((pConnectorEvo->or.secondaryMask == 0) || + (pConnectorEvo->or.primary != NV_INVALID_OR)); } } /* - * Ask RM to assign an SOR for the given connector. + * Ask RM to assign an SOR to given displayId. + * + * In 2Heads1OR MST case, this function gets called with the dynamic displayId. * * Note that this assignment may be temporary. This function will always call * RM, and unless the connector is currently in use (i.e., being driven by a * head), a previously-assigned SOR may be reused. * * The RM will either: - * a) return an SOR that's already assigned/attached to this connector, or + * a) return an SOR that's already assigned/attached + * to root port of this displayId, or * b) pick a new "unused" SOR, assign and attach it to this connector, and * return that -- where "unused" means both not being actively driven by a * head and not in the "exclude mask" argument. @@ -4188,39 +4698,25 @@ static void RefreshSORAssignments(NVDispEvoPtr pDispEvo, * finishes the "assessment", the SOR is again eligible for reuse. * * Because of the potential for SOR reuse, nvAssignSOREvo() will always call - * RefreshSORAssignments() to update pConnectorEvo->or.mask on *every* - * connector after calling NV0073_CTRL_CMD_DFP_ASSIGN_SOR for *any* connector. + * RefreshSORAssignments() to update pConnectorEvo->or.primary and + * pConnectorEvo->or.secondaryMask on *every* connector after calling + * NV0073_CTRL_CMD_DFP_ASSIGN_SOR for *any* connector. */ -NvBool nvAssignSOREvo(NVConnectorEvoPtr pConnectorEvo, NvU32 sorExcludeMask) +NvBool nvAssignSOREvo(const NVDispEvoRec *pDispEvo, const NvU32 displayId, + const NvBool b2Heads1Or, const NvU32 sorExcludeMask) { - NVDispEvoPtr pDispEvo = pConnectorEvo->pDispEvo; - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - - NvU32 displayId = 0x0; - + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS params = { 0 }; NvU32 ret; - /* - * Skip assigning an SOR for non-SOR connectors or if an SOR is already - * assigned. - */ - if (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { - return TRUE; - } - if (!NV0073_CTRL_SYSTEM_GET_CAP(pDevEvo->commonCapsBits, NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED)) { return TRUE; } - /* Mode-set is not possible without SOR */ - nvAssert(!nvIsConnectorActiveEvo(pConnectorEvo)); - - displayId = nvDpyIdToNvU32(pConnectorEvo->displayId); - params.subDeviceInstance = pDispEvo->displayOwner; params.displayId = displayId; + params.bIs2Head1Or = b2Heads1Or; params.sorExcludeMask = sorExcludeMask; ret = nvRmApiControl(nvEvoGlobal.clientHandle, @@ -4234,7 +4730,6 @@ NvBool nvAssignSOREvo(NVConnectorEvoPtr pConnectorEvo, NvU32 sorExcludeMask) } RefreshSORAssignments(pDispEvo, ¶ms); - nvAssert(pConnectorEvo->or.mask != 0); return TRUE; } @@ -4245,25 +4740,23 @@ static void CacheSorAssignList(const NVDispEvoRec *pDispEvo, const NVConnectorEvoRec *pConnectorEvo; FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { - NvU32 i; - - if (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { + if ((pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) || + (pConnectorEvo->or.primary == NV_INVALID_OR)) { continue; } - FOR_EACH_INDEX_IN_MASK(32, i, pConnectorEvo->or.mask) { - /* - * RM populates same sor index into more than one connectors if - * they are are DCC partners, this checks make sure SOR - * assignment happens only for a single connector. The sor - * assignment call before modeset/dp-link-training makes sure - * assignment happens for the correct connector. - */ - if (sorAssignList[i] != NULL) { - continue; - } - sorAssignList[i] = pConnectorEvo; - } FOR_EACH_INDEX_IN_MASK_END + /* + * RM populates same sor index into more than one connectors if + * they are are DCC partners, this checks make sure SOR + * assignment happens only for a single connector. The sor + * assignment call before modeset/dp-link-training makes sure + * assignment happens for the correct connector. + */ + if (sorAssignList[pConnectorEvo->or.primary] != NULL) { + continue; + } + sorAssignList[pConnectorEvo->or.primary] = + pConnectorEvo; } } @@ -4734,13 +5227,19 @@ NvBool nvLayerSetPositionEvo( NvBool nvConstructHwModeTimingsImpCheckEvo( const NVConnectorEvoRec *pConnectorEvo, - NVHwModeTimingsEvoPtr pTimings, + const NVHwModeTimingsEvo *pTimings, + const NvBool enableDsc, + const NvBool b2Heads1Or, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pParams, - NVEvoInfoStringPtr pInfoString, - const int head) + NVHwModeTimingsEvo timings[NVKMS_MAX_HEADS_PER_DISP], + NvU32 *pNumHeads, + NVEvoInfoStringPtr pInfoString) { + NvU32 head; + NvU32 activeRmId; + const NvU32 numHeads = b2Heads1Or ? 2 : 1; NVValidateImpOneDispHeadParamsRec timingsParams[NVKMS_MAX_HEADS_PER_DISP]; NvBool requireBootClocks = !!(pParams->overrides & NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS); @@ -4753,34 +5252,46 @@ NvBool nvConstructHwModeTimingsImpCheckEvo( return TRUE; } + activeRmId = nvRmAllocDisplayId(pConnectorEvo->pDispEvo, + nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId)); + if (activeRmId == 0x0) { + return FALSE; + } + nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); - timingsParams[head].pConnectorEvo = pConnectorEvo; - timingsParams[head].activeRmId = - nvRmAllocDisplayId( - pConnectorEvo->pDispEvo, - nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId)); - if (timingsParams[head].activeRmId == 0x0) { - return FALSE; + for (head = 0; head < numHeads; head++) { + timingsParams[head].pConnectorEvo = pConnectorEvo; + timingsParams[head].activeRmId = activeRmId; + timingsParams[head].pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(colorSpace, colorBpc); + if (!nvEvoGetSingleTileHwModeTimings(pTimings, numHeads, + &timings[head])) { + ret = FALSE; + goto done; + } + timingsParams[head].pTimings = &timings[head]; + timingsParams[head].enableDsc = enableDsc; + timingsParams[head].b2Heads1Or = b2Heads1Or; + timingsParams[head].pUsage = &timings[head].viewPort.guaranteedUsage; } - timingsParams[head].pixelDepth = - nvEvoColorSpaceBpcToPixelDepth(colorSpace, colorBpc); - timingsParams[head].pTimings = pTimings; - timingsParams[head].pUsage = &pTimings->viewPort.guaranteedUsage; ret = nvValidateImpOneDispDowngrade(pConnectorEvo->pDispEvo, timingsParams, requireBootClocks, NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE, /* downgradePossibleHeadsBitMask */ (NVBIT(NVKMS_MAX_HEADS_PER_DISP) - 1UL)); - if (!ret) { + if (ret) { + *pNumHeads = numHeads; + } else { nvEvoLogInfoString(pInfoString, "ViewPort %dx%d exceeds hardware capabilities.", pTimings->viewPort.out.width, pTimings->viewPort.out.height); } - nvRmFreeDisplayId(pConnectorEvo->pDispEvo, timingsParams[head].activeRmId); +done: + nvRmFreeDisplayId(pConnectorEvo->pDispEvo, activeRmId); return ret; } @@ -5002,27 +5513,6 @@ static NvBool ApplyDualLinkRequirements(const NVDpyEvoRec *pDpyEvo, return TRUE; } -/* Query the HDMI 2.1 FRL configuration, if applicable. */ -static NvBool QueryHdmiFrlConfig(const NVDpyEvoRec *pDpyEvo, - const struct - NvKmsModeValidationParams *pParams, - const NvModeTimings *pModeTimings, - NVHwModeTimingsEvoPtr pTimings, - NVEvoInfoStringPtr pInfoString) -{ - /* TODO: apply any overrides from ModeValidationParams. */ - if (!nvHdmiFrlQueryConfig(pDpyEvo, - pModeTimings, - pTimings, - pParams)) { - nvEvoLogInfoString(pInfoString, - "Unable to determine HDMI 2.1 Fixed Rate Link configuration."); - return FALSE; - } - - return TRUE; -} - void nvInitScalingUsageBounds(const NVDevEvoRec *pDevEvo, struct NvKmsScalingUsageBounds *pScaling) { @@ -5481,7 +5971,11 @@ static NvBool GetDfpProtocol(const NVDpyEvoRec *pDpyEvo, if (pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { /* Override protocol if this mode requires HDMI FRL. */ - if (pTimings->hdmiFrlConfig.frlRate != HDMI_FRL_DATA_RATE_NONE) { + if (nvDpyIsHdmiEvo(pDpyEvo) && + nvHdmiTimingsNeedFrl(pDpyEvo, pTimings)) { + if (!nvHdmiDpySupportsFrl(pDpyEvo)) { + return FALSE; + } nvAssert(nvDpyIsHdmiEvo(pDpyEvo)); nvAssert(rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A || rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B); @@ -5601,24 +6095,16 @@ static NvBool ConstructHwModeTimingsEvoDfp(const NVDpyEvoRec *pDpyEvo, ConstructHwModeTimingsFromNvModeTimings(pModeTimings, pTimings); - ret = QueryHdmiFrlConfig(pDpyEvo, pParams, - pModeTimings, pTimings, - pInfoString); - - if (!ret) { - return FALSE; - } - ret = GetDfpProtocol(pDpyEvo, pTimings); if (!ret) { - return FALSE; + return ret; } ret = ApplyDualLinkRequirements(pDpyEvo, pParams, pTimings, pInfoString); if (!ret) { - return FALSE; + return ret; } return ConstructHwModeTimingsViewPort(pDpyEvo->pDispEvo, pTimings, @@ -5689,6 +6175,8 @@ NvBool nvDowngradeColorSpaceAndBpc( NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, + const NvBool b2Heads1Or, + NVDscInfoEvoRec *pDscInfo, const struct NvKmsModeValidationParams *pParams) { NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; @@ -5728,7 +6216,7 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, tryAgain: if (!nvDPValidateModeForDpyEvo(pDpyEvo, colorSpace, colorBpc, pParams, - pTimings)) { + pTimings, b2Heads1Or, pDscInfo)) { if (nvDowngradeColorSpaceAndBpc(&supportedColorFormats, &colorSpace, &colorBpc, &colorRange)) { goto tryAgain; @@ -6353,6 +6841,8 @@ static void AssignNVEvoIsModePossibleDispInput( } pImpInput->head[head].pTimings = timingsParams[head].pTimings; + pImpInput->head[head].enableDsc = timingsParams[head].enableDsc; + pImpInput->head[head].b2Heads1Or = timingsParams[head].b2Heads1Or; pImpInput->head[head].pixelDepth = timingsParams[head].pixelDepth; pImpInput->head[head].displayId = timingsParams[head].activeRmId; pImpInput->head[head].orType = pConnectorEvo->or.type; @@ -6362,10 +6852,9 @@ static void AssignNVEvoIsModePossibleDispInput( NV0073_CTRL_SYSTEM_CAPS_CROSS_BAR_SUPPORTED) || pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { - nvAssert(pConnectorEvo->or.mask != 0x0); + nvAssert(pConnectorEvo->or.primary != NV_INVALID_OR); - pImpInput->head[head].orIndex = - nvEvoConnectorGetPrimaryOr(pConnectorEvo); + pImpInput->head[head].orIndex = pConnectorEvo->or.primary; continue; } @@ -7429,12 +7918,12 @@ NVDevEvoPtr nvAllocDevEvo(const struct NvKmsAllocDeviceRequest *pRequest, // Note that we use pDev and subdevice here instead of pDisp since this is used // per-subdev in SLI (including the pDispEvo->numSubDevices > 1 case). // -static NvBool EvoWaitForLock(NVDevEvoPtr pDevEvo, - NvU32 sd, NvU32 head, NvU32 type) +static NvBool EvoWaitForLock(const NVDevEvoRec *pDevEvo, const NvU32 sd, + const NvU32 head, const NvU32 type, + NvU64 *pStartTime) { NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS status = { }; NvU32 ret; - NvU64 startTime = 0; nvAssert(type == EVO_RASTER_LOCK || type == EVO_FLIP_LOCK); @@ -7472,7 +7961,7 @@ static NvBool EvoWaitForLock(NVDevEvoPtr pDevEvo, break; } - if (nvExceedsTimeoutUSec(&startTime, LOCK_TIMEOUT)) { + if (nvExceedsTimeoutUSec(pStartTime, LOCK_TIMEOUT)) { nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "SLI lock timeout exceeded (type %d)", type); return FALSE; @@ -7605,7 +8094,7 @@ NvBool nvReadCRC32Evo(NVDispEvoPtr pDispEvo, NvU32 head, dma, pConnectorEvo, pTimings->protocol, - nvEvoConnectorGetPrimaryOr(pConnectorEvo), + pConnectorEvo->or.primary, head, pDispEvo->displayOwner, &updateState); @@ -7650,9 +8139,14 @@ NvU32 nvGetActiveSorMask(const NVDispEvoRec *pDispEvo) if (pConnectorEvo != NULL && pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { - nvAssert(pConnectorEvo->or.mask != 0x0); - - activeSorMask |= pConnectorEvo->or.mask; + NvU32 orIndex; + nvAssert(pConnectorEvo->or.primary != NV_INVALID_OR); + FOR_EACH_INDEX_IN_MASK(32, orIndex, nvConnectorGetORMaskEvo(pConnectorEvo)) { + if (pConnectorEvo->or.ownerHeadMask[orIndex] == 0x0) { + continue; + } + activeSorMask |= NVBIT(orIndex); + } FOR_EACH_INDEX_IN_MASK_END; } } @@ -7711,7 +8205,7 @@ static void DPSerializerLinkTrain(NVDispEvoPtr pDispEvo, NvBool reTrain) { const NvU32 displayId = nvDpyIdToNvU32(pConnectorEvo->displayId); - const NvU32 sorNumber = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + const NvU32 sorNumber = pConnectorEvo->or.primary; const NvU32 headMask = nvConnectorGetAttachedHeadMaskEvo(pConnectorEvo); NvBool force = NV_FALSE; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -8035,3 +8529,224 @@ enum nvKmsPixelDepth nvEvoColorSpaceBpcToPixelDepth( return NVKMS_PIXEL_DEPTH_18_444; } + +void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NvU32 primaryHead = nvGetPrimaryHwHeadFromMask(headsMask); + NvU32 head; + + nvAssert(pDevEvo->hal->caps.supportsMergeMode); + nvAssert((nvPopCount32(headsMask) > 1) && + (primaryHead != NV_INVALID_HEAD)); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + NVEvoHeadControl *pHC = + &pDevEvo->gpus[sd].headControl[head]; + + nvAssert(pHeadState->mergeMode == + NV_EVO_MERGE_MODE_DISABLED); + + /* + * Heads requires to be raster locked before they transition to + * PRIMARY/SECONDARY merge mode. + * + * SETUP should be the intermediate state before head transition to + * PRIMARY/SECONDARY merge mode. During SETUP state, there is no pixel + * transmission from secondary to primary head, RG fetches and drops + * pixels, viewport gets filled by the special gray/black pixels. + */ + pHeadState->mergeMode = NV_EVO_MERGE_MODE_SETUP; + pDevEvo->hal->SetMergeMode(pDispEvo, head, pHeadState->mergeMode, + pUpdateState); + + nvAssert((pHC->serverLock == NV_EVO_NO_LOCK) && + (pHC->clientLock == NV_EVO_NO_LOCK)); + + if (head == primaryHead) { + pHC->serverLock = NV_EVO_RASTER_LOCK; + pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); + pHC->setLockOffsetX = TRUE; + } else { + pHC->clientLock = NV_EVO_RASTER_LOCK; + pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); + if (pTimings->vrr.type != NVKMS_DPY_VRR_TYPE_NONE) { + pHC->clientLockoutWindow = 4; + pHC->useStallLockPin = TRUE; + pHC->stallLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); + } else { + pHC->clientLockoutWindow = 2; + } + } + + if (pTimings->vrr.type != NVKMS_DPY_VRR_TYPE_NONE) { + pHC->crashLockUnstallMode = TRUE; + } + pHC->stereoLocked = FALSE; + + EvoUpdateHeadParams(pDispEvo, head, pUpdateState); + } +} + +void nvEvoEnableMergeModePostModeset(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NvU32 primaryHead = nvGetPrimaryHwHeadFromMask(headsMask); + NvU64 startTime = 0; + NvU32 head; + + nvAssert(pDevEvo->hal->caps.supportsMergeMode); + nvAssert((nvPopCount32(headsMask) > 1) && + (primaryHead != NV_INVALID_HEAD)); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + nvAssert(pDispEvo->headState[head].mergeMode == + NV_EVO_MERGE_MODE_SETUP); + + if (!EvoWaitForLock(pDevEvo, sd, head, EVO_RASTER_LOCK, + &startTime)) { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, "Raster lock timeout"); + return; + } + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NVEvoHeadControl *pHC = &pDevEvo->gpus[sd].headControl[head]; + + pHC->flipLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); + pHC->flipLock = TRUE; + + EvoUpdateHeadParams(pDispEvo, head, pUpdateState); + + pHeadState->mergeMode = (head == primaryHead) ? + NV_EVO_MERGE_MODE_PRIMARY : NV_EVO_MERGE_MODE_SECONDARY; + pDevEvo->hal->SetMergeMode(pDispEvo, head, pHeadState->mergeMode, + pUpdateState); + } +} + +void nvEvoDisableMergeMode(NVDispEvoRec *pDispEvo, + const NvU32 headsMask, + NVEvoUpdateState *pUpdateState) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + NvU32 head; + + nvAssert(pDevEvo->hal->caps.supportsMergeMode); + nvAssert(nvPopCount32(headsMask) > 1); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NVEvoHeadControl *pHC = + &pDevEvo->gpus[sd].headControl[head]; + + pHeadState->mergeMode = NV_EVO_MERGE_MODE_DISABLED; + pDevEvo->hal->SetMergeMode(pDispEvo, head, pHeadState->mergeMode, + pUpdateState); + + pHC->serverLock = NV_EVO_NO_LOCK; + pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->clientLock = NV_EVO_NO_LOCK; + pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->clientLockoutWindow = 0; + pHC->setLockOffsetX = FALSE; + pHC->flipLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->flipLock = FALSE; + pHC->useStallLockPin = FALSE; + pHC->stallLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->crashLockUnstallMode = FALSE; + + + EvoUpdateHeadParams(pDispEvo, head, pUpdateState); + } +} + +NvBool nvEvoGetSingleTileHwModeTimings(const NVHwModeTimingsEvo *pSrc, + const NvU32 numTiles, + NVHwModeTimingsEvo *pDst) +{ + if (numTiles == 1) { + *pDst = *pSrc; + return TRUE; + } + + if ((numTiles == 0) || + (pSrc->viewPort.out.xAdjust != 0) || + (pSrc->viewPort.out.width != nvEvoVisibleWidth(pSrc))) { + return FALSE; + } + + if (((pSrc->rasterSize.x % numTiles) != 0) || + (((pSrc->rasterSyncEnd.x + 1) % numTiles) != 0) || + (((pSrc->rasterBlankEnd.x + 1) % numTiles) != 0) || + (((pSrc->rasterBlankStart.x + 1) % numTiles) != 0) || + ((pSrc->pixelClock % numTiles) != 0) || + ((pSrc->viewPort.in.width % numTiles) != 0)) { + return FALSE; + } + + *pDst = *pSrc; + + pDst->rasterSize.x /= numTiles; + pDst->rasterSyncEnd.x /= numTiles; + pDst->rasterBlankEnd.x /= numTiles; + pDst->rasterBlankStart.x /= numTiles; + + pDst->pixelClock /= numTiles; + + pDst->viewPort.out.width /= numTiles; + pDst->viewPort.in.width /= numTiles; + + return TRUE; +} + +NvBool nvEvoUse2Heads1OR(const NVDpyEvoRec *pDpyEvo, + const NVHwModeTimingsEvo *pTimings, + const struct NvKmsModeValidationParams *pParams) +{ + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NVEvoHeadCaps *pHeadCaps = + &pDispEvo->pDevEvo->gpus[sd].capabilities.head[0]; + + /* The 2Heads1OR mode can not be used if GPU does not + * support merge mode, or */ + if (!pDispEvo->pDevEvo->hal->caps.supportsMergeMode || + /* the 2Heads1OR mode is forced disabled by client, or */ + ((pParams->overrides & + NVKMS_MODE_VALIDATION_MAX_ONE_HARDWARE_HEAD) != 0) || + /* the given dpy does not support the display stream compression + * and the given mode timings are not using the hardware YUV420 + * packer, or */ + (!nvDPDpyIsDscPossible(pDpyEvo) && !nvHdmiDpySupportsDsc(pDpyEvo) && + (pTimings->yuv420Mode != NV_YUV420_MODE_HW)) || + /* the non-centered viewport out does not work with 2Heads1OR mode + * an for simplicity disable all customized viewport out, or */ + (pTimings->viewPort.out.width != nvEvoVisibleWidth(pTimings)) || + (pTimings->viewPort.out.xAdjust != 0) || + /* either HVisible, HSyncWidth, HBackPorch, HForntPorch, + * pixelClock, or viewPortIn width is odd and can not be split + * equally across two heads, or */ + ((pTimings->rasterSize.x & 1 ) != 0) || + ((pTimings->rasterSyncEnd.x & 1) != 1) || + ((pTimings->rasterBlankEnd.x & 1) != 1) || + ((pTimings->rasterBlankStart.x & 1) != 1) || + ((pTimings->pixelClock & 1) != 0) || + ((pTimings->viewPort.in.width & 1) != 0)) { + return FALSE; + } + + /* Use 2Heads1OR mode only if the required pixel clock is greater than the + * maximum pixel clock support by a head. */ + return (pTimings->pixelClock > pHeadCaps->maxPClkKHz); +} diff --git a/src/nvidia-modeset/src/nvkms-evo1.c b/src/nvidia-modeset/src/nvkms-evo1.c index 01a1bd01da..d6f3780639 100644 --- a/src/nvidia-modeset/src/nvkms-evo1.c +++ b/src/nvidia-modeset/src/nvkms-evo1.c @@ -543,8 +543,8 @@ NvBool nvEvo1IsChannelMethodPending(NVDevEvoPtr pDevEvo, void nvEvo1SetDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo, const enum nvKmsPixelDepth pixelDepth) { - nvAssert(!pTimings->dpDsc.enable); + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DISABLED); } diff --git a/src/nvidia-modeset/src/nvkms-evo2.c b/src/nvidia-modeset/src/nvkms-evo2.c index 5761f42026..3642c5384a 100644 --- a/src/nvidia-modeset/src/nvkms-evo2.c +++ b/src/nvidia-modeset/src/nvkms-evo2.c @@ -328,6 +328,8 @@ static void EvoSetRasterParams90(NVDevEvoPtr pDevEvo, int head, */ static void EvoSetRasterParams91(NVDevEvoPtr pDevEvo, int head, const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, const NVEvoColorRec *pOverscanColor, NVEvoUpdateState *updateState) { @@ -336,6 +338,9 @@ static void EvoSetRasterParams91(NVDevEvoPtr pDevEvo, int head, DRF_DEF(917D, _HEAD_SET_HDMI_CTRL, _STEREO3D_STRUCTURE, _FRAME_PACKED) | DRF_NUM(917D, _HEAD_SET_HDMI_CTRL, _HDMI_VIC, 0); + nvAssert(tilePosition == 0); + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DISABLED); + EvoSetRasterParams90(pDevEvo, head, pTimings, pOverscanColor, updateState); @@ -2518,8 +2523,11 @@ static void EvoSetLUTContextDma90(const NVDispEvoRec *pDispEvo, REF_VAL(NV##cl##_CORE_NOTIFIER_##n##_CAPABILITIES_CAP_HEAD##i##_##x##_MAX_PIXELS##t##TAP444, \ (pCaps)[NV##cl##_CORE_NOTIFIER_##n##_CAPABILITIES_CAP_HEAD##i##_##x])) -#define NV_EVO2_CAP_GET_HEAD(cl, n, pEvoCaps, i, x, y, z, pCaps) \ +#define NV_EVO2_CAP_GET_HEAD(cl, n, pEvoCaps, i, x, y, z, a, pCaps) \ (pEvoCaps)->head[(i)].usable = TRUE; \ + (pEvoCaps)->head[(i)].maxPClkKHz = \ + DRF_VAL(cl##_CORE_NOTIFIER_##n, _CAPABILITIES_CAP_HEAD##i##_##a, _PCLK_MAX, \ + (pCaps)[NV##cl##_CORE_NOTIFIER_##n##_CAPABILITIES_CAP_HEAD##i##_##a]) * 10000; \ (pEvoCaps)->head[(i)].scalerCaps.present = TRUE; \ NV_EVO2_CAP_GET_HEAD_MAX_PIXELS(cl, n, pEvoCaps, i, x, 5, pCaps); \ NV_EVO2_CAP_GET_HEAD_MAX_PIXELS(cl, n, pEvoCaps, i, y, 3, pCaps); \ @@ -2570,10 +2578,10 @@ static void EvoParseCapabilityNotifier3(NVEvoCapabilitiesPtr pEvoCaps, pEvoCaps->misc.supportsDSI = FALSE; // Heads - NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 0, 53, 54, 55, pCaps); - NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 1, 61, 62, 63, pCaps); - NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 2, 69, 70, 71, pCaps); - NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 3, 77, 78, 79, pCaps); + NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 0, 53, 54, 55, 56, pCaps); + NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 1, 61, 62, 63, 64, pCaps); + NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 2, 69, 70, 71, 72, pCaps); + NV_EVO2_CAP_GET_HEAD(917D, 3, pEvoCaps, 3, 77, 78, 79, 80, pCaps); // SORs NV_EVO2_CAP_GET_SOR(917D, 3, pEvoCaps, 0, 20, 21, pCaps); @@ -3851,6 +3859,7 @@ NVEvoHAL nvEvo94 = { EvoClearSurfaceUsage91, /* ClearSurfaceUsage */ EvoComputeWindowScalingTaps91, /* ComputeWindowScalingTaps */ NULL, /* GetWindowScalingCaps */ + NULL, /* SetMergeMode */ { /* caps */ FALSE, /* supportsNonInterlockedUsageBoundsUpdate */ FALSE, /* supportsDisplayRate */ @@ -3868,6 +3877,7 @@ NVEvoHAL nvEvo94 = { FALSE, /* supportsSynchronizedOverlayPositionUpdate */ FALSE, /* supportsVblankSyncObjects */ TRUE, /* requiresScalingTapsInBothDimensions */ + FALSE, /* supportsMergeMode */ NV_EVO2_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_1TAP, /* minScalerTaps */ diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c index f4c9f9d146..e4bc5d634b 100644 --- a/src/nvidia-modeset/src/nvkms-evo3.c +++ b/src/nvidia-modeset/src/nvkms-evo3.c @@ -36,6 +36,7 @@ #include "nvkms-prealloc.h" #include "nv-float.h" #include "nvkms-dpy.h" +#include "nvkms-vrr.h" #include @@ -1268,10 +1269,10 @@ static NvBool ComputeMinFrameIdle( return TRUE; } -static void EvoSetRasterParamsC3(NVDevEvoPtr pDevEvo, int head, - const NVHwModeTimingsEvo *pTimings, - const NVEvoColorRec *pOverscanColor, - NVEvoUpdateState *updateState) +static void EvoSetRasterParams3(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; /* XXXnvdisplay: Convert these for YCbCr, as necessary */ @@ -1376,6 +1377,118 @@ static void EvoSetRasterParamsC3(NVDevEvoPtr pDevEvo, int head, nvDmaSetEvoMethodData(pChannel, hdmiStereoCtrl); } +static void EvoSetRasterParamsC3(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) +{ + nvAssert(tilePosition == 0); + EvoSetRasterParams3(pDevEvo, head, pTimings, pOverscanColor, updateState); +} + +static void EvoSetRasterParams5(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) +{ + NVEvoChannelPtr pChannel = pDevEvo->core; + + /* These methods should only apply to a single pDpy */ + nvAssert(pDevEvo->subDevMaskStackDepth > 0); + + nvUpdateUpdateState(pDevEvo, updateState, pChannel); + + EvoSetRasterParams3(pDevEvo, head, pTimings, pOverscanColor, updateState); + + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_TILE_POSITION(head), 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57D, _HEAD_SET_TILE_POSITION, _X, tilePosition) | + DRF_NUM(C57D, _HEAD_SET_TILE_POSITION, _Y, 0)); +} + +static void EvoSetRasterParamsC5(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) +{ + nvAssert(pDscInfo->type != NV_DSC_INFO_EVO_TYPE_HDMI); + EvoSetRasterParams5(pDevEvo, head, pTimings, tilePosition, pOverscanColor, + updateState); +} + +static NvU32 GetHdmiDscHBlankPixelTarget(const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo) +{ + nvAssert((pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) || + (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_SINGLE)); + + const NvU32 hblankMin = + (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) ? + ((pDscInfo->hdmi.hblankMin + 1) / 2) : + pDscInfo->hdmi.hblankMin; + + NvU32 hBlankPixelTarget = + NV_UNSIGNED_DIV_CEIL((pTimings->rasterSize.x * + pDscInfo->hdmi.dscTBlankToTTotalRatioX1k), + 1000); + + hBlankPixelTarget = NV_MAX(hblankMin, hBlankPixelTarget); + + if (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) { + hBlankPixelTarget += (hBlankPixelTarget % 2); + } + + return hBlankPixelTarget; +} + +static void EvoSetRasterParamsC6(NVDevEvoPtr pDevEvo, int head, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, + const NVDscInfoEvoRec *pDscInfo, + const NVEvoColorRec *pOverscanColor, + NVEvoUpdateState *updateState) +{ + NvU32 rasterHBlankDelay; + NVEvoChannelPtr pChannel = pDevEvo->core; + + /* These methods should only apply to a single pDpy */ + nvAssert(pDevEvo->subDevMaskStackDepth > 0); + + nvUpdateUpdateState(pDevEvo, updateState, pChannel); + + EvoSetRasterParams5(pDevEvo, head, pTimings, tilePosition, pOverscanColor, + updateState); + + if (pDscInfo->type == NV_DSC_INFO_EVO_TYPE_HDMI) { + const NvU32 hBlank = pTimings->rasterSize.x - + pTimings->rasterBlankStart.x + pTimings->rasterBlankEnd.x; + const NvU32 hBlankPixelTarget = + GetHdmiDscHBlankPixelTarget(pTimings, pDscInfo); + + const NvU32 headSetRasterHBlankDelayStart = + pTimings->rasterSize.x - pTimings->rasterBlankStart.x - 2; + const NvU32 headSetRasterHBlankDelayEnd = + hBlankPixelTarget - hBlank + headSetRasterHBlankDelayStart; + + rasterHBlankDelay = + DRF_NUM(C67D, _HEAD_SET_RASTER_HBLANK_DELAY, _BLANK_START, + headSetRasterHBlankDelayStart); + rasterHBlankDelay |= + DRF_NUM(C67D, _HEAD_SET_RASTER_HBLANK_DELAY, _BLANK_END, + headSetRasterHBlankDelayEnd); + } else { + rasterHBlankDelay = 0; + } + + nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_RASTER_HBLANK_DELAY(head), 1); + nvDmaSetEvoMethodData(pChannel, rasterHBlankDelay); +} + static void EvoSetProcAmpC3(NVDispEvoPtr pDispEvo, const NvU32 head, NVEvoUpdateState *updateState) { @@ -1979,6 +2092,18 @@ static void EvoSetHeadControlC3(NVDevEvoPtr pDevEvo, int sd, int head, nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_LOCK_CHAIN(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_NUM(C37D, _HEAD_SET_LOCK_CHAIN, _POSITION, pHC->lockChainPosition)); + +/* XXX temporary WAR; see bug 4028718 */ +#if !defined(NVC37D_HEAD_SET_LOCK_OFFSET) +#define NVC37D_HEAD_SET_LOCK_OFFSET(a) (0x00002040 + (a)*0x00000400) +#define NVC37D_HEAD_SET_LOCK_OFFSET_X 14:0 +#define NVC37D_HEAD_SET_LOCK_OFFSET_Y 30:16 +#endif + + nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_LOCK_OFFSET(head), 1); + nvDmaSetEvoMethodData(pChannel, pHC->setLockOffsetX ? + DRF_NUM(C37D, _HEAD_SET_LOCK_OFFSET, _X, + 27) : 0); } static void EvoSetHeadRefClkC3(NVDevEvoPtr pDevEvo, int head, NvBool external, @@ -2911,6 +3036,8 @@ static void EvoUpdateC3(NVDevEvoPtr pDevEvo, */ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead, const NVHwModeTimingsEvo *pTimings, + const NvBool enableDsc, + const NvBool b2Heads1Or, const int head, const NVEvoScalerCaps *pScalerCaps) { @@ -2964,8 +3091,9 @@ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead, /* Cursor width, in units of 32 pixels. Assume we use the maximum size. */ pImpHead->cursorSize32p = 256 / 32; - pImpHead->bEnableDsc = pTimings->hdmiFrlConfig.dscInfo.bEnableDSC || - pTimings->dpDsc.enable; + pImpHead->bEnableDsc = enableDsc; + + pImpHead->bIs2Head1Or = b2Heads1Or; pImpHead->bYUV420Format = (pTimings->yuv420Mode == NV_YUV420_MODE_HW); @@ -3080,6 +3208,8 @@ EvoIsModePossibleC3(NVDispEvoPtr pDispEvo, for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { const NVHwModeTimingsEvo *pTimings = pInput->head[head].pTimings; + const NvU32 enableDsc = pInput->head[head].enableDsc; + const NvBool b2Heads1Or = pInput->head[head].b2Heads1Or; const struct NvKmsUsageBounds *pUsage = pInput->head[head].pUsage; const NVHwModeViewPortEvo *pViewPort; NvU8 impHeadIndex; @@ -3097,6 +3227,8 @@ EvoIsModePossibleC3(NVDispEvoPtr pDispEvo, if (!AssignPerHeadImpParams(&pImp->head[impHeadIndex], pTimings, + enableDsc, + b2Heads1Or, head, &pEvoCaps->head[head].scalerCaps)) { goto done; @@ -3478,7 +3610,8 @@ static NvBool EvoFlipC3Common(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NVFlipChannelEvoHwState *pHwState, - NVEvoUpdateState *updateState) + NVEvoUpdateState *updateState, + NvU32 head) { const NvKmsSurfaceMemoryFormatInfo *pFormatInfo; NvU32 presentControl, eye; @@ -3490,12 +3623,36 @@ EvoFlipC3Common(NVDevEvoPtr pDevEvo, /* program notifier */ if (pHwState->completionNotifier.surface.pSurfaceEvo == NULL) { + /* + * if no notifier surface is attached but vrr RGLine calculations + * for frame pacing are enabled then we need to provide our own + * surface and keep getting flip completion updates. + */ + NvU32 offset; + const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); + const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; + NVDispHeadStateEvoRec *pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; + struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo = &pHeadState->vrrFramePacingInfo; - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, 0); - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); - nvDmaSetEvoMethodData(pChannel, 0); + if (pVrrFramePacingInfo->framePacingActive) { + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37E, + _SET_CONTEXT_DMA_NOTIFIER, + _HANDLE, + pChannel->notifiersDma[sd].ctxHandle)); + offset = nvPrepareNextVrrNotifier(pChannel, sd, head); + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37E, _SET_NOTIFIER_CONTROL, _OFFSET, offset) | + (DRF_DEF(C37E, _SET_NOTIFIER_CONTROL, _MODE, _WRITE_AWAKEN))); + } else { + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); + nvDmaSetEvoMethodData(pChannel, 0); + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, 0); + } } else { const NVFlipNIsoSurfaceEvoHwState *pNIso = &pHwState->completionNotifier.surface; @@ -4013,13 +4170,15 @@ EvoFlipC3(NVDevEvoPtr pDevEvo, enum NvKmsSurfaceMemoryFormat format; NVLutSurfaceEvoPtr pLutSurfaceEvo = EvoGetLutSurface3(pDevEvo, pChannel, pHwState); + NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); + NvU32 head = pDevEvo->headForWindow[win]; if (pHwState->timeStamp != 0) { InsertAdditionalTimestampFlip(pDevEvo, pChannel, pHwState, updateState); } - flip3Return = EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState); + flip3Return = EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState, head); /* program semaphore */ EvoProgramSemaphore3(pDevEvo, pChannel, pHwState); @@ -4178,7 +4337,7 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, pLutSurfaceEvo = EvoGetLutSurface3(pDevEvo, pChannel, pHwState); } - if (!EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState)) { + if (!EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState, head)) { ConfigureTmoLut(pDevEvo, pHwState, pChannel); return; } @@ -5231,6 +5390,14 @@ static void EvoParseCapabilityNotifier3(NVDevEvoPtr pDevEvo, // NVDisplay does not support interlaced modes. pEvoCaps->misc.supportsInterlaced = FALSE; +/* XXX temporary WAR; see bug 4028718 */ +#if !defined(NVC373_HEAD_CLK_CAP) +#define NVC373_HEAD_CLK_CAP(i) (0x5e8+(i)*4) /* RW-4A */ +#define NVC373_HEAD_CLK_CAP__SIZE_1 8 /* */ +#define NVC373_HEAD_CLK_CAP_PCLK_MAX 7:0 /* RWIUF */ +#define NVC373_HEAD_CLK_CAP_PCLK_MAX_INIT 0x00000085 /* RWI-V */ +#endif + // Heads ct_assert(ARRAY_LEN(pEvoCaps->head) >= NVC373_HEAD_CAPA__SIZE_1); for (i = 0; i < NVC373_HEAD_CAPA__SIZE_1; i++) { @@ -5238,6 +5405,12 @@ static void EvoParseCapabilityNotifier3(NVDevEvoPtr pDevEvo, pHeadCaps->usable = FLD_IDX_TEST_DRF(C373, _SYS_CAP, _HEAD_EXISTS, i, _YES, sysCap); + if (pHeadCaps->usable) { + pHeadCaps->maxPClkKHz = + DRF_VAL(C373, _HEAD_CLK_CAP, _PCLK_MAX, + ReadCapReg(pCaps, NVC373_HEAD_CLK_CAP(i))) * 10000; + } + } // SORs @@ -6464,16 +6637,35 @@ static void EvoSetStallLockC3(NVDispEvoPtr pDispEvo, const int head, { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoChannelPtr pChannel = pDevEvo->core; + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; nvUpdateUpdateState(pDevEvo, updateState, pChannel); if (enable) { + NvU32 data = DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _TRUE) | + DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _MODE, _ONE_SHOT); + + if (!pHC->useStallLockPin) { + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, _LOCK_PIN_NONE); + } else if (NV_EVO_LOCK_PIN_IS_INTERNAL(pHC->stallLockPin)) { + NvU32 pin = pHC->stallLockPin - NV_EVO_LOCK_PIN_INTERNAL_0; + data |= DRF_NUM(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, + NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_INTERNAL_SCAN_LOCK(pin)); + } else { + NvU32 pin = pHC->stallLockPin - NV_EVO_LOCK_PIN_0; + data |= DRF_NUM(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, + NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(pin)); + } + + if (pHC->crashLockUnstallMode) { + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _CRASH_LOCK); + } else { + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _LINE_LOCK); + } + nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1); - nvDmaSetEvoMethodData(pChannel, - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _TRUE) | - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _MODE, _ONE_SHOT) | - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, _LOCK_PIN_NONE) | - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _LINE_LOCK)); + nvDmaSetEvoMethodData(pChannel, data); } else { nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1); nvDmaSetEvoMethodData(pChannel, @@ -7222,19 +7414,17 @@ EvoConfigureVblankSyncObjectC6(const NVDevEvoPtr pDevEvo, rasterLine)); } -static void EvoSetHdmiFrlDscParams(const NVDispEvoRec *pDispEvo, +static void EvoSetHdmiDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo, const enum nvKmsPixelDepth pixelDepth) { NVEvoChannelPtr pChannel = pDispEvo->pDevEvo->core; - const HDMI_FRL_CONFIG *pFrl = &pTimings->hdmiFrlConfig; NvU32 bpc, flatnessDetThresh; NvU32 i; nvAssert(pDispEvo->pDevEvo->hal->caps.supportsHDMIFRL && - pFrl->frlRate != HDMI_FRL_DATA_RATE_NONE && - pFrl->dscInfo.bEnableDSC); + pDscInfo->type == NV_DSC_INFO_EVO_TYPE_HDMI); bpc = nvPixelDepthToBitsPerComponent(pixelDepth); if (bpc < 8) { @@ -7246,7 +7436,9 @@ static void EvoSetHdmiFrlDscParams(const NVDispEvoRec *pDispEvo, nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_DSC_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_DEF(C67D, _HEAD_SET_DSC_CONTROL, _ENABLE, _TRUE) | - DRF_DEF(C67D, _HEAD_SET_DSC_CONTROL, _MODE, _SINGLE) | /* TODO DUAL for 2Head1OR */ + ((pDscInfo->hdmi.dscMode == NV_DSC_EVO_MODE_DUAL) ? + DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _DUAL) : + DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _SINGLE)) | DRF_NUM(C67D, _HEAD_SET_DSC_CONTROL, _FLATNESS_DET_THRESH, flatnessDetThresh) | DRF_DEF(C67D, _HEAD_SET_DSC_CONTROL, _FULL_ICH_ERR_PRECISION, _ENABLE) | DRF_DEF(C67D, _HEAD_SET_DSC_CONTROL, _AUTO_RESET, _ENABLE) | @@ -7261,12 +7453,12 @@ static void EvoSetHdmiFrlDscParams(const NVDispEvoRec *pDispEvo, DRF_NUM(C67D, _HEAD_SET_DSC_PPS_CONTROL, _SIZE, 0x21)); /* The loop below assumes the methods are tightly packed. */ - ct_assert(ARRAY_LEN(pFrl->dscInfo.pps) == 32); + ct_assert(ARRAY_LEN(pDscInfo->hdmi.pps) == 32); ct_assert((NVC67D_HEAD_SET_DSC_PPS_DATA1(0) - NVC67D_HEAD_SET_DSC_PPS_DATA0(0)) == 4); ct_assert((NVC67D_HEAD_SET_DSC_PPS_DATA31(0) - NVC67D_HEAD_SET_DSC_PPS_DATA0(0)) == (31 * 4)); - for (i = 0; i < ARRAY_LEN(pFrl->dscInfo.pps); i++) { + for (i = 0; i < ARRAY_LEN(pDscInfo->hdmi.pps); i++) { nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_DSC_PPS_DATA0(head) + (i * 4), 1); - nvDmaSetEvoMethodData(pChannel, pFrl->dscInfo.pps[i]); + nvDmaSetEvoMethodData(pChannel, pDscInfo->hdmi.pps[i]); } /* Byte 0 must be 0x7f, the rest are don't care (will be filled in by HW) */ @@ -7276,32 +7468,37 @@ static void EvoSetHdmiFrlDscParams(const NVDispEvoRec *pDispEvo, nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_HDMI_DSC_HCACTIVE(head), 1); nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCACTIVE, _BYTES, pFrl->dscInfo.dscHActiveBytes) | - DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCACTIVE, _TRI_BYTES, pFrl->dscInfo.dscHActiveTriBytes)); + DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCACTIVE, _BYTES, pDscInfo->hdmi.dscHActiveBytes) | + DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCACTIVE, _TRI_BYTES, pDscInfo->hdmi.dscHActiveTriBytes)); nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_HDMI_DSC_HCBLANK(head), 1); nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCBLANK, _WIDTH, pFrl->dscInfo.dscHBlankTriBytes)); + DRF_NUM(C67D, _HEAD_SET_HDMI_DSC_HCBLANK, _WIDTH, pDscInfo->hdmi.dscHBlankTriBytes)); } static void EvoSetDpDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings) + const NVDscInfoEvoRec *pDscInfo) { NVEvoChannelPtr pChannel = pDispEvo->pDevEvo->core; NvU32 flatnessDetThresh; NvU32 i; - nvAssert(pTimings->dpDsc.enable); + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DP); // XXX: I'm pretty sure that this is wrong. // BitsPerPixelx16 is something like (24 * 16) = 384, and 2 << (384 - 8) is // an insanely large number. - flatnessDetThresh = (2 << (pTimings->dpDsc.bitsPerPixelX16 - 8)); /* ??? */ + flatnessDetThresh = (2 << (pDscInfo->dp.bitsPerPixelX16 - 8)); /* ??? */ + + nvAssert((pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) || + (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_SINGLE)); nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_DSC_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _ENABLE, _TRUE) | - DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _SINGLE) | /* TODO DUAL for 2Head1OR */ + ((pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) ? + DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _DUAL) : + DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _MODE, _SINGLE)) | DRF_NUM(C57D, _HEAD_SET_DSC_CONTROL, _FLATNESS_DET_THRESH, flatnessDetThresh) | DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _FULL_ICH_ERR_PRECISION, _ENABLE) | DRF_DEF(C57D, _HEAD_SET_DSC_CONTROL, _AUTO_RESET, _DISABLE) | @@ -7318,11 +7515,11 @@ static void EvoSetDpDscParams(const NVDispEvoRec *pDispEvo, #define NV_EVO5_NUM_HEAD_SET_DSC_PPS_DATA_DWORDS \ (((NVC57D_HEAD_SET_DSC_PPS_DATA31(0) - NVC57D_HEAD_SET_DSC_PPS_DATA0(0)) / 4) + 1) - ct_assert(NV_EVO5_NUM_HEAD_SET_DSC_PPS_DATA_DWORDS <= ARRAY_LEN(pTimings->dpDsc.pps)); + ct_assert(NV_EVO5_NUM_HEAD_SET_DSC_PPS_DATA_DWORDS <= ARRAY_LEN(pDscInfo->dp.pps)); for (i = 0; i < NV_EVO5_NUM_HEAD_SET_DSC_PPS_DATA_DWORDS; i++) { nvDmaSetStartEvoMethod(pChannel,(NVC57D_HEAD_SET_DSC_PPS_DATA0(head) + (i * 4)), 1); - nvDmaSetEvoMethodData(pChannel, pTimings->dpDsc.pps[i]); + nvDmaSetEvoMethodData(pChannel, pDscInfo->dp.pps[i]); } /* @@ -7342,19 +7539,18 @@ static void EvoSetDpDscParams(const NVDispEvoRec *pDispEvo, static void EvoSetDscParamsC5(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings, + const NVDscInfoEvoRec *pDscInfo, const enum nvKmsPixelDepth pixelDepth) { - - if (pTimings->hdmiFrlConfig.frlRate != HDMI_FRL_DATA_RATE_NONE) { - if (pTimings->hdmiFrlConfig.dscInfo.bEnableDSC) { - EvoSetHdmiFrlDscParams(pDispEvo, head, pTimings, pixelDepth); - } - } else if (pTimings->dpDsc.enable) { - EvoSetDpDscParams(pDispEvo, head, pTimings); + if (pDscInfo->type == NV_DSC_INFO_EVO_TYPE_HDMI) { + EvoSetHdmiDscParams(pDispEvo, head, pDscInfo, pixelDepth); + } else if (pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DP) { + EvoSetDpDscParams(pDispEvo, head, pDscInfo); } else { NVEvoChannelPtr pChannel = pDispEvo->pDevEvo->core; + nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DISABLED); + /* Disable DSC function */ nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_DSC_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, @@ -7365,7 +7561,6 @@ static void EvoSetDscParamsC5(const NVDispEvoRec *pDispEvo, nvDmaSetEvoMethodData(pChannel, DRF_DEF(C57D, _HEAD_SET_DSC_PPS_CONTROL, _ENABLE, _FALSE)); } - } static void @@ -7482,6 +7677,39 @@ EvoGetWindowScalingCapsC3(const NVDevEvoRec *pDevEvo) return &pDevEvo->gpus[0].capabilities.window[0].scalerCaps; } +static void EvoSetMergeModeC5(const NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVEvoMergeMode mode, + NVEvoUpdateState* pUpdateState) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NVEvoChannelPtr pChannel = pDevEvo->core; + NvU32 data = 0x0; + + nvPushEvoSubDevMask(pDevEvo, NVBIT(pDispEvo->displayOwner)); + + nvUpdateUpdateState(pDevEvo, pUpdateState, pChannel); + + switch (mode) { + case NV_EVO_MERGE_MODE_DISABLED: + data = DRF_DEF(C57D, _HEAD_SET_RG_MERGE, _MODE, _DISABLE); + break; + case NV_EVO_MERGE_MODE_SETUP: + data = DRF_DEF(C57D, _HEAD_SET_RG_MERGE, _MODE, _SETUP); + break; + case NV_EVO_MERGE_MODE_PRIMARY: + data = DRF_DEF(C57D, _HEAD_SET_RG_MERGE, _MODE, _MASTER); + break; + case NV_EVO_MERGE_MODE_SECONDARY: + data = DRF_DEF(C57D, _HEAD_SET_RG_MERGE, _MODE, _SLAVE); + break; + } + + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_RG_MERGE(head), 1); + nvDmaSetEvoMethodData(pChannel, data); + + nvPopEvoSubDevMask(pDevEvo); +} NVEvoHAL nvEvoC3 = { EvoSetRasterParamsC3, /* SetRasterParams */ @@ -7536,6 +7764,7 @@ NVEvoHAL nvEvoC3 = { NULL, /* ClearSurfaceUsage */ EvoComputeWindowScalingTapsC3, /* ComputeWindowScalingTaps */ EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + NULL, /* SetMergeMode */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ @@ -7553,6 +7782,7 @@ NVEvoHAL nvEvoC3 = { TRUE, /* supportsSynchronizedOverlayPositionUpdate */ FALSE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ + FALSE, /* supportsMergeMode */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ @@ -7561,7 +7791,7 @@ NVEvoHAL nvEvoC3 = { }; NVEvoHAL nvEvoC5 = { - EvoSetRasterParamsC3, /* SetRasterParams */ + EvoSetRasterParamsC5, /* SetRasterParams */ EvoSetProcAmpC5, /* SetProcAmp */ EvoSetHeadControlC3, /* SetHeadControl */ EvoSetHeadRefClkC3, /* SetHeadRefClk */ @@ -7613,6 +7843,7 @@ NVEvoHAL nvEvoC5 = { NULL, /* ClearSurfaceUsage */ EvoComputeWindowScalingTapsC5, /* ComputeWindowScalingTaps */ EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + EvoSetMergeModeC5, /* SetMergeMode */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ @@ -7630,6 +7861,7 @@ NVEvoHAL nvEvoC5 = { TRUE, /* supportsSynchronizedOverlayPositionUpdate */ FALSE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ + TRUE, /* supportsMergeMode */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ @@ -7638,7 +7870,7 @@ NVEvoHAL nvEvoC5 = { }; NVEvoHAL nvEvoC6 = { - EvoSetRasterParamsC3, /* SetRasterParams */ + EvoSetRasterParamsC6, /* SetRasterParams */ EvoSetProcAmpC5, /* SetProcAmp */ EvoSetHeadControlC3, /* SetHeadControl */ EvoSetHeadRefClkC3, /* SetHeadRefClk */ @@ -7690,6 +7922,7 @@ NVEvoHAL nvEvoC6 = { NULL, /* ClearSurfaceUsage */ EvoComputeWindowScalingTapsC5, /* ComputeWindowScalingTaps */ EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + EvoSetMergeModeC5, /* SetMergeMode */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ @@ -7707,6 +7940,7 @@ NVEvoHAL nvEvoC6 = { TRUE, /* supportsSynchronizedOverlayPositionUpdate */ TRUE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ + TRUE, /* supportsMergeMode */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ diff --git a/src/nvidia-modeset/src/nvkms-flip.c b/src/nvidia-modeset/src/nvkms-flip.c index 5797924550..4c4e0e010c 100644 --- a/src/nvidia-modeset/src/nvkms-flip.c +++ b/src/nvidia-modeset/src/nvkms-flip.c @@ -360,6 +360,109 @@ static void InitNvKmsFlipWorkArea(const NVDevEvoRec *pDevEvo, } } +static void FlipEvoOneApiHead(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const struct NvKmsFlipWorkArea *pWorkArea, + const NvBool allowFlipLock, + NVEvoUpdateState *pUpdateState) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + NvU32 head; + const NVProposedFlipStateOneApiHead *pProposedApiHead = + &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; + const NVT_HDR_STATIC_METADATA *pHdrInfo = + &pInfo->hdr_static_metadata_info; + + nvAssert(nvApiHeadIsActive(pDispEvo, apiHead)); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvFlipEvoOneHead(pDevEvo, sd, head, pHdrInfo, + &pWorkArea->sd[sd].head[head].newState, + allowFlipLock, + pUpdateState); + + if (pProposedApiHead->dirty.hdr) { + /* Update hardware's current colorSpace and colorRange */ + nvUpdateCurrentHardwareColorSpaceAndRangeEvo( + pDispEvo, + head, + pProposedApiHead->hdr.colorSpace, + pProposedApiHead->hdr.colorRange, + pUpdateState); + } + } + + if (pProposedApiHead->dirty.hdr) { + pApiHeadState->attributes.colorSpace = + pProposedApiHead->hdr.colorSpace; + pApiHeadState->attributes.colorBpc = + pProposedApiHead->hdr.colorBpc; + pApiHeadState->attributes.colorRange = + pProposedApiHead->hdr.colorRange; + + if (pProposedApiHead->hdr.tf == NVKMS_OUTPUT_TF_PQ) { + nvCancelSDRTransitionTimer(pApiHeadState); + } else if (pApiHeadState->tf == NVKMS_OUTPUT_TF_PQ) { + ScheduleSDRTransitionTimer(pDispEvo, apiHead); + } + + pApiHeadState->tf = pProposedApiHead->hdr.tf; + + nvUpdateInfoFrames(pDpyEvo); + } + + if (pProposedApiHead->dirty.viewPortPointIn) { + pApiHeadState->viewPortPointIn = + pProposedApiHead->viewPortPointIn; + } +} + +static NvU32 FlipEvo2Head1OrOneDisp(NVDispEvoRec *pDispEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool skipUpdate) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 flip2Heads1OrApiHeadsMask = 0x0; + + for (NvU32 apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NvBool b2Heads1Or = + (nvPopCount32(pApiHeadState->hwHeadsMask) >= 2); + + if (!nvApiHeadIsActive(pDispEvo, apiHead) || !b2Heads1Or) { + continue; + } + + nvkms_memset(&pWorkArea->updateState, 0, + sizeof(pWorkArea->updateState)); + + FlipEvoOneApiHead(pDispEvo, apiHead, pWorkArea, + TRUE /* allowFlipLock */, &pWorkArea->updateState); + + /* + * If api-head is using 2Heads1OR mode then it can not be flip with + * other ap-heads in a single update; because each api-head, which is + * using 2Heads1OR mode, uses different fliplock group and kicking off + * multiple fliplock groups as part of a single update call is not + * supported yet. + */ + pDevEvo->hal->Update(pDevEvo, &pWorkArea->updateState, + TRUE /* releaseElv */); + nvAssert(!skipUpdate); + + flip2Heads1OrApiHeadsMask |= NVBIT(apiHead); + } + + return flip2Heads1OrApiHeadsMask; +} + /*! * Program a flip on all requested layers on all requested heads on * all requested disps in NvKmsFlipRequest. @@ -491,7 +594,7 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, nvPreFlip(pDevEvo, pWorkArea, applyAllowVrr, allowVrr, skipUpdate); for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - NVEvoUpdateState updateState = { }; + NvU32 flip2Heads1OrApiHeadsMask = 0x0; if (!pWorkArea->sd[sd].changed) { continue; @@ -499,64 +602,25 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, pDispEvo = pDevEvo->gpus[sd].pDispEvo; - for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { - NvU32 head; - const NVProposedFlipStateOneApiHead *pProposedApiHead = - &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState; - NVDispApiHeadStateEvoRec *pApiHeadState = - &pDispEvo->apiHeadState[apiHead]; - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; - const NVT_HDR_STATIC_METADATA *pHdrInfo = - &pInfo->hdr_static_metadata_info; - - + flip2Heads1OrApiHeadsMask = + FlipEvo2Head1OrOneDisp(pDispEvo, pWorkArea, skipUpdate); - FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { - nvFlipEvoOneHead(pDevEvo, sd, head, pHdrInfo, - &pWorkArea->sd[sd].head[head].newState, - allowFlipLock, - &updateState); - - if (pProposedApiHead->dirty.hdr) { - /* Update hardware's current colorSpace and colorRange */ - nvUpdateCurrentHardwareColorSpaceAndRangeEvo( - pDispEvo, - head, - pProposedApiHead->hdr.colorSpace, - pProposedApiHead->hdr.colorRange, - &updateState); - } - } + nvkms_memset(&pWorkArea->updateState, 0, + sizeof(pWorkArea->updateState)); - if (pProposedApiHead->dirty.hdr) { - pApiHeadState->attributes.colorSpace = - pProposedApiHead->hdr.colorSpace; - pApiHeadState->attributes.colorBpc = - pProposedApiHead->hdr.colorBpc; - pApiHeadState->attributes.colorRange = - pProposedApiHead->hdr.colorRange; - - if (pProposedApiHead->hdr.tf == NVKMS_OUTPUT_TF_PQ) { - nvCancelSDRTransitionTimer(pApiHeadState); - } else if (pApiHeadState->tf == NVKMS_OUTPUT_TF_PQ) { - ScheduleSDRTransitionTimer(pDispEvo, apiHead); - } - - pApiHeadState->tf = pProposedApiHead->hdr.tf; - - nvUpdateInfoFrames(pDpyEvo); + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + if (!nvApiHeadIsActive(pDispEvo, apiHead) || + ((NVBIT(apiHead) & flip2Heads1OrApiHeadsMask) != 0x0)) { + continue; } - if (pProposedApiHead->dirty.viewPortPointIn) { - pApiHeadState->viewPortPointIn = - pProposedApiHead->viewPortPointIn; - } + FlipEvoOneApiHead(pDispEvo, apiHead, pWorkArea, allowFlipLock, + &pWorkArea->updateState); } if (!skipUpdate) { - pDevEvo->hal->Update(pDevEvo, &updateState, TRUE /* releaseElv */); + pDevEvo->hal->Update(pDevEvo, &pWorkArea->updateState, + TRUE /* releaseElv */); } } diff --git a/src/nvidia-modeset/src/nvkms-hal.c b/src/nvidia-modeset/src/nvkms-hal.c index d7bf0e56db..e98f85ef90 100644 --- a/src/nvidia-modeset/src/nvkms-hal.c +++ b/src/nvidia-modeset/src/nvkms-hal.c @@ -188,13 +188,21 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) * classPrefix | | | | | | | | * | | | | | | | | | */ + /* Ada */ ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + /* Ampere */ ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + /* Turing */ ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + /* Volta */ ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 0, FERMI_GENERIC_KIND, 12, 12), + /* gp10x */ ENTRY_EVO(98, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND, 12, 12), + /* gp100 */ ENTRY_EVO(97, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND, 12, 12), + /* gm20x */ ENTRY_EVO(95, &nvEvo94, 0, 1, 1, FERMI_GENERIC_KIND, 8, 0), + /* gm10x */ ENTRY_EVO(94, &nvEvo94, 0, 0, 1, FERMI_GENERIC_KIND, 8, 0), }; diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c index 0a359387b7..2ffcfa35b0 100644 --- a/src/nvidia-modeset/src/nvkms-hdmi.c +++ b/src/nvidia-modeset/src/nvkms-hdmi.c @@ -1267,6 +1267,32 @@ void nvDpyUpdateHdmiPreModesetEvo(NVDpyEvoPtr pDpyEvo) */ void nvDpyUpdateHdmiVRRCaps(NVDpyEvoPtr pDpyEvo) { + + const NVParsedEdidEvoRec *pParsedEdid = &pDpyEvo->parsedEdid; + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + + const NvBool gpuSupportsHDMIVRR = pDevEvo->hal->caps.supportsHDMIVRR; + + const NvBool dispSupportsVrr = nvDispSupportsVrr(pDispEvo); + + const NvU32 edidVrrMin = pParsedEdid->info.hdmiForumInfo.vrr_min; + + nvAssert(pParsedEdid->valid); + + if (dispSupportsVrr && gpuSupportsHDMIVRR && (edidVrrMin > 0)) { + if (nvDpyIsAdaptiveSyncDefaultlisted(pDpyEvo)) { + pDpyEvo->vrr.type = + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED; + } else { + pDpyEvo->vrr.type = + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED; + } + + pDpyEvo->vrr.needsSwFramePacing = TRUE; + + pDpyEvo->vrr.edidTimeoutMicroseconds = 1000000 / edidVrrMin; + } } void nvRemoveUnusedHdmiDpAudioDevice(const NVDispEvoRec *pDispEvo) @@ -1279,7 +1305,7 @@ void nvRemoveUnusedHdmiDpAudioDevice(const NVDispEvoRec *pDispEvo) // Only connectors with assigned SORs can have audio. if (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR || - pConnectorEvo->or.mask == 0x0) { + pConnectorEvo->or.primary == NV_INVALID_OR) { continue; } @@ -1289,7 +1315,7 @@ void nvRemoveUnusedHdmiDpAudioDevice(const NVDispEvoRec *pDispEvo) // NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS takes a displayId rather than // an SOR index. See bug 1953489. if (nvIsConnectorActiveEvo(pConnectorEvo) && - (pConnectorEvo->or.mask & activeSorMask) != 0x0) { + (NVBIT(pConnectorEvo->or.primary) & activeSorMask) != 0x0) { continue; } @@ -1699,6 +1725,7 @@ void nvHdmiSetVRR(NVDispEvoPtr pDispEvo, NvU32 head, NvBool enable) sizeof(empCtrl)); empCtrl.EnableVRR = enable; + empCtrl.EnableQMS = FALSE; status = NvTiming_ConstructExtendedMetadataPacketInfoframe(&empCtrl, &empInfoFrame); @@ -2002,8 +2029,8 @@ NvBool nvHdmiDpySupportsFrl(const NVDpyEvoRec *pDpyEvo) * * Returns TRUE if FRL is needed, or FALSE otherwise. * */ -static NvBool HdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, - const NVHwModeTimingsEvo *pHwTimings) +NvBool nvHdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, + const NVHwModeTimingsEvo *pHwTimings) { const NvU32 pixelClock = (pHwTimings->yuv420Mode == NV_YUV420_MODE_HW) ? (pHwTimings->pixelClock / 2) : pHwTimings->pixelClock; @@ -2017,11 +2044,47 @@ static NvBool HdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, return pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz; } +static NvU64 GetHdmiFrlLinkRate(HDMI_FRL_DATA_RATE frlRate) +{ + const NvU64 giga = 1000000000ULL; + NvU64 hdmiLinkRate = 0; + switch(frlRate ) + { + case HDMI_FRL_DATA_RATE_NONE: + hdmiLinkRate = 0; + break; + case HDMI_FRL_DATA_RATE_3LANES_3GBPS: + hdmiLinkRate = 3 * giga; + break; + case HDMI_FRL_DATA_RATE_3LANES_6GBPS: + case HDMI_FRL_DATA_RATE_4LANES_6GBPS: + hdmiLinkRate = 6 * giga; + break; + case HDMI_FRL_DATA_RATE_4LANES_8GBPS: + hdmiLinkRate = 8 * giga; + break; + case HDMI_FRL_DATA_RATE_4LANES_10GBPS: + hdmiLinkRate = 10 * giga; + break; + case HDMI_FRL_DATA_RATE_4LANES_12GBPS: + hdmiLinkRate = 12 * giga; + break; + case HDMI_FRL_DATA_RATE_UNSPECIFIED: + nvAssert(!"Unspecified FRL data rate"); + break; + }; + + return hdmiLinkRate; +} + NvBool nvHdmiFrlQueryConfig( const NVDpyEvoRec *pDpyEvo, const NvModeTimings *pModeTimings, - NVHwModeTimingsEvo *pHwTimings, - const struct NvKmsModeValidationParams *pValidationParams) + const NVHwModeTimingsEvo *pHwTimings, + const NvBool b2Heads1Or, + const struct NvKmsModeValidationParams *pValidationParams, + HDMI_FRL_CONFIG *pConfig, + NVDscInfoEvoRec *pDscInfo) { const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; @@ -2031,14 +2094,15 @@ NvBool nvHdmiFrlQueryConfig( NVT_TIMING nvtTiming = { }; NVHDMIPKT_RESULT ret; - if (!nvDpyIsHdmiEvo(pDpyEvo) || - !HdmiTimingsNeedFrl(pDpyEvo, pHwTimings)) { + if (pHwTimings->protocol != NVKMS_PROTOCOL_SOR_HDMI_FRL) { + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); + nvkms_memset(pConfig, 0, sizeof(*pConfig)); return TRUE; } - if (!nvHdmiDpySupportsFrl(pDpyEvo)) { - return FALSE; - } + nvAssert(nvDpyIsHdmiEvo(pDpyEvo) && + nvHdmiDpySupportsFrl(pDpyEvo) && + nvHdmiTimingsNeedFrl(pDpyEvo, pHwTimings)); /* See if we can find an NVT_TIMING for this mode from the EDID. */ pNvtTiming = nvFindEdidNVT_TIMING(pDpyEvo, pModeTimings, pValidationParams); @@ -2102,14 +2166,23 @@ NvBool nvHdmiFrlQueryConfig( videoTransportInfo.packing = HDMI_PIXEL_PACKING_YCbCr420; break; } - /* TODO: implement 2head1or+FRL */ - videoTransportInfo.bDualHeadMode = FALSE; + + videoTransportInfo.bDualHeadMode = b2Heads1Or; clientControl.option = HDMI_QUERY_FRL_HIGHEST_PIXEL_QUALITY; if (pValidationParams->forceDsc) { clientControl.enableDSC = TRUE; } + + /* + * 2Heads1Or requires either YUV420 or DSC; if b2Heads1Or is enabled + * but YUV420 is not, force DSC. + */ + if (b2Heads1Or && (pHwTimings->yuv420Mode != NV_YUV420_MODE_HW)) { + clientControl.enableDSC = TRUE; + } + if (pValidationParams->dscOverrideBitsPerPixelX16 != 0) { clientControl.forceBppx16 = TRUE; clientControl.bitsPerPixelX16 = @@ -2121,7 +2194,54 @@ NvBool nvHdmiFrlQueryConfig( &clientControl, &pDpyEvo->hdmi.srcCaps, &pDpyEvo->hdmi.sinkCaps, - &pHwTimings->hdmiFrlConfig); + pConfig); + + if ((ret == NVHDMIPKT_SUCCESS) && b2Heads1Or) { + /* + * 2Heads1Or requires either YUV420 or DSC; pConfig->dscInfo.bEnableDSC + * is assigned by NvHdmi_QueryFRLConfig(). + */ + nvAssert(pConfig->dscInfo.bEnableDSC || + (pHwTimings->yuv420Mode == NV_YUV420_MODE_HW)); + } + + if (ret == NVHDMIPKT_SUCCESS && (pDscInfo != NULL)) { + const NvU64 hdmiLinkRate = GetHdmiFrlLinkRate(pConfig->frlRate); + + nvAssert((hdmiLinkRate != 0) || + (pConfig->frlRate == HDMI_FRL_DATA_RATE_NONE)); + + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); + + if ((pConfig->frlRate != HDMI_FRL_DATA_RATE_NONE) && + pConfig->dscInfo.bEnableDSC && + (hdmiLinkRate != 0)) { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_HDMI; + pDscInfo->hdmi.dscMode = b2Heads1Or ? + NV_DSC_EVO_MODE_DUAL : NV_DSC_EVO_MODE_SINGLE; + pDscInfo->hdmi.bitsPerPixelX16 = + pConfig->dscInfo.bitsPerPixelX16; + ct_assert(sizeof(pDscInfo->hdmi.pps) == + sizeof(pConfig->dscInfo.pps)); + nvkms_memcpy(pDscInfo->hdmi.pps, + pConfig->dscInfo.pps, + sizeof(pDscInfo->hdmi.pps)); + pDscInfo->hdmi.dscHActiveBytes = + pConfig->dscInfo.dscHActiveBytes; + pDscInfo->hdmi.dscHActiveTriBytes = + pConfig->dscInfo.dscHActiveTriBytes; + pDscInfo->hdmi.dscHBlankTriBytes = + pConfig->dscInfo.dscHBlankTriBytes; + pDscInfo->hdmi.dscTBlankToTTotalRatioX1k = + pConfig->dscInfo.dscTBlankToTTotalRatioX1k; + pDscInfo->hdmi.hblankMin = + NV_UNSIGNED_DIV_CEIL(((pHwTimings->pixelClock * 1000) * + pConfig->dscInfo.dscHBlankTriBytes), + (hdmiLinkRate / 6)); + } else { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DISABLED; + } + } return ret == NVHDMIPKT_SUCCESS; } @@ -2143,7 +2263,7 @@ void nvHdmiFrlSetConfig(NVDispEvoRec *pDispEvo, NvU32 head) const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - HDMI_FRL_CONFIG *pFrlConfig = &pHeadState->timings.hdmiFrlConfig; + HDMI_FRL_CONFIG *pFrlConfig = &pHeadState->hdmiFrlConfig; NVHDMIPKT_RESULT ret; NvU32 retries = 0; const NvU32 MAX_RETRIES = 5; diff --git a/src/nvidia-modeset/src/nvkms-headsurface-config.c b/src/nvidia-modeset/src/nvkms-headsurface-config.c index 6530b53e33..6238a503f5 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-config.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-config.c @@ -1837,21 +1837,16 @@ static void HsConfigInitFlipQueue( } static void HsConfigUpdateSurfaceRefCount( - NVDevEvoPtr pDevEvo, const NVHsChannelConfig *pChannelConfig, NvBool increase) { - HsChangeSurfaceFlipRefCount( - pDevEvo, pChannelConfig->warpMesh.pSurface, increase); + HsChangeSurfaceFlipRefCount(pChannelConfig->warpMesh.pSurface, increase); - HsChangeSurfaceFlipRefCount( - pDevEvo, pChannelConfig->pBlendTexSurface, increase); + HsChangeSurfaceFlipRefCount(pChannelConfig->pBlendTexSurface, increase); - HsChangeSurfaceFlipRefCount( - pDevEvo, pChannelConfig->pOffsetTexSurface, increase); + HsChangeSurfaceFlipRefCount(pChannelConfig->pOffsetTexSurface, increase); - HsChangeSurfaceFlipRefCount( - pDevEvo, pChannelConfig->cursor.pSurfaceEvo, increase); + HsChangeSurfaceFlipRefCount(pChannelConfig->cursor.pSurfaceEvo, increase); } /*! @@ -2263,7 +2258,6 @@ void nvHsConfigStart( */ if (pHsConfigOneHead->pHsChannel != NULL) { HsConfigUpdateSurfaceRefCount( - pDevEvo, &pHsConfigOneHead->channelConfig, TRUE /* increase */); } @@ -2274,7 +2268,6 @@ void nvHsConfigStart( */ if (pDispEvo->pHsChannel[apiHead] != NULL) { HsConfigUpdateSurfaceRefCount( - pDevEvo, &pDispEvo->pHsChannel[apiHead]->config, FALSE /* increase */); } diff --git a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c index 51254f05ed..c3a843cde4 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c @@ -169,8 +169,6 @@ static void HsIoctlSetCursorImage( NVHsChannelEvoRec *pHsChannel, NVSurfaceEvoRec *pSurfaceEvo) { - NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; - /* * Increment the refcnt of the new surface, and * decrement the refcnt of the old surface. @@ -180,10 +178,10 @@ static void HsIoctlSetCursorImage( */ HsChangeSurfaceFlipRefCount( - pDevEvo, pSurfaceEvo, TRUE /* increase */); + pSurfaceEvo, TRUE /* increase */); HsChangeSurfaceFlipRefCount( - pDevEvo, pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); + pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); pHsChannel->config.cursor.pSurfaceEvo = pSurfaceEvo; diff --git a/src/nvidia-modeset/src/nvkms-headsurface.c b/src/nvidia-modeset/src/nvkms-headsurface.c index 0903f9bf52..be7fcf7bc7 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface.c +++ b/src/nvidia-modeset/src/nvkms-headsurface.c @@ -549,22 +549,21 @@ static NvBool HsFlipQueueEntryIsReady( * Update the reference count of all the surfaces described in the pFlipState. */ static void HsUpdateFlipQueueEntrySurfaceRefCount( - NVDevEvoPtr pDevEvo, const NVHsLayerRequestedFlipState *pFlipState, NvBool increase) { HsChangeSurfaceFlipRefCount( - pDevEvo, pFlipState->pSurfaceEvo[NVKMS_LEFT], increase); + pFlipState->pSurfaceEvo[NVKMS_LEFT], increase); HsChangeSurfaceFlipRefCount( - pDevEvo, pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase); + pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase); if (!pFlipState->syncObject.usingSyncpt) { HsChangeSurfaceFlipRefCount( - pDevEvo, pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); + pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); HsChangeSurfaceFlipRefCount( - pDevEvo, pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); + pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); } } @@ -603,7 +602,7 @@ static void HsReleaseFlipQueueEntry( * HeadSurface no longer needs to read from the surfaces in pFlipState; * decrement their reference counts. */ - HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE); + HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE); } /*! @@ -685,7 +684,6 @@ void nvHsPushFlipQueueEntry( const NvU8 layer, const NVHsLayerRequestedFlipState *pFlipState) { - NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; NVHsChannelFlipQueueEntry *pEntry = nvCalloc(1, sizeof(*pEntry)); @@ -702,7 +700,7 @@ void nvHsPushFlipQueueEntry( /* Increment the ref counts on the surfaces in the flip queue entry. */ - HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, &pEntry->hwState, TRUE); + HsUpdateFlipQueueEntrySurfaceRefCount(&pEntry->hwState, TRUE); /* "Fast forward" through existing flip queue entries that are ready. */ @@ -724,7 +722,7 @@ void nvHsPushFlipQueueEntry( * If this function returns TRUE, it is the caller's responsibility to * eventually call * - * HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE) + * HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE) * * for the returned pFlipState. * @@ -2086,6 +2084,17 @@ static NvBool HsCanOmitNonSgHsUpdate(NVHsChannelEvoPtr pHsChannel) const NVSwapGroupRec *pHeadSwapGroup = pHsChannel->pDispEvo->pSwapGroup[pHsChannel->apiHead]; + /* + * When fullscreen swapgroup flipping, updating + * non-swapgroup content at vblank is unnecessary and + * dangerous, since it results in releasing client + * semaphores before their contents have actually been + * displayed. + */ + if (pHsChannel->swapGroupFlipping) { + return NV_TRUE; + } + /* * In the case of a fullscreen swapgroup, we can generally omit updating * the headsurface entirely upon vblank as long as the client is @@ -2099,15 +2108,9 @@ static NvBool HsCanOmitNonSgHsUpdate(NVHsChannelEvoPtr pHsChannel) * config) still require rendering an updated frame to the backbuffer. * Thus, we will simply limit this optimization for frames that come * within one frame time after the last recorded flip. - * - * This doesn't apply with full screen swap group flipping clients, which - * must have one fliplocked hardware flip for each flip IOCTL request, - * and would break if RG interrupt fake flips interfered with the flip - * queue. */ if (pHeadSwapGroup && - pHeadSwapGroup->swapGroupIsFullscreen && - !pHsChannel->swapGroupFlipping) { + pHeadSwapGroup->swapGroupIsFullscreen) { NvU64 nowUs = nvkms_get_usec(); NvU64 frameTimeUs = nvEvoFrametimeUsFromTimings( diff --git a/src/nvidia-modeset/src/nvkms-hw-flip.c b/src/nvidia-modeset/src/nvkms-hw-flip.c index d0445e45c9..1496a0981c 100644 --- a/src/nvidia-modeset/src/nvkms-hw-flip.c +++ b/src/nvidia-modeset/src/nvkms-hw-flip.c @@ -935,6 +935,8 @@ static NvBool UpdateCursorLayerFlipEvoHwState( const struct NvKmsPerOpenDev *pOpenDev, const NVDevEvoRec *pDevEvo, const struct NvKmsFlipCommonParams *pParams, + const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, NVFlipEvoHwState *pFlipState) { if (pParams->cursor.imageSpecified) { @@ -952,7 +954,8 @@ static NvBool UpdateCursorLayerFlipEvoHwState( } if (pParams->cursor.positionSpecified) { - pFlipState->cursor.x = pParams->cursor.position.x; + pFlipState->cursor.x = (pParams->cursor.position.x - + (pTimings->viewPort.in.width * tilePosition)); pFlipState->cursor.y = pParams->cursor.position.y; pFlipState->dirty.cursorPosition = TRUE; @@ -1040,6 +1043,7 @@ NvBool nvUpdateFlipEvoHwState( const NvU32 head, const struct NvKmsFlipCommonParams *pParams, const NVHwModeTimingsEvo *pTimings, + const NvU8 tilePosition, NVFlipEvoHwState *pFlipState, NvBool allowVrr) { @@ -1047,11 +1051,13 @@ NvBool nvUpdateFlipEvoHwState( if (pParams->viewPortIn.specified) { pFlipState->dirty.viewPortPointIn = TRUE; - pFlipState->viewPortPointIn = pParams->viewPortIn.point; + pFlipState->viewPortPointIn.x = pParams->viewPortIn.point.x + + (pTimings->viewPort.in.width * tilePosition); + pFlipState->viewPortPointIn.y = pParams->viewPortIn.point.y; } - if (!UpdateCursorLayerFlipEvoHwState(pOpenDev, pDevEvo, pParams, - pFlipState)) { + if (!UpdateCursorLayerFlipEvoHwState(pOpenDev, pDevEvo, pParams, pTimings, + tilePosition, pFlipState)) { return FALSE; } @@ -1790,7 +1796,7 @@ static void ChangeSurfaceFlipRefCount( if (increase) { nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); } else { - nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); } } } @@ -1876,6 +1882,44 @@ void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, } } +static void IntersectScalingUsageBounds( + const struct NvKmsScalingUsageBounds *a, + const struct NvKmsScalingUsageBounds *b, + struct NvKmsScalingUsageBounds *ret) +{ + ret->maxVDownscaleFactor = NV_MIN(a->maxVDownscaleFactor, + b->maxVDownscaleFactor); + ret->maxHDownscaleFactor = NV_MIN(a->maxHDownscaleFactor, + b->maxHDownscaleFactor); + ret->vTaps = NV_MIN(a->vTaps, b->vTaps); + ret->vUpscalingAllowed = a->vUpscalingAllowed && b->vUpscalingAllowed; +} + +void nvIntersectUsageBounds(const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b, + struct NvKmsUsageBounds *ret) +{ + NvU32 i; + + nvkms_memset(ret, 0, sizeof(*ret)); + + for (i = 0; i < ARRAY_LEN(a->layer); i++) { + nvAssert(a->layer[i].usable == + !!a->layer[i].supportedSurfaceMemoryFormats); + nvAssert(b->layer[i].usable == + !!b->layer[i].supportedSurfaceMemoryFormats); + + ret->layer[i].usable = a->layer[i].usable && b->layer[i].usable; + + ret->layer[i].supportedSurfaceMemoryFormats = + a->layer[i].supportedSurfaceMemoryFormats & + b->layer[i].supportedSurfaceMemoryFormats; + + IntersectScalingUsageBounds(&a->layer[i].scaling, + &b->layer[i].scaling, + &ret->layer[i].scaling); + } +} NvBool UsageBoundsEqual( const struct NvKmsUsageBounds *a, const struct NvKmsUsageBounds *b) @@ -1948,6 +1992,10 @@ NvBool nvAllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, timingsParams[head].activeRmId = pHeadState->activeRmId; timingsParams[head].pixelDepth = pHeadState->pixelDepth; timingsParams[head].pTimings = &pHeadState->timings; + timingsParams[head].enableDsc = (pHeadState->dscInfo.type != + NV_DSC_INFO_EVO_TYPE_DISABLED); + timingsParams[head].b2Heads1Or = + (pHeadState->mergeMode != NV_EVO_MERGE_MODE_DISABLED); nvUnionUsageBounds(pCurrent, pNew, ¤tAndNew[head]); nvUnionUsageBounds(&pHeadState->timings.viewPort.guaranteedUsage, @@ -2178,6 +2226,10 @@ static void LowerDispBandwidth(void *dataPtr, NvU32 dataU32) timingsParams[head].activeRmId = pHeadState->activeRmId; timingsParams[head].pixelDepth = pHeadState->pixelDepth; timingsParams[head].pTimings = &pHeadState->timings; + timingsParams[head].enableDsc = (pHeadState->dscInfo.type != + NV_DSC_INFO_EVO_TYPE_DISABLED); + timingsParams[head].b2Heads1Or = + (pHeadState->mergeMode != NV_EVO_MERGE_MODE_DISABLED); nvUnionUsageBounds(pGuaranteed, pCurrent, &guaranteedAndCurrent[head]); timingsParams[head].pUsage = &guaranteedAndCurrent[head]; @@ -2488,6 +2540,7 @@ void nvPreFlip(NVDevEvoRec *pDevEvo, const NvBool skipUpdate) { NvU32 sd, head; + NVDispEvoRec *pDispEvo; for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { @@ -2523,6 +2576,51 @@ void nvPreFlip(NVDevEvoRec *pDevEvo, nvSetVrrActive(pDevEvo, allowVrr); } + /* + * Update flip metering for Frame pacing smoothing/frame splitting for direct + * drive and adaptive sync VRR, and override the flip timestamp if + * necessary. + */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (NvU32 inputHead = 0; inputHead < pDevEvo->numHeads; inputHead++) { + const NVDispHeadStateEvoRec *pInputHeadState = + &pDispEvo->headState[inputHead]; + const struct NvKmsVrrFramePacingInfo *pInputVrrFramePacingInfo = + &pInputHeadState->vrrFramePacingInfo; + const NvU32 headsMask = pInputHeadState->mergeModeVrrSecondaryHeadMask | + NVBIT(inputHead); + + /* + * XXX[2Heads1OR] Implement per api-head frame pacing and remove this + * mergeMode check and NVDispEvoRec::mergeModeVrrSecondaryHeadMask. + */ + if (pInputHeadState->mergeMode == NV_EVO_MERGE_MODE_SECONDARY) { + continue; + } + +#if defined(DEBUG) + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + const NVFlipEvoHwState *pInputHeadNewState = + &pWorkArea->sd[sd].head[inputHead].newState; + const NVFlipEvoHwState *pNewState = + &pWorkArea->sd[sd].head[head].newState; + + nvAssert(pNewState->dirty.layer[NVKMS_MAIN_LAYER] == + pInputHeadNewState->dirty.layer[NVKMS_MAIN_LAYER]); + } +#endif + + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + NVFlipEvoHwState *pNewState = + &pWorkArea->sd[sd].head[head].newState; + if (pNewState->dirty.layer[NVKMS_MAIN_LAYER]) { + nvTrackAndDelayFlipForVrrSwFramePacing(pDispEvo, + pInputVrrFramePacingInfo, + &pNewState->layer[NVKMS_MAIN_LAYER]); + } + } + } + } } void nvPostFlip(NVDevEvoRec *pDevEvo, @@ -2604,7 +2702,8 @@ NvBool nvAssignNVFlipEvoHwState(NVDevEvoRec *pDevEvo, &pHeadState->timings.viewPort.possibleUsage; if (!nvUpdateFlipEvoHwState(pOpenDev, pDevEvo, sd, head, pParams, - &pHeadState->timings, pFlipHwState, allowVrr)) { + &pHeadState->timings, pHeadState->tilePosition, + pFlipHwState, allowVrr)) { return FALSE; } diff --git a/src/nvidia-modeset/src/nvkms-hw-states.c b/src/nvidia-modeset/src/nvkms-hw-states.c index 184d7ce4dc..a227019aa5 100644 --- a/src/nvidia-modeset/src/nvkms-hw-states.c +++ b/src/nvidia-modeset/src/nvkms-hw-states.c @@ -245,6 +245,28 @@ * change the pin here, prior to enabling flip lock. */ +NvBool nvEvoLockHWStateNoChange(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, + const NvU32 *pHeads) +{ + return TRUE; +} + +NvBool nvEvoLockHWStateMergeMode(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, + const NvU32 *pHeads) +{ + unsigned int i; + + nvAssert(pHeads != NULL && pHeads[0] != NV_INVALID_HEAD); + + for (i = 0; pHeads[i] != NV_INVALID_HEAD; i++) { + const int head = pHeads[i]; + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControlAssy[head]; + pHC->mergeMode = TRUE; + } + + return TRUE; +} + NvBool nvEvoLockHWStateNoLock(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, const NvU32 *pHeads) { @@ -262,6 +284,11 @@ NvBool nvEvoLockHWStateNoLock(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, pHC->clientLock = NV_EVO_NO_LOCK; pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); pHC->clientLockoutWindow = 0; + pHC->mergeMode = FALSE; + pHC->setLockOffsetX = FALSE; + pHC->useStallLockPin = FALSE; + pHC->stallLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + pHC->crashLockUnstallMode = FALSE; /* Reset the flip lock pin to internal, if not needed for SLI */ if (!HEAD_MASK_QUERY(pEvoSubDev->flipLockPinSetForSliHeadMask, head)) { diff --git a/src/nvidia-modeset/src/nvkms-modepool.c b/src/nvidia-modeset/src/nvkms-modepool.c index 0d4a251b74..d8209c1e14 100644 --- a/src/nvidia-modeset/src/nvkms-modepool.c +++ b/src/nvidia-modeset/src/nvkms-modepool.c @@ -1557,28 +1557,51 @@ static NvBool ValidateModeTimings( * particular ViewPort. */ -static void LogViewPort(NVEvoInfoStringPtr pInfoString, - const NVHwModeTimingsEvo *pTimings) +static +void LogViewPort(NVEvoInfoStringPtr pInfoString, + const NVHwModeTimingsEvo timings[NVKMS_MAX_HEADS_PER_DISP], + const NvU32 numHeads) { - const NVHwModeViewPortEvo *pViewPort = &pTimings->viewPort; - const struct NvKmsRect viewPortOut = nvEvoViewPortOutClientView(pTimings); + NvU32 head; + char str[64] = { }, *s = NULL; - /* print the viewport name, size, and taps */ + nvAssert(numHeads <= 2); nvEvoLogInfoString(pInfoString, - "Viewport %dx%d+%d+%d", - viewPortOut.width, - viewPortOut.height, - viewPortOut.x, - viewPortOut.y); + "DualHead Mode: %s", (numHeads > 1) ? "Yes" : "No"); + /* print the viewport name, size, and taps */ + nvkms_memset(str, 0, sizeof(str)); + for (head = 0, s = str; head < numHeads; head++) { + const struct NvKmsRect viewPortOut = + nvEvoViewPortOutClientView(&timings[head]); + size_t n = str + sizeof(str) - s; + s += nvkms_snprintf(s, n, "%s%dx%d+%d+%d", (s != str) ? ", " : "", + viewPortOut.width, viewPortOut.height, + viewPortOut.x, viewPortOut.x); + } nvEvoLogInfoString(pInfoString, - " Horizontal Taps %d", - NVEvoScalerTapsToNum(pViewPort->hTaps)); - + "Viewport %s", str); + + nvkms_memset(str, 0, sizeof(str)); + for (head = 0, s = str; head < numHeads; head++) { + const NVHwModeViewPortEvo *pViewPort = &timings[head].viewPort; + size_t n = str + sizeof(str) - s; + s += nvkms_snprintf(s, n, "%s%d", (s != str) ? ", " : "", + NVEvoScalerTapsToNum(pViewPort->hTaps)); + } + nvEvoLogInfoString(pInfoString, + " Horizontal Taps %s", str); + + nvkms_memset(str, 0, sizeof(str)); + for (head = 0, s = str; head < numHeads; head++) { + const NVHwModeViewPortEvo *pViewPort = &timings[head].viewPort; + size_t n = str + sizeof(str) - s; + s += nvkms_snprintf(s, n, "%s%d", (s != str) ? ", " : "", + NVEvoScalerTapsToNum(pViewPort->vTaps)); + } nvEvoLogInfoString(pInfoString, - " Vertical Taps %d", - NVEvoScalerTapsToNum(pViewPort->hTaps)); + " Vertical Taps %s", str); } /* @@ -1598,14 +1621,28 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, const NvModeTimings *pModeTimings = &pKmsMode->timings; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; - + NvBool b2Heads1Or = FALSE; char localModeName[NV_MAX_MODE_NAME_LEN]; NVHwModeTimingsEvo *pTimingsEvo = nvPreallocGet(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS, sizeof(*pTimingsEvo)); - + HDMI_FRL_CONFIG *pHdmiFrlConfig = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_VALIDATE_MODE_HDMI_FRL_CONFIG, + sizeof(*pHdmiFrlConfig)); + NVDscInfoEvoRec *pDscInfo = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_VALIDATE_MODE_DSC_INFO, + sizeof(*pDscInfo)); + NVHwModeTimingsEvo *impOutTimings = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS, + sizeof(*impOutTimings) * + NVKMS_MAX_HEADS_PER_DISP); + NvU32 impOutNumHeads = 0x0; + NvU32 head; NvBool ret = FALSE; if (modeName[0] == '\0') { @@ -1617,6 +1654,9 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, /* Initialize the EVO hwModeTimings structure */ nvkms_memset(pTimingsEvo, 0, sizeof(*pTimingsEvo)); + nvkms_memset(pHdmiFrlConfig, 0, sizeof(*pHdmiFrlConfig)); + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); + nvkms_memset(impOutTimings, 0, sizeof(*impOutTimings) * NVKMS_MAX_HEADS_PER_DISP); /* begin logging of ModeValidation for this mode */ @@ -1659,10 +1699,27 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, goto done; } - if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, pParams)) { - LogModeValidationEnd(pDispEvo, - pInfoString, "DP Bandwidth check failed"); - goto done; + b2Heads1Or = nvEvoUse2Heads1OR(pDpyEvo, pTimingsEvo, pParams); + + if (nvDpyIsHdmiEvo(pDpyEvo)) { + if (!nvHdmiFrlQueryConfig(pDpyEvo, + &pKmsMode->timings, + pTimingsEvo, + b2Heads1Or, + pParams, + pHdmiFrlConfig, + pDscInfo)) { + LogModeValidationEnd(pDispEvo, pInfoString, + "Unable to determine HDMI 2.1 Fixed Rate Link configuration."); + goto done; + } + } else { + if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, b2Heads1Or, pDscInfo, + pParams)) { + LogModeValidationEnd(pDispEvo, + pInfoString, "DP Bandwidth check failed"); + goto done; + } } /* @@ -1686,24 +1743,49 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, if (!nvGetDefaultColorSpace(&colorFormats, &colorSpace, &colorBpc) || !nvConstructHwModeTimingsImpCheckEvo(pDpyEvo->pConnectorEvo, pTimingsEvo, + (pDscInfo->type != + NV_DSC_INFO_EVO_TYPE_DISABLED), + b2Heads1Or, colorSpace, colorBpc, pParams, - pInfoString, - 0 /* head */)) { + impOutTimings, + &impOutNumHeads, + pInfoString)) { LogModeValidationEnd(pDispEvo, pInfoString, "GPU extended capability check failed"); goto done; } } + nvAssert(impOutNumHeads > 0); + /* Log modevalidation information about the viewport. */ - LogViewPort(pInfoString, pTimingsEvo); + LogViewPort(pInfoString, impOutTimings, impOutNumHeads); - /* Copy out the usage bounds that passed validation */ + /* + * Copy out the usage bounds that passed validation; note we intersect + * the usage bounds across the hardware heads that would be used with + * this apiHead, accumulating the results in pModeUsage. + */ + for (head = 0; head < impOutNumHeads; head++) { + if (head == 0) { + *pModeUsage = impOutTimings[0].viewPort.possibleUsage; + } else { + struct NvKmsUsageBounds *pTmpUsageBounds = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS, + sizeof(*pTmpUsageBounds)); - nvkms_memcpy(pModeUsage, &pTimingsEvo->viewPort.possibleUsage, sizeof(*pModeUsage)); + nvIntersectUsageBounds(pModeUsage, + &impOutTimings[head].viewPort.possibleUsage, + pTmpUsageBounds); + *pModeUsage = *pTmpUsageBounds; + + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS); + } + } /* Whew, if we got this far, the mode is valid. */ @@ -1713,6 +1795,9 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, done: nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_HDMI_FRL_CONFIG); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_DSC_INFO); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS); return ret; } diff --git a/src/nvidia-modeset/src/nvkms-modeset.c b/src/nvidia-modeset/src/nvkms-modeset.c index 566315e63b..3f9d7ea753 100644 --- a/src/nvidia-modeset/src/nvkms-modeset.c +++ b/src/nvidia-modeset/src/nvkms-modeset.c @@ -72,7 +72,7 @@ * TODO: * - Would it be worthwhile to centralize SOR (re)assignment, disp-wide, * in ApplyProposedModeSetHwStateOneDisp() between the calls to - * ApplyProposedModeSetHwStateOneHeadShutDown() and + * ApplyProposedModeSetStateOneApiHeadShutDown() and * ApplyProposedModeSetHwStateOneHeadPreUpdate()? */ @@ -89,6 +89,7 @@ #include "nvkms-private.h" #include "nvkms-vrr.h" #include "nvkms-lut.h" +#include "nvkms-dma.h" #include "dp/nvdp-connector.h" @@ -113,15 +114,15 @@ ClearProposedModeSetHwState(const NVDevEvoRec *pDevEvo, if (!committed) { /* Free new allocated RM display IDs for changed heads */ - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[dispIndex].head[head]; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposed->disp[dispIndex].apiHead[apiHead]; - if (!pProposedHead->changed || - (pProposedHead->activeRmId == 0x0)) { + if (!pProposedApiHead->changed || + (pProposedApiHead->activeRmId == 0x0)) { continue; } - nvRmFreeDisplayId(pDispEvo, pProposedHead->activeRmId); + nvRmFreeDisplayId(pDispEvo, pProposedApiHead->activeRmId); } } @@ -170,18 +171,18 @@ static NvU8 GetAvailableAllowFlipLockGroupValue( * allowFlipLockGroupMask. */ for (dispIndex = 0; dispIndex < ARRAY_LEN(pProposed->disp); dispIndex++) { - NvU32 head; - for (head = 0; - head < ARRAY_LEN(pProposed->disp[dispIndex].head); - head++) { + NvU32 apiHead; + for (apiHead = 0; + apiHead < ARRAY_LEN(pProposed->disp[dispIndex].apiHead); + apiHead++) { - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[dispIndex].head[head]; + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposed->disp[dispIndex].apiHead[apiHead]; - if (pProposedHead->allowFlipLockGroup != 0) { - nvAssert(pProposedHead->allowFlipLockGroup <= 64); + if (pProposedApiHead->allowFlipLockGroup != 0) { + nvAssert(pProposedApiHead->allowFlipLockGroup <= 64); allowFlipLockGroupMask |= - NVBIT64(pProposedHead->allowFlipLockGroup - 1); + NVBIT64(pProposedApiHead->allowFlipLockGroup - 1); } } } @@ -273,7 +274,7 @@ static NvBool GetColorSpaceAndColorRange( const NVDispEvoPtr pDispEvo, const struct NvKmsSetModeOneHeadRequest *pRequestHead, - NVProposedModeSetHwStateOneHead *pProposedHead) + NVProposedModeSetStateOneApiHead *pProposedApiHead) { enum NvKmsDpyAttributeColorRangeValue requestedColorRange; enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace; @@ -309,13 +310,13 @@ GetColorSpaceAndColorRange( * timings and the requested color space and range. */ if (!nvChooseCurrentColorSpaceAndRangeEvo(pOneArbitraryDpyEvo, - pProposedHead->timings.yuv420Mode, - pProposedHead->tf, + pProposedApiHead->timings.yuv420Mode, + pProposedApiHead->tf, requestedColorSpace, requestedColorRange, - &pProposedHead->attributes.colorSpace, - &pProposedHead->attributes.colorBpc, - &pProposedHead->attributes.colorRange)) { + &pProposedApiHead->attributes.colorSpace, + &pProposedApiHead->attributes.colorBpc, + &pProposedApiHead->attributes.colorRange)) { return FALSE; } @@ -325,7 +326,7 @@ GetColorSpaceAndColorRange( */ if (pRequestHead->colorSpaceSpecified) { NvBool ret = FALSE; - switch (pProposedHead->attributes.colorSpace) { + switch (pProposedApiHead->attributes.colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: ret = (pRequestHead->colorSpace == NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_RGB); @@ -351,16 +352,94 @@ GetColorSpaceAndColorRange( * match the proposed color range. */ if (pRequestHead->colorRangeSpecified && - (pProposedHead->attributes.colorRange != pRequestHead->colorRange)) { + (pProposedApiHead->attributes.colorRange != pRequestHead->colorRange)) { return FALSE; } - pProposedHead->colorSpaceSpecified = pRequestHead->colorSpaceSpecified; - pProposedHead->colorRangeSpecified = pRequestHead->colorRangeSpecified; + pProposedApiHead->colorSpaceSpecified = pRequestHead->colorSpaceSpecified; + pProposedApiHead->colorRangeSpecified = pRequestHead->colorRangeSpecified; return TRUE; } +/* count existing unchanged and new vrr heads */ +static NvU32 CountProposedVrrApiHeads(NVDevEvoPtr pDevEvo, + const struct NvKmsSetModeRequest *pRequest) +{ + NvU32 sd; + NVDispEvoPtr pDispEvo; + NvU32 numVRRApiHeads = 0; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 apiHead; + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const struct NvKmsSetModeOneDispRequest *pRequestDisp = + &pRequest->disp[sd]; + const struct NvKmsSetModeOneHeadRequest *pRequestHead = + &pRequestDisp->head[apiHead]; + + if (((pRequest->requestedDispsBitMask & (1 << sd)) == 0) || + ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0)) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + + if (pApiHeadState->timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE) { + numVRRApiHeads++; + } + } else { + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pRequestHead->dpyIdList, pDispEvo); + + if (pDpyEvo == NULL) { + continue; + } + + if (nvGetAllowedDpyVrrType(pDpyEvo, + &pRequestHead->mode.timings, + pRequestHead->modeValidationParams.stereoMode, + pRequestHead->allowGsync, + pRequestHead->allowAdaptiveSync) != + NVKMS_DPY_VRR_TYPE_NONE) { + numVRRApiHeads++; + } + } + } + } + + return numVRRApiHeads; +} + +static void AdjustHwModeTimingsForVrr(const NVDispEvoRec *pDispEvo, + const struct NvKmsSetModeOneHeadRequest *pRequestHead, + const NvU32 prohibitAdaptiveSync, + NVHwModeTimingsEvo *pTimings) +{ + NVDpyEvoPtr pDpyEvo = + nvGetOneArbitraryDpyEvo(pRequestHead->dpyIdList, pDispEvo); + if (pDpyEvo == NULL) { + return; + } + + const NvBool allowGsync = pRequestHead->allowGsync; + const enum NvKmsAllowAdaptiveSync allowAdaptiveSync = + prohibitAdaptiveSync ? NVKMS_ALLOW_ADAPTIVE_SYNC_DISABLED : + pRequestHead->allowAdaptiveSync; + const NvU32 vrrOverrideMinRefreshRate = pRequestHead->vrrOverrideMinRefreshRate; + const enum NvKmsDpyVRRType vrrType = + nvGetAllowedDpyVrrType(pDpyEvo, + &pRequestHead->mode.timings, + pRequestHead->modeValidationParams.stereoMode, + allowGsync, + allowAdaptiveSync); + + nvAdjustHwModeTimingsForVrrEvo(pTimings, + vrrType, + pDpyEvo->vrr.edidTimeoutMicroseconds, + vrrOverrideMinRefreshRate, + pDpyEvo->vrr.needsSwFramePacing); +} + /* * Return whether headSurface is allowed. But, only honor the requestor's * setting if they are the modeset owner. Otherwise, inherit the cached value @@ -377,6 +456,74 @@ NvBool nvGetAllowHeadSurfaceInNvKms(const NVDevEvoRec *pDevEvo, return pDevEvo->allowHeadSurfaceInNvKms; } +static void +InitNVProposedModeSetStateOneApiHead( + const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVProposedModeSetStateOneApiHead *pProposedApiHead) +{ +#if defined(DEBUG) + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pDispEvo->apiHeadState[apiHead].activeDpys, + pDispEvo); +#endif + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + return; + } + + nvAssert(pDispEvo->apiHeadState[apiHead].hwHeadsMask != 0x0); + nvAssert(pDpyEvo != NULL); + + pProposedApiHead->hwHeadsMask = + pDispEvo->apiHeadState[apiHead].hwHeadsMask; + pProposedApiHead->timings = + pDispEvo->apiHeadState[apiHead].timings; + pProposedApiHead->dpyIdList = + pDispEvo->apiHeadState[apiHead].activeDpys; + pProposedApiHead->attributes = + pDispEvo->apiHeadState[apiHead].attributes; + pProposedApiHead->changed = FALSE; + pProposedApiHead->hs10bpcHint = + pDispEvo->apiHeadState[apiHead].hs10bpcHint; + pProposedApiHead->infoFrame = + pDispEvo->apiHeadState[apiHead].infoFrame; + pProposedApiHead->tf = pDispEvo->apiHeadState[apiHead].tf; + pProposedApiHead->viewPortPointIn = + pDispEvo->apiHeadState[apiHead].viewPortPointIn; + + NvU32 head; + NvU32 hwHeadCount = 0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, + head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + nvAssert(pDpyEvo->pConnectorEvo == + pHeadState->pConnectorEvo); + + if (hwHeadCount == 0) { + pProposedApiHead->dscInfo = pHeadState->dscInfo; + pProposedApiHead->activeRmId = pHeadState->activeRmId; + pProposedApiHead->allowFlipLockGroup = + pHeadState->allowFlipLockGroup; + pProposedApiHead->modeValidationParams = + pHeadState->modeValidationParams; + } else { + nvAssert(nvkms_memcmp(&pProposedApiHead->dscInfo, + &pHeadState->dscInfo, + sizeof(pProposedApiHead->dscInfo)) == 0x0); + nvAssert(pProposedApiHead->activeRmId == + pHeadState->activeRmId); + nvAssert(pProposedApiHead->allowFlipLockGroup == + pHeadState->allowFlipLockGroup); + nvAssert(nvkms_memcmp(&pProposedApiHead->modeValidationParams, + &pHeadState->modeValidationParams, + sizeof(pProposedApiHead->modeValidationParams)) == 0x0); + } + } +} + static void InitProposedModeSetHwState(const NVDevEvoRec *pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, @@ -387,58 +534,51 @@ InitProposedModeSetHwState(const NVDevEvoRec *pDevEvo, nvkms_memset(pProposed, 0, sizeof(*pProposed)); - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { - const NVDispHeadStateEvoRec *pHeadState; - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[sd].head[head]; - const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); - - /* - * If the previous modeset can not be inherited then initialize the - * proposed modeset state to shutdown all heads. - */ - if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { + /* + * If the previous modeset can not be inherited then initialize the + * proposed modeset state to shutdown all heads. + */ + if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { NvU32 layer; NVFlipEvoHwState *pFlip = &pProposed->sd[sd].head[head].flip; for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { pFlip->dirty.layer[layer] = TRUE; } - pProposedHead->changed = TRUE; - continue; } - /* - * Case of invalid hardware head is handled inside - * nvInitFlipEvoHwState(). - */ - nvInitFlipEvoHwState(pDevEvo, sd, head, - &pProposed->sd[sd].head[head].flip); - - if (!nvHeadIsActive(pDispEvo, head)) { - continue; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + pProposed->disp[sd].apiHead[apiHead].changed = TRUE; + } + } + } else { + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposed->disp[sd].apiHead[apiHead];; + + InitNVProposedModeSetStateOneApiHead(pDispEvo, apiHead, + pProposedApiHead); + + NvU32 head; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, + head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposed->disp[sd].head[head]; + + nvInitFlipEvoHwState(pDevEvo, sd, head, + &pProposed->sd[sd].head[head].flip); + + pProposedHead->tilePosition = pHeadState->tilePosition; + pProposedHead->timings = pHeadState->timings; + pProposedHead->pConnectorEvo = pHeadState->pConnectorEvo; + pProposedHead->hdmiFrlConfig = pHeadState->hdmiFrlConfig; + pProposedHead->audio = pHeadState->audio; + } } - - pHeadState = &pDispEvo->headState[head]; - - pProposedHead->timings = pHeadState->timings; - pProposedHead->dpyIdList = - pDispEvo->apiHeadState[apiHead].activeDpys; - pProposedHead->pConnectorEvo = pHeadState->pConnectorEvo; - pProposedHead->activeRmId = pHeadState->activeRmId; - pProposedHead->allowFlipLockGroup = pHeadState->allowFlipLockGroup; - pProposedHead->modeValidationParams = - pHeadState->modeValidationParams; - pProposedHead->attributes = - pDispEvo->apiHeadState[apiHead].attributes; - pProposedHead->changed = FALSE; - pProposedHead->hs10bpcHint = - pDispEvo->apiHeadState[apiHead].hs10bpcHint; - pProposedHead->audio = pHeadState->audio; - pProposedHead->infoFrame = - pDispEvo->apiHeadState[apiHead].infoFrame; - pProposedHead->tf = pHeadState->tf; } } } @@ -449,15 +589,11 @@ AssignProposedModeSetNVFlipEvoHwState( const struct NvKmsPerOpenDev *pOpenDev, const NvU32 sd, const NvU32 head, - const struct NvKmsSetModeRequest *pRequest, + const struct NvKmsSetModeOneHeadRequest *pRequestHead, NVFlipEvoHwState *pFlip, - NVProposedModeSetHwStateOneHead *pProposedHead) + NVProposedModeSetHwStateOneHead *pProposedHead, + const NvBool commit) { - const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); - const struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[sd]; - const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[apiHead]; - /* * Clear the flipStates of all layers: * @@ -476,7 +612,7 @@ AssignProposedModeSetNVFlipEvoHwState( nvClearFlipEvoHwState(pFlip); - if (pRequest->commit) { + if (commit) { NvU32 layer; for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { @@ -494,10 +630,7 @@ AssignProposedModeSetNVFlipEvoHwState( * Window channels are interlocked. */ if (pDevEvo->supportsSyncpts && - IsPreSyncptSpecified( - pDevEvo, - head, - &pRequest->disp[sd].head[apiHead].flip)) { + IsPreSyncptSpecified(pDevEvo, head, &pRequestHead->flip)) { return FALSE; } @@ -507,26 +640,12 @@ AssignProposedModeSetNVFlipEvoHwState( head, &pRequestHead->flip, &pProposedHead->timings, + pProposedHead->tilePosition, pFlip, FALSE /* allowVrr */)) { return FALSE; } - /* - * If the modeset is flipping to a depth 30 surface, record this as - * a hint to headSurface, so it can also allocate its surfaces at - * depth 30. - */ - { - const NVSurfaceEvoRec *pSurfaceEvo = - pFlip->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - - pProposedHead->hs10bpcHint = - (pSurfaceEvo != NULL) && - (pSurfaceEvo->format == NvKmsSurfaceMemoryFormatA2B10G10R10 || - pSurfaceEvo->format == NvKmsSurfaceMemoryFormatX2B10G10R10); - } - /* * EVO3 hal simulates USE_CORE_LUT behavior. * NVDisplay window channel does allow to change the input LUT @@ -545,6 +664,330 @@ AssignProposedModeSetNVFlipEvoHwState( return TRUE; } +static +NvBool AssignProposedHwHeadsForDsiConnector( + const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwStateOneDisp *pProposedDisp, + NvU32 *pFreeHwHeadsMask) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 freeHwHeadsMask = *pFreeHwHeadsMask; + NvU32 ret = TRUE; + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + + if (!pProposedApiHead->changed || + nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList) || + (pDpyEvo->pConnectorEvo->signalFormat != + NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI)) { + continue; + } + + if (pProposedApiHead->hwHeadsMask == 0x0) { + /* DSI supports only HEAD0 assignment */ + if ((freeHwHeadsMask & NVBIT(0)) != 0x0) { + nvAssert(pDevEvo->apiHead[apiHead].numLayers <= + pDevEvo->head[0].numLayers); + nvAssignHwHeadsMaskProposedApiHead(pProposedApiHead, 0x1); + freeHwHeadsMask &= ~pProposedApiHead->hwHeadsMask; + } else { + ret = FALSE; + } + } else { + nvAssert(pProposedApiHead->hwHeadsMask == 0x1); + } + + /* There can be only one DSI dpy */ + break; + } + + *pFreeHwHeadsMask &= freeHwHeadsMask; + return ret; +} + +static +NvBool AssignProposedHwHeadsForDPSerializer( + const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwStateOneDisp *pProposedDisp, + NvU32 *pFreeHwHeadsMask) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 freeHwHeadsMask = *pFreeHwHeadsMask; + NvU32 ret = TRUE; + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + + if (!pProposedApiHead->changed || + nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList) || + !nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)) { + continue; + } + + const NvU32 boundHead = pDpyEvo->dp.serializerStreamIndex; + if (pProposedApiHead->hwHeadsMask == 0x0) { + if ((freeHwHeadsMask & NVBIT(boundHead)) != 0x0) { + nvAssert(pDevEvo->apiHead[apiHead].numLayers <= + pDevEvo->head[boundHead].numLayers); + nvAssignHwHeadsMaskProposedApiHead( + pProposedApiHead, NVBIT(boundHead)); + freeHwHeadsMask &= ~pProposedApiHead->hwHeadsMask; + } else { + ret = FALSE; + break; + } + } else { + nvAssert(pProposedApiHead->hwHeadsMask == + NVBIT(boundHead)); + } + } + + *pFreeHwHeadsMask &= freeHwHeadsMask; + return ret; +} + +static NvBool HeadIsFree(const NVDevEvoRec *pDevEvo, + const NvU32 apiHead, + const NvU32 freeHwHeadsMask, + const NvU32 head) +{ + if ((NVBIT(head) & freeHwHeadsMask) == 0x0) { + return FALSE; + } + + if (pDevEvo->apiHead[apiHead].numLayers > + pDevEvo->head[head].numLayers) { + return FALSE; + } + + return TRUE; +} + +static NvU32 GetFree2Heads1ORHeadsMask(const NVDevEvoRec *pDevEvo, + const NvU32 apiHead, + const NvU32 freeHwHeadsMask) +{ + /* + * Hardware allows to setup 2Heads1OR mode + * between head-0 and head-1, or head-2 and head-3 only. + */ + + if (HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, 0) && + HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, 1)) { + return NVBIT(0) | NVBIT(1); + } + + if (HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, 2) && + HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, 3)) { + return NVBIT(2) | NVBIT(3); + } + + return 0; +} + +static NvU32 GetFreeHeads(const NVDevEvoRec *pDevEvo, + const NvU32 apiHead, + const NvU32 freeHwHeadsMask) +{ + NvU32 foundHead = NV_INVALID_HEAD; + + for (NvS32 head = (pDevEvo->numHeads - 1); head >= 0; head--) { + if (HeadIsFree(pDevEvo, apiHead, freeHwHeadsMask, head)) { + if ((foundHead == NV_INVALID_HEAD) || + (pDevEvo->head[head].numLayers < + pDevEvo->head[foundHead].numLayers)) { + foundHead = head; + } + } + } + + return foundHead; +} + +static NvBool AssignProposedHwHeadsGeneric( + const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwStateOneDisp *pProposedDisp, + NvU32 *pFreeHwHeadsMask, + const NvBool b2Heads1Or) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 freeHwHeadsMask = *pFreeHwHeadsMask; + NvU32 ret = TRUE; + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + + if (!pProposedApiHead->changed || + nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList) || + (pProposedApiHead->hwHeadsMask != 0x0)) { + continue; + } + + /* + * The hardware-head assigment for the DSI and dp-serializer dpys + * should be already done. + */ + nvAssert((pDpyEvo->pConnectorEvo->signalFormat != + NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) && + !nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)); + + NvU32 foundHeadsMask = 0x0; + + if (b2Heads1Or) { + if (!nvEvoUse2Heads1OR( + pDpyEvo, + &pProposedApiHead->timings, + &pProposedApiHead->modeValidationParams)) { + continue; + } + foundHeadsMask = GetFree2Heads1ORHeadsMask(pDevEvo, apiHead, + freeHwHeadsMask); + } else { + nvAssert(!nvEvoUse2Heads1OR( + pDpyEvo, + &pProposedApiHead->timings, + &pProposedApiHead->modeValidationParams)); + + NvU32 foundHead = GetFreeHeads(pDevEvo, apiHead, freeHwHeadsMask); + if (foundHead != NV_INVALID_HEAD) { + foundHeadsMask = NVBIT(foundHead); + } + } + + if (foundHeadsMask != 0x0) { + nvAssignHwHeadsMaskProposedApiHead( + pProposedApiHead, foundHeadsMask); + freeHwHeadsMask &= ~pProposedApiHead->hwHeadsMask; + } else { + ret = FALSE; + goto done; + } + } + +done: + *pFreeHwHeadsMask &= freeHwHeadsMask; + return ret; +} + +static void ClearHwHeadsMaskOneApiHead(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVProposedModeSetHwState *pProposed) +{ + const NvU32 sd = pDispEvo->displayOwner; + NVProposedModeSetHwStateOneDisp *pProposedDisp = + &pProposed->disp[sd]; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + NvU32 head; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + nvkms_memset(&pProposedDisp->head[head], + 0, sizeof(pProposedDisp->head[head])); + nvkms_memset(&pProposed->sd[sd].head[head], + 0, sizeof(pProposed->sd[sd].head[head])); + } + nvAssignHwHeadsMaskProposedApiHead(pProposedApiHead, 0); +} + +static +void ClearIncompatibleHwHeadsMaskOneDisp(const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwState *pProposed) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + NVProposedModeSetHwStateOneDisp *pProposedDisp = + &pProposed->disp[sd]; + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + if (!pProposedApiHead->changed || (pDpyEvo == NULL)) { + continue; + } + + NvBool current2Heads1OrState = + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1); + + const NvBool new2Heads1OrState = + nvEvoUse2Heads1OR(pDpyEvo, + &pProposedApiHead->timings, + &pProposedApiHead->modeValidationParams); + + if (new2Heads1OrState != current2Heads1OrState) { + ClearHwHeadsMaskOneApiHead(pDispEvo, apiHead, pProposed); + } + } +} + +static +NvBool AssignProposedHwHeadsOneDisp(const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwState *pProposed) +{ + const NvU32 sd = pDispEvo->displayOwner; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NVProposedModeSetHwStateOneDisp *pProposedDisp = + &pProposed->disp[sd]; + NvU32 freeHwHeadsMask; + /* + * In first pass, keep the all existing api-head to + * hardware-head(s) assignment unchanged. + */ + NvU32 pass = 0; + + ClearIncompatibleHwHeadsMaskOneDisp(pDispEvo, pProposed); + +repeatHwHeadsAssigment: + freeHwHeadsMask = NVBIT(pDevEvo->numHeads) - 1; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + nvAssert((pProposedApiHead->hwHeadsMask == 0) || + !nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList)); + freeHwHeadsMask &= ~pProposedApiHead->hwHeadsMask; + } + + if (!AssignProposedHwHeadsForDsiConnector(pDispEvo, pProposedDisp, + &freeHwHeadsMask) || + !AssignProposedHwHeadsForDPSerializer(pDispEvo, pProposedDisp, + &freeHwHeadsMask) || + !AssignProposedHwHeadsGeneric(pDispEvo, pProposedDisp, + &freeHwHeadsMask, + TRUE /* b2Heads1Or */) || + !AssignProposedHwHeadsGeneric(pDispEvo, pProposedDisp, + &freeHwHeadsMask, + FALSE /* b2Heads1Or */)) { + if (pass == 1) { + return FALSE; + } + + /* + * In second pass, do the fresh hardware-head(s) assigment for + * the all changed api-heads. + */ + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (pProposedDisp->apiHead[apiHead].changed) { + ClearHwHeadsMaskOneApiHead(pDispEvo, apiHead, pProposed); + } + } + pass = 1; + goto repeatHwHeadsAssigment; + } + + return TRUE; +} + /*! * Assign the NVProposedModeSetHwState structure. * @@ -577,6 +1020,10 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, NVDispEvoPtr pDispEvo; NvBool ret = TRUE; NvU8 allowFlipLockGroup = 0; + /* If more than one head will enable VRR on Pascal, disallow Adaptive-Sync */ + const enum NvKmsAllowAdaptiveSync prohibitAdaptiveSync = + (!pDevEvo->hal->caps.supportsDisplayRate && + (CountProposedVrrApiHeads(pDevEvo, pRequest) > 1)); /* Initialize pProposed with the current hardware configuration. */ InitProposedModeSetHwState(pDevEvo, pOpenDev, pProposed); @@ -589,7 +1036,6 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { const struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[sd]; - NvU32 head; if ((pRequest->requestedDispsBitMask & (1 << sd)) == 0) { continue; @@ -600,12 +1046,12 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, pDispEvo = pDevEvo->pDispEvo[sd]; - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); + /* Construct the per api head proposed modeset state */ + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { const struct NvKmsSetModeOneHeadRequest *pRequestHead = &pRequestDisp->head[apiHead]; - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; const NVDpyEvoRec *pDpyEvo; if ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0) { @@ -624,17 +1070,17 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, * Clear the pProposedHead, so that no state leaks to the new * configuration. */ - nvkms_memset(pProposedHead, 0, sizeof(*pProposedHead)); - pProposedHead->changed = TRUE; + ClearHwHeadsMaskOneApiHead(pDispEvo, apiHead, pProposed); + nvkms_memset(pProposedApiHead, 0, sizeof(*pProposedApiHead)); + pProposedApiHead->changed = TRUE; continue; } - pProposedHead->changed = TRUE; - pProposedHead->dpyIdList = pRequestHead->dpyIdList; - pProposedHead->pConnectorEvo = pDpyEvo->pConnectorEvo; - pProposedHead->activeRmId = - nvRmAllocDisplayId(pDispEvo, pProposedHead->dpyIdList); - if (pProposedHead->activeRmId == 0x0) { + pProposedApiHead->changed = TRUE; + pProposedApiHead->dpyIdList = pRequestHead->dpyIdList; + pProposedApiHead->activeRmId = + nvRmAllocDisplayId(pDispEvo, pProposedApiHead->dpyIdList); + if (pProposedApiHead->activeRmId == 0x0) { /* XXX Need separate error code? */ pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY; @@ -642,8 +1088,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, continue; } - /* Verify that the requested dpys are valid on this head. */ - if ((pProposedHead->pConnectorEvo->validHeadMask & NVBIT(head)) == 0) { + if ((nvDpyGetPossibleApiHeadsMask(pDpyEvo) & NVBIT(apiHead)) == 0) { pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY; ret = FALSE; @@ -657,48 +1102,56 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, * head so that if additional heads fail, we can report * more complete failure information to the client. */ - if (!nvGetHwModeTimings(pDispEvo, pRequestHead, - &pProposedHead->timings, &pProposedHead->infoFrame.ctrl)) { + if (!nvGetHwModeTimings(pDispEvo, + pRequestHead, + &pProposedApiHead->timings, + &pProposedApiHead->infoFrame.ctrl)) { pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; continue; } - pProposedHead->stereo.mode = + AdjustHwModeTimingsForVrr(pDispEvo, + pRequestHead, + prohibitAdaptiveSync, + &pProposedApiHead->timings); + + pProposedApiHead->stereo.mode = pRequestHead->modeValidationParams.stereoMode; - pProposedHead->stereo.isAegis = pDpyEvo->stereo3DVision.isAegis; - pProposedHead->infoFrame.hdTimings = - nvEvoIsHDQualityVideoTimings(&pProposedHead->timings); + pProposedApiHead->stereo.isAegis = pDpyEvo->stereo3DVision.isAegis; + pProposedApiHead->infoFrame.hdTimings = + nvEvoIsHDQualityVideoTimings(&pProposedApiHead->timings); - pProposedHead->allowFlipLockGroup = 0; - pProposedHead->modeValidationParams = + pProposedApiHead->allowFlipLockGroup = 0; + pProposedApiHead->modeValidationParams = pRequestHead->modeValidationParams; - if (!GetColorSpaceAndColorRange(pDispEvo, pRequestHead, pProposedHead)) { + if (!GetColorSpaceAndColorRange(pDispEvo, pRequestHead, + pProposedApiHead)) { pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; continue; } - pProposedHead->attributes.digitalSignal = - nvGetDefaultDpyAttributeDigitalSignalValue(pProposedHead->pConnectorEvo); - if (pProposedHead->timings.hdmiFrlConfig.frlRate != - HDMI_FRL_DATA_RATE_NONE) { - nvAssert(pProposedHead->attributes.digitalSignal == + pProposedApiHead->attributes.digitalSignal = + nvGetDefaultDpyAttributeDigitalSignalValue(pDpyEvo->pConnectorEvo); + if (pProposedApiHead->timings.protocol == + NVKMS_PROTOCOL_SOR_HDMI_FRL) { + nvAssert(pProposedApiHead->attributes.digitalSignal == NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_TMDS); - pProposedHead->attributes.digitalSignal = + pProposedApiHead->attributes.digitalSignal = NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_HDMI_FRL; } - pProposedHead->attributes.dvc = + pProposedApiHead->attributes.dvc = pDpyEvo->currentAttributes.dvc; /* Image sharpening is available when scaling is enabled. */ - pProposedHead->attributes.imageSharpening.available = - nvIsImageSharpeningAvailable(&pProposedHead->timings.viewPort); - pProposedHead->attributes.imageSharpening.value = + pProposedApiHead->attributes.imageSharpening.available = + nvIsImageSharpeningAvailable(&pProposedApiHead->timings.viewPort); + pProposedApiHead->attributes.imageSharpening.value = pDpyEvo->currentAttributes.imageSharpening.value; /* @@ -708,41 +1161,156 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, * keep them disabled by default. */ if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { - pProposedHead->lut = pRequestHead->lut; + pProposedApiHead->lut = pRequestHead->lut; if (!pRequestHead->lut.input.specified) { - pProposedHead->lut.input.specified = TRUE; - pProposedHead->lut.input.end = 0; + pProposedApiHead->lut.input.specified = TRUE; + pProposedApiHead->lut.input.end = 0; } if (!pRequestHead->lut.output.specified) { - pProposedHead->lut.output.specified = TRUE; - pProposedHead->lut.output.enabled = FALSE; + pProposedApiHead->lut.output.specified = TRUE; + pProposedApiHead->lut.output.enabled = FALSE; } } else if (pRequestHead->lut.input.specified) { - pProposedHead->lut = pRequestHead->lut; + pProposedApiHead->lut = pRequestHead->lut; } else { - pProposedHead->lut.input.specified = FALSE; + pProposedApiHead->lut.input.specified = FALSE; } - if (!AssignProposedModeSetNVFlipEvoHwState( - pDevEvo, - pOpenDev, - sd, - head, - pRequest, - &pProposed->sd[sd].head[head].flip, - pProposedHead)) { + if (pRequestHead->flip.viewPortIn.specified) { + pProposedApiHead->viewPortPointIn = + pRequestHead->flip.viewPortIn.point; + } + } /* apiHead */ + + if (!AssignProposedHwHeadsOneDisp(pDispEvo, pProposed)) { + pReply->disp[sd].status = + NVKMS_SET_MODE_ONE_DISP_STATUS_FAILED_TO_ASSIGN_HARDWARE_HEADS; + ret = FALSE; + continue; + } + + /* + * Construct the per hardware head proposed modeset/flip state, and + * assign the dependant per api head modeset parameters. + */ + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const struct NvKmsSetModeOneHeadRequest *pRequestHead; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NvU32 primaryHead = + nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); + const NvU32 numTiles = nvPopCount32(pProposedApiHead->hwHeadsMask); + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + NVProposedModeSetHwStateOneHead *pProposedPrimaryHead; + NvU32 secondaryHeadTilePosition = 1; + NvU32 head; + + nvAssert((pProposedApiHead->hwHeadsMask != 0x0) || + (pDpyEvo == NULL)); + + if (!pProposedApiHead->changed || + (pProposedApiHead->hwHeadsMask == 0x0)) { + continue; + } + + nvAssert(primaryHead != NV_INVALID_HEAD); + pProposedPrimaryHead = &pProposedDisp->head[primaryHead]; + + nvAssert((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) != 0); + pRequestHead = &pRequestDisp->head[apiHead]; + + enum NvKmsSetModeOneHeadStatus status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposedDisp->head[head]; + + pProposedHead->tilePosition = + (head == primaryHead) ? 0 : (secondaryHeadTilePosition++); + + if (!nvEvoGetSingleTileHwModeTimings(&pProposedApiHead->timings, + numTiles, + &pProposedHead->timings)) { + status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; + break; + } + + /* + * Broadcast the connector and the requested flip state across + * the corresponding hardware heads. + */ + pProposedHead->pConnectorEvo = pDpyEvo->pConnectorEvo; + if (!AssignProposedModeSetNVFlipEvoHwState( + pDevEvo, + pOpenDev, + sd, + head, + &pRequest->disp[sd].head[apiHead], + &pProposed->sd[sd].head[head].flip, + pProposedHead, + pRequest->commit)) { + status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + break; + } + } + + if (status != NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS) { + pReply->disp[sd].head[apiHead].status = status; + ret = FALSE; + continue; /* next api head */ + } + + nvAssert(nvPopCount32(pProposedApiHead->hwHeadsMask) <= 2); + + /* + * Query the per api head HDMI FRL configuration, and pass it to + * the primary head. Save the dsc info into the per api head + * proposed modeset state, to broadcast it onto all hardware heads + * during modeset. + */ + if (!nvHdmiFrlQueryConfig(pDpyEvo, + &pRequestHead->mode.timings, + &pProposedApiHead->timings, + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1) + /* b2Heads1Or */, + &pProposedApiHead->modeValidationParams, + &pProposedPrimaryHead->hdmiFrlConfig, + &pProposedApiHead->dscInfo)) { pReply->disp[sd].head[apiHead].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; - continue; /* next head */ + continue; } - /* Construct audio state */ - nvHdmiDpConstructHeadAudioState(pProposedHead->activeRmId, - pDpyEvo, &pProposedHead->audio); - } /* head */ + /* + * Construct the api head audio state, and pass it + * to the primary hardware head. + */ + nvHdmiDpConstructHeadAudioState(pProposedApiHead->activeRmId, + pDpyEvo, + &pProposedPrimaryHead->audio); + + /* + * If the modeset is flipping to a depth 30 surface, record this as + * a hint to headSurface, so it can also allocate its surfaces at + * depth 30. + */ + { + const NVFlipEvoHwState *pFlip = + &pProposed->sd[sd].head[primaryHead].flip; + const NVSurfaceEvoRec *pSurfaceEvo = + pFlip->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; + + pProposedApiHead->hs10bpcHint = + (pSurfaceEvo != NULL) && + ((pSurfaceEvo->format == NvKmsSurfaceMemoryFormatA2B10G10R10) || + (pSurfaceEvo->format == NvKmsSurfaceMemoryFormatX2B10G10R10)); + } + } /* apiHead */ } /* pDispEvo */ /* Assign allowFlipLockGroup for the heads specified in the request. */ @@ -750,19 +1318,15 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, allowFlipLockGroup = GetAvailableAllowFlipLockGroupValue(pProposed); FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - - NvU32 head; - if ((pRequest->requestedDispsBitMask & NVBIT(sd)) == 0) { continue; } - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { const struct NvKmsSetModeOneHeadRequest *pRequestHead = &pRequest->disp[sd].head[apiHead]; - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[sd].head[head]; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposed->disp[sd].apiHead[apiHead]; if ((pRequest->disp[sd].requestedHeadsBitMask & NVBIT(apiHead)) == 0) { @@ -770,7 +1334,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, } if (pRequestHead->allowFlipLock) { - pProposedHead->allowFlipLockGroup = allowFlipLockGroup; + pProposedApiHead->allowFlipLockGroup = allowFlipLockGroup; } } } @@ -805,25 +1369,27 @@ ValidateProposedModeSetHwStateOneDispImp(NVDispEvoPtr pDispEvo, NVValidateImpOneDispHeadParamsRec timingsParams[NVKMS_MAX_HEADS_PER_DISP]; NvBool skipImpCheck = TRUE, requireBootClocks = FALSE; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 head, downgradePossibleHeadsBitMask = 0; + NvU32 downgradePossibleHeadsBitMask = 0; NVEvoReallocateBandwidthMode reallocBandwidth = pDevEvo->isSOCDisplay ? NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE : NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE; nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; const NvBool skipImpCheckThisHead = - (pProposedHead->modeValidationParams.overrides & + (pProposedApiHead->modeValidationParams.overrides & NVKMS_MODE_VALIDATION_NO_EXTENDED_GPU_CAPABILITIES_CHECK) != 0; const NvBool requireBootClocksThisHead = - (pProposedHead->modeValidationParams.overrides & + (pProposedApiHead->modeValidationParams.overrides & NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS) != 0; + NvU32 head; + /* * Don't try to downgrade heads which are not marked as changed. * This could lead to unchanged/not-requested heads hogging all @@ -835,22 +1401,28 @@ ValidateProposedModeSetHwStateOneDispImp(NVDispEvoPtr pDispEvo, * to handle it. This seems to be a fair trade-off for Orin, as by * default all heads are initialized with minimal usage bounds. */ - if (pProposedHead->changed) { - downgradePossibleHeadsBitMask |= NVBIT(head); + if (pProposedApiHead->changed) { + downgradePossibleHeadsBitMask |= pProposedApiHead->hwHeadsMask; } - if (pProposedHead->pConnectorEvo == NULL) { - continue; - } + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposedDisp->head[head]; - timingsParams[head].pConnectorEvo = pProposedHead->pConnectorEvo; - timingsParams[head].activeRmId = pProposedHead->activeRmId; - timingsParams[head].pixelDepth = - nvEvoColorSpaceBpcToPixelDepth(pProposedHead->attributes.colorSpace, - pProposedHead->attributes.colorBpc); - timingsParams[head].pTimings = &pProposedHead->timings; - timingsParams[head].pUsage = - &pProposedHead->timings.viewPort.guaranteedUsage; + timingsParams[head].pConnectorEvo = pProposedHead->pConnectorEvo; + timingsParams[head].activeRmId = pProposedApiHead->activeRmId; + timingsParams[head].pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorBpc); + timingsParams[head].pTimings = &pProposedHead->timings; + timingsParams[head].enableDsc = (pProposedApiHead->dscInfo.type != + NV_DSC_INFO_EVO_TYPE_DISABLED); + nvAssert(nvPopCount32(pProposedApiHead->hwHeadsMask) <= 2); + timingsParams[head].b2Heads1Or = + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1); + timingsParams[head].pUsage = + &pProposedHead->timings.viewPort.guaranteedUsage; + } skipImpCheck = skipImpCheck && skipImpCheckThisHead; requireBootClocks = requireBootClocks || requireBootClocksThisHead; @@ -877,25 +1449,27 @@ ValidateProposedModeSetHwStateOneDispImp(NVDispEvoPtr pDispEvo, return FALSE; } - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - const struct NvKmsUsageBounds *pProposedUsage; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + NvU32 head; - if (pProposedHead->pConnectorEvo == NULL) { - continue; - } + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposedDisp->head[head]; + const struct NvKmsUsageBounds *pProposedUsage; + + if (pProposedApiHead->changed) { + pProposedUsage = &pProposed->sd[0].head[head].flip.usage; + } else { + pProposedUsage = + &pDevEvo->gpus[0].headState[head].preallocatedUsage; + } - if (pProposedHead->changed) { - pProposedUsage = &pProposed->sd[0].head[head].flip.usage; - } else { - pProposedUsage = - &pDevEvo->gpus[0].headState[head].preallocatedUsage; + nvUnionUsageBounds(&pProposedHead->timings.viewPort.guaranteedUsage, + pProposedUsage, &guaranteedAndProposed[head]); + timingsParams[head].pUsage = &guaranteedAndProposed[head]; } - - nvUnionUsageBounds(&pProposedHead->timings.viewPort.guaranteedUsage, - pProposedUsage, &guaranteedAndProposed[head]); - timingsParams[head].pUsage = &guaranteedAndProposed[head]; } ret = nvValidateImpOneDisp(pDispEvo, timingsParams, @@ -917,24 +1491,24 @@ ValidateProposedModeSetHwStateOneDispImp(NVDispEvoPtr pDispEvo, } static NvBool SkipDisplayPortBandwidthCheck( - const NVProposedModeSetHwStateOneHead *pProposedHead) + const NVProposedModeSetStateOneApiHead *pProposedApiHead) { - return (pProposedHead->modeValidationParams.overrides & + return (pProposedApiHead->modeValidationParams.overrides & NVKMS_MODE_VALIDATION_NO_DISPLAYPORT_BANDWIDTH_CHECK) != 0; } static NvBool DowngradeColorSpaceAndBpcOneHead( const NVDispEvoRec *pDispEvo, - NVProposedModeSetHwStateOneHead *pProposedHead) + NVProposedModeSetStateOneApiHead *pProposedApiHead) { enum NvKmsDpyAttributeColorRangeValue colorRange = - pProposedHead->attributes.colorRange; + pProposedApiHead->attributes.colorRange; enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = - pProposedHead->attributes.colorSpace; + pProposedApiHead->attributes.colorSpace; enum NvKmsDpyAttributeColorBpcValue colorBpc = - pProposedHead->attributes.colorBpc; + pProposedApiHead->attributes.colorBpc; NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); const NVColorFormatInfoRec supportedColorFormats = nvGetColorFormatInfo(pDpyEvo); @@ -944,19 +1518,19 @@ static NvBool DowngradeColorSpaceAndBpcOneHead( return FALSE; } - if (pProposedHead->colorRangeSpecified && - (colorRange != pProposedHead->attributes.colorRange)) { + if (pProposedApiHead->colorRangeSpecified && + (colorRange != pProposedApiHead->attributes.colorRange)) { return FALSE; } - if (pProposedHead->colorSpaceSpecified && - (colorSpace != pProposedHead->attributes.colorSpace)) { + if (pProposedApiHead->colorSpaceSpecified && + (colorSpace != pProposedApiHead->attributes.colorSpace)) { return FALSE; } - pProposedHead->attributes.colorRange = colorRange; - pProposedHead->attributes.colorSpace = colorSpace; - pProposedHead->attributes.colorBpc = colorBpc; + pProposedApiHead->attributes.colorRange = colorRange; + pProposedApiHead->attributes.colorSpace = colorSpace; + pProposedApiHead->attributes.colorBpc = colorBpc; return TRUE; } @@ -967,24 +1541,27 @@ static NvBool DowngradeColorSpaceAndBpcOneDisp( const NVConnectorEvoRec *pConnectorEvo) { NvBool ret = FALSE; - NvU32 head; + NvU32 apiHead; /* * In DP-MST case, many heads can share same connector and dp-bandwidth * therefore its necessary to validate and downgrade dp-pixel-depth across * all head which are sharing same connector before retry. */ - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + for (apiHead = 0; apiHead < pDispEvo->pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); - if (!pProposedHead->changed || - SkipDisplayPortBandwidthCheck(pProposedHead)) { + if (!pProposedApiHead->changed || + SkipDisplayPortBandwidthCheck(pProposedApiHead)) { continue; } - if ((pProposedHead->pConnectorEvo == pConnectorEvo) && - DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedHead)) { + if ((pDpyEvo != NULL) && + (pDpyEvo->pConnectorEvo == pConnectorEvo) && + DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedApiHead)) { ret = TRUE; } } @@ -1005,9 +1582,8 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( NVDispEvoPtr pDispEvo, NVProposedModeSetHwStateOneDisp *pProposedDisp) { - NvU32 head; NvBool bResult = TRUE, bTryAgain = FALSE; - + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; tryAgain: @@ -1016,26 +1592,35 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( nvDPBeginValidation(pDispEvo); - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - NVHwModeTimingsEvoPtr pTimings = &pProposedHead->timings; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NvU32 primaryHead = + nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + const NvBool b2Heads1Or = + nvPopCount32(pProposedApiHead->hwHeadsMask) > 1; - if ((pProposedHead->pConnectorEvo == NULL) || - SkipDisplayPortBandwidthCheck(pProposedHead)) { + nvAssert(nvPopCount32(pProposedApiHead->hwHeadsMask) <= 2); + + if ((pDpyEvo == NULL) || + SkipDisplayPortBandwidthCheck(pProposedApiHead)) { continue; } bResult = !!nvDPLibValidateTimings(pDispEvo, - head, - pProposedHead->activeRmId, - pProposedHead->dpyIdList, - pProposedHead->attributes.colorSpace, - pProposedHead->attributes.colorBpc, - &pProposedHead->modeValidationParams, - pTimings); - - if (!bResult && pProposedHead->changed) { + primaryHead, + pProposedApiHead->activeRmId, + pProposedApiHead->dpyIdList, + pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorBpc, + &pProposedApiHead->modeValidationParams, + &pProposedApiHead->timings, + b2Heads1Or, + &pProposedApiHead->dscInfo); + + if (!bResult && pProposedApiHead->changed) { /* * First, try to downgrade the pixel depth for this current head. @@ -1044,10 +1629,10 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( * changed heads which are sharing same connector and dp-bandwidth. */ - if (DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedHead) || + if (DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedApiHead) || DowngradeColorSpaceAndBpcOneDisp(pDispEvo, pProposedDisp, - pProposedHead->pConnectorEvo)) { + pDpyEvo->pConnectorEvo)) { bTryAgain = TRUE; } @@ -1075,25 +1660,40 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( } if (bResult) { - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NvU32 primaryHead = + nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + NVProposedModeSetHwStateOneHead *pProposedPrimaryHead; + + nvAssert((pProposedApiHead->hwHeadsMask != 0x0) || + (pDpyEvo == NULL)); + + if ((pProposedApiHead->hwHeadsMask == 0x0)) { + continue; + } - if ((pProposedHead->pConnectorEvo == NULL) || - !nvConnectorUsesDPLib(pProposedHead->pConnectorEvo)) { - pProposedHead->pDpLibModesetState = NULL; + nvAssert(primaryHead != NV_INVALID_HEAD); + pProposedPrimaryHead = &pProposedDisp->head[primaryHead]; + + if (!nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { + pProposedPrimaryHead->pDpLibModesetState = NULL; continue; } - pProposedHead->pDpLibModesetState = + pProposedPrimaryHead->pDpLibModesetState = nvDPLibCreateModesetState(pDispEvo, - head, - pProposedHead->activeRmId, - pProposedHead->dpyIdList, - pProposedHead->attributes.colorSpace, - pProposedHead->attributes.colorBpc, - &pProposedHead->timings); - if (pProposedHead->pDpLibModesetState == NULL) { + primaryHead, + pProposedApiHead->activeRmId, + pProposedApiHead->dpyIdList, + pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorBpc, + &pProposedApiHead->timings, + &pProposedApiHead->dscInfo); + if (pProposedPrimaryHead->pDpLibModesetState == NULL) { return FALSE; } } @@ -1154,17 +1754,16 @@ ValidateProposedModeSetHwStateOneDisp( { const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NVDpyIdList dpyIdList; - NvU32 head; /* * Check that the requested configuration of connectors can be * driven simultaneously. */ dpyIdList = nvEmptyDpyIdList(); - for (head = 0; head < pDevEvo->numHeads; head++) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVDpyEvoPtr pDpyEvo; FOR_ALL_EVO_DPYS(pDpyEvo, - pProposedDisp->head[head].dpyIdList, pDispEvo) { + pProposedDisp->apiHead[apiHead].dpyIdList, pDispEvo) { dpyIdList = nvAddDpyIdToDpyIdList(pDpyEvo->pConnectorEvo->displayId, dpyIdList); } @@ -1179,15 +1778,15 @@ ValidateProposedModeSetHwStateOneDisp( * Check that no dpyId is used by multiple heads. */ dpyIdList = nvEmptyDpyIdList(); - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (NvU32 apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { /* * Intersect the proposed dpys for this head with the * accumulated list of dpys for this disp; if the intersection * is not empty, a dpy is proposed to be used on multiple - * heads. + * api heads. */ NVDpyIdList proposedDpyIdList = - pProposedDisp->head[head].dpyIdList; + pProposedDisp->apiHead[apiHead].dpyIdList; NVDpyIdList intersectedDpyIdList = nvIntersectDpyIdListAndDpyIdList(dpyIdList, proposedDpyIdList); @@ -1202,18 +1801,23 @@ ValidateProposedModeSetHwStateOneDisp( /* * Check ViewPortIn dimensions and ensure valid h/vTaps can be assigned. */ - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); - /* XXX assume the gpus have equal capabilities */ - const NVEvoScalerCaps *pScalerCaps = - &pDevEvo->gpus[0].capabilities.head[head].scalerCaps; - const NVHwModeTimingsEvoPtr pTimings = &pProposedDisp->head[head].timings; - - if (!nvValidateHwModeTimingsViewPort(pDevEvo, pScalerCaps, pTimings, - &dummyInfoString)) { - pReplyDisp->head[apiHead].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; - return FALSE; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NvU32 head; + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + /* XXX assume the gpus have equal capabilities */ + const NVEvoScalerCaps *pScalerCaps = + &pDevEvo->gpus[0].capabilities.head[head].scalerCaps; + const NVHwModeTimingsEvoPtr pTimings = &pProposedDisp->head[head].timings; + + if (!nvValidateHwModeTimingsViewPort(pDevEvo, pScalerCaps, pTimings, + &dummyInfoString)) { + pReplyDisp->head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; + return FALSE; + } } } @@ -1231,21 +1835,20 @@ ValidateProposedModeSetHwStateOneDisp( * configuration, gets finalized as part of the DisplayPort bandwidth * validation. */ - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, - pDispEvo); + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); - if (!pProposedHead->changed || (pDpyEvo == NULL)) { + if (!pProposedApiHead->changed || (pDpyEvo == NULL)) { continue; } nvChooseDitheringEvo(pDpyEvo->pConnectorEvo, - pProposedHead->attributes.colorBpc, + pProposedApiHead->attributes.colorBpc, &pDpyEvo->requestedDithering, - &pProposedHead->attributes.dithering); + &pProposedApiHead->attributes.dithering); } /* @@ -1279,29 +1882,31 @@ ValidateProposedFlipHwStateOneSubDev( NVProposedModeSetHwStateOneSubDev *pProposedSd, struct NvKmsSetModeOneDispReply *pReplyDisp) { - NvU32 head; - - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NvU32 head; + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; - if (!pProposedDisp->head[head].changed || - nvDpyIdListIsEmpty(pProposedDisp->head[head].dpyIdList)) { + if (!pProposedApiHead->changed || + nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList)) { continue; } - nvOverrideScalingUsageBounds( - pDevEvo, - head, - &pProposedSd->head[head].flip, - &pProposedDisp->head[head].timings.viewPort.possibleUsage); - - if (!nvValidateFlipEvoHwState(pDevEvo, - head, - &pProposedDisp->head[head].timings, - &pProposedSd->head[head].flip)) { - pReplyDisp->head[apiHead].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; - return FALSE; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + nvOverrideScalingUsageBounds( + pDevEvo, + head, + &pProposedSd->head[head].flip, + &pProposedDisp->head[head].timings.viewPort.possibleUsage); + + if (!nvValidateFlipEvoHwState(pDevEvo, + head, + &pProposedDisp->head[head].timings, + &pProposedSd->head[head].flip)) { + pReplyDisp->head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + return FALSE; + } } } @@ -1387,100 +1992,66 @@ ValidateProposedModeSetHwState(NVDevEvoPtr pDevEvo, * already been assigned and need to be excluded from consideration for * the new SOR assignment request. */ -static void AssignSor(NVModeSetWorkArea *pWorkArea, - NVConnectorEvoPtr pConnectorEvo) +static void AssignSor(const NVDispEvoRec *pDispEvo, + const NVProposedModeSetStateOneApiHead *pProposedApiHead, + NVModeSetWorkArea *pWorkArea) { - const NvU32 sd = pConnectorEvo->pDispEvo->displayOwner; + const NvU32 sd = pDispEvo->displayOwner; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo; + + const NvBool b2Heads1Or = + (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1); + /* + * In 2Heads1OR DP-MST case, NV0073_CTRL_CMD_DFP_ASSIGN_SOR needs + * to be called with the dynamic displayId. + */ + const NvU32 displayId = (nvDpyEvoIsDPMST(pDpyEvo) && b2Heads1Or) ? + pProposedApiHead->activeRmId : nvDpyIdToNvU32(pConnectorEvo->displayId); + /* + * There are two usecases: + * 1. Two 2Heads1OR DP-MST streams over a same connector. + * 2. One legacy and one 2Heads1OR DP-MST stream over a same connector. + * For both of these usecases, NV0073_CTRL_CMD_DFP_ASSIGN_SOR will get + * called over the same connector multiple times, + * + * Two DP-MST streams over a same connector shares a same primary SOR index. + * + * Remove the already assigned assigned primary SOR index from + * sorExcludeMask, so that NV0073_CTRL_CMD_DFP_ASSIGN_SOR + * re-use it. + */ + const NvU32 sorExcludeMask = + (pConnectorEvo->or.primary != NV_INVALID_OR) ? + (pWorkArea->sd[sd].assignedSorMask & ~NVBIT(pConnectorEvo->or.primary)) : + (pWorkArea->sd[sd].assignedSorMask); if (pConnectorEvo->or.type != NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { // Nothing to do! return; } - /* If an OR has already been assigned for this connector, we are done. */ - if (nvDpyIdIsInDpyIdList( - pConnectorEvo->displayId, - pWorkArea->sd[sd].sorAssignedConnectorsList)) { - nvAssert(pConnectorEvo->or.mask != 0x0); - return; - } - - /* - * We keep a record all the SORs assigned for this modeset, so that - * it can be used as the sorExcludeMask argument to - * nvAssignSOREvo(). - */ - if (nvAssignSOREvo( - pConnectorEvo, - pWorkArea->sd[sd].assignedSorMask /* sorExcludeMask */)) { - nvAssert(pConnectorEvo->or.mask != 0x0); - - pWorkArea->sd[sd].sorAssignedConnectorsList = - nvAddDpyIdToDpyIdList( - pConnectorEvo->displayId, - pWorkArea->sd[sd].sorAssignedConnectorsList); - pWorkArea->sd[sd].assignedSorMask |= pConnectorEvo->or.mask; + if (nvAssignSOREvo(pDispEvo, displayId, b2Heads1Or, sorExcludeMask)) { + nvAssert(pConnectorEvo->or.primary != NV_INVALID_OR); + pWorkArea->sd[sd].assignedSorMask |= nvConnectorGetORMaskEvo(pConnectorEvo); } else { nvAssert(!"Failed to assign SOR, this failure might cause hang!"); } } -static void AssignProposedUsageOneHead( - NVDevEvoPtr pDevEvo, - const NVProposedModeSetHwState *pProposed, - NvU32 head) -{ - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[0].head[head]; - const NVProposedModeSetHwStateOneSubDev *pProposedSd = - &pProposed->sd[0]; - - if (!pDevEvo->isSOCDisplay || (pProposedHead->pConnectorEvo == NULL)) { - return; - } - - pDevEvo->gpus[0].headState[head].preallocatedUsage = - pProposedSd->head[head].flip.usage; -} - -static NvBool IsProposedModeSetHwStateOneDispIncompatibleWithDpy -( - NVDispEvoPtr pDispEvo, - const NVProposedModeSetHwStateOneDisp *pProposedDisp, - const NVConnectorEvoRec *pConnectorEvo -) -{ - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 head; - - for (head = 0; head < pDevEvo->numHeads; head++) { - - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; - - if (!pProposedHead->changed) { - continue; - } - - /* - * DDC partners incompatible with each other, only one should be active - * at a time. - */ - if ((pProposedHead->pConnectorEvo != NULL) && - nvDpyIdIsInDpyIdList(pProposedHead->pConnectorEvo->displayId, - pConnectorEvo->ddcPartnerDpyIdsList)) { - return TRUE; - } - } - - return FALSE; -} - static void KickoffModesetUpdateState( NVDispEvoPtr pDispEvo, NVEvoModesetUpdateState *modesetUpdateState) { + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + nvEvoPreModesetRegisterFlipOccurredEvent(pDispEvo, head, + modesetUpdateState); + } + if (!nvDpyIdListIsEmpty(modesetUpdateState->connectorIds)) { NVConnectorEvoRec *pConnectorEvo; @@ -1512,15 +2083,20 @@ KickoffModesetUpdateState( } if (pConnectorEvo->pDpLibConnector != NULL) { - nvDPPostSetMode(pConnectorEvo->pDpLibConnector); + nvDPPostSetMode(pConnectorEvo->pDpLibConnector, + modesetUpdateState); } else if (nvConnectorIsDPSerializer(pConnectorEvo)) { nvDPSerializerPostSetMode(pDispEvo, pConnectorEvo); } } } - *modesetUpdateState = - (NVEvoModesetUpdateState) { }; + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + nvEvoPostModesetUnregisterFlipOccurredEvent(pDispEvo, head, + modesetUpdateState); + } + + nvkms_memset(modesetUpdateState, 0, sizeof(*modesetUpdateState)); } /*! @@ -1528,28 +2104,69 @@ KickoffModesetUpdateState( * activated display devices. */ static NvBool -IsProposedModeSetHwStateOneHeadIncompatible( +IsProposedModeSetStateOneApiHeadIncompatible( NVDispEvoPtr pDispEvo, - NvU32 head, + NvU32 apiHead, const NVProposedModeSetHwStateOneDisp *pProposedDisp) { - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NvBool isIncompatible; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + + nvAssert(pDpyEvo != NULL); /* * DisplayPort devices require an EVO update when detaching the head * from the SOR, because DPlib performs link-training to powerdown * the link. So, always consider DisplayPort as incompatible. + * + * Consider this api-head incompatible if there is change in the api-head + * to hardware-head(s) mapping. */ - isIncompatible = - nvConnectorUsesDPLib(pHeadState->pConnectorEvo) || - IsProposedModeSetHwStateOneDispIncompatibleWithDpy(pDispEvo, - pProposedDisp, - pHeadState->pConnectorEvo); + if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) || + ((pProposedApiHead->hwHeadsMask != 0x0) && + (pProposedApiHead->hwHeadsMask != pApiHeadState->hwHeadsMask))) { + return TRUE; + } + + for (NvU32 tmpApiHead = 0; tmpApiHead < pDevEvo->numApiHeads; tmpApiHead++) { + const NVProposedModeSetStateOneApiHead *pTmpProposedApiHead = + &pProposedDisp->apiHead[tmpApiHead]; + const NVDpyEvoRec *pDpyEvoTmp = + nvGetOneArbitraryDpyEvo(pTmpProposedApiHead->dpyIdList, pDispEvo); + + if (!pTmpProposedApiHead->changed) { + continue; + } + + /* + * DDC partners incompatible with each other, only one should be active + * at a time. + */ + if ((pDpyEvoTmp != NULL) && + nvDpyIdIsInDpyIdList(pDpyEvoTmp->pConnectorEvo->displayId, + pDpyEvo->pConnectorEvo->ddcPartnerDpyIdsList)) { + return TRUE; + } + + /* + * Consider this api-head incompatible if its current hardware heads + * are proposed to map onto the different api-head. + */ + if ((tmpApiHead != apiHead) && + ((pTmpProposedApiHead->hwHeadsMask & + pApiHeadState->hwHeadsMask) != 0x0)) { + return TRUE; + } + } - return isIncompatible; + return FALSE; } static void DisableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, @@ -1577,52 +2194,124 @@ static void DisableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, } } +static void +ApplyProposedModeSetHwStateOneHeadShutDown( + NVDispEvoPtr pDispEvo, + NvU32 head, + const + NVProposedModeSetHwStateOneDisp + *pProposedDisp, + NVModeSetWorkArea *pWorkArea) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[head]; + + nvHdmiDpEnableDisableAudio(pDispEvo, head, FALSE /* enable */); + + nvEvoDetachConnector(pHeadState->pConnectorEvo, head, + &pWorkArea->modesetUpdateState); + + nvEvoDisableHwYUV420Packer(pDispEvo, head, + &pWorkArea->modesetUpdateState.updateState); + + pHeadState->pConnectorEvo = NULL; + + pHeadState->bypassComposition = FALSE; + pHeadState->tilePosition = 0; + nvkms_memset(&pHeadState->timings, 0, sizeof(pHeadState->timings)); + pHeadState->activeRmId = 0; + + pHeadState->allowFlipLockGroup = 0; + + nvkms_memset(&pHeadState->audio, 0, sizeof(pHeadState->audio)); + + nvkms_memset(&pHeadState->modeValidationParams, 0, + sizeof(pHeadState->modeValidationParams)); + + nvkms_memset(&pDevEvo->gpus[sd].headState[head], 0, + sizeof(pDevEvo->gpus[sd].headState[head])); + + pDevEvo->gpus[sd].headState[head].cursor.cursorCompParams = + nvDefaultCursorCompositionParams(pDevEvo); + + for (NvU32 layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + nvEvoSetFlipOccurredEvent(pDispEvo, + head, + layer, + NULL, + &pWorkArea->modesetUpdateState); + } +} + /*! - * Send methods to shut down a head + * Send methods to shut down a api-head * * \param[in,out] pDispEvo The disp of the head. - * \param[in] head The head to consider. + * \param[in] apiHead The api head to consider. * \param[in] pProposedDisp The requested configuration of the display * \param[in/out] modesetUpdateState Structure tracking channels which need to * be updated/kicked off */ static void -ApplyProposedModeSetHwStateOneHeadShutDown( +ApplyProposedModeSetStateOneApiHeadShutDown( NVDispEvoPtr pDispEvo, - NvU32 head, + NvU32 apiHead, const NVProposedModeSetHwStateOneDisp *pProposedDisp, NVModeSetWorkArea *pWorkArea) { - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVDispHeadStateEvoPtr pHeadState; NVDpyEvoPtr pDpyEvo; - const NvU32 sd = pDispEvo->displayOwner; - NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); - NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; /* * If nothing changed about this head's configuration, then we * should not shut it down. */ - if (!pProposedDisp->head[head].changed) { + if (!pProposedDisp->apiHead[apiHead].changed) { return; } /* * Otherwise, go through the shutdown process for any head that - * changed. If NVProposedModeSetHwStateOneHead::dpyIdList is + * changed. If NVProposedModeSetStateOneApiHead::dpyIdList is * empty, then we'll leave it shut down. If it is non-empty, then * ApplyProposedModeSetHwStateOneHead{Pre,Post}Update() will * update the head with its new configuration. */ - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { return; } - pHeadState = &pDispEvo->headState[head]; + nvAssert(pWorkArea->sd[pDispEvo->displayOwner]. + apiHead[apiHead].oldActiveRmId == 0); + + if (nvPopCount32(pApiHeadState->hwHeadsMask) > 1) { + nvEvoDisableMergeMode(pDispEvo, pApiHeadState->hwHeadsMask, + &pWorkArea->modesetUpdateState.updateState); + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + /* Track old activeRmId and free it after end modeset */ + if (pWorkArea->sd[pDispEvo->displayOwner].apiHead[apiHead].oldActiveRmId == 0) { + pWorkArea->sd[pDispEvo->displayOwner]. + apiHead[apiHead].oldActiveRmId = pHeadState->activeRmId; + } else { + nvAssert(pWorkArea->sd[pDispEvo->displayOwner]. + apiHead[apiHead].oldActiveRmId == pHeadState->activeRmId); + } + + ApplyProposedModeSetHwStateOneHeadShutDown(pDispEvo, head, + pProposedDisp, pWorkArea); + } + pDpyEvo = nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); nvCancelSDRTransitionTimer(pApiHeadState); @@ -1633,7 +2322,7 @@ ApplyProposedModeSetHwStateOneHeadShutDown( * Note: the disable occurs at the hardware level; this intentionally does * not clear the software state tracking the existence of these sync * objects, which will be re-enabled at the hardware level in - * ApplyProposedModeSetHwStateOneHeadPreUpdate(), if the given head will be + * ApplyProposedModeSetStateOneApiHeadPreUpdate(), if the given head will be * active after the modeset. */ DisableActiveCoreRGSyncObjects(pDispEvo, apiHead, @@ -1647,15 +2336,10 @@ ApplyProposedModeSetHwStateOneHeadShutDown( nvDisable3DVisionAegis(pDpyEvo); - nvHdmiDpEnableDisableAudio(pDispEvo, head, FALSE /* enable */); - /* Cancel any pending LUT updates. */ nvCancelLutUpdateEvo(pDispEvo, apiHead); - nvEvoDetachConnector(pHeadState->pConnectorEvo, head, &pWorkArea->modesetUpdateState); - /* Clear software shadow state. */ - pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList = nvAddDpyIdListToDpyIdList( pApiHeadState->activeDpys, @@ -1663,77 +2347,58 @@ ApplyProposedModeSetHwStateOneHeadShutDown( pApiHeadState->activeDpys = nvEmptyDpyIdList(); nvkms_memset(&pApiHeadState->timings, 0, sizeof(pApiHeadState->timings)); nvkms_memset(&pApiHeadState->stereo, 0, sizeof(pApiHeadState->stereo)); - pHeadState->pConnectorEvo = NULL; - - pHeadState->bypassComposition = FALSE; - nvkms_memset(&pHeadState->timings, 0, sizeof(pHeadState->timings)); - - /* Track old activeRmId and free it after end modeset */ - pWorkArea->sd[pDispEvo->displayOwner].head[head].oldActiveRmId = - pHeadState->activeRmId; - pHeadState->activeRmId = 0; - - pHeadState->allowFlipLockGroup = 0; - - nvkms_memset(&pHeadState->audio, 0, sizeof(pHeadState->audio)); - - nvkms_memset(&pHeadState->modeValidationParams, 0, - sizeof(pHeadState->modeValidationParams)); - - nvkms_memset(&pDevEvo->gpus[sd].headState[head], 0, - sizeof(pDevEvo->gpus[sd].headState[head])); - - pDevEvo->gpus[sd].headState[head].cursor.cursorCompParams = - nvDefaultCursorCompositionParams(pDevEvo); pDpyEvo->apiHead = NV_INVALID_HEAD; + nvAssignHwHeadsMaskApiHeadState(pApiHeadState, 0x0); } static void -ApplyProposedModeSetHwStateOneDispFlip( +ApplyProposedModeSetStateOneDispFlip( NVDispEvoPtr pDispEvo, const NVProposedModeSetHwState *pProposed, const NVProposedModeSetHwStateOneDisp *pProposedDisp, NVEvoUpdateState *pUpdateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 head; - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; const NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, pDispEvo); - NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); const NvU32 sd = pDispEvo->displayOwner; + NvU32 head; /* - * If nothing changed about this head's configuration, then there - * is nothing to do. + * If nothing changed about this api-head's configuration or this + * api-head is disabled, then there is nothing to do. */ - if (!pProposedHead->changed) { - continue; - } - - /* Check for disabled heads. */ - if (pProposedHead->pConnectorEvo == NULL) { + if (!pProposedApiHead->changed || + (pProposedApiHead->hwHeadsMask == 0)) { continue; } nvAssert(pDpyEvo != NULL); - nvSetUsageBoundsEvo(pDevEvo, sd, head, - &pProposed->sd[sd].head[head].flip.usage, - pUpdateState); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + nvSetUsageBoundsEvo(pDevEvo, sd, head, + &pProposed->sd[sd].head[head].flip.usage, + pUpdateState); + + nvFlipEvoOneHead(pDevEvo, sd, head, + &pDpyEvo->parsedEdid.info.hdr_static_metadata_info, + &pProposed->sd[sd].head[head].flip, + FALSE /* allowFlipLock */, + pUpdateState); - nvFlipEvoOneHead(pDevEvo, sd, head, - &pDpyEvo->parsedEdid.info.hdr_static_metadata_info, - &pProposed->sd[sd].head[head].flip, - FALSE /* allowFlipLock */, - pUpdateState); + if (pDevEvo->isSOCDisplay) { + pDevEvo->gpus[0].headState[head].preallocatedUsage = + pProposed->sd[sd].head[head].flip.usage; + } + } pDispEvo->apiHeadState[apiHead].viewPortPointIn = - pProposed->sd[sd].head[head].flip.viewPortPointIn; + pProposedApiHead->viewPortPointIn; } } @@ -1762,14 +2427,90 @@ static void ReEnableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, } } +static void +ApplyProposedModeSetHwStateOneHeadPreUpdate( + NVDispEvoPtr pDispEvo, + const NVProposedModeSetStateOneApiHead *pProposedApiHead, + const NvU32 head, + const NvU32 isPrimaryHead, + const NVProposedModeSetHwStateOneHead *pProposedHead, + NvBool bypassComposition, + NVEvoModesetUpdateState *pModesetUpdateState) +{ + NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[head]; + NVEvoUpdateState *updateState = &pModesetUpdateState->updateState; + + pHeadState->allowFlipLockGroup = pProposedApiHead->allowFlipLockGroup; + pHeadState->modeValidationParams = pProposedApiHead->modeValidationParams; + pHeadState->bypassComposition = bypassComposition; + pHeadState->activeRmId = pProposedApiHead->activeRmId; + pHeadState->pConnectorEvo = pProposedHead->pConnectorEvo; + pHeadState->tilePosition = pProposedHead->tilePosition; + pHeadState->timings = pProposedHead->timings; + pHeadState->dscInfo = pProposedApiHead->dscInfo; + pHeadState->hdmiFrlConfig = pProposedHead->hdmiFrlConfig; + pHeadState->pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorBpc); + pHeadState->audio = pProposedHead->audio; + + /* Update current LUT to hardware */ + nvEvoSetLUTContextDma(pDispEvo, head, updateState); + + nvEvoSetTimings(pDispEvo, head, updateState); + + nvSetDitheringEvo(pDispEvo, + head, + &pProposedApiHead->attributes.dithering, + updateState); + + nvEvoHeadSetControlOR(pDispEvo, head, updateState); + + /* Update hardware's current colorSpace and colorRange */ + nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, + head, + pProposedApiHead->attributes.colorSpace, + pProposedApiHead->attributes.colorRange, + updateState); + + nvEvoAttachConnector(pProposedHead->pConnectorEvo, + head, + isPrimaryHead, + pProposedHead->pDpLibModesetState, + pModesetUpdateState); + + nvSetViewPortsEvo(pDispEvo, head, updateState); + + nvSetImageSharpeningEvo( + pDispEvo, + head, + pProposedApiHead->attributes.imageSharpening.value, + updateState); + + + nvSetDVCEvo(pDispEvo, head, + pProposedApiHead->attributes.dvc, + updateState); + + + nvHdmiFrlSetConfig(pDispEvo, head); + + if (isPrimaryHead) { + pHeadState->mergeModeVrrSecondaryHeadMask = + pProposedApiHead->hwHeadsMask & ~NVBIT(head); + } else { + pHeadState->mergeModeVrrSecondaryHeadMask = 0x0; + } +} + /*! - * Update the heads to be modified on this disp. + * Update the api heads to be modified on this disp. * * This should update the ASSY state of the head, but not trigger an * UPDATE method. * * \param[in,out] pDispEvo The disp of the head. - * \param[in] head The head to consider. + * \param[in] apiHead The api head to consider. * \param[in] pProposedHead The requested configuration of the head. * \param[in,out] updateState Indicates which channels require UPDATEs * \param[in] bypassComposition @@ -1777,40 +2518,41 @@ static void ReEnableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, * composition pipeline bypass mode. */ static void -ApplyProposedModeSetHwStateOneHeadPreUpdate( +ApplyProposedModeSetStateOneApiHeadPreUpdate( NVDispEvoPtr pDispEvo, - NvU32 head, - const NVProposedModeSetHwState *pProposed, + const NvU32 apiHead, const NVProposedModeSetHwStateOneDisp *pProposedDisp, NVModeSetWorkArea *pWorkArea, NvBool bypassComposition) { - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NVEvoModesetUpdateState *pModesetUpdateState = &pWorkArea->modesetUpdateState; NVEvoUpdateState *updateState = &pModesetUpdateState->updateState; - NVDispHeadStateEvoPtr pHeadState; - NVDpyEvoPtr pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, pDispEvo); - NvU32 apiHead = nvHardwareHeadToApiHead(pDispEvo->pDevEvo, head); NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + const NvU32 proposedPrimaryHead = + nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); + NVDpyEvoPtr pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); + NvU32 head; /* * If nothing changed about this head's configuration, then there * is nothing to do. */ - if (!pProposedHead->changed) { + if (!pProposedApiHead->changed) { return; } /* Check for disabled heads. */ - if (pProposedHead->pConnectorEvo == NULL) { + if (nvDpyIdListIsEmpty(pProposedApiHead->dpyIdList)) { /* - * ApplyProposedModeSetHwStateOneHeadShutDown() should have + * ApplyProposedModeSetStateOneApiHeadShutDown() should have * already been called for this head. */ - nvAssert(!nvHeadIsActive(pDispEvo, head)); + nvAssert(!nvApiHeadIsActive(pDispEvo, apiHead)); return; } @@ -1819,88 +2561,65 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( return; } - pDpyEvo->apiHead = apiHead; - - AssignSor(pWorkArea, pProposedHead->pConnectorEvo); + /* + * pDevEvo->apiHead[apiHead].numLayers is the number of layers which are + * visible to nvkms clients, and that number should be less than or equal + * to pDevEvo->head[proposedPrimaryHead].numLayers. + * + * If (pDevEvo->head[proposedPrimaryHead].numLayers > + * pDevEvo->apiHead[apiHead].numLayers) then the extra per hardware-head + * layers remain unused and there is no need to register the completion + * notifier callback for those extra per hardware-head layers. + */ - nvDpyUpdateHdmiPreModesetEvo(pDpyEvo); + nvAssert(pDevEvo->head[proposedPrimaryHead].numLayers >= + pDevEvo->apiHead[apiHead].numLayers); - pHeadState = &pDispEvo->headState[head]; + for (NvU32 layer = 0; layer < + pDevEvo->apiHead[apiHead].numLayers; layer++) { + nvEvoSetFlipOccurredEvent(pDispEvo, + proposedPrimaryHead, + layer, + pApiHeadState->flipOccurredEvent[layer]. + ref_ptr, + &pWorkArea->modesetUpdateState); + } + pApiHeadState->hwHeadsMask = pProposedApiHead->hwHeadsMask; + pDpyEvo->apiHead = apiHead; - pHeadState->bypassComposition = bypassComposition; + AssignSor(pDispEvo, pProposedApiHead, pWorkArea); - pHeadState->activeRmId = pProposedHead->activeRmId; + nvDpyUpdateHdmiPreModesetEvo(pDpyEvo); /* * Cache the list of active pDpys for this head, as well as the * mode timings. */ - pApiHeadState->activeDpys = pProposedHead->dpyIdList; - pApiHeadState->timings = pProposedHead->timings; - pApiHeadState->stereo = pProposedHead->stereo; + pApiHeadState->activeDpys = pProposedApiHead->dpyIdList; + pApiHeadState->timings = pProposedApiHead->timings; + pApiHeadState->stereo = pProposedApiHead->stereo; pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList = nvAddDpyIdListToDpyIdList( pApiHeadState->activeDpys, pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList); - nvAssert(pDpyEvo->pConnectorEvo == pProposedHead->pConnectorEvo); - pHeadState->pConnectorEvo = pProposedHead->pConnectorEvo; - - pHeadState->timings = pProposedHead->timings; - pHeadState->pixelDepth = - nvEvoColorSpaceBpcToPixelDepth(pProposedHead->attributes.colorSpace, - pProposedHead->attributes.colorBpc); - - - pHeadState->audio = pProposedHead->audio; - pApiHeadState->infoFrame = pProposedHead->infoFrame; - - AssignProposedUsageOneHead(pDispEvo->pDevEvo, pProposed, head); + pApiHeadState->infoFrame = pProposedApiHead->infoFrame; nvSendHwModeTimingsToAegisEvo(pDispEvo, apiHead); /* Set LUT settings */ - nvEvoSetLut(pDispEvo, apiHead, FALSE /* kickoff */, &pProposedHead->lut); - - /* Update current LUT to hardware */ - nvEvoSetLUTContextDma(pDispEvo, head, updateState); - - nvEvoSetTimings(pDispEvo, head, updateState); - - nvSetDitheringEvo(pDispEvo, - head, - &pProposedHead->attributes.dithering, - updateState); - - nvEvoHeadSetControlOR(pDispEvo, head, updateState); - - /* Update hardware's current colorSpace and colorRange */ - nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, - head, - pProposedHead->attributes.colorSpace, - pProposedHead->attributes.colorRange, - updateState); - - nvEvoAttachConnector(pProposedHead->pConnectorEvo, - head, - pProposedHead->pDpLibModesetState, - pModesetUpdateState); - - nvSetViewPortsEvo(pDispEvo, head, updateState); - - nvSetImageSharpeningEvo( - pDispEvo, - head, - pProposedHead->attributes.imageSharpening.value, - updateState); + nvEvoSetLut(pDispEvo, apiHead, FALSE /* kickoff */, &pProposedApiHead->lut); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { + const NvBool isPrimaryHead = (head == proposedPrimaryHead); - nvSetDVCEvo(pDispEvo, head, - pProposedHead->attributes.dvc, - updateState); - + nvAssert(pDpyEvo->pConnectorEvo == + pProposedDisp->head[head].pConnectorEvo); - nvHdmiFrlSetConfig(pDispEvo, head); + ApplyProposedModeSetHwStateOneHeadPreUpdate(pDispEvo, pProposedApiHead, + head, isPrimaryHead, &pProposedDisp->head[head], + bypassComposition, pModesetUpdateState); + } /* * Re-enable any active sync objects, configuring them in accordance with @@ -1911,12 +2630,19 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( nvAssert(pApiHeadState->rmVBlankCallbackHandle == 0); if (!nvListIsEmpty(&pApiHeadState->vblankCallbackList)) { pApiHeadState->rmVBlankCallbackHandle = - nvRmAddVBlankCallback(pDispEvo, head, VBlankCallback, - (void *)(NvUPtr)apiHead); + nvRmAddVBlankCallback(pDispEvo, proposedPrimaryHead, + VBlankCallback, (void *)(NvUPtr)apiHead); } - pApiHeadState->attributes = pProposedHead->attributes; - pApiHeadState->tf = pProposedHead->tf; + pApiHeadState->attributes = pProposedApiHead->attributes; + pApiHeadState->tf = pProposedApiHead->tf; + pApiHeadState->hs10bpcHint = pProposedApiHead->hs10bpcHint; + + if (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1) { + nvEvoEnableMergeModePreModeset(pDispEvo, + pProposedApiHead->hwHeadsMask, + &pModesetUpdateState->updateState); + } } @@ -1926,81 +2652,81 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( * PreUpdate() will have already been called on this head, and an * UPDATE method sent. * - * \param[in,out] pDispEvo The disp of the head. - * \param[in] head The head to consider. - * \param[in] pProposedHead The requested configuration of the head. + * \param[in,out] pDispEvo The disp of the head. + * \param[in] apihead The api head to consider. + * \param[in] pProposedApiHead The requested configuration of the api head. */ static void -ApplyProposedModeSetHwStateOneHeadPostUpdate(NVDispEvoPtr pDispEvo, - NvU32 head, - const - NVProposedModeSetHwStateOneHead - *pProposedHead) +ApplyProposedModeSetStateOneApiHeadPostModesetUpdate( + NVDispEvoPtr pDispEvo, + NvU32 apiHead, + const NVProposedModeSetStateOneApiHead *pProposedApiHead, + NVEvoUpdateState *pUpdateState) { - NVDispHeadStateEvoRec *pHeadState; + NvU32 head; NVDpyEvoRec *pDpyEvo; - NvU32 apiHead = nvHardwareHeadToApiHead(pDispEvo->pDevEvo, head); NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; /* * If nothing changed about this head's configuration, then there * is nothing to do. */ - if (!pProposedHead->changed) { + if (!pProposedApiHead->changed) { return; } - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { return; } - /* - * Cache configuration state in the headState, so that - * AssignProposedModeSetHwState() can preserve the configuration - * if this head is left alone in the next NvKmsSetModeRequest. - */ - pHeadState = &pDispEvo->headState[head]; + if (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1) { + nvEvoEnableMergeModePostModeset(pDispEvo, + pProposedApiHead->hwHeadsMask, + pUpdateState); + } pDpyEvo = nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); nvAssert(pDpyEvo != NULL); - pHeadState->allowFlipLockGroup = pProposedHead->allowFlipLockGroup; - pHeadState->modeValidationParams = pProposedHead->modeValidationParams; - pApiHeadState->hs10bpcHint = pProposedHead->hs10bpcHint; - nvUpdateInfoFrames(pDpyEvo); /* Perform 3D vision authentication */ nv3DVisionAuthenticationEvo(pDispEvo, apiHead); - nvHdmiDpEnableDisableAudio(pDispEvo, head, TRUE /* enable */); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvHdmiDpEnableDisableAudio(pDispEvo, head, TRUE /* enable */); + } } /* - * Shut down all heads that are incompatible with pProposedDisp. This + * Shut down all api-heads that are incompatible with pProposedDisp. This * requires doing an update immediately. */ static void -KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( +KickoffProposedModeSetStateIncompatibleApiHeadsShutDown( NVDispEvoPtr pDispEvo, const NVProposedModeSetHwStateOneDisp *pProposedDisp, NVModeSetWorkArea *pWorkArea) { - NvU32 head; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NvBool foundIncompatibleHead = FALSE; NvU32 clearHdmiFrlActiveRmId[NVKMS_MAX_HEADS_PER_DISP] = { }; NVDpyIdList proposedActiveConnectorsList = nvEmptyDpyIdList(); NVDpyIdList currActiveConnectorsList = nvEmptyDpyIdList(); NVDpyIdList proposedInactiveConnectorList, unionOfActiveConnectorList; - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - NVDpyId activeConnectorId = - (pDispEvo->headState[head].pConnectorEvo != NULL) ? - pDispEvo->headState[head].pConnectorEvo->displayId : + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDpyEvoRec *pActiveDpyEvo = + nvGetOneArbitraryDpyEvo(pDispEvo->apiHeadState[apiHead].activeDpys, + pDispEvo); + const NVDpyEvoRec *pProposedDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedDisp->apiHead[apiHead].dpyIdList, + pDispEvo); + NVDpyId activeConnectorId = (pActiveDpyEvo != NULL) ? + pActiveDpyEvo->pConnectorEvo->displayId : nvInvalidDpyId(); - NVDpyId proposedConnectorId = - (pProposedDisp->head[head].pConnectorEvo != NULL) ? - pProposedDisp->head[head].pConnectorEvo->displayId : + NVDpyId proposedConnectorId = (pProposedDpyEvo != NULL) ? + pProposedDpyEvo->pConnectorEvo->displayId : nvInvalidDpyId(); currActiveConnectorsList = @@ -2019,15 +2745,21 @@ KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( nvAddDpyIdListToDpyIdList(proposedActiveConnectorsList, currActiveConnectorsList); - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NvBool thisHeadIncompatible = FALSE; - const NVConnectorEvoRec *pCurrConnectorEvo = - pDispEvo->headState[head].pConnectorEvo; - if (!pProposedDisp->head[head].changed || !nvHeadIsActive(pDispEvo, head)) { + if (!pProposedDisp->apiHead[apiHead].changed || + !nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } + const NVDpyEvoRec *pCurrDpyEvo = + nvGetOneArbitraryDpyEvo(pDispEvo->apiHeadState[apiHead].activeDpys, + pDispEvo); + const NVConnectorEvoRec *pCurrConnectorEvo = + pCurrDpyEvo->pConnectorEvo; + + /* * If the number of current active connectors + proposed active * connectors is greater than number of heads then modeset is under @@ -2040,6 +2772,10 @@ KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( * In this situation, all the connectors which are not going active * after modeset, mark them incompatible and shut down them before * triggering modeset on all the active connectors. + * + * [2Heads1OR] XXX This incompatibility check will not work because in + * the 2Heads1OR configuration two heads gets attached to a single + * connector. */ if (nvCountDpyIdsInDpyIdList(unionOfActiveConnectorList) > pDispEvo->pDevEvo->numHeads && @@ -2049,25 +2785,36 @@ KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( } /* if the *new* timings are FRL, then we need to shut down the head. */ - if (pProposedDisp->head[head].timings.hdmiFrlConfig.frlRate != - HDMI_FRL_DATA_RATE_NONE) { + if (pProposedDisp->apiHead[apiHead].timings.protocol == + NVKMS_PROTOCOL_SOR_HDMI_FRL) { thisHeadIncompatible = TRUE; } /* if the *old* timings are FRL, then we need to shut down the head and * clear the FRL config. */ - if (pDispEvo->headState[head].timings.hdmiFrlConfig.frlRate != - HDMI_FRL_DATA_RATE_NONE) { + if (pDispEvo->apiHeadState[apiHead].timings.protocol == + NVKMS_PROTOCOL_SOR_HDMI_FRL) { + NvU32 head; thisHeadIncompatible = TRUE; /* cache the activeRmId since it will be cleared below, but * we don't want to actually call into the HDMI library until * afterwards. */ - clearHdmiFrlActiveRmId[head] = pDispEvo->headState[head].activeRmId; + FOR_EACH_EVO_HW_HEAD_IN_MASK( + pDispEvo->apiHeadState[apiHead].hwHeadsMask, + head) { + if (clearHdmiFrlActiveRmId[apiHead] == 0) { + clearHdmiFrlActiveRmId[apiHead] = + pDispEvo->headState[head].activeRmId; + } else { + nvAssert(clearHdmiFrlActiveRmId[apiHead] == + pDispEvo->headState[head].activeRmId); + } + } } - if (IsProposedModeSetHwStateOneHeadIncompatible(pDispEvo, - head, - pProposedDisp)) { + if (IsProposedModeSetStateOneApiHeadIncompatible(pDispEvo, + apiHead, + pProposedDisp)) { thisHeadIncompatible = TRUE; } @@ -2075,9 +2822,9 @@ KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( continue; } - ApplyProposedModeSetHwStateOneHeadShutDown( + ApplyProposedModeSetStateOneApiHeadShutDown( pDispEvo, - head, + apiHead, pProposedDisp, pWorkArea); @@ -2087,11 +2834,11 @@ KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( /* Submit UPDATE method and kick off, to shut down incompatible heads. */ if (foundIncompatibleHead) { KickoffModesetUpdateState(pDispEvo, &pWorkArea->modesetUpdateState); - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - if (clearHdmiFrlActiveRmId[head] == 0) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numHeads; apiHead++) { + if (clearHdmiFrlActiveRmId[apiHead] == 0) { continue; } - nvHdmiFrlClearConfig(pDispEvo, clearHdmiFrlActiveRmId[head]); + nvHdmiFrlClearConfig(pDispEvo, clearHdmiFrlActiveRmId[apiHead]); } } } @@ -2119,23 +2866,22 @@ KickoffProposedModeSetHwState( */ const NvBool decoupleFlipUpdates = pModesetUpdateState->windowMappingChanged; - NvU32 head; /* Send methods to shut down any other unused heads, but don't update yet. */ - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - ApplyProposedModeSetHwStateOneHeadShutDown( + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + ApplyProposedModeSetStateOneApiHeadShutDown( pDispEvo, - head, + apiHead, pProposedDisp, pWorkArea); } /* Apply pre-UPDATE modifications for any enabled heads. */ - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - ApplyProposedModeSetHwStateOneHeadPreUpdate( + for (NvU32 apiHead = 0; + apiHead < pDispEvo->pDevEvo->numApiHeads; apiHead++) { + ApplyProposedModeSetStateOneApiHeadPreUpdate( pDispEvo, - head, - pProposed, + apiHead, pProposedDisp, pWorkArea, bypassComposition); @@ -2143,7 +2889,7 @@ KickoffProposedModeSetHwState( if (!decoupleFlipUpdates) { /* Merge modeset and flip state updates together */ - ApplyProposedModeSetHwStateOneDispFlip( + ApplyProposedModeSetStateOneDispFlip( pDispEvo, pProposed, pProposedDisp, @@ -2157,7 +2903,7 @@ KickoffProposedModeSetHwState( if (decoupleFlipUpdates) { NVEvoUpdateState flipUpdateState = { }; - ApplyProposedModeSetHwStateOneDispFlip( + ApplyProposedModeSetStateOneDispFlip( pDispEvo, pProposed, pProposedDisp, @@ -2170,16 +2916,22 @@ KickoffProposedModeSetHwState( nvRemoveUnusedHdmiDpAudioDevice(pDispEvo); - /* Apply post-UPDATE modifications for any enabled heads. */ - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + { + NVEvoUpdateState updateState = { }; - const NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposedDisp->head[head]; + /* Apply post-MODESET-UPDATE modifications for any enabled api-heads. */ + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + ApplyProposedModeSetStateOneApiHeadPostModesetUpdate( + pDispEvo, + apiHead, + &pProposedDisp->apiHead[apiHead], + &updateState); + } - ApplyProposedModeSetHwStateOneHeadPostUpdate( - pDispEvo, - head, - pProposedHead); + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + pDevEvo->hal->Update(pDevEvo, &updateState, + TRUE /* releaseElv */); + } } } @@ -2307,7 +3059,7 @@ ApplyProposedModeSetHwStateOneDisp( "Unexpectedly failed to lock to max DRAM pre-modeset!"); } - KickoffProposedModeSetHwStateIncompatibleHeadsShutDown( + KickoffProposedModeSetStateIncompatibleApiHeadsShutDown( pDispEvo, pProposedDisp, pWorkArea); @@ -2319,6 +3071,8 @@ ApplyProposedModeSetHwStateOneDisp( bypassComposition, pWorkArea); + nvEvoLockStateSetMergeMode(pDispEvo); + /* * This function waits for 2 frames to make sure that the final IMP * arbitration settings have been programmed by the post-SV3 worker thread @@ -2565,7 +3319,7 @@ static void FillPostSyncptReplyForModeset( * \param[out] pReply The reply to the client. */ static void -AssignReplySuccess(const NVDevEvoRec *pDevEvo, +AssignReplySuccess(NVDevEvoRec *pDevEvo, const struct NvKmsSetModeRequest *pRequest, struct NvKmsSetModeReply *pReply, const NVModeSetWorkArea *pWorkArea) @@ -2576,8 +3330,6 @@ AssignReplySuccess(const NVDevEvoRec *pDevEvo, nvkms_memset(pReply, 0, sizeof(*pReply)); FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - - NvU32 head; const struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[dispIndex]; @@ -2585,8 +3337,7 @@ AssignReplySuccess(const NVDevEvoRec *pDevEvo, continue; } - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { const struct NvKmsSetModeOneHeadRequest *pRequestHead = &pRequestDisp->head[apiHead]; struct NvKmsSetModeOneHeadReply *pReplyHead = @@ -2599,25 +3350,58 @@ AssignReplySuccess(const NVDevEvoRec *pDevEvo, pReplyHead->status = NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS; if (!nvDpyIdListIsEmpty(pRequestHead->dpyIdList)) { - const NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - pReplyHead->possibleUsage = pHeadState->timings.viewPort.possibleUsage; - pReplyHead->guaranteedUsage = pHeadState->timings.viewPort.guaranteedUsage; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NvU32 primaryHwHead = + nvGetPrimaryHwHeadFromMask(pApiHeadState->hwHeadsMask); + + nvAssert((pApiHeadState->hwHeadsMask != 0x0) && + (primaryHwHead != NV_INVALID_HEAD)); + + struct NvKmsUsageBounds *pTmpUsageBounds = + nvPreallocGet(pDevEvo, + PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS, + sizeof(*pTmpUsageBounds)); + NvU32 head; + + pReplyHead->possibleUsage = pDispEvo->headState[primaryHwHead]. + timings.viewPort.possibleUsage; + pReplyHead->guaranteedUsage = pDispEvo->headState[primaryHwHead]. + timings.viewPort.guaranteedUsage; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + nvIntersectUsageBounds(&pReplyHead->possibleUsage, + &pHeadState->timings.viewPort.possibleUsage, + pTmpUsageBounds); + pReplyHead->possibleUsage = *pTmpUsageBounds; + + nvIntersectUsageBounds(&pReplyHead->guaranteedUsage, + &pHeadState->timings.viewPort.guaranteedUsage, + pTmpUsageBounds); + pReplyHead->guaranteedUsage = *pTmpUsageBounds; + } + + nvPreallocRelease(pDevEvo, + PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS); + pReplyHead->usingHeadSurface = (pDispEvo->pHsChannel[apiHead] != NULL); pReplyHead->vrrEnabled = - (pDispEvo->headState[head].timings.vrr.type != + (pApiHeadState->timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE); - pReplyHead->hwHead = head; + pReplyHead->hwHead = primaryHwHead; + + FillPostSyncptReplyForModeset( + pDevEvo, + primaryHwHead, + &pRequestHead->flip, + &pReplyHead->flipReply, + &pWorkArea->sd[dispIndex].head[primaryHwHead].newState); } else { pReplyHead->hwHead = NV_INVALID_HEAD; } - FillPostSyncptReplyForModeset( - pDevEvo, - head, - &pRequestHead->flip, - &pReplyHead->flipReply, - &pWorkArea->sd[dispIndex].head[head].newState); } } } @@ -2640,12 +3424,16 @@ BeginEndModeset(NVDevEvoPtr pDevEvo, NvU32 dispIndex; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head, dpyMask = 0; + const NVProposedModeSetHwStateOneDisp *pProposedDisp = + &pProposed->disp[dispIndex]; + NvU32 apiHead, dpyMask = 0; /* Compute dpyMask: take all the dpyIds on this dispIndex. */ - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - dpyMask |= - nvDpyIdListToNvU32(pProposed->disp[dispIndex].head[head].dpyIdList); + for (apiHead = 0; apiHead < + ARRAY_LEN(pProposedDisp->apiHead); apiHead++) { + const NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + dpyMask |= nvDpyIdListToNvU32(pProposedApiHead->dpyIdList); } nvRmBeginEndModeset(pDispEvo, beginOrEnd, dpyMask); @@ -2944,8 +3732,6 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, pDevEvo->modesetOwnerChanged = FALSE; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - /* * In case of successful commit, update current attribute values and * free old display IDs. @@ -2958,11 +3744,11 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, nvDpyUpdateCurrentAttributes(pDpyEvo); } - for (head = 0; head < pDevEvo->numHeads; head++) { - if (pWorkArea->sd[dispIndex].head[head].oldActiveRmId != 0x0) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (pWorkArea->sd[dispIndex].apiHead[apiHead].oldActiveRmId != 0x0) { nvRmFreeDisplayId( pDispEvo, - pWorkArea->sd[dispIndex].head[head].oldActiveRmId); + pWorkArea->sd[dispIndex].apiHead[apiHead].oldActiveRmId); } } } diff --git a/src/nvidia-modeset/src/nvkms-prealloc.c b/src/nvidia-modeset/src/nvkms-prealloc.c index 82160cadca..c1eb1fef5a 100644 --- a/src/nvidia-modeset/src/nvkms-prealloc.c +++ b/src/nvidia-modeset/src/nvkms-prealloc.c @@ -50,8 +50,18 @@ static size_t GetSizeForType(NVDevEvoPtr pDevEvo, enum NVPreallocType type) case PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS: /* fallthrough */ case PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS: return sizeof(NVHwModeTimingsEvo); + case PREALLOC_TYPE_VALIDATE_MODE_HDMI_FRL_CONFIG: + return sizeof(HDMI_FRL_CONFIG); + case PREALLOC_TYPE_VALIDATE_MODE_DSC_INFO: + return sizeof(NVDscInfoEvoRec); case PREALLOC_TYPE_HS_PATCHED_MODESET_REQUEST: return sizeof(struct NvKmsSetModeRequest); + case PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS: + return sizeof(struct NvKmsUsageBounds); + case PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS: + return sizeof(NVHwModeTimingsEvo) * NVKMS_MAX_HEADS_PER_DISP; + case PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS: + return sizeof(struct NvKmsUsageBounds); case PREALLOC_TYPE_MAX: /* Not a real option, but added for -Wswitch-enum */ break; diff --git a/src/nvidia-modeset/src/nvkms-rm.c b/src/nvidia-modeset/src/nvkms-rm.c index 4f0a498e00..0daf65556b 100644 --- a/src/nvidia-modeset/src/nvkms-rm.c +++ b/src/nvidia-modeset/src/nvkms-rm.c @@ -282,6 +282,9 @@ static void FreeDisplay(NVDispEvoPtr pDispEvo) return; } + nvAssert(pDispEvo->vrrSetTimeoutEventUsageCount == 0); + nvAssert(pDispEvo->vrrSetTimeoutEventHandle == 0); + #if defined(DEBUG) for (NvU32 apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->pSwapGroup); apiHead++) { @@ -293,6 +296,7 @@ static void FreeDisplay(NVDispEvoPtr pDispEvo) nvkms_free_ref_ptr(pDispEvo->ref_ptr); + nvInvalidateTopologiesEvo(); nvFree(pDispEvo); } @@ -731,20 +735,6 @@ static NvBool AllocConnector( pConnectorEvo->dfpInfo = GetDfpInfo(pConnectorEvo); - if (pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { - nvAssert(pDevEvo->numHeads >= 1); - // DSI supports only HEAD0 assignment - pConnectorEvo->validHeadMask = 0x1; - - if (pConnectorEvo->type != NVKMS_CONNECTOR_TYPE_DSI) { - nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, - "Mismatch between connector type and signal format for DSI!"); - goto fail; - } - } else { - pConnectorEvo->validHeadMask = (1 << pDevEvo->numHeads) - 1; - } - /* Assign connector indices. */ pConnectorEvo->legacyType = @@ -1144,11 +1134,11 @@ static void MarkConnectorBootHeadActive(NVDispEvoPtr pDispEvo, NvU32 head) } else { // Track the SOR assignment for this connector. See the comment in // nvRmGetConnectorORInfo() for why this is deferred until now. - nvAssert(pConnectorEvo->or.mask == 0x0); - pConnectorEvo->or.mask |= NVBIT(params.index); + nvAssert(pConnectorEvo->or.primary == NV_INVALID_OR); + pConnectorEvo->or.primary = params.index; } } - nvAssert((pConnectorEvo->or.mask & NVBIT(params.index)) != 0x0); + nvAssert(pConnectorEvo->or.primary == params.index); pHeadState = &pDispEvo->headState[head]; @@ -2030,7 +2020,8 @@ void nvRmGetConnectorORInfo(NVConnectorEvoPtr pConnectorEvo, NvBool assertOnly) return; } pConnectorEvo->or.type = NV0073_CTRL_SPECIFIC_OR_TYPE_DAC; - pConnectorEvo->or.mask = 0; + pConnectorEvo->or.primary = NV_INVALID_OR; + pConnectorEvo->or.secondaryMask = 0; pConnectorEvo->or.protocol = NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT; pConnectorEvo->or.ditherType = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF; @@ -2053,9 +2044,11 @@ void nvRmGetConnectorORInfo(NVConnectorEvoPtr pConnectorEvo, NvBool assertOnly) // // All we really need to know is which SOR is assigned to the boot // display, so we defer the query to MarkConnectorBootHeadActive(). - pConnectorEvo->or.mask = 0x0; + pConnectorEvo->or.secondaryMask = 0x0; + pConnectorEvo->or.primary = NV_INVALID_OR; } else { - pConnectorEvo->or.mask = NVBIT(params.index); + pConnectorEvo->or.secondaryMask = 0x0; + pConnectorEvo->or.primary = params.index; } pConnectorEvo->or.protocol = params.protocol; pConnectorEvo->or.ditherType = params.ditherType; @@ -2063,7 +2056,7 @@ void nvRmGetConnectorORInfo(NVConnectorEvoPtr pConnectorEvo, NvBool assertOnly) pConnectorEvo->or.location = params.location; } else { nvAssert(pConnectorEvo->or.type == params.type); - nvAssert((pConnectorEvo->or.mask & NVBIT(params.index)) != 0x0); + nvAssert(pConnectorEvo->or.primary == params.index); nvAssert(pConnectorEvo->or.protocol == params.protocol); nvAssert(pConnectorEvo->or.ditherType == params.ditherType); nvAssert(pConnectorEvo->or.ditherAlgo == params.ditherAlgo); @@ -2221,11 +2214,11 @@ NvBool nvRmSetDpmsEvo(NVDpyEvoPtr pDpyEvo, NvS64 value) NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS powerParams = { { 0 }, 0 }; powerParams.base.subdeviceIndex = pDispEvo->displayOwner; - if (pConnectorEvo->or.mask == 0x0) { - nvAssert(pConnectorEvo->or.mask != 0x0); + if (pConnectorEvo->or.primary == NV_INVALID_OR) { + nvAssert(pConnectorEvo->or.primary != NV_INVALID_OR); return FALSE; } - powerParams.orNumber = nvEvoConnectorGetPrimaryOr(pConnectorEvo); + powerParams.orNumber = pConnectorEvo->or.primary; switch (value) { case NV_KMS_DPY_ATTRIBUTE_DPMS_ON: @@ -3157,7 +3150,7 @@ static NvBool AllocPostSyncptPerChannel(NVDevEvoPtr pDevEvo, NvBool nvRMAllocateWindowChannels(NVDevEvoPtr pDevEvo) { int index; - NvU32 window; + NvU32 window, sd; static const struct { NvU32 windowClass; @@ -3198,6 +3191,18 @@ NvBool nvRMAllocateWindowChannels(NVDevEvoPtr pDevEvo) return FALSE; } + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + NvU32 ret = nvRmEvoBindDispContextDMA(pDevEvo, + pDevEvo->window[window], + pDevEvo->window[window]->notifiersDma[sd].ctxHandle); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to bind(window channel) display engine notify context DMA: 0x%x (%s)", + ret, nvstatusToString(ret)); + return FALSE; + } + } + if (!AllocImmediateChannelDma(pDevEvo, pDevEvo->window[window], c->immClass)) { return FALSE; @@ -3431,6 +3436,7 @@ void nvRmFreeCoreRGSyncpts(NVDevEvoPtr pDevEvo) /* Free all core RG syncpts. */ NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[i]; for (int j = 0; j < pApiHeadState->numVblankSyncObjectsCreated; j++) { + nvAssert(!pApiHeadState->vblankSyncObjects[j].inUse); nvRmEvoFreeSyncpt(pDevEvo, &pApiHeadState->vblankSyncObjects[j].evoSyncpt); } diff --git a/src/nvidia-modeset/src/nvkms-surface.c b/src/nvidia-modeset/src/nvkms-surface.c index bc8ac003f1..38298a3270 100644 --- a/src/nvidia-modeset/src/nvkms-surface.c +++ b/src/nvidia-modeset/src/nvkms-surface.c @@ -958,7 +958,7 @@ void nvEvoFreeClientSurfaces(NVDevEvoPtr pDevEvo, nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); if (isOwner) { - nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); } else { nvEvoDecrementSurfaceStructRefCnt(pSurfaceEvo); } @@ -1003,7 +1003,7 @@ void nvEvoUnregisterSurface(NVDevEvoPtr pDevEvo, /* Remove the handle from the calling client's namespace. */ nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); - nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); } void nvEvoReleaseSurface(NVDevEvoPtr pDevEvo, @@ -1041,13 +1041,15 @@ void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) pSurfaceEvo->structRefCnt++; } -void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo, - NVSurfaceEvoPtr pSurfaceEvo) +void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) { nvAssert(pSurfaceEvo->rmRefCnt >= 1); pSurfaceEvo->rmRefCnt--; if (pSurfaceEvo->rmRefCnt == 0) { + NVDevEvoPtr pDevEvo = + nvGetDevEvoFromOpenDev(pSurfaceEvo->owner.pOpenDev); + /* * Don't sync if this surface was registered as not requiring display * hardware access, to WAR timeouts that result from OGL unregistering @@ -1222,7 +1224,7 @@ void nvEvoUnregisterDeferredRequestFifo( pDeferredRequestFifo->fifo, 0); - nvEvoDecrementSurfaceRefCnts(pDevEvo, pDeferredRequestFifo->pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDeferredRequestFifo->pSurfaceEvo); nvFree(pDeferredRequestFifo); } diff --git a/src/nvidia-modeset/src/nvkms-vrr.c b/src/nvidia-modeset/src/nvkms-vrr.c index 4b1a7c7053..c606e90487 100644 --- a/src/nvidia-modeset/src/nvkms-vrr.c +++ b/src/nvidia-modeset/src/nvkms-vrr.c @@ -29,8 +29,78 @@ #include "dp/nvdp-connector-event-sink.h" #include "nvkms-hdmi.h" #include "nvkms-dpy.h" +#include "nvkms-sync.h" #include +#include /* NV01_MEMORY_LOCAL_USER */ +#include /* NV20_SUBDEVICE_0 */ +#include /* NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION */ + +#define MAX_VRR_NOTIFIER_SLOTS_PER_HEAD 4 +#define MAX_NOTIFIER_SIZE 0x10 +#define NOTIFIER_BYTES_PER_HEAD \ + (MAX_VRR_NOTIFIER_SLOTS_PER_HEAD * MAX_NOTIFIER_SIZE) + +#define MAX_VRR_FLIP_DELAY_TIME_RETRY_COUNT 5 + +typedef struct _vrrSurfaceNotifier +{ + NvU8 notifier[NV_MAX_HEADS][NOTIFIER_BYTES_PER_HEAD]; +} vrrSurfaceNotifier, *vrrSurfaceNotifierPtr; + +/*! + * This file contains routines for handling Variable Refresh Rate (VRR) display + * mode, also known as G-SYNC (not to be confused with the feature formerly + * known as G-SYNC, which is now called Quadro Sync). + * + * VRR in NVKMS is handled in several phases: + * + * 1. During modeset, if NvKmsSetModeRequest::allowVrr is true and VRR-capable + * dpys are present, VRR is "enabled". This means that + * + * a. VRR is disabled, if it was enabled before. + * b. The raster timings are adjusted by extending the back porch by 2 + * lines. This signals to the monitor that it should enter G-SYNC mode. + * c. The mode is set. + * d. (EVO only) The RM VRR state machine is initialized, but left in + * "suspended" mode. + * e. Raster lock and frame lock are disabled. + * + * pDevEvo->vrr.enabled indicates whether VRR was enabled successfully at + * modeset time. + * + * 2. At flip time, if NvKmsFlipRequest::allowVrr is true, VRR is "activated". + * + * a. Stall lock is enabled. + * b. (NVDisplay only) The RG is switched from continuous mode to one-shot + * mode. + * c. (EVO only) RM's VRR state machine is enabled. + * d. (EVO only) The NVKMS client is told to release a special frame ready + * semaphore which tells RM to unstall the head. + * e. (NVDisplay only) The window channel flip is submitted with + * NVC37E_UPDATE_RELEASE_ELV_TRUE to trigger an unstall when the frame is + * ready. + * + * pDevEvo->vrr.active (not to be confused with pDevEvo->vrr.enabled, + * described above) indicates whether VRR was activated successfully at flip + * time. + * + * 3. Also at flip time, if NvKmsFlipRequest::allowVrr is false, VRR is + * "deactivated". + * + * a. Stall lock is disabled. + * b. (NVDisplay only) the RG is switched from one-shot mode to continuous + * mode. + * c. (EVO only) RM's VRR state machine is suspended. + */ + +static NvBool SetVrrActivePriv(NVDevEvoPtr pDevEvo, NvBool active); +static void ConfigVrrPstateSwitch(NVDispEvoPtr pDispEvo, + NvBool vrrEnabled, + NvBool vrrState, + NvBool vrrDirty, + NvU32 head); + /*! * Allocate the VRR semaphore surface. @@ -105,15 +175,619 @@ NvBool nvExportVrrSemaphoreSurface(const NVDevEvoRec *pDevEvo, int fd) return status == NVOS_STATUS_SUCCESS; } -NvBool nvDispSupportsVrr( - const NVDispEvoRec *pDispEvo) +/*! + * Return TRUE dpy support G-SYNC. + */ +static NvBool DpyIsGsync(const NVDpyEvoRec *pDpyEvo) +{ + return pDpyEvo->vrr.type == NVKMS_DPY_VRR_TYPE_GSYNC; +} + +static NvBool IsAdaptiveSyncDpyVrrType(enum NvKmsDpyVRRType type) +{ + return ((type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED) || + (type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED)); +} + + +static NvBool AnyEnabledAdaptiveSyncDpys(const NVDevEvoRec *pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 head; + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + if (IsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) { + return TRUE; + } + } + } + + return FALSE; +} + +static NvBool DpyAllowsAdaptiveSync( + const NVDpyEvoRec *pDpyEvo, + const enum NvKmsAllowAdaptiveSync allowAdaptiveSync, + const NvModeTimings *pTimings) +{ + /* + * HDMI VRR and HDMI 3D both use the vendor specific infoframe in HW, + * so disallow HDMI VRR when attempting to set an HDMI 3D mode. + */ + + if (pTimings->hdmi3D) { + return FALSE; + } + + return ((allowAdaptiveSync == + NVKMS_ALLOW_ADAPTIVE_SYNC_DEFAULTLISTED_ONLY) && + (pDpyEvo->vrr.type == + NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED)) || + ((allowAdaptiveSync == NVKMS_ALLOW_ADAPTIVE_SYNC_ALL) && + nvDpyIsAdaptiveSync(pDpyEvo)); +} + +NvBool nvDispSupportsVrr(const NVDispEvoRec *pDispEvo) +{ + // Don't allow VRR if a framelock device is present. + // (In other words, don't allow G-SYNC with Quadro Sync). + return !pDispEvo->pFrameLockEvo; +} + +enum NvKmsDpyVRRType +nvGetAllowedDpyVrrType(const NVDpyEvoRec *pDpyEvo, + const NvModeTimings *pTimings, + enum NvKmsStereoMode stereoMode, + const NvBool allowGsync, + const enum NvKmsAllowAdaptiveSync allowAdaptiveSync) +{ + /* + * Mark these mode timings as indicating a VRR mode, even if the timings + * don't need to be adjusted; this is used to distinguish between VRR and + * non-VRR heads elsewhere. + */ + + if ((stereoMode == NVKMS_STEREO_DISABLED) && + ((allowGsync && DpyIsGsync(pDpyEvo)) || + DpyAllowsAdaptiveSync(pDpyEvo, allowAdaptiveSync, pTimings))) { + return pDpyEvo->vrr.type; + } + + return NVKMS_DPY_VRR_TYPE_NONE; +} + +/*! Adjust mode timings as necessary for VRR. */ +void nvAdjustHwModeTimingsForVrrEvo(NVHwModeTimingsEvoPtr pTimings, + const enum NvKmsDpyVRRType vrrType, + const NvU32 edidTimeoutMicroseconds, + const NvU32 vrrOverrideMinRefreshRate, + const NvBool needsSwFramePacing) +{ + if (vrrType == NVKMS_DPY_VRR_TYPE_NONE) { + return; + } + + /* + * On G-SYNC panels, the back porch extension is used to indicate to + * the monitor that VRR is enabled. It is not necessary on + * Adaptive-Sync displays. + */ + if (vrrType == NVKMS_DPY_VRR_TYPE_GSYNC) { + pTimings->rasterSize.y += 2; + pTimings->rasterBlankEnd.y += 2; + pTimings->rasterBlankStart.y += 2; + } + + // Allow overriding the EDID min refresh rate on Adaptive-Sync + // displays. + if (IsAdaptiveSyncDpyVrrType(vrrType) && vrrOverrideMinRefreshRate) { + NvU32 minMinRefreshRate, maxMinRefreshRate; + NvU32 clampedMinRefreshRate; + + nvGetDpyMinRefreshRateValidValues(pTimings, + vrrType, + edidTimeoutMicroseconds, + &minMinRefreshRate, + &maxMinRefreshRate); + + clampedMinRefreshRate = + NV_MAX(vrrOverrideMinRefreshRate, minMinRefreshRate); + + clampedMinRefreshRate = + NV_MIN(clampedMinRefreshRate, maxMinRefreshRate); + + pTimings->vrr.timeoutMicroseconds = 1000000 / + clampedMinRefreshRate; + } else { + pTimings->vrr.timeoutMicroseconds = edidTimeoutMicroseconds; + } + pTimings->vrr.needsSwFramePacing = needsSwFramePacing; + pTimings->vrr.type = vrrType; +} + +static void TellRMAboutVrrHead(NVDispEvoPtr pDispEvo, + NVDispHeadStateEvoRec *pHeadState, + NvBool vrrPossible) +{ + if (pHeadState->activeRmId != 0) { + NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS params = { }; + NvU32 ret; + + params.subDeviceInstance = pDispEvo->displayOwner; + params.displayId = pHeadState->activeRmId; + params.bAddition = vrrPossible; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO, + ¶ms, sizeof(params)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_WARN, + "NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO failed"); + } + } +} + +static void RmDisableVrr(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 head, dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + ConfigVrrPstateSwitch(pDispEvo, FALSE /* vrrEnabled */, + FALSE /* vrrState */, + TRUE /* vrrDirty */, + head); + } + } + nvAssert(pDevEvo->hal->caps.supportsDisplayRate); +} + +NvU16 nvPrepareNextVrrNotifier(NVEvoChannelPtr pChannel, NvU32 sd, NvU32 head) +{ + enum NvKmsNIsoFormat nIsoFormat = NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY; + + vrrSurfaceNotifierPtr pNotifiers = pChannel->notifiersDma[sd].subDeviceAddress[sd]; + + const NvU32 notifierSize = + nvKmsSizeOfNotifier(nIsoFormat, FALSE /* overlay */); + + const NvU8 nextSlot = + pChannel->notifiersDma[sd].vrrNotifierHead[head].vrrNotifierNextSlot; + + const NvU8 *headBase = pNotifiers->notifier[head]; + + const NvU8 offsetInBytes = + (headBase - ((const NvU8 *) pNotifiers)) + (notifierSize * nextSlot); + + nvAssert(notifierSize <= MAX_NOTIFIER_SIZE); + + nvKmsResetNotifier(nIsoFormat, FALSE /* overlay */, + nextSlot, pNotifiers->notifier[head]); + + pChannel->notifiersDma[sd].vrrNotifierHead[head].vrrNotifierNextSlot = + (nextSlot + 1) % MAX_VRR_NOTIFIER_SLOTS_PER_HEAD; + + return offsetInBytes / 4; +} + +static void SetTimeoutPerFrame(void *dataPtr, NvU32 dataU32) +{ + // Set the timeout after which the current frame will self-refresh. + NVDispEvoPtr pDispEvo = dataPtr; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoUpdateState updateState = { }; + NvU32 head; + NvU32 inputHead = dataU32; + NVDispHeadStateEvoRec *pInputHeadState = &pDispEvo->headState[inputHead]; + NvU32 displayRate = pInputHeadState->displayRate; + struct NvKmsVrrFramePacingInfo *pInputVrrFramePacingInfo = + &(pInputHeadState->vrrFramePacingInfo); + const NvU32 headsMask = pInputHeadState->mergeModeVrrSecondaryHeadMask | + NVBIT(inputHead); + volatile NV0073_CTRL_RM_VRR_SHARED_DATA *pData = pInputVrrFramePacingInfo->pData; + + /* + * XXX[2Heads1OR] Implement per api-head frame pacing and remove this + * mergeMode check and NVDispEvoRec::mergeModeVrrSecondaryHeadMask. + */ + if ((pInputHeadState->mergeMode == NV_EVO_MERGE_MODE_SECONDARY) || + !pInputVrrFramePacingInfo->framePacingActive || + (displayRate == pData->timeout)) { + return; + } + + nvPushEvoSubDevMaskDisp(pDispEvo); + FOR_EACH_EVO_HW_HEAD_IN_MASK(headsMask, head) { + pDispEvo->headState[head].displayRate = pData->timeout; + + pDevEvo->hal->SetDisplayRate(pDispEvo, head, + TRUE /* enable */, + &updateState, + pDispEvo->headState[head].displayRate / 1000); + } + + /* + * In order to change the one shot self refresh timeout mid-frame without + * immediately triggering a new frame, skip setting RELEASE_ELV for this + * update. + */ + nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, + FALSE /* releaseElv */); + nvPopEvoSubDevMask(pDevEvo); +} + +static void SetTimeoutEvent(void *arg, void *pEventDataVoid, NvU32 hEvent, + NvU32 Data, NV_STATUS Status) +{ + Nv2080VrrSetTimeoutNotification *pParams = pEventDataVoid; + + (void) nvkms_alloc_timer_with_ref_ptr( + SetTimeoutPerFrame, /* callback */ + arg, /* argument (this is a ref_ptr to a pDispEvo) */ + pParams->head, /* dataU32 */ + 0); +} + +static void DisableVrrSetTimeoutEvent(NVDispEvoRec *pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NvU32 subdeviceHandle = pDevEvo->pSubDevices[sd]->handle; + NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams = {0}; + NvU32 ret; + + nvAssert(pDispEvo->vrrSetTimeoutEventUsageCount != 0); + + pDispEvo->vrrSetTimeoutEventUsageCount--; + if (pDispEvo->vrrSetTimeoutEventUsageCount != 0) { + return; + } + + nvAssert(pDispEvo->vrrSetTimeoutEventHandle != 0); + + setEventParams.event = NV2080_NOTIFIERS_VRR_SET_TIMEOUT; + setEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + subdeviceHandle, + NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, + &setEventParams, + sizeof(setEventParams)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE failed for vrr %d", ret); + } + + ret = nvRmApiFree(nvEvoGlobal.clientHandle, + subdeviceHandle, + pDispEvo->vrrSetTimeoutEventHandle); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "nvRmApiFree(notify) failed for vrr %d", ret); + } + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDispEvo->vrrSetTimeoutEventHandle); + pDispEvo->vrrSetTimeoutEventHandle = 0; +} + +static NvBool EnableVrrSetTimeoutEvent(NVDispEvoRec *pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NvU32 subdeviceHandle = pDevEvo->pSubDevices[sd]->handle; + NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams = { }; + NvU32 ret; + + if (pDispEvo->vrrSetTimeoutEventUsageCount != 0) { + nvAssert(pDispEvo->vrrSetTimeoutEventHandle != 0); + goto done; + } + + nvAssert(pDispEvo->vrrSetTimeoutEventHandle == 0); + + pDispEvo->vrrSetTimeoutEventHandle = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + if (!nvRmRegisterCallback(pDevEvo, + &pDispEvo->vrrSetTimeoutCallback, + pDispEvo->ref_ptr, + subdeviceHandle, + pDispEvo->vrrSetTimeoutEventHandle, + SetTimeoutEvent, + NV2080_NOTIFIERS_VRR_SET_TIMEOUT)) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDispEvo->vrrSetTimeoutEventHandle); + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "nvRmRegisterCallback failed for vrr"); + return FALSE; + } + + // Enable VRR notifications from this subdevice. + setEventParams.event = NV2080_NOTIFIERS_VRR_SET_TIMEOUT; + setEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT; + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + subdeviceHandle, + NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, + &setEventParams, + sizeof(setEventParams)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT failed for vrr 0x%x", ret); + nvRmApiFree(nvEvoGlobal.clientHandle, + subdeviceHandle, pDispEvo->vrrSetTimeoutEventHandle); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDispEvo->vrrSetTimeoutEventHandle); + pDispEvo->vrrSetTimeoutEventHandle = 0; + return FALSE; + } + +done: + pDispEvo->vrrSetTimeoutEventUsageCount++; + return TRUE; +} + +static NvBool VrrRgLineActiveSessionOpen(NVDispEvoPtr pDispEvo, + struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo) { + NvU32 ret = 0; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NvU32 subdeviceHandle = pDevEvo->pSubDevices[sd]->handle; + NV_MEMORY_ALLOCATION_PARAMS memAllocParams = { }; + NvHandle memoryHandle; + void *address = NULL; + + if (!EnableVrrSetTimeoutEvent(pDispEvo)) { + return FALSE; + } + + /* allocate memory from vidmem */ + memoryHandle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + memAllocParams.owner = NVKMS_RM_HEAP_ID; + memAllocParams.type = NVOS32_TYPE_DMA; + memAllocParams.size = sizeof(NV0073_CTRL_RM_VRR_SHARED_DATA); + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _4KB) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED) | + DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); + + memAllocParams.flags |= (NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED | + NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM); + + ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + memoryHandle, + NV01_MEMORY_LOCAL_USER, + &memAllocParams); + + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "nvRmApiAlloc(memory) failed for vrr 0x%x", ret); + goto free_memory_handle; + } + + ret = nvRmApiMapMemory(nvEvoGlobal.clientHandle, + subdeviceHandle, + memoryHandle, + 0, + sizeof(NV0073_CTRL_RM_VRR_SHARED_DATA), + &address, + 0); + if ((ret != NVOS_STATUS_SUCCESS) || (address == NULL)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, " nvRmApiMapMemory failed for vrr 0x%x addr: %p", + ret, address); + nvRmApiFree(nvEvoGlobal.clientHandle, + subdeviceHandle, memoryHandle); + goto free_memory_handle; + } + + pVrrFramePacingInfo->pData = (NV0073_CTRL_RM_VRR_SHARED_DATA *)address; + pVrrFramePacingInfo->memoryHandle = memoryHandle; + + return TRUE; + +free_memory_handle: + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, memoryHandle); + DisableVrrSetTimeoutEvent(pDispEvo); return FALSE; } +static void VrrRgLineActiveSessionClose(NVDispEvoPtr pDispEvo, + struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NvU32 subdeviceHandle = pDevEvo->pSubDevices[sd]->handle; + NvU32 ret = 0; + + // clean up allocated memory + ret = nvRmApiUnmapMemory(nvEvoGlobal.clientHandle, + subdeviceHandle, + pVrrFramePacingInfo->memoryHandle, + (void *)pVrrFramePacingInfo->pData, + 0); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, "nvRmApiUnmapMemory failed for vrr %d", ret); + } + + ret = nvRmApiFree(nvEvoGlobal.clientHandle, + subdeviceHandle, + pVrrFramePacingInfo->memoryHandle); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, "nvRmApiFree(memory) failed for vrr %d", ret); + } + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, pVrrFramePacingInfo->memoryHandle); + + DisableVrrSetTimeoutEvent(pDispEvo); +} + +/*! + * Enable or disable SW Frame Pacing for one head. + * + * This will reset the NVDispHeadStateEvoRec::NvKmsVrrFramePacingInfo state used + * to track Frame pacing per head and call RM to set an interrupt to be called + * at every first RG scanline of every frame (whether initiated by a flip or + * a self-refresh). + */ +static NvBool SetSwFramePacing(NVDispEvoPtr pDispEvo, NvU32 head, NvBool enable) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo = + &pHeadState->vrrFramePacingInfo; + const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + const NvU32 timeout = pTimings->vrr.timeoutMicroseconds; + struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS params = { }; + NvU32 maxFrameTime = 0; + NvU32 minFrameTime = 0; + + if (pVrrFramePacingInfo->framePacingActive == enable) { + return TRUE; + } + + if (enable) { + maxFrameTime = timeout * 1000; + minFrameTime = 1000 * + axb_div_c(pTimings->rasterSize.y * 1000, + pTimings->rasterSize.x, + pTimings->pixelClock); + + /* + * SW Frame pacing won't work with infinite self-refresh adaptive sync + * or direct drive panels (none of which currently exist) or when + * driving a mode below the panel's minimum refresh rate. + */ + if ((maxFrameTime == 0) || + (minFrameTime == 0) || + (minFrameTime >= maxFrameTime)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to set variable refresh rate with invalid " + "minimum frame time (%u ns) or maximum frame time " + "(%u ns)", minFrameTime, maxFrameTime); + return FALSE; + } + + if (!VrrRgLineActiveSessionOpen(pDispEvo, pVrrFramePacingInfo)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to setup Rgline active session for vrr"); + return FALSE; + } + } + + params.head = head; + params.height = 1; + params.bEnable = enable; + params.subDeviceInstance = pDispEvo->displayOwner; + params.maxFrameTime = maxFrameTime; + params.minFrameTime = minFrameTime; + params.hMemory = pVrrFramePacingInfo->memoryHandle; + if (nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE, + ¶ms, sizeof(params)) + != NVOS_STATUS_SUCCESS) { + nvAssert(!"NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE failed"); + VrrRgLineActiveSessionClose(pDispEvo, pVrrFramePacingInfo); + return FALSE; + } + + if (!enable) { + VrrRgLineActiveSessionClose(pDispEvo, pVrrFramePacingInfo); + + // Reset the state used to track SW Frame pacing. + nvkms_memset(pVrrFramePacingInfo, 0, sizeof(*pVrrFramePacingInfo)); + } + + pVrrFramePacingInfo->framePacingActive = enable; + return TRUE; +} + void nvDisableVrr(NVDevEvoPtr pDevEvo) { - return; + NVDispEvoPtr pDispEvo; + NvU32 head, dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + TellRMAboutVrrHead(pDispEvo, pHeadState, FALSE); + + SetSwFramePacing(pDispEvo, head, FALSE); + } + } + + if (!pDevEvo->vrr.enabled) { + return; + } + + SetVrrActivePriv(pDevEvo, FALSE); + RmDisableVrr(pDevEvo); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + if ((pHeadState->pConnectorEvo != NULL) && + IsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) { + if (nvConnectorUsesDPLib(pHeadState->pConnectorEvo)) { + nvDPLibSetAdaptiveSync(pDispEvo, head, FALSE); + } else { + nvHdmiSetVRR(pDispEvo, head, FALSE); + } + } + } + } + + pDevEvo->vrr.enabled = FALSE; + nvAssert(!pDevEvo->vrr.active); +} + +static NvBool AnyEnabledGsyncDpys(const NVDevEvoRec *pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 head; + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + if (pHeadState->timings.vrr.type == NVKMS_DPY_VRR_TYPE_GSYNC) { + return TRUE; + } + } + } + + return FALSE; +} + +static NvBool RmEnableVrr(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex, head; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + ConfigVrrPstateSwitch(pDispEvo, TRUE /* vrrEnabled */, + FALSE /* vrrState */, + TRUE/* vrrDirty */, + head); + } + } + nvAssert(pDevEvo->hal->caps.supportsDisplayRate); + return TRUE; + + return FALSE; } void nvGetDpyMinRefreshRateValidValues( @@ -123,56 +797,487 @@ void nvGetDpyMinRefreshRateValidValues( NvU32 *minMinRefreshRate, NvU32 *maxMinRefreshRate) { - return; + NvU32 edidMinRefreshRate; + + if (IsAdaptiveSyncDpyVrrType(vrrType)) { + /* + * Adaptive-Sync monitors must always define a nonzero minimum refresh + * rate in the EDID, and a modeset may override this within a range + * of NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE, as long as the minimum + * is not below 1hz and the maximum does not exceed the current + * refresh rate. + */ + NvU32 minTimeoutMicroseconds = + axb_div_c(pTimings->rasterSize.y * 1000, + pTimings->rasterSize.x, pTimings->pixelClock); + NvU32 maxRefreshRate = 1000000 / minTimeoutMicroseconds; + + nvAssert(edidTimeoutMicroseconds != 0); + + edidMinRefreshRate = + 1000000 / edidTimeoutMicroseconds; + + if (edidMinRefreshRate <= NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE) { + *minMinRefreshRate = 1; + } else { + *minMinRefreshRate = edidMinRefreshRate - + NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE; + } + + *maxMinRefreshRate = NV_MIN(maxRefreshRate, + edidMinRefreshRate + NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE); + } else { + /* + * Non-Adaptive-Sync panels may not override the EDID-provided minimum + * refresh rate, which will be 1hz for most G-SYNC panels or 0hz for + * true self-refresh panels. + */ + edidMinRefreshRate = edidTimeoutMicroseconds ? + 1000000 / edidTimeoutMicroseconds : 0; + *minMinRefreshRate = *maxMinRefreshRate = edidMinRefreshRate; + } } +/*! + * Modify the VRR state to enable (but not activate) VRR at modeset time. + * + * This prepares VRR displays for VRR (through a DP MSA override for + * Adaptive-Sync and a backporch extension for G-SYNC) and sets up the RM + * VRR state machine (for pre-nvdisplay) but does not actually start VRR + * flipping until nvSetVrrActive() is called at flip time. + * + * \param[in] pDevEvo The device that is enabling VRR. + */ void nvEnableVrr(NVDevEvoPtr pDevEvo) { - return; + NVDispEvoPtr pDispEvo; + NvU32 head, dispIndex; + + nvAssert(!pDevEvo->vrr.enabled); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + if ((pHeadState->pConnectorEvo != NULL) && + IsAdaptiveSyncDpyVrrType(pHeadState->timings.vrr.type)) { + if (nvConnectorUsesDPLib(pHeadState->pConnectorEvo)) { + nvDPLibSetAdaptiveSync(pDispEvo, head, TRUE); + } else { + nvHdmiSetVRR(pDispEvo, head, TRUE); + } + } + } + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + // To allow VRR-based mclk switching, RM needs to know which heads + // are driving VRR displays capable of extending vblank. This + // includes all G-SYNC displays (regardless of whether the modeset + // indicates that G-SYNC is allowed) but only Adaptive-Sync + // displays which put the display into Adaptive-Sync mode by calling + // nvDPLibSetAdaptiveSync above. + TellRMAboutVrrHead(pDispEvo, + pHeadState, + (pHeadState->timings.vrr.type != + NVKMS_DPY_VRR_TYPE_NONE)); + } + } + + if (!(AnyEnabledGsyncDpys(pDevEvo) || + AnyEnabledAdaptiveSyncDpys(pDevEvo))) { + return; + } + + if (!RmEnableVrr(pDevEvo)) { + return; + } + + pDevEvo->vrr.enabled = TRUE; } -void nvSetVrrActive( - NVDevEvoPtr pDevEvo, - NvBool active) +static void ClearElvBlock(NVDispEvoPtr pDispEvo, NvU32 head) { - return; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS params = { }; + + params.subDeviceInstance = pDispEvo->displayOwner; + params.displayId = pHeadState->activeRmId; + + if (nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_CLEAR_ELV_BLOCK, + ¶ms, sizeof(params)) + != NVOS_STATUS_SUCCESS) { + nvAssert(!"CLEAR_ELV_BLOCK failed"); + } } -void nvApplyVrrBaseFlipOverrides( - const NVDispEvoRec *pDispEvo, - NvU32 head, - const NVFlipChannelEvoHwState *pOld, - NVFlipChannelEvoHwState *pNew) +static void ConfigVrrPstateSwitch(NVDispEvoPtr pDispEvo, NvBool vrrEnabled, + NvBool vrrState, NvBool vrrDirty, NvU32 head) { - return; + NV0073_CTRL_SYSTEM_CONFIG_VRR_PSTATE_SWITCH_PARAMS params = { }; + NvU32 ret; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + params.displayId = pHeadState->activeRmId; + params.bVrrEnabled = vrrEnabled; + params.bVrrState = vrrState; + params.bVrrDirty = vrrDirty; + + params.subDeviceInstance = pDispEvo->displayOwner; + + if (pHeadState->timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE) { + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH, + ¶ms, sizeof(params)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_WARN, + "NV0073_CTRL_CMD_SYSTEM_CONFIG_VRR_PSTATE_SWITCH failed"); + } + } } -void nvCancelVrrFrameReleaseTimers( - NVDevEvoPtr pDevEvo) +static void SetStallLockOneDisp(NVDispEvoPtr pDispEvo, NvBool enable) { - return; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvBool enableVrrOnHead[NVKMS_MAX_HEADS_PER_DISP]; + NVEvoUpdateState updateState = { }; + NvU32 head; + + if (enable) { + for (head = 0; head < pDevEvo->numHeads; head++) { + ConfigVrrPstateSwitch(pDispEvo, TRUE /* vrrEnabled */, + TRUE /* vrrState */, + FALSE/* vrrDirty */, + head); + } + } + + nvPushEvoSubDevMaskDisp(pDispEvo); + + // Make sure any pending updates that we didn't wait for previously have + // completed. + nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const NvU32 timeout = pHeadState->timings.vrr.timeoutMicroseconds; + + enableVrrOnHead[head] = ((pHeadState->timings.vrr.type != + NVKMS_DPY_VRR_TYPE_NONE) && enable); + + nvEvoArmLightweightSupervisor(pDispEvo, head, + enableVrrOnHead[head], TRUE); + if (!enableVrrOnHead[head]) { + ClearElvBlock(pDispEvo, head); + } + pDevEvo->hal->SetStallLock(pDispEvo, head, + enableVrrOnHead[head], + &updateState); + + if (pDevEvo->hal->caps.supportsDisplayRate) { + pDevEvo->hal->SetDisplayRate(pDispEvo, head, + enableVrrOnHead[head], + &updateState, + timeout); + + if ((pHeadState->timings.vrr.type != + NVKMS_DPY_VRR_TYPE_NONE) && + pHeadState->timings.vrr.needsSwFramePacing) { + SetSwFramePacing(pDispEvo, head, + enableVrrOnHead[head]); + } + } + } + + nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, + TRUE /* releaseElv */); + + for (head = 0; head < pDevEvo->numHeads; head++) { + nvEvoArmLightweightSupervisor(pDispEvo, head, + enableVrrOnHead[head], FALSE); + } + + nvPopEvoSubDevMask(pDevEvo); + + if (!enable) { + for (head = 0; head < pDevEvo->numHeads; head++) { + ConfigVrrPstateSwitch(pDispEvo, TRUE /* vrrEnabled */, + FALSE /* vrrState */, + FALSE /* vrrDirty */, + head); + } + } } +static void SetStallLockOneDev(NVDevEvoPtr pDevEvo, NvBool enable) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + SetStallLockOneDisp(pDispEvo, enable); + } +} + +/*! + * Modify the VRR state to activate or deactivate VRR on the heads of a pDevEvo. + */ +static NvBool SetVrrActivePriv(NVDevEvoPtr pDevEvo, NvBool active) +{ + if (!pDevEvo->vrr.enabled || + pDevEvo->vrr.active == active) { + return NV_TRUE; + } + + // TODO: Drain the base channel first? + SetStallLockOneDev(pDevEvo, active); + + pDevEvo->vrr.active = active; + pDevEvo->vrr.flipCounter = 0; + return NV_TRUE; +} + +void nvSetVrrActive(NVDevEvoPtr pDevEvo, NvBool active) +{ + if (!SetVrrActivePriv(pDevEvo, active)) { + nvDisableVrr(pDevEvo); + } +} + +/*! + * Track the minimum and average time between flips over the last 16 flips, and + * add a timestamp to delay the next flip to adjust Frame pacing if necessary. + */ +void nvTrackAndDelayFlipForVrrSwFramePacing(NVDispEvoPtr pDispEvo, + const struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo, + NVFlipChannelEvoHwState *pFlip) +{ + volatile NV0073_CTRL_RM_VRR_SHARED_DATA *pData = pVrrFramePacingInfo->pData; + NvU32 retryCount = MAX_VRR_FLIP_DELAY_TIME_RETRY_COUNT; + NvU64 flipTimeStamp = 0; + NvU64 dataTimeStamp1 = 0, dataTimeStamp2 = 0; + NvU32 expectedFrameNum = 0; + NvBool bFlipTimeAdjustment = NV_FALSE; + NvBool bCheckFlipTime = NV_FALSE; + + // If the RG interrupt isn't active, then SW Frame pacing isn't in use. + if (!pVrrFramePacingInfo->framePacingActive) { + return; + } + + do { + // read the data timestamp first + dataTimeStamp1 = pData->dataTimeStamp; + + // now read the actual data required + expectedFrameNum = pData->expectedFrameNum; + bFlipTimeAdjustment = pData->bFlipTimeAdjustment; + bCheckFlipTime = pData->bCheckFlipTime; + flipTimeStamp = pData->flipTimeStamp; + + // read the data timestamp again to check if values were updated + // by RM in between while nvkms was reading them. + dataTimeStamp2 = pData->dataTimeStamp; + } while ((dataTimeStamp1 != dataTimeStamp2) && --retryCount); + + if (retryCount == 0) { + nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, + "Failed to sync with RM to get flipTimeStamp related data"); + return; + } + + if (expectedFrameNum > 1) { + pFlip->tearing = FALSE; + } + + if (bFlipTimeAdjustment && !(pFlip->tearing && bCheckFlipTime)) { + pFlip->timeStamp = flipTimeStamp; + } +} + +/*! + * Override flip parameters for a head based on VRR state. + */ +void nvApplyVrrBaseFlipOverrides(const NVDispEvoRec *pDispEvo, NvU32 head, + const NVFlipChannelEvoHwState *pOld, + NVFlipChannelEvoHwState *pNew) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVDispHeadStateEvoRec *pHeadState = NULL; + + if (!pDevEvo->vrr.enabled) { + return; + } + + if (head != NV_INVALID_HEAD) { + pHeadState = &pDispEvo->headState[head]; + nvAssert(pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]->caps.vrrTearingFlips); + } + + // Tell RM the real requested tearing mode so that it can honor + // __GL_SYNC_TO_VBLANK. + pNew->vrrTearing = pNew->tearing; + + // If this head is driving non-VRR displays, force swap interval to be 0. + // RM will block the flips as necessary using the pre-update trap methods + // based on the vrrTearing flag above. + if (pHeadState != NULL && + (pHeadState->timings.vrr.type == NVKMS_DPY_VRR_TYPE_NONE)) { + pNew->tearing = TRUE; + pNew->minPresentInterval = 0; + } + + // If oneshot mode is in use, and the previous flip was non-tearing with + // nonzero MIN_PRESENT_INTERVAL, and the new flip will be tearing with + // MIN_PRESENT_INTERVAL 0, then force this first new flip to be + // non-tearing to WAR bug 2406398 which causes these transitional flips + // to stall for up to the display's minimum refresh rate. + if ((pHeadState != NULL) && + (pHeadState->timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE) && + !pOld->tearing && + (pOld->minPresentInterval != 0) && + pNew->tearing && + (pNew->minPresentInterval == 0)) { + pNew->tearing = FALSE; + } +} + +void nvCancelVrrFrameReleaseTimers(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + nvkms_free_timer(pDispEvo->vrr.unstallTimer); + pDispEvo->vrr.unstallTimer = NULL; + } +} + +/* Get active vrr type used by the flips. */ enum NvKmsVrrFlipType nvGetActiveVrrType(const NVDevEvoRec *pDevEvo) { + /* + * If VRR is active, and any connected display is G-SYNC, then report that + * this flip was a G-SYNC flip, otherwise report it as an Adaptive-Sync + * flip. + * + * XXX NVKMS TODO: We could be smarter about reporting whether this flip + * exclusively changed surfaces on Adaptive-Sync or G-SYNC heads. + */ + if (pDevEvo->vrr.active) { + if (AnyEnabledGsyncDpys(pDevEvo)) { + return NV_KMS_VRR_FLIP_GSYNC; + } else { + return NV_KMS_VRR_FLIP_ADAPTIVE_SYNC; + } + } + return NV_KMS_VRR_FLIP_NON_VRR; } +/*! + * Get the next VRR semaphore index to be released + * by the client, increments the counter and handles wrapping. + */ NvS32 nvIncVrrSemaphoreIndex(NVDevEvoPtr pDevEvo) { - return -1; + NvS32 vrrSemaphoreIndex = -1; + + // If there are pending unstall timers (e.g. triggered by cursor motion), + // cancel them now. The flip that was just requested will trigger an + // unstall. + nvCancelVrrFrameReleaseTimers(pDevEvo); + + if (pDevEvo->vrr.active && !pDevEvo->hal->caps.supportsDisplayRate) { + vrrSemaphoreIndex = pDevEvo->vrr.flipCounter++; + if (pDevEvo->vrr.flipCounter >= + NVKMS_VRR_SEMAPHORE_SURFACE_SIZE / sizeof(NvU32)) { + pDevEvo->vrr.flipCounter = 0; + } + } + + return vrrSemaphoreIndex; +} + +static void +VrrUnstallNow(NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 head; + + nvAssert(pDevEvo->hal->caps.supportsDisplayRate); + + for (head = 0; head < pDevEvo->numHeads; head++) { + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + pDevEvo->cursorHal->ReleaseElv(pDevEvo, pDispEvo->displayOwner, head); + } +} + +static void +VrrUnstallTimer(void *dataPtr, NvU32 dataU32) +{ + NVDispEvoPtr pDispEvo = dataPtr; + + VrrUnstallNow(pDispEvo); + pDispEvo->vrr.unstallTimer = NULL; } -void nvTriggerVrrUnstallMoveCursor( - NVDispEvoPtr pDispEvo) +/*! + * Schedule a timer to trigger a VRR unstall if no flip occurs soon. + * + * When VRR is active and something other than a flip (i.e. cursor motion) + * changes the screen, RM needs to be notified so that it can trigger a VRR + * unstall to present the new frame. However, if it does that immediately, then + * applications that flip in response to cursor motion will end up always + * flipping during the unstall, causing stutter. So instead, schedule a timeout + * for some time in the future in order to give the application some time to + * respond, but force a minimum refresh rate if it doesn't. + * + * On nvdisplay, this schedules an nvkms timer and uses a method to trigger an + * unstall. On EVO, it calls into RM to do something equivalent. + */ +void nvTriggerVrrUnstallMoveCursor(NVDispEvoPtr pDispEvo) { - return; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NvU32 timeoutMs = 33; // 30 fps + + if (!pDevEvo->vrr.active) { + return; + } + + { + if (!pDispEvo->vrr.unstallTimer) { + pDispEvo->vrr.unstallTimer = + nvkms_alloc_timer(VrrUnstallTimer, pDispEvo, 0, timeoutMs * 1000); + } + } } -void nvTriggerVrrUnstallSetCursorImage( - NVDispEvoPtr pDispEvo, - NvBool elvReleased) +/*! + * Trigger a VRR unstall in response to a cursor image change. + */ +void nvTriggerVrrUnstallSetCursorImage(NVDispEvoPtr pDispEvo, + NvBool elvReleased) { - return; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + + if (pDevEvo->vrr.active) { + if (!elvReleased) { + // On nvdisplay, no unstall is necessary if the cursor image update + // path did a releaseElv=true Update. + // + // But, if elv was not released, then force an immediate unstall + // now. + VrrUnstallNow(pDispEvo); + } + } } diff --git a/src/nvidia-modeset/src/nvkms.c b/src/nvidia-modeset/src/nvkms.c index 7063d16915..d597be7b6e 100644 --- a/src/nvidia-modeset/src/nvkms.c +++ b/src/nvidia-modeset/src/nvkms.c @@ -221,6 +221,9 @@ struct NvKmsPerOpen { static void AllocSurfaceCtxDmasForAllOpens(NVDevEvoRec *pDevEvo); static void FreeSurfaceCtxDmasForAllOpens(NVDevEvoRec *pDevEvo); +static void EnableAndSetupVblankSyncObjectForAllOpens(NVDevEvoRec *pDevEvo); +static void DisableAndCleanVblankSyncObjectForAllOpens(NVDevEvoRec *pDevEvo); + static NVListRec perOpenList = NV_LIST_INIT(&perOpenList); static NVListRec perOpenIoctlList = NV_LIST_INIT(&perOpenIoctlList); @@ -1061,6 +1064,7 @@ static void RestoreConsole(NVDevEvoPtr pDevEvo) // If that didn't work, free the core channel to trigger RM's console // restore code. FreeSurfaceCtxDmasForAllOpens(pDevEvo); + DisableAndCleanVblankSyncObjectForAllOpens(pDevEvo); nvFreeCoreChannelEvo(pDevEvo); // Reallocate the core channel right after freeing it. This makes sure @@ -1068,6 +1072,7 @@ static void RestoreConsole(NVDevEvoPtr pDevEvo) // started. if (nvAllocCoreChannelEvo(pDevEvo)) { nvDPSetAllowMultiStreaming(pDevEvo, TRUE /* allowMST */); + EnableAndSetupVblankSyncObjectForAllOpens(pDevEvo); AllocSurfaceCtxDmasForAllOpens(pDevEvo); } } @@ -1462,11 +1467,10 @@ static void UnregisterDeferredRequestFifos(struct NvKmsPerOpenDev *pOpenDev) * Forward declaration since this function is used by * DisableRemainingVblankSyncObjects(). */ -static void DisableAndCleanVblankSyncObject(struct NvKmsPerOpenDisp *pOpenDisp, - NvU32 apiHead, +static void DisableAndCleanVblankSyncObject(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, NVVblankSyncObjectRec *pVblankSyncObject, - NVEvoUpdateState *pUpdateState, - NvKmsVblankSyncObjectHandle handle); + NVEvoUpdateState *pUpdateState); static void DisableRemainingVblankSyncObjects(struct NvKmsPerOpen *pOpen, struct NvKmsPerOpenDev *pOpenDev) @@ -1500,10 +1504,11 @@ static void DisableRemainingVblankSyncObjects(struct NvKmsPerOpen *pOpen, /* For each still-active vblank sync object: */ FOR_ALL_POINTERS_IN_EVO_API_HANDLES(pHandles, pVblankSyncObject, handle) { - DisableAndCleanVblankSyncObject(pOpenDisp, apiHead, + DisableAndCleanVblankSyncObject(pOpenDisp->pDispEvo, apiHead, pVblankSyncObject, - &updateState, - handle); + &updateState); + /* Remove the handle from the map. */ + nvEvoDestroyApiHandle(pHandles, handle); } } @@ -1656,7 +1661,6 @@ static NvBool QueryConnectorStaticData(struct NvKmsPerOpen *pOpen, pParams->reply.signalFormat = pConnectorEvo->signalFormat; pParams->reply.physicalIndex = pConnectorEvo->physicalIndex; pParams->reply.physicalLocation = pConnectorEvo->physicalLocation; - pParams->reply.headMask = pConnectorEvo->validApiHeadMask; pParams->reply.isLvds = (pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) && @@ -1757,6 +1761,7 @@ static NvBool QueryDpyStaticData(struct NvKmsPerOpen *pOpen, pParams->reply.mobileInternal = pDpyEvo->internal; pParams->reply.isDpMST = nvDpyEvoIsDPMST(pDpyEvo); + pParams->reply.headMask = nvDpyGetPossibleApiHeadsMask(pDpyEvo); return TRUE; } @@ -4056,6 +4061,92 @@ static NvBool ExportVrrSemaphoreSurface( return nvExportVrrSemaphoreSurface(pOpenDev->pDevEvo, req->memFd); } +static void EnableAndSetupVblankSyncObject(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVVblankSyncObjectRec *pVblankSyncObject, + NVEvoUpdateState *pUpdateState) +{ + /* + * The core channel re-allocation code path may end up allocating + * the fewer number of sync objects than the number of sync objects which + * are allocated and in use by the NVKMS clients, hCtxDma = 0 if the + * nvAllocCoreChannelEvo()-> InitApiHeadState()-> nvRmAllocCoreRGSyncpts() + * code path failes to re-allocate that sync object. + */ + if (nvApiHeadIsActive(pDispEvo, apiHead) && + (pVblankSyncObject->evoSyncpt.hCtxDma != 0)) { + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + nvAssert(head != NV_INVALID_HEAD); + + pDispEvo->pDevEvo->hal->ConfigureVblankSyncObject( + pDispEvo->pDevEvo, + pDispEvo->headState[head].timings.rasterBlankStart.y, + head, + pVblankSyncObject->index, + pVblankSyncObject->evoSyncpt.hCtxDma, + pUpdateState); + + pVblankSyncObject->enabled = TRUE; + } + + pVblankSyncObject->inUse = TRUE; +} + +static void EnableAndSetupVblankSyncObjectForAllOpens(NVDevEvoRec *pDevEvo) +{ + /* + * An NVEvoUpdateState has disp-scope, and we will only have + * one disp when programming syncpts. + */ + NVEvoUpdateState updateState = { }; + struct NvKmsPerOpen *pOpen; + + if (!pDevEvo->supportsSyncpts || + !pDevEvo->hal->caps.supportsVblankSyncObjects) { + return; + } + + /* If Syncpts are supported, we're on Orin, which only has one display. */ + nvAssert(pDevEvo->nDispEvo == 1); + + nvListForEachEntry(pOpen, &perOpenIoctlList, perOpenIoctlListEntry) { + struct NvKmsPerOpenDev *pOpenDev = DevEvoToOpenDev(pOpen, pDevEvo); + struct NvKmsPerOpenDisp *pOpenDisp; + NvKmsGenericHandle disp; + + if (pOpenDev == NULL) { + continue; + } + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDev->dispHandles, + pOpenDisp, disp) { + + nvAssert(pOpenDisp->pDispEvo == pDevEvo->pDispEvo[0]); + + for (NvU32 apiHead = 0; apiHead < + ARRAY_LEN(pOpenDisp->vblankSyncObjectHandles); apiHead++) { + NVEvoApiHandlesRec *pHandles = + &pOpenDisp->vblankSyncObjectHandles[apiHead]; + NVVblankSyncObjectRec *pVblankSyncObject; + NvKmsVblankSyncObjectHandle handle; + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(pHandles, + pVblankSyncObject, handle) { + EnableAndSetupVblankSyncObject(pOpenDisp->pDispEvo, apiHead, + pVblankSyncObject, + &updateState); + } + } + } + } + + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + nvEvoUpdateAndKickOff(pDevEvo->pDispEvo[0], TRUE, &updateState, + TRUE); + } +} + static NvBool EnableVblankSyncObject( struct NvKmsPerOpen *pOpen, void *pParamsVoid) @@ -4123,36 +4214,13 @@ static NvBool EnableVblankSyncObject( return FALSE; } - if (nvApiHeadIsActive(pDispEvo, apiHead)) { - NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); - - nvAssert(head != NV_INVALID_HEAD); - - /* - * Instruct the hardware to enable a semaphore corresponding to this - * syncpt. The Update State will be populated. - */ - pDevEvo->hal->ConfigureVblankSyncObject( - pDevEvo, - pDispEvo->headState[head].timings.rasterBlankStart.y, - head, - freeVblankSyncObjectIdx, - vblankSyncObjects[freeVblankSyncObjectIdx].evoSyncpt.hCtxDma, - &updateState); - - /* - * Instruct hardware to execute the staged commands from the - * ConfigureVblankSyncObject() call above. This will set up and wait for a - * notification that the hardware execution actually completed. - */ + EnableAndSetupVblankSyncObject(pDispEvo, apiHead, + &vblankSyncObjects[freeVblankSyncObjectIdx], + &updateState); + if (!nvIsUpdateStateEmpty(pOpenDisp->pDispEvo->pDevEvo, &updateState)) { nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, TRUE); - - vblankSyncObjects[freeVblankSyncObjectIdx].enabled = TRUE; } - /* Populate the vblankSyncObjects array. */ - vblankSyncObjects[freeVblankSyncObjectIdx].inUse = TRUE; - /* Populate the reply field. */ pParams->reply.vblankHandle = vblankHandle; /* Note: the syncpt ID is NOT the same as the vblank handle. */ @@ -4162,14 +4230,11 @@ static NvBool EnableVblankSyncObject( return TRUE; } -static void DisableAndCleanVblankSyncObject(struct NvKmsPerOpenDisp *pOpenDisp, - NvU32 apiHead, +static void DisableAndCleanVblankSyncObject(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, NVVblankSyncObjectRec *pVblankSyncObject, - NVEvoUpdateState *pUpdateState, - NvKmsVblankSyncObjectHandle handle) + NVEvoUpdateState *pUpdateState) { - NVDispEvoPtr pDispEvo = pOpenDisp->pDispEvo; - if (nvApiHeadIsActive(pDispEvo, apiHead)) { NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); @@ -4196,9 +4261,60 @@ static void DisableAndCleanVblankSyncObject(struct NvKmsPerOpenDisp *pOpenDisp, pVblankSyncObject->inUse = FALSE; pVblankSyncObject->enabled = FALSE; +} - /* Remove the handle from the map. */ - nvEvoDestroyApiHandle(&pOpenDisp->vblankSyncObjectHandles[apiHead], handle); +static void DisableAndCleanVblankSyncObjectForAllOpens(NVDevEvoRec *pDevEvo) +{ + /* + * An NVEvoUpdateState has disp-scope, and we will only have + * one disp when programming syncpts. + */ + NVEvoUpdateState updateState = { }; + struct NvKmsPerOpen *pOpen; + + if (!pDevEvo->supportsSyncpts || + !pDevEvo->hal->caps.supportsVblankSyncObjects) { + return; + } + + /* If Syncpts are supported, we're on Orin, which only has one display. */ + nvAssert(pDevEvo->nDispEvo == 1); + + nvListForEachEntry(pOpen, &perOpenIoctlList, perOpenIoctlListEntry) { + struct NvKmsPerOpenDev *pOpenDev = DevEvoToOpenDev(pOpen, pDevEvo); + struct NvKmsPerOpenDisp *pOpenDisp; + NvKmsGenericHandle disp; + + if (pOpenDev == NULL) { + continue; + } + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDev->dispHandles, + pOpenDisp, disp) { + + nvAssert(pOpenDisp->pDispEvo == pDevEvo->pDispEvo[0]); + + for (NvU32 apiHead = 0; apiHead < + ARRAY_LEN(pOpenDisp->vblankSyncObjectHandles); apiHead++) { + NVEvoApiHandlesRec *pHandles = + &pOpenDisp->vblankSyncObjectHandles[apiHead]; + NVVblankSyncObjectRec *pVblankSyncObject; + NvKmsVblankSyncObjectHandle handle; + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(pHandles, + pVblankSyncObject, handle) { + DisableAndCleanVblankSyncObject(pOpenDisp->pDispEvo, apiHead, + pVblankSyncObject, + &updateState); + } + } + } + } + + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + nvEvoUpdateAndKickOff(pDevEvo->pDispEvo[0], TRUE, &updateState, + TRUE); + } } static NvBool DisableVblankSyncObject( @@ -4245,8 +4361,8 @@ static NvBool DisableVblankSyncObject( return FALSE; } - DisableAndCleanVblankSyncObject(pOpenDisp, apiHead, pVblankSyncObject, - &updateState, pParams->request.vblankHandle); + DisableAndCleanVblankSyncObject(pOpenDisp->pDispEvo, apiHead, + pVblankSyncObject, &updateState); if (!nvIsUpdateStateEmpty(pOpenDisp->pDispEvo->pDevEvo, &updateState)) { /* @@ -4258,6 +4374,10 @@ static NvBool DisableVblankSyncObject( nvEvoUpdateAndKickOff(pOpenDisp->pDispEvo, TRUE, &updateState, TRUE); } + /* Remove the handle from the map. */ + nvEvoDestroyApiHandle(&pOpenDisp->vblankSyncObjectHandles[apiHead], + pParams->request.vblankHandle); + return TRUE; } @@ -5327,6 +5447,8 @@ void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles) static void FreeGlobalState(void) { + nvInvalidateTopologiesEvo(); + nvKmsClose(nvEvoGlobal.nvKmsPerOpen); nvEvoGlobal.nvKmsPerOpen = NULL; @@ -5795,6 +5917,13 @@ NvBool nvSurfaceEvoInAnyOpens(const NVSurfaceEvoRec *pSurfaceEvo) } #endif +NVDevEvoPtr nvGetDevEvoFromOpenDev( + const struct NvKmsPerOpenDev *pOpenDev) +{ + nvAssert(pOpenDev != NULL); + return pOpenDev->pDevEvo; +} + const struct NvKmsFlipPermissions *nvGetFlipPermissionsFromOpenDev( const struct NvKmsPerOpenDev *pOpenDev) { @@ -5862,6 +5991,8 @@ void nvKmsSuspend(NvU32 gpuId) NULL /* pTestFunc, shut down all heads */); pDevEvo->skipConsoleRestore = TRUE; + DisableAndCleanVblankSyncObjectForAllOpens(pDevEvo); + FreeSurfaceCtxDmasForAllOpens(pDevEvo); nvSuspendDevEvo(pDevEvo); @@ -5883,6 +6014,7 @@ void nvKmsResume(NvU32 gpuId) if (nvResumeDevEvo(pDevEvo)) { nvDPSetAllowMultiStreaming(pDevEvo, TRUE /* allowMST */); + EnableAndSetupVblankSyncObjectForAllOpens(pDevEvo); AllocSurfaceCtxDmasForAllOpens(pDevEvo); } diff --git a/src/nvidia/Makefile b/src/nvidia/Makefile index b7ca09b251..49e2f60575 100644 --- a/src/nvidia/Makefile +++ b/src/nvidia/Makefile @@ -59,10 +59,21 @@ CFLAGS += -I inc/libraries CFLAGS += -I src/libraries CFLAGS += -I inc/kernel +# Libspdm source requires additional include paths and build flags. +include src/libraries/libspdm/nvidia/openspdm.mk +$(call BUILD_OBJECT_LIST,$(LIBSPDM_SOURCES)): CFLAGS += $(addprefix -I ,$(LIBSPDM_INCLUDES)) +$(call BUILD_OBJECT_LIST,$(LIBSPDM_SOURCES)): CFLAGS += $(addprefix -D,$(LIBSPDM_DEFINES)) + +CFLAGS += -I $(SRC_COMMON)/mbedtls/include +CFLAGS += -I $(SRC_COMMON)/mbedtls/nvidia +CFLAGS += -DMBEDTLS_USER_CONFIG_FILE=\"nvrm_mbedtls_config.h\" + CFLAGS += -Werror-implicit-function-declaration CFLAGS += -Wwrite-strings +CFLAGS += -Wundef CFLAGS += -fno-common CFLAGS += -ffreestanding +CFLAGS += -fno-stack-protector ifeq ($(TARGET_ARCH),x86_64) CFLAGS += -msoft-float diff --git a/src/nvidia/arch/nvalloc/common/inc/conf_compute/cc_keystore.h b/src/nvidia/arch/nvalloc/common/inc/conf_compute/cc_keystore.h new file mode 100644 index 0000000000..2f30a13193 --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/conf_compute/cc_keystore.h @@ -0,0 +1,293 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CC_KEYSTORE_H +#define CC_KEYSTORE_H + +// +// Keys are typically grouped in two's so that the first key is used for CPU-to-GPU encryption +// and the second key is used for GPU-to-CPU encryption. +// + +// Keyspace identifiers. +enum +{ + CC_KEYSPACE_GSP, + CC_KEYSPACE_SEC2, + CC_KEYSPACE_LCE0, + CC_KEYSPACE_LCE1, + CC_KEYSPACE_LCE2, + CC_KEYSPACE_LCE3, + CC_KEYSPACE_LCE4, + CC_KEYSPACE_LCE5, + CC_KEYSPACE_LCE6, + CC_KEYSPACE_LCE7, + CC_KEYSPACE_SIZE // This is always the last element. +}; + +enum +{ + CC_LKEYID_GSP_CPU_LOCKED_RPC, + CC_LKEYID_CPU_GSP_LOCKED_RPC, + CC_LKEYID_GSP_CPU_DMA, + CC_LKEYID_CPU_GSP_DMA, + CC_LKEYID_CPU_GSP_RESERVED1, + CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT, + CC_LKEYID_CPU_GSP_RESERVED2, + CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT, + CC_KEYSPACE_GSP_SIZE // This is always the last element. +}; +// The fault buffers only support GPU-to-CPU encryption, so the CPU-to-GPU encryption slot +// is left reserved. + +#define CC_LKEYID_GSP_CPU_LOCKED_RPC_STR "gsp_cpu_locked_rpc" +#define CC_LKEYID_CPU_GSP_LOCKED_RPC_STR "cpu_gsp_locked_rpc" +#define CC_LKEYID_GSP_CPU_DMA_STR "gsp_cpu_dma" +#define CC_LKEYID_CPU_GSP_DMA_STR "cpu_gsp_dma" +#define CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT_STR "gsp_cpu_replayable_fault" +#define CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT_STR "gsp_cpu_non_replayable_fault" + +enum +{ + CC_LKEYID_CPU_SEC2_DATA_USER, + CC_LKEYID_CPU_SEC2_HMAC_USER, + CC_LKEYID_CPU_SEC2_DATA_KERN, + CC_LKEYID_CPU_SEC2_HMAC_KERN, + CC_KEYSPACE_SEC2_SIZE // This is always the last element. +}; + +#define CC_LKEYID_CPU_SEC2_DATA_USER_STR "cpu_sec2_data_user" +#define CC_LKEYID_CPU_SEC2_HMAC_USER_STR "cpu_sec2_hmac_user" +#define CC_LKEYID_CPU_SEC2_DATA_KERN_STR "cpu_sec2_data_kernel" +#define CC_LKEYID_CPU_SEC2_HMAC_KERN_STR "cpu_sec2_hmac_kernel" + +enum +{ + CC_LKEYID_LCE_H2D_USER, + CC_LKEYID_LCE_D2H_USER, + CC_LKEYID_LCE_H2D_KERN, + CC_LKEYID_LCE_D2H_KERN, + CC_LKEYID_LCE_H2D_P2P, + CC_LKEYID_LCE_D2H_P2P, + CC_KEYSPACE_LCE_SIZE // This is always the last element. +}; + +#define CC_KEYSPACE_TOTAL_SIZE (CC_KEYSPACE_GSP_SIZE + CC_KEYSPACE_SEC2_SIZE + (8 * CC_KEYSPACE_LCE_SIZE)) + +#define CC_LKEYID_LCE0_H2D_USER_STR "Lce0_h2d_user" +#define CC_LKEYID_LCE0_D2H_USER_STR "Lce0_d2h_user" +#define CC_LKEYID_LCE0_H2D_KERN_STR "Lce0_h2d_kernel" +#define CC_LKEYID_LCE0_D2H_KERN_STR "Lce0_d2h_kernel" +#define CC_LKEYID_LCE0_H2D_P2P_STR "Lce0_h2d_p2p" +#define CC_LKEYID_LCE0_D2H_P2P_STR "Lce0_d2h_p2p" + +#define CC_LKEYID_LCE1_H2D_USER_STR "Lce1_h2d_user" +#define CC_LKEYID_LCE1_D2H_USER_STR "Lce1_d2h_user" +#define CC_LKEYID_LCE1_H2D_KERN_STR "Lce1_h2d_kernel" +#define CC_LKEYID_LCE1_D2H_KERN_STR "Lce1_d2h_kernel" +#define CC_LKEYID_LCE1_H2D_P2P_STR "Lce1_h2d_p2p" +#define CC_LKEYID_LCE1_D2H_P2P_STR "Lce1_d2h_p2p" + +#define CC_LKEYID_LCE2_H2D_USER_STR "Lce2_h2d_user" +#define CC_LKEYID_LCE2_D2H_USER_STR "Lce2_d2h_user" +#define CC_LKEYID_LCE2_H2D_KERN_STR "Lce2_h2d_kernel" +#define CC_LKEYID_LCE2_D2H_KERN_STR "Lce2_d2h_kernel" +#define CC_LKEYID_LCE2_H2D_P2P_STR "Lce2_h2d_p2p" +#define CC_LKEYID_LCE2_D2H_P2P_STR "Lce2_d2h_p2p" + +#define CC_LKEYID_LCE3_H2D_USER_STR "Lce3_h2d_user" +#define CC_LKEYID_LCE3_D2H_USER_STR "Lce3_d2h_user" +#define CC_LKEYID_LCE3_H2D_KERN_STR "Lce3_h2d_kernel" +#define CC_LKEYID_LCE3_D2H_KERN_STR "Lce3_d2h_kernel" +#define CC_LKEYID_LCE3_H2D_P2P_STR "Lce3_h2d_p2p" +#define CC_LKEYID_LCE3_D2H_P2P_STR "Lce3_d2h_p2p" + +#define CC_LKEYID_LCE4_H2D_USER_STR "Lce4_h2d_user" +#define CC_LKEYID_LCE4_D2H_USER_STR "Lce4_d2h_user" +#define CC_LKEYID_LCE4_H2D_KERN_STR "Lce4_h2d_kernel" +#define CC_LKEYID_LCE4_D2H_KERN_STR "Lce4_d2h_kernel" +#define CC_LKEYID_LCE4_H2D_P2P_STR "Lce4_h2d_p2p" +#define CC_LKEYID_LCE4_D2H_P2P_STR "Lce4_d2h_p2p" + +#define CC_LKEYID_LCE5_H2D_USER_STR "Lce5_h2d_user" +#define CC_LKEYID_LCE5_D2H_USER_STR "Lce5_d2h_user" +#define CC_LKEYID_LCE5_H2D_KERN_STR "Lce5_h2d_kernel" +#define CC_LKEYID_LCE5_D2H_KERN_STR "Lce5_d2h_kernel" +#define CC_LKEYID_LCE5_H2D_P2P_STR "Lce5_h2d_p2p" +#define CC_LKEYID_LCE5_D2H_P2P_STR "Lce5_d2h_p2p" + +#define CC_LKEYID_LCE6_H2D_USER_STR "Lce6_h2d_user" +#define CC_LKEYID_LCE6_D2H_USER_STR "Lce6_d2h_user" +#define CC_LKEYID_LCE6_H2D_KERN_STR "Lce6_h2d_kernel" +#define CC_LKEYID_LCE6_D2H_KERN_STR "Lce6_d2h_kernel" +#define CC_LKEYID_LCE6_H2D_P2P_STR "Lce6_h2d_p2p" +#define CC_LKEYID_LCE6_D2H_P2P_STR "Lce6_d2h_p2p" + +#define CC_LKEYID_LCE7_H2D_USER_STR "Lce7_h2d_user" +#define CC_LKEYID_LCE7_D2H_USER_STR "Lce7_d2h_user" +#define CC_LKEYID_LCE7_H2D_KERN_STR "Lce7_h2d_kernel" +#define CC_LKEYID_LCE7_D2H_KERN_STR "Lce7_d2h_kernel" +#define CC_LKEYID_LCE7_H2D_P2P_STR "Lce7_h2d_p2p" +#define CC_LKEYID_LCE7_D2H_P2P_STR "Lce7_d2h_p2p" + +// Generate a global key ID from a keyspace (a) and local key ID (b). +#define CC_GKEYID_GEN(a, b) (NvU32)(((a) << 16) | (b)) + +// Get the keyspace component from a global key ID. +#define CC_GKEYID_GET_KEYSPACE(a) (NvU16)((a) >> 16) + +// Get the local key ID from a global key ID. +#define CC_GKEYID_GET_LKEYID(a) (NvU16)((a) & 0xffff) + +// Get the unqiue string from a global key ID. +#define CC_GKEYID_GET_STR(a) \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_GSP) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_LOCKED_RPC) ? \ + CC_LKEYID_GSP_CPU_LOCKED_RPC_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_GSP_LOCKED_RPC) ? \ + CC_LKEYID_CPU_GSP_LOCKED_RPC_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_DMA) ? \ + CC_LKEYID_GSP_CPU_DMA_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_GSP_DMA) ? \ + CC_LKEYID_CPU_GSP_DMA_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT) ? \ + CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT) ? \ + CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_SEC2) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_DATA_USER) ? \ + CC_LKEYID_CPU_SEC2_DATA_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_HMAC_USER) ? \ + CC_LKEYID_CPU_SEC2_HMAC_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_DATA_KERN) ? \ + CC_LKEYID_CPU_SEC2_DATA_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_CPU_SEC2_HMAC_KERN) ? \ + CC_LKEYID_CPU_SEC2_HMAC_KERN_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE0) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE0_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE0_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE0_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE0_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE0_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE0_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE1) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE1_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE1_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE1_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE1_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE1_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE1_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE2) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE2_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE2_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE2_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE2_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE2_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE2_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE3) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE3_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE3_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE3_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE3_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE3_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE3_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE4) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE4_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE4_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE4_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE4_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE4_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE4_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE5) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE5_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE5_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE5_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE5_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE5_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE5_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE6) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE6_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE6_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE6_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE6_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE6_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE6_D2H_P2P_STR : NULL : \ + (CC_GKEYID_GET_KEYSPACE(a) == CC_KEYSPACE_LCE7) ? \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_USER) ? \ + CC_LKEYID_LCE7_H2D_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_USER) ? \ + CC_LKEYID_LCE7_D2H_USER_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_KERN) ? \ + CC_LKEYID_LCE7_H2D_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_KERN) ? \ + CC_LKEYID_LCE7_D2H_KERN_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_H2D_P2P) ? \ + CC_LKEYID_LCE7_H2D_P2P_STR : \ + (CC_GKEYID_GET_LKEYID(a) == CC_LKEYID_LCE_D2H_P2P) ? \ + CC_LKEYID_LCE7_D2H_P2P_STR : NULL : NULL + +#define CC_EXPORT_MASTER_KEY_SIZE_BYTES 32 + +#endif // CC_KEYSTORE_H diff --git a/src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h b/src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h index 854c84ef17..c315524edc 100644 --- a/src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h +++ b/src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h @@ -31,10 +31,6 @@ #include "nvtypes.h" #include "flcnretval.h" -#ifndef NV_SIZEOF32 -#define NV_SIZEOF32(v) (sizeof(v)) -#endif - #ifndef NV_ARRAY_ELEMENTS #define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) #endif diff --git a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h index c43cbb22d7..0aac7349fe 100644 --- a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h +++ b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h @@ -289,4 +289,7 @@ typedef NvU8 FLCN_STATUS; // Arithmetic errors #define FLCN_ERR_ARITHMETIC_OVERFLOW (0xFAU) +// Pri errros +#define FLCN_ERR_OUTSTANDING_PRI_ERROR (0xFBU) + #endif // FLCNRETVAL_H diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h index 40f28b31c3..d24af25ba7 100644 --- a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,6 +39,8 @@ #define NVDM_TYPE_FSP_RESPONSE 0x15 #define NVDM_TYPE_INFOROM 0x17 #define NVDM_TYPE_SMBPBI 0x18 +#define NVDM_TYPE_ROMREAD 0x1A #define NVDM_TYPE_UEFI_RM 0x1C +#define NVDM_TYPE_UEFI_XTL_DEBUG_INTR 0x1D #endif // _FSP_NVDM_FORMAT_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h index 731c0fc133..d0bcc70817 100644 --- a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,9 @@ #ifndef GSP_FW_SR_META_H_ #define GSP_FW_SR_META_H_ +#define GSP_FW_SR_META_MAGIC 0x8a3bb9e6c6c39d93ULL +#define GSP_FW_SR_META_REVISION 2 + /*! * GSP firmware SR metadata * @@ -39,14 +42,14 @@ typedef struct // Magic // Use for verification by Booter // - NvU64 magic; // = GSP_FW_SR_META_MAGIC; + NvU64 magic; // = GSP_FW_SR_META_MAGIC; // // Revision number // Bumped up when we change this interface so it is not backward compatible. // Bumped up when we revoke GSP-RM ucode // - NvU64 revision; // = GSP_FW_SR_META_MAGIC_REVISION; + NvU64 revision; // = GSP_FW_SR_META_MAGIC_REVISION; // // ---- Members regarding data in SYSMEM ---------------------------- @@ -58,26 +61,26 @@ typedef struct // ---- Members for crypto ops across S/R --------------------------- // - // IV used for encryption of the Suspend/Resume data + // HMAC over the entire GspFwSRMeta structure (including padding) + // with the hmac field itself zeroed. // - NvU8 IV[32]; + NvU8 hmac[32]; - // - // Hash generated of the Suspend/Resume data - // - NvU8 hash[64]; + // Hash over GspFwWprMeta structure + NvU8 wprMetaHash[32]; - // ---- Unused members ---------------------------------------------- + // Hash over GspFwHeapFreeList structure. All zeros signifies no free list. + NvU8 heapFreeListHash[32]; + + // Hash over data in WPR2 (skipping over free heap chunks; see Booter for details) + NvU8 dataHash[32]; // - // Pad structure to exactly 256 bytes (1 DMA chunk). Can replace padding with additional - // fields without incrementing revision. Padding initialized to 0. + // Pad structure to exactly 256 bytes (1 DMA chunk). + // Padding initialized to zero. // - NvU32 padding[32]; + NvU32 padding[24]; } GspFwSRMeta; -#define GSP_FW_SR_META_REVISION 1 -#define GSP_FW_SR_META_MAGIC 0x8a3bb9e6c6c39d93ULL - #endif // GSP_FW_SR_META_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h index 9b88eb89c3..c23a8a977a 100644 --- a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -80,8 +80,26 @@ typedef struct NvU64 bootloaderDataOffset; NvU64 bootloaderManifestOffset; - NvU64 sysmemAddrOfSignature; - NvU64 sizeOfSignature; + union + { + // Used only at initial boot + struct + { + NvU64 sysmemAddrOfSignature; + NvU64 sizeOfSignature; + }; + + // + // Used at suspend/resume to read GspFwHeapFreeList + // Offset relative to GspFwWprMeta FBMEM PA (gspFwWprStart) + // + struct + { + NvU32 gspFwHeapFreeListWprOffset; + NvU32 unused0; + NvU64 unused1; + }; + }; // ---- Members describing FB layout -------------------------------- NvU64 gspFwRsvdStart; @@ -158,4 +176,25 @@ typedef struct #define GSP_FW_WPR_META_REVISION 1 #define GSP_FW_WPR_META_MAGIC 0xdc3aae21371a60b3ULL +#define GSP_FW_WPR_HEAP_FREE_REGION_COUNT 128 + +typedef struct +{ + // + // offset relative to GspFwWprMeta FBMEM PA + // describes a region at [offs, offs + length) + // + NvU32 offs; // start, inclusive + NvU32 length; +} GspFwHeapFreeRegion; + +typedef struct +{ + NvU64 magic; + NvU32 nregions; + GspFwHeapFreeRegion regions[GSP_FW_WPR_HEAP_FREE_REGION_COUNT]; +} GspFwHeapFreeList; + +#define GSP_FW_HEAP_FREE_LIST_MAGIC 0x4845415046524545ULL + #endif // GSP_FW_WPR_META_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h new file mode 100644 index 0000000000..2ccc49cff3 --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGSP_PROXY_REG_H +#define NVGSP_PROXY_REG_H + +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE 0:0 +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONFIDENTIAL_COMPUTE_ENABLE 0x00000001 + +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT 1:1 +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONF_COMPUTE_EARLY_INIT_ENABLE 0x00000001 + +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE 2:2 +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_DISABLE 0x00000000 +#define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_ENABLE 0x00000001 + +#endif // NVGSP_PROXY_REG_H diff --git a/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h b/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h index 068cc44d55..f9c8b68579 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h +++ b/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,8 +52,8 @@ static inline nv_firmware_chip_family_t nv_firmware_get_chip_family( return NV_FIRMWARE_CHIP_FAMILY_AD10X; case GPU_ARCHITECTURE_HOPPER: - if (gpuImpl == GPU_IMPLEMENTATION_GH100) - return NV_FIRMWARE_CHIP_FAMILY_GH100; + return NV_FIRMWARE_CHIP_FAMILY_GH100; + } return NV_FIRMWARE_CHIP_FAMILY_NULL; diff --git a/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h b/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h index d5f161bc32..47d84fd06d 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h +++ b/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,11 +81,11 @@ static inline const char *nv_firmware_path( { switch (fw_chip_family) { + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ga10x.bin"); - case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: @@ -100,11 +100,11 @@ static inline const char *nv_firmware_path( { switch (fw_chip_family) { + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ga10x.bin"); - case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: diff --git a/src/nvidia/arch/nvalloc/common/inc/nvcst.h b/src/nvidia/arch/nvalloc/common/inc/nvcst.h index 9a86d5e42a..daa7cda333 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvcst.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvcst.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -62,7 +62,6 @@ CHIPSET_SETUP_FUNC(Intel_A2D2_setupFunc) CHIPSET_SETUP_FUNC(Intel_A2C9_setupFunc) CHIPSET_SETUP_FUNC(Intel_A301_setupFunc) CHIPSET_SETUP_FUNC(Intel_0685_setupFunc) -CHIPSET_SETUP_FUNC(Intel_IceLake_setupFunc) CHIPSET_SETUP_FUNC(Intel_4381_setupFunc) CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc) CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc) @@ -91,6 +90,7 @@ CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc) CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc) +CHIPSET_SETUP_FUNC(Nvidia_TH500_setupFunc) // Keep string length <=32 (including termination) to avoid string copy overflow @@ -179,13 +179,13 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_INTEL, 0xA30D, CS_INTEL_A2C9, "IntelH370", Intel_A2C9_setupFunc}, {PCI_VENDOR_ID_INTEL, 0xA301, CS_INTEL_A301, "Intel-CannonLake", Intel_A301_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x0685, CS_INTEL_0685, "Intel-CometLake", Intel_0685_setupFunc}, - {PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", Intel_IceLake_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", NULL}, {PCI_VENDOR_ID_INTEL, 0x4381, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL}, - {PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", Intel_IceLake_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL}, {PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc}, {PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc}, @@ -200,6 +200,12 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc}, {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x, "T23x", Nvidia_T194_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B1, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B2, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B3, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B4, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B8, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, + {PCI_VENDOR_ID_NVIDIA, 0x22B9, CS_NVIDIA_TH500, "TH500", Nvidia_TH500_setupFunc}, {PCI_VENDOR_ID_SIS, 0x0649, CS_SIS_649, "649", SiS_656_setupFunc}, {PCI_VENDOR_ID_SIS, 0x0656, CS_SIS_656, "656", SiS_656_setupFunc}, @@ -238,6 +244,7 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD, "Mellanox BlueField", Mellanox_BlueField_setupFunc}, {PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2", NULL}, {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled", NULL}, + {PCI_VENDOR_ID_MELLANOX, 0xA2DB, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3", NULL}, {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2", Amazon_Gravitron2_setupFunc}, {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX, "Fujitsu A64FX", Fujitsu_A64FX_setupFunc}, {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, @@ -290,6 +297,7 @@ VENDORNAME vendorName[] = {PCI_VENDOR_ID_FUJITSU, "Fujitsu"}, {PCI_VENDOR_ID_CADENCE, "Cadence"}, {PCI_VENDOR_ID_ARM, "ARM"}, + {PCI_VENDOR_ID_ALIBABA, "Alibaba"}, {0, "Unknown"} // Indicates end of the table }; @@ -312,6 +320,12 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP2 {PCI_VENDOR_ID_NVIDIA, 0x22C2, CS_NVIDIA_T23x}, // NVIDIA Tegra RP0 {PCI_VENDOR_ID_NVIDIA, 0x22C3, CS_NVIDIA_T23x}, // NVIDIA Tegra RP1 + {PCI_VENDOR_ID_NVIDIA, 0x22B1, CS_NVIDIA_TH500}, // NVIDIA TH500 RP for GH100 GPU in GH180. + {PCI_VENDOR_ID_NVIDIA, 0x22B2, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x16 + {PCI_VENDOR_ID_NVIDIA, 0x22B3, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x4 + {PCI_VENDOR_ID_NVIDIA, 0x22B4, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x1 + {PCI_VENDOR_ID_NVIDIA, 0x22B8, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x8 + {PCI_VENDOR_ID_NVIDIA, 0x22B9, CS_NVIDIA_TH500}, // NVIDIA TH500 RP x2 {PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM}, // Applied Micro X-Gene "Storm" {PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2}, // Marvell ThunderX2 @@ -328,6 +342,7 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD}, // Mellanox BlueField {PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 Crypto disabled + {PCI_VENDOR_ID_MELLANOX, 0xA2DB, CS_MELLANOX_BLUEFIELD3},// Mellanox BlueField 3 {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2}, // Amazon Gravitron2 {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX}, // Fujitsu A64FX {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500}, // Phytium S2500 @@ -345,6 +360,7 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1}, // Arm Neoverse N1 {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx + {PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian // last element must have chipset CS_UNKNOWN (zero) {0, 0, CS_UNKNOWN} diff --git a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h index f1946ede03..f26c717e7b 100644 --- a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h +++ b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -112,6 +112,7 @@ #define NV_MSGBOX_CMD_ARG1_POWER_TOTAL 0x00000000 #define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER 0x00000001 #define NV_MSGBOX_CMD_ARG1_POWER_FB 0x00000002 +#define NV_MSGBOX_CMD_ARG1_POWER_MODULE 0x00000003 /* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */ #define NV_MSGBOX_CMD_ARG1_BOARD_PART_NUM_V1 0x00000000 #define NV_MSGBOX_CMD_ARG1_OEM_INFO_V1 0x00000001 @@ -134,7 +135,8 @@ #define NV_MSGBOX_CMD_ARG1_PCIE_SPEED_V1 0x00000012 #define NV_MSGBOX_CMD_ARG1_PCIE_WIDTH_V1 0x00000013 #define NV_MSGBOX_CMD_ARG1_TGP_LIMIT_V1 0x00000014 -#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX 0x00000014 /* Adjust, when adding new types */ +#define NV_MSGBOX_CMD_ARG1_MODULE_POWER_LIMIT_V1 0x00000016 +#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX 0x00000016 /* Adjust, when adding new types */ #define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_WRITE 0x00000000 #define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_READ 0x00000001 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET 0x00000000 @@ -142,6 +144,11 @@ #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SHUTDN 0x00000002 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HBM_SLOWDN 0x00000003 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SW_SLOWDN 0x00000004 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET_TLIMIT 0x00000005 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HW_SLOWDN_TLIMIT 0x00000006 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SHUTDN_TLIMIT 0x00000007 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_HBM_SLOWDN_TLIMIT 0x00000008 +#define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_SW_SLOWDN_TLIMIT 0x00000009 #define NV_MSGBOX_CMD_ARG1_GET_MISC_ECC_ENABLED_STATE 0x00000000 #define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_RESET_REQUIRED 0x00000001 #define NV_MSGBOX_CMD_ARG1_GET_MISC_GPU_FLAGS_PAGE_0 0x00000000 @@ -181,6 +188,10 @@ #define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 0x00000001 #define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 0x00000002 #define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_6 0x00000006 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 0x00000008 +#define NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 0x00000009 /* Async requests */ #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET \ @@ -219,6 +230,12 @@ 0x00000010 #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CONFIGURE_PROGRAMMABLE_EDPP \ 0x00000011 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_GET \ + 0x00000012 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET \ + 0x00000013 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_INFO_GET \ + 0x00000014 #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POLL 0x000000ff @@ -324,6 +341,9 @@ #define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_CORRECTABLE_ERROR 0 #define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_UNCORRECTABLE_ERROR 1 +#define NV_MSGBOX_CMD_ARG1_ENERGY_COUNTER_GPU 0x00000000 +#define NV_MSGBOX_CMD_ARG1_ENERGY_COUNTER_MODULE 0x00000003 + // Query type of _GET_POWER_HINT_INFO #define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_CLK 0x00000000 #define NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_TEMP 0x00000001 @@ -439,6 +459,34 @@ #define NV_MSGBOX_CMD_ARG2_REMAP_ROWS_STATE_FLAGS_PAGE0 0x00000000 +/*! + * Arg2 for _GET_PCIE_LINK_INFO + * Arg1 == _GET_PCIE_LINK_INFO_PAGE_8 + * Return TX EQ parameters + */ +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_LANE_IDX 3:0 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT 5:4 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_3 \ + 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_4 \ + 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_8_SPEED_SELECT_GEN_5 \ + 0x00000002 + +/*! + * Arg2 for _GET_PCIE_LINK_INFO + * Arg1 == _GET_PCIE_LINK_INFO_PAGE_9 + * Return RX EQ parameters + */ +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_LANE_IDX 3:0 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT 5:4 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_3 \ + 0x00000000 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_4 \ + 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GET_PCIE_LINK_INFO_PAGE_9_SPEED_SELECT_GEN_5 \ + 0x00000002 + /*! * Arg2 for _GET_POWER_HINT_INFO * ARG1 == _GET_POWER_HINT_INFO_CLK @@ -614,6 +662,18 @@ #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_ADT7473 0x00000002 #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_SFXP11_5 0x00000005 #define NV_MSGBOX_DATA_CAP_0_EXT_TEMP_BITS_SFXP24_8 0x00000008 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE 12:12 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_GET_ENERGY_COUNTER_MODULE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET 13:13 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_GET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET 14:14 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_CONTROL_SET_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET 15:15 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_MODULE_LIMIT_INFO_GET_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL 16:16 #define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_0_POWER_TOTAL_AVAILABLE 0x00000001 @@ -623,7 +683,24 @@ #define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL 18:18 #define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_0_GPU_SYSCONTROL_AVAILABLE 0x00000001 -#define NV_MSGBOX_DATA_CAP_0_THERMP_BITS 28:24 // Adjust when adding new bits +#define NV_MSGBOX_DATA_CAP_0_THERMP_BITS 28:19 // Adjust when adding new bits +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_TLIMIT_BITS 23:19 // Adjust when adding new bits +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_BITS 28:24 // Adjust when adding new bits +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT 19:19 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT 20:20 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SLOWDN_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT 21:21 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_SHUTDN_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT 22:22 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_MEMORY_TLIMIT_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT 23:23 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_GPU_SW_SLOWDOWN_TLIMIT_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC 24:24 #define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_0_THERMP_TEMP_ACOUSTIC_AVAILABLE 0x00000001 @@ -645,6 +722,9 @@ #define NV_MSGBOX_DATA_CAP_0_POWER_FB 30:30 #define NV_MSGBOX_DATA_CAP_0_POWER_FB_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_0_POWER_FB_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE 31:31 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_POWER_MODULE_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_1 1 #define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1 0:0 @@ -692,6 +772,9 @@ #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1 14:14 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1 15:15 +#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_1_ECC_V1 16:16 #define NV_MSGBOX_DATA_CAP_1_ECC_V1_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_1_ECC_V1_AVAILABLE 0x00000001 @@ -1070,16 +1153,14 @@ * Response to * NV_MSGBOX_CMD_ARG1_GET_CLOCK_THROTTLE_REASON */ -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON 31:0 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_NONE 0x00000000 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_POWER_CAP 0x00000001 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_SLOWDOWN 0x00000002 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SYNC_BOOST 0x00000004 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TLIMIT 0x00000008 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TAVG 0x00000010 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TMEM 0x00000020 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN 0x00000040 -#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_POWER_BREAK_SLOWDOWN 0x00000080 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON 31:0 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_NONE 0x00000000 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_POWER_CAP 0x00000001 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_SLOWDOWN 0x00000002 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN 0x00000004 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_POWER_BREAK_SLOWDOWN 0x00000008 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SYNC_BOOST 0x00000010 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN 0x00000020 /* * Number of Nvlink data outputs (dataOut, extData) for @@ -1105,6 +1186,8 @@ #define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_SAFE 0x00000001 #define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_ACTIVE 0x00000002 #define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_ERROR 0x00000003 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_L1_LOW_POWER 0x00000004 +#define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_NVLINK_DISABLED 0x00000005 #define NV_MSGBOX_DATA_NVLINK_INFO_LINK_STATE_V2_INVALID 0x000000ff /* Response to NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK_BANDWIDTH (in Mps) */ @@ -1171,7 +1254,7 @@ #define NV_MSGBOX_DATA_REMAP_ROW_HISTOGRAM_LOW_AVAILABILITY 15:0 #define NV_MSGBOX_DATA_REMAP_ROW_HISTOGRAM_PARTIAL_AVAILABILITY 31:16 -/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 */ +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_0 */ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED 2:0 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_UNKNOWN 0x00000000 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_LINK_SPEED_2500_MTPS 0x00000001 @@ -1191,13 +1274,61 @@ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_FATAL_ERROR_COUNT 23:16 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_0_UNSUPP_REQ_COUNT 31:24 -/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 */ +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_1 */ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_1_L0_TO_RECOVERY_COUNT 31:0 -/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_REPLAY_ROLLOVER_COUNT 15:0 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_RCVD_COUNT 31:16 +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED 2:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_UNKNOWN 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_2500_MTPS 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_5000_MTPS 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_8000_MTPS 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_16000_MTPS 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_32000_MTPS 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_RESERVED 2:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_4_TX_COUNT 31:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_6 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE 4:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_DETECT 0x00000000 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_POLLING 0x00000001 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_CONFIGURATION 0x00000002 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_RECOVERY 0x00000003 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_RECOVERY_EQZN 0x00000004 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L0 0x00000005 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L0S 0x00000006 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1 0x00000007 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_PLL_PD 0x00000008 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L2 0x00000009 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_CPM 0x0000000a +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_1 0x0000000b +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_L1_2 0x0000000c +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_HOT_RESET 0x0000000d +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LOOPBACK 0x0000000e +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_DISABLED 0x0000000f +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LINK_DOWN 0x00000010 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LINK_READY 0x00000011 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_LANES_IN_SLEEP 0x00000012 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_6_LTSSM_STATE_ILLEGAL 0x0000001f + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_PRESET 3:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_USE_PRESET 4:4 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_FS 10:5 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_LF 16:11 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 */ +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_PRESET 3:0 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_USE_PRESET 4:4 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_FS 10:5 +#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_LF 16:11 + /* * Input for NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING. Value is valid * only if Arg2 != GPM_PARTITION_AGGREGATE and Arg2.Bit7 == 1 @@ -1224,15 +1355,18 @@ /* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_2 */ #define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_SENT_COUNT 15:0 -/* Respones to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_3 */ -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED 2:0 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_UNKNOWN 0x00000000 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_2500_MTPS 0x00000001 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_5000_MTPS 0x00000002 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_8000_MTPS 0x00000003 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_16000_MTPS 0x00000004 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_32000_MTPS 0x00000005 -#define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_3_TARGET_LINK_SPEED_RESERVED 2:0 +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_4 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_4_RX_COUNT 31:0 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_8 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_PRECUR 5:0 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_MAINCUR 11:6 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_8_EQ_TX_LOCAL_POSTCUR 17:12 + +/* Response to NV_MSGBOX_CMD_ARG1_GET_PCIE_LINK_INFO_PAGE_9 */ +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_PRECUR 5:0 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_MAINCUR 11:6 +#define NV_MSGBOX_EXT_DATA_PCIE_LINK_INFO_PAGE_9_EQ_RX_REMOTE_POSTCUR 17:12 /* Response to NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM */ #define NV_MSGBOX_EXT_DATA_REMAP_ROW_HISTOGRAM_MAX_AVAILABILITY 31:16 @@ -1341,6 +1475,7 @@ typedef enum NV_MSGBOX_EVENT_TYPE_MIG_TOGGLE_SUCCESS, NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_WARM, NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_NEW, + NV_MSGBOX_EVENT_TYPE_MODULE_LIMIT_SET_SUCCESS, NV_MSGBOX_NUM_EVENTS, /* insert new event types before this line */ } NvMsgboxEventType; @@ -1680,8 +1815,10 @@ typedef enum /*! * This structure is used to hold parameters for - * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET and - * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_GET, + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET, + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_GET and + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET */ typedef struct { @@ -1693,12 +1830,12 @@ typedef struct * If flags:_CLEAR is _ON, it will clear the TGP limit. The * persistence still depends on persist flag. */ -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST 0:0 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_OFF 0x00000000 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_ON 0x00000001 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR 1:1 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_OFF 0x00000000 -#define NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_ON 0x00000001 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST 0:0 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_OFF 0x00000000 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_PERSIST_ON 0x00000001 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR 1:1 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_OFF 0x00000000 +#define NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS_FLAGS_CLEAR_ON 0x00000001 /*! * Current total GPU power limit value to enforce, requested by the @@ -1714,11 +1851,12 @@ typedef struct * in milliwatts. */ NvU32 limitCurrOutput; -} NV_MSGBOX_PMGR_PWR_TGP_LIMIT_CONTROL_PARAMS; +} NV_MSGBOX_PMGR_PWR_POWER_LIMIT_CONTROL_PARAMS; /*! * This structure is used to hold parameters for - * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_INFO_GET + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_INFO_GET and + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_INFO_GET */ typedef struct { @@ -1726,13 +1864,14 @@ typedef struct * Current total GPU power limit lower and upper bounds and the * default setting, expressed in milliwatts. * These constraints must be observed, when the limit - * is being set with - * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET. + * is being set with either + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_TGP_LIMIT_CONTROL_SET or + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_CONTROL_SET. */ NvU32 limitMin; NvU32 limitMax; NvU32 limitDefault; -} NV_MSGBOX_PMGR_PWR_TGP_LIMIT_INFO_PARAMS; +} NV_MSGBOX_PMGR_PWR_POWER_LIMIT_INFO_PARAMS; /*! * This structure is used to hold parameters for @@ -1917,6 +2056,7 @@ typedef struct // + +/*! + * Defines structures and interfaces for any SPDM Vendor-defined behavior. + */ + +/* ------------------------- NVIDIA Export Secrets -------------------------- */ + + +/* ------------------------- Macros ----------------------------------------- */ +#define SPDM_ATTESTATION_REPORT_MAX_SIZE (0x2000) +#define SPDM_MAX_MESSAGE_BUFFER_SIZE (0x1000) +#define SPDM_MAX_EXCHANGE_BUFFER_SIZE (2 * SPDM_MAX_MESSAGE_BUFFER_SIZE) +#define SPDM_MAX_CERT_CHAIN_SIZE (SPDM_MAX_MESSAGE_BUFFER_SIZE) +#define SPDM_CERT_DEFAULT_SLOT_ID (0) +#define SPDM_CAPABILITIES_CT_EXPONENT_MAX (0xFF) +#define BIN_STR_CONCAT_BUFFER_MAX_BYTES (128) + +#define NV_BYTE_TO_BIT_OVERFLOW_MASK_UINT32 (0xE0000000) +#define IS_BYTE_TO_BIT_OVERFLOW_UINT32(a) \ + ((a & NV_BYTE_TO_BIT_OVERFLOW_MASK_UINT32) != 0) + +#endif // _RMSPDMVENDORDEF_H_ diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h index cdb51417fe..c8ea2ced09 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h @@ -21,10 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// +// This file holds Unix-specific NVIDIA driver options +// + #ifndef _RM_REG_H_ #define _RM_REG_H_ #include "nvtypes.h" +#include "nv-firmware-registry.h" /* * use NV_REG_STRING to stringify a registry key when using that registry key @@ -723,72 +728,33 @@ * When this option is enabled, the NVIDIA driver will enable use of GPU * firmware. * - * Possible mode values: - * 0 - Do not enable GPU firmware - * 1 - Enable GPU firmware - * 2 - (Default) Use the default enablement policy for GPU firmware - * - * Setting this to anything other than 2 will alter driver firmware- - * enablement policies, possibly disabling GPU firmware where it would - * have otherwise been enabled by default. - * * If this key is set globally to the system, the driver may still attempt * to apply some policies to maintain uniform firmware modes across all * GPUS. This may result in the driver failing initialization on some GPUs * to maintain such a policy. - * + * * If this key is set using NVreg_RegistryDwordsPerDevice, then the driver * will attempt to honor whatever configuration is specified without applying * additional policies. This may also result in failed GPU initialzations if * the configuration is not possible (for example if the firmware is missing - * from the filesystem, or the GPU is not capable). - * - * Policy bits: - * - * POLICY_ALLOW_FALLBACK: - * As the normal behavior is to fail GPU initialization if this registry - * entry is set in such a way that results in an invalid configuration, if - * instead the user would like the driver to automatically try to fallback - * to initializing the failing GPU with firmware disabled, then this bit can - * be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). - * Note that this can result in a mixed mode configuration (ex: GPU0 has - * firmware enabled, but GPU1 does not). + * from the filesystem, or the GPU is not capable). * + * NOTE: More details for this regkey can be found in nv-firmware-registry.h */ - #define __NV_ENABLE_GPU_FIRMWARE EnableGpuFirmware #define NV_REG_ENABLE_GPU_FIRMWARE NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE) -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 -#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 - -#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 -#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 - -#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 -#define NV_REG_ENABLE_GPU_FIRMWARE_INVALID_VALUE 0xFFFFFFFF - /* * Option: EnableGpuFirmwareLogs * * When this option is enabled, the NVIDIA driver will send GPU firmware logs * to the system log, when possible. * - * Possible values: - * 0 - Do not send GPU firmware logs to the system log - * 1 - Enable sending of GPU firmware logs to the system log - * 2 - (Default) Enable sending of GPU firmware logs to the system log for - * the debug kernel driver build only + * NOTE: More details for this regkey can be found in nv-firmware-registry.h */ #define __NV_ENABLE_GPU_FIRMWARE_LOGS EnableGpuFirmwareLogs #define NV_REG_ENABLE_GPU_FIRMWARE_LOGS NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE_LOGS) -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 -#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 - /* * Option: EnableDbgBreakpoint * diff --git a/src/nvidia/arch/nvalloc/unix/include/nv.h b/src/nvidia/arch/nvalloc/unix/include/nv.h index 4212040046..067060f1be 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv.h @@ -347,6 +347,12 @@ typedef struct nv_soc_irq_info_s { /* DMA-capable device data, defined by kernel interface layer */ typedef struct nv_dma_device nv_dma_device_t; +typedef struct nv_phys_addr_range +{ + NvU64 addr; + NvU64 len; +} nv_phys_addr_range_t; + typedef struct nv_state_t { void *priv; /* private data */ @@ -466,6 +472,9 @@ typedef struct nv_state_t /* Bool to check if ISO iommu enabled */ NvBool iso_iommu_present; + /* Bool to check if NISO iommu enabled */ + NvBool niso_iommu_present; + /* Bool to check if dma-buf is supported */ NvBool dma_buf_supported; @@ -477,6 +486,8 @@ typedef struct nv_state_t /* Bool to check if the device received a shutdown notification */ NvBool is_shutdown; + /* Bool to check if the GPU has a coherent sysmem link */ + NvBool coherent; } nv_state_t; // These define need to be in sync with defines in system.h @@ -505,6 +516,8 @@ struct nv_file_private_t typedef struct gpuSession *nvgpuSessionHandle_t; typedef struct gpuDevice *nvgpuDeviceHandle_t; typedef struct gpuAddressSpace *nvgpuAddressSpaceHandle_t; +typedef struct gpuTsg *nvgpuTsgHandle_t; +typedef struct UvmGpuTsgAllocParams_tag nvgpuTsgAllocParams_t; typedef struct gpuChannel *nvgpuChannelHandle_t; typedef struct UvmGpuChannelInfo_tag *nvgpuChannelInfo_t; typedef struct UvmGpuChannelAllocParams_tag nvgpuChannelAllocParams_t; @@ -531,7 +544,7 @@ typedef struct UvmGpuPagingChannelAllocParams_tag nvgpuPagingChannelAllocPara typedef struct UvmGpuPagingChannel_tag *nvgpuPagingChannelHandle_t; typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t; typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t; -typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU64, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t); /* @@ -599,6 +612,8 @@ typedef enum #define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ ((nv)->iso_iommu_present) +#define NV_SOC_IS_NISO_IOMMU_PRESENT(nv) \ + ((nv)->niso_iommu_present) /* * GPU add/remove events */ @@ -813,6 +828,7 @@ nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); void NV_API_CALL nv_put_file_private(void *); NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode); @@ -920,6 +936,7 @@ NV_STATUS NV_API_CALL rm_write_registry_string (nvidia_stack_t *, nv_state_t * void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char *); char* NV_API_CALL rm_remove_spaces (const char *); char* NV_API_CALL rm_string_token (char **, const char); +void NV_API_CALL rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool); NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *); @@ -951,12 +968,12 @@ NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent (nvidia_stack_t *, NvU64, N NV_STATUS NV_API_CALL rm_p2p_register_callback (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *); NV_STATUS NV_API_CALL rm_p2p_put_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, void *); NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *); -NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU32, NvU32, NvU64 *, void **); -NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *); +NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **); void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle); -NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, NvU64 *); -NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64); -NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **); +NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, void *, nv_phys_addr_range_t **, NvU32 *); +void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, nv_phys_addr_range_t **, NvU32); +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *); void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *); NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); @@ -994,7 +1011,7 @@ void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *); NvBool NV_API_CALL rm_is_altstack_in_use(void); /* vGPU VFIO specific functions */ -NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); +NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32); NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); diff --git a/src/nvidia/arch/nvalloc/unix/include/os-interface.h b/src/nvidia/arch/nvalloc/unix/include/os-interface.h index 588092f618..32ccc0adc2 100644 --- a/src/nvidia/arch/nvalloc/unix/include/os-interface.h +++ b/src/nvidia/arch/nvalloc/unix/include/os-interface.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -188,7 +188,7 @@ NV_STATUS NV_API_CALL os_read_file (void *, NvU8 *, NvU64, NvU NV_STATUS NV_API_CALL os_open_readonly_file (const char *, void **); NV_STATUS NV_API_CALL os_open_and_read_file (const char *, NvU8 *, NvU64); NvBool NV_API_CALL os_is_nvswitch_present (void); -void NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); +NV_STATUS NV_API_CALL os_get_random_bytes (NvU8 *, NvU16); NV_STATUS NV_API_CALL os_alloc_wait_queue (os_wait_queue **); void NV_API_CALL os_free_wait_queue (os_wait_queue *); void NV_API_CALL os_wait_uninterruptible (os_wait_queue *); @@ -207,6 +207,9 @@ enum os_pci_req_atomics_type { OS_INTF_PCIE_REQ_ATOMICS_128BIT }; NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type); +NV_STATUS NV_API_CALL os_numa_add_gpu_memory (void *, NvU64, NvU64, NvU32 *); +NV_STATUS NV_API_CALL os_numa_remove_gpu_memory (void *, NvU64, NvU64, NvU32); +NV_STATUS NV_API_CALL os_offline_page_at_address(NvU64 address); extern NvU32 os_page_size; extern NvU64 os_page_mask; diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h new file mode 100644 index 0000000000..6a37dfa762 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/debug.h @@ -0,0 +1,211 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for debug definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_DEBUG_H +#define __X86EMU_DEBUG_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* checks to be enabled for "runtime" */ + +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ + +#ifdef X86EMU_DEBUG +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +#else +# define CHECK_IP_FETCH() 0 +# define CHECK_SP_ACCESS() 0 +# define CHECK_MEM_ACCESS() 0 +# define CHECK_DATA_ACCESS() 0 +#endif + +#ifdef X86EMU_DEBUG +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) +#else +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 +# define DEBUG_DECODE_NOPRINT() 0 +#endif + +#ifdef X86EMU_DEBUG + +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) + +/* + * The following allow us to look at the bytes of an instruction. The + * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * the decoding process. The SAVE_IP_CS is called initially when the + * major opcode of the instruction is accessed. + */ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) + +#define SAVE_IP_CS(x,y) \ + if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ + } +#else +# define INC_DECODED_INST_LEN(x) +# define DECODE_PRINTF(x) +# define DECODE_PRINTF2(x,y) +# define SAVE_IP_CS(x,y) +#endif + +#ifdef X86EMU_DEBUG +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ + if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() +#else +# define TRACE_REGS() +#endif + +#ifdef X86EMU_DEBUG +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +#else +# define SINGLE_STEP() +#endif + +#define TRACE_AND_STEP() \ + TRACE_REGS(); \ + SINGLE_STEP() + +#ifdef X86EMU_DEBUG +# define START_OF_INSTR() +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); +#else +# define START_OF_INSTR() +# define END_OF_INSTR() +# define END_OF_INSTR_NO_TRACE() +#endif + +#ifdef X86EMU_DEBUG +#include +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + NV_PRINTF(LEVEL_INFO, "%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + NV_PRINTF(LEVEL_INFO, "%04x:%04x: %s\n",u,v,n); +#else +# define CALL_TRACE(u,v,w,x,s) +# define RETURN_TRACE(n,u,v) +#endif + +#ifdef X86EMU_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void x86emu_inc_decoded_inst_len (int x); +extern void x86emu_decode_printf (const char *x); +extern void x86emu_decode_printf2 (const char *x, int y); +extern void x86emu_just_disassemble (void); +extern void x86emu_single_step (void); +extern void x86emu_end_instr (void); +extern void x86emu_dump_regs (void); +extern void x86emu_dump_xregs (void); +extern void x86emu_print_int_vect (u16 iv); +extern void x86emu_instrument_instruction (void); +extern void x86emu_check_ip_access (void); +extern void x86emu_check_sp_access (void); +extern void x86emu_check_mem_access (u32 p); +extern void x86emu_check_data_access (uint s, uint o); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DEBUG_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h new file mode 100644 index 0000000000..52eff1843b --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/decode.h @@ -0,0 +1,88 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for instruction decoding logic. +* +****************************************************************************/ + +#ifndef __X86EMU_DECODE_H +#define __X86EMU_DECODE_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Instruction Decoding Stuff */ + +#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) +#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) +#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) +#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void x86emu_intr_raise (u8 type); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); +u8* decode_rm_byte_register(int reg); +u16* decode_rm_word_register(int reg); +u32* decode_rm_long_register(int reg); +u16* decode_rm_seg_register(int reg); +u32 decode_rm00_address(int rm); +u32 decode_rm01_address(int rm); +u32 decode_rm10_address(int rm); +u32 decode_sib_address(int sib, int mod); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DECODE_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h new file mode 100644 index 0000000000..7c4f24e280 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu.h @@ -0,0 +1,61 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU instruction decoding. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_H +#define __X86EMU_FPU_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* these have to be defined, whether 8087 support compiled in or not. */ + +extern void x86emuOp_esc_coprocess_d8 (u8 op1); +extern void x86emuOp_esc_coprocess_d9 (u8 op1); +extern void x86emuOp_esc_coprocess_da (u8 op1); +extern void x86emuOp_esc_coprocess_db (u8 op1); +extern void x86emuOp_esc_coprocess_dc (u8 op1); +extern void x86emuOp_esc_coprocess_dd (u8 op1); +extern void x86emuOp_esc_coprocess_de (u8 op1); +extern void x86emuOp_esc_coprocess_df (u8 op1); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_FPU_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h new file mode 100644 index 0000000000..39ee7fe506 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/fpu_regs.h @@ -0,0 +1,119 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_REGS_H +#define __X86EMU_FPU_REGS_H + +#ifdef X86_FPU_SUPPORT + +#ifdef PACK +# pragma PACK +#endif + +/* Basic 8087 register can hold any of the following values: */ + +union x86_fpu_reg_u { + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; + }; + +struct x86_fpu_reg { + union x86_fpu_reg_u reg; + char tag; + }; + +/* + * Since we are not going to worry about the problems of aliasing + * registers, every time a register is modified, its result type is + * set in the tag fields for that register. If some operation + * attempts to access the type in a way inconsistent with its current + * storage format, then we flag the operation. If common, we'll + * attempt the conversion. + */ + +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F) + +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6 + +#define X86_FPU_STKTOP 0 + +struct x86_fpu_registers { + struct x86_fpu_reg x86_fpu_stack[8]; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; + }; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/* + * There are two versions of the following macro. + * + * One version is for opcode D9, for which there are more than 32 + * instructions encoded in the second byte of the opcode. + * + * The other version, deals with all the other 7 i87 opcodes, for + * which there are only 32 strings needed to describe the + * instructions. + */ + +#endif /* X86_FPU_SUPPORT */ + +#ifdef X86EMU_DEBUG +# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<3)+(rh)]); +# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); +#else +# define DECODE_PRINTINSTR32(t,mod,rh,rl) +# define DECODE_PRINTINSTR256(t,mod,rh,rl) +#endif + +#endif /* __X86EMU_FPU_REGS_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h new file mode 100644 index 0000000000..82d2bbe0a0 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/ops.h @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for operand decoding functions. +* +****************************************************************************/ + +#ifndef __X86EMU_OPS_H +#define __X86EMU_OPS_H + +extern void (*x86emu_optab[0x100])(u8 op1); +extern void (*x86emu_optab2[0x100])(u8 op2); + +#endif /* __X86EMU_OPS_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h new file mode 100644 index 0000000000..89780042df --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/prim_ops.h @@ -0,0 +1,141 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for primitive operation functions. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_OPS_H +#define __X86EMU_PRIM_OPS_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); +u32 pop_long (void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_PRIM_OPS_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h new file mode 100644 index 0000000000..4cd0f8b0c8 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/regs.h @@ -0,0 +1,340 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +#include "x86emu/debug.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK +#endif + +/* + * General EAX, EBX, ECX, EDX type registers. Note that for + * portability, and speed, the issue of byte swapping is not addressed + * in the registers. All registers are stored in the default format + * available on the host machine. The only critical issue is that the + * registers should line up EXACTLY in the same manner as they do in + * the 386. That is: + * + * EAX & 0xff === AL + * EAX & 0xffff == AX + * + * etc. The result is that alot of the calculations can then be + * done using the native instruction set fully. + */ + +#ifdef __BIG_ENDIAN__ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 filler0, x_reg; + } I16_reg_t; + +typedef struct { + u8 filler0, filler1, h_reg, l_reg; + } I8_reg_t; + +#else /* !__BIG_ENDIAN__ */ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 x_reg; + } I16_reg_t; + +typedef struct { + u8 l_reg, h_reg; + } I8_reg_t; + +#endif /* __BIG_ENDIAN__ */ + +typedef union { + I32_reg_t I32_reg; + I16_reg_t I16_reg; + I8_reg_t I8_reg; + } i386_general_register; + +struct i386_general_regs { + i386_general_register A, B, C, D; + }; + +typedef struct i386_general_regs Gen_reg_t; + +struct i386_special_regs { + i386_general_register SP, BP, SI, DI, IP; + u32 FLAGS; + }; + +/* + * Segment registers here represent the 16 bit quantities + * CS, DS, ES, SS. + */ + +struct i386_segment_regs { + u16 CS, DS, SS, ES, FS, GS; + }; + +/* 8 bit registers */ +#define R_AH gen.A.I8_reg.h_reg +#define R_AL gen.A.I8_reg.l_reg +#define R_BH gen.B.I8_reg.h_reg +#define R_BL gen.B.I8_reg.l_reg +#define R_CH gen.C.I8_reg.h_reg +#define R_CL gen.C.I8_reg.l_reg +#define R_DH gen.D.I8_reg.h_reg +#define R_DL gen.D.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX gen.A.I16_reg.x_reg +#define R_BX gen.B.I16_reg.x_reg +#define R_CX gen.C.I16_reg.x_reg +#define R_DX gen.D.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX gen.A.I32_reg.e_reg +#define R_EBX gen.B.I32_reg.e_reg +#define R_ECX gen.C.I32_reg.e_reg +#define R_EDX gen.D.I32_reg.e_reg + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_ESP spc.SP.I32_reg.e_reg +#define R_EBP spc.BP.I32_reg.e_reg +#define R_ESI spc.SI.I32_reg.e_reg +#define R_EDI spc.DI.I32_reg.e_reg +#define R_EIP spc.IP.I32_reg.e_reg +#define R_EFLG spc.FLAGS + +/* segment registers */ +#define R_CS seg.CS +#define R_DS seg.DS +#define R_SS seg.SS +#define R_ES seg.ES +#define R_FS seg.FS +#define R_GS seg.GS + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 + +typedef struct { + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; + /* + * MODE contains information on: + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits + */ + u32 mode; + volatile int intr; /* mask of pending interrupts */ + int debug; +#ifdef X86EMU_DEBUG + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ + char debug_cmd[64]; /* input for x86emu_single_step */ +#endif + u8 intno; + u8 __pad[3]; + } X86EMU_regs; + +/**************************************************************************** +REMARKS: +Structure maintaining the emulator machine state. + +MEMBERS: +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator +private - private data pointer +x86 - X86 registers +****************************************************************************/ +typedef struct { + unsigned long mem_base; + unsigned long mem_size; + void* private; + X86EMU_regs x86; + } X86EMU_sysEnv; + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*----------------------------- Global Variables --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Global emulator machine state. + * + * We keep it global to avoid pointer dereferences in the code for speed. + */ + +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* Function to log information at runtime */ + +void printk(const char *fmt, ...); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_REGS_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/types.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/types.h new file mode 100644 index 0000000000..53c3e871ba --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/types.h @@ -0,0 +1,93 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 emulator type definitions. +* +****************************************************************************/ + + +#ifndef __X86EMU_TYPES_H +#define __X86EMU_TYPES_H + +#ifndef NO_SYS_HEADERS +#include +#endif + +/* + * The following kludge is an attempt to work around typedef conflicts with + * . + */ +#define u8 x86emuu8 +#define u16 x86emuu16 +#define u32 x86emuu32 +#define u64 x86emuu64 +#define s8 x86emus8 +#define s16 x86emus16 +#define s32 x86emus32 +#define s64 x86emus64 +#define uint x86emuuint +#define sint x86emusint + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Currently only for Linux/32bit */ +#undef __HAS_LONG_LONG__ +#if defined(__GNUC__) && !defined(NO_LONG_LONG) +#define __HAS_LONG_LONG__ +#endif + +#define NUM32 int + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned NUM32 u32; +#ifdef __HAS_LONG_LONG__ +typedef unsigned long long u64; +#endif + +typedef char s8; +typedef short s16; +typedef NUM32 s32; +#ifdef __HAS_LONG_LONG__ +typedef long long s64; +#endif + +typedef unsigned int uint; +typedef int sint; + +typedef u16 X86EMU_pioAddr; + +#undef NUM32 + +#endif /* __X86EMU_TYPES_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h new file mode 100644 index 0000000000..935cc70225 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emu.h @@ -0,0 +1,205 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for public specific functions. +* Any application linking against us should only +* include this header +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMU_H +#define __X86EMU_X86EMU_H + +// NV +#ifndef NO_SYS_HEADERS +#define NO_SYS_HEADERS +#endif + +#ifdef SCITECH +#include "scitech.h" +#define X86API _ASMAPI +#define X86APIP _ASMAPIP +typedef int X86EMU_pioAddr; +#else +#include "x86emu/types.h" +#define X86API +#define X86APIP * +#endif +#include "x86emu/regs.h" +#include "x86emu/debug.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef PACK +# pragma PACK /* Don't pack structs with function pointers! */ +#endif + +/**************************************************************************** +REMARKS: +Data structure containing ponters to programmed I/O functions used by the +emulator. This is used so that the user program can hook all programmed +I/O for the emulator to handled as necessary by the user program. By +default the emulator contains simple functions that do not do access the +hardware in any way. To allow the emualtor access the hardware, you will +need to override the programmed I/O functions using the X86EMU_setupPioFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +inb - Function to read a byte from an I/O port +inw - Function to read a word from an I/O port +inl - Function to read a dword from an I/O port +outb - Function to write a byte to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port +****************************************************************************/ +typedef struct { + u8 (X86APIP inb)(X86EMU_pioAddr addr); + u16 (X86APIP inw)(X86EMU_pioAddr addr); + u32 (X86APIP inl)(X86EMU_pioAddr addr); + void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); + void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); + void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); + } X86EMU_pioFuncs; + +/**************************************************************************** +REMARKS: +Data structure containing ponters to memory access functions used by the +emulator. This is used so that the user program can hook all memory +access functions as necessary for the emulator. By default the emulator +contains simple functions that only access the internal memory of the +emulator. If you need specialised functions to handle access to different +types of memory (ie: hardware framebuffer accesses and BIOS memory access +etc), you will need to override this using the X86EMU_setupMemFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +rdb - Function to read a byte from an address +rdw - Function to read a word from an address +rdl - Function to read a dword from an address +wrb - Function to write a byte to an address +wrw - Function to write a word to an address +wrl - Function to write a dword to an address +****************************************************************************/ +typedef struct { + u8 (X86APIP rdb)(u32 addr); + u16 (X86APIP rdw)(u32 addr); + u32 (X86APIP rdl)(u32 addr); + void (X86APIP wrb)(u32 addr, u8 val); + void (X86APIP wrw)(u32 addr, u16 val); + void (X86APIP wrl)(u32 addr, u32 val); + } X86EMU_memFuncs; + +/**************************************************************************** + Here are the default memory read and write + function in case they are needed as fallbacks. +***************************************************************************/ +extern u8 X86API rdb(u32 addr); +extern u16 X86API rdw(u32 addr); +extern u32 X86API rdl(u32 addr); +extern void X86API wrb(u32 addr, u8 val); +extern void X86API wrw(u32 addr, u16 val); +extern void X86API wrl(u32 addr, u32 val); + +#ifdef END_PACK +# pragma END_PACK +#endif + +/*--------------------- type definitions -----------------------------------*/ + +typedef void (X86APIP X86EMU_intrFuncs)(int num); +extern X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); +void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); +void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); +void X86EMU_prepareForInt(int num); + +/* decode.c */ + +void X86EMU_exec(void); +void X86EMU_halt_sys(void); + +#ifdef X86EMU_DEBUG +#define HALT_SYS() do { \ + NV_PRINTF(LEVEL_INFO, "halt_sys: file %s, line %d\n", __FILE__, __LINE__); \ + X86EMU_halt_sys(); \ + } while (0) +#else +#define HALT_SYS() X86EMU_halt_sys() +#endif + +/* Debug options */ + +#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x000004 +#define DEBUG_DISASSEMBLE_F 0x000008 +#define DEBUG_BREAK_F 0x000010 +#define DEBUG_SVC_F 0x000020 +#define DEBUG_SAVE_IP_CS_F 0x000040 +#define DEBUG_FS_F 0x000080 +#define DEBUG_PROC_F 0x000100 +#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x000400 +#define DEBUG_INSTRUMENT_F 0x000800 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_TRACECALL_REGS_F 0x004000 +#define DEBUG_DECODE_NOPRINT_F 0x008000 +#define DEBUG_EXIT 0x010000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) + +void X86EMU_trace_regs(void); +void X86EMU_trace_xregs(void); +void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); +int X86EMU_trace_on(void); +int X86EMU_trace_off(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMU_H */ diff --git a/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h b/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h new file mode 100644 index 0000000000..5788558d8a --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/x86emu/x86emui.h @@ -0,0 +1,113 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for system specific functions. These functions +* are always compiled and linked in the OS depedent libraries, +* and never in a binary portable driver. +* +****************************************************************************/ + + +#ifndef __X86EMU_X86EMUI_H +#define __X86EMU_X86EMUI_H + +/* If we are compiling in C++ mode, we can compile some functions as + * inline to increase performance (however the code size increases quite + * dramatically in this case). + */ + +// NV +#ifndef NO_SYS_HEADERS +#define NO_SYS_HEADERS +#endif +#include /* NULL */ +#if defined(__cplusplus) && !defined(_NO_INLINE) +#define _INLINE inline +#else +#define _INLINE static +#endif + +/* Get rid of unused parameters in C++ compilation mode */ + +#ifdef __cplusplus +#define X86EMU_UNUSED(v) +#else +#define X86EMU_UNUSED(v) v +#endif + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/decode.h" +#include "x86emu/ops.h" +#include "x86emu/prim_ops.h" +#include "x86emu/fpu.h" +#include "x86emu/fpu_regs.h" + +#ifndef NO_SYS_HEADERS +#include +#include +#include +#endif + +// On x86_64 abs() is not recognized. I don't understand why. +#ifndef abs +#define abs(i) __builtin_abs(i) +#endif + +/*--------------------------- Inline Functions ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern u8 (X86APIP sys_rdb)(u32 addr); +extern u16 (X86APIP sys_rdw)(u32 addr); +extern u32 (X86APIP sys_rdl)(u32 addr); +extern void (X86APIP sys_wrb)(u32 addr,u8 val); +extern void (X86APIP sys_wrw)(u32 addr,u16 val); +extern void (X86APIP sys_wrl)(u32 addr,u32 val); + +extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); +extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); +extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); +extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); +extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); +extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMUI_H */ diff --git a/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c index ad8684ca2a..f42896a929 100644 --- a/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c +++ b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c @@ -23,17 +23,2062 @@ #include +/* + * NOTE: + * The driver disables dynamic power management by effectively setting + * nv_dynamic_power_t::mode to NV_DYNAMIC_PM_NEVER at two places: + * 1) During module probe, when the _PRx methods are not supported + * by the SBIOS or when the kernel does not support runtime PM. + * 2) During RM Init, when the GPU is not Turing+ or when the system is not + * a laptop or when the VBIOS does not support RTD3/GC6. + * + * Thus, after RMInit, if the nv_dynamic_power_t::mode is still + * NV_DYNAMIC_PM_FINE, then we know for sure that the fine grained power + * control is active and running. In this case, the runtime D3 status is + * shown as "Enabled (fine-grained)". + * + * If the nv_dynamic_power_t::mode is NV_DYNAMIC_PM_NEVER, we have to + * distinguish between four cases: + * 1) The driver disabled dynamic power management due to lack of kernel/SBIOS + * support. + * 2) The driver disabled dynamic power management because the GPU does not + * support it or the system is not a laptop. + * 3) The user has explicitly disabled the feature. + * 4) Configuration is not supported by default. + * + * In order to differentiate between these four cases, + * we use the value of regkey NVreg_DynamicPowerManagement. If this value is + * set to 0, then we know that the user has explicitly disabled the + * feature. In this case we show the runtime D3 status as "Disabled". This + * handles case (3) above. + * + * For case (4), we look at the combination of nv_dynamic_power_t::mode and + * NVreg_DynamicPowerManagement value. If mode is never and regkey value is + * default, then status is shown as "Disabled by default". + * + * For remaining cases, (case (1) and (2)) we show status as "Not Supported". + * + * When the regkey is set to 0 and the driver disables the feature due to lack + * of some support, then precedence will be given to regkey value. Thus, when + * both "Not supported" and "Disabled" are possible values, precedence will be + * given to "Disabled" over "Not Supported". + * + * For coarse-grain power control, we show runtime D3 status as + * "Enabled (coarse-grained)". + * + * The runtime D3 status is shown as "?" when RM has not been initialized. + * This is because we do not have full knowledge regarding driver triggered + * disablement until RM is initialized. + */ + #include #include #include #include #include -#include +#include + +#include +#include +#include +#include "kernel/gpu/intr/intr.h" + +#include +#include +#include +#include + +// +// Schedule timer based callback, to check for the complete GPU Idleness. +// Windows has idle time from 70msec to 10sec, we opted for present duration +// considering windows limit. Duration is not much aggressive or slow, hence +// less thrashing. +// +#define GC6_PRECONDITION_CHECK_TIME ((NvU64)5 * 1000 * 1000 * 1000) + +// +// Timeout needed for back to back GC6 cycles. +// Timeout is kept same as the timeout selected for GC6 precondition check. +// There are cases where GPU is in GC6 and then kernel wakes GPU out of GC6 +// as part of say accessing pci tree through lspci and then again ask driver +// to put GPU in GC6 state after access to device info is done. +// Below are the reasons for having timeout limit for back to back GC6 cycle. +// 1> Less chip life cycle. +// 2> P-state is not reached to GC6 supported P-state, in some cycles. +// P-state case returns error to kernel, resulting in corrupted sysfs entry +// and then kernel never calls driver to put device in low power state. +// +#define GC6_CYCLE_IDLE_HOLDOFF_CHECK_TIME GC6_PRECONDITION_CHECK_TIME + +// +// Once GPU is found to be idle, driver will schedule another callback of +// smaller duration. Driver needs to be sure that methods that are present +// in host pipeline are flushed to the respective engines and engines become +// idle upon consumption. +// +#define GC6_BAR1_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME (200 * 1000 * 1000) + +// +// Cap Maximum FB allocation size for GCOFF. If regkey value is greater +// than this value then it will be capped to this value. +// +#define GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB 1024 + +static void RmScheduleCallbackForIdlePreConditions(OBJGPU *); +static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock(OBJGPU *); +static void RmScheduleCallbackToIndicateIdle(OBJGPU *); +static NvBool RmCheckForGc6SupportOnCurrentState(OBJGPU *); +static void RmScheduleCallbackToRemoveIdleHoldoff(OBJGPU *); +static void RmQueueIdleSustainedWorkitem(OBJGPU *); + +/*! + * @brief Wrapper that checks lock order for the dynamic power mutex. Locking + * order dictates that the GPU lock must not be taken before taking the dynamic + * power mutex. + * + * The GPU lock must not be held when calling this function. + * + * @param[in] nvp nv_priv_t pointer. + */ +static void acquireDynamicPowerMutex(nv_priv_t *nvp) +{ + /* + * Note that this may be called before nvp->pGpu has been initialized, for + * example at the very beginning of nv_start_device. + */ + NV_ASSERT_CHECKED(!nvp->pGpu || !rmDeviceGpuLockIsOwner(nvp->pGpu->gpuInstance)); + + portSyncMutexAcquire(nvp->dynamic_power.mutex); +} + +/*! + * @brief Wrapper to release the mutex, just for consistency with + * acquireDynamicPowerMutex() above. + * + * @param[in] nvp nv_priv_t pointer. + */ +static void releaseDynamicPowerMutex(nv_priv_t *nvp) +{ + portSyncMutexRelease(nvp->dynamic_power.mutex); +} + +/*! + * @brief: Helper function to get a string for the given state. + * + * @param[in] state Dynamic power state. + * + * @return String for the given state. + */ +const char *nv_dynamic_power_state_string( + nv_dynamic_power_state_t state +) +{ + switch (state) + { +#define DPCASE(_case) \ + case NV_DYNAMIC_POWER_STATE_ ## _case: return # _case; + + DPCASE(IN_USE); + DPCASE(IDLE_INSTANT); + DPCASE(IDLE_SUSTAINED); + DPCASE(IDLE_INDICATED); + DPCASE(UNKNOWN); +#undef DPCASE + } + NV_ASSERT(0); + return "UNEXPECTED"; +} + +/*! + * @brief: Helper function to transition the GPU represented by the 'nv' + * pointer from the power state 'old_state' to the power state 'new_state'. + * + * An atomic compare-and-swap is used; the function returns true if the + * operation was successful. If the function returns false, the state is + * unchanged. + * + * @param[in] nv nv_state_t pointer. + * @param[in] old_state Previous (current) state. + * @param[in] new_state New (requested) state. + * + * @return TRUE if the operation was successful; FALSE otherwise. + */ +NvBool nv_dynamic_power_state_transition( + nv_state_t *nv, + nv_dynamic_power_state_t old_state, + nv_dynamic_power_state_t new_state +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + NV_ASSERT(old_state != new_state); + + ct_assert(sizeof(nv_dynamic_power_state_t) == sizeof(NvS32)); + NvBool ret = portAtomicCompareAndSwapS32((NvS32*)&nvp->dynamic_power.state, + new_state, old_state); + + if (ret) + { + NV_PRINTF(LEVEL_INFO, "%s: state transition %s -> %s\n", + __FUNCTION__, + nv_dynamic_power_state_string(old_state), + nv_dynamic_power_state_string(new_state)); + } + else + { + NV_PRINTF(LEVEL_INFO, "%s: FAILED state transition %s -> %s\n", + __FUNCTION__, + nv_dynamic_power_state_string(old_state), + nv_dynamic_power_state_string(new_state)); + } + + return ret; + +} + +/*! + * @brief: Check if the GPU hardware appears to be idle. + * + * Assumes the GPU lock is held. + * + * @param[in] pGpu OBJGPU pointer. + * + * @return TRUE if the GPU appears to be currently idle; FALSE otherwise. + */ +static NvBool RmCheckForGpuIdlenessUnderGpuLock( + OBJGPU *pGpu +) +{ + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + // Check the instantaneous engine level idleness. + return RmCheckForGc6SupportOnCurrentState(pGpu); +} + +/*! + * @brief: Check if the GPU hardware appears to be idle. + * + * Takes the GPU lock. + * + * @param[in] pGpu OBJGPU pointer. + * + * @return TRUE if the GPU appears to be currently idle; FALSE otherwise. + */ +static NvBool RmCheckForGpuIdleness( + OBJGPU *pGpu +) +{ + NvBool result = NV_FALSE; + NV_STATUS status; + GPU_MASK gpuMask; + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask); + if (status == NV_OK) + { + result = RmCheckForGpuIdlenessUnderGpuLock(pGpu); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + return result; +} + +/*! + * @brief: Force the GPU to be "not idle", if it had previously been indicated + * idle. This is triggered by GPU usage (i.e., writing through a revoked + * mapping), not tracked through the refcount maintained through + * os_{ref,unref}_dynamic_power. So, if we'd previously indicated the GPU was + * idle, we transition to the IDLE_INSTANT state. + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmForceGpuNotIdle( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + nv_dynamic_power_state_t old_state; + NvBool ret; + + acquireDynamicPowerMutex(nvp); + + old_state = nvp->dynamic_power.state; + + switch (old_state) + { + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + nv_indicate_not_idle(nv); + NV_ASSERT(nvp->dynamic_power.deferred_idle_enabled); + RmScheduleCallbackForIdlePreConditions(pGpu); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + ret = nv_dynamic_power_state_transition(nv, old_state, NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + NV_ASSERT(ret); + break; + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + break; + } + + /* + * Now that the GPU is guaranteed to not be powered off, we can resume + * servicing mmap requests as usual. + */ + nv_acquire_mmap_lock(nv); + nv_set_safe_to_mmap_locked(nv, NV_TRUE); + nv_release_mmap_lock(nv); + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief: Work item to actually indicate the GPU is idle. This rechecks the + * preconditions one last time and verifies nothing has attempted to write + * through any mappings which were revoked. + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmIndicateIdle( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + acquireDynamicPowerMutex(nvp); + + nv_acquire_mmap_lock(nv); + + if (nv_get_all_mappings_revoked_locked(nv) && + nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED && + RmCheckForGpuIdleness(pGpu)) + { + nv_set_safe_to_mmap_locked(nv, NV_FALSE); + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INDICATED); + nv_indicate_idle(nv); + } + else + { + RmScheduleCallbackForIdlePreConditions(pGpu); + } + + nv_release_mmap_lock(nv); + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief: Helper function to trigger the GPU to be forced indicated + * "non-idle", which powers it on if it had been previously powered off, and + * allows mmap processing to continue. + * + * Triggered when a revoked mapping is accessed. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + void *fp; + NV_STATUS ret; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + OBJOS *pOS = GPU_GET_OS(pGpu); + + NV_ENTER_RM_RUNTIME(sp, fp); + + ret = pOS->osQueueWorkItem(pGpu, RmForceGpuNotIdle, NULL); + + NV_EXIT_RM_RUNTIME(sp, fp); + + return ret; +} + +/*! + * @brief Function to increment/decrement refcount for GPU driving console. + * + * @params[in] nv nv_state_t pointer. + * @params[in] bIncrease If true, increase refcount else decrease. + */ +void +RmUpdateGc6ConsoleRefCount +( + nv_state_t *nv, + NvBool bIncrease +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (nv->console_device == NV_FALSE) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + if (bIncrease) + { + /* + * Here refcount value should atleast be 2 due to below: + * 1> Refcount increased by NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT. + * 2> Refcount increased by the Rm entry points for current thread. + */ + if (nvp->dynamic_power.refcount <= 1) + { + NV_PRINTF(LEVEL_INFO, + "%s: Unexpected dynamic power refcount value\n", __FUNCTION__); + } + else + { + nvp->dynamic_power.refcount++; + } + } + else + { + /* + * Here refcount value should atleast be 3 due to below: + * 1> Refcount set by RM at the probe time for console device. + * 2> Refcount increased by NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT. + * 3> Refcount increased by the Rm entry points for current thread. + */ + if (nvp->dynamic_power.refcount <= 2) + { + NV_PRINTF(LEVEL_INFO, + "%s: Unexpected dynamic power refcount value\n", __FUNCTION__); + } + else + { + nvp->dynamic_power.refcount--; + } + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT RmControl + * request. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid pParams->action + */ +NV_STATUS +subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + /* TODO: keep track of inc/dec on a per-client basis, clean up after + * clients which are unbalanced. */ + if (pParams->action == NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC) + { + return osRefGpuAccessNeeded(pGpu->pOsGpuInfo); + } + else if (pParams->action == NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC) + { + osUnrefGpuAccessNeeded(pGpu->pOsGpuInfo); + } + else + { + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER RmControl + * request. It will perform dynamic power management for GPU + * HDA contoller. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + */ +NV_STATUS +subdeviceCtrlCmdOsUnixAudioDynamicPower_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + /* + * Ideally, we need to honor pParams->bEnter. If it is true, then send the + * request for suspending the HDA controller and if is false, then send the + * request for waking up the HDA controller. Currently, for unix based OS, + * we don't have any proper way to do this and it is implemented with + * workaround. This workaround will wake up the HDA controller for few + * seconds and then bring it back to suspended state. We are using this + * workaround for both the cases (bEnter is true or false). It will help + * in keeping HDA controller active for the duration, when GPU is + * processing HDA controller commands (like writing ELD data). + */ + nv_audio_dynamic_power(NV_GET_NV_STATE(pGpu)); + + return NV_OK; +} + +/*! + * @brief: Function to indicate if Video Memory is powered off or not by + * checking if GPU is in GCOFF state. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] pNv nv_state_t pointer. + * + * @return String indicating Video Memory power status. + */ + +const char* NV_API_CALL rm_get_vidmem_power_status( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + void *fp; + GPU_MASK gpuMask; + const char *pVidmemPowerStatus = "?"; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // LOCK: acquire per device lock + if ((pGpu != NULL) && + ((rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask)) == NV_OK)) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED)) + { + pVidmemPowerStatus = "Off"; + } + else + { + pVidmemPowerStatus = "Active"; + } + + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return pVidmemPowerStatus; +} + +/*! + * @brief: Function to indicate if GC6/GC-OFF is supported + * or not on the SKU. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] pNv nv_state_t pointer. + * @param[in] bGcxTypeGc6 If true, returns string indicating GC6 support + * otherwise returns GC-OFF support. + * + * @return String indicating GC6/GC-OFF support status. + */ +const char* NV_API_CALL rm_get_gpu_gcx_support( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvBool bGcxTypeGC6 +) +{ + THREAD_STATE_NODE threadState; + void *fp; + GPU_MASK gpuMask; + const char *pSupported = "?"; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // LOCK: acquire per device lock + if ((pGpu != NULL) && + ((rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask)) == NV_OK)) + { + pSupported = "Not Supported"; + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED)) + { + goto done; + } + + if (bGcxTypeGC6) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED)) + { + pSupported = "Supported"; + } + } + else + { + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED)) || + (pGpu->getProperty(pGpu, PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED))) + { + pSupported = "Supported"; + } + } + +done: + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } + + //UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return pSupported; +} + +/*! + * @brief Function to increment/decrement global Gcoff disallow refcount. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer. + * @params[in] bIsGcoffDisallow If true, increase refcount else decrease. + */ +void osClientGcoffDisallowRefcount( + OS_GPU_INFO *pOsGpuInfo, + NvBool bIsGcoffDisallow +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pOsGpuInfo); + + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_NEVER) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + if (bIsGcoffDisallow) + { + nvp->dynamic_power.clients_gcoff_disallow_refcount++; + } + else + { + nvp->dynamic_power.clients_gcoff_disallow_refcount--; + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Implements the NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF RmControl + * request. + * + * @param[in] pSubdevice + * @param[in,out] pParams + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid pParams->action + * NV_ERR_INVALID_OBJECT_HANDLE Invalid Object handle + * NV_ERR_OBJECT_NOT_FOUND Object not found + */ +NV_STATUS +subdeviceCtrlCmdOsUnixAllowDisallowGcoff_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *pParams +) +{ + NV_STATUS status; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + if (pParams->action == NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW) + { + if (pSubdevice->bGcoffDisallowed) + { + pSubdevice->bGcoffDisallowed = NV_FALSE; + osClientGcoffDisallowRefcount(pGpu->pOsGpuInfo, NV_FALSE); + status = NV_OK; + } + else + { + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + } + else if (pParams->action == NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW) + { + if (!pSubdevice->bGcoffDisallowed) + { + pSubdevice->bGcoffDisallowed = NV_TRUE; + osClientGcoffDisallowRefcount(pGpu->pOsGpuInfo, NV_TRUE); + status = NV_OK; + } + else + { + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + + return status; +} + +/*! + * @brief Read and Parse the Dynamic Power Management regkey. + * This function modifies the default value of regkey to either enable + * or disable RTD3 as per System form factor and GPU architecture. + * + * @param[in] pNv nv_state_t pointer. + * @param[out] pRegkeyValue Original value of regkey. + * @param[out] pOption Modified value of regkey. + * + * @return NV_STATUS code. + */ + +#define NV_PMC_BOOT_42_CHIP_ID_GA102 0x00000172 + +static NV_STATUS +rmReadAndParseDynamicPowerRegkey +( + nv_state_t *pNv, + NvU32 *pRegkeyValue, + NvU32 *pOption +) +{ + NV_STATUS status; + NvU32 chipId; + nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv); + + status = osReadRegistryDword(NULL, NV_REG_DYNAMIC_POWER_MANAGEMENT, pRegkeyValue); + + if (status != NV_OK) + return status; + + // If User has set some value, honor that value + if (*pRegkeyValue != NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT) + { + *pOption = *pRegkeyValue; + return NV_OK; + } + + chipId = DRF_VAL(_PMC, _BOOT_42, _CHIP_ID, pNvp->pmc_boot_42); + + // From GA102+, we enable RTD3 only if system is found to be Notebook + if ((chipId >= NV_PMC_BOOT_42_CHIP_ID_GA102) && + (rm_is_system_notebook())) + { + *pOption = NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE; + return NV_OK; + } + + *pOption = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + return NV_OK; +} +#undef NV_PMC_BOOT_42_CHIP_ID_GA102 + +/*! + * @brief Initialize state related to dynamic power management. + * Called once per GPU during driver initialization. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_init_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv, + NvBool bPr3AcpiMethodPresent +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 option = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + NvU32 gcOffMaxFbSizeMb; + void *fp; + NvBool bUefiConsole; + NvU32 status; + NvU32 regkeyValue; + + NV_ENTER_RM_RUNTIME(sp,fp); + + portMemSet(&nvp->dynamic_power, 0, sizeof(nvp->dynamic_power)); + + /* + * Program an impossible value so that we show correct status + * during procfs read of runtime D3 status. + */ + nvp->dynamic_power.dynamic_power_regkey = 0xFFFFFFFFu; + + /* + * Dynamic power management will be disabled in either of + * following 3 cases: + * 1. The driver does not support dynamic PM for this + * distro/kernel version. + * 2. _PR3 ACPI method is not supported by upstream port of GPU. + * 3. This feature is not enabled by regkey. + * Also see NOTE + */ + status = rmReadAndParseDynamicPowerRegkey(nv, ®keyValue, &option); + + if (status == NV_OK) + { + nvp->dynamic_power.dynamic_power_regkey = regkeyValue; + } + + if (!nv_dynamic_power_available(nv) || !bPr3AcpiMethodPresent || + (status != NV_OK)) + { + NV_PRINTF(LEVEL_NOTICE, + "%s: Disabling dynamic power management either due to lack" + " of system support or due to error (%d) in reading regkey." + "\n", __FUNCTION__, status); + option = NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER; + } + + /* + * Read the OS registry for Maximum FB size during GCOFF based dynamic PM. + * This will be capped to GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB. + */ + if (osReadRegistryDword(NULL, + NV_REG_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, + &gcOffMaxFbSizeMb) == NV_OK) + { + if (gcOffMaxFbSizeMb > GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB) + gcOffMaxFbSizeMb = GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB; + } + else + { + gcOffMaxFbSizeMb = GCOFF_DYNAMIC_PM_MAX_FB_SIZE_MB; + } + + nvp->dynamic_power.gcoff_max_fb_size = + (NvU64)gcOffMaxFbSizeMb * 1024 * 1024; + + nvp->dynamic_power.mutex = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + if (nvp->dynamic_power.mutex == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "%s: failed to create power mutex\n", __FUNCTION__); + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + goto done; + } + + switch (option) + { + case NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_FINE; + break; + case NV_REG_DYNAMIC_POWER_MANAGEMENT_COARSE: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_COARSE; + break; + default: + nv_printf(LEVEL_ERROR, + "NVRM: Unknown DynamicPowerManagement value '%u' specified; " + "disabling dynamic power management.\n", option); + // fallthrough + case NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER: + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + break; + } + + // Enable RTD3 infrastructure from OS side. + if ((nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) && + (nvp->dynamic_power.dynamic_power_regkey == NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT)) + { + nv_allow_runtime_suspend(nv); + } + + // Legacy case: check if device is primary and driven by VBIOS or fb driver. + nv->primary_vga = NV_FALSE; + + // + // Below function always return NV_OK and depends upon kernel flags + // IORESOURCE_ROM_SHADOW & PCI_ROM_RESOURCE for Primary VGA detection. + // + nv_set_primary_vga_status(nv); + + // UEFI case: where console is driven by GOP driver. + bUefiConsole = rm_get_uefi_console_status(nv); + + nv->console_device = bUefiConsole || nv->primary_vga; + + // + // Initialize refcount as 1 and state as IN_USE. + // rm_enable_dynamic_power_management() will decrease the refcount + // and change state to IDLE_INDICATED, if all prerequisites are met. + // + nvp->dynamic_power.refcount = 1; + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_UNKNOWN, + NV_DYNAMIC_POWER_STATE_IN_USE); +done: + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Clean up state related to dynamic power management. + * Called during driver removal. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_cleanup_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + void *fp; + NvBool ret; + + NV_ENTER_RM_RUNTIME(sp,fp); + + // Disable RTD3 infrastructure from OS side. + if ((nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) && + (nvp->dynamic_power.dynamic_power_regkey == NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT)) + { + nv_disallow_runtime_suspend(nv); + } + + nv_dynamic_power_state_t old_state = nvp->dynamic_power.state; + + switch (old_state) + { + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + nv_indicate_not_idle(nv); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + ret = nv_dynamic_power_state_transition(nv, old_state, + NV_DYNAMIC_POWER_STATE_IN_USE); + /* + * Nothing else should be running asynchronous to teardown that could + * change the state so this should always succeed. + */ + NV_ASSERT(ret); + break; + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + break; + } + + if (nvp->dynamic_power.mutex) + { + portSyncMutexDestroy(nvp->dynamic_power.mutex); + nvp->dynamic_power.mutex = NULL; + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Initialize the dynamic power management refcount and enable GPUOFF, + * if all prerequisites are met. + * Called once per GPU during driver initialization. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void NV_API_CALL rm_enable_dynamic_power_management( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + /* + * If dynamic power management is enabled and device is not driving console, + * then dynamic power management can be engaged (since we're not + * using the GPU yet, so it's okay to power it off). + */ + if ((nvp->dynamic_power.mode != NV_DYNAMIC_PM_NEVER) && !nv->console_device) + { + os_unref_dynamic_power(nv, NV_DYNAMIC_PM_COARSE); + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/* + * @brief Increment the dynamic power refcount to prevent the GPU from being + * powered off until a corresponding os_unref_dynamic_power() call is made. + * These two calls must always be balanced in pairs. + * + * This call may block until the GPU is powered on. + * + * The caller must not be holding the GPU lock, but may be holding the API + * lock. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +NV_STATUS +os_ref_dynamic_power( + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NV_STATUS status = NV_OK; + NvS32 ref; + + if (nvp == NULL) + { + NV_ASSERT(nv->removed); + return NV_OK; + } + + if (mode > nvp->dynamic_power.mode) + { + return NV_OK; + } + + acquireDynamicPowerMutex(nvp); + + ref = nvp->dynamic_power.refcount++; + + NV_ASSERT(ref >= 0); + + if (ref > 0) + { + NV_ASSERT(nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IN_USE); + } + else + { + /* + * Just transitioned from 0 -> 1. + * The current dynamic power state could be any of: + * + * - IDLE_INDICATED: call nv_indicate_not_idle() to ensure + * the GPU is at full power and ready to be used. + * + * - IDLE_INSTANT/IDLE_SUSTAINED: transition to IN_USE. + * Note that in these states, callbacks may be operating + * asynchronously, so care has to be taken to retry the write if it + * fails. + */ + + nv_dynamic_power_state_t old_state = nvp->dynamic_power.state; + NvBool ret; + + switch (old_state) + { + default: + case NV_DYNAMIC_POWER_STATE_IN_USE: + NV_PRINTF(LEVEL_ERROR, "NVRM: %s: Unexpected dynamic power state 0x%x\n", + __FUNCTION__, old_state); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + status = nv_indicate_not_idle(nv); + if (status != NV_OK) + { + nvp->dynamic_power.refcount--; + break; + } + if (nvp->dynamic_power.deferred_idle_enabled) + { + RmScheduleCallbackForIdlePreConditions(NV_GET_NV_PRIV_PGPU(nv)); + } + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + do { + ret = nv_dynamic_power_state_transition(nv, old_state, NV_DYNAMIC_POWER_STATE_IN_USE); + if (!ret) + { + old_state = nvp->dynamic_power.state; + NV_ASSERT(old_state == NV_DYNAMIC_POWER_STATE_IDLE_INSTANT || + old_state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED); + } + } while (!ret); + break; + } + } + + releaseDynamicPowerMutex(nvp); + + return status; +} + +/*! + * @brief Wrapper around os_ref_dynamic_power() suitable for use from the + * per-OS layers. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +NV_STATUS NV_API_CALL rm_ref_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + NV_STATUS status; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + status = os_ref_dynamic_power(nv, mode); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +/*! + * @brief Decrement the dynamic power refcount to release an earlier + * requirement that the GPU be powered on made by calling + * os_ref_dynamic_power(). + * These two calls must always be balanced in pairs. + * + * This call may block until the GPU is powered on. + * + * The caller must not be holding the GPU lock, but may be holding the API + * lock. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +void +os_unref_dynamic_power( + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvS32 ref; + + if (nvp == NULL) + { + NV_ASSERT(nv->removed); + return; + } + + if (mode > nvp->dynamic_power.mode) + { + return; + } + + acquireDynamicPowerMutex(nvp); + + ref = --nvp->dynamic_power.refcount; + + NV_ASSERT(ref >= 0); + + if (ref == 0) { + NvBool ret; + + /* + * Just transitioned from 1 -> 0. We should have been in the IN_USE + * state previously; now we transition to an idle state: "instant" idle + * if deferred idle is enabled; otherwise indicate idle immediately. + * + * Nothing should be asynchronously changing the state from IN_USE, + * so the state transitions are not expected to fail. + */ + + NV_ASSERT(nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IN_USE); + + if (nvp->dynamic_power.deferred_idle_enabled) + { + ret = nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IN_USE, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + NV_ASSERT(ret); + } + else + { + nv_indicate_idle(nv); + ret = nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IN_USE, + NV_DYNAMIC_POWER_STATE_IDLE_INDICATED); + NV_ASSERT(ret); + } + } + + releaseDynamicPowerMutex(nvp); +} + +/*! + * @brief Wrapper around os_unref_dynamic_power() suitable for use from the + * per-OS layers. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] mode Dynamic power mode this refcount bump is used for. + */ +void NV_API_CALL rm_unref_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + nv_dynamic_power_mode_t mode +) +{ + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + os_unref_dynamic_power(nv, mode); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + +/*! + * @brief Wrapper around os_ref_dynamic_power() suitable for use from core RM. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer + */ +NV_STATUS osRefGpuAccessNeeded( + OS_GPU_INFO *pOsGpuInfo +) +{ + return os_ref_dynamic_power(pOsGpuInfo, NV_DYNAMIC_PM_FINE); +} + +/*! + * @brief Wrapper around os_unref_dynamic_power() suitable for use from core RM. + * + * @params[in] pOsGpuInfo OS specific GPU information pointer + */ +void osUnrefGpuAccessNeeded( + OS_GPU_INFO *pOsGpuInfo +) +{ + os_unref_dynamic_power(pOsGpuInfo, NV_DYNAMIC_PM_FINE); +} + +/*! + * @brief Check if GC6 is supported on current pstate and if engines are idle. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NvBool RmCheckForGc6SupportOnCurrentState( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS entryPrerequisiteParams; + + portMemSet(&entryPrerequisiteParams, 0, sizeof(entryPrerequisiteParams)); + + status = pRmApi->Control(pRmApi, + nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE, + (void*)&entryPrerequisiteParams, + sizeof(entryPrerequisiteParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM, Failed to get GC6 pre-requisite, status=0x%x\n", + status); + return NV_FALSE; + } + + return entryPrerequisiteParams.bIsSatisfied; +} + +/*! + * @brief: Work item to actually remove the idle holdoff which was applied + * on GC6 exit. + * This workitem is scheduled after the timeout limit for idle holdoff is + * finished. + * + * Queue with lock flags: + * OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW + * + * @param[in] gpuInstance GPU instance ID. + * @param[in] pArgs Unused callback closure. + */ +static void RmRemoveIdleHoldoff( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + if (nvp->dynamic_power.b_idle_holdoff == NV_TRUE) + { + if ((RmCheckForGc6SupportOnCurrentState(pGpu) == NV_TRUE) || + (nvp->dynamic_power.idle_precondition_check_callback_scheduled)) + { + nv_indicate_idle(nv); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + else + { + RmScheduleCallbackToRemoveIdleHoldoff(pGpu); + } + } +} + +/*! + * @brief Timer callback to schedule a work item to remove idle hold off + * that was applied after GC6 exit. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackToRemoveIdleHoldoff( + void *pCallbackData +) +{ + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + OBJOS *pOS = GPU_GET_OS(pGpu); + + pOS->osQueueWorkItemWithFlags(pGpu, + RmRemoveIdleHoldoff, + NULL, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); +} + +/*! + * @brief Timer callback to check if all idle conditions remain met and + * if so schedule a work item to indicate the GPU is idle. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackToIndicateIdle( + void *pCallbackData +) +{ + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJOS *pOS = GPU_GET_OS(pGpu); + + nv_acquire_mmap_lock(nv); + + if (nv_get_all_mappings_revoked_locked(nv) && + nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED && + RmCheckForGpuIdlenessUnderGpuLock(pGpu)) + { + pOS->osQueueWorkItem(pGpu, RmIndicateIdle, NULL); + } + else + { + if (nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED) + { + /* + * Something used the GPU between when we last sampled and now. + * Go back to the "instant" state to start waiting from scratch. + */ + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + } + + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + } + + nv_release_mmap_lock(nv); +} + +/*! + * @brief Timer callback to periodically check if all idle preconditions are + * met. If so, the dynamic power state is advanced from IDLE_INSTANT to + * IDLE_SUSTAINED, or (if already in the IDLE_SUSTAINED state) mappings are + * revoked and timerCallbackToIndicateIdle() is scheduled. + * + * @param[in] pCallbackData OBJGPU pointer (with void pointer type). + */ +static void timerCallbackForIdlePreConditions( + void *pCallbackData +) +{ + OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_FALSE; + + /* + * Note: It is not safe to take the dynamic power mutex here. + * Lock ordering dictates that the dynamic power mutex must be taken before + * the GPU lock, and this function is called with the GPU lock held. + * + * Therefore, this function is careful about *only* triggering specific + * transitions: + * NV_DYNAMIC_POWER_STATE_IDLE_INSTANT -> NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED + * NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED -> NV_DYNAMIC_POWER_STATE_IDLE_INSTANT + * + * Other codepaths are resilient to these state transitions occurring + * asynchronously. The state transition itself is done with an atomic + * compare and swap, so there should be no danger of inadvertently + * triggering a transition from a different state due to a + * read-modify-write or "time of check to time of use" (TOCTTOU) race + * condition. + */ + + if (nvp->dynamic_power.state != NV_DYNAMIC_POWER_STATE_IN_USE) + { + if (RmCheckForGpuIdlenessUnderGpuLock(pGpu)) + { + switch (nvp->dynamic_power.state) + { + case NV_DYNAMIC_POWER_STATE_UNKNOWN: + NV_ASSERT(0); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: + NV_PRINTF(LEVEL_ERROR, "NVRM: %s: unexpected dynamic power state 0x%x\n", + __FUNCTION__, nvp->dynamic_power.state); + /* fallthrough */ + case NV_DYNAMIC_POWER_STATE_IN_USE: + break; + case NV_DYNAMIC_POWER_STATE_IDLE_INSTANT: + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_INSTANT, + NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED); + break; + case NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED: + RmQueueIdleSustainedWorkitem(pGpu); + return; + } + + } + else + { + if (nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED) + { + /* + * Something used the GPU between when we last sampled and now. + * Go back to the "instant" state to start waiting from scratch. + */ + nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, + NV_DYNAMIC_POWER_STATE_IDLE_INSTANT); + } + } + } + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); +} + +/*! + * @brief Cancel any in-flight callback to remove idle holdoff. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmCancelCallbackToRemoveIdleHoldoff( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS cancelParams; + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } +} + +/*! + * @brief Cancel any in-flight timer callbacks. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmCancelDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS cancelParams; + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + // Cancel precondition check callback. + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + // Cancel callback to indicate idle + portMemSet(&cancelParams, 0, sizeof(cancelParams)); + + cancelParams.pEvent = nvp->dynamic_power.indicate_idle_event; + + tmrCtrlCmdEventCancel(pGpu, &cancelParams); + } + + RmCancelCallbackToRemoveIdleHoldoff(pGpu); + + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_FALSE; +} + +/*! + * @brief Free timer events allocated by CreateDynamicPowerCallbacks() + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmDestroyDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_GENERAL_PARAMS destroyParams; + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + // Destroy precondition check callback. + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + } + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + // Destroy callback to indicate idle + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.indicate_idle_event; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + } + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + // Destroy callback to decrease kernel refcount + portMemSet(&destroyParams, 0, sizeof(destroyParams)); + + destroyParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + + tmrCtrlCmdEventDestroy(pGpu, &destroyParams); + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + } + + nvp->dynamic_power.deferred_idle_enabled = NV_FALSE; +} + +/* + * @brief Adds a GPU to OBJOS::dynamicPowerSupportGpuMask + * + * @param[in] instance + */ +void osAddGpuDynPwrSupported +( + NvU32 instance +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJOS *pOS = SYS_GET_OS(pSys); + + pOS->dynamicPowerSupportGpuMask |= (1 << instance); +} + +/* + * @brief Removes a GPU from OBJOS::dynamicPowerSupportGpuMask + * + * @param[in] instance + */ +void osRemoveGpuDynPwrSupported +( + NvU32 instance +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJOS *pOS = SYS_GET_OS(pSys); + + pOS->dynamicPowerSupportGpuMask &= ~(1 << instance); +} + +/* + * @brief queries OBJOS::dynamicPowerSupportGpuMask + * + * @param[in] void + */ +NvU32 osGetDynamicPowerSupportMask +( + void +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJOS *pOS = SYS_GET_OS(pSys); + + return pOS->dynamicPowerSupportGpuMask; +} + +/*! + * @brief Cancel any outstanding callbacks, and free RM resources allocated by + * RmInitDeferredDynamicPowerManagement(). + * + * @param[in] nv nv_state_t pointer. + */ +void RmDestroyDeferredDynamicPowerManagement( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + // + // Re-instate the dynamic power mode to fine if it was + // disabled due to lack of platform support + // + if (nvp->dynamic_power.b_fine_not_supported == NV_TRUE) + { + nvp->dynamic_power.mode = NV_DYNAMIC_PM_FINE; + nvp->dynamic_power.b_fine_not_supported = NV_FALSE; + } + + // + // Before cancelling and destroying the callbacks, make sure to + // remove the idle holfoff that was applied during gc6 exit. + // + if (nvp->dynamic_power.b_idle_holdoff == NV_TRUE) + { + nv_indicate_idle(nv); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + + RmCancelDynamicPowerCallbacks(pGpu); + RmDestroyDynamicPowerCallbacks(pGpu); + osRemoveGpuDynPwrSupported(gpuGetInstance(pGpu)); +} + +/*! + * @brief Allocate timer events to call the functions: + * timerCallbackForIdlePreConditions() + * timerCallbackToIndicateIdle() + * + * The callbacks must be scheduled separately. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NV_STATUS CreateDynamicPowerCallbacks( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SET_PARAMS createEventParams; + NV_STATUS status; + + // Creating PreCondition check callback. + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.idle_precondition_check_event); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackForIdlePreConditions); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Error creating dynamic power precondition check callback\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + // Create callback to indicate idle.. + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.indicate_idle_event); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackToIndicateIdle); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Error creating callback to indicate GPU idle\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + // Create callback to remove idle holdoff + portMemSet(&createEventParams, 0, sizeof(createEventParams)); + + createEventParams.ppEvent = &(nvp->dynamic_power.remove_idle_holdoff); + createEventParams.pTimeProc = NV_PTR_TO_NvP64(timerCallbackToRemoveIdleHoldoff); + createEventParams.pCallbackData = NV_PTR_TO_NvP64(pGpu); + createEventParams.flags = TMR_FLAG_USE_OS_TIMER; + + status = tmrCtrlCmdEventCreate(pGpu, &createEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Error creating callback to decrease kernel refcount\n"); + nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; + nvp->dynamic_power.indicate_idle_event = NvP64_NULL; + nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; + return status; + } + + return NV_OK; +} + +/*! + * @brief Schedule the timerCallbackForIdlePreConditions() function to be called. + * + * If it is already scheduled, the function is a noop. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (nvp->dynamic_power.idle_precondition_check_callback_scheduled) + { + return; + } + + if (NvP64_VALUE(nvp->dynamic_power.idle_precondition_check_event) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.idle_precondition_check_event; + scheduleEventParams.timeNs = GC6_PRECONDITION_CHECK_TIME; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status == NV_OK) + { + nvp->dynamic_power.idle_precondition_check_callback_scheduled = NV_TRUE; + } + else + { + NV_PRINTF(LEVEL_ERROR, "NVRM: Error scheduling precondition callback\n"); + } + } +} + +/*! + * @brief Schedule the timerCallbackForIdlePreConditions() function to be called. + * + * If it is already scheduled, the function is a noop. + * + * This function takes the GPU lock. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackForIdlePreConditions( + OBJGPU *pGpu +) +{ + NV_STATUS status; + GPU_MASK gpuMask; + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER, + &gpuMask); + if (status == NV_OK) + { + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } +} + +/*! + * @brief Schedule the timerCallbackToIndicateIdle() function to be called. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackToIndicateIdle( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; + + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (NvP64_VALUE(nvp->dynamic_power.indicate_idle_event) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.indicate_idle_event; + scheduleEventParams.timeNs = GC6_BAR1_BLOCKER_CHECK_AND_METHOD_FLUSH_TIME; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "NVRM: Error scheduling indicate idle callback\n"); + } +} + +/*! + * @brief Schedule the timerCallbackToRemoveIdleHoldoff() function. + * + * The GPU lock must be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + */ +static void RmScheduleCallbackToRemoveIdleHoldoff( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + TMR_EVENT_SCHEDULE_PARAMS scheduleEventParams; + NV_STATUS status; -#include -#include -#include "kernel/gpu/intr/intr.h" + NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (NvP64_VALUE(nvp->dynamic_power.remove_idle_holdoff) != NULL) + { + portMemSet(&scheduleEventParams, 0, sizeof(scheduleEventParams)); + + scheduleEventParams.pEvent = nvp->dynamic_power.remove_idle_holdoff; + scheduleEventParams.timeNs = GC6_CYCLE_IDLE_HOLDOFF_CHECK_TIME; + scheduleEventParams.bUseTimeAbs = NV_FALSE; + + status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Error scheduling kernel refcount decrement callback\n"); + } + else + { + nvp->dynamic_power.b_idle_holdoff = NV_TRUE; + } + } +} + +/*! + * @brief Check if the system supports RTD3-GC6. + * + * @param[in] pGpu OBJGPU pointer. + */ +static NvBool RmCheckRtd3Gc6Support( + nv_state_t *pNv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS status; + NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS virtModeParams = { 0 }; + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED)) + { + NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported for this arch\n"); + return NV_FALSE; + } + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED)) + { + NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported in Vbios\n"); + return NV_FALSE; + } + + if (!nvp->b_mobile_config_enabled) + { + NV_PRINTF(LEVEL_NOTICE, "NVRM: Disabling RTD3/GC6, as it is only supported on Notebook SKU\n"); + return NV_FALSE; + } + + status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDevice, + NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE, + &virtModeParams, sizeof(virtModeParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM: Failed to get Virtualization mode, status=0x%x\n", + status); + return NV_FALSE; + } + + if ((virtModeParams.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE) && + (virtModeParams.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS)) + { + NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported on VM\n"); + return NV_FALSE; + } + + return NV_TRUE; +} + +/*! + * @brief Allocate resources needed to track deferred power management, and + * schedule the initial periodic callbacks. + * + * @param[in] nv nv_state_t pointer. + */ +void RmInitDeferredDynamicPowerManagement( + nv_state_t *nv +) +{ + NV_STATUS status; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + // LOCK: acquire GPUs lock + if ((status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (!RmCheckRtd3Gc6Support(nv)) + { + nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; + nvp->dynamic_power.b_fine_not_supported = NV_TRUE; + NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported\n"); + goto unlock; + } + osAddGpuDynPwrSupported(gpuGetInstance(pGpu)); + nvp->dynamic_power.b_fine_not_supported = NV_FALSE; + status = CreateDynamicPowerCallbacks(pGpu); + + if (status == NV_OK) + { + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + + nvp->dynamic_power.deferred_idle_enabled = NV_TRUE; + // RM's default is GCOFF allow + nvp->dynamic_power.clients_gcoff_disallow_refcount = 0; + } + } +unlock: + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "NVRM: Failed to register for dynamic power callbacks\n"); +} + +/*! + * @brief Check if GCOFF state can be used for Power Management. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] usedFbSize Used FB Allocation size. + * @param[in] bIsDynamicPM If true, check for dynamic PM; otherwise, check + * for system PM (suspend/resume). + * + * returns NV_TRUE if GCOFF state can be used, otherwise NV_FALSE. + * + */ +static NvBool RmCheckForGcOffPM( + OBJGPU *pGpu, + NvU64 usedFbSize, + NvBool bIsDynamicPM +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU64 gcoff_max_fb_size; + + if (bIsDynamicPM) + { + /* + * GCOFF won't be enaged for Dynamic PM if X server does not allow. + * The dynamic_power.clients_gcoff_disallow_refcount is being accessed + * without acquiring dynamic power mutex since this value can be + * modified only when GPU is in active state. The os_ref_dynamic_power() + * function will be called to hold a reference to the GPU whenever + * RM is processing osClientGcoffDisallowRefcount() calls. This either + * prevents the GPU from going into a low power state or will wait for + * it to be resumed before proceeding. + */ + if (nvp->dynamic_power.clients_gcoff_disallow_refcount != 0) + return NV_FALSE; + + gcoff_max_fb_size = nvp->dynamic_power.gcoff_max_fb_size; + } + else + { + gcoff_max_fb_size = nvp->s0ix_gcoff_max_fb_size; + } + + /* + * GCOFF will be engaged whenever the following necessary preconditions + * are met: + * + * 1. The GCOFF has not been disabled with regkey by setting it to zero. + * 2. Used FB allocation size are within limits. + */ + return (gcoff_max_fb_size > 0) && + (usedFbSize <= gcoff_max_fb_size); +} // // Function to update fixed fbsr modes to support multiple vairants such as @@ -158,6 +2203,170 @@ RmPowerManagement( return rmStatus; } +/*! + * @brief Call core RM to perform the GCx (GC6/GCOF) entry sequence (before + * powering off the GPU) or exit sequence (after powering the GPU back on). + * + * The GPU lock should be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * @param[in] bIsDynamicPM If true, it is for dynamic PM; otherwise, it is + * for system PM (suspend/resume). + * + * @return NV_STATUS code indicating if the operation was successful. + */ +NV_STATUS RmGcxPowerManagement( + OBJGPU *pGpu, + NvBool bEnter, + NvBool bIsDynamicPM +) +{ + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NV_STATUS status = NV_OK; + + if (pGpu->acpiMethodData.jtMethodData.bSBIOSCaps && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE)) + { + // + // AML override is expected only on NB platforms to support GCOFF-1.0( + // which is legacy GCOFF) and GC6-3.0 + // GC6 3.0 is possible without AML override but due to changes required + // for GCOFF-1.0 in SBIOS & HW, AML override is needed for GC6-3.0 also. + // + NV_PRINTF(LEVEL_INFO,"NVRM: AML overrides present in Desktop"); + } + + nv->d0_state_in_suspend = NV_FALSE; + + if (bEnter) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 usedFbSize; + NvBool bCanUseGc6; + + // + // Check if GC6 can be used for current power management request. + // For dynamic PM, it can be used always. + // For system PM, it can be used only if current system suspend + // happened with s2idle. + // + bCanUseGc6 = bIsDynamicPM ? NV_TRUE : nv_s2idle_pm_configured(); + + // + // If GC6 cannot be used, then no need to compare the used FB size with + // threshold value and select GCOFF irrespective of FB size. + // + if ((memmgrGetUsedRamSize(pGpu, pMemoryManager, &usedFbSize) == NV_OK) && + (!bCanUseGc6 || RmCheckForGcOffPM(pGpu, usedFbSize, bIsDynamicPM)) && + (fbsrReserveSysMemoryForPowerMgmt(pGpu, pMemoryManager->pFbsr[FBSR_TYPE_DMA], + usedFbSize) == NV_OK)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING, NV_TRUE); + + // + // Set 'bPreserveComptagBackingStoreOnSuspendDef' so that comptag + // related handling can be done during state unload/load. + // + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_TRUE; + status = RmPowerManagement(pGpu, NV_PM_ACTION_STANDBY); + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING, NV_FALSE); + + if (status == NV_OK) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED, NV_TRUE); + } + else + { + /* + * Normally the NV_PM_ACTION_RESUME resume should free the + * the reserved memory while doing FB state load. But if the + * failure has happened at very early stage in FB state unload + * while doing NV_PM_ACTION_STANDBY, then reserved system memory + * might not be freed. + */ + fbsrFreeReservedSysMemoryForPowerMgmt(pMemoryManager->pFbsr[FBSR_TYPE_DMA]); + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_FALSE; + } + } + else if (bCanUseGc6) + { + NV2080_CTRL_GC6_ENTRY_PARAMS entryParams; + portMemSet(&entryParams, 0, sizeof(entryParams)); + + entryParams.flavorId = NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID; + entryParams.stepMask = NVBIT(NV2080_CTRL_GC6_STEP_ID_GPU_OFF); + entryParams.params.bIsRTD3Transition = NV_TRUE; + + // + // Currently if the GPU is not in the Lowest P-State, then the + // GC6 entry will fail in its internal sanity check. The system + // suspend can be triggered in any P-State, so sanity check + // for the lowest P-State needs to be skipped. In this case, during + // Perf state unload time, the forceful P-State switch will + // happen which will bring the GPU into lowest P-State. + // + entryParams.params.bSkipPstateSanity = !bIsDynamicPM; + + status = gpuGc6Entry(pGpu, &entryParams); + + // + // The GC6 state requires SW involvement before each transition + // from D0 to D3cold. In case of system suspend with pass-through + // mode, the VM suspend should happen before host suspend. During + // VM suspend, the NVIDIA driver running in the VM side will be + // involved in D3cold transition, but in the host side, it will + // go through D3cold->D0->D3cold transition and will make the + // second D3cold transition without NVIDIA driver. To handle this + // use-case, during VM suspend, use the D0 state and the host linux + // kernel will put the device into D3cold state. + // + if ((status == NV_OK) && ((nv->flags & NV_FLAG_PASSTHRU) != 0)) + { + nv->d0_state_in_suspend = NV_TRUE; + } + } + // + // This condition will hit only for systems which support s2idle but + // are currently configured for deep sleep based system power + // management, and that too when sufficient system memory + // is not available. For this case, the suspend request will fail + // and the system will remain in S0. + // + else + { + status = NV_ERR_NOT_SUPPORTED; + NV_PRINTF(LEVEL_ERROR, + "NVRM: %s: System suspend failed with current system suspend configuration. " + "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n", + __FUNCTION__); + } + } + else + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED)) + { + status = RmPowerManagement(pGpu, NV_PM_ACTION_RESUME); + pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED, NV_FALSE); + pKernelMemorySystem->bPreserveComptagBackingStoreOnSuspend = NV_FALSE; + } + else + { + NV2080_CTRL_GC6_EXIT_PARAMS exitParams; + portMemSet(&exitParams, 0, sizeof(exitParams)); + + exitParams.flavorId = NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID; + exitParams.params.bIsRTD3Transition = NV_TRUE; + + status = gpuGc6Exit(pGpu, &exitParams); + } + } + + return status; +} + NV_STATUS NV_API_CALL rm_power_management( nvidia_stack_t *sp, nv_state_t *pNv, @@ -185,6 +2394,36 @@ NV_STATUS NV_API_CALL rm_power_management( // LOCK: acquire GPUs lock if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) { + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + + // + // Before going to S3 or S4, remove idle holdoff which was + // applied during gc6 exit. + // + if ((pmAction != NV_PM_ACTION_RESUME) && + (nvp->dynamic_power.b_idle_holdoff == NV_TRUE)) + { + nv_indicate_idle(pNv); + RmCancelCallbackToRemoveIdleHoldoff(pGpu); + nvp->dynamic_power.b_idle_holdoff = NV_FALSE; + } + + // + // Use GCx (GCOFF/GC6) power management if S0ix-based PM is + // enabled and the request is for system suspend/resume. + // Otherwise, use the existing mechanism. + // + if (nvp->s0ix_pm_enabled && + (pmAction == NV_PM_ACTION_STANDBY || + (pmAction == NV_PM_ACTION_RESUME && + !nvp->pm_state.InHibernate))) + { + rmStatus = RmGcxPowerManagement(pGpu, + pmAction == NV_PM_ACTION_STANDBY, + NV_FALSE); + + } + else { rmStatus = RmPowerManagement(pGpu, pmAction); } @@ -207,4 +2446,296 @@ NV_STATUS NV_API_CALL rm_power_management( return rmStatus; } +/*! + * @brief Wrapper around RmGcxPowerManagement() and removes the Idle holdoff + * during exit sequence. + * + * The GPU lock should be held when calling this function. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * + * @return NV_STATUS code indicating if the operation was successful. + */ +static NV_STATUS RmTransitionDynamicPower( + OBJGPU *pGpu, + NvBool bEnter +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NV_STATUS status; + + status = RmGcxPowerManagement(pGpu, bEnter, NV_TRUE); + + if (!bEnter && status == NV_OK) + { + nv_idle_holdoff(nv); + RmScheduleCallbackToRemoveIdleHoldoff(pGpu); + } + + return status; +} + +/*! + * @brief Wrapper around RmTransitionDynamicPower() which sets up the RM + * runtime (thread state and altstack), and takes the GPU lock for the duration + * of the operation. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + * @param[in] bEnter If true, perform entry sequence; exit sequence + * otherwise. + * + * @return NV_STATUS code indicating if the operation was successful. + */ +NV_STATUS NV_API_CALL rm_transition_dynamic_power( + nvidia_stack_t *sp, + nv_state_t *nv, + NvBool bEnter +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + NV_STATUS status = NV_OK; + THREAD_STATE_NODE threadState; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire GPUs lock + status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER); + if (status == NV_OK) + { + status = RmTransitionDynamicPower(pGpu, bEnter); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +/*! + * @brief: Notify client about hot-plugged/unplugged displays. + * Called after GPU exits GC6 because of display hot-plug/unplug. + * + * @param[in] nv nv_state_t pointer. + */ +static void RmNotifyClientAboutHotplug( + nv_state_t *nv +) +{ + NV_STATUS status; + GPU_MASK gpuMask; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + Nv2080HotplugNotification hotplugNotificationParams; + + portMemSet(&hotplugNotificationParams, 0, sizeof(hotplugNotificationParams)); + + // LOCK: acquire per device lock + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HOTPLUG, + &gpuMask); + if (status == NV_OK) + { + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_HOTPLUG, + &hotplugNotificationParams, + sizeof(hotplugNotificationParams), 0, 0); + // UNLOCK: release per device lock + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + } +} + +/*! + * @brief If GPU is in GC6, exit GC6 state and + * notify client about display hot-plug/unplug. + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] nv nv_state_t pointer. + */ +void RmHandleDisplayChange( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (pGpu && + (IS_GPU_GC6_STATE_ENTERED(pGpu) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERED))) + { + if (rm_ref_dynamic_power(sp, nv, NV_DYNAMIC_PM_FINE) == NV_OK) + { + RmNotifyClientAboutHotplug(nv); + rm_unref_dynamic_power(sp, nv, NV_DYNAMIC_PM_FINE); + } + else + NV_PRINTF(LEVEL_ERROR, + "NVRM: %s: Failed to increment dynamic power refcount\n", + __FUNCTION__); + } +} + +/*! + * @brief: Function to query Dynamic Power Management + * + * @param[in] sp nvidia_stack_t pointer. + * @param[in] pNv nv_state_t pointer. + * + * @return String indicating Dynamic Power Management status. + */ +const char* NV_API_CALL rm_get_dynamic_power_management_status( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + void *fp; + nv_priv_t *nvp = NV_GET_NV_PRIV(pNv); + const char *returnString = "?"; + + NV_ENTER_RM_RUNTIME(sp,fp); + + // LOCK: acquire API lock + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + // Check if RM is inited + if (pGpu != NULL) + { + /* + * If the platform/driver does not support Dynamic Power Management, + * we set mode as NV_DYNAMIC_PM_NEVER. Hence, after RmInit if the + * mode is still NV_DYNAMIC_PM_FINE, we are sure that it is + * supported and enabled. Also see NOTE. + */ + if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_FINE) + { + returnString = "Enabled (fine-grained)"; + } + else if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_COARSE) + { + returnString = "Enabled (coarse-grained)"; + } + else if (nvp->dynamic_power.mode == NV_DYNAMIC_PM_NEVER) + { + + if (nvp->dynamic_power.dynamic_power_regkey == + NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER) + returnString = "Disabled"; + else if (nvp->dynamic_power.dynamic_power_regkey == + NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT) + returnString = "Disabled by default"; + else + returnString = "Not supported"; + } + } + //UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return returnString; +} + +static void RmHandleIdleSustained( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + + nv_revoke_gpu_mappings(NV_GET_NV_STATE(pGpu)); + RmScheduleCallbackToIndicateIdle(pGpu); + nvp->dynamic_power.b_idle_sustained_workitem_queued = NV_FALSE; +} + +/* + * Queue a workitem for revoking GPU mappings, and scheduling a callback to indicate idle. + */ +static void RmQueueIdleSustainedWorkitem( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + OBJOS *pOS = GPU_GET_OS(pGpu); + NV_STATUS status = NV_OK; + + if (!nvp->dynamic_power.b_idle_sustained_workitem_queued) + { + status = pOS->osQueueWorkItemWithFlags(pGpu, + RmHandleIdleSustained, + NULL, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "NVRM: %s: Failed to queue RmHandleIdleSustained() workitem.\n", + __FUNCTION__); + RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); + return; + } + nvp->dynamic_power.b_idle_sustained_workitem_queued = NV_TRUE; + } +} + +/* + * Allocate resources needed for S0ix-based system power management. + */ +void +RmInitS0ixPowerManagement( + nv_state_t *nv +) +{ + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 data; + NvBool bRtd3Gc6Support = NV_FALSE; + + // LOCK: acquire GPUs lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + bRtd3Gc6Support = RmCheckRtd3Gc6Support(nv); + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + + /* + * The GPU S0ix-based system power management will be enabled + * only if all the following necessary requirements are met: + * + * 1. The GPU has RTD3 support. + * 2. The platform has support for s0ix. + * 3. Feature regkey EnableS0ixPowerManagement is enabled. + */ + if (bRtd3Gc6Support && + nv_platform_supports_s0ix() && + (osReadRegistryDword(NULL, NV_REG_ENABLE_S0IX_POWER_MANAGEMENT, + &data) == NV_OK) && (data == 1)) + { + nvp->s0ix_pm_enabled = NV_TRUE; + /* + * Read the OS registry for Maximum FB size for S0ix-based PM + * which will be expressed in Megabytes (1048576 bytes) and + * convert it into bytes. + */ + if ((osReadRegistryDword(NULL, + NV_REG_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, + &data) == NV_OK)) + { + nvp->s0ix_gcoff_max_fb_size = (NvU64)data * 1024 * 1024; + } + } +} diff --git a/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c b/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c index 2ccc9c5237..b9d3781050 100644 --- a/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c +++ b/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c @@ -22,205 +22,9 @@ */ #include +#include "os/os.h" #include #include #include #include -NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup( - nvidia_stack_t *sp, - nv_state_t *nv -) -{ - return NV_OK; -} - -void NV_API_CALL rm_init_dynamic_power_management( - nvidia_stack_t *sp, - nv_state_t *nv, - NvBool bPr3AcpiMethodPresent -) -{ -} - -void NV_API_CALL rm_cleanup_dynamic_power_management( - nvidia_stack_t *sp, - nv_state_t *nv -) -{ -} - -void NV_API_CALL rm_enable_dynamic_power_management( - nvidia_stack_t *sp, - nv_state_t *nv -) -{ -} - -NV_STATUS NV_API_CALL rm_ref_dynamic_power( - nvidia_stack_t *sp, - nv_state_t *nv, - nv_dynamic_power_mode_t mode -) -{ - return NV_OK; -} - -void NV_API_CALL rm_unref_dynamic_power( - nvidia_stack_t *sp, - nv_state_t *nv, - nv_dynamic_power_mode_t mode -) -{ -} - -NV_STATUS NV_API_CALL rm_transition_dynamic_power( - nvidia_stack_t *sp, - nv_state_t *nv, - NvBool bEnter -) -{ - return NV_OK; -} - -const char* NV_API_CALL rm_get_vidmem_power_status( - nvidia_stack_t *sp, - nv_state_t *pNv -) -{ - return "?"; -} - -const char* NV_API_CALL rm_get_dynamic_power_management_status( - nvidia_stack_t *sp, - nv_state_t *pNv -) -{ - return "?"; -} - -const char* NV_API_CALL rm_get_gpu_gcx_support( - nvidia_stack_t *sp, - nv_state_t *pNv, - NvBool bGcxTypeGC6 -) -{ - return "?"; -} - -NV_STATUS -subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams -) -{ - return NV_OK; -} - -NV_STATUS -subdeviceCtrlCmdOsUnixAllowDisallowGcoff_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *pParams -) -{ - return NV_OK; -} - -NV_STATUS -subdeviceCtrlCmdOsUnixAudioDynamicPower_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *pParams -) -{ - return NV_OK; -} - -void -RmUpdateGc6ConsoleRefCount -( - nv_state_t *nv, - NvBool bIncrease -) -{ -} - -void -RmInitS0ixPowerManagement -( - nv_state_t *nv -) -{ -} - -void -RmInitDeferredDynamicPowerManagement -( - nv_state_t *nv -) -{ -} - -void -RmDestroyDeferredDynamicPowerManagement -( - nv_state_t *nv -) -{ -} - -void RmHandleDisplayChange -( - nvidia_stack_t *sp, - nv_state_t *nv -) -{ -} - -NV_STATUS -os_ref_dynamic_power -( - nv_state_t *nv, - nv_dynamic_power_mode_t mode -) -{ - return NV_OK; -} - -void -os_unref_dynamic_power -( - nv_state_t *nv, - nv_dynamic_power_mode_t mode -) -{ -} - -NV_STATUS -deviceCtrlCmdOsUnixVTSwitch_IMPL -( - Device *pDevice, - NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *pParams -) -{ - return NV_OK; -} - -NV_STATUS NV_API_CALL rm_save_low_res_mode( - nvidia_stack_t *sp, - nv_state_t *pNv -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS RmInitX86EmuState(OBJGPU *pGpu) -{ - return NV_OK; -} - -void RmFreeX86EmuState(OBJGPU *pGpu) -{ -} diff --git a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c index 0ad10b8986..1d0a128699 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c +++ b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -62,6 +62,16 @@ NvBool hypervisorIsVgxHyper_IMPL(void) return os_is_vgx_hyper(); } +NvBool hypervisorIsAC_IMPL(void) +{ + return NV_FALSE; +} + +void hypervisorSetACSupported_IMPL(POBJHYPERVISOR pHypervisor) +{ + pHypervisor->bIsACSupported = NV_TRUE; +} + NV_STATUS hypervisorInjectInterrupt_IMPL ( POBJHYPERVISOR pHypervisor, @@ -225,7 +235,6 @@ NV_STATUS NV_API_CALL nv_vgpu_get_type_info( { THREAD_STATE_NODE threadState; OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJGPU *pGpu = NULL; KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); NV_STATUS rmStatus = NV_OK; VGPU_TYPE *vgpuTypeInfo; @@ -238,14 +247,6 @@ NV_STATUS NV_API_CALL nv_vgpu_get_type_info( // LOCK: acquire API lock if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) { - pGpu = NV_GET_NV_PRIV_PGPU(pNv); - if (pGpu == NULL) - { - NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); - rmStatus = NV_ERR_INVALID_STATE; - goto exit; - } - if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex)) == NV_OK) { @@ -447,14 +448,11 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request( const NvU8 *pMdevUuid, NvU32 vgpuTypeId, NvU16 *vgpuId, - NvU32 gpuPciBdf, - NvBool *is_driver_vm + NvU32 gpuPciBdf ) { THREAD_STATE_NODE threadState; - OBJSYS *pSys = SYS_GET_INSTANCE(); void *fp = NULL; - OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); NV_STATUS rmStatus = NV_OK; NV_ENTER_RM_RUNTIME(sp,fp); @@ -466,8 +464,6 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request( rmStatus = kvgpumgrCreateRequestVgpu(pNv->gpu_id, pMdevUuid, vgpuTypeId, vgpuId, gpuPciBdf); - *is_driver_vm = pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED); - // UNLOCK: release API lock rmapiLockRelease(); } @@ -725,7 +721,8 @@ NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( { if (pKernelHostVgpuDevice->gfid != 0) { - rmStatus = kbifGetNumVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas); + rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, + numAreas, NULL, NULL); if (rmStatus == NV_OK) { os_alloc_mem((void **)&vfRegionOffsets, sizeof(NvU64) * (*numAreas)); @@ -733,7 +730,7 @@ NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( if (vfRegionOffsets && vfRegionSizes) { rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, - vfRegionOffsets, vfRegionSizes); + numAreas, vfRegionOffsets, vfRegionSizes); if (rmStatus == NV_OK) { *offsets = vfRegionOffsets; @@ -917,7 +914,7 @@ NV_STATUS osVgpuRegisterMdev ) { NV_STATUS status = NV_OK; - vgpu_vfio_info vgpu_info; + vgpu_vfio_info vgpu_info = {0}; OBJSYS *pSys = SYS_GET_INSTANCE(); KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; @@ -935,12 +932,22 @@ NV_STATUS osVgpuRegisterMdev status = os_alloc_mem((void **)&vgpu_info.vgpuTypeIds, ((vgpu_info.numVgpuTypes) * sizeof(NvU32))); if (status != NV_OK) - return status; + goto free_mem; + + status = os_alloc_mem((void **)&vgpu_info.vgpuNames, + ((vgpu_info.numVgpuTypes) * sizeof(char *))); + if (status != NV_OK) + goto free_mem; vgpu_info.nv = pOsGpuInfo; for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++) { + status = os_alloc_mem((void *)&vgpu_info.vgpuNames[i], (VGPU_STRING_BUFFER_SIZE * sizeof(char))); + if (status != NV_OK) + goto free_mem; + vgpu_info.vgpuTypeIds[i] = pPhysGpuInfo->vgpuTypes[i]->vgpuTypeId; + os_snprintf((char *) vgpu_info.vgpuNames[i], VGPU_STRING_BUFFER_SIZE, "%s\n", pPhysGpuInfo->vgpuTypes[i]->vgpuName); } if ((!pPhysGpuInfo->sriovEnabled) || @@ -970,7 +977,22 @@ NV_STATUS osVgpuRegisterMdev } } - os_free_mem(vgpu_info.vgpuTypeIds); +free_mem: + if (vgpu_info.vgpuTypeIds) + os_free_mem(vgpu_info.vgpuTypeIds); + + if (vgpu_info.vgpuNames) + { + for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++) + { + if (vgpu_info.vgpuNames[i]) + { + os_free_mem(vgpu_info.vgpuNames[i]); + } + } + os_free_mem(vgpu_info.vgpuNames); + } + return status; } @@ -981,15 +1003,20 @@ NV_STATUS osIsVgpuVfioPresent(void) return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_PRESENT); } +NV_STATUS osIsVfioPciCorePresent(void) +{ + vgpu_vfio_info vgpu_info; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VFIO_PCI_CORE_PRESENT); +} + + void initVGXSpecificRegistry(OBJGPU *pGpu) { NvU32 data32; osWriteRegistryDword(pGpu, NV_REG_STR_RM_POWER_FEATURES, 0x55455555); osWriteRegistryDword(pGpu, NV_REG_STR_RM_INFOROM_DISABLE_BBX, NV_REG_STR_RM_INFOROM_DISABLE_BBX_YES); -#if !defined(NVCPU_X86_64) - osWriteRegistryDword(pGpu, NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB, 4); -#endif osWriteRegistryDword(pGpu, NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR, NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE); if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_DUMP_NVLOG, &data32) != NV_OK)) diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c index 2623476e07..6bd4f8c90e 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os.c +++ b/src/nvidia/arch/nvalloc/unix/src/os.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -931,6 +931,20 @@ NV_STATUS osAllocPagesInternal( if (nv && (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_32BIT_ADDRESSABLE))) nv->force_dma32_alloc = NV_TRUE; + // + // If AMD SEV is enabled but APM(Ampere protected) or CC(Confidential + // Compute) mode is not enabled on the GPU, all RM and client + // allocations must be an unprotected sysmem. If APM is enabled and RM + // is allocating sysmem for its internal use, then it has to be + // unprotected as protected sysmem is not accessible to GPU. + // + unencrypted = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY); + + if (pMemDesc->_addressSpace == ADDR_EGM) + { + nodeId = GPU_GET_MEMORY_MANAGER(pGpu)->localEgmNodeId; + } + if (NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount) > NV_U32_MAX) { status = NV_ERR_INVALID_LIMIT; @@ -1220,14 +1234,6 @@ void osUnmapGPU( } } -NV_STATUS osDeviceClassToDeviceName( - NvU32 deviceInstance, - NvU8 *szName -) -{ - return NV_ERR_GENERIC; -} - static void postEvent( nv_event_t *event, NvU32 hEvent, @@ -1818,12 +1824,25 @@ void osGetTimeoutParams(OBJGPU *pGpu, NvU32 *pTimeoutUs, NvU32 *pScale, NvU32 *p if (hypervisorIsVgxHyper()) { - // - // 1.8 seconds is chosen because it is 90% of the overall hard limit of 2.0 - // seconds, imposed by WDDM driver rules. - // Currently primary use case of VGX is Windows, so setting 1.8 as default - // - *pTimeoutUs = 1.8 * 1000000; + if (IS_GSP_CLIENT(pGpu) && pGpu->getProperty(pGpu, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX) && + !pGpu->gspRmInitialized) + { + // + // For Hopper, 1.8 seconds is not enough to boot GSP-RM. + // To avoid this issue, 4 seconds timeout is set on initialization, + // and then it's going to be changed 1.8 seconds after GSP initialization. + // + *pTimeoutUs = 4 * 1000000; + } + else + { + // + // 1.8 seconds is chosen because it is 90% of the overall hard limit of 2.0 + // seconds, imposed by WDDM driver rules. + // Currently primary use case of VGX is Windows, so setting 1.8 as default + // + *pTimeoutUs = 1.8 * 1000000; + } } else { @@ -2527,6 +2546,26 @@ NV_STATUS osCallACPI_DSM pAcpiDsmGuid = (NvU8 *) &PCFG_DSM_GUID; acpiDsmRev = PCFG_REVISION_ID; break; + case ACPI_DSM_FUNCTION_GPS_2X: + pAcpiDsmGuid = (NvU8 *) &GPS_DSM_GUID; + acpiDsmRev = GPS_2X_REVISION_ID; + acpiDsmInArgSize = (*pSize); + break; + case ACPI_DSM_FUNCTION_GPS: + if ((IsTU10X(pGpu)) || + ((gpuIsACPIPatchRequiredForBug2473619_HAL(pGpu)) && + ((acpiDsmSubFunction == GPS_FUNC_SUPPORT) || + (acpiDsmSubFunction == GPS_FUNC_GETCALLBACKS)))) + { + pAcpiDsmGuid = (NvU8 *) &GPS_DSM_GUID; + acpiDsmRev = GPS_REVISION_ID; + acpiDsmInArgSize = (*pSize); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + break; case ACPI_DSM_FUNCTION_PEX: pAcpiDsmGuid = (NvU8 *) &PEX_DSM_GUID; acpiDsmRev = PEX_REVISION_ID; @@ -3038,7 +3077,32 @@ osGC6PowerControl NvU32 *pOut ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS status; + NvU32 inOut = cmd; + NvU16 rtnSize = sizeof(inOut); + + if (FLD_TEST_DRF(_JT_FUNC, _POWERCONTROL, _GPU_POWER_CONTROL, _GSS, inOut)) + { + if (!pOut) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + + status = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_POWERCONTROL, + &inOut, + &rtnSize); + + if ((status != NV_OK) || !pOut) + { + return status; + } + + *pOut = inOut; + + return NV_OK; } NvBool osTestPcieExtendedConfigAccess(void *handle, NvU32 offset) @@ -3593,8 +3657,8 @@ osValidateClientTokens PTOKEN_USER pClientTokenUser = (PTOKEN_USER)pClientSecurityToken; PTOKEN_USER pCurrentTokenUser = (PTOKEN_USER)pCurrentSecurityToken; - NV_ASSERT_OR_RETURN((pClientTokenUser != NULL), NV_ERR_INVALID_POINTER); - NV_ASSERT_OR_RETURN((pCurrentTokenUser != NULL), NV_ERR_INVALID_POINTER); + if (pClientTokenUser == NULL || pCurrentTokenUser == NULL) + return NV_ERR_INVALID_POINTER; if ((pClientTokenUser->euid != pCurrentTokenUser->euid) && (pClientTokenUser->pid != pCurrentTokenUser->pid)) @@ -3911,7 +3975,7 @@ osGetSmbiosTable void *pMappedAddr = NULL; NvU64 basePAddr = 0; - if (!NVCPU_IS_X86_64) + if (!NVCPU_IS_X86_64 && !NVCPU_IS_AARCH64) { return NV_ERR_NOT_SUPPORTED; } @@ -4192,7 +4256,7 @@ osWaitForIbmnpuRsync nv_wait_for_ibmnpu_rsync(pOsGpuInfo); } -NvU32 +NvU64 osGetPageSize(void) { return os_page_size; @@ -4784,6 +4848,8 @@ osRmCapInitDescriptor * @brief Generates random bytes which can be used as a universally unique * identifier. * + * This function may sleep (interruptible). + * * @param[out] pBytes Array of random bytes * @param[in] numBytes Size of the array */ @@ -4794,9 +4860,7 @@ osGetRandomBytes NvU16 numBytes ) { - os_get_random_bytes(pBytes, numBytes); - - return NV_OK; + return os_get_random_bytes(pBytes, numBytes); } /* @@ -4879,6 +4943,46 @@ osReadPFPciConfigInVF return NV_ERR_NOT_SUPPORTED; } +/*! + * @brief Sends an MRQ (message-request) to BPMP + * + * The request, response, and ret parameters of this function correspond to the + * components of the tegra_bpmp_message struct, which BPMP uses to receive + * MRQs. + * + * @param[in] pOsGpuInfo OS specific GPU information pointer + * @param[in] mrq MRQ_xxx ID specifying what is requested + * @param[in] pRequestData Pointer to request input data + * @param[in] requestDataSize Size of structure pointed to by pRequestData + * @param[out] pResponseData Pointer to response output data + * @param[in] responseDataSize Size of structure pointed to by pResponseData + * @param[out] ret MRQ return code (from "ret" element of + * tegra_bpmp_message struct) + * @param[out] apiRet Return code from tegra_bpmp_transfer call + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, + * NV_ERR_INVALID_POINTER if the tegra_bpmp struct pointer could not + * be obtained from nv, or + * NV_ERR_GENERIC if the tegra_bpmp_transfer call failed (see apiRet + * for Linux error code). + */ +NV_STATUS +osTegraSocBpmpSendMrq +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 mrq, + const void *pRequestData, + NvU32 requestDataSize, + void *pResponseData, + NvU32 responseDataSize, + NvS32 *pRet, + NvS32 *pApiRet +) +{ + return NV_ERR_NOT_SUPPORTED; +} + /*! * @brief Returns IMP-relevant data collected from other modules * @@ -4988,7 +5092,7 @@ osCreateNanoTimer * * @param[in] pOsGpuInfo OS specific GPU information pointer * @param[in] pTimer pointer to high resolution timer object - * @param[in] timens time in nano seconds + * @param[in] timeNs Relative time in nano seconds */ NV_STATUS osStartNanoTimer @@ -5251,9 +5355,89 @@ osReleaseGpuOsInfo nv_put_file_private(pOsInfo); } +/*! + * @brief Add GPU memory as a NUMA node. + * + * @param[in/out] pOsGpuInfo OS specific GPU information pointer + * @param[in] offset start offset of the partition within FB + * @param[in] size size of the partition + * @param[out] pNumaNodeId OS NUMA node id for the added memory. + * + * @returns NV_OK if all is okay. Otherwise an error-specific value. + * + */ +NV_STATUS +osNumaAddGpuMemory +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 offset, + NvU64 size, + NvU32 *pNumaNodeId +) +{ + nv_state_t *nv = pOsGpuInfo; + + return os_numa_add_gpu_memory(nv->handle, offset, size, pNumaNodeId); +} + +/*! + * @brief Remove a particular SMC partition's GPU memory from OS kernel. + * + * Remove GPU memory from the OS kernel that is earlier added as a NUMA node + * to the kernel in platforms where GPU is coherently connected to the CPU. + * + * @param[in/out] pOsGpuInfo OS_GPU_INFO OS specific GPU information pointer + * @param[in] offset start offset of the partition within FB + * @param[in] size size of the partition + * @param[in] numaNodeId OS NUMA node id of the memory to be removed. + * + */ +void +osNumaRemoveGpuMemory +( + OS_GPU_INFO *pOsGpuInfo, + NvU64 offset, + NvU64 size, + NvU32 numaNodeId +) +{ + nv_state_t *nv = pOsGpuInfo; + + NV_STATUS status = os_numa_remove_gpu_memory(nv->handle, offset, size, numaNodeId); + NV_ASSERT(status == NV_OK); + + return; +} + NvBool osDmabufIsSupported(void) { return os_dma_buf_enabled; } +NV_STATUS +osGetEgmInfo +( + OBJGPU *pGpu, + NvU64 *pPhysAddr, + NvU64 *pSize, + NvS32 *pNodeId +) +{ + return nv_get_egm_info(NV_GET_NV_STATE(pGpu), pPhysAddr, pSize, pNodeId); +} + +/*! + * @brief Offline (i.e., blacklist) the page containing a given address from OS kernel. + * + * @param[in] address Address (SPA) of the page to be offlined + * + */ +NV_STATUS +osOfflinePageAtAddress +( + NvU64 address +) +{ + return os_offline_page_at_address(address); +} diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c index 6896bb8ec1..d51b270f93 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osapi.c +++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c @@ -59,6 +59,7 @@ #include #include #include "nv-reg.h" +#include "nv-firmware-registry.h" #include "core/hal_mgr.h" #include "gpu/device/device.h" @@ -337,6 +338,11 @@ RmLogGpuCrash(OBJGPU *pGpu) "NVRM: A GPU crash dump has been created. If possible, please run\n" "NVRM: nvidia-bug-report.sh as root to collect this data before\n" "NVRM: the NVIDIA kernel module is unloaded.\n"); + if (hypervisorIsVgxHyper()) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Dumping nvlogs buffers\n"); + nvlogDumpToKernelLog(NV_FALSE); + } } // Restore the disconnected properties, if they were reset @@ -1214,12 +1220,13 @@ static void RmHandleDNotifierEvent( static NV_STATUS RmDmabufVerifyMemHandle( - OBJGPU *pGpu, - NvHandle hSrcClient, - NvHandle hMemory, - NvU64 offset, - NvU64 size, - void *pGpuInstanceInfo + OBJGPU *pGpu, + NvHandle hSrcClient, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + void *pGpuInstanceInfo, + MEMORY_DESCRIPTOR **ppMemDesc ) { NV_STATUS status; @@ -1282,6 +1289,8 @@ RmDmabufVerifyMemHandle( return NV_ERR_INVALID_ARGUMENT; } + *ppMemDesc = pMemDesc; + return NV_OK; } @@ -1662,6 +1671,43 @@ static void RmHandleGPSStatusChange nv_state_t *pNv ) { + NV_STATUS rmStatus; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS gpsControl = { 0 }; + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI); + if (pRmApi == NULL) + { + return; + } + + gpsControl.command = NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK; + gpsControl.locale = NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM; + + // + // NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL is not a subdevice command. + // But, Inside GPS module, the first GPU, which has GPS + // enabled will be grabbed with GPU manager. The RMAPI_API_LOCK_INTERNAL + // will internally grab the GPU locks and wake-up all the GPUs. Ideally + // this control call should be GPU specific command, if internally + // it uses the GPU. + // + rmStatus = pRmApi->Control(pRmApi, + pNv->rmapi.hClient, + pNv->rmapi.hClient, + NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL, + (void *)&gpsControl, + sizeof(NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS)); + + RmUnixRmApiEpilogue(pNv, &threadState); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle ACPI GPS status change event, status=0x%x\n", + __FUNCTION__, rmStatus); + } } /*! @@ -1918,15 +1964,20 @@ static NV_STATUS RmCreateMmapContextLocked( { if (CliSetGpuContext(hClient, hDevice, &pGpu, NULL) != NV_OK) { - NvU32 tmp; - if (CliSetSubDeviceContext(hClient, hDevice, &tmp, &pGpu) != NV_OK) - { - // - // If this mapping isn't for a GPU then we don't need to - // create a context for it. - // + RsClient *pClient; + Subdevice *pSubdevice; + + status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); + if (status != NV_OK) return status; - } + + status = subdeviceGetByHandle(pClient, hDevice, &pSubdevice); + if (status != NV_OK) + return status; + + pGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); } } @@ -2125,6 +2176,7 @@ static NV_STATUS RmGetAllocPrivate( switch (memdescGetAddressSpace(pMemDesc)) { case ADDR_SYSMEM: + case ADDR_EGM: break; default: rmStatus = NV_ERR_OBJECT_NOT_FOUND; @@ -3147,37 +3199,6 @@ NV_STATUS rm_update_device_mapping_info( return RmStatus; } -static void rm_is_device_rm_firmware_capable( - nv_state_t *pNv, - NvU32 pmcBoot42, - NvBool *pbIsFirmwareCapable, - NvBool *pbEnableByDefault -) -{ - NvBool bIsFirmwareCapable = NV_FALSE; - NvBool bEnableByDefault = NV_FALSE; - - if (NV_IS_SOC_DISPLAY_DEVICE(pNv)) - { - bIsFirmwareCapable = NV_TRUE; - } - else - { - bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pNv->pci_info.device_id, - pmcBoot42, - &bEnableByDefault); - } - - if (pbIsFirmwareCapable != NULL) - { - *pbIsFirmwareCapable = bIsFirmwareCapable; - } - if (pbEnableByDefault != NULL) - { - *pbEnableByDefault = bEnableByDefault; - } -} - static NvBool NV_API_CALL rm_is_legacy_device( NvU16 device_id, NvU16 subsystem_vendor, @@ -3268,10 +3289,10 @@ NV_STATUS NV_API_CALL rm_is_supported_device( { NvBool bIsFirmwareCapable; - rm_is_device_rm_firmware_capable(pNv, - pmc_boot_42, - &bIsFirmwareCapable, - NULL); + bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pNv->pci_info.device_id, + pmc_boot_42, + NV_IS_SOC_DISPLAY_DEVICE(pNv), + NULL); if (!bIsFirmwareCapable) { nv_printf(NV_DBG_ERRORS, @@ -4042,7 +4063,7 @@ NV_STATUS NV_API_CALL rm_p2p_dma_map_pages( nvidia_stack_t *sp, nv_dma_device_t *peer, NvU8 *pGpuUuid, - NvU32 pageSize, + NvU64 pageSize, NvU32 pageCount, NvU64 *pDmaAddresses, void **ppPriv @@ -4444,25 +4465,14 @@ static void rm_set_firmware_logs( nv_state_t *nv ) { - NV_STATUS status; - NvU32 data; void *fp; + NvU32 enableFirmwareLogsRegVal = NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG; NV_ENTER_RM_RUNTIME(sp,fp); - status = RmReadRegistryDword(nv, NV_REG_ENABLE_GPU_FIRMWARE_LOGS, &data); - if (status == NV_OK) - { - if ((data == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE) -#if defined(DEBUG) || defined(DEVELOP) - || (data == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG) -#endif - ) - { - nv->enable_firmware_logs = NV_TRUE; - } - } - + (void) RmReadRegistryDword(nv, NV_REG_ENABLE_GPU_FIRMWARE_LOGS, + &enableFirmwareLogsRegVal); + nv->enable_firmware_logs = gpumgrGetRmFirmwareLogsEnabled(enableFirmwareLogsRegVal); NV_EXIT_RM_RUNTIME(sp,fp); } @@ -4677,7 +4687,6 @@ void RmInitAcpiMethods(OBJOS *pOS, OBJSYS *pSys, OBJGPU *pGpu) // Check if NVPCF _DSM functions are implemented under NVPCF or GPU device scope. RmCheckNvpcfDsmScope(pGpu); acpiDsmInit(pGpu); - } // @@ -5094,7 +5103,8 @@ NvBool NV_API_CALL rm_is_iommu_needed_for_sriov( NvBool NV_API_CALL rm_disable_iomap_wc(void) { OBJSYS *pSys = SYS_GET_INSTANCE(); - return pSys->pCl->getProperty(pSys, PDB_PROP_CL_DISABLE_IOMAP_WC) == NV_TRUE; + OBJCL *pCl = pSys->pCl; + return pCl->getProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC) == NV_TRUE; } // @@ -5112,9 +5122,11 @@ NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle( NvHandle hMemory, NvU64 offset, NvU64 size, - NvHandle *phMemoryDuped + NvHandle *phMemoryDuped, + void **ppStaticMemInfo ) { + MEMORY_DESCRIPTOR *pMemDesc; THREAD_STATE_NODE threadState; NV_STATUS rmStatus; OBJGPU *pGpu; @@ -5130,7 +5142,8 @@ NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle( NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); rmStatus = RmDmabufVerifyMemHandle(pGpu, hSrcClient, hMemory, - offset, size, pGpuInstanceInfo); + offset, size, pGpuInstanceInfo, + &pMemDesc); if (rmStatus == NV_OK) { RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); @@ -5164,6 +5177,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle( *phMemoryDuped = hMemoryDuped; } } + *ppStaticMemInfo = (void *) pMemDesc; } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -5205,39 +5219,102 @@ void NV_API_CALL rm_dma_buf_undup_mem_handle( NV_EXIT_RM_RUNTIME(sp,fp); } -// -// Maps a handle to BAR1. -// Must be called with API lock and GPU lock held. -// NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle( - nvidia_stack_t *sp, - nv_state_t *nv, - NvHandle hClient, - NvHandle hMemory, - NvU64 offset, - NvU64 size, - NvU64 *pBar1Va + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + NvU64 offset, + NvU64 size, + void *pStaticMemInfo, + nv_phys_addr_range_t **ppRanges, + NvU32 *pRangeCount ) { THREAD_STATE_NODE threadState; - NV_STATUS rmStatus; + NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu; - KernelBus *pKernelBus; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + NV_ASSERT_OR_GOTO(((ppRanges != NULL) && (pRangeCount != NULL)), Done); + pGpu = NV_GET_NV_PRIV_PGPU(nv); - pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NV_ASSERT(rmapiLockIsOwner()); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR *) pStaticMemInfo; + NvU32 pageSize = 0; + NvU32 pageCount = 0; + NvU32 i = 0; - NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + pageCount = size / pageSize; - rmStatus = kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, - hMemory, offset, size, pBar1Va); + rmStatus = os_alloc_mem((void **) ppRanges, + pageCount * sizeof(nv_phys_addr_range_t)); + if (rmStatus != NV_OK) + { + goto Done; + } + + for (i = 0; i < pageCount; i++) + { + NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, offset); + (*ppRanges)[i].addr = pKernelMemorySystem->coherentCpuFbBase + physAddr; + (*ppRanges)[i].len = pageSize; + + offset += pageSize; + } + *pRangeCount = pageCount; + } + else + { + Device *pDevice; + RsClient *pClient; + KernelBus *pKernelBus; + NvU64 bar1Va; + + NV_ASSERT(rmapiLockIsOwner()); + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), + Done); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice), + Done); + + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + rmStatus = kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, + hMemory, offset, size, &bar1Va, + pDevice); + if (rmStatus != NV_OK) + { + goto Done; + } + + // Adjust this alloc when discontiguous BAR1 is supported + rmStatus = os_alloc_mem((void **) ppRanges, + sizeof(nv_phys_addr_range_t)); + if (rmStatus != NV_OK) + { + kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient, + hMemory, bar1Va); + goto Done; + } + (*ppRanges)[0].addr = bar1Va; + (*ppRanges)[0].len = size; + *pRangeCount = 1; + } + +Done: threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp,fp); @@ -5248,38 +5325,52 @@ NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle( // Unmaps a handle from BAR1. // Must be called with API lock and GPU lock held. // -NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle( - nvidia_stack_t *sp, - nv_state_t *nv, - NvHandle hClient, - NvHandle hMemory, - NvU64 size, - NvU64 bar1Va +void NV_API_CALL rm_dma_buf_unmap_mem_handle( + nvidia_stack_t *sp, + nv_state_t *nv, + NvHandle hClient, + NvHandle hMemory, + NvU64 size, + nv_phys_addr_range_t **ppRanges, + NvU32 rangeCount ) { THREAD_STATE_NODE threadState; - NV_STATUS rmStatus; + NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu; - KernelBus *pKernelBus; + NvU32 i; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + NV_ASSERT_OR_GOTO(((ppRanges != NULL) && (rangeCount != 0)), Done); + pGpu = NV_GET_NV_PRIV_PGPU(nv); - pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NV_ASSERT(rmapiLockIsOwner()); + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + KernelBus *pKernelBus; - NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + NV_ASSERT(rmapiLockIsOwner()); + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + for (i = 0; i < rangeCount; i++) + { + rmStatus = kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient, + hMemory, (*ppRanges)[i].addr); + NV_ASSERT_OK(rmStatus); + } + } - rmStatus = kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient, - hMemory, bar1Va); + os_free_mem(*ppRanges); + *ppRanges = NULL; +Done: threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp,fp); - - return rmStatus; } NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( @@ -5289,7 +5380,8 @@ NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( NvHandle *phClient, NvHandle *phDevice, NvHandle *phSubdevice, - void **ppGpuInstanceInfo + void **ppGpuInstanceInfo, + NvBool *pbStaticPhysAddrs ) { THREAD_STATE_NODE threadState; @@ -5310,6 +5402,12 @@ NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( { rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, phClient, phDevice, phSubdevice, ppGpuInstanceInfo); + if (rmStatus == NV_OK) + { + // Note: revisit this when BAR1 static map is supported. + *pbStaticPhysAddrs = pGpu->getProperty(pGpu, + PDB_PROP_GPU_COHERENT_CPU_MAPPING); + } rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); } @@ -5369,6 +5467,25 @@ void NV_API_CALL rm_dma_buf_put_client_and_device( // NOTE: Used only on VMWware // +void NV_API_CALL rm_vgpu_vfio_set_driver_vm( + nvidia_stack_t *sp, + NvBool is_driver_vm +) +{ + OBJSYS *pSys; + POBJHYPERVISOR pHypervisor; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pSys = SYS_GET_INSTANCE(); + pHypervisor = SYS_GET_HYPERVISOR(pSys); + + pHypervisor->setProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED, is_driver_vm); + + NV_EXIT_RM_RUNTIME(sp,fp); +} + NvBool NV_API_CALL rm_is_altstack_in_use(void) { #if defined(__use_altstack__) diff --git a/src/nvidia/arch/nvalloc/unix/src/osinit.c b/src/nvidia/arch/nvalloc/unix/src/osinit.c index 7af025e8a5..8022c6c347 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osinit.c +++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c @@ -80,6 +80,8 @@ #include #include +#include + #include // RMCONFIG: need definition of REGISTER_ALL_HALS() #include "g_hal_register.h" @@ -476,6 +478,8 @@ RmInitGpuInfoWithRmApi NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES); } + nv->coherent = pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING); + portMemFree(pGpuInfoParams); // UNLOCK: release GPUs lock @@ -1381,7 +1385,8 @@ static NvBool RmUnixAllocRmApi( NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &nv->rmapi.hClient) != NV_OK) + &nv->rmapi.hClient, + sizeof(nv->rmapi.hClient)) != NV_OK) { goto fail; } @@ -1405,7 +1410,8 @@ static NvBool RmUnixAllocRmApi( nv->rmapi.hClient, &nv->rmapi.hDevice, NV01_DEVICE_0, - &deviceParams) != NV_OK) + &deviceParams, + sizeof(deviceParams)) != NV_OK) { goto fail; } @@ -1418,7 +1424,8 @@ static NvBool RmUnixAllocRmApi( nv->rmapi.hDevice, &nv->rmapi.hSubDevice, NV20_SUBDEVICE_0, - &subDeviceParams) != NV_OK) + &subDeviceParams, + sizeof(subDeviceParams)) != NV_OK) { goto fail; } @@ -1433,7 +1440,8 @@ static NvBool RmUnixAllocRmApi( nv->rmapi.hSubDevice, &nv->rmapi.hI2C, NV40_I2C, - NULL) != NV_OK) + NULL, + 0) != NV_OK) { nv->rmapi.hI2C = 0; } @@ -1449,7 +1457,8 @@ static NvBool RmUnixAllocRmApi( nv->rmapi.hDevice, &nv->rmapi.hDisp, NV04_DISPLAY_COMMON, - NULL) != NV_OK) + NULL, + 0) != NV_OK) { nv->rmapi.hDisp = 0; } @@ -1461,6 +1470,59 @@ static NvBool RmUnixAllocRmApi( return NV_FALSE; } +static NV_STATUS RmFetchGspRmImages +( + nv_state_t *nv, + GSP_FIRMWARE *pGspFw, + const void **gspFwHandle, + const void **gspFwLogHandle +) +{ + nv_firmware_chip_family_t chipFamily; + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU32 gpuArch = (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, nvp->pmc_boot_42) << + GPU_ARCH_SHIFT); + NvU32 gpuImpl = DRF_VAL(_PMC, _BOOT_42, _IMPLEMENTATION, nvp->pmc_boot_42); + + chipFamily = nv_firmware_get_chip_family(gpuArch, gpuImpl); + + portMemSet(pGspFw, 0, sizeof(*pGspFw)); + + *gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP, + chipFamily, + &pGspFw->pBuf, + &pGspFw->size); + if (*gspFwHandle == NULL && + !nv->allow_fallback_to_monolithic_rm) + { + NV_PRINTF(LEVEL_ERROR, "No firmware image found\n"); + return NV_ERR_NOT_SUPPORTED; + } + else if (*gspFwHandle != NULL) + { +#if LIBOS_LOG_DECODE_ENABLE + if (nv->enable_firmware_logs) + { + *gspFwLogHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP_LOG, + chipFamily, + &pGspFw->pLogElf, + &pGspFw->logElfSize); + if (*gspFwLogHandle == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to load gsp_log_*.bin, no GSP-RM logs will be printed (non-fatal)\n"); + } + } +#endif + nv->request_fw_client_rm = NV_TRUE; + } + else + { + nv->request_fw_client_rm = NV_FALSE; + } + + return NV_OK; +} + NvBool RmInitAdapter( nv_state_t *nv ) @@ -1524,46 +1586,14 @@ NvBool RmInitAdapter( // if (nv->request_firmware) { - NvU32 gpuArch = (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, nvp->pmc_boot_42) << - GPU_ARCH_SHIFT); - NvU32 gpuImpl = DRF_VAL(_PMC, _BOOT_42, _IMPLEMENTATION, nvp->pmc_boot_42); - - nv_firmware_chip_family_t chipFamily = nv_firmware_get_chip_family(gpuArch, gpuImpl); - nv_set_dma_address_size(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); - gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP, - chipFamily, - &gspFw.pBuf, - &gspFw.size); - if (gspFwHandle == NULL && - !nv->allow_fallback_to_monolithic_rm) + status.rmStatus = RmFetchGspRmImages(nv, &gspFw, &gspFwHandle, &gspFwLogHandle); + if (status.rmStatus != NV_OK) { RM_SET_ERROR(status, RM_INIT_FIRMWARE_FETCH_FAILED); goto shutdown; } - else if (gspFwHandle != NULL) - { -#if LIBOS_LOG_DECODE_ENABLE - if (nv->enable_firmware_logs) - { - gspFwLogHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP_LOG, - chipFamily, - &gspFw.pLogElf, - &gspFw.logElfSize); - if (gspFwLogHandle == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Failed to load gsp_log_*.bin, no GSP-RM logs will be printed (non-fatal)\n"); - } - } -#endif - - nv->request_fw_client_rm = NV_TRUE; - } - else - { - nv->request_fw_client_rm = NV_FALSE; - } } // initialize the RM device register mapping @@ -1606,6 +1636,7 @@ NvBool RmInitAdapter( if (status.rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "FSP boot command failed.\n"); + RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED); goto shutdown; } } @@ -1661,6 +1692,17 @@ NvBool RmInitAdapter( initNbsiTable(pGpu); } + // + // Load GSP proxy if early init is required. We need to do this + // before we trigger a full gpuStateInit and gpuStateLoad in + // RmInitNvDevice + // TODO: Check bug 200744430 + // + if (gpuIsCCFeatureEnabled(pGpu)) + { + confComputeEarlyInit(pGpu, GPU_GET_CONF_COMPUTE(pGpu)); + } + // finally, initialize the device RmInitNvDevice(devicereference, &status); if (! RM_INIT_SUCCESS(status.initStatus) ) @@ -1710,6 +1752,14 @@ NvBool RmInitAdapter( intrSetIntrEn(pIntr, INTERRUPT_TYPE_HARDWARE); } + // LOCK: acquire GPUs lock + status.rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_INIT); + if (status.rmStatus != NV_OK) + { + goto shutdown; + } + KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu); // initialize the watchdog (disabled by default) status.rmStatus = pKernelRc != NULL ? krcWatchdogInit_HAL(pGpu, pKernelRc) : @@ -1729,8 +1779,13 @@ NvBool RmInitAdapter( RM_SET_ERROR(status, RM_INIT_WATCHDOG_FAILED); NV_PRINTF(LEVEL_ERROR, "krcWatchdogInit failed, bailing out of RmInitAdapter\n"); + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); goto shutdown; } + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); nv_start_rc_timer(nv); nvp->status = NV_OK; diff --git a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c index ad49cf71a8..54cba07578 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c +++ b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -71,9 +71,10 @@ osCreateMemFromOsDescriptor NV_STATUS rmStatus; void *pPrivate; + pClient = serverutilGetClientUnderLock(hClient); if ((pDescriptor == NvP64_NULL) || (*pLimit == 0) || - (serverutilGetClientUnderLock(hClient, &pClient) != NV_OK)) + (pClient == NULL)) { return NV_ERR_INVALID_PARAM_STRUCT; } diff --git a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c index 2d597a149c..b2c17e824d 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c +++ b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -95,6 +95,15 @@ static void NV_API_CALL osNvlinkFreeAltStack(nvidia_stack_t *sp) #endif } +static NV_STATUS NV_API_CALL osNvlinkGetAltStack(nvidia_stack_t **sp) +{ + return osNvlinkAllocAltStack(sp); +} +static void NV_API_CALL osNvlinkPutAltStack(nvidia_stack_t *sp) +{ + osNvlinkFreeAltStack(sp); +} + static NvlStatus NV_API_CALL rm_nvlink_ops_add_link ( struct nvlink_link *link @@ -102,10 +111,9 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_add_link { void *fp; NvlStatus status; - KNVLINK_RM_LINK *pLink = link->link_info; nvidia_stack_t *sp; - if (NV_OK != osNvlinkAllocAltStack(&sp)) + if (osNvlinkGetAltStack(&sp) != NV_OK) { return NVL_ERR_GENERIC; } @@ -116,14 +124,7 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_add_link NV_EXIT_RM_RUNTIME(sp, fp); - if (status == NVL_SUCCESS) - { - pLink->pOsInfo = sp; - } - else - { - osNvlinkFreeAltStack(sp); - } + osNvlinkPutAltStack(sp); return status; } @@ -135,10 +136,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_remove_link { void *fp; NvlStatus status; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; - pLink->pOsInfo = NULL; + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -146,7 +149,7 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_remove_link NV_EXIT_RM_RUNTIME(sp, fp); - osNvlinkFreeAltStack(sp); + osNvlinkPutAltStack(sp); return status; } @@ -159,8 +162,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_lock_link void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -170,6 +177,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_lock_link NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -180,8 +189,12 @@ static void NV_API_CALL rm_nvlink_ops_unlock_link { void *fp; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -190,6 +203,8 @@ static void NV_API_CALL rm_nvlink_ops_unlock_link threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); } static NvlStatus NV_API_CALL rm_nvlink_ops_queue_link_change @@ -200,8 +215,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_queue_link_change void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link_change->master->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -211,6 +230,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_queue_link_change NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -224,8 +245,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_dl_link_mode void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -235,6 +260,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_dl_link_mode NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -247,8 +274,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_dl_link_mode void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -258,6 +289,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_dl_link_mode NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -271,8 +304,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_tl_link_mode void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -281,6 +318,7 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_tl_link_mode threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); return status; } @@ -294,8 +332,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_tl_link_mode void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -305,6 +347,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_tl_link_mode NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -318,8 +362,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_tx_mode void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -329,6 +377,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_tx_mode NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -342,8 +392,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_tx_mode void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -353,6 +407,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_tx_mode NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -366,8 +422,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_mode void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -377,6 +437,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_mode NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -390,8 +452,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_mode void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -401,6 +467,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_mode NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -413,8 +481,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_detect void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -424,6 +496,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_set_link_rx_detect NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -435,8 +509,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_detect void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -446,6 +524,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_get_link_rx_detect NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -457,8 +537,12 @@ static void NV_API_CALL rm_nvlink_get_uphy_load { void *fp; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -467,6 +551,8 @@ static void NV_API_CALL rm_nvlink_get_uphy_load threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); } static NvlStatus NV_API_CALL rm_nvlink_ops_read_link_discovery_token @@ -478,8 +564,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_read_link_discovery_token void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -489,6 +579,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_read_link_discovery_token NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -501,8 +593,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_write_link_discovery_token void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -512,6 +608,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_write_link_discovery_token NV_EXIT_RM_RUNTIME(sp, fp); + osNvlinkPutAltStack(sp); + return status; } @@ -522,8 +620,12 @@ static void NV_API_CALL rm_nvlink_ops_training_complete { void *fp; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK *pLink = link->link_info; - nvidia_stack_t *sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t *sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -532,6 +634,8 @@ static void NV_API_CALL rm_nvlink_ops_training_complete threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); } static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training @@ -542,8 +646,12 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training void *fp; NvlStatus status; THREAD_STATE_NODE threadState = {0}; - KNVLINK_RM_LINK * pLink = link->link_info; - nvidia_stack_t * sp = (nvidia_stack_t *)pLink->pOsInfo; + nvidia_stack_t * sp; + + if (osNvlinkGetAltStack(&sp) != NV_OK) + { + return NVL_ERR_GENERIC; + } NV_ENTER_RM_RUNTIME(sp, fp); @@ -552,6 +660,8 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp, fp); + + osNvlinkPutAltStack(sp); return status; } diff --git a/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c b/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c index f198f9f15b..2d3b3d1b87 100644 --- a/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c +++ b/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -214,7 +214,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_get_pma_object( NV_STATUS NV_API_CALL rm_gpu_ops_pma_alloc_pages( nvidia_stack_t *sp, void *pPma, - NvLength pageCount, NvU32 pageSize, + NvLength pageCount, NvU64 pageSize, nvgpuPmaAllocationOptions_t pPmaAllocOptions, NvU64 *pPages) { @@ -229,7 +229,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_pma_alloc_pages( NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages( nvidia_stack_t *sp, void *pPma, - NvU64 *pPages, NvLength pageCount, NvU32 pageSize, NvU32 flags) + NvU64 *pPages, NvLength pageCount, NvU64 pageSize, NvU32 flags) { NV_STATUS rmStatus; void *fp; @@ -241,7 +241,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages( NV_STATUS NV_API_CALL rm_gpu_ops_pma_unpin_pages( nvidia_stack_t *sp, void *pPma, - NvU64 *pPages, NvLength pageCount, NvU32 pageSize) + NvU64 *pPages, NvLength pageCount, NvU64 pageSize) { NV_STATUS rmStatus; void *fp; @@ -253,7 +253,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_pma_unpin_pages( NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_map( nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, - NvU64 gpuOffset, NvLength length, void **cpuPtr, NvU32 pageSize) + NvU64 gpuOffset, NvLength length, void **cpuPtr, NvU64 pageSize) { NV_STATUS rmStatus; void *fp; @@ -274,8 +274,31 @@ NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_ummap( return NV_OK; } +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_allocate(nvidia_stack_t *sp, + gpuAddressSpaceHandle vaspace, + const gpuTsgAllocParams *allocParams, + gpuTsgHandle *tsg) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsTsgAllocate(vaspace, allocParams, tsg); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_tsg_destroy(nvidia_stack_t * sp, + nvgpuTsgHandle_t tsg) +{ + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + nvGpuOpsTsgDestroy(tsg); + NV_EXIT_RM_RUNTIME(sp,fp); + return NV_OK; +} + NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *sp, - gpuAddressSpaceHandle vaspace, + const gpuTsgHandle tsg, const gpuChannelAllocParams *allocParams, gpuChannelHandle *channel, gpuChannelInfo *channelInfo) @@ -283,7 +306,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *sp, NV_STATUS rmStatus; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); - rmStatus = nvGpuOpsChannelAllocate(vaspace, allocParams, channel, + rmStatus = nvGpuOpsChannelAllocate(tsg, allocParams, channel, channelInfo); NV_EXIT_RM_RUNTIME(sp,fp); return rmStatus; @@ -300,7 +323,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_channel_destroy(nvidia_stack_t * sp, } NV_STATUS NV_API_CALL rm_gpu_ops_pma_free_pages(nvidia_stack_t *sp, - void *pPma, NvU64 *pPages, NvLength pageCount, NvU32 pageSize, NvU32 flags) + void *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize, NvU32 flags) { void *fp; NV_ENTER_RM_RUNTIME(sp,fp); @@ -583,12 +606,13 @@ NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *sp, gpuDeviceHandle device, - gpuAccessCntrInfo *accessCntrInfo) + gpuAccessCntrInfo *accessCntrInfo, + NvU32 accessCntrIndex) { NV_STATUS rmStatus; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); - rmStatus = nvGpuOpsInitAccessCntrInfo(device, accessCntrInfo); + rmStatus = nvGpuOpsInitAccessCntrInfo(device, accessCntrInfo, accessCntrIndex); NV_EXIT_RM_RUNTIME(sp,fp); return rmStatus; } @@ -822,3 +846,136 @@ rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *sp, return rmStatus; } +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *sp, + struct ccslContext_t **ctx, + gpuChannelHandle channel) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslContextInit(ctx, channel); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *sp, + struct ccslContext_t *ctx) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslContextClear(ctx); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_acquire_encryption_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 *encryptIv) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslAcquireEncryptionIv(ctx, encryptIv); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_log_device_encryption(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 *decryptIv) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslLogDeviceEncryption(ctx, decryptIv); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslRotateIv(ctx, direction); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt_with_iv(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslEncryptWithIv(ctx, bufferSize, inputBuffer, encryptIv, outputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslEncrypt(ctx, bufferSize, inputBuffer, outputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *authTagData) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslDecrypt(ctx, bufferSize, inputBuffer, decryptIv, outputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_sign(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagData) + +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslSign(ctx, bufferSize, inputBuffer, authTagData); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_query_message_pool(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsQueryMessagePool(ctx, direction, messageNum); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} diff --git a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c index dcc8d94ada..10be0f8de3 100644 --- a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c +++ b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c @@ -262,7 +262,8 @@ static NV_STATUS RmRefObjExportImport(void) NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &hObjExportRmClient); + &hObjExportRmClient, + sizeof(hObjExportRmClient)); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to alloc root in %s\n", __FUNCTION__); @@ -426,7 +427,8 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, hObjExportRmClient, objExportDevice[deviceInstance].hRmDevice, NV01_DEVICE_0, - ¶ms); + ¶ms, + sizeof(params)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to alloc device in %s\n", @@ -443,7 +445,8 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, objExportDevice[deviceInstance].hRmDevice, objExportDevice[deviceInstance].hRmSubDevice, NV20_SUBDEVICE_0, - &subdevParams); + &subdevParams, + sizeof(subdevParams)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to alloc subdevice in %s\n", diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_console.c b/src/nvidia/arch/nvalloc/unix/src/unix_console.c index 8b1c055373..271769ed3f 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_console.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_console.c @@ -30,6 +30,291 @@ #include #include +#include +#include "vgpu/vgpu_events.h" + +static NV_STATUS +unixCallVideoBIOS +( + OBJGPU *pGpu, + NvU32 *eax, + NvU32 *ebx +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (NVCPU_IS_X86_64) + { + NvU32 eax_in = *eax; + NvU32 ebx_in = *ebx; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_PRINTF(LEVEL_INFO, "unixCallVideoBIOS: 0x%x 0x%x, vga_satus = %d\n", *eax, *ebx, NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))); + + status = nv_vbios_call(pGpu, eax, ebx); + + // this was originally changed for nt in changelist 644223 + if (*eax != 0x4f) + { + NV_PRINTF(LEVEL_ERROR, + "int10h(%04x, %04x) vesa call failed! (%04x, %04x)\n", + eax_in, ebx_in, *eax, *ebx); + status = NV_ERR_GENERIC; + } + } + + return status; +} + +static void +RmSaveDisplayState +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv); + NvU32 eax, ebx; + NV_STATUS status; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS unixConsoleParams = {0}; + + + if (IS_VIRTUAL(pGpu) || pKernelDisplay == NULL) + { + return; + } + + os_disable_console_access(); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + NV_PRINTF(LEVEL_INFO, "RM fallback doesn't support saving of efifb console\n"); + goto done; + } + + unixConsoleParams.bSaveOrRestore = NV_TRUE; + unixConsoleParams.bUseVbios = use_vbios; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR,pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE, + &unixConsoleParams, sizeof(unixConsoleParams)), done); + + if (use_vbios) + { + // + // Attempt to identify the currently set VESA mode; assume + // vanilla VGA text if the VBIOS call fails. + // + eax = 0x4f03; + ebx = 0; + if (NV_OK == unixCallVideoBIOS(pGpu, &eax, &ebx)) + { + nvp->vga.vesaMode = (ebx & 0x3fff); + } + else + { + nvp->vga.vesaMode = 3; + } + } + +done: + os_enable_console_access(); +} + +static void RmRestoreDisplayState +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv);; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NV_STATUS status; + NvU32 eax, ebx; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS unixConsoleParams = {0}; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS restoreParams = {0}; + + NV_ASSERT_OR_RETURN_VOID(pKernelDisplay != NULL); + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, there is nothing to do at this point in the + // guest OS (where IS_VIRTUAL(pGpu) is true). + // + if (IS_VIRTUAL(pGpu)) + { + // we don't have VGA state that's needing to be restored. + NV_PRINTF(LEVEL_INFO, "skipping RestoreDisplayState on VGPU (0x%x)\n", + pGpu->gpuId); + return; + } + + os_disable_console_access(); + + // + // Fix up DCB index VBIOS scratch registers. + // The strategies employed are: + // + // SBIOS/VBIOS: + // Clear the DCB index, and set the previous DCB index to the original + // value. This allows the VBIOS (during the int10h mode-set) to + // determine which display to enable, and to set the head-enabled bit + // as needed (see bugs #264873 and #944398). + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + NV_PRINTF(LEVEL_INFO, "RM fallback doesn't support efifb console restore\n"); + goto done; + } + + unixConsoleParams.bUseVbios = use_vbios; + unixConsoleParams.bSaveOrRestore = NV_FALSE; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE, + &unixConsoleParams, sizeof(unixConsoleParams)), done); + + eax = 0x4f02; + ebx = nvp->vga.vesaMode; + + if (NV_OK == unixCallVideoBIOS(pGpu, &eax, &ebx)) + { + restoreParams.bWriteCr = NV_TRUE; + } + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE, + &restoreParams, sizeof(restoreParams)), done); + +done: + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) + { + } + os_enable_console_access(); +} + +static void +RmChangeResMode +( + OBJGPU *pGpu, + NvBool hires +) +{ + if (hires) + { + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + RmSaveDisplayState(pGpu); + + SLI_LOOP_END + } + else + { + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + + RmRestoreDisplayState(pGpu); + // + // vGPU: + // + // Since vGPU does all real hardware management in the host, if we + // are in guest OS (where IS_VIRTUAL(pGpu) is true), do an RPC to + // the host to trigger switch from HIRES to (LORES)VGA. + // + if (IS_VIRTUAL(pGpu)) + { + NV_STATUS status = NV_OK; + NV_RM_RPC_SWITCH_TO_VGA(pGpu, status); + } + + SLI_LOOP_END + } +} + +NV_STATUS NV_API_CALL +rm_save_low_res_mode +( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + THREAD_STATE_NODE threadState; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + RmSaveDisplayState(pGpu); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return NV_OK; +} + +NV_STATUS +deviceCtrlCmdOsUnixVTSwitch_IMPL +( + Device *pDevice, + NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvBool hires; + NvBool bChangeResMode = NV_TRUE; + + switch (pParams->cmd) + { + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE: + hires = NV_TRUE; + break; + + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE: + hires = NV_FALSE; + break; + + case NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED: + bChangeResMode = NV_FALSE; + break; + + default: + return NV_ERR_INVALID_ARGUMENT; + } + + RmUpdateGc6ConsoleRefCount(nv, + pParams->cmd != NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE); + + if (!bChangeResMode) + { + return NV_OK; + } + + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FB) == NV_OK) + { + RmChangeResMode(pGpu, hires); + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + else + { + NV_PRINTF(LEVEL_INFO,"%s: Failed to acquire GPU lock", __FUNCTION__); + } + return NV_OK; +} + NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL ( Device *pDevice, diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c index 09d022b245..56a2103cb1 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c @@ -174,6 +174,18 @@ static NvBool osInterruptPending( } } + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + !IS_VIRTUAL(pGpu) && bitVectorTest(&intr0Pending, MC_ENGINE_IDX_TMR)) + { + // We have to clear the top level interrupt bit here since otherwise + // the bottom half will attempt to service the interrupt on the CPU + // side before GSP receives the notification and services it + intrClearLeafVector_HAL(pGpu, pIntr, MC_ENGINE_IDX_TMR, &threadState); + bitVectorClr(&intr0Pending, MC_ENGINE_IDX_TMR); + + NV_ASSERT_OK(intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_HANDLE)); + } + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) { diff --git a/src/nvidia/arch/nvalloc/unix/src/vbioscall.c b/src/nvidia/arch/nvalloc/unix/src/vbioscall.c new file mode 100644 index 0000000000..8eeb85e993 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/src/vbioscall.c @@ -0,0 +1,457 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/****************************************************************************** +* +* Description: +* This file provides the glue layer between the RM's OS object +* unixCallVideoBIOS() method and the x86 real mode emulator +* +******************************************************************************/ + + +#include +#include +#include +#include + +#include + +#include + +#define IO_LOG(port, val) + +#define NV_ROMLEY_VGA_PHYS_ADDR 0x9d000 +#define NV_VGA_PHYS_ADDR 0xa0000 +#define NV_VIDEO_ROM_PHYS_ADDR 0xc0000 +#define NV_EXPANSION_VIDEO_ROM_PHYS_ADDR 0xc8000 +#define NV_SYSTEM_ROM_PHYS_ADDR 0xf0000 + +#define X86EMU_LOWMEM 0x600 // Interrupt vectors, BIOS data size +#define X86EMU_STACK_ADDR 0x10000 +#define X86EMU_STACK_SIZE 0x1000 +#define X86EMU_BUF_ADDR 0x20000 // EDID buffer for VESA int10 0x4f15 +#define X86EMU_BUF_SIZE 128 + +#define OP_HLT 0xf4 // HLT instruction - causes the emulator to return + +// This is where IRET from int10 will take us +#define X86EMU_IRET_SEG (X86EMU_STACK_ADDR >> 4) +#define X86EMU_IRET_OFF 0 + +#define X86EMU_DFLT_FLAGS (F_IF) + +static NvBool x86emuReady; +static void *x86emuStack; + +static struct x86emu_mem_seg { + NvU32 start; + NvU32 end; + void *vaddr; +} x86emu_mem_map[] = { + {NV_ROMLEY_VGA_PHYS_ADDR, NV_VGA_PHYS_ADDR - 1}, + {NV_VGA_PHYS_ADDR, NV_VIDEO_ROM_PHYS_ADDR - 1}, // vga + {NV_VIDEO_ROM_PHYS_ADDR, NV_EXPANSION_VIDEO_ROM_PHYS_ADDR -1}, // vbios, sbios + {NV_EXPANSION_VIDEO_ROM_PHYS_ADDR, NV_SYSTEM_ROM_PHYS_ADDR -1}, // vbios, sbios + {NV_SYSTEM_ROM_PHYS_ADDR, 0xFFFFF}, // Motherboard BIOS + {X86EMU_STACK_ADDR, X86EMU_STACK_ADDR + X86EMU_STACK_SIZE - 1}, // emulator stack + {0, X86EMU_LOWMEM - 1}, // Interrupt vectors, BIOS data + {X86EMU_BUF_ADDR, X86EMU_BUF_ADDR + X86EMU_BUF_SIZE - 1}, +}; + +enum { + X86EMU_SEG_ROMLEY_VGA = 0, + X86EMU_SEG_VGA, + X86EMU_SEG_ROM, + X86EMU_SEG_ROM_EXPANSION, + X86EMU_SEG_ROM_MOTHERBOARD_BIOS, + X86EMU_SEG_EMULATOR_STACK, + X86EMU_SEG_BIOS_DATA, + X86EMU_SEG_EDID_BUFFER, + X86EMU_NUM_SEGS +}; + +ct_assert(X86EMU_NUM_SEGS == NV_ARRAY_ELEMENTS(x86emu_mem_map)); + +static NvU8 +x_inb(NvU16 port) +{ + NvU8 val; + + val = os_io_read_byte(port); + IO_LOG(port, val); + return val; +} + +static void +x_outb(NvU16 port, NvU8 val) +{ + IO_LOG(port, val); + os_io_write_byte(port, val); +} + +static NvU16 +x_inw(NvU16 port) +{ + NvU16 val; + + val = os_io_read_word(port); + IO_LOG(port, val); + return val; +} + +static void +x_outw(NvU16 port, NvU16 val) +{ + IO_LOG(port, val); + os_io_write_word(port, val); +} + +static u32 +x_inl(X86EMU_pioAddr port) +{ + NvU32 val; + + val = os_io_read_dword(port); + IO_LOG(port, val); + return val; +} + +static void +x_outl(X86EMU_pioAddr port, u32 val) +{ + IO_LOG(port, val); + os_io_write_dword(port, val); +} + +static void * +Mem_addr_xlat(NvU32 addr, NvU32 sz) +{ + int i; + struct x86emu_mem_seg *pseg; + + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + if (pseg->vaddr != 0 && addr >= pseg->start && addr + sz - 1 <= pseg->end) + return (void *)((char *)pseg->vaddr + addr - pseg->start); + } + + X86EMU_halt_sys(); + + return 0; +} + +static NvU8 +Mem_rb(u32 addr) +{ + NvU8 *va = Mem_addr_xlat(addr, 1); + + return va != 0 ? *va : 0; +} + +static NvU16 +Mem_rw(u32 addr) +{ + NvU16 *va = Mem_addr_xlat(addr, 2); + + return va != 0 ? *va : 0; +} + +static u32 +Mem_rl(u32 addr) +{ + NvU32 *va = Mem_addr_xlat(addr, 4); + + return va != 0 ? *va : 0; +} + +static void +Mem_wb(u32 addr, NvU8 val) +{ + NvU8 *va = Mem_addr_xlat(addr, 1); + + if (va != 0) + *va = val; +} + +static void +Mem_ww(u32 addr, NvU16 val) +{ + NvU16 *va = Mem_addr_xlat(addr, 2); + + if (va != 0) + *va = val; +} + +static void +Mem_wl(u32 addr, u32 val) +{ + NvU32 *va = Mem_addr_xlat(addr, 4); + + if (va != 0) + *va = val; +} + +static NvU16 +get_int_seg(int i) +{ + return Mem_rw(i * 4 + 2); +} + + +static NvU16 +get_int_off(int i) +{ + return Mem_rw(i * 4); +} + + +static void +pushw(NvU16 i) +{ + M.x86.R_ESP -= 2; + Mem_ww((M.x86.R_SS << 4) + M.x86.R_ESP, i); +} + +static void +x86emu_do_int(int num) +{ +#if 0 + Int10Current->num = num; + + if (!int_handler(Int10Current)) { + X86EMU_halt_sys(); + } +#else + if ((num == 0x15) && (M.x86.R_AX == 0x5f80)) + { + // + // Handle the MXM_SYS_INFO_CALLBACK_NUM int 15h SBIOS + // callback: disclaim support by returning a value + // other than 005fh (MXM_SYS_INFO_CALLBACK_FUNC_SUPPORTED) + // to the caller. + // + M.x86.R_AX = 0; + } + else + { + NV_PRINTF(LEVEL_ERROR, "x86emu: int $%d (eax = %08x)\n", + num, M.x86.R_EAX); + DBG_BREAKPOINT(); + X86EMU_halt_sys(); + } +#endif +} + +NV_STATUS +RmInitX86EmuState(OBJGPU *pGpu) { + int i; + struct x86emu_mem_seg *pseg; + X86EMU_intrFuncs *intFuncs; + X86EMU_pioFuncs pioFuncs = { + (&x_inb), + (&x_inw), + (&x_inl), + (&x_outb), + (&x_outw), + (&x_outl) + }; + + X86EMU_memFuncs memFuncs = { + (&Mem_rb), + (&Mem_rw), + (&Mem_rl), + (&Mem_wb), + (&Mem_ww), + (&Mem_wl) + }; + + if (!NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) // not the primary GPU + return NV_OK; + + NV_ASSERT(!x86emuReady); + + x86emuStack = portMemAllocNonPaged( + X86EMU_STACK_SIZE + sizeof(X86EMU_intrFuncs*) * 256); + if (x86emuStack == NULL) + return NV_ERR_NO_MEMORY; + + // Interrupt dispatch table + intFuncs = (void *)((NvU8 *)x86emuStack + X86EMU_STACK_SIZE); + + // Fill virtual addresses in the memory map + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + switch (i) + { + case X86EMU_SEG_ROM: + case X86EMU_SEG_ROM_EXPANSION: + case X86EMU_SEG_ROM_MOTHERBOARD_BIOS: + nv_get_updated_emu_seg(&pseg->start, &pseg->end); + /* fallthrough */ + case X86EMU_SEG_VGA: + case X86EMU_SEG_BIOS_DATA: + pseg->vaddr = os_map_kernel_space(pseg->start, + pseg->end - pseg->start + 1, + NV_MEMORY_CACHED); + if (pseg->vaddr == 0) + { + NV_PRINTF(LEVEL_ERROR, "x86emu can't map phys addr 0x%05x\n", + pseg->start); + return NV_ERR_GENERIC; + } + break; + case X86EMU_SEG_EMULATOR_STACK: + pseg->vaddr = x86emuStack; + break; + default: + pseg->vaddr = 0; + break; + } + } + X86EMU_setupMemFuncs(&memFuncs); + + M.mem_base = 0; + M.mem_size = 1024*1024; + X86EMU_setupPioFuncs(&pioFuncs); + + for (i=0;i<256;i++) + intFuncs[i] = x86emu_do_int; + X86EMU_setupIntrFuncs(intFuncs); + + x86emuReady = NV_TRUE; + + return NV_OK; +} + +void +RmFreeX86EmuState(OBJGPU *pGpu) +{ + int i; + struct x86emu_mem_seg *pseg; + + if (! x86emuReady || !NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) // not the primary GPU + return; + + portMemFree(x86emuStack); + x86emuStack = 0; + + for (i = 0; i < X86EMU_NUM_SEGS; ++i) + { + pseg = x86emu_mem_map + i; + switch (i) + { + case X86EMU_SEG_ROMLEY_VGA: + case X86EMU_SEG_VGA: + case X86EMU_SEG_ROM: + case X86EMU_SEG_ROM_EXPANSION: + case X86EMU_SEG_ROM_MOTHERBOARD_BIOS: + case X86EMU_SEG_BIOS_DATA: + if (pseg->vaddr != 0) + os_unmap_kernel_space(pseg->vaddr, pseg->end - pseg->start + 1); + } + pseg->vaddr = 0; + } + + x86emuReady = NV_FALSE; +} + +NV_STATUS +nv_vbios_call( + OBJGPU *pGpu, + NvU32 *eax, + NvU32 *ebx) +{ + NvU16 seg; + NvU16 off; + struct x86emu_mem_seg *pseg; + + if (!NV_PRIMARY_VGA(NV_GET_NV_STATE(pGpu))) + return NV_ERR_GENERIC; + + seg = get_int_seg(0x10); + off = get_int_off(0x10); + + pseg = &x86emu_mem_map[X86EMU_SEG_VGA]; + if (seg < (pseg->start >> 4)) + { + pseg = &x86emu_mem_map[X86EMU_SEG_ROMLEY_VGA]; + if (seg < (pseg->start >> 4)) + { + NV_PRINTF(LEVEL_ERROR, + "cannot call the VBIOS. INT10 vector not in ROM: %04x:%04x\n", + seg, off); + return NV_ERR_GENERIC; + } + else if (pseg->vaddr == NULL) + { + pseg->vaddr = os_map_kernel_space(pseg->start, + (pseg->end - pseg->start + 1), + NV_MEMORY_CACHED); + if (pseg->vaddr == NULL) + { + NV_PRINTF(LEVEL_ERROR, "x86emu can't map phys addr 0x%05x\n", + pseg->start); + return NV_ERR_GENERIC; + } + } + } + + // Reset the CPU + portMemSet(&M, 0, sizeof(M)); + + M.x86.R_SS = X86EMU_STACK_ADDR >> 4; + M.x86.R_ESP = X86EMU_STACK_SIZE; + M.x86.R_CS = seg; + M.x86.R_EIP = off; + M.x86.R_EFLG = X86EMU_DFLT_FLAGS; + M.x86.R_EAX = *eax; + M.x86.R_EBX = *ebx; + M.x86.R_ECX = 0; + M.x86.R_EDX = 0; + M.x86.R_ES = X86EMU_BUF_ADDR >> 4; + + X86EMU_trace_on(); + + // Map ES:EDI to buffer. Used by vesa intr 4f15 - read EDID + pseg = &x86emu_mem_map[X86EMU_SEG_EDID_BUFFER]; + pseg->vaddr = NULL; + + // Prepare the code for IRET to jump to + Mem_wb((X86EMU_IRET_SEG << 4) + X86EMU_IRET_OFF, OP_HLT); + + pushw(X86EMU_DFLT_FLAGS); + pushw(X86EMU_IRET_SEG); + pushw(X86EMU_IRET_OFF); + + // Run the emulator + X86EMU_exec(); + + *eax = M.x86.R_EAX; + *ebx = M.x86.R_EBX; + + return NV_OK; +} diff --git a/src/nvidia/arch/nvalloc/unix/x86emu/debug.c b/src/nvidia/arch/nvalloc/unix/x86emu/debug.c new file mode 100644 index 0000000000..ccf8be74e2 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/x86emu/debug.c @@ -0,0 +1,547 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to handle debugging of the +* emulator. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" +#ifndef NO_SYS_HEADERS +#include +#include +#endif + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef X86EMU_DEBUG + +static void print_encoded_bytes (u16 s, u16 o); +static void print_decoded_instruction (void); +static int parse_line (char *s, int *ps, int *n); + +/* should look something like debug's output. */ +void X86EMU_trace_regs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_regs(); + } + if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", M.x86.saved_cs, + M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); + } +} + +void X86EMU_trace_xregs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_xregs(); + } +} + +void x86emu_just_disassemble (void) +{ + /* + * This routine called if the flag DEBUG_DISASSEMBLE is set kind + * of a hack! + */ + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", M.x86.saved_cs, + M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); +} + +static void disassemble_forward (u16 seg, u16 off, int n) +{ + X86EMU_sysEnv tregs; + int i; + u8 op1; + /* + * hack, hack, hack. What we do is use the exact machinery set up + * for execution, except that now there is an additional state + * flag associated with the "execution", and we are using a copy + * of the register struct. All the major opcodes, once fully + * decoded, have the following two steps: TRACE_REGS(r,m); + * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to + * the preprocessor. The TRACE_REGS macro expands to: + * + * if (debug&DEBUG_DISASSEMBLE) + * {just_disassemble(); goto EndOfInstruction;} + * if (debug&DEBUG_TRACE) trace_regs(r,m); + * + * ...... and at the last line of the routine. + * + * EndOfInstruction: end_instr(); + * + * Up to the point where TRACE_REG is expanded, NO modifications + * are done to any register EXCEPT the IP register, for fetch and + * decoding purposes. + * + * This was done for an entirely different reason, but makes a + * nice way to get the system to help debug codes. + */ + tregs = M; + tregs.x86.R_IP = off; + tregs.x86.R_CS = seg; + + /* reset the decoding buffers */ + tregs.x86.enc_str_pos = 0; + tregs.x86.enc_pos = 0; + + /* turn on the "disassemble only, no execute" flag */ + tregs.x86.debug |= DEBUG_DISASSEMBLE_F; + + /* DUMP NEXT n instructions to screen in straight_line fashion */ + /* + * This looks like the regular instruction fetch stream, except + * that when this occurs, each fetched opcode, upon seeing the + * DEBUG_DISASSEMBLE flag set, exits immediately after decoding + * the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!! + * Note the use of a copy of the register structure... + */ + for (i=0; i 256) return; + seg = fetch_data_word_abs(0,iv*4); + off = fetch_data_word_abs(0,iv*4+2); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "%04x:%04x ", seg, off); +} + +void X86EMU_dump_memory (u16 seg, u16 off, u32 amt) +{ + u32 start = off & 0xfffffff0; + u32 end = (off+16) & 0xfffffff0; + u32 i; + + while (end <= off + amt) { + NV_PRINTF(LEVEL_INFO, "%04x:%04x ", seg, start); + for (i=start; i< off; i++) + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, " "); + for ( ; i< end; i++) + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "%02x ", fetch_data_byte_abs(seg, i)); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); + start = end; + end = start + 16; + } +} + +void x86emu_single_step (void) +{ + int ps[10]; + int ntok; + int cmd; + int done; + int segment; + int offset; + static int breakpoint; + static int noDecode = 1; + + if (DEBUG_BREAK()) { + if (M.x86.saved_ip != breakpoint) { + return; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + M.x86.debug |= DEBUG_TRACE_F; + M.x86.debug &= ~DEBUG_BREAK_F; + print_decoded_instruction (); + X86EMU_trace_regs(); + } + } + done=0; + offset = M.x86.saved_ip; + while (!done) { + NV_PRINTF(LEVEL_INFO, "-"); + + /* + * Set _X86EMU_env.x86.debug_cmd from a kernel debugger to a command to + * control the emulator debugger + */ + if (M.x86.debug_cmd[0] == '\0') + { + DBG_BREAKPOINT(); + } + + cmd = parse_line(M.x86.debug_cmd, ps, &ntok); + switch(cmd) { + case 'u': + disassemble_forward(M.x86.saved_cs,(u16)offset,10); + break; + case 'd': + if (ntok == 2) { + segment = M.x86.saved_cs; + offset = ps[1]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else if (ntok == 3) { + segment = ps[1]; + offset = ps[2]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else { + segment = M.x86.saved_cs; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } + break; + case 'c': + M.x86.debug ^= DEBUG_TRACECALL_F; + break; + case 's': + M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; + break; + case 'r': + X86EMU_trace_regs(); + break; + case 'x': + X86EMU_trace_xregs(); + break; + case 'g': + if (ntok == 2) { + breakpoint = ps[1]; + if (noDecode) { + M.x86.debug |= DEBUG_DECODE_NOPRINT_F; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + } + M.x86.debug &= ~DEBUG_TRACE_F; + M.x86.debug |= DEBUG_BREAK_F; + done = 1; + } + break; + case 'q': + M.x86.debug |= DEBUG_EXIT; + return; + case 'P': + noDecode = (noDecode)?0:1; + NV_PRINTF(LEVEL_INFO, "Toggled decoding to %s\n", + (noDecode) ? "FALSE" : "TRUE"); + break; + case 'a': + X86EMU_trace_off(); + /* fall thru */ + case 't': + case 0: + done = 1; + break; + } + portMemSet(&M.x86.debug_cmd, 0, sizeof(M.x86.debug_cmd)); + } +} + +int X86EMU_trace_on(void) +{ + return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F; +} + +int X86EMU_trace_off(void) +{ + return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); +} + +static void parse_hex (char *s, int *pval) +{ + unsigned int val = 0; + unsigned char c; + + if (s[0] == '0' && s[1] == 'x') + s += 2; + + while ((c = *(s++))) + { + if (c >= '0' && c <= '9') + { + val <<= 4; + val |= c - '0'; + continue; + } + else if (c >= 'a' && c <= 'f') + { + val <<= 4; + val |= c - 'a'; + continue; + } + else if (c >= 'A' && c <= 'F') + { + val <<= 4; + val |= c - 'A'; + continue; + } + break; + } + + *pval = val; +} + +static int parse_line (char *s, int *ps, int *n) +{ + int cmd; + + *n = 0; + while(*s == ' ' || *s == '\t') s++; + ps[*n] = *s; + switch (*s) { + case '\n': + *n += 1; + return 0; + default: + cmd = *s; + *n += 1; + } + + while (1) + { + while (*s != ' ' && *s != '\t' && *s != '\n' && *s != '\0') + s++; + + if (*s == '\n' || *s == '\0') + return cmd; + + while(*s == ' ' || *s == '\t') + s++; + + parse_hex(s, &ps[*n]); + *n += 1; + } +} + +void x86emu_dump_regs (void) +{ + NV_PRINTF(LEVEL_INFO, "\tAX=%04x ", M.x86.R_AX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "BX=%04x ", M.x86.R_BX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CX=%04x ", M.x86.R_CX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DX=%04x ", M.x86.R_DX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SP=%04x ", M.x86.R_SP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "BP=%04x ", M.x86.R_BP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SI=%04x ", M.x86.R_SI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI=%04x\n", M.x86.R_DI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tDS=%04x ", M.x86.R_DS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ES=%04x ", M.x86.R_ES); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SS=%04x ", M.x86.R_SS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CS=%04x ", M.x86.R_CS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "IP=%04x ", M.x86.R_IP); + if (ACCESS_FLAG(F_OF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "OV "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NV "); + } + if (ACCESS_FLAG(F_DF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DN "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "UP "); + } + if (ACCESS_FLAG(F_IF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EI "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI "); + } + if (ACCESS_FLAG(F_SF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NG "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PL "); + } + if (ACCESS_FLAG(F_ZF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ZR "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NZ "); + } + if (ACCESS_FLAG(F_AF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "AC "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NA "); + } + if (ACCESS_FLAG(F_PF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PE "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PO "); + } + if (ACCESS_FLAG(F_CF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CY "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NC "); + } + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); +} + +void x86emu_dump_xregs (void) +{ + NV_PRINTF(LEVEL_INFO, "\tEAX=%08x ", M.x86.R_EAX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EBX=%08x ", M.x86.R_EBX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ECX=%08x ", M.x86.R_ECX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EDX=%08x \n", M.x86.R_EDX); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tESP=%08x ", M.x86.R_ESP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EBP=%08x ", M.x86.R_EBP); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ESI=%08x ", M.x86.R_ESI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EDI=%08x\n", M.x86.R_EDI); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\tDS=%04x ", M.x86.R_DS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ES=%04x ", M.x86.R_ES); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SS=%04x ", M.x86.R_SS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CS=%04x ", M.x86.R_CS); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EIP=%08x\n\t", M.x86.R_EIP); + if (ACCESS_FLAG(F_OF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "OV "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NV "); + } + if (ACCESS_FLAG(F_DF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DN "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "UP "); + } + if (ACCESS_FLAG(F_IF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "EI "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "DI "); + } + if (ACCESS_FLAG(F_SF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NG "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PL "); + } + if (ACCESS_FLAG(F_ZF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "ZR "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NZ "); + } + if (ACCESS_FLAG(F_AF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "AC "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NA "); + } + if (ACCESS_FLAG(F_PF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PE "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "PO "); + } + if (ACCESS_FLAG(F_CF)) { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "CY "); + } else { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "NC "); + } + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "\n"); +} + +#else + +void x86emu_dump_regs (void) +{ +} + +void x86emu_dump_xregs (void) +{ +} + +int X86EMU_trace_on(void) +{ + return 0; +} + +int X86EMU_trace_off(void) +{ + return 0; +} + +#endif /* X86EMU_DEBUG */ + diff --git a/src/nvidia/arch/nvalloc/unix/x86emu/decode.c b/src/nvidia/arch/nvalloc/unix/x86emu/decode.c new file mode 100644 index 0000000000..a683ce45e7 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/x86emu/decode.c @@ -0,0 +1,1094 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* instruction decoding and accessess of immediate data via IP. etc. +* +****************************************************************************/ + + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Handles any pending asychronous interrupts. +****************************************************************************/ +static void x86emu_intr_handle(void) +{ + u8 intno; + + if (M.x86.intr & INTR_SYNCH) { + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } + } +} + +/**************************************************************************** +PARAMETERS: +intrnum - Interrupt number to raise + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. +****************************************************************************/ +void x86emu_intr_raise( + u8 intrnum) +{ + M.x86.intno = intrnum; + M.x86.intr |= INTR_SYNCH; +} + +/**************************************************************************** +REMARKS: +Main execution loop for the emulator. We return from here when the system +halts, which is normally caused by a stack fault when we return from the +original real mode call. +****************************************************************************/ +void X86EMU_exec(void) +{ + u8 op1; + + M.x86.intr = 0; + DB(x86emu_end_instr();) + + for (;;) { +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { +DB( if (M.x86.R_SP != 0) { + NV_PRINTF(LEVEL_INFO, "halted\n"); + X86EMU_trace_regs(); + } + else { + if (M.x86.debug) + NV_PRINTF(LEVEL_INFO, + "Service completed successfully\n"); + }) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + if (M.x86.debug & DEBUG_EXIT) { + M.x86.debug &= ~DEBUG_EXIT; + return; + } + } +} + +/**************************************************************************** +REMARKS: +Halts the system by setting the halted system flag. +****************************************************************************/ +void X86EMU_halt_sys(void) +{ + M.x86.intr |= INTR_HALTED; +} + +/**************************************************************************** +PARAMETERS: +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +void fetch_decode_modrm( + int *mod, + int *regh, + int *regl) +{ + int fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + *mod = (fetched >> 6) & 0x03; + *regh = (fetched >> 3) & 0x07; + *regl = (fetched >> 0) & 0x07; +} + +/**************************************************************************** +RETURNS: +Immediate byte value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +u8 fetch_byte_imm(void) +{ + u8 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate word value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u16 fetch_word_imm(void) +{ + u16 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 2; + INC_DECODED_INST_LEN(2); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate lone value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u32 fetch_long_imm(void) +{ + u32 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 4; + INC_DECODED_INST_LEN(4); + return fetched; +} + +/**************************************************************************** +RETURNS: +Value of the default data segment + +REMARKS: +Inline function that returns the default data segment for the current +instruction. + +On the x86 processor, the default segment is not always DS if there is +no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to +addresses relative to SS (ie: on the stack). So, at the minimum, all +decodings of addressing modes would have to set/clear a bit describing +whether the access is relative to DS or SS. That is the function of the +cpu-state-varible M.x86.mode. There are several potential states: + + repe prefix seen (handled elsewhere) + repne prefix seen (ditto) + + cs segment override + ds segment override + es segment override + fs segment override + gs segment override + ss segment override + + ds/ss select (in absense of override) + +Each of the above 7 items are handled with a bit in the mode field. +****************************************************************************/ +_INLINE u32 get_data_segment(void) +{ +#define GET_SEGMENT(segment) + switch (M.x86.mode & SYSMODE_SEGMASK) { + case 0: /* default case: use ds register */ + case SYSMODE_SEGOVR_DS: + case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; + case SYSMODE_SEGOVR_CS: + case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: + return M.x86.R_CS; + case SYSMODE_SEGOVR_ES: + case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: + return M.x86.R_ES; + case SYSMODE_SEGOVR_FS: + case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: + return M.x86.R_FS; + case SYSMODE_SEGOVR_GS: + case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: + return M.x86.R_GS; + case SYSMODE_SEGOVR_SS: + case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: + return M.x86.R_SS; + default: +#ifdef X86EMU_DEBUG + NV_PRINTF(LEVEL_INFO, + "error: should not happen: multiple overrides.\n"); +#endif + HALT_SYS(); + return 0; + } +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdb)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdw)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long( + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdl)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdb)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdw)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long_abs( + uint segment, + uint offset) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdl)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte( + uint offset, + u8 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrb)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word( + uint offset, + u16 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrw)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long( + uint offset, + u32 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrl)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a byte value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte_abs( + uint segment, + uint offset, + u8 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrb)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word_abs( + uint segment, + uint offset, + u16 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrw)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long_abs( + uint segment, + uint offset, + u32 val) +{ +#ifdef X86EMU_DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrl)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for byte operands. Also enables the decoding of instructions. +****************************************************************************/ +u8* decode_rm_byte_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AL"); + return &M.x86.R_AL; + case 1: + DECODE_PRINTF("CL"); + return &M.x86.R_CL; + case 2: + DECODE_PRINTF("DL"); + return &M.x86.R_DL; + case 3: + DECODE_PRINTF("BL"); + return &M.x86.R_BL; + case 4: + DECODE_PRINTF("AH"); + return &M.x86.R_AH; + case 5: + DECODE_PRINTF("CH"); + return &M.x86.R_CH; + case 6: + DECODE_PRINTF("DH"); + return &M.x86.R_DH; + case 7: + DECODE_PRINTF("BH"); + return &M.x86.R_BH; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_word_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AX"); + return &M.x86.R_AX; + case 1: + DECODE_PRINTF("CX"); + return &M.x86.R_CX; + case 2: + DECODE_PRINTF("DX"); + return &M.x86.R_DX; + case 3: + DECODE_PRINTF("BX"); + return &M.x86.R_BX; + case 4: + DECODE_PRINTF("SP"); + return &M.x86.R_SP; + case 5: + DECODE_PRINTF("BP"); + return &M.x86.R_BP; + case 6: + DECODE_PRINTF("SI"); + return &M.x86.R_SI; + case 7: + DECODE_PRINTF("DI"); + return &M.x86.R_DI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for dword operands. Also enables the decoding of instructions. +****************************************************************************/ +u32* decode_rm_long_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; + case 1: + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; + case 2: + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; + case 3: + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; + case 4: + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; + case 5: + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; + case 6: + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; + case 7: + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands, modified from above for the weirdo +special case of segreg operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_seg_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("ES"); + return &M.x86.R_ES; + case 1: + DECODE_PRINTF("CS"); + return &M.x86.R_CS; + case 2: + DECODE_PRINTF("SS"); + return &M.x86.R_SS; + case 3: + DECODE_PRINTF("DS"); + return &M.x86.R_DS; + case 4: + DECODE_PRINTF("FS"); + return &M.x86.R_FS; + case 5: + DECODE_PRINTF("GS"); + return &M.x86.R_GS; + case 6: + case 7: + DECODE_PRINTF("ILLEGAL SEGREG"); + break; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/* + * + * return offset from the SIB Byte + */ +u32 decode_sib_address(int sib, int mod) +{ + u32 base = 0, i = 0, scale = 1; + + switch(sib & 0x07) { + case 0: + DECODE_PRINTF("[EAX]"); + base = M.x86.R_EAX; + break; + case 1: + DECODE_PRINTF("[ECX]"); + base = M.x86.R_ECX; + break; + case 2: + DECODE_PRINTF("[EDX]"); + base = M.x86.R_EDX; + break; + case 3: + DECODE_PRINTF("[EBX]"); + base = M.x86.R_EBX; + break; + case 4: + DECODE_PRINTF("[ESP]"); + base = M.x86.R_ESP; + M.x86.mode |= SYSMODE_SEG_DS_SS; + break; + case 5: + if (mod == 0) { + base = fetch_long_imm(); + DECODE_PRINTF2("%08x", base); + } else { + DECODE_PRINTF("[EBP]"); + base = M.x86.R_ESP; + M.x86.mode |= SYSMODE_SEG_DS_SS; + } + break; + case 6: + DECODE_PRINTF("[ESI]"); + base = M.x86.R_ESI; + break; + case 7: + DECODE_PRINTF("[EDI]"); + base = M.x86.R_EDI; + break; + } + switch ((sib >> 3) & 0x07) { + case 0: + DECODE_PRINTF("[EAX"); + i = M.x86.R_EAX; + break; + case 1: + DECODE_PRINTF("[ECX"); + i = M.x86.R_ECX; + break; + case 2: + DECODE_PRINTF("[EDX"); + i = M.x86.R_EDX; + break; + case 3: + DECODE_PRINTF("[EBX"); + i = M.x86.R_EBX; + break; + case 4: + i = 0; + break; + case 5: + DECODE_PRINTF("[EBP"); + i = M.x86.R_EBP; + break; + case 6: + DECODE_PRINTF("[ESI"); + i = M.x86.R_ESI; + break; + case 7: + DECODE_PRINTF("[EDI"); + i = M.x86.R_EDI; + break; + } + scale = 1 << ((sib >> 6) & 0x03); + if (((sib >> 3) & 0x07) != 4) { + if (scale == 1) { + DECODE_PRINTF("]"); + } else { + DECODE_PRINTF2("*%d]", scale); + } + } + return base + (i * scale); +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=00 addressing. Also enables the +decoding of instructions. + +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). +****************************************************************************/ +u32 decode_rm00_address( + int rm) +{ + u32 offset; + int sib; + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); + return M.x86.R_EBX; + case 4: + sib = fetch_byte_imm(); + return decode_sib_address(sib, 0); + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; + case 1: + DECODE_PRINTF("[BX+DI]"); + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } + HALT_SYS(); + } + return 0; +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=01 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +u32 decode_rm01_address( + int rm) +{ + int displacement = 0; + int sib; + + /* Fetch disp8 if no SIB byte */ + if (!((M.x86.mode & SYSMODE_PREFIX_ADDR) && (rm == 4))) + displacement = (s8)fetch_byte_imm(); + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + sib = fetch_byte_imm(); + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("%d", displacement); + return decode_sib_address(sib, 1) + displacement; + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + HALT_SYS(); + } + return 0; /* SHOULD NOT HAPPEN */ +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=10 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +u32 decode_rm10_address( + int rm) +{ + u32 displacement = 0; + int sib; + + /* Fetch disp16 if 16-bit addr mode */ + if (!(M.x86.mode & SYSMODE_PREFIX_ADDR)) + displacement = (u16)fetch_word_imm(); + else { + /* Fetch disp32 if no SIB byte */ + if (rm != 4) + displacement = (u32)fetch_long_imm(); + } + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%08x[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%08x[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%08x[EDX]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%08x[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + sib = fetch_byte_imm(); + displacement = (u32)fetch_long_imm(); + DECODE_PRINTF2("%08x", displacement); + return decode_sib_address(sib, 2) + displacement; + break; + case 5: + DECODE_PRINTF2("%08x[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%08x[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%08x[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + HALT_SYS(); + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%04x[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%04x[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%04x[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%04x[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%04x[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%04x[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%04x[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%04x[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + HALT_SYS(); + } + return 0; + /*NOTREACHED */ +} diff --git a/src/nvidia/arch/nvalloc/unix/x86emu/fpu.c b/src/nvidia/arch/nvalloc/unix/x86emu/fpu.c new file mode 100644 index 0000000000..0a21c9981e --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/x86emu/fpu.c @@ -0,0 +1,965 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the decoding and +* emulation of the FPU instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/* opcode=0xd8 */ +void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ESC D8\n"); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_d9_tab[] = { + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", +}; + +static char *x86emu_fpu_op_d9_tab1[] = { + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + + "FNOP", "ESC_D9", "ESC_D9", "ESC_D9", + "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", + + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + + "FCHS", "FABS", "ESC_D9", "ESC_D9", + "FTST", "FXAM", "ESC_D9", "ESC_D9", + + "FLD1", "FLDL2T", "FLDL2E", "FLDPI", + "FLDLG2", "FLDLN2", "FLDZ", "ESC_D9", + + "F2XM1", "FYL2X", "FPTAN", "FPATAN", + "FXTRACT", "ESC_D9", "FDECSTP", "FINCSTP", + + "FPREM", "FYL2XP1", "FSQRT", "ESC_D9", + "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xd9 */ +void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); + } else { + DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + if (rh < 4) { + DECODE_PRINTF2("ST(%d)\n", stkelem); + } else { + DECODE_PRINTF("\n"); + } + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); + break; + case 1: + x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); + break; + case 2: + switch (rl) { + case 0: + x86emu_fpu_R_nop(); + break; + default: + x86emu_fpu_illegal(); + break; + } + case 3: + x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); + break; + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); + break; + default: + /* 2,3,6,7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 5: + switch (rl) { + case 0: + x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); + break; + default: + /* 7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 6: + switch (rl) { + case 0: + x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_R_decstp(); + break; + case 7: + x86emu_fpu_R_incstp(); + break; + } + break; + + case 7: + switch (rl) { + case 0: + x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); + break; + case 6: + case 7: + default: + x86emu_fpu_illegal(); + break; + } + break; + + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); + break; + case 4: + x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); + break; + } + } + } +#else + (void)destoffset; + (void)stkelem; +#endif /* X86EMU_FPU_PRESENT */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +char *x86emu_fpu_op_da_tab[] = { + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xda */ +void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + x86emu_fpu_illegal(); + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); + break; + case 2: + x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); + break; + case 5: + x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); + break; + case 6: + x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); + break; + case 7: + x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +char *x86emu_fpu_op_db_tab[] = { + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdb */ +void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); + } else if (rh == 4) { /* === 11 10 0 nnn */ + switch (rl) { + case 0: + DECODE_PRINTF("FENI\n"); + break; + case 1: + DECODE_PRINTF("FDISI\n"); + break; + case 2: + DECODE_PRINTF("FCLEX\n"); + break; + case 3: + DECODE_PRINTF("FINIT\n"); + break; + } + } else { + DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); + } +#endif /* X86EMU_DEBUG */ + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + break; + case 1: + destoffset = decode_rm01_address(rl); + break; + case 2: + destoffset = decode_rm10_address(rl); + break; + case 3: /* register to register */ + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_feni(); + break; + case 1: + x86emu_fpu_R_fdisi(); + break; + case 2: + x86emu_fpu_R_fclex(); + break; + case 3: + x86emu_fpu_R_finit(); + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_illegal(); + break; + case 5: + x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); + break; + case 6: + x86emu_fpu_illegal(); + break; + case 7: + x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); + break; + } + } +#else + (void)destoffset; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG +char *x86emu_fpu_op_dc_tab[] = { + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", + "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", +}; +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdc */ +void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); + break; + case 2: + x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); + break; + case 5: + x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); + break; + case 6: + x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); + break; + case 7: + x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_dd_tab[] = { + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdd */ +void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_de_tab[] = +{ + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FADDP\t", "FMULP\t", "FCOMP\t", "FCOMPP\t", + "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xde */ +void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + if (stkelem == 1) + x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); + else + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); + break; + case 2: + x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef X86EMU_DEBUG + +static char *x86emu_fpu_op_df_tab[] = { + /* mod == 00 */ + "FILD\tWORD PTR ", "ESC_DF\t39\n", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 01 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 10 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 11 */ + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," +}; + +#endif /* X86EMU_DEBUG */ + +/* opcode=0xdf */ +void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset = 0; + u8 stkelem = 0; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d)\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); + break; + case 5: + x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); + break; + case 6: + x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); + break; + case 7: + x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); + break; + } + } +#else + (void)destoffset; + (void)stkelem; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} diff --git a/src/nvidia/arch/nvalloc/unix/x86emu/ops.c b/src/nvidia/arch/nvalloc/unix/x86emu/ops.c new file mode 100644 index 0000000000..52b97b4f32 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/x86emu/ops.c @@ -0,0 +1,11761 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 processor instructions. +* +* There are approximately 250 subroutines in here, which correspond +* to the 256 byte-"opcodes" found on the 8086. The table which +* dispatches this is found in the files optab.[ch]. +* +* Each opcode proc has a comment preceeding it which gives it's table +* address. Several opcodes are missing (undefined) in the table. +* +* Each proc includes information for decoding (DECODE_PRINTF and +* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc +* functions (START_OF_INSTR, END_OF_INSTR). +* +* Many of the procedures are *VERY* similar in coding. This has +* allowed for a very large amount of code to be generated in a fairly +* short amount of time (i.e. cut, paste, and modify). The result is +* that much of the code below could have been folded into subroutines +* for a large reduction in size of this file. The downside would be +* that there would be a penalty in execution speed. The file could +* also have been *MUCH* larger by inlining certain functions which +* were called. This could have resulted even faster execution. The +* prime directive I used to decide whether to inline the code or to +* modularize it, was basically: 1) no unnecessary subroutine calls, +* 2) no routines more than about 200 lines in size, and 3) modularize +* any code that I might not get right the first time. The fetch_* +* subroutines fall into the latter category. The The decode_* fall +* into the second category. The coding of the "switch(mod){ .... }" +* in many of the subroutines below falls into the first category. +* Especially, the coding of {add,and,or,sub,...}_{byte,word} +* subroutines are an especially glaring case of the third guideline. +* Since so much of the code is cloned from other modules (compare +* opcode #00 to opcode #01), making the basic operations subroutine +* calls is especially important; otherwise mistakes in coding an +* "add" would represent a nightmare in maintenance. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +static void x86emuOp_illegal_op( + u8 op1) +{ + START_OF_INSTR(); + if (M.x86.R_SP != 0) { + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + DB( NV_PRINTF(LEVEL_INFO, "%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP - 1, op1);) + HALT_SYS(); + } + else { + /* If we get here, it means the stack pointer is back to zero + * so we are just returning from an emulator service call + * so therte is no need to display an error message. We trap + * the emulator with an 0xF1 opcode to finish the service + * call. + */ + X86EMU_halt_sys(); + } + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x00 +****************************************************************************/ +static void x86emuOp_add_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x01 +****************************************************************************/ +static void x86emuOp_add_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x02 +****************************************************************************/ +static void x86emuOp_add_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x03 +****************************************************************************/ +static void x86emuOp_add_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x04 +****************************************************************************/ +static void x86emuOp_add_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = add_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x05 +****************************************************************************/ +static void x86emuOp_add_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADD\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADD\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = add_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = add_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x06 +****************************************************************************/ +static void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tES\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_ES); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x07 +****************************************************************************/ +static void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tES\n"); + TRACE_AND_STEP(); + M.x86.R_ES = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x08 +****************************************************************************/ +static void x86emuOp_or_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x09 +****************************************************************************/ +static void x86emuOp_or_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0a +****************************************************************************/ +static void x86emuOp_or_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0b +****************************************************************************/ +static void x86emuOp_or_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0c +****************************************************************************/ +static void x86emuOp_or_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = or_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0d +****************************************************************************/ +static void x86emuOp_or_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("OR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = or_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = or_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0e +****************************************************************************/ +static void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tCS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f. Escape for two-byte opcode (286 or better) +****************************************************************************/ +static void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + (*x86emu_optab2[op2])(op2); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x10 +****************************************************************************/ +static void x86emuOp_adc_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x11 +****************************************************************************/ +static void x86emuOp_adc_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x12 +****************************************************************************/ +static void x86emuOp_adc_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x13 +****************************************************************************/ +static void x86emuOp_adc_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x14 +****************************************************************************/ +static void x86emuOp_adc_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = adc_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x15 +****************************************************************************/ +static void x86emuOp_adc_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADC\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADC\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = adc_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = adc_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x16 +****************************************************************************/ +static void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tSS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_SS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x17 +****************************************************************************/ +static void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tSS\n"); + TRACE_AND_STEP(); + M.x86.R_SS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x18 +****************************************************************************/ +static void x86emuOp_sbb_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x19 +****************************************************************************/ +static void x86emuOp_sbb_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1a +****************************************************************************/ +static void x86emuOp_sbb_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1b +****************************************************************************/ +static void x86emuOp_sbb_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1c +****************************************************************************/ +static void x86emuOp_sbb_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sbb_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1d +****************************************************************************/ +static void x86emuOp_sbb_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SBB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SBB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sbb_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sbb_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1e +****************************************************************************/ +static void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tDS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_DS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1f +****************************************************************************/ +static void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tDS\n"); + TRACE_AND_STEP(); + M.x86.R_DS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x20 +****************************************************************************/ +static void x86emuOp_and_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x21 +****************************************************************************/ +static void x86emuOp_and_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x22 +****************************************************************************/ +static void x86emuOp_and_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x23 +****************************************************************************/ +static void x86emuOp_and_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + break; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + break; + } + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x24 +****************************************************************************/ +static void x86emuOp_and_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = and_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x25 +****************************************************************************/ +static void x86emuOp_and_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("AND\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("AND\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = and_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = and_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x26 +****************************************************************************/ +static void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ES:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_ES; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x27 +****************************************************************************/ +static void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAA\n"); + TRACE_AND_STEP(); + M.x86.R_AL = daa_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x28 +****************************************************************************/ +static void x86emuOp_sub_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x29 +****************************************************************************/ +static void x86emuOp_sub_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2a +****************************************************************************/ +static void x86emuOp_sub_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2b +****************************************************************************/ +static void x86emuOp_sub_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2c +****************************************************************************/ +static void x86emuOp_sub_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sub_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2d +****************************************************************************/ +static void x86emuOp_sub_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SUB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SUB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sub_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sub_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2e +****************************************************************************/ +static void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("CS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_CS; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2f +****************************************************************************/ +static void x86emuOp_das(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAS\n"); + TRACE_AND_STEP(); + M.x86.R_AL = das_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x30 +****************************************************************************/ +static void x86emuOp_xor_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x31 +****************************************************************************/ +static void x86emuOp_xor_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x32 +****************************************************************************/ +static void x86emuOp_xor_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x33 +****************************************************************************/ +static void x86emuOp_xor_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x34 +****************************************************************************/ +static void x86emuOp_xor_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = xor_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x35 +****************************************************************************/ +static void x86emuOp_xor_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XOR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("XOR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = xor_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = xor_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x36 +****************************************************************************/ +static void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_SS; + /* no DECODE_CLEAR_SEGOVR ! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x37 +****************************************************************************/ +static void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAA\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aaa_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x38 +****************************************************************************/ +static void x86emuOp_cmp_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x39 +****************************************************************************/ +static void x86emuOp_cmp_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3a +****************************************************************************/ +static void x86emuOp_cmp_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3b +****************************************************************************/ +static void x86emuOp_cmp_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3c +****************************************************************************/ +static void x86emuOp_cmp_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + cmp_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3d +****************************************************************************/ +static void x86emuOp_cmp_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMP\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("CMP\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + cmp_long(M.x86.R_EAX, srcval); + } else { + cmp_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3e +****************************************************************************/ +static void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_DS; + /* NO DECODE_CLEAR_SEGOVR! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3f +****************************************************************************/ +static void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAS\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aas_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x40 +****************************************************************************/ +static void x86emuOp_inc_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEAX\n"); + } else { + DECODE_PRINTF("INC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = inc_long(M.x86.R_EAX); + } else { + M.x86.R_AX = inc_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x41 +****************************************************************************/ +static void x86emuOp_inc_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tECX\n"); + } else { + DECODE_PRINTF("INC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = inc_long(M.x86.R_ECX); + } else { + M.x86.R_CX = inc_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x42 +****************************************************************************/ +static void x86emuOp_inc_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDX\n"); + } else { + DECODE_PRINTF("INC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = inc_long(M.x86.R_EDX); + } else { + M.x86.R_DX = inc_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x43 +****************************************************************************/ +static void x86emuOp_inc_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBX\n"); + } else { + DECODE_PRINTF("INC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = inc_long(M.x86.R_EBX); + } else { + M.x86.R_BX = inc_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x44 +****************************************************************************/ +static void x86emuOp_inc_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESP\n"); + } else { + DECODE_PRINTF("INC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = inc_long(M.x86.R_ESP); + } else { + M.x86.R_SP = inc_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x45 +****************************************************************************/ +static void x86emuOp_inc_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBP\n"); + } else { + DECODE_PRINTF("INC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = inc_long(M.x86.R_EBP); + } else { + M.x86.R_BP = inc_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x46 +****************************************************************************/ +static void x86emuOp_inc_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESI\n"); + } else { + DECODE_PRINTF("INC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = inc_long(M.x86.R_ESI); + } else { + M.x86.R_SI = inc_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x47 +****************************************************************************/ +static void x86emuOp_inc_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDI\n"); + } else { + DECODE_PRINTF("INC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = inc_long(M.x86.R_EDI); + } else { + M.x86.R_DI = inc_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x48 +****************************************************************************/ +static void x86emuOp_dec_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEAX\n"); + } else { + DECODE_PRINTF("DEC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = dec_long(M.x86.R_EAX); + } else { + M.x86.R_AX = dec_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x49 +****************************************************************************/ +static void x86emuOp_dec_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tECX\n"); + } else { + DECODE_PRINTF("DEC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = dec_long(M.x86.R_ECX); + } else { + M.x86.R_CX = dec_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4a +****************************************************************************/ +static void x86emuOp_dec_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDX\n"); + } else { + DECODE_PRINTF("DEC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = dec_long(M.x86.R_EDX); + } else { + M.x86.R_DX = dec_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4b +****************************************************************************/ +static void x86emuOp_dec_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBX\n"); + } else { + DECODE_PRINTF("DEC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = dec_long(M.x86.R_EBX); + } else { + M.x86.R_BX = dec_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4c +****************************************************************************/ +static void x86emuOp_dec_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESP\n"); + } else { + DECODE_PRINTF("DEC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = dec_long(M.x86.R_ESP); + } else { + M.x86.R_SP = dec_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4d +****************************************************************************/ +static void x86emuOp_dec_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBP\n"); + } else { + DECODE_PRINTF("DEC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = dec_long(M.x86.R_EBP); + } else { + M.x86.R_BP = dec_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4e +****************************************************************************/ +static void x86emuOp_dec_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESI\n"); + } else { + DECODE_PRINTF("DEC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = dec_long(M.x86.R_ESI); + } else { + M.x86.R_SI = dec_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4f +****************************************************************************/ +static void x86emuOp_dec_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDI\n"); + } else { + DECODE_PRINTF("DEC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = dec_long(M.x86.R_EDI); + } else { + M.x86.R_DI = dec_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x50 +****************************************************************************/ +static void x86emuOp_push_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEAX\n"); + } else { + DECODE_PRINTF("PUSH\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EAX); + } else { + push_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x51 +****************************************************************************/ +static void x86emuOp_push_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tECX\n"); + } else { + DECODE_PRINTF("PUSH\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ECX); + } else { + push_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x52 +****************************************************************************/ +static void x86emuOp_push_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDX\n"); + } else { + DECODE_PRINTF("PUSH\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDX); + } else { + push_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x53 +****************************************************************************/ +static void x86emuOp_push_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBX\n"); + } else { + DECODE_PRINTF("PUSH\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBX); + } else { + push_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x54 +****************************************************************************/ +static void x86emuOp_push_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESP\n"); + } else { + DECODE_PRINTF("PUSH\tSP\n"); + } + TRACE_AND_STEP(); + /* Always push (E)SP, since we are emulating an i386 and above + * processor. This is necessary as some BIOS'es use this to check + * what type of processor is in the system. + */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESP); + } else { + push_word((u16)(M.x86.R_SP)); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x55 +****************************************************************************/ +static void x86emuOp_push_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBP\n"); + } else { + DECODE_PRINTF("PUSH\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBP); + } else { + push_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x56 +****************************************************************************/ +static void x86emuOp_push_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESI\n"); + } else { + DECODE_PRINTF("PUSH\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESI); + } else { + push_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x57 +****************************************************************************/ +static void x86emuOp_push_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDI\n"); + } else { + DECODE_PRINTF("PUSH\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDI); + } else { + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x58 +****************************************************************************/ +static void x86emuOp_pop_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEAX\n"); + } else { + DECODE_PRINTF("POP\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x59 +****************************************************************************/ +static void x86emuOp_pop_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tECX\n"); + } else { + DECODE_PRINTF("POP\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = pop_long(); + } else { + M.x86.R_CX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5a +****************************************************************************/ +static void x86emuOp_pop_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDX\n"); + } else { + DECODE_PRINTF("POP\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = pop_long(); + } else { + M.x86.R_DX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5b +****************************************************************************/ +static void x86emuOp_pop_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBX\n"); + } else { + DECODE_PRINTF("POP\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = pop_long(); + } else { + M.x86.R_BX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5c +****************************************************************************/ +static void x86emuOp_pop_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESP\n"); + } else { + DECODE_PRINTF("POP\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = pop_long(); + } else { + M.x86.R_SP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5d +****************************************************************************/ +static void x86emuOp_pop_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBP\n"); + } else { + DECODE_PRINTF("POP\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = pop_long(); + } else { + M.x86.R_BP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5e +****************************************************************************/ +static void x86emuOp_pop_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESI\n"); + } else { + DECODE_PRINTF("POP\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = pop_long(); + } else { + M.x86.R_SI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5f +****************************************************************************/ +static void x86emuOp_pop_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDI\n"); + } else { + DECODE_PRINTF("POP\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + } else { + M.x86.R_DI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x60 +****************************************************************************/ +static void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHAD\n"); + } else { + DECODE_PRINTF("PUSHA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); + } else { + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x61 +****************************************************************************/ +static void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPAD\n"); + } else { + DECODE_PRINTF("POPA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ + +/**************************************************************************** +REMARKS: +Handles opcode 0x64 +****************************************************************************/ +static void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("FS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_FS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x65 +****************************************************************************/ +static void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("GS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_GS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x66 - prefix for 32-bit register +****************************************************************************/ +static void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DATA:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_DATA; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x67 - prefix for 32-bit address +****************************************************************************/ +static void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ADDR:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_ADDR; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x68 +****************************************************************************/ +static void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 imm; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + imm = fetch_long_imm(); + } else { + imm = fetch_word_imm(); + } + DECODE_PRINTF2("PUSH\t%x\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(imm); + } else { + push_word((u16)imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x69 +****************************************************************************/ +static void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6a +****************************************************************************/ +static void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 imm; + + START_OF_INSTR(); + imm = (s8)fetch_byte_imm(); + DECODE_PRINTF2("PUSH\t%d\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long((s32)imm); + } else { + push_word(imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6b +****************************************************************************/ +static void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + s8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6c +****************************************************************************/ +static void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INSB\n"); + ins(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6d +****************************************************************************/ +static void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INSD\n"); + ins(4); + } else { + DECODE_PRINTF("INSW\n"); + ins(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6e +****************************************************************************/ +static void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUTSB\n"); + outs(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6f +****************************************************************************/ +static void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUTSD\n"); + outs(4); + } else { + DECODE_PRINTF("OUTSW\n"); + outs(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x70 +****************************************************************************/ +static void x86emuOp_jump_near_O(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x71 +****************************************************************************/ +static void x86emuOp_jump_near_NO(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow is not set */ + START_OF_INSTR(); + DECODE_PRINTF("JNO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x72 +****************************************************************************/ +static void x86emuOp_jump_near_B(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x73 +****************************************************************************/ +static void x86emuOp_jump_near_NB(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x74 +****************************************************************************/ +static void x86emuOp_jump_near_Z(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x75 +****************************************************************************/ +static void x86emuOp_jump_near_NZ(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x76 +****************************************************************************/ +static void x86emuOp_jump_near_BE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set or if the zero + flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x77 +****************************************************************************/ +static void x86emuOp_jump_near_NBE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear and if the zero + flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x78 +****************************************************************************/ +static void x86emuOp_jump_near_S(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x79 +****************************************************************************/ +static void x86emuOp_jump_near_NS(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7a +****************************************************************************/ +static void x86emuOp_jump_near_P(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is set (even parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7b +****************************************************************************/ +static void x86emuOp_jump_near_NP(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is clear (odd parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JNP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7c +****************************************************************************/ +static void x86emuOp_jump_near_L(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if (sf ^ of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7d +****************************************************************************/ +static void x86emuOp_jump_near_NL(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JNL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + /* note: inverse of above, but using == instead of xor. */ + if (sf == of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7e +****************************************************************************/ +static void x86emuOp_jump_near_LE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag + or the zero flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf ^ of) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7f +****************************************************************************/ +static void x86emuOp_jump_near_NLE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag equal to overflow flag. + and the zero flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf == of) && !ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc80_byte_operation[])(u8 d, u8 s) = +{ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x80 +****************************************************************************/ +static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc81_word_operation[])(u16 d, u16 s) = +{ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ +}; + +static u32 (*opc81_long_operation[])(u32 d, u32 s) = +{ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x81 +****************************************************************************/ +static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* + * Know operation, decode the mod byte to find the addressing + * mode. + */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc82_byte_operation[])(u8 s, u8 d) = +{ + add_byte, /*00 */ + or_byte, /*01 *//*YYY UNUSED ???? */ + adc_byte, /*02 */ + sbb_byte, /*03 */ + and_byte, /*04 *//*YYY UNUSED ???? */ + sub_byte, /*05 */ + xor_byte, /*06 *//*YYY UNUSED ???? */ + cmp_byte, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x82 +****************************************************************************/ +static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc83_word_operation[])(u16 s, u16 d) = +{ + add_word, /*00 */ + or_word, /*01 *//*YYY UNUSED ???? */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 *//*YYY UNUSED ???? */ + sub_word, /*05 */ + xor_word, /*06 *//*YYY UNUSED ???? */ + cmp_word, /*07 */ +}; + +static u32 (*opc83_long_operation[])(u32 s, u32 d) = +{ + add_long, /*00 */ + or_long, /*01 *//*YYY UNUSED ???? */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 *//*YYY UNUSED ???? */ + sub_long, /*05 */ + xor_long, /*06 *//*YYY UNUSED ???? */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x83 +****************************************************************************/ +static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x84 +****************************************************************************/ +static void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x85 +****************************************************************************/ +static void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x86 +****************************************************************************/ +static void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + u8 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x87 +****************************************************************************/ +static void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x88 +****************************************************************************/ +static void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x89 +****************************************************************************/ +static void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u32 destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8a +****************************************************************************/ +static void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8b +****************************************************************************/ +static void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8c +****************************************************************************/ +static void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint destoffset; + u16 destval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8d +****************************************************************************/ +static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LEA\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + break; + case 3: /* register to register */ + /* undefined. Do nothing. */ + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8e +****************************************************************************/ +static void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint srcoffset; + u16 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + /* + * Clean up, and reset all the R_xSP pointers to the correct + * locations. This is about 3x too much overhead (doing all the + * segreg ptrs when only one is needed, but this instruction + * *cannot* be that common, and this isn't too much work anyway. + */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8f +****************************************************************************/ +static void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("POP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x90 +****************************************************************************/ +static void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("NOP\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x91 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_CX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ECX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,CX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ECX; + M.x86.R_ECX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_CX; + M.x86.R_CX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x92 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDX; + M.x86.R_EDX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DX; + M.x86.R_DX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x93 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_BX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBX; + M.x86.R_EBX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BX; + M.x86.R_BX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x94 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_SP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESP; + M.x86.R_ESP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SP; + M.x86.R_SP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x95 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_BP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBP; + M.x86.R_EBP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BP; + M.x86.R_BP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x96 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_SI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESI; + M.x86.R_ESI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SI; + M.x86.R_SI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x97 +****************************************************************************/ +static void x86emuOp_xchg_word_AX_DI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDI; + M.x86.R_EDI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DI; + M.x86.R_DI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x98 +****************************************************************************/ +static void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CWDE\n"); + } else { + DECODE_PRINTF("CBW\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } + } else { + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x99 +****************************************************************************/ +static void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CDQ\n"); + } else { + DECODE_PRINTF("CWD\n"); + } + DECODE_PRINTF("CWD\n"); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } + } else { + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9a +****************************************************************************/ +static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 farseg, faroff; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + faroff = fetch_long_imm(); + farseg = fetch_word_imm(); + } else { + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); + } + DECODE_PRINTF2("%04x:", farseg); + DECODE_PRINTF2("%04x\n", faroff); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); + + /* XXX + * + * Hooked interrupt vectors calling into our "BIOS" will cause + * problems unless all intersegment stuff is checked for BIOS + * access. Check needed here. For moment, let it alone. + */ + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = farseg; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + } else { + push_word(M.x86.R_IP); + } + M.x86.R_EIP = faroff & 0xffff; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9b +****************************************************************************/ +static void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("WAIT"); + TRACE_AND_STEP(); + /* NADA. */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9c +****************************************************************************/ +static void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) +{ + u32 flags; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHFD\n"); + } else { + DECODE_PRINTF("PUSHF\n"); + } + TRACE_AND_STEP(); + + /* clear out *all* bits not representing flags, and turn on real bits */ + flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(flags); + } else { + push_word((u16)flags); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9d +****************************************************************************/ +static void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPFD\n"); + } else { + DECODE_PRINTF("POPF\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EFLG = pop_long(); + } else { + M.x86.R_FLG = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9e +****************************************************************************/ +static void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SAHF\n"); + TRACE_AND_STEP(); + /* clear the lower bits of the flag register */ + M.x86.R_FLG &= 0xffffff00; + /* or in the AH register into the flags register */ + M.x86.R_FLG |= M.x86.R_AH; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9f +****************************************************************************/ +static void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LAHF\n"); + TRACE_AND_STEP(); + M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff); + /*undocumented TC++ behavior??? Nope. It's documented, but + you have too look real hard to notice it. */ + M.x86.R_AH |= 0x2; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa0 +****************************************************************************/ +static void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]\n", offset); + TRACE_AND_STEP(); + M.x86.R_AL = fetch_data_byte(offset); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa1 +****************************************************************************/ +static void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + } else { + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(offset); + } else { + M.x86.R_AX = fetch_data_word(offset); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa2 +****************************************************************************/ +static void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x],AL\n", offset); + TRACE_AND_STEP(); + store_data_byte(offset, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa3 +****************************************************************************/ +static void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + } else { + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long(offset, M.x86.R_EAX); + } else { + store_data_word(offset, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa4 +****************************************************************************/ +static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 val; + u32 count; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("MOVS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa5 +****************************************************************************/ +static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val; + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa6 +****************************************************************************/ +static void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val1, val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("CMPS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa7 +****************************************************************************/ +static void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val1,val2; + int inc; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMPS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("CMPS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa8 +****************************************************************************/ +static void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + int imm; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%04x\n", imm); + TRACE_AND_STEP(); + test_byte(M.x86.R_AL, (u8)imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa9 +****************************************************************************/ +static void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + test_long(M.x86.R_EAX, srcval); + } else { + test_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaa +****************************************************************************/ +static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("STOS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xab +****************************************************************************/ +static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xac +****************************************************************************/ +static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("LODS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xad +****************************************************************************/ +static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xae +****************************************************************************/ +static void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("SCAS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaf +****************************************************************************/ +static void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 val; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb0 +****************************************************************************/ +static void x86emuOp_mov_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb1 +****************************************************************************/ +static void x86emuOp_mov_byte_CL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb2 +****************************************************************************/ +static void x86emuOp_mov_byte_DL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb3 +****************************************************************************/ +static void x86emuOp_mov_byte_BL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb4 +****************************************************************************/ +static void x86emuOp_mov_byte_AH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb5 +****************************************************************************/ +static void x86emuOp_mov_byte_CH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb6 +****************************************************************************/ +static void x86emuOp_mov_byte_DH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb7 +****************************************************************************/ +static void x86emuOp_mov_byte_BH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb8 +****************************************************************************/ +static void x86emuOp_mov_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = srcval; + } else { + M.x86.R_AX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb9 +****************************************************************************/ +static void x86emuOp_mov_word_CX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tECX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tCX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = srcval; + } else { + M.x86.R_CX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xba +****************************************************************************/ +static void x86emuOp_mov_word_DX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = srcval; + } else { + M.x86.R_DX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbb +****************************************************************************/ +static void x86emuOp_mov_word_BX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = srcval; + } else { + M.x86.R_BX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbc +****************************************************************************/ +static void x86emuOp_mov_word_SP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = srcval; + } else { + M.x86.R_SP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbd +****************************************************************************/ +static void x86emuOp_mov_word_BP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = srcval; + } else { + M.x86.R_BP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbe +****************************************************************************/ +static void x86emuOp_mov_word_SI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = srcval; + } else { + M.x86.R_SI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbf +****************************************************************************/ +static void x86emuOp_mov_word_DI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = srcval; + } else { + M.x86.R_DI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c0, d0, and d2. */ +static u8(*opcD0_byte_operation[])(u8 d, u8 s) = +{ + rol_byte, + ror_byte, + rcl_byte, + rcr_byte, + shl_byte, + shr_byte, + shl_byte, /* sal_byte === shl_byte by definition */ + sar_byte, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc0 +****************************************************************************/ +static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c1, d1, and d3. */ +static u16(*opcD1_word_operation[])(u16 s, u8 d) = +{ + rol_word, + ror_word, + rcl_word, + rcr_word, + shl_word, + shr_word, + shl_word, /* sal_byte === shl_byte by definition */ + sar_word, +}; + +/* used by opcodes c1, d1, and d3. */ +static u32 (*opcD1_long_operation[])(u32 s, u8 d) = +{ + rol_long, + ror_long, + rcl_long, + rcr_long, + shl_long, + shr_long, + shl_long, /* sal_byte === shl_byte by definition */ + sar_long, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc1 +****************************************************************************/ +static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc2 +****************************************************************************/ +static void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RET\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc3 +****************************************************************************/ +static void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RET\n"); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc4 +****************************************************************************/ +static void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LES\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc5 +****************************************************************************/ +static void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LDS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc6 +****************************************************************************/ +static void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc7 +****************************************************************************/ +static void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { + u16 *destreg; + u16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc8 +****************************************************************************/ +static void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) +{ + u16 local,frame_pointer; + u8 nesting; + int i; + + START_OF_INSTR(); + local = fetch_word_imm(); + nesting = fetch_byte_imm(); + DECODE_PRINTF2("ENTER %x\n", local); + DECODE_PRINTF2(",%x\n", nesting); + TRACE_AND_STEP(); + push_word(M.x86.R_BP); + frame_pointer = M.x86.R_SP; + if (nesting > 0) { + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } + M.x86.R_BP = frame_pointer; + M.x86.R_SP = (u16)(M.x86.R_SP - local); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc9 +****************************************************************************/ +static void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LEAVE\n"); + TRACE_AND_STEP(); + M.x86.R_SP = M.x86.R_BP; + M.x86.R_BP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xca +****************************************************************************/ +static void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RETF\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcb +****************************************************************************/ +static void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RETF\n"); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcc +****************************************************************************/ +static void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INT 3\n"); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[3]) { + (*_X86EMU_intrTab[3])(3); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcd +****************************************************************************/ +static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 intnum; + + START_OF_INSTR(); + DECODE_PRINTF("INT\t"); + intnum = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", intnum); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[intnum]) { + (*_X86EMU_intrTab[intnum])(intnum); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xce +****************************************************************************/ +static void x86emuOp_into(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INTO\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) { + if (_X86EMU_intrTab[4]) { + (*_X86EMU_intrTab[4])(4); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcf +****************************************************************************/ +static void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IRET\n"); + + TRACE_AND_STEP(); + + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_FLG = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd0 +****************************************************************************/ +static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd1 +****************************************************************************/ +static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { + u16 destval; + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd2 +****************************************************************************/ +static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd3 +****************************************************************************/ +static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd4 +****************************************************************************/ +static void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAM\n"); + a = fetch_byte_imm(); /* this is a stupid encoding. */ + if (a != 10) { + /* fix: add base decoding + aam_word(u8 val, int base a) */ + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + /* note the type change here --- returning AL and AH in AX. */ + M.x86.R_AX = aam_word(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd5 +****************************************************************************/ +static void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAD\n"); + a = fetch_byte_imm(); + if (a != 10) { + /* fix: add base decoding + aad_word(u16 val, int base a) */ + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + M.x86.R_AX = aad_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* opcode 0xd6 ILLEGAL OPCODE */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xd7 +****************************************************************************/ +static void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) +{ + u16 addr; + + START_OF_INSTR(); + DECODE_PRINTF("XLAT\n"); + TRACE_AND_STEP(); + addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL); + M.x86.R_AL = fetch_data_byte(addr); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* instuctions D8 .. DF are in i87_ops.c */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xe0 +****************************************************************************/ +static void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPNE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe1 +****************************************************************************/ +static void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe2 +****************************************************************************/ +static void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOP\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0) + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe3 +****************************************************************************/ +static void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JCXZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (M.x86.R_CX == 0) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe4 +****************************************************************************/ +static void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(port); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe5 +****************************************************************************/ +static void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("EAX,%x\n", port); + } else { + DECODE_PRINTF2("AX,%x\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(port); + } else { + M.x86.R_AX = (*sys_inw)(port); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe6 +****************************************************************************/ +static void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + (*sys_outb)(port, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe7 +****************************************************************************/ +static void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%x,EAX\n", port); + } else { + DECODE_PRINTF2("%x,AX\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(port, M.x86.R_EAX); + } else { + (*sys_outw)(port, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe8 +****************************************************************************/ +static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 ip16 = 0; + s32 ip32 = 0; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip32 = (s32) fetch_long_imm(); + ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip32); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); + } else { + ip16 = (s16) fetch_word_imm(); + ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip16); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + M.x86.R_EIP = ip32 & 0xffff; + } else { + push_word(M.x86.R_IP); + M.x86.R_EIP = ip16; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe9 +****************************************************************************/ +static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s32 ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = (s32)fetch_long_imm(); + ip += (s32)M.x86.R_EIP; + DECODE_PRINTF2("%08x\n", (u32)ip); + TRACE_AND_STEP(); + M.x86.R_EIP = (u32)ip; + } else { + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", (u16)ip); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xea +****************************************************************************/ +static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 cs; + u32 ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\tFAR "); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = fetch_long_imm(); + } else { + ip = fetch_word_imm(); + } + cs = fetch_word_imm(); + DECODE_PRINTF2("%04x:", cs); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%08x\n", ip); + } else { + DECODE_PRINTF2("%04x\n", (u16)ip); + } + TRACE_AND_STEP(); + M.x86.R_EIP = ip & 0xffff; + M.x86.R_CS = cs; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xeb +****************************************************************************/ +static void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xec +****************************************************************************/ +static void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IN\tAL,DX\n"); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(M.x86.R_DX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xed +****************************************************************************/ +static void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("IN\tEAX,DX\n"); + } else { + DECODE_PRINTF("IN\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + } else { + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xee +****************************************************************************/ +static void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUT\tDX,AL\n"); + TRACE_AND_STEP(); + (*sys_outb)(M.x86.R_DX, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xef +****************************************************************************/ +static void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUT\tDX,EAX\n"); + } else { + DECODE_PRINTF("OUT\tDX,AX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + } else { + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf0 +****************************************************************************/ +static void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LOCK:\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0xf1 ILLEGAL OPERATION */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xf2 +****************************************************************************/ +static void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPNE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPNE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf3 +****************************************************************************/ +static void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf4 +****************************************************************************/ +static void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("HALT\n"); + TRACE_AND_STEP(); + HALT_SYS(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf5 +****************************************************************************/ +static void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) +{ + /* complement the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CMC\n"); + TRACE_AND_STEP(); + TOGGLE_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf6 +****************************************************************************/ +static void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval, srcval; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + case 7: + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf7 +****************************************************************************/ +static void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + } else { + u16 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + } + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf8 +****************************************************************************/ +static void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) +{ + /* clear the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CLC\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf9 +****************************************************************************/ +static void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) +{ + /* set the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("STC\n"); + TRACE_AND_STEP(); + SET_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfa +****************************************************************************/ +static void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLI\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfb +****************************************************************************/ +static void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) +{ + /* enable interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STI\n"); + TRACE_AND_STEP(); + SET_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfc +****************************************************************************/ +static void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLD\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfd +****************************************************************************/ +static void x86emuOp_std(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STD\n"); + TRACE_AND_STEP(); + SET_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfe +****************************************************************************/ +static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u8 destval; + uint destoffset; + u8 *destreg; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: /* dec word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 3: + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + TRACE_AND_STEP(); + *destreg = inc_byte(*destreg); + break; + case 1: + TRACE_AND_STEP(); + *destreg = dec_byte(*destreg); + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xff +****************************************************************************/ +static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + uint destoffset = 0; + u16 *destreg; + u16 destval,destval2; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef X86EMU_DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t"); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 3: + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + case 7: + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Single byte operation code table: + **************************************************************************/ +void (*x86emu_optab[256])(u8) = +{ +/* 0x00 */ x86emuOp_add_byte_RM_R, +/* 0x01 */ x86emuOp_add_word_RM_R, +/* 0x02 */ x86emuOp_add_byte_R_RM, +/* 0x03 */ x86emuOp_add_word_R_RM, +/* 0x04 */ x86emuOp_add_byte_AL_IMM, +/* 0x05 */ x86emuOp_add_word_AX_IMM, +/* 0x06 */ x86emuOp_push_ES, +/* 0x07 */ x86emuOp_pop_ES, + +/* 0x08 */ x86emuOp_or_byte_RM_R, +/* 0x09 */ x86emuOp_or_word_RM_R, +/* 0x0a */ x86emuOp_or_byte_R_RM, +/* 0x0b */ x86emuOp_or_word_R_RM, +/* 0x0c */ x86emuOp_or_byte_AL_IMM, +/* 0x0d */ x86emuOp_or_word_AX_IMM, +/* 0x0e */ x86emuOp_push_CS, +/* 0x0f */ x86emuOp_two_byte, + +/* 0x10 */ x86emuOp_adc_byte_RM_R, +/* 0x11 */ x86emuOp_adc_word_RM_R, +/* 0x12 */ x86emuOp_adc_byte_R_RM, +/* 0x13 */ x86emuOp_adc_word_R_RM, +/* 0x14 */ x86emuOp_adc_byte_AL_IMM, +/* 0x15 */ x86emuOp_adc_word_AX_IMM, +/* 0x16 */ x86emuOp_push_SS, +/* 0x17 */ x86emuOp_pop_SS, + +/* 0x18 */ x86emuOp_sbb_byte_RM_R, +/* 0x19 */ x86emuOp_sbb_word_RM_R, +/* 0x1a */ x86emuOp_sbb_byte_R_RM, +/* 0x1b */ x86emuOp_sbb_word_R_RM, +/* 0x1c */ x86emuOp_sbb_byte_AL_IMM, +/* 0x1d */ x86emuOp_sbb_word_AX_IMM, +/* 0x1e */ x86emuOp_push_DS, +/* 0x1f */ x86emuOp_pop_DS, + +/* 0x20 */ x86emuOp_and_byte_RM_R, +/* 0x21 */ x86emuOp_and_word_RM_R, +/* 0x22 */ x86emuOp_and_byte_R_RM, +/* 0x23 */ x86emuOp_and_word_R_RM, +/* 0x24 */ x86emuOp_and_byte_AL_IMM, +/* 0x25 */ x86emuOp_and_word_AX_IMM, +/* 0x26 */ x86emuOp_segovr_ES, +/* 0x27 */ x86emuOp_daa, + +/* 0x28 */ x86emuOp_sub_byte_RM_R, +/* 0x29 */ x86emuOp_sub_word_RM_R, +/* 0x2a */ x86emuOp_sub_byte_R_RM, +/* 0x2b */ x86emuOp_sub_word_R_RM, +/* 0x2c */ x86emuOp_sub_byte_AL_IMM, +/* 0x2d */ x86emuOp_sub_word_AX_IMM, +/* 0x2e */ x86emuOp_segovr_CS, +/* 0x2f */ x86emuOp_das, + +/* 0x30 */ x86emuOp_xor_byte_RM_R, +/* 0x31 */ x86emuOp_xor_word_RM_R, +/* 0x32 */ x86emuOp_xor_byte_R_RM, +/* 0x33 */ x86emuOp_xor_word_R_RM, +/* 0x34 */ x86emuOp_xor_byte_AL_IMM, +/* 0x35 */ x86emuOp_xor_word_AX_IMM, +/* 0x36 */ x86emuOp_segovr_SS, +/* 0x37 */ x86emuOp_aaa, + +/* 0x38 */ x86emuOp_cmp_byte_RM_R, +/* 0x39 */ x86emuOp_cmp_word_RM_R, +/* 0x3a */ x86emuOp_cmp_byte_R_RM, +/* 0x3b */ x86emuOp_cmp_word_R_RM, +/* 0x3c */ x86emuOp_cmp_byte_AL_IMM, +/* 0x3d */ x86emuOp_cmp_word_AX_IMM, +/* 0x3e */ x86emuOp_segovr_DS, +/* 0x3f */ x86emuOp_aas, + +/* 0x40 */ x86emuOp_inc_AX, +/* 0x41 */ x86emuOp_inc_CX, +/* 0x42 */ x86emuOp_inc_DX, +/* 0x43 */ x86emuOp_inc_BX, +/* 0x44 */ x86emuOp_inc_SP, +/* 0x45 */ x86emuOp_inc_BP, +/* 0x46 */ x86emuOp_inc_SI, +/* 0x47 */ x86emuOp_inc_DI, + +/* 0x48 */ x86emuOp_dec_AX, +/* 0x49 */ x86emuOp_dec_CX, +/* 0x4a */ x86emuOp_dec_DX, +/* 0x4b */ x86emuOp_dec_BX, +/* 0x4c */ x86emuOp_dec_SP, +/* 0x4d */ x86emuOp_dec_BP, +/* 0x4e */ x86emuOp_dec_SI, +/* 0x4f */ x86emuOp_dec_DI, + +/* 0x50 */ x86emuOp_push_AX, +/* 0x51 */ x86emuOp_push_CX, +/* 0x52 */ x86emuOp_push_DX, +/* 0x53 */ x86emuOp_push_BX, +/* 0x54 */ x86emuOp_push_SP, +/* 0x55 */ x86emuOp_push_BP, +/* 0x56 */ x86emuOp_push_SI, +/* 0x57 */ x86emuOp_push_DI, + +/* 0x58 */ x86emuOp_pop_AX, +/* 0x59 */ x86emuOp_pop_CX, +/* 0x5a */ x86emuOp_pop_DX, +/* 0x5b */ x86emuOp_pop_BX, +/* 0x5c */ x86emuOp_pop_SP, +/* 0x5d */ x86emuOp_pop_BP, +/* 0x5e */ x86emuOp_pop_SI, +/* 0x5f */ x86emuOp_pop_DI, + +/* 0x60 */ x86emuOp_push_all, +/* 0x61 */ x86emuOp_pop_all, +/* 0x62 */ x86emuOp_illegal_op, /* bound */ +/* 0x63 */ x86emuOp_illegal_op, /* arpl */ +/* 0x64 */ x86emuOp_segovr_FS, +/* 0x65 */ x86emuOp_segovr_GS, +/* 0x66 */ x86emuOp_prefix_data, +/* 0x67 */ x86emuOp_prefix_addr, + +/* 0x68 */ x86emuOp_push_word_IMM, +/* 0x69 */ x86emuOp_imul_word_IMM, +/* 0x6a */ x86emuOp_push_byte_IMM, +/* 0x6b */ x86emuOp_imul_byte_IMM, +/* 0x6c */ x86emuOp_ins_byte, +/* 0x6d */ x86emuOp_ins_word, +/* 0x6e */ x86emuOp_outs_byte, +/* 0x6f */ x86emuOp_outs_word, + +/* 0x70 */ x86emuOp_jump_near_O, +/* 0x71 */ x86emuOp_jump_near_NO, +/* 0x72 */ x86emuOp_jump_near_B, +/* 0x73 */ x86emuOp_jump_near_NB, +/* 0x74 */ x86emuOp_jump_near_Z, +/* 0x75 */ x86emuOp_jump_near_NZ, +/* 0x76 */ x86emuOp_jump_near_BE, +/* 0x77 */ x86emuOp_jump_near_NBE, + +/* 0x78 */ x86emuOp_jump_near_S, +/* 0x79 */ x86emuOp_jump_near_NS, +/* 0x7a */ x86emuOp_jump_near_P, +/* 0x7b */ x86emuOp_jump_near_NP, +/* 0x7c */ x86emuOp_jump_near_L, +/* 0x7d */ x86emuOp_jump_near_NL, +/* 0x7e */ x86emuOp_jump_near_LE, +/* 0x7f */ x86emuOp_jump_near_NLE, + +/* 0x80 */ x86emuOp_opc80_byte_RM_IMM, +/* 0x81 */ x86emuOp_opc81_word_RM_IMM, +/* 0x82 */ x86emuOp_opc82_byte_RM_IMM, +/* 0x83 */ x86emuOp_opc83_word_RM_IMM, +/* 0x84 */ x86emuOp_test_byte_RM_R, +/* 0x85 */ x86emuOp_test_word_RM_R, +/* 0x86 */ x86emuOp_xchg_byte_RM_R, +/* 0x87 */ x86emuOp_xchg_word_RM_R, + +/* 0x88 */ x86emuOp_mov_byte_RM_R, +/* 0x89 */ x86emuOp_mov_word_RM_R, +/* 0x8a */ x86emuOp_mov_byte_R_RM, +/* 0x8b */ x86emuOp_mov_word_R_RM, +/* 0x8c */ x86emuOp_mov_word_RM_SR, +/* 0x8d */ x86emuOp_lea_word_R_M, +/* 0x8e */ x86emuOp_mov_word_SR_RM, +/* 0x8f */ x86emuOp_pop_RM, + +/* 0x90 */ x86emuOp_nop, +/* 0x91 */ x86emuOp_xchg_word_AX_CX, +/* 0x92 */ x86emuOp_xchg_word_AX_DX, +/* 0x93 */ x86emuOp_xchg_word_AX_BX, +/* 0x94 */ x86emuOp_xchg_word_AX_SP, +/* 0x95 */ x86emuOp_xchg_word_AX_BP, +/* 0x96 */ x86emuOp_xchg_word_AX_SI, +/* 0x97 */ x86emuOp_xchg_word_AX_DI, + +/* 0x98 */ x86emuOp_cbw, +/* 0x99 */ x86emuOp_cwd, +/* 0x9a */ x86emuOp_call_far_IMM, +/* 0x9b */ x86emuOp_wait, +/* 0x9c */ x86emuOp_pushf_word, +/* 0x9d */ x86emuOp_popf_word, +/* 0x9e */ x86emuOp_sahf, +/* 0x9f */ x86emuOp_lahf, + +/* 0xa0 */ x86emuOp_mov_AL_M_IMM, +/* 0xa1 */ x86emuOp_mov_AX_M_IMM, +/* 0xa2 */ x86emuOp_mov_M_AL_IMM, +/* 0xa3 */ x86emuOp_mov_M_AX_IMM, +/* 0xa4 */ x86emuOp_movs_byte, +/* 0xa5 */ x86emuOp_movs_word, +/* 0xa6 */ x86emuOp_cmps_byte, +/* 0xa7 */ x86emuOp_cmps_word, +/* 0xa8 */ x86emuOp_test_AL_IMM, +/* 0xa9 */ x86emuOp_test_AX_IMM, +/* 0xaa */ x86emuOp_stos_byte, +/* 0xab */ x86emuOp_stos_word, +/* 0xac */ x86emuOp_lods_byte, +/* 0xad */ x86emuOp_lods_word, +/* 0xac */ x86emuOp_scas_byte, +/* 0xad */ x86emuOp_scas_word, + + +/* 0xb0 */ x86emuOp_mov_byte_AL_IMM, +/* 0xb1 */ x86emuOp_mov_byte_CL_IMM, +/* 0xb2 */ x86emuOp_mov_byte_DL_IMM, +/* 0xb3 */ x86emuOp_mov_byte_BL_IMM, +/* 0xb4 */ x86emuOp_mov_byte_AH_IMM, +/* 0xb5 */ x86emuOp_mov_byte_CH_IMM, +/* 0xb6 */ x86emuOp_mov_byte_DH_IMM, +/* 0xb7 */ x86emuOp_mov_byte_BH_IMM, + +/* 0xb8 */ x86emuOp_mov_word_AX_IMM, +/* 0xb9 */ x86emuOp_mov_word_CX_IMM, +/* 0xba */ x86emuOp_mov_word_DX_IMM, +/* 0xbb */ x86emuOp_mov_word_BX_IMM, +/* 0xbc */ x86emuOp_mov_word_SP_IMM, +/* 0xbd */ x86emuOp_mov_word_BP_IMM, +/* 0xbe */ x86emuOp_mov_word_SI_IMM, +/* 0xbf */ x86emuOp_mov_word_DI_IMM, + +/* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM, +/* 0xc1 */ x86emuOp_opcC1_word_RM_MEM, +/* 0xc2 */ x86emuOp_ret_near_IMM, +/* 0xc3 */ x86emuOp_ret_near, +/* 0xc4 */ x86emuOp_les_R_IMM, +/* 0xc5 */ x86emuOp_lds_R_IMM, +/* 0xc6 */ x86emuOp_mov_byte_RM_IMM, +/* 0xc7 */ x86emuOp_mov_word_RM_IMM, +/* 0xc8 */ x86emuOp_enter, +/* 0xc9 */ x86emuOp_leave, +/* 0xca */ x86emuOp_ret_far_IMM, +/* 0xcb */ x86emuOp_ret_far, +/* 0xcc */ x86emuOp_int3, +/* 0xcd */ x86emuOp_int_IMM, +/* 0xce */ x86emuOp_into, +/* 0xcf */ x86emuOp_iret, + +/* 0xd0 */ x86emuOp_opcD0_byte_RM_1, +/* 0xd1 */ x86emuOp_opcD1_word_RM_1, +/* 0xd2 */ x86emuOp_opcD2_byte_RM_CL, +/* 0xd3 */ x86emuOp_opcD3_word_RM_CL, +/* 0xd4 */ x86emuOp_aam, +/* 0xd5 */ x86emuOp_aad, +/* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */ +/* 0xd7 */ x86emuOp_xlat, +/* 0xd8 */ x86emuOp_esc_coprocess_d8, +/* 0xd9 */ x86emuOp_esc_coprocess_d9, +/* 0xda */ x86emuOp_esc_coprocess_da, +/* 0xdb */ x86emuOp_esc_coprocess_db, +/* 0xdc */ x86emuOp_esc_coprocess_dc, +/* 0xdd */ x86emuOp_esc_coprocess_dd, +/* 0xde */ x86emuOp_esc_coprocess_de, +/* 0xdf */ x86emuOp_esc_coprocess_df, + +/* 0xe0 */ x86emuOp_loopne, +/* 0xe1 */ x86emuOp_loope, +/* 0xe2 */ x86emuOp_loop, +/* 0xe3 */ x86emuOp_jcxz, +/* 0xe4 */ x86emuOp_in_byte_AL_IMM, +/* 0xe5 */ x86emuOp_in_word_AX_IMM, +/* 0xe6 */ x86emuOp_out_byte_IMM_AL, +/* 0xe7 */ x86emuOp_out_word_IMM_AX, + +/* 0xe8 */ x86emuOp_call_near_IMM, +/* 0xe9 */ x86emuOp_jump_near_IMM, +/* 0xea */ x86emuOp_jump_far_IMM, +/* 0xeb */ x86emuOp_jump_byte_IMM, +/* 0xec */ x86emuOp_in_byte_AL_DX, +/* 0xed */ x86emuOp_in_word_AX_DX, +/* 0xee */ x86emuOp_out_byte_DX_AL, +/* 0xef */ x86emuOp_out_word_DX_AX, + +/* 0xf0 */ x86emuOp_lock, +/* 0xf1 */ x86emuOp_illegal_op, +/* 0xf2 */ x86emuOp_repne, +/* 0xf3 */ x86emuOp_repe, +/* 0xf4 */ x86emuOp_halt, +/* 0xf5 */ x86emuOp_cmc, +/* 0xf6 */ x86emuOp_opcF6_byte_RM, +/* 0xf7 */ x86emuOp_opcF7_word_RM, + +/* 0xf8 */ x86emuOp_clc, +/* 0xf9 */ x86emuOp_stc, +/* 0xfa */ x86emuOp_cli, +/* 0xfb */ x86emuOp_sti, +/* 0xfc */ x86emuOp_cld, +/* 0xfd */ x86emuOp_std, +/* 0xfe */ x86emuOp_opcFE_byte_RM, +/* 0xff */ x86emuOp_opcFF_word_RM, +}; diff --git a/src/nvidia/arch/nvalloc/unix/x86emu/ops2.c b/src/nvidia/arch/nvalloc/unix/x86emu/ops2.c new file mode 100644 index 0000000000..6053b4821a --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/x86emu/ops2.c @@ -0,0 +1,2877 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 extended two-byte processor +* instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +static void x86emuOp2_illegal_op( + u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); +DB( NV_PRINTF(LEVEL_INFO, + "%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP - 2, op2);) + HALT_SYS(); + END_OF_INSTR(); +} + +#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x80-0x8F +****************************************************************************/ +static void x86emuOp2_long_jump(u8 op2) +{ + s32 target; + const char *name = 0; + int cond = 0; + + /* conditional jump to word offset. */ + START_OF_INSTR(); + switch (op2) { + case 0x80: + name = "JO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x81: + name = "JNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x82: + name = "JB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x83: + name = "JNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x84: + name = "JZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x85: + name = "JNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x86: + name = "JBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x87: + name = "JNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x88: + name = "JS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x89: + name = "JNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x8a: + name = "JP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x8b: + name = "JNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x8c: + name = "JL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8d: + name = "JNL\t"; + cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8e: + name = "JLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x8f: + name = "JNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + (void)name; + target = (s16) fetch_word_imm(); + target += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", target); + TRACE_AND_STEP(); + if (cond) + M.x86.R_IP = (u16)target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x90-0x9F +****************************************************************************/ +static void x86emuOp2_set_byte(u8 op2) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg; + const char *name = 0; + int cond = 0; + + START_OF_INSTR(); + switch (op2) { + case 0x90: + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x91: + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x92: + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x93: + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x94: + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x95: + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x96: + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x97: + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x98: + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x99: + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x9a: + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x9b: + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x9c: + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9d: + name = "SETNL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9e: + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x9f: + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + (void)name; + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa0 +****************************************************************************/ +static void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tFS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_FS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa1 +****************************************************************************/ +static void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tFS\n"); + TRACE_AND_STEP(); + M.x86.R_FS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa3 +****************************************************************************/ +static void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BT\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa4 +****************************************************************************/ +static void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa5 +****************************************************************************/ +static void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa8 +****************************************************************************/ +static void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tGS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_GS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa9 +****************************************************************************/ +static void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tGS\n"); + TRACE_AND_STEP(); + M.x86.R_GS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +#if 1 +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xab +****************************************************************************/ +static void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} +#endif + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xac +****************************************************************************/ +static void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xad +****************************************************************************/ +static void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaf +****************************************************************************/ +static void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb2 +****************************************************************************/ +static void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LSS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb3 +****************************************************************************/ +static void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb4 +****************************************************************************/ +static void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LFS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb5 +****************************************************************************/ +static void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LGS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb6 +****************************************************************************/ +static void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb7 +****************************************************************************/ +static void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xba +****************************************************************************/ +static void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (rh) { + case 4: + DECODE_PRINTF("BT\t"); + break; + case 5: + DECODE_PRINTF("BTS\t"); + break; + case 6: + DECODE_PRINTF("BTR\t"); + break; + case 7: + DECODE_PRINTF("BTC\t"); + break; + default: + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); +DB( NV_PRINTF(LEVEL_INFO, + "%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP - 3, op2, + (mod << 6) | (rh << 3) | rl);) + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + u8 shift; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + u8 shift; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbb +****************************************************************************/ +static void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbc +****************************************************************************/ +static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcval = *DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcval = *DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbd +****************************************************************************/ +static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcval = *DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcval = *DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbe +****************************************************************************/ +static void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbf +****************************************************************************/ +static void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Double byte operation code table: + **************************************************************************/ +void (*x86emu_optab2[256])(u8) = +{ +/* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ +/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x04 */ x86emuOp2_illegal_op, +/* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ +/* 0x0a */ x86emuOp2_illegal_op, +/* 0x0b */ x86emuOp2_illegal_op, +/* 0x0c */ x86emuOp2_illegal_op, +/* 0x0d */ x86emuOp2_illegal_op, +/* 0x0e */ x86emuOp2_illegal_op, +/* 0x0f */ x86emuOp2_illegal_op, + +/* 0x10 */ x86emuOp2_illegal_op, +/* 0x11 */ x86emuOp2_illegal_op, +/* 0x12 */ x86emuOp2_illegal_op, +/* 0x13 */ x86emuOp2_illegal_op, +/* 0x14 */ x86emuOp2_illegal_op, +/* 0x15 */ x86emuOp2_illegal_op, +/* 0x16 */ x86emuOp2_illegal_op, +/* 0x17 */ x86emuOp2_illegal_op, +/* 0x18 */ x86emuOp2_illegal_op, +/* 0x19 */ x86emuOp2_illegal_op, +/* 0x1a */ x86emuOp2_illegal_op, +/* 0x1b */ x86emuOp2_illegal_op, +/* 0x1c */ x86emuOp2_illegal_op, +/* 0x1d */ x86emuOp2_illegal_op, +/* 0x1e */ x86emuOp2_illegal_op, +/* 0x1f */ x86emuOp2_illegal_op, + +/* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */ +/* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */ +/* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */ +/* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */ +/* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */ +/* 0x25 */ x86emuOp2_illegal_op, +/* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */ +/* 0x27 */ x86emuOp2_illegal_op, +/* 0x28 */ x86emuOp2_illegal_op, +/* 0x29 */ x86emuOp2_illegal_op, +/* 0x2a */ x86emuOp2_illegal_op, +/* 0x2b */ x86emuOp2_illegal_op, +/* 0x2c */ x86emuOp2_illegal_op, +/* 0x2d */ x86emuOp2_illegal_op, +/* 0x2e */ x86emuOp2_illegal_op, +/* 0x2f */ x86emuOp2_illegal_op, + +/* 0x30 */ x86emuOp2_illegal_op, +/* 0x31 */ x86emuOp2_illegal_op, +/* 0x32 */ x86emuOp2_illegal_op, +/* 0x33 */ x86emuOp2_illegal_op, +/* 0x34 */ x86emuOp2_illegal_op, +/* 0x35 */ x86emuOp2_illegal_op, +/* 0x36 */ x86emuOp2_illegal_op, +/* 0x37 */ x86emuOp2_illegal_op, +/* 0x38 */ x86emuOp2_illegal_op, +/* 0x39 */ x86emuOp2_illegal_op, +/* 0x3a */ x86emuOp2_illegal_op, +/* 0x3b */ x86emuOp2_illegal_op, +/* 0x3c */ x86emuOp2_illegal_op, +/* 0x3d */ x86emuOp2_illegal_op, +/* 0x3e */ x86emuOp2_illegal_op, +/* 0x3f */ x86emuOp2_illegal_op, + +/* 0x40 */ x86emuOp2_illegal_op, +/* 0x41 */ x86emuOp2_illegal_op, +/* 0x42 */ x86emuOp2_illegal_op, +/* 0x43 */ x86emuOp2_illegal_op, +/* 0x44 */ x86emuOp2_illegal_op, +/* 0x45 */ x86emuOp2_illegal_op, +/* 0x46 */ x86emuOp2_illegal_op, +/* 0x47 */ x86emuOp2_illegal_op, +/* 0x48 */ x86emuOp2_illegal_op, +/* 0x49 */ x86emuOp2_illegal_op, +/* 0x4a */ x86emuOp2_illegal_op, +/* 0x4b */ x86emuOp2_illegal_op, +/* 0x4c */ x86emuOp2_illegal_op, +/* 0x4d */ x86emuOp2_illegal_op, +/* 0x4e */ x86emuOp2_illegal_op, +/* 0x4f */ x86emuOp2_illegal_op, + +/* 0x50 */ x86emuOp2_illegal_op, +/* 0x51 */ x86emuOp2_illegal_op, +/* 0x52 */ x86emuOp2_illegal_op, +/* 0x53 */ x86emuOp2_illegal_op, +/* 0x54 */ x86emuOp2_illegal_op, +/* 0x55 */ x86emuOp2_illegal_op, +/* 0x56 */ x86emuOp2_illegal_op, +/* 0x57 */ x86emuOp2_illegal_op, +/* 0x58 */ x86emuOp2_illegal_op, +/* 0x59 */ x86emuOp2_illegal_op, +/* 0x5a */ x86emuOp2_illegal_op, +/* 0x5b */ x86emuOp2_illegal_op, +/* 0x5c */ x86emuOp2_illegal_op, +/* 0x5d */ x86emuOp2_illegal_op, +/* 0x5e */ x86emuOp2_illegal_op, +/* 0x5f */ x86emuOp2_illegal_op, + +/* 0x60 */ x86emuOp2_illegal_op, +/* 0x61 */ x86emuOp2_illegal_op, +/* 0x62 */ x86emuOp2_illegal_op, +/* 0x63 */ x86emuOp2_illegal_op, +/* 0x64 */ x86emuOp2_illegal_op, +/* 0x65 */ x86emuOp2_illegal_op, +/* 0x66 */ x86emuOp2_illegal_op, +/* 0x67 */ x86emuOp2_illegal_op, +/* 0x68 */ x86emuOp2_illegal_op, +/* 0x69 */ x86emuOp2_illegal_op, +/* 0x6a */ x86emuOp2_illegal_op, +/* 0x6b */ x86emuOp2_illegal_op, +/* 0x6c */ x86emuOp2_illegal_op, +/* 0x6d */ x86emuOp2_illegal_op, +/* 0x6e */ x86emuOp2_illegal_op, +/* 0x6f */ x86emuOp2_illegal_op, + +/* 0x70 */ x86emuOp2_illegal_op, +/* 0x71 */ x86emuOp2_illegal_op, +/* 0x72 */ x86emuOp2_illegal_op, +/* 0x73 */ x86emuOp2_illegal_op, +/* 0x74 */ x86emuOp2_illegal_op, +/* 0x75 */ x86emuOp2_illegal_op, +/* 0x76 */ x86emuOp2_illegal_op, +/* 0x77 */ x86emuOp2_illegal_op, +/* 0x78 */ x86emuOp2_illegal_op, +/* 0x79 */ x86emuOp2_illegal_op, +/* 0x7a */ x86emuOp2_illegal_op, +/* 0x7b */ x86emuOp2_illegal_op, +/* 0x7c */ x86emuOp2_illegal_op, +/* 0x7d */ x86emuOp2_illegal_op, +/* 0x7e */ x86emuOp2_illegal_op, +/* 0x7f */ x86emuOp2_illegal_op, + +/* 0x80 */ x86emuOp2_long_jump, +/* 0x81 */ x86emuOp2_long_jump, +/* 0x82 */ x86emuOp2_long_jump, +/* 0x83 */ x86emuOp2_long_jump, +/* 0x84 */ x86emuOp2_long_jump, +/* 0x85 */ x86emuOp2_long_jump, +/* 0x86 */ x86emuOp2_long_jump, +/* 0x87 */ x86emuOp2_long_jump, +/* 0x88 */ x86emuOp2_long_jump, +/* 0x89 */ x86emuOp2_long_jump, +/* 0x8a */ x86emuOp2_long_jump, +/* 0x8b */ x86emuOp2_long_jump, +/* 0x8c */ x86emuOp2_long_jump, +/* 0x8d */ x86emuOp2_long_jump, +/* 0x8e */ x86emuOp2_long_jump, +/* 0x8f */ x86emuOp2_long_jump, + +/* 0x90 */ x86emuOp2_set_byte, +/* 0x91 */ x86emuOp2_set_byte, +/* 0x92 */ x86emuOp2_set_byte, +/* 0x93 */ x86emuOp2_set_byte, +/* 0x94 */ x86emuOp2_set_byte, +/* 0x95 */ x86emuOp2_set_byte, +/* 0x96 */ x86emuOp2_set_byte, +/* 0x97 */ x86emuOp2_set_byte, +/* 0x98 */ x86emuOp2_set_byte, +/* 0x99 */ x86emuOp2_set_byte, +/* 0x9a */ x86emuOp2_set_byte, +/* 0x9b */ x86emuOp2_set_byte, +/* 0x9c */ x86emuOp2_set_byte, +/* 0x9d */ x86emuOp2_set_byte, +/* 0x9e */ x86emuOp2_set_byte, +/* 0x9f */ x86emuOp2_set_byte, + +/* 0xa0 */ x86emuOp2_push_FS, +/* 0xa1 */ x86emuOp2_pop_FS, +/* 0xa2 */ x86emuOp2_illegal_op, +/* 0xa3 */ x86emuOp2_bt_R, +/* 0xa4 */ x86emuOp2_shld_IMM, +/* 0xa5 */ x86emuOp2_shld_CL, +/* 0xa6 */ x86emuOp2_illegal_op, +/* 0xa7 */ x86emuOp2_illegal_op, +/* 0xa8 */ x86emuOp2_push_GS, +/* 0xa9 */ x86emuOp2_pop_GS, +/* 0xaa */ x86emuOp2_illegal_op, +/* 0xab */ x86emuOp2_bts_R, +/* 0xac */ x86emuOp2_shrd_IMM, +/* 0xad */ x86emuOp2_shrd_CL, +/* 0xae */ x86emuOp2_illegal_op, +/* 0xaf */ x86emuOp2_imul_R_RM, + +/* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb2 */ x86emuOp2_lss_R_IMM, +/* 0xb3 */ x86emuOp2_btr_R, +/* 0xb4 */ x86emuOp2_lfs_R_IMM, +/* 0xb5 */ x86emuOp2_lgs_R_IMM, +/* 0xb6 */ x86emuOp2_movzx_byte_R_RM, +/* 0xb7 */ x86emuOp2_movzx_word_R_RM, +/* 0xb8 */ x86emuOp2_illegal_op, +/* 0xb9 */ x86emuOp2_illegal_op, +/* 0xba */ x86emuOp2_btX_I, +/* 0xbb */ x86emuOp2_btc_R, +/* 0xbc */ x86emuOp2_bsf, +/* 0xbd */ x86emuOp2_bsr, +/* 0xbe */ x86emuOp2_movsx_byte_R_RM, +/* 0xbf */ x86emuOp2_movsx_word_R_RM, + +/* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc2 */ x86emuOp2_illegal_op, +/* 0xc3 */ x86emuOp2_illegal_op, +/* 0xc4 */ x86emuOp2_illegal_op, +/* 0xc5 */ x86emuOp2_illegal_op, +/* 0xc6 */ x86emuOp2_illegal_op, +/* 0xc7 */ x86emuOp2_illegal_op, +/* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */ + +/* 0xd0 */ x86emuOp2_illegal_op, +/* 0xd1 */ x86emuOp2_illegal_op, +/* 0xd2 */ x86emuOp2_illegal_op, +/* 0xd3 */ x86emuOp2_illegal_op, +/* 0xd4 */ x86emuOp2_illegal_op, +/* 0xd5 */ x86emuOp2_illegal_op, +/* 0xd6 */ x86emuOp2_illegal_op, +/* 0xd7 */ x86emuOp2_illegal_op, +/* 0xd8 */ x86emuOp2_illegal_op, +/* 0xd9 */ x86emuOp2_illegal_op, +/* 0xda */ x86emuOp2_illegal_op, +/* 0xdb */ x86emuOp2_illegal_op, +/* 0xdc */ x86emuOp2_illegal_op, +/* 0xdd */ x86emuOp2_illegal_op, +/* 0xde */ x86emuOp2_illegal_op, +/* 0xdf */ x86emuOp2_illegal_op, + +/* 0xe0 */ x86emuOp2_illegal_op, +/* 0xe1 */ x86emuOp2_illegal_op, +/* 0xe2 */ x86emuOp2_illegal_op, +/* 0xe3 */ x86emuOp2_illegal_op, +/* 0xe4 */ x86emuOp2_illegal_op, +/* 0xe5 */ x86emuOp2_illegal_op, +/* 0xe6 */ x86emuOp2_illegal_op, +/* 0xe7 */ x86emuOp2_illegal_op, +/* 0xe8 */ x86emuOp2_illegal_op, +/* 0xe9 */ x86emuOp2_illegal_op, +/* 0xea */ x86emuOp2_illegal_op, +/* 0xeb */ x86emuOp2_illegal_op, +/* 0xec */ x86emuOp2_illegal_op, +/* 0xed */ x86emuOp2_illegal_op, +/* 0xee */ x86emuOp2_illegal_op, +/* 0xef */ x86emuOp2_illegal_op, + +/* 0xf0 */ x86emuOp2_illegal_op, +/* 0xf1 */ x86emuOp2_illegal_op, +/* 0xf2 */ x86emuOp2_illegal_op, +/* 0xf3 */ x86emuOp2_illegal_op, +/* 0xf4 */ x86emuOp2_illegal_op, +/* 0xf5 */ x86emuOp2_illegal_op, +/* 0xf6 */ x86emuOp2_illegal_op, +/* 0xf7 */ x86emuOp2_illegal_op, +/* 0xf8 */ x86emuOp2_illegal_op, +/* 0xf9 */ x86emuOp2_illegal_op, +/* 0xfa */ x86emuOp2_illegal_op, +/* 0xfb */ x86emuOp2_illegal_op, +/* 0xfc */ x86emuOp2_illegal_op, +/* 0xfd */ x86emuOp2_illegal_op, +/* 0xfe */ x86emuOp2_illegal_op, +/* 0xff */ x86emuOp2_illegal_op, +}; diff --git a/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c b/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c new file mode 100644 index 0000000000..4740072230 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c @@ -0,0 +1,2655 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the primitive +* machine operations used by the emulation code in ops.c +* +* Carry Chain Calculation +* +* This represents a somewhat expensive calculation which is +* apparently required to emulate the setting of the OF and AF flag. +* The latter is not so important, but the former is. The overflow +* flag is the XOR of the top two bits of the carry chain for an +* addition (similar for subtraction). Since we do not want to +* simulate the addition in a bitwise manner, we try to calculate the +* carry chain given the two operands and the result. +* +* So, given the following table, which represents the addition of two +* bits, we can derive a formula for the carry chain. +* +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 +* +* By inspection, one gets: cc = ab + r'(a + b) +* +* That represents alot of operations, but NO CHOICE.... +* +* Borrow Chain Calculation. +* +* The following table represents the subtraction of two bits, from +* which we can derive a formula for the borrow chain. +* +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 +* +* By inspection, one gets: bc = a'b + r(a' + b) +* +****************************************************************************/ + +#define PRIM_OPS_NO_REDEFINE_ASM +#include "x86emu/x86emui.h" + +/*------------------------- Global Variables ------------------------------*/ + +static u32 x86emu_parity_tab[8] = +{ + 0x96696996, + 0x69969669, + 0x69969669, + 0x96696996, + 0x69969669, + 0x96696996, + 0x96696996, + 0x69969669, +}; + +#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aaa_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aas_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAD instruction and side effects. +****************************************************************************/ +u16 aad_word(u16 d) +{ + u16 l; + u8 hb, lb; + + hb = (u8)((d >> 8) & 0xff); + lb = (u8)((d & 0xff)); + l = (u16)((lb + 10 * hb) & 0xFF); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the AAM instruction and side effects. +****************************************************************************/ +u16 aam_word(u8 d) +{ + u16 h, l; + + h = (u16)(d / 10); + l = (u16)(d % 10); + l |= (u16)(h << 8); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u8 adc_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u16 adc_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u32 adc_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + if (ACCESS_FLAG(F_CF)) { + lo = 1 + (d & 0xFFFF) + (s & 0xFFFF); + res = 1 + d + s; + } + else { + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + } + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u8 add_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u16 add_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u32 add_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u8 and_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u16 and_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u32 and_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u8 cmp_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CLEAR_FLAG(F_CF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u16 cmp_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u32 cmp_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DAA instruction and side effects. +****************************************************************************/ +u8 daa_byte(u8 d) +{ + u32 res = d; + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + res += 6; + SET_FLAG(F_AF); + } + if (res > 0x9F || ACCESS_FLAG(F_CF)) { + res += 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DAS instruction and side effects. +****************************************************************************/ +u8 das_byte(u8 d) +{ + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + d -= 6; + SET_FLAG(F_AF); + } + if (d > 0x9F || ACCESS_FLAG(F_CF)) { + d -= 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(d & 0x80, F_SF); + CONDITIONAL_SET_FLAG(d == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u8 dec_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on sub_byte, uses s==1. */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u16 dec_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on the sub_byte routine, with s==1 */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u32 dec_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u8 inc_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = ((1 & d) | (~res)) & (1 | d); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u16 inc_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u32 inc_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 or_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d | s; + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 or_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d | s; + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 or_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d | s; + + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 neg_byte(u8 s) +{ + register u8 res; + register u8 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u8)-s; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 neg_word(u16 s) +{ + register u16 res; + register u16 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u16)-s; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 neg_long(u32 s) +{ + register u32 res; + register u32 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u32)-s; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u8 not_byte(u8 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u16 not_word(u16 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u32 not_long(u32 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u8 rcl_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + /* s is the rotate distance. It varies from 0 - 8. */ + /* have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + want to rotate through the carry by "s" bits. We could + loop, but that's inefficient. So the width is 9, + and we split into three parts: + + The new carry flag (was B_n) + the stuff in B_n-1 .. B_0 + the stuff in B_7 .. B_n+1 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the MSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(8-n) + 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 + 3) B_(n-1) <- cf + 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); + + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u16 rcl_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + res = d; + if ((cnt = s % 17) != 0) { + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u32 rcl_long(u32 d, u8 s) +{ + register u32 res, cnt, mask, cf; + + res = d; + if ((cnt = s % 33) != 0) { + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u8 rcr_byte(u8 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the LSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(n-1) + 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 3) B_(8-n) <- cf + 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u16 rcr_word(u16 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 17) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u32 rcr_long(u32 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 33) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u8 rol_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate left */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 ... B_0 + + The new rotate is done mod 8. + Much simpler than the "rcl" or "rcr" operations. + + IF n > 0 + 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) + 2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) + */ + res = d; + if ((cnt = s % 8) != 0) { + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u16 rol_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u32 rol_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u8 ror_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate right */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + B_7 ... B_0 + + The rotate is done mod 8. + + IF n > 0 + 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) + */ + res = d; + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u16 ror_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u32 ror_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u8 shl_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u16 shl_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u32 shl_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u8 shr_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u16 shr_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u32 shr_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u8 sar_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + res = d; + sf = d & 0x80; + cnt = s % 8; + if (cnt > 0 && cnt < 8) { + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + } else if (cnt >= 8) { + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u16 sar_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + sf = d & 0x8000; + cnt = s % 16; + res = d; + if (cnt > 0 && cnt < 16) { + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 16) { + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u32 sar_long(u32 d, u8 s) +{ + u32 cnt, res, cf, mask, sf; + + sf = d & 0x80000000; + cnt = s % 32; + res = d; + if (cnt > 0 && cnt < 32) { + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 32) { + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u16 shld_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u32 shld_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u16 shrd_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u32 shrd_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u8 sbb_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u16 sbb_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u32 sbb_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u8 sub_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u16 sub_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u32 sub_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u8 xor_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u16 xor_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u32 xor_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_byte(u8 s) +{ + s16 res = (s16)((s8)M.x86.R_AL * (s8)s); + + M.x86.R_AX = res; + if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_word(u16 s) +{ + s32 res = (s16)M.x86.R_AX * (s16)s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x00) || + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 res = (s64)(s32)d * (s32)s; + + *res_lo = (u32)res; + *res_hi = (u32)(res >> 32); +#else + u32 d_lo,d_hi,d_sign; + u32 s_lo,s_hi,s_sign; + u32 rlo_lo,rlo_hi,rhi_lo; + + if ((d_sign = d & 0x80000000) != 0) + d = -d; + d_lo = d & 0xFFFF; + d_hi = d >> 16; + if ((s_sign = s & 0x80000000) != 0) + s = -s; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = d_lo * s_lo; + rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = d_hi * s_hi + (rlo_hi >> 16); + *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + *res_hi = rhi_lo; + if (d_sign != s_sign) { + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } +#endif +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long(u32 s) +{ + imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); + if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00) || + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_byte(u8 s) +{ + u16 res = (u16)(M.x86.R_AL * s); + + M.x86.R_AX = res; + if (M.x86.R_AH == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_word(u16 s) +{ + u32 res = M.x86.R_AX * s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (M.x86.R_DX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 res = (u64)M.x86.R_EAX * s; + + M.x86.R_EAX = (u32)res; + M.x86.R_EDX = (u32)(res >> 32); +#else + u32 a,a_lo,a_hi; + u32 s_lo,s_hi; + u32 rlo_lo,rlo_hi,rhi_lo; + + a = M.x86.R_EAX; + a_lo = a & 0xFFFF; + a_hi = a >> 16; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = a_lo * s_lo; + rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = a_hi * s_hi + (rlo_hi >> 16); + M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + M.x86.R_EDX = rhi_lo; +#endif + + if (M.x86.R_EDX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_byte(u8 s) +{ + s32 dvd, div, mod; + + dvd = (s16)M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s8)s; + mod = dvd % (s8)s; + if (abs(div) > 0x7f) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (s8) div; + M.x86.R_AH = (s8) mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_word(u16 s) +{ + s32 dvd, div, mod; + + dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s16)s; + mod = dvd % (s16)s; + if (abs(div) > 0x7fff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 dvd, div, mod; + + dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s32)s; + mod = dvd % (s32)s; + if (((u64)div >> 32) != 0 && + ((u64)div >> 32) != 0xFFFFFFFFUL) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + u32 abs_s = s & 0x7FFFFFFF; + u32 abs_h_dvd = h_dvd & 0x7FFFFFFF; + u32 h_s = abs_s >> 1; + u32 l_s = abs_s << 31; + int counter = 31; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (abs_h_dvd || (l_dvd > abs_s)) { + x86emu_intr_raise(0); + return; + } + /* sign */ + div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); + mod = l_dvd; + +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_byte(u8 s) +{ + u32 dvd, div, mod; + + dvd = M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u8)s; + mod = dvd % (u8)s; + if (div > 0xff) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (u8)div; + M.x86.R_AH = (u8)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_word(u16 s) +{ + u32 dvd, div, mod; + + dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u16)s; + mod = dvd % (u16)s; + if (div > 0xffff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 dvd, div, mod; + + dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u32)s; + mod = dvd % (u32)s; + if (div > 0xffffffffULL) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + + u32 h_s = s; + u32 l_s = 0; + int counter = 32; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (h_dvd || (l_dvd > s)) { + x86emu_intr_raise(0); + return; + } + mod = l_dvd; +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IN string instruction and side effects. +****************************************************************************/ +void ins(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + + case 2: + while (count--) { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + case 4: + while (count--) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + M.x86.R_DI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + break; + case 2: + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + break; + case 4: + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + break; + } + M.x86.R_DI += inc; + } +} + +/**************************************************************************** +REMARKS: +Implements the OUT string instruction and side effects. +****************************************************************************/ +void outs(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + + case 2: + while (count--) { + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + case 4: + while (count--) { + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 2: + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 4: + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + break; + } + M.x86.R_SI += inc; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Address to fetch word from + +REMARKS: +Fetches a word from emulator memory using an absolute address. +****************************************************************************/ +u16 mem_access_word(int addr) +{ +DB( if (CHECK_MEM_ACCESS()) + x86emu_check_mem_access(addr);) + return (*sys_rdw)(addr); +} + +/**************************************************************************** +REMARKS: +Pushes a word onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_word(u16 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 2; + (*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pushes a long onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_long(u32 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 4; + (*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pops a word from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u16 pop_word(void) +{ + register u16 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 2; + return res; +} + +/**************************************************************************** +REMARKS: +Pops a long from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u32 pop_long(void) +{ + register u32 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 4; + return res; +} + diff --git a/src/nvidia/arch/nvalloc/unix/x86emu/sys.c b/src/nvidia/arch/nvalloc/unix/x86emu/sys.c new file mode 100644 index 0000000000..9a5527f659 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/x86emu/sys.c @@ -0,0 +1,663 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* programmed I/O and memory access. Included in this module +* are default functions with limited usefulness. For real +* uses these functions will most likely be overriden by the +* user library. +* +****************************************************************************/ + +#include "x86emu/x86emu.h" +#include "x86emu/x86emui.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/prim_ops.h" +#ifndef NO_SYS_HEADERS +#include +#endif +/*------------------------- Global Variables ------------------------------*/ + +X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ +X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*----------------------------- Implementation ----------------------------*/ +#if defined(__alpha__) || defined(__alpha) +/* to cope with broken egcs-1.1.2 :-(((( */ + +#define ALPHA_UALOADS +/* + * inline functions to do unaligned accesses + * from linux/include/asm-alpha/unaligned.h + */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; +#endif + +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extql %0,%2,%0\n\t" + "extqh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(7+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extll %0,%2,%0\n\t" + "extlh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(3+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extwl %0,%2,%0\n\t" + "extwh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(1+(char *) r11))); + return r1 | r2; +#endif +} + +/* + * Elemental unaligned stores + */ + +static __inline__ void stq_u(unsigned long r5, unsigned long * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "insqh %6,%7,%5\n\t" + "insql %6,%7,%4\n\t" + "mskqh %3,%7,%3\n\t" + "mskql %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(7+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stl_u(unsigned long r5, unsigned int * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inslh %6,%7,%5\n\t" + "insll %6,%7,%4\n\t" + "msklh %3,%7,%3\n\t" + "mskll %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(3+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stw_u(unsigned long r5, unsigned short * r11) +{ +#if defined(__GNUC__) && ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 91)) + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inswh %6,%7,%5\n\t" + "inswl %6,%7,%4\n\t" + "mskwh %3,%7,%3\n\t" + "mskwl %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(1+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +#elif defined(__GNUC__) && ((__GNUC__ < 3)) && \ + (defined (__ia64__) || defined (ia64__)) +#define IA64_UALOADS +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ unsigned long +__uldq (const unsigned long * r11) +{ + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldl (const unsigned int * r11) +{ + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldw (const unsigned short * r11) +{ + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +} + +static __inline__ void +ustq (unsigned long r5, unsigned long * r11) +{ + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustl (unsigned long r5, unsigned int * r11) +{ + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustw (unsigned long r5, unsigned short * r11) +{ + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +} + +#endif + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. +****************************************************************************/ +u8 X86API rdb( + u32 addr) +{ + u8 val; + + if (addr > M.mem_size - 1) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } + val = *(u8*)(M.mem_base + addr); +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 1 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. +****************************************************************************/ +u16 X86API rdw( + u32 addr) +{ + u16 val = 0; + + if (addr > M.mem_size - 2) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + val = (*(u8*)(M.mem_base + addr) | + (*(u8*)(M.mem_base + addr + 1) << 8)); + } + else +#endif +#if defined(ALPHA_UALOADS) + val = ldw_u((u16*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + val = uldw((u16*)(M.mem_base + addr)); +#else + val = *(u16*)(M.mem_base + addr); +#endif +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 2 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. +REMARKS: +Reads a long value from the emulator memory. +****************************************************************************/ +u32 X86API rdl( + u32 addr) +{ + u32 val = 0; + + if (addr > M.mem_size - 4) { + DB(NV_PRINTF(LEVEL_INFO, "mem_read: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + val = (*(u8*)(M.mem_base + addr + 0) | + (*(u8*)(M.mem_base + addr + 1) << 8) | + (*(u8*)(M.mem_base + addr + 2) << 16) | + (*(u8*)(M.mem_base + addr + 3) << 24)); + } + else +#endif +#if defined(ALPHA_UALOADS) + val = ldl_u((u32*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + val = uldl((u32*)(M.mem_base + addr)); +#else + val = *(u32*)(M.mem_base + addr); +#endif +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 4 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. +****************************************************************************/ +void X86API wrb( + u32 addr, + u8 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 1 <- %#x\n", addr, val);) + if (addr > M.mem_size - 1) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } + *(u8*)(M.mem_base + addr) = val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. +****************************************************************************/ +void X86API wrw( + u32 addr, + u16 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 2 <- %#x\n", addr, val);) + if (addr > M.mem_size - 2) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif +#if defined(ALPHA_UALOADS) + stw_u(val,(u16*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + ustw(val,(u16*)(M.mem_base + addr)); +#else + *(u16*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a long value to emulator memory. +****************************************************************************/ +void X86API wrl( + u32 addr, + u32 val) +{ +DB( if (DEBUG_MEM_TRACE()) + NV_PRINTF(LEVEL_INFO, "%#08x 4 <- %#x\n", addr, val);) + if (addr > M.mem_size - 4) { + DB(NV_PRINTF(LEVEL_INFO, "mem_write: address %#x out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif +#if defined(ALPHA_UALOADS) + stl_u(val,(u32*)(M.mem_base + addr)); +#elif defined(IA64_UALOADS) + ustl(val,(u32*)(M.mem_base + addr)); +#else + *(u32*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO byte read function. Doesn't perform real inb. +****************************************************************************/ +static u8 X86API p_inb( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inb %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO word read function. Doesn't perform real inw. +****************************************************************************/ +static u16 X86API p_inw( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inw %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO long read function. Doesn't perform real inl. +****************************************************************************/ +static u32 X86API p_inl( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "inl %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO byte write function. Doesn't perform real outb. +****************************************************************************/ +static void X86API p_outb( + X86EMU_pioAddr addr, + u8 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outb %#02x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO word write function. Doesn't perform real outw. +****************************************************************************/ +static void X86API p_outw( + X86EMU_pioAddr addr, + u16 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outw %#04x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO ;ong write function. Doesn't perform real outl. +****************************************************************************/ +static void X86API p_outl( + X86EMU_pioAddr addr, + u32 val) +{ +DB( if (DEBUG_IO_TRACE()) + NV_PRINTF(LEVEL_INFO, "outl %#08x -> %#04x \n", val, addr);) + return; +} + +/*------------------------- Global Variables ------------------------------*/ + +u8 (X86APIP sys_rdb)(u32 addr) = rdb; +u16 (X86APIP sys_rdw)(u32 addr) = rdw; +u32 (X86APIP sys_rdl)(u32 addr) = rdl; +void (X86APIP sys_wrb)(u32 addr,u8 val) = wrb; +void (X86APIP sys_wrw)(u32 addr,u16 val) = wrw; +void (X86APIP sys_wrl)(u32 addr,u32 val) = wrl; +u8 (X86APIP sys_inb)(X86EMU_pioAddr addr) = p_inb; +u16 (X86APIP sys_inw)(X86EMU_pioAddr addr) = p_inw; +u32 (X86APIP sys_inl)(X86EMU_pioAddr addr) = p_inl; +void (X86APIP sys_outb)(X86EMU_pioAddr addr, u8 val) = p_outb; +void (X86APIP sys_outw)(X86EMU_pioAddr addr, u16 val) = p_outw; +void (X86APIP sys_outl)(X86EMU_pioAddr addr, u32 val) = p_outl; + +/*----------------------------- Setup -------------------------------------*/ + +/**************************************************************************** +PARAMETERS: +funcs - New memory function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +memory space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupMemFuncs( + X86EMU_memFuncs *funcs) +{ + sys_rdb = funcs->rdb; + sys_rdw = funcs->rdw; + sys_rdl = funcs->rdl; + sys_wrb = funcs->wrb; + sys_wrw = funcs->wrw; + sys_wrl = funcs->wrl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New programmed I/O function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +I/O space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupPioFuncs( + X86EMU_pioFuncs *funcs) +{ + sys_inb = funcs->inb; + sys_inw = funcs->inw; + sys_inl = funcs->inl; + sys_outb = funcs->outb; + sys_outw = funcs->outw; + sys_outl = funcs->outl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New interrupt vector table to make active + +REMARKS: +This function is used to set the pointers to functions which handle +interrupt processing in the emulator, allowing the user application to +hook interrupts as necessary for their application. Any interrupts that +are not hooked by the user application, and reflected and handled internally +in the emulator via the interrupt vector table. This allows the application +to get control when the code being emulated executes specific software +interrupts. +****************************************************************************/ +void X86EMU_setupIntrFuncs( + X86EMU_intrFuncs funcs[]) +{ + int i; + + for (i=0; i < 256; i++) + _X86EMU_intrTab[i] = NULL; + if (funcs) { + for (i = 0; i < 256; i++) + _X86EMU_intrTab[i] = funcs[i]; + } +} + +/**************************************************************************** +PARAMETERS: +int - New software interrupt to prepare for + +REMARKS: +This function is used to set up the emulator state to exceute a software +interrupt. This can be used by the user application code to allow an +interrupt to be hooked, examined and then reflected back to the emulator +so that the code in the emulator will continue processing the software +interrupt as per normal. This essentially allows system code to actively +hook and handle certain software interrupts as necessary. +****************************************************************************/ +void X86EMU_prepareForInt( + int num) +{ + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(num * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(num * 4); + M.x86.intr = 0; +} diff --git a/src/nvidia/exports_link_command.txt b/src/nvidia/exports_link_command.txt index 7958588614..16d06bbef6 100644 --- a/src/nvidia/exports_link_command.txt +++ b/src/nvidia/exports_link_command.txt @@ -16,6 +16,7 @@ --undefined=rm_init_adapter --undefined=rm_init_private_state --undefined=rm_init_rm +--undefined=rm_vgpu_vfio_set_driver_vm --undefined=rm_ioctl --undefined=rm_is_supported_device --undefined=rm_is_supported_pci_device @@ -63,11 +64,13 @@ --undefined=rm_dma_buf_put_client_and_device --undefined=rm_gpu_ops_address_space_destroy --undefined=rm_gpu_ops_memory_cpu_ummap +--undefined=rm_gpu_ops_tsg_destroy --undefined=rm_gpu_ops_channel_destroy --undefined=rm_gpu_ops_memory_free --undefined=rm_gpu_ops_create_session --undefined=rm_gpu_ops_memory_alloc_sys --undefined=rm_gpu_ops_address_space_create +--undefined=rm_gpu_ops_tsg_allocate --undefined=rm_gpu_ops_channel_allocate --undefined=rm_gpu_ops_memory_alloc_fb --undefined=rm_gpu_ops_memory_cpu_map @@ -118,6 +121,16 @@ --undefined=rm_gpu_ops_paging_channel_push_stream --undefined=rm_gpu_ops_device_create --undefined=rm_gpu_ops_device_destroy +--undefined=rm_gpu_ops_ccsl_acquire_encryption_iv +--undefined=rm_gpu_ops_ccsl_sign +--undefined=rm_gpu_ops_ccsl_encrypt +--undefined=rm_gpu_ops_ccsl_encrypt_with_iv +--undefined=rm_gpu_ops_ccsl_context_init +--undefined=rm_gpu_ops_ccsl_context_clear +--undefined=rm_gpu_ops_ccsl_log_device_encryption +--undefined=rm_gpu_ops_ccsl_rotate_iv +--undefined=rm_gpu_ops_ccsl_decrypt +--undefined=rm_gpu_ops_ccsl_query_message_pool --undefined=rm_log_gpu_crash --undefined=rm_kernel_rmapi_op --undefined=nv_get_hypervisor_type diff --git a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h index 335cd93789..5670473f87 100644 --- a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h +++ b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h @@ -99,6 +99,8 @@ struct AccessCounterBuffer { PEVENTNOTIFICATION *(*__accesscntrGetNotificationListPtr__)(struct AccessCounterBuffer *); struct NotifShare *(*__accesscntrGetNotificationShare__)(struct AccessCounterBuffer *); NvBool (*__accesscntrAccessCallback__)(struct AccessCounterBuffer *, struct RsClient *, void *, RsAccessRight); + struct MEMORY_DESCRIPTOR *pUvmAccessCntrAllocMemDesc; + NvU32 accessCounterIndex; }; #ifndef __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ diff --git a/src/nvidia/generated/g_allclasses.h b/src/nvidia/generated/g_allclasses.h index 9a10516940..1ab9f5c3c2 100644 --- a/src/nvidia/generated/g_allclasses.h +++ b/src/nvidia/generated/g_allclasses.h @@ -47,6 +47,7 @@ #include // NV01_MEMORY_SYSTEM #include // NV01_MEMORY_LOCAL_PRIVILEGED #include // NV01_MEMORY_LOCAL_USER +#include // NV_MEMORY_EXTENDED_USER #include // NV01_MEMORY_VIRTUAL #include // NV_MEMORY_MAPPER #include // NV01_MEMORY_LOCAL_PHYSICAL @@ -58,6 +59,7 @@ #include // NV01_MEMORY_LIST_FBMEM #include // NV01_MEMORY_LIST_OBJECT #include // NV01_MEMORY_FLA +#include // NV_CE_UTILS #include // NV_MEMORY_FABRIC #include // FABRIC_VASPACE_A #include // NV_MEMORY_MULTICAST_FABRIC @@ -123,6 +125,7 @@ #include // NV50_THIRD_PARTY_P2P #include // FERMI_TWOD_A #include // FERMI_VASPACE_A +#include // HOPPER_SEC2_WORK_LAUNCH_A #include // GF100_HDACODEC #include // NVB8B0_VIDEO_DECODER #include // NVC4B0_VIDEO_DECODER @@ -176,7 +179,9 @@ #include // NV0060_SYNC_GPU_BOOST #include // GP100_UVM_SW #include // NV_EVENT_BUFFER +#include // NV_CONFIDENTIAL_COMPUTE #include // NV_COUNTER_COLLECTION_UNIT +#include // NV_SEMAPHORE_SURFACE #else // defined(SDK_ALL_CLASSES_INCLUDE_FULL_HEADER) @@ -271,6 +276,10 @@ #define NV1_MEMORY_USER (0x00000040) // alias #endif +#ifndef NV_MEMORY_EXTENDED_USER +#define NV_MEMORY_EXTENDED_USER (0x00000042) +#endif + #ifndef NV01_MEMORY_VIRTUAL #define NV01_MEMORY_VIRTUAL (0x00000070) #endif @@ -321,6 +330,10 @@ #define NV01_MEMORY_FLA (0x000000f3) #endif +#ifndef NV_CE_UTILS +#define NV_CE_UTILS (0x00000050) +#endif + #ifndef NV_MEMORY_FABRIC #define NV_MEMORY_FABRIC (0x000000f8) #endif @@ -608,6 +621,10 @@ #define FERMI_VASPACE_A (0x000090f1) #endif +#ifndef HOPPER_SEC2_WORK_LAUNCH_A +#define HOPPER_SEC2_WORK_LAUNCH_A (0x0000cba2) +#endif + #ifndef GF100_HDACODEC #define GF100_HDACODEC (0x000090ec) #endif @@ -820,9 +837,17 @@ #define NV_EVENT_BUFFER (0x000090cd) #endif +#ifndef NV_CONFIDENTIAL_COMPUTE +#define NV_CONFIDENTIAL_COMPUTE (0x0000cb33) +#endif + #ifndef NV_COUNTER_COLLECTION_UNIT #define NV_COUNTER_COLLECTION_UNIT (0x0000cbca) #endif +#ifndef NV_SEMAPHORE_SURFACE +#define NV_SEMAPHORE_SURFACE (0x000000da) +#endif + #endif // defined(SDK_ALL_CLASSES_INCLUDE_FULL_HEADER) diff --git a/src/nvidia/generated/g_bindata.c b/src/nvidia/generated/g_bindata.c index 0bbb5217fa..05337d9358 100644 --- a/src/nvidia/generated/g_bindata.c +++ b/src/nvidia/generated/g_bindata.c @@ -56,8 +56,11 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -85,8 +88,11 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -112,8 +118,11 @@ BINDATA_CONST struct BINDATA_STORAGE_PVT_ALL g_bindata_pvt = #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -142,8 +151,11 @@ const NvU32 g_bindata_pvt_count = sizeof(g_bindata_pvt) / sizeof(BINDATA_STORAGE #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c" +#include "g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c index ffead9b0bd..b4b36687b4 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c @@ -34,1634 +34,1891 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 37120 -// COMPRESSED SIZE (bytes): 25955 +// DATA SIZE (bytes): 54784 +// COMPRESSED SIZE (bytes): 30079 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data[] = { - 0xed, 0xfd, 0x63, 0xac, 0x6d, 0x41, 0xff, 0x38, 0x78, 0x1e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x75, 0x8f, 0x6d, 0xdb, 0xd6, 0x3d, 0xb6, 0x31, 0xcf, 0xbf, 0xfb, - 0x37, 0x99, 0xce, 0x93, 0xe9, 0xcc, 0x8b, 0xee, 0x64, 0x5e, 0xf4, 0xfd, 0x24, 0xdf, 0x14, 0x76, - 0x25, 0xb5, 0x77, 0xed, 0xbd, 0x92, 0x55, 0xb5, 0xaa, 0xb2, 0x01, 0x00, 0xfe, 0x9f, 0xed, 0x36, - 0x42, 0x4d, 0x83, 0x05, 0x8a, 0xe0, 0x2c, 0xe4, 0x73, 0x61, 0x56, 0x05, 0x2b, 0x51, 0x2d, 0xf1, - 0x57, 0xf0, 0xc8, 0x38, 0xa4, 0x12, 0xfa, 0x9e, 0xb2, 0xdd, 0xa7, 0x3d, 0x7d, 0x70, 0x80, 0x9b, - 0x30, 0x77, 0xa2, 0xce, 0xd7, 0x39, 0x26, 0xd4, 0x2e, 0x42, 0x25, 0x4e, 0xea, 0xee, 0x4f, 0x40, - 0xf1, 0x93, 0x03, 0x5e, 0x97, 0x1f, 0xf5, 0x95, 0xd1, 0xa0, 0xf8, 0x5b, 0xf6, 0x7b, 0xd7, 0x69, - 0x57, 0xea, 0x58, 0x2c, 0x75, 0xe8, 0x1f, 0xc8, 0x1a, 0x9f, 0x34, 0x9b, 0x6b, 0x8a, 0xcd, 0xf6, - 0x4d, 0x61, 0x4b, 0xec, 0x64, 0x96, 0x40, 0xc8, 0x86, 0x30, 0xbe, 0xc6, 0x5a, 0x6c, 0xaf, 0x8d, - 0xf2, 0x22, 0xc5, 0x8b, 0xe1, 0x9a, 0xd3, 0xa3, 0x2b, 0x1d, 0x61, 0xee, 0x24, 0x74, 0x7d, 0xeb, - 0x91, 0xae, 0x53, 0x48, 0xcd, 0x3b, 0x41, 0x30, 0x4e, 0x99, 0xc1, 0xa8, 0xb9, 0x25, 0x3f, 0xb9, - 0x43, 0x12, 0x78, 0x51, 0x37, 0x28, 0x0a, 0x18, 0xc3, 0x59, 0x0e, 0x4d, 0x8c, 0x06, 0xff, 0x25, - 0x8e, 0x95, 0xd1, 0xb0, 0x60, 0x22, 0x76, 0xeb, 0x8b, 0x75, 0x44, 0xcd, 0x96, 0x09, 0x89, 0xc3, - 0xd6, 0xb2, 0x87, 0x27, 0xa4, 0x12, 0x8b, 0x09, 0xf9, 0xf9, 0x07, 0x30, 0xfd, 0x92, 0x2e, 0xe4, - 0x9a, 0xc4, 0x97, 0xd9, 0xde, 0x9b, 0x34, 0x7e, 0xb0, 0x4f, 0x09, 0xc2, 0x2a, 0x1a, 0xca, 0xc4, - 0x81, 0x5a, 0x86, 0x80, 0x85, 0xd1, 0x75, 0x60, 0x1d, 0x9b, 0xc2, 0x73, 0x37, 0x8c, 0xc8, 0xeb, - 0xd1, 0xbc, 0x55, 0x8f, 0x31, 0x5d, 0x5f, 0xe4, 0x26, 0x4e, 0xb7, 0x0e, 0x17, 0x52, 0xb0, 0x95, - 0x75, 0x3d, 0xb8, 0x0d, 0x54, 0x35, 0x22, 0x48, 0x02, 0xa7, 0x6c, 0xbf, 0x4c, 0x40, 0xec, 0xd6, - 0x35, 0x41, 0x95, 0xb1, 0x98, 0xc6, 0x25, 0xaf, 0xd5, 0x77, 0x9b, 0x94, 0x9b, 0x50, 0x66, 0x08, - 0x18, 0xea, 0xf1, 0xd5, 0x51, 0xd7, 0xd3, 0x93, 0x96, 0x00, 0x4e, 0xe7, 0x3a, 0x5f, 0xaa, 0xc8, - 0x9f, 0x72, 0xd3, 0x71, 0x08, 0xcb, 0xec, 0x64, 0x74, 0x70, 0x2a, 0x3b, 0x82, 0x06, 0x41, 0xdd, - 0x1e, 0x52, 0xc1, 0x33, 0x16, 0x26, 0x0e, 0xb0, 0x32, 0xb7, 0xe8, 0xac, 0x3b, 0x16, 0x6d, 0xc9, - 0x52, 0x8a, 0x6d, 0xb3, 0x1a, 0x82, 0x61, 0xc8, 0x67, 0xe2, 0xa7, 0xcf, 0x2f, 0x04, 0x5b, 0xd5, - 0xbc, 0x2f, 0x0f, 0x9f, 0x0a, 0x8e, 0xf5, 0xcd, 0x0a, 0x62, 0x53, 0x6b, 0x7c, 0x94, 0x80, 0xbd, - 0xd0, 0xd1, 0x85, 0xed, 0xf7, 0x25, 0xbc, 0xbe, 0xfd, 0x51, 0xca, 0xa0, 0x6f, 0xa1, 0xb2, 0xfd, - 0xf7, 0x79, 0x9b, 0x50, 0x5c, 0x8a, 0x6d, 0x47, 0x82, 0xd7, 0x07, 0xe9, 0x92, 0x3b, 0x80, 0x50, - 0x2c, 0xe2, 0x0c, 0x4d, 0x8d, 0xb3, 0x2f, 0x2d, 0xde, 0x3d, 0xba, 0x97, 0xf0, 0x3c, 0x73, 0xad, - 0x89, 0x2a, 0xed, 0x53, 0x49, 0x0e, 0xf5, 0xb0, 0x45, 0xa0, 0x5a, 0x79, 0xe9, 0xd7, 0x74, 0x96, - 0x06, 0xde, 0x36, 0xd0, 0xad, 0x06, 0xd3, 0x11, 0xc5, 0xd3, 0x8f, 0x3b, 0x33, 0xe1, 0xb4, 0xfa, - 0xad, 0xa5, 0x2d, 0x0f, 0xb7, 0xb0, 0x76, 0xde, 0x76, 0x6a, 0x84, 0xbf, 0x55, 0xb8, 0x46, 0xad, - 0xbb, 0x48, 0x8c, 0xf8, 0x91, 0x3f, 0xb6, 0x5c, 0xe7, 0x75, 0xb5, 0x15, 0x0a, 0x7c, 0xd1, 0xad, - 0x0d, 0x0c, 0x6c, 0x48, 0x05, 0xe4, 0xb9, 0x53, 0xb8, 0xb1, 0x98, 0x74, 0x17, 0xab, 0xa0, 0x92, - 0x95, 0xd1, 0x41, 0xb2, 0x8e, 0x81, 0xd1, 0xa5, 0x7d, 0x6f, 0x11, 0x5b, 0xfb, 0x4a, 0xfe, 0xd2, - 0x19, 0x39, 0xd7, 0x45, 0x42, 0x3d, 0x7b, 0x2e, 0x9d, 0x23, 0x2f, 0x9e, 0xda, 0x43, 0xfd, 0xf1, - 0x07, 0xcb, 0x7c, 0xde, 0x72, 0x4e, 0xce, 0x7f, 0x03, 0x3f, 0x28, 0xa7, 0x96, 0x7b, 0x22, 0x00, - 0x97, 0xa5, 0x29, 0x4b, 0x20, 0x86, 0xdc, 0x5d, 0xd6, 0x20, 0x6c, 0xbb, 0x51, 0xe6, 0x79, 0x65, - 0xd3, 0x0f, 0x8d, 0x3d, 0x32, 0xdf, 0x8b, 0x46, 0x7c, 0x88, 0x38, 0xc3, 0x97, 0x31, 0x7a, 0x08, - 0xa5, 0x0e, 0xf4, 0x24, 0xd2, 0xa7, 0xd5, 0x7f, 0x33, 0x71, 0x31, 0xd6, 0x44, 0x01, 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0xf8, 0x36, 0x76, 0xc6, 0x26, 0x3a, 0xff, 0x35, 0x5f, 0x44, 0x48, 0xe8, + 0x7f, 0xe6, 0xff, 0x87, 0xf9, 0x7f, 0x1e, 0xe9, 0xff, 0x13, 0x0c, 0xff, 0xa9, 0xe3, 0xff, 0x5f, + 0xbc, 0x4d, 0xd0, 0xff, 0x09, 0xb4, 0xff, 0x04, 0xc1, 0x7f, 0xc2, 0xe5, 0x3f, 0x39, 0xf8, 0xff, + 0x97, 0x5c, 0xff, 0xa9, 0x03, 0x01, 0xfe, 0x7f, 0x5e, 0x9e, 0xf2, 0xff, 0x44, 0x2e, 0x54, 0x80, + 0xff, 0xf5, 0xf5, 0xc7, 0xfc, 0xef, 0xf2, 0x80, 0x80, 0xff, 0x1f, 0x2f, 0x9f, 0xf6, 0xbf, 0xab, + 0xa7, 0xff, 0x27, 0x32, 0xfe, 0x13, 0x62, 0xff, 0x09, 0xf1, 0xff, 0x84, 0xc4, 0x7f, 0x42, 0xf2, + 0x7f, 0x9e, 0x93, 0xfe, 0x9f, 0x52, 0xe6, 0xbf, 0xf2, 0xc8, 0xff, 0x6f, 0x79, 0x74, 0xfe, 0xe7, + 0x3d, 0x00, 0xf8, 0x4f, 0x13, 0x03, 0x28, 0x89, 0xd0, 0x03, 0x08, 0xfd, 0xa7, 0x79, 0x0d, 0x1c, + 0x2d, 0x9c, 0xcd, 0x6d, 0x4c, 0x9c, 0x2d, 0x8c, 0xf0, 0x4d, 0x1c, 0x1d, 0xed, 0x1c, 0x21, 0xff, + 0x0f, 0xe6, 0xfe, 0xff, 0xaf, 0xff, 0x07, 0x01, 0xc2, 0x94, 0x48, 0x00, 0xd6, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1671,8 +1928,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 37120, // uncompressed data size (bytes) - 25955, // compressed data size (bytes) + 54784, // uncompressed data size (bytes) + 30079, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1694,8 +1951,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x03, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0xa4, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x9f, 0x5d, 0x93, 0xe9, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x03, 0xe2, 0x04, 0x08, 0x13, 0x4c, 0x94, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x2a, 0x51, 0x87, 0x6a, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1723,1634 +1980,1892 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 37120 -// COMPRESSED SIZE (bytes): 25956 +// DATA SIZE (bytes): 54784 +// COMPRESSED SIZE (bytes): 30081 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_prod_data[] = { - 0xed, 0xdd, 0x63, 0xac, 0xb4, 0xcd, 0xff, 0x20, 0xf8, 0x63, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xe3, 0x3e, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xfb, 0xdc, 0xe7, 0xec, 0x33, 0x33, - 0xff, 0xcd, 0x4e, 0x7e, 0xbb, 0x93, 0x7d, 0xb1, 0x9b, 0xec, 0x8b, 0x7d, 0x3e, 0xc9, 0x37, 0x85, - 0xae, 0xa4, 0xba, 0xab, 0x73, 0x75, 0x5f, 0x55, 0x5d, 0x95, 0x06, 0x00, 0xf8, 0xff, 0xb7, 0x1e, - 0x3f, 0x45, 0x13, 0x45, 0x44, 0x3e, 0x09, 0x01, 0xae, 0xad, 0x57, 0xb6, 0x9d, 0xc5, 0x6e, 0x74, - 0x41, 0x8e, 0xa0, 0x4f, 0x52, 0x42, 0x8b, 0x49, 0x34, 0x4c, 0x5e, 0xaf, 0x03, 0x88, 0x0f, 0x5d, - 0x73, 0xe2, 0x76, 0x05, 0x5e, 0x3a, 0xf0, 0x9f, 0x1f, 0x11, 0x4e, 0x3d, 0x62, 0x19, 0xc9, 0x9b, - 0x66, 0xdb, 0xaa, 0xd9, 0xb7, 0xe1, 0xe1, 0x44, 0x85, 0xd8, 0x33, 0x9d, 0x1d, 0x65, 0x7f, 0x45, - 0x62, 0x5a, 0xd0, 0x29, 0x39, 0x25, 0x25, 0xc3, 0x15, 0xd3, 0xec, 0x2f, 0xbd, 0x89, 0xa5, 0x83, - 0x90, 0x82, 0x16, 0x49, 0xc8, 0x0d, 0xdd, 0x38, 0xf7, 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defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 37120, // uncompressed data size (bytes) - 25956, // compressed data size (bytes) + 54784, // uncompressed data size (bytes) + 30081, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3383,8 +3898,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x03, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0xa4, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x9f, 0x5d, 0x93, 0xe9, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x03, 0xe2, 0x04, 0x08, 0x13, 0x4c, 0x94, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x2a, 0x51, 0x87, 0x6a, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3417,55 +3932,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xf3, 0x8f, 0x9c, 0x44, 0xbc, 0x38, 0x1a, 0x8e, 0x17, 0xff, 0xa9, - 0x02, 0xad, 0x83, 0x67, 0x00, 0xd0, 0x2a, 0xef, 0xf0, 0x98, 0x99, 0x7a, 0xb5, 0x65, 0x89, 0x08, - 0x7e, 0xc2, 0xfe, 0x14, 0x86, 0x63, 0xf9, 0xe2, 0x4b, 0xf2, 0x22, 0x5d, 0xbb, 0x91, 0x1d, 0xba, - 0x6e, 0x8f, 0xdb, 0x3c, 0xbc, 0xba, 0xf3, 0x59, 0x3d, 0x2c, 0x73, 0x87, 0xb2, 0x16, 0xe3, 0x7e, - 0x46, 0x68, 0x0d, 0xc5, 0x2e, 0x0b, 0x93, 0xa9, 0xf1, 0x24, 0x76, 0x79, 0x0b, 0xce, 0x29, 0xd6, - 0x69, 0xd5, 0x0e, 0xbb, 0x7a, 0xc2, 0xe8, 0x53, 0xcb, 0xaa, 0x2b, 0x28, 0x1e, 0xf8, 0xd3, 0xa6, - 0xf9, 0x10, 0xb7, 0xac, 0xaa, 0x6a, 0x35, 0x29, 0x3f, 0xea, 0x2c, 0x05, 0xd5, 0xe2, 0x63, 0x0a, - 0x57, 0x6e, 0xbb, 0xb4, 0x4f, 0xa0, 0xdb, 0x8b, 0x9a, 0x5f, 0xfb, 0xb0, 0x58, 0xca, 0x7f, 0xea, - 0x2a, 0xda, 0x12, 0xe5, 0xb4, 0x4b, 0x4b, 0x49, 0xc2, 0x83, 0x73, 0xd4, 0x2c, 0x78, 0xd2, 0xcc, - 0xd1, 0x9c, 0x46, 0x36, 0xe6, 0x8d, 0x74, 0xa2, 0x1f, 0x17, 0xd4, 0x87, 0x00, 0x9c, 0xe5, 0x3a, - 0x1a, 0x3b, 0xa7, 0x13, 0xd4, 0x6e, 0x1d, 0x27, 0x1d, 0x77, 0xb3, 0x80, 0xae, 0xf3, 0xfa, 0x60, - 0xdf, 0xba, 0x7f, 0x95, 0x19, 0xe5, 0xa8, 0x05, 0x90, 0x16, 0x52, 0x22, 0x86, 0xac, 0xa6, 0xf6, - 0x95, 0x83, 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0x9f, 0x40, 0x74, + 0xcf, 0xaa, 0x5e, 0x0e, 0x2c, 0xd1, 0x97, 0xb3, 0x38, 0x21, 0x71, 0x4d, 0x7b, 0x0c, 0x45, 0x33, + 0x49, 0x3e, 0x84, 0xae, 0x09, 0x85, 0x63, 0xad, 0xd5, 0xb6, 0x56, 0x81, 0xcf, 0x6c, 0x28, 0x2f, + 0xcc, 0x30, 0xf4, 0x57, 0xc3, 0x75, 0x25, 0x36, 0x94, 0x3c, 0x56, 0x7c, 0x34, 0x90, 0x5a, 0xc6, + 0xcc, 0x6b, 0x7a, 0x3f, 0x74, 0x66, 0xf3, 0xbf, 0xa0, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3498,55 +4013,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_prod_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xcc, 0x44, 0xec, 0x51, 0xab, 0xd7, 0xca, 0xc2, 0x90, 0xc1, 0xe6, - 0xba, 0xfd, 0x01, 0x3b, 0x5b, 0xa9, 0x86, 0x4b, 0x43, 0xcd, 0x21, 0x84, 0xb6, 0x8f, 0x60, 0xe1, - 0x3b, 0xce, 0x70, 0x73, 0x81, 0xeb, 0x92, 0x5d, 0x62, 0xf6, 0x4c, 0xe0, 0x87, 0x0f, 0x16, 0x02, - 0x87, 0xee, 0x43, 0xc3, 0x97, 0x55, 0x34, 0x77, 0x9d, 0x6c, 0x4c, 0x31, 0x9b, 0x7d, 0x7f, 0xb1, - 0x45, 0xa2, 0x4f, 0x75, 0x27, 0x12, 0x77, 0xcb, 0x53, 0xf6, 0x67, 0x2a, 0xdf, 0x63, 0x99, 0x94, - 0x8b, 0x0b, 0xa8, 0xb2, 0xa2, 0x81, 0xcb, 0xd0, 0x5f, 0x0b, 0x19, 0xe3, 0x1d, 0x93, 0xf7, 0xf4, - 0xaf, 0x95, 0x2e, 0x3c, 0x85, 0x5c, 0x33, 0x9c, 0x3a, 0xf9, 0x74, 0xed, 0x10, 0x43, 0x02, 0x5c, - 0x26, 0x85, 0xd4, 0x8c, 0x5f, 0xe0, 0xa0, 0x69, 0x54, 0xeb, 0x25, 0xe9, 0x98, 0x2b, 0xde, 0xd7, - 0xec, 0xb7, 0xed, 0xf3, 0xc5, 0xcd, 0xae, 0xa5, 0x14, 0xda, 0x0a, 0x11, 0x84, 0x52, 0x46, 0x20, - 0xc0, 0xaf, 0xe4, 0x34, 0x7c, 0x47, 0xd0, 0x7b, 0x8d, 0x61, 0xa2, 0x64, 0xb3, 0x0e, 0xc2, 0x5e, - 0x9a, 0x5c, 0x47, 0x96, 0xf0, 0x06, 0x17, 0xcd, 0xf0, 0xcf, 0x18, 0xc8, 0x2b, 0xb0, 0xdc, 0xbd, - 0x50, 0xc2, 0xc5, 0x44, 0xe4, 0x9d, 0xa9, 0x4a, 0x28, 0xfe, 0x12, 0x65, 0x05, 0xc4, 0xb6, 0x76, - 0xff, 0x14, 0x09, 0xc5, 0xab, 0x3c, 0xca, 0x3f, 0x8b, 0xe6, 0x0c, 0x0b, 0xa4, 0x52, 0xdc, 0xc9, - 0xfe, 0x8b, 0xfd, 0x8a, 0x07, 0x24, 0x5e, 0x99, 0x90, 0xb4, 0xf2, 0x8a, 0x62, 0xf2, 0xa2, 0x4a, - 0xaa, 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0xe3, 0x46, 0xf5, 0x9d, 0xce, 0xb9, - 0x5a, 0xf5, 0xd6, 0x05, 0x07, 0xeb, 0xfe, 0x2e, 0xc6, 0x9f, 0x5d, 0xcc, 0x43, 0x34, 0x28, 0xff, - 0x9f, 0xdc, 0x80, 0x09, 0xa8, 0x0e, 0x6f, 0xee, 0x42, 0x4a, 0x4b, 0xca, 0xf9, 0xb3, 0x28, 0x69, - 0xfa, 0x9a, 0xef, 0x22, 0x98, 0xd1, 0x4a, 0x91, 0x2c, 0xb7, 0xd3, 0xad, 0x30, 0x84, 0x0a, 0x84, - 0x41, 0x80, 0x26, 0xd1, 0x26, 0x1b, 0x51, 0xf1, 0xc0, 0x00, 0x03, 0x00, 0x00, + 0x01, 0x00, 0x03, 0xff, 0xfc, 0x34, 0xf8, 0xde, 0xcb, 0x27, 0x51, 0xa1, 0xb6, 0x89, 0xe8, 0x26, + 0x08, 0xab, 0xb1, 0xca, 0xeb, 0x6b, 0x24, 0x5e, 0x36, 0x40, 0x49, 0x59, 0x12, 0x5f, 0xa4, 0x0b, + 0xc1, 0xcb, 0xed, 0x28, 0x73, 0x33, 0x85, 0xa6, 0xcf, 0xa6, 0x7d, 0x84, 0x10, 0x37, 0x65, 0x26, + 0x0e, 0x7d, 0x13, 0xa3, 0x2b, 0x9c, 0x66, 0x5f, 0xb9, 0x0a, 0x49, 0x14, 0x17, 0x53, 0xfc, 0xcb, + 0x00, 0xd9, 0xa3, 0x4e, 0x36, 0xf3, 0x79, 0x9a, 0xef, 0xe0, 0x07, 0xde, 0x9a, 0x1d, 0xbc, 0x46, + 0x79, 0x33, 0x4a, 0x4e, 0x77, 0x4c, 0x45, 0x27, 0xaf, 0xc9, 0x7c, 0x00, 0x31, 0x18, 0x8c, 0x44, + 0xd1, 0x9b, 0x76, 0xe1, 0xa1, 0x0e, 0x97, 0x93, 0xf9, 0xbc, 0x01, 0xa1, 0x0e, 0x8d, 0x94, 0x1a, + 0x0c, 0x8c, 0x82, 0x05, 0x5d, 0xa5, 0x91, 0x92, 0xee, 0x89, 0x8c, 0xe1, 0x73, 0xd9, 0x1e, 0x2a, + 0x4c, 0xb1, 0x91, 0x14, 0xf6, 0x44, 0x2a, 0x14, 0x8f, 0xd4, 0xb6, 0x4b, 0xc5, 0xfd, 0x41, 0xf0, + 0x5b, 0x2c, 0xf1, 0xec, 0x9a, 0x52, 0x73, 0x81, 0xa7, 0x1a, 0x0c, 0xda, 0x5b, 0x35, 0x67, 0x2a, + 0xd5, 0x83, 0xb9, 0xf6, 0xa9, 0xbe, 0xec, 0x1f, 0xb6, 0xac, 0x50, 0x13, 0x72, 0x8e, 0xe4, 0xca, + 0x52, 0xd6, 0xd2, 0x8e, 0x29, 0x48, 0xfe, 0xb7, 0x44, 0x4c, 0x1e, 0xfe, 0x92, 0x64, 0xda, 0x90, + 0x01, 0x3e, 0x1e, 0xdf, 0x3f, 0x94, 0x9e, 0x34, 0xf4, 0xd0, 0x0c, 0xfb, 0xc6, 0x10, 0xb3, 0xa3, + 0xb0, 0x28, 0x3f, 0x01, 0x8f, 0x0f, 0x5f, 0xf4, 0x1e, 0x3b, 0xf0, 0x48, 0x27, 0x3a, 0x5c, 0xcb, + 0x2f, 0xa7, 0x75, 0x00, 0x68, 0x6f, 0x11, 0xdc, 0x5e, 0x11, 0x55, 0x40, 0x5b, 0xab, 0x61, 0x6f, + 0x23, 0x50, 0x7a, 0xad, 0x72, 0xfb, 0x17, 0x2f, 0x2d, 0x71, 0x83, 0x4b, 0xd5, 0x88, 0xab, 0x75, + 0x9c, 0x5b, 0x8a, 0x4c, 0x81, 0x96, 0x51, 0xb1, 0x64, 0x9d, 0x41, 0x88, 0x87, 0x98, 0xae, 0xad, + 0x27, 0xa7, 0x27, 0x78, 0x70, 0x47, 0x34, 0xd0, 0xd1, 0x31, 0x12, 0xdf, 0x0b, 0x71, 0x10, 0x17, + 0x09, 0x6d, 0xdb, 0x40, 0xb4, 0x9d, 0xf1, 0x90, 0x0a, 0xeb, 0x13, 0x11, 0x8e, 0x57, 0x2c, 0x68, + 0x93, 0x4c, 0x2d, 0x03, 0x71, 0xb8, 0x44, 0xb8, 0x67, 0x56, 0x03, 0x42, 0x22, 0xee, 0xea, 0xc4, + 0x0e, 0x9b, 0x61, 0x28, 0xe2, 0x67, 0x17, 0xcb, 0xa3, 0x63, 0x63, 0xe4, 0x6e, 0xeb, 0x84, 0xe1, + 0x1d, 0xd3, 0x66, 0x74, 0x1b, 0xfc, 0x12, 0x78, 0x9d, 0x15, 0xd8, 0x57, 0x17, 0x30, 0x74, 0x7a, + 0x1b, 0x3e, 0xe3, 0x28, 0x4f, 0x04, 0xb9, 0xbe, 0x56, 0x7f, 0x02, 0x12, 0xdc, 0x1d, 0x8a, 0x6a, + 0xf4, 0x35, 0xf2, 0xbe, 0xc5, 0x83, 0x8e, 0x95, 0xa6, 0x7f, 0xb4, 0xed, 0x00, 0xa4, 0xaf, 0xbf, + 0xa6, 0x41, 0xfa, 0xc5, 0x5e, 0x2b, 0xf0, 0x07, 0xc9, 0x69, 0x2a, 0xf2, 0xa4, 0x46, 0x57, 0x44, + 0x59, 0x56, 0x29, 0x0b, 0x3e, 0xed, 0x5a, 0x22, 0xa7, 0x95, 0x4b, 0xb5, 0x5e, 0x7a, 0x82, 0xd4, + 0xb9, 0x6f, 0x6d, 0xee, 0x14, 0x10, 0x1b, 0x18, 0x4f, 0xe2, 0xc5, 0xa5, 0xd2, 0x67, 0x92, 0x65, + 0x81, 0xb8, 0x0d, 0xb9, 0xda, 0x91, 0xc9, 0xa3, 0x35, 0x81, 0x65, 0xff, 0x25, 0x53, 0xfa, 0xf9, + 0x57, 0x9e, 0x89, 0x34, 0x78, 0x06, 0x3d, 0xa7, 0x16, 0xe3, 0x17, 0x04, 0x1a, 0x7b, 0x20, 0xfa, + 0xf0, 0x9a, 0xbb, 0xc3, 0xc1, 0x86, 0x6c, 0x24, 0x35, 0x97, 0xae, 0x31, 0xf8, 0xb7, 0xc2, 0xae, + 0x75, 0x43, 0xfc, 0x78, 0x96, 0x6a, 0xbe, 0xc8, 0x87, 0x5a, 0xe6, 0x44, 0xe0, 0xa3, 0x7d, 0x8d, + 0x9b, 0xf7, 0x6c, 0xa1, 0xa3, 0xfd, 0x3f, 0x81, 0x62, 0xf8, 0xd9, 0xf0, 0x1e, 0x9e, 0x9e, 0xa7, + 0x2e, 0xba, 0x11, 0x6d, 0x93, 0x2a, 0x45, 0xbb, 0x8b, 0x6d, 0xa7, 0xea, 0x66, 0xac, 0x0d, 0x03, + 0xb1, 0xc6, 0x5e, 0x5f, 0x62, 0x11, 0x80, 0x01, 0x05, 0xba, 0xc0, 0x01, 0x97, 0x16, 0xca, 0xef, + 0xd7, 0xb2, 0x0d, 0x65, 0xc8, 0xda, 0x35, 0xf4, 0xe0, 0x04, 0x4c, 0xd2, 0xf0, 0x60, 0xfe, 0x02, + 0xaf, 0x25, 0x50, 0x7a, 0xb2, 0x60, 0x0a, 0x08, 0x5e, 0xa1, 0x4a, 0x70, 0xcd, 0xe3, 0xe1, 0x9c, + 0xdc, 0x9a, 0xf5, 0x2f, 0xa3, 0xce, 0xb6, 0x4c, 0x06, 0x82, 0x2f, 0x6a, 0x08, 0x9e, 0xca, 0x67, + 0xf7, 0xad, 0x0e, 0xb0, 0x4f, 0xa8, 0x30, 0xa8, 0xa4, 0x55, 0xef, 0x36, 0x5e, 0x29, 0xc0, 0xc0, + 0x0d, 0xb3, 0xb6, 0x0e, 0xe5, 0xf6, 0x64, 0xa8, 0x34, 0xf5, 0x34, 0x0b, 0x71, 0x34, 0xcc, 0xa0, + 0x3e, 0x4b, 0x42, 0x86, 0x09, 0xf5, 0x14, 0x2c, 0xf7, 0xb6, 0x31, 0x9f, 0xd2, 0x05, 0x11, 0x81, + 0xe4, 0x30, 0x19, 0xf2, 0xa0, 0x53, 0x57, 0x46, 0x1e, 0x11, 0x26, 0x36, 0x8b, 0x9d, 0xbc, 0x04, + 0x72, 0x3f, 0xba, 0x20, 0x7d, 0xfc, 0xaf, 0xbf, 0x55, 0x80, 0x0f, 0x7f, 0x3e, 0x08, 0xd4, 0xc4, + 0x45, 0x57, 0xb8, 0xbd, 0xd3, 0xe5, 0xd9, 0x22, 0x88, 0xb4, 0xc4, 0xe2, 0x74, 0x5f, 0x56, 0xf8, + 0xca, 0x55, 0xd6, 0x9c, 0x55, 0x55, 0xb8, 0x72, 0xed, 0xbc, 0x5d, 0xf4, 0x0e, 0x6e, 0x96, 0x09, + 0x12, 0x3a, 0x5a, 0x34, 0x45, 0xa1, 0x2f, 0x0d, 0x39, 0xca, 0xb0, 0xf7, 0xc9, 0xb5, 0x49, 0x07, + 0x5b, 0xa5, 0x25, 0x37, 0xab, 0xe4, 0xef, 0x10, 0x96, 0xef, 0xd1, 0x97, 0xb6, 0x6c, 0x58, 0x66, + 0x57, 0x45, 0x45, 0x68, 0xf3, 0x27, 0x2c, 0x1f, 0xea, 0x1e, 0xa4, 0xdb, 0xe2, 0x44, 0x15, 0xc9, + 0x2e, 0x1b, 0x40, 0xe0, 0x73, 0xdd, 0x97, 0xac, 0x29, 0xa1, 0xa6, 0x8f, 0x53, 0xa7, 0x6e, 0x39, + 0xdb, 0x82, 0x97, 0xdd, 0x84, 0x4e, 0x48, 0xb9, 0x05, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3579,7 +4094,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_patch_loc_data[] = { - 0x10, 0x66, 0x00, 0x00, + 0x10, 0x76, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c index 25899e9d4b..da718bfe60 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c @@ -34,1794 +34,2052 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 40704 -// COMPRESSED SIZE (bytes): 28516 +// DATA SIZE (bytes): 58624 +// COMPRESSED SIZE (bytes): 32644 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = { - 0xed, 0xfd, 0x53, 0x8c, 0xe8, 0xde, 0xfb, 0x00, 0xfc, 0x8e, 0x3d, 0x7b, 0x6c, 0xdb, 0xb6, 0x6d, - 0x7b, 0x66, 0x8f, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xed, 0x99, 0xf3, 0xfb, - 0x9f, 0xe4, 0xdc, 0x7c, 0xcf, 0xc5, 0x7b, 0xfd, 0x26, 0xfb, 0x73, 0xb3, 0x90, 0xb4, 0x6b, 0x25, - 0x45, 0xfa, 0xb4, 0x4f, 0x5b, 0x09, 0x00, 0xf8, 0x99, 0x74, 0x80, 0x58, 0x3d, 0x74, 0x80, 0xee, - 0xa3, 0xbc, 0xf7, 0xe6, 0x1f, 0x40, 0x09, 0x00, 0x84, 0xff, 0xeb, 0x30, 0x43, 0x07, 0xf8, 0xff, - 0x36, 0xc3, 0x01, 0x00, 0x00, 0x7f, 0x92, 0x00, 0x7c, 0xe8, 0x00, 0x00, 0xde, 0x80, 0xde, 0x00, - 0xde, 0x81, 0xa2, 0x01, 0x80, 0x00, 0x7a, 0x77, 0x76, 0x7f, 0x7f, 0x7f, 0xe1, 0xc2, 0x01, 0x00, - 0x01, 0x7e, 0x73, 0x41, 0x1a, 0x8f, 0x00, 0x98, 0xd2, 0xd6, 0x01, 0x1b, 0x93, 0x00, 0xa8, 0xd3, - 0xd6, 0x81, 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0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, + 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0xff, 0x67, 0xff, 0x0f, 0x87, 0x3f, 0x0e, 0x19, + 0x00, 0xe5, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1831,8 +2089,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 40704, // uncompressed data size (bytes) - 28516, // compressed data size (bytes) + 58624, // uncompressed data size (bytes) + 32644, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1854,8 +2112,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x00, 0x62, 0x7d, 0x08, 0x13, 0x4c, 0xe4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x1a, 0x52, 0x4d, 0xe9, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x04, 0xe2, 0x14, 0x08, 0x13, 0x4c, 0x34, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x90, 0x7b, 0x92, 0x9e, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1883,1794 +2141,2051 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 40704 -// COMPRESSED SIZE (bytes): 28514 +// DATA SIZE (bytes): 58624 +// COMPRESSED SIZE (bytes): 32640 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] = { - 0xed, 0xfd, 0x53, 0x8c, 0x28, 0x4d, 0xdb, 0x00, 0x6a, 0x8f, 0xed, 0x59, 0x63, 0xdb, 0xb6, 0x6d, - 0xdb, 0x9e, 0x59, 0x63, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xed, 0x99, 0xfd, 0x7e, - 0x7f, 0xf2, 0x9f, 0x3c, 0x27, 0xfb, 0x78, 0x27, 0xeb, 0x3a, 0xa9, 0xea, 0x4a, 0xba, 0xba, 0x93, - 0x4e, 0x57, 0xe5, 0x2e, 0x74, 0x4b, 0x00, 0x20, 0xcc, 0xa4, 0x03, 0xc4, 0xea, 0xa3, 0x03, 0x74, - 0x1f, 0xe5, 0xbd, 0x37, 0xff, 0x00, 0x4a, 0x00, 0x20, 0xfe, 0x5f, 0x81, 0x19, 0x3a, 0xc0, 0xff, - 0xef, 0x30, 0x1c, 0x00, 0x00, 0xf0, 0x27, 0x09, 0xc0, 0x87, 0x0e, 0x00, 0xe0, 0x0d, 0xe8, 0x0d, - 0xe0, 0x1d, 0x28, 0x1a, 0x00, 0x08, 0xa0, 0x77, 0x67, 0xf7, 0xf7, 0xf7, 0x17, 0x3e, 0x1c, 0x00, - 0x10, 0xe0, 0x37, 0x17, 0xa4, 0xf1, 0x08, 0x80, 0x29, 0x6d, 0x1d, 0xb0, 0x31, 0x09, 0x80, 0x3a, - 0x6d, 0x1d, 0xe8, 0x7f, 0x09, 0x49, 0xda, 0x3a, 0xf0, 0xff, 0x12, 0xdc, 0xff, 0x9d, 0x0b, 0x90, - 0x96, 0x0b, 0xdc, 0xbc, 0x0b, 0xdc, 0x9b, 0x9b, 0xb7, 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0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, - 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0x1f, 0xf0, 0xff, 0x00, 0x56, 0x0b, 0xad, 0xbe, 0x00, 0x9f, - 0x00, 0x00, + 0xff, 0xfc, 0xf3, 0xcf, 0xff, 0xcf, 0xfe, 0x1f, 0x97, 0x70, 0x5d, 0xd9, 0x00, 0xe5, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3680,8 +4195,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 40704, // uncompressed data size (bytes) - 28514, // compressed data size (bytes) + 58624, // uncompressed data size (bytes) + 32640, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3703,8 +4218,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x00, 0x62, 0x7d, 0x08, 0x13, 0x4c, 0xe4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x1a, 0x52, 0x4d, 0xe9, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x04, 0xe2, 0x14, 0x08, 0x13, 0x4c, 0x34, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x90, 0x7b, 0x92, 0x9e, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3737,31 +4252,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xe5, 0x3a, 0x94, 0x96, 0x95, 0x55, 0x26, 0x8f, 0x19, 0x5f, 0x14, - 0xe5, 0x91, 0x1c, 0x16, 0x26, 0xca, 0xac, 0xc2, 0x66, 0x7f, 0x05, 0x1b, 0xed, 0x62, 0xb5, 0x6b, - 0xb2, 0xb0, 0x67, 0x10, 0x27, 0x56, 0xe5, 0xe7, 0x6f, 0x32, 0xba, 0xf1, 0x43, 0x78, 0x92, 0x48, - 0xe4, 0xc5, 0x51, 0xe6, 0xc9, 0x15, 0x05, 0xd5, 0xfd, 0x79, 0x42, 0x03, 0x15, 0xeb, 0x76, 0xee, - 0xb3, 0x9a, 0xae, 0x42, 0xec, 0x39, 0xb0, 0x28, 0x1d, 0xb7, 0xe3, 0xa2, 0x72, 0x0f, 0x34, 0xbd, - 0x57, 0xb8, 0x4f, 0x5b, 0x5c, 0x2b, 0x9e, 0x0f, 0x1a, 0x8b, 0x66, 0x98, 0x16, 0xd4, 0x4b, 0x10, - 0x3b, 0xdb, 0x6c, 0x1a, 0xea, 0xd5, 0xc2, 0xfd, 0x72, 0x79, 0x92, 0x22, 0x3a, 0xb9, 0xaa, 0x8c, - 0x6a, 0xe4, 0x05, 0x32, 0x47, 0x12, 0xf0, 0x78, 0xfa, 0xa8, 0xd6, 0x2d, 0x39, 0x33, 0x5b, 0x94, - 0x93, 0x91, 0x93, 0xb3, 0xbc, 0xd0, 0x44, 0x20, 0x5c, 0xe2, 0x8a, 0xd2, 0x41, 0xc2, 0xae, 0x45, - 0xaa, 0x96, 0xef, 0x4f, 0x73, 0x07, 0xaa, 0x6a, 0x79, 0xde, 0xb6, 0xbd, 0x6a, 0x6c, 0x98, 0xd7, - 0x07, 0x43, 0xa6, 0x6e, 0x62, 0xd6, 0x97, 0x5d, 0x01, 0xf0, 0xe0, 0x0f, 0xc2, 0x84, 0x51, 0x8f, - 0x23, 0x94, 0xb9, 0xf6, 0xa2, 0xbf, 0xde, 0x81, 0x84, 0xd4, 0xed, 0x03, 0xf1, 0x8c, 0xc7, 0xd0, - 0x6c, 0x93, 0x40, 0x91, 0xcc, 0x4c, 0x9f, 0x13, 0xd3, 0x10, 0x7a, 0x0e, 0xc1, 0x1b, 0x1b, 0x02, - 0x9b, 0xa4, 0x59, 0x06, 0x9a, 0x21, 0x66, 0x3c, 0xae, 0xda, 0xf5, 0xd3, 0x4a, 0xe7, 0x4c, 0xef, - 0x85, 0x88, 0x16, 0x04, 0x03, 0xf7, 0x02, 0x67, 0x0e, 0x7e, 0xdf, 0x8c, 0x4c, 0xca, 0xc1, 0x06, - 0x3a, 0x4c, 0xf8, 0xef, 0xe6, 0x1f, 0x9d, 0x95, 0x60, 0x0d, 0xf0, 0xb6, 0xe5, 0xe1, 0xe4, 0x80, - 0x24, 0xef, 0x9d, 0x22, 0x9c, 0x09, 0xa6, 0xae, 0x2a, 0xe9, 0xeb, 0xa3, 0x55, 0x2d, 0x1a, 0xd5, - 0x4a, 0x81, 0x3d, 0x03, 0xc6, 0x9d, 0xc3, 0x64, 0x8a, 0xe3, 0xc8, 0x23, 0x90, 0x93, 0x77, 0x8b, - 0xdc, 0xf7, 0xa4, 0xd3, 0xec, 0x3c, 0xa6, 0x9c, 0x41, 0xc6, 0xa1, 0xe4, 0xd5, 0xe4, 0xf2, 0x30, - 0xb9, 0x5d, 0x00, 0x4b, 0x3a, 0x0c, 0x3b, 0x67, 0xaf, 0x00, 0x34, 0x6d, 0x11, 0x05, 0xdb, 0x42, - 0x11, 0x3a, 0x08, 0xc6, 0x53, 0x5a, 0xda, 0xdf, 0x9f, 0x9d, 0xe7, 0x18, 0x59, 0xc6, 0x06, 0x70, - 0xae, 0xd6, 0x0c, 0xd7, 0xba, 0x43, 0xbd, 0x6c, 0x21, 0x13, 0x3f, 0xdd, 0x27, 0xaf, 0x68, 0x66, - 0x63, 0x99, 0x33, 0x12, 0x98, 0x80, 0x0b, 0x56, 0x42, 0x00, 0x76, 0xf0, 0x92, 0x5f, 0xd9, 0xac, - 0x73, 0x1a, 0x52, 0x02, 0x23, 0xca, 0x82, 0xf8, 0x15, 0x9a, 0x47, 0x9b, 0x78, 0x5b, 0xdf, 0xd9, - 0xcb, 0x81, 0xb0, 0x6e, 0x91, 0xd4, 0xcd, 0xa6, 0xbe, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb1, 0x66, 0x3d, 0x0d, 0x01, 0x24, 0xf8, 0x06, 0xfc, 0xec, 0x40, + 0x15, 0x44, 0xcc, 0x95, 0x55, 0xbd, 0xe0, 0x59, 0x61, 0xb8, 0xc1, 0x76, 0xd0, 0xb1, 0x7b, 0x97, + 0xab, 0x4b, 0xfe, 0x48, 0x55, 0x66, 0xc5, 0x4e, 0x16, 0x4b, 0x97, 0xda, 0xcf, 0xfe, 0x8b, 0xb6, + 0xfd, 0x74, 0xbe, 0x3b, 0xf3, 0xba, 0x72, 0x98, 0x1a, 0xca, 0x05, 0x59, 0x22, 0xf5, 0x22, 0x36, + 0xe2, 0xc0, 0x90, 0x88, 0x0e, 0x3a, 0xf1, 0xc6, 0x97, 0x17, 0xf0, 0xf3, 0xa9, 0xb0, 0x28, 0xf7, + 0x46, 0x2c, 0xa2, 0x61, 0x36, 0xd5, 0xce, 0x98, 0xe0, 0xd3, 0x77, 0xf4, 0xb1, 0x35, 0x06, 0x7f, + 0xdb, 0xcc, 0xc9, 0x6f, 0xcc, 0x7f, 0xe0, 0x31, 0xbb, 0xa7, 0xde, 0xa8, 0x5c, 0xf4, 0xc8, 0x9f, + 0xe9, 0xce, 0x7f, 0x0b, 0x7b, 0x2f, 0x40, 0x20, 0x6c, 0xf7, 0x9a, 0xe0, 0xff, 0x31, 0x0a, 0x1d, + 0xbc, 0x73, 0x1d, 0xcb, 0xa4, 0x71, 0xe8, 0x49, 0x0e, 0x19, 0xfa, 0x38, 0x20, 0x97, 0x56, 0xdc, + 0xea, 0x92, 0xbe, 0xc9, 0x80, 0xcb, 0x84, 0xa7, 0x44, 0x9b, 0x0f, 0x2c, 0x63, 0x4e, 0xce, 0x5e, + 0xa8, 0xe1, 0xe6, 0x07, 0x4e, 0xd5, 0x8a, 0x97, 0x41, 0xcc, 0x04, 0xc6, 0x66, 0x50, 0xfd, 0x65, + 0x24, 0x87, 0xde, 0xa1, 0xc0, 0xf1, 0x8d, 0xcc, 0xa6, 0x54, 0xba, 0x4b, 0x62, 0x20, 0x82, 0xa4, + 0x94, 0x38, 0x87, 0xa1, 0x8f, 0x75, 0x60, 0xc5, 0xed, 0x89, 0xa8, 0x37, 0x9c, 0xe6, 0x72, 0x7c, + 0x0c, 0x63, 0xcf, 0x99, 0x43, 0x49, 0x0e, 0xd1, 0x24, 0xf1, 0x65, 0xe4, 0x7b, 0x0a, 0x56, 0x16, + 0xf3, 0x71, 0xed, 0x0d, 0xfe, 0x6e, 0xcb, 0x06, 0x55, 0xdb, 0x9c, 0x29, 0x25, 0x47, 0xe3, 0x72, + 0x43, 0x98, 0x7b, 0x80, 0xc5, 0x7f, 0x98, 0x67, 0xbe, 0x37, 0x4a, 0xd0, 0xd6, 0xda, 0x85, 0x03, + 0xd4, 0xaa, 0x70, 0x4f, 0x1e, 0x0e, 0x42, 0xb8, 0x77, 0x3c, 0xa2, 0xa8, 0x15, 0x98, 0x56, 0xbc, + 0xc5, 0x52, 0x57, 0x67, 0x2f, 0xd0, 0x17, 0xbc, 0x6d, 0xd3, 0x6e, 0x9a, 0xe8, 0x5a, 0x91, 0x68, + 0x71, 0x7a, 0x2f, 0x00, 0x7b, 0xb0, 0xb9, 0x9c, 0xf8, 0x6f, 0xff, 0x8a, 0xd5, 0x3f, 0x72, 0x35, + 0xe6, 0x83, 0x10, 0xa0, 0x6e, 0xae, 0x94, 0xeb, 0x75, 0xed, 0x13, 0xb6, 0x5b, 0xab, 0x2a, 0xff, + 0x81, 0x3d, 0x0f, 0x86, 0xc5, 0xbc, 0x13, 0x5e, 0x5f, 0xa9, 0xc8, 0x15, 0x4b, 0xbe, 0x2f, 0xca, + 0xe8, 0xd1, 0xf5, 0x59, 0x67, 0x28, 0x55, 0xc2, 0x82, 0x75, 0x53, 0xad, 0xba, 0xb6, 0xe6, 0xd3, + 0x8e, 0xca, 0x4a, 0x1f, 0x75, 0xb3, 0x99, 0x7c, 0xdb, 0x10, 0xc7, 0xe6, 0xb0, 0x88, 0x12, 0xc2, + 0x1b, 0x74, 0x8f, 0x33, 0x4c, 0xb9, 0xc8, 0xeb, 0xd5, 0xdb, 0x0b, 0xa6, 0xa7, 0x92, 0x25, 0x4e, + 0x1f, 0x9c, 0xc6, 0xa9, 0x50, 0xee, 0xb9, 0xd0, 0x83, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3794,31 +4309,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x05, 0x55, 0xf4, 0x0a, 0xf8, 0xa9, 0x87, 0xf9, 0x09, 0xd0, 0x64, - 0xcf, 0x89, 0x6d, 0x0f, 0xcc, 0xad, 0x20, 0x7a, 0x47, 0x37, 0xfa, 0x8c, 0x66, 0x25, 0x3b, 0x8e, - 0x71, 0x08, 0x30, 0x76, 0x3c, 0xd4, 0x0c, 0xf9, 0x83, 0x98, 0x41, 0xe2, 0x90, 0x62, 0x06, 0xe6, - 0xa3, 0x46, 0xcd, 0xc1, 0x35, 0x24, 0xa9, 0xfe, 0x2b, 0x4d, 0x1f, 0xb0, 0xfc, 0x36, 0x0b, 0x37, - 0x1b, 0x9e, 0x6c, 0x6d, 0x54, 0xdb, 0x62, 0xc0, 0x96, 0x81, 0x99, 0x3b, 0xfa, 0xc6, 0xae, 0xdb, - 0x31, 0xff, 0x34, 0xd4, 0x45, 0xa8, 0xee, 0x25, 0x36, 0xef, 0xa3, 0x6f, 0xe3, 0x33, 0x6d, 0x99, - 0x60, 0xc1, 0x43, 0xa7, 0x98, 0xc5, 0xe7, 0x8b, 0x0a, 0x72, 0xaf, 0xb3, 0x7f, 0x45, 0x0c, 0x31, - 0xd1, 0x69, 0x60, 0x88, 0x79, 0xb9, 0x77, 0x61, 0x3e, 0xf2, 0x4e, 0x23, 0x17, 0x12, 0x10, 0xa1, - 0x19, 0xfc, 0xd9, 0x26, 0xed, 0xb7, 0x5f, 0x63, 0xfe, 0xcf, 0x4c, 0x1d, 0xd7, 0xb0, 0xa4, 0xc0, - 0x53, 0x48, 0x87, 0x4d, 0x13, 0x11, 0x88, 0xfe, 0x89, 0x08, 0xc7, 0xa8, 0x36, 0x46, 0xda, 0x58, - 0x18, 0xd0, 0x6d, 0x36, 0xc2, 0x71, 0xf4, 0xa3, 0xa5, 0xcd, 0x7e, 0xf9, 0xdf, 0xd9, 0xa3, 0x66, - 0xaf, 0x2d, 0x34, 0xb7, 0xcb, 0x1e, 0x9a, 0xc0, 0xdb, 0xca, 0x15, 0xed, 0x95, 0x79, 0x07, 0x23, - 0xda, 0x75, 0x78, 0x15, 0x89, 0xc0, 0x71, 0x75, 0xc4, 0xf4, 0x65, 0x6a, 0xb0, 0xff, 0x82, 0x48, - 0x43, 0xa2, 0x96, 0xe4, 0x1b, 0xb5, 0xee, 0x37, 0x9f, 0x48, 0x6d, 0xcf, 0x7b, 0x5f, 0xe6, 0xbe, - 0x47, 0xb2, 0xa6, 0xdd, 0xa6, 0x84, 0x36, 0xd4, 0xde, 0x6e, 0x46, 0x1a, 0x65, 0x97, 0x8a, 0xe3, - 0xad, 0x07, 0x92, 0xe8, 0x84, 0x72, 0x35, 0xc3, 0xb5, 0x1d, 0x24, 0xb6, 0x3a, 0x14, 0x80, 0xef, - 0x2d, 0x70, 0x6d, 0x7b, 0x6a, 0x1b, 0x77, 0x07, 0xd2, 0xf9, 0xcd, 0x21, 0x9d, 0xd4, 0x56, 0x26, - 0x38, 0xbe, 0xcd, 0xab, 0x1c, 0xf2, 0x40, 0x15, 0xce, 0x11, 0xb1, 0x4a, 0x71, 0x51, 0x32, 0x12, - 0x94, 0x20, 0xc6, 0xa9, 0xe2, 0x88, 0xb6, 0xc5, 0x5d, 0xf7, 0x1d, 0x0a, 0x89, 0x5f, 0xd2, 0x61, - 0x16, 0xe6, 0xba, 0x48, 0x14, 0x54, 0xd0, 0x57, 0xdb, 0xe9, 0x8c, 0x82, 0x2d, 0xa1, 0x0c, 0xe2, - 0x6c, 0xba, 0xd8, 0x22, 0xfc, 0xee, 0xac, 0x51, 0xd1, 0x7e, 0x1c, 0x5f, 0x85, 0xa0, 0x59, 0xdf, - 0x6e, 0x31, 0x28, 0x26, 0x8f, 0xf6, 0x29, 0x03, 0x48, 0x5b, 0x09, 0x8b, 0xfd, 0xe7, 0x32, 0xb6, - 0xe5, 0x9f, 0x84, 0xba, 0xca, 0x42, 0x83, 0xdb, 0x39, 0x66, 0xa9, 0x81, 0xdf, 0x55, 0x7e, 0x52, - 0xec, 0x4f, 0x01, 0x18, 0x30, 0xa5, 0x58, 0xbe, 0x96, 0x9d, 0x04, 0x0d, 0x6e, 0x7e, 0x1c, 0x46, - 0xc8, 0xe8, 0x97, 0x78, 0x0f, 0x91, 0xa8, 0xbb, 0x8b, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb8, 0xce, 0x5e, 0xf2, 0x4d, 0xe3, 0x99, 0x0c, 0xa0, 0x1f, 0xcf, + 0xdc, 0x09, 0x99, 0x1e, 0xf1, 0x46, 0x2b, 0x10, 0x6f, 0x27, 0xf0, 0x3f, 0xd5, 0xeb, 0x73, 0x27, + 0xad, 0xfb, 0xbd, 0x93, 0xb6, 0x85, 0x27, 0x92, 0x15, 0x15, 0x9e, 0xc9, 0x3e, 0x85, 0xb9, 0x3f, + 0xdd, 0x28, 0xd1, 0x4e, 0x7d, 0x27, 0x52, 0xb6, 0xf0, 0x03, 0xf0, 0x66, 0xda, 0x52, 0x17, 0x8b, + 0xb6, 0x1e, 0xd2, 0x1d, 0x82, 0xa4, 0x4e, 0x2f, 0x3a, 0x7d, 0xe1, 0xd3, 0xbf, 0xe1, 0x2e, 0xc4, + 0xad, 0xb2, 0xb0, 0x82, 0x61, 0x27, 0xa0, 0x6f, 0x73, 0xe4, 0x4c, 0xc1, 0x24, 0x11, 0xb8, 0xa2, + 0x42, 0x15, 0xd3, 0xd3, 0x79, 0x90, 0xb8, 0xd6, 0xfe, 0x0f, 0x9c, 0x90, 0x0d, 0x48, 0xa3, 0xcd, + 0x0b, 0xd2, 0x37, 0x45, 0x60, 0x84, 0x2c, 0x27, 0xcf, 0xaf, 0xcf, 0xd2, 0xe6, 0x9b, 0x87, 0xb5, + 0x1a, 0x6d, 0x53, 0x37, 0x48, 0x84, 0xbe, 0x7b, 0x71, 0x43, 0x94, 0x97, 0xd4, 0x8f, 0xed, 0xa8, + 0x51, 0xbd, 0x92, 0x85, 0xfd, 0xdc, 0xf2, 0x57, 0x46, 0x0f, 0x9b, 0x65, 0x44, 0x04, 0xed, 0x33, + 0x00, 0x04, 0x88, 0x1e, 0xcd, 0x9b, 0xb8, 0x62, 0xc7, 0x0c, 0x9b, 0x1d, 0xe7, 0xd1, 0x47, 0xfb, + 0x4a, 0x97, 0x33, 0x5f, 0x2f, 0x61, 0x54, 0x95, 0xbb, 0xee, 0x25, 0xf9, 0x4d, 0x17, 0xfb, 0xe6, + 0x67, 0x29, 0x15, 0x58, 0x68, 0x71, 0x7f, 0xbc, 0x66, 0xb2, 0xe2, 0x67, 0x8d, 0x4b, 0x5a, 0x24, + 0x05, 0x8d, 0x08, 0x6d, 0xbf, 0xee, 0xfe, 0xfe, 0x42, 0x34, 0xef, 0xeb, 0x8b, 0xe8, 0x32, 0xc0, + 0xf4, 0x8a, 0x82, 0xc1, 0x78, 0x21, 0x5c, 0x04, 0x1d, 0x51, 0x13, 0xd7, 0x9f, 0xc0, 0x10, 0xc7, + 0xad, 0x0e, 0x71, 0x91, 0x48, 0xb3, 0x05, 0xc1, 0x4d, 0xff, 0x83, 0xf1, 0x79, 0x26, 0x17, 0x10, + 0x12, 0x3e, 0x92, 0xce, 0x25, 0xb8, 0x48, 0x63, 0x6f, 0x22, 0x7d, 0xf6, 0xf4, 0xbf, 0x13, 0x6c, + 0x97, 0xa5, 0xb1, 0x8b, 0x34, 0x44, 0xb4, 0x21, 0x16, 0xa3, 0x90, 0x0b, 0x0f, 0xd0, 0x72, 0x3a, + 0xeb, 0x6d, 0x58, 0x51, 0x31, 0x5c, 0x35, 0x53, 0x6f, 0x4a, 0xf3, 0x12, 0x47, 0xe5, 0xe1, 0xc1, + 0xee, 0xba, 0xa6, 0xfb, 0x8f, 0x70, 0xf1, 0xc0, 0xb5, 0x93, 0x2e, 0x10, 0xf9, 0xb5, 0x03, 0x1e, + 0x72, 0xd6, 0x70, 0xea, 0x9d, 0x59, 0x02, 0x79, 0x18, 0x22, 0xb8, 0xb9, 0xbb, 0xf5, 0x4e, 0x6f, + 0x13, 0x8c, 0x5d, 0x2a, 0xac, 0x81, 0x58, 0x3e, 0x1b, 0x0b, 0xee, 0xc4, 0xd9, 0xe0, 0x23, 0x15, + 0x69, 0x6a, 0xe9, 0xca, 0xdc, 0xae, 0xa0, 0x9f, 0xdc, 0x91, 0xb3, 0xc9, 0x86, 0x2f, 0xc5, 0xe7, + 0x78, 0x1f, 0xd9, 0xd9, 0x44, 0xa9, 0x6f, 0x20, 0x13, 0xb9, 0xc2, 0x1f, 0x81, 0x4f, 0xff, 0x3b, + 0xdd, 0x4e, 0xb7, 0x74, 0x5e, 0x41, 0x6d, 0xaf, 0xa8, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3851,7 +4366,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_patch_loc_data[] = { - 0x00, 0x72, 0x00, 0x00, + 0x00, 0x83, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c index 5276018134..7869e9cce2 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c @@ -34,1833 +34,2080 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 41216 -// COMPRESSED SIZE (bytes): 29140 +// DATA SIZE (bytes): 58880 +// COMPRESSED SIZE (bytes): 33102 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data[] = { - 0xed, 0xdd, 0x43, 0x90, 0x30, 0xcd, 0xf3, 0x00, 0xe8, 0xb1, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xbe, 0x63, 0xdb, 0x9e, 0xd9, 0xff, 0xf9, 0x77, 0xda, - 0xdb, 0x1e, 0xf6, 0x7b, 0x6e, 0x7d, 0xea, 0xa8, 0xa8, 0xae, 0x8a, 0xc8, 0xec, 0xac, 0x2c, 0x00, - 0x80, 0xff, 0x7f, 0xbb, 0x8b, 0x50, 0xd3, 0x60, 0x81, 0x22, 0x38, 0x0b, 0xf9, 0x5a, 0x9c, 0x53, - 0xc1, 0x4a, 0x54, 0x4b, 0xfc, 0x13, 0x3c, 0x32, 0x0e, 0xa9, 0x84, 0x7e, 0xa0, 0x6c, 0xf7, 0x69, - 0x4f, 0x1f, 0x1a, 0xe4, 0x26, 0xcc, 0x9d, 0xac, 0xf3, 0x75, 0x8e, 0x09, 0xb5, 0x8b, 0x50, 0x89, - 0x93, 0xba, 0xef, 0x0c, 0x28, 0x7e, 0x76, 0xc0, 0xeb, 0xf6, 0xa3, 0xbe, 0x36, 0x1a, 0x12, 0x7f, - 0xcf, 0xfe, 0xe8, 0x3e, 0xed, 0x4e, 0x1d, 0x8f, 0xa5, 0x0e, 0xed, 0x84, 0xac, 0xf1, 0x49, 0xb3, - 0xb9, 0xa1, 0xd8, 0x6a, 0xdf, 0x12, 0xb6, 0xc4, 0x4e, 0x66, 0x09, 0x84, 0x6c, 0x08, 0xe3, 0x6b, - 0xac, 0xc5, 0xf6, 0xda, 0x2c, 0x2f, 0x52, 0xbc, 0x1c, 0xa9, 0x39, 0x3d, 0xba, 0xd6, 0x11, 0xe6, - 0x4e, 0x42, 0xd7, 0xb7, 0x1e, 0xed, 0x3e, 0x85, 0xd4, 0xbc, 0x17, 0x04, 0xe3, 0x94, 0x19, 0x8a, - 0x9a, 0x5f, 0xf6, 0x93, 0x3b, 0x24, 0x81, 0x17, 0x75, 0x83, 0xa2, 0x80, 0x31, 0x9c, 0xe3, 0xd0, - 0xc4, 0x68, 0xf0, 0x5f, 0xe6, 0x58, 0x1d, 0x0b, 0x0b, 0x26, 0x62, 0xb7, 0xbe, 0xdc, 0x40, 0xd4, - 0x6c, 0x99, 0x94, 0x38, 0x6c, 0x2d, 0x7b, 0x7c, 0x46, 0x2a, 0xb1, 0x98, 0x94, 0x5f, 0x78, 0x04, - 0xd3, 0x2f, 0xe9, 0x46, 0xae, 0x49, 0x7c, 0x9d, 0xeb, 0xbb, 0x4d, 0xe3, 0x07, 0xfb, 0x92, 0x20, - 0xac, 0xa2, 0xa1, 0x4c, 0x1c, 0xac, 0x65, 0x08, 0x58, 0x1c, 0xdb, 0x00, 0xd6, 0xb1, 0x29, 0x3c, - 0x77, 0xc3, 0x88, 0x6c, 0x9d, 0x16, 0x27, 0x25, 0xf6, 0x6f, 0xb4, 0xa0, 0xba, 0x79, 0xf6, 0x2e, - 0x0c, 0xca, 0xdd, 0x5c, 0xdd, 0xd0, 0x83, 0xdb, 0x44, 0x55, 0x23, 0x82, 0x24, 0x70, 0xca, 0xf6, - 0xcb, 0x04, 0xc4, 0x6e, 0x5d, 0x17, 0x54, 0x19, 0x8f, 0x69, 0x5c, 0xf6, 0x5a, 0xfb, 0xb0, 0x49, - 0xb9, 0x0d, 0x65, 0x86, 0x80, 0xa1, 0x9e, 0x58, 0x1b, 0x73, 0x3d, 0x3d, 0x69, 0x09, 0xe0, 0x74, - 0xae, 0xf3, 0xa5, 0x8a, 0xfc, 0x2d, 0x37, 0x9d, 0x80, 0xb0, 0xcc, 0x4e, 0x46, 0x07, 0xa7, 0xb2, - 0x23, 0x68, 0x10, 0xd4, 0xed, 0x25, 0x15, 0x3c, 0x63, 0x61, 0xe2, 0x00, 0x2b, 0x73, 0x8b, 0xce, - 0xba, 0x67, 0xd1, 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// compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1893,8 +2140,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x01, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0x14, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xba, 0xbc, 0x76, 0xc1, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x01, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x34, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xef, 0x1f, 0x77, 0xe5, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1922,1833 +2169,2080 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 41216 -// COMPRESSED SIZE (bytes): 29139 +// DATA SIZE (bytes): 58880 +// COMPRESSED SIZE (bytes): 33101 // static BINDATA_CONST NvU8 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kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 41216, // uncompressed data size (bytes) - 29139, // compressed data size (bytes) + 58880, // uncompressed data size (bytes) + 33101, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3781,8 +4275,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x01, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0x14, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xba, 0xbc, 0x76, 0xc1, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x01, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x34, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xef, 0x1f, 0x77, 0xe5, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3815,55 +4309,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x5c, 0x08, 0x12, 0x1a, 0xe1, 0x2f, 0x84, 0x44, 0x86, 0xed, 0x3a, - 0x40, 0x04, 0x9a, 0x83, 0xa9, 0x67, 0x6c, 0xe1, 0xe5, 0x43, 0x28, 0x02, 0x81, 0x2f, 0x18, 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kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 420, // compressed data size (bytes) + 417, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3955,7 +4449,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_patch_loc_data[] = { - 0x10, 0x74, 0x00, 0x00, + 0x10, 0x84, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c index 3de2c6a6bd..97446c1b61 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c @@ -34,1768 +34,2035 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 39936 -// COMPRESSED SIZE (bytes): 28110 +// DATA SIZE (bytes): 57600 +// COMPRESSED SIZE (bytes): 32381 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data[] = 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0x5d, 0xd0, 0xca, 0x61, 0x7b, 0x32, 0xbf, 0xc4, 0x44, + 0x42, 0xb2, 0xb4, 0x26, 0x41, 0x6e, 0x2e, 0xce, 0x2e, 0x3c, 0xa0, 0xb5, 0x04, 0xdd, 0x68, 0xa6, + 0x2f, 0x6f, 0x8e, 0x0a, 0xf0, 0xd5, 0x67, 0xc5, 0x0b, 0xe7, 0x12, 0x18, 0x14, 0x6a, 0x9c, 0x33, + 0xa7, 0xcf, 0xdd, 0x2d, 0x74, 0x54, 0x00, 0xf0, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, + 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, + 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0xff, 0x2f, 0xff, 0x07, 0x19, 0x65, 0xec, 0xa6, 0x00, 0xe1, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1805,8 +2072,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 39936, // uncompressed data size (bytes) - 28110, // compressed data size (bytes) + 57600, // uncompressed data size (bytes) + 32381, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1828,8 +2095,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xce, 0x07, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0xe4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x6a, 0x65, 0x76, 0x8b, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xae, 0x07, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x4c, 0xc8, 0x3e, 0x08, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1857,1769 +2124,2035 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 39936 -// COMPRESSED SIZE (bytes): 28113 +// DATA SIZE (bytes): 57600 +// COMPRESSED SIZE (bytes): 32379 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_prod_data[] = { - 0xed, 0xfd, 0x53, 0x90, 0x2c, 0xcf, 0x1b, 0x38, 0x78, 0x8f, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x9e, - 0x33, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x33, 0x67, 0xec, 0x99, 0xfd, 0xfd, - 0xdf, 0xbb, 0xf7, 0x7b, 0xb3, 0xb1, 0x17, 0x7b, 0xb1, 0x11, 0xe7, 0x73, 0x93, 0x99, 0x15, 0xd1, - 0x9d, 0x1d, 0x51, 0xd5, 0xd9, 0x4f, 0x66, 0x67, 0x3d, 0x25, 0x09, 0x80, 0x30, 0x9b, 0x01, 0x10, - 0xa7, 0x8f, 0x06, 0xd0, 0x73, 0x9c, 0xff, 0xde, 0xf2, 0x03, 0x28, 0x09, 0x80, 0xf8, 0x7f, 0x0e, - 0x98, 0xa3, 0x01, 0xfc, 0xff, 0x9a, 0x11, 0x00, 0x00, 0x80, 0x3f, 0xc9, 0x00, 0xbe, 0xf4, 0x00, - 0x00, 0x6f, 0x40, 0x6f, 0x00, 0xef, 0x40, 0x31, 0x00, 0x40, 0x00, 0x7d, 0xbb, 0x7b, 0xbf, 0xbf, - 0xbf, 0xf0, 0x11, 0x00, 0x80, 0x00, 0xbf, 0x79, 0x20, 0x4d, 0xc7, 0x00, 0xcc, 0xe9, 0x1b, 0x80, - 0x4d, 0xc9, 0x00, 0x34, 0xe9, 0x1b, 0x40, 0xff, 0x2b, 0x48, 0xd3, 0x37, 0x80, 0xff, 0x57, 0xe0, - 0xfd, 0xef, 0xb5, 0x00, 0xe9, 0x79, 0xc0, 0x2d, 0x7b, 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0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, - 0xfe, 0xf9, 0xe7, 0x9f, 0xff, 0x8f, 0xf8, 0xbf, 0x00, 0x15, 0x32, 0x1b, 0xfa, 0x00, 0x9c, 0x00, - 0x00, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xff, + 0xe5, 0xff, 0x00, 0x56, 0x4e, 0x33, 0x23, 0x00, 0xe1, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3629,8 +4162,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 39936, // uncompressed data size (bytes) - 28113, // compressed data size (bytes) + 57600, // uncompressed data size (bytes) + 32379, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3652,8 +4185,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xce, 0x07, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0xe4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x6a, 0x65, 0x76, 0x8b, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xae, 0x07, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x4c, 0xc8, 0x3e, 0x08, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3686,7 +4219,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_data[] = { - 0xbc, 0x1c, 0x6d, 0x20, 0xde, 0x55, 0x42, 0xd2, 0x0a, 0x80, 0x8b, 0xc0, 0xe1, 0xf3, 0x3c, 0x4b, + 0xc4, 0x9c, 0xbb, 0xda, 0x28, 0xdb, 0xdb, 0xef, 0x51, 0xdb, 0x43, 0x4a, 0xa2, 0x9e, 0x2b, 0xf6, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3719,7 +4252,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_prod_data[] = { - 0xd6, 0xa7, 0x37, 0x0d, 0x47, 0x15, 0x71, 0x56, 0x03, 0x40, 0x93, 0xbd, 0xf0, 0xfc, 0x3c, 0x93, + 0xad, 0x80, 0x9b, 0x7a, 0x70, 0x99, 0x4e, 0xae, 0xd1, 0x54, 0xce, 0x2a, 0xf1, 0xd5, 0xf1, 0xb5, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3752,7 +4285,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_patch_loc_data[] = { - 0x00, 0x71, 0x00, 0x00, + 0x00, 0x81, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c index 74baa0e094..7d468044bd 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c @@ -34,1770 +34,2035 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 39936 -// COMPRESSED SIZE (bytes): 28132 +// DATA SIZE (bytes): 57600 +// COMPRESSED SIZE (bytes): 32382 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = { - 0xed, 0xdd, 0x43, 0xac, 0x28, 0xcd, 0x1b, 0x38, 0xe8, 0x63, 0xdb, 0xb6, 0x8d, 0x7b, 0x6c, 0xdb, - 0xb6, 0x71, 0x8f, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x36, 0xe7, 0xf7, 0x9f, 0xdd, - 0x7c, 0xbb, 0x59, 0xcc, 0x62, 0x92, 0xfb, 0x6c, 0xaa, 0xaa, 0x93, 0xee, 0xea, 0xa4, 0x93, 0xee, - 0xe2, 0xdb, 0x12, 0x00, 0x08, 0x33, 0xe9, 0x00, 0xb1, 0xfa, 0x68, 0x00, 0xdd, 0x47, 0x79, 0xef, - 0xcd, 0x3f, 0x80, 0x12, 0x00, 0x88, 0xff, 0xe7, 0x80, 0x39, 0x1a, 0xc0, 0xff, 0x5d, 0x0c, 0x07, - 0x00, 0x00, 0xfc, 0x49, 0x02, 0xf0, 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0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, - 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xff, 0xc4, 0xff, 0x05, 0x5e, 0xd6, 0x73, 0x23, - 0x00, 0x9c, 0x00, 0x00, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xff, 0xf2, 0xff, 0x00, 0x8b, 0xf3, 0xdf, 0x56, 0x00, 0xe1, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1807,8 +2072,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 39936, // uncompressed data size (bytes) - 28132, // compressed data size (bytes) + 57600, // uncompressed data size (bytes) + 32382, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1830,8 +2095,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xce, 0x07, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0xe4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x6a, 0x65, 0x76, 0x8b, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xae, 0x07, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x4c, 0xc8, 0x3e, 0x08, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1859,1770 +2124,2035 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 39936 -// COMPRESSED SIZE (bytes): 28132 +// DATA SIZE (bytes): 57600 +// COMPRESSED SIZE (bytes): 32377 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] = { - 0xed, 0xfd, 0x43, 0x90, 0x30, 0x4d, 0xd7, 0x00, 0x6c, 0xb6, 0x6d, 0xdb, 0xb6, 0xdd, 0x7d, 0xb7, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xe6, 0x7c, 0xff, 0xec, 0xe6, - 0xdd, 0xcd, 0x62, 0x16, 0x13, 0xf1, 0x5c, 0x9b, 0xcc, 0xac, 0x88, 0xaa, 0x53, 0xab, 0xaa, 0xac, - 0xc4, 0x29, 0x09, 0x00, 0x84, 0xd9, 0x0c, 0x80, 0x38, 0x7d, 0x34, 0x80, 0x9e, 0xe3, 0xfc, 0x8f, - 0x96, 0x5f, 0x40, 0x09, 0x00, 0xc4, 0xff, 0xe7, 0x80, 0x39, 0x1a, 0xc0, 0xff, 0xbb, 0x19, 0x01, - 0x00, 0x00, 0xf8, 0x9b, 0x0c, 0xe0, 0x4b, 0x0f, 0x00, 0xf0, 0x0e, 0xf4, 0x0e, 0xf0, 0x01, 0x14, - 0x03, 0x00, 0x04, 0xd0, 0xb7, 0xbb, 0xf7, 0xf7, 0xf7, 0x07, 0x1f, 0x01, 0x00, 0x08, 0xf0, 0x97, - 0x07, 0xd2, 0x74, 0x0c, 0xc0, 0x9c, 0xbe, 0x01, 0xd8, 0x94, 0x0c, 0x40, 0x93, 0xbe, 0x01, 0xf4, - 0x7f, 0x05, 0x69, 0xfa, 0x06, 0xf0, 0xff, 0x15, 0x78, 0xff, 0x77, 0x2e, 0x40, 0x7a, 0x1e, 0x70, - 0xcb, 0x1e, 0x70, 0x5f, 0x5e, 0xfe, 0x5e, 0x7a, 0x1e, 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0x7f, 0xfe, 0xf9, 0xe7, 0x9f, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0xff, 0x97, 0xff, + 0x07, 0x56, 0xc0, 0x78, 0x1a, 0x00, 0xe1, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3632,8 +4162,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 39936, // uncompressed data size (bytes) - 28132, // compressed data size (bytes) + 57600, // uncompressed data size (bytes) + 32377, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3655,8 +4185,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xce, 0x07, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0xe4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x6a, 0x65, 0x76, 0x8b, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xae, 0x07, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x4c, 0xc8, 0x3e, 0x08, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3689,7 +4219,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_data[] = { - 0x93, 0x0a, 0x99, 0x09, 0x4d, 0xaa, 0xeb, 0xac, 0x32, 0x20, 0x4c, 0xba, 0x57, 0xbf, 0xe3, 0xf2, + 0x3f, 0x38, 0xb1, 0xac, 0x54, 0x82, 0x24, 0x16, 0xef, 0xf8, 0x6f, 0xad, 0x12, 0xfb, 0xdf, 0xe2, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3722,7 +4252,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_prod_data[] = { - 0x98, 0xd3, 0xbe, 0x5a, 0x6f, 0x0e, 0xe7, 0x74, 0x73, 0x08, 0xa6, 0xf9, 0x16, 0x51, 0x4d, 0x26, + 0x4c, 0xc9, 0x13, 0xb3, 0xc8, 0xfa, 0x1f, 0x91, 0x8b, 0xa3, 0x6f, 0xbc, 0xc9, 0x93, 0x36, 0x07, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3755,7 +4285,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_patch_loc_data[] = { - 0x00, 0x71, 0x00, 0x00, + 0x00, 0x81, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c index 6b9ff60b74..f65ed3d89a 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c @@ -34,911 +34,1160 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20992 -// COMPRESSED SIZE (bytes): 14399 +// DATA SIZE (bytes): 38912 +// COMPRESSED SIZE (bytes): 18371 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data[] = { - 0xed, 0xbb, 0x63, 0xac, 0x28, 0xdd, 0xf7, 0xe7, 0x79, 0x6c, 0xdb, 0xb6, 0x6d, 0xdc, 0x63, 0xdb, - 0xb6, 0x6d, 0xde, 0x63, 0xdb, 0xb6, 0x75, 0x8f, 0x6d, 0xdb, 0xb6, 0x6d, 0x1b, 0xfd, 0xf4, 0x7f, - 0x7e, 0x93, 0xe9, 0x3c, 0x99, 0xc9, 0xbc, 0xe8, 0xce, 0xcc, 0x8b, 0xbe, 0x9f, 0xe4, 0x9b, 0xbd, - 0xd6, 0xae, 0x95, 0x5a, 0xb5, 0x77, 0xa5, 0xaa, 0x36, 0x52, 0x00, 0x00, 0xff, 0x7b, 0x73, 0x13, - 0xa6, 0xaa, 0xce, 0x02, 0x45, 0x70, 0x12, 0xf4, 0x31, 0x37, 0xad, 0x8c, 0x15, 0xaf, 0x1a, 0xff, - 0x23, 0x70, 0x60, 0x14, 0x54, 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0x3f, 0x75, + 0x20, 0xc0, 0xff, 0xf7, 0xfe, 0xbf, 0xfe, 0x27, 0xc6, 0x42, 0x03, 0xf8, 0xaf, 0xdf, 0x3f, 0xfa, + 0xbf, 0x1b, 0x07, 0x04, 0xe2, 0x7f, 0xdc, 0x3f, 0xf5, 0xbf, 0xab, 0xa7, 0xfd, 0x93, 0xf4, 0x7f, + 0x22, 0xf6, 0x4f, 0xc4, 0xff, 0x89, 0xc4, 0x3f, 0x91, 0xfc, 0xcf, 0x67, 0xd2, 0xff, 0x29, 0x65, + 0xfe, 0x35, 0x8e, 0xfc, 0x7f, 0x1b, 0x47, 0xfa, 0x3f, 0xff, 0x01, 0xc0, 0x3f, 0x3f, 0x31, 0x80, + 0x92, 0x08, 0xfd, 0xff, 0xc4, 0x1c, 0xfe, 0x77, 0xf2, 0x7f, 0x01, 0x12, 0x35, 0x5c, 0xdd, 0x00, + 0x98, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -948,8 +1197,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20992, // uncompressed data size (bytes) - 14399, // compressed data size (bytes) + 38912, // uncompressed data size (bytes) + 18371, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -971,8 +1220,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xb6, 0x04, 0x62, 0x49, 0x08, 0x13, 0x4c, 0x58, 0x40, 0x69, - 0x20, 0x00, 0x00, 0xcd, 0x04, 0x38, 0x58, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x04, 0x62, 0x3f, 0x08, 0x13, 0x4c, 0x78, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x06, 0x07, 0x25, 0x94, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1000,912 +1249,1160 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20992 -// COMPRESSED SIZE (bytes): 14401 +// DATA SIZE (bytes): 38912 +// COMPRESSED SIZE (bytes): 18373 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data[] = { - 0xed, 0xbb, 0x63, 0x90, 0x28, 0xcd, 0xf7, 0xe7, 0xd9, 0xb6, 0x6d, 0xdb, 0xb6, 0xed, 0xbe, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xed, 0xee, 0xdb, 0xb6, 0x6d, 0xe3, 0xb6, 0x6d, 0x63, 0xee, 0xfc, - 0xf7, 0xb7, 0xb1, 0x13, 0x4f, 0xec, 0xc6, 0xbe, 0x98, 0x89, 0xdd, 0x17, 0xf3, 0x7c, 0x22, 0xbe, - 0x91, 0xe7, 0x64, 0x65, 0xd4, 0xa9, 0xcc, 0x8a, 0x8a, 0x3c, 0x99, 0x19, 0x05, 0x00, 0xf0, 0xbf, - 0x37, 0xdd, 0x7e, 0x0a, 0xc6, 0x0a, 0x88, 0x7c, 0x12, 0x02, 0x5c, 0x9b, 0xcf, 0x6c, 0xdb, 0x0b, - 0x5d, 0xe8, 0x82, 0x1c, 0x41, 0xef, 0xa4, 0x84, 0xe6, 0x13, 0x68, 0x98, 0xbc, 0x5e, 0xfb, 0x10, - 0x6f, 0x3a, 0x66, 0xc4, 0xed, 0xbf, 0x78, 0xe9, 0xc0, 0xbf, 0xbf, 0x45, 0x38, 0x75, 0x89, 0x65, - 0x24, 0xaf, 0x9a, 0x6d, 0xaa, 0x66, 0x5e, 0x86, 0x86, 0x12, 0x7f, 0xc5, 0x9e, 0x68, 0x6f, 0x2b, - 0xf9, 0x2b, 0x10, 0xd3, 0x82, 0x4e, 0xca, 0x29, 0x2a, 0x1a, 0x2c, 0x9b, 0x64, 0x7f, 0xe8, 0x8e, - 0x2f, 0xee, 0x87, 0x14, 0xb4, 0x48, 0x42, 0xae, 0xeb, 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0xa5, 0x34, 0x00, + 0x00, 0xd0, 0x3f, 0x2d, 0xe0, 0x7f, 0xe2, 0x5e, 0xfa, 0xff, 0xe9, 0xff, 0x97, 0x78, 0x96, 0xfe, + 0xaf, 0xf3, 0xfe, 0xdb, 0x18, 0x00, 0xd1, 0xe3, 0xff, 0x6e, 0x65, 0x54, 0x14, 0x64, 0x44, 0xf1, + 0x8d, 0x6d, 0x4c, 0xcd, 0x6d, 0x8c, 0xff, 0x19, 0xc8, 0x49, 0xf2, 0xff, 0x67, 0x80, 0xaf, 0xa9, + 0xa0, 0xc8, 0x8f, 0x6f, 0x6d, 0x6b, 0x64, 0xac, 0xfd, 0xaf, 0xed, 0xc2, 0x82, 0x82, 0xff, 0xd9, + 0xfe, 0x0f, 0x33, 0x29, 0x00, 0x00, 0xfa, 0x7f, 0x82, 0xe1, 0x9f, 0x3e, 0xfe, 0xff, 0xcf, 0x6b, + 0x82, 0xf9, 0x27, 0xd0, 0xfe, 0x09, 0x82, 0x7f, 0xc2, 0xf9, 0x9f, 0x1c, 0x7c, 0xff, 0x25, 0xd7, + 0x3f, 0x7d, 0x20, 0xc0, 0xff, 0xf7, 0xf9, 0x94, 0xff, 0x13, 0xb9, 0x50, 0x01, 0xfe, 0xeb, 0xe7, + 0x8f, 0xfe, 0xef, 0xf2, 0x80, 0x40, 0xfc, 0x8f, 0xe7, 0xa7, 0xfe, 0x77, 0xfd, 0xb4, 0x7f, 0x22, + 0xfd, 0x9f, 0x10, 0xfd, 0x27, 0xc4, 0xfe, 0x09, 0xf1, 0x7f, 0x42, 0xe2, 0x3f, 0xfb, 0xa4, 0xfe, + 0xd3, 0x4a, 0xff, 0x2b, 0x8f, 0xdc, 0x7f, 0xcb, 0x23, 0xf5, 0x9f, 0xdf, 0x00, 0xe0, 0x9f, 0xaf, + 0x18, 0x40, 0x51, 0x98, 0xfe, 0x7f, 0x62, 0x0d, 0xff, 0x3b, 0xf9, 0xbf, 0x00, 0xc1, 0x74, 0xb3, + 0xba, 0x00, 0x98, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1915,8 +2412,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20992, // uncompressed data size (bytes) - 14401, // compressed data size (bytes) + 38912, // uncompressed data size (bytes) + 18373, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1938,8 +2435,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xb6, 0x04, 0x62, 0x49, 0x08, 0x13, 0x4c, 0x58, 0x40, 0x69, - 0x20, 0x00, 0x00, 0xcd, 0x04, 0x38, 0x58, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x04, 0x62, 0x3f, 0x08, 0x13, 0x4c, 0x78, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x06, 0x07, 0x25, 0x94, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1972,55 +2469,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xc0, 0x07, 0xb0, 0x83, 0x17, 0x5d, 0x06, 0xfd, 0xce, 0x4d, 0x3a, - 0x68, 0x08, 0xbe, 0x75, 0xcf, 0xe1, 0x73, 0x1f, 0xc9, 0x72, 0x4c, 0x42, 0x22, 0x1a, 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0x7b, 0x36, 0xc3, 0x68, 0x29, 0x90, + 0x08, 0x7b, 0x4f, 0x3e, 0x54, 0x99, 0x79, 0x33, 0x8c, 0x68, 0xb1, 0x3d, 0x0e, 0xc0, 0x1f, 0x88, + 0x6f, 0x6e, 0x9b, 0x3a, 0x1c, 0xe7, 0xa3, 0x07, 0x92, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2134,7 +2631,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_patch_loc_data[] = { - 0x10, 0x39, 0x00, 0x00, + 0x10, 0x49, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c index c976f86963..57446b11aa 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c @@ -34,884 +34,1134 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20480 -// COMPRESSED SIZE (bytes): 13953 +// DATA SIZE (bytes): 38400 +// COMPRESSED SIZE (bytes): 17960 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data[] = { - 0xed, 0xfa, 0x43, 0x90, 0x66, 0x4d, 0xd7, 0x00, 0xec, 0xde, 0xe5, 0xaa, 0x2e, 0xdb, 0xb6, 0x6d, - 0x74, 0xd9, 0xd5, 0x65, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xec, 0xb2, 0x6d, 0xdb, 0xae, - 0xf3, 0x7c, 0x27, 0xe2, 0x4c, 0xde, 0xc9, 0x89, 0x7f, 0xfa, 0x47, 0x5f, 0x93, 0xcc, 0x5c, 0x11, - 0x3b, 0x23, 0xf7, 0x20, 0x63, 0xaf, 0x58, 0x6b, 0x4b, 0x00, 0x10, 0xa6, 0xd3, 0x01, 0xb1, 0x7a, - 0x18, 0x80, 0xee, 0xc3, 0xbc, 0xb7, 0xe6, 0x6f, 0x20, 0x09, 0x00, 0xe2, 0xff, 0x05, 0xcc, 0x30, - 0x00, 0xff, 0xdf, 0x65, 0x38, 0x00, 0x00, 0xf4, 0x9d, 0x04, 0xf0, 0xa1, 0x07, 0x00, 0x5e, 0x81, - 0x5f, 0x01, 0x6f, 0xc0, 0xd1, 0x00, 0x60, 0x40, 0xef, 0xf6, 0xce, 0xcf, 0xcf, 0x0f, 0x7c, 0x38, - 0x00, 0x08, 0xf0, 0x93, 0x0b, 0xda, 0x78, 0x08, 0x60, 0x4e, 0x5b, 0x03, 0x6a, 0x4c, 0x02, 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0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -921,8 +1171,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20480, // uncompressed data size (bytes) - 13953, // compressed data size (bytes) + 38400, // uncompressed data size (bytes) + 17960, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -944,8 +1194,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x49, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x86, 0xa4, 0x95, 0x74, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x7f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x99, 0x4d, 0xfb, 0x23, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -973,883 +1223,1134 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20480 -// COMPRESSED SIZE (bytes): 13951 +// DATA SIZE (bytes): 38400 +// COMPRESSED SIZE (bytes): 17958 // static BINDATA_CONST NvU8 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0x39, 0x0f, 0xf4, 0xc3, 0x2d, 0xe4, 0x62, 0x7a, 0x17, 0x6c, 0x46, 0xfb, 0x5d, 0x27, 0x17, 0x32, + 0x9f, 0xff, 0x69, 0x6b, 0xa2, 0xba, 0xb3, 0x02, 0xd3, 0x3e, 0xef, 0x89, 0xca, 0xff, 0xff, 0xba, + 0x0d, 0xf0, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, + 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, + 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, + 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0x7f, 0xe0, 0xff, 0x07, 0x92, 0x43, + 0xee, 0x81, 0x00, 0x96, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1859,8 +2360,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20480, // uncompressed data size (bytes) - 13951, // compressed data size (bytes) + 38400, // uncompressed data size (bytes) + 17958, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1882,8 +2383,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x49, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x86, 0xa4, 0x95, 0x74, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x7f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x99, 0x4d, 0xfb, 0x23, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1916,31 +2417,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x3d, 0x8f, 0x43, 0x51, 0x1e, 0x76, 0xd8, 0x14, 0xef, 0x47, 0xfe, - 0x79, 0xa7, 0x4f, 0x2c, 0x63, 0x08, 0x1f, 0x93, 0x61, 0x90, 0x61, 0x8d, 0x14, 0x60, 0x06, 0x09, - 0xb0, 0x4c, 0x9b, 0x39, 0x35, 0xc5, 0xb8, 0xc4, 0x8b, 0x60, 0x4d, 0x50, 0xd0, 0x26, 0xf1, 0x91, - 0x11, 0xb0, 0x67, 0x95, 0x81, 0x01, 0x5c, 0x6c, 0xae, 0x28, 0x4c, 0x53, 0x58, 0x5f, 0x56, 0x42, - 0xc9, 0xa8, 0x74, 0x34, 0x75, 0x9e, 0x60, 0x2f, 0x89, 0xc0, 0x13, 0xaa, 0xb7, 0x1f, 0xad, 0x28, - 0x5b, 0xcf, 0xfd, 0x1d, 0x3f, 0x4a, 0xc8, 0xf7, 0x20, 0x7a, 0x0b, 0xae, 0x06, 0xef, 0xef, 0xb3, - 0xfb, 0x8d, 0xa0, 0xc4, 0xc2, 0x8b, 0x07, 0x98, 0x7d, 0x60, 0x1b, 0x48, 0xeb, 0x68, 0x94, 0xec, - 0x2e, 0x6a, 0x8e, 0x09, 0x70, 0x62, 0xe3, 0xd7, 0x73, 0x0b, 0x60, 0x19, 0x2c, 0x28, 0x03, 0xe4, - 0xd5, 0xe1, 0x0e, 0x5e, 0x1c, 0xcf, 0x1b, 0x97, 0xa9, 0xcd, 0x74, 0xc6, 0x1e, 0xec, 0xda, 0x90, - 0xa0, 0xb4, 0x46, 0xc0, 0x1e, 0x16, 0xa1, 0x51, 0x24, 0xeb, 0xb2, 0x09, 0x51, 0x7c, 0x75, 0x5a, - 0xa7, 0x4a, 0x00, 0x44, 0x3f, 0xf0, 0x27, 0x7b, 0xa3, 0xd1, 0xa0, 0x80, 0x34, 0xa2, 0xc2, 0x51, - 0xb3, 0xd0, 0x5f, 0x90, 0x87, 0x9d, 0xd3, 0x07, 0x12, 0x92, 0xc1, 0x38, 0x03, 0x0c, 0xcd, 0x90, - 0xf4, 0xe9, 0xe4, 0x8f, 0xa6, 0x51, 0xf6, 0x79, 0x5b, 0xb3, 0xf7, 0x05, 0x29, 0x8d, 0x65, 0xab, - 0x76, 0xe8, 0x8e, 0x5f, 0x7e, 0x1b, 0x72, 0x4b, 0x3b, 0x11, 0x66, 0x1f, 0x9b, 0x9d, 0xa0, 0x9a, - 0x41, 0x8d, 0xc8, 0x64, 0xdc, 0xae, 0x40, 0x91, 0x6a, 0x00, 0x48, 0x69, 0xa1, 0x00, 0xde, 0x56, - 0x77, 0x18, 0xeb, 0xc9, 0xbf, 0x39, 0x95, 0xaa, 0x16, 0x42, 0x15, 0x51, 0x94, 0xc9, 0xd1, 0x6f, - 0x75, 0x8a, 0xb3, 0xff, 0x73, 0xd5, 0xd5, 0x08, 0xe5, 0x59, 0xf1, 0x0a, 0x46, 0xf7, 0x39, 0x4d, - 0x78, 0xe2, 0x55, 0x6e, 0x69, 0x54, 0x7b, 0x21, 0x85, 0xcd, 0x99, 0x2a, 0x59, 0x3d, 0xf7, 0x43, - 0xec, 0x90, 0x4d, 0x82, 0xcb, 0xd0, 0xc4, 0xff, 0x4c, 0xfe, 0x72, 0x1b, 0x15, 0xfe, 0x60, 0x4a, - 0x74, 0x78, 0x18, 0x42, 0xcc, 0x49, 0x28, 0x63, 0x3a, 0xc6, 0x5a, 0x53, 0xd4, 0x3d, 0x5b, 0x2b, - 0xba, 0x4b, 0x52, 0xad, 0xfc, 0xc8, 0x09, 0xe1, 0x6c, 0xd4, 0xac, 0x72, 0x79, 0x62, 0xf8, 0x8f, - 0x05, 0x18, 0x2e, 0x86, 0x00, 0xf3, 0x0f, 0xa6, 0x75, 0xb8, 0x3c, 0x3a, 0x0a, 0x22, 0x90, 0xe8, - 0xc5, 0x93, 0x0b, 0x27, 0xa6, 0x45, 0xe3, 0xf7, 0x75, 0x8b, 0x4f, 0x28, 0x6f, 0xc4, 0xd6, 0x7f, - 0xd7, 0x5b, 0x26, 0xd1, 0xc8, 0x05, 0xd9, 0xbf, 0x18, 0x10, 0x52, 0x28, 0x88, 0x88, 0x77, 0x09, - 0x1d, 0x6b, 0x49, 0xd8, 0x74, 0x8f, 0x9a, 0xff, 0x6a, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x70, 0x8a, 0x98, 0xf7, 0xb3, 0x6b, 0x05, 0xac, 0x47, 0xcb, 0x02, + 0xd8, 0xbd, 0x70, 0x76, 0xdd, 0xf0, 0x55, 0x9a, 0x26, 0x72, 0xd2, 0x4f, 0x9a, 0xae, 0x27, 0x67, + 0xe2, 0x62, 0x03, 0xe8, 0xc1, 0xe3, 0xf9, 0x62, 0x03, 0x2a, 0xa7, 0x5c, 0xfb, 0x54, 0x8f, 0x35, + 0x49, 0x27, 0x41, 0x17, 0x85, 0xab, 0x5b, 0xd1, 0x5e, 0xbe, 0xef, 0xb2, 0x67, 0x95, 0x60, 0xee, + 0x0d, 0x7f, 0x75, 0xb7, 0x0a, 0xd7, 0x5e, 0x19, 0xb0, 0xf0, 0x16, 0x8e, 0xc0, 0x4d, 0xc2, 0xa1, + 0x16, 0x8c, 0xf9, 0x7a, 0xea, 0x9e, 0xb7, 0xcb, 0x82, 0x88, 0x06, 0x82, 0x89, 0x70, 0xa1, 0x48, + 0xac, 0x97, 0xed, 0x63, 0x15, 0x2f, 0xaa, 0xce, 0x86, 0x65, 0xd2, 0xff, 0x9e, 0xa6, 0x31, 0xcf, + 0x79, 0x34, 0x69, 0x88, 0x61, 0x54, 0x3b, 0x66, 0xee, 0xf4, 0x86, 0x81, 0xde, 0xd6, 0xf1, 0xc0, + 0x72, 0x62, 0xf9, 0x3c, 0xb3, 0x72, 0x18, 0x11, 0x4c, 0x01, 0xdc, 0xc7, 0xea, 0xf3, 0x7f, 0xea, + 0x00, 0xa2, 0xce, 0x92, 0x38, 0x13, 0xb6, 0x4c, 0xa2, 0xf3, 0x3c, 0x94, 0xda, 0x70, 0x29, 0x7d, + 0xb6, 0x5a, 0xc6, 0x7c, 0x42, 0x31, 0x34, 0xcf, 0x52, 0x0b, 0xcb, 0xa6, 0x51, 0x1e, 0xba, 0x5d, + 0xba, 0xae, 0x53, 0xdb, 0x82, 0x89, 0x40, 0x7b, 0xb1, 0xf1, 0xc0, 0x44, 0x3f, 0x1f, 0x75, 0xb0, + 0xf3, 0x32, 0x8b, 0x94, 0xcb, 0x52, 0x24, 0x96, 0xbf, 0x58, 0x4f, 0xb1, 0x49, 0x65, 0x9c, 0x96, + 0x4f, 0xd8, 0x64, 0xf0, 0x7b, 0xfb, 0x7d, 0x98, 0xed, 0x2d, 0xb9, 0x6a, 0x91, 0xf3, 0x12, 0x34, + 0x56, 0xec, 0x5f, 0x71, 0xf2, 0xb0, 0xa4, 0x7f, 0xb4, 0x1c, 0x56, 0xc6, 0xc5, 0x11, 0x9a, 0xae, + 0x1a, 0xbe, 0xb8, 0x9a, 0x97, 0xa4, 0x38, 0xf7, 0x1e, 0xff, 0xa7, 0x9a, 0xf1, 0xa0, 0x30, 0x55, + 0x75, 0x72, 0x09, 0xae, 0xc3, 0xcd, 0x69, 0x0d, 0x08, 0x10, 0x38, 0xdc, 0xf3, 0x68, 0x51, 0xb0, + 0xb0, 0x52, 0x44, 0x92, 0xc1, 0x84, 0xdf, 0x92, 0x70, 0x0e, 0x43, 0xae, 0x2c, 0x32, 0x2d, 0x72, + 0xe1, 0xf7, 0xcd, 0x16, 0x08, 0x5d, 0x18, 0x4f, 0xf7, 0xc7, 0xa0, 0xb0, 0xdc, 0x2a, 0xc7, 0x61, + 0x13, 0x0d, 0x3a, 0x6d, 0x14, 0xa0, 0x62, 0x44, 0xdf, 0x29, 0xb3, 0x51, 0xe2, 0x4e, 0x5b, 0xa6, + 0xa3, 0xb9, 0x23, 0xf1, 0xd8, 0xf6, 0x3d, 0x40, 0xbc, 0xe6, 0x59, 0x8f, 0xc0, 0xf9, 0xb8, 0x95, + 0xf3, 0xfa, 0x32, 0x26, 0x77, 0x72, 0x86, 0xfb, 0xac, 0x7d, 0x08, 0x48, 0x3f, 0x03, 0x90, 0xbd, + 0xbc, 0x86, 0xe4, 0xd1, 0xc0, 0x96, 0x69, 0x4e, 0x9e, 0x60, 0x0f, 0x55, 0x43, 0x7e, 0x60, 0x09, + 0x62, 0x06, 0xe9, 0x4f, 0xe1, 0x37, 0x0e, 0x0a, 0x7e, 0xcc, 0x4f, 0x66, 0xd5, 0x04, 0x31, 0xb9, + 0xf6, 0x90, 0x24, 0xc6, 0x21, 0xca, 0xe0, 0xbb, 0xb8, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1973,31 +2474,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x26, 0x87, 0xb7, 0xa1, 0xb9, 0xcd, 0xb0, 0xe8, 0x9f, 0x7d, 0x06, - 0xfc, 0xe3, 0x24, 0x48, 0x8d, 0xbf, 0x18, 0x7f, 0x07, 0x98, 0xda, 0xe7, 0x41, 0xb4, 0xde, 0x89, - 0xe8, 0x4f, 0xf1, 0xcb, 0xee, 0x09, 0xf9, 0x1b, 0xd2, 0x3a, 0x9f, 0x12, 0xce, 0x1a, 0xfa, 0xed, - 0x2d, 0x15, 0x23, 0xa6, 0x56, 0x88, 0x4f, 0xbc, 0xa5, 0x77, 0x35, 0x6a, 0x8e, 0xdb, 0x53, 0x6d, - 0x6b, 0x51, 0x58, 0xe9, 0x94, 0xed, 0x80, 0x5f, 0x6c, 0x71, 0x7a, 0x52, 0x47, 0x09, 0xbb, 0x15, - 0xa5, 0xd4, 0x2e, 0x68, 0x53, 0x26, 0xf7, 0xdb, 0x39, 0xc9, 0x52, 0xda, 0x99, 0xe1, 0xc8, 0x97, - 0x94, 0xfd, 0xa0, 0xf2, 0x95, 0x60, 0x69, 0x75, 0x83, 0x57, 0x46, 0x89, 0x13, 0xa0, 0x02, 0x21, - 0xca, 0xc2, 0x8a, 0x54, 0x46, 0xc6, 0x87, 0xf8, 0x8c, 0x54, 0x4d, 0xf8, 0xf5, 0x2f, 0xc3, 0x94, - 0x6f, 0x94, 0x5e, 0xa1, 0x89, 0xf5, 0xf4, 0x48, 0x49, 0x83, 0x9a, 0x07, 0x80, 0xe2, 0x12, 0x3e, - 0x6f, 0x2b, 0xb7, 0x05, 0xe8, 0x22, 0x0a, 0xb2, 0xc6, 0x21, 0x42, 0x03, 0x6d, 0x32, 0xf0, 0x30, - 0x32, 0x72, 0xc8, 0xb9, 0x81, 0xb4, 0xa1, 0x3d, 0x6c, 0xb9, 0xdd, 0xfc, 0xe6, 0x2a, 0x2f, 0xcb, - 0xe7, 0xe5, 0x57, 0x21, 0x3a, 0x7d, 0x29, 0x83, 0x9d, 0xc9, 0x86, 0x21, 0xbf, 0xf2, 0x8f, 0xab, - 0xa6, 0xe3, 0xe4, 0x2c, 0x36, 0xaa, 0x86, 0xd6, 0x07, 0x16, 0x90, 0x4d, 0x82, 0xdd, 0xf4, 0x6d, - 0x2d, 0x88, 0x2e, 0xa4, 0xbf, 0x35, 0x58, 0x8e, 0x1f, 0x9a, 0x52, 0xb7, 0x9d, 0x9e, 0x10, 0x95, - 0xe9, 0x7c, 0x61, 0x58, 0x76, 0xfe, 0x59, 0xf4, 0x9c, 0x83, 0x9c, 0x5e, 0xa1, 0x0c, 0x46, 0x94, - 0xac, 0xe9, 0x33, 0x01, 0x34, 0x5a, 0xca, 0x9b, 0x6e, 0x89, 0xe5, 0xc1, 0xf7, 0xc5, 0xc9, 0xb3, - 0x2b, 0x87, 0x00, 0xad, 0xa6, 0x8c, 0xa6, 0xbc, 0x81, 0xdb, 0x54, 0x2c, 0x71, 0xfe, 0xc4, 0x88, - 0x55, 0x76, 0x97, 0x9f, 0x53, 0xb3, 0xb4, 0xbe, 0x16, 0xf9, 0xf8, 0xc8, 0x2e, 0x85, 0x9a, 0x1b, - 0x14, 0x83, 0x80, 0x30, 0x99, 0x00, 0xf8, 0x34, 0xbc, 0xe4, 0xc4, 0x8c, 0xbf, 0x84, 0x9e, 0x5b, - 0xfd, 0xb3, 0x5a, 0x84, 0x4f, 0x3d, 0x59, 0xb7, 0xea, 0x5e, 0x02, 0xf3, 0xb6, 0x89, 0xdd, 0x50, - 0xa7, 0x35, 0x6e, 0xc8, 0x3f, 0x36, 0x3b, 0x67, 0xf2, 0xc0, 0x22, 0xb7, 0x0f, 0x13, 0x2d, 0x59, - 0xc8, 0x4e, 0xb3, 0x2f, 0x0e, 0xb9, 0x72, 0xe1, 0x82, 0x64, 0x0c, 0xb9, 0xe6, 0x54, 0xed, 0x99, - 0x59, 0x47, 0x77, 0xd3, 0x24, 0x38, 0xd8, 0x8c, 0xdc, 0x60, 0x4e, 0xa8, 0x25, 0x6a, 0x62, 0x3b, - 0x32, 0x39, 0xff, 0xef, 0x82, 0xb8, 0x1b, 0x78, 0x99, 0x38, 0x80, 0xef, 0x6a, 0xaf, 0xc5, 0x0d, - 0x9e, 0x9f, 0x9f, 0xae, 0x3e, 0xf6, 0x20, 0x8c, 0xc6, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x6a, 0xd1, 0x35, 0xe4, 0x21, 0xe5, 0xd4, 0xed, 0x0e, 0x20, 0x15, + 0x57, 0x58, 0x8f, 0x09, 0xb0, 0x5d, 0xec, 0xdf, 0xe1, 0x2e, 0xb2, 0x21, 0x77, 0x71, 0x39, 0x9d, + 0x8a, 0xbc, 0x9b, 0x38, 0xd1, 0x23, 0x1a, 0x98, 0xe6, 0xd5, 0xa1, 0x9c, 0xab, 0x27, 0xcb, 0xb2, + 0x9e, 0x9b, 0xf5, 0xb5, 0x08, 0x74, 0x62, 0x83, 0x57, 0x4a, 0x61, 0x4f, 0xc9, 0x2d, 0x88, 0x14, + 0xcc, 0x16, 0xb8, 0x44, 0x89, 0xe1, 0x52, 0x27, 0x90, 0x1e, 0xf2, 0x4a, 0xb0, 0x85, 0xe5, 0x1e, + 0x76, 0x92, 0xcb, 0x94, 0xb8, 0xb4, 0x65, 0xdd, 0xca, 0x81, 0xed, 0x3e, 0x89, 0x2c, 0x99, 0xda, + 0xcb, 0x39, 0x24, 0xeb, 0x25, 0x36, 0xc5, 0x40, 0xa3, 0x48, 0x12, 0x6b, 0xf7, 0xe8, 0x1d, 0x9c, + 0xfc, 0x2d, 0x7d, 0x40, 0xd7, 0x97, 0x7c, 0x63, 0xee, 0xaa, 0x1e, 0x2e, 0x97, 0x88, 0xb7, 0x1f, + 0x33, 0x45, 0xeb, 0x28, 0xde, 0x3a, 0xd4, 0x16, 0x14, 0xf6, 0x32, 0x60, 0x76, 0xe9, 0x86, 0x86, + 0x2e, 0xbb, 0x6a, 0x83, 0x8b, 0x6a, 0xb7, 0x16, 0x91, 0x20, 0x17, 0xf2, 0x21, 0x1d, 0x27, 0x7a, + 0x57, 0x03, 0x1e, 0xfd, 0x34, 0xe2, 0x3a, 0x80, 0xb8, 0xbc, 0xfb, 0xa8, 0x83, 0x7a, 0xe3, 0x6d, + 0x20, 0xd1, 0x0c, 0x31, 0x51, 0x7f, 0xe0, 0x6e, 0x70, 0x88, 0x32, 0xfc, 0xc9, 0xab, 0x8b, 0x9e, + 0x4e, 0x70, 0x0a, 0x11, 0x0b, 0x96, 0x48, 0xf7, 0x32, 0x10, 0x78, 0x2c, 0xc7, 0xb7, 0x7e, 0x47, + 0xdc, 0x8c, 0x53, 0xbc, 0xe5, 0xa7, 0x29, 0x56, 0xd6, 0xe6, 0xb1, 0x81, 0xf2, 0xa9, 0xbb, 0x95, + 0xc8, 0xe4, 0x7a, 0x49, 0x29, 0xf8, 0xbb, 0x1a, 0xd4, 0x2b, 0x47, 0x3b, 0x8d, 0x41, 0x7b, 0x92, + 0x73, 0xfe, 0xcb, 0x90, 0x04, 0x97, 0xc7, 0xb2, 0x03, 0xd1, 0xb1, 0x06, 0x32, 0x67, 0x72, 0x7a, + 0xf9, 0xa2, 0xcb, 0x7d, 0x44, 0x6a, 0xfa, 0x34, 0x93, 0x0e, 0xf3, 0xe5, 0x4f, 0x4e, 0x80, 0x6c, + 0x93, 0x10, 0x8e, 0x10, 0xb7, 0x2d, 0x8e, 0x70, 0xb0, 0x2f, 0x73, 0x97, 0x78, 0x4b, 0x06, 0x3d, + 0xd6, 0xf8, 0x89, 0xf1, 0xf8, 0x11, 0x13, 0x0f, 0xea, 0x31, 0x0b, 0x90, 0x02, 0xae, 0x38, 0x89, + 0xf4, 0xe1, 0x88, 0xc6, 0x5f, 0x4d, 0x35, 0x7e, 0x29, 0x2f, 0xb6, 0x94, 0xe9, 0xae, 0xcb, 0xda, + 0x8e, 0x1f, 0x51, 0x2f, 0xa0, 0xc6, 0x2a, 0xf1, 0xfc, 0x5a, 0x58, 0xc4, 0x11, 0x98, 0xb3, 0x1f, + 0xa5, 0x7d, 0x0a, 0xa4, 0xf7, 0x70, 0xb6, 0x8b, 0x1c, 0xcd, 0xf8, 0x24, 0xbe, 0x3e, 0xf1, 0xbe, + 0x9d, 0x7e, 0xf9, 0xde, 0xda, 0x28, 0x2e, 0x1c, 0xb5, 0x8f, 0x81, 0x2e, 0x69, 0xb3, 0x49, 0x09, + 0xe1, 0x13, 0xa6, 0xad, 0x34, 0x9c, 0x8b, 0xf9, 0xba, 0xa9, 0xd2, 0x30, 0xc1, 0x69, 0x36, 0xbe, + 0x3b, 0xcf, 0xe2, 0xd6, 0x01, 0x89, 0xc3, 0x89, 0xb7, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2030,7 +2531,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_patch_loc_data[] = { - 0x00, 0x39, 0x00, 0x00, + 0x00, 0x49, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c index 448ac7c04c..4b46314af5 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c @@ -34,917 +34,1162 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20736 -// COMPRESSED SIZE (bytes): 14495 +// DATA SIZE (bytes): 38656 +// COMPRESSED SIZE (bytes): 18402 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data[] = { - 0xed, 0xdb, 0x43, 0x97, 0x20, 0x6c, 0xac, 0x20, 0xe0, 0xb2, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x56, - 0x97, 0xab, 0xba, 0x6c, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 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0x10, 0xe0, 0xf2, 0xff, 0xfb, 0xfa, 0xff, 0xf5, 0xff, + 0x4b, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, + 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, + 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, + 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xbf, 0xe3, 0x7f, 0x00, 0x5d, 0xe2, 0xab, 0x28, 0x00, 0x97, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -954,8 +1199,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20736, // uncompressed data size (bytes) - 14495, // compressed data size (bytes) + 38656, // uncompressed data size (bytes) + 18402, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -977,8 +1222,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xb6, 0x02, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x58, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x92, 0xc7, 0x51, 0xc7, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x02, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x38, 0xcc, 0xda, 0x90, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1006,918 +1251,1162 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20736 -// COMPRESSED SIZE (bytes): 14499 +// DATA SIZE (bytes): 38656 +// COMPRESSED SIZE (bytes): 18404 // static BINDATA_CONST NvU8 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BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20736, // uncompressed data size (bytes) - 14499, // compressed data size (bytes) + 38656, // uncompressed data size (bytes) + 18404, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1950,8 +2439,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xb6, 0x02, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x58, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x92, 0xc7, 0x51, 0xc7, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x02, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x38, 0xcc, 0xda, 0x90, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1984,55 +2473,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xaf, 0xc6, 0x36, 0x42, 0xdd, 0xe8, 0x83, 0x74, 0x89, 0xbc, 0x4c, - 0x92, 0xfb, 0x8b, 0x28, 0xa4, 0xdd, 0x1c, 0x0e, 0x6f, 0x5e, 0x2f, 0x67, 0xa6, 0xcd, 0x72, 0xe7, - 0x4e, 0x12, 0xb8, 0x23, 0x7f, 0x2c, 0x4f, 0x99, 0x7a, 0xbb, 0x89, 0x6e, 0x80, 0x82, 0xdd, 0x84, - 0xc7, 0x36, 0x77, 0x46, 0x52, 0x1e, 0x77, 0xd5, 0x62, 0xb9, 0x46, 0x39, 0xe5, 0x54, 0x99, 0x38, - 0x68, 0x8d, 0x29, 0xd3, 0xcd, 0xb4, 0xcd, 0xd0, 0x1b, 0x74, 0x8e, 0x45, 0xda, 0x9d, 0x96, 0x9f, - 0x9a, 0x9e, 0x7f, 0x87, 0x7a, 0x32, 0x63, 0xb1, 0xa5, 0x22, 0x58, 0x27, 0x75, 0xf7, 0x5b, 0x3b, - 0xf0, 0xc5, 0xa5, 0xbd, 0x94, 0x27, 0xd9, 0x7f, 0x5b, 0x55, 0xdb, 0xc8, 0x78, 0xb4, 0xed, 0x5e, - 0x5b, 0xe4, 0x5a, 0x1f, 0x15, 0x4a, 0x60, 0x82, 0x31, 0x82, 0xc4, 0xc4, 0x91, 0x95, 0xcb, 0xdc, - 0x06, 0x6e, 0xe4, 0x8b, 0x1c, 0xa1, 0x3d, 0xe2, 0x4b, 0x0a, 0xa8, 0xd5, 0x47, 0x30, 0xb9, 0x42, - 0xa8, 0xf4, 0xbc, 0x27, 0xe2, 0x12, 0xc8, 0x4f, 0x72, 0xad, 0xd8, 0x34, 0x50, 0x25, 0x8c, 0x3e, - 0xdb, 0xc3, 0x8e, 0xcc, 0xf3, 0x00, 0xbd, 0x98, 0x0b, 0x3b, 0x91, 0x0a, 0x0a, 0x51, 0x24, 0x40, - 0x05, 0x57, 0x61, 0xf6, 0xad, 0xac, 0x63, 0x18, 0xe5, 0x6d, 0x18, 0x3a, 0xbf, 0x57, 0x16, 0xaa, - 0xed, 0x41, 0x0b, 0x50, 0x0b, 0xbf, 0x82, 0xcb, 0x11, 0x3f, 0xee, 0x16, 0x68, 0xa2, 0x39, 0x2f, - 0x99, 0xfc, 0x97, 0x2a, 0x98, 0x0f, 0x0d, 0xed, 0x30, 0xce, 0xba, 0xf6, 0x64, 0x23, 0x64, 0x27, - 0x3e, 0x68, 0x64, 0x7e, 0xbd, 0xcd, 0xaa, 0x71, 0x46, 0x7e, 0x7a, 0xe0, 0xda, 0xd2, 0xff, 0xf9, - 0x1e, 0x2d, 0xe9, 0x16, 0x5a, 0x52, 0x11, 0xbd, 0xe7, 0xd8, 0x61, 0xcf, 0x3e, 0x74, 0x02, 0x21, - 0xed, 0xfa, 0x6c, 0x19, 0xd6, 0x49, 0x59, 0x37, 0x51, 0x27, 0xda, 0x06, 0x54, 0xb0, 0xc4, 0xe0, - 0xb4, 0x59, 0x23, 0xc8, 0xed, 0xa9, 0x9f, 0xb0, 0xfc, 0x8b, 0x9a, 0xa7, 0x28, 0x51, 0x8c, 0x56, - 0xfe, 0xa7, 0x78, 0x03, 0xb1, 0x28, 0xac, 0x32, 0xf8, 0xe7, 0xe6, 0x24, 0xa6, 0xfd, 0xed, 0x13, - 0x1c, 0xb5, 0x9a, 0xe4, 0x45, 0xa5, 0xec, 0xf1, 0x03, 0x46, 0xb0, 0x5c, 0x95, 0xbe, 0x49, 0x79, - 0x39, 0x28, 0xad, 0xa6, 0x62, 0x28, 0xc2, 0x92, 0xbe, 0x95, 0xca, 0x6e, 0xdb, 0xea, 0xdf, 0xf6, - 0xb4, 0xba, 0x55, 0xf3, 0x65, 0xcf, 0x02, 0xfd, 0xff, 0x64, 0x56, 0xfb, 0x4a, 0x3c, 0x2a, 0x3b, - 0xb7, 0x7f, 0xdb, 0x9b, 0x0c, 0x9b, 0x6a, 0xd8, 0xd8, 0xba, 0xaa, 0xb8, 0x7f, 0x85, 0xf6, 0x98, - 0x11, 0x7b, 0xcc, 0x11, 0xf6, 0x56, 0xec, 0x73, 0x70, 0x84, 0xfe, 0x93, 0x89, 0x0f, 0x07, 0xe5, - 0x03, 0xde, 0x37, 0x6d, 0x12, 0x6a, 0x07, 0xdf, 0x6d, 0xb1, 0x85, 0xba, 0x42, 0x10, 0x9b, 0x2c, - 0x48, 0x1f, 0xcd, 0xab, 0x16, 0x22, 0x2a, 0xfb, 0x9e, 0x18, 0xeb, 0xe4, 0xfd, 0xa1, 0xf2, 0xe1, - 0xc3, 0xf3, 0x80, 0xe2, 0xe5, 0x50, 0x02, 0xa6, 0x79, 0xd8, 0xd6, 0x04, 0xad, 0x89, 0x01, 0x32, - 0x5c, 0x45, 0xf7, 0x15, 0x07, 0x8f, 0x0e, 0xba, 0xe3, 0x34, 0x6f, 0x3c, 0x5f, 0xcd, 0x57, 0x1a, - 0x0f, 0x54, 0xc6, 0xa3, 0x56, 0xbb, 0x41, 0x72, 0xc5, 0x1b, 0xa2, 0x5c, 0xcb, 0x49, 0x4a, 0x87, - 0xac, 0xf2, 0x44, 0x68, 0x40, 0xda, 0xfc, 0xec, 0xa8, 0xfb, 0xb5, 0xb5, 0xbc, 0xc3, 0x4e, 0x87, - 0xf6, 0x6c, 0x18, 0x93, 0x16, 0x6e, 0x47, 0x64, 0x26, 0x55, 0x04, 0x33, 0x01, 0x5a, 0xd3, 0x2f, - 0xa7, 0x9f, 0x53, 0x9c, 0x13, 0x09, 0x8e, 0x06, 0x03, 0xe2, 0x1c, 0xe4, 0x78, 0xcf, 0xe5, 0x0d, - 0x7b, 0xd9, 0xea, 0xc7, 0x47, 0x3a, 0xf3, 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0x3b, 0x7b, 0x46, 0xc6, 0x31, 0x31, 0x71, 0x1c, 0x13, 0x2f, 0xb0, 0x4f, 0xd0, 0x41, 0x27, 0xed, + 0xfc, 0xc7, 0x24, 0xc2, 0x2d, 0x3f, 0xa7, 0x07, 0x1a, 0xba, 0xb2, 0x9d, 0x4c, 0x65, 0x88, 0xd0, + 0xa2, 0x4a, 0x18, 0xd6, 0x1a, 0x20, 0xd3, 0xd1, 0xb4, 0xb7, 0x85, 0xda, 0x1f, 0x56, 0xd6, 0x06, + 0xb0, 0x6b, 0xa5, 0x5f, 0x38, 0xec, 0xd1, 0x86, 0x67, 0x14, 0x9e, 0x87, 0x84, 0xb7, 0x84, 0xe1, + 0x16, 0x35, 0x9b, 0x4f, 0x98, 0xd2, 0x9d, 0xd2, 0x77, 0xe9, 0xe8, 0x45, 0xd7, 0x6d, 0xa4, 0x35, + 0xa3, 0xe2, 0x6f, 0xb6, 0xae, 0x63, 0x8e, 0x31, 0x30, 0x10, 0x78, 0xdd, 0x20, 0x2b, 0xd4, 0xff, + 0x62, 0x1b, 0xe6, 0xff, 0x87, 0x30, 0xd2, 0x8e, 0x7c, 0xc2, 0xf0, 0x36, 0x3e, 0x4e, 0x2b, 0xd1, + 0xdb, 0x11, 0x06, 0x28, 0x00, 0xe3, 0x1a, 0xb3, 0x3f, 0x2e, 0x4a, 0xd1, 0x81, 0x30, 0xf3, 0x54, + 0x19, 0xd8, 0xdc, 0xcb, 0x45, 0x5e, 0x0d, 0xa5, 0xe6, 0x21, 0x38, 0xab, 0xa5, 0x5c, 0xab, 0x33, + 0xe1, 0x49, 0x7f, 0xb1, 0x3a, 0xa9, 0x8d, 0x61, 0x93, 0x10, 0x38, 0x25, 0xd7, 0x61, 0xfd, 0xe5, + 0xaa, 0x67, 0x9b, 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0xb1, 0xb2, 0xfc, 0xf9, 0xe9, 0xd5, 0x71, + 0x0f, 0xa1, 0x19, 0x5b, 0xb8, 0x0f, 0x52, 0x45, 0x1e, 0x91, 0x0f, 0x1d, 0x81, 0x4b, 0x63, 0x82, + 0xa2, 0xa8, 0xa6, 0x6e, 0x69, 0xfe, 0xf2, 0x5b, 0xd5, 0xf7, 0xef, 0x5a, 0xe7, 0xb7, 0xa5, 0x6d, + 0xd5, 0x7f, 0x4f, 0xec, 0x98, 0xc1, 0x03, 0x0a, 0x50, 0xb4, 0x2f, 0x48, 0x38, 0x8c, 0x81, 0x85, + 0x6c, 0x2a, 0xa6, 0xfa, 0xb4, 0x4e, 0x5b, 0x8f, 0x3d, 0x53, 0x72, 0x65, 0x10, 0x9f, 0x61, 0xc9, + 0x02, 0x2a, 0xb7, 0xb9, 0x3a, 0x5f, 0xcc, 0xd8, 0xbe, 0x42, 0x4f, 0x5d, 0xd1, 0xc9, 0xb8, 0x52, + 0x04, 0x4a, 0xb4, 0x5c, 0xb5, 0xe4, 0x0a, 0x8b, 0x02, 0xc9, 0x00, 0x1f, 0x86, 0x4f, 0x0f, 0xb3, + 0xcf, 0x50, 0x12, 0x51, 0x38, 0x56, 0x52, 0xce, 0x98, 0x6c, 0x05, 0x46, 0x54, 0x87, 0xc7, 0xd3, + 0x06, 0x93, 0x4b, 0x21, 0x29, 0x2f, 0xf1, 0x48, 0xe1, 0x1d, 0x5a, 0x99, 0x71, 0x07, 0x50, 0x2a, + 0x63, 0xa5, 0xb8, 0x64, 0xdd, 0x55, 0x8e, 0x60, 0x70, 0xd6, 0x3d, 0x8f, 0x2b, 0xee, 0x8f, 0x90, + 0x86, 0xd9, 0xda, 0x94, 0x53, 0x48, 0x84, 0xe4, 0xd6, 0xb8, 0x28, 0x23, 0x70, 0xc2, 0xea, 0xbb, + 0x8c, 0x14, 0x23, 0x03, 0x08, 0xf1, 0x97, 0x4a, 0xce, 0xc1, 0x6f, 0x5c, 0x29, 0xb6, 0x8c, 0xb4, + 0x29, 0x2b, 0x4a, 0xf1, 0x82, 0x00, 0x78, 0x55, 0xe6, 0x83, 0x5a, 0xfd, 0xbc, 0x4e, 0x0e, 0x1c, + 0x17, 0xbb, 0x53, 0x14, 0xaf, 0x2c, 0x82, 0x24, 0xcc, 0x83, 0x8e, 0xfb, 0xe7, 0xe9, 0xb9, 0xf3, + 0xda, 0x45, 0x4c, 0xbe, 0xc1, 0x19, 0x26, 0x99, 0x33, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2061,37 +2550,36 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 418 +// COMPRESSED SIZE (bytes): 415 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data[] = { - 0xb3, 0xfa, 0x7f, 0xa2, 0xf2, 0xa0, 0xc0, 0x7e, 0x73, 0x4e, 0x21, 0x83, 0xa7, 0xec, 0x5f, 0x42, - 0xb6, 0x78, 0x3e, 0x73, 0xae, 0x5c, 0x7f, 0x85, 0x49, 0xd6, 0x24, 0xb6, 0xea, 0x58, 0x21, 0xf7, - 0xf5, 0x9f, 0x39, 0x7d, 0xd3, 0x55, 0xbb, 0xad, 0x85, 0x34, 0x66, 0xb9, 0xf9, 0x4c, 0x4d, 0xfb, - 0xcd, 0xfa, 0x7e, 0xf7, 0x8e, 0xc3, 0xe5, 0xd3, 0xc5, 0xeb, 0x6d, 0x24, 0x3f, 0x39, 0xef, 0x60, - 0xd3, 0x33, 0xfa, 0xfb, 0x95, 0x33, 0x3a, 0x6f, 0x67, 0x65, 0x8d, 0x69, 0xe2, 0xb2, 0x0e, 0xef, - 0x4d, 0x75, 0x52, 0x75, 0xf6, 0x37, 0x96, 0xee, 0x95, 0xbc, 0xed, 0xa8, 0x69, 0x67, 0x6b, 0xde, - 0xbb, 0x6b, 0x69, 0x9b, 0x68, 0xe3, 0x86, 0x9b, 0xc7, 0xef, 0xa7, 0x84, 0x7e, 0xd5, 0x5d, 0x71, - 0x2b, 0x62, 0x83, 0xee, 0x01, 0x83, 0x25, 0x12, 0xed, 0xff, 0x2f, 0x85, 0xaa, 0x28, 0x04, 0x71, - 0x1b, 0x68, 0xab, 0x86, 0x79, 0xbf, 0xfb, 0x1d, 0x58, 0xf4, 0xc6, 0x52, 0xf3, 0x40, 0xbf, 0xc5, - 0x9d, 0x20, 0x83, 0x95, 0xdf, 0xfe, 0x2b, 0x6a, 0x4b, 0xfd, 0x31, 0x7a, 0x56, 0xd1, 0x16, 0xf4, - 0x7c, 0x79, 0xcc, 0xf7, 0x6d, 0x61, 0xb7, 0xda, 0x7f, 0xf4, 0xb9, 0x48, 0x3c, 0x32, 0x7b, 0xb0, - 0xe2, 0x92, 0xd0, 0xa5, 0xc0, 0x6d, 0x0e, 0x66, 0xfa, 0xea, 0x8e, 0x8e, 0xa7, 0x0f, 0xfa, 0x9e, - 0x8e, 0x2b, 0xee, 0xe0, 0xe8, 0x3b, 0x70, 0xdd, 0xd3, 0xc1, 0xa8, 0xfe, 0xdf, 0xb4, 0xbf, 0xa7, - 0x1a, 0x97, 0x77, 0xd8, 0xc4, 0x29, 0x1b, 0x2e, 0x29, 0xaa, 0x58, 0x3b, 0xef, 0xea, 0x86, 0x5e, - 0xd1, 0xed, 0x21, 0x53, 0xbf, 0x08, 0x4f, 0xb4, 0x5c, 0x31, 0x6f, 0x71, 0x75, 0x71, 0xdf, 0xb6, - 0x1d, 0x5f, 0x3c, 0xe7, 0xee, 0xfc, 0xb6, 0xc2, 0xdb, 0x87, 0x49, 0xc3, 0xce, 0x46, 0xa0, 0xd9, - 0xf2, 0x71, 0xcd, 0x92, 0x03, 0x76, 0xff, 0x7c, 0xfe, 0x7c, 0x71, 0x28, 0xf7, 0x35, 0xb1, 0x7a, - 0x1b, 0x33, 0x7f, 0xf5, 0xee, 0xbe, 0xd2, 0x19, 0x33, 0x3e, 0x39, 0x76, 0x2d, 0x57, 0x7b, 0x1e, - 0x6f, 0xda, 0x7e, 0x21, 0x9c, 0x3f, 0x96, 0x39, 0x8e, 0xaf, 0xbc, 0x44, 0xab, 0x45, 0x77, 0x11, - 0x73, 0xf2, 0xfa, 0x8f, 0xe1, 0x7d, 0xff, 0xcc, 0x2e, 0x5b, 0xca, 0x95, 0xdd, 0xfd, 0xf6, 0xc5, - 0xfe, 0xc7, 0xe3, 0x5f, 0xb1, 0x8e, 0x3b, 0xc5, 0xa7, 0x5e, 0x66, 0xe5, 0xf9, 0xb0, 0x49, 0x70, - 0x7d, 0x6c, 0xeb, 0xd5, 0x0c, 0x66, 0xf6, 0x06, 0xe7, 0x82, 0xdd, 0x35, 0x59, 0x7d, 0x5f, 0xef, - 0xfc, 0x7b, 0xb3, 0x5c, 0x3d, 0xfd, 0x93, 0x5f, 0xed, 0xc5, 0x55, 0xc1, 0xa7, 0x8b, 0xcf, 0xda, - 0x3f, 0xe9, 0x65, 0xfd, 0xc9, 0xc8, 0x5d, 0x38, 0x75, 0xb9, 0x62, 0x8b, 0xc3, 0x97, 0xad, 0x4a, - 0xd7, 0x8f, 0x34, 0x4c, 0x6e, 0x99, 0x1f, 0xd7, 0xff, 0xe8, 0x88, 0x41, 0xce, 0xba, 0xb6, 0x69, - 0x97, 0x45, 0x4b, 0xec, 0x19, 0x46, 0xc1, 0x80, 0x02, 0x00, 0x5a, 0x0e, 0xb9, 0xb4, 0x00, 0x03, - 0x00, 0x00, + 0x7b, 0x39, 0x27, 0xe8, 0xf1, 0xcb, 0x47, 0x17, 0x13, 0x0c, 0x8c, 0x2c, 0x8b, 0xf8, 0x1b, 0x7e, + 0xef, 0x09, 0xaf, 0xd5, 0x36, 0x6e, 0xe4, 0xea, 0x32, 0xca, 0x98, 0xe8, 0x6d, 0xbd, 0xa2, 0xfd, + 0x99, 0x87, 0xd5, 0x26, 0xa9, 0xbd, 0x8b, 0x4c, 0x96, 0x06, 0x7b, 0x08, 0xed, 0xbe, 0x16, 0x54, + 0x26, 0xf7, 0xf4, 0x73, 0x73, 0x0b, 0x73, 0xc6, 0x1f, 0x36, 0x36, 0x6d, 0xc3, 0x46, 0xe9, 0xd2, + 0xe9, 0xd5, 0x6e, 0xf7, 0xdd, 0xeb, 0x7c, 0x8e, 0xec, 0x60, 0x8b, 0xad, 0xf6, 0x79, 0xc4, 0x75, + 0xc3, 0x66, 0xaf, 0xe8, 0xc2, 0x88, 0x43, 0xdb, 0xee, 0x0b, 0xfb, 0xd6, 0x9f, 0x0a, 0xdd, 0x57, + 0xa5, 0x72, 0x68, 0x83, 0xd0, 0x8c, 0xef, 0x3b, 0x0f, 0x9c, 0xfb, 0xec, 0xf6, 0x64, 0xa6, 0xe1, + 0x8f, 0xe2, 0xc2, 0x84, 0x18, 0xaf, 0xbb, 0x26, 0xe2, 0x09, 0x39, 0x55, 0x67, 0xdf, 0x74, 0xcd, + 0x63, 0xb5, 0x57, 0xfd, 0xa5, 0x75, 0x5e, 0x69, 0x91, 0x71, 0xb9, 0xfd, 0xdc, 0x9e, 0xe0, 0x99, + 0xcf, 0x4c, 0xf4, 0x5e, 0x7b, 0xff, 0xba, 0xb5, 0x6e, 0x87, 0x9f, 0xb7, 0x84, 0xa3, 0xee, 0x9b, + 0xac, 0x9b, 0xf7, 0xef, 0xb9, 0x25, 0x7f, 0x8c, 0x8a, 0xa9, 0xd8, 0x60, 0xde, 0xfa, 0x2d, 0xe1, + 0x95, 0xbf, 0x83, 0xa7, 0x74, 0x41, 0xea, 0xda, 0x5e, 0x99, 0xe9, 0x91, 0x7f, 0x73, 0x38, 0xc4, + 0x04, 0xd9, 0x02, 0x39, 0x67, 0x44, 0xf4, 0xf7, 0xf2, 0xb9, 0xa5, 0xaf, 0x77, 0x33, 0xfb, 0x97, + 0xc5, 0x13, 0x19, 0xb1, 0xb8, 0xf9, 0x6a, 0x83, 0x9b, 0x88, 0x56, 0x4f, 0xa9, 0xdf, 0xc7, 0x52, + 0x87, 0x40, 0x59, 0xe3, 0xe2, 0xc7, 0xdc, 0xfb, 0x3d, 0xf9, 0x56, 0x4e, 0x39, 0x75, 0x28, 0x54, + 0xae, 0xe8, 0x38, 0xeb, 0x64, 0x7d, 0xdb, 0x36, 0xeb, 0x32, 0xfe, 0xca, 0x0f, 0xeb, 0xd6, 0x49, + 0x06, 0xf2, 0xde, 0xe7, 0xde, 0x5d, 0xad, 0x1c, 0x98, 0x99, 0x7b, 0xb9, 0x20, 0xa5, 0xa6, 0xf5, + 0xd9, 0x96, 0xe0, 0x5c, 0xa7, 0x28, 0x46, 0xff, 0x1f, 0x93, 0x99, 0xb8, 0x85, 0x39, 0x17, 0xac, + 0x7b, 0x5f, 0xe0, 0xc7, 0xb1, 0xd0, 0x60, 0xd9, 0x56, 0x5f, 0x87, 0xb7, 0xc6, 0x2c, 0x4d, 0x1b, + 0x99, 0x6d, 0x7e, 0x5f, 0x99, 0xd0, 0x37, 0x25, 0x4e, 0xcb, 0x6a, 0x1a, 0x9f, 0x68, 0x72, 0x7b, + 0x27, 0xd7, 0x1d, 0xed, 0xbf, 0xcf, 0x95, 0x25, 0x0f, 0x7a, 0x74, 0x97, 0x68, 0xff, 0x55, 0x0b, + 0x72, 0x52, 0xfa, 0x67, 0x5b, 0x5b, 0x1d, 0x7c, 0xc5, 0xf8, 0xda, 0xc3, 0x32, 0x49, 0xe6, 0x8e, + 0xce, 0x3e, 0x51, 0xfb, 0x73, 0xb2, 0xee, 0x92, 0x71, 0x5b, 0x23, 0x6f, 0xcb, 0x3f, 0x74, 0xbd, + 0xf2, 0x7a, 0xe7, 0x54, 0x3b, 0xdb, 0xee, 0x8f, 0x32, 0xfd, 0x1b, 0xb4, 0xa6, 0xfe, 0x72, 0x7b, + 0xc9, 0x13, 0xb3, 0x94, 0x65, 0x8b, 0x9e, 0xde, 0xf3, 0xcf, 0x0a, 0xe6, 0x1f, 0x4f, 0x44, 0xc7, + 0x2d, 0x64, 0x18, 0x05, 0x03, 0x0a, 0x00, 0x33, 0xd5, 0x6c, 0xbd, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2102,7 +2590,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 418, // compressed data size (bytes) + 415, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2124,7 +2612,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_patch_loc_data[] = { - 0x10, 0x3a, 0x00, 0x00, + 0x10, 0x4a, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c index 19a88d95a7..d2543b4c28 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c @@ -34,883 +34,1131 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 19968 -// COMPRESSED SIZE (bytes): 13941 +// DATA SIZE (bytes): 37888 +// COMPRESSED SIZE (bytes): 17918 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data[] = { - 0xed, 0xfa, 0x43, 0x90, 0x26, 0xef, 0x13, 0x30, 0x6a, 0x3f, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0xdd, 0x3d, 0x6d, 0xdb, 0xe6, 0xb4, 0x6d, 0x63, 0xda, 0xb6, 0x6d, 0x1b, 0xd3, 0xb6, 0x6d, 0x9e, - 0xdf, 0xfb, 0xed, 0xbe, 0xff, 0xe6, 0x8d, 0xb3, 0x3d, 0x31, 0xd7, 0x26, 0xef, 0xac, 0x88, 0xaa, - 0xac, 0x5a, 0x54, 0x45, 0x56, 0xe4, 0x2d, 0x05, 0x40, 0x9c, 0xc9, 0x00, 0xc4, 0x19, 0xa2, 0x03, - 0xba, 0x0f, 0xf3, 0xdf, 0x9a, 0xbf, 0x81, 0xa4, 0x00, 0x48, 0xff, 0xe7, 0x80, 0x05, 0x3a, 0xe0, - 0xff, 0x97, 0xfe, 0x06, 0x00, 0x80, 0xbe, 0x93, 0x01, 0x7e, 0x0c, 0x00, 0xc0, 0x2b, 0xf0, 0x2b, - 0xe0, 0x0d, 0x38, 0x06, 0x00, 0x0c, 0xe8, 0xdd, 0xde, 0xf9, 0xf9, 0xf9, 0x41, 0xf8, 0x0d, 0x00, - 0x02, 0xfc, 0xe4, 0x81, 0x36, 0x1e, 0x02, 0x58, 0xd2, 0xd7, 0x81, 0x1a, 0x93, 0x01, 0xb4, 0xe9, - 0xeb, 0xc0, 0xff, 0x05, 0xb2, 0xf4, 0x75, 0x90, 0xff, 0x02, 0xfe, 0x7f, 0xe7, 0x02, 0xd2, 0xf3, - 0x40, 0x9a, 0x77, 0x40, 0x7a, 0xf3, 0xf2, 0x77, 0xd2, 0xf3, 0x80, 0xd2, 0x33, 0x80, 0x9b, 0x77, - 0x80, 0x9a, 0xd7, 0x81, 0xfd, 0x56, 0x00, 0x00, 0x04, 0x26, 0x29, 0x00, 0xe2, 0x4b, 0x1e, 0x00, - 0xe1, 0xbf, 0x1a, 0xe6, 0xa0, 0xff, 0x67, 0x01, 0xd7, 0x96, 0x01, 0x00, 0x02, 0xfe, 0x6f, 0xf5, - 0xc8, 0x0b, 0x1c, 0x07, 0x00, 0x80, 0xff, 0xfe, 0xaf, 0xd4, 0x57, 0x1e, 0x58, 0xf7, 0xe3, 0xfb, - 0x1b, 0xf8, 0x2b, 0xc8, 0x7f, 0x57, 0x03, 0x4e, 0x41, 0x80, 0xdc, 0xfe, 0x3f, 0x95, 0xbf, 0xde, - 0xc0, 0x7e, 0x03, 0x38, 0x00, 0x5f, 0xb9, 0xa0, 0x9d, 0xf1, 0xc0, 0x2d, 0xc9, 0x88, 0xff, 0xe5, - 0xdf, 0xef, 0x00, 0xbf, 0xff, 0xee, 0xe7, 0x15, 0xb8, 0xbb, 0xf8, 0x03, 0x28, 0x2e, 0xad, 0x12, - 0xea, 0x77, 0xdd, 0x7f, 0x8f, 0x90, 0xf7, 0x0a, 0x88, 0xfb, 0x2f, 0xf6, 0xfe, 0x3c, 0x32, 0x7e, - 0x7e, 0x4b, 0x01, 0xe5, 0xe7, 0xf1, 0xdf, 0x02, 0xfe, 0xff, 0x40, 0xad, 0xe9, 0x91, 0x2f, 0x8e, - 0x96, 0x94, 0x25, 0xae, 0xab, 0x71, 0x5c, 0x91, 0x8b, 0xe1, 0xe5, 0x0a, 0xea, 0xb4, 0xe8, 0x4b, - 0x19, 0x96, 0xda, 0x45, 0x1d, 0xe3, 0x1c, 0x10, 0x99, 0x15, 0x7c, 0xbb, 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0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, + 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, + 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, + 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, + 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, + 0xe3, 0xc7, 0xff, 0x47, 0xfe, 0x2f, 0xd1, 0x43, 0xab, 0x12, 0x00, 0x94, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -920,8 +1168,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 19968, // uncompressed data size (bytes) - 13941, // compressed data size (bytes) + 37888, // uncompressed data size (bytes) + 17918, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -943,8 +1191,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, - 0x20, 0x00, 0x00, 0xda, 0x95, 0xe6, 0x99, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -972,883 +1220,1131 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 19968 -// COMPRESSED SIZE (bytes): 13940 +// DATA SIZE (bytes): 37888 +// COMPRESSED SIZE (bytes): 17914 // static BINDATA_CONST NvU8 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0xaf, 0x5f, 0xbf, 0x7e, 0xfd, + 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, + 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, + 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0xfe, 0x3f, 0xf2, + 0x7f, 0x01, 0x58, 0x3a, 0xb1, 0xf5, 0x00, 0x94, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1858,8 +2354,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 19968, // uncompressed data size (bytes) - 13940, // compressed data size (bytes) + 37888, // uncompressed data size (bytes) + 17914, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1881,8 +2377,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, - 0x20, 0x00, 0x00, 0xda, 0x95, 0xe6, 0x99, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1915,7 +2411,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_data[] = { - 0x10, 0xf0, 0x2c, 0x6d, 0xec, 0xb3, 0x69, 0x81, 0x7f, 0x52, 0x0a, 0x94, 0x5d, 0x50, 0x0b, 0xdf, + 0x74, 0xa9, 0x48, 0xda, 0x1d, 0xf2, 0x3f, 0x30, 0xae, 0xee, 0x5c, 0x6e, 0x29, 0xf0, 0x7b, 0xf6, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1948,7 +2444,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_data[] = { - 0xa3, 0xad, 0x00, 0x41, 0x0c, 0xf3, 0x83, 0x0d, 0x21, 0x82, 0x37, 0x80, 0xcd, 0x36, 0xa6, 0x4d, + 0x8e, 0x59, 0xca, 0x0a, 0x99, 0x27, 0x9b, 0xb4, 0xab, 0xee, 0x71, 0x1b, 0x81, 0xf9, 0x44, 0xbc, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1981,7 +2477,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_patch_loc_data[] = { - 0x00, 0x39, 0x00, 0x00, + 0x00, 0x49, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c index ff78b68c57..f9ef318ed5 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c @@ -34,881 +34,1132 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 19968 -// COMPRESSED SIZE (bytes): 13907 +// DATA SIZE (bytes): 37888 +// COMPRESSED SIZE (bytes): 17934 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data[] = { - 0xed, 0xdb, 0x53, 0x90, 0xef, 0x5a, 0xd4, 0x20, 0xf0, 0x7f, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0x3c, 0x6d, 0xdb, 0xb6, 0xdd, 0xa7, 0x6d, 0xdb, 0xb6, 0xbb, 0x4f, 0xdb, 0x36, 0x4e, 0xbb, - 0xe7, 0x7e, 0xf3, 0x36, 0xf7, 0x65, 0x6a, 0x5e, 0xa7, 0xee, 0xef, 0x65, 0xed, 0x9d, 0xaa, 0x64, - 0xed, 0x54, 0x2a, 0xa9, 0x9d, 0xac, 0x1d, 0x29, 0x00, 0xe2, 0x6c, 0x26, 0x20, 0xde, 0x10, 0x1d, - 0xd0, 0x73, 0x54, 0xf0, 0xd6, 0xf2, 0x0d, 0x24, 0x05, 0x40, 0xfa, 0x9f, 0x0d, 0x96, 0xe8, 0x80, - 0xff, 0xdd, 0x8d, 0x04, 0x00, 0x80, 0xbe, 0x53, 0x00, 0x7e, 0x0c, 0x00, 0xc0, 0x2b, 0xf0, 0x2b, - 0xe0, 0x0d, 0x38, 0x16, 0x00, 0x0c, 0xe8, 0xdb, 0xd9, 0xfd, 0xf9, 0xf9, 0x41, 0x88, 0x04, 0x00, - 0x01, 0x7e, 0xf2, 0x41, 0x9b, 0x8e, 0x00, 0x2c, 0x19, 0x1b, 0x40, 0x4d, 0x29, 0x00, 0xda, 0x8c, - 0x0d, 0xe0, 0x7f, 0x02, 0x59, 0xc6, 0x06, 0xc8, 0x3f, 0x01, 0xff, 0x9f, 0x7d, 0x01, 0x19, 0xf9, - 0x20, 0x2d, 0xbb, 0x20, 0x7d, 0xf9, 0x05, 0xbb, 0x19, 0xf9, 0x40, 0x19, 0x99, 0xc0, 0x2d, 0xbb, - 0x40, 0x2d, 0x1b, 0xc0, 0x7e, 0xab, 0x00, 0x00, 0x02, 0x93, 0x14, 0x00, 0xf1, 0x6f, 0x3e, 0x00, - 0xe1, 0x9f, 0x1c, 0x16, 0xa0, 0xff, 0xd3, 0x80, 0x6b, 0xcf, 0x04, 0x00, 0x01, 0xff, 0xd3, 0x7a, - 0xe2, 0x05, 0x8e, 0x07, 0x00, 0xc0, 0x23, 0xff, 0x49, 0xf5, 0x95, 0x0f, 0xd6, 0xf3, 0xf4, 0xfe, - 0x06, 0xfe, 0x0a, 0xf2, 0xcf, 0xd1, 0x80, 0x53, 0x11, 0x20, 0x77, 0xfe, 0x27, 0xf3, 0xd7, 0x1b, - 0x58, 0x24, 0x80, 0x03, 0xf0, 0x95, 0x07, 0xda, 0x95, 0x00, 0xdc, 0x9a, 0x82, 0xf8, 0x4f, 0xff, - 0xfb, 0x1d, 0xe0, 0xf7, 0xcf, 0x78, 0x5e, 0x81, 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defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 19968, // uncompressed data size (bytes) - 13907, // compressed data size (bytes) + 37888, // uncompressed data size (bytes) + 17934, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -941,8 +1192,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, - 0x20, 0x00, 0x00, 0xda, 0x95, 0xe6, 0x99, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -970,881 +1221,1132 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 19968 -// COMPRESSED SIZE (bytes): 13906 +// DATA SIZE (bytes): 37888 +// COMPRESSED SIZE (bytes): 17936 // static BINDATA_CONST NvU8 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0xc9, 0x6c, 0x60, 0x7a, 0x3d, 0xd8, 0x02, 0x79, 0x92, 0xd1, 0x21, 0x9f, + 0xf9, 0x0f, 0x59, 0x4d, 0x29, 0xaf, 0x81, 0x32, 0x2d, 0x6f, 0x5d, 0xb7, 0x09, 0x26, 0xa0, 0xc1, + 0x14, 0x6e, 0x4c, 0x9f, 0x90, 0x06, 0x6d, 0xb3, 0x5d, 0xac, 0x4a, 0x6b, 0xbf, 0xc8, 0xac, 0x90, + 0x74, 0x0c, 0x5e, 0x5c, 0xc5, 0xfc, 0x59, 0xec, 0xf8, 0xcc, 0xbe, 0x9e, 0x2f, 0x9f, 0x52, 0xa0, + 0x15, 0x26, 0x08, 0xbb, 0x53, 0x63, 0x04, 0x7c, 0x32, 0x41, 0x50, 0x20, 0xd1, 0x39, 0x54, 0xc2, + 0xd3, 0x18, 0x09, 0x19, 0xbc, 0x19, 0x35, 0x97, 0x4a, 0x0b, 0x2a, 0x40, 0x56, 0x70, 0xbb, 0x44, + 0xc5, 0x10, 0x62, 0x56, 0x76, 0x85, 0xcd, 0x30, 0x55, 0x6e, 0x3f, 0x94, 0x2a, 0xbe, 0x71, 0xdc, + 0x03, 0xdd, 0xbc, 0xbd, 0x02, 0x4c, 0x3f, 0xbc, 0x95, 0x4d, 0x7f, 0xf1, 0xa7, 0x21, 0xd7, 0x6c, + 0xb4, 0x0f, 0x8f, 0x82, 0xb5, 0x1c, 0x89, 0x30, 0x4a, 0x2a, 0xb5, 0xa4, 0x68, 0xea, 0xf8, 0xef, + 0x93, 0xb7, 0xad, 0xee, 0xbd, 0x94, 0xce, 0x35, 0x4c, 0xad, 0x47, 0x1b, 0x8d, 0xbb, 0x51, 0x6a, + 0x40, 0x75, 0x46, 0x78, 0x12, 0x4e, 0x1a, 0x0a, 0x45, 0x81, 0x96, 0xa6, 0xc4, 0xbf, 0x27, 0xf7, + 0x2d, 0x16, 0xb4, 0x8d, 0xc9, 0xbe, 0xb8, 0x90, 0x93, 0x00, 0x3f, 0x2a, 0x29, 0xe2, 0x4d, 0x80, + 0xdb, 0xed, 0xbc, 0x59, 0x97, 0x36, 0x29, 0x84, 0x14, 0x77, 0x5f, 0xad, 0x24, 0x22, 0x80, 0xa6, + 0xaa, 0x53, 0xb4, 0x8a, 0x15, 0xff, 0x46, 0xcd, 0xa1, 0x77, 0x37, 0xde, 0x24, 0x15, 0x6b, 0x9d, + 0x78, 0x74, 0x95, 0x89, 0x41, 0xc1, 0x5c, 0x6e, 0x65, 0x97, 0x08, 0xa3, 0xed, 0x55, 0x25, 0x84, + 0x60, 0x72, 0x3a, 0x59, 0x6b, 0x6f, 0xff, 0xaa, 0x7b, 0x21, 0xd8, 0x40, 0xc2, 0xda, 0xf6, 0x79, + 0x40, 0xae, 0x13, 0x6c, 0x24, 0x71, 0x65, 0x5d, 0x4b, 0xcf, 0x11, 0x07, 0xce, 0x74, 0x64, 0x67, + 0x1d, 0x26, 0xd8, 0xbc, 0x25, 0x05, 0x83, 0x57, 0x3b, 0xcd, 0x19, 0xf3, 0xdc, 0xca, 0xda, 0xfe, + 0xdd, 0x35, 0x28, 0x92, 0x62, 0x1f, 0xc6, 0x6a, 0x24, 0xe7, 0x1a, 0x5f, 0x14, 0x15, 0xf9, 0x94, + 0x39, 0xec, 0x5a, 0x13, 0xe9, 0x65, 0x50, 0x84, 0x50, 0x5c, 0x14, 0xa9, 0x9c, 0x1b, 0x26, 0xf2, + 0xa0, 0xf4, 0x29, 0x8e, 0xa7, 0xc2, 0x4f, 0x06, 0x3a, 0xdb, 0x7a, 0xb7, 0x73, 0x33, 0x2c, 0x9f, + 0x05, 0xe3, 0x0a, 0x0e, 0xe6, 0x89, 0xc0, 0x79, 0x21, 0xdc, 0x05, 0x97, 0xa5, 0xfc, 0x97, 0x3a, + 0x63, 0x84, 0x3f, 0xfc, 0xcd, 0xb1, 0x8d, 0xf7, 0xa9, 0xb9, 0x9d, 0x2d, 0xf8, 0x86, 0xf4, 0xf3, + 0x15, 0xb7, 0xd0, 0x0f, 0xb4, 0x57, 0x56, 0x75, 0x4a, 0x68, 0x0e, 0xd8, 0x02, 0xe9, 0xa4, 0x60, + 0xe7, 0xed, 0x23, 0x30, 0x16, 0xc8, 0x1a, 0x79, 0x4f, 0x50, 0xd4, 0x78, 0xdf, 0x40, 0xfb, 0xc3, + 0xf2, 0x90, 0xac, 0x8a, 0xdb, 0xfd, 0x28, 0x6b, 0x0d, 0x04, 0x55, 0xb2, 0x9d, 0x43, 0xbf, 0x1c, + 0x05, 0x28, 0xe6, 0x00, 0x35, 0x03, 0xa4, 0x0b, 0xa6, 0xe8, 0x9c, 0x34, 0xc7, 0x7e, 0x69, 0x6b, + 0x11, 0x92, 0x47, 0xfb, 0x44, 0x7d, 0x3c, 0xe4, 0x2a, 0x9d, 0x14, 0x6a, 0xbf, 0xf7, 0x37, 0xca, + 0xc5, 0x9d, 0x60, 0xac, 0xde, 0xb6, 0xe9, 0x21, 0xb2, 0xf0, 0xff, 0xef, 0x65, 0x80, 0x5f, 0xbf, + 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, + 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, + 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, + 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, + 0xbf, 0x7e, 0xfd, 0xfa, 0xff, 0xc8, 0xff, 0x01, 0x52, 0x9d, 0xe4, 0x91, 0x00, 0x94, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1854,8 +2356,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 19968, // uncompressed data size (bytes) - 13906, // compressed data size (bytes) + 37888, // uncompressed data size (bytes) + 17936, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1877,8 +2379,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, - 0x20, 0x00, 0x00, 0xda, 0x95, 0xe6, 0x99, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1911,7 +2413,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_data[] = { - 0x0d, 0x0a, 0x86, 0x3d, 0x58, 0x5c, 0x19, 0x82, 0xfe, 0x07, 0x84, 0x4d, 0x20, 0xd0, 0xe8, 0xc8, + 0x93, 0xd1, 0x80, 0x47, 0x05, 0x9b, 0x77, 0x9b, 0xd2, 0x8f, 0x56, 0x7e, 0x23, 0xe4, 0x7a, 0xb0, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1944,7 +2446,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_data[] = { - 0x23, 0x4b, 0x2a, 0xa1, 0x16, 0xcc, 0x7e, 0x43, 0x97, 0xfc, 0x16, 0x7f, 0x7c, 0x23, 0x80, 0x28, + 0x8b, 0xed, 0x67, 0xe2, 0xd9, 0x24, 0xa7, 0xed, 0x0c, 0x89, 0x82, 0x8d, 0xe5, 0x07, 0x17, 0x8b, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1977,7 +2479,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_patch_loc_data[] = { - 0x00, 0x39, 0x00, 0x00, + 0x00, 0x49, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c new file mode 100644 index 0000000000..7f8f88e60a --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMCDesc_GH100.c @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveConcatenatedFMCDesc_GH100("ucode_desc_prod") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_desc.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 28 +// +static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMCDesc_GH100_ucode_desc_prod_data[] = +{ + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0xf1, 0x32, 0x20, 0xde, 0x00, 0xc4, 0x37, 0x19, 0x19, 0x18, + 0xf1, 0xe8, 0x03, 0x00, 0x7f, 0x51, 0xb9, 0x4d, 0x54, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveConcatenatedFMCDesc_GH100_ucode_desc_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 84, // uncompressed data size (bytes) + 28, // compressed data size (bytes) + kgspBinArchiveConcatenatedFMCDesc_GH100_ucode_desc_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveConcatenatedFMCDesc_GH100 = +{ + 1, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_desc_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveConcatenatedFMCDesc_GH100_ucode_desc_prod_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveConcatenatedFMCDesc_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c new file mode 100644 index 0000000000..fa2e5dd8c9 --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c @@ -0,0 +1,20471 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveConcatenatedFMC_GH100("ucode_image_prod") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_concatenated_fmc_prod_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 331776 +// COMPRESSED SIZE (bytes): 325996 +// +static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data[] = +{ + 0x9c, 0xd6, 0xc3, 0x72, 0x28, 0x0a, 0x80, 0x04, 0xd0, 0xd8, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, + 0xbc, 0xb1, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xc9, 0xbc, 0x1f, 0x98, 0x59, 0x4c, + 0xaf, 0x7b, 0xd3, 0x55, 0xbd, 0x38, 0x5a, 0x76, 0xe6, 0xa4, 0x7e, 0xfe, 0x1f, 0x7a, 0xb8, 0xb2, + 0x9e, 0xdf, 0x39, 0xb8, 0x4a, 0x22, 0x45, 0xb6, 0x46, 0xeb, 0xe5, 0x88, 0xda, 0xc2, 0xe3, 0xdf, + 0x87, 0x46, 0x37, 0x1e, 0x96, 0x6c, 0x61, 0x33, 0x93, 0x43, 0xe7, 0x2b, 0x6c, 0xbd, 0x93, 0xa8, + 0xe0, 0x2d, 0x46, 0xcd, 0x4e, 0x98, 0xdc, 0x4f, 0x65, 0xb1, 0x03, 0x77, 0x13, 0xde, 0x24, 0x37, + 0xca, 0xa4, 0x0e, 0xb0, 0x5d, 0x23, 0x9b, 0x18, 0x0a, 0x16, 0x36, 0x0d, 0x72, 0xda, 0xdc, 0x24, + 0xf0, 0x21, 0xb7, 0x90, 0xe2, 0x7b, 0x63, 0x3a, 0xc9, 0x70, 0x75, 0xb8, 0xfb, 0xee, 0x04, 0xf6, + 0x73, 0x93, 0x70, 0xb4, 0x82, 0x44, 0xba, 0x05, 0xed, 0xcb, 0xeb, 0xd9, 0xf4, 0xbd, 0x1a, 0xc3, + 0x10, 0x40, 0xe1, 0x06, 0x4f, 0xbf, 0xb5, 0x6e, 0x15, 0x09, 0xc7, 0xdc, 0x68, 0xdd, 0xbb, 0xef, + 0xaa, 0xb8, 0xb9, 0x79, 0x1e, 0x99, 0x62, 0x9f, 0xdc, 0xed, 0x4a, 0x04, 0x0b, 0x7e, 0x4a, 0x28, + 0xb3, 0xc1, 0x13, 0xf2, 0xf8, 0x86, 0x8c, 0xbc, 0x20, 0x48, 0x8e, 0xf1, 0x76, 0x7b, 0xaf, 0x11, + 0xfc, 0x0f, 0x67, 0x4f, 0x33, 0x18, 0x22, 0x48, 0xf3, 0x4e, 0x5e, 0xde, 0x5d, 0x5c, 0x4d, 0x0e, + 0x6b, 0x2f, 0x29, 0x9c, 0xde, 0x97, 0x34, 0x51, 0x6d, 0x2e, 0x51, 0x15, 0xce, 0x3e, 0x1b, 0xa0, + 0x65, 0x4d, 0xde, 0x5b, 0xa6, 0x9d, 0x68, 0x3a, 0x95, 0x65, 0xf5, 0x82, 0xfc, 0x3c, 0x96, 0x8d, + 0x12, 0x35, 0xc2, 0x68, 0xf1, 0x01, 0x13, 0xe8, 0x4c, 0x30, 0xe8, 0x20, 0x79, 0xf5, 0x35, 0x04, + 0xaf, 0x2e, 0xd3, 0xc3, 0xaf, 0x0e, 0xf8, 0x44, 0x19, 0x46, 0x91, 0xf6, 0x71, 0xa8, 0x4e, 0xcb, + 0x23, 0x76, 0x18, 0xbe, 0x07, 0xf8, 0x0b, 0xc3, 0xd8, 0x6a, 0x2f, 0x67, 0x20, 0x95, 0x5b, 0x2d, + 0x4a, 0x83, 0x30, 0xa5, 0xbd, 0xc2, 0xdc, 0x34, 0xfa, 0x0e, 0xac, 0x10, 0xac, 0xc8, 0x3c, 0x0b, + 0x06, 0x1b, 0xf0, 0x27, 0x11, 0xd4, 0xb2, 0xcc, 0xb9, 0x2e, 0x23, 0xfe, 0xa3, 0xc5, 0x63, 0x94, + 0x9f, 0x03, 0x2f, 0x38, 0x39, 0x18, 0x68, 0xbc, 0x82, 0xd6, 0x31, 0x2d, 0x22, 0x4c, 0xe1, 0xf8, + 0xdc, 0x1d, 0xe4, 0xe0, 0x9c, 0x71, 0x97, 0x52, 0x98, 0x5b, 0xab, 0x1a, 0x11, 0x64, 0xeb, 0x2e, + 0xeb, 0xfe, 0x8c, 0x3d, 0x23, 0xd0, 0x04, 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0x8f, 0x14, + 0x32, 0x32, 0xf5, 0x51, 0xfb, 0x86, 0xe1, 0xcb, 0x8b, 0x40, 0xe1, 0x7d, 0x57, 0x75, 0x3f, 0xca, + 0x8d, 0xbe, 0x17, 0xba, 0xcd, 0xc7, 0xa9, 0xca, 0x15, 0xb7, 0x03, 0x8c, 0x3d, 0x54, 0x84, 0xc1, + 0x17, 0x71, 0x77, 0xcb, 0x40, 0x82, 0x53, 0x4a, 0x3c, 0xad, 0x0c, 0x72, 0xac, 0xfd, 0x9e, 0x75, + 0x3f, 0xcc, 0x0f, 0x20, 0xca, 0x9e, 0x12, 0xdc, 0xae, 0x59, 0xe7, 0x36, 0x07, 0x67, 0x3a, 0x0b, + 0xc6, 0x26, 0xf6, 0xcf, 0x41, 0x7b, 0x8c, 0x41, 0x01, 0x32, 0x54, 0x37, 0xae, 0x56, 0x38, 0x83, + 0xd6, 0x11, 0xcc, 0xf8, 0x38, 0x0f, 0x9b, 0xb3, 0x61, 0xec, 0xa7, 0x3f, 0x53, 0xa3, 0xd1, 0x78, + 0x43, 0x36, 0xc5, 0x4b, 0x7b, 0xc2, 0xcb, 0x68, 0xdd, 0x2b, 0x1d, 0x22, 0x30, 0xb9, 0x0a, 0x93, + 0xf4, 0x89, 0xdd, 0xf7, 0x18, 0xa8, 0x1b, 0x3d, 0x00, 0x10, 0x05, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 331776, // uncompressed data size (bytes) + 325996, // compressed data size (bytes) + kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveConcatenatedFMC_GH100 = +{ + 1, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveConcatenatedFMC_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c index a6d9a3b9f3..0e7bcf927f 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c @@ -35,1861 +35,1811 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 29605 +// COMPRESSED SIZE (bytes): 28813 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data[] = { - 0xed, 0xb7, 0x53, 0x98, 0x6e, 0xdb, 0xb2, 0x2d, 0x98, 0xb6, 0x6d, 0xdb, 0xb6, 0x67, 0xda, 0xb6, - 0x6d, 0xdb, 0xb6, 0x9d, 0x33, 0x6d, 0xcf, 0xb4, 0x6d, 0xdb, 0xb6, 0x6d, 0x67, 0xd6, 0xda, 0x7b, - 0xad, 0x73, 0xce, 0xad, 0x7b, 0xeb, 0xa1, 0xde, 0xea, 0xa1, 0x76, 0x7c, 0xdf, 0x3f, 0x5a, 0xc4, - 0xe8, 0xbd, 0x47, 0xeb, 0x11, 0xd1, 0x63, 0x8c, 0xf1, 0x33, 0x0d, 0x48, 0x0a, 0x44, 0x81, 0xfd, - 0x56, 0x69, 0xd1, 0x64, 0x9e, 0x82, 0x08, 0xc1, 0xd3, 0x5c, 0xec, 0x48, 0xeb, 0xcd, 0x59, 0xd1, - 0x96, 0x0f, 0x1d, 0x05, 0xdd, 0x49, 0x87, 0xd2, 0x61, 0x85, 0x0f, 0x2f, 0x3f, 0x5b, 0xa8, 0x12, - 0x39, 0x0d, 0xb9, 0xe2, 0x23, 0x7e, 0x45, 0x17, 0xf9, 0xe9, 0xe3, 0x1a, 0x6a, 0xe8, 0x55, 0xc0, - 0x6c, 0x22, 0xf6, 0xa3, 0x95, 0x37, 0x03, 0xb9, 0x32, 0x0d, 0x8f, 0xd9, 0xc8, 0x02, 0x3e, 0x87, - 0x84, 0xe7, 0x6d, 0xb3, 0x8c, 0xd2, 0x50, 0xcc, 0xf0, 0x75, 0xe9, 0x16, 0x47, 0x6b, 0x3a, 0x76, - 0xc9, 0x04, 0xe1, 0xa7, 0x71, 0x4a, 0x07, 0xa0, 0x40, 0x80, 0x91, 0x83, 0xa3, 0x7c, 0xe1, 0xba, - 0xd7, 0xdc, 0x53, 0xe7, 0xdc, 0xcb, 0x8d, 0x90, 0xf9, 0x95, 0xb0, 0x86, 0xe7, 0xb9, 0xba, 0x1c, - 0x1c, 0x7c, 0x32, 0x6b, 0xae, 0xa8, 0xc7, 0xb2, 0x7a, 0xf8, 0x4d, 0xb2, 0x97, 0x4b, 0x03, 0x80, - 0xc6, 0xe7, 0x01, 0x2a, 0x6b, 0xca, 0xa0, 0x63, 0xc5, 0x8c, 0xe6, 0x9d, 0xa1, 0xd4, 0x93, 0x42, - 0x47, 0x25, 0x76, 0x2d, 0xf4, 0x49, 0x11, 0xa9, 0xd6, 0xf8, 0x4d, 0xe1, 0x1a, 0x5d, 0xaf, 0x2b, - 0x06, 0xf4, 0xd2, 0xd4, 0x7d, 0x91, 0x04, 0x96, 0x44, 0xd0, 0xbf, 0xae, 0x4f, 0xb7, 0x1e, 0x03, - 0x6c, 0x99, 0xd1, 0xec, 0xda, 0x41, 0x02, 0xe6, 0x03, 0x3c, 0x6f, 0x20, 0xc7, 0x2a, 0x39, 0x4f, - 0x4e, 0xc2, 0x4b, 0x0f, 0xb2, 0xfb, 0x5b, 0x86, 0x06, 0x38, 0x28, 0x81, 0xea, 0xa5, 0x31, 0xa8, - 0x22, 0xe8, 0xb8, 0xef, 0xd5, 0x75, 0x17, 0x50, 0xc3, 0x3c, 0xe9, 0x97, 0xe9, 0x1a, 0xc2, 0xf8, - 0x41, 0xb6, 0x24, 0x77, 0xa8, 0xa8, 0x1b, 0x0d, 0x53, 0x92, 0x61, 0xde, 0x08, 0x70, 0x63, 0xc4, - 0x23, 0xd5, 0x5b, 0x35, 0x31, 0x3b, 0x12, 0x74, 0x35, 0x74, 0xd3, 0x3e, 0x64, 0x11, 0x12, 0x16, - 0x43, 0x14, 0xbe, 0x20, 0x95, 0xb5, 0x8b, 0xb0, 0x82, 0xab, 0xc6, 0xa2, 0xda, 0xe1, 0x36, 0xcb, - 0x95, 0xe5, 0x6c, 0xbc, 0x54, 0x5f, 0xbc, 0xdd, 0xa8, 0x50, 0xbe, 0xc0, 0x6e, 0xda, 0xcd, 0x26, - 0xd5, 0xd5, 0x6f, 0x07, 0xf4, 0x11, 0x29, 0x27, 0xde, 0x2d, 0x3e, 0xc8, 0x92, 0x74, 0xcf, 0x99, - 0x30, 0xf4, 0x2c, 0x1d, 0x05, 0x4d, 0x3d, 0x1a, 0xaa, 0x47, 0xbe, 0x80, 0x1c, 0xaa, 0xab, 0x8e, - 0x4f, 0xb0, 0xbc, 0xe7, 0x5d, 0x22, 0xbd, 0xad, 0x80, 0x0e, 0xc6, 0x33, 0x6d, 0x0f, 0x94, 0xd3, - 0xf8, 0xf6, 0xaf, 0xb9, 0xa2, 0x0b, 0x8c, 0xbd, 0x7d, 0x10, 0xaf, 0xd2, 0x09, 0xf9, 0xa5, 0xf8, - 0x23, 0xf9, 0x8d, 0x5a, 0x47, 0xdf, 0xcd, 0x90, 0x0e, 0x0e, 0xfe, 0x2f, 0x52, 0x53, 0x32, 0x70, - 0x03, 0x27, 0xcc, 0xb4, 0xb3, 0xf2, 0xa4, 0x9b, 0x75, 0x6c, 0xf4, 0x03, 0xce, 0xdc, 0xda, 0xda, - 0x1e, 0xb7, 0x1f, 0x0c, 0x22, 0x30, 0x57, 0x01, 0x75, 0x26, 0xfd, 0xc2, 0x4e, 0x64, 0x6b, 0x27, - 0x46, 0xeb, 0x84, 0x52, 0x26, 0x36, 0x86, 0xe6, 0x19, 0xd4, 0x61, 0x20, 0x9d, 0xe7, 0xd2, 0x79, - 0x53, 0xeb, 0x6e, 0x26, 0x7e, 0x27, 0x9d, 0x5e, 0x19, 0xd4, 0x09, 0x50, 0x13, 0x8f, 0xcb, 0xe3, - 0x3f, 0x1f, 0x48, 0x89, 0x3a, 0x0a, 0x76, 0xa7, 0x6e, 0x52, 0x03, 0x41, 0x1a, 0x79, 0x12, 0x98, - 0x83, 0x2f, 0xbb, 0x72, 0x31, 0x22, 0xd1, 0x81, 0x16, 0xd6, 0xac, 0x6c, 0x0f, 0xa9, 0xd4, 0x1a, - 0x8f, 0xbf, 0xe5, 0xcb, 0x6a, 0x83, 0x6a, 0xba, 0xb6, 0x22, 0x49, 0x4d, 0x7b, 0x6e, 0x3f, 0xec, - 0x0f, 0x27, 0xb2, 0x87, 0xd9, 0xee, 0xeb, 0x83, 0x07, 0x6b, 0x3f, 0xec, 0xf8, 0xf4, 0x21, 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defined(BINDATA_INCLUDE_DATA) @@ -1900,7 +1850,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 32768, // uncompressed data size (bytes) - 29605, // compressed data size (bytes) + 28813, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1922,9 +1872,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x06, 0x07, 0x36, 0x20, 0x2e, 0x63, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x9d, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, - 0x88, 0x20, 0x00, 0x3c, 0xec, 0x41, 0xdd, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x86, 0x08, 0x16, 0x20, 0x2e, 0x61, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x95, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, + 0x88, 0x20, 0x00, 0x06, 0x3c, 0x73, 0x3c, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1953,1861 +1903,1811 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 29603 +// COMPRESSED SIZE (bytes): 28812 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data[] = { - 0xed, 0xf7, 0x53, 0xb4, 0x30, 0x4d, 0xb3, 0x2e, 0x0a, 0x4e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0x36, 0xdf, 0x69, 0xdb, 0xb6, 0xf9, 0x4e, 0xdb, 0xb6, 0x6d, 0xdb, 0x9e, 0xfd, 0xad, 0xf5, - 0x7f, 0x7b, 0xef, 0xd3, 0xe7, 0xf4, 0x45, 0xdf, 0xf5, 0x45, 0xaf, 0x18, 0xa3, 0xea, 0x89, 0xa8, - 0xcc, 0x8c, 0x27, 0x23, 0x22, 0xa3, 0x6a, 0x94, 0x63, 0xde, 0x6b, 0x00, 0xcc, 0xf9, 0xbc, 0x24, - 0xaa, 0xd8, 0x0f, 0x16, 0x8e, 0x90, 0xa9, 0xa3, 0x92, 0x5f, 0xd4, 0xfa, 0x89, 0xae, 0x7d, 0x22, - 0xf7, 0xbe, 0x32, 0x8e, 0x25, 0x2a, 0x46, 0x70, 0x58, 0x08, 0x56, 0x05, 0x32, 0x66, 0x0a, 0x11, - 0xcb, 0x23, 0x4d, 0x28, 0x5b, 0x5d, 0xc3, 0xbb, 0x53, 0x74, 0x06, 0x98, 0x2e, 0x91, 0x3a, 0x5c, - 0xaf, 0x54, 0x61, 0x5c, 0x50, 0xe9, 0xb6, 0xd5, 0x94, 0x6f, 0x94, 0xe3, 0xb8, 0x66, 0x1f, 0xeb, - 0x73, 0x90, 0xfc, 0x3a, 0x3f, 0xc9, 0x00, 0x95, 0xc9, 0x18, 0x78, 0x86, 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0x00, 0xf4, 0x5f, 0x3d, 0x90, 0xff, 0x30, 0xcd, + 0xff, 0x6e, 0xff, 0xc7, 0xaf, 0x3d, 0xea, 0xbf, 0xec, 0xfc, 0x1f, 0x76, 0xff, 0x0f, 0xff, 0x9f, + 0x0f, 0x87, 0x08, 0xc6, 0xff, 0xa2, 0x60, 0x00, 0x84, 0xff, 0xc5, 0xbf, 0xff, 0xc1, 0xff, 0xe9, + 0xf7, 0xff, 0xcf, 0xf3, 0x0f, 0xd2, 0xa0, 0xff, 0xbf, 0xf8, 0x40, 0xfd, 0x17, 0xff, 0xc5, 0x7f, + 0xf1, 0x5f, 0xfc, 0x17, 0xff, 0xc5, 0x7f, 0xf1, 0x5f, 0xfc, 0x17, 0xff, 0xc5, 0x7f, 0xf1, 0xff, + 0x33, 0xfc, 0x3f, 0x00, 0xdf, 0x38, 0xdc, 0x45, 0x00, 0x80, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3818,7 +3718,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 32768, // uncompressed data size (bytes) - 29603, // compressed data size (bytes) + 28812, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3840,9 +3740,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x06, 0x07, 0x36, 0x20, 0x2e, 0x63, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x9d, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, - 0x88, 0x20, 0x00, 0x3c, 0xec, 0x41, 0xdd, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x86, 0x08, 0x16, 0x20, 0x2e, 0x61, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x95, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, + 0x88, 0x20, 0x00, 0x06, 0x3c, 0x73, 0x3c, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c index fe13c21c4c..1dc4353715 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c @@ -35,1092 +35,1042 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 20480 -// COMPRESSED SIZE (bytes): 17302 +// COMPRESSED SIZE (bytes): 16512 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data[] = { - 0xed, 0xb7, 0x53, 0x98, 0x65, 0xdd, 0xd2, 0x2e, 0xb8, 0xd2, 0xb6, 0x51, 0x69, 0xbb, 0xd2, 0xb6, - 0x6d, 0x57, 0xda, 0xb6, 0x6d, 0x56, 0xda, 0xb6, 0x6d, 0xdb, 0x36, 0x2b, 0x6d, 0xbb, 0x32, 0x2b, - 0xd5, 0xf5, 0xed, 0xaa, 0xfd, 0xef, 0xd3, 0xe7, 0xf4, 0x45, 0xdf, 0xf5, 0x45, 0xef, 0x78, 0x9e, - 0x35, 0xdf, 0x88, 0x39, 0xc6, 0x88, 0x77, 0x44, 0xc4, 0x88, 0x39, 0xe7, 0x7a, 0x3b, 0x08, 0x15, - 0xda, 0xaa, 0x2b, 0x76, 0xbd, 0xb1, 0xe7, 0xd5, 0xe8, 0x43, 0x04, 0x83, 0x2e, 0xb8, 0x69, 0xb5, - 0x24, 0xd7, 0x2a, 0xa3, 0xcb, 0x50, 0x40, 0xd4, 0xbb, 0x5f, 0xc6, 0x98, 0x0d, 0x1c, 0x65, 0xb5, - 0xf7, 0xc2, 0x76, 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defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 20480, // uncompressed data size (bytes) - 17302, // compressed data size (bytes) + 16512, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1149,13 +1099,13 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 41 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x00, 0x02, 0x07, 0x20, 0x62, 0x03, 0x62, 0x37, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, - 0x03, 0x8a, 0x41, 0x92, 0x12, 0x40, 0xac, 0xce, 0xc0, 0xc0, 0x88, 0x4d, 0x5d, 0x00, 0x44, 0x10, - 0x00, 0xf4, 0x78, 0x36, 0x05, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x02, 0x07, 0x06, 0x86, 0x08, 0x16, 0x20, 0x76, 0x61, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0xaa, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x05, 0x40, + 0x04, 0x01, 0xce, 0xa8, 0x04, 0xe4, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1166,7 +1116,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 41, // compressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1184,1092 +1134,1043 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 20480 -// COMPRESSED SIZE (bytes): 17301 +// COMPRESSED SIZE (bytes): 16514 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data[] = { - 0xed, 0xb7, 0x63, 0x98, 0x20, 0xcf, 0xf2, 0x2e, 0xd8, 0xb6, 0xed, 0x9e, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0x3d, 0x6d, 0xdb, 0xb6, 0xdd, 0xd3, 0xb6, 0xa7, 0x6d, 0x5b, 0xd3, 0xb6, 0xad, 0x9d, - 0xdf, 0x99, 0x39, 0xff, 0x73, 0xf7, 0xde, 0xfd, 0xb0, 0xdf, 0xf6, 0xc3, 0x9e, 0x78, 0x9e, 0xaa, - 0x37, 0xa2, 0x32, 0x23, 0xde, 0x8c, 0xcc, 0x8c, 0xaa, 0xac, 0xa4, 0x31, 0x52, 0xeb, 0xde, 0xd7, - 0x62, 0x35, 0xf6, 0xf0, 0xda, 0xa2, 0xa2, 0x81, 0xde, 0x1f, 0xde, 0xfd, 0x26, 0x44, 0x6f, 0x5e, - 0xee, 0x3c, 0x84, 0x1a, 0x38, 0x48, 0x87, 0xc8, 0x86, 0xea, 0xa4, 0x2e, 0xc7, 0x2b, 0x86, 0x91, - 0x09, 0x72, 0xf9, 0x63, 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0xff, 0x9c, 0xdc, 0xef, 0xff, 0xd4, 0xc9, + 0x12, 0xa8, 0xff, 0x7a, 0x1b, 0xff, 0xbe, 0x91, 0xc9, 0xbf, 0xdf, 0x5b, 0x48, 0x50, 0xc4, 0xff, + 0x10, 0x01, 0x0b, 0x68, 0xc0, 0x7f, 0xb1, 0x3e, 0xda, 0xdf, 0xeb, 0x17, 0xbf, 0xbf, 0x99, 0xa4, + 0x14, 0xff, 0xbf, 0x98, 0xe2, 0x1f, 0xce, 0xfd, 0x07, 0x0d, 0xfa, 0x58, 0xec, 0x84, 0xd5, 0x5c, + 0x9b, 0x00, 0xb0, 0xbf, 0xe3, 0x40, 0xff, 0x61, 0x9a, 0xff, 0x5e, 0xff, 0x53, 0xd7, 0x1e, 0xf5, + 0x6f, 0x76, 0xfe, 0x87, 0x7f, 0xfd, 0xc3, 0xff, 0xf3, 0xe1, 0x40, 0xc1, 0xf8, 0x2f, 0x0a, 0x02, + 0x20, 0xfc, 0x17, 0x7f, 0xff, 0x83, 0xff, 0xf1, 0xcb, 0xff, 0xf3, 0xfb, 0x0b, 0x69, 0x30, 0xff, + 0xaf, 0x3e, 0x51, 0xff, 0xe2, 0x5f, 0xfc, 0x8b, 0x7f, 0xf1, 0x2f, 0xfe, 0xc5, 0xbf, 0xf8, 0x17, + 0xff, 0xe2, 0x5f, 0xfc, 0x8b, 0xff, 0x8f, 0xf0, 0x7f, 0x00, 0xaa, 0xc6, 0x1c, 0x68, 0x00, 0x50, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2280,7 +2181,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 20480, // uncompressed data size (bytes) - 17301, // compressed data size (bytes) + 16514, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2298,13 +2199,13 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 41 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x00, 0x02, 0x07, 0x20, 0x62, 0x03, 0x62, 0x37, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, - 0x03, 0x8a, 0x41, 0x92, 0x12, 0x40, 0xac, 0xce, 0xc0, 0xc0, 0x88, 0x4d, 0x5d, 0x00, 0x44, 0x10, - 0x00, 0xf4, 0x78, 0x36, 0x05, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x02, 0x07, 0x06, 0x86, 0x08, 0x16, 0x20, 0x76, 0x61, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0xaa, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x05, 0x40, + 0x04, 0x01, 0xce, 0xa8, 0x04, 0xe4, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2315,7 +2216,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 41, // compressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c index 2b0813db4d..7382d1adfb 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c @@ -29,7898 +29,10332 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_image_dbg") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 126976 -// COMPRESSED SIZE (bytes): 126108 +// DATA SIZE (bytes): 167936 +// COMPRESSED SIZE (bytes): 165046 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data[] = { - 0xec, 0x9d, 0x43, 0x93, 0x30, 0x0c, 0xac, 0xa5, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xed, 0xb7, 0x6d, 0xbb, 0xe7, 0x9b, 0x3f, 0x30, 0xab, 0xa9, - 0xba, 0x9b, 0x7b, 0xd6, 0xd9, 0xa4, 0x9e, 0x9c, 0xca, 0xc9, 0x2a, 0x00, 0x00, 0xff, 0xab, 0xff, - 0x49, 0xc1, 0xe2, 0x95, 0x30, 0xf9, 0xfb, 0xfd, 0xf3, 0xc3, 0x3b, 0x38, 0x8c, 0xbb, 0x49, 0x03, - 0x70, 0xb9, 0xa2, 0xd2, 0x68, 0x48, 0x31, 0x95, 0xbd, 0x7e, 0x68, 0x4f, 0xa1, 0xaa, 0x81, 0x04, - 0xa7, 0x44, 0xb4, 0x70, 0x3e, 0xfa, 0x5b, 0xed, 0x65, 0x51, 0x10, 0xb7, 0x50, 0xc5, 0x65, 0xa8, - 0x08, 0x79, 0x2f, 0x18, 0x04, 0x9d, 0xd7, 0xe6, 0x6c, 0xc5, 0x8b, 0x74, 0xee, 0xab, 0xaf, 0xf8, - 0x17, 0xf3, 0x3c, 0x43, 0x41, 0x80, 0x54, 0xb2, 0x0d, 0x3e, 0x4f, 0x82, 0xe2, 0xc1, 0x47, 0x9d, - 0x1d, 0x30, 0x68, 0xd5, 0xf9, 0x28, 0x16, 0xdf, 0x37, 0x28, 0x51, 0x12, 0x27, 0xd3, 0x8d, 0xb5, - 0x90, 0x03, 0x66, 0x97, 0x22, 0xe8, 0x53, 0xe8, 0xdd, 0x73, 0xad, 0x96, 0x75, 0xd7, 0x0e, 0x8b, - 0x00, 0xb9, 0xf0, 0x0a, 0x50, 0x2f, 0xab, 0x9c, 0x16, 0xc2, 0xd1, 0x1b, 0xb1, 0x02, 0xe6, 0x7c, - 0x08, 0xb0, 0x37, 0x6a, 0x1a, 0x50, 0xab, 0x63, 0x71, 0x2c, 0xa9, 0x70, 0x60, 0x88, 0x2d, 0x01, - 0x94, 0x21, 0x71, 0x63, 0xa6, 0x46, 0xc7, 0x82, 0xa6, 0x30, 0x46, 0x80, 0xfd, 0xfc, 0x3a, 0xce, - 0x54, 0x1c, 0x93, 0x45, 0x5d, 0x2b, 0x8e, 0x9f, 0x03, 0x3e, 0xa6, 0x46, 0x44, 0x97, 0xca, 0xe0, - 0xcf, 0x6f, 0x1c, 0x29, 0x4d, 0x03, 0x34, 0xdb, 0xff, 0x90, 0x05, 0x85, 0x55, 0x16, 0xb6, 0x66, - 0x0b, 0x69, 0xb8, 0x7d, 0x74, 0xec, 0x1a, 0xeb, 0x3b, 0x32, 0x0d, 0x9f, 0x94, 0x7a, 0x1b, 0x82, - 0xc2, 0x9c, 0x77, 0x11, 0x18, 0x04, 0xef, 0xff, 0x19, 0x1e, 0xe1, 0x45, 0x84, 0x02, 0x57, 0x33, - 0xaa, 0x77, 0x96, 0xdf, 0xdc, 0xe5, 0x43, 0xf1, 0x0c, 0x4e, 0xce, 0xc3, 0x1e, 0xbe, 0x2f, 0x57, - 0xc4, 0xab, 0x68, 0x6f, 0x65, 0xaf, 0xb0, 0x7b, 0x1f, 0xf6, 0xbe, 0x83, 0x8a, 0xd0, 0x84, 0x34, - 0x7c, 0x84, 0x20, 0xbd, 0x59, 0x4e, 0xb0, 0x7d, 0x65, 0x66, 0x58, 0xfe, 0x91, 0x6f, 0xf5, 0xbc, - 0x9c, 0x65, 0xc2, 0x95, 0x39, 0x1d, 0xfe, 0x43, 0x92, 0xaf, 0x93, 0x69, 0x94, 0x0e, 0x2b, 0x75, - 0x70, 0x70, 0x8a, 0x86, 0xf1, 0x2a, 0xb0, 0x6e, 0xf5, 0x9e, 0xb1, 0x91, 0x36, 0xe8, 0x65, 0xa2, - 0x76, 0x42, 0x82, 0x7a, 0x50, 0xe5, 0xfb, 0x12, 0x58, 0x8c, 0x0e, 0x87, 0xa1, 0x67, 0xee, 0x60, - 0x24, 0xe3, 0x8f, 0x76, 0x6b, 0xba, 0x4b, 0x8c, 0x61, 0x62, 0x6a, 0x2f, 0x75, 0xe3, 0xa5, 0x51, - 0xb7, 0xa1, 0x4f, 0x8e, 0x62, 0x51, 0xd5, 0x5a, 0x86, 0x03, 0x57, 0xdf, 0x09, 0x97, 0xc4, 0x51, - 0xcc, 0xf4, 0x0c, 0x5a, 0x28, 0xe6, 0x39, 0xe6, 0x23, 0x7a, 0x98, 0x83, 0x29, 0x68, 0x8a, 0xe7, - 0x58, 0x57, 0x15, 0x8d, 0x36, 0x05, 0x73, 0xfb, 0xa5, 0x7b, 0x3f, 0xb8, 0x79, 0x0d, 0x18, 0xef, - 0x89, 0x2b, 0xf4, 0x1f, 0x83, 0xaa, 0xff, 0x07, 0x9f, 0xd6, 0xbe, 0xe9, 0xc3, 0x0d, 0xe3, 0x92, - 0x5c, 0x81, 0x63, 0x07, 0x11, 0xc3, 0x36, 0xa7, 0x7f, 0xff, 0xbf, 0xf9, 0xfb, 0x4c, 0xe0, 0x4b, - 0xb8, 0x1e, 0x47, 0xe2, 0xfe, 0xab, 0x8a, 0x09, 0xd3, 0x53, 0x81, 0x12, 0x12, 0x34, 0xef, 0x62, - 0xdd, 0x30, 0x6f, 0x95, 0x9b, 0x83, 0xa6, 0x95, 0xf4, 0x97, 0x35, 0xbd, 0x60, 0xe6, 0xfc, 0xac, - 0x86, 0x7d, 0x9d, 0xd7, 0xa8, 0x62, 0x9c, 0x32, 0x74, 0xad, 0x00, 0x76, 0xaa, 0x6b, 0x36, 0x85, - 0xc1, 0xef, 0x97, 0x38, 0xb6, 0x1f, 0xf8, 0x56, 0x0c, 0xda, 0x39, 0x70, 0xa9, 0xed, 0xed, 0x30, - 0x0e, 0x60, 0xd3, 0xa6, 0xaf, 0xe4, 0x41, 0xcd, 0xee, 0x11, 0xc9, 0x86, 0x48, 0x6c, 0xeb, 0xed, - 0xa9, 0x16, 0x66, 0x2c, 0xe4, 0xa0, 0x1c, 0xdc, 0x46, 0xa8, 0x18, 0x87, 0xc8, 0xa5, 0x71, 0x2e, - 0x9c, 0x60, 0xee, 0x7c, 0x1a, 0x34, 0x7b, 0x38, 0x0a, 0x7b, 0xbd, 0x06, 0x23, 0xa4, 0xbf, 0xba, - 0xe4, 0xe6, 0x7c, 0xe2, 0xdf, 0xd3, 0x68, 0x9d, 0x2d, 0xcd, 0x71, 0xcd, 0xe9, 0x12, 0x21, 0x3b, - 0x69, 0x52, 0x23, 0x5b, 0xc5, 0xdf, 0x69, 0x0e, 0x2f, 0x03, 0xc4, 0x42, 0xeb, 0x10, 0x7a, 0xc2, - 0xee, 0x6d, 0x10, 0xa1, 0xe9, 0xe3, 0x1b, 0x24, 0x70, 0x69, 0x2c, 0x8c, 0xc4, 0xa0, 0x75, 0x48, - 0x65, 0x6a, 0xc9, 0xc0, 0x26, 0x6e, 0x57, 0xb5, 0xf1, 0xcf, 0x50, 0xc8, 0x9d, 0x62, 0x6e, 0x43, - 0xb0, 0x3d, 0x02, 0x38, 0x80, 0x50, 0xfd, 0x31, 0xbd, 0x76, 0xd0, 0x40, 0x4e, 0xa9, 0x47, 0x83, - 0xda, 0x8f, 0xca, 0x99, 0x94, 0x1c, 0x78, 0x4c, 0xad, 0xa9, 0x56, 0x94, 0x4c, 0x7f, 0x56, 0x7f, - 0xd7, 0x8e, 0xae, 0x3e, 0x89, 0x63, 0x12, 0xfb, 0xd0, 0x1d, 0x88, 0x57, 0x91, 0xfe, 0x26, 0xa7, - 0xf2, 0xa5, 0x5e, 0x02, 0x64, 0x10, 0xfa, 0x5a, 0xc1, 0x48, 0x2e, 0x5a, 0xab, 0x0e, 0x1c, 0x6c, - 0x71, 0xda, 0xe1, 0x04, 0xfd, 0x97, 0x0d, 0xe1, 0xf6, 0x5a, 0x8b, 0x3e, 0x90, 0xaa, 0x7c, 0xbf, - 0xa9, 0x85, 0xe7, 0xe5, 0x9b, 0x9f, 0xe5, 0x31, 0xfc, 0x61, 0x17, 0x47, 0xbb, 0x73, 0xd8, 0xc5, - 0xc1, 0xdb, 0xe9, 0x59, 0xe8, 0x12, 0xdd, 0xaf, 0x96, 0x1f, 0xac, 0xab, 0xfa, 0x82, 0x08, 0x60, - 0x52, 0x57, 0xae, 0xba, 0x33, 0x60, 0x00, 0x03, 0x9a, 0x1c, 0xbe, 0x69, 0x56, 0x40, 0xf9, 0xa2, - 0xa8, 0x05, 0x1f, 0x71, 0x69, 0x81, 0x4e, 0x3b, 0x47, 0xf7, 0x30, 0xc0, 0x58, 0xdc, 0xbc, 0x52, - 0xce, 0x36, 0x28, 0xa9, 0x91, 0xea, 0x78, 0x35, 0x45, 0x28, 0xdf, 0xe2, 0x22, 0xfa, 0x22, 0xc7, - 0xf0, 0xa6, 0x44, 0xc9, 0x14, 0x5d, 0x92, 0x9b, 0x9e, 0x7d, 0x96, 0xca, 0x67, 0x05, 0x5b, 0xb0, - 0xce, 0x6b, 0x7d, 0x88, 0xb7, 0x2e, 0xd5, 0xa4, 0x4c, 0x90, 0x64, 0xbf, 0x0f, 0x15, 0xf8, 0xc9, - 0x9c, 0x73, 0x51, 0xc2, 0xc6, 0x4f, 0x50, 0x4a, 0x4c, 0x0a, 0x8c, 0xcd, 0xce, 0xe1, 0xbd, 0xb7, - 0x1a, 0x2f, 0x02, 0x08, 0x50, 0x7d, 0x3e, 0x26, 0x5c, 0xc1, 0x4a, 0xe0, 0x9f, 0x93, 0xc8, 0xa2, - 0x2a, 0xcc, 0x7a, 0xfe, 0xfd, 0xb9, 0xb5, 0x26, 0x20, 0xb6, 0x4e, 0x3c, 0x06, 0x28, 0x74, 0xe0, - 0x6a, 0x9d, 0x90, 0x55, 0x1e, 0xac, 0x3a, 0xae, 0xb7, 0x2a, 0x0a, 0xce, 0x6d, 0x1a, 0xac, 0x5c, - 0x27, 0x38, 0x52, 0xf8, 0x83, 0xd2, 0x19, 0x7f, 0x1d, 0x0b, 0x11, 0x4f, 0xed, 0x55, 0xeb, 0xce, - 0xa2, 0x0b, 0x64, 0xb2, 0x91, 0xe8, 0x0a, 0xeb, 0x53, 0xd1, 0x7b, 0xe6, 0x8c, 0x89, 0x2a, 0xb0, - 0x82, 0x27, 0xd0, 0x12, 0x5c, 0x34, 0x18, 0xf0, 0x0f, 0x26, 0xca, 0x8c, 0x5e, 0x57, 0xa0, 0x8e, - 0xd9, 0xec, 0x5b, 0x07, 0xad, 0xed, 0x69, 0x1b, 0x21, 0xa9, 0x70, 0x86, 0xe8, 0x9b, 0x04, 0xee, - 0x8a, 0xb0, 0x38, 0x75, 0x8f, 0xe9, 0xf9, 0xfd, 0xe2, 0x29, 0xa5, 0xff, 0x0e, 0x9f, 0x40, 0x85, - 0xb5, 0x01, 0xf5, 0xca, 0xe3, 0xf8, 0x14, 0x2c, 0x25, 0x49, 0x65, 0xa9, 0xe7, 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0x91, 0x8c, 0xbe, 0x6f, 0x19, 0x14, + 0xc4, 0x8b, 0x4c, 0x6a, 0x85, 0x3d, 0xc7, 0x8e, 0x41, 0x3b, 0x17, 0x9f, 0x96, 0x64, 0x92, 0x36, + 0xd1, 0x69, 0x6c, 0x46, 0x46, 0xf4, 0xcc, 0x6c, 0x04, 0x63, 0x60, 0x8e, 0xe4, 0x76, 0x4b, 0x80, + 0x34, 0x61, 0x6d, 0xea, 0xee, 0x73, 0x50, 0x28, 0x86, 0xbd, 0x67, 0x02, 0xab, 0x34, 0x41, 0x23, + 0x63, 0x9a, 0xf9, 0xbd, 0x5c, 0xf2, 0xc8, 0x69, 0x4a, 0x7d, 0x78, 0x02, 0x09, 0x00, 0xf1, 0xd6, + 0x4f, 0x4f, 0xf4, 0x9c, 0xc4, 0x02, 0xe5, 0x2f, 0x8f, 0x20, 0x5b, 0x5d, 0x36, 0x18, 0x90, 0x77, + 0xe1, 0x79, 0xcb, 0x44, 0x38, 0x61, 0x7f, 0x6d, 0x5b, 0xa2, 0xae, 0x1d, 0x19, 0xbe, 0xed, 0xbb, + 0x52, 0xfa, 0x0a, 0x88, 0xb0, 0x1b, 0xd8, 0xc0, 0xc7, 0x7e, 0x9f, 0x7c, 0x89, 0xa6, 0xba, 0x7d, + 0xb6, 0x64, 0x31, 0x4f, 0xdc, 0x9a, 0xd5, 0x8c, 0xc7, 0x49, 0xb7, 0x67, 0x24, 0x15, 0x8a, 0xe9, + 0x44, 0x44, 0xc7, 0xbb, 0xc8, 0x2b, 0x54, 0x4b, 0x4d, 0x41, 0xdc, 0x56, 0xf0, 0x2a, 0xa7, 0xf0, + 0x74, 0x42, 0x24, 0x4a, 0xba, 0x6c, 0xaa, 0xe8, 0x7e, 0xeb, 0x4a, 0xc7, 0x4f, 0x8e, 0xc1, 0xc2, + 0x8c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0xfe, 0x57, 0xfe, 0x03, 0xcb, 0xd2, + 0x27, 0x8f, 0x00, 0x90, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7930,8 +10364,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 126976, // uncompressed data size (bytes) - 126108, // compressed data size (bytes) + 167936, // uncompressed data size (bytes) + 165046, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7943,18 +10377,18 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_desc_dbg") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_desc.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 27 +// COMPRESSED SIZE (bytes): 28 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x36, 0x23, 0x03, 0x23, - 0x1e, 0x7d, 0x00, 0xc6, 0x9c, 0xd4, 0x6c, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0xf1, 0x72, 0x20, 0xde, 0x08, 0xc4, 0x57, 0x19, 0x19, 0x18, + 0xf1, 0xe8, 0x03, 0x00, 0xd2, 0xa8, 0x0e, 0x80, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7965,7 +10399,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 27, // compressed data size (bytes) + 28, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7977,7922 +10411,10355 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_image_prod") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 126976 -// COMPRESSED SIZE (bytes): 126481 +// DATA SIZE (bytes): 167936 +// COMPRESSED SIZE (bytes): 165416 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data[] = { - 0x9c, 0x97, 0xc3, 0xb6, 0x28, 0x0a, 0x60, 0x43, 0x8f, 0x6d, 0xdb, 0xb6, 0x71, 0x8f, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xfa, 0x7e, 0xa0, 0x1d, 0x34, 0xe3, - 0x0c, 0x93, 0xac, 0x9d, 0xa1, 0x40, 0x02, 0x31, 0xb3, 0x30, 0x7a, 0x67, 0x9b, 0xdc, 0xaf, 0x37, - 0x35, 0x7c, 0x72, 0xe4, 0x37, 0x88, 0x62, 0x96, 0xf8, 0x52, 0xb3, 0xb5, 0x5d, 0xce, 0xa8, 0x3d, - 0xb6, 0xb5, 0x37, 0xd2, 0x00, 0x9d, 0x20, 0x96, 0x4d, 0x42, 0x6c, 0xbf, 0xf5, 0x53, 0x92, 0xac, - 0xc2, 0x03, 0x52, 0xd1, 0x1b, 0x97, 0x39, 0x0f, 0x7e, 0x01, 0x87, 0x5e, 0xd7, 0x90, 0x8b, 0x92, - 0xa1, 0xa2, 0xa2, 0x62, 0xd4, 0xbf, 0x25, 0x9d, 0x29, 0xc8, 0xae, 0x90, 0xd0, 0x7d, 0x9d, 0xb9, - 0xbe, 0xbb, 0x84, 0xf6, 0x72, 0x56, 0x09, 0x76, 0x9d, 0x11, 0xa9, 0xe8, 0x43, 0xb3, 0x42, 0xb1, - 0x79, 0x2b, 0xf2, 0x5f, 0x53, 0x8d, 0xef, 0xba, 0x63, 0x28, 0xd7, 0x69, 0xd1, 0x61, 0x6b, 0x40, - 0x2f, 0xff, 0xcd, 0xca, 0x05, 0x37, 0x62, 0x9d, 0x51, 0x14, 0x09, 0xec, 0x9f, 0xdb, 0x36, 0xd3, - 0x83, 0x8e, 0xd3, 0x9f, 0xc3, 0x82, 0x1b, 0x44, 0xbd, 0xc5, 0xf8, 0x52, 0xd9, 0xf6, 0x67, 0x2e, - 0x52, 0x3f, 0x43, 0x78, 0xb4, 0xef, 0x2d, 0xed, 0xaf, 0xf9, 0x05, 0x6a, 0xe1, 0x52, 0xe2, 0x11, - 0xa3, 0x79, 0xf9, 0xca, 0xa6, 0x51, 0x59, 0xc1, 0x2c, 0x8e, 0x1d, 0x21, 0xe4, 0x41, 0xb7, 0x59, - 0x11, 0x11, 0x6f, 0x10, 0x8b, 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0xd6, 0x1f, 0x22, 0x56, 0x27, 0xb4, 0x68, 0x27, 0xa8, 0xae, 0x90, + 0xbd, 0x35, 0x4f, 0x89, 0x32, 0x48, 0x8d, 0xba, 0x76, 0x25, 0xd1, 0x98, 0xf5, 0x36, 0x54, 0x4e, + 0x4d, 0x77, 0xb8, 0xca, 0x87, 0x3a, 0x60, 0xd0, 0xd5, 0x77, 0x63, 0x3e, 0x33, 0xae, 0x8c, 0xd4, + 0x89, 0xb2, 0x9a, 0x63, 0xc9, 0xec, 0x18, 0xd9, 0x1f, 0xae, 0x97, 0xca, 0xe6, 0xe7, 0x12, 0x18, + 0xb4, 0x75, 0x6b, 0x7f, 0x3c, 0x7b, 0x9c, 0x5e, 0x61, 0x39, 0xa6, 0xca, 0x0f, 0xf9, 0x3a, 0x5d, + 0x21, 0x07, 0x66, 0x64, 0xd4, 0xac, 0x5d, 0x52, 0x95, 0x65, 0x89, 0x1b, 0x85, 0xa9, 0xd6, 0x92, + 0xab, 0x76, 0x87, 0xc2, 0x34, 0xb5, 0x47, 0xa5, 0x7e, 0x1b, 0xb8, 0x3f, 0xef, 0x16, 0x97, 0x2a, + 0x24, 0x7a, 0x4b, 0x42, 0x91, 0xe8, 0xbe, 0xfd, 0xd1, 0xe3, 0x7d, 0x8c, 0xb5, 0xbf, 0xef, 0x5c, + 0x94, 0x6e, 0xe2, 0x30, 0x79, 0x71, 0x0d, 0xe9, 0x4e, 0xc9, 0xbe, 0x22, 0xed, 0xee, 0x7c, 0xd3, + 0x57, 0xd4, 0xe1, 0x1d, 0xf9, 0xce, 0x4e, 0x0b, 0x85, 0x6e, 0x7a, 0xa6, 0x7a, 0xd2, 0xc1, 0x46, + 0xa2, 0xd8, 0xe6, 0x09, 0xad, 0x62, 0x3c, 0x71, 0xf9, 0x59, 0x1b, 0x54, 0x0a, 0xab, 0x38, 0x9c, + 0x7f, 0xe5, 0xc3, 0x0f, 0x9e, 0x09, 0x1e, 0xf7, 0xe6, 0x39, 0xb1, 0xa2, 0xd7, 0x0e, 0x2a, 0x73, + 0x1e, 0xa2, 0x76, 0xe5, 0x44, 0x80, 0x2e, 0xdc, 0x7f, 0x41, 0x5e, 0x03, 0xc5, 0xc8, 0x9a, 0x7f, + 0x51, 0x94, 0x69, 0xce, 0x5e, 0xf5, 0x0a, 0xb5, 0xa3, 0xe3, 0x97, 0x2e, 0xde, 0x1f, 0xad, 0x3e, + 0x91, 0xf0, 0xbe, 0xb4, 0xc1, 0xe5, 0xd0, 0x15, 0x9a, 0x7b, 0x11, 0x25, 0x15, 0x73, 0xb3, 0x66, + 0x0a, 0xf4, 0xf5, 0x16, 0x83, 0x04, 0x6a, 0xd3, 0x3a, 0x56, 0x7b, 0xdb, 0x7c, 0x3d, 0x84, 0x5b, + 0x3d, 0x65, 0xd2, 0x14, 0x01, 0x57, 0xb4, 0x1f, 0x39, 0x6b, 0x64, 0xab, 0xb7, 0x06, 0x3e, 0xf8, + 0x1c, 0x6f, 0x77, 0x57, 0x0b, 0x41, 0x83, 0xee, 0xd7, 0xa9, 0xf8, 0x0f, 0x4f, 0xe9, 0x7c, 0x3a, + 0x32, 0x41, 0xbc, 0xe2, 0xc3, 0x6f, 0xaa, 0xc8, 0x27, 0x52, 0x79, 0x65, 0x21, 0xb7, 0x41, 0xe7, + 0x7d, 0xea, 0xa3, 0x6d, 0x7b, 0xdf, 0xec, 0xa9, 0xae, 0xa2, 0xcb, 0x5e, 0xb3, 0x8f, 0x84, 0x7d, + 0x90, 0xc2, 0x2e, 0x38, 0xdc, 0x7d, 0xd0, 0x36, 0x68, 0xf3, 0xef, 0xef, 0xc3, 0xec, 0x0e, 0x18, + 0x63, 0x4c, 0x76, 0x32, 0x51, 0x8f, 0xdb, 0xaa, 0x99, 0x0c, 0x49, 0x7b, 0x09, 0xa2, 0x8e, 0xb7, + 0x5f, 0xdf, 0xc6, 0x0c, 0xd8, 0x4f, 0xcd, 0x8a, 0xb4, 0xe1, 0x23, 0xd2, 0xcb, 0x90, 0xfa, 0x39, + 0x67, 0x67, 0x83, 0x27, 0xa8, 0xcf, 0xcb, 0xc7, 0x1b, 0x64, 0xac, 0xb1, 0x38, 0x82, 0x70, 0x25, + 0xff, 0x50, 0x35, 0x17, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xc7, 0xff, 0xca, 0xbf, + 0x62, 0xda, 0x98, 0x4c, 0x00, 0x90, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -15902,8 +20769,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 126976, // uncompressed data size (bytes) - 126481, // compressed data size (bytes) + 167936, // uncompressed data size (bytes) + 165416, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -15915,18 +20782,18 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_desc_prod") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_desc.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 27 +// COMPRESSED SIZE (bytes): 28 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x36, 0x23, 0x03, 0x23, - 0x1e, 0x7d, 0x00, 0xc6, 0x9c, 0xd4, 0x6c, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0xf1, 0x72, 0x20, 0xde, 0x08, 0xc4, 0x57, 0x19, 0x19, 0x18, + 0xf1, 0xe8, 0x03, 0x00, 0xd2, 0xa8, 0x0e, 0x80, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -15937,7 +20804,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 27, // compressed data size (bytes) + 28, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c new file mode 100644 index 0000000000..25a3ec1934 --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c @@ -0,0 +1,10637 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100("ucode_image") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 166216 +// COMPRESSED SIZE (bytes): 166206 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_data[] = +{ + 0x00, 0x38, 0x80, 0xc7, 0x7f, 0x03, 0x04, 0x48, 0x00, 0x00, 0x89, 0x02, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xd9, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x00, 0x00, 0x04, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb2, 0x54, 0x1f, + 0x85, 0x51, 0x06, 0xb7, 0x36, 0x94, 0x67, 0x62, 0x6e, 0x03, 0x39, 0x6a, 0x92, 0x36, 0xd5, 0x63, + 0xe5, 0x81, 0x6e, 0x13, 0x49, 0x59, 0xc9, 0x0d, 0xe3, 0x28, 0x62, 0x34, 0xad, 0x0d, 0x7f, 0x64, + 0x3e, 0x85, 0x89, 0x7d, 0xa4, 0xbf, 0xa0, 0xa1, 0xf8, 0xc8, 0xdd, 0x74, 0x57, 0x68, 0xce, 0x75, + 0xe1, 0x7f, 0x7e, 0x22, 0x18, 0xb7, 0xa8, 0x4c, 0x75, 0x0a, 0xd0, 0x8e, 0x71, 0xb9, 0xc4, 0x94, + 0x13, 0x8a, 0x81, 0xa3, 0x29, 0xf6, 0xcf, 0x97, 0x31, 0x13, 0x0c, 0xd7, 0x98, 0xa2, 0x13, 0xcc, + 0x5a, 0xc4, 0xe4, 0x16, 0x94, 0x7b, 0xbe, 0xa2, 0x0c, 0xd5, 0xcb, 0x67, 0xd5, 0xb4, 0x4f, 0xa8, + 0xad, 0x45, 0xe9, 0x70, 0xe3, 0x7b, 0x78, 0x74, 0x56, 0x82, 0xb5, 0x9a, 0xc0, 0xb9, 0x4e, 0x09, + 0x8f, 0xb7, 0x4b, 0xe8, 0xfd, 0xb0, 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0xca, 0xa1, 0xf1, 0xd2, 0x2d, 0x60, 0xbf, 0x7b, 0x81, 0xb0, 0xcc, 0x21, + 0x08, 0xc4, 0x29, 0x02, 0x9d, 0x73, 0xa3, 0x2b, 0xc7, 0xeb, 0xc2, 0x7d, 0xfd, 0x31, 0xf3, 0x15, + 0x79, 0x4d, 0xd3, 0xc8, 0x5d, 0x70, 0x0c, 0xea, 0x30, 0x06, 0xb8, 0x6a, 0x28, 0xd5, 0x27, 0x8c, + 0xbb, 0x4b, 0x39, 0xc1, 0xfb, 0x2d, 0x2f, 0xef, 0x68, 0x9f, 0x32, 0x56, 0x12, 0x3b, 0x72, 0x84, + 0x66, 0x30, 0x24, 0xf7, 0x7f, 0x03, 0x04, 0xf2, 0xa5, 0xb2, 0x48, 0x89, 0x02, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 166216, // uncompressed data size (bytes) + 166206, // compressed data size (bytes) + kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100("ucode_hash") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_hash.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 48 +// COMPRESSED SIZE (bytes): 61 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_data[] = +{ + 0x01, 0x30, 0x00, 0xcf, 0xff, 0xd6, 0x59, 0x82, 0x06, 0xad, 0xc8, 0x9b, 0xd7, 0x13, 0x8e, 0x9e, + 0x12, 0xc5, 0x6d, 0x9a, 0xba, 0x7f, 0xde, 0x90, 0xb9, 0xb9, 0x31, 0xd9, 0x8a, 0x9a, 0x90, 0xcd, + 0xa0, 0xbe, 0x00, 0x38, 0xc8, 0x37, 0x79, 0x0c, 0xe9, 0x9c, 0x6c, 0x0c, 0xe8, 0xca, 0x85, 0x67, + 0x50, 0xa7, 0x1a, 0x59, 0xd4, 0x7b, 0x62, 0xe1, 0x5b, 0x30, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 48, // uncompressed data size (bytes) + 61, // compressed data size (bytes) + kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100("ucode_sig") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_sig.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x6c, 0x07, 0x8d, 0x56, 0xa0, 0xe7, 0x58, 0x69, 0x73, 0xd3, 0x2e, + 0x4d, 0x23, 0x09, 0x27, 0x89, 0x99, 0xf4, 0x71, 0xf9, 0xfb, 0xe3, 0x34, 0x0f, 0x13, 0x47, 0xf2, + 0x59, 0x4a, 0xb5, 0x14, 0x76, 0xed, 0x05, 0x7a, 0xbc, 0x0b, 0x53, 0xf7, 0xe7, 0x6a, 0xf6, 0x47, + 0x27, 0x24, 0x4b, 0x44, 0x08, 0x3b, 0x32, 0xaf, 0x6c, 0x7c, 0xb8, 0xa7, 0x5c, 0x7c, 0x37, 0x00, + 0xc1, 0xd9, 0xfa, 0x88, 0x7e, 0xcf, 0xf3, 0xe8, 0xe5, 0x9f, 0x6a, 0x16, 0x27, 0x9e, 0x29, 0xc9, + 0x78, 0xae, 0xed, 0xee, 0x4e, 0x03, 0x23, 0x82, 0x6c, 0x27, 0x3a, 0x40, 0x0b, 0x35, 0xaa, 0x87, + 0x81, 0xd3, 0xcc, 0xb5, 0xb8, 0x35, 0x58, 0x4d, 0x73, 0x8d, 0x66, 0x6a, 0x59, 0x2f, 0x8a, 0x9d, + 0xcb, 0x30, 0x05, 0xc3, 0x7f, 0x83, 0x20, 0x1e, 0xf2, 0xc0, 0x19, 0x1b, 0x1d, 0xf2, 0xb2, 0x9a, + 0x0d, 0x23, 0x51, 0x30, 0xf0, 0xbf, 0xa5, 0x13, 0x0a, 0x30, 0xe7, 0x99, 0xb3, 0x12, 0x08, 0x3d, + 0xeb, 0x79, 0x22, 0x5a, 0xfa, 0xd2, 0x8c, 0x14, 0xe7, 0xfb, 0x85, 0x5e, 0x87, 0x69, 0x94, 0x25, + 0x20, 0x36, 0x0f, 0xb6, 0x39, 0x60, 0x6f, 0xf4, 0x25, 0x9f, 0x5d, 0x6f, 0xa9, 0x24, 0x83, 0x49, + 0x45, 0x1b, 0x40, 0x87, 0x6e, 0xbc, 0xb5, 0x7e, 0xf4, 0x37, 0x05, 0x05, 0x19, 0xb1, 0x4d, 0xa9, + 0x3f, 0x21, 0x2c, 0xe3, 0x3e, 0xe1, 0xbc, 0xc6, 0x88, 0xd0, 0x46, 0xd4, 0x6c, 0xa8, 0x1b, 0xc8, + 0xce, 0x10, 0x3f, 0x08, 0xbd, 0x03, 0xb7, 0xba, 0x14, 0x20, 0x0b, 0x5f, 0xf0, 0xfb, 0xde, 0x49, + 0x47, 0xb1, 0x96, 0x5e, 0x96, 0x89, 0xe4, 0xaa, 0xed, 0x74, 0xa1, 0xb3, 0xcb, 0xda, 0x58, 0xa4, + 0x3a, 0x4c, 0xa3, 0xa6, 0x33, 0x5d, 0x14, 0xa3, 0x95, 0xa0, 0x36, 0x26, 0x59, 0xcf, 0x6b, 0x74, + 0x3f, 0x17, 0x9a, 0xcc, 0x15, 0xa8, 0x7a, 0x05, 0x3a, 0x91, 0x03, 0xe9, 0x7e, 0xc5, 0x9c, 0x63, + 0x54, 0xbb, 0x8e, 0xd6, 0x93, 0x69, 0xad, 0x1f, 0x65, 0x99, 0x8b, 0x7e, 0xe5, 0x89, 0x22, 0x1e, + 0xae, 0x20, 0x87, 0x2a, 0xf5, 0x33, 0x41, 0xfe, 0x57, 0x2f, 0x46, 0xde, 0xad, 0xee, 0x4f, 0x93, + 0x91, 0xca, 0x81, 0x20, 0xd7, 0xeb, 0x12, 0x0b, 0x6a, 0xd3, 0xcb, 0x22, 0x30, 0x20, 0x35, 0x8f, + 0x07, 0xb7, 0x10, 0xf5, 0xf3, 0x4d, 0xa0, 0xbe, 0xb1, 0xf0, 0x88, 0xd7, 0x80, 0xb1, 0x20, 0x1c, + 0x9d, 0xfe, 0xb3, 0x0c, 0x43, 0x69, 0x08, 0x71, 0x78, 0xb1, 0x25, 0x71, 0xbd, 0xc0, 0x75, 0x5b, + 0xe7, 0x8e, 0xab, 0xdd, 0xc7, 0x32, 0xd3, 0xb3, 0x8d, 0x2f, 0xb9, 0xbf, 0x8c, 0x48, 0xb9, 0x2a, + 0xc6, 0x8a, 0x86, 0xd9, 0x12, 0x6d, 0x9b, 0x7c, 0x07, 0x49, 0x38, 0x27, 0x3c, 0x0c, 0xbf, 0xcc, + 0xe7, 0x81, 0x5b, 0x4e, 0x74, 0x22, 0x02, 0xe9, 0x98, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100("ucode_pkey") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_pub_key.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, + 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, + 0x8b, 0x37, 0xf9, 0x3e, 0x5a, 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, + 0xa1, 0x40, 0xae, 0x82, 0x22, 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, + 0xfc, 0xd6, 0x6c, 0x61, 0x38, 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, + 0x86, 0x2b, 0xe2, 0x5e, 0xf8, 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, + 0x59, 0x24, 0x67, 0xf8, 0x5d, 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, + 0x53, 0x4d, 0x35, 0xda, 0x06, 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, + 0xed, 0x40, 0x9c, 0x84, 0x8a, 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, + 0xc2, 0x7c, 0x39, 0x7c, 0xdb, 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, + 0x18, 0xed, 0x12, 0xdf, 0x72, 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, + 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, + 0xe8, 0x09, 0xe6, 0x2a, 0xca, 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, + 0x15, 0xd2, 0x42, 0x47, 0x71, 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, + 0xca, 0x36, 0xd4, 0x85, 0x6a, 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, + 0xf8, 0x65, 0xaf, 0xea, 0x63, 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, + 0xe5, 0xa3, 0x32, 0x5e, 0x22, 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, + 0x94, 0x7b, 0x6f, 0x77, 0xea, 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, + 0x0c, 0x30, 0x9a, 0xa7, 0xe7, 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, + 0x1f, 0xc1, 0x5e, 0xda, 0xf3, 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, + 0xaa, 0x65, 0x31, 0x00, 0x0b, 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, + 0x98, 0x07, 0x52, 0xbc, 0x3e, 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, + 0xf9, 0xc1, 0x33, 0x69, 0x1b, 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, + 0x4b, 0xd1, 0x51, 0x83, 0xaa, 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, + 0x4f, 0x02, 0x0d, 0xf6, 0x1b, 0xdb, 0x48, 0x80, 0x58, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100 = +{ + 4, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_storage_pvt }, + { "ucode_hash" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_storage_pvt }, + { "ucode_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_storage_pvt }, + { "ucode_pkey" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c index 27f6432349..3a9f2068f3 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c @@ -29,7899 +29,10332 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_image") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 126536 -// COMPRESSED SIZE (bytes): 126124 +// DATA SIZE (bytes): 165448 +// COMPRESSED SIZE (bytes): 165050 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data[] = { - 0x8c, 0x96, 0x53, 0x92, 0x28, 0x00, 0x82, 0xc0, 0xda, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xee, - 0x7e, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x39, 0x53, 0x5b, 0x73, 0x80, 0xcd, - 0x4f, 0x72, 0x84, 0x00, 0x83, 0x48, 0x00, 0x00, 0xdc, 0x02, 0x02, 0xfc, 0x1f, 0xd6, 0xff, 0xb3, - 0x07, 0x00, 0x00, 0xc8, 0xff, 0x12, 0x90, 0x02, 0xe0, 0xff, 0x85, 0x87, 0xd1, 0xcd, 0x53, 0x36, - 0x1e, 0x92, 0x4f, 0x54, 0xde, 0x2c, 0x70, 0x5e, 0xe0, 0x57, 0xe7, 0xde, 0xb5, 0x8c, 0x2c, 0xb3, - 0x8d, 0xc3, 0xed, 0x6d, 0xf6, 0x75, 0xfe, 0x59, 0x50, 0x32, 0xce, 0xb9, 0xa0, 0xed, 0xbe, 0x18, - 0xd8, 0x1a, 0x95, 0x69, 0x54, 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0x40, 0x50, 0x62, 0x1a, 0x2f, 0x86, 0x19, 0x92, 0xab, 0x6b, 0x75, 0x9d, + 0xec, 0x32, 0xa8, 0x32, 0x97, 0x99, 0x67, 0xc0, 0xfe, 0x02, 0xb9, 0xc8, 0x7f, 0x9c, 0x44, 0x73, + 0x8c, 0x80, 0x07, 0xdc, 0xc1, 0xa9, 0xff, 0x60, 0xee, 0xf3, 0x3a, 0xb6, 0x81, 0xe8, 0x31, 0x6c, + 0x72, 0xe4, 0x7b, 0xb3, 0x0d, 0x24, 0x94, 0x08, 0x78, 0x1f, 0x03, 0x24, 0xe8, 0x10, 0x1d, 0x1a, + 0xfb, 0xba, 0xee, 0x53, 0x09, 0xec, 0xa1, 0x70, 0x4d, 0x5e, 0x0e, 0x2d, 0xb8, 0x1e, 0x18, 0x82, + 0x38, 0x51, 0xeb, 0x31, 0x6f, 0x7c, 0x19, 0x39, 0xf9, 0x03, 0x87, 0x50, 0x7d, 0x9e, 0x75, 0x5f, + 0x46, 0xa9, 0xe5, 0xef, 0xdd, 0xc6, 0xe3, 0x14, 0x35, 0xdc, 0x1d, 0x3c, 0xe0, 0x73, 0xa8, 0x1f, + 0xf1, 0x47, 0x44, 0xcc, 0xd8, 0x61, 0x48, 0x86, 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7931,8 +10364,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 126536, // uncompressed data size (bytes) - 126124, // compressed data size (bytes) + 165448, // uncompressed data size (bytes) + 165050, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7944,7 +10377,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_hash") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_hash.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_hash.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -7954,10 +10387,10 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0xc8, 0x81, 0x78, 0x61, 0x05, 0x0d, 0xf6, 0x5c, 0x2a, 0x7d, 0x76, - 0x7e, 0x0e, 0x15, 0xb9, 0xc0, 0x7b, 0x8c, 0x9c, 0xa3, 0xc9, 0x89, 0xd9, 0x93, 0x59, 0xed, 0xa0, - 0xb2, 0xa0, 0xe8, 0xa7, 0xd4, 0x9f, 0x0d, 0x42, 0x5c, 0x9e, 0x2b, 0x84, 0xba, 0x1c, 0x58, 0x6b, - 0x24, 0xd5, 0x18, 0x93, 0xbc, 0x3f, 0xe7, 0xe2, 0x4d, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0x7f, 0x1e, 0xa1, 0x0c, 0x20, 0xb3, 0x51, 0x80, 0x45, 0x55, 0x19, + 0x35, 0xd8, 0x82, 0x97, 0x64, 0x31, 0xc3, 0x1c, 0x29, 0xe1, 0x86, 0x7e, 0x09, 0xac, 0xbd, 0x51, + 0xf5, 0x5b, 0x6f, 0x09, 0x18, 0x5d, 0xdc, 0x55, 0x3e, 0xa2, 0x99, 0x3e, 0x95, 0x59, 0x5d, 0xb8, + 0xf3, 0x5c, 0xc9, 0x57, 0x74, 0xdd, 0xd2, 0xa2, 0xe7, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7980,7 +10413,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storag #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_sig") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_sig.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_sig.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -7990,31 +10423,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storag // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x4d, 0x2e, 0xd9, 0x9d, 0xe6, 0x9c, 0x0e, 0xc3, 0xf6, 0x69, 0x89, - 0xb2, 0xd2, 0x7d, 0x0d, 0x86, 0x10, 0xfc, 0x28, 0x9f, 0x7b, 0x75, 0x88, 0x13, 0x67, 0xd0, 0xf6, - 0xed, 0x97, 0x6f, 0xf1, 0xd2, 0xf8, 0x39, 0xeb, 0xf1, 0xf1, 0xab, 0x6a, 0xe7, 0x8c, 0x9a, 0xa9, - 0x07, 0xbc, 0x31, 0xca, 0x17, 0xa4, 0x0f, 0x03, 0x20, 0xab, 0x72, 0xec, 0xff, 0x8a, 0x31, 0x52, - 0x90, 0x21, 0xe4, 0x35, 0x3f, 0x42, 0xbf, 0x36, 0x19, 0xb6, 0x90, 0xca, 0x89, 0xd5, 0x98, 0x7b, - 0x19, 0xcf, 0xd2, 0x48, 0x30, 0x70, 0xc4, 0xe1, 0x04, 0xe9, 0xa0, 0x3a, 0xb1, 0x83, 0xbe, 0x7f, - 0x4f, 0x00, 0xa2, 0x62, 0xf2, 0xd6, 0x2b, 0x89, 0xb8, 0x31, 0xd1, 0x1e, 0x54, 0xf5, 0xab, 0x5f, - 0xac, 0x86, 0xd1, 0x36, 0x85, 0xf7, 0x8f, 0xee, 0x8f, 0x57, 0xb0, 0x86, 0x96, 0x9f, 0x2c, 0x3e, - 0xac, 0xb7, 0xa0, 0x2e, 0xba, 0x83, 0x7c, 0x74, 0xa9, 0xfe, 0xca, 0xb4, 0xc2, 0xea, 0xfe, 0x39, - 0xe3, 0x33, 0x35, 0xaa, 0xb5, 0xf0, 0x03, 0x5e, 0x81, 0x21, 0x04, 0x17, 0x23, 0xef, 0xc7, 0xa9, - 0x3a, 0x42, 0xf8, 0xe2, 0xac, 0x07, 0xfb, 0x91, 0xff, 0xc8, 0x37, 0xfe, 0x21, 0x60, 0x71, 0x77, - 0x2e, 0x79, 0x95, 0xcd, 0xf1, 0x52, 0x1b, 0x4c, 0x7e, 0x95, 0x15, 0x2c, 0x04, 0xdb, 0xc7, 0xe3, - 0x95, 0x32, 0xb5, 0x78, 0x99, 0xae, 0x88, 0x43, 0x7e, 0x06, 0xe5, 0x86, 0x5c, 0x6e, 0x7e, 0x45, - 0xf8, 0x42, 0x49, 0x1c, 0x5a, 0xaa, 0x91, 0xa5, 0x1c, 0xc0, 0xad, 0x85, 0x48, 0x11, 0x4d, 0x42, - 0x50, 0x27, 0x31, 0xc6, 0x10, 0xec, 0x60, 0xd7, 0x7b, 0x47, 0xba, 0x6c, 0x86, 0xae, 0x94, 0xeb, - 0x31, 0x9c, 0x80, 0xca, 0xd7, 0xcf, 0x5e, 0x49, 0x7c, 0x6f, 0x28, 0xb8, 0x8a, 0x70, 0xcd, 0x0d, - 0x06, 0x05, 0x34, 0xf7, 0xa1, 0xa6, 0x30, 0x34, 0x90, 0xaf, 0xcd, 0x04, 0xfd, 0xba, 0xc0, 0x96, - 0x04, 0x0f, 0xa2, 0x27, 0xba, 0xa3, 0xb6, 0x3a, 0x1c, 0x9a, 0xb7, 0x9b, 0x83, 0x39, 0xe6, 0x97, - 0x8a, 0x0c, 0xce, 0x8d, 0xc1, 0x42, 0x15, 0xa3, 0xd9, 0x33, 0x31, 0x16, 0xeb, 0xe3, 0xd0, 0xfb, - 0x00, 0x7c, 0xa3, 0x73, 0x19, 0x02, 0x05, 0xb6, 0xed, 0xd4, 0xd5, 0x6c, 0x3a, 0xbc, 0x39, 0xa9, - 0xd6, 0x5d, 0xd1, 0x5c, 0x54, 0xde, 0x4e, 0xe8, 0x5f, 0xf6, 0xe7, 0xac, 0x94, 0x22, 0x21, 0xff, - 0xce, 0x22, 0xfb, 0x60, 0x08, 0x6a, 0x4d, 0xdf, 0xf3, 0x0a, 0x51, 0xfe, 0x02, 0x7b, 0x51, 0x13, - 0x14, 0xec, 0xea, 0x95, 0xa0, 0x6e, 0x24, 0x5e, 0x31, 0x1a, 0x85, 0xd9, 0x80, 0x4a, 0x9d, 0xca, - 0x1b, 0x5e, 0xa5, 0xfd, 0x9a, 0xf5, 0x51, 0x2d, 0x37, 0xfa, 0xdd, 0xce, 0xfa, 0x2c, 0xb3, 0x21, - 0xcb, 0x31, 0x93, 0x33, 0x97, 0xfa, 0x1d, 0xe8, 0x50, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x4a, 0xa7, 0x47, 0xb4, 0x16, 0xeb, 0x4e, 0xbd, 0xd2, 0x1f, 0x6a, + 0x71, 0xe2, 0xdd, 0xe8, 0x04, 0x12, 0xd8, 0x82, 0xc9, 0x89, 0x00, 0xae, 0x14, 0xa8, 0x75, 0x8b, + 0xc4, 0xff, 0x84, 0x00, 0x48, 0xa0, 0xc6, 0x9f, 0x06, 0x8a, 0x5e, 0x00, 0x6e, 0x1e, 0xe1, 0xa2, + 0x03, 0x1a, 0x38, 0x8c, 0xd3, 0xac, 0x5b, 0xb6, 0x64, 0xed, 0x71, 0xdf, 0x59, 0x89, 0xd5, 0x10, + 0xce, 0xf5, 0x02, 0x23, 0x67, 0x62, 0x70, 0x0f, 0x3f, 0xb7, 0x0e, 0xc6, 0x5c, 0x70, 0x2c, 0x94, + 0xb0, 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@@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_storage #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_pkey") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_pub_key.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_pub_key.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c index 3650c3f8ab..8629bbf51f 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c @@ -29,7923 +29,10356 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_image") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 126536 -// COMPRESSED SIZE (bytes): 126502 +// DATA SIZE (bytes): 165448 +// COMPRESSED SIZE (bytes): 165426 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data[] = { - 0x8c, 0x97, 0x53, 0x92, 0x28, 0x0a, 0x80, 0x43, 0xdb, 0xb6, 0xfb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf3, 0x6a, 0x6a, 0x16, 0x30, 0xf9, - 0x49, 0x56, 0x90, 0xe4, 0x00, 0x83, 0x88, 0x03, 0x00, 0xdc, 0x02, 0x02, 0xfc, 0xaf, 0xac, 0xfe, - 0xcf, 0x3d, 0x00, 0x00, 0x40, 0xfe, 0x2f, 0x02, 0x92, 0x03, 0xfc, 0xbf, 0xb4, 0xa4, 0xb9, 0x22, - 0xe8, 0x30, 0xc4, 0xe5, 0x2c, 0x4c, 0xa1, 0xf5, 0x03, 0x3c, 0x01, 0x8a, 0x50, 0x2f, 0xcd, 0x52, - 0xc8, 0x3b, 0xc9, 0x05, 0x5d, 0x82, 0xe5, 0x1b, 0x76, 0x2b, 0xe2, 0x8f, 0x2d, 0x8f, 0xe7, 0x33, - 0xf3, 0x8d, 0xbe, 0xdf, 0xef, 0xb4, 0x52, 0x08, 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0xbc, 0x64, 0x31, 0x8e, 0x0f, 0xc3, 0x3f, + 0x2f, 0x07, 0xde, 0xdc, 0xd6, 0xf5, 0xcf, 0x3a, 0xed, 0x8b, 0x93, 0x54, 0x36, 0xae, 0xcb, 0xd9, + 0x77, 0xfd, 0x10, 0xd1, 0x62, 0x9d, 0x84, 0x8e, 0xe9, 0xcb, 0x75, 0xdf, 0x5b, 0x88, 0x5b, 0xdd, + 0x26, 0x27, 0xd0, 0xa5, 0x34, 0x4f, 0xa8, 0xf1, 0x97, 0x93, 0x8c, 0x35, 0xbe, 0x05, 0xe2, 0x31, + 0xab, 0x8b, 0xc9, 0x33, 0xa2, 0x0e, 0x35, 0xcd, 0x5d, 0x25, 0xe5, 0x8d, 0x94, 0xd0, 0x8c, 0x81, + 0x9f, 0x09, 0xd7, 0xf5, 0xb6, 0xee, 0xe5, 0x1a, 0x5a, 0xea, 0x45, 0x3d, 0x8e, 0x0c, 0xc3, 0xb9, + 0x5f, 0x61, 0xc8, 0x60, 0x5a, 0x6b, 0x5f, 0x33, 0xf0, 0x95, 0xbe, 0xa2, 0x73, 0xbb, 0x93, 0x42, + 0xab, 0x59, 0x1f, 0x37, 0xf7, 0xb8, 0x31, 0xb1, 0xca, 0x9f, 0x0d, 0x19, 0x82, 0x27, 0x25, 0x57, + 0x79, 0xe1, 0xdb, 0xfc, 0x37, 0xfc, 0x2c, 0xcc, 0xc6, 0xdf, 0xf5, 0xd0, 0xbe, 0xef, 0x85, 0x5b, + 0xf4, 0x71, 0x82, 0x01, 0xdf, 0x63, 0x29, 0x18, 0x97, 0x97, 0x40, 0x6b, 0x2a, 0xe0, 0xfe, 0xd7, + 0x16, 0x96, 0xed, 0xdc, 0xea, 0x61, 0x4d, 0x27, 0xc0, 0x75, 0x05, 0x59, 0xe2, 0xbe, 0xe8, 0xb1, + 0x10, 0x11, 0x82, 0x75, 0xde, 0xe4, 0x5d, 0x10, 0x22, 0xad, 0x76, 0x9c, 0x5c, 0x40, 0x3f, 0x54, + 0x31, 0x7c, 0x36, 0x33, 0x88, 0xef, 0x08, 0x27, 0x1c, 0x08, 0x21, 0x53, 0x7f, 0xa8, 0x22, 0xcd, + 0x15, 0xbb, 0x0e, 0x98, 0x36, 0xd0, 0x13, 0x94, 0xa3, 0xc6, 0x48, 0xaa, 0xed, 0x36, 0x48, 0x86, + 0x02, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7955,8 +10388,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 126536, // uncompressed data size (bytes) - 126502, // compressed data size (bytes) + 165448, // uncompressed data size (bytes) + 165426, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7968,7 +10401,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_hash") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_hash.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_hash.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -7978,10 +10411,10 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x95, 0xd7, 0x99, 0x29, 0xc6, 0xba, 0x9e, 0xf6, 0x5a, 0xf9, 0x11, - 0xd5, 0x07, 0x19, 0xae, 0x2c, 0xf5, 0x75, 0xae, 0xff, 0x71, 0xc1, 0x4f, 0x9e, 0xba, 0x3a, 0x0b, - 0xa5, 0xf0, 0x67, 0xf7, 0x9d, 0x28, 0x17, 0x6e, 0xea, 0xd6, 0x47, 0xaf, 0xd1, 0xe3, 0xa5, 0x79, - 0x48, 0x74, 0x6b, 0x39, 0xfe, 0x0b, 0xe4, 0x21, 0xf3, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0xd5, 0xe8, 0xe5, 0x36, 0x6d, 0x3f, 0x19, 0x62, 0x00, 0x41, 0x0f, + 0x7e, 0xd3, 0x3e, 0xeb, 0xa4, 0x63, 0xd8, 0xd3, 0xd7, 0x9b, 0x0d, 0xc3, 0xf2, 0xe0, 0xb3, 0xa4, + 0xd1, 0x7f, 0xdf, 0x8a, 0x76, 0xab, 0xbf, 0xa8, 0xe1, 0xcf, 0x07, 0x9a, 0x02, 0xdf, 0x27, 0x1f, + 0xfe, 0xfd, 0x4c, 0x3f, 0x36, 0x8f, 0x59, 0x1e, 0x8f, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -8004,7 +10437,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_sig") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_sig.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_sig.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -8014,31 +10447,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x8b, 0xe3, 0x0f, 0xdd, 0x2d, 0x07, 0xaf, 0x06, 0x29, 0x5a, 0xee, - 0xc8, 0x8c, 0x39, 0x04, 0x6c, 0xf7, 0x0f, 0xcf, 0x4f, 0xdd, 0x37, 0x4c, 0xb7, 0x07, 0x0b, 0xfa, - 0x21, 0xaa, 0x22, 0x7b, 0xbe, 0x74, 0xca, 0xf2, 0x15, 0x16, 0x67, 0x23, 0x05, 0xed, 0x37, 0xd5, - 0xd5, 0x69, 0x78, 0xf8, 0xcb, 0x90, 0x39, 0x4d, 0x8b, 0x51, 0x00, 0x32, 0x6c, 0x8e, 0x88, 0xa4, - 0x94, 0xcc, 0xdb, 0x7d, 0xf0, 0x9e, 0x34, 0x91, 0x7e, 0xcc, 0x8f, 0xd0, 0xca, 0x74, 0xf0, 0x80, - 0x25, 0x4b, 0x6b, 0x3b, 0x2c, 0x07, 0xb6, 0x37, 0x43, 0xe6, 0x94, 0x79, 0x14, 0x56, 0x9a, 0xd0, - 0xd7, 0xe2, 0xbb, 0xc0, 0x40, 0xb2, 0x17, 0x4f, 0x62, 0x9d, 0x57, 0x4a, 0x8a, 0x0f, 0xd5, 0xdb, - 0x1b, 0xad, 0x28, 0x33, 0x47, 0x4a, 0x99, 0x18, 0x54, 0x85, 0x01, 0xeb, 0x62, 0x28, 0x0d, 0xf2, - 0x18, 0x87, 0x26, 0x4b, 0xd7, 0x8c, 0xe0, 0x6e, 0x98, 0x05, 0x30, 0x77, 0xc7, 0x43, 0x40, 0x6e, - 0x78, 0x97, 0x4c, 0x52, 0x86, 0xc9, 0xf3, 0x02, 0xc8, 0x9d, 0x3a, 0xc2, 0x09, 0x14, 0x0b, 0xde, - 0xb7, 0x1e, 0xee, 0xa7, 0xdd, 0xca, 0x60, 0x97, 0x5c, 0x42, 0x9e, 0x5c, 0x09, 0x12, 0x96, 0xba, - 0x49, 0x5e, 0xad, 0x2b, 0x69, 0xe2, 0xba, 0x60, 0x22, 0x31, 0x96, 0x2b, 0xf4, 0x09, 0xa4, 0xce, - 0x1b, 0x6e, 0x4a, 0x09, 0xb9, 0xbb, 0x36, 0xd6, 0x52, 0xb6, 0x08, 0xbd, 0x49, 0xc2, 0xba, 0xf5, - 0xe1, 0x62, 0x5d, 0x34, 0xf1, 0x72, 0x77, 0x90, 0xa1, 0x25, 0x79, 0x23, 0x24, 0x5a, 0xf6, 0xd0, - 0x37, 0xad, 0x58, 0x3e, 0x71, 0x22, 0x62, 0xa3, 0x91, 0x30, 0x6f, 0x9d, 0x7a, 0x5c, 0x06, 0x49, - 0x87, 0xf2, 0xdb, 0x22, 0x74, 0xf9, 0x50, 0xbc, 0x40, 0x8d, 0x6c, 0xd6, 0x02, 0x08, 0xa8, 0xb8, - 0xc8, 0xea, 0xd2, 0x99, 0x0c, 0x9b, 0x27, 0x09, 0xe7, 0x42, 0xe6, 0x39, 0x1c, 0xa7, 0x0c, 0xa9, - 0xfd, 0x4c, 0xfb, 0xbd, 0xd0, 0x3e, 0x64, 0xe8, 0x39, 0x4f, 0xcc, 0x90, 0x56, 0x80, 0xcf, 0x10, - 0x09, 0xc7, 0x12, 0xb0, 0xd6, 0xec, 0xee, 0x26, 0xa8, 0x86, 0x9e, 0x1f, 0x48, 0xc4, 0x29, 0x94, - 0xf3, 0x92, 0x5c, 0xd7, 0xc0, 0xea, 0x88, 0x67, 0x76, 0x14, 0x8f, 0xb1, 0x36, 0x47, 0x5b, 0x1d, - 0xb0, 0x7f, 0xcf, 0x86, 0x82, 0x00, 0xf5, 0xb5, 0xff, 0x4c, 0x73, 0xf7, 0x64, 0x25, 0x22, 0x97, - 0x88, 0x4b, 0x7d, 0x2d, 0x84, 0x95, 0xf6, 0xad, 0x22, 0x1b, 0x9a, 0xfa, 0xf1, 0x58, 0xcd, 0xa4, - 0x75, 0xf9, 0xea, 0x85, 0x74, 0x86, 0x9e, 0x94, 0x1d, 0xc1, 0xd6, 0xc7, 0xd1, 0xc9, 0x05, 0xe4, - 0x36, 0x77, 0x89, 0xe8, 0x27, 0x98, 0x83, 0xf9, 0x22, 0x37, 0x64, 0x3e, 0x0f, 0x5b, 0x4c, 0x22, - 0xcb, 0x76, 0x8c, 0x26, 0xba, 0x6d, 0x6e, 0xda, 0x49, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x13, 0xe7, 0xa8, 0xef, 0x77, 0x38, 0xfe, 0x4f, 0xad, 0xcd, 0x5f, + 0xb3, 0xbf, 0x23, 0xc2, 0x58, 0x7e, 0x8b, 0xfe, 0x4f, 0xb5, 0xbc, 0x69, 0x81, 0x03, 0xb5, 0x83, + 0x70, 0xd2, 0x9e, 0x98, 0xfc, 0x11, 0x41, 0x89, 0xa3, 0x0d, 0x46, 0x4e, 0x5f, 0x4b, 0xeb, 0x3d, + 0xb3, 0xcb, 0x27, 0x81, 0x07, 0x25, 0xc1, 0xe5, 0xe5, 0xcc, 0x20, 0xa9, 0xfb, 0x9a, 0x9b, 0x36, + 0xd6, 0x6e, 0x6d, 0x35, 0xa9, 0x39, 0x21, 0xec, 0x56, 0x3a, 0x71, 0xb2, 0x9e, 0xbe, 0x0d, 0x97, + 0xeb, 0x84, 0xd3, 0x54, 0x18, 0xcd, 0x9c, 0x8e, 0xfc, 0x22, 0x22, 0xf3, 0xd6, 0x3a, 0x63, 0x09, + 0xbc, 0xc2, 0x83, 0xc2, 0x92, 0x16, 0x56, 0x99, 0x9b, 0xb1, 0x55, 0xf8, 0x46, 0xfc, 0x81, 0x7a, + 0xc6, 0x5a, 0x35, 0x39, 0x41, 0x80, 0xbc, 0x60, 0x60, 0xc3, 0x66, 0x43, 0xa6, 0xf4, 0xb7, 0x5d, + 0xa5, 0xd2, 0x06, 0xa4, 0x29, 0x5f, 0x08, 0xba, 0x2d, 0x2d, 0xba, 0x0e, 0x6a, 0x8e, 0x0e, 0xeb, + 0x3e, 0xcb, 0x9a, 0x84, 0xd7, 0xf0, 0x90, 0x5c, 0x08, 0x92, 0xa1, 0xae, 0x97, 0x0f, 0xd1, 0x34, + 0xf1, 0xad, 0x85, 0xa0, 0x3e, 0x11, 0xc8, 0xdd, 0x97, 0x8a, 0xb4, 0x04, 0xbe, 0x7d, 0xac, 0xe1, + 0x42, 0x2a, 0xcb, 0xf5, 0x09, 0xdf, 0xd7, 0x51, 0xe5, 0xcc, 0x02, 0xcd, 0xd3, 0x01, 0x14, 0x24, + 0xb4, 0xa5, 0xc4, 0xf6, 0xbf, 0xb7, 0x3d, 0x37, 0xdb, 0xe0, 0x3e, 0x6a, 0xca, 0x09, 0xf9, 0xef, + 0xd4, 0x77, 0xad, 0x98, 0x5f, 0xd4, 0x6c, 0x31, 0xc7, 0x49, 0x78, 0x1c, 0x5b, 0xb0, 0x27, 0xc4, + 0x21, 0x91, 0x93, 0x72, 0xb4, 0x16, 0x8e, 0x83, 0x55, 0xd1, 0x3e, 0xfd, 0x6c, 0xa5, 0x74, 0x10, + 0x72, 0x27, 0xe0, 0xd2, 0xfc, 0x57, 0xb1, 0x97, 0xf4, 0x0a, 0x03, 0x80, 0xf7, 0xe9, 0xbe, 0x90, + 0xc1, 0x4f, 0x8f, 0xac, 0x25, 0xe8, 0x11, 0x83, 0x93, 0x82, 0xf1, 0x75, 0x9a, 0xec, 0xc1, 0x49, + 0x00, 0x4c, 0x98, 0x4b, 0x19, 0x9f, 0x97, 0x43, 0xe7, 0x27, 0x5a, 0xab, 0x89, 0x51, 0xfe, 0xcd, + 0x43, 0xdf, 0xf8, 0x78, 0x26, 0xcc, 0x54, 0x92, 0xea, 0xd4, 0xda, 0x9c, 0xd7, 0x28, 0x37, 0xa6, + 0x4a, 0x14, 0xd4, 0xf0, 0x37, 0xbb, 0x42, 0x55, 0x4e, 0x36, 0x3c, 0x0f, 0xfb, 0xc4, 0x9b, 0x3e, + 0x35, 0xe5, 0xbe, 0x70, 0xcc, 0x45, 0xc8, 0x20, 0x64, 0xf6, 0x36, 0x94, 0x12, 0x99, 0x95, 0x95, + 0xf9, 0xa9, 0x58, 0xf6, 0xc9, 0xb5, 0x9d, 0x25, 0x10, 0x34, 0x80, 0x23, 0xf8, 0x51, 0xa2, 0x51, + 0x85, 0xe9, 0x59, 0x0c, 0xe8, 0x60, 0xb6, 0x92, 0x9c, 0xf4, 0x45, 0x10, 0xd8, 0xd9, 0xab, 0x4e, + 0xde, 0x9a, 0x00, 0xd2, 0x5e, 0x9d, 0x6b, 0xb2, 0x06, 0x2d, 0x0b, 0x24, 0xc9, 0x28, 0x16, 0x02, + 0x64, 0x77, 0x2a, 0x11, 0xe0, 0x3a, 0x39, 0x8d, 0x4a, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -8061,7 +10494,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_storage_ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_pkey") -// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_pub_key.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_pub_key.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES diff --git a/src/nvidia/generated/g_ce_utils_nvoc.c b/src/nvidia/generated/g_ce_utils_nvoc.c new file mode 100644 index 0000000000..fe0012affb --- /dev/null +++ b/src/nvidia/generated/g_ce_utils_nvoc.c @@ -0,0 +1,165 @@ +#define NVOC_CE_UTILS_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_ce_utils_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x8b8bae = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtils; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_CeUtils(CeUtils*); +void __nvoc_init_funcTable_CeUtils(CeUtils*); +NV_STATUS __nvoc_ctor_CeUtils(CeUtils*, OBJGPU * arg_pGpu, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams); +void __nvoc_init_dataField_CeUtils(CeUtils*); +void __nvoc_dtor_CeUtils(CeUtils*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_CeUtils; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtils_CeUtils = { + /*pClassDef=*/ &__nvoc_class_def_CeUtils, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_CeUtils, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtils_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CeUtils, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_CeUtils = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_CeUtils_CeUtils, + &__nvoc_rtti_CeUtils_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtils = +{ + /*classInfo=*/ { + /*size=*/ sizeof(CeUtils), + /*classId=*/ classId(CeUtils), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "CeUtils", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_CeUtils, + /*pCastInfo=*/ &__nvoc_castinfo_CeUtils, + /*pExportInfo=*/ &__nvoc_export_info_CeUtils +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_CeUtils = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_CeUtils(CeUtils *pThis) { + __nvoc_ceutilsDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_CeUtils(CeUtils *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_CeUtils(CeUtils *pThis, OBJGPU * arg_pGpu, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_CeUtils_fail_Object; + __nvoc_init_dataField_CeUtils(pThis); + + status = __nvoc_ceutilsConstruct(pThis, arg_pGpu, arg_pAllocParams); + if (status != NV_OK) goto __nvoc_ctor_CeUtils_fail__init; + goto __nvoc_ctor_CeUtils_exit; // Success + +__nvoc_ctor_CeUtils_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_CeUtils_fail_Object: +__nvoc_ctor_CeUtils_exit: + + return status; +} + +static void __nvoc_init_funcTable_CeUtils_1(CeUtils *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_CeUtils(CeUtils *pThis) { + __nvoc_init_funcTable_CeUtils_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_CeUtils(CeUtils *pThis) { + pThis->__nvoc_pbase_CeUtils = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_CeUtils(pThis); +} + +NV_STATUS __nvoc_objCreate_CeUtils(CeUtils **ppThis, Dynamic *pParent, NvU32 createFlags, OBJGPU * arg_pGpu, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams) { + NV_STATUS status; + Object *pParentObj; + CeUtils *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CeUtils), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(CeUtils)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CeUtils); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_CeUtils(pThis); + status = __nvoc_ctor_CeUtils(pThis, arg_pGpu, arg_pAllocParams); + if (status != NV_OK) goto __nvoc_objCreate_CeUtils_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_CeUtils_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(CeUtils)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_CeUtils(CeUtils **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + OBJGPU * arg_pGpu = va_arg(args, OBJGPU *); + NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams = va_arg(args, NV0050_ALLOCATION_PARAMETERS *); + + status = __nvoc_objCreate_CeUtils(ppThis, pParent, createFlags, arg_pGpu, arg_pAllocParams); + + return status; +} + diff --git a/src/nvidia/generated/g_ce_utils_nvoc.h b/src/nvidia/generated/g_ce_utils_nvoc.h new file mode 100644 index 0000000000..c42aca51eb --- /dev/null +++ b/src/nvidia/generated/g_ce_utils_nvoc.h @@ -0,0 +1,233 @@ +#ifndef _G_CE_UTILS_NVOC_H_ +#define _G_CE_UTILS_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_ce_utils_nvoc.h" + +#ifndef CE_UTILS_H +#define CE_UTILS_H + +#include "gpu/gpu_resource.h" // GpuResource +#include "class/cl0050.h" +#include "ctrl/ctrl0050.h" + +#include "kernel/gpu/mem_mgr/channel_utils.h" + +typedef struct +{ + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 offset; + NvU64 length; + NvU32 pattern; + NvU64 flags; + NvU64 submittedWorkId; // Payload to poll for async completion +} CEUTILS_MEMSET_PARAMS; + +typedef struct +{ + MEMORY_DESCRIPTOR *pSrcMemDesc; + MEMORY_DESCRIPTOR *pDstMemDesc; + NvU64 dstOffset; + NvU64 srcOffset; + NvU64 length; + NvU64 flags; + NvU64 submittedWorkId; // Payload to poll for async completion +} CEUTILS_MEMCOPY_PARAMS; + + +#ifdef NVOC_CE_UTILS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct CeUtils { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct CeUtils *__nvoc_pbase_CeUtils; + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + OBJCHANNEL *pChannel; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance; + OBJGPU *pGpu; + struct KernelCE *pKCe; + NvBool bUseVasForCeCopy; + NvU32 hTdCopyClass; + NvU64 lastSubmittedPayload; + NvU64 lastCompletedPayload; +}; + +#ifndef __NVOC_CLASS_CeUtils_TYPEDEF__ +#define __NVOC_CLASS_CeUtils_TYPEDEF__ +typedef struct CeUtils CeUtils; +#endif /* __NVOC_CLASS_CeUtils_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CeUtils +#define __nvoc_class_id_CeUtils 0x8b8bae +#endif /* __nvoc_class_id_CeUtils */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtils; + +#define __staticCast_CeUtils(pThis) \ + ((pThis)->__nvoc_pbase_CeUtils) + +#ifdef __nvoc_ce_utils_h_disabled +#define __dynamicCast_CeUtils(pThis) ((CeUtils*)NULL) +#else //__nvoc_ce_utils_h_disabled +#define __dynamicCast_CeUtils(pThis) \ + ((CeUtils*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(CeUtils))) +#endif //__nvoc_ce_utils_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_CeUtils(CeUtils**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_CeUtils(CeUtils**, Dynamic*, NvU32, OBJGPU * arg_pGpu, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams); +#define __objCreate_CeUtils(ppNewObj, pParent, createFlags, arg_pGpu, arg_pAllocParams) \ + __nvoc_objCreate_CeUtils((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pGpu, arg_pAllocParams) + +NV_STATUS ceutilsConstruct_IMPL(struct CeUtils *arg_pCeUtils, OBJGPU *arg_pGpu, NV0050_ALLOCATION_PARAMETERS *arg_pAllocParams); + +#define __nvoc_ceutilsConstruct(arg_pCeUtils, arg_pGpu, arg_pAllocParams) ceutilsConstruct_IMPL(arg_pCeUtils, arg_pGpu, arg_pAllocParams) +void ceutilsDestruct_IMPL(struct CeUtils *pCeUtils); + +#define __nvoc_ceutilsDestruct(pCeUtils) ceutilsDestruct_IMPL(pCeUtils) +NV_STATUS ceutilsInitialize_IMPL(struct CeUtils *pCeUtils, OBJGPU *pGpu, NV0050_ALLOCATION_PARAMETERS *pAllocParams); + +#ifdef __nvoc_ce_utils_h_disabled +static inline NV_STATUS ceutilsInitialize(struct CeUtils *pCeUtils, OBJGPU *pGpu, NV0050_ALLOCATION_PARAMETERS *pAllocParams) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsInitialize(pCeUtils, pGpu, pAllocParams) ceutilsInitialize_IMPL(pCeUtils, pGpu, pAllocParams) +#endif //__nvoc_ce_utils_h_disabled + +void ceutilsDeinit_IMPL(struct CeUtils *pCeUtils); + +#ifdef __nvoc_ce_utils_h_disabled +static inline void ceutilsDeinit(struct CeUtils *pCeUtils) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsDeinit(pCeUtils) ceutilsDeinit_IMPL(pCeUtils) +#endif //__nvoc_ce_utils_h_disabled + +void ceutilsRegisterGPUInstance_IMPL(struct CeUtils *pCeUtils, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance); + +#ifdef __nvoc_ce_utils_h_disabled +static inline void ceutilsRegisterGPUInstance(struct CeUtils *pCeUtils, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsRegisterGPUInstance(pCeUtils, pKernelMIGGPUInstance) ceutilsRegisterGPUInstance_IMPL(pCeUtils, pKernelMIGGPUInstance) +#endif //__nvoc_ce_utils_h_disabled + +NV_STATUS ceutilsMemset_IMPL(struct CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams); + +#ifdef __nvoc_ce_utils_h_disabled +static inline NV_STATUS ceutilsMemset(struct CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsMemset(pCeUtils, pParams) ceutilsMemset_IMPL(pCeUtils, pParams) +#endif //__nvoc_ce_utils_h_disabled + +NV_STATUS ceutilsMemcopy_IMPL(struct CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams); + +#ifdef __nvoc_ce_utils_h_disabled +static inline NV_STATUS ceutilsMemcopy(struct CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsMemcopy(pCeUtils, pParams) ceutilsMemcopy_IMPL(pCeUtils, pParams) +#endif //__nvoc_ce_utils_h_disabled + +NvU64 ceutilsUpdateProgress_IMPL(struct CeUtils *pCeUtils); + +#ifdef __nvoc_ce_utils_h_disabled +static inline NvU64 ceutilsUpdateProgress(struct CeUtils *pCeUtils) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); + return 0; +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsUpdateProgress(pCeUtils) ceutilsUpdateProgress_IMPL(pCeUtils) +#endif //__nvoc_ce_utils_h_disabled + +void ceutilsServiceInterrupts_IMPL(struct CeUtils *pCeUtils); + +#ifdef __nvoc_ce_utils_h_disabled +static inline void ceutilsServiceInterrupts(struct CeUtils *pCeUtils) { + NV_ASSERT_FAILED_PRECOMP("CeUtils was disabled!"); +} +#else //__nvoc_ce_utils_h_disabled +#define ceutilsServiceInterrupts(pCeUtils) ceutilsServiceInterrupts_IMPL(pCeUtils) +#endif //__nvoc_ce_utils_h_disabled + +#undef PRIVATE_FIELD + + + +#if defined(DEBUG) || defined (DEVELOP) +NVOC_PREFIX(ceutilsapi) class CeUtilsApi : GpuResource +{ +public: + NV_STATUS ceutilsapiConstruct(CeUtilsApi *pCeUtilsApi, CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams) + : GpuResource(pCallContext, pParams); + + void ceutilsapiDestruct(CeUtilsApi *pCeUtilsApi); + + // + // Below APIs are only provided for SRT testing, thus only available for debug or + // develop driver builds + // + // + RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMSET, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdMemset(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams); + + RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMCOPY, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdMemcopy(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams); + + RMCTRL_EXPORT(NV0050_CTRL_CMD_CHECK_PROGRESS, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdCheckProgress(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams); + + CeUtils *pCeUtils; +}; +#endif + +#endif // CE_UTILS_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CE_UTILS_NVOC_H_ diff --git a/src/nvidia/generated/g_chips2halspec_nvoc.c b/src/nvidia/generated/g_chips2halspec_nvoc.c index 14461df74f..87adce7f78 100644 --- a/src/nvidia/generated/g_chips2halspec_nvoc.c +++ b/src/nvidia/generated/g_chips2halspec_nvoc.c @@ -125,7 +125,7 @@ void __nvoc_init_halspec_DispIpHal(DispIpHal *pDispIpHal, NvU32 ipver) // DISPv0000 else if(ipver == 0x0) { - pDispIpHal->__nvoc_HalVarIdx = 15; + pDispIpHal->__nvoc_HalVarIdx = 17; } } diff --git a/src/nvidia/generated/g_chipset_nvoc.h b/src/nvidia/generated/g_chipset_nvoc.h index 9ef3faa476..b712a21f64 100644 --- a/src/nvidia/generated/g_chipset_nvoc.h +++ b/src/nvidia/generated/g_chipset_nvoc.h @@ -114,6 +114,7 @@ struct PCIECONFIGSPACEBASE // PCI Express Link control ASPM capability Bits #define CL_PCIE_LINK_CAP_ASPM_L0S_BIT NVBIT(10) #define CL_PCIE_LINK_CAP_ASPM_L1_BIT NVBIT(11) +#define CL_PCIE_LINK_CAP_CLOCK_PM_BIT NVBIT(18) // PCI Express Slot Capabilities #define CL_PCIE_SLOT_CAP_HOTPLUG_SURPRISE NVBIT(5) @@ -1031,6 +1032,20 @@ static inline NvBool clIsL1MaskEnabledForUpstreamPort(struct OBJGPU *arg0, struc #define clIsL1MaskEnabledForUpstreamPort_HAL(arg0, arg1) clIsL1MaskEnabledForUpstreamPort(arg0, arg1) +NvBool clIsL0sMaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + + +#ifdef __nvoc_chipset_h_disabled +static inline NvBool clIsL0sMaskEnabledForUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); + return NV_FALSE; +} +#else //__nvoc_chipset_h_disabled +#define clIsL0sMaskEnabledForUpstreamPort(arg0, arg1) clIsL0sMaskEnabledForUpstreamPort_IMPL(arg0, arg1) +#endif //__nvoc_chipset_h_disabled + +#define clIsL0sMaskEnabledForUpstreamPort_HAL(arg0, arg1) clIsL0sMaskEnabledForUpstreamPort(arg0, arg1) + NV_STATUS clControlL0sL1LinkControlUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2); @@ -1087,6 +1102,20 @@ static inline NvU16 clPcieGetGpuLostDiagnosticData(struct OBJGPU *pGpu, struct O #define clPcieGetGpuLostDiagnosticData_HAL(pGpu, arg0, pBuffer, size) clPcieGetGpuLostDiagnosticData(pGpu, arg0, pBuffer, size) +NvU32 clGetChipsetL1ClockPMSupport_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + + +#ifdef __nvoc_chipset_h_disabled +static inline NvU32 clGetChipsetL1ClockPMSupport(struct OBJGPU *arg0, struct OBJCL *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); + return 0; +} +#else //__nvoc_chipset_h_disabled +#define clGetChipsetL1ClockPMSupport(arg0, arg1) clGetChipsetL1ClockPMSupport_IMPL(arg0, arg1) +#endif //__nvoc_chipset_h_disabled + +#define clGetChipsetL1ClockPMSupport_HAL(arg0, arg1) clGetChipsetL1ClockPMSupport(arg0, arg1) + NV_STATUS clConstruct_IMPL(struct OBJCL *arg_pCl); #define __nvoc_clConstruct(arg_pCl) clConstruct_IMPL(arg_pCl) diff --git a/src/nvidia/generated/g_client_resource_nvoc.c b/src/nvidia/generated/g_client_resource_nvoc.c index 7fe2e34143..87fbd21dd6 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.c +++ b/src/nvidia/generated/g_client_resource_nvoc.c @@ -308,6 +308,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x122u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsControl" +#endif + }, + { /* [8] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsBatchControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x123u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsBatchControl" +#endif + }, + { /* [9] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetHwbcInfo_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) @@ -320,7 +350,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetHwbcInfo" #endif }, - { /* [8] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -335,7 +365,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCaps" #endif }, - { /* [9] */ + { /* [11] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsCtrl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x12au, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsCtrl" +#endif + }, + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -350,7 +395,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCapsV2" #endif }, - { /* [10] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -365,7 +410,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetPerfSensorCounters" #endif }, - { /* [11] */ + { /* [14] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsCallAcpi_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x12du, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsCallAcpi" +#endif + }, + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -380,7 +440,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetExtendedPerfSensorCounters" #endif }, - { /* [12] */ + { /* [16] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsGetFrmData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x12fu, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsGetFrmData" +#endif + }, + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -395,7 +470,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemExecuteAcpiMethod" #endif }, - { /* [13] */ + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGpsSetFrmData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x132u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGpsSetFrmData" +#endif + }, + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -410,7 +500,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetGpusPowerStatus" #endif }, - { /* [14] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -425,7 +515,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetPrivilegedStatus" #endif }, - { /* [15] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -440,7 +530,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetFabricStatus" #endif }, - { /* [16] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -455,7 +545,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdVgpuGetVgpuVersion" #endif }, - { /* [17] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -470,7 +560,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdVgpuSetVgpuVersion" #endif }, - { /* [18] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -485,7 +575,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetRmInstanceId" #endif }, - { /* [19] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -500,7 +590,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCapsMatrix" #endif }, - { /* [20] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -515,7 +605,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemNVPCFGetPowerModeInfo" #endif }, - { /* [21] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -530,7 +620,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemSyncExternalFabricMgmt" #endif }, - { /* [22] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -545,7 +635,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetClientDatabaseInfo" #endif }, - { /* [23] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -560,7 +650,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetBuildVersionV2" #endif }, - { /* [24] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -575,7 +665,97 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemRmctrlCacheModeCtrl" #endif }, - { /* [25] */ + { /* [31] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x140u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrControl" +#endif + }, + { /* [32] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrBatchControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x141u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrBatchControl" +#endif + }, + { /* [33] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x142u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrCtrl" +#endif + }, + { /* [34] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrCallAcpi_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x143u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrCallAcpi" +#endif + }, + { /* [35] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrGetFrmData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x144u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetFrmData" +#endif + }, + { /* [36] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrSetFrmData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x145u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrSetFrmData" +#endif + }, + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -590,7 +770,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters" #endif }, - { /* [26] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -605,7 +785,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters" #endif }, - { /* [27] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -620,7 +800,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetFeatures" #endif }, - { /* [28] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -635,7 +815,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetAttachedIds" #endif }, - { /* [29] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -650,7 +830,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetIdInfo" #endif }, - { /* [30] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -665,7 +845,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetInitStatus" #endif }, - { /* [31] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -680,7 +860,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetDeviceIds" #endif }, - { /* [32] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -695,7 +875,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetIdInfoV2" #endif }, - { /* [33] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -710,7 +890,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetProbedIds" #endif }, - { /* [34] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -725,7 +905,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAttachIds" #endif }, - { /* [35] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -740,7 +920,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuDetachIds" #endif }, - { /* [36] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -755,7 +935,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetVideoLinks" #endif }, - { /* [37] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -770,7 +950,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetPciInfo" #endif }, - { /* [38] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -785,7 +965,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetSvmSize" #endif }, - { /* [39] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -800,7 +980,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetUuidInfo" #endif }, - { /* [40] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -815,7 +995,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetUuidFromGpuId" #endif }, - { /* [41] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -830,7 +1010,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuModifyGpuDrainState" #endif }, - { /* [42] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -845,7 +1025,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuQueryGpuDrainState" #endif }, - { /* [43] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -860,7 +1040,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetMemOpEnable" #endif }, - { /* [44] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -875,7 +1055,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuDisableNvlinkInit" #endif }, - { /* [45] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -890,7 +1070,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdLegacyConfig" #endif }, - { /* [46] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -905,7 +1085,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdIdleChannels" #endif }, - { /* [47] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -920,7 +1100,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdPushGspUcode" #endif }, - { /* [48] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -935,7 +1115,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuSetNvlinkBwMode" #endif }, - { /* [49] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -950,7 +1130,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetNvlinkBwMode" #endif }, - { /* [50] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -965,7 +1145,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetAttachedIds" #endif }, - { /* [51] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -980,7 +1160,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetIdInfo" #endif }, - { /* [52] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -995,7 +1175,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventSetNotification" #endif }, - { /* [53] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1010,7 +1190,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventGetSystemEventStatus" #endif }, - { /* [54] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1025,7 +1205,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDumpSize" #endif }, - { /* [55] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1040,7 +1220,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDump" #endif }, - { /* [56] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1055,7 +1235,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetTimestamp" #endif }, - { /* [57] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1070,7 +1250,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogInfo" #endif }, - { /* [58] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1085,7 +1265,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogBufferInfo" #endif }, - { /* [59] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1100,7 +1280,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlog" #endif }, - { /* [60] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1115,7 +1295,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetRcerrRpt" #endif }, - { /* [61] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1130,7 +1310,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSetSubProcessID" #endif }, - { /* [62] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1145,7 +1325,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdDisableSubProcessUserdIsolation" #endif }, - { /* [63] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1160,7 +1340,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostInfo" #endif }, - { /* [64] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1175,7 +1355,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupCreate" #endif }, - { /* [65] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1190,7 +1370,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupDestroy" #endif }, - { /* [66] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1205,7 +1385,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupInfo" #endif }, - { /* [67] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1220,7 +1400,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctSetAccountingState" #endif }, - { /* [68] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1235,7 +1415,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingState" #endif }, - { /* [69] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1250,7 +1430,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetProcAccountingInfo" #endif }, - { /* [70] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1265,7 +1445,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingPids" #endif }, - { /* [71] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1280,7 +1460,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctClearAccountingData" #endif }, - { /* [72] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1295,7 +1475,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdVgpuGetStartData" #endif }, - { /* [73] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1310,7 +1490,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAddrSpaceType" #endif }, - { /* [74] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1325,7 +1505,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetHandleInfo" #endif }, - { /* [75] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1340,7 +1520,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAccessRights" #endif }, - { /* [76] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1355,7 +1535,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientSetInheritedSharePolicy" #endif }, - { /* [77] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1370,7 +1550,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetChildHandle" #endif }, - { /* [78] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1385,7 +1565,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientShareObject" #endif }, - { /* [79] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1400,7 +1580,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdObjectsAreDuplicates" #endif }, - { /* [80] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1415,7 +1595,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixFlushUserCache" #endif }, - { /* [81] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1430,7 +1610,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectToFd" #endif }, - { /* [82] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1445,13 +1625,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixImportObjectFromFd" #endif }, - { /* [83] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [95] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdOsUnixGetExportObjectInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x3d08u, /*paramSize=*/ sizeof(NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS), @@ -1460,7 +1640,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixGetExportObjectInfo" #endif }, - { /* [84] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1475,7 +1655,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixCreateExportObjectFd" #endif }, - { /* [85] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1490,7 +1670,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectsToFd" #endif }, - { /* [86] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1510,7 +1690,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient const struct NVOC_EXPORT_INFO __nvoc_export_info_RmClientResource = { - /*numEntries=*/ 87, + /*numEntries=*/ 99, /*pExportEntries=*/ __nvoc_exported_method_def_RmClientResource }; @@ -1609,6 +1789,14 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemDebugCtrlRmMsg__ = &cliresCtrlCmdSystemDebugCtrlRmMsg_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsControl__ = &cliresCtrlCmdSystemGpsControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsBatchControl__ = &cliresCtrlCmdSystemGpsBatchControl_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdSystemGetHwbcInfo__ = &cliresCtrlCmdSystemGetHwbcInfo_IMPL; #endif @@ -1625,6 +1813,22 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetP2pCapsMatrix__ = &cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsCtrl__ = &cliresCtrlCmdSystemGpsCtrl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsGetFrmData__ = &cliresCtrlCmdSystemGpsGetFrmData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsSetFrmData__ = &cliresCtrlCmdSystemGpsSetFrmData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemGpsCallAcpi__ = &cliresCtrlCmdSystemGpsCallAcpi_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdSystemGetPerfSensorCounters__ = &cliresCtrlCmdSystemGetPerfSensorCounters_IMPL; #endif @@ -1825,7 +2029,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdOsUnixImportObjectFromFd__ = &cliresCtrlCmdOsUnixImportObjectFromFd_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdOsUnixGetExportObjectInfo__ = &cliresCtrlCmdOsUnixGetExportObjectInfo_IMPL; #endif @@ -1909,6 +2113,30 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemSyncExternalFabricMgmt__ = &cliresCtrlCmdSystemSyncExternalFabricMgmt_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrCtrl__ = &cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrGetFrmData__ = &cliresCtrlCmdSystemPfmreqhndlrGetFrmData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrSetFrmData__ = &cliresCtrlCmdSystemPfmreqhndlrSetFrmData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrCallAcpi__ = &cliresCtrlCmdSystemPfmreqhndlrCallAcpi_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrControl__ = &cliresCtrlCmdSystemPfmreqhndlrControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrBatchControl__ = &cliresCtrlCmdSystemPfmreqhndlrBatchControl_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters__ = &cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL; #endif diff --git a/src/nvidia/generated/g_client_resource_nvoc.h b/src/nvidia/generated/g_client_resource_nvoc.h index 13ac6c37b0..e53cfa0980 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.h +++ b/src/nvidia/generated/g_client_resource_nvoc.h @@ -88,10 +88,16 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdSystemNotifyEvent__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetPlatformType__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemDebugCtrlRmMsg__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsControl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsBatchControl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetHwbcInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetP2pCaps__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetP2pCapsV2__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetP2pCapsMatrix__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsCtrl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsGetFrmData__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsSetFrmData__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGpsCallAcpi__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetExtendedPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetGpusPowerStatus__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS *); @@ -163,6 +169,12 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdVgpuSetVgpuVersion__)(struct RmClientResource *, NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemSyncExternalFabricMgmt__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrCtrl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrGetFrmData__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrSetFrmData__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrCallAcpi__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrControl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrBatchControl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresControl__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -228,10 +240,16 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdSystemNotifyEvent(pRmCliRes, pParams) cliresCtrlCmdSystemNotifyEvent_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetPlatformType(pRmCliRes, pSysParams) cliresCtrlCmdSystemGetPlatformType_DISPATCH(pRmCliRes, pSysParams) #define cliresCtrlCmdSystemDebugCtrlRmMsg(pRmCliRes, pParams) cliresCtrlCmdSystemDebugCtrlRmMsg_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGpsControl(pRmCliRes, controlParams) cliresCtrlCmdSystemGpsControl_DISPATCH(pRmCliRes, controlParams) +#define cliresCtrlCmdSystemGpsBatchControl(pRmCliRes, controlParams) cliresCtrlCmdSystemGpsBatchControl_DISPATCH(pRmCliRes, controlParams) #define cliresCtrlCmdSystemGetHwbcInfo(pRmCliRes, pParams) cliresCtrlCmdSystemGetHwbcInfo_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetP2pCaps(pRmCliRes, pP2PParams) cliresCtrlCmdSystemGetP2pCaps_DISPATCH(pRmCliRes, pP2PParams) #define cliresCtrlCmdSystemGetP2pCapsV2(pRmCliRes, pP2PParams) cliresCtrlCmdSystemGetP2pCapsV2_DISPATCH(pRmCliRes, pP2PParams) #define cliresCtrlCmdSystemGetP2pCapsMatrix(pRmCliRes, pP2PParams) cliresCtrlCmdSystemGetP2pCapsMatrix_DISPATCH(pRmCliRes, pP2PParams) +#define cliresCtrlCmdSystemGpsCtrl(pRmCliRes, pParams) cliresCtrlCmdSystemGpsCtrl_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGpsGetFrmData(pRmCliRes, pParams) cliresCtrlCmdSystemGpsGetFrmData_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGpsSetFrmData(pRmCliRes, pParams) cliresCtrlCmdSystemGpsSetFrmData_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGpsCallAcpi(pRmCliRes, pParams) cliresCtrlCmdSystemGpsCallAcpi_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemGetPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetExtendedPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemGetExtendedPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetGpusPowerStatus(pRmCliRes, pGpusPowerStatus) cliresCtrlCmdSystemGetGpusPowerStatus_DISPATCH(pRmCliRes, pGpusPowerStatus) @@ -303,6 +321,12 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdVgpuSetVgpuVersion(pRmCliRes, vgpuVersionInfo) cliresCtrlCmdVgpuSetVgpuVersion_DISPATCH(pRmCliRes, vgpuVersionInfo) #define cliresCtrlCmdSystemNVPCFGetPowerModeInfo(pRmCliRes, pParams) cliresCtrlCmdSystemNVPCFGetPowerModeInfo_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemSyncExternalFabricMgmt(pRmCliRes, pExtFabricMgmtParams) cliresCtrlCmdSystemSyncExternalFabricMgmt_DISPATCH(pRmCliRes, pExtFabricMgmtParams) +#define cliresCtrlCmdSystemPfmreqhndlrCtrl(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrCtrl_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrGetFrmData(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrGetFrmData_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrSetFrmData(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrSetFrmData_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrCallAcpi(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrCallAcpi_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrControl(pRmCliRes, controlParams) cliresCtrlCmdSystemPfmreqhndlrControl_DISPATCH(pRmCliRes, controlParams) +#define cliresCtrlCmdSystemPfmreqhndlrBatchControl(pRmCliRes, controlParams) cliresCtrlCmdSystemPfmreqhndlrBatchControl_DISPATCH(pRmCliRes, controlParams) #define cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresControl(pResource, pCallContext, pParams) cliresControl_DISPATCH(pResource, pCallContext, pParams) @@ -408,6 +432,18 @@ static inline NV_STATUS cliresCtrlCmdSystemDebugCtrlRmMsg_DISPATCH(struct RmClie return pRmCliRes->__cliresCtrlCmdSystemDebugCtrlRmMsg__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdSystemGpsControl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS *controlParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsControl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS *controlParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsControl__(pRmCliRes, controlParams); +} + +NV_STATUS cliresCtrlCmdSystemGpsBatchControl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS *controlParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsBatchControl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS *controlParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsBatchControl__(pRmCliRes, controlParams); +} + NV_STATUS cliresCtrlCmdSystemGetHwbcInfo_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdSystemGetHwbcInfo_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS *pParams) { @@ -432,6 +468,30 @@ static inline NV_STATUS cliresCtrlCmdSystemGetP2pCapsMatrix_DISPATCH(struct RmCl return pRmCliRes->__cliresCtrlCmdSystemGetP2pCapsMatrix__(pRmCliRes, pP2PParams); } +NV_STATUS cliresCtrlCmdSystemGpsCtrl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsCtrl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsCtrl__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemGpsGetFrmData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsGetFrmData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsGetFrmData__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemGpsSetFrmData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsSetFrmData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsSetFrmData__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemGpsCallAcpi_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGpsCallAcpi_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGpsCallAcpi__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdSystemGetPerfSensorCounters_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdSystemGetPerfSensorCounters_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams) { @@ -858,6 +918,42 @@ static inline NV_STATUS cliresCtrlCmdSystemSyncExternalFabricMgmt_DISPATCH(struc return pRmCliRes->__cliresCtrlCmdSystemSyncExternalFabricMgmt__(pRmCliRes, pExtFabricMgmtParams); } +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrCtrl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrCtrl__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetFrmData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetFrmData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrGetFrmData__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrSetFrmData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrSetFrmData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrSetFrmData__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrCallAcpi_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrCallAcpi_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrCallAcpi__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrControl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *controlParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrControl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *controlParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrControl__(pRmCliRes, controlParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrBatchControl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS *controlParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrBatchControl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS *controlParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrBatchControl__(pRmCliRes, controlParams); +} + NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams) { diff --git a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h index 67baf2ed14..652f757d49 100644 --- a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -90,8 +90,8 @@ struct ComputeInstanceSubscription { void (*__cisubscriptionControlSerialization_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionMap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__cisubscriptionAccessCallback__)(struct ComputeInstanceSubscription *, struct RsClient *, void *, RsAccessRight); - MIG_COMPUTE_INSTANCE *pMIGComputeInstance; - NvU64 dupedCapDescriptor; + MIG_COMPUTE_INSTANCE *PRIVATE_FIELD(pMIGComputeInstance); + NvU64 PRIVATE_FIELD(dupedCapDescriptor); }; #ifndef __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ diff --git a/src/nvidia/generated/g_conf_compute_api_nvoc.c b/src/nvidia/generated/g_conf_compute_api_nvoc.c new file mode 100644 index 0000000000..fabcbd929e --- /dev/null +++ b/src/nvidia/generated/g_conf_compute_api_nvoc.c @@ -0,0 +1,482 @@ +#define NVOC_CONF_COMPUTE_API_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_conf_compute_api_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xea5cb0 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialComputeApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +void __nvoc_init_ConfidentialComputeApi(ConfidentialComputeApi*); +void __nvoc_init_funcTable_ConfidentialComputeApi(ConfidentialComputeApi*); +NV_STATUS __nvoc_ctor_ConfidentialComputeApi(ConfidentialComputeApi*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_ConfidentialComputeApi(ConfidentialComputeApi*); +void __nvoc_dtor_ConfidentialComputeApi(ConfidentialComputeApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialComputeApi; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_ConfidentialComputeApi = { + /*pClassDef=*/ &__nvoc_class_def_ConfidentialComputeApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_ConfidentialComputeApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialComputeApi, __nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialComputeApi, __nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialComputeApi, __nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialComputeApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialComputeApi, __nvoc_base_RmResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_ConfidentialComputeApi = { + /*numRelatives=*/ 5, + /*relatives=*/ { + &__nvoc_rtti_ConfidentialComputeApi_ConfidentialComputeApi, + &__nvoc_rtti_ConfidentialComputeApi_RmResource, + &__nvoc_rtti_ConfidentialComputeApi_RmResourceCommon, + &__nvoc_rtti_ConfidentialComputeApi_RsResource, + &__nvoc_rtti_ConfidentialComputeApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialComputeApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(ConfidentialComputeApi), + /*classId=*/ classId(ConfidentialComputeApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "ConfidentialComputeApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_ConfidentialComputeApi, + /*pCastInfo=*/ &__nvoc_castinfo_ConfidentialComputeApi, + /*pExportInfo=*/ &__nvoc_export_info_ConfidentialComputeApi +}; + +static NvBool __nvoc_thunk_RmResource_confComputeApiShareCallback(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiCheckMemInterUnmap(struct ConfidentialComputeApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiControl(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiGetMemInterMapParams(struct ConfidentialComputeApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiGetMemoryMappingDescriptor(struct ConfidentialComputeApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), ppMemDesc); +} + +static NvU32 __nvoc_thunk_RsResource_confComputeApiGetRefCount(struct ConfidentialComputeApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiControlFilter(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_confComputeApiAddAdditionalDependants(struct RsClient *pClient, struct ConfidentialComputeApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiUnmapFrom(struct ConfidentialComputeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiControlSerialization_Prologue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_confComputeApiControl_Prologue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_confComputeApiCanCopy(struct ConfidentialComputeApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiUnmap(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pCpuMapping); +} + +static void __nvoc_thunk_RsResource_confComputeApiPreDestruct(struct ConfidentialComputeApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiMapTo(struct ConfidentialComputeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiIsDuplicate(struct ConfidentialComputeApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_confComputeApiControlSerialization_Epilogue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmResource_confComputeApiControl_Epilogue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiControlLookup(struct ConfidentialComputeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiMap(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_confComputeApiAccessCallback(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_ConfidentialComputeApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdSystemGetCapabilities_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330101u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdSystemGetCapabilities" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdSystemGetGpusState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330104u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdSystemGetGpusState" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdSystemSetGpusState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330105u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdSystemSetGpusState" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGpuGetVidmemSize_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330106u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGpuGetVidmemSize" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGpuSetVidmemSize_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330107u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGpuSetVidmemSize" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGetGpuCertificate_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb330109u, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGetGpuCertificate" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGetGpuAttestationReport_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb33010au, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGetGpuAttestationReport" +#endif + }, + { /* [7] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcb33010bu, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdGpuGetNumSecureChannels" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialComputeApi = +{ + /*numEntries=*/ 8, + /*pExportEntries=*/ __nvoc_exported_method_def_ConfidentialComputeApi +}; + +void __nvoc_dtor_RmResource(RmResource*); +void __nvoc_dtor_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { + __nvoc_confComputeApiDestruct(pThis); + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RmResource(RmResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_ConfidentialComputeApi(ConfidentialComputeApi *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_RmResource(&pThis->__nvoc_base_RmResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ConfidentialComputeApi_fail_RmResource; + __nvoc_init_dataField_ConfidentialComputeApi(pThis); + + status = __nvoc_confComputeApiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ConfidentialComputeApi_fail__init; + goto __nvoc_ctor_ConfidentialComputeApi_exit; // Success + +__nvoc_ctor_ConfidentialComputeApi_fail__init: + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); +__nvoc_ctor_ConfidentialComputeApi_fail_RmResource: +__nvoc_ctor_ConfidentialComputeApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_ConfidentialComputeApi_1(ConfidentialComputeApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdSystemGetCapabilities__ = &confComputeApiCtrlCmdSystemGetCapabilities_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdSystemGetGpusState__ = &confComputeApiCtrlCmdSystemGetGpusState_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__confComputeApiCtrlCmdSystemSetGpusState__ = &confComputeApiCtrlCmdSystemSetGpusState_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdGpuGetVidmemSize__ = &confComputeApiCtrlCmdGpuGetVidmemSize_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__confComputeApiCtrlCmdGpuSetVidmemSize__ = &confComputeApiCtrlCmdGpuSetVidmemSize_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdGetGpuCertificate__ = &confComputeApiCtrlCmdGetGpuCertificate_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdGetGpuAttestationReport__ = &confComputeApiCtrlCmdGetGpuAttestationReport_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdGpuGetNumSecureChannels__ = &confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL; +#endif + + pThis->__confComputeApiShareCallback__ = &__nvoc_thunk_RmResource_confComputeApiShareCallback; + + pThis->__confComputeApiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_confComputeApiCheckMemInterUnmap; + + pThis->__confComputeApiControl__ = &__nvoc_thunk_RsResource_confComputeApiControl; + + pThis->__confComputeApiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_confComputeApiGetMemInterMapParams; + + pThis->__confComputeApiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_confComputeApiGetMemoryMappingDescriptor; + + pThis->__confComputeApiGetRefCount__ = &__nvoc_thunk_RsResource_confComputeApiGetRefCount; + + pThis->__confComputeApiControlFilter__ = &__nvoc_thunk_RsResource_confComputeApiControlFilter; + + pThis->__confComputeApiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_confComputeApiAddAdditionalDependants; + + pThis->__confComputeApiUnmapFrom__ = &__nvoc_thunk_RsResource_confComputeApiUnmapFrom; + + pThis->__confComputeApiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_confComputeApiControlSerialization_Prologue; + + pThis->__confComputeApiControl_Prologue__ = &__nvoc_thunk_RmResource_confComputeApiControl_Prologue; + + pThis->__confComputeApiCanCopy__ = &__nvoc_thunk_RsResource_confComputeApiCanCopy; + + pThis->__confComputeApiUnmap__ = &__nvoc_thunk_RsResource_confComputeApiUnmap; + + pThis->__confComputeApiPreDestruct__ = &__nvoc_thunk_RsResource_confComputeApiPreDestruct; + + pThis->__confComputeApiMapTo__ = &__nvoc_thunk_RsResource_confComputeApiMapTo; + + pThis->__confComputeApiIsDuplicate__ = &__nvoc_thunk_RsResource_confComputeApiIsDuplicate; + + pThis->__confComputeApiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_confComputeApiControlSerialization_Epilogue; + + pThis->__confComputeApiControl_Epilogue__ = &__nvoc_thunk_RmResource_confComputeApiControl_Epilogue; + + pThis->__confComputeApiControlLookup__ = &__nvoc_thunk_RsResource_confComputeApiControlLookup; + + pThis->__confComputeApiMap__ = &__nvoc_thunk_RsResource_confComputeApiMap; + + pThis->__confComputeApiAccessCallback__ = &__nvoc_thunk_RmResource_confComputeApiAccessCallback; +} + +void __nvoc_init_funcTable_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { + __nvoc_init_funcTable_ConfidentialComputeApi_1(pThis); +} + +void __nvoc_init_RmResource(RmResource*); +void __nvoc_init_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { + pThis->__nvoc_pbase_ConfidentialComputeApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_RmResource; + __nvoc_init_RmResource(&pThis->__nvoc_base_RmResource); + __nvoc_init_funcTable_ConfidentialComputeApi(pThis); +} + +NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + ConfidentialComputeApi *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConfidentialComputeApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(ConfidentialComputeApi)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConfidentialComputeApi); + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_ConfidentialComputeApi(pThis); + status = __nvoc_ctor_ConfidentialComputeApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_ConfidentialComputeApi_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_ConfidentialComputeApi_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ConfidentialComputeApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_ConfidentialComputeApi(ConfidentialComputeApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_ConfidentialComputeApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_conf_compute_api_nvoc.h b/src/nvidia/generated/g_conf_compute_api_nvoc.h new file mode 100644 index 0000000000..8268bd3bc8 --- /dev/null +++ b/src/nvidia/generated/g_conf_compute_api_nvoc.h @@ -0,0 +1,297 @@ +#ifndef _G_CONF_COMPUTE_API_NVOC_H_ +#define _G_CONF_COMPUTE_API_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_conf_compute_api_nvoc.h" + +#ifndef CONF_COMPUTE_API_H +#define CONF_COMPUTE_API_H + +#include "gpu/gpu.h" +#include "rmapi/resource.h" +#include "ctrl/ctrlcb33.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu/conf_compute/conf_compute.h" + + +/****************************************************************************\ + * * + * Confidential Compute module header. * + * * + ****************************************************************************/ + +#ifdef NVOC_CONF_COMPUTE_API_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct ConfidentialComputeApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct RmResource __nvoc_base_RmResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct ConfidentialComputeApi *__nvoc_pbase_ConfidentialComputeApi; + NV_STATUS (*__confComputeApiCtrlCmdSystemGetCapabilities__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdSystemGetGpusState__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdSystemSetGpusState__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGpuGetVidmemSize__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGpuSetVidmemSize__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGetGpuCertificate__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGetGpuAttestationReport__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdGpuGetNumSecureChannels__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *); + NvBool (*__confComputeApiShareCallback__)(struct ConfidentialComputeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__confComputeApiCheckMemInterUnmap__)(struct ConfidentialComputeApi *, NvBool); + NV_STATUS (*__confComputeApiControl__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__confComputeApiGetMemInterMapParams__)(struct ConfidentialComputeApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__confComputeApiGetMemoryMappingDescriptor__)(struct ConfidentialComputeApi *, struct MEMORY_DESCRIPTOR **); + NvU32 (*__confComputeApiGetRefCount__)(struct ConfidentialComputeApi *); + NV_STATUS (*__confComputeApiControlFilter__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__confComputeApiAddAdditionalDependants__)(struct RsClient *, struct ConfidentialComputeApi *, RsResourceRef *); + NV_STATUS (*__confComputeApiUnmapFrom__)(struct ConfidentialComputeApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__confComputeApiControlSerialization_Prologue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__confComputeApiControl_Prologue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__confComputeApiCanCopy__)(struct ConfidentialComputeApi *); + NV_STATUS (*__confComputeApiUnmap__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, RsCpuMapping *); + void (*__confComputeApiPreDestruct__)(struct ConfidentialComputeApi *); + NV_STATUS (*__confComputeApiMapTo__)(struct ConfidentialComputeApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__confComputeApiIsDuplicate__)(struct ConfidentialComputeApi *, NvHandle, NvBool *); + void (*__confComputeApiControlSerialization_Epilogue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__confComputeApiControl_Epilogue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__confComputeApiControlLookup__)(struct ConfidentialComputeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__confComputeApiMap__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__confComputeApiAccessCallback__)(struct ConfidentialComputeApi *, struct RsClient *, void *, RsAccessRight); + struct CONF_COMPUTE_CAPS *pCcCaps; +}; + +#ifndef __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ +#define __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ +typedef struct ConfidentialComputeApi ConfidentialComputeApi; +#endif /* __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConfidentialComputeApi +#define __nvoc_class_id_ConfidentialComputeApi 0xea5cb0 +#endif /* __nvoc_class_id_ConfidentialComputeApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialComputeApi; + +#define __staticCast_ConfidentialComputeApi(pThis) \ + ((pThis)->__nvoc_pbase_ConfidentialComputeApi) + +#ifdef __nvoc_conf_compute_api_h_disabled +#define __dynamicCast_ConfidentialComputeApi(pThis) ((ConfidentialComputeApi*)NULL) +#else //__nvoc_conf_compute_api_h_disabled +#define __dynamicCast_ConfidentialComputeApi(pThis) \ + ((ConfidentialComputeApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ConfidentialComputeApi))) +#endif //__nvoc_conf_compute_api_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_ConfidentialComputeApi(ConfidentialComputeApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_ConfidentialComputeApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_ConfidentialComputeApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define confComputeApiCtrlCmdSystemGetCapabilities(pConfComputeApi, pParams) confComputeApiCtrlCmdSystemGetCapabilities_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdSystemGetGpusState(pConfComputeApi, pParams) confComputeApiCtrlCmdSystemGetGpusState_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdSystemSetGpusState(pConfComputeApi, pParams) confComputeApiCtrlCmdSystemSetGpusState_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGpuGetVidmemSize(pConfComputeApi, pParams) confComputeApiCtrlCmdGpuGetVidmemSize_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGpuSetVidmemSize(pConfComputeApi, pParams) confComputeApiCtrlCmdGpuSetVidmemSize_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGetGpuCertificate(pConfComputeApi, pParams) confComputeApiCtrlCmdGetGpuCertificate_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGetGpuAttestationReport(pConfComputeApi, pParams) confComputeApiCtrlCmdGetGpuAttestationReport_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdGpuGetNumSecureChannels(pConfComputeApi, pParams) confComputeApiCtrlCmdGpuGetNumSecureChannels_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) confComputeApiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define confComputeApiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) confComputeApiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define confComputeApiControl(pResource, pCallContext, pParams) confComputeApiControl_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiGetMemInterMapParams(pRmResource, pParams) confComputeApiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define confComputeApiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) confComputeApiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define confComputeApiGetRefCount(pResource) confComputeApiGetRefCount_DISPATCH(pResource) +#define confComputeApiControlFilter(pResource, pCallContext, pParams) confComputeApiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiAddAdditionalDependants(pClient, pResource, pReference) confComputeApiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define confComputeApiUnmapFrom(pResource, pParams) confComputeApiUnmapFrom_DISPATCH(pResource, pParams) +#define confComputeApiControlSerialization_Prologue(pResource, pCallContext, pParams) confComputeApiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiControl_Prologue(pResource, pCallContext, pParams) confComputeApiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiCanCopy(pResource) confComputeApiCanCopy_DISPATCH(pResource) +#define confComputeApiUnmap(pResource, pCallContext, pCpuMapping) confComputeApiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define confComputeApiPreDestruct(pResource) confComputeApiPreDestruct_DISPATCH(pResource) +#define confComputeApiMapTo(pResource, pParams) confComputeApiMapTo_DISPATCH(pResource, pParams) +#define confComputeApiIsDuplicate(pResource, hMemory, pDuplicate) confComputeApiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define confComputeApiControlSerialization_Epilogue(pResource, pCallContext, pParams) confComputeApiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiControl_Epilogue(pResource, pCallContext, pParams) confComputeApiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define confComputeApiControlLookup(pResource, pParams, ppEntry) confComputeApiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define confComputeApiMap(pResource, pCallContext, pParams, pCpuMapping) confComputeApiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) +#define confComputeApiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) confComputeApiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS confComputeApiCtrlCmdSystemGetCapabilities_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdSystemGetCapabilities_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdSystemGetCapabilities__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdSystemGetGpusState_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdSystemGetGpusState_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdSystemGetGpusState__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdSystemSetGpusState_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdSystemSetGpusState_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdSystemSetGpusState__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGpuGetVidmemSize_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGpuGetVidmemSize_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGpuGetVidmemSize__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGpuSetVidmemSize_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGpuSetVidmemSize_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGpuSetVidmemSize__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGetGpuCertificate_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGetGpuCertificate_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGetGpuCertificate__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGetGpuAttestationReport_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGetGpuAttestationReport_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGetGpuAttestationReport__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdGpuGetNumSecureChannels_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdGpuGetNumSecureChannels__(pConfComputeApi, pParams); +} + +static inline NvBool confComputeApiShareCallback_DISPATCH(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__confComputeApiShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS confComputeApiCheckMemInterUnmap_DISPATCH(struct ConfidentialComputeApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__confComputeApiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS confComputeApiControl_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__confComputeApiControl__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS confComputeApiGetMemInterMapParams_DISPATCH(struct ConfidentialComputeApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__confComputeApiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS confComputeApiGetMemoryMappingDescriptor_DISPATCH(struct ConfidentialComputeApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__confComputeApiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NvU32 confComputeApiGetRefCount_DISPATCH(struct ConfidentialComputeApi *pResource) { + return pResource->__confComputeApiGetRefCount__(pResource); +} + +static inline NV_STATUS confComputeApiControlFilter_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__confComputeApiControlFilter__(pResource, pCallContext, pParams); +} + +static inline void confComputeApiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ConfidentialComputeApi *pResource, RsResourceRef *pReference) { + pResource->__confComputeApiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS confComputeApiUnmapFrom_DISPATCH(struct ConfidentialComputeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__confComputeApiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS confComputeApiControlSerialization_Prologue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__confComputeApiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS confComputeApiControl_Prologue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__confComputeApiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool confComputeApiCanCopy_DISPATCH(struct ConfidentialComputeApi *pResource) { + return pResource->__confComputeApiCanCopy__(pResource); +} + +static inline NV_STATUS confComputeApiUnmap_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__confComputeApiUnmap__(pResource, pCallContext, pCpuMapping); +} + +static inline void confComputeApiPreDestruct_DISPATCH(struct ConfidentialComputeApi *pResource) { + pResource->__confComputeApiPreDestruct__(pResource); +} + +static inline NV_STATUS confComputeApiMapTo_DISPATCH(struct ConfidentialComputeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__confComputeApiMapTo__(pResource, pParams); +} + +static inline NV_STATUS confComputeApiIsDuplicate_DISPATCH(struct ConfidentialComputeApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__confComputeApiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void confComputeApiControlSerialization_Epilogue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__confComputeApiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline void confComputeApiControl_Epilogue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__confComputeApiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS confComputeApiControlLookup_DISPATCH(struct ConfidentialComputeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__confComputeApiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS confComputeApiMap_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pResource->__confComputeApiMap__(pResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool confComputeApiAccessCallback_DISPATCH(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__confComputeApiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS confComputeApiConstruct_IMPL(struct ConfidentialComputeApi *arg_pConfComputeApi, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_confComputeApiConstruct(arg_pConfComputeApi, arg_pCallContext, arg_pParams) confComputeApiConstruct_IMPL(arg_pConfComputeApi, arg_pCallContext, arg_pParams) +void confComputeApiDestruct_IMPL(struct ConfidentialComputeApi *pConfComputeApi); + +#define __nvoc_confComputeApiDestruct(pConfComputeApi) confComputeApiDestruct_IMPL(pConfComputeApi) +#undef PRIVATE_FIELD + +#endif // CONF_COMPUTE_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CONF_COMPUTE_API_NVOC_H_ diff --git a/src/nvidia/generated/g_conf_compute_nvoc.c b/src/nvidia/generated/g_conf_compute_nvoc.c new file mode 100644 index 0000000000..8b58563df9 --- /dev/null +++ b/src/nvidia/generated/g_conf_compute_nvoc.c @@ -0,0 +1,434 @@ +#define NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_conf_compute_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x9798cc = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialCompute; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; + +void __nvoc_init_ConfidentialCompute(ConfidentialCompute*, RmHalspecOwner* ); +void __nvoc_init_funcTable_ConfidentialCompute(ConfidentialCompute*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_ConfidentialCompute(ConfidentialCompute*, RmHalspecOwner* ); +void __nvoc_init_dataField_ConfidentialCompute(ConfidentialCompute*, RmHalspecOwner* ); +void __nvoc_dtor_ConfidentialCompute(ConfidentialCompute*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialCompute; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialCompute_ConfidentialCompute = { + /*pClassDef=*/ &__nvoc_class_def_ConfidentialCompute, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_ConfidentialCompute, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialCompute_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialCompute, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ConfidentialCompute_OBJENGSTATE = { + /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ConfidentialCompute, __nvoc_base_OBJENGSTATE), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_ConfidentialCompute = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_ConfidentialCompute_ConfidentialCompute, + &__nvoc_rtti_ConfidentialCompute_OBJENGSTATE, + &__nvoc_rtti_ConfidentialCompute_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialCompute = +{ + /*classInfo=*/ { + /*size=*/ sizeof(ConfidentialCompute), + /*classId=*/ classId(ConfidentialCompute), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "ConfidentialCompute", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_ConfidentialCompute, + /*pCastInfo=*/ &__nvoc_castinfo_ConfidentialCompute, + /*pExportInfo=*/ &__nvoc_export_info_ConfidentialCompute +}; + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateConstructEngine(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute, ENGDESCRIPTOR engDesc) { + return confComputeConstructEngine(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), engDesc); +} + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStateInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute) { + return confComputeStateInitLocked(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStatePostLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute, NvU32 flags) { + return confComputeStatePostLoad(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), flags); +} + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStatePreInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute) { + return confComputeStatePreInitLocked(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStatePreUnload(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute, NvU32 flags) { + return confComputeStatePreUnload(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), flags); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStateLoad(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStateUnload(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStatePreLoad(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStatePostUnload(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); +} + +static void __nvoc_thunk_OBJENGSTATE_confComputeStateDestroy(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStateInitUnlocked(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static void __nvoc_thunk_OBJENGSTATE_confComputeInitMissing(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStatePreInitUnlocked(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +static NvBool __nvoc_thunk_OBJENGSTATE_confComputeIsPresent(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialCompute = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_dtor_ConfidentialCompute(ConfidentialCompute *pThis) { + __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, ((NvBool)(0 != 0))); +} + +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + if (status != NV_OK) goto __nvoc_ctor_ConfidentialCompute_fail_OBJENGSTATE; + __nvoc_init_dataField_ConfidentialCompute(pThis, pRmhalspecowner); + goto __nvoc_ctor_ConfidentialCompute_exit; // Success + +__nvoc_ctor_ConfidentialCompute_fail_OBJENGSTATE: +__nvoc_ctor_ConfidentialCompute_exit: + + return status; +} + +static void __nvoc_init_funcTable_ConfidentialCompute_1(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + pThis->__confComputeConstructEngine__ = &confComputeConstructEngine_IMPL; + + pThis->__confComputeStateInitLocked__ = &confComputeStateInitLocked_IMPL; + + pThis->__confComputeStatePostLoad__ = &confComputeStatePostLoad_IMPL; + + pThis->__confComputeStatePreInitLocked__ = &confComputeStatePreInitLocked_IMPL; + + pThis->__confComputeStatePreUnload__ = &confComputeStatePreUnload_IMPL; + + // Hal function -- confComputeKeyStoreRetrieveViaChannel + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreRetrieveViaChannel__ = &confComputeKeyStoreRetrieveViaChannel_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreRetrieveViaChannel__ = &confComputeKeyStoreRetrieveViaChannel_46f6a7; + } + + // Hal function -- confComputeKeyStoreRetrieveViaKeyId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreRetrieveViaKeyId__ = &confComputeKeyStoreRetrieveViaKeyId_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreRetrieveViaKeyId__ = &confComputeKeyStoreRetrieveViaKeyId_46f6a7; + } + + // Hal function -- confComputeDeriveSecrets + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeDeriveSecrets__ = &confComputeDeriveSecrets_GH100; + } + // default + else + { + pThis->__confComputeDeriveSecrets__ = &confComputeDeriveSecrets_46f6a7; + } + + // Hal function -- confComputeIsSpdmEnabled + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeIsSpdmEnabled__ = &confComputeIsSpdmEnabled_cbe027; + } + // default + else + { + pThis->__confComputeIsSpdmEnabled__ = &confComputeIsSpdmEnabled_491d52; + } + + // Hal function -- confComputeIsDebugModeEnabled + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeIsDebugModeEnabled__ = &confComputeIsDebugModeEnabled_GH100; + } + // default + else + { + pThis->__confComputeIsDebugModeEnabled__ = &confComputeIsDebugModeEnabled_491d52; + } + + // Hal function -- confComputeIsGpuCcCapable + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeIsGpuCcCapable__ = &confComputeIsGpuCcCapable_GH100; + } + // default + else + { + pThis->__confComputeIsGpuCcCapable__ = &confComputeIsGpuCcCapable_491d52; + } + + // Hal function -- confComputeKeyStoreInit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreInit__ = &confComputeKeyStoreInit_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreInit__ = &confComputeKeyStoreInit_46f6a7; + } + + // Hal function -- confComputeKeyStoreDeinit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreDeinit__ = &confComputeKeyStoreDeinit_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreDeinit__ = &confComputeKeyStoreDeinit_b3696a; + } + + // Hal function -- confComputeKeyStoreGetExportMasterKey + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreGetExportMasterKey__ = &confComputeKeyStoreGetExportMasterKey_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreGetExportMasterKey__ = &confComputeKeyStoreGetExportMasterKey_fa6e19; + } + + // Hal function -- confComputeKeyStoreDeriveKey + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreDeriveKey__ = &confComputeKeyStoreDeriveKey_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreDeriveKey__ = &confComputeKeyStoreDeriveKey_46f6a7; + } + + // Hal function -- confComputeKeyStoreDepositIvMask + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreDepositIvMask__ = &confComputeKeyStoreDepositIvMask_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreDepositIvMask__ = &confComputeKeyStoreDepositIvMask_b3696a; + } + + // Hal function -- confComputeKeyStoreClearExportMasterKey + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreClearExportMasterKey__ = &confComputeKeyStoreClearExportMasterKey_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreClearExportMasterKey__ = &confComputeKeyStoreClearExportMasterKey_b3696a; + } + + // Hal function -- confComputeKeyStoreUpdateKey + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__confComputeKeyStoreUpdateKey__ = &confComputeKeyStoreUpdateKey_GH100; + } + // default + else + { + pThis->__confComputeKeyStoreUpdateKey__ = &confComputeKeyStoreUpdateKey_46f6a7; + } + + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_ConfidentialCompute_engstateConstructEngine; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_ConfidentialCompute_engstateStateInitLocked; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_ConfidentialCompute_engstateStatePostLoad; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_ConfidentialCompute_engstateStatePreInitLocked; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_ConfidentialCompute_engstateStatePreUnload; + + pThis->__confComputeStateLoad__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateLoad; + + pThis->__confComputeStateUnload__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateUnload; + + pThis->__confComputeStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_confComputeStatePreLoad; + + pThis->__confComputeStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_confComputeStatePostUnload; + + pThis->__confComputeStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateDestroy; + + pThis->__confComputeStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateInitUnlocked; + + pThis->__confComputeInitMissing__ = &__nvoc_thunk_OBJENGSTATE_confComputeInitMissing; + + pThis->__confComputeStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_confComputeStatePreInitUnlocked; + + pThis->__confComputeIsPresent__ = &__nvoc_thunk_OBJENGSTATE_confComputeIsPresent; +} + +void __nvoc_init_funcTable_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_ConfidentialCompute_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_ConfidentialCompute = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; + pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_funcTable_ConfidentialCompute(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + ConfidentialCompute *pThis; + RmHalspecOwner *pRmhalspecowner; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConfidentialCompute), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(ConfidentialCompute)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConfidentialCompute); + + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_ConfidentialCompute(pThis, pRmhalspecowner); + status = __nvoc_ctor_ConfidentialCompute(pThis, pRmhalspecowner); + if (status != NV_OK) goto __nvoc_objCreate_ConfidentialCompute_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_ConfidentialCompute_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ConfidentialCompute)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_ConfidentialCompute(ConfidentialCompute **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_ConfidentialCompute(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_conf_compute_nvoc.h b/src/nvidia/generated/g_conf_compute_nvoc.h new file mode 100644 index 0000000000..c84cb72057 --- /dev/null +++ b/src/nvidia/generated/g_conf_compute_nvoc.h @@ -0,0 +1,481 @@ +#ifndef _G_CONF_COMPUTE_NVOC_H_ +#define _G_CONF_COMPUTE_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_conf_compute_nvoc.h" + +#ifndef CONF_COMPUTE_H +#define CONF_COMPUTE_H + +#include "gpu/gpu.h" +#include "gpu/eng_state.h" +#include "gpu/spdm/spdm.h" +#include "ctrl/ctrl2080/ctrl2080spdm.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" +#include "cc_drv.h" +#include "conf_compute/cc_keystore.h" +#include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/gpu/intr/engine_idx.h" + +/****************************************************************************\ + * * + * Confidential Compute module header. * + * * + ****************************************************************************/ + +#ifdef NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct ConfidentialCompute { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct ConfidentialCompute *__nvoc_pbase_ConfidentialCompute; + NV_STATUS (*__confComputeConstructEngine__)(struct OBJGPU *, struct ConfidentialCompute *, ENGDESCRIPTOR); + NV_STATUS (*__confComputeStateInitLocked__)(struct OBJGPU *, struct ConfidentialCompute *); + NV_STATUS (*__confComputeStatePostLoad__)(struct OBJGPU *, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStatePreInitLocked__)(struct OBJGPU *, struct ConfidentialCompute *); + NV_STATUS (*__confComputeStatePreUnload__)(struct OBJGPU *, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeKeyStoreRetrieveViaChannel__)(struct ConfidentialCompute *, struct KernelChannel *, ROTATE_IV_TYPE, NvBool, CC_KMB *); + NV_STATUS (*__confComputeKeyStoreRetrieveViaKeyId__)(struct ConfidentialCompute *, NvU32, ROTATE_IV_TYPE, NvBool, CC_KMB *); + NV_STATUS (*__confComputeDeriveSecrets__)(struct ConfidentialCompute *, NvU32); + NvBool (*__confComputeIsSpdmEnabled__)(struct OBJGPU *, struct ConfidentialCompute *); + NvBool (*__confComputeIsDebugModeEnabled__)(struct OBJGPU *, struct ConfidentialCompute *); + NvBool (*__confComputeIsGpuCcCapable__)(struct OBJGPU *, struct ConfidentialCompute *); + NV_STATUS (*__confComputeKeyStoreInit__)(struct ConfidentialCompute *); + void (*__confComputeKeyStoreDeinit__)(struct ConfidentialCompute *); + void *(*__confComputeKeyStoreGetExportMasterKey__)(struct ConfidentialCompute *); + NV_STATUS (*__confComputeKeyStoreDeriveKey__)(struct ConfidentialCompute *, NvU32); + void (*__confComputeKeyStoreDepositIvMask__)(struct ConfidentialCompute *, NvU32, void *); + void (*__confComputeKeyStoreClearExportMasterKey__)(struct ConfidentialCompute *); + NV_STATUS (*__confComputeKeyStoreUpdateKey__)(struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStateLoad__)(POBJGPU, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStateUnload__)(POBJGPU, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStatePreLoad__)(POBJGPU, struct ConfidentialCompute *, NvU32); + NV_STATUS (*__confComputeStatePostUnload__)(POBJGPU, struct ConfidentialCompute *, NvU32); + void (*__confComputeStateDestroy__)(POBJGPU, struct ConfidentialCompute *); + NV_STATUS (*__confComputeStateInitUnlocked__)(POBJGPU, struct ConfidentialCompute *); + void (*__confComputeInitMissing__)(POBJGPU, struct ConfidentialCompute *); + NV_STATUS (*__confComputeStatePreInitUnlocked__)(POBJGPU, struct ConfidentialCompute *); + NvBool (*__confComputeIsPresent__)(POBJGPU, struct ConfidentialCompute *); + NvBool PDB_PROP_CONFCOMPUTE_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT; + NvBool PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_SPDM_ENABLED; + NvU32 gspProxyRegkeys; + struct Spdm *pSpdm; + NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS ccStaticInfo; + NvU8 PRIVATE_FIELD(m_exportMasterKey)[32]; + void *PRIVATE_FIELD(m_keySlot); +}; + +#ifndef __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ +#define __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ +typedef struct ConfidentialCompute ConfidentialCompute; +#endif /* __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConfidentialCompute +#define __nvoc_class_id_ConfidentialCompute 0x9798cc +#endif /* __nvoc_class_id_ConfidentialCompute */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialCompute; + +#define __staticCast_ConfidentialCompute(pThis) \ + ((pThis)->__nvoc_pbase_ConfidentialCompute) + +#ifdef __nvoc_conf_compute_h_disabled +#define __dynamicCast_ConfidentialCompute(pThis) ((ConfidentialCompute*)NULL) +#else //__nvoc_conf_compute_h_disabled +#define __dynamicCast_ConfidentialCompute(pThis) \ + ((ConfidentialCompute*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ConfidentialCompute))) +#endif //__nvoc_conf_compute_h_disabled + +#define PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED +#define PDB_PROP_CONFCOMPUTE_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. +#define PDB_PROP_CONFCOMPUTE_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING +#define PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT_BASE_NAME PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT +#define PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED +#define PDB_PROP_CONFCOMPUTE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_ENABLED +#define PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED +#define PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED +#define PDB_PROP_CONFCOMPUTE_SPDM_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_SPDM_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_SPDM_ENABLED + +NV_STATUS __nvoc_objCreateDynamic_ConfidentialCompute(ConfidentialCompute**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute**, Dynamic*, NvU32); +#define __objCreate_ConfidentialCompute(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_ConfidentialCompute((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define confComputeConstructEngine(pGpu, pConfCompute, engDesc) confComputeConstructEngine_DISPATCH(pGpu, pConfCompute, engDesc) +#define confComputeStateInitLocked(pGpu, pConfCompute) confComputeStateInitLocked_DISPATCH(pGpu, pConfCompute) +#define confComputeStatePostLoad(pGpu, pConfCompute, flags) confComputeStatePostLoad_DISPATCH(pGpu, pConfCompute, flags) +#define confComputeStatePreInitLocked(pGpu, pConfCompute) confComputeStatePreInitLocked_DISPATCH(pGpu, pConfCompute) +#define confComputeStatePreUnload(pGpu, pConfCompute, flags) confComputeStatePreUnload_DISPATCH(pGpu, pConfCompute, flags) +#define confComputeKeyStoreRetrieveViaChannel(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaChannel_DISPATCH(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) +#define confComputeKeyStoreRetrieveViaChannel_HAL(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaChannel_DISPATCH(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) +#define confComputeKeyStoreRetrieveViaKeyId(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaKeyId_DISPATCH(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) +#define confComputeKeyStoreRetrieveViaKeyId_HAL(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaKeyId_DISPATCH(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) +#define confComputeDeriveSecrets(pConfCompute, engine) confComputeDeriveSecrets_DISPATCH(pConfCompute, engine) +#define confComputeDeriveSecrets_HAL(pConfCompute, engine) confComputeDeriveSecrets_DISPATCH(pConfCompute, engine) +#define confComputeIsSpdmEnabled(pGpu, pConfCompute) confComputeIsSpdmEnabled_DISPATCH(pGpu, pConfCompute) +#define confComputeIsSpdmEnabled_HAL(pGpu, pConfCompute) confComputeIsSpdmEnabled_DISPATCH(pGpu, pConfCompute) +#define confComputeIsDebugModeEnabled(pGpu, pConfCompute) confComputeIsDebugModeEnabled_DISPATCH(pGpu, pConfCompute) +#define confComputeIsDebugModeEnabled_HAL(pGpu, pConfCompute) confComputeIsDebugModeEnabled_DISPATCH(pGpu, pConfCompute) +#define confComputeIsGpuCcCapable(pGpu, pConfCompute) confComputeIsGpuCcCapable_DISPATCH(pGpu, pConfCompute) +#define confComputeIsGpuCcCapable_HAL(pGpu, pConfCompute) confComputeIsGpuCcCapable_DISPATCH(pGpu, pConfCompute) +#define confComputeKeyStoreInit(pConfCompute) confComputeKeyStoreInit_DISPATCH(pConfCompute) +#define confComputeKeyStoreInit_HAL(pConfCompute) confComputeKeyStoreInit_DISPATCH(pConfCompute) +#define confComputeKeyStoreDeinit(pConfCompute) confComputeKeyStoreDeinit_DISPATCH(pConfCompute) +#define confComputeKeyStoreDeinit_HAL(pConfCompute) confComputeKeyStoreDeinit_DISPATCH(pConfCompute) +#define confComputeKeyStoreGetExportMasterKey(pConfCompute) confComputeKeyStoreGetExportMasterKey_DISPATCH(pConfCompute) +#define confComputeKeyStoreGetExportMasterKey_HAL(pConfCompute) confComputeKeyStoreGetExportMasterKey_DISPATCH(pConfCompute) +#define confComputeKeyStoreDeriveKey(pConfCompute, globalKeyId) confComputeKeyStoreDeriveKey_DISPATCH(pConfCompute, globalKeyId) +#define confComputeKeyStoreDeriveKey_HAL(pConfCompute, globalKeyId) confComputeKeyStoreDeriveKey_DISPATCH(pConfCompute, globalKeyId) +#define confComputeKeyStoreDepositIvMask(pConfCompute, globalKeyId, ivMask) confComputeKeyStoreDepositIvMask_DISPATCH(pConfCompute, globalKeyId, ivMask) +#define confComputeKeyStoreDepositIvMask_HAL(pConfCompute, globalKeyId, ivMask) confComputeKeyStoreDepositIvMask_DISPATCH(pConfCompute, globalKeyId, ivMask) +#define confComputeKeyStoreClearExportMasterKey(pConfCompute) confComputeKeyStoreClearExportMasterKey_DISPATCH(pConfCompute) +#define confComputeKeyStoreClearExportMasterKey_HAL(pConfCompute) confComputeKeyStoreClearExportMasterKey_DISPATCH(pConfCompute) +#define confComputeKeyStoreUpdateKey(pConfCompute, globalKeyId) confComputeKeyStoreUpdateKey_DISPATCH(pConfCompute, globalKeyId) +#define confComputeKeyStoreUpdateKey_HAL(pConfCompute, globalKeyId) confComputeKeyStoreUpdateKey_DISPATCH(pConfCompute, globalKeyId) +#define confComputeStateLoad(pGpu, pEngstate, arg0) confComputeStateLoad_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStateUnload(pGpu, pEngstate, arg0) confComputeStateUnload_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStatePreLoad(pGpu, pEngstate, arg0) confComputeStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStatePostUnload(pGpu, pEngstate, arg0) confComputeStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStateDestroy(pGpu, pEngstate) confComputeStateDestroy_DISPATCH(pGpu, pEngstate) +#define confComputeStateInitUnlocked(pGpu, pEngstate) confComputeStateInitUnlocked_DISPATCH(pGpu, pEngstate) +#define confComputeInitMissing(pGpu, pEngstate) confComputeInitMissing_DISPATCH(pGpu, pEngstate) +#define confComputeStatePreInitUnlocked(pGpu, pEngstate) confComputeStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) +#define confComputeIsPresent(pGpu, pEngstate) confComputeIsPresent_DISPATCH(pGpu, pEngstate) +static inline NV_STATUS confComputeEarlyInit_56cd7a(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return NV_OK; +} + + +#ifdef __nvoc_conf_compute_h_disabled +static inline NV_STATUS confComputeEarlyInit(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_conf_compute_h_disabled +#define confComputeEarlyInit(pGpu, pConfCompute) confComputeEarlyInit_56cd7a(pGpu, pConfCompute) +#endif //__nvoc_conf_compute_h_disabled + +#define confComputeEarlyInit_HAL(pGpu, pConfCompute) confComputeEarlyInit(pGpu, pConfCompute) + +NV_STATUS confComputeConstructEngine_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc); + +static inline NV_STATUS confComputeConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc) { + return pConfCompute->__confComputeConstructEngine__(pGpu, pConfCompute, engDesc); +} + +NV_STATUS confComputeStateInitLocked_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NV_STATUS confComputeStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeStateInitLocked__(pGpu, pConfCompute); +} + +NV_STATUS confComputeStatePostLoad_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags); + +static inline NV_STATUS confComputeStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags) { + return pConfCompute->__confComputeStatePostLoad__(pGpu, pConfCompute, flags); +} + +NV_STATUS confComputeStatePreInitLocked_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NV_STATUS confComputeStatePreInitLocked_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeStatePreInitLocked__(pGpu, pConfCompute); +} + +NV_STATUS confComputeStatePreUnload_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags); + +static inline NV_STATUS confComputeStatePreUnload_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags) { + return pConfCompute->__confComputeStatePreUnload__(pGpu, pConfCompute, flags); +} + +NV_STATUS confComputeKeyStoreRetrieveViaChannel_GH100(struct ConfidentialCompute *pConfCompute, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); + +static inline NV_STATUS confComputeKeyStoreRetrieveViaChannel_46f6a7(struct ConfidentialCompute *pConfCompute, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreRetrieveViaChannel_DISPATCH(struct ConfidentialCompute *pConfCompute, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return pConfCompute->__confComputeKeyStoreRetrieveViaChannel__(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle); +} + +NV_STATUS confComputeKeyStoreRetrieveViaKeyId_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); + +static inline NV_STATUS confComputeKeyStoreRetrieveViaKeyId_46f6a7(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreRetrieveViaKeyId_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return pConfCompute->__confComputeKeyStoreRetrieveViaKeyId__(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle); +} + +NV_STATUS confComputeDeriveSecrets_GH100(struct ConfidentialCompute *pConfCompute, NvU32 engine); + +static inline NV_STATUS confComputeDeriveSecrets_46f6a7(struct ConfidentialCompute *pConfCompute, NvU32 engine) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeDeriveSecrets_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 engine) { + return pConfCompute->__confComputeDeriveSecrets__(pConfCompute, engine); +} + +static inline NvBool confComputeIsSpdmEnabled_cbe027(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return ((NvBool)(0 == 0)); +} + +static inline NvBool confComputeIsSpdmEnabled_491d52(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool confComputeIsSpdmEnabled_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeIsSpdmEnabled__(pGpu, pConfCompute); +} + +NvBool confComputeIsDebugModeEnabled_GH100(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NvBool confComputeIsDebugModeEnabled_491d52(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool confComputeIsDebugModeEnabled_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeIsDebugModeEnabled__(pGpu, pConfCompute); +} + +NvBool confComputeIsGpuCcCapable_GH100(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NvBool confComputeIsGpuCcCapable_491d52(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool confComputeIsGpuCcCapable_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeIsGpuCcCapable__(pGpu, pConfCompute); +} + +NV_STATUS confComputeKeyStoreInit_GH100(struct ConfidentialCompute *pConfCompute); + +static inline NV_STATUS confComputeKeyStoreInit_46f6a7(struct ConfidentialCompute *pConfCompute) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreInit_DISPATCH(struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeKeyStoreInit__(pConfCompute); +} + +void confComputeKeyStoreDeinit_GH100(struct ConfidentialCompute *pConfCompute); + +static inline void confComputeKeyStoreDeinit_b3696a(struct ConfidentialCompute *pConfCompute) { + return; +} + +static inline void confComputeKeyStoreDeinit_DISPATCH(struct ConfidentialCompute *pConfCompute) { + pConfCompute->__confComputeKeyStoreDeinit__(pConfCompute); +} + +void *confComputeKeyStoreGetExportMasterKey_GH100(struct ConfidentialCompute *pConfCompute); + +static inline void *confComputeKeyStoreGetExportMasterKey_fa6e19(struct ConfidentialCompute *pConfCompute) { + return ((void *)0); +} + +static inline void *confComputeKeyStoreGetExportMasterKey_DISPATCH(struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeKeyStoreGetExportMasterKey__(pConfCompute); +} + +NV_STATUS confComputeKeyStoreDeriveKey_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +static inline NV_STATUS confComputeKeyStoreDeriveKey_46f6a7(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreDeriveKey_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { + return pConfCompute->__confComputeKeyStoreDeriveKey__(pConfCompute, globalKeyId); +} + +void confComputeKeyStoreDepositIvMask_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask); + +static inline void confComputeKeyStoreDepositIvMask_b3696a(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask) { + return; +} + +static inline void confComputeKeyStoreDepositIvMask_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask) { + pConfCompute->__confComputeKeyStoreDepositIvMask__(pConfCompute, globalKeyId, ivMask); +} + +void confComputeKeyStoreClearExportMasterKey_GH100(struct ConfidentialCompute *pConfCompute); + +static inline void confComputeKeyStoreClearExportMasterKey_b3696a(struct ConfidentialCompute *pConfCompute) { + return; +} + +static inline void confComputeKeyStoreClearExportMasterKey_DISPATCH(struct ConfidentialCompute *pConfCompute) { + pConfCompute->__confComputeKeyStoreClearExportMasterKey__(pConfCompute); +} + +NV_STATUS confComputeKeyStoreUpdateKey_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +static inline NV_STATUS confComputeKeyStoreUpdateKey_46f6a7(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeKeyStoreUpdateKey_DISPATCH(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { + return pConfCompute->__confComputeKeyStoreUpdateKey__(pConfCompute, globalKeyId); +} + +static inline NV_STATUS confComputeStateLoad_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return pEngstate->__confComputeStateLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS confComputeStateUnload_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return pEngstate->__confComputeStateUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS confComputeStatePreLoad_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return pEngstate->__confComputeStatePreLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS confComputeStatePostUnload_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { + return pEngstate->__confComputeStatePostUnload__(pGpu, pEngstate, arg0); +} + +static inline void confComputeStateDestroy_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + pEngstate->__confComputeStateDestroy__(pGpu, pEngstate); +} + +static inline NV_STATUS confComputeStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return pEngstate->__confComputeStateInitUnlocked__(pGpu, pEngstate); +} + +static inline void confComputeInitMissing_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + pEngstate->__confComputeInitMissing__(pGpu, pEngstate); +} + +static inline NV_STATUS confComputeStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return pEngstate->__confComputeStatePreInitUnlocked__(pGpu, pEngstate); +} + +static inline NvBool confComputeIsPresent_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + return pEngstate->__confComputeIsPresent__(pGpu, pEngstate); +} + +NvBool confComputeAcceptClientRequest_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +#ifdef __nvoc_conf_compute_h_disabled +static inline NvBool confComputeAcceptClientRequest(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); + return NV_FALSE; +} +#else //__nvoc_conf_compute_h_disabled +#define confComputeAcceptClientRequest(pGpu, pConfCompute) confComputeAcceptClientRequest_IMPL(pGpu, pConfCompute) +#endif //__nvoc_conf_compute_h_disabled + +#undef PRIVATE_FIELD + +#ifndef NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED +#undef confComputeKeyStoreInit +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreInit)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreInit_HAL +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreInit_HAL)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreDeinit +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDeinit)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreDeinit_HAL +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDeinit_HAL)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreGetExportMasterKey +void *NVOC_PRIVATE_FUNCTION(confComputeKeyStoreGetExportMasterKey)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreGetExportMasterKey_HAL +void *NVOC_PRIVATE_FUNCTION(confComputeKeyStoreGetExportMasterKey_HAL)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreDeriveKey +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDeriveKey)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +#undef confComputeKeyStoreDeriveKey_HAL +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDeriveKey_HAL)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +#undef confComputeKeyStoreDepositIvMask +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDepositIvMask)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask); + +#undef confComputeKeyStoreDepositIvMask_HAL +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreDepositIvMask_HAL)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask); + +#undef confComputeKeyStoreClearExportMasterKey +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreClearExportMasterKey)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreClearExportMasterKey_HAL +void NVOC_PRIVATE_FUNCTION(confComputeKeyStoreClearExportMasterKey_HAL)(struct ConfidentialCompute *pConfCompute); + +#undef confComputeKeyStoreUpdateKey +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreUpdateKey)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +#undef confComputeKeyStoreUpdateKey_HAL +NV_STATUS NVOC_PRIVATE_FUNCTION(confComputeKeyStoreUpdateKey_HAL)(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId); + +#endif // NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED + + +// Refactor spdmCtrlSpdmPartition into SPDM module. + +/*! + * @brief spdmCtrlSpdmPartition + * Common function used to call gspCommandPostBlocking based on the platform on which it runs (i.e. vGPU, GSP-RM, Monolithic). + * + * @param[in] pGpu : OBJGPU Pointer + * @param[in] pSpdmPartitionParams : SPDM RPC structure pointer + */ +NV_STATUS spdmCtrlSpdmPartition(struct OBJGPU *pGpu, NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *pSpdmPartitionParams); + +// spdmCtrlWriteSharedMemory is a common function called from both Physical-RM and Kernel-RM. +// However, SPDM module is disabled on Phyiscal-RM and hence declared in conf_compute.h. + +#endif // CONF_COMPUTE_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_CONF_COMPUTE_NVOC_H_ diff --git a/src/nvidia/generated/g_console_mem_nvoc.c b/src/nvidia/generated/g_console_mem_nvoc.c index 5517d86937..ed96fb0f25 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.c +++ b/src/nvidia/generated/g_console_mem_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_conmemIsReady(struct ConsoleMemory *pMemory return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_conmemCheckCopyPermissions(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_conmemCheckCopyPermissions(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_conmemPreDestruct(struct ConsoleMemory *pResource) { diff --git a/src/nvidia/generated/g_console_mem_nvoc.h b/src/nvidia/generated/g_console_mem_nvoc.h index b183315979..ddab10389d 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.h +++ b/src/nvidia/generated/g_console_mem_nvoc.h @@ -72,7 +72,7 @@ struct ConsoleMemory { NV_STATUS (*__conmemControlFilter__)(struct ConsoleMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemControlSerialization_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemIsReady__)(struct ConsoleMemory *, NvBool); - NV_STATUS (*__conmemCheckCopyPermissions__)(struct ConsoleMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__conmemCheckCopyPermissions__)(struct ConsoleMemory *, struct OBJGPU *, struct Device *); void (*__conmemPreDestruct__)(struct ConsoleMemory *); NV_STATUS (*__conmemIsDuplicate__)(struct ConsoleMemory *, NvHandle, NvBool *); void (*__conmemControlSerialization_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -127,7 +127,7 @@ NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory**, Dynamic*, NvU32, CALL_ #define conmemControlFilter(pResource, pCallContext, pParams) conmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define conmemControlSerialization_Prologue(pResource, pCallContext, pParams) conmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define conmemIsReady(pMemory, bCopyConstructorContext) conmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define conmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) conmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define conmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) conmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define conmemPreDestruct(pResource) conmemPreDestruct_DISPATCH(pResource) #define conmemIsDuplicate(pMemory, hMemory, pDuplicate) conmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define conmemControlSerialization_Epilogue(pResource, pCallContext, pParams) conmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -211,8 +211,8 @@ static inline NV_STATUS conmemIsReady_DISPATCH(struct ConsoleMemory *pMemory, Nv return pMemory->__conmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS conmemCheckCopyPermissions_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__conmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS conmemCheckCopyPermissions_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__conmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void conmemPreDestruct_DISPATCH(struct ConsoleMemory *pResource) { diff --git a/src/nvidia/generated/g_dce_client_nvoc.h b/src/nvidia/generated/g_dce_client_nvoc.h index cba98be2ea..21338e8bcc 100644 --- a/src/nvidia/generated/g_dce_client_nvoc.h +++ b/src/nvidia/generated/g_dce_client_nvoc.h @@ -239,7 +239,7 @@ NV_STATUS rpcRmApiControl_dce(RM_API *pRmApi, NV_STATUS rpcRmApiAlloc_dce(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams); + void *pAllocParams, NvU32 allocParamsSize); NV_STATUS rpcRmApiDupObject_dce(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, NvHandle *phObject, NvHandle hClientSrc, NvHandle hObjectSrc, NvU32 flags); diff --git a/src/nvidia/generated/g_deferred_api_nvoc.c b/src/nvidia/generated/g_deferred_api_nvoc.c index 65c7dc3af9..66946ab61e 100644 --- a/src/nvidia/generated/g_deferred_api_nvoc.c +++ b/src/nvidia/generated/g_deferred_api_nvoc.c @@ -255,12 +255,12 @@ static NV_STATUS __nvoc_thunk_Notifier_defapiGetOrAllocNotifShare(struct Deferre static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DeferredApiObject[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) defapiCtrlCmdDeferredApi_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0x50800101u, /*paramSize=*/ sizeof(NV5080_CTRL_DEFERRED_API_PARAMS), @@ -270,12 +270,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Deferred #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) defapiCtrlCmdRemoveApi_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0x50800102u, /*paramSize=*/ sizeof(NV5080_CTRL_REMOVE_API_PARAMS), @@ -285,12 +285,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Deferred #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) defapiCtrlCmdDeferredApiV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0x50800103u, /*paramSize=*/ sizeof(NV5080_CTRL_DEFERRED_API_V2_PARAMS), @@ -345,15 +345,15 @@ static void __nvoc_init_funcTable_DeferredApiObject_1(DeferredApiObject *pThis) pThis->__defapiIsSwMethodStalling__ = &defapiIsSwMethodStalling_IMPL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__defapiCtrlCmdDeferredApi__ = &defapiCtrlCmdDeferredApi_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__defapiCtrlCmdDeferredApiV2__ = &defapiCtrlCmdDeferredApiV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__defapiCtrlCmdRemoveApi__ = &defapiCtrlCmdRemoveApi_IMPL; #endif diff --git a/src/nvidia/generated/g_device_nvoc.c b/src/nvidia/generated/g_device_nvoc.c index acdcafe7fe..6b9e2989ee 100644 --- a/src/nvidia/generated/g_device_nvoc.c +++ b/src/nvidia/generated/g_device_nvoc.c @@ -200,21 +200,6 @@ static NvBool __nvoc_thunk_RmResource_deviceAccessCallback(struct Device *pResou static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) deviceCtrlCmdBifReset_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x800102u, - /*paramSize=*/ sizeof(NV0080_CTRL_BIF_RESET_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "deviceCtrlCmdBifReset" -#endif - }, - { /* [1] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -229,7 +214,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBifGetDmaBaseSysmemAddr" #endif }, - { /* [2] */ + { /* [1] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -244,7 +229,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBifAspmFeatureSupported" #endif }, - { /* [3] */ + { /* [2] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -259,7 +244,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBifAspmCyaUpdate" #endif }, - { /* [4] */ + { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -274,7 +259,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBifGetPciePowerControlMask" #endif }, - { /* [5] */ + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -289,7 +274,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetClasslist" #endif }, - { /* [6] */ + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -304,7 +289,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetNumSubdevices" #endif }, - { /* [7] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -319,7 +304,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuModifyGpuSwStatePersistence" #endif }, - { /* [8] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -334,7 +319,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuQueryGpuSwStatePersistence" #endif }, - { /* [9] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -349,7 +334,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetVirtualizationMode" #endif }, - { /* [10] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -364,7 +349,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetSparseTextureComputeMode" #endif }, - { /* [11] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -379,7 +364,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuSetSparseTextureComputeMode" #endif }, - { /* [12] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -394,7 +379,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetVgxCaps" #endif }, - { /* [13] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -409,7 +394,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetSriovCaps" #endif }, - { /* [14] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -424,7 +409,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetClasslistV2" #endif }, - { /* [15] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -439,7 +424,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetFindSubDeviceHandle" #endif }, - { /* [16] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -454,7 +439,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetBrandCaps" #endif }, - { /* [17] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -469,7 +454,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuSetVgpuVfBar1Size" #endif }, - { /* [18] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -484,7 +469,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCaps" #endif }, - { /* [19] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -499,7 +484,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfo" #endif }, - { /* [20] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -514,7 +499,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetTpcPartitionMode" #endif }, - { /* [21] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -529,7 +514,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [22] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -544,7 +529,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [23] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -559,7 +544,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [24] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -574,7 +559,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCaps" #endif }, - { /* [25] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -589,13 +574,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCompbitStoreInfo" #endif }, - { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [25] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdFbGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x801307u, /*paramSize=*/ sizeof(NV0080_CTRL_FB_GET_CAPS_V2_PARAMS), @@ -604,7 +589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCapsV2" #endif }, - { /* [27] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -619,7 +604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCaps" #endif }, - { /* [28] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -634,7 +619,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCapsV2" #endif }, - { /* [29] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -649,7 +634,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCaps" #endif }, - { /* [30] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -664,7 +649,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartSelectedChannels" #endif }, - { /* [31] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -679,7 +664,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetEngineContextProperties" #endif }, - { /* [32] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -694,7 +679,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetChannelList" #endif }, - { /* [33] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -709,7 +694,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetLatencyBufferSize" #endif }, - { /* [34] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -724,7 +709,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoSetChannelProperties" #endif }, - { /* [35] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -739,7 +724,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStopRunlist" #endif }, - { /* [36] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -754,7 +739,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartRunlist" #endif }, - { /* [37] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -769,7 +754,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCapsV2" #endif }, - { /* [38] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -784,7 +769,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoIdleChannels" #endif }, - { /* [39] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -799,7 +784,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPteInfo" #endif }, - { /* [40] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -814,7 +799,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaFlush" #endif }, - { /* [41] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -829,7 +814,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaAdvSchedGetVaCaps" #endif }, - { /* [42] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -844,7 +829,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPdeInfo" #endif }, - { /* [43] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -859,7 +844,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPteInfo" #endif }, - { /* [44] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -874,7 +859,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [45] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -889,7 +874,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetCaps" #endif }, - { /* [46] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -904,7 +889,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetVASpaceSize" #endif }, - { /* [47] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -919,7 +904,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUpdatePde2" #endif }, - { /* [48] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -934,7 +919,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaEnablePrivilegedRange" #endif }, - { /* [49] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -949,7 +934,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetDefaultVASpace" #endif }, - { /* [50] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -964,7 +949,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPageDirectory" #endif }, - { /* [51] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -979,7 +964,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUnsetPageDirectory" #endif }, - { /* [52] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -994,7 +979,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdMsencGetCaps" #endif }, - { /* [53] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1009,7 +994,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBspGetCapsV2" #endif }, - { /* [54] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1024,7 +1009,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTSwitch" #endif }, - { /* [55] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1039,7 +1024,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTGetFBInfo" #endif }, - { /* [56] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1054,7 +1039,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdNvjpgGetCapsV2" #endif }, - { /* [57] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1069,7 +1054,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [58] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1084,13 +1069,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount" #endif }, - { /* [59] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) + { /* [58] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdInternalPerfCudaLimitSetControl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) - /*flags=*/ 0xe10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) + /*flags=*/ 0xe50u, /*accessRight=*/0x0u, /*methodId=*/ 0x802009u, /*paramSize=*/ sizeof(NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS), @@ -1104,7 +1089,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] const struct NVOC_EXPORT_INFO __nvoc_export_info_Device = { - /*numEntries=*/ 60, + /*numEntries=*/ 59, /*pExportEntries=*/ __nvoc_exported_method_def_Device }; @@ -1145,10 +1130,6 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceInternalControlForward__ = &deviceInternalControlForward_IMPL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - pThis->__deviceCtrlCmdBifReset__ = &deviceCtrlCmdBifReset_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__deviceCtrlCmdBifGetDmaBaseSysmemAddr__ = &deviceCtrlCmdBifGetDmaBaseSysmemAddr_IMPL; #endif @@ -1249,7 +1230,7 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdFbGetCaps__ = &deviceCtrlCmdFbGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__deviceCtrlCmdFbGetCapsV2__ = &deviceCtrlCmdFbGetCapsV2_IMPL; #endif @@ -1301,7 +1282,7 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdHostGetCapsV2__ = &deviceCtrlCmdHostGetCapsV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) pThis->__deviceCtrlCmdInternalPerfCudaLimitSetControl__ = &deviceCtrlCmdInternalPerfCudaLimitSetControl_IMPL; #endif diff --git a/src/nvidia/generated/g_device_nvoc.h b/src/nvidia/generated/g_device_nvoc.h index 99d7b0171b..6f58d1f22a 100644 --- a/src/nvidia/generated/g_device_nvoc.h +++ b/src/nvidia/generated/g_device_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -83,7 +83,6 @@ struct Device { struct Device *__nvoc_pbase_Device; NV_STATUS (*__deviceControl__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__deviceInternalControlForward__)(struct Device *, NvU32, void *, NvU32); - NV_STATUS (*__deviceCtrlCmdBifReset__)(struct Device *, NV0080_CTRL_BIF_RESET_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifGetDmaBaseSysmemAddr__)(struct Device *, NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifAspmFeatureSupported__)(struct Device *, NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifAspmCyaUpdate__)(struct Device *, NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS *); @@ -216,7 +215,6 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceControl(pResource, pCallContext, pParams) deviceControl_DISPATCH(pResource, pCallContext, pParams) #define deviceInternalControlForward(pDevice, command, pParams, size) deviceInternalControlForward_DISPATCH(pDevice, command, pParams, size) -#define deviceCtrlCmdBifReset(pDevice, pBifResetParams) deviceCtrlCmdBifReset_DISPATCH(pDevice, pBifResetParams) #define deviceCtrlCmdBifGetDmaBaseSysmemAddr(pDevice, pBifDmaBaseSysmemParams) deviceCtrlCmdBifGetDmaBaseSysmemAddr_DISPATCH(pDevice, pBifDmaBaseSysmemParams) #define deviceCtrlCmdBifAspmFeatureSupported(pDevice, pBifAspmParams) deviceCtrlCmdBifAspmFeatureSupported_DISPATCH(pDevice, pBifAspmParams) #define deviceCtrlCmdBifAspmCyaUpdate(pDevice, pBifAspmCyaParams) deviceCtrlCmdBifAspmCyaUpdate_DISPATCH(pDevice, pBifAspmCyaParams) @@ -311,12 +309,6 @@ static inline NV_STATUS deviceInternalControlForward_DISPATCH(struct Device *pDe return pDevice->__deviceInternalControlForward__(pDevice, command, pParams, size); } -NV_STATUS deviceCtrlCmdBifReset_IMPL(struct Device *pDevice, NV0080_CTRL_BIF_RESET_PARAMS *pBifResetParams); - -static inline NV_STATUS deviceCtrlCmdBifReset_DISPATCH(struct Device *pDevice, NV0080_CTRL_BIF_RESET_PARAMS *pBifResetParams) { - return pDevice->__deviceCtrlCmdBifReset__(pDevice, pBifResetParams); -} - NV_STATUS deviceCtrlCmdBifGetDmaBaseSysmemAddr_IMPL(struct Device *pDevice, NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS *pBifDmaBaseSysmemParams); static inline NV_STATUS deviceCtrlCmdBifGetDmaBaseSysmemAddr_DISPATCH(struct Device *pDevice, NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS *pBifDmaBaseSysmemParams) { @@ -839,11 +831,6 @@ static inline NV_STATUS deviceSetDefaultVASpace(struct Device *pDevice, NvHandle // Deprecated Definitions // **************************************************************************** -/** - * WARNING: This function is deprecated! Please use deviceGetByHandle. - */ -struct Device *CliGetDeviceInfo(NvHandle, NvHandle); - /** * WARNING: This function is deprecated and use is *strongly* discouraged * (especially for new code!) diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.c b/src/nvidia/generated/g_disp_inst_mem_nvoc.c index 9ca145cf1c..f19fab2c4c 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.c +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.c @@ -107,73 +107,73 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); // Hal function -- instmemGetSize - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemGetSize__ = &instmemGetSize_v03_00; + pThis->__instmemGetSize__ = &instmemGetSize_f2d351; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemGetSize__ = &instmemGetSize_f2d351; + pThis->__instmemGetSize__ = &instmemGetSize_v03_00; } // Hal function -- instmemGetHashTableBaseAddr - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_v03_00; + pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_4a4dee; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_4a4dee; + pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_v03_00; } // Hal function -- instmemIsValid - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemIsValid__ = &instmemIsValid_v03_00; + pThis->__instmemIsValid__ = &instmemIsValid_491d52; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemIsValid__ = &instmemIsValid_491d52; + pThis->__instmemIsValid__ = &instmemIsValid_v03_00; } // Hal function -- instmemGenerateHashTableData - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_v03_00; + pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_4a4dee; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_4a4dee; + pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_v03_00; } // Hal function -- instmemHashFunc - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemHashFunc__ = &instmemHashFunc_v03_00; + pThis->__instmemHashFunc__ = &instmemHashFunc_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemHashFunc__ = &instmemHashFunc_46f6a7; + pThis->__instmemHashFunc__ = &instmemHashFunc_v03_00; } // Hal function -- instmemCommitContextDma - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_v03_00; + pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_46f6a7; + pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_v03_00; } // Hal function -- instmemUpdateContextDma - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_v03_00; + pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_46f6a7; + pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_v03_00; } } diff --git a/src/nvidia/generated/g_disp_objs_nvoc.c b/src/nvidia/generated/g_disp_objs_nvoc.c index e27e649f9b..e3f0e9d39c 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.c +++ b/src/nvidia/generated/g_disp_objs_nvoc.c @@ -2714,12 +2714,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [11] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetAcpiIdMap_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73015au, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS), @@ -2744,6 +2744,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [13] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemAcpiSubsystemActivated_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x73015cu, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemAcpiSubsystemActivated" +#endif + }, + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2758,7 +2773,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetConnectorTable" #endif }, - { /* [14] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2773,7 +2788,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetBootDisplays" #endif }, - { /* [15] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2788,7 +2803,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemExecuteAcpiMethod" #endif }, - { /* [16] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2803,7 +2818,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetHotplugUnplugState" #endif }, - { /* [17] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2818,7 +2833,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdClearELVBlock" #endif }, - { /* [18] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2833,7 +2848,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemArmLightweightSupervisor" #endif }, - { /* [19] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2848,7 +2863,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemConfigVrrPstateSwitch" #endif }, - { /* [20] */ + { /* [21] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemVrrDisplayInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730185u, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemVrrDisplayInfo" +#endif + }, + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2863,7 +2893,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemQueryDisplayIdsWithMux" #endif }, - { /* [21] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2878,7 +2908,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemAllocateDisplayBandwidth" #endif }, - { /* [22] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2893,7 +2923,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetHotplugEventConfig" #endif }, - { /* [23] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2908,7 +2938,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemSetHotplugEventConfig" #endif }, - { /* [24] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2923,7 +2953,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRecordChannelRegisters" #endif }, - { /* [25] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2938,7 +2968,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemCheckSidebandI2cSupport" #endif }, - { /* [26] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2953,7 +2983,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemCheckSidebandSrSupport" #endif }, - { /* [27] */ + { /* [29] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdVRRSetRgLineActive_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x73019eu, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdVRRSetRgLineActive" +#endif + }, + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2968,7 +3013,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetI2cPortid" #endif }, - { /* [28] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2983,7 +3028,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetType" #endif }, - { /* [29] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2998,7 +3043,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificFakeDevice" #endif }, - { /* [30] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3013,7 +3058,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetEdidV2" #endif }, - { /* [31] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3028,7 +3073,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetEdidV2" #endif }, - { /* [32] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3043,7 +3088,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetConnectorData" #endif }, - { /* [33] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3058,7 +3103,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiEnable" #endif }, - { /* [34] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3073,7 +3118,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificCtrlHdmi" #endif }, - { /* [35] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3088,7 +3133,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiAudioMutestream" #endif }, - { /* [36] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3103,7 +3148,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetAcpiIdMapping" #endif }, - { /* [37] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3118,7 +3163,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment" #endif }, - { /* [38] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3133,7 +3178,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetAllHeadMask" #endif }, - { /* [39] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3148,7 +3193,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacket" #endif }, - { /* [40] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3163,7 +3208,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacketCtrl" #endif }, - { /* [41] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3178,7 +3223,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetPclkLimit" #endif }, - { /* [42] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3193,7 +3238,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificOrGetInfo" #endif }, - { /* [43] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3208,7 +3253,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetBacklightBrightness" #endif }, - { /* [44] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3223,7 +3268,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetBacklightBrightness" #endif }, - { /* [45] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3238,7 +3283,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiSinkCaps" #endif }, - { /* [46] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3253,7 +3298,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetMonitorPower" #endif }, - { /* [47] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3268,7 +3313,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig" #endif }, - { /* [48] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3283,7 +3328,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificApplyEdidOverrideV2" #endif }, - { /* [49] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3298,7 +3343,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiGpuCaps" #endif }, - { /* [50] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3313,7 +3358,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDisplayChange" #endif }, - { /* [51] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3328,7 +3373,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiScdcData" #endif }, - { /* [52] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3343,7 +3388,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificIsDirectmodeDisplay" #endif }, - { /* [53] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3358,7 +3403,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation" #endif }, - { /* [54] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3373,7 +3418,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetSharedGenericPacket" #endif }, - { /* [55] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3388,7 +3433,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificAcquireSharedGenericPacket" #endif }, - { /* [56] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3403,7 +3448,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificReleaseSharedGenericPacket" #endif }, - { /* [57] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3418,7 +3463,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDispI2cReadWrite" #endif }, - { /* [58] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3433,7 +3478,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment" #endif }, - { /* [59] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3448,7 +3493,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay" #endif }, - { /* [60] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3463,7 +3508,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdInternalGetHotplugUnplugState" #endif }, - { /* [61] */ + { /* [64] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdInternalVRRSetRgLineActive_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730402u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdInternalVRRSetRgLineActive" +#endif + }, + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3478,7 +3538,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetInfo" #endif }, - { /* [62] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3493,7 +3553,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDisplayportDongleInfo" #endif }, - { /* [63] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3508,7 +3568,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetEldAudioCaps" #endif }, - { /* [64] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3523,7 +3583,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetSpreadSpectrum" #endif }, - { /* [65] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3538,7 +3598,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpUpdateDynamicDfpCache" #endif }, - { /* [66] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3553,7 +3613,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetAudioEnable" #endif }, - { /* [67] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3568,7 +3628,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpAssignSor" #endif }, - { /* [68] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3583,7 +3643,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetPadlinkMask" #endif }, - { /* [69] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3598,7 +3658,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetLcdGpioPinNum" #endif }, - { /* [70] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3613,7 +3673,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpConfigTwoHeadOneOr" #endif }, - { /* [71] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3628,7 +3688,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpDscCrcControl" #endif }, - { /* [72] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3643,7 +3703,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInitMuxData" #endif }, - { /* [73] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3658,7 +3718,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSwitchDispMux" #endif }, - { /* [74] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3673,7 +3733,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPreDispMuxOperations" #endif }, - { /* [75] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3688,7 +3748,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPostDispMuxOperations" #endif }, - { /* [76] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3703,7 +3763,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDispMuxStatus" #endif }, - { /* [77] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3718,7 +3778,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDsiModeTiming" #endif }, - { /* [78] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x202u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3733,7 +3793,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetFixedModeTiming" #endif }, - { /* [79] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3748,7 +3808,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchCtrl" #endif }, - { /* [80] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3763,7 +3823,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchSetSema" #endif }, - { /* [81] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3778,7 +3838,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpCtrl" #endif }, - { /* [82] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3793,7 +3853,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLaneData" #endif }, - { /* [83] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3808,7 +3868,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetLaneData" #endif }, - { /* [84] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3823,7 +3883,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTestpattern" #endif }, - { /* [85] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3838,7 +3898,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [86] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3853,7 +3913,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [87] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3868,7 +3928,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpMainLinkCtrl" #endif }, - { /* [88] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3883,7 +3943,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAudioMuteStream" #endif }, - { /* [89] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3898,7 +3958,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetAudioMuteStream" #endif }, - { /* [90] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3913,7 +3973,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpASSRCtrl" #endif }, - { /* [91] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3928,7 +3988,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyAllocateDisplayId" #endif }, - { /* [92] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3943,7 +4003,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyFreeDisplayId" #endif }, - { /* [93] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3958,7 +4018,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLinkConfig" #endif }, - { /* [94] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3973,7 +4033,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetEDPData" #endif }, - { /* [95] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3988,7 +4048,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigStream" #endif }, - { /* [96] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4003,7 +4063,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetRateGov" #endif }, - { /* [97] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4018,7 +4078,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetManualDisplayPort" #endif }, - { /* [98] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4033,7 +4093,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetEcf" #endif }, - { /* [99] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4048,7 +4108,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSendACT" #endif }, - { /* [100] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4063,7 +4123,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetCaps" #endif }, - { /* [101] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4078,7 +4138,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGenerateFakeInterrupt" #endif }, - { /* [102] */ + { /* [106] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4093,7 +4153,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigRadScratchReg" #endif }, - { /* [103] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4108,7 +4168,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigSingleHeadMultiStream" #endif }, - { /* [104] */ + { /* [108] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4123,7 +4183,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerSelect" #endif }, - { /* [105] */ + { /* [109] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4138,13 +4198,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerAll" #endif }, - { /* [106] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [110] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetAuxLogData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731373u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS), @@ -4153,7 +4213,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAuxLogData" #endif }, - { /* [107] */ + { /* [111] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4168,7 +4228,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigIndexedLinkRates" #endif }, - { /* [108] */ + { /* [112] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4183,7 +4243,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetStereoMSAProperties" #endif }, - { /* [109] */ + { /* [113] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4198,7 +4258,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigureFec" #endif }, - { /* [110] */ + { /* [114] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4213,7 +4273,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigMacroPad" #endif }, - { /* [111] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4228,13 +4288,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchI2cTransferCtrl" #endif }, - { /* [112] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + { /* [116] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpEnableVrr_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) + /*flags=*/ 0x8204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73137du, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS), @@ -4243,7 +4303,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpEnableVrr" #endif }, - { /* [113] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4258,7 +4318,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetGenericInfoframe" #endif }, - { /* [114] */ + { /* [118] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4273,7 +4333,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetMsaAttributes" #endif }, - { /* [115] */ + { /* [119] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4288,7 +4348,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInternalLcdOverdrive" #endif }, - { /* [116] */ + { /* [120] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4303,7 +4363,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetMSAPropertiesv2" #endif }, - { /* [117] */ + { /* [121] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4318,7 +4378,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy" #endif }, - { /* [118] */ + { /* [122] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4333,7 +4393,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdPsrGetSrPanelInfo" #endif }, - { /* [119] */ + { /* [123] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4353,7 +4413,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm const struct NVOC_EXPORT_INFO __nvoc_export_info_DispCommon = { - /*numEntries=*/ 120, + /*numEntries=*/ 124, /*pExportEntries=*/ __nvoc_exported_method_def_DispCommon }; @@ -4413,6 +4473,22 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSystemGetConnectorTable__ = &dispcmnCtrlCmdSystemGetConnectorTable_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdSystemVrrDisplayInfo__ = &dispcmnCtrlCmdSystemVrrDisplayInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__dispcmnCtrlCmdVRRSetRgLineActive__ = &dispcmnCtrlCmdVRRSetRgLineActive_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__dispcmnCtrlCmdInternalVRRSetRgLineActive__ = &dispcmnCtrlCmdInternalVRRSetRgLineActive_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) + pThis->__dispcmnCtrlCmdDpEnableVrr__ = &dispcmnCtrlCmdDpEnableVrr_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispcmnCtrlCmdClearELVBlock__ = &dispcmnCtrlCmdClearELVBlock_IMPL; #endif @@ -4429,10 +4505,6 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpGetLcdGpioPinNum__ = &dispcmnCtrlCmdDfpGetLcdGpioPinNum_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - pThis->__dispcmnCtrlCmdDpEnableVrr__ = &dispcmnCtrlCmdDpEnableVrr_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetAudioMuteStream__ = &dispcmnCtrlCmdDpGetAudioMuteStream_IMPL; #endif @@ -4497,10 +4569,14 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSystemExecuteAcpiMethod__ = &dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSystemGetAcpiIdMap__ = &dispcmnCtrlCmdSystemGetAcpiIdMap_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__dispcmnCtrlCmdSystemAcpiSubsystemActivated__ = &dispcmnCtrlCmdSystemAcpiSubsystemActivated_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__dispcmnCtrlCmdSpecificSetAcpiIdMapping__ = &dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL; #endif @@ -4837,7 +4913,7 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDpSetTriggerAll__ = &dispcmnCtrlCmdDpSetTriggerAll_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetAuxLogData__ = &dispcmnCtrlCmdDpGetAuxLogData_IMPL; #endif diff --git a/src/nvidia/generated/g_disp_objs_nvoc.h b/src/nvidia/generated/g_disp_objs_nvoc.h index 41689864e8..7a407ca2e5 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.h +++ b/src/nvidia/generated/g_disp_objs_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -204,19 +204,19 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi**, Dynamic*, NvU32, struct CALL #define dispapiGetNotificationShare(pNotifier) dispapiGetNotificationShare_DISPATCH(pNotifier) #define dispapiMap(pResource, pCallContext, pParams, pCpuMapping) dispapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS dispapiSetUnicastAndSynchronize_KERNEL(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, NvU32 subDeviceInstance); +NV_STATUS dispapiSetUnicastAndSynchronize_KERNEL(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, OBJDISP **ppDisp, NvU32 subDeviceInstance); #ifdef __nvoc_disp_objs_h_disabled -static inline NV_STATUS dispapiSetUnicastAndSynchronize(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, NvU32 subDeviceInstance) { +static inline NV_STATUS dispapiSetUnicastAndSynchronize(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, OBJDISP **ppDisp, NvU32 subDeviceInstance) { NV_ASSERT_FAILED_PRECOMP("DisplayApi was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_disp_objs_h_disabled -#define dispapiSetUnicastAndSynchronize(pDisplayApi, pGpuGroup, ppGpu, subDeviceInstance) dispapiSetUnicastAndSynchronize_KERNEL(pDisplayApi, pGpuGroup, ppGpu, subDeviceInstance) +#define dispapiSetUnicastAndSynchronize(pDisplayApi, pGpuGroup, ppGpu, ppDisp, subDeviceInstance) dispapiSetUnicastAndSynchronize_KERNEL(pDisplayApi, pGpuGroup, ppGpu, ppDisp, subDeviceInstance) #endif //__nvoc_disp_objs_h_disabled -#define dispapiSetUnicastAndSynchronize_HAL(pDisplayApi, pGpuGroup, ppGpu, subDeviceInstance) dispapiSetUnicastAndSynchronize(pDisplayApi, pGpuGroup, ppGpu, subDeviceInstance) +#define dispapiSetUnicastAndSynchronize_HAL(pDisplayApi, pGpuGroup, ppGpu, ppDisp, subDeviceInstance) dispapiSetUnicastAndSynchronize(pDisplayApi, pGpuGroup, ppGpu, ppDisp, subDeviceInstance) NV_STATUS dispapiControl_IMPL(struct DisplayApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -1387,11 +1387,14 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdSystemGetHotplugState__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetInternalDisplays__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetConnectorTable__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemVrrDisplayInfo__)(struct DispCommon *, NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdVRRSetRgLineActive__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdInternalVRRSetRgLineActive__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDpEnableVrr__)(struct DispCommon *, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdClearELVBlock__)(struct DispCommon *, NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificDisplayChange__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetSpreadSpectrum__)(struct DispCommon *, NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetLcdGpioPinNum__)(struct DispCommon *, NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS *); - NV_STATUS (*__dispcmnCtrlCmdDpEnableVrr__)(struct DispCommon *, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGetAudioMuteStream__)(struct DispCommon *, NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpAuxchI2cTransferCtrl__)(struct DispCommon *, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpASSRCtrl__)(struct DispCommon *, NV0073_CTRL_DP_ASSR_CTRL_PARAMS *); @@ -1409,6 +1412,7 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy__)(struct DispCommon *, NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemExecuteAcpiMethod__)(struct DispCommon *, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetAcpiIdMap__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemAcpiSubsystemActivated__)(struct DispCommon *, NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetAcpiIdMapping__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment__)(struct DispCommon *, NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetCapsV2__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS *); @@ -1565,11 +1569,14 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSystemGetHotplugState(pDispCommon, pHotplugParams) dispcmnCtrlCmdSystemGetHotplugState_DISPATCH(pDispCommon, pHotplugParams) #define dispcmnCtrlCmdSystemGetInternalDisplays(pDispCommon, pInternalDisplaysParams) dispcmnCtrlCmdSystemGetInternalDisplays_DISPATCH(pDispCommon, pInternalDisplaysParams) #define dispcmnCtrlCmdSystemGetConnectorTable(pDispCommon, pParams) dispcmnCtrlCmdSystemGetConnectorTable_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSystemVrrDisplayInfo(pDispCommon, pParams) dispcmnCtrlCmdSystemVrrDisplayInfo_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdVRRSetRgLineActive(pDispCommon, pParams) dispcmnCtrlCmdVRRSetRgLineActive_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdInternalVRRSetRgLineActive(pDispCommon, pParams) dispcmnCtrlCmdInternalVRRSetRgLineActive_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdDpEnableVrr(pDispCommon, pParams) dispcmnCtrlCmdDpEnableVrr_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdClearELVBlock(pDispCommon, pParams) dispcmnCtrlCmdClearELVBlock_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificDisplayChange(pDispCommon, pParams) dispcmnCtrlCmdSpecificDisplayChange_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetSpreadSpectrum(pDispCommon, pParams) dispcmnCtrlCmdDfpGetSpreadSpectrum_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetLcdGpioPinNum(pDispCommon, pParams) dispcmnCtrlCmdDfpGetLcdGpioPinNum_DISPATCH(pDispCommon, pParams) -#define dispcmnCtrlCmdDpEnableVrr(pDispCommon, pParams) dispcmnCtrlCmdDpEnableVrr_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGetAudioMuteStream(pDispCommon, pParams) dispcmnCtrlCmdDpGetAudioMuteStream_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpAuxchI2cTransferCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpAuxchI2cTransferCtrl_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpASSRCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpASSRCtrl_DISPATCH(pDispCommon, pParams) @@ -1587,6 +1594,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy(pDispCommon, pParams) dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSystemExecuteAcpiMethod(pDispCommon, pAcpiMethodParams) dispcmnCtrlCmdSystemExecuteAcpiMethod_DISPATCH(pDispCommon, pAcpiMethodParams) #define dispcmnCtrlCmdSystemGetAcpiIdMap(pDispCommon, pAcpiIdMapParams) dispcmnCtrlCmdSystemGetAcpiIdMap_DISPATCH(pDispCommon, pAcpiIdMapParams) +#define dispcmnCtrlCmdSystemAcpiSubsystemActivated(pDispCommon, pParams) dispcmnCtrlCmdSystemAcpiSubsystemActivated_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificSetAcpiIdMapping(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetAcpiIdMapping_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSystemGetCapsV2(pDispCommon, pCapsParams) dispcmnCtrlCmdSystemGetCapsV2_DISPATCH(pDispCommon, pCapsParams) @@ -1741,6 +1749,30 @@ static inline NV_STATUS dispcmnCtrlCmdSystemGetConnectorTable_DISPATCH(struct Di return pDispCommon->__dispcmnCtrlCmdSystemGetConnectorTable__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSystemVrrDisplayInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemVrrDisplayInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSystemVrrDisplayInfo__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdVRRSetRgLineActive__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdInternalVRRSetRgLineActive_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdInternalVRRSetRgLineActive_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdInternalVRRSetRgLineActive__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdDpEnableVrr_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdDpEnableVrr_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDpEnableVrr__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdClearELVBlock_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdClearELVBlock_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS *pParams) { @@ -1765,12 +1797,6 @@ static inline NV_STATUS dispcmnCtrlCmdDfpGetLcdGpioPinNum_DISPATCH(struct DispCo return pDispCommon->__dispcmnCtrlCmdDfpGetLcdGpioPinNum__(pDispCommon, pParams); } -NV_STATUS dispcmnCtrlCmdDpEnableVrr_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams); - -static inline NV_STATUS dispcmnCtrlCmdDpEnableVrr_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams) { - return pDispCommon->__dispcmnCtrlCmdDpEnableVrr__(pDispCommon, pParams); -} - NV_STATUS dispcmnCtrlCmdDpGetAudioMuteStream_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDpGetAudioMuteStream_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS *pParams) { @@ -1873,6 +1899,12 @@ static inline NV_STATUS dispcmnCtrlCmdSystemGetAcpiIdMap_DISPATCH(struct DispCom return pDispCommon->__dispcmnCtrlCmdSystemGetAcpiIdMap__(pDispCommon, pAcpiIdMapParams); } +NV_STATUS dispcmnCtrlCmdSystemAcpiSubsystemActivated_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemAcpiSubsystemActivated_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSystemAcpiSubsystemActivated__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdSpecificSetAcpiIdMapping_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *pParams) { diff --git a/src/nvidia/generated/g_dispsw_nvoc.c b/src/nvidia/generated/g_dispsw_nvoc.c index 6ef4a73d7a..e728944840 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.c +++ b/src/nvidia/generated/g_dispsw_nvoc.c @@ -322,10 +322,7 @@ static void __nvoc_init_funcTable_DispSwObject_1(DispSwObject *pThis, RmHalspecO PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- dispswGetSwMethods - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__dispswGetSwMethods__ = &dispswGetSwMethods_46f6a7; - } + pThis->__dispswGetSwMethods__ = &dispswGetSwMethods_46f6a7; #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__dispswCtrlCmdNotifyOnVblank__ = &dispswCtrlCmdNotifyOnVblank_IMPL; diff --git a/src/nvidia/generated/g_dispsw_nvoc.h b/src/nvidia/generated/g_dispsw_nvoc.h index 1f52101330..8e9a7bd7bd 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.h +++ b/src/nvidia/generated/g_dispsw_nvoc.h @@ -99,7 +99,7 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill(struct OBJGPU *pGpu, NvU32 releasevalue, NvU32 flags, NvU32 completionStatus, - NvHandle hClient, + struct RsClient *pClient, NvHandle hEvent); /*! diff --git a/src/nvidia/generated/g_egm_mem_nvoc.c b/src/nvidia/generated/g_egm_mem_nvoc.c new file mode 100644 index 0000000000..ad97458e35 --- /dev/null +++ b/src/nvidia/generated/g_egm_mem_nvoc.c @@ -0,0 +1,364 @@ +#define NVOC_EGM_MEM_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_egm_mem_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xeffa5c = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ExtendedGpuMemory; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_StandardMemory; + +void __nvoc_init_ExtendedGpuMemory(ExtendedGpuMemory*); +void __nvoc_init_funcTable_ExtendedGpuMemory(ExtendedGpuMemory*); +NV_STATUS __nvoc_ctor_ExtendedGpuMemory(ExtendedGpuMemory*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_ExtendedGpuMemory(ExtendedGpuMemory*); +void __nvoc_dtor_ExtendedGpuMemory(ExtendedGpuMemory*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ExtendedGpuMemory; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_ExtendedGpuMemory = { + /*pClassDef=*/ &__nvoc_class_def_ExtendedGpuMemory, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_ExtendedGpuMemory, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_Memory = { + /*pClassDef=*/ &__nvoc_class_def_Memory, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory.__nvoc_base_Memory), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ExtendedGpuMemory_StandardMemory = { + /*pClassDef=*/ &__nvoc_class_def_StandardMemory, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ExtendedGpuMemory, __nvoc_base_StandardMemory), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_ExtendedGpuMemory = { + /*numRelatives=*/ 7, + /*relatives=*/ { + &__nvoc_rtti_ExtendedGpuMemory_ExtendedGpuMemory, + &__nvoc_rtti_ExtendedGpuMemory_StandardMemory, + &__nvoc_rtti_ExtendedGpuMemory_Memory, + &__nvoc_rtti_ExtendedGpuMemory_RmResource, + &__nvoc_rtti_ExtendedGpuMemory_RmResourceCommon, + &__nvoc_rtti_ExtendedGpuMemory_RsResource, + &__nvoc_rtti_ExtendedGpuMemory_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_ExtendedGpuMemory = +{ + /*classInfo=*/ { + /*size=*/ sizeof(ExtendedGpuMemory), + /*classId=*/ classId(ExtendedGpuMemory), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "ExtendedGpuMemory", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_ExtendedGpuMemory, + /*pCastInfo=*/ &__nvoc_castinfo_ExtendedGpuMemory, + /*pExportInfo=*/ &__nvoc_export_info_ExtendedGpuMemory +}; + +static NV_STATUS __nvoc_thunk_Memory_egmmemCheckMemInterUnmap(struct ExtendedGpuMemory *pMemory, NvBool bSubdeviceHandleProvided) { + return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), bSubdeviceHandleProvided); +} + +static NvBool __nvoc_thunk_RmResource_egmmemShareCallback(struct ExtendedGpuMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_egmmemMapTo(struct ExtendedGpuMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemGetMapAddrSpace(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_egmmemGetRefCount(struct ExtendedGpuMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_egmmemAddAdditionalDependants(struct RsClient *pClient, struct ExtendedGpuMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_egmmemControl_Prologue(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_egmmemIsGpuMapAllowed(struct ExtendedGpuMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_egmmemUnmapFrom(struct ExtendedGpuMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_egmmemControl_Epilogue(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_egmmemControlLookup(struct ExtendedGpuMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemControl(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemUnmap(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemGetMemInterMapParams(struct ExtendedGpuMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemGetMemoryMappingDescriptor(struct ExtendedGpuMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_egmmemControlFilter(struct ExtendedGpuMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_egmmemControlSerialization_Prologue(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_StandardMemory_egmmemCanCopy(struct ExtendedGpuMemory *pStandardMemory) { + return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_ExtendedGpuMemory_StandardMemory.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemIsReady(struct ExtendedGpuMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemCheckCopyPermissions(struct ExtendedGpuMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pDstGpu, pDstDevice); +} + +static void __nvoc_thunk_RsResource_egmmemPreDestruct(struct ExtendedGpuMemory *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemIsDuplicate(struct ExtendedGpuMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_egmmemControlSerialization_Epilogue(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_egmmemMap(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_egmmemAccessCallback(struct ExtendedGpuMemory *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_ExtendedGpuMemory = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_StandardMemory(StandardMemory*); +void __nvoc_dtor_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { + __nvoc_dtor_StandardMemory(&pThis->__nvoc_base_StandardMemory); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_StandardMemory(StandardMemory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_ExtendedGpuMemory(ExtendedGpuMemory *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_StandardMemory(&pThis->__nvoc_base_StandardMemory, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ExtendedGpuMemory_fail_StandardMemory; + __nvoc_init_dataField_ExtendedGpuMemory(pThis); + + status = __nvoc_egmmemConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ExtendedGpuMemory_fail__init; + goto __nvoc_ctor_ExtendedGpuMemory_exit; // Success + +__nvoc_ctor_ExtendedGpuMemory_fail__init: + __nvoc_dtor_StandardMemory(&pThis->__nvoc_base_StandardMemory); +__nvoc_ctor_ExtendedGpuMemory_fail_StandardMemory: +__nvoc_ctor_ExtendedGpuMemory_exit: + + return status; +} + +static void __nvoc_init_funcTable_ExtendedGpuMemory_1(ExtendedGpuMemory *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__egmmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_egmmemCheckMemInterUnmap; + + pThis->__egmmemShareCallback__ = &__nvoc_thunk_RmResource_egmmemShareCallback; + + pThis->__egmmemMapTo__ = &__nvoc_thunk_RsResource_egmmemMapTo; + + pThis->__egmmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_egmmemGetMapAddrSpace; + + pThis->__egmmemGetRefCount__ = &__nvoc_thunk_RsResource_egmmemGetRefCount; + + pThis->__egmmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_egmmemAddAdditionalDependants; + + pThis->__egmmemControl_Prologue__ = &__nvoc_thunk_RmResource_egmmemControl_Prologue; + + pThis->__egmmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_egmmemIsGpuMapAllowed; + + pThis->__egmmemUnmapFrom__ = &__nvoc_thunk_RsResource_egmmemUnmapFrom; + + pThis->__egmmemControl_Epilogue__ = &__nvoc_thunk_RmResource_egmmemControl_Epilogue; + + pThis->__egmmemControlLookup__ = &__nvoc_thunk_RsResource_egmmemControlLookup; + + pThis->__egmmemControl__ = &__nvoc_thunk_Memory_egmmemControl; + + pThis->__egmmemUnmap__ = &__nvoc_thunk_Memory_egmmemUnmap; + + pThis->__egmmemGetMemInterMapParams__ = &__nvoc_thunk_Memory_egmmemGetMemInterMapParams; + + pThis->__egmmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_egmmemGetMemoryMappingDescriptor; + + pThis->__egmmemControlFilter__ = &__nvoc_thunk_RsResource_egmmemControlFilter; + + pThis->__egmmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_egmmemControlSerialization_Prologue; + + pThis->__egmmemCanCopy__ = &__nvoc_thunk_StandardMemory_egmmemCanCopy; + + pThis->__egmmemIsReady__ = &__nvoc_thunk_Memory_egmmemIsReady; + + pThis->__egmmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_egmmemCheckCopyPermissions; + + pThis->__egmmemPreDestruct__ = &__nvoc_thunk_RsResource_egmmemPreDestruct; + + pThis->__egmmemIsDuplicate__ = &__nvoc_thunk_Memory_egmmemIsDuplicate; + + pThis->__egmmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_egmmemControlSerialization_Epilogue; + + pThis->__egmmemMap__ = &__nvoc_thunk_Memory_egmmemMap; + + pThis->__egmmemAccessCallback__ = &__nvoc_thunk_RmResource_egmmemAccessCallback; +} + +void __nvoc_init_funcTable_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { + __nvoc_init_funcTable_ExtendedGpuMemory_1(pThis); +} + +void __nvoc_init_StandardMemory(StandardMemory*); +void __nvoc_init_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { + pThis->__nvoc_pbase_ExtendedGpuMemory = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource; + pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory; + pThis->__nvoc_pbase_StandardMemory = &pThis->__nvoc_base_StandardMemory; + __nvoc_init_StandardMemory(&pThis->__nvoc_base_StandardMemory); + __nvoc_init_funcTable_ExtendedGpuMemory(pThis); +} + +NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + ExtendedGpuMemory *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ExtendedGpuMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(ExtendedGpuMemory)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ExtendedGpuMemory); + + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_ExtendedGpuMemory(pThis); + status = __nvoc_ctor_ExtendedGpuMemory(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_ExtendedGpuMemory_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_ExtendedGpuMemory_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ExtendedGpuMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_ExtendedGpuMemory(ExtendedGpuMemory **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_ExtendedGpuMemory(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_egm_mem_nvoc.h b/src/nvidia/generated/g_egm_mem_nvoc.h new file mode 100644 index 0000000000..b9a5cc6eda --- /dev/null +++ b/src/nvidia/generated/g_egm_mem_nvoc.h @@ -0,0 +1,257 @@ +#ifndef _G_EGM_MEM_NVOC_H_ +#define _G_EGM_MEM_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_egm_mem_nvoc.h" + +#ifndef _EGM_MEMORY_H_ +#define _EGM_MEMORY_H_ + +#include "mem_mgr/video_mem.h" +#include "mem_mgr/system_mem.h" + + +/*! + * Allocator for Extended GPU Memory (EGM) + * EGM is CPU_MEM accessed like peer GPU_MEM + */ +#ifdef NVOC_EGM_MEM_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct ExtendedGpuMemory { + const struct NVOC_RTTI *__nvoc_rtti; + struct StandardMemory __nvoc_base_StandardMemory; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct Memory *__nvoc_pbase_Memory; + struct StandardMemory *__nvoc_pbase_StandardMemory; + struct ExtendedGpuMemory *__nvoc_pbase_ExtendedGpuMemory; + NV_STATUS (*__egmmemCheckMemInterUnmap__)(struct ExtendedGpuMemory *, NvBool); + NvBool (*__egmmemShareCallback__)(struct ExtendedGpuMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__egmmemMapTo__)(struct ExtendedGpuMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__egmmemGetMapAddrSpace__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__egmmemGetRefCount__)(struct ExtendedGpuMemory *); + void (*__egmmemAddAdditionalDependants__)(struct RsClient *, struct ExtendedGpuMemory *, RsResourceRef *); + NV_STATUS (*__egmmemControl_Prologue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__egmmemIsGpuMapAllowed__)(struct ExtendedGpuMemory *, struct OBJGPU *); + NV_STATUS (*__egmmemUnmapFrom__)(struct ExtendedGpuMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__egmmemControl_Epilogue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__egmmemControlLookup__)(struct ExtendedGpuMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__egmmemControl__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__egmmemUnmap__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__egmmemGetMemInterMapParams__)(struct ExtendedGpuMemory *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__egmmemGetMemoryMappingDescriptor__)(struct ExtendedGpuMemory *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__egmmemControlFilter__)(struct ExtendedGpuMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__egmmemControlSerialization_Prologue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__egmmemCanCopy__)(struct ExtendedGpuMemory *); + NV_STATUS (*__egmmemIsReady__)(struct ExtendedGpuMemory *, NvBool); + NV_STATUS (*__egmmemCheckCopyPermissions__)(struct ExtendedGpuMemory *, struct OBJGPU *, struct Device *); + void (*__egmmemPreDestruct__)(struct ExtendedGpuMemory *); + NV_STATUS (*__egmmemIsDuplicate__)(struct ExtendedGpuMemory *, NvHandle, NvBool *); + void (*__egmmemControlSerialization_Epilogue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__egmmemMap__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__egmmemAccessCallback__)(struct ExtendedGpuMemory *, struct RsClient *, void *, RsAccessRight); +}; + +#ifndef __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ +#define __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ +typedef struct ExtendedGpuMemory ExtendedGpuMemory; +#endif /* __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ExtendedGpuMemory +#define __nvoc_class_id_ExtendedGpuMemory 0xeffa5c +#endif /* __nvoc_class_id_ExtendedGpuMemory */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ExtendedGpuMemory; + +#define __staticCast_ExtendedGpuMemory(pThis) \ + ((pThis)->__nvoc_pbase_ExtendedGpuMemory) + +#ifdef __nvoc_egm_mem_h_disabled +#define __dynamicCast_ExtendedGpuMemory(pThis) ((ExtendedGpuMemory*)NULL) +#else //__nvoc_egm_mem_h_disabled +#define __dynamicCast_ExtendedGpuMemory(pThis) \ + ((ExtendedGpuMemory*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ExtendedGpuMemory))) +#endif //__nvoc_egm_mem_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_ExtendedGpuMemory(ExtendedGpuMemory**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_ExtendedGpuMemory(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_ExtendedGpuMemory((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define egmmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) egmmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define egmmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) egmmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define egmmemMapTo(pResource, pParams) egmmemMapTo_DISPATCH(pResource, pParams) +#define egmmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) egmmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define egmmemGetRefCount(pResource) egmmemGetRefCount_DISPATCH(pResource) +#define egmmemAddAdditionalDependants(pClient, pResource, pReference) egmmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define egmmemControl_Prologue(pResource, pCallContext, pParams) egmmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define egmmemIsGpuMapAllowed(pMemory, pGpu) egmmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define egmmemUnmapFrom(pResource, pParams) egmmemUnmapFrom_DISPATCH(pResource, pParams) +#define egmmemControl_Epilogue(pResource, pCallContext, pParams) egmmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define egmmemControlLookup(pResource, pParams, ppEntry) egmmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define egmmemControl(pMemory, pCallContext, pParams) egmmemControl_DISPATCH(pMemory, pCallContext, pParams) +#define egmmemUnmap(pMemory, pCallContext, pCpuMapping) egmmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define egmmemGetMemInterMapParams(pMemory, pParams) egmmemGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define egmmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) egmmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define egmmemControlFilter(pResource, pCallContext, pParams) egmmemControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define egmmemControlSerialization_Prologue(pResource, pCallContext, pParams) egmmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define egmmemCanCopy(pStandardMemory) egmmemCanCopy_DISPATCH(pStandardMemory) +#define egmmemIsReady(pMemory, bCopyConstructorContext) egmmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define egmmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) egmmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) +#define egmmemPreDestruct(pResource) egmmemPreDestruct_DISPATCH(pResource) +#define egmmemIsDuplicate(pMemory, hMemory, pDuplicate) egmmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define egmmemControlSerialization_Epilogue(pResource, pCallContext, pParams) egmmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define egmmemMap(pMemory, pCallContext, pParams, pCpuMapping) egmmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) +#define egmmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) egmmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +static inline NV_STATUS egmmemCheckMemInterUnmap_DISPATCH(struct ExtendedGpuMemory *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__egmmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); +} + +static inline NvBool egmmemShareCallback_DISPATCH(struct ExtendedGpuMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__egmmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS egmmemMapTo_DISPATCH(struct ExtendedGpuMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__egmmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS egmmemGetMapAddrSpace_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__egmmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 egmmemGetRefCount_DISPATCH(struct ExtendedGpuMemory *pResource) { + return pResource->__egmmemGetRefCount__(pResource); +} + +static inline void egmmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ExtendedGpuMemory *pResource, RsResourceRef *pReference) { + pResource->__egmmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS egmmemControl_Prologue_DISPATCH(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__egmmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool egmmemIsGpuMapAllowed_DISPATCH(struct ExtendedGpuMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__egmmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS egmmemUnmapFrom_DISPATCH(struct ExtendedGpuMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__egmmemUnmapFrom__(pResource, pParams); +} + +static inline void egmmemControl_Epilogue_DISPATCH(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__egmmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS egmmemControlLookup_DISPATCH(struct ExtendedGpuMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__egmmemControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS egmmemControl_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__egmmemControl__(pMemory, pCallContext, pParams); +} + +static inline NV_STATUS egmmemUnmap_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__egmmemUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS egmmemGetMemInterMapParams_DISPATCH(struct ExtendedGpuMemory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__egmmemGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS egmmemGetMemoryMappingDescriptor_DISPATCH(struct ExtendedGpuMemory *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__egmmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS egmmemControlFilter_DISPATCH(struct ExtendedGpuMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__egmmemControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS egmmemControlSerialization_Prologue_DISPATCH(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__egmmemControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool egmmemCanCopy_DISPATCH(struct ExtendedGpuMemory *pStandardMemory) { + return pStandardMemory->__egmmemCanCopy__(pStandardMemory); +} + +static inline NV_STATUS egmmemIsReady_DISPATCH(struct ExtendedGpuMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__egmmemIsReady__(pMemory, bCopyConstructorContext); +} + +static inline NV_STATUS egmmemCheckCopyPermissions_DISPATCH(struct ExtendedGpuMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__egmmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); +} + +static inline void egmmemPreDestruct_DISPATCH(struct ExtendedGpuMemory *pResource) { + pResource->__egmmemPreDestruct__(pResource); +} + +static inline NV_STATUS egmmemIsDuplicate_DISPATCH(struct ExtendedGpuMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__egmmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + +static inline void egmmemControlSerialization_Epilogue_DISPATCH(struct ExtendedGpuMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__egmmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS egmmemMap_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pMemory->__egmmemMap__(pMemory, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool egmmemAccessCallback_DISPATCH(struct ExtendedGpuMemory *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__egmmemAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS egmmemConstruct_IMPL(struct ExtendedGpuMemory *arg_pStandardMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_egmmemConstruct(arg_pStandardMemory, arg_pCallContext, arg_pParams) egmmemConstruct_IMPL(arg_pStandardMemory, arg_pCallContext, arg_pParams) +NV_STATUS egmmemValidateParams_IMPL(struct OBJGPU *pGpu, NvHandle hClient, NV_MEMORY_ALLOCATION_PARAMS *pAllocData); + +#define egmmemValidateParams(pGpu, hClient, pAllocData) egmmemValidateParams_IMPL(pGpu, hClient, pAllocData) +#undef PRIVATE_FIELD + + +NV_STATUS egmmemAllocResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, + MEMORY_ALLOCATION_REQUEST *pAllocRequest, FB_ALLOC_INFO *pFbAllocInfo); + +#endif // _EGM_MEMORY_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_EGM_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_eng_desc_nvoc.h b/src/nvidia/generated/g_eng_desc_nvoc.h index ddd1484f47..a311f40563 100644 --- a/src/nvidia/generated/g_eng_desc_nvoc.h +++ b/src/nvidia/generated/g_eng_desc_nvoc.h @@ -1340,6 +1340,18 @@ typedef struct OBJGMMU OBJGMMU; #endif /* __nvoc_class_id_OBJGMMU */ +struct ConfidentialCompute; + +#ifndef __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ +#define __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ +typedef struct ConfidentialCompute ConfidentialCompute; +#endif /* __NVOC_CLASS_ConfidentialCompute_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConfidentialCompute +#define __nvoc_class_id_ConfidentialCompute 0x9798cc +#endif /* __nvoc_class_id_ConfidentialCompute */ + + struct KernelCcu; #ifndef __NVOC_CLASS_KernelCcu_TYPEDEF__ @@ -1449,6 +1461,7 @@ typedef struct KernelCcu KernelCcu; #define ENG_KERNEL_NVLINK MKENGDESC(classId(KernelNvlink), 0) #define ENG_GMMU MKENGDESC(classId(OBJGMMU), 0) #define ENG_KERNEL_GMMU MKENGDESC(classId(KernelGmmu), 0) +#define ENG_CONF_COMPUTE MKENGDESC(classId(ConfidentialCompute), 0) #define ENG_KERNEL_CCU MKENGDESC(classId(KernelCcu), 0) // Indexed CE engine tag reference diff --git a/src/nvidia/generated/g_event_nvoc.h b/src/nvidia/generated/g_event_nvoc.h index 830f5b92d9..cff1aa55de 100644 --- a/src/nvidia/generated/g_event_nvoc.h +++ b/src/nvidia/generated/g_event_nvoc.h @@ -542,7 +542,7 @@ NV_STATUS CliGetEventNotificationList(NvHandle hClient, NvHandle hObject, struct INotifier **ppNotifier, PEVENTNOTIFICATION **pppEventNotification); -NV_STATUS registerEventNotification(PEVENTNOTIFICATION*, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvP64, NvBool); +NV_STATUS registerEventNotification(PEVENTNOTIFICATION*, struct RsClient *, NvHandle, NvHandle, NvU32, NvU32, NvP64, NvBool); NV_STATUS unregisterEventNotification(PEVENTNOTIFICATION*, NvHandle, NvHandle, NvHandle); NV_STATUS unregisterEventNotificationWithData(PEVENTNOTIFICATION *, NvHandle, NvHandle, NvHandle, NvBool, NvP64); NV_STATUS bindEventNotificationToSubdevice(PEVENTNOTIFICATION, NvHandle, NvU32); diff --git a/src/nvidia/generated/g_fabric_nvoc.h b/src/nvidia/generated/g_fabric_nvoc.h index fb07d76156..8727dce4f9 100644 --- a/src/nvidia/generated/g_fabric_nvoc.h +++ b/src/nvidia/generated/g_fabric_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.c b/src/nvidia/generated/g_fabric_vaspace_nvoc.c index ee1e4a19ef..19c0e893f2 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.c +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.c @@ -126,7 +126,7 @@ static NvBool __nvoc_thunk_OBJVASPACE_fabricvaspaceIsAtsEnabled(struct FABRIC_VA return vaspaceIsAtsEnabled((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset)); } -static NvU32 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetBigPageSize(struct FABRIC_VASPACE *pVAS) { +static NvU64 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetBigPageSize(struct FABRIC_VASPACE *pVAS) { return vaspaceGetBigPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset)); } diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.h b/src/nvidia/generated/g_fabric_vaspace_nvoc.h index 926df7dbda..5aee210e9f 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.h +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,6 +48,7 @@ extern "C" { #include "gpu/mem_mgr/heap.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "ctrl/ctrl0080/ctrl0080dma.h" +#include "ctrl/ctrl90f1.h" #include "gpu/mem_mgr/mem_desc.h" #include "containers/list.h" @@ -92,7 +93,7 @@ struct FABRIC_VASPACE { NvBool (*__fabricvaspaceIsInternalVaRestricted__)(struct FABRIC_VASPACE *); NvU32 (*__fabricvaspaceGetFlags__)(struct FABRIC_VASPACE *); NvBool (*__fabricvaspaceIsAtsEnabled__)(struct FABRIC_VASPACE *); - NvU32 (*__fabricvaspaceGetBigPageSize__)(struct FABRIC_VASPACE *); + NvU64 (*__fabricvaspaceGetBigPageSize__)(struct FABRIC_VASPACE *); NV_STATUS (*__fabricvaspaceGetPteInfo__)(struct FABRIC_VASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); NvU64 (*__fabricvaspaceGetVaLimit__)(struct FABRIC_VASPACE *); PMEMORY_DESCRIPTOR (*__fabricvaspaceGetPageDirBase__)(struct FABRIC_VASPACE *, struct OBJGPU *); @@ -258,7 +259,7 @@ static inline NvBool fabricvaspaceIsAtsEnabled_DISPATCH(struct FABRIC_VASPACE *p return pVAS->__fabricvaspaceIsAtsEnabled__(pVAS); } -static inline NvU32 fabricvaspaceGetBigPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS) { +static inline NvU64 fabricvaspaceGetBigPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS) { return pVAS->__fabricvaspaceGetBigPageSize__(pVAS); } @@ -446,6 +447,38 @@ static inline NV_STATUS fabricvaspaceInitUCRange(struct FABRIC_VASPACE *pFabricV #define fabricvaspaceInitUCRange(pFabricVAS, pGpu, ucFabricBase, ucFabricSize) fabricvaspaceInitUCRange_IMPL(pFabricVAS, pGpu, ucFabricBase, ucFabricSize) #endif //__nvoc_fabric_vaspace_h_disabled +void fabricvaspaceClearUCRange_IMPL(struct FABRIC_VASPACE *pFabricVAS); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline void fabricvaspaceClearUCRange(struct FABRIC_VASPACE *pFabricVAS) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceClearUCRange(pFabricVAS) fabricvaspaceClearUCRange_IMPL(pFabricVAS) +#endif //__nvoc_fabric_vaspace_h_disabled + +NV_STATUS fabricvaspaceGetPageLevelInfo_IMPL(struct FABRIC_VASPACE *pFabricVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS *pParams); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline NV_STATUS fabricvaspaceGetPageLevelInfo(struct FABRIC_VASPACE *pFabricVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceGetPageLevelInfo(pFabricVAS, pGpu, pParams) fabricvaspaceGetPageLevelInfo_IMPL(pFabricVAS, pGpu, pParams) +#endif //__nvoc_fabric_vaspace_h_disabled + +NvBool fabricvaspaceIsInUse_IMPL(struct FABRIC_VASPACE *pFabricVAS); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline NvBool fabricvaspaceIsInUse(struct FABRIC_VASPACE *pFabricVAS) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); + return NV_FALSE; +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceIsInUse(pFabricVAS) fabricvaspaceIsInUse_IMPL(pFabricVAS) +#endif //__nvoc_fabric_vaspace_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_fbsr_nvoc.c b/src/nvidia/generated/g_fbsr_nvoc.c index cdc63a610e..c0d8ba2d77 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.c +++ b/src/nvidia/generated/g_fbsr_nvoc.c @@ -109,29 +109,34 @@ static void __nvoc_init_funcTable_OBJFBSR_1(OBJFBSR *pThis, RmHalspecOwner *pRmh PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- fbsrBegin - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__fbsrBegin__ = &fbsrBegin_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ - { - pThis->__fbsrBegin__ = &fbsrBegin_GM107; - } + pThis->__fbsrBegin__ = &fbsrBegin_GM107; + } + else + { + pThis->__fbsrBegin__ = &fbsrBegin_GA100; } // Hal function -- fbsrEnd - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + { + pThis->__fbsrEnd__ = &fbsrEnd_GM107; + } + else + { + pThis->__fbsrEnd__ = &fbsrEnd_GA100; + } + + // Hal function -- fbsrSendMemsysProgramRawCompressionMode + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__fbsrSendMemsysProgramRawCompressionMode__ = &fbsrSendMemsysProgramRawCompressionMode_GA100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__fbsrEnd__ = &fbsrEnd_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ - { - pThis->__fbsrEnd__ = &fbsrEnd_GM107; - } + pThis->__fbsrSendMemsysProgramRawCompressionMode__ = &fbsrSendMemsysProgramRawCompressionMode_56cd7a; } } diff --git a/src/nvidia/generated/g_fbsr_nvoc.h b/src/nvidia/generated/g_fbsr_nvoc.h index d77d7da234..2472a65b16 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.h +++ b/src/nvidia/generated/g_fbsr_nvoc.h @@ -103,6 +103,7 @@ struct OBJFBSR { struct OBJFBSR *__nvoc_pbase_OBJFBSR; NV_STATUS (*__fbsrBegin__)(struct OBJGPU *, struct OBJFBSR *, FBSR_OP_TYPE); NV_STATUS (*__fbsrEnd__)(struct OBJGPU *, struct OBJFBSR *); + NV_STATUS (*__fbsrSendMemsysProgramRawCompressionMode__)(struct OBJGPU *, struct OBJFBSR *, NvBool); NvU32 type; struct OBJCE *pCe; FBSR_OP_TYPE op; @@ -158,6 +159,8 @@ NV_STATUS __nvoc_objCreate_OBJFBSR(OBJFBSR**, Dynamic*, NvU32); #define fbsrBegin_HAL(pGpu, pFbsr, op) fbsrBegin_DISPATCH(pGpu, pFbsr, op) #define fbsrEnd(pGpu, pFbsr) fbsrEnd_DISPATCH(pGpu, pFbsr) #define fbsrEnd_HAL(pGpu, pFbsr) fbsrEnd_DISPATCH(pGpu, pFbsr) +#define fbsrSendMemsysProgramRawCompressionMode(pGpu, pFbsr, bRawMode) fbsrSendMemsysProgramRawCompressionMode_DISPATCH(pGpu, pFbsr, bRawMode) +#define fbsrSendMemsysProgramRawCompressionMode_HAL(pGpu, pFbsr, bRawMode) fbsrSendMemsysProgramRawCompressionMode_DISPATCH(pGpu, pFbsr, bRawMode) static inline NV_STATUS fbsrCreateChannelForCopy_46f6a7(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { return NV_ERR_NOT_SUPPORTED; } @@ -262,6 +265,16 @@ static inline NV_STATUS fbsrEnd_DISPATCH(struct OBJGPU *pGpu, struct OBJFBSR *pF return pFbsr->__fbsrEnd__(pGpu, pFbsr); } +NV_STATUS fbsrSendMemsysProgramRawCompressionMode_GA100(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, NvBool bRawMode); + +static inline NV_STATUS fbsrSendMemsysProgramRawCompressionMode_56cd7a(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, NvBool bRawMode) { + return NV_OK; +} + +static inline NV_STATUS fbsrSendMemsysProgramRawCompressionMode_DISPATCH(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, NvBool bRawMode) { + return pFbsr->__fbsrSendMemsysProgramRawCompressionMode__(pGpu, pFbsr, bRawMode); +} + NV_STATUS fbsrObjectInit_IMPL(struct OBJFBSR *pFbsr, NvU32 arg0); #ifdef __nvoc_fbsr_h_disabled diff --git a/src/nvidia/generated/g_fecs_event_list_nvoc.h b/src/nvidia/generated/g_fecs_event_list_nvoc.h index 05c45d2a1e..d14386741d 100644 --- a/src/nvidia/generated/g_fecs_event_list_nvoc.h +++ b/src/nvidia/generated/g_fecs_event_list_nvoc.h @@ -44,6 +44,7 @@ extern "C" { #include "class/cl90cdfecs.h" #include "containers/multimap.h" #include "resserv/resserv.h" +#include "rmapi/client.h" #include "ctrl/ctrl2080/ctrl2080gr.h" // NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD @@ -127,7 +128,7 @@ ct_assert(sizeof(FECS_EVENT_RECORD_OUTPUT) == sizeof(NV_EVENT_BUFFER_RECORD_HEAD NV_STATUS fecsAddBindpoint ( OBJGPU *pGpu, - struct RsClient *pClient, + struct RmClient *pClient, RsResourceRef *pEventBufferRef, NvHandle hNotifier, NvBool bAllUsers, diff --git a/src/nvidia/generated/g_fla_mem_nvoc.c b/src/nvidia/generated/g_fla_mem_nvoc.c index 268fa7b905..4eb683b598 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.c +++ b/src/nvidia/generated/g_fla_mem_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_flamemIsReady(struct FlaMemory *pMemory, Nv return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_flamemCheckCopyPermissions(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_flamemCheckCopyPermissions(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_flamemPreDestruct(struct FlaMemory *pResource) { diff --git a/src/nvidia/generated/g_fla_mem_nvoc.h b/src/nvidia/generated/g_fla_mem_nvoc.h index 88ec60e82c..57ce040512 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.h +++ b/src/nvidia/generated/g_fla_mem_nvoc.h @@ -73,7 +73,7 @@ struct FlaMemory { NV_STATUS (*__flamemControlFilter__)(struct FlaMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemControlSerialization_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemIsReady__)(struct FlaMemory *, NvBool); - NV_STATUS (*__flamemCheckCopyPermissions__)(struct FlaMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__flamemCheckCopyPermissions__)(struct FlaMemory *, struct OBJGPU *, struct Device *); void (*__flamemPreDestruct__)(struct FlaMemory *); NV_STATUS (*__flamemIsDuplicate__)(struct FlaMemory *, NvHandle, NvBool *); void (*__flamemControlSerialization_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -132,7 +132,7 @@ NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory**, Dynamic*, NvU32, CALL_CONTEXT #define flamemControlFilter(pResource, pCallContext, pParams) flamemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define flamemControlSerialization_Prologue(pResource, pCallContext, pParams) flamemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define flamemIsReady(pMemory, bCopyConstructorContext) flamemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define flamemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) flamemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define flamemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) flamemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define flamemPreDestruct(pResource) flamemPreDestruct_DISPATCH(pResource) #define flamemIsDuplicate(pMemory, hMemory, pDuplicate) flamemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define flamemControlSerialization_Epilogue(pResource, pCallContext, pParams) flamemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -222,8 +222,8 @@ static inline NV_STATUS flamemIsReady_DISPATCH(struct FlaMemory *pMemory, NvBool return pMemory->__flamemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS flamemCheckCopyPermissions_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__flamemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS flamemCheckCopyPermissions_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__flamemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void flamemPreDestruct_DISPATCH(struct FlaMemory *pResource) { diff --git a/src/nvidia/generated/g_gpu_access_nvoc.h b/src/nvidia/generated/g_gpu_access_nvoc.h index 6116af33c3..26e77e7155 100644 --- a/src/nvidia/generated/g_gpu_access_nvoc.h +++ b/src/nvidia/generated/g_gpu_access_nvoc.h @@ -246,6 +246,8 @@ void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 v #define GPU_VREG_IDX_RD_DRF(g,d,r,i,f) (((GPU_VREG_RD32(g, NV ## d ## r(i)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) #define GPU_VREG_FLD_IDX_WR_DRF_DEF(g,d,r,i,f,c) GPU_VREG_WR32(g, NV##d##r(i),(GPU_VREG_RD32(g,NV##d##r(i))&~(GPU_DRF_MASK(NV##d##r##f)<bDeviceProfiling; + struct GPUInstanceSubscription_PRIVATE *pGPUInstanceSubscription_PRIVATE = (struct GPUInstanceSubscription_PRIVATE *)pGPUInstanceSubscription; + return pGPUInstanceSubscription_PRIVATE->bDeviceProfiling; } NV_STATUS gisubscriptionGetGPUInstanceSubscription_IMPL(struct RsClient *arg0, NvHandle arg1, struct GPUInstanceSubscription **arg2); diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.h b/src/nvidia/generated/g_gpu_mgr_nvoc.h index 9aec97a53d..1ed26c67ca 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.h @@ -51,7 +51,6 @@ struct OBJGPU; #include "ctrl/ctrl2080/ctrl2080internal.h" #include "ctrl/ctrlc637.h" #include "nvoc/utility.h" -#include "nv_firmware_types.h" #include "gpu_mgr/gpu_mgr_sli.h" @@ -121,6 +120,15 @@ typedef struct _def_gpumgr_save_vbios_state void *pSaveRegsOpaque; //setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0))); } pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0))); + pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322, ((NvBool)(0 != 0))); + + // NVOC Property Hal field -- PDB_PROP_GPU_CC_FEATURE_CAPABLE + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_APM_FEATURE_CAPABLE + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF, ((NvBool)(0 == 0))); + } pThis->boardId = ~0; @@ -325,6 +365,8 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { { pThis->bRecheckSliSupportAtResume = ((NvBool)(0 == 0)); } + + pThis->bIsGspOwnedFaultBuffersEnabled = ((NvBool)(0 != 0)); } NV_STATUS __nvoc_ctor_Object(Object* ); @@ -368,97 +410,94 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- gpuConstructDeviceInfoTable - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; - } - // default - else - { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; - } + pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; + } + // default + else + { + pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; } // Hal function -- gpuWriteBusConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107; + pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GH100; + pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107; } // Hal function -- gpuReadBusConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107; + pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100; + pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107; } // Hal function -- gpuReadBusConfigRegEx - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107; + pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_5baef9; + pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107; } // Hal function -- gpuReadFunctionConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107; + pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9; + pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107; } // Hal function -- gpuWriteFunctionConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107; + pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9; + pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107; } // Hal function -- gpuWriteFunctionConfigRegEx - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; + pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9; + pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; } // Hal function -- gpuGetIdInfo - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; + pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100; + pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; } // Hal function -- gpuHandleSanityCheckRegReadError - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; + pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; } // Hal function -- gpuHandleSecFault @@ -473,11 +512,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { } // Hal function -- gpuGetChildrenPresent - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */ - { - pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU104; } @@ -489,25 +524,25 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */ + { + pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU102; + } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_AD102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100; - } // Hal function -- gpuGetClassDescriptorList - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */ - { - pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU104; } @@ -523,72 +558,69 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */ + { + pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU102; + } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_AD102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100; - } // Hal function -- gpuGetPhysAddrWidth - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; + pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100; + pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; } // Hal function -- gpuFuseSupportsDisplay - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; + pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; + pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + else { - pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_491d52; + pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; } // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; - } + pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; } // Hal function -- gpuReadDeviceId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GM107; + pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; + pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GM107; } // Hal function -- gpuGetFlaVasSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GH100; } @@ -596,6 +628,32 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_474d46; } + else + { + pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; + } + + // Hal function -- gpuDetermineSelfHostedMode + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_KERNEL_GH100; + } + // default + else + { + pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_b3696a; + } + + // Hal function -- gpuDetermineMIGSupport + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_GH100; + } + // default + else + { + pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a; + } // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ @@ -618,6 +676,39 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_491d52; } + + // Hal function -- gpuIsCCEnabledInHw + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GH100; + } + // default + else + { + pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52; + } + + // Hal function -- gpuIsDevModeEnabledInHw + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_GH100; + } + // default + else + { + pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_491d52; + } + + // Hal function -- gpuIsCtxBufAllocInPmaSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_GA100; + } + // default + else + { + pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_491d52; + } } void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 6e5f1bc823..32228ba092 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,6 +73,7 @@ typedef struct GPUATTACHARG GPUATTACHARG; #include "gpu/gpu_timeout.h" #include "gpu/gpu_access.h" #include "gpu/gpu_shared_data_map.h" +#include "gpu/kern_gpu_power.h" #include "platform/acpi_common.h" #include "gpu/gpu_acpi_data.h" @@ -299,7 +300,7 @@ typedef enum COMPUTE_BRANDING_TYPE_TESLA, } COMPUTE_BRANDING_TYPE; -#define OOR_ARCH_DEF(x) \ +#define OOR_ARCH_DEF(x) \ NV_ENUM_ENTRY(x, OOR_ARCH_X86_64, 0x00000000) \ NV_ENUM_ENTRY(x, OOR_ARCH_PPC64LE, 0x00000001) \ NV_ENUM_ENTRY(x, OOR_ARCH_ARM, 0x00000002) \ @@ -318,8 +319,61 @@ typedef struct { NvU32 classId; NvU32 instances; + + /*! + * Pointer to the @ref NVOC_CLASS_INFO for the concrete class to instantiate + * for this child. + */ + const NVOC_CLASS_INFO *pClassInfo; } GPUCHILDPRESENT; +/*! + * @brief Generates an entry for a list of @ref GPUCHILDPRESENT objects for a + * class of the given name + * + * @param[in] _childClassName + * Name of the class for the entry + * @param[in] _instances + * Number of instances of the child that may be present; see + * @ref GPUCHILDPRESENT::instances + * + * @return An entry suitable for a list of @ref GPUCHILDPRESENT for the given + * child of @ref OBJGPU + */ +#define GPU_CHILD_PRESENT(_childClassName, _instances) \ + GPU_CHILD_PRESENT_POLYMORPHIC(_childClassName, (_instances), _childClassName) + +/*! + * @brief Generates an entry for a list of @ref GPUCHILDPRESENT objects that + * allows the @ref OBJGPU child to instantiate a sub-class of the base + * @ref OBJGPU child class. + * + * @details The intention of this macro is to allow a list of + * @ref GPUCHILDPRESENT to essentially state "this child should be + * present with this concrete class type". This allows for different + * @ref GPUCHILDPRESENT lists to request different classes with + * different behavior via sub-classes, for the same basic @ref OBJGPU + * child. + * + * @param[in] _childClassName + * Name of the base class at which @ref OBJGPU points + * @param[in] _instances + * Number of instances of the child that may be present; see + * @ref GPUCHILDPRESENT::instances + * @param[in] _concreteClassName + * Name of the sub-class of _childClassName that should actually be + * instantiated + * + * @return An entry suitable for a list of @ref GPUCHILDPRESENT for the given + * child of @ref OBJGPU with the given concrete class type. + */ +#define GPU_CHILD_PRESENT_POLYMORPHIC(_childClassName, _instances, _concreteClassName) \ + { \ + .classId = classId(_childClassName), \ + .instances = (_instances), \ + .pClassInfo = classInfo(_concreteClassName) \ + } + // GPU Child Order Flags #define GCO_LIST_INIT NVBIT(0) // entry is used for init ordering (DO NOT USE) #define GCO_LIST_LOAD NVBIT(1) // entry is used for load and postload ordering (DO NOT USE) @@ -490,16 +544,6 @@ typedef struct NvU32 PCIRevisionID; NvU32 Subrevision; - // - // ImplentationExternal and ArchitectureExternal are only valid if they are - // not both zero. They are used when we want to report a different - // arch/imp to an external client. For example, MCP73 is almost the same - // as MCP67, so we report the MCP67 arch/imp to external clients of MCP73. - // (If an MCP73 client really needs to know that it is running on MCP73 - // instead of MCP67, it should check capability bits.) - // - NvU32 ImplementationExternal; - NvU32 ArchitectureExternal; } GPUIDINFO; @@ -509,7 +553,6 @@ typedef struct NvU32 arch; NvU32 majorRev; NvU32 minorRev; - NvU32 devIDStrap; NvU32 minorExtRev; } PMCBOOT0; @@ -519,7 +562,6 @@ typedef struct NvU32 arch; NvU32 majorRev; NvU32 minorRev; - NvU32 devIDStrap; NvU32 minorExtRev; } PMCBOOT42; @@ -740,6 +782,7 @@ typedef struct PSRIOV_P2P_INFO pP2PInfo; NvBool bP2PAllocated; NvU32 maxP2pGfid; + NvU32 p2pFabricPartitionId; } _GPU_SRIOV_STATE; // Max # of instances for GPU children @@ -844,11 +887,16 @@ struct OBJGPU { NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *); void (*__gpuReadDeviceId__)(struct OBJGPU *, NvU32 *, NvU32 *); NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool); + void (*__gpuDetermineSelfHostedMode__)(struct OBJGPU *); + void (*__gpuDetermineMIGSupport__)(struct OBJGPU *); NvBool (*__gpuIsAtsSupportedWithSmcMemPartitioning__)(struct OBJGPU *); NvBool (*__gpuIsSliCapableWithoutDisplay__)(struct OBJGPU *); + NvBool (*__gpuIsCCEnabledInHw__)(struct OBJGPU *); + NvBool (*__gpuIsDevModeEnabledInHw__)(struct OBJGPU *); + NvBool (*__gpuIsCtxBufAllocInPmaSupported__)(struct OBJGPU *); NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED; NvBool bVideoLinkDisabled; - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; NvU32 moduleId; NvU8 nvswitchSupport; NvBool PDB_PROP_GPU_IN_STANDBY; @@ -906,10 +954,13 @@ struct OBJGPU { NvBool PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH; NvBool PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL; NvBool PDB_PROP_GPU_IS_MOBILE; + NvBool PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC; NvBool PDB_PROP_GPU_RTD3_GC6_SUPPORTED; NvBool PDB_PROP_GPU_RTD3_GC6_ACTIVE; NvBool PDB_PROP_GPU_FAST_GC6_ACTIVE; NvBool PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED; + NvBool PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA; + NvBool PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED; NvBool PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED; NvBool PDB_PROP_GPU_GCOFF_STATE_ENTERING; NvBool PDB_PROP_GPU_GCOFF_STATE_ENTERED; @@ -926,7 +977,6 @@ struct OBJGPU { NvBool PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS; NvBool PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU; NvBool PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA; - NvBool PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA; NvBool PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED; NvBool PDB_PROP_GPU_NV_USERMODE_ENABLED; NvBool PDB_PROP_GPU_IN_FATAL_ERROR; @@ -935,6 +985,13 @@ struct OBJGPU { NvBool PDB_PROP_GPU_IS_MXM_3X; NvBool PDB_PROP_GPU_GSYNC_III_ATTACHED; NvBool PDB_PROP_GPU_QSYNC_II_ATTACHED; + NvBool PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322; + NvBool PDB_PROP_GPU_CC_FEATURE_CAPABLE; + NvBool PDB_PROP_GPU_APM_FEATURE_CAPABLE; + NvBool PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX; + NvBool PDB_PROP_GPU_SKIP_TABLE_CE_MAP; + NvBool PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF; + NvBool PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL; OS_GPU_INFO *pOsGpuInfo; OS_RM_CAPS *pOsRmCaps; NvU32 halImpl; @@ -949,6 +1006,7 @@ struct OBJGPU { NvU32 subdeviceInstance; NvS32 numaNodeId; _GPU_UUID gpuUuid; + NvBool gspRmInitialized; _GPU_PCIE_PEER_CLIQUE pciePeerClique; NvU32 i2cPortForExtdev; GPUIDINFO idInfo; @@ -1015,6 +1073,7 @@ struct OBJGPU { struct OBJGPUMON *pGpuMon; struct OBJSWENG *pSwEng; struct KernelFsp *pKernelFsp; + struct ConfidentialCompute *pConfCompute; struct KernelCcu *pKernelCcu; HWBC_LIST *pHWBCList; GPUCLDATA gpuClData; @@ -1075,6 +1134,7 @@ struct OBJGPU { NvBool bIsVirtualWithSriov; NvU32 P2PPeerGpuCount; GPU_P2P_PEER_GPU_CAPS P2PPeerGpuCaps[32]; + NvBool bIsSelfHosted; NvBool bStateLoading; NvBool bStateUnloading; NvBool bStateLoaded; @@ -1113,6 +1173,7 @@ struct OBJGPU { NvBool bIsNvidiaNvs; NvBool bIsTitan; NvBool bIsTesla; + NvBool bIsAC; BRANDING_TYPE brandingCache; NvBool bComputePolicyTimesliceSupported; NvBool bGlobalPoisonFuseEnabled; @@ -1125,6 +1186,7 @@ struct OBJGPU { NvBool bRecheckSliSupportAtResume; _GPU_SLI_PEER peer[2]; NvBool bIsGspOwnedFaultBuffersEnabled; + _GPU_GC6_STATE gc6State; }; #ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__ @@ -1154,6 +1216,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_RTD3_GC6_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GC6_SUPPORTED #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_CAST #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_NAME PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU +#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_CAST +#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_NAME PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K #define PDB_PROP_GPU_INACCESSIBLE_BASE_CAST #define PDB_PROP_GPU_INACCESSIBLE_BASE_NAME PDB_PROP_GPU_INACCESSIBLE #define PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH_BASE_CAST @@ -1194,12 +1258,18 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_CAST #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE +#define PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC_BASE_CAST +#define PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC_BASE_NAME PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_NAME PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED #define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_CAST #define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_NAME PDB_PROP_GPU_RM_UNLINKED_SLI +#define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_CAST +#define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_NAME PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL #define PDB_PROP_GPU_IS_UEFI_BASE_CAST #define PDB_PROP_GPU_IS_UEFI_BASE_NAME PDB_PROP_GPU_IS_UEFI +#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST +#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_CAST #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_NAME PDB_PROP_GPU_IN_SECONDARY_BUS_RESET #define PDB_PROP_GPU_OPTIMIZE_SPARSE_TEXTURE_BY_DEFAULT_BASE_CAST @@ -1214,6 +1284,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_IS_MOBILE_BASE_NAME PDB_PROP_GPU_IS_MOBILE #define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_CAST #define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_RTD3_GC6_ACTIVE +#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_CAST +#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_CC_FEATURE_CAPABLE #define PDB_PROP_GPU_ALTERNATE_TREE_ENABLED_BASE_CAST #define PDB_PROP_GPU_ALTERNATE_TREE_ENABLED_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_ENABLED #define PDB_PROP_GPU_PERSISTENT_SW_STATE_BASE_CAST @@ -1274,12 +1346,16 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_IS_MXM_3X_BASE_NAME PDB_PROP_GPU_IS_MXM_3X #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_CAST #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS +#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_CAST +#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_NAME PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322 #define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_CAST #define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_NAME PDB_PROP_GPU_GSYNC_III_ATTACHED #define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_CAST #define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_NAME PDB_PROP_GPU_QSYNC_II_ATTACHED #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_CAST #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR04_PRESENT +#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_CAST +#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_NAME PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_CAST #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_NAME PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE #define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_CAST @@ -1302,6 +1378,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_NAME PDB_PROP_GPU_ATS_SUPPORTED #define PDB_PROP_GPU_EMULATION_BASE_CAST #define PDB_PROP_GPU_EMULATION_BASE_NAME PDB_PROP_GPU_EMULATION +#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_CAST +#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_APM_FEATURE_CAPABLE #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_CAST #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_NAME PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS #define PDB_PROP_GPU_PRIMARY_DEVICE_BASE_CAST @@ -1316,8 +1394,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST_BASE_NAME PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST #define PDB_PROP_GPU_IS_LOST_BASE_CAST #define PDB_PROP_GPU_IS_LOST_BASE_NAME PDB_PROP_GPU_IS_LOST -#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_CAST -#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_NAME PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K +#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED +#define PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX_BASE_CAST +#define PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX_BASE_NAME PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU**, Dynamic*, NvU32, va_list); @@ -1362,10 +1442,20 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, #define gpuReadDeviceId_HAL(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) #define gpuGetFlaVasSize(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) #define gpuGetFlaVasSize_HAL(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) +#define gpuDetermineSelfHostedMode(pGpu) gpuDetermineSelfHostedMode_DISPATCH(pGpu) +#define gpuDetermineSelfHostedMode_HAL(pGpu) gpuDetermineSelfHostedMode_DISPATCH(pGpu) +#define gpuDetermineMIGSupport(pGpu) gpuDetermineMIGSupport_DISPATCH(pGpu) +#define gpuDetermineMIGSupport_HAL(pGpu) gpuDetermineMIGSupport_DISPATCH(pGpu) #define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) #define gpuIsAtsSupportedWithSmcMemPartitioning_HAL(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) #define gpuIsSliCapableWithoutDisplay(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu) #define gpuIsSliCapableWithoutDisplay_HAL(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu) +#define gpuIsCCEnabledInHw(pGpu) gpuIsCCEnabledInHw_DISPATCH(pGpu) +#define gpuIsCCEnabledInHw_HAL(pGpu) gpuIsCCEnabledInHw_DISPATCH(pGpu) +#define gpuIsDevModeEnabledInHw(pGpu) gpuIsDevModeEnabledInHw_DISPATCH(pGpu) +#define gpuIsDevModeEnabledInHw_HAL(pGpu) gpuIsDevModeEnabledInHw_DISPATCH(pGpu) +#define gpuIsCtxBufAllocInPmaSupported(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu) +#define gpuIsCtxBufAllocInPmaSupported_HAL(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu) static inline NV_STATUS gpuConstructPhysical_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } @@ -1591,6 +1681,22 @@ static inline NV_STATUS gpuPowerManagementResumePostLoadPhysical(struct OBJGPU * #define gpuPowerManagementResumePostLoadPhysical_HAL(pGpu) gpuPowerManagementResumePostLoadPhysical(pGpu) +static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx_46f6a7(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx_46f6a7(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) +#endif //__nvoc_gpu_h_disabled + +#define gpuInitializeMemDescFromPromotedCtx_HAL(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) + NV_STATUS gpuGetNameString_KERNEL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); NV_STATUS gpuGetNameString_IMPL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); @@ -1828,7 +1934,23 @@ static inline RmPhysAddr gpuGetDmaEndAddress(struct OBJGPU *pGpu) { #define gpuGetDmaEndAddress_HAL(pGpu) gpuGetDmaEndAddress(pGpu) -static inline NV_STATUS gpuMarkDeviceForReset_46f6a7(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuSetStateResetRequired_395e98(struct OBJGPU *pGpu, NvU32 exceptType) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuSetStateResetRequired(struct OBJGPU *pGpu, NvU32 exceptType) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuSetStateResetRequired(pGpu, exceptType) gpuSetStateResetRequired_395e98(pGpu, exceptType) +#endif //__nvoc_gpu_h_disabled + +#define gpuSetStateResetRequired_HAL(pGpu, exceptType) gpuSetStateResetRequired(pGpu, exceptType) + +static inline NV_STATUS gpuMarkDeviceForReset_395e98(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } @@ -1839,12 +1961,12 @@ static inline NV_STATUS gpuMarkDeviceForReset(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuMarkDeviceForReset(pGpu) gpuMarkDeviceForReset_46f6a7(pGpu) +#define gpuMarkDeviceForReset(pGpu) gpuMarkDeviceForReset_395e98(pGpu) #endif //__nvoc_gpu_h_disabled #define gpuMarkDeviceForReset_HAL(pGpu) gpuMarkDeviceForReset(pGpu) -static inline NV_STATUS gpuUnmarkDeviceForReset_46f6a7(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuUnmarkDeviceForReset_395e98(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } @@ -1855,13 +1977,17 @@ static inline NV_STATUS gpuUnmarkDeviceForReset(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuUnmarkDeviceForReset(pGpu) gpuUnmarkDeviceForReset_46f6a7(pGpu) +#define gpuUnmarkDeviceForReset(pGpu) gpuUnmarkDeviceForReset_395e98(pGpu) #endif //__nvoc_gpu_h_disabled #define gpuUnmarkDeviceForReset_HAL(pGpu) gpuUnmarkDeviceForReset(pGpu) -static inline NV_STATUS gpuIsDeviceMarkedForReset_46f6a7(struct OBJGPU *pGpu, NvBool *pbResetRequired) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS gpuIsDeviceMarkedForReset_82f166(struct OBJGPU *pGpu, NvBool *pbResetRequired) { + *pbResetRequired = ((NvBool)(0 != 0)); + { + return NV_ERR_NOT_SUPPORTED; + } + ; } @@ -1871,12 +1997,12 @@ static inline NV_STATUS gpuIsDeviceMarkedForReset(struct OBJGPU *pGpu, NvBool *p return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset_46f6a7(pGpu, pbResetRequired) +#define gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset_82f166(pGpu, pbResetRequired) #endif //__nvoc_gpu_h_disabled #define gpuIsDeviceMarkedForReset_HAL(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) -static inline NV_STATUS gpuMarkDeviceForDrainAndReset_46f6a7(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuMarkDeviceForDrainAndReset_395e98(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } @@ -1887,12 +2013,12 @@ static inline NV_STATUS gpuMarkDeviceForDrainAndReset(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuMarkDeviceForDrainAndReset(pGpu) gpuMarkDeviceForDrainAndReset_46f6a7(pGpu) +#define gpuMarkDeviceForDrainAndReset(pGpu) gpuMarkDeviceForDrainAndReset_395e98(pGpu) #endif //__nvoc_gpu_h_disabled #define gpuMarkDeviceForDrainAndReset_HAL(pGpu) gpuMarkDeviceForDrainAndReset(pGpu) -static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset_46f6a7(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset_395e98(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } @@ -1903,13 +2029,17 @@ static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuUnmarkDeviceForDrainAndReset(pGpu) gpuUnmarkDeviceForDrainAndReset_46f6a7(pGpu) +#define gpuUnmarkDeviceForDrainAndReset(pGpu) gpuUnmarkDeviceForDrainAndReset_395e98(pGpu) #endif //__nvoc_gpu_h_disabled #define gpuUnmarkDeviceForDrainAndReset_HAL(pGpu) gpuUnmarkDeviceForDrainAndReset(pGpu) -static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset_46f6a7(struct OBJGPU *pGpu, NvBool *pbDrainRecommended) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset_244f65(struct OBJGPU *pGpu, NvBool *pbDrainRecommended) { + *pbDrainRecommended = ((NvBool)(0 != 0)); + { + return NV_ERR_NOT_SUPPORTED; + } + ; } @@ -1919,7 +2049,7 @@ static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset(struct OBJGPU *pGpu, N return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset_46f6a7(pGpu, pbDrainRecommended) +#define gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset_244f65(pGpu, pbDrainRecommended) #endif //__nvoc_gpu_h_disabled #define gpuIsDeviceMarkedForDrainAndReset_HAL(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) @@ -1971,6 +2101,20 @@ static inline void gpuDestroyOverrides(struct OBJGPU *pGpu) { #define gpuDestroyOverrides_HAL(pGpu) gpuDestroyOverrides(pGpu) +NV_STATUS gpuPowerOff_KERNEL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuPowerOff(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuPowerOff(pGpu) gpuPowerOff_KERNEL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuPowerOff_HAL(pGpu) gpuPowerOff(pGpu) + NV_STATUS gpuSetPower_GM107(struct OBJGPU *pGpu, NvU32 arg1, NvU32 arg2, NvU32 arg3); @@ -2287,6 +2431,40 @@ static inline NV_STATUS gpuJtVersionSanityCheck(struct OBJGPU *pGpu) { #define gpuJtVersionSanityCheck_HAL(pGpu) gpuJtVersionSanityCheck(pGpu) +static inline NvBool gpuCompletedGC6PowerOff_cbe027(struct OBJGPU *pGpu) { + return ((NvBool)(0 == 0)); +} + +NvBool gpuCompletedGC6PowerOff_GV100(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuCompletedGC6PowerOff(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuCompletedGC6PowerOff(pGpu) gpuCompletedGC6PowerOff_cbe027(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuCompletedGC6PowerOff_HAL(pGpu) gpuCompletedGC6PowerOff(pGpu) + +static inline NvBool gpuIsACPIPatchRequiredForBug2473619_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsACPIPatchRequiredForBug2473619(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsACPIPatchRequiredForBug2473619(pGpu) gpuIsACPIPatchRequiredForBug2473619_491d52(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuIsACPIPatchRequiredForBug2473619_HAL(pGpu) gpuIsACPIPatchRequiredForBug2473619(pGpu) + NvU32 gpuGetActiveFBIOs_FWCLIENT(struct OBJGPU *pGpu); NvU32 gpuGetActiveFBIOs_GM107(struct OBJGPU *pGpu); @@ -2448,6 +2626,58 @@ static inline void gpuDecodeDeviceInfoTableGroupId(struct OBJGPU *pGpu, DEVICE_I #define gpuDecodeDeviceInfoTableGroupId_HAL(pGpu, pEntry, pDeviceAccum) gpuDecodeDeviceInfoTableGroupId(pGpu, pEntry, pDeviceAccum) +static inline NV_STATUS gpuGc6EntryPstateCheck_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGc6EntryPstateCheck(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGc6EntryPstateCheck(pGpu) gpuGc6EntryPstateCheck_56cd7a(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuGc6EntryPstateCheck_HAL(pGpu) gpuGc6EntryPstateCheck(pGpu) + +static inline NV_STATUS gpuWaitGC6Ready_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuWaitGC6Ready_GM107(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuWaitGC6Ready(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuWaitGC6Ready(pGpu) gpuWaitGC6Ready_56cd7a(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuWaitGC6Ready_HAL(pGpu) gpuWaitGC6Ready(pGpu) + +static inline NV_STATUS gpuPrePowerOff_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuPrePowerOff_GM107(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuPrePowerOff(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuPrePowerOff(pGpu) gpuPrePowerOff_56cd7a(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuPrePowerOff_HAL(pGpu) gpuPrePowerOff(pGpu) + NV_STATUS gpuVerifyExistence_IMPL(struct OBJGPU *pGpu); @@ -2851,6 +3081,28 @@ static inline NvU64 gpuGetFlaVasSize_DISPATCH(struct OBJGPU *pGpu, NvBool bNvswi return pGpu->__gpuGetFlaVasSize__(pGpu, bNvswitchVirtualization); } +void gpuDetermineSelfHostedMode_PHYSICAL_GH100(struct OBJGPU *pGpu); + +static inline void gpuDetermineSelfHostedMode_b3696a(struct OBJGPU *pGpu) { + return; +} + +void gpuDetermineSelfHostedMode_KERNEL_GH100(struct OBJGPU *pGpu); + +static inline void gpuDetermineSelfHostedMode_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuDetermineSelfHostedMode__(pGpu); +} + +void gpuDetermineMIGSupport_GH100(struct OBJGPU *pGpu); + +static inline void gpuDetermineMIGSupport_b3696a(struct OBJGPU *pGpu) { + return; +} + +static inline void gpuDetermineMIGSupport_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuDetermineMIGSupport__(pGpu); +} + NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(struct OBJGPU *pGpu); static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_491d52(struct OBJGPU *pGpu) { @@ -2873,6 +3125,36 @@ static inline NvBool gpuIsSliCapableWithoutDisplay_DISPATCH(struct OBJGPU *pGpu) return pGpu->__gpuIsSliCapableWithoutDisplay__(pGpu); } +NvBool gpuIsCCEnabledInHw_GH100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsCCEnabledInHw_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsCCEnabledInHw_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsCCEnabledInHw__(pGpu); +} + +NvBool gpuIsDevModeEnabledInHw_GH100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsDevModeEnabledInHw_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsDevModeEnabledInHw_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsDevModeEnabledInHw__(pGpu); +} + +NvBool gpuIsCtxBufAllocInPmaSupported_GA100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsCtxBufAllocInPmaSupported_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsCtxBufAllocInPmaSupported_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsCtxBufAllocInPmaSupported__(pGpu); +} + static inline PENGDESCRIPTOR gpuGetInitEngineDescriptors(struct OBJGPU *pGpu) { return pGpu->engineOrder.pEngineInitDescriptors; } @@ -2930,22 +3212,6 @@ static inline RmPhysAddr gpuGetDmaStartAddress(struct OBJGPU *pGpu) { return pGpu->dmaStartAddress; } -static inline NvBool gpuIsCCFeatureEnabled(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - -static inline NvBool gpuIsApmFeatureEnabled(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - -static inline NvBool gpuIsCCorApmFeatureEnabled(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - -static inline NvBool gpuIsInCCorApmDevMode(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - static inline NV_STATUS gpuFreeEventHandle(struct OBJGPU *pGpu) { return NV_OK; } @@ -3094,6 +3360,10 @@ static inline NvBool gpuIsVgxBranded(struct OBJGPU *pGpu) { return pGpu->bIsVgx; } +static inline NvBool gpuIsACBranded(struct OBJGPU *pGpu) { + return pGpu->bIsAC; +} + static inline NvBool gpuIsNvidiaNvsBranded(struct OBJGPU *pGpu) { return pGpu->bIsNvidiaNvs; } @@ -3114,6 +3384,10 @@ static inline NvBool gpuIsSriovCapable(struct OBJGPU *pGpu) { return pGpu->bSriovCapable; } +static inline NvBool gpuIsSelfHosted(struct OBJGPU *pGpu) { + return pGpu->bIsSelfHosted; +} + static inline NvBool gpuIsGspOwnedFaultBuffersEnabled(struct OBJGPU *pGpu) { return pGpu->bIsGspOwnedFaultBuffersEnabled; } @@ -3121,15 +3395,15 @@ static inline NvBool gpuIsGspOwnedFaultBuffersEnabled(struct OBJGPU *pGpu) { NV_STATUS gpuConstruct_IMPL(struct OBJGPU *arg_pGpu, NvU32 arg_gpuInstance); #define __nvoc_gpuConstruct(arg_pGpu, arg_gpuInstance) gpuConstruct_IMPL(arg_pGpu, arg_gpuInstance) -NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1); +NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1, NvU32 socChipId0); #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuBindHalLegacy(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1) { +static inline NV_STATUS gpuBindHalLegacy(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1, NvU32 socChipId0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuBindHalLegacy(pGpu, chipId0, chipId1) gpuBindHalLegacy_IMPL(pGpu, chipId0, chipId1) +#define gpuBindHalLegacy(pGpu, chipId0, chipId1, socChipId0) gpuBindHalLegacy_IMPL(pGpu, chipId0, chipId1, socChipId0) #endif //__nvoc_gpu_h_disabled NV_STATUS gpuPostConstruct_IMPL(struct OBJGPU *pGpu, GPUATTACHARG *arg0); @@ -3932,6 +4206,61 @@ static inline NV_STATUS gpuFindClientInfoWithPidIterator(struct OBJGPU *pGpu, Nv #define gpuFindClientInfoWithPidIterator(pGpu, pid, subPid, internalClassId, pData, pSmcInfo, pRef, bGlobalInfo) gpuFindClientInfoWithPidIterator_IMPL(pGpu, pid, subPid, internalClassId, pData, pSmcInfo, pRef, bGlobalInfo) #endif //__nvoc_gpu_h_disabled +NvBool gpuIsCCFeatureEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsCCFeatureEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsCCFeatureEnabled(pGpu) gpuIsCCFeatureEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NvBool gpuIsApmFeatureEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsApmFeatureEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsApmFeatureEnabled(pGpu) gpuIsApmFeatureEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NvBool gpuIsCCorApmFeatureEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsCCorApmFeatureEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsCCorApmFeatureEnabled(pGpu) gpuIsCCorApmFeatureEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NvBool gpuIsCCDevToolsModeEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsCCDevToolsModeEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsCCDevToolsModeEnabled(pGpu) gpuIsCCDevToolsModeEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NvBool gpuIsOnTheBus_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsOnTheBus(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsOnTheBus(pGpu) gpuIsOnTheBus_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuEnterStandby_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -4041,6 +4370,39 @@ static inline NV_STATUS gpuSetGC6SBIOSCapabilities(struct OBJGPU *pGpu) { #define gpuSetGC6SBIOSCapabilities(pGpu) gpuSetGC6SBIOSCapabilities_IMPL(pGpu) #endif //__nvoc_gpu_h_disabled +NV_STATUS gpuGc6Entry_IMPL(struct OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *arg0); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGc6Entry(struct OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGc6Entry(pGpu, arg0) gpuGc6Entry_IMPL(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuGc6EntryGpuPowerOff_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGc6EntryGpuPowerOff(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGc6EntryGpuPowerOff(pGpu) gpuGc6EntryGpuPowerOff_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuGc6Exit_IMPL(struct OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *arg0); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGc6Exit(struct OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGc6Exit(pGpu, arg0) gpuGc6Exit_IMPL(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + #undef PRIVATE_FIELD @@ -4055,12 +4417,13 @@ NV_STATUS gpuGetByHandle(struct RsClient *pClient, NvHandle hResource, NvBool *p #define IS_GFID_VF(gfid) (((NvU32)(gfid)) != GPU_GFID_PF) // Invalid P2P GFID #define INVALID_P2P_GFID (0xFFFFFFFF) +#define INVALID_FABRIC_PARTITION_ID (0xFFFFFFFF) // // Generates GPU child accessor macros (i.e.: GPU_GET_{ENG}) // #define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ - static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return pGpu->gpuField; } \ + static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return pGpu->gpuField; } \ ct_assert(numInstances == 1); #define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ @@ -4141,7 +4504,6 @@ static NvU32 gpuGetNumCEs(struct OBJGPU *pGpu) // IS_SILICON Real hardware // IS_VIRTUAL RM is running within a guest VM // IS_GSP_CLIENT RM is a GSP/DCE client with GPU support offloaded to GSP/DCE -// IS_FW_CLIENT RM is a firmware client with GPU support offloaded microprocessor // #define IS_EMULATION(pGpu) ((pGpu)->getProperty((pGpu), PDB_PROP_GPU_EMULATION)) @@ -4152,7 +4514,6 @@ static NvU32 gpuGetNumCEs(struct OBJGPU *pGpu) #define IS_SILICON(pGpu) (!(IS_EMULATION(pGpu) || IS_SIMULATION(pGpu))) #define IS_PASSTHRU(pGpu) ((pGpu)->bIsPassthru) #define IS_GSP_CLIENT(pGpu) ((RMCFG_FEATURE_GSP_CLIENT_RM || RMCFG_FEATURE_DCE_CLIENT_RM) && (pGpu)->isGspClient) -#define IS_FW_CLIENT(pGpu) IS_GSP_CLIENT(pGpu) // TODO to be removed #define IS_VIRTUAL(pGpu) NV_FALSE #define IS_VIRTUAL_WITH_SRIOV(pGpu) NV_FALSE #define IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu) NV_FALSE @@ -4269,13 +4630,6 @@ VGPU_STATIC_INFO *gpuGetStaticInfo(struct OBJGPU *pGpu); GspStaticConfigInfo *gpuGetGspStaticInfo(struct OBJGPU *pGpu); #define GPU_GET_GSP_STATIC_INFO(pGpu) gpuGetGspStaticInfo(pGpu) - -#define IS_GPU_GC6_STATE_POWERED_ON(obj) NV_TRUE -#define IS_GPU_GC6_STATE_EXITED(obj) NV_FALSE -#define IS_GPU_GC6_STATE_ENTERING(obj) NV_FALSE -#define IS_GPU_GC6_STATE_ENTERED(obj) NV_FALSE -#define IS_GPU_GC6_STATE_EXITING(obj) NV_FALSE - #endif // _OBJGPU_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c index 6537d28651..02992a5f0f 100644 --- a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c @@ -21,11 +21,11 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; -extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; void __nvoc_init_GpuUserSharedData(GpuUserSharedData*); void __nvoc_init_funcTable_GpuUserSharedData(GpuUserSharedData*); -NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); void __nvoc_init_dataField_GpuUserSharedData(GpuUserSharedData*); void __nvoc_dtor_GpuUserSharedData(GpuUserSharedData*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_GpuUserSharedData; @@ -39,38 +39,38 @@ static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_GpuUserSharedData = static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_Object = { /*pClassDef=*/ &__nvoc_class_def_Object, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), }; static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RsResource = { /*pClassDef=*/ &__nvoc_class_def_RsResource, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource), }; static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RmResourceCommon = { /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), }; static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RmResource = { /*pClassDef=*/ &__nvoc_class_def_RmResource, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory.__nvoc_base_RmResource), }; -static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_GpuResource = { - /*pClassDef=*/ &__nvoc_class_def_GpuResource, +static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_Memory = { + /*pClassDef=*/ &__nvoc_class_def_Memory, /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource), + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_Memory), }; static const struct NVOC_CASTINFO __nvoc_castinfo_GpuUserSharedData = { /*numRelatives=*/ 6, /*relatives=*/ { &__nvoc_rtti_GpuUserSharedData_GpuUserSharedData, - &__nvoc_rtti_GpuUserSharedData_GpuResource, + &__nvoc_rtti_GpuUserSharedData_Memory, &__nvoc_rtti_GpuUserSharedData_RmResource, &__nvoc_rtti_GpuUserSharedData_RmResourceCommon, &__nvoc_rtti_GpuUserSharedData_RsResource, @@ -93,34 +93,26 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_GpuUserSharedData = /*pExportInfo=*/ &__nvoc_export_info_GpuUserSharedData }; -static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresMap(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { - return gpushareddataMap((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pParams, pCpuMapping); +static NvBool __nvoc_thunk_GpuUserSharedData_resCanCopy(struct RsResource *pData) { + return gpushareddataCanCopy((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresUnmap(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpushareddataUnmap((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataCheckMemInterUnmap(struct GpuUserSharedData *pMemory, NvBool bSubdeviceHandleProvided) { + return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresGetMapAddrSpace(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpushareddataGetMapAddrSpace((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NV_STATUS __nvoc_thunk_GpuUserSharedData_rmresGetMemoryMappingDescriptor(struct RmResource *pData, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return gpushareddataGetMemoryMappingDescriptor((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_RmResource.offset), ppMemDesc); -} - -static NvBool __nvoc_thunk_GpuResource_gpushareddataShareCallback(struct GpuUserSharedData *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - -static NV_STATUS __nvoc_thunk_RmResource_gpushareddataCheckMemInterUnmap(struct GpuUserSharedData *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), bSubdeviceHandleProvided); +static NvBool __nvoc_thunk_RmResource_gpushareddataShareCallback(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } static NV_STATUS __nvoc_thunk_RsResource_gpushareddataMapTo(struct GpuUserSharedData *pResource, RS_RES_MAP_TO_PARAMS *pParams) { return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_Memory_gpushareddataGetMapAddrSpace(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + static NvU32 __nvoc_thunk_RsResource_gpushareddataGetRefCount(struct GpuUserSharedData *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); } @@ -129,23 +121,19 @@ static void __nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants(struct resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControl_Prologue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControl_Prologue(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataGetRegBaseOffsetAndSize(struct GpuUserSharedData *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pGpu, pOffset, pSize); -} - -static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataInternalControlForward(struct GpuUserSharedData *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), command, pParams, size); +static NvBool __nvoc_thunk_Memory_gpushareddataIsGpuMapAllowed(struct GpuUserSharedData *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pGpu); } static NV_STATUS __nvoc_thunk_RsResource_gpushareddataUnmapFrom(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); } -static void __nvoc_thunk_RmResource_gpushareddataControl_Epilogue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static void __nvoc_thunk_RmResource_gpushareddataControl_Epilogue(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } @@ -153,42 +141,54 @@ static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlLookup(struct GpuUs return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams, ppEntry); } -static NvHandle __nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle(struct GpuUserSharedData *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset)); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataControl(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataControl(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataUnmap(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pParams); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataGetMemInterMapParams(struct GpuUserSharedData *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_gpushareddataGetMemoryMappingDescriptor(struct GpuUserSharedData *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), ppMemDesc); } static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlFilter(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControlSerialization_Prologue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControlSerialization_Prologue(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RsResource_gpushareddataCanCopy(struct GpuUserSharedData *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataIsReady(struct GpuUserSharedData *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_Memory_gpushareddataCheckCopyPermissions(struct GpuUserSharedData *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_gpushareddataPreDestruct(struct GpuUserSharedData *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataIsDuplicate(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), hMemory, pDuplicate); +static NV_STATUS __nvoc_thunk_Memory_gpushareddataIsDuplicate(struct GpuUserSharedData *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_gpushareddataControlSerialization_Epilogue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static void __nvoc_thunk_RmResource_gpushareddataControlSerialization_Epilogue(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } +static NV_STATUS __nvoc_thunk_Memory_gpushareddataMap(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, pParams, pCpuMapping); +} + static NvBool __nvoc_thunk_RmResource_gpushareddataAccessCallback(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } @@ -199,10 +199,9 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_GpuUserSharedData = /*pExportEntries=*/ 0 }; -void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_Memory(Memory*); void __nvoc_dtor_GpuUserSharedData(GpuUserSharedData *pThis) { - __nvoc_gpushareddataDestruct(pThis); - __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -210,11 +209,11 @@ void __nvoc_init_dataField_GpuUserSharedData(GpuUserSharedData *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); } -NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); -NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_ctor_Memory(Memory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; - status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); - if (status != NV_OK) goto __nvoc_ctor_GpuUserSharedData_fail_GpuResource; + status = __nvoc_ctor_Memory(&pThis->__nvoc_base_Memory, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_GpuUserSharedData_fail_Memory; __nvoc_init_dataField_GpuUserSharedData(pThis); status = __nvoc_gpushareddataConstruct(pThis, arg_pCallContext, arg_pParams); @@ -222,8 +221,8 @@ NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData *pThis, struct CALL_CO goto __nvoc_ctor_GpuUserSharedData_exit; // Success __nvoc_ctor_GpuUserSharedData_fail__init: - __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); -__nvoc_ctor_GpuUserSharedData_fail_GpuResource: + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); +__nvoc_ctor_GpuUserSharedData_fail_Memory: __nvoc_ctor_GpuUserSharedData_exit: return status; @@ -232,37 +231,25 @@ NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData *pThis, struct CALL_CO static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - pThis->__gpushareddataMap__ = &gpushareddataMap_IMPL; - - pThis->__gpushareddataUnmap__ = &gpushareddataUnmap_IMPL; - - pThis->__gpushareddataGetMapAddrSpace__ = &gpushareddataGetMapAddrSpace_IMPL; - - pThis->__gpushareddataGetMemoryMappingDescriptor__ = &gpushareddataGetMemoryMappingDescriptor_IMPL; - - pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_GpuUserSharedData_gpuresMap; - - pThis->__nvoc_base_GpuResource.__gpuresUnmap__ = &__nvoc_thunk_GpuUserSharedData_gpuresUnmap; + pThis->__gpushareddataCanCopy__ = &gpushareddataCanCopy_IMPL; - pThis->__nvoc_base_GpuResource.__gpuresGetMapAddrSpace__ = &__nvoc_thunk_GpuUserSharedData_gpuresGetMapAddrSpace; + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_GpuUserSharedData_resCanCopy; - pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__rmresGetMemoryMappingDescriptor__ = &__nvoc_thunk_GpuUserSharedData_rmresGetMemoryMappingDescriptor; + pThis->__gpushareddataCheckMemInterUnmap__ = &__nvoc_thunk_Memory_gpushareddataCheckMemInterUnmap; - pThis->__gpushareddataShareCallback__ = &__nvoc_thunk_GpuResource_gpushareddataShareCallback; - - pThis->__gpushareddataCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gpushareddataCheckMemInterUnmap; + pThis->__gpushareddataShareCallback__ = &__nvoc_thunk_RmResource_gpushareddataShareCallback; pThis->__gpushareddataMapTo__ = &__nvoc_thunk_RsResource_gpushareddataMapTo; + pThis->__gpushareddataGetMapAddrSpace__ = &__nvoc_thunk_Memory_gpushareddataGetMapAddrSpace; + pThis->__gpushareddataGetRefCount__ = &__nvoc_thunk_RsResource_gpushareddataGetRefCount; pThis->__gpushareddataAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants; pThis->__gpushareddataControl_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Prologue; - pThis->__gpushareddataGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_gpushareddataGetRegBaseOffsetAndSize; - - pThis->__gpushareddataInternalControlForward__ = &__nvoc_thunk_GpuResource_gpushareddataInternalControlForward; + pThis->__gpushareddataIsGpuMapAllowed__ = &__nvoc_thunk_Memory_gpushareddataIsGpuMapAllowed; pThis->__gpushareddataUnmapFrom__ = &__nvoc_thunk_RsResource_gpushareddataUnmapFrom; @@ -270,24 +257,30 @@ static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) pThis->__gpushareddataControlLookup__ = &__nvoc_thunk_RsResource_gpushareddataControlLookup; - pThis->__gpushareddataGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle; + pThis->__gpushareddataControl__ = &__nvoc_thunk_Memory_gpushareddataControl; - pThis->__gpushareddataControl__ = &__nvoc_thunk_GpuResource_gpushareddataControl; + pThis->__gpushareddataUnmap__ = &__nvoc_thunk_Memory_gpushareddataUnmap; - pThis->__gpushareddataGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams; + pThis->__gpushareddataGetMemInterMapParams__ = &__nvoc_thunk_Memory_gpushareddataGetMemInterMapParams; + + pThis->__gpushareddataGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_gpushareddataGetMemoryMappingDescriptor; pThis->__gpushareddataControlFilter__ = &__nvoc_thunk_RsResource_gpushareddataControlFilter; pThis->__gpushareddataControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControlSerialization_Prologue; - pThis->__gpushareddataCanCopy__ = &__nvoc_thunk_RsResource_gpushareddataCanCopy; + pThis->__gpushareddataIsReady__ = &__nvoc_thunk_Memory_gpushareddataIsReady; + + pThis->__gpushareddataCheckCopyPermissions__ = &__nvoc_thunk_Memory_gpushareddataCheckCopyPermissions; pThis->__gpushareddataPreDestruct__ = &__nvoc_thunk_RsResource_gpushareddataPreDestruct; - pThis->__gpushareddataIsDuplicate__ = &__nvoc_thunk_RsResource_gpushareddataIsDuplicate; + pThis->__gpushareddataIsDuplicate__ = &__nvoc_thunk_Memory_gpushareddataIsDuplicate; pThis->__gpushareddataControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gpushareddataControlSerialization_Epilogue; + pThis->__gpushareddataMap__ = &__nvoc_thunk_Memory_gpushareddataMap; + pThis->__gpushareddataAccessCallback__ = &__nvoc_thunk_RmResource_gpushareddataAccessCallback; } @@ -295,19 +288,19 @@ void __nvoc_init_funcTable_GpuUserSharedData(GpuUserSharedData *pThis) { __nvoc_init_funcTable_GpuUserSharedData_1(pThis); } -void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_Memory(Memory*); void __nvoc_init_GpuUserSharedData(GpuUserSharedData *pThis) { pThis->__nvoc_pbase_GpuUserSharedData = pThis; - pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; - pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; - pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; - pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; - pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; - __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource; + pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_Memory; + __nvoc_init_Memory(&pThis->__nvoc_base_Memory); __nvoc_init_funcTable_GpuUserSharedData(pThis); } -NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status; Object *pParentObj; GpuUserSharedData *pThis; @@ -320,16 +313,16 @@ NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuUserSharedData); - pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); - objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); } else { - pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; } __nvoc_init_GpuUserSharedData(pThis); @@ -353,7 +346,7 @@ NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic NV_STATUS __nvoc_objCreateDynamic_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { NV_STATUS status; - struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); status = __nvoc_objCreate_GpuUserSharedData(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h index 407a6a9179..3893723156 100644 --- a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h @@ -35,8 +35,9 @@ extern "C" { #define GPU_USER_SHARED_DATA_H #include "core/core.h" -#include "gpu/gpu_resource.h" -#include "gpu/mem_mgr/mem_desc.h" +#include "mem_mgr/mem.h" +#include "gpu/gpu.h" +#include "nvoc/utility.h" // **************************************************************************** // Type definitions @@ -52,37 +53,37 @@ extern "C" { #endif struct GpuUserSharedData { const struct NVOC_RTTI *__nvoc_rtti; - struct GpuResource __nvoc_base_GpuResource; + struct Memory __nvoc_base_Memory; struct Object *__nvoc_pbase_Object; struct RsResource *__nvoc_pbase_RsResource; struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; struct RmResource *__nvoc_pbase_RmResource; - struct GpuResource *__nvoc_pbase_GpuResource; + struct Memory *__nvoc_pbase_Memory; struct GpuUserSharedData *__nvoc_pbase_GpuUserSharedData; - NV_STATUS (*__gpushareddataMap__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); - NV_STATUS (*__gpushareddataUnmap__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__gpushareddataGetMapAddrSpace__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NV_STATUS (*__gpushareddataGetMemoryMappingDescriptor__)(struct GpuUserSharedData *, struct MEMORY_DESCRIPTOR **); - NvBool (*__gpushareddataShareCallback__)(struct GpuUserSharedData *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NvBool (*__gpushareddataCanCopy__)(struct GpuUserSharedData *); NV_STATUS (*__gpushareddataCheckMemInterUnmap__)(struct GpuUserSharedData *, NvBool); + NvBool (*__gpushareddataShareCallback__)(struct GpuUserSharedData *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__gpushareddataMapTo__)(struct GpuUserSharedData *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__gpushareddataGetMapAddrSpace__)(struct GpuUserSharedData *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NvU32 (*__gpushareddataGetRefCount__)(struct GpuUserSharedData *); void (*__gpushareddataAddAdditionalDependants__)(struct RsClient *, struct GpuUserSharedData *, RsResourceRef *); - NV_STATUS (*__gpushareddataControl_Prologue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gpushareddataGetRegBaseOffsetAndSize__)(struct GpuUserSharedData *, struct OBJGPU *, NvU32 *, NvU32 *); - NV_STATUS (*__gpushareddataInternalControlForward__)(struct GpuUserSharedData *, NvU32, void *, NvU32); + NV_STATUS (*__gpushareddataControl_Prologue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__gpushareddataIsGpuMapAllowed__)(struct GpuUserSharedData *, struct OBJGPU *); NV_STATUS (*__gpushareddataUnmapFrom__)(struct GpuUserSharedData *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__gpushareddataControl_Epilogue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__gpushareddataControl_Epilogue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpushareddataControlLookup__)(struct GpuUserSharedData *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NvHandle (*__gpushareddataGetInternalObjectHandle__)(struct GpuUserSharedData *); - NV_STATUS (*__gpushareddataControl__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataControl__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataUnmap__)(struct GpuUserSharedData *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__gpushareddataGetMemInterMapParams__)(struct GpuUserSharedData *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__gpushareddataGetMemoryMappingDescriptor__)(struct GpuUserSharedData *, MEMORY_DESCRIPTOR **); NV_STATUS (*__gpushareddataControlFilter__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gpushareddataControlSerialization_Prologue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__gpushareddataCanCopy__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataControlSerialization_Prologue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataIsReady__)(struct GpuUserSharedData *, NvBool); + NV_STATUS (*__gpushareddataCheckCopyPermissions__)(struct GpuUserSharedData *, struct OBJGPU *, struct Device *); void (*__gpushareddataPreDestruct__)(struct GpuUserSharedData *); NV_STATUS (*__gpushareddataIsDuplicate__)(struct GpuUserSharedData *, NvHandle, NvBool *); - void (*__gpushareddataControlSerialization_Epilogue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__gpushareddataControlSerialization_Epilogue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataMap__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__gpushareddataAccessCallback__)(struct GpuUserSharedData *, struct RsClient *, void *, RsAccessRight); }; @@ -110,71 +111,57 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuUserSharedData; NV_STATUS __nvoc_objCreateDynamic_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU32, va_list); -NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); #define __objCreate_GpuUserSharedData(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_GpuUserSharedData((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define gpushareddataMap(pData, pCallContext, pParams, pCpuMapping) gpushareddataMap_DISPATCH(pData, pCallContext, pParams, pCpuMapping) -#define gpushareddataUnmap(pData, pCallContext, pCpuMapping) gpushareddataUnmap_DISPATCH(pData, pCallContext, pCpuMapping) -#define gpushareddataGetMapAddrSpace(pData, pCallContext, mapFlags, pAddrSpace) gpushareddataGetMapAddrSpace_DISPATCH(pData, pCallContext, mapFlags, pAddrSpace) -#define gpushareddataGetMemoryMappingDescriptor(pData, ppMemDesc) gpushareddataGetMemoryMappingDescriptor_DISPATCH(pData, ppMemDesc) -#define gpushareddataShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) gpushareddataShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define gpushareddataCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gpushareddataCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define gpushareddataCanCopy(pData) gpushareddataCanCopy_DISPATCH(pData) +#define gpushareddataCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) gpushareddataCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define gpushareddataShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) gpushareddataShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define gpushareddataMapTo(pResource, pParams) gpushareddataMapTo_DISPATCH(pResource, pParams) +#define gpushareddataGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) gpushareddataGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) #define gpushareddataGetRefCount(pResource) gpushareddataGetRefCount_DISPATCH(pResource) #define gpushareddataAddAdditionalDependants(pClient, pResource, pReference) gpushareddataAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define gpushareddataControl_Prologue(pResource, pCallContext, pParams) gpushareddataControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define gpushareddataGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) gpushareddataGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define gpushareddataInternalControlForward(pGpuResource, command, pParams, size) gpushareddataInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define gpushareddataIsGpuMapAllowed(pMemory, pGpu) gpushareddataIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define gpushareddataUnmapFrom(pResource, pParams) gpushareddataUnmapFrom_DISPATCH(pResource, pParams) #define gpushareddataControl_Epilogue(pResource, pCallContext, pParams) gpushareddataControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpushareddataControlLookup(pResource, pParams, ppEntry) gpushareddataControlLookup_DISPATCH(pResource, pParams, ppEntry) -#define gpushareddataGetInternalObjectHandle(pGpuResource) gpushareddataGetInternalObjectHandle_DISPATCH(pGpuResource) -#define gpushareddataControl(pGpuResource, pCallContext, pParams) gpushareddataControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define gpushareddataGetMemInterMapParams(pRmResource, pParams) gpushareddataGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define gpushareddataControl(pMemory, pCallContext, pParams) gpushareddataControl_DISPATCH(pMemory, pCallContext, pParams) +#define gpushareddataUnmap(pMemory, pCallContext, pCpuMapping) gpushareddataUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define gpushareddataGetMemInterMapParams(pMemory, pParams) gpushareddataGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define gpushareddataGetMemoryMappingDescriptor(pMemory, ppMemDesc) gpushareddataGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define gpushareddataControlFilter(pResource, pCallContext, pParams) gpushareddataControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gpushareddataControlSerialization_Prologue(pResource, pCallContext, pParams) gpushareddataControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define gpushareddataCanCopy(pResource) gpushareddataCanCopy_DISPATCH(pResource) +#define gpushareddataIsReady(pMemory, bCopyConstructorContext) gpushareddataIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define gpushareddataCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) gpushareddataCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define gpushareddataPreDestruct(pResource) gpushareddataPreDestruct_DISPATCH(pResource) -#define gpushareddataIsDuplicate(pResource, hMemory, pDuplicate) gpushareddataIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gpushareddataIsDuplicate(pMemory, hMemory, pDuplicate) gpushareddataIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define gpushareddataControlSerialization_Epilogue(pResource, pCallContext, pParams) gpushareddataControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataMap(pMemory, pCallContext, pParams, pCpuMapping) gpushareddataMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define gpushareddataAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpushareddataAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS gpushareddataMap_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); - -static inline NV_STATUS gpushareddataMap_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { - return pData->__gpushareddataMap__(pData, pCallContext, pParams, pCpuMapping); -} - -NV_STATUS gpushareddataUnmap_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping); - -static inline NV_STATUS gpushareddataUnmap_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pData->__gpushareddataUnmap__(pData, pCallContext, pCpuMapping); -} - -NV_STATUS gpushareddataGetMapAddrSpace_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); - -static inline NV_STATUS gpushareddataGetMapAddrSpace_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pData->__gpushareddataGetMapAddrSpace__(pData, pCallContext, mapFlags, pAddrSpace); -} +NvBool gpushareddataCanCopy_IMPL(struct GpuUserSharedData *pData); -NV_STATUS gpushareddataGetMemoryMappingDescriptor_IMPL(struct GpuUserSharedData *pData, struct MEMORY_DESCRIPTOR **ppMemDesc); - -static inline NV_STATUS gpushareddataGetMemoryMappingDescriptor_DISPATCH(struct GpuUserSharedData *pData, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pData->__gpushareddataGetMemoryMappingDescriptor__(pData, ppMemDesc); +static inline NvBool gpushareddataCanCopy_DISPATCH(struct GpuUserSharedData *pData) { + return pData->__gpushareddataCanCopy__(pData); } -static inline NvBool gpushareddataShareCallback_DISPATCH(struct GpuUserSharedData *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pGpuResource->__gpushareddataShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +static inline NV_STATUS gpushareddataCheckMemInterUnmap_DISPATCH(struct GpuUserSharedData *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__gpushareddataCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } -static inline NV_STATUS gpushareddataCheckMemInterUnmap_DISPATCH(struct GpuUserSharedData *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__gpushareddataCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NvBool gpushareddataShareCallback_DISPATCH(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__gpushareddataShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } static inline NV_STATUS gpushareddataMapTo_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_MAP_TO_PARAMS *pParams) { return pResource->__gpushareddataMapTo__(pResource, pParams); } +static inline NV_STATUS gpushareddataGetMapAddrSpace_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__gpushareddataGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + static inline NvU32 gpushareddataGetRefCount_DISPATCH(struct GpuUserSharedData *pResource) { return pResource->__gpushareddataGetRefCount__(pResource); } @@ -183,23 +170,19 @@ static inline void gpushareddataAddAdditionalDependants_DISPATCH(struct RsClient pResource->__gpushareddataAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS gpushareddataControl_Prologue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static inline NV_STATUS gpushareddataControl_Prologue_DISPATCH(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gpushareddataControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpushareddataGetRegBaseOffsetAndSize_DISPATCH(struct GpuUserSharedData *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__gpushareddataGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); -} - -static inline NV_STATUS gpushareddataInternalControlForward_DISPATCH(struct GpuUserSharedData *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__gpushareddataInternalControlForward__(pGpuResource, command, pParams, size); +static inline NvBool gpushareddataIsGpuMapAllowed_DISPATCH(struct GpuUserSharedData *pMemory, struct OBJGPU *pGpu) { + return pMemory->__gpushareddataIsGpuMapAllowed__(pMemory, pGpu); } static inline NV_STATUS gpushareddataUnmapFrom_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__gpushareddataUnmapFrom__(pResource, pParams); } -static inline void gpushareddataControl_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static inline void gpushareddataControl_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpushareddataControl_Epilogue__(pResource, pCallContext, pParams); } @@ -207,52 +190,61 @@ static inline NV_STATUS gpushareddataControlLookup_DISPATCH(struct GpuUserShared return pResource->__gpushareddataControlLookup__(pResource, pParams, ppEntry); } -static inline NvHandle gpushareddataGetInternalObjectHandle_DISPATCH(struct GpuUserSharedData *pGpuResource) { - return pGpuResource->__gpushareddataGetInternalObjectHandle__(pGpuResource); +static inline NV_STATUS gpushareddataControl_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__gpushareddataControl__(pMemory, pCallContext, pParams); +} + +static inline NV_STATUS gpushareddataUnmap_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__gpushareddataUnmap__(pMemory, pCallContext, pCpuMapping); } -static inline NV_STATUS gpushareddataControl_DISPATCH(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__gpushareddataControl__(pGpuResource, pCallContext, pParams); +static inline NV_STATUS gpushareddataGetMemInterMapParams_DISPATCH(struct GpuUserSharedData *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__gpushareddataGetMemInterMapParams__(pMemory, pParams); } -static inline NV_STATUS gpushareddataGetMemInterMapParams_DISPATCH(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__gpushareddataGetMemInterMapParams__(pRmResource, pParams); +static inline NV_STATUS gpushareddataGetMemoryMappingDescriptor_DISPATCH(struct GpuUserSharedData *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__gpushareddataGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } static inline NV_STATUS gpushareddataControlFilter_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gpushareddataControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpushareddataControlSerialization_Prologue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static inline NV_STATUS gpushareddataControlSerialization_Prologue_DISPATCH(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gpushareddataControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NvBool gpushareddataCanCopy_DISPATCH(struct GpuUserSharedData *pResource) { - return pResource->__gpushareddataCanCopy__(pResource); +static inline NV_STATUS gpushareddataIsReady_DISPATCH(struct GpuUserSharedData *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__gpushareddataIsReady__(pMemory, bCopyConstructorContext); +} + +static inline NV_STATUS gpushareddataCheckCopyPermissions_DISPATCH(struct GpuUserSharedData *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__gpushareddataCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void gpushareddataPreDestruct_DISPATCH(struct GpuUserSharedData *pResource) { pResource->__gpushareddataPreDestruct__(pResource); } -static inline NV_STATUS gpushareddataIsDuplicate_DISPATCH(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__gpushareddataIsDuplicate__(pResource, hMemory, pDuplicate); +static inline NV_STATUS gpushareddataIsDuplicate_DISPATCH(struct GpuUserSharedData *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__gpushareddataIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline void gpushareddataControlSerialization_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static inline void gpushareddataControlSerialization_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpushareddataControlSerialization_Epilogue__(pResource, pCallContext, pParams); } +static inline NV_STATUS gpushareddataMap_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pMemory->__gpushareddataMap__(pMemory, pCallContext, pParams, pCpuMapping); +} + static inline NvBool gpushareddataAccessCallback_DISPATCH(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__gpushareddataAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -NV_STATUS gpushareddataConstruct_IMPL(struct GpuUserSharedData *arg_pData, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); +NV_STATUS gpushareddataConstruct_IMPL(struct GpuUserSharedData *arg_pData, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); #define __nvoc_gpushareddataConstruct(arg_pData, arg_pCallContext, arg_pParams) gpushareddataConstruct_IMPL(arg_pData, arg_pCallContext, arg_pParams) -void gpushareddataDestruct_IMPL(struct GpuUserSharedData *pData); - -#define __nvoc_gpushareddataDestruct(pData) gpushareddataDestruct_IMPL(pData) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.c b/src/nvidia/generated/g_gpu_vaspace_nvoc.c index 4f86b25d2e..e4740e01ee 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.c +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.c @@ -106,7 +106,7 @@ static NvU64 __nvoc_thunk_OBJGVASPACE_vaspaceGetMapPageSize(struct OBJVASPACE *p return gvaspaceGetMapPageSize((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } -static NvU32 __nvoc_thunk_OBJGVASPACE_vaspaceGetBigPageSize(struct OBJVASPACE *pVAS) { +static NvU64 __nvoc_thunk_OBJGVASPACE_vaspaceGetBigPageSize(struct OBJVASPACE *pVAS) { return gvaspaceGetBigPageSize((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset)); } diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.h b/src/nvidia/generated/g_gpu_vaspace_nvoc.h index 0d4efef879..e1fa9d77b3 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.h +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.h @@ -228,7 +228,7 @@ struct OBJGVASPACE { void (*__gvaspaceUnmap__)(struct OBJGVASPACE *, struct OBJGPU *, const NvU64, const NvU64); struct OBJEHEAP *(*__gvaspaceGetHeap__)(struct OBJGVASPACE *); NvU64 (*__gvaspaceGetMapPageSize__)(struct OBJGVASPACE *, struct OBJGPU *, EMEMBLOCK *); - NvU32 (*__gvaspaceGetBigPageSize__)(struct OBJGVASPACE *); + NvU64 (*__gvaspaceGetBigPageSize__)(struct OBJGVASPACE *); NvU32 (*__gvaspaceGetFlags__)(struct OBJGVASPACE *); NvBool (*__gvaspaceIsMirrored__)(struct OBJGVASPACE *); NvBool (*__gvaspaceIsFaultCapable__)(struct OBJGVASPACE *); @@ -249,8 +249,7 @@ struct OBJGVASPACE { NvU64 (*__gvaspaceGetVaLimit__)(struct OBJGVASPACE *); NvU64 (*__gvaspaceGetVaStart__)(struct OBJGVASPACE *); struct OBJEHEAP *pHeap; - NvU32 bigPageSize; - NvU64 maxPageSizeSupported; + NvU64 bigPageSize; NvU64 compPageSize; NvU64 extManagedAlign; NvU32 flags; @@ -392,9 +391,9 @@ static inline NvU64 gvaspaceGetMapPageSize_DISPATCH(struct OBJGVASPACE *pVAS, st return pVAS->__gvaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } -NvU32 gvaspaceGetBigPageSize_IMPL(struct OBJGVASPACE *pVAS); +NvU64 gvaspaceGetBigPageSize_IMPL(struct OBJGVASPACE *pVAS); -static inline NvU32 gvaspaceGetBigPageSize_DISPATCH(struct OBJGVASPACE *pVAS) { +static inline NvU64 gvaspaceGetBigPageSize_DISPATCH(struct OBJGVASPACE *pVAS) { return pVAS->__gvaspaceGetBigPageSize__(pVAS); } diff --git a/src/nvidia/generated/g_hw_resources_nvoc.c b/src/nvidia/generated/g_hw_resources_nvoc.c index adb0378bf2..61e32e807d 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.c +++ b/src/nvidia/generated/g_hw_resources_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_hwresIsReady(struct MemoryHwResources *pMem return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_hwresCheckCopyPermissions(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_hwresCheckCopyPermissions(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_hwresPreDestruct(struct MemoryHwResources *pResource) { diff --git a/src/nvidia/generated/g_hw_resources_nvoc.h b/src/nvidia/generated/g_hw_resources_nvoc.h index a284f6662a..3f7d3fa51b 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.h +++ b/src/nvidia/generated/g_hw_resources_nvoc.h @@ -72,7 +72,7 @@ struct MemoryHwResources { NV_STATUS (*__hwresControlFilter__)(struct MemoryHwResources *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresControlSerialization_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresIsReady__)(struct MemoryHwResources *, NvBool); - NV_STATUS (*__hwresCheckCopyPermissions__)(struct MemoryHwResources *, struct OBJGPU *, NvHandle); + NV_STATUS (*__hwresCheckCopyPermissions__)(struct MemoryHwResources *, struct OBJGPU *, struct Device *); void (*__hwresPreDestruct__)(struct MemoryHwResources *); NV_STATUS (*__hwresIsDuplicate__)(struct MemoryHwResources *, NvHandle, NvBool *); void (*__hwresControlSerialization_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -127,7 +127,7 @@ NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources**, Dynamic*, NvU3 #define hwresControlFilter(pResource, pCallContext, pParams) hwresControlFilter_DISPATCH(pResource, pCallContext, pParams) #define hwresControlSerialization_Prologue(pResource, pCallContext, pParams) hwresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define hwresIsReady(pMemory, bCopyConstructorContext) hwresIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define hwresCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) hwresCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define hwresCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) hwresCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define hwresPreDestruct(pResource) hwresPreDestruct_DISPATCH(pResource) #define hwresIsDuplicate(pMemory, hMemory, pDuplicate) hwresIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define hwresControlSerialization_Epilogue(pResource, pCallContext, pParams) hwresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -211,8 +211,8 @@ static inline NV_STATUS hwresIsReady_DISPATCH(struct MemoryHwResources *pMemory, return pMemory->__hwresIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS hwresCheckCopyPermissions_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__hwresCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS hwresCheckCopyPermissions_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__hwresCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void hwresPreDestruct_DISPATCH(struct MemoryHwResources *pResource) { diff --git a/src/nvidia/generated/g_hypervisor_nvoc.h b/src/nvidia/generated/g_hypervisor_nvoc.h index 1ae0b4b69a..80c55dc5c4 100644 --- a/src/nvidia/generated/g_hypervisor_nvoc.h +++ b/src/nvidia/generated/g_hypervisor_nvoc.h @@ -88,6 +88,7 @@ struct OBJHYPERVISOR { HYPERVISOR_TYPE type; NvBool bIsHypervHost; NvBool bIsHypervVgpuSupported; + NvBool bIsACSupported; }; #ifndef __NVOC_CLASS_OBJHYPERVISOR_TYPEDEF__ @@ -153,6 +154,25 @@ static inline void hypervisorSetHypervVgpuSupported(struct OBJHYPERVISOR *arg0) #define hypervisorSetHypervVgpuSupported_HAL(arg0) hypervisorSetHypervVgpuSupported(arg0) +NvBool hypervisorIsAC_IMPL(void); + + +#define hypervisorIsAC() hypervisorIsAC_IMPL() +#define hypervisorIsAC_HAL() hypervisorIsAC() + +void hypervisorSetACSupported_IMPL(struct OBJHYPERVISOR *arg0); + + +#ifdef __nvoc_hypervisor_h_disabled +static inline void hypervisorSetACSupported(struct OBJHYPERVISOR *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorSetACSupported(arg0) hypervisorSetACSupported_IMPL(arg0) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorSetACSupported_HAL(arg0) hypervisorSetACSupported(arg0) + NvBool hypervisorCheckForObjectAccess_IMPL(NvHandle hClient); #define hypervisorCheckForObjectAccess(hClient) hypervisorCheckForObjectAccess_IMPL(hClient) @@ -200,6 +220,16 @@ static inline HYPERVISOR_TYPE hypervisorGetHypervisorType(struct OBJHYPERVISOR * #define hypervisorGetHypervisorType(arg0) hypervisorGetHypervisorType_IMPL(arg0) #endif //__nvoc_hypervisor_h_disabled +void hypervisorSetHypervisorType_IMPL(struct OBJHYPERVISOR *pHypervisor, HYPERVISOR_TYPE type); + +#ifdef __nvoc_hypervisor_h_disabled +static inline void hypervisorSetHypervisorType(struct OBJHYPERVISOR *pHypervisor, HYPERVISOR_TYPE type) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorSetHypervisorType(pHypervisor, type) hypervisorSetHypervisorType_IMPL(pHypervisor, type) +#endif //__nvoc_hypervisor_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_intr_nvoc.c b/src/nvidia/generated/g_intr_nvoc.c index f9d2d96c34..c756e72338 100644 --- a/src/nvidia/generated/g_intr_nvoc.c +++ b/src/nvidia/generated/g_intr_nvoc.c @@ -193,11 +193,16 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->bDefaultNonstallNotify = ((NvBool)(0 == 0)); } - pThis->bTablesPopulated = ((NvBool)(0 != 0)); - - pThis->numPhysicalEntries = 0; - - pThis->numKernelEntries = 0; + // Hal field -- bUseLegacyVectorAssignment + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bUseLegacyVectorAssignment = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bUseLegacyVectorAssignment = ((NvBool)(0 == 0)); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -239,7 +244,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_4a4dee; } @@ -249,7 +254,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_c067f9; } @@ -259,7 +264,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_GA100; } @@ -280,7 +285,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_GA102; } @@ -290,7 +295,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_GA102; } @@ -300,49 +305,49 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_GA102; } // Hal function -- intrGetNumLeaves - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_TU102; + pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_GH100; + pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_TU102; } // Hal function -- intrGetLeafSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrGetLeafSize__ = &intrGetLeafSize_TU102; + pThis->__intrGetLeafSize__ = &intrGetLeafSize_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__intrGetLeafSize__ = &intrGetLeafSize_GH100; + pThis->__intrGetLeafSize__ = &intrGetLeafSize_TU102; } // Hal function -- intrGetIntrTopNonStallMask - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_TU102; + pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_GH100; + pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_TU102; } // Hal function -- intrSanityCheckEngineIntrStallVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GA100; + pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GH100; + pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GA100; } // default else @@ -351,13 +356,13 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec } // Hal function -- intrSanityCheckEngineIntrNotificationVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GA100; + pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GH100; + pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GA100; } // default else @@ -366,23 +371,17 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec } // Hal function -- intrStateLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__intrStateLoad__ = &intrStateLoad_TU102; - } + pThis->__intrStateLoad__ = &intrStateLoad_TU102; // Hal function -- intrStateUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__intrStateUnload__ = &intrStateUnload_TU102; - } + pThis->__intrStateUnload__ = &intrStateUnload_TU102; // Hal function -- intrSetIntrMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__intrSetIntrMask__ = &intrSetIntrMask_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrSetIntrMask__ = &intrSetIntrMask_46f6a7; } @@ -392,7 +391,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_d44104; } @@ -402,7 +401,7 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_b2b553; } diff --git a/src/nvidia/generated/g_intr_nvoc.h b/src/nvidia/generated/g_intr_nvoc.h index 0cd5721803..11d5b70c88 100644 --- a/src/nvidia/generated/g_intr_nvoc.h +++ b/src/nvidia/generated/g_intr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -34,15 +34,21 @@ extern "C" { #ifndef INTR_H #define INTR_H -#include "gpu/gpu.h" -#include "gpu/eng_state.h" -#include "nvoc/utility.h" -#include "utils/nvbitvector.h" -#include "dev_ctrl_defines.h" +#include "kernel/gpu/eng_state.h" +#include "kernel/gpu/gpu.h" #include "kernel/gpu/intr/engine_idx.h" +#include "kernel/gpu/intr/intr_common.h" #include "kernel/gpu/intr/intr_service.h" + #include "ctrl/ctrl2080/ctrl2080internal.h" +#include "dev_ctrl_defines.h" +#include "libraries/containers/list.h" +#include "libraries/containers/vector.h" +#include "libraries/nvoc/utility.h" +#include "libraries/utils/nvbitvector.h" + + // // Interrupt Type // @@ -80,33 +86,13 @@ typedef struct * unavailable */ NvU32 intrVectorNonStall; - /** Boolean set to NV_TRUE if Nonstalling interrupt is disabled in CTRL - * interrupt tree (Turing+). This may change to Enum in future. We are - * moving towards the direction where GSP-RM is fully aware of MC interrupt - * table and it provisions a subset of entries to CPU RM. - */ - NvBool bDisableNonStall; } INTR_TABLE_ENTRY; #define INTR_TABLE_MAX_INTRS_PER_ENTRY 6 -// -// The max number of interrupts we can fit in the dynamically populated, -// but statically sized, interrupt table. -// -#define INTR_TABLE_MAX_STATIC_KERNEL_INTRS 17 - -#define POPULATE_INTR_TABLE(pTable, numEntries, localMcEngineIdxs, localIntrVectors, localCount, localMax) \ -NV_ASSERT(numEntries + localCount <= localMax); \ -for (i = 0; i < localCount; i++) \ -{ \ - (pTable)[(numEntries)].mcEngine = (localMcEngineIdxs)[i]; \ - (pTable)[(numEntries)].pmcIntrMask = NV_PMC_INTR_INVALID_MASK; \ - (pTable)[(numEntries)].intrVector = (intrVectors)[i]; \ - (pTable)[(numEntries)].intrVectorNonStall = NV_INTR_VECTOR_INVALID; \ - numEntries++; \ -} +MAKE_VECTOR(InterruptTable, INTR_TABLE_ENTRY); +// // Default value for intrStuckThreshold #define INTR_STUCK_THRESHOLD 1000 @@ -189,6 +175,20 @@ typedef struct // #define INTR_MASK_FLAGS_ISR_SKIP_MASK_UPDATE NVBIT(0) + +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + + + #ifdef NVOC_INTR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else @@ -244,12 +244,11 @@ struct Intr { NvU32 accessCntrIntrVector; NvU32 displayIntrVector; NvU64 intrTopEnMask; - IntrServiceRecord intrServiceTable[166]; + IntrServiceRecord intrServiceTable[167]; NvBool bDefaultNonstallNotify; - NvU32 intrTableSz; - INTR_TABLE_ENTRY *pIntrTable; + NvBool bUseLegacyVectorAssignment; + InterruptTable intrTable; NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[7]; - INTR_TABLE_ENTRY pStaticKernelTable[17]; NvBool bDpcStarted; union MC_ENGINE_BITVECTOR pmcIntrPending; DPCQUEUE dpcQueue; @@ -263,9 +262,6 @@ struct Intr { NvU32 intrEn0Orig; NvBool halIntrEnabled; NvU32 saveIntrEn0; - NvBool bTablesPopulated; - NvU32 numPhysicalEntries; - NvU32 numKernelEntries; }; #ifndef __NVOC_CLASS_Intr_TYPEDEF__ @@ -995,37 +991,37 @@ static inline void intrRouteInterruptsToSystemFirmware(OBJGPU *pGpu, struct Intr #define intrRouteInterruptsToSystemFirmware_HAL(pGpu, pIntr, bEnable) intrRouteInterruptsToSystemFirmware(pGpu, pIntr, bEnable) -static inline NV_STATUS intrInitDynamicInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, INTR_TABLE_ENTRY *arg1, NvU32 arg2, NvU32 initFlags) { +static inline NV_STATUS intrInitDynamicInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, InterruptTable *arg1, NvU32 initFlags) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitDynamicInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, INTR_TABLE_ENTRY *arg1, NvU32 arg2, NvU32 initFlags) { +static inline NV_STATUS intrInitDynamicInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, InterruptTable *arg1, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrInitDynamicInterruptTable(pGpu, pIntr, arg0, arg1, arg2, initFlags) intrInitDynamicInterruptTable_5baef9(pGpu, pIntr, arg0, arg1, arg2, initFlags) +#define intrInitDynamicInterruptTable(pGpu, pIntr, arg0, arg1, initFlags) intrInitDynamicInterruptTable_5baef9(pGpu, pIntr, arg0, arg1, initFlags) #endif //__nvoc_intr_h_disabled -#define intrInitDynamicInterruptTable_HAL(pGpu, pIntr, arg0, arg1, arg2, initFlags) intrInitDynamicInterruptTable(pGpu, pIntr, arg0, arg1, arg2, initFlags) +#define intrInitDynamicInterruptTable_HAL(pGpu, pIntr, arg0, arg1, initFlags) intrInitDynamicInterruptTable(pGpu, pIntr, arg0, arg1, initFlags) -static inline NV_STATUS intrInitAnyInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **ppIntrTable, NvU32 *pIntrTableSz, NvU32 initFlags) { +static inline NV_STATUS intrInitAnyInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitAnyInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **ppIntrTable, NvU32 *pIntrTableSz, NvU32 initFlags) { +static inline NV_STATUS intrInitAnyInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrInitAnyInterruptTable(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) intrInitAnyInterruptTable_5baef9(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) +#define intrInitAnyInterruptTable(pGpu, pIntr, pIntrTable, initFlags) intrInitAnyInterruptTable_5baef9(pGpu, pIntr, pIntrTable, initFlags) #endif //__nvoc_intr_h_disabled -#define intrInitAnyInterruptTable_HAL(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) intrInitAnyInterruptTable(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) +#define intrInitAnyInterruptTable_HAL(pGpu, pIntr, pIntrTable, initFlags) intrInitAnyInterruptTable(pGpu, pIntr, pIntrTable, initFlags) static inline NV_STATUS intrInitSubtreeMap_395e98(OBJGPU *pGpu, struct Intr *pIntr) { return NV_ERR_NOT_SUPPORTED; @@ -1061,19 +1057,19 @@ static inline NV_STATUS intrInitInterruptTable(OBJGPU *pGpu, struct Intr *pIntr) #define intrInitInterruptTable_HAL(pGpu, pIntr) intrInitInterruptTable(pGpu, pIntr) -NV_STATUS intrGetInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **arg0, NvU32 *arg1); +NV_STATUS intrGetInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable **ppIntrTable); #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrGetInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **arg0, NvU32 *arg1) { +static inline NV_STATUS intrGetInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable **ppIntrTable) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrGetInterruptTable(pGpu, pIntr, arg0, arg1) intrGetInterruptTable_IMPL(pGpu, pIntr, arg0, arg1) +#define intrGetInterruptTable(pGpu, pIntr, ppIntrTable) intrGetInterruptTable_IMPL(pGpu, pIntr, ppIntrTable) #endif //__nvoc_intr_h_disabled -#define intrGetInterruptTable_HAL(pGpu, pIntr, arg0, arg1) intrGetInterruptTable(pGpu, pIntr, arg0, arg1) +#define intrGetInterruptTable_HAL(pGpu, pIntr, ppIntrTable) intrGetInterruptTable(pGpu, pIntr, ppIntrTable) NV_STATUS intrDestroyInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr); @@ -1109,85 +1105,65 @@ static inline NV_STATUS intrGetStaticVFmcEngines(OBJGPU *pGpu, struct Intr *pInt #define intrGetStaticVFmcEngines_HAL(pGpu, pIntr, ppMcEngines, pCount) intrGetStaticVFmcEngines(pGpu, pIntr, ppMcEngines, pCount) -static inline NV_STATUS intrGetStaticInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags) { +static inline NV_STATUS intrGetStaticInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -NV_STATUS intrGetStaticInterruptTable_TU102(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); +NV_STATUS intrGetStaticInterruptTable_TU102(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags); -NV_STATUS intrGetStaticInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); +NV_STATUS intrGetStaticInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags); -NV_STATUS intrGetStaticInterruptTable_GA102(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); +NV_STATUS intrGetStaticInterruptTable_GA102(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags); -NV_STATUS intrGetStaticInterruptTable_GH100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); +NV_STATUS intrGetStaticInterruptTable_GH100(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags); #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrGetStaticInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags) { +static inline NV_STATUS intrGetStaticInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pTable, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrGetStaticInterruptTable(pGpu, pIntr, pTable, pCount, maxCount, initFlags) intrGetStaticInterruptTable_5baef9(pGpu, pIntr, pTable, pCount, maxCount, initFlags) -#endif //__nvoc_intr_h_disabled - -#define intrGetStaticInterruptTable_HAL(pGpu, pIntr, pTable, pCount, maxCount, initFlags) intrGetStaticInterruptTable(pGpu, pIntr, pTable, pCount, maxCount, initFlags) - -static inline NvU32 intrGetGPUHostInterruptTableSize_5baef9(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - -NvU32 intrGetGPUHostInterruptTableSize_GM107(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags); - -NvU32 intrGetGPUHostInterruptTableSize_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags); - - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrGetGPUHostInterruptTableSize(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrGetGPUHostInterruptTableSize(pGpu, pIntr, initFlags) intrGetGPUHostInterruptTableSize_5baef9(pGpu, pIntr, initFlags) +#define intrGetStaticInterruptTable(pGpu, pIntr, pTable, initFlags) intrGetStaticInterruptTable_5baef9(pGpu, pIntr, pTable, initFlags) #endif //__nvoc_intr_h_disabled -#define intrGetGPUHostInterruptTableSize_HAL(pGpu, pIntr, initFlags) intrGetGPUHostInterruptTableSize(pGpu, pIntr, initFlags) +#define intrGetStaticInterruptTable_HAL(pGpu, pIntr, pTable, initFlags) intrGetStaticInterruptTable(pGpu, pIntr, pTable, initFlags) -static inline NV_STATUS intrInitGPUHostInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags) { +static inline NV_STATUS intrInitGPUHostInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -NV_STATUS intrInitGPUHostInterruptTable_GM107(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags); +NV_STATUS intrInitGPUHostInterruptTable_GM107(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags); -NV_STATUS intrInitGPUHostInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags); +NV_STATUS intrInitGPUHostInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags); #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitGPUHostInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags) { +static inline NV_STATUS intrInitGPUHostInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrInitGPUHostInterruptTable(pGpu, pIntr, arg0, arg1, initFlags) intrInitGPUHostInterruptTable_5baef9(pGpu, pIntr, arg0, arg1, initFlags) +#define intrInitGPUHostInterruptTable(pGpu, pIntr, pIntrTable, initFlags) intrInitGPUHostInterruptTable_5baef9(pGpu, pIntr, pIntrTable, initFlags) #endif //__nvoc_intr_h_disabled -#define intrInitGPUHostInterruptTable_HAL(pGpu, pIntr, arg0, arg1, initFlags) intrInitGPUHostInterruptTable(pGpu, pIntr, arg0, arg1, initFlags) +#define intrInitGPUHostInterruptTable_HAL(pGpu, pIntr, pIntrTable, initFlags) intrInitGPUHostInterruptTable(pGpu, pIntr, pIntrTable, initFlags) -static inline NV_STATUS intrInitEngineSchedInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1) { +static inline NV_STATUS intrInitEngineSchedInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitEngineSchedInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1) { +static inline NV_STATUS intrInitEngineSchedInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable *pIntrTable) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrInitEngineSchedInterruptTable(pGpu, pIntr, arg0, arg1) intrInitEngineSchedInterruptTable_5baef9(pGpu, pIntr, arg0, arg1) +#define intrInitEngineSchedInterruptTable(pGpu, pIntr, pIntrTable) intrInitEngineSchedInterruptTable_5baef9(pGpu, pIntr, pIntrTable) #endif //__nvoc_intr_h_disabled -#define intrInitEngineSchedInterruptTable_HAL(pGpu, pIntr, arg0, arg1) intrInitEngineSchedInterruptTable(pGpu, pIntr, arg0, arg1) +#define intrInitEngineSchedInterruptTable_HAL(pGpu, pIntr, pIntrTable) intrInitEngineSchedInterruptTable(pGpu, pIntr, pIntrTable) void intrServiceStall_IMPL(OBJGPU *pGpu, struct Intr *pIntr); @@ -1299,27 +1275,27 @@ static inline NV_STATUS intrGetNvlinkIntrMaskOffset(OBJGPU *pGpu, struct Intr *p #define intrGetNvlinkIntrMaskOffset_HAL(pGpu, pIntr, arg0, arg1) intrGetNvlinkIntrMaskOffset(pGpu, pIntr, arg0, arg1) -static inline NV_STATUS intrGetEccVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1) { +static inline NV_STATUS intrGetEccVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -NV_STATUS intrGetEccVirtualFunctionIntrMask_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); +NV_STATUS intrGetEccVirtualFunctionIntrMask_TU102(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); -NV_STATUS intrGetEccVirtualFunctionIntrMask_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); +NV_STATUS intrGetEccVirtualFunctionIntrMask_GA100(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); -NV_STATUS intrGetEccVirtualFunctionIntrMask_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); +NV_STATUS intrGetEccVirtualFunctionIntrMask_GH100(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); #ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrGetEccVirtualFunctionIntrMask(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1) { +static inline NV_STATUS intrGetEccVirtualFunctionIntrMask(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, arg0, arg1) intrGetEccVirtualFunctionIntrMask_5baef9(pGpu, pIntr, arg0, arg1) +#define intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, pDevice, arg0) intrGetEccVirtualFunctionIntrMask_5baef9(pGpu, pIntr, pDevice, arg0) #endif //__nvoc_intr_h_disabled -#define intrGetEccVirtualFunctionIntrMask_HAL(pGpu, pIntr, arg0, arg1) intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, arg0, arg1) +#define intrGetEccVirtualFunctionIntrMask_HAL(pGpu, pIntr, pDevice, arg0) intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, pDevice, arg0) static inline NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); @@ -1979,19 +1955,6 @@ static inline void intrGetGmmuInterrupts(OBJGPU *pGpu, struct Intr *pIntr, union // This mask is used for interrupts that should be masked off in the PMC tree #define NV_PMC_INTR_INVALID_MASK (0) -#define INTR_WRITE_TABLE(status, pTable, maxCount, count, entry) \ - do { \ - if ((count) < (maxCount)) \ - { \ - (pTable)[count] = entry; \ - } \ - else \ - { \ - status = NV_ERR_BUFFER_TOO_SMALL; \ - } \ - count += 1; \ - } while(0) - #endif // INTR_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_intr_service_nvoc.h b/src/nvidia/generated/g_intr_service_nvoc.h index 2747294410..1476bd2413 100644 --- a/src/nvidia/generated/g_intr_service_nvoc.h +++ b/src/nvidia/generated/g_intr_service_nvoc.h @@ -122,9 +122,9 @@ NV_STATUS __nvoc_objCreate_IntrService(IntrService**, Dynamic*, NvU32); #define intrservClearInterrupt(pGpu, pIntrService, pParams) intrservClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceInterrupt(pGpu, pIntrService, pParams) intrservServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceNotificationInterrupt(pGpu, pIntrService, pParams) intrservServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) -void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[166]); +void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[167]); -static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[166]) { +static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[167]) { pIntrService->__intrservRegisterIntrService__(pGpu, pIntrService, pRecords); } diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.c b/src/nvidia/generated/g_io_vaspace_nvoc.c index dd2ffaa401..66009efdd9 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.c +++ b/src/nvidia/generated/g_io_vaspace_nvoc.c @@ -118,7 +118,7 @@ static NvBool __nvoc_thunk_OBJVASPACE_iovaspaceIsAtsEnabled(struct OBJIOVASPACE return vaspaceIsAtsEnabled((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset)); } -static NvU32 __nvoc_thunk_OBJVASPACE_iovaspaceGetBigPageSize(struct OBJIOVASPACE *pVAS) { +static NvU64 __nvoc_thunk_OBJVASPACE_iovaspaceGetBigPageSize(struct OBJIOVASPACE *pVAS) { return vaspaceGetBigPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset)); } diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.h b/src/nvidia/generated/g_io_vaspace_nvoc.h index b38a7747b7..10376ebe28 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.h +++ b/src/nvidia/generated/g_io_vaspace_nvoc.h @@ -159,7 +159,7 @@ struct OBJIOVASPACE { NvBool (*__iovaspaceIsInternalVaRestricted__)(struct OBJIOVASPACE *); NvU32 (*__iovaspaceGetFlags__)(struct OBJIOVASPACE *); NvBool (*__iovaspaceIsAtsEnabled__)(struct OBJIOVASPACE *); - NvU32 (*__iovaspaceGetBigPageSize__)(struct OBJIOVASPACE *); + NvU64 (*__iovaspaceGetBigPageSize__)(struct OBJIOVASPACE *); NV_STATUS (*__iovaspaceGetPteInfo__)(struct OBJIOVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); PMEMORY_DESCRIPTOR (*__iovaspaceGetPageDirBase__)(struct OBJIOVASPACE *, struct OBJGPU *); PMEMORY_DESCRIPTOR (*__iovaspaceGetKernelPageDirBase__)(struct OBJIOVASPACE *, struct OBJGPU *); @@ -305,7 +305,7 @@ static inline NvBool iovaspaceIsAtsEnabled_DISPATCH(struct OBJIOVASPACE *pVAS) { return pVAS->__iovaspaceIsAtsEnabled__(pVAS); } -static inline NvU32 iovaspaceGetBigPageSize_DISPATCH(struct OBJIOVASPACE *pVAS) { +static inline NvU64 iovaspaceGetBigPageSize_DISPATCH(struct OBJIOVASPACE *pVAS) { return pVAS->__iovaspaceGetBigPageSize__(pVAS); } diff --git a/src/nvidia/generated/g_kern_bus_nvoc.c b/src/nvidia/generated/g_kern_bus_nvoc.c index ccf872aacd..c2927afc75 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.c +++ b/src/nvidia/generated/g_kern_bus_nvoc.c @@ -78,6 +78,10 @@ static NV_STATUS __nvoc_thunk_KernelBus_engstateStateInitLocked(OBJGPU *pGpu, st return kbusStateInitLocked(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } +static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePreLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { + return kbusStatePreLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); +} + static NV_STATUS __nvoc_thunk_KernelBus_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { return kbusStateLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } @@ -98,10 +102,6 @@ static void __nvoc_thunk_KernelBus_engstateStateDestroy(OBJGPU *pGpu, struct OBJ kbusStateDestroy(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStatePreLoad(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { - return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStatePostUnload(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } @@ -258,100 +258,87 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusConstructEngine__ = &kbusConstructEngine_IMPL; // Hal function -- kbusStatePreInitLocked - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStatePreInitLocked__ = &kbusStatePreInitLocked_GM107; - } + pThis->__kbusStatePreInitLocked__ = &kbusStatePreInitLocked_GM107; pThis->__kbusStateInitLocked__ = &kbusStateInitLocked_IMPL; + // Hal function -- kbusStatePreLoad + pThis->__kbusStatePreLoad__ = &kbusStatePreLoad_56cd7a; + // Hal function -- kbusStateLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStateLoad__ = &kbusStateLoad_GM107; - } - } + pThis->__kbusStateLoad__ = &kbusStateLoad_GM107; // Hal function -- kbusStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStatePostLoad__ = &kbusStatePostLoad_GM107; - } + pThis->__kbusStatePostLoad__ = &kbusStatePostLoad_GM107; // Hal function -- kbusStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStatePreUnload__ = &kbusStatePreUnload_GM107; - } + pThis->__kbusStatePreUnload__ = &kbusStatePreUnload_GM107; // Hal function -- kbusStateUnload - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; - } - } + pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; // Hal function -- kbusStateDestroy - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusStateDestroy__ = &kbusStateDestroy_GM107; - } + pThis->__kbusStateDestroy__ = &kbusStateDestroy_GM107; // Hal function -- kbusTeardownBar2CpuAperture - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GH100; - } + pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GH100; + } + else + { + pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GM107; } // Hal function -- kbusGetP2PMailboxAttributes - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GM200; + pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GH100; + pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GM200; } // Hal function -- kbusCreateP2PMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GP100; + pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GH100; + pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GP100; } // Hal function -- kbusRemoveP2PMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GH100; + } + else { pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kbusGetEgmPeerId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GH100; + pThis->__kbusGetEgmPeerId__ = &kbusGetEgmPeerId_GH100; + } + // default + else + { + pThis->__kbusGetEgmPeerId__ = &kbusGetEgmPeerId_56cd7a; } // Hal function -- kbusGetPeerId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusGetPeerId__ = &kbusGetPeerId_GP100; + pThis->__kbusGetPeerId__ = &kbusGetPeerId_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusGetPeerId__ = &kbusGetPeerId_GH100; + pThis->__kbusGetPeerId__ = &kbusGetPeerId_GP100; } // Hal function -- kbusGetNvSwitchPeerId @@ -366,70 +353,67 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusGetUnusedPciePeerId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_GM107; + pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_TU102; + pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_GM107; } // Hal function -- kbusIsPeerIdValid - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GP100; + pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GH100; + pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GP100; } // Hal function -- kbusGetNvlinkP2PPeerId - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; + } + else + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; } // Hal function -- kbusWriteP2PWmbTag - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GM200; + pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GH100; + pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GM200; } // Hal function -- kbusSetupP2PDomainAccess - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GM200; + pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GH100; + pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GM200; } // Hal function -- kbusNeedWarForBug999673 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_GM200; + pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_491d52; + pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_GM200; } // Hal function -- kbusCreateP2PMappingForC2C @@ -455,13 +439,79 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusUnreserveP2PPeerIds - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_46f6a7; + } + else { pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + + // Hal function -- kbusNeedStaticBar1Mapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_46f6a7; + pThis->__kbusNeedStaticBar1Mapping__ = &kbusNeedStaticBar1Mapping_GH100; + } + // default + else + { + pThis->__kbusNeedStaticBar1Mapping__ = &kbusNeedStaticBar1Mapping_bf6dfa; + } + + // Hal function -- kbusEnableStaticBar1Mapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusEnableStaticBar1Mapping__ = &kbusEnableStaticBar1Mapping_GH100; + } + // default + else + { + pThis->__kbusEnableStaticBar1Mapping__ = &kbusEnableStaticBar1Mapping_46f6a7; + } + + // Hal function -- kbusDisableStaticBar1Mapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusDisableStaticBar1Mapping__ = &kbusDisableStaticBar1Mapping_GH100; + } + // default + else + { + pThis->__kbusDisableStaticBar1Mapping__ = &kbusDisableStaticBar1Mapping_56cd7a; + } + + // Hal function -- kbusGetBar1P2PDmaInfo + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_GH100; + } + // default + else + { + pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_395e98; + } + + // Hal function -- kbusStaticMapFbAperture + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusStaticMapFbAperture__ = &kbusStaticMapFbAperture_GH100; + } + // default + else + { + pThis->__kbusStaticMapFbAperture__ = &kbusStaticMapFbAperture_395e98; + } + + // Hal function -- kbusStaticUnmapFbAperture + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusStaticUnmapFbAperture__ = &kbusStaticUnmapFbAperture_GH100; + } + // default + else + { + pThis->__kbusStaticUnmapFbAperture__ = &kbusStaticUnmapFbAperture_395e98; } // Hal function -- kbusCreateP2PMappingForBar1P2P @@ -497,12 +547,34 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_491d52; } + // Hal function -- kbusIsPcieBar1P2PMappingSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_GH100; + } + // default + else + { + pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_491d52; + } + + // Hal function -- kbusSetupBar1P2PCapability + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetupBar1P2PCapability__ = &kbusSetupBar1P2PCapability_GH100; + } + // default + else + { + pThis->__kbusSetupBar1P2PCapability__ = &kbusSetupBar1P2PCapability_b3696a; + } + // Hal function -- kbusCheckFlaSupportedAndInit if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusCheckFlaSupportedAndInit__ = &kbusCheckFlaSupportedAndInit_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusCheckFlaSupportedAndInit__ = &kbusCheckFlaSupportedAndInit_ac1694; } @@ -557,7 +629,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusAllocateLegacyFlaVaspace__ = &kbusAllocateLegacyFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusAllocateLegacyFlaVaspace__ = &kbusAllocateLegacyFlaVaspace_395e98; } @@ -567,7 +639,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusAllocateHostManagedFlaVaspace__ = &kbusAllocateHostManagedFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusAllocateHostManagedFlaVaspace__ = &kbusAllocateHostManagedFlaVaspace_395e98; } @@ -592,7 +664,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_395e98; } @@ -602,7 +674,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusDestroyHostManagedFlaVaspace__ = &kbusDestroyHostManagedFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusDestroyHostManagedFlaVaspace__ = &kbusDestroyHostManagedFlaVaspace_d44104; } @@ -612,7 +684,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusVerifyFlaRange__ = &kbusVerifyFlaRange_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusVerifyFlaRange__ = &kbusVerifyFlaRange_bf6dfa; } @@ -622,7 +694,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusConstructFlaInstBlk__ = &kbusConstructFlaInstBlk_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusConstructFlaInstBlk__ = &kbusConstructFlaInstBlk_395e98; } @@ -632,7 +704,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusDestructFlaInstBlk__ = &kbusDestructFlaInstBlk_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusDestructFlaInstBlk__ = &kbusDestructFlaInstBlk_d44104; } @@ -642,43 +714,37 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusValidateFlaBaseAddress__ = &kbusValidateFlaBaseAddress_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusValidateFlaBaseAddress__ = &kbusValidateFlaBaseAddress_395e98; } // Hal function -- kbusSetupUnbindFla - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_46f6a7; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GH100; + } + else + { + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_46f6a7; } // Hal function -- kbusSetupBindFla - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_46f6a7; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GH100; + } + else + { + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_46f6a7; } // Hal function -- kbusIsDirectMappingAllowed @@ -686,7 +752,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusIsDirectMappingAllowed__ = &kbusIsDirectMappingAllowed_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kbusIsDirectMappingAllowed__ = &kbusIsDirectMappingAllowed_GA100; } @@ -696,7 +762,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GA100; } @@ -706,7 +772,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusWriteBAR0WindowBase__ = &kbusWriteBAR0WindowBase_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusWriteBAR0WindowBase__ = &kbusWriteBAR0WindowBase_395e98; } @@ -716,7 +782,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusReadBAR0WindowBase__ = &kbusReadBAR0WindowBase_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusReadBAR0WindowBase__ = &kbusReadBAR0WindowBase_13cd8d; } @@ -726,45 +792,50 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusValidateBAR0WindowBase__ = &kbusValidateBAR0WindowBase_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusValidateBAR0WindowBase__ = &kbusValidateBAR0WindowBase_ceaee8; } // Hal function -- kbusSetBAR0WindowVidOffset - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GH100; - } + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GH100; + } + else + { + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GM107; } // Hal function -- kbusGetBAR0WindowVidOffset - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GM107; + pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GH100; + pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GM107; } // Hal function -- kbusVerifyBar2 - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GH100; - } + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GH100; + } + else + { + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GM107; + } + + // Hal function -- kbusVerifyCoherentLink + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusVerifyCoherentLink__ = &kbusVerifyCoherentLink_GH100; + } + // default + else + { + pThis->__kbusVerifyCoherentLink__ = &kbusVerifyCoherentLink_56cd7a; } // Hal function -- kbusFlushPcieForBar0Doorbell @@ -772,11 +843,22 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusFlushPcieForBar0Doorbell__ = &kbusFlushPcieForBar0Doorbell_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kbusFlushPcieForBar0Doorbell__ = &kbusFlushPcieForBar0Doorbell_56cd7a; } + // Hal function -- kbusCreateCoherentCpuMapping + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusCreateCoherentCpuMapping__ = &kbusCreateCoherentCpuMapping_GH100; + } + // default + else + { + pThis->__kbusCreateCoherentCpuMapping__ = &kbusCreateCoherentCpuMapping_46f6a7; + } + // Hal function -- kbusMapCoherentCpuMapping if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -816,6 +898,8 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelBus_engstateStateInitLocked; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreLoad__ = &__nvoc_thunk_KernelBus_engstateStatePreLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelBus_engstateStateLoad; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelBus_engstateStatePostLoad; @@ -826,8 +910,6 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelBus_engstateStateDestroy; - pThis->__kbusStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePreLoad; - pThis->__kbusStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePostUnload; pThis->__kbusStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kbusStateInitUnlocked; @@ -851,7 +933,7 @@ NvU32 kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(OBJGPU *pGpu) { { return kbusGetP2PWriteMailboxAddressSize_GH100(pGpu); } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { return kbusGetP2PWriteMailboxAddressSize_474d46(pGpu); } diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h index 20ed69026e..13981ff486 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.h +++ b/src/nvidia/generated/g_kern_bus_nvoc.h @@ -52,7 +52,7 @@ extern "C" { // // Virtual BAR2 mapping info is shared by tesla and fermi code // -#if defined(NV_UNIX) && defined(NVCPU_X86_64) +#if defined(NV_UNIX) && (defined(NVCPU_X86_64) || defined(NVCPU_AARCH64)) // 64-bit Unix can support many more mappings than some other operating systems: #define BUS_BAR2_MAX_MAPPINGS 200 #else @@ -174,6 +174,19 @@ typedef struct MAKE_INTRUSIVE_LIST(VirtualBar2MapList, VirtualBar2MapEntry, node); +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + + + #ifdef NVOC_KERN_BUS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else @@ -185,6 +198,13 @@ struct __nvoc_inner_struc_KernelBus_1__ { struct OBJVASPACE *pVAS; NvU64 instBlockBase; MEMORY_DESCRIPTOR *pInstBlkMemDesc; + NvBool bStaticBar1Enabled; + struct { + MEMORY_DESCRIPTOR *pVidMemDesc; + MEMORY_DESCRIPTOR *pDmaMemDesc; + NvU64 base; + NvU64 size; + } staticBar1; }; struct __nvoc_inner_struc_KernelBus_2__ { @@ -214,6 +234,7 @@ struct __nvoc_inner_struc_KernelBus_2__ { NvU32 pageDirSize; NvU32 numPageTbls; NvU32 pageTblSize; + NvBool bIsBar2SizeReduced; NvU32 pageDirInit; NvU32 pageTblInit; }; @@ -269,6 +290,7 @@ struct __nvoc_inner_struc_KernelBus_6__ { NvU32 busNvlinkMappingRefcountPerGpu[32]; NvU32 busNvlinkMappingRefcountPerPeerId[8]; NvU32 busNvlinkMappingRefcountPerPeerIdSpa[8]; + NvBool bEgmPeer[8]; }; struct __nvoc_inner_struc_KernelBus_7__ { @@ -297,6 +319,7 @@ struct KernelBus { NV_STATUS (*__kbusConstructEngine__)(OBJGPU *, struct KernelBus *, ENGDESCRIPTOR); NV_STATUS (*__kbusStatePreInitLocked__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusStateInitLocked__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusStatePreLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePostLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePreUnload__)(OBJGPU *, struct KernelBus *, NvU32); @@ -306,20 +329,29 @@ struct KernelBus { void (*__kbusGetP2PMailboxAttributes__)(OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32 *); NV_STATUS (*__kbusCreateP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kbusRemoveP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); + NvU32 (*__kbusGetEgmPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *); NvU32 (*__kbusGetPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *); NvU32 (*__kbusGetNvSwitchPeerId__)(OBJGPU *, struct KernelBus *); NvU32 (*__kbusGetUnusedPciePeerId__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusIsPeerIdValid__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusGetNvlinkP2PPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *); + NV_STATUS (*__kbusGetNvlinkP2PPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32); void (*__kbusWriteP2PWmbTag__)(OBJGPU *, struct KernelBus *, NvU32, NvU64); RmPhysAddr (*__kbusSetupP2PDomainAccess__)(OBJGPU *, struct KernelBus *, OBJGPU *, PMEMORY_DESCRIPTOR *); NvBool (*__kbusNeedWarForBug999673__)(OBJGPU *, struct KernelBus *, OBJGPU *); NV_STATUS (*__kbusCreateP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kbusRemoveP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); NV_STATUS (*__kbusUnreserveP2PPeerIds__)(OBJGPU *, struct KernelBus *, NvU32); + NvBool (*__kbusNeedStaticBar1Mapping__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusEnableStaticBar1Mapping__)(OBJGPU *, struct KernelBus *, NvU64, NvU32); + NV_STATUS (*__kbusDisableStaticBar1Mapping__)(OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusGetBar1P2PDmaInfo__)(OBJGPU *, OBJGPU *, struct KernelBus *, NvU64 *, NvU64 *); + NV_STATUS (*__kbusStaticMapFbAperture__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU64, NvU64 *, NvU64 *, NvU32); + NV_STATUS (*__kbusStaticUnmapFbAperture__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU32); NV_STATUS (*__kbusCreateP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusRemoveP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); NvBool (*__kbusHasPcieBar1P2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *); + NvBool (*__kbusIsPcieBar1P2PMappingSupported__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *); + void (*__kbusSetupBar1P2PCapability__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusCheckFlaSupportedAndInit__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); NV_STATUS (*__kbusDetermineFlaRangeAndAllocate__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); NV_STATUS (*__kbusAllocateFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); @@ -343,11 +375,12 @@ struct KernelBus { NV_STATUS (*__kbusSetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *, NvU64); NvU64 (*__kbusGetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusVerifyBar2__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU8 *, NvU64, NvU64); + NV_STATUS (*__kbusVerifyCoherentLink__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusFlushPcieForBar0Doorbell__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusCreateCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvU64, NvBool); NvU8 *(*__kbusMapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusUnmapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusTeardownCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvBool); - NV_STATUS (*__kbusStatePreLoad__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePostUnload__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateInitUnlocked__)(POBJGPU, struct KernelBus *); void (*__kbusInitMissing__)(POBJGPU, struct KernelBus *); @@ -392,6 +425,7 @@ struct KernelBus { NvBool bIsBar2SetupInPhysicalMode; NvBool bPreserveBar1ConsoleEnabled; NvBool bBar1ConsolePreserved; + NvBool bBarAccessBlocked; NvBool bBug2751296LimitBar2PtSize; NvBool bAllowReflectedMappingAccess; NvBool bBar2Tunnelled; @@ -447,6 +481,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusStatePreInitLocked(pGpu, pKernelBus) kbusStatePreInitLocked_DISPATCH(pGpu, pKernelBus) #define kbusStatePreInitLocked_HAL(pGpu, pKernelBus) kbusStatePreInitLocked_DISPATCH(pGpu, pKernelBus) #define kbusStateInitLocked(pGpu, pKernelBus) kbusStateInitLocked_DISPATCH(pGpu, pKernelBus) +#define kbusStatePreLoad(pGpu, pKernelBus, arg0) kbusStatePreLoad_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusStatePreLoad_HAL(pGpu, pKernelBus, arg0) kbusStatePreLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStateLoad(pGpu, pKernelBus, arg0) kbusStateLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStateLoad_HAL(pGpu, pKernelBus, arg0) kbusStateLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStatePostLoad(pGpu, pKernelBus, arg0) kbusStatePostLoad_DISPATCH(pGpu, pKernelBus, arg0) @@ -467,6 +503,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusCreateP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusRemoveP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusRemoveP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) +#define kbusGetEgmPeerId(pLocalGpu, pLocalKernelBus, pRemoteGpu) kbusGetEgmPeerId_DISPATCH(pLocalGpu, pLocalKernelBus, pRemoteGpu) +#define kbusGetEgmPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu) kbusGetEgmPeerId_DISPATCH(pLocalGpu, pLocalKernelBus, pRemoteGpu) #define kbusGetPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) #define kbusGetPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) #define kbusGetNvSwitchPeerId(pGpu, pKernelBus) kbusGetNvSwitchPeerId_DISPATCH(pGpu, pKernelBus) @@ -475,8 +513,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusGetUnusedPciePeerId_HAL(pGpu, pKernelBus) kbusGetUnusedPciePeerId_DISPATCH(pGpu, pKernelBus) #define kbusIsPeerIdValid(pGpu, pKernelBus, peerId) kbusIsPeerIdValid_DISPATCH(pGpu, pKernelBus, peerId) #define kbusIsPeerIdValid_HAL(pGpu, pKernelBus, peerId) kbusIsPeerIdValid_DISPATCH(pGpu, pKernelBus, peerId) -#define kbusGetNvlinkP2PPeerId(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) -#define kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer) +#define kbusGetNvlinkP2PPeerId(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes) +#define kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes) kbusGetNvlinkP2PPeerId_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes) #define kbusWriteP2PWmbTag(pGpu, pKernelBus, remote2Local, p2pWmbTag) kbusWriteP2PWmbTag_DISPATCH(pGpu, pKernelBus, remote2Local, p2pWmbTag) #define kbusWriteP2PWmbTag_HAL(pGpu, pKernelBus, remote2Local, p2pWmbTag) kbusWriteP2PWmbTag_DISPATCH(pGpu, pKernelBus, remote2Local, p2pWmbTag) #define kbusSetupP2PDomainAccess(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) kbusSetupP2PDomainAccess_DISPATCH(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) @@ -489,12 +527,28 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusRemoveP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusUnreserveP2PPeerIds(pGpu, pKernelBus, peerMask) kbusUnreserveP2PPeerIds_DISPATCH(pGpu, pKernelBus, peerMask) #define kbusUnreserveP2PPeerIds_HAL(pGpu, pKernelBus, peerMask) kbusUnreserveP2PPeerIds_DISPATCH(pGpu, pKernelBus, peerMask) +#define kbusNeedStaticBar1Mapping(pGpu, pKernelBus) kbusNeedStaticBar1Mapping_DISPATCH(pGpu, pKernelBus) +#define kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus) kbusNeedStaticBar1Mapping_DISPATCH(pGpu, pKernelBus) +#define kbusEnableStaticBar1Mapping(pGpu, pKernelBus, reservedFbSize, gfid) kbusEnableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, reservedFbSize, gfid) +#define kbusEnableStaticBar1Mapping_HAL(pGpu, pKernelBus, reservedFbSize, gfid) kbusEnableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, reservedFbSize, gfid) +#define kbusDisableStaticBar1Mapping(pGpu, pKernelBus, gfid) kbusDisableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusDisableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid) kbusDisableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusGetBar1P2PDmaInfo(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) kbusGetBar1P2PDmaInfo_DISPATCH(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) +#define kbusGetBar1P2PDmaInfo_HAL(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) kbusGetBar1P2PDmaInfo_DISPATCH(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) +#define kbusStaticMapFbAperture(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) kbusStaticMapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) +#define kbusStaticMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) kbusStaticMapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) +#define kbusStaticUnmapFbAperture(pGpu, pKernelBus, pMemDesc, gfid) kbusStaticUnmapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, gfid) +#define kbusStaticUnmapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, gfid) kbusStaticUnmapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, gfid) #define kbusCreateP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusCreateP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusRemoveP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusRemoveP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusHasPcieBar1P2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) #define kbusHasPcieBar1P2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusSetupBar1P2PCapability(pGpu, pKernelBus) kbusSetupBar1P2PCapability_DISPATCH(pGpu, pKernelBus) +#define kbusSetupBar1P2PCapability_HAL(pGpu, pKernelBus) kbusSetupBar1P2PCapability_DISPATCH(pGpu, pKernelBus) #define kbusCheckFlaSupportedAndInit(pGpu, pKernelBus, base, size) kbusCheckFlaSupportedAndInit_DISPATCH(pGpu, pKernelBus, base, size) #define kbusCheckFlaSupportedAndInit_HAL(pGpu, pKernelBus, base, size) kbusCheckFlaSupportedAndInit_DISPATCH(pGpu, pKernelBus, base, size) #define kbusDetermineFlaRangeAndAllocate(pGpu, pKernelBus, base, size) kbusDetermineFlaRangeAndAllocate_DISPATCH(pGpu, pKernelBus, base, size) @@ -541,15 +595,18 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus) #define kbusVerifyBar2(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_DISPATCH(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) #define kbusVerifyBar2_HAL(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_DISPATCH(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) +#define kbusVerifyCoherentLink(pGpu, pKernelBus) kbusVerifyCoherentLink_DISPATCH(pGpu, pKernelBus) +#define kbusVerifyCoherentLink_HAL(pGpu, pKernelBus) kbusVerifyCoherentLink_DISPATCH(pGpu, pKernelBus) #define kbusFlushPcieForBar0Doorbell(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_DISPATCH(pGpu, pKernelBus) #define kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_DISPATCH(pGpu, pKernelBus) +#define kbusCreateCoherentCpuMapping(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) kbusCreateCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) +#define kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) kbusCreateCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) #define kbusMapCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusMapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusMapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusMapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusUnmapCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) -#define kbusStatePreLoad(pGpu, pEngstate, arg0) kbusStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbusStatePostUnload(pGpu, pEngstate, arg0) kbusStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbusStateInitUnlocked(pGpu, pEngstate) kbusStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbusInitMissing(pGpu, pEngstate) kbusInitMissing_DISPATCH(pGpu, pEngstate) @@ -1078,6 +1135,24 @@ static inline void kbusDestroyPeerAccess(OBJGPU *pGpu, struct KernelBus *pKernel #define kbusDestroyPeerAccess_HAL(pGpu, pKernelBus, peerNum) kbusDestroyPeerAccess(pGpu, pKernelBus, peerNum) +NvU32 kbusGetNvlinkPeerId_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); + +static inline NvU32 kbusGetNvlinkPeerId_c732fb(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu) { + return 4294967295U; +} + + +#ifdef __nvoc_kern_bus_h_disabled +static inline NvU32 kbusGetNvlinkPeerId(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu) { + NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); + return 0; +} +#else //__nvoc_kern_bus_h_disabled +#define kbusGetNvlinkPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetNvlinkPeerId_c732fb(pGpu, pKernelBus, pPeerGpu) +#endif //__nvoc_kern_bus_h_disabled + +#define kbusGetNvlinkPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetNvlinkPeerId(pGpu, pKernelBus, pPeerGpu) + NvU32 kbusGetPeerIdFromTable_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx); @@ -1216,37 +1291,6 @@ static inline void kbusUnlinkP2P(OBJGPU *pGpu, struct KernelBus *pKernelBu) { #define kbusUnlinkP2P_HAL(pGpu, pKernelBu) kbusUnlinkP2P(pGpu, pKernelBu) -static inline NvBool kbusIsPcieBar1P2PMappingSupported_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { - return ((NvBool)(0 != 0)); -} - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvBool kbusIsPcieBar1P2PMappingSupported(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_491d52(pGpu0, pKernelBus0, pGpu1, pKernelBus1) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) - -static inline void kbusSetupBar1P2PCapability_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return; -} - - -#ifdef __nvoc_kern_bus_h_disabled -static inline void kbusSetupBar1P2PCapability(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); -} -#else //__nvoc_kern_bus_h_disabled -#define kbusSetupBar1P2PCapability(pGpu, pKernelBus) kbusSetupBar1P2PCapability_b3696a(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusSetupBar1P2PCapability_HAL(pGpu, pKernelBus) kbusSetupBar1P2PCapability(pGpu, pKernelBus) - NV_STATUS kbusFlushSingle_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); @@ -1427,19 +1471,19 @@ static inline NV_STATUS kbusDestroyBar1(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusDestroyBar1_HAL(pGpu, pKernelBus, gfid) kbusDestroyBar1(pGpu, pKernelBus, gfid) -NV_STATUS kbusMapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, NvHandle hClient); +NV_STATUS kbusMapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, struct Device *pDevice); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMapFbAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, NvHandle hClient) { +static inline NV_STATUS kbusMapFbAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, struct Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, hClient) kbusMapFbAperture_GM107(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, hClient) +#define kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) kbusMapFbAperture_GM107(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) #endif //__nvoc_kern_bus_h_disabled -#define kbusMapFbAperture_HAL(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, hClient) kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, hClient) +#define kbusMapFbAperture_HAL(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) NV_STATUS kbusUnmapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 aperOffset, NvU64 length, NvU32 flags); @@ -1482,13 +1526,13 @@ static inline struct OBJVASPACE *kbusGetBar1VASpace(OBJGPU *pGpu, struct KernelB #define kbusGetBar1VASpace_HAL(pGpu, pKernelBus) kbusGetBar1VASpace(pGpu, pKernelBus) -static inline NV_STATUS kbusInitInstBlk_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU32 bigPageSize, struct OBJVASPACE *pVAS) { +static inline NV_STATUS kbusInitInstBlk_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { return NV_OK; } #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitInstBlk(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU32 bigPageSize, struct OBJVASPACE *pVAS) { +static inline NV_STATUS kbusInitInstBlk(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1544,22 +1588,6 @@ static inline NV_STATUS kbusFlush(OBJGPU *pGpu, struct KernelBus *pKernelBus, Nv #define kbusFlush_HAL(pGpu, pKernelBus, flags) kbusFlush(pGpu, pKernelBus, flags) -static inline NV_STATUS kbusCreateCoherentCpuMapping_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool bFlush) { - return NV_ERR_NOT_SUPPORTED; -} - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCreateCoherentCpuMapping(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool bFlush) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusCreateCoherentCpuMapping(pGpu, pKernelBus, bFlush) kbusCreateCoherentCpuMapping_46f6a7(pGpu, pKernelBus, bFlush) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, bFlush) kbusCreateCoherentCpuMapping(pGpu, pKernelBus, bFlush) - static inline void kbusTeardownCoherentCpuMappingAcr_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { return; } @@ -1593,6 +1621,14 @@ static inline NV_STATUS kbusStateInitLocked_DISPATCH(OBJGPU *pGpu, struct Kernel return pKernelBus->__kbusStateInitLocked__(pGpu, pKernelBus); } +static inline NV_STATUS kbusStatePreLoad_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { + return NV_OK; +} + +static inline NV_STATUS kbusStatePreLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { + return pKernelBus->__kbusStatePreLoad__(pGpu, pKernelBus, arg0); +} + NV_STATUS kbusStateLoad_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); static inline NV_STATUS kbusStateLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { @@ -1663,6 +1699,16 @@ static inline NV_STATUS kbusRemoveP2PMapping_DISPATCH(OBJGPU *pGpu0, struct Kern return pKernelBus0->__kbusRemoveP2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); } +NvU32 kbusGetEgmPeerId_GH100(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu); + +static inline NvU32 kbusGetEgmPeerId_56cd7a(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu) { + return NV_OK; +} + +static inline NvU32 kbusGetEgmPeerId_DISPATCH(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu) { + return pLocalKernelBus->__kbusGetEgmPeerId__(pLocalGpu, pLocalKernelBus, pRemoteGpu); +} + NvU32 kbusGetPeerId_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); NvU32 kbusGetPeerId_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); @@ -1697,16 +1743,16 @@ static inline NV_STATUS kbusIsPeerIdValid_DISPATCH(OBJGPU *pGpu, struct KernelBu return pKernelBus->__kbusIsPeerIdValid__(pGpu, pKernelBus, peerId); } -NV_STATUS kbusGetNvlinkP2PPeerId_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer); +NV_STATUS kbusGetNvlinkP2PPeerId_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); -NV_STATUS kbusGetNvlinkP2PPeerId_GA100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer); +NV_STATUS kbusGetNvlinkP2PPeerId_GA100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); -static inline NV_STATUS kbusGetNvlinkP2PPeerId_56cd7a(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer) { +static inline NV_STATUS kbusGetNvlinkP2PPeerId_56cd7a(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes) { return NV_OK; } -static inline NV_STATUS kbusGetNvlinkP2PPeerId_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer) { - return pKernelBus0->__kbusGetNvlinkP2PPeerId__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer); +static inline NV_STATUS kbusGetNvlinkP2PPeerId_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes) { + return pKernelBus0->__kbusGetNvlinkP2PPeerId__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes); } void kbusWriteP2PWmbTag_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); @@ -1765,6 +1811,66 @@ static inline NV_STATUS kbusUnreserveP2PPeerIds_DISPATCH(OBJGPU *pGpu, struct Ke return pKernelBus->__kbusUnreserveP2PPeerIds__(pGpu, pKernelBus, peerMask); } +NvBool kbusNeedStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvBool kbusNeedStaticBar1Mapping_bf6dfa(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kbusNeedStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusNeedStaticBar1Mapping__(pGpu, pKernelBus); +} + +NV_STATUS kbusEnableStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid); + +static inline NV_STATUS kbusEnableStaticBar1Mapping_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusEnableStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid) { + return pKernelBus->__kbusEnableStaticBar1Mapping__(pGpu, pKernelBus, reservedFbSize, gfid); +} + +NV_STATUS kbusDisableStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline NV_STATUS kbusDisableStaticBar1Mapping_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return NV_OK; +} + +static inline NV_STATUS kbusDisableStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusDisableStaticBar1Mapping__(pGpu, pKernelBus, gfid); +} + +NV_STATUS kbusGetBar1P2PDmaInfo_GH100(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size); + +static inline NV_STATUS kbusGetBar1P2PDmaInfo_395e98(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusGetBar1P2PDmaInfo_DISPATCH(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size) { + return pPeerKernelBus->__kbusGetBar1P2PDmaInfo__(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size); +} + +NV_STATUS kbusStaticMapFbAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid); + +static inline NV_STATUS kbusStaticMapFbAperture_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusStaticMapFbAperture_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid) { + return pKernelBus->__kbusStaticMapFbAperture__(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid); +} + +NV_STATUS kbusStaticUnmapFbAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid); + +static inline NV_STATUS kbusStaticUnmapFbAperture_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusStaticUnmapFbAperture_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid) { + return pKernelBus->__kbusStaticUnmapFbAperture__(pGpu, pKernelBus, pMemDesc, gfid); +} + NV_STATUS kbusCreateP2PMappingForBar1P2P_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes); static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { @@ -1795,6 +1901,26 @@ static inline NvBool kbusHasPcieBar1P2PMapping_DISPATCH(OBJGPU *pGpu0, struct Ke return pKernelBus0->__kbusHasPcieBar1P2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1); } +NvBool kbusIsPcieBar1P2PMappingSupported_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1); + +static inline NvBool kbusIsPcieBar1P2PMappingSupported_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kbusIsPcieBar1P2PMappingSupported_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { + return pKernelBus0->__kbusIsPcieBar1P2PMappingSupported__(pGpu0, pKernelBus0, pGpu1, pKernelBus1); +} + +void kbusSetupBar1P2PCapability_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline void kbusSetupBar1P2PCapability_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return; +} + +static inline void kbusSetupBar1P2PCapability_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + pKernelBus->__kbusSetupBar1P2PCapability__(pGpu, pKernelBus); +} + NV_STATUS kbusCheckFlaSupportedAndInit_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); static inline NV_STATUS kbusCheckFlaSupportedAndInit_ac1694(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { @@ -2029,6 +2155,16 @@ static inline NV_STATUS kbusVerifyBar2_DISPATCH(OBJGPU *pGpu, struct KernelBus * return pKernelBus->__kbusVerifyBar2__(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size); } +static inline NV_STATUS kbusVerifyCoherentLink_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +NV_STATUS kbusVerifyCoherentLink_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusVerifyCoherentLink_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusVerifyCoherentLink__(pGpu, pKernelBus); +} + NV_STATUS kbusFlushPcieForBar0Doorbell_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); static inline NV_STATUS kbusFlushPcieForBar0Doorbell_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { @@ -2039,6 +2175,16 @@ static inline NV_STATUS kbusFlushPcieForBar0Doorbell_DISPATCH(OBJGPU *pGpu, stru return pKernelBus->__kbusFlushPcieForBar0Doorbell__(pGpu, pKernelBus); } +NV_STATUS kbusCreateCoherentCpuMapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush); + +static inline NV_STATUS kbusCreateCoherentCpuMapping_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusCreateCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush) { + return pKernelBus->__kbusCreateCoherentCpuMapping__(pGpu, pKernelBus, numaOnlineMemorySize, bFlush); +} + NvU8 *kbusMapCoherentCpuMapping_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); static inline NvU8 *kbusMapCoherentCpuMapping_9e2234(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { @@ -2069,10 +2215,6 @@ static inline void kbusTeardownCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct pKernelBus->__kbusTeardownCoherentCpuMapping__(pGpu, pKernelBus, arg0); } -static inline NV_STATUS kbusStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { - return pEngstate->__kbusStatePreLoad__(pGpu, pEngstate, arg0); -} - static inline NV_STATUS kbusStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { return pEngstate->__kbusStatePostUnload__(pGpu, pEngstate, arg0); } @@ -2165,6 +2307,10 @@ static inline NvBool kbusIsBar1P2PCapable(struct KernelBus *pKernelBus) { return pKernelBus->bBar1P2pCapable; } +static inline NvBool kbusIsBarAccessBlocked(struct KernelBus *pKernelBus) { + return pKernelBus->bBarAccessBlocked; +} + void kbusDestruct_IMPL(struct KernelBus *pKernelBus); #define __nvoc_kbusDestruct(pKernelBus) kbusDestruct_IMPL(pKernelBus) @@ -2268,15 +2414,15 @@ static inline void kbusDetermineBar1ApertureLength(struct KernelBus *pKernelBus, #define kbusDetermineBar1ApertureLength(pKernelBus, gfid) kbusDetermineBar1ApertureLength_IMPL(pKernelBus, gfid) #endif //__nvoc_kern_bus_h_disabled -NV_STATUS kbusMapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va); +NV_STATUS kbusMapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va, struct Device *pDevice); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va) { +static inline NV_STATUS kbusMapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va, struct Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va) kbusMapFbApertureByHandle_IMPL(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va) +#define kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va, pDevice) kbusMapFbApertureByHandle_IMPL(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va, pDevice) #endif //__nvoc_kern_bus_h_disabled NV_STATUS kbusUnmapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 bar1Va); @@ -2340,8 +2486,12 @@ static inline NvU8 *kbusCpuOffsetInBar2WindowGet(OBJGPU *pGpu, struct KernelBus // For SHH/GH180, BAR0 PRAMIN and CPU-visible BAR1/2 should be disabled when C2C is being used. // For P9+GV100, BAR0 PRAMIN and CPU-visible BAR1/2 should never be disabled. // -#define KBUS_BAR0_PRAMIN_DISABLED(pGpu) NV_FALSE -#define KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu) NV_FALSE +#define KBUS_BAR0_PRAMIN_DISABLED(pGpu) \ + ( pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && \ + gpuIsSelfHosted(pGpu) ) +#define KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu) \ + ( pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && \ + gpuIsSelfHosted(pGpu) ) #endif // KERN_BUS_H diff --git a/src/nvidia/generated/g_kern_disp_nvoc.c b/src/nvidia/generated/g_kern_disp_nvoc.c index db6be6f5a0..35afa01123 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.c +++ b/src/nvidia/generated/g_kern_disp_nvoc.c @@ -99,7 +99,7 @@ static NV_STATUS __nvoc_thunk_KernelDisplay_engstateStateUnload(OBJGPU *pGpu, st return kdispStateUnload(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[166]) { +static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[167]) { kdispRegisterIntrService(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_IntrService.offset), pRecords); } @@ -190,6 +190,12 @@ void __nvoc_init_dataField_KernelDisplay(KernelDisplay *pThis, RmHalspecOwner *p pThis->setProperty(pThis, PDB_PROP_KDISP_IMP_ENABLE, ((NvBool)(0 == 0))); } + // NVOC Property Hal field -- PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS, ((NvBool)(0 == 0))); + } + pThis->pStaticInfo = ((void *)0); pThis->bWarPurgeSatellitesOnCoreFree = ((NvBool)(0 != 0)); @@ -247,150 +253,140 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe pThis->__kdispRegisterIntrService__ = &kdispRegisterIntrService_IMPL; // Hal function -- kdispServiceInterrupt - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kdispServiceInterrupt__ = &kdispServiceInterrupt_d3ef2b; - } + pThis->__kdispServiceInterrupt__ = &kdispServiceInterrupt_acff5e; // Hal function -- kdispSelectClass - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ - { - pThis->__kdispSelectClass__ = &kdispSelectClass_46f6a7; - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ - { - pThis->__kdispSelectClass__ = &kdispSelectClass_v03_00_KERNEL; - } + pThis->__kdispSelectClass__ = &kdispSelectClass_46f6a7; + } + else + { + pThis->__kdispSelectClass__ = &kdispSelectClass_v03_00_KERNEL; } // Hal function -- kdispGetChannelNum - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { pThis->__kdispGetChannelNum__ = &kdispGetChannelNum_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + else { pThis->__kdispGetChannelNum__ = &kdispGetChannelNum_v03_00; } // Hal function -- kdispGetDisplayCapsBaseAndSize - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ )) { pThis->__kdispGetDisplayCapsBaseAndSize__ = &kdispGetDisplayCapsBaseAndSize_b3696a; } - else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + else { pThis->__kdispGetDisplayCapsBaseAndSize__ = &kdispGetDisplayCapsBaseAndSize_v03_00; } // Hal function -- kdispGetDisplaySfUserBaseAndSize - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { pThis->__kdispGetDisplaySfUserBaseAndSize__ = &kdispGetDisplaySfUserBaseAndSize_b3696a; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + else { pThis->__kdispGetDisplaySfUserBaseAndSize__ = &kdispGetDisplaySfUserBaseAndSize_v03_00; } // Hal function -- kdispGetDisplayChannelUserBaseAndSize - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { pThis->__kdispGetDisplayChannelUserBaseAndSize__ = &kdispGetDisplayChannelUserBaseAndSize_46f6a7; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + else { pThis->__kdispGetDisplayChannelUserBaseAndSize__ = &kdispGetDisplayChannelUserBaseAndSize_v03_00; } // Hal function -- kdispGetVgaWorkspaceBase - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_v04_00; + pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + else { - pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_491d52; + pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_v04_00; } // Hal function -- kdispReadRgLineCountAndFrameCount - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ - { - pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_v03_00_KERNEL; - } - // default - else - { - pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_46f6a7; - } + pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_v03_00_KERNEL; + } + // default + else + { + pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_46f6a7; } // Hal function -- kdispRestoreOriginalLsrMinTime - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ )) { - pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_v03_00; + pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_b3696a; } - else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + else { - pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_b3696a; + pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_v03_00; } // Hal function -- kdispComputeLsrMinTimeValue - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ { - pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_v02_07; + pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_56cd7a; } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + else { - pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_56cd7a; + pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_v02_07; } // Hal function -- kdispSetSwapBarrierLsrMinTime - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ )) { - pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_v03_00; + pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_b3696a; } - else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + else { - pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_b3696a; + pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_v03_00; } // Hal function -- kdispGetRgScanLock - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ - { - pThis->__kdispGetRgScanLock__ = &kdispGetRgScanLock_v02_01; - } - // default - else - { - pThis->__kdispGetRgScanLock__ = &kdispGetRgScanLock_92bfc3; - } + pThis->__kdispGetRgScanLock__ = &kdispGetRgScanLock_v02_01; + } + // default + else + { + pThis->__kdispGetRgScanLock__ = &kdispGetRgScanLock_92bfc3; } // Hal function -- kdispDetectSliLink - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + { + pThis->__kdispDetectSliLink__ = &kdispDetectSliLink_v04_00; + } + // default + else + { + pThis->__kdispDetectSliLink__ = &kdispDetectSliLink_92bfc3; + } + + // Hal function -- kdispInitRegistryOverrides + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ )) + { + pThis->__kdispInitRegistryOverrides__ = &kdispInitRegistryOverrides_b3696a; + } + // default + else { - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ - { - pThis->__kdispDetectSliLink__ = &kdispDetectSliLink_v04_00; - } - // default - else - { - pThis->__kdispDetectSliLink__ = &kdispDetectSliLink_92bfc3; - } + pThis->__kdispInitRegistryOverrides__ = &kdispInitRegistryOverrides_IMPL; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelDisplay_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kern_disp_nvoc.h b/src/nvidia/generated/g_kern_disp_nvoc.h index 2932236b3f..97269ed133 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.h +++ b/src/nvidia/generated/g_kern_disp_nvoc.h @@ -120,6 +120,7 @@ struct KernelDisplay { void (*__kdispSetSwapBarrierLsrMinTime__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32 *, NvU32); NV_STATUS (*__kdispGetRgScanLock__)(OBJGPU *, struct KernelDisplay *, NvU32, OBJGPU *, NvU32, NvBool *, NvU32 *, NvBool *, NvU32 *); NV_STATUS (*__kdispDetectSliLink__)(struct KernelDisplay *, OBJGPU *, OBJGPU *, NvU32, NvU32); + void (*__kdispInitRegistryOverrides__)(OBJGPU *, struct KernelDisplay *); NV_STATUS (*__kdispServiceNotificationInterrupt__)(OBJGPU *, struct KernelDisplay *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kdispStatePreLoad__)(POBJGPU, struct KernelDisplay *, NvU32); NV_STATUS (*__kdispStatePostUnload__)(POBJGPU, struct KernelDisplay *, NvU32); @@ -131,6 +132,9 @@ struct KernelDisplay { NV_STATUS (*__kdispStatePostLoad__)(POBJGPU, struct KernelDisplay *, NvU32); NvBool (*__kdispIsPresent__)(POBJGPU, struct KernelDisplay *); NvBool PDB_PROP_KDISP_IMP_ENABLE; + NvBool PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS; + NvBool PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE; + NvBool PDB_PROP_KDISP_IN_AWAKEN_INTR; struct DisplayInstanceMemory *pInst; struct KernelHead *pKernelHead[4]; const KernelDisplayStaticInfo *pStaticInfo; @@ -139,6 +143,11 @@ struct KernelDisplay { NvU32 isrVblankHeads; NvBool bExtdevIntrSupported; NvU32 numHeads; + NvU32 deferredVblankHeadMask; + NvHandle hInternalClient; + NvHandle hInternalDevice; + NvHandle hInternalSubdevice; + NvHandle hDispCommonHandle; }; #ifndef __NVOC_CLASS_KernelDisplay_TYPEDEF__ @@ -164,8 +173,14 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelDisplay; #define PDB_PROP_KDISP_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. #define PDB_PROP_KDISP_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING +#define PDB_PROP_KDISP_IN_AWAKEN_INTR_BASE_CAST +#define PDB_PROP_KDISP_IN_AWAKEN_INTR_BASE_NAME PDB_PROP_KDISP_IN_AWAKEN_INTR +#define PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS_BASE_CAST +#define PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS_BASE_NAME PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS #define PDB_PROP_KDISP_IMP_ENABLE_BASE_CAST #define PDB_PROP_KDISP_IMP_ENABLE_BASE_NAME PDB_PROP_KDISP_IMP_ENABLE +#define PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE_BASE_CAST +#define PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE_BASE_NAME PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE NV_STATUS __nvoc_objCreateDynamic_KernelDisplay(KernelDisplay**, Dynamic*, NvU32, va_list); @@ -206,6 +221,8 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay**, Dynamic*, NvU32); #define kdispGetRgScanLock_HAL(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) kdispGetRgScanLock_DISPATCH(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) #define kdispDetectSliLink(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) kdispDetectSliLink_DISPATCH(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) #define kdispDetectSliLink_HAL(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) kdispDetectSliLink_DISPATCH(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) +#define kdispInitRegistryOverrides(pGpu, pKernelDisplay) kdispInitRegistryOverrides_DISPATCH(pGpu, pKernelDisplay) +#define kdispInitRegistryOverrides_HAL(pGpu, pKernelDisplay) kdispInitRegistryOverrides_DISPATCH(pGpu, pKernelDisplay) #define kdispServiceNotificationInterrupt(pGpu, pIntrService, pParams) kdispServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kdispStatePreLoad(pGpu, pEngstate, arg0) kdispStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kdispStatePostUnload(pGpu, pEngstate, arg0) kdispStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -404,7 +421,7 @@ static inline void kdispServiceVblank(OBJGPU *pGpu, struct KernelDisplay *pKerne #define kdispServiceVblank_HAL(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispServiceVblank(pGpu, pKernelDisplay, arg0, arg1, arg2) -NvU32 kdispReadPendingVblank_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct THREAD_STATE_NODE *arg0); +NvU32 kdispReadPendingVblank_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct THREAD_STATE_NODE *arg0); #ifdef __nvoc_kern_disp_h_disabled @@ -413,7 +430,7 @@ static inline NvU32 kdispReadPendingVblank(OBJGPU *pGpu, struct KernelDisplay *p return 0; } #else //__nvoc_kern_disp_h_disabled -#define kdispReadPendingVblank(pGpu, pKernelDisplay, arg0) kdispReadPendingVblank_KERNEL(pGpu, pKernelDisplay, arg0) +#define kdispReadPendingVblank(pGpu, pKernelDisplay, arg0) kdispReadPendingVblank_IMPL(pGpu, pKernelDisplay, arg0) #endif //__nvoc_kern_disp_h_disabled #define kdispReadPendingVblank_HAL(pGpu, pKernelDisplay, arg0) kdispReadPendingVblank(pGpu, pKernelDisplay, arg0) @@ -464,6 +481,93 @@ static inline NV_STATUS kdispInitBrightcStateLoad(OBJGPU *pGpu, struct KernelDis #define kdispInitBrightcStateLoad_HAL(pGpu, pKernelDisplay) kdispInitBrightcStateLoad(pGpu, pKernelDisplay) +NV_STATUS kdispSetupAcpiEdid_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispSetupAcpiEdid(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispSetupAcpiEdid(pGpu, pKernelDisplay) kdispSetupAcpiEdid_IMPL(pGpu, pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispSetupAcpiEdid_HAL(pGpu, pKernelDisplay) kdispSetupAcpiEdid(pGpu, pKernelDisplay) + +static inline NvBool kdispReadPendingAwakenIntr_ceaee8(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *pCachedIntr, struct THREAD_STATE_NODE *arg0) { + NV_ASSERT_PRECOMP(0); + return ((NvBool)(0 != 0)); +} + +NvBool kdispReadPendingAwakenIntr_v03_00_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *pCachedIntr, struct THREAD_STATE_NODE *arg0); + +static inline NvBool kdispReadPendingAwakenIntr_491d52(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *pCachedIntr, struct THREAD_STATE_NODE *arg0) { + return ((NvBool)(0 != 0)); +} + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NvBool kdispReadPendingAwakenIntr(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *pCachedIntr, struct THREAD_STATE_NODE *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispReadPendingAwakenIntr(pGpu, pKernelDisplay, pCachedIntr, arg0) kdispReadPendingAwakenIntr_ceaee8(pGpu, pKernelDisplay, pCachedIntr, arg0) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispReadPendingAwakenIntr_HAL(pGpu, pKernelDisplay, pCachedIntr, arg0) kdispReadPendingAwakenIntr(pGpu, pKernelDisplay, pCachedIntr, arg0) + +static inline NV_STATUS kdispReadAwakenChannelNumMask_92bfc3(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *arg0, DISPCHNCLASS arg1, struct THREAD_STATE_NODE *arg2) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kdispReadAwakenChannelNumMask_v03_00_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *arg0, DISPCHNCLASS arg1, struct THREAD_STATE_NODE *arg2); + +static inline NV_STATUS kdispReadAwakenChannelNumMask_46f6a7(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *arg0, DISPCHNCLASS arg1, struct THREAD_STATE_NODE *arg2) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispReadAwakenChannelNumMask(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *arg0, DISPCHNCLASS arg1, struct THREAD_STATE_NODE *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispReadAwakenChannelNumMask(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispReadAwakenChannelNumMask_92bfc3(pGpu, pKernelDisplay, arg0, arg1, arg2) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispReadAwakenChannelNumMask_HAL(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispReadAwakenChannelNumMask(pGpu, pKernelDisplay, arg0, arg1, arg2) + +NV_STATUS kdispAllocateCommonHandle_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispAllocateCommonHandle(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispAllocateCommonHandle(pGpu, pKernelDisplay) kdispAllocateCommonHandle_IMPL(pGpu, pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispAllocateCommonHandle_HAL(pGpu, pKernelDisplay) kdispAllocateCommonHandle(pGpu, pKernelDisplay) + +void kdispDestroyCommonHandle_IMPL(struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline void kdispDestroyCommonHandle(struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); +} +#else //__nvoc_kern_disp_h_disabled +#define kdispDestroyCommonHandle(pKernelDisplay) kdispDestroyCommonHandle_IMPL(pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispDestroyCommonHandle_HAL(pKernelDisplay) kdispDestroyCommonHandle(pKernelDisplay) + NV_STATUS kdispConstructEngine_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, ENGDESCRIPTOR engDesc); static inline NV_STATUS kdispConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, ENGDESCRIPTOR engDesc) { @@ -500,14 +604,14 @@ static inline NV_STATUS kdispStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelDis return pKernelDisplay->__kdispStateUnload__(pGpu, pKernelDisplay, flags); } -void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[166]); +void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[167]); -static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[166]) { +static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[167]) { pKernelDisplay->__kdispRegisterIntrService__(pGpu, pKernelDisplay, pRecords); } -static inline NvU32 kdispServiceInterrupt_d3ef2b(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceServiceInterruptArguments *pParams) { - kdispServiceVblank(pGpu, pKernelDisplay, 0, ((2) | (16)), ((void *)0)); +static inline NvU32 kdispServiceInterrupt_acff5e(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceServiceInterruptArguments *pParams) { + kdispServiceVblank(pGpu, pKernelDisplay, 0, (4), ((void *)0)); return NV_OK; } @@ -639,6 +743,16 @@ static inline NV_STATUS kdispDetectSliLink_DISPATCH(struct KernelDisplay *pKerne return pKernelDisplay->__kdispDetectSliLink__(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort); } +static inline void kdispInitRegistryOverrides_b3696a(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + return; +} + +void kdispInitRegistryOverrides_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + +static inline void kdispInitRegistryOverrides_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + pKernelDisplay->__kdispInitRegistryOverrides__(pGpu, pKernelDisplay); +} + static inline NV_STATUS kdispServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { return pIntrService->__kdispServiceNotificationInterrupt__(pGpu, pIntrService, pParams); } @@ -737,7 +851,7 @@ static inline void kdispSetWarPurgeSatellitesOnCoreFree(struct KernelDisplay *pK #undef PRIVATE_FIELD -void +void dispdeviceFillVgaSavedDisplayState( OBJGPU *pGpu, NvU64 vgaAddr, NvU8 vgaMemType, @@ -764,19 +878,44 @@ kdispGetHead return pKernelDisplay->pKernelHead[head]; } -static NV_INLINE NvU32 +static NV_INLINE NvU32 kdispGetNumHeads(struct KernelDisplay *pKernelDisplay) { NV_ASSERT(pKernelDisplay != NULL); return pKernelDisplay->numHeads; } -static NV_INLINE NvU32 +static NV_INLINE NvU32 kdispGetIsPrimaryVga(struct KernelDisplay *pKernelDisplay) { NV_ASSERT(pKernelDisplay->pStaticInfo != NULL); return pKernelDisplay->pStaticInfo->bPrimaryVga; } + +static NV_INLINE NvU32 +kdispGetDeferredVblankHeadMask(struct KernelDisplay *pKernelDisplay) +{ + return pKernelDisplay->deferredVblankHeadMask; +} + +static NV_INLINE void +kdispSetDeferredVblankHeadMask(struct KernelDisplay *pKernelDisplay, NvU32 vblankHeadMask) +{ + pKernelDisplay->deferredVblankHeadMask = vblankHeadMask; +} + +static NV_INLINE NvHandle +kdispGetInternalClientHandle(struct KernelDisplay *pKernelDisplay) +{ + return pKernelDisplay->hInternalClient; +} + +static NV_INLINE NvHandle +kdispGetDispCommonHandle(struct KernelDisplay *pKernelDisplay) +{ + return pKernelDisplay->hDispCommonHandle; +} + #endif // KERN_DISP_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.c b/src/nvidia/generated/g_kern_fsp_nvoc.c index 07da73a8c2..e53bfc2942 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.c +++ b/src/nvidia/generated/g_kern_fsp_nvoc.c @@ -210,7 +210,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_ac1694; } @@ -220,7 +220,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspWaitForSecureBoot__ = &kfspWaitForSecureBoot_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspWaitForSecureBoot__ = &kfspWaitForSecureBoot_395e98; } @@ -230,7 +230,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspGetRmChannelSize__ = &kfspGetRmChannelSize_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspGetRmChannelSize__ = &kfspGetRmChannelSize_b2b553; } @@ -240,7 +240,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspConfigEmemc__ = &kfspConfigEmemc_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspConfigEmemc__ = &kfspConfigEmemc_395e98; } @@ -250,7 +250,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspUpdateQueueHeadTail__ = &kfspUpdateQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspUpdateQueueHeadTail__ = &kfspUpdateQueueHeadTail_d44104; } @@ -260,7 +260,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspGetQueueHeadTail__ = &kfspGetQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspGetQueueHeadTail__ = &kfspGetQueueHeadTail_d44104; } @@ -270,7 +270,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspUpdateMsgQueueHeadTail__ = &kfspUpdateMsgQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspUpdateMsgQueueHeadTail__ = &kfspUpdateMsgQueueHeadTail_d44104; } @@ -280,7 +280,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspGetMsgQueueHeadTail__ = &kfspGetMsgQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspGetMsgQueueHeadTail__ = &kfspGetMsgQueueHeadTail_d44104; } @@ -290,7 +290,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspNvdmToSeid__ = &kfspNvdmToSeid_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspNvdmToSeid__ = &kfspNvdmToSeid_b2b553; } @@ -300,7 +300,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspCreateMctpHeader__ = &kfspCreateMctpHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspCreateMctpHeader__ = &kfspCreateMctpHeader_b2b553; } @@ -310,7 +310,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspCreateNvdmHeader__ = &kfspCreateNvdmHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspCreateNvdmHeader__ = &kfspCreateNvdmHeader_b2b553; } @@ -320,7 +320,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspWriteToEmem__ = &kfspWriteToEmem_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspWriteToEmem__ = &kfspWriteToEmem_395e98; } @@ -330,7 +330,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspReadFromEmem__ = &kfspReadFromEmem_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspReadFromEmem__ = &kfspReadFromEmem_395e98; } @@ -340,7 +340,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspGetPacketInfo__ = &kfspGetPacketInfo_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspGetPacketInfo__ = &kfspGetPacketInfo_395e98; } @@ -350,7 +350,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspValidateMctpPayloadHeader__ = &kfspValidateMctpPayloadHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspValidateMctpPayloadHeader__ = &kfspValidateMctpPayloadHeader_395e98; } @@ -360,7 +360,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspProcessNvdmMessage__ = &kfspProcessNvdmMessage_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspProcessNvdmMessage__ = &kfspProcessNvdmMessage_395e98; } @@ -370,7 +370,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspProcessCommandResponse__ = &kfspProcessCommandResponse_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspProcessCommandResponse__ = &kfspProcessCommandResponse_395e98; } @@ -380,7 +380,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspDumpDebugState__ = &kfspDumpDebugState_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspDumpDebugState__ = &kfspDumpDebugState_d44104; } @@ -390,7 +390,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspErrorCode2NvStatusMap__ = &kfspErrorCode2NvStatusMap_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspErrorCode2NvStatusMap__ = &kfspErrorCode2NvStatusMap_395e98; } @@ -422,11 +422,22 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * { pThis->__kfspWaitForGspTargetMaskReleased__ = &kfspWaitForGspTargetMaskReleased_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kfspWaitForGspTargetMaskReleased__ = &kfspWaitForGspTargetMaskReleased_395e98; } + // Hal function -- kfspRequiresBug3957833WAR + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspRequiresBug3957833WAR__ = &kfspRequiresBug3957833WAR_GH100; + } + // default + else + { + pThis->__kfspRequiresBug3957833WAR__ = &kfspRequiresBug3957833WAR_491d52; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelFsp_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelFsp_engstateStateDestroy; diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.h b/src/nvidia/generated/g_kern_fsp_nvoc.h index be7c0ae431..3d7d371bf0 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.h +++ b/src/nvidia/generated/g_kern_fsp_nvoc.h @@ -40,12 +40,6 @@ extern "C" { #include "kernel/gpu/intr/intr_service.h" #include "fsp/nvdm_payload_cmd_response.h" -#if RMCFG_MODULE_ENABLED (FSP) -#include "gpu/falcon/falcon.h" -#include "gpu/falcon/falcon_queue.h" -#include "objflcnable.h" -#endif - // // VBIOS ucode descriptor v4 format. Used for the CPU command to FSP to boot // GSP FMC. @@ -167,6 +161,7 @@ struct KernelFsp { NvU64 (*__kfspGetExtraReservedMemorySize__)(struct OBJGPU *, struct KernelFsp *); NvBool (*__kfspCheckGspSecureScratch__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspWaitForGspTargetMaskReleased__)(struct OBJGPU *, struct KernelFsp *); + NvBool (*__kfspRequiresBug3957833WAR__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspStateLoad__)(POBJGPU, struct KernelFsp *, NvU32); NV_STATUS (*__kfspStateUnload__)(POBJGPU, struct KernelFsp *, NvU32); NV_STATUS (*__kfspStateInitLocked__)(POBJGPU, struct KernelFsp *); @@ -287,6 +282,8 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp**, Dynamic*, NvU32); #define kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) #define kfspWaitForGspTargetMaskReleased(pGpu, pKernelFsp) kfspWaitForGspTargetMaskReleased_DISPATCH(pGpu, pKernelFsp) #define kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp) kfspWaitForGspTargetMaskReleased_DISPATCH(pGpu, pKernelFsp) +#define kfspRequiresBug3957833WAR(pGpu, pKernelFsp) kfspRequiresBug3957833WAR_DISPATCH(pGpu, pKernelFsp) +#define kfspRequiresBug3957833WAR_HAL(pGpu, pKernelFsp) kfspRequiresBug3957833WAR_DISPATCH(pGpu, pKernelFsp) #define kfspStateLoad(pGpu, pEngstate, arg0) kfspStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kfspStateUnload(pGpu, pEngstate, arg0) kfspStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kfspStateInitLocked(pGpu, pEngstate) kfspStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -583,6 +580,16 @@ static inline NV_STATUS kfspWaitForGspTargetMaskReleased_DISPATCH(struct OBJGPU return pKernelFsp->__kfspWaitForGspTargetMaskReleased__(pGpu, pKernelFsp); } +NvBool kfspRequiresBug3957833WAR_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NvBool kfspRequiresBug3957833WAR_491d52(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kfspRequiresBug3957833WAR_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspRequiresBug3957833WAR__(pGpu, pKernelFsp); +} + static inline NV_STATUS kfspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return pEngstate->__kfspStateLoad__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.c b/src/nvidia/generated/g_kern_gmmu_nvoc.c index 73d7016db6..6e905e2bb2 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.c +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.c @@ -95,7 +95,7 @@ static void __nvoc_thunk_KernelGmmu_engstateStateDestroy(OBJGPU *pGpu, struct OB kgmmuStateDestroy(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[166]) { +static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[167]) { kgmmuRegisterIntrService(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), arg0); } @@ -257,16 +257,10 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuStateInitLocked__ = &kgmmuStateInitLocked_IMPL; // Hal function -- kgmmuStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgmmuStatePostLoad__ = &kgmmuStatePostLoad_IMPL; - } + pThis->__kgmmuStatePostLoad__ = &kgmmuStatePostLoad_IMPL; // Hal function -- kgmmuStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgmmuStatePreUnload__ = &kgmmuStatePreUnload_IMPL; - } + pThis->__kgmmuStatePreUnload__ = &kgmmuStatePreUnload_IMPL; pThis->__kgmmuStateDestroy__ = &kgmmuStateDestroy_IMPL; @@ -279,7 +273,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuInstBlkVaLimitGet__ = &kgmmuInstBlkVaLimitGet_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kgmmuInstBlkVaLimitGet__ = &kgmmuInstBlkVaLimitGet_f03539; } @@ -289,103 +283,103 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuSetTlbInvalidateMembarWarParameters__ = &kgmmuSetTlbInvalidateMembarWarParameters_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kgmmuSetTlbInvalidateMembarWarParameters__ = &kgmmuSetTlbInvalidateMembarWarParameters_4a4dee; } // Hal function -- kgmmuSetTlbInvalidationScope - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_GA100; + pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_46f6a7; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_46f6a7; + pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_GA100; } // Hal function -- kgmmuFmtInitPteComptagLine - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_TU10X; + pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_b3696a; + pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_TU10X; } // Hal function -- kgmmuFmtInitPeerPteFld - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_TU10X; + pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_b3696a; + pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_TU10X; } // Hal function -- kgmmuFmtInitPte - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GP10X; + pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GH10X; + pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GP10X; } // Hal function -- kgmmuFmtInitPde - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GP10X; + pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GH10X; + pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GP10X; } // Hal function -- kgmmuFmtIsVersionSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GP10X; + pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GH10X; + pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GP10X; } // Hal function -- kgmmuFmtInitLevels - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GP10X; + pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GA10X; + pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GP10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GH10X; + pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GA10X; } // Hal function -- kgmmuFmtInitPdeMulti - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GP10X; + pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GH10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GH10X; + pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GP10X; } // Hal function -- kgmmuFmtFamiliesInit - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_TU102; + pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_GH100; + pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_TU102; } // Hal function -- kgmmuTranslatePtePcfFromSw @@ -393,7 +387,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuTranslatePtePcfFromSw__ = &kgmmuTranslatePtePcfFromSw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuTranslatePtePcfFromSw__ = &kgmmuTranslatePtePcfFromSw_56cd7a; } @@ -403,7 +397,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuTranslatePtePcfFromHw__ = &kgmmuTranslatePtePcfFromHw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuTranslatePtePcfFromHw__ = &kgmmuTranslatePtePcfFromHw_56cd7a; } @@ -413,7 +407,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuTranslatePdePcfFromSw__ = &kgmmuTranslatePdePcfFromSw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuTranslatePdePcfFromSw__ = &kgmmuTranslatePdePcfFromSw_56cd7a; } @@ -423,19 +417,19 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_56cd7a; } // Hal function -- kgmmuGetFaultRegisterMappings - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuGetFaultRegisterMappings__ = &kgmmuGetFaultRegisterMappings_TU102; + pThis->__kgmmuGetFaultRegisterMappings__ = &kgmmuGetFaultRegisterMappings_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgmmuGetFaultRegisterMappings__ = &kgmmuGetFaultRegisterMappings_GH100; + pThis->__kgmmuGetFaultRegisterMappings__ = &kgmmuGetFaultRegisterMappings_TU102; } // Hal function -- kgmmuIssueReplayableFaultBufferFlush @@ -443,7 +437,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuIssueReplayableFaultBufferFlush__ = &kgmmuIssueReplayableFaultBufferFlush_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuIssueReplayableFaultBufferFlush__ = &kgmmuIssueReplayableFaultBufferFlush_46f6a7; } @@ -453,7 +447,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuFaultBufferAllocSharedMemory__ = &kgmmuFaultBufferAllocSharedMemory_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuFaultBufferAllocSharedMemory__ = &kgmmuFaultBufferAllocSharedMemory_56cd7a; } @@ -463,7 +457,7 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuFaultBufferFreeSharedMemory__ = &kgmmuFaultBufferFreeSharedMemory_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kgmmuFaultBufferFreeSharedMemory__ = &kgmmuFaultBufferFreeSharedMemory_b3696a; } @@ -473,19 +467,30 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuSetupWarForBug2720120__ = &kgmmuSetupWarForBug2720120_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kgmmuSetupWarForBug2720120__ = &kgmmuSetupWarForBug2720120_56cd7a; } // Hal function -- kgmmuGetGraphicsEngineId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GH100; + } + else { pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kgmmuReadShadowBufPutIndex + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GH100; + pThis->__kgmmuReadShadowBufPutIndex__ = &kgmmuReadShadowBufPutIndex_GH100; + } + // default + else + { + pThis->__kgmmuReadShadowBufPutIndex__ = &kgmmuReadShadowBufPutIndex_4a4dee; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGmmu_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.h b/src/nvidia/generated/g_kern_gmmu_nvoc.h index 673a4923a9..ee90338254 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.h +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -205,6 +205,12 @@ typedef struct NvU32 numBufferPages; + /*! + * Start index of the page containing the fault buffer metadata. + * 0 if no metadata is present. + */ + NvU32 metadataStartIndex; + /*! * Used only by the replayable fault buffer. Memory descriptor used to * describe shared memory b/w CPU-RM and GSP-RM. @@ -214,6 +220,9 @@ typedef struct NvP64 pFaultBufferSharedMemoryAddress; NvP64 pFaultBufferSharedMemoryPriv; + + NvP64 pFaultBufferMetadataAddress; + } GMMU_CLIENT_SHADOW_FAULT_BUFFER; /*! @@ -253,6 +262,9 @@ struct GMMU_FAULT_BUFFER * Flag stating fatalfault interrupt pending */ NvS32 fatalFaultIntrPending; + + /*! Generational counter for fault buffer. Incremented when the fault buffer wraps around. */ + volatile NvU64 faultBufferGenerationCounter; }; typedef struct GMMU_FAULT_PACKET @@ -264,6 +276,18 @@ typedef struct GMMU_FAULT_PACKET // Initialize Circular Queue for MMU Shadow fault buffer MAKE_QUEUE_CIRCULAR(GMMU_SHADOW_FAULT_BUF, GMMU_FAULT_PACKET); +#define GMMU_FAULT_PACKET_METADATA_SIZE 32 +#define GMMU_FAULT_PACKET_METADATA_AUTHTAG_IDX 0 +#define GMMU_FAULT_PACKET_METADATA_AUTHTAG_SIZE 16 +#define GMMU_FAULT_PACKET_METADATA_VALID_IDX 16 +#define GMMU_FAULT_PACKET_METADATA_VALID_SIZE 1 +#define GMMU_FAULT_PACKET_METADATA_VALID_YES NV_TRUE +#define GMMU_FAULT_PACKET_METADATA_VALID_NO NV_FALSE + +typedef struct GMMU_FAULT_PACKET_METADATA +{ + NvU8 metadata[GMMU_FAULT_PACKET_METADATA_SIZE]; +} GMMU_FAULT_PACKET_METADATA; /*! * Structure that holds different parameters passed by an engine to kgmmuInstBlkInit @@ -331,6 +355,7 @@ struct KernelGmmu { void (*__kgmmuFaultBufferFreeSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); + NvU32 (*__kgmmuReadShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); @@ -345,7 +370,7 @@ struct KernelGmmu { NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; - NvU32 defaultBigPageSize; + NvU64 defaultBigPageSize; NvU32 uvmSharedIntrRmOwnsMask; GMMU_FMT_FAMILY *PRIVATE_FIELD(pFmtFamilies)[3]; NvU32 PRIVATE_FIELD(PDEAperture); @@ -356,7 +381,7 @@ struct KernelGmmu { NvU32 PRIVATE_FIELD(PTEAttr); NvU32 PRIVATE_FIELD(PTEBAR1Aperture); NvU32 PRIVATE_FIELD(PTEBAR1Attr); - NvU32 PRIVATE_FIELD(overrideBigPageSize); + NvU64 PRIVATE_FIELD(overrideBigPageSize); NvBool PRIVATE_FIELD(bEnablePerVaspaceBigPage); NvBool PRIVATE_FIELD(bIgnoreHubTlbInvalidate); NvU64 PRIVATE_FIELD(maxVASize); @@ -407,6 +432,7 @@ struct KernelGmmu_PRIVATE { void (*__kgmmuFaultBufferFreeSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); + NvU32 (*__kgmmuReadShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); @@ -421,7 +447,7 @@ struct KernelGmmu_PRIVATE { NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; - NvU32 defaultBigPageSize; + NvU64 defaultBigPageSize; NvU32 uvmSharedIntrRmOwnsMask; GMMU_FMT_FAMILY *pFmtFamilies[3]; NvU32 PDEAperture; @@ -432,7 +458,7 @@ struct KernelGmmu_PRIVATE { NvU32 PTEAttr; NvU32 PTEBAR1Aperture; NvU32 PTEBAR1Attr; - NvU32 overrideBigPageSize; + NvU64 overrideBigPageSize; NvBool bEnablePerVaspaceBigPage; NvBool bIgnoreHubTlbInvalidate; NvU64 maxVASize; @@ -533,6 +559,8 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuSetupWarForBug2720120_HAL(pKernelGmmu, pFam) kgmmuSetupWarForBug2720120_DISPATCH(pKernelGmmu, pFam) #define kgmmuGetGraphicsEngineId(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) #define kgmmuGetGraphicsEngineId_HAL(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) +#define kgmmuReadShadowBufPutIndex(pGpu, pKernelGmmu, type) kgmmuReadShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, type) +#define kgmmuReadShadowBufPutIndex_HAL(pGpu, pKernelGmmu, type) kgmmuReadShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, type) #define kgmmuStateLoad(pGpu, pEngstate, arg0) kgmmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStateUnload(pGpu, pEngstate, arg0) kgmmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuServiceNotificationInterrupt(pGpu, pIntrService, pParams) kgmmuServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -544,11 +572,11 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuStatePreInitUnlocked(pGpu, pEngstate) kgmmuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgmmuClearInterrupt(pGpu, pIntrService, pParams) kgmmuClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kgmmuIsPresent(pGpu, pEngstate) kgmmuIsPresent_DISPATCH(pGpu, pEngstate) -NvU32 kgmmuGetMaxBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); +NvU64 kgmmuGetMaxBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NvU32 kgmmuGetMaxBigPageSize(struct KernelGmmu *pKernelGmmu) { +static inline NvU64 kgmmuGetMaxBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return 0; } @@ -588,6 +616,22 @@ static inline NV_STATUS kgmmuInstBlkAtsGet(struct KernelGmmu *pKernelGmmu, struc #define kgmmuInstBlkAtsGet_HAL(pKernelGmmu, pVAS, subctxid, pOffset, pData) kgmmuInstBlkAtsGet(pKernelGmmu, pVAS, subctxid, pOffset, pData) +static inline NV_STATUS kgmmuInstBlkMagicValueGet_46f6a7(struct KernelGmmu *pKernelGmmu, NvU32 *pOffset, NvU32 *pData) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuInstBlkMagicValueGet(struct KernelGmmu *pKernelGmmu, NvU32 *pOffset, NvU32 *pData) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuInstBlkMagicValueGet(pKernelGmmu, pOffset, pData) kgmmuInstBlkMagicValueGet_46f6a7(pKernelGmmu, pOffset, pData) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuInstBlkMagicValueGet_HAL(pKernelGmmu, pOffset, pData) kgmmuInstBlkMagicValueGet(pKernelGmmu, pOffset, pData) + NV_STATUS kgmmuInstBlkPageDirBaseGet_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct OBJVASPACE *pVAS, INST_BLK_INIT_PARAMS *pParams, NvU32 subctxid, NvU32 *pOffsetLo, NvU32 *pDataLo, NvU32 *pOffsetHi, NvU32 *pDataHi); @@ -616,11 +660,11 @@ static inline NvU32 kgmmuGetPDBAllocSize(struct KernelGmmu *pKernelGmmu, const M #define kgmmuGetPDBAllocSize_HAL(pKernelGmmu, arg0, arg1) kgmmuGetPDBAllocSize(pKernelGmmu, arg0, arg1) -NvU32 kgmmuGetBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); +NvU64 kgmmuGetBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NvU32 kgmmuGetBigPageSize(struct KernelGmmu *pKernelGmmu) { +static inline NvU64 kgmmuGetBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return 0; } @@ -999,6 +1043,19 @@ static inline void kgmmuClearNonReplayableFaultIntr(OBJGPU *pGpu, struct KernelG #define kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, arg0) kgmmuClearNonReplayableFaultIntr(pGpu, pKernelGmmu, arg0) +void kgmmuClearReplayableFaultIntr_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline void kgmmuClearReplayableFaultIntr(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuClearReplayableFaultIntr(pGpu, pKernelGmmu, arg0) kgmmuClearReplayableFaultIntr_TU102(pGpu, pKernelGmmu, arg0) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuClearReplayableFaultIntr_HAL(pGpu, pKernelGmmu, arg0) kgmmuClearReplayableFaultIntr(pGpu, pKernelGmmu, arg0) + NV_STATUS kgmmuConstructEngine_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, ENGDESCRIPTOR arg0); static inline NV_STATUS kgmmuConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, ENGDESCRIPTOR arg0) { @@ -1029,9 +1086,9 @@ static inline void kgmmuStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *p pKernelGmmu->__kgmmuStateDestroy__(pGpu, pKernelGmmu); } -void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[166]); +void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[167]); -static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[166]) { +static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[167]) { pKernelGmmu->__kgmmuRegisterIntrService__(pGpu, pKernelGmmu, arg0); } @@ -1238,6 +1295,16 @@ static inline NvU32 kgmmuGetGraphicsEngineId_DISPATCH(struct KernelGmmu *pKernel return pKernelGmmu->__kgmmuGetGraphicsEngineId__(pKernelGmmu); } +NvU32 kgmmuReadShadowBufPutIndex_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE type); + +static inline NvU32 kgmmuReadShadowBufPutIndex_4a4dee(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE type) { + return 0; +} + +static inline NvU32 kgmmuReadShadowBufPutIndex_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE type) { + return pKernelGmmu->__kgmmuReadShadowBufPutIndex__(pGpu, pKernelGmmu, type); +} + static inline NV_STATUS kgmmuStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { return pEngstate->__kgmmuStateLoad__(pGpu, pEngstate, arg0); } @@ -1322,12 +1389,12 @@ static inline NvU32 kgmmuGetPTEAttr(struct KernelGmmu *pKernelGmmu) { return pKernelGmmu_PRIVATE->PTEAttr; } -static inline NvU32 kgmmuGetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu) { +static inline NvU64 kgmmuGetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu) { struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; return pKernelGmmu_PRIVATE->overrideBigPageSize; } -static inline void kgmmuSetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu, NvU32 bigPageSize) { +static inline void kgmmuSetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu, NvU64 bigPageSize) { struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; pKernelGmmu_PRIVATE->overrideBigPageSize = bigPageSize; } @@ -1474,10 +1541,10 @@ static inline const struct GMMU_FMT *kgmmuFmtGetLatestSupportedFormat(OBJGPU *pG #define kgmmuFmtGetLatestSupportedFormat(pGpu, pKernelGmmu) kgmmuFmtGetLatestSupportedFormat_IMPL(pGpu, pKernelGmmu) #endif //__nvoc_kern_gmmu_h_disabled -NvU32 kgmmuGetMinBigPageSize_IMPL(struct KernelGmmu *pKernelGmmu); +NvU64 kgmmuGetMinBigPageSize_IMPL(struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NvU32 kgmmuGetMinBigPageSize(struct KernelGmmu *pKernelGmmu) { +static inline NvU64 kgmmuGetMinBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return 0; } @@ -1714,6 +1781,17 @@ static inline struct HW_FAULT_BUFFER *kgmmuGetHwFaultBufferPtr(struct KernelGmmu #define kgmmuGetHwFaultBufferPtr(pKernelGmmu, gfid, faultBufferIndex) kgmmuGetHwFaultBufferPtr_IMPL(pKernelGmmu, gfid, faultBufferIndex) #endif //__nvoc_kern_gmmu_h_disabled +NvU64 kgmmuGetFaultBufferGenCnt_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU8 gfid); + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NvU64 kgmmuGetFaultBufferGenCnt(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU8 gfid) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return 0; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuGetFaultBufferGenCnt(pGpu, pKernelGmmu, gfid) kgmmuGetFaultBufferGenCnt_IMPL(pGpu, pKernelGmmu, gfid) +#endif //__nvoc_kern_gmmu_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.c b/src/nvidia/generated/g_kern_mem_sys_nvoc.c index 5b41d8af15..54d7ca88dc 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.c +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.c @@ -78,6 +78,10 @@ static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStatePreLoad(OBJGPU *pG return kmemsysStatePreLoad(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); } +static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem, NvU32 flags) { + return kmemsysStatePostLoad(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); +} + static void __nvoc_thunk_KernelMemorySystem_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem) { kmemsysStateDestroy(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } @@ -114,10 +118,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStatePreInitUnlocked(POBJGPU pG return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStatePostLoad(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), arg0); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kmemsysIsPresent(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } @@ -215,16 +215,18 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysStatePreLoad__ = &kmemsysStatePreLoad_IMPL; + pThis->__kmemsysStatePostLoad__ = &kmemsysStatePostLoad_IMPL; + pThis->__kmemsysStateDestroy__ = &kmemsysStateDestroy_IMPL; // Hal function -- kmemsysGetFbNumaInfo - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_GV100; + pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_56cd7a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_56cd7a; + pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_GV100; } // Hal function -- kmemsysReadUsableFbSize @@ -232,155 +234,183 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis { pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GP102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GA102; } // Hal function -- kmemsysCacheOp - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GM200; + pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GH100; + pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GM200; } // Hal function -- kmemsysDoCacheOp - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GM107; + pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GH100; + pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GM107; } // Hal function -- kmemsysReadL2SysmemInvalidateReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_TU102; + pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_68b109; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_68b109; + pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_TU102; } // Hal function -- kmemsysWriteL2SysmemInvalidateReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_TU102; + pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_f2d351; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_f2d351; + pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_TU102; } // Hal function -- kmemsysReadL2PeermemInvalidateReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_TU102; + pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_68b109; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_68b109; + pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_TU102; } // Hal function -- kmemsysWriteL2PeermemInvalidateReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_TU102; + pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_f2d351; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_f2d351; + pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_TU102; } // Hal function -- kmemsysInitFlushSysmemBuffer - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GA100; - } + pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GM107; + } + else + { + pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GA100; } // Hal function -- kmemsysProgramSysmemFlushBuffer - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GH100; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GM107; + } + else + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GA100; } // Hal function -- kmemsysIsPagePLCable - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA102; - } - // default - else - { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_510167; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA102; + } + // default + else + { + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_510167; } // Hal function -- kmemsysReadMIGMemoryCfg - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_GA100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_GA100; - } - // default - else - { - pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_46f6a7; - } + pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_46f6a7; } // Hal function -- kmemsysInitMIGMemoryPartitionTable - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_GA100; - } - // default - else - { - pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_56cd7a; - } + pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_GA100; + } + // default + else + { + pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_56cd7a; } // Hal function -- kmemsysSwizzIdToVmmuSegmentsRange - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GH100; + } + else { pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kmemsysNumaAddMemory + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GH100; + pThis->__kmemsysNumaAddMemory__ = &kmemsysNumaAddMemory_GH100; + } + // default + else + { + pThis->__kmemsysNumaAddMemory__ = &kmemsysNumaAddMemory_56cd7a; + } + + // Hal function -- kmemsysNumaRemoveMemory + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysNumaRemoveMemory__ = &kmemsysNumaRemoveMemory_GH100; + } + // default + else + { + pThis->__kmemsysNumaRemoveMemory__ = &kmemsysNumaRemoveMemory_b3696a; + } + + // Hal function -- kmemsysNumaRemoveAllMemory + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysNumaRemoveAllMemory__ = &kmemsysNumaRemoveAllMemory_GH100; + } + // default + else + { + pThis->__kmemsysNumaRemoveAllMemory__ = &kmemsysNumaRemoveAllMemory_b3696a; + } + + // Hal function -- kmemsysSetupAllAtsPeers + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysSetupAllAtsPeers__ = &kmemsysSetupAllAtsPeers_46f6a7; + } + else + { + pThis->__kmemsysSetupAllAtsPeers__ = &kmemsysSetupAllAtsPeers_GV100; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMemorySystem_engstateConstructEngine; @@ -389,6 +419,8 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreLoad__ = &__nvoc_thunk_KernelMemorySystem_engstateStatePreLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelMemorySystem_engstateStatePostLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelMemorySystem_engstateStateDestroy; pThis->__kmemsysStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStateLoad; @@ -407,8 +439,6 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePreInitUnlocked; - pThis->__kmemsysStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePostLoad; - pThis->__kmemsysIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kmemsysIsPresent; } diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.h b/src/nvidia/generated/g_kern_mem_sys_nvoc.h index 60607fd59e..ff9ca88f0b 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.h +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.h @@ -28,7 +28,7 @@ extern "C" { * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - + #include "g_kern_mem_sys_nvoc.h" #ifndef KERN_MEM_SYS_H @@ -157,7 +157,7 @@ typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS MEMORY_SYSTEM_STATI #define FB_HWRESID_CTAGID_NUM_FERMI(i) \ (((i) & DRF_MASK(FB_HWRESID_CTAGID_FERMI)) << DRF_SHIFT(FB_HWRESID_CTAGID_FERMI)) -#define FB_SET_HWRESID_CTAGID_FERMI(h, i) \ +#define FB_SET_HWRESID_CTAGID_FERMI(h, i) \ h = ( ((h) & ~(DRF_MASK(FB_HWRESID_CTAGID_FERMI) << DRF_SHIFT(FB_HWRESID_CTAGID_FERMI))) | \ FB_HWRESID_CTAGID_NUM_FERMI(i) ) @@ -200,6 +200,7 @@ struct KernelMemorySystem { NV_STATUS (*__kmemsysConstructEngine__)(OBJGPU *, struct KernelMemorySystem *, ENGDESCRIPTOR); NV_STATUS (*__kmemsysStateInitLocked__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreLoad__)(OBJGPU *, struct KernelMemorySystem *, NvU32); + NV_STATUS (*__kmemsysStatePostLoad__)(OBJGPU *, struct KernelMemorySystem *, NvU32); void (*__kmemsysStateDestroy__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysGetFbNumaInfo__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *, NvS32 *); NV_STATUS (*__kmemsysReadUsableFbSize__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *); @@ -215,6 +216,10 @@ struct KernelMemorySystem { NV_STATUS (*__kmemsysReadMIGMemoryCfg__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysInitMIGMemoryPartitionTable__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysSwizzIdToVmmuSegmentsRange__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32, NvU32); + NV_STATUS (*__kmemsysNumaAddMemory__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU64, NvU64, NvS32 *); + void (*__kmemsysNumaRemoveMemory__)(OBJGPU *, struct KernelMemorySystem *, NvU32); + void (*__kmemsysNumaRemoveAllMemory__)(OBJGPU *, struct KernelMemorySystem *); + NV_STATUS (*__kmemsysSetupAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStateLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStateUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStatePostUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); @@ -223,7 +228,6 @@ struct KernelMemorySystem { void (*__kmemsysInitMissing__)(POBJGPU, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreInitLocked__)(POBJGPU, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreInitUnlocked__)(POBJGPU, struct KernelMemorySystem *); - NV_STATUS (*__kmemsysStatePostLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); NvBool (*__kmemsysIsPresent__)(POBJGPU, struct KernelMemorySystem *); NvBool bDisableTiledCachingInvalidatesWithEccBug1521641; NvBool bGpuCacheEnable; @@ -277,6 +281,7 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysConstructEngine(pGpu, pKernelMemorySystem, arg0) kmemsysConstructEngine_DISPATCH(pGpu, pKernelMemorySystem, arg0) #define kmemsysStateInitLocked(pGpu, pKernelMemorySystem) kmemsysStateInitLocked_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysStatePreLoad(pGpu, pKernelMemorySystem, flags) kmemsysStatePreLoad_DISPATCH(pGpu, pKernelMemorySystem, flags) +#define kmemsysStatePostLoad(pGpu, pKernelMemorySystem, flags) kmemsysStatePostLoad_DISPATCH(pGpu, pKernelMemorySystem, flags) #define kmemsysStateDestroy(pGpu, pKernelMemorySystem) kmemsysStateDestroy_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysGetFbNumaInfo(pGpu, pKernelMemorySystem, physAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, numaNodeId) #define kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, physAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, numaNodeId) @@ -306,6 +311,14 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysInitMIGMemoryPartitionTable_HAL(pGpu, pKernelMemorySystem) kmemsysInitMIGMemoryPartitionTable_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysSwizzIdToVmmuSegmentsRange(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) #define kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) +#define kmemsysNumaAddMemory(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId) kmemsysNumaAddMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId) +#define kmemsysNumaAddMemory_HAL(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId) kmemsysNumaAddMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId) +#define kmemsysNumaRemoveMemory(pGpu, pKernelMemorySystem, swizzId) kmemsysNumaRemoveMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId) +#define kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, swizzId) kmemsysNumaRemoveMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId) +#define kmemsysNumaRemoveAllMemory(pGpu, pKernelMemorySystem) kmemsysNumaRemoveAllMemory_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysNumaRemoveAllMemory_HAL(pGpu, pKernelMemorySystem) kmemsysNumaRemoveAllMemory_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysSetupAllAtsPeers(pGpu, pKernelMemorySystem) kmemsysSetupAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysSetupAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysSetupAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysStateLoad(pGpu, pEngstate, arg0) kmemsysStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStateUnload(pGpu, pEngstate, arg0) kmemsysStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStatePostUnload(pGpu, pEngstate, arg0) kmemsysStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -314,7 +327,6 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysInitMissing(pGpu, pEngstate) kmemsysInitMissing_DISPATCH(pGpu, pEngstate) #define kmemsysStatePreInitLocked(pGpu, pEngstate) kmemsysStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kmemsysStatePreInitUnlocked(pGpu, pEngstate) kmemsysStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kmemsysStatePostLoad(pGpu, pEngstate, arg0) kmemsysStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysIsPresent(pGpu, pEngstate) kmemsysIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmemsysGetUsableFbSize_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize); @@ -486,6 +498,20 @@ static inline NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig(OBJGPU *pGpu, str #define kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem) kmemsysPopulateMIGGPUInstanceMemConfig(pGpu, pKernelMemorySystem) +NvBool kmemsysNeedInvalidateGpuCacheOnMap_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bIsVolatile, NvU32 aperture); + + +#ifdef __nvoc_kern_mem_sys_h_disabled +static inline NvBool kmemsysNeedInvalidateGpuCacheOnMap(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bIsVolatile, NvU32 aperture) { + NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kern_mem_sys_h_disabled +#define kmemsysNeedInvalidateGpuCacheOnMap(pGpu, pKernelMemorySystem, bIsVolatile, aperture) kmemsysNeedInvalidateGpuCacheOnMap_GV100(pGpu, pKernelMemorySystem, bIsVolatile, aperture) +#endif //__nvoc_kern_mem_sys_h_disabled + +#define kmemsysNeedInvalidateGpuCacheOnMap_HAL(pGpu, pKernelMemorySystem, bIsVolatile, aperture) kmemsysNeedInvalidateGpuCacheOnMap(pGpu, pKernelMemorySystem, bIsVolatile, aperture) + NV_STATUS kmemsysConstructEngine_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, ENGDESCRIPTOR arg0); static inline NV_STATUS kmemsysConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, ENGDESCRIPTOR arg0) { @@ -504,6 +530,12 @@ static inline NV_STATUS kmemsysStatePreLoad_DISPATCH(OBJGPU *pGpu, struct Kernel return pKernelMemorySystem->__kmemsysStatePreLoad__(pGpu, pKernelMemorySystem, flags); } +NV_STATUS kmemsysStatePostLoad_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags); + +static inline NV_STATUS kmemsysStatePostLoad_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { + return pKernelMemorySystem->__kmemsysStatePostLoad__(pGpu, pKernelMemorySystem, flags); +} + void kmemsysStateDestroy_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); static inline void kmemsysStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { @@ -642,6 +674,46 @@ static inline NV_STATUS kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(OBJGPU *pGpu, return pKernelMemorySystem->__kmemsysSwizzIdToVmmuSegmentsRange__(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments); } +NV_STATUS kmemsysNumaAddMemory_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU64 offset, NvU64 size, NvS32 *numaNodeId); + +static inline NV_STATUS kmemsysNumaAddMemory_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU64 offset, NvU64 size, NvS32 *numaNodeId) { + return NV_OK; +} + +static inline NV_STATUS kmemsysNumaAddMemory_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, NvU64 offset, NvU64 size, NvS32 *numaNodeId) { + return pKernelMemorySystem->__kmemsysNumaAddMemory__(pGpu, pKernelMemorySystem, swizzId, offset, size, numaNodeId); +} + +void kmemsysNumaRemoveMemory_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId); + +static inline void kmemsysNumaRemoveMemory_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId) { + return; +} + +static inline void kmemsysNumaRemoveMemory_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId) { + pKernelMemorySystem->__kmemsysNumaRemoveMemory__(pGpu, pKernelMemorySystem, swizzId); +} + +void kmemsysNumaRemoveAllMemory_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline void kmemsysNumaRemoveAllMemory_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return; +} + +static inline void kmemsysNumaRemoveAllMemory_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + pKernelMemorySystem->__kmemsysNumaRemoveAllMemory__(pGpu, pKernelMemorySystem); +} + +static inline NV_STATUS kmemsysSetupAllAtsPeers_46f6a7(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kmemsysSetupAllAtsPeers_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NV_STATUS kmemsysSetupAllAtsPeers_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysSetupAllAtsPeers__(pGpu, pKernelMemorySystem); +} + static inline NV_STATUS kmemsysStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { return pEngstate->__kmemsysStateLoad__(pGpu, pEngstate, arg0); } @@ -674,10 +746,6 @@ static inline NV_STATUS kmemsysStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struc return pEngstate->__kmemsysStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kmemsysStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return pEngstate->__kmemsysStatePostLoad__(pGpu, pEngstate, arg0); -} - static inline NvBool kmemsysIsPresent_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { return pEngstate->__kmemsysIsPresent__(pGpu, pEngstate); } @@ -813,7 +881,7 @@ static inline NV_STATUS kmemsysInitMIGGPUInstanceMemConfigForSwizzId(OBJGPU *arg #define IS_COHERENT_CPU_ATS_OFFSET(kmemsys, offset, length) \ - (kmemsys && ((offset) >= kmemsys->coherentCpuFbBase) && \ + (kmemsys && ((offset) >= kmemsys->coherentCpuFbBase) && \ (((NvU64)offset + size) <= kmemsys->coherentCpuFbEnd)) #endif // KERN_MEM_SYS_H diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.h b/src/nvidia/generated/g_kern_pmu_nvoc.h index d954f7e5c6..706c74179e 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.h +++ b/src/nvidia/generated/g_kern_pmu_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index 280089ebb2..1be5cb2a1c 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -230,238 +230,205 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifStateInitLocked__ = &kbifStateInitLocked_IMPL; // Hal function -- kbifStateLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbifStateLoad__ = &kbifStateLoad_IMPL; - } + pThis->__kbifStateLoad__ = &kbifStateLoad_IMPL; // Hal function -- kbifStatePostLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_IMPL; - } + pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_IMPL; // Hal function -- kbifStateUnload - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbifStateUnload__ = &kbifStateUnload_IMPL; - } + pThis->__kbifStateUnload__ = &kbifStateUnload_IMPL; // Hal function -- kbifGetXveStatusBits - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GM107; + pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GH100; + pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GM107; } // Hal function -- kbifClearXveStatus - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GM107; + pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GH100; + pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GM107; } // Hal function -- kbifGetXveAerBits - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GM107; + pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GH100; + pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GM107; } // Hal function -- kbifClearXveAer - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifClearXveAer__ = &kbifClearXveAer_GM107; + pThis->__kbifClearXveAer__ = &kbifClearXveAer_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifClearXveAer__ = &kbifClearXveAer_GH100; + pThis->__kbifClearXveAer__ = &kbifClearXveAer_GM107; } // Hal function -- kbifGetPcieConfigAccessTestRegisters - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_b3696a; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_b3696a; - } + pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_GM107; } // Hal function -- kbifVerifyPcieConfigAccessTestRegisters - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_56cd7a; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_56cd7a; - } + pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_GM107; } // Hal function -- kbifRearmMSI - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifRearmMSI__ = &kbifRearmMSI_GM107; + pThis->__kbifRearmMSI__ = &kbifRearmMSI_f2d351; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifRearmMSI__ = &kbifRearmMSI_f2d351; + pThis->__kbifRearmMSI__ = &kbifRearmMSI_GM107; } // Hal function -- kbifIsMSIEnabledInHW - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GM107; + pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GH100; + pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GM107; } // Hal function -- kbifIsMSIXEnabledInHW - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_TU102; + pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_GH100; + pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_TU102; } // Hal function -- kbifIsPciIoAccessEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_GM107; + pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + else { - pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_491d52; + pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_GM107; } // Hal function -- kbifIs3dController - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifIs3dController__ = &kbifIs3dController_GM107; + pThis->__kbifIs3dController__ = &kbifIs3dController_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifIs3dController__ = &kbifIs3dController_GH100; + pThis->__kbifIs3dController__ = &kbifIs3dController_GM107; } // Hal function -- kbifExecC73War - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifExecC73War__ = &kbifExecC73War_GM107; + pThis->__kbifExecC73War__ = &kbifExecC73War_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifExecC73War__ = &kbifExecC73War_b3696a; + pThis->__kbifExecC73War__ = &kbifExecC73War_GM107; } // Hal function -- kbifEnableExtendedTagSupport - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_GH100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_GH100; - } - // default - else - { - pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_b3696a; - } + pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_b3696a; } // Hal function -- kbifPcieConfigEnableRelaxedOrdering - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GH100; - } + pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GH100; + } + else + { + pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GM107; } // Hal function -- kbifPcieConfigDisableRelaxedOrdering - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GH100; - } + pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GH100; + } + else + { + pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GM107; } // Hal function -- kbifInitRelaxedOrderingFromEmulatedConfigSpace - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100; - } - // default - else - { - pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a; - } + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100; + } + // default + else + { + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a; } // Hal function -- kbifEnableNoSnoop - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GH100; - } + pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GH100; + } + else + { + pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GM107; } // Hal function -- kbifApplyWARBug3208922 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { - pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_GA100; + pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + else { - pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_b3696a; + pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_GA100; } // Hal function -- kbifProbePcieReqAtomicCaps - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_GH100; - } - // default - else - { - pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_b3696a; - } + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_GH100; + } + // default + else + { + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_b3696a; } // Hal function -- kbifEnablePcieAtomics @@ -476,23 +443,23 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } // Hal function -- kbifGetPciConfigSpacePriMirror - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GM107; + pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GH100; + pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GM107; } // Hal function -- kbifGetBusOptionsAddr - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GM107; + pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GH100; + pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GM107; } // Hal function -- kbifPreOsGlobalErotGrantRequest diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index 1b93d9d806..5f48c7580c 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -146,6 +146,7 @@ struct KernelBif { NvBool peerMappingOverride; NvBool EnteredRecoverySinceErrorsLastChecked; NvU32 osPcieAtomicsOpMask; + NvBool bMnocAvailable; }; #ifndef __NVOC_CLASS_KernelBif_TYPEDEF__ @@ -326,47 +327,48 @@ static inline void kbifDisableP2PTransactions(struct OBJGPU *pGpu, struct Kernel #define kbifDisableP2PTransactions_HAL(pGpu, pKernelBif) kbifDisableP2PTransactions(pGpu, pKernelBif) -NV_STATUS kbifGetNumVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU32 *numAreas); +NV_STATUS kbifGetVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 osPageSize, NvU32 *pNumAreas, NvU64 *pOffsets, NvU64 *pSizes); #ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetNumVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU32 *numAreas) { +static inline NV_STATUS kbifGetVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 osPageSize, NvU32 *pNumAreas, NvU64 *pOffsets, NvU64 *pSizes) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifGetNumVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) kbifGetNumVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) +#define kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) kbifGetVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) #endif //__nvoc_kernel_bif_h_disabled -#define kbifGetNumVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) kbifGetNumVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) +#define kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) -NV_STATUS kbifGetVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 os_page_size, NvU64 *offsets, NvU64 *sizes); +NV_STATUS kbifDisableSysmemAccess_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable); #ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 os_page_size, NvU64 *offsets, NvU64 *sizes) { +static inline NV_STATUS kbifDisableSysmemAccess(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) kbifGetVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) +#define kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess_GM107(pGpu, pKernelBif, bDisable) #endif //__nvoc_kernel_bif_h_disabled -#define kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) +#define kbifDisableSysmemAccess_HAL(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) -NV_STATUS kbifDisableSysmemAccess_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable); +static inline void kbifIsMnocSupported_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; +} #ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifDisableSysmemAccess(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable) { +static inline void kbifIsMnocSupported(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess_GM107(pGpu, pKernelBif, bDisable) +#define kbifIsMnocSupported(pGpu, pKernelBif) kbifIsMnocSupported_b3696a(pGpu, pKernelBif) #endif //__nvoc_kernel_bif_h_disabled -#define kbifDisableSysmemAccess_HAL(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) +#define kbifIsMnocSupported_HAL(pGpu, pKernelBif) kbifIsMnocSupported(pGpu, pKernelBif) NV_STATUS kbifConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0); @@ -704,6 +706,28 @@ static inline NV_STATUS kbifPollDeviceOnBus(struct OBJGPU *pGpu, struct KernelBi #define kbifPollDeviceOnBus(pGpu, pKernelBif) kbifPollDeviceOnBus_IMPL(pGpu, pKernelBif) #endif //__nvoc_kernel_bif_h_disabled +NvU32 kbifGetGpuLinkCapabilities_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NvU32 kbifGetGpuLinkCapabilities(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return 0; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetGpuLinkCapabilities(pGpu, pKernelBif) kbifGetGpuLinkCapabilities_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + +NvU32 kbifGetGpuLinkControlStatus_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NvU32 kbifGetGpuLinkControlStatus(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return 0; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetGpuLinkControlStatus(pGpu, pKernelBif) kbifGetGpuLinkControlStatus_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + NvBool kbifIsPciBusFamily_IMPL(struct KernelBif *pKernelBif); #ifdef __nvoc_kernel_bif_h_disabled diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.c b/src/nvidia/generated/g_kernel_ccu_nvoc.c index e77ee50ec3..df0a042fb4 100644 --- a/src/nvidia/generated/g_kernel_ccu_nvoc.c +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.c @@ -175,10 +175,7 @@ static void __nvoc_init_funcTable_KernelCcu_1(KernelCcu *pThis, RmHalspecOwner * PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- kccuConstructEngine - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kccuConstructEngine__ = &kccuConstructEngine_IMPL; - } + pThis->__kccuConstructEngine__ = &kccuConstructEngine_IMPL; pThis->__kccuStateLoad__ = &kccuStateLoad_IMPL; diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.c b/src/nvidia/generated/g_kernel_ce_nvoc.c index 4a2beca94d..54d03c2e5e 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_nvoc.c @@ -91,7 +91,7 @@ static NV_STATUS __nvoc_thunk_KernelCE_engstateStateUnload(OBJGPU *pGpu, struct return kceStateUnload(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[166]) { +static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { kceRegisterIntrService(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); } @@ -208,22 +208,14 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceConstructEngine__ = &kceConstructEngine_IMPL; // Hal function -- kceIsPresent - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kceIsPresent__ = &kceIsPresent_IMPL; - } + pThis->__kceIsPresent__ = &kceIsPresent_IMPL; // Hal function -- kceStateLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kceStateLoad__ = &kceStateLoad_GP100; - } + pThis->__kceStateLoad__ = &kceStateLoad_GP100; // Hal function -- kceStateUnload // default - { - pThis->__kceStateUnload__ = &kceStateUnload_56cd7a; - } + pThis->__kceStateUnload__ = &kceStateUnload_56cd7a; pThis->__kceRegisterIntrService__ = &kceRegisterIntrService_IMPL; @@ -234,7 +226,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_GA100; } @@ -244,45 +236,51 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_491d52; } // Hal function -- kceIsCurrentMaxTopology - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_GA100; + pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_491d52; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_491d52; + pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_GA100; } - // Hal function -- kceGetPce2lceConfigSize1 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + // Hal function -- kceGetAutoConfigTableEntry + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_TU102; + pThis->__kceGetAutoConfigTableEntry__ = &kceGetAutoConfigTableEntry_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else { - pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA100; + pThis->__kceGetAutoConfigTableEntry__ = &kceGetAutoConfigTableEntry_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + + // Hal function -- kceGetPce2lceConfigSize1 + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA102; + pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA100; } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GH100; } - - // Hal function -- kceGetMappings - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kceGetMappings__ = &kceGetMappings_GA100; + pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else + { + pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA102; + } + + // Hal function -- kceGetMappings + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceGetMappings__ = &kceGetMappings_GH100; } @@ -290,13 +288,17 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetMappings__ = &kceGetMappings_46f6a7; } + else + { + pThis->__kceGetMappings__ = &kceGetMappings_GA100; + } // Hal function -- kceMapPceLceForC2C if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_46f6a7; } @@ -317,21 +319,17 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_46f6a7; } - - // Hal function -- kceMapPceLceForNvlinkPeers - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { - pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GA100; + pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kceMapPceLceForNvlinkPeers + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GH100; } @@ -339,27 +337,27 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_46f6a7; } + else + { + pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GA100; + } // Hal function -- kceGetSysmemSupportedLceMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_4a4dee; } - - // Hal function -- kceMapAsyncLceDefault - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { - pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GA100; + pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + + // Hal function -- kceMapAsyncLceDefault + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GH100; } @@ -367,34 +365,38 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_46f6a7; } + else + { + pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GA100; + } // Hal function -- kceGetNvlinkPeerSupportedLceMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_4a4dee; } + else + { + pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA102; + } // Hal function -- kceGetGrceSupportedLceMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_4a4dee; } + else + { + pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA102; + } // Hal function -- kceIsGenXorHigherSupported if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ @@ -405,7 +407,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_cbe027; } @@ -415,7 +417,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_b3696a; } diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.h b/src/nvidia/generated/g_kernel_ce_nvoc.h index 865aca6467..bb03062a21 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -116,6 +116,7 @@ struct KernelCE { NV_STATUS (*__kceGetNvlinkAutoConfigCeValues__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); NvBool (*__kceGetNvlinkMaxTopoForTable__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, void *, NvU32, NvU32 *); NvBool (*__kceIsCurrentMaxTopology__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *); + NvBool (*__kceGetAutoConfigTableEntry__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, struct NVLINK_CE_AUTO_CONFIG_TABLE *, NvU32, NvU32 *, NvU32 *); NvU32 (*__kceGetPce2lceConfigSize1__)(struct KernelCE *); NV_STATUS (*__kceGetMappings__)(OBJGPU *, struct KernelCE *, NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *, NvU32 *); NV_STATUS (*__kceMapPceLceForC2C__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); @@ -195,6 +196,8 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceGetNvlinkMaxTopoForTable_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3) kceGetNvlinkMaxTopoForTable_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3) #define kceIsCurrentMaxTopology(pGpu, arg0, arg1, arg2, arg3) kceIsCurrentMaxTopology_DISPATCH(pGpu, arg0, arg1, arg2, arg3) #define kceIsCurrentMaxTopology_HAL(pGpu, arg0, arg1, arg2, arg3) kceIsCurrentMaxTopology_DISPATCH(pGpu, arg0, arg1, arg2, arg3) +#define kceGetAutoConfigTableEntry(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) +#define kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) #define kceGetPce2lceConfigSize1(arg0) kceGetPce2lceConfigSize1_DISPATCH(arg0) #define kceGetPce2lceConfigSize1_HAL(arg0) kceGetPce2lceConfigSize1_DISPATCH(arg0) #define kceGetMappings(pGpu, pCe, arg0, arg1, arg2, arg3) kceGetMappings_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) @@ -342,20 +345,6 @@ static inline void kceClearAssignedNvlinkPeerMasks(OBJGPU *pGpu, struct KernelCE #define kceClearAssignedNvlinkPeerMasks_HAL(pGpu, pKCe) kceClearAssignedNvlinkPeerMasks(pGpu, pKCe) -NvBool kceGetAutoConfigTableEntry_GV100(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4); - - -#ifdef __nvoc_kernel_ce_h_disabled -static inline NvBool kceGetAutoConfigTableEntry(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4) { - NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_ce_h_disabled -#define kceGetAutoConfigTableEntry(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry_GV100(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) -#endif //__nvoc_kernel_ce_h_disabled - -#define kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) - NvU32 kceGetGrceConfigSize1_TU102(struct KernelCE *arg0); @@ -396,9 +385,9 @@ static inline NV_STATUS kceStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelCE *p return pKCe->__kceStateUnload__(pGpu, pKCe, flags); } -void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[166]); +void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[167]); -static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[166]) { +static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[167]) { arg1->__kceRegisterIntrService__(arg0, arg1, arg2); } @@ -436,6 +425,14 @@ static inline NvBool kceIsCurrentMaxTopology_DISPATCH(OBJGPU *pGpu, struct Kerne return arg0->__kceIsCurrentMaxTopology__(pGpu, arg0, arg1, arg2, arg3); } +NvBool kceGetAutoConfigTableEntry_GV100(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4); + +NvBool kceGetAutoConfigTableEntry_GH100(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4); + +static inline NvBool kceGetAutoConfigTableEntry_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4) { + return pKCe->__kceGetAutoConfigTableEntry__(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4); +} + NvU32 kceGetPce2lceConfigSize1_TU102(struct KernelCE *arg0); NvU32 kceGetPce2lceConfigSize1_GA100(struct KernelCE *arg0); @@ -701,24 +698,24 @@ static inline NV_STATUS kceGetCeFromNvlinkConfig(OBJGPU *pGpu, struct KernelCE * continue; \ } -// Iterate over all CE visible to hClient -#define KCE_ITER_CLIENT_BEGIN(pGpu, pKCeIter, hClient) \ - { \ - NvU32 maxCe = ENG_CE__SIZE_1; \ - NV_STATUS kceStatus; \ - NvU32 kceInst; \ - NvU32 kceIdx; \ - for (kceInst = 0; kceInst < maxCe; kceInst++) \ - { \ - kceStatus = ceIndexFromType(pGpu, hClient, RM_ENGINE_TYPE_COPY(kceInst), &kceIdx); \ - if (kceStatus != NV_OK) \ - { \ - continue; \ - } \ - pKCeIter = GPU_GET_KCE(pGpu, kceIdx); \ - if (pKCeIter == NULL) \ - { \ - continue; \ +// Iterate over all CE visible to Device +#define KCE_ITER_DEVICE_BEGIN(pGpu, pKCeIter, pDevice) \ + { \ + NvU32 maxCe = ENG_CE__SIZE_1; \ + NV_STATUS kceStatus; \ + NvU32 kceInst; \ + NvU32 kceIdx; \ + for (kceInst = 0; kceInst < maxCe; kceInst++) \ + { \ + kceStatus = ceIndexFromType(pGpu, pDevice, RM_ENGINE_TYPE_COPY(kceInst), &kceIdx); \ + if (kceStatus != NV_OK) \ + { \ + continue; \ + } \ + pKCeIter = GPU_GET_KCE(pGpu, kceIdx); \ + if (pKCeIter == NULL) \ + { \ + continue; \ } #define KCE_ITER_END \ diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.c b/src/nvidia/generated/g_kernel_channel_nvoc.c index 12c1d4b564..0e5ca2ccb5 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_nvoc.c @@ -955,6 +955,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*pClassInfo=*/ &(__nvoc_class_def_KernelChannel.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex" +#endif + }, + { /* [48] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdGetKmb_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc56f010bu, + /*paramSize=*/ sizeof(NVC56F_CTRL_CMD_GET_KMB_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelChannel.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kchannelCtrlCmdGetKmb" +#endif + }, + { /* [49] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kchannelCtrlRotateSecureChannelIv_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc56f010cu, + /*paramSize=*/ sizeof(NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelChannel.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kchannelCtrlRotateSecureChannelIv" #endif }, @@ -962,7 +992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelChannel = { - /*numEntries=*/ 48, + /*numEntries=*/ 50, /*pExportEntries=*/ __nvoc_exported_method_def_KernelChannel }; @@ -1035,27 +1065,27 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCheckMemInterUnmap__ = &kchannelCheckMemInterUnmap_IMPL; // Hal function -- kchannelCreateUserMemDesc - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GM107; + pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GA10B; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GA10B; + pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GM107; } // Hal function -- kchannelIsUserdAddrSizeValid - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GV100; + pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GA100; + pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GH100; + pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GA100; } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) @@ -1234,6 +1264,14 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCtrlCmdStopChannel__ = &kchannelCtrlCmdStopChannel_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + pThis->__kchannelCtrlCmdGetKmb__ = &kchannelCtrlCmdGetKmb_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + pThis->__kchannelCtrlRotateSecureChannelIv__ = &kchannelCtrlRotateSecureChannelIv_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__kchannelCtrlGetTpcPartitionMode__ = &kchannelCtrlGetTpcPartitionMode_a094e1; #endif diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.h b/src/nvidia/generated/g_kernel_channel_nvoc.h index ac74876817..919a656b14 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -257,6 +257,8 @@ struct KernelChannel { NV_STATUS (*__kchannelCtrlCmdGpfifoUpdateFaultMethodBuffer__)(struct KernelChannel *, NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS *); NV_STATUS (*__kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex__)(struct KernelChannel *, NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *); NV_STATUS (*__kchannelCtrlCmdStopChannel__)(struct KernelChannel *, NVA06F_CTRL_STOP_CHANNEL_PARAMS *); + NV_STATUS (*__kchannelCtrlCmdGetKmb__)(struct KernelChannel *, NVC56F_CTRL_CMD_GET_KMB_PARAMS *); + NV_STATUS (*__kchannelCtrlRotateSecureChannelIv__)(struct KernelChannel *, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *); NV_STATUS (*__kchannelCtrlGetTpcPartitionMode__)(struct KernelChannel *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); NV_STATUS (*__kchannelCtrlSetTpcPartitionMode__)(struct KernelChannel *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); NV_STATUS (*__kchannelCtrlGetMMUDebugMode__)(struct KernelChannel *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); @@ -407,6 +409,8 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelCtrlCmdGpfifoUpdateFaultMethodBuffer(pKernelChannel, pFaultMthdBufferParams) kchannelCtrlCmdGpfifoUpdateFaultMethodBuffer_DISPATCH(pKernelChannel, pFaultMthdBufferParams) #define kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex(pKernelChannel, pParams) kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlCmdStopChannel(pKernelChannel, pStopChannelParams) kchannelCtrlCmdStopChannel_DISPATCH(pKernelChannel, pStopChannelParams) +#define kchannelCtrlCmdGetKmb(pKernelChannel, pStopChannelParams) kchannelCtrlCmdGetKmb_DISPATCH(pKernelChannel, pStopChannelParams) +#define kchannelCtrlRotateSecureChannelIv(pKernelChannel, pRotateIvParams) kchannelCtrlRotateSecureChannelIv_DISPATCH(pKernelChannel, pRotateIvParams) #define kchannelCtrlGetTpcPartitionMode(pKernelChannel, pParams) kchannelCtrlGetTpcPartitionMode_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlSetTpcPartitionMode(pKernelChannel, pParams) kchannelCtrlSetTpcPartitionMode_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlGetMMUDebugMode(pKernelChannel, pParams) kchannelCtrlGetMMUDebugMode_DISPATCH(pKernelChannel, pParams) @@ -1063,6 +1067,18 @@ static inline NV_STATUS kchannelCtrlCmdStopChannel_DISPATCH(struct KernelChannel return pKernelChannel->__kchannelCtrlCmdStopChannel__(pKernelChannel, pStopChannelParams); } +NV_STATUS kchannelCtrlCmdGetKmb_IMPL(struct KernelChannel *pKernelChannel, NVC56F_CTRL_CMD_GET_KMB_PARAMS *pStopChannelParams); + +static inline NV_STATUS kchannelCtrlCmdGetKmb_DISPATCH(struct KernelChannel *pKernelChannel, NVC56F_CTRL_CMD_GET_KMB_PARAMS *pStopChannelParams) { + return pKernelChannel->__kchannelCtrlCmdGetKmb__(pKernelChannel, pStopChannelParams); +} + +NV_STATUS kchannelCtrlRotateSecureChannelIv_IMPL(struct KernelChannel *pKernelChannel, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams); + +static inline NV_STATUS kchannelCtrlRotateSecureChannelIv_DISPATCH(struct KernelChannel *pKernelChannel, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams) { + return pKernelChannel->__kchannelCtrlRotateSecureChannelIv__(pKernelChannel, pRotateIvParams); +} + static inline NV_STATUS kchannelCtrlGetTpcPartitionMode_a094e1(struct KernelChannel *pKernelChannel, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *pParams) { return kgrctxCtrlHandle(resservGetTlsCallContext(), pKernelChannel->hKernelGraphicsContext); } @@ -1271,6 +1287,17 @@ static inline void kchannelNotifyGeneric(struct KernelChannel *pKernelChannel, N #define kchannelNotifyGeneric(pKernelChannel, notifyIndex, pNotifyParams, notifyParamsSize) kchannelNotifyGeneric_IMPL(pKernelChannel, notifyIndex, pNotifyParams, notifyParamsSize) #endif //__nvoc_kernel_channel_h_disabled +NvBool kchannelCheckIsUserMode_IMPL(struct KernelChannel *pKernelChannel); + +#ifdef __nvoc_kernel_channel_h_disabled +static inline NvBool kchannelCheckIsUserMode(struct KernelChannel *pKernelChannel) { + NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_channel_h_disabled +#define kchannelCheckIsUserMode(pKernelChannel) kchannelCheckIsUserMode_IMPL(pKernelChannel) +#endif //__nvoc_kernel_channel_h_disabled + NvBool kchannelCheckIsKernel_IMPL(struct KernelChannel *pKernelChannel); #ifdef __nvoc_kernel_channel_h_disabled @@ -1391,10 +1418,10 @@ static inline void kchannelUnmapUserD(struct OBJGPU *pGpu, struct KernelChannel #define kchannelUnmapUserD(pGpu, arg0, arg1, arg2, arg3) kchannelUnmapUserD_IMPL(pGpu, arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_channel_h_disabled -NV_STATUS kchannelGetFromDualHandle_IMPL(NvHandle arg0, NvHandle arg1, struct KernelChannel **arg2); +NV_STATUS kchannelGetFromDualHandle_IMPL(struct RsClient *arg0, NvHandle arg1, struct KernelChannel **arg2); #define kchannelGetFromDualHandle(arg0, arg1, arg2) kchannelGetFromDualHandle_IMPL(arg0, arg1, arg2) -NV_STATUS kchannelGetFromDualHandleRestricted_IMPL(NvHandle arg0, NvHandle arg1, struct KernelChannel **arg2); +NV_STATUS kchannelGetFromDualHandleRestricted_IMPL(struct RsClient *arg0, NvHandle arg1, struct KernelChannel **arg2); #define kchannelGetFromDualHandleRestricted(arg0, arg1, arg2) kchannelGetFromDualHandleRestricted_IMPL(arg0, arg1, arg2) NvU32 kchannelGetGfid_IMPL(struct KernelChannel *pKernelChannel); @@ -1420,13 +1447,13 @@ NV_STATUS kchannelGetNextKernelChannel( CHANNEL_ITERATOR *pIt, struct KernelChannel **ppKernelChannel); -NV_STATUS CliGetKernelChannelWithDevice(NvHandle hClient, - NvHandle hParent, - NvHandle hKernelChannel, +NV_STATUS CliGetKernelChannelWithDevice(struct RsClient *pClient, + NvHandle hParent, + NvHandle hKernelChannel, struct KernelChannel **ppKernelChannel); -NV_STATUS CliGetKernelChannel(NvHandle hClient, - NvHandle hKernelChannel, +NV_STATUS CliGetKernelChannel(struct RsClient *pClient, + NvHandle hKernelChannel, struct KernelChannel **ppKernelChannel); /*! diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.c b/src/nvidia/generated/g_kernel_falcon_nvoc.c index 97113bb73d..850c10f08b 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.c +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.c @@ -97,123 +97,96 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- kflcnIsRiscvActive - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_GA10X; - } + pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_TU102; + } + else + { + pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_GA10X; } // Hal function -- kflcnRiscvProgramBcr - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_f2d351; - } + pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_f2d351; + } + else + { + pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_GA102; } // Hal function -- kflcnSwitchToFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_b3696a; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_GA10X; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_b3696a; - } + pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_GA10X; } pThis->__kflcnResetHw__ = NULL; // Hal function -- kflcnPreResetWait - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_GA10X; - } - // default - else - { - pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_56cd7a; - } + pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_GA10X; + } + // default + else + { + pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_56cd7a; } // Hal function -- kflcnWaitForResetToFinish - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_TU102; - } + pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_TU102; + } + else + { + pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_GA102; } // Hal function -- kflcnReadIntrStatus - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_TU102; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_GA102; - } + pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_GA102; } // Hal function -- kflcnIntrRetrigger - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_b3696a; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_b3696a; - } + pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_GA100; } // Hal function -- kflcnMaskImemAddr - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_GA100; - } + pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_TU102; + } + else + { + pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_GA100; } // Hal function -- kflcnMaskDmemAddr - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_TU102; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_GA100; - } + pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_GA100; } } @@ -298,7 +271,7 @@ static NV_STATUS __nvoc_thunk_GenericKernelFalcon_kflcnResetHw(struct OBJGPU *pG return gkflcnResetHw(pGpu, (struct GenericKernelFalcon *)(((unsigned char *)pGenKernFlcn) - __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset)); } -static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[166]) { +static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { gkflcnRegisterIntrService(arg0, (struct GenericKernelFalcon *)(((unsigned char *)arg1) - __nvoc_rtti_GenericKernelFalcon_IntrService.offset), arg2); } diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.h b/src/nvidia/generated/g_kernel_falcon_nvoc.h index 4d1263fb33..3c606c54bc 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.h +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -479,9 +479,9 @@ static inline NV_STATUS gkflcnResetHw_DISPATCH(struct OBJGPU *pGpu, struct Gener return pGenKernFlcn->__gkflcnResetHw__(pGpu, pGenKernFlcn); } -void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[166]); +void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[167]); -static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[166]) { +static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[167]) { arg1->__gkflcnRegisterIntrService__(arg0, arg1, arg2); } diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.c b/src/nvidia/generated/g_kernel_fifo_nvoc.c index d368d28408..8d0278416c 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.c +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.c @@ -207,6 +207,12 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals { pThis->bIsSchedSupported = ((NvBool)(0 == 0)); } + + pThis->pBar1VF = ((void *)0); + + pThis->pBar1PrivVF = ((void *)0); + + pThis->pRegVF = ((void *)0); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -242,16 +248,10 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoStateDestroy__ = &kfifoStateDestroy_IMPL; // Hal function -- kfifoStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kfifoStatePostLoad__ = &kfifoStatePostLoad_GM107; - } + pThis->__kfifoStatePostLoad__ = &kfifoStatePostLoad_GM107; // Hal function -- kfifoStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kfifoStatePreUnload__ = &kfifoStatePreUnload_GM107; - } + pThis->__kfifoStatePreUnload__ = &kfifoStatePreUnload_GM107; // Hal function -- kfifoCheckChannelAllocAddrSpaces if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ @@ -264,24 +264,14 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoCheckChannelAllocAddrSpaces__ = &kfifoCheckChannelAllocAddrSpaces_56cd7a; } - // Hal function -- kfifoGetMmioUsermodeOffset + // Hal function -- kfifoConstructUsermodeMemdescs if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kfifoGetMmioUsermodeOffset__ = &kfifoGetMmioUsermodeOffset_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kfifoGetMmioUsermodeOffset__ = &kfifoGetMmioUsermodeOffset_474d46; + pThis->__kfifoConstructUsermodeMemdescs__ = &kfifoConstructUsermodeMemdescs_GH100; } - - // Hal function -- kfifoGetMmioUsermodeSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kfifoGetMmioUsermodeSize__ = &kfifoGetMmioUsermodeSize_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { - pThis->__kfifoGetMmioUsermodeSize__ = &kfifoGetMmioUsermodeSize_474d46; + pThis->__kfifoConstructUsermodeMemdescs__ = &kfifoConstructUsermodeMemdescs_GV100; } // Hal function -- kfifoChannelGroupGetLocalMaxSubcontext @@ -289,7 +279,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoChannelGroupGetLocalMaxSubcontext__ = &kfifoChannelGroupGetLocalMaxSubcontext_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoChannelGroupGetLocalMaxSubcontext__ = &kfifoChannelGroupGetLocalMaxSubcontext_GA100; } @@ -310,7 +300,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoEngineInfoXlate__ = &kfifoEngineInfoXlate_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoEngineInfoXlate__ = &kfifoEngineInfoXlate_GA100; } @@ -320,7 +310,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoGenerateWorkSubmitToken__ = &kfifoGenerateWorkSubmitToken_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoGenerateWorkSubmitToken__ = &kfifoGenerateWorkSubmitToken_GA100; } @@ -330,21 +320,21 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoUpdateUsermodeDoorbell__ = &kfifoUpdateUsermodeDoorbell_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoUpdateUsermodeDoorbell__ = &kfifoUpdateUsermodeDoorbell_GA100; } // Hal function -- kfifoRunlistGetBaseShift - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GM107; + pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA100; + pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA102; } @@ -354,7 +344,7 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GA100; } diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.h b/src/nvidia/generated/g_kernel_fifo_nvoc.h index a72cc768bd..0c3102aa2d 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.h +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -348,8 +348,13 @@ typedef enum // ENGINE_INFO_TYPE_CHRAM_PRI_BASE, + // This entry added to copy data at RMCTRL_EXPORT() call for Kernel RM + ENGINE_INFO_TYPE_KERNEL_RM_MAX, // Used for iterating the engine info table by the index passed. - ENGINE_INFO_TYPE_INVALID, + ENGINE_INFO_TYPE_INVALID = ENGINE_INFO_TYPE_KERNEL_RM_MAX, + + // Size of FIFO_ENGINE_LIST.engineData + ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE = ENGINE_INFO_TYPE_INVALID, // Input-only parameter for kfifoEngineInfoXlate. ENGINE_INFO_TYPE_PBDMA_ID @@ -370,12 +375,12 @@ typedef enum typedef struct _def_fifo_engine_list { - NvU32 engineData[ENGINE_INFO_TYPE_INVALID]; + NvU32 engineData[ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE]; NvU32 pbdmaIds[FIFO_ENGINE_MAX_NUM_PBDMA]; NvU32 pbdmaFaultIds[FIFO_ENGINE_MAX_NUM_PBDMA]; NvU32 numPbdmas; char engineName[FIFO_ENGINE_NAME_MAX_SIZE]; -} FIFO_ENGINE_LIST, *PFIFO_ENGINE_LIST; +} FIFO_ENGINE_LIST; typedef struct { @@ -455,8 +460,8 @@ MAKE_LIST(FifoSchedulingHandlerEntryList, FifoSchedulingHandlerEntry); #define INST_BLOCK_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 // Macro to verify HW and class defines are compatible -#define VERIFY_INST_BLOCK_APERTURE(vid, coh, ncoh) \ - ct_assert((vid) == INST_BLOCK_APERTURE_VIDEO_MEMORY); \ +#define VERIFY_INST_BLOCK_APERTURE(vid, coh, ncoh) \ + ct_assert((vid) == INST_BLOCK_APERTURE_VIDEO_MEMORY); \ ct_assert((coh) == INST_BLOCK_APERTURE_SYSTEM_COHERENT_MEMORY); \ ct_assert((ncoh) == INST_BLOCK_APERTURE_SYSTEM_NON_COHERENT_MEMORY) @@ -480,8 +485,7 @@ struct KernelFifo { NV_STATUS (*__kfifoStatePostLoad__)(struct OBJGPU *, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStatePreUnload__)(struct OBJGPU *, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoCheckChannelAllocAddrSpaces__)(struct KernelFifo *, NV_ADDRESS_SPACE, NV_ADDRESS_SPACE, NV_ADDRESS_SPACE); - NvU64 (*__kfifoGetMmioUsermodeOffset__)(struct OBJGPU *, struct KernelFifo *, NvBool); - NvU64 (*__kfifoGetMmioUsermodeSize__)(struct OBJGPU *, struct KernelFifo *, NvBool); + NV_STATUS (*__kfifoConstructUsermodeMemdescs__)(struct OBJGPU *, struct KernelFifo *); NvU32 (*__kfifoChannelGroupGetLocalMaxSubcontext__)(struct OBJGPU *, struct KernelFifo *, struct KernelChannelGroup *, NvBool); void (*__kfifoGetCtxBufferMapFlags__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32 *); NV_STATUS (*__kfifoEngineInfoXlate__)(struct OBJGPU *, struct KernelFifo *, ENGINE_INFO_TYPE, NvU32, ENGINE_INFO_TYPE, NvU32 *); @@ -507,6 +511,8 @@ struct KernelFifo { NvU32 maxSubcontextCount; FifoSchedulingHandlerEntryList postSchedulingEnableHandlerList; FifoSchedulingHandlerEntryList preSchedulingDisableHandlerList; + NvU32 maxSec2SecureChannels; + NvU32 maxCeSecureChannels; NvBool bUseChidHeap; NvBool bUsePerRunlistChram; NvBool bDisableChidIsolation; @@ -527,6 +533,9 @@ struct KernelFifo { NvU32 InstAttr; const NV_ADDRESS_SPACE *pInstAllocList; MEMORY_DESCRIPTOR *pDummyPageMemDesc; + MEMORY_DESCRIPTOR *pBar1VF; + MEMORY_DESCRIPTOR *pBar1PrivVF; + MEMORY_DESCRIPTOR *pRegVF; CTX_BUF_POOL_INFO *pRunlistBufPool[62]; MEMORY_DESCRIPTOR ***pppRunlistBufMemDesc; }; @@ -570,10 +579,8 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo**, Dynamic*, NvU32); #define kfifoStatePreUnload_HAL(pGpu, pKernelFifo, flags) kfifoStatePreUnload_DISPATCH(pGpu, pKernelFifo, flags) #define kfifoCheckChannelAllocAddrSpaces(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) kfifoCheckChannelAllocAddrSpaces_DISPATCH(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) #define kfifoCheckChannelAllocAddrSpaces_HAL(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) kfifoCheckChannelAllocAddrSpaces_DISPATCH(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace) -#define kfifoGetMmioUsermodeOffset(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeOffset_DISPATCH(pGpu, pKernelFifo, arg0) -#define kfifoGetMmioUsermodeOffset_HAL(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeOffset_DISPATCH(pGpu, pKernelFifo, arg0) -#define kfifoGetMmioUsermodeSize(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeSize_DISPATCH(pGpu, pKernelFifo, arg0) -#define kfifoGetMmioUsermodeSize_HAL(pGpu, pKernelFifo, arg0) kfifoGetMmioUsermodeSize_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoConstructUsermodeMemdescs(pGpu, pKernelFifo) kfifoConstructUsermodeMemdescs_DISPATCH(pGpu, pKernelFifo) +#define kfifoConstructUsermodeMemdescs_HAL(pGpu, pKernelFifo) kfifoConstructUsermodeMemdescs_DISPATCH(pGpu, pKernelFifo) #define kfifoChannelGroupGetLocalMaxSubcontext(pGpu, pKernelFifo, arg0, arg1) kfifoChannelGroupGetLocalMaxSubcontext_DISPATCH(pGpu, pKernelFifo, arg0, arg1) #define kfifoChannelGroupGetLocalMaxSubcontext_HAL(pGpu, pKernelFifo, arg0, arg1) kfifoChannelGroupGetLocalMaxSubcontext_DISPATCH(pGpu, pKernelFifo, arg0, arg1) #define kfifoGetCtxBufferMapFlags(pGpu, pKernelFifo, engine, pFlags) kfifoGetCtxBufferMapFlags_DISPATCH(pGpu, pKernelFifo, engine, pFlags) @@ -1304,6 +1311,20 @@ static inline NV_STATUS kfifoRestoreSchedPolicy(struct OBJGPU *pGpu, struct Kern #define kfifoRestoreSchedPolicy_HAL(pGpu, pKernelFifo) kfifoRestoreSchedPolicy(pGpu, pKernelFifo) +NV_STATUS kfifoGetMaxSecureChannels_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoGetMaxSecureChannels(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoGetMaxSecureChannels(pGpu, pKernelFifo) kfifoGetMaxSecureChannels_KERNEL(pGpu, pKernelFifo) +#endif //__nvoc_kernel_fifo_h_disabled + +#define kfifoGetMaxSecureChannels_HAL(pGpu, pKernelFifo) kfifoGetMaxSecureChannels(pGpu, pKernelFifo) + NV_STATUS kfifoRunlistSetId_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 runlistId); @@ -1385,24 +1406,12 @@ static inline NV_STATUS kfifoCheckChannelAllocAddrSpaces_DISPATCH(struct KernelF return pKernelFifo->__kfifoCheckChannelAllocAddrSpaces__(pKernelFifo, userdAddrSpace, pushBuffAddrSpace, gpFifoAddrSpace); } -NvU64 kfifoGetMmioUsermodeOffset_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0); - -static inline NvU64 kfifoGetMmioUsermodeOffset_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - -static inline NvU64 kfifoGetMmioUsermodeOffset_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - return pKernelFifo->__kfifoGetMmioUsermodeOffset__(pGpu, pKernelFifo, arg0); -} - -NvU64 kfifoGetMmioUsermodeSize_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0); +NV_STATUS kfifoConstructUsermodeMemdescs_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); -static inline NvU64 kfifoGetMmioUsermodeSize_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} +NV_STATUS kfifoConstructUsermodeMemdescs_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); -static inline NvU64 kfifoGetMmioUsermodeSize_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { - return pKernelFifo->__kfifoGetMmioUsermodeSize__(pGpu, pKernelFifo, arg0); +static inline NV_STATUS kfifoConstructUsermodeMemdescs_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + return pKernelFifo->__kfifoConstructUsermodeMemdescs__(pGpu, pKernelFifo); } NvU32 kfifoChannelGroupGetLocalMaxSubcontext_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *arg0, NvBool arg1); diff --git a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h index 6ac1b20858..ec32570ccd 100644 --- a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -97,9 +97,6 @@ typedef struct // Tracks whether Physical has initialized the memory descriptor for the promoted Kernel buffer NvBool bInitialized[GR_GLOBALCTX_BUFFER_COUNT]; - - // Check if vGPU Guest is running with FECS Trace feature supported driver - NvBool bFecsTraceUnsupportedInGuest; } GR_GLOBALCTX_BUFFERS; struct KernelGraphicsContextUnicast; @@ -191,7 +188,7 @@ struct KernelGraphicsContext { void (*__kgrctxControlSerialization_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxMap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kgrctxAccessCallback__)(struct KernelGraphicsContext *, struct RsClient *, void *, RsAccessRight); - struct KernelGraphicsContextShared *pShared; + struct KernelGraphicsContextShared *PRIVATE_FIELD(pShared); }; #ifndef __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ @@ -973,7 +970,7 @@ struct KernelGraphicsContextShared { struct Object *__nvoc_pbase_Object; struct RsShared *__nvoc_pbase_RsShared; struct KernelGraphicsContextShared *__nvoc_pbase_KernelGraphicsContextShared; - struct KernelGraphicsContextUnicast kernelGraphicsContextUnicast; + struct KernelGraphicsContextUnicast PRIVATE_FIELD(kernelGraphicsContextUnicast); }; #ifndef __NVOC_CLASS_KernelGraphicsContextShared_TYPEDEF__ diff --git a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h index a259bfb4f4..28cb4def22 100644 --- a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -65,6 +65,31 @@ struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO { struct KernelGraphicsManager { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelGraphicsManager *__nvoc_pbase_KernelGraphicsManager; + NV_STATUS (*__kgrmgrConstructEngine__)(struct OBJGPU *, struct KernelGraphicsManager *, ENGDESCRIPTOR); + NV_STATUS (*__kgrmgrStateLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NV_STATUS (*__kgrmgrStateUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NV_STATUS (*__kgrmgrStateInitLocked__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePreLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NV_STATUS (*__kgrmgrStatePostUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + void (*__kgrmgrStateDestroy__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePreUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NV_STATUS (*__kgrmgrStateInitUnlocked__)(POBJGPU, struct KernelGraphicsManager *); + void (*__kgrmgrInitMissing__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePreInitLocked__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePreInitUnlocked__)(POBJGPU, struct KernelGraphicsManager *); + NV_STATUS (*__kgrmgrStatePostLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); + NvBool (*__kgrmgrIsPresent__)(POBJGPU, struct KernelGraphicsManager *); + struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO PRIVATE_FIELD(legacyKgraphicsStaticInfo); + NvU64 PRIVATE_FIELD(veidInUseMask); + NvU64 PRIVATE_FIELD(grIdxVeidMask)[8]; + CTX_BUF_INFO PRIVATE_FIELD(globalCtxBufInfo)[10]; +}; +struct KernelGraphicsManager_PRIVATE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; struct Object *__nvoc_pbase_Object; @@ -192,6 +217,11 @@ static inline NvBool kgrmgrIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGraphic return pEngstate->__kgrmgrIsPresent__(pGpu, pEngstate); } +static inline NvU64 kgrmgrGetGrIdxVeidMask(struct OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager, NvU32 grIdx) { + struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; + return pKernelGraphicsManager_PRIVATE->grIdxVeidMask[grIdx]; +} + void kgrmgrGetGrObjectType_IMPL(NvU32 classNum, NvU32 *pObjectType); #define kgrmgrGetGrObjectType(classNum, pObjectType) kgrmgrGetGrObjectType_IMPL(classNum, pObjectType) @@ -231,6 +261,17 @@ static inline NV_STATUS kgrmgrCtrlRouteKGR(struct OBJGPU *arg0, struct KernelGra #define kgrmgrCtrlRouteKGR(arg0, arg1, hClient, pGrRouteInfo, ppKernelGraphics) kgrmgrCtrlRouteKGR_IMPL(arg0, arg1, hClient, pGrRouteInfo, ppKernelGraphics) #endif //__nvoc_kernel_graphics_manager_h_disabled +NV_STATUS kgrmgrCtrlRouteKGRWithDevice_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct Device *pDevice, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics); + +#ifdef __nvoc_kernel_graphics_manager_h_disabled +static inline NV_STATUS kgrmgrCtrlRouteKGRWithDevice(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct Device *pDevice, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_graphics_manager_h_disabled +#define kgrmgrCtrlRouteKGRWithDevice(arg0, arg1, pDevice, pGrRouteInfo, ppKernelGraphics) kgrmgrCtrlRouteKGRWithDevice_IMPL(arg0, arg1, pDevice, pGrRouteInfo, ppKernelGraphics) +#endif //__nvoc_kernel_graphics_manager_h_disabled + NvU32 kgrmgrGetLegacyGpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1); #ifdef __nvoc_kernel_graphics_manager_h_disabled @@ -242,6 +283,17 @@ static inline NvU32 kgrmgrGetLegacyGpcMask(struct OBJGPU *arg0, struct KernelGra #define kgrmgrGetLegacyGpcMask(arg0, arg1) kgrmgrGetLegacyGpcMask_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_manager_h_disabled +NvU32 kgrmgrGetLegacyPhysGfxGpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1); + +#ifdef __nvoc_kernel_graphics_manager_h_disabled +static inline NvU32 kgrmgrGetLegacyPhysGfxGpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); + return 0; +} +#else //__nvoc_kernel_graphics_manager_h_disabled +#define kgrmgrGetLegacyPhysGfxGpcMask(arg0, arg1) kgrmgrGetLegacyPhysGfxGpcMask_IMPL(arg0, arg1) +#endif //__nvoc_kernel_graphics_manager_h_disabled + NvU32 kgrmgrGetLegacyTpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId); #ifdef __nvoc_kernel_graphics_manager_h_disabled diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.c b/src/nvidia/generated/g_kernel_graphics_nvoc.c index 30ba127711..820a450efb 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.c @@ -107,7 +107,7 @@ static NV_STATUS __nvoc_thunk_KernelGraphics_engstateStatePostLoad(OBJGPU *arg0, return kgraphicsStatePostLoad(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[166]) { +static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { kgraphicsRegisterIntrService(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_IntrService.offset), arg2); } @@ -277,16 +277,10 @@ static void __nvoc_init_funcTable_KernelGraphics_1(KernelGraphics *pThis, RmHals pThis->__kgraphicsServiceNotificationInterrupt__ = &kgraphicsServiceNotificationInterrupt_IMPL; // Hal function -- kgraphicsClearInterrupt - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgraphicsClearInterrupt__ = &kgraphicsClearInterrupt_GP100; - } + pThis->__kgraphicsClearInterrupt__ = &kgraphicsClearInterrupt_GP100; // Hal function -- kgraphicsServiceInterrupt - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgraphicsServiceInterrupt__ = &kgraphicsServiceInterrupt_GP100; - } + pThis->__kgraphicsServiceInterrupt__ = &kgraphicsServiceInterrupt_GP100; pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGraphics_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.h b/src/nvidia/generated/g_kernel_graphics_nvoc.h index 9e62cd2ef5..d1f12b6215 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.h @@ -151,6 +151,50 @@ typedef struct KGRAPHICS_FECS_TRACE_INFO KGRAPHICS_FECS_TRACE_INFO; #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif struct KernelGraphics { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct IntrService __nvoc_base_IntrService; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct IntrService *__nvoc_pbase_IntrService; + struct KernelGraphics *__nvoc_pbase_KernelGraphics; + NV_STATUS (*__kgraphicsConstructEngine__)(OBJGPU *, struct KernelGraphics *, ENGDESCRIPTOR); + NV_STATUS (*__kgraphicsStateInitLocked__)(OBJGPU *, struct KernelGraphics *); + NV_STATUS (*__kgraphicsStateLoad__)(OBJGPU *, struct KernelGraphics *, NvU32); + NV_STATUS (*__kgraphicsStatePreUnload__)(OBJGPU *, struct KernelGraphics *, NvU32); + NV_STATUS (*__kgraphicsStateUnload__)(OBJGPU *, struct KernelGraphics *, NvU32); + void (*__kgraphicsStateDestroy__)(OBJGPU *, struct KernelGraphics *); + NvBool (*__kgraphicsIsPresent__)(OBJGPU *, struct KernelGraphics *); + NV_STATUS (*__kgraphicsStatePostLoad__)(OBJGPU *, struct KernelGraphics *, NvU32); + void (*__kgraphicsRegisterIntrService__)(OBJGPU *, struct KernelGraphics *, IntrServiceRecord *); + NV_STATUS (*__kgraphicsServiceNotificationInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceNotificationInterruptArguments *); + NvBool (*__kgraphicsClearInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceClearInterruptArguments *); + NvU32 (*__kgraphicsServiceInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceInterruptArguments *); + NV_STATUS (*__kgraphicsStatePreLoad__)(POBJGPU, struct KernelGraphics *, NvU32); + NV_STATUS (*__kgraphicsStatePostUnload__)(POBJGPU, struct KernelGraphics *, NvU32); + NV_STATUS (*__kgraphicsStateInitUnlocked__)(POBJGPU, struct KernelGraphics *); + void (*__kgraphicsInitMissing__)(POBJGPU, struct KernelGraphics *); + NV_STATUS (*__kgraphicsStatePreInitLocked__)(POBJGPU, struct KernelGraphics *); + NV_STATUS (*__kgraphicsStatePreInitUnlocked__)(POBJGPU, struct KernelGraphics *); + NvBool PRIVATE_FIELD(bCtxswLoggingSupported); + NvBool PRIVATE_FIELD(bIntrDrivenCtxswLoggingEnabled); + NvBool PRIVATE_FIELD(bBottomHalfCtxswLoggingEnabled); + NvBool PRIVATE_FIELD(bDeferContextInit); + NvBool PRIVATE_FIELD(bPerSubcontextContextHeaderSupported); + NvBool PRIVATE_FIELD(bSetContextBuffersGPUPrivileged); + NvBool PRIVATE_FIELD(bUcodeSupportsPrivAccessMap); + NvBool PRIVATE_FIELD(bRtvCbSupported); + NvBool PRIVATE_FIELD(bFecsRecordUcodeSeqnoSupported); + NvU32 PRIVATE_FIELD(instance); + KGRAPHICS_PRIVATE_DATA *PRIVATE_FIELD(pPrivate); + NvBool PRIVATE_FIELD(bCollectingDeferredStaticData); + KGRAPHICS_FECS_TRACE_INFO *PRIVATE_FIELD(pFecsTraceInfo); + struct KGRAPHICS_GLOBAL_CTX_BUFFERS_INFO PRIVATE_FIELD(globalCtxBuffersInfo); + struct CTX_BUF_POOL_INFO *PRIVATE_FIELD(pCtxBufPool); + CTX_BUF_INFO PRIVATE_FIELD(maxCtxBufSize)[9]; + GR_BUFFER_ATTR PRIVATE_FIELD(ctxAttr)[9]; +}; +struct KernelGraphics_PRIVATE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; struct IntrService __nvoc_base_IntrService; @@ -407,9 +451,9 @@ static inline NV_STATUS kgraphicsStatePostLoad_DISPATCH(OBJGPU *arg0, struct Ker return arg1->__kgraphicsStatePostLoad__(arg0, arg1, flags); } -void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[166]); +void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[167]); -static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[166]) { +static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[167]) { arg1->__kgraphicsRegisterIntrService__(arg0, arg1, arg2); } @@ -456,63 +500,78 @@ static inline NV_STATUS kgraphicsStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, str } static inline KGRAPHICS_FECS_TRACE_INFO *kgraphicsGetFecsTraceInfo(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->pFecsTraceInfo; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->pFecsTraceInfo; } static inline NvU32 kgraphicsGetInstance(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->instance; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->instance; } static inline NvBool kgraphicsIsCtxswLoggingSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bCtxswLoggingSupported; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bCtxswLoggingSupported; } static inline void kgraphicsSetCtxswLoggingSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics, NvBool bProp) { - pKernelGraphics->bCtxswLoggingSupported = bProp; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + pKernelGraphics_PRIVATE->bCtxswLoggingSupported = bProp; } static inline NvBool kgraphicsIsIntrDrivenCtxswLoggingEnabled(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bIntrDrivenCtxswLoggingEnabled; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bIntrDrivenCtxswLoggingEnabled; } static inline void kgraphicsSetIntrDrivenCtxswLoggingEnabled(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics, NvBool bProp) { - pKernelGraphics->bIntrDrivenCtxswLoggingEnabled = bProp; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + pKernelGraphics_PRIVATE->bIntrDrivenCtxswLoggingEnabled = bProp; } static inline NvBool kgraphicsIsBottomHalfCtxswLoggingEnabled(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bBottomHalfCtxswLoggingEnabled; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bBottomHalfCtxswLoggingEnabled; } static inline void kgraphicsSetBottomHalfCtxswLoggingEnabled(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics, NvBool bProp) { - pKernelGraphics->bBottomHalfCtxswLoggingEnabled = bProp; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + pKernelGraphics_PRIVATE->bBottomHalfCtxswLoggingEnabled = bProp; } static inline NvBool kgraphicsShouldDeferContextInit(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bDeferContextInit; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bDeferContextInit; } static inline NvBool kgraphicsIsPerSubcontextContextHeaderSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bPerSubcontextContextHeaderSupported; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bPerSubcontextContextHeaderSupported; } static inline void kgraphicsSetPerSubcontextContextHeaderSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics, NvBool bProp) { - pKernelGraphics->bPerSubcontextContextHeaderSupported = bProp; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + pKernelGraphics_PRIVATE->bPerSubcontextContextHeaderSupported = bProp; } static inline NvBool kgraphicsShouldSetContextBuffersGPUPrivileged(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bSetContextBuffersGPUPrivileged; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bSetContextBuffersGPUPrivileged; } static inline NvBool kgraphicsDoesUcodeSupportPrivAccessMap(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bUcodeSupportsPrivAccessMap; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bUcodeSupportsPrivAccessMap; } static inline NvBool kgraphicsIsRtvCbSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bRtvCbSupported; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bRtvCbSupported; } static inline NvBool kgraphicsIsFecsRecordUcodeSeqnoSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { - return pKernelGraphics->bFecsRecordUcodeSeqnoSupported; + struct KernelGraphics_PRIVATE *pKernelGraphics_PRIVATE = (struct KernelGraphics_PRIVATE *)pKernelGraphics; + return pKernelGraphics_PRIVATE->bFecsRecordUcodeSeqnoSupported; } void kgraphicsDestruct_IMPL(struct KernelGraphics *arg0); diff --git a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h index a9391348a7..714e80d530 100644 --- a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -108,7 +108,7 @@ struct KernelGraphicsObject { struct NotifShare *(*__kgrobjGetNotificationShare__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjMap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NV_STATUS (*__kgrobjGetOrAllocNotifShare__)(struct KernelGraphicsObject *, NvHandle, NvHandle, struct NotifShare **); - MEMORY_DESCRIPTOR *pMmioMemDesc; + MEMORY_DESCRIPTOR *PRIVATE_FIELD(pMmioMemDesc); KernelSMDebuggerSessionList activeDebuggers; struct KernelGraphicsContext *pKernelGraphicsContext; }; diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index 12c36becf3..57df681851 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -88,7 +88,7 @@ static NV_STATUS __nvoc_thunk_KernelGsp_engstateConstructEngine(struct OBJGPU *p return kgspConstructEngine(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[166]) { +static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[167]) { kgspRegisterIntrService(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_IntrService.offset), pRecords); } @@ -202,6 +202,40 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe { pThis->bPartitionedFmc = ((NvBool)(0 != 0)); } + + // Hal field -- bScrubberUcodeSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->bScrubberUcodeSupported = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bScrubberUcodeSupported = ((NvBool)(0 != 0)); + } + + // Hal field -- fwHeapParamBaseSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->fwHeapParamBaseSize = (8 << 20); + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->fwHeapParamBaseSize = (14 << 20); + } + + // Hal field -- fwHeapParamOsCarveoutSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->fwHeapParamOsCarveoutSize = (0 << 20); + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->fwHeapParamOsCarveoutSize = (20 << 20); + } + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -247,466 +281,424 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__kgspServiceInterrupt__ = &kgspServiceInterrupt_IMPL; // Hal function -- kgspConfigureFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; - } + pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; + } + else + { + pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; } // Hal function -- kgspIsDebugModeEnabled - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; - } + pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; + } + else + { + pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; } // Hal function -- kgspAllocBootArgs - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; - } + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; + } + else + { + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; } // Hal function -- kgspFreeBootArgs - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; - } + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; + } + else + { + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; } // Hal function -- kgspBootstrapRiscvOSEarly - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GH100; - } + pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_TU102; + } + else + { + pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GA102; } // Hal function -- kgspGetGspRmBootUcodeStorage - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GH100; - } + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; + } + else + { + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; } // Hal function -- kgspGetBinArchiveGspRmBoot - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; - } + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; + } + else + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; + } + + // Hal function -- kgspGetBinArchiveConcatenatedFMCDesc + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_GH100; + } + else + { + pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_80f438; + } + + // Hal function -- kgspGetBinArchiveConcatenatedFMC + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_GH100; + } + else + { + pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_80f438; } // Hal function -- kgspGetBinArchiveGspRmFmcGfwDebugSigned - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; - } - // default - else - { - pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; - } + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; } // Hal function -- kgspGetBinArchiveGspRmFmcGfwProdSigned - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; - } - // default - else - { - pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; - } + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; + } + + // Hal function -- kgspGetBinArchiveGspRmCcFmcGfwProdSigned + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_80f438; } // Hal function -- kgspCalculateFbLayout - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; - } + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; + } + else + { + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; } // Hal function -- kgspGetNonWprHeapSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; - } + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; + } + else + { + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; } // Hal function -- kgspExecuteSequencerCommand - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; - } + pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; + } + else + { + pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; } // Hal function -- kgspReadUcodeFuseVersion - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; - } + pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; + } + else + { + pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; } // Hal function -- kgspResetHw - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspResetHw__ = &kgspResetHw_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspResetHw__ = &kgspResetHw_GH100; - } + pThis->__kgspResetHw__ = &kgspResetHw_GH100; + } + else + { + pThis->__kgspResetHw__ = &kgspResetHw_TU102; + } + + // Hal function -- kgspIsWpr2Up + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_GH100; + } + else + { + pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_TU102; } // Hal function -- kgspGetFrtsSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; - } + pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; + } + else + { + pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; } // Hal function -- kgspGetPrescrubbedTopFbSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_dd2c0b; - } + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_604eb7; + } + else + { + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623; } // Hal function -- kgspExtractVbiosFromRom - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; - } + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; + } + else + { + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; } // Hal function -- kgspExecuteFwsecFrts - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_5baef9; - } + pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_5baef9; + } + else + { + pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_TU102; } // Hal function -- kgspExecuteFwsecSb - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_ac1694; - } + pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_ac1694; + } + else + { + pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_TU102; } // Hal function -- kgspExecuteScrubberIfNeeded - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ - { - pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9; - } + pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102; + } + else + { + pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9; } // Hal function -- kgspExecuteBooterLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; - } + pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; + } + else + { + pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; } // Hal function -- kgspExecuteBooterUnloadIfNeeded - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; - } + pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; + } + else + { + pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; } // Hal function -- kgspExecuteHsFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; - } + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; + } + else + { + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; } // Hal function -- kgspWaitForGfwBootOk - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; - } + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; + } + else + { + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; } // Hal function -- kgspGetBinArchiveBooterLoadUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU116; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; - } + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU116; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; + } + else + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; } // Hal function -- kgspGetBinArchiveBooterUnloadUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU116; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; - } + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU116; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; + } + else + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; } - // Hal function -- kgspGetWprHeapSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + // Hal function -- kgspGetMinWprHeapSizeMB + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GH100 */ - { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_45a5e0; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_31541f; - } + pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_7185bf; + } + else + { + pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_907c84; + } + + // Hal function -- kgspGetMaxWprHeapSizeMB + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_ad4e6a; + } + else + { + pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_5839e2; } // Hal function -- kgspInitVgpuPartitionLogging - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GH100 */ - { - pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; - } + pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; + } + else + { + pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; } // Hal function -- kgspFreeVgpuPartitionLogging - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GH100 */ - { - pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; - } + pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; + } + else + { + pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; } // Hal function -- kgspGetSignatureSectionNamePrefix - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_GH100; - } - // default - else - { - pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_789efb; - } + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_GH100; + } + // default + else + { + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_789efb; } // Hal function -- kgspSetupGspFmcArgs - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; - } - // default - else - { - pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; - } + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; + } + // default + else + { + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGsp_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index 13762fe38e..7c06383516 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -209,6 +209,7 @@ typedef struct GSP_FIRMWARE #define GSP_IMAGE_SECTION_NAME ".fwimage" #define GSP_LOGGING_SECTION_NAME ".fwlogging" #define GSP_SIGNATURE_SECTION_NAME_PREFIX ".fwsignature_" +#define GSP_CC_SIGNATURE_SECTION_NAME_PREFIX ".fwsignature_cc_" /*! * Index into libosLogDecode array. @@ -264,13 +265,17 @@ struct KernelGsp { NV_STATUS (*__kgspBootstrapRiscvOSEarly__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); void (*__kgspGetGspRmBootUcodeStorage__)(struct OBJGPU *, struct KernelGsp *, BINDATA_STORAGE **, BINDATA_STORAGE **); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmBoot__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveConcatenatedFMCDesc__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveConcatenatedFMC__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmFmcGfwDebugSigned__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmFmcGfwProdSigned__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__)(struct KernelGsp *); NV_STATUS (*__kgspCalculateFbLayout__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); NvU32 (*__kgspGetNonWprHeapSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteSequencerCommand__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32 *, NvU32); NvU32 (*__kgspReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelGsp *, NvU32); NV_STATUS (*__kgspResetHw__)(struct OBJGPU *, struct KernelGsp *); + NvBool (*__kgspIsWpr2Up__)(struct OBJGPU *, struct KernelGsp *); NvU32 (*__kgspGetFrtsSize__)(struct OBJGPU *, struct KernelGsp *); NvU64 (*__kgspGetPrescrubbedTopFbSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExtractVbiosFromRom__)(struct OBJGPU *, struct KernelGsp *, KernelGspVbiosImg **); @@ -283,7 +288,8 @@ struct KernelGsp { NV_STATUS (*__kgspWaitForGfwBootOk__)(struct OBJGPU *, struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *); - NvU64 (*__kgspGetWprHeapSize__)(struct OBJGPU *, struct KernelGsp *); + NvU64 (*__kgspGetMinWprHeapSizeMB__)(struct OBJGPU *, struct KernelGsp *); + NvU64 (*__kgspGetMaxWprHeapSizeMB__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspInitVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU64, NvU64, NvU64, NvU64); NV_STATUS (*__kgspFreeVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32); const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *); @@ -342,13 +348,18 @@ struct KernelGsp { NvBool bInInit; NvBool bInLockdown; NvBool bPollingForRpcResponse; - NvBool bXid119Printed; MEMORY_DESCRIPTOR *pMemDesc_simAccessBuf; SimAccessBuffer *pSimAccessBuf; NvP64 pSimAccessBufPriv; + MEMORY_DESCRIPTOR *pProfilerSamplesMD; + void *pProfilerSamplesMDPriv; + void *pProfilerSamples; GspStaticConfigInfo gspStaticInfo; NvBool bIsTaskIsrQueueRequired; NvBool bPartitionedFmc; + NvBool bScrubberUcodeSupported; + NvU32 fwHeapParamBaseSize; + NvU32 fwHeapParamOsCarveoutSize; }; #ifndef __NVOC_CLASS_KernelGsp_TYPEDEF__ @@ -398,10 +409,16 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetGspRmBootUcodeStorage_HAL(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) kgspGetGspRmBootUcodeStorage_DISPATCH(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) #define kgspGetBinArchiveGspRmBoot(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmBoot_HAL(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveConcatenatedFMCDesc(pKernelGsp) kgspGetBinArchiveConcatenatedFMCDesc_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveConcatenatedFMCDesc_HAL(pKernelGsp) kgspGetBinArchiveConcatenatedFMCDesc_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveConcatenatedFMC(pKernelGsp) kgspGetBinArchiveConcatenatedFMC_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveConcatenatedFMC_HAL(pKernelGsp) kgspGetBinArchiveConcatenatedFMC_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmFmcGfwDebugSigned(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwDebugSigned_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmFmcGfwDebugSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwDebugSigned_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmFmcGfwProdSigned(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwProdSigned_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmFmcGfwProdSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwProdSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmCcFmcGfwProdSigned(pKernelGsp) kgspGetBinArchiveGspRmCcFmcGfwProdSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmCcFmcGfwProdSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmCcFmcGfwProdSigned_DISPATCH(pKernelGsp) #define kgspCalculateFbLayout(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspCalculateFbLayout_HAL(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspGetNonWprHeapSize(pGpu, pKernelGsp) kgspGetNonWprHeapSize_DISPATCH(pGpu, pKernelGsp) @@ -412,6 +429,8 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspReadUcodeFuseVersion_HAL(pGpu, pKernelGsp, ucodeId) kgspReadUcodeFuseVersion_DISPATCH(pGpu, pKernelGsp, ucodeId) #define kgspResetHw(pGpu, pKernelGsp) kgspResetHw_DISPATCH(pGpu, pKernelGsp) #define kgspResetHw_HAL(pGpu, pKernelGsp) kgspResetHw_DISPATCH(pGpu, pKernelGsp) +#define kgspIsWpr2Up(pGpu, pKernelGsp) kgspIsWpr2Up_DISPATCH(pGpu, pKernelGsp) +#define kgspIsWpr2Up_HAL(pGpu, pKernelGsp) kgspIsWpr2Up_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize_HAL(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) #define kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp) kgspGetPrescrubbedTopFbSize_DISPATCH(pGpu, pKernelGsp) @@ -436,8 +455,10 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetBinArchiveBooterLoadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterLoadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) -#define kgspGetWprHeapSize(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp) -#define kgspGetWprHeapSize_HAL(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp) +#define kgspGetMinWprHeapSizeMB(pGpu, pKernelGsp) kgspGetMinWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) +#define kgspGetMinWprHeapSizeMB_HAL(pGpu, pKernelGsp) kgspGetMinWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) +#define kgspGetMaxWprHeapSizeMB(pGpu, pKernelGsp) kgspGetMaxWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) +#define kgspGetMaxWprHeapSizeMB_HAL(pGpu, pKernelGsp) kgspGetMaxWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) #define kgspInitVgpuPartitionLogging(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) #define kgspInitVgpuPartitionLogging_HAL(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) #define kgspFreeVgpuPartitionLogging(pGpu, pKernelGsp, gfid) kgspFreeVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid) @@ -576,9 +597,9 @@ static inline NV_STATUS kgspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspConstructEngine__(pGpu, pKernelGsp, arg0); } -void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[166]); +void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[167]); -static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[166]) { +static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[167]) { pKernelGsp->__kgspRegisterIntrService__(pGpu, pKernelGsp, pRecords); } @@ -654,6 +675,26 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_DISPATCH(struct return pKernelGsp->__kgspGetBinArchiveGspRmBoot__(pKernelGsp); } +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_GH100(struct KernelGsp *pKernelGsp); + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMCDesc_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveConcatenatedFMCDesc__(pKernelGsp); +} + +const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_GH100(struct KernelGsp *pKernelGsp); + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveConcatenatedFMC_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveConcatenatedFMC__(pKernelGsp); +} + const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp); static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438(struct KernelGsp *pKernelGsp) { @@ -674,6 +715,16 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwProdSigned_DISP return pKernelGsp->__kgspGetBinArchiveGspRmFmcGfwProdSigned__(pKernelGsp); } +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp); + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcFmcGfwProdSigned_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__(pKernelGsp); +} + NV_STATUS kgspCalculateFbLayout_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); NV_STATUS kgspCalculateFbLayout_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); @@ -720,6 +771,14 @@ static inline NV_STATUS kgspResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelG return pKernelGsp->__kgspResetHw__(pGpu, pKernelGsp); } +NvBool kgspIsWpr2Up_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +NvBool kgspIsWpr2Up_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NvBool kgspIsWpr2Up_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspIsWpr2Up__(pGpu, pKernelGsp); +} + NvU32 kgspGetFrtsSize_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); static inline NvU32 kgspGetFrtsSize_4a4dee(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { @@ -734,8 +793,8 @@ static inline NvU64 kgspGetPrescrubbedTopFbSize_e1e623(struct OBJGPU *pGpu, stru return 256 * 1024 * 1024; } -static inline NvU64 kgspGetPrescrubbedTopFbSize_dd2c0b(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return (NvU64)(-1); +static inline NvU64 kgspGetPrescrubbedTopFbSize_604eb7(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (+18446744073709551615ULL); } static inline NvU64 kgspGetPrescrubbedTopFbSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { @@ -858,16 +917,28 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_DISPATCH return pKernelGsp->__kgspGetBinArchiveBooterUnloadUcode__(pKernelGsp); } -static inline NvU64 kgspGetWprHeapSize_45a5e0(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return (64U << 20); +static inline NvU64 kgspGetMinWprHeapSizeMB_7185bf(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (64U); } -static inline NvU64 kgspGetWprHeapSize_31541f(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pGpu->bVgpuGspPluginOffloadEnabled ? (549U << 20) : (84U << 20); +static inline NvU64 kgspGetMinWprHeapSizeMB_907c84(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pGpu->bVgpuGspPluginOffloadEnabled ? (549U) : (84U); } -static inline NvU64 kgspGetWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspGetWprHeapSize__(pGpu, pKernelGsp); +static inline NvU64 kgspGetMinWprHeapSizeMB_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetMinWprHeapSizeMB__(pGpu, pKernelGsp); +} + +static inline NvU64 kgspGetMaxWprHeapSizeMB_ad4e6a(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (256U); +} + +static inline NvU64 kgspGetMaxWprHeapSizeMB_5839e2(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pGpu->bVgpuGspPluginOffloadEnabled ? (1024U) : (276U); +} + +static inline NvU64 kgspGetMaxWprHeapSizeMB_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetMaxWprHeapSizeMB__(pGpu, pKernelGsp); } static inline NV_STATUS kgspInitVgpuPartitionLogging_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize) { @@ -1027,6 +1098,17 @@ static inline NV_STATUS kgspPrepareBootBinaryImage(struct OBJGPU *pGpu, struct K #define kgspPrepareBootBinaryImage(pGpu, pKernelGsp) kgspPrepareBootBinaryImage_IMPL(pGpu, pKernelGsp) #endif //__nvoc_kernel_gsp_h_disabled +NvU64 kgspGetFwHeapSize_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU64 posteriorFbSize); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NvU64 kgspGetFwHeapSize(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU64 posteriorFbSize) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return 0; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspGetFwHeapSize(pGpu, pKernelGsp, posteriorFbSize) kgspGetFwHeapSize_IMPL(pGpu, pKernelGsp, posteriorFbSize) +#endif //__nvoc_kernel_gsp_h_disabled + void kgspSetupLibosInitArgs_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -1058,17 +1140,6 @@ static inline NV_STATUS kgspWaitForRmInitDone(struct OBJGPU *pGpu, struct Kernel #define kgspWaitForRmInitDone(pGpu, pKernelGsp) kgspWaitForRmInitDone_IMPL(pGpu, pKernelGsp) #endif //__nvoc_kernel_gsp_h_disabled -NV_STATUS kgspInitLogging_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspInitLogging(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspInitLogging(pGpu, pKernelGsp, pGspFw) kgspInitLogging_IMPL(pGpu, pKernelGsp, pGspFw) -#endif //__nvoc_kernel_gsp_h_disabled - NV_STATUS kgspStartLogPolling_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -1151,7 +1222,7 @@ static inline NV_STATUS kgspAllocateBooterUnloadUcodeImage(struct OBJGPU *pGpu, NV_STATUS rpcRmApiControl_GSP(RM_API *pRmApi, NvHandle hClient, NvHandle hObject, NvU32 cmd, void *pParamStructPtr, NvU32 paramsSize); NV_STATUS rpcRmApiAlloc_GSP(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle hObject, NvU32 hClass, void *pAllocParams); + NvHandle hObject, NvU32 hClass, void *pAllocParams, NvU32 allocParamsSize); NV_STATUS rpcRmApiDupObject_GSP(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, NvHandle *phObject, NvHandle hClientSrc, NvHandle hObjectSrc, NvU32 flags); NV_STATUS rpcRmApiFree_GSP(RM_API *pRmApi, NvHandle hClient, NvHandle hObject); diff --git a/src/nvidia/generated/g_kernel_head_nvoc.c b/src/nvidia/generated/g_kernel_head_nvoc.c index 7ede9a947b..dbb37ed281 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.c +++ b/src/nvidia/generated/g_kernel_head_nvoc.c @@ -74,12 +74,16 @@ void __nvoc_init_dataField_KernelHead(KernelHead *pThis, RmHalspecOwner *pRmhals const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + DispIpHal *dispIpHal = &pRmhalspecowner->dispIpHal; + const unsigned long dispIpHal_HalVarIdx = (unsigned long)dispIpHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(dispIpHal); + PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); } NV_STATUS __nvoc_ctor_Object(Object* ); @@ -106,63 +110,93 @@ static void __nvoc_init_funcTable_KernelHead_1(KernelHead *pThis, RmHalspecOwner const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + DispIpHal *dispIpHal = &pRmhalspecowner->dispIpHal; + const unsigned long dispIpHal_HalVarIdx = (unsigned long)dispIpHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(dispIpHal); + PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); + + // Hal function -- kheadReadVblankIntrEnable + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadReadVblankIntrEnable__ = &kheadReadVblankIntrEnable_KERNEL; + } + // default + else + { + pThis->__kheadReadVblankIntrEnable__ = &kheadReadVblankIntrEnable_108313; + } + + // Hal function -- kheadGetDisplayInitialized + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadGetDisplayInitialized__ = &kheadGetDisplayInitialized_KERNEL; + } + // default + else + { + pThis->__kheadGetDisplayInitialized__ = &kheadGetDisplayInitialized_108313; + } + + // Hal function -- kheadWriteVblankIntrEnable + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadWriteVblankIntrEnable__ = &kheadWriteVblankIntrEnable_KERNEL; + } + // default + else + { + pThis->__kheadWriteVblankIntrEnable__ = &kheadWriteVblankIntrEnable_e426af; + } // Hal function -- kheadProcessVblankCallbacks - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_IMPL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_e426af; - } + pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_IMPL; + } + // default + else + { + pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_e426af; } // Hal function -- kheadResetPendingVblank - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_v04_00_KERNEL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_e426af; - } + pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_KERNEL; } - - // Hal function -- kheadResetPendingVblankForKernel - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_8305c4; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_e426af; - } + pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_e426af; } // Hal function -- kheadReadPendingVblank - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_KERNEL; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_v04_00_KERNEL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_92bfc3; - } + pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_108313; } } diff --git a/src/nvidia/generated/g_kernel_head_nvoc.h b/src/nvidia/generated/g_kernel_head_nvoc.h index 6a35b4e9c0..ebb1e67350 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.h +++ b/src/nvidia/generated/g_kernel_head_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,15 +41,10 @@ extern "C" { #define KERNEL_HEAD_H /* ------------------------ Includes --------------------------------------- */ +#include "gpu/eng_state.h" #include "gpu/disp/vblank_callback/vblank.h" #include "gpu/gpu_halspec.h" /* ------------------------ Types definitions ------------------------------ */ -enum -{ - headIntr_none = 0, - headIntr_vblank = NVBIT(0), -}; - /* ------------------------ Macros & Defines ------------------------------- */ #ifdef NVOC_KERNEL_HEAD_H_PRIVATE_ACCESS_ALLOWED @@ -76,10 +71,12 @@ struct KernelHead { struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct KernelHead *__nvoc_pbase_KernelHead; + NvBool (*__kheadReadVblankIntrEnable__)(struct OBJGPU *, struct KernelHead *); + NvBool (*__kheadGetDisplayInitialized__)(struct OBJGPU *, struct KernelHead *); + void (*__kheadWriteVblankIntrEnable__)(struct OBJGPU *, struct KernelHead *, NvBool); void (*__kheadProcessVblankCallbacks__)(struct OBJGPU *, struct KernelHead *, NvU32); void (*__kheadResetPendingVblank__)(struct OBJGPU *, struct KernelHead *, THREAD_STATE_NODE *); - void (*__kheadResetPendingVblankForKernel__)(struct OBJGPU *, struct KernelHead *, THREAD_STATE_NODE *); - NvU32 (*__kheadReadPendingVblank__)(struct OBJGPU *, struct KernelHead *, NvU32); + NvBool (*__kheadReadPendingVblank__)(struct OBJGPU *, struct KernelHead *, NvU32 *, THREAD_STATE_NODE *); struct __nvoc_inner_struc_KernelHead_1__ Vblank; NvU32 PublicId; }; @@ -112,14 +109,18 @@ NV_STATUS __nvoc_objCreate_KernelHead(KernelHead**, Dynamic*, NvU32); #define __objCreate_KernelHead(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_KernelHead((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) +#define kheadReadVblankIntrEnable(pGpu, pKernelHead) kheadReadVblankIntrEnable_DISPATCH(pGpu, pKernelHead) +#define kheadReadVblankIntrEnable_HAL(pGpu, pKernelHead) kheadReadVblankIntrEnable_DISPATCH(pGpu, pKernelHead) +#define kheadGetDisplayInitialized(pGpu, pKernelHead) kheadGetDisplayInitialized_DISPATCH(pGpu, pKernelHead) +#define kheadGetDisplayInitialized_HAL(pGpu, pKernelHead) kheadGetDisplayInitialized_DISPATCH(pGpu, pKernelHead) +#define kheadWriteVblankIntrEnable(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable_DISPATCH(pGpu, pKernelHead, arg0) +#define kheadWriteVblankIntrEnable_HAL(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable_DISPATCH(pGpu, pKernelHead, arg0) #define kheadProcessVblankCallbacks(pGpu, pKernelHead, arg0) kheadProcessVblankCallbacks_DISPATCH(pGpu, pKernelHead, arg0) #define kheadProcessVblankCallbacks_HAL(pGpu, pKernelHead, arg0) kheadProcessVblankCallbacks_DISPATCH(pGpu, pKernelHead, arg0) #define kheadResetPendingVblank(pGpu, pKernelHead, arg0) kheadResetPendingVblank_DISPATCH(pGpu, pKernelHead, arg0) #define kheadResetPendingVblank_HAL(pGpu, pKernelHead, arg0) kheadResetPendingVblank_DISPATCH(pGpu, pKernelHead, arg0) -#define kheadResetPendingVblankForKernel(pGpu, pKernelHead, pThreadState) kheadResetPendingVblankForKernel_DISPATCH(pGpu, pKernelHead, pThreadState) -#define kheadResetPendingVblankForKernel_HAL(pGpu, pKernelHead, pThreadState) kheadResetPendingVblankForKernel_DISPATCH(pGpu, pKernelHead, pThreadState) -#define kheadReadPendingVblank(pGpu, pKernelHead, intr) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, intr) -#define kheadReadPendingVblank_HAL(pGpu, pKernelHead, intr) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, intr) +#define kheadReadPendingVblank(pGpu, pKernelHead, pCachedIntr, pThreadState) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, pCachedIntr, pThreadState) +#define kheadReadPendingVblank_HAL(pGpu, pKernelHead, pCachedIntr, pThreadState) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, pCachedIntr, pThreadState) NvU32 kheadGetVblankTotalCounter_IMPL(struct KernelHead *pKernelHead); @@ -205,52 +206,45 @@ static inline void kheadSetVblankNormLatencyCounter(struct KernelHead *pKernelHe #define kheadSetVblankNormLatencyCounter_HAL(pKernelHead, arg0) kheadSetVblankNormLatencyCounter(pKernelHead, arg0) -static inline NvBool kheadReadVblankIntrEnable_491d52(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { - return ((NvBool)(0 != 0)); -} - +NvBool kheadReadVblankIntrEnable_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); -#ifdef __nvoc_kernel_head_h_disabled -static inline NvBool kheadReadVblankIntrEnable(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { - NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); - return NV_FALSE; +static inline NvBool kheadReadVblankIntrEnable_108313(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); } -#else //__nvoc_kernel_head_h_disabled -#define kheadReadVblankIntrEnable(pGpu, pKernelHead) kheadReadVblankIntrEnable_491d52(pGpu, pKernelHead) -#endif //__nvoc_kernel_head_h_disabled -#define kheadReadVblankIntrEnable_HAL(pGpu, pKernelHead) kheadReadVblankIntrEnable(pGpu, pKernelHead) +NvBool kheadReadVblankIntrEnable_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); -static inline NvBool kheadGetDisplayInitialized_491d52(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { +static inline NvBool kheadReadVblankIntrEnable_ceaee8(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + NV_ASSERT_PRECOMP(0); return ((NvBool)(0 != 0)); } +static inline NvBool kheadReadVblankIntrEnable_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + return pKernelHead->__kheadReadVblankIntrEnable__(pGpu, pKernelHead); +} -#ifdef __nvoc_kernel_head_h_disabled -static inline NvBool kheadGetDisplayInitialized(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { - NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); - return NV_FALSE; +NvBool kheadGetDisplayInitialized_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); + +static inline NvBool kheadGetDisplayInitialized_108313(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + +static inline NvBool kheadGetDisplayInitialized_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + return pKernelHead->__kheadGetDisplayInitialized__(pGpu, pKernelHead); } -#else //__nvoc_kernel_head_h_disabled -#define kheadGetDisplayInitialized(pGpu, pKernelHead) kheadGetDisplayInitialized_491d52(pGpu, pKernelHead) -#endif //__nvoc_kernel_head_h_disabled -#define kheadGetDisplayInitialized_HAL(pGpu, pKernelHead) kheadGetDisplayInitialized(pGpu, pKernelHead) +void kheadWriteVblankIntrEnable_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0); -static inline void kheadWriteVblankIntrEnable_b3696a(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { +static inline void kheadWriteVblankIntrEnable_e426af(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { + NV_ASSERT_PRECOMP(0); return; } +void kheadWriteVblankIntrEnable_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0); -#ifdef __nvoc_kernel_head_h_disabled -static inline void kheadWriteVblankIntrEnable(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); +static inline void kheadWriteVblankIntrEnable_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { + pKernelHead->__kheadWriteVblankIntrEnable__(pGpu, pKernelHead, arg0); } -#else //__nvoc_kernel_head_h_disabled -#define kheadWriteVblankIntrEnable(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable_b3696a(pGpu, pKernelHead, arg0) -#endif //__nvoc_kernel_head_h_disabled - -#define kheadWriteVblankIntrEnable_HAL(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable(pGpu, pKernelHead, arg0) void kheadProcessVblankCallbacks_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0); @@ -263,39 +257,40 @@ static inline void kheadProcessVblankCallbacks_DISPATCH(struct OBJGPU *pGpu, str pKernelHead->__kheadProcessVblankCallbacks__(pGpu, pKernelHead, arg0); } -void kheadResetPendingVblank_v04_00_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0); +void kheadResetPendingVblank_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0); static inline void kheadResetPendingVblank_e426af(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0) { NV_ASSERT_PRECOMP(0); return; } -static inline void kheadResetPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0) { - pKernelHead->__kheadResetPendingVblank__(pGpu, pKernelHead, arg0); -} +void kheadResetPendingVblank_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0); -static inline void kheadResetPendingVblankForKernel_8305c4(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) { - kheadResetPendingVblank(pGpu, pKernelHead, pThreadState); -} +void kheadResetPendingVblank_v04_01(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0); -static inline void kheadResetPendingVblankForKernel_e426af(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) { +static inline void kheadResetPendingVblank_f2d351(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0) { NV_ASSERT_PRECOMP(0); - return; } -static inline void kheadResetPendingVblankForKernel_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) { - pKernelHead->__kheadResetPendingVblankForKernel__(pGpu, pKernelHead, pThreadState); +static inline void kheadResetPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, THREAD_STATE_NODE *arg0) { + pKernelHead->__kheadResetPendingVblank__(pGpu, pKernelHead, arg0); } -NvU32 kheadReadPendingVblank_v04_00_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 intr); +NvBool kheadReadPendingVblank_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState); -static inline NvU32 kheadReadPendingVblank_92bfc3(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 intr) { +static inline NvBool kheadReadPendingVblank_108313(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + +NvBool kheadReadPendingVblank_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState); + +static inline NvBool kheadReadPendingVblank_ceaee8(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState) { NV_ASSERT_PRECOMP(0); - return NV_ERR_NOT_SUPPORTED; + return ((NvBool)(0 != 0)); } -static inline NvU32 kheadReadPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 intr) { - return pKernelHead->__kheadReadPendingVblank__(pGpu, pKernelHead, intr); +static inline NvBool kheadReadPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState) { + return pKernelHead->__kheadReadPendingVblank__(pGpu, pKernelHead, pCachedIntr, pThreadState); } NV_STATUS kheadConstruct_IMPL(struct KernelHead *arg_pKernelHead); diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c index 7f6a2f662f..f8d230b209 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c @@ -510,45 +510,30 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelHo #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL, + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, /*accessRight=*/0x0u, - /*methodId=*/ 0xa0840108u, - /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS), + /*methodId=*/ 0xa084010au, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetSriovState" + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges" #endif }, { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL, + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, /*accessRight=*/0x0u, - /*methodId=*/ 0xa0840109u, - /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS), + /*methodId=*/ 0xa084010bu, + /*paramSize=*/ 0, /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetGuestId" -#endif - }, - { /* [9] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, - /*accessRight=*/0x0u, - /*methodId=*/ 0xa084010au, - /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges" + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition" #endif }, @@ -556,7 +541,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelHo const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHostVgpuDeviceApi = { - /*numEntries=*/ 10, + /*numEntries=*/ 9, /*pExportEntries=*/ __nvoc_exported_method_def_KernelHostVgpuDeviceApi }; @@ -631,15 +616,11 @@ static void __nvoc_init_funcTable_KernelHostVgpuDeviceApi_1(KernelHostVgpuDevice #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__kernelhostvgpudeviceapiCtrlCmdSetSriovState__ = &kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__kernelhostvgpudeviceapiCtrlCmdSetGuestId__ = &kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL; + pThis->__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__ = &kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__ = &kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL; + pThis->__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__ = &kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL; #endif pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_KernelHostVgpuDeviceApi_resCanCopy; diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h index f27b6ff19a..7ca99754c9 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -119,9 +119,8 @@ struct KernelHostVgpuDeviceApi { NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *); - NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetSriovState__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *); - NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetGuestId__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__)(struct KernelHostVgpuDeviceApi *); NvBool (*__kernelhostvgpudeviceapiShareCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__kernelhostvgpudeviceapiCheckMemInterUnmap__)(struct KernelHostVgpuDeviceApi *, NvBool); NV_STATUS (*__kernelhostvgpudeviceapiGetOrAllocNotifShare__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, struct NotifShare **); @@ -191,9 +190,8 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi**, Dy #define kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiCtrlCmdEventSetNotification(pKernelHostVgpuDeviceApi, pSetEventParams) kernelhostvgpudeviceapiCtrlCmdEventSetNotification_DISPATCH(pKernelHostVgpuDeviceApi, pSetEventParams) -#define kernelhostvgpudeviceapiCtrlCmdSetSriovState(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetSriovState_DISPATCH(pKernelHostVgpuDeviceApi, pParams) -#define kernelhostvgpudeviceapiCtrlCmdSetGuestId(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetGuestId_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition(pKernelHostVgpuDeviceApi) kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_DISPATCH(pKernelHostVgpuDeviceApi) #define kernelhostvgpudeviceapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kernelhostvgpudeviceapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define kernelhostvgpudeviceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define kernelhostvgpudeviceapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) @@ -271,24 +269,18 @@ static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdEventSetNotification_DISPA return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__(pKernelHostVgpuDeviceApi, pSetEventParams); } -NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pParams); - -static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetSriovState_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pParams) { - return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetSriovState__(pKernelHostVgpuDeviceApi, pParams); -} - -NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams); - -static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetGuestId_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams) { - return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetGuestId__(pKernelHostVgpuDeviceApi, pParams); -} - NV_STATUS kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams); static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams) { return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__(pKernelHostVgpuDeviceApi, pParams); } +NV_STATUS kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__(pKernelHostVgpuDeviceApi); +} + static inline NvBool kernelhostvgpudeviceapiShareCallback_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__kernelhostvgpudeviceapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c index 479c618817..4f2704ad00 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c @@ -193,29 +193,23 @@ static void __nvoc_init_funcTable_KernelIoctrl_1(KernelIoctrl *pThis, RmHalspecO pThis->__kioctrlConstructEngine__ = &kioctrlConstructEngine_IMPL; // Hal function -- kioctrlGetMinionEnableDefault - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_bf6dfa; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_bf6dfa; - } + pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_GV100; } // Hal function -- kioctrlMinionConstruct - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_ac1694; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_ac1694; - } + pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_GV100; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelIoctrl_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h index f133e3be14..a7bb372a38 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,7 +47,7 @@ extern "C" { /*! * KernelIoctrl is a logical abstraction of the GPU Ioctrl Engine. The - * Public API of the Ioctrl Engine is exposed through this object, and + * Public API of the Ioctrl Engine is exposed through this object, and * any interfaces which do not manage the underlying Ioctrl hardware * can be managed by this object. */ @@ -81,13 +81,13 @@ struct KernelIoctrl { NvBool PDB_PROP_KIOCTRL_MINION_AVAILABLE; NvBool PDB_PROP_KIOCTRL_MINION_FORCE_BOOT; NvBool PDB_PROP_KIOCTRL_MINION_CACHE_SEEDS; - NvU32 PublicId; - NvU32 localDiscoveredLinks; - NvU32 localGlobalLinkOffset; - NvU32 ipVerIoctrl; - NvU32 ipVerMinion; - NvU32 ioctrlDiscoverySize; - NvU8 numDevices; + NvU32 PRIVATE_FIELD(PublicId); + NvU32 PRIVATE_FIELD(localDiscoveredLinks); + NvU32 PRIVATE_FIELD(localGlobalLinkOffset); + NvU32 PRIVATE_FIELD(ipVerIoctrl); + NvU32 PRIVATE_FIELD(ipVerMinion); + NvU32 PRIVATE_FIELD(ioctrlDiscoverySize); + NvU8 PRIVATE_FIELD(numDevices); }; #ifndef __NVOC_CLASS_KernelIoctrl_TYPEDEF__ diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.c b/src/nvidia/generated/g_kernel_mc_nvoc.c index e1053aa9f4..fd663fc2be 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.c +++ b/src/nvidia/generated/g_kernel_mc_nvoc.c @@ -174,7 +174,7 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GK104; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GA100; } @@ -184,7 +184,7 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GK104; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GA100; } diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.h b/src/nvidia/generated/g_kernel_mc_nvoc.h index 7961b3f295..c3232bcaeb 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.h +++ b/src/nvidia/generated/g_kernel_mc_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c index e18880a031..ec0e95cf9f 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c @@ -185,23 +185,20 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm { pThis->__kmigmgrCreateGPUInstanceCheck__ = &kmigmgrCreateGPUInstanceCheck_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kmigmgrCreateGPUInstanceCheck__ = &kmigmgrCreateGPUInstanceCheck_46f6a7; } // Hal function -- kmigmgrIsDevinitMIGBitSet - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_GA100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_GA100; - } - // default - else - { - pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_491d52; - } + pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_491d52; } // Hal function -- kmigmgrIsGPUInstanceCombinationValid @@ -239,7 +236,7 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm { pThis->__kmigmgrIsMemoryPartitioningRequested__ = &kmigmgrIsMemoryPartitioningRequested_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kmigmgrIsMemoryPartitioningRequested__ = &kmigmgrIsMemoryPartitioningRequested_491d52; } @@ -249,22 +246,19 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm { pThis->__kmigmgrIsMemoryPartitioningNeeded__ = &kmigmgrIsMemoryPartitioningNeeded_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__kmigmgrIsMemoryPartitioningNeeded__ = &kmigmgrIsMemoryPartitioningNeeded_491d52; } // Hal function -- kmigmgrMemSizeFlagToSwizzIdRange - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_GA100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; - } + pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMIGManager_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h index a4aa473b6e..560c2ceef6 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -56,13 +56,13 @@ typedef struct MIG_GPU_INSTANCE MIG_GPU_INSTANCE; #define IS_MIG_IN_USE(pGpu) (((pGpu) != NULL) && (GPU_GET_KERNEL_MIG_MANAGER(pGpu) != NULL) && \ kmigmgrIsMIGGpuInstancingEnabled((pGpu), GPU_GET_KERNEL_MIG_MANAGER(pGpu))) -#define FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pLocal) \ - { \ - NvU32 i; \ - for (i = 0; i < KMIGMGR_MAX_GPU_INSTANCES; ++i) \ - { \ - (pLocal) = kmigmgrGetMIGGpuInstanceSlot((pGpu), (pKernelMIGManager), i);\ - if (((pLocal) == NULL) || !(pLocal)->bValid) \ +#define FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pLocal) \ + { \ + NvU32 i; \ + for (i = 0; i < KMIGMGR_MAX_GPU_INSTANCES; ++i) \ + { \ + (pLocal) = kmigmgrGetMIGGpuInstanceSlot((pGpu), (pKernelMIGManager), i); \ + if (((pLocal) == NULL) || !(pLocal)->bValid) \ continue; #define FOR_EACH_VALID_GPU_INSTANCE_END() \ @@ -79,7 +79,7 @@ typedef struct MIG_GPU_INSTANCE MIG_GPU_INSTANCE; #define KMIGMGR_CTSID_INVALID 0xFFFFFFFFUL #define KMIGMGR_SPAN_OFFSET_INVALID KMIGMGR_CTSID_INVALID -#define KMIGMGR_INSTANCE_ATTRIBUTION_ID_INVALID \ +#define KMIGMGR_INSTANCE_ATTRIBUTION_ID_INVALID \ ((KMIGMGR_MAX_GPU_SWIZZID * KMIGMGR_MAX_GPU_SWIZZID) + \ KMIGMGR_MAX_COMPUTE_INSTANCES) @@ -243,7 +243,7 @@ typedef struct MIG_COMPUTE_INSTANCE * instance ID support. (bug 2938187) * TYPE_REQUEST_AT_SPAN * Parameter refers to request data passed in via EXEC_PARTITIONS_CREATE ctrl - * call. All resources claimed by new instance are attempt to be claimed by + * call. All resources claimed by new instance are attempt to be claimed by * the RM allocater starting at the specified resource span. */ typedef struct KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS @@ -384,10 +384,10 @@ typedef struct KERNEL_MIG_GPU_INSTANCE * GR to CTS ID mapping */ NvU32 grCtsIdMap[KMIGMGR_MAX_COMPUTE_INSTANCES]; - + /*! * Mask tracking which compute spans are currently in-use - */ + */ NvU32 spanInUseMask; } KERNEL_MIG_GPU_INSTANCE; @@ -463,6 +463,44 @@ typedef struct KERNEL_MIG_MANAGER_STATIC_INFO #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif struct KernelMIGManager { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelMIGManager *__nvoc_pbase_KernelMIGManager; + NV_STATUS (*__kmigmgrConstructEngine__)(OBJGPU *, struct KernelMIGManager *, ENGDESCRIPTOR); + NV_STATUS (*__kmigmgrStateInitLocked__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStateUnload__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrCreateGPUInstanceCheck__)(OBJGPU *, struct KernelMIGManager *, NvBool); + NvBool (*__kmigmgrIsDevinitMIGBitSet__)(OBJGPU *, struct KernelMIGManager *); + NvBool (*__kmigmgrIsGPUInstanceCombinationValid__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NvBool (*__kmigmgrIsGPUInstanceFlagValid__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NvBool (*__kmigmgrIsMemoryPartitioningRequested__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NvBool (*__kmigmgrIsMemoryPartitioningNeeded__)(OBJGPU *, struct KernelMIGManager *, NvU32); + struct NV_RANGE (*__kmigmgrMemSizeFlagToSwizzIdRange__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrStateLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrStatePreLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrStatePostUnload__)(POBJGPU, struct KernelMIGManager *, NvU32); + void (*__kmigmgrStateDestroy__)(POBJGPU, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStatePreUnload__)(POBJGPU, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrStateInitUnlocked__)(POBJGPU, struct KernelMIGManager *); + void (*__kmigmgrInitMissing__)(POBJGPU, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStatePreInitLocked__)(POBJGPU, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStatePreInitUnlocked__)(POBJGPU, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrStatePostLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); + NvBool (*__kmigmgrIsPresent__)(POBJGPU, struct KernelMIGManager *); + NvBool PRIVATE_FIELD(bIsA100ReducedConfig); + KERNEL_MIG_MANAGER_PRIVATE_DATA *PRIVATE_FIELD(pPrivate); + KERNEL_MIG_GPU_INSTANCE PRIVATE_FIELD(kernelMIGGpuInstance)[8]; + NvBool PRIVATE_FIELD(bMIGEnabled); + NvU64 PRIVATE_FIELD(swizzIdInUseMask); + NvBool PRIVATE_FIELD(bRestoreWatchdog); + NvBool PRIVATE_FIELD(bReenableWatchdog); + union ENGTYPE_BIT_VECTOR PRIVATE_FIELD(partitionableEnginesInUse); + NvBool PRIVATE_FIELD(bDeviceProfilingInUse); + NvBool PRIVATE_FIELD(bMIGAutoOnlineEnabled); +}; +struct KernelMIGManager_PRIVATE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; struct Object *__nvoc_pbase_Object; @@ -878,11 +916,13 @@ static inline NvBool kmigmgrIsMIGNvlinkP2PSupportOverridden(OBJGPU *pGpu, struct } static inline const union ENGTYPE_BIT_VECTOR *kmigmgrGetPartitionableEnginesInUse(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { - return &pKernelMIGManager->partitionableEnginesInUse; + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + return &pKernelMIGManager_PRIVATE->partitionableEnginesInUse; } static inline NvBool kmigmgrIsA100ReducedConfig(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { - return pKernelMIGManager->bIsA100ReducedConfig; + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + return pKernelMIGManager_PRIVATE->bIsA100ReducedConfig; } NV_STATUS kmigmgrIncRefCount_IMPL(struct RsShared *arg0); @@ -918,9 +958,9 @@ NvU32 kmigmgrCountEnginesOfType_IMPL(const union ENGTYPE_BIT_VECTOR *arg0, RM_EN NvU16 kmigmgrGetAttributionIdFromMIGReference_IMPL(struct MIG_INSTANCE_REF arg0); #define kmigmgrGetAttributionIdFromMIGReference(arg0) kmigmgrGetAttributionIdFromMIGReference_IMPL(arg0) -NV_STATUS kmigmgrAllocateInstanceEngines_IMPL(union ENGTYPE_BIT_VECTOR *pSourceEngines, NvBool bShared, struct NV_RANGE engTypeRange, NvU32 reqEngCount, union ENGTYPE_BIT_VECTOR *pOutEngines, union ENGTYPE_BIT_VECTOR *pExclusiveEngines, union ENGTYPE_BIT_VECTOR *pSharedEngines); +NV_STATUS kmigmgrAllocateInstanceEngines_IMPL(union ENGTYPE_BIT_VECTOR *pSourceEngines, NvBool bShared, struct NV_RANGE engTypeRange, NvU32 reqEngCount, union ENGTYPE_BIT_VECTOR *pOutEngines, union ENGTYPE_BIT_VECTOR *pExclusiveEngines, union ENGTYPE_BIT_VECTOR *pSharedEngines, union ENGTYPE_BIT_VECTOR *pAllocatableEngines); -#define kmigmgrAllocateInstanceEngines(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines) kmigmgrAllocateInstanceEngines_IMPL(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines) +#define kmigmgrAllocateInstanceEngines(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines, pAllocatableEngines) kmigmgrAllocateInstanceEngines_IMPL(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines, pAllocatableEngines) void kmigmgrGetLocalEngineMask_IMPL(union ENGTYPE_BIT_VECTOR *pPhysicalEngineMask, union ENGTYPE_BIT_VECTOR *pLocalEngineMask); #define kmigmgrGetLocalEngineMask(pPhysicalEngineMask, pLocalEngineMask) kmigmgrGetLocalEngineMask_IMPL(pPhysicalEngineMask, pLocalEngineMask) @@ -1166,17 +1206,6 @@ static inline NvBool kmigmgrIsEngineInInstance(OBJGPU *arg0, struct KernelMIGMan #define kmigmgrIsEngineInInstance(arg0, arg1, globalRmEngType, arg2) kmigmgrIsEngineInInstance_IMPL(arg0, arg1, globalRmEngType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetFreeEngines_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineCount, struct NV_RANGE engineRange, union ENGTYPE_BIT_VECTOR *pInstanceEngines); - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetFreeEngines(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineCount, struct NV_RANGE engineRange, union ENGTYPE_BIT_VECTOR *pInstanceEngines) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetFreeEngines(arg0, arg1, engineCount, engineRange, pInstanceEngines) kmigmgrGetFreeEngines_IMPL(arg0, arg1, engineCount, engineRange, pInstanceEngines) -#endif //__nvoc_kernel_mig_manager_h_disabled - NV_STATUS kmigmgrCreateGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pSwizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, NvBool bValid, NvBool bCreateCap); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1367,70 +1396,70 @@ static inline NvBool kmigmgrIsClientUsingDeviceProfiling(OBJGPU *arg0, struct Ke #define kmigmgrIsClientUsingDeviceProfiling(arg0, arg1, hClient) kmigmgrIsClientUsingDeviceProfiling_IMPL(arg0, arg1, hClient) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrEnableAllLCEs_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bEnableAllLCEs); +NvBool kmigmgrIsDeviceUsingDeviceProfiling_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrEnableAllLCEs(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bEnableAllLCEs) { +static inline NvBool kmigmgrIsDeviceUsingDeviceProfiling(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return NV_FALSE; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrEnableAllLCEs(arg0, arg1, bEnableAllLCEs) kmigmgrEnableAllLCEs_IMPL(arg0, arg1, bEnableAllLCEs) +#define kmigmgrIsDeviceUsingDeviceProfiling(arg0, arg1, pDevice) kmigmgrIsDeviceUsingDeviceProfiling_IMPL(arg0, arg1, pDevice) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetInstanceRefFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvHandle hDevice, struct MIG_INSTANCE_REF *arg2); +NV_STATUS kmigmgrEnableAllLCEs_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bEnableAllLCEs); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetInstanceRefFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvHandle hDevice, struct MIG_INSTANCE_REF *arg2) { +static inline NV_STATUS kmigmgrEnableAllLCEs(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bEnableAllLCEs) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetInstanceRefFromDevice(arg0, arg1, hClient, hDevice, arg2) kmigmgrGetInstanceRefFromDevice_IMPL(arg0, arg1, hClient, hDevice, arg2) +#define kmigmgrEnableAllLCEs(arg0, arg1, bEnableAllLCEs) kmigmgrEnableAllLCEs_IMPL(arg0, arg1, bEnableAllLCEs) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetInstanceRefFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2); +NV_STATUS kmigmgrGetInstanceRefFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct MIG_INSTANCE_REF *arg3); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetInstanceRefFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2) { +static inline NV_STATUS kmigmgrGetInstanceRefFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct MIG_INSTANCE_REF *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetInstanceRefFromClient(arg0, arg1, hClient, arg2) kmigmgrGetInstanceRefFromClient_IMPL(arg0, arg1, hClient, arg2) +#define kmigmgrGetInstanceRefFromDevice(arg0, arg1, arg2, arg3) kmigmgrGetInstanceRefFromDevice_IMPL(arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvHandle hDevice, struct Heap **arg2); +NV_STATUS kmigmgrGetInstanceRefFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvHandle hDevice, struct Heap **arg2) { +static inline NV_STATUS kmigmgrGetInstanceRefFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetMemoryPartitionHeapFromDevice(arg0, arg1, hClient, hDevice, arg2) kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(arg0, arg1, hClient, hDevice, arg2) +#define kmigmgrGetInstanceRefFromClient(arg0, arg1, hClient, arg2) kmigmgrGetInstanceRefFromClient_IMPL(arg0, arg1, hClient, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetMemoryPartitionHeapFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct Heap **arg2); +NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct Heap **arg3); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct Heap **arg2) { +static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct Heap **arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetMemoryPartitionHeapFromClient(arg0, arg1, hClient, arg2) kmigmgrGetMemoryPartitionHeapFromClient_IMPL(arg0, arg1, hClient, arg2) +#define kmigmgrGetMemoryPartitionHeapFromDevice(arg0, arg1, arg2, arg3) kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetSwizzIdFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *pSwizzId); +NV_STATUS kmigmgrGetSwizzIdFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *pSwizzId); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetSwizzIdFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *pSwizzId) { +static inline NV_STATUS kmigmgrGetSwizzIdFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *pSwizzId) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetSwizzIdFromClient(arg0, arg1, hClient, pSwizzId) kmigmgrGetSwizzIdFromClient_IMPL(arg0, arg1, hClient, pSwizzId) +#define kmigmgrGetSwizzIdFromDevice(arg0, arg1, pDevice, pSwizzId) kmigmgrGetSwizzIdFromDevice_IMPL(arg0, arg1, pDevice, pSwizzId) #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrPrintGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); @@ -1553,15 +1582,15 @@ static inline NV_STATUS kmigmgrGetMIGReferenceFromEngineType(OBJGPU *arg0, struc #define kmigmgrGetMIGReferenceFromEngineType(arg0, arg1, rmEngineType, arg2) kmigmgrGetMIGReferenceFromEngineType_IMPL(arg0, arg1, rmEngineType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetGPUInstanceScrubberCe_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *ceInst); +NV_STATUS kmigmgrGetGPUInstanceScrubberCe_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *ceInst); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetGPUInstanceScrubberCe(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *ceInst) { +static inline NV_STATUS kmigmgrGetGPUInstanceScrubberCe(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *ceInst) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetGPUInstanceScrubberCe(arg0, arg1, hClient, ceInst) kmigmgrGetGPUInstanceScrubberCe_IMPL(arg0, arg1, hClient, ceInst) +#define kmigmgrGetGPUInstanceScrubberCe(arg0, arg1, pDevice, ceInst) kmigmgrGetGPUInstanceScrubberCe_IMPL(arg0, arg1, pDevice, ceInst) #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrDescribeGPUInstances_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS *arg2); @@ -1805,6 +1834,17 @@ static inline NvBool kmigmgrIsCTSIdAvailable(OBJGPU *arg0, struct KernelMIGManag #define kmigmgrIsCTSIdAvailable(arg0, arg1, ctsIdValidMask, ctsIdInUseMask, ctsId) kmigmgrIsCTSIdAvailable_IMPL(arg0, arg1, ctsIdValidMask, ctsIdInUseMask, ctsId) #endif //__nvoc_kernel_mig_manager_h_disabled +NV_STATUS kmigmgrUpdateCiConfigForVgpu_IMPL(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, NvU32 execPartCount, NvU32 *pExecPartId, NvU32 gfid, NvBool bDelete); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrUpdateCiConfigForVgpu(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, NvU32 execPartCount, NvU32 *pExecPartId, NvU32 gfid, NvBool bDelete) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrUpdateCiConfigForVgpu(pGpu, pKernelMIGManager, execPartCount, pExecPartId, gfid, bDelete) kmigmgrUpdateCiConfigForVgpu_IMPL(pGpu, pKernelMIGManager, execPartCount, pExecPartId, gfid, bDelete) +#endif //__nvoc_kernel_mig_manager_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.c b/src/nvidia/generated/g_kernel_nvlink_nvoc.c index 0803262a8b..db6ddeb170 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.c @@ -300,334 +300,283 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO pThis->__knvlinkIsPresent__ = &knvlinkIsPresent_IMPL; // Hal function -- knvlinkSetUniqueFabricBaseAddress - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GH100; - } - // default - else - { - pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_46f6a7; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GV100; + } + // default + else + { + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_46f6a7; + } + + // Hal function -- knvlinkClearUniqueFabricBaseAddress + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkClearUniqueFabricBaseAddress__ = &knvlinkClearUniqueFabricBaseAddress_GH100; + } + // default + else + { + pThis->__knvlinkClearUniqueFabricBaseAddress__ = &knvlinkClearUniqueFabricBaseAddress_b3696a; } // Hal function -- knvlinkHandleFaultUpInterrupt - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_GH100; + } + // default + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_GH100; - } - // default - else - { - pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_46f6a7; - } + pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_46f6a7; } // Hal function -- knvlinkValidateFabricBaseAddress - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GH100; - } - // default - else - { - pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_46f6a7; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GA100; + } + // default + else + { + pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_46f6a7; } // Hal function -- knvlinkGetConnectedLinksMask - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000380UL) )) /* ChipHal: TU106 | TU116 | TU117 | GH100 */ + { + pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_15a734; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000380UL) )) /* ChipHal: TU106 | TU116 | TU117 | GH100 */ - { - pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_15a734; - } + pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_TU102; } // Hal function -- knvlinkEnableLinksPostTopology - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_GV100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_56cd7a; - } + pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_56cd7a; } // Hal function -- knvlinkOverrideConfig - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_56cd7a; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GV100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_56cd7a; + } + else + { + pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GA100; } // Hal function -- knvlinkFilterBridgeLinks - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_46f6a7; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_46f6a7; - } + pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_TU102; } // Hal function -- knvlinkGetUniquePeerIdMask - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_GP100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_15a734; - } + pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_15a734; } // Hal function -- knvlinkGetUniquePeerId - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_c732fb; - } + pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_GP100; + } + else + { + pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_c732fb; } // Hal function -- knvlinkRemoveMapping - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_56cd7a; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_56cd7a; + } + else + { + pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GA100; } // Hal function -- knvlinkGetP2POptimalCEs - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_56cd7a; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_56cd7a; - } + pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_GP100; } // Hal function -- knvlinkConstructHal - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_56cd7a; - } + pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_56cd7a; + } + else + { + pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_GV100; } // Hal function -- knvlinkSetupPeerMapping - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_b3696a; - } + pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_b3696a; + } + else + { + pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_GP100; } // Hal function -- knvlinkProgramLinkSpeed - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_56cd7a; - } + pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_56cd7a; + } + else + { + pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_GV100; } // Hal function -- knvlinkPoweredUpForD3 - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_TU102; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_491d52; - } + pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_491d52; } // Hal function -- knvlinkIsAliSupported - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_56cd7a; - } + pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_56cd7a; } // Hal function -- knvlinkPostSetupNvlinkPeer - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_56cd7a; - } + pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_GH100; + } + else + { + pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_56cd7a; } // Hal function -- knvlinkDiscoverPostRxDetLinks - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_46f6a7; - } + pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_GH100; + } + else + { + pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_46f6a7; } // Hal function -- knvlinkLogAliDebugMessages - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_46f6a7; - } + pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_GH100; + } + else + { + pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_46f6a7; } // Hal function -- knvlinkGetEffectivePeerLinkMask - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkGetEffectivePeerLinkMask__ = &knvlinkGetEffectivePeerLinkMask_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkGetEffectivePeerLinkMask__ = &knvlinkGetEffectivePeerLinkMask_b3696a; - } + pThis->__knvlinkGetEffectivePeerLinkMask__ = &knvlinkGetEffectivePeerLinkMask_GH100; + } + else + { + pThis->__knvlinkGetEffectivePeerLinkMask__ = &knvlinkGetEffectivePeerLinkMask_b3696a; } // Hal function -- knvlinkGetNumLinksToBeReducedPerIoctrl - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkGetNumLinksToBeReducedPerIoctrl__ = &knvlinkGetNumLinksToBeReducedPerIoctrl_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkGetNumLinksToBeReducedPerIoctrl__ = &knvlinkGetNumLinksToBeReducedPerIoctrl_4a4dee; - } + pThis->__knvlinkGetNumLinksToBeReducedPerIoctrl__ = &knvlinkGetNumLinksToBeReducedPerIoctrl_GH100; + } + else + { + pThis->__knvlinkGetNumLinksToBeReducedPerIoctrl__ = &knvlinkGetNumLinksToBeReducedPerIoctrl_4a4dee; } // Hal function -- knvlinkIsBandwidthModeOff - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsBandwidthModeOff__ = &knvlinkIsBandwidthModeOff_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkIsBandwidthModeOff__ = &knvlinkIsBandwidthModeOff_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkIsBandwidthModeOff__ = &knvlinkIsBandwidthModeOff_491d52; - } + pThis->__knvlinkIsBandwidthModeOff__ = &knvlinkIsBandwidthModeOff_491d52; } // Hal function -- knvlinkDirectConnectCheck - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkDirectConnectCheck__ = &knvlinkDirectConnectCheck_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkDirectConnectCheck__ = &knvlinkDirectConnectCheck_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkDirectConnectCheck__ = &knvlinkDirectConnectCheck_b3696a; - } + pThis->__knvlinkDirectConnectCheck__ = &knvlinkDirectConnectCheck_b3696a; + } + + // Hal function -- knvlinkIsGpuReducedNvlinkConfig + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__knvlinkIsGpuReducedNvlinkConfig__ = &knvlinkIsGpuReducedNvlinkConfig_GA100; + } + else + { + pThis->__knvlinkIsGpuReducedNvlinkConfig__ = &knvlinkIsGpuReducedNvlinkConfig_491d52; } // Hal function -- knvlinkIsFloorSweepingNeeded - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_491d52; - } + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_GH100; + } + else + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_491d52; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelNvlink_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.h b/src/nvidia/generated/g_kernel_nvlink_nvoc.h index 81acbb097c..4b181b5b5f 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,6 +81,7 @@ typedef struct _def_knvlink_conn_info #define NVLINK_VERSION_30 0x00000005 #define NVLINK_VERSION_31 0x00000006 #define NVLINK_VERSION_40 0x00000007 +#define NVLINK_VERSION_50 0x00000008 // Maximum links the GPU NVLink SW can currently support #define NVLINK_MAX_LINKS_SW 18 @@ -190,7 +191,7 @@ typedef struct _def_knvlink_link typedef struct NVLINK_INBAND_CALLBACK { NvU32 messageType; - void (*pCallback)(NvU32 gpuInstance, + NV_STATUS (*pCallback)(NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); NvU32 wqItemFlags; } NVLINK_INBAND_MSG_CALLBACK; @@ -227,6 +228,7 @@ struct KernelNvlink { NV_STATUS (*__knvlinkStatePostUnload__)(OBJGPU *, struct KernelNvlink *, NvU32); NvBool (*__knvlinkIsPresent__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); + void (*__knvlinkClearUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkHandleFaultUpInterrupt__)(OBJGPU *, struct KernelNvlink *, NvU32); NV_STATUS (*__knvlinkValidateFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); NvU32 (*__knvlinkGetConnectedLinksMask__)(OBJGPU *, struct KernelNvlink *); @@ -249,6 +251,7 @@ struct KernelNvlink { NvU32 (*__knvlinkGetNumLinksToBeReducedPerIoctrl__)(struct KernelNvlink *); NvBool (*__knvlinkIsBandwidthModeOff__)(struct KernelNvlink *); void (*__knvlinkDirectConnectCheck__)(OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkIsGpuReducedNvlinkConfig__)(OBJGPU *, struct KernelNvlink *); NvBool (*__knvlinkIsFloorSweepingNeeded__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32); NV_STATUS (*__knvlinkStateInitLocked__)(POBJGPU, struct KernelNvlink *); NV_STATUS (*__knvlinkStatePreLoad__)(POBJGPU, struct KernelNvlink *, NvU32); @@ -271,53 +274,53 @@ struct KernelNvlink { NvBool PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING; NvBool PDB_PROP_KNVLINK_MINION_GFW_BOOT; NvBool PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED; - struct KernelIoctrl *pKernelIoctrl[3]; - NvU32 ioctrlMask; - NvU32 ipVerNvlink; - NvU8 ioctrlNumEntries; - NvU32 ioctrlSize; - NvU32 registryControl; - NvU32 minionControl; - NvU32 verboseMask; - NvU32 *pLinkConnection; - NvBool bChiplibConfig; - NvBool bRegistryLinkOverride; - NvU32 registryLinkMask; - NvBool bOverrideComputePeerMode; - NvU32 discoveredLinks; - NvU32 vbiosDisabledLinkMask; - NvU32 regkeyDisabledLinksMask; - NvU32 initDisabledLinksMask; - NvU32 connectedLinksMask; - NvU32 bridgeSensableLinks; - NvU32 bridgedLinks; - NvU32 enabledLinks; - FaultUpList faultUpLinks; - NvU32 initializedLinks; - KNVLINK_RM_LINK nvlinkLinks[18]; - NvBool bIsGpuDegraded; - NvU32 postRxDetLinkMask; - NvU32 disconnectedLinkMask; - NvU32 sysmemLinkMask; - NvU32 peerLinkMasks[32]; - NvU32 forcedSysmemDeviceType; - NVLINK_INBAND_MSG_CALLBACK inbandCallback[5]; - nvlink_device *pNvlinkDev; - NvU32 deviceLockRefcount; - NvBool bVerifTrainingEnable; - NvBool bL2Entry; - NvBool bSkipLinkTraining; - NvBool bForceAutoconfig; - NvBool bForceEnableCoreLibRtlsims; - NvBool bEnableTrainingAtLoad; - NvBool bEnableSafeModeAtLoad; - NvBool bEnableAli; - NvBool bFloorSwept; - NvBool bLinkTrainingDebugSpew; - NvBool bDisableL2Mode; - NvU32 nvlinkLinkSpeed; - NvU32 errorRecoveries[18]; - NvBool bNvswitchProxy; + struct KernelIoctrl *PRIVATE_FIELD(pKernelIoctrl)[3]; + NvU32 PRIVATE_FIELD(ioctrlMask); + NvU32 PRIVATE_FIELD(ipVerNvlink); + NvU8 PRIVATE_FIELD(ioctrlNumEntries); + NvU32 PRIVATE_FIELD(ioctrlSize); + NvU32 PRIVATE_FIELD(registryControl); + NvU32 PRIVATE_FIELD(minionControl); + NvU32 PRIVATE_FIELD(verboseMask); + NvU32 *PRIVATE_FIELD(pLinkConnection); + NvBool PRIVATE_FIELD(bChiplibConfig); + NvBool PRIVATE_FIELD(bRegistryLinkOverride); + NvU32 PRIVATE_FIELD(registryLinkMask); + NvBool PRIVATE_FIELD(bOverrideComputePeerMode); + NvU32 PRIVATE_FIELD(discoveredLinks); + NvU32 PRIVATE_FIELD(vbiosDisabledLinkMask); + NvU32 PRIVATE_FIELD(regkeyDisabledLinksMask); + NvU32 PRIVATE_FIELD(initDisabledLinksMask); + NvU32 PRIVATE_FIELD(connectedLinksMask); + NvU32 PRIVATE_FIELD(bridgeSensableLinks); + NvU32 PRIVATE_FIELD(bridgedLinks); + NvU32 PRIVATE_FIELD(enabledLinks); + FaultUpList PRIVATE_FIELD(faultUpLinks); + NvU32 PRIVATE_FIELD(initializedLinks); + KNVLINK_RM_LINK PRIVATE_FIELD(nvlinkLinks)[18]; + NvBool PRIVATE_FIELD(bIsGpuDegraded); + NvU32 PRIVATE_FIELD(postRxDetLinkMask); + NvU32 PRIVATE_FIELD(disconnectedLinkMask); + NvU32 PRIVATE_FIELD(sysmemLinkMask); + NvU32 PRIVATE_FIELD(peerLinkMasks)[32]; + NvU32 PRIVATE_FIELD(forcedSysmemDeviceType); + NVLINK_INBAND_MSG_CALLBACK PRIVATE_FIELD(inbandCallback)[5]; + nvlink_device *PRIVATE_FIELD(pNvlinkDev); + NvU32 PRIVATE_FIELD(deviceLockRefcount); + NvBool PRIVATE_FIELD(bVerifTrainingEnable); + NvBool PRIVATE_FIELD(bL2Entry); + NvBool PRIVATE_FIELD(bSkipLinkTraining); + NvBool PRIVATE_FIELD(bForceAutoconfig); + NvBool PRIVATE_FIELD(bForceEnableCoreLibRtlsims); + NvBool PRIVATE_FIELD(bEnableTrainingAtLoad); + NvBool PRIVATE_FIELD(bEnableSafeModeAtLoad); + NvBool PRIVATE_FIELD(bEnableAli); + NvBool PRIVATE_FIELD(bFloorSwept); + NvBool PRIVATE_FIELD(bLinkTrainingDebugSpew); + NvBool PRIVATE_FIELD(bDisableL2Mode); + NvU32 PRIVATE_FIELD(nvlinkLinkSpeed); + NvU32 PRIVATE_FIELD(errorRecoveries)[18]; + NvBool PRIVATE_FIELD(bNvswitchProxy); NvU64 fabricBaseAddr; }; @@ -388,6 +391,8 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkIsPresent(arg0, arg1) knvlinkIsPresent_DISPATCH(arg0, arg1) #define knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) +#define knvlinkClearUniqueFabricBaseAddress(pGpu, pKernelNvlink) knvlinkClearUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkClearUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink) knvlinkClearUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink) #define knvlinkHandleFaultUpInterrupt(pGpu, pKernelNvlink, arg0) knvlinkHandleFaultUpInterrupt_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkHandleFaultUpInterrupt_HAL(pGpu, pKernelNvlink, arg0) knvlinkHandleFaultUpInterrupt_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkValidateFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkValidateFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) @@ -432,6 +437,8 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkIsBandwidthModeOff_HAL(pKernelNvlink) knvlinkIsBandwidthModeOff_DISPATCH(pKernelNvlink) #define knvlinkDirectConnectCheck(pGpu, pKernelNvlink) knvlinkDirectConnectCheck_DISPATCH(pGpu, pKernelNvlink) #define knvlinkDirectConnectCheck_HAL(pGpu, pKernelNvlink) knvlinkDirectConnectCheck_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkIsGpuReducedNvlinkConfig(pGpu, pKernelNvlink) knvlinkIsGpuReducedNvlinkConfig_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkIsGpuReducedNvlinkConfig_HAL(pGpu, pKernelNvlink) knvlinkIsGpuReducedNvlinkConfig_DISPATCH(pGpu, pKernelNvlink) #define knvlinkIsFloorSweepingNeeded(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) #define knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) #define knvlinkStateInitLocked(pGpu, pEngstate) knvlinkStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -1360,6 +1367,16 @@ static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_DISPATCH(OBJGPU *pGpu, return pKernelNvlink->__knvlinkSetUniqueFabricBaseAddress__(pGpu, pKernelNvlink, arg0); } +static inline void knvlinkClearUniqueFabricBaseAddress_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return; +} + +void knvlinkClearUniqueFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + +static inline void knvlinkClearUniqueFabricBaseAddress_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + pKernelNvlink->__knvlinkClearUniqueFabricBaseAddress__(pGpu, pKernelNvlink); +} + NV_STATUS knvlinkHandleFaultUpInterrupt_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); static inline NV_STATUS knvlinkHandleFaultUpInterrupt_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { @@ -1586,6 +1603,16 @@ static inline void knvlinkDirectConnectCheck_DISPATCH(OBJGPU *pGpu, struct Kerne pKernelNvlink->__knvlinkDirectConnectCheck__(pGpu, pKernelNvlink); } +static inline NvBool knvlinkIsGpuReducedNvlinkConfig_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return ((NvBool)(0 != 0)); +} + +NvBool knvlinkIsGpuReducedNvlinkConfig_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + +static inline NvBool knvlinkIsGpuReducedNvlinkConfig_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkIsGpuReducedNvlinkConfig__(pGpu, pKernelNvlink); +} + static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { return ((NvBool)(0 != 0)); } diff --git a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h index fca8739889..3bb156abd5 100644 --- a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h +++ b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -104,6 +104,10 @@ static inline NvU32 kschedmgrGetSchedPolicy(struct KernelSchedMgr *pKernelSchedM return pKernelSchedMgr->configSchedPolicy; } +static inline NvBool kschedmgrIsPvmrlEnabled(struct KernelSchedMgr *pKernelSchedMgr) { + return ((NvBool)(0 != 0)); +} + void kschedmgrConstructPolicy_IMPL(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu); #ifdef __nvoc_kernel_sched_mgr_h_disabled @@ -114,6 +118,16 @@ static inline void kschedmgrConstructPolicy(struct KernelSchedMgr *pKernelSchedM #define kschedmgrConstructPolicy(pKernelSchedMgr, pGpu) kschedmgrConstructPolicy_IMPL(pKernelSchedMgr, pGpu) #endif //__nvoc_kernel_sched_mgr_h_disabled +void kschedmgrSetConfigPolicyFromUser_IMPL(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu, NvU32 schedSwPolicy); + +#ifdef __nvoc_kernel_sched_mgr_h_disabled +static inline void kschedmgrSetConfigPolicyFromUser(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu, NvU32 schedSwPolicy) { + NV_ASSERT_FAILED_PRECOMP("KernelSchedMgr was disabled!"); +} +#else //__nvoc_kernel_sched_mgr_h_disabled +#define kschedmgrSetConfigPolicyFromUser(pKernelSchedMgr, pGpu, schedSwPolicy) kschedmgrSetConfigPolicyFromUser_IMPL(pKernelSchedMgr, pGpu, schedSwPolicy) +#endif //__nvoc_kernel_sched_mgr_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.c b/src/nvidia/generated/g_kernel_sec2_nvoc.c index fc2b0159c6..096998e2ac 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.c +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.c @@ -88,7 +88,7 @@ static NV_STATUS __nvoc_thunk_KernelSec2_engstateConstructEngine(struct OBJGPU * return ksec2ConstructEngine(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelSec2_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelSec2, IntrServiceRecord pRecords[166]) { +static void __nvoc_thunk_KernelSec2_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelSec2, IntrServiceRecord pRecords[167]) { ksec2RegisterIntrService(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_IntrService.offset), pRecords); } @@ -227,99 +227,69 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- ksec2ConstructEngine - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__ksec2ConstructEngine__ = &ksec2ConstructEngine_IMPL; - } + pThis->__ksec2ConstructEngine__ = &ksec2ConstructEngine_IMPL; // Hal function -- ksec2RegisterIntrService - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__ksec2RegisterIntrService__ = &ksec2RegisterIntrService_IMPL; - } + pThis->__ksec2RegisterIntrService__ = &ksec2RegisterIntrService_IMPL; // Hal function -- ksec2ServiceNotificationInterrupt - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__ksec2ServiceNotificationInterrupt__ = &ksec2ServiceNotificationInterrupt_IMPL; - } + pThis->__ksec2ServiceNotificationInterrupt__ = &ksec2ServiceNotificationInterrupt_IMPL; // Hal function -- ksec2ConfigureFalcon - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA102; - } + pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA100; } - - // Hal function -- ksec2ResetHw - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_TU102; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; - } + pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA102; } + // Hal function -- ksec2ResetHw + pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; + // Hal function -- ksec2ReadUcodeFuseVersion - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_b2b553; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_GA100; - } + pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_b2b553; + } + else + { + pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_GA100; } // Hal function -- ksec2GetBinArchiveBlUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_80f438; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_80f438; - } + pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_TU102; } // Hal function -- ksec2GetGenericBlUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_5baef9; - } + pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_5baef9; + } + else + { + pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_TU102; } // Hal function -- ksec2GetBinArchiveSecurescrubUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_AD10X; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_AD10X; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ - { - pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438; - } + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelSec2_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.h b/src/nvidia/generated/g_kernel_sec2_nvoc.h index 78a94d49c6..71e0bba424 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.h +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.h @@ -156,9 +156,9 @@ static inline NV_STATUS ksec2ConstructEngine_DISPATCH(struct OBJGPU *pGpu, struc return pKernelSec2->__ksec2ConstructEngine__(pGpu, pKernelSec2, arg0); } -void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[166]); +void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[167]); -static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[166]) { +static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[167]) { pKernelSec2->__ksec2RegisterIntrService__(pGpu, pKernelSec2, pRecords); } diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c index 0c48136680..94962f24f8 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c @@ -422,6 +422,36 @@ static NvBool __nvoc_thunk_RmResource_ksmdbgssnAccessCallback(struct KernelSMDeb static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSMDebuggerSession[] = { { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdSMDebugModeEnable_fcf1ac, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*flags=*/ 0x2200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x83de0301u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_KernelSMDebuggerSession.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "ksmdbgssnCtrlCmdSMDebugModeEnable" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdSMDebugModeDisable_fcf1ac, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + /*flags=*/ 0x2200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x83de0302u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_KernelSMDebuggerSession.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "ksmdbgssnCtrlCmdSMDebugModeDisable" +#endif + }, + { /* [2] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -436,7 +466,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetModeMMUDebug" #endif }, - { /* [1] */ + { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -451,7 +481,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugGetModeMMUDebug" #endif }, - { /* [2] */ + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -466,7 +496,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetExceptionMask" #endif }, - { /* [3] */ + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -481,7 +511,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugReadSingleSmErrorState" #endif }, - { /* [4] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -496,7 +526,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugReadAllSmErrorStates" #endif }, - { /* [5] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -511,7 +541,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugClearSingleSmErrorState" #endif }, - { /* [6] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -526,7 +556,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugClearAllSmErrorStates" #endif }, - { /* [7] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -541,7 +571,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetNextStopTriggerType" #endif }, - { /* [8] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -556,7 +586,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleStepInterruptHandling" #endif }, - { /* [9] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -571,7 +601,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugReadMemory" #endif }, - { /* [10] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -586,7 +616,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugWriteMemory" #endif }, - { /* [11] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -601,7 +631,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSuspendContext" #endif }, - { /* [12] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -616,7 +646,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugResumeContext" #endif }, - { /* [13] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -631,7 +661,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdReadSurface" #endif }, - { /* [14] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -646,7 +676,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdWriteSurface" #endif }, - { /* [15] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -661,7 +691,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdGetMappings" #endif }, - { /* [16] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -676,7 +706,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugExecRegOps" #endif }, - { /* [17] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -691,7 +721,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetModeErrbarDebug" #endif }, - { /* [18] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -706,7 +736,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugGetModeErrbarDebug" #endif }, - { /* [19] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -721,7 +751,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleSmSingleStep" #endif }, - { /* [20] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -736,7 +766,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleSmStopTrigger" #endif }, - { /* [21] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -751,7 +781,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleSmRunTrigger" #endif }, - { /* [22] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -766,7 +796,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugSetSingleSmSkipIdleWarpDetect" #endif }, - { /* [23] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -781,7 +811,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugGetSingleSmDebuggerStatus" #endif }, - { /* [24] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -796,7 +826,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugReadBatchMemory" #endif }, - { /* [25] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -811,7 +841,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*func=*/ "ksmdbgssnCtrlCmdDebugWriteBatchMemory" #endif }, - { /* [26] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -831,7 +861,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelSMDebuggerSession = { - /*numEntries=*/ 27, + /*numEntries=*/ 29, /*pExportEntries=*/ __nvoc_exported_method_def_KernelSMDebuggerSession }; @@ -879,6 +909,14 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnGetInternalObjectHandle__ = &ksmdbgssnGetInternalObjectHandle_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + pThis->__ksmdbgssnCtrlCmdSMDebugModeEnable__ = &ksmdbgssnCtrlCmdSMDebugModeEnable_fcf1ac; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + pThis->__ksmdbgssnCtrlCmdSMDebugModeDisable__ = &ksmdbgssnCtrlCmdSMDebugModeDisable_fcf1ac; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__ksmdbgssnCtrlCmdDebugSetModeMMUDebug__ = &ksmdbgssnCtrlCmdDebugSetModeMMUDebug_fcf1ac; #endif diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h index a88c70c880..42547d0bce 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -158,6 +158,8 @@ struct KernelSMDebuggerSession { struct KernelSMDebuggerSession *__nvoc_pbase_KernelSMDebuggerSession; NV_STATUS (*__ksmdbgssnInternalControlForward__)(struct KernelSMDebuggerSession *, NvU32, void *, NvU32); NvHandle (*__ksmdbgssnGetInternalObjectHandle__)(struct KernelSMDebuggerSession *); + NV_STATUS (*__ksmdbgssnCtrlCmdSMDebugModeEnable__)(struct KernelSMDebuggerSession *); + NV_STATUS (*__ksmdbgssnCtrlCmdSMDebugModeDisable__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugSetModeMMUDebug__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugGetModeMMUDebug__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugSetModeErrbarDebug__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *); @@ -213,18 +215,18 @@ struct KernelSMDebuggerSession { struct NotifShare *(*__ksmdbgssnGetNotificationShare__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnMap__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__ksmdbgssnAccessCallback__)(struct KernelSMDebuggerSession *, struct RsClient *, void *, RsAccessRight); - struct RmDebuggerSession *pDebugSession; - struct KernelGraphicsObject *pObject; - NvHandle hDebugger; - NvHandle hDebuggerClient; - NvHandle hChannel; - NvHandle hChannelClient; - NvHandle hSubdevice; - NvHandle hInternalClient; - NvHandle hInternalDevice; - NvHandle hInternalSubdevice; - NvHandle hInternalSubscription; - NvHandle hInternalMemMapping; + struct RmDebuggerSession *PRIVATE_FIELD(pDebugSession); + struct KernelGraphicsObject *PRIVATE_FIELD(pObject); + NvHandle PRIVATE_FIELD(hDebugger); + NvHandle PRIVATE_FIELD(hDebuggerClient); + NvHandle PRIVATE_FIELD(hChannel); + NvHandle PRIVATE_FIELD(hChannelClient); + NvHandle PRIVATE_FIELD(hSubdevice); + NvHandle PRIVATE_FIELD(hInternalClient); + NvHandle PRIVATE_FIELD(hInternalDevice); + NvHandle PRIVATE_FIELD(hInternalSubdevice); + NvHandle PRIVATE_FIELD(hInternalSubscription); + NvHandle PRIVATE_FIELD(hInternalMemMapping); }; #ifndef __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ @@ -257,6 +259,8 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession**, Dy #define ksmdbgssnInternalControlForward(arg0, command, pParams, size) ksmdbgssnInternalControlForward_DISPATCH(arg0, command, pParams, size) #define ksmdbgssnGetInternalObjectHandle(arg0) ksmdbgssnGetInternalObjectHandle_DISPATCH(arg0) +#define ksmdbgssnCtrlCmdSMDebugModeEnable(pKernelSMDebuggerSession) ksmdbgssnCtrlCmdSMDebugModeEnable_DISPATCH(pKernelSMDebuggerSession) +#define ksmdbgssnCtrlCmdSMDebugModeDisable(pKernelSMDebuggerSession) ksmdbgssnCtrlCmdSMDebugModeDisable_DISPATCH(pKernelSMDebuggerSession) #define ksmdbgssnCtrlCmdDebugSetModeMMUDebug(pKernelSMDebuggerSession, pParams) ksmdbgssnCtrlCmdDebugSetModeMMUDebug_DISPATCH(pKernelSMDebuggerSession, pParams) #define ksmdbgssnCtrlCmdDebugGetModeMMUDebug(pKernelSMDebuggerSession, pParams) ksmdbgssnCtrlCmdDebugGetModeMMUDebug_DISPATCH(pKernelSMDebuggerSession, pParams) #define ksmdbgssnCtrlCmdDebugSetModeErrbarDebug(pKernelSMDebuggerSession, pParams) ksmdbgssnCtrlCmdDebugSetModeErrbarDebug_DISPATCH(pKernelSMDebuggerSession, pParams) @@ -324,6 +328,22 @@ static inline NvHandle ksmdbgssnGetInternalObjectHandle_DISPATCH(struct KernelSM return arg0->__ksmdbgssnGetInternalObjectHandle__(arg0); } +static inline NV_STATUS ksmdbgssnCtrlCmdSMDebugModeEnable_fcf1ac(struct KernelSMDebuggerSession *pKernelSMDebuggerSession) { + return ksmdbgssnInternalControlForward(pKernelSMDebuggerSession, (2212365313U), ((void *)0), 0); +} + +static inline NV_STATUS ksmdbgssnCtrlCmdSMDebugModeEnable_DISPATCH(struct KernelSMDebuggerSession *pKernelSMDebuggerSession) { + return pKernelSMDebuggerSession->__ksmdbgssnCtrlCmdSMDebugModeEnable__(pKernelSMDebuggerSession); +} + +static inline NV_STATUS ksmdbgssnCtrlCmdSMDebugModeDisable_fcf1ac(struct KernelSMDebuggerSession *pKernelSMDebuggerSession) { + return ksmdbgssnInternalControlForward(pKernelSMDebuggerSession, (2212365314U), ((void *)0), 0); +} + +static inline NV_STATUS ksmdbgssnCtrlCmdSMDebugModeDisable_DISPATCH(struct KernelSMDebuggerSession *pKernelSMDebuggerSession) { + return pKernelSMDebuggerSession->__ksmdbgssnCtrlCmdSMDebugModeDisable__(pKernelSMDebuggerSession); +} + static inline NV_STATUS ksmdbgssnCtrlCmdDebugSetModeMMUDebug_fcf1ac(struct KernelSMDebuggerSession *pKernelSMDebuggerSession, NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams) { return ksmdbgssnInternalControlForward(pKernelSMDebuggerSession, (2212365315U), pParams, sizeof (*pParams)); } diff --git a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h index ee2bb0fee9..db92ef59f4 100644 --- a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -37,6 +37,7 @@ extern "C" { #include "ctrl/ctrl2080/ctrl2080vgpumgrinternal.h" #include "ctrl/ctrla081.h" #include "ctrl/ctrla084.h" +#include "ctrl/ctrlc637.h" #include "gpu/gpu.h" #include "nv-hypervisor.h" @@ -71,6 +72,7 @@ typedef struct VgpuConfigApi VgpuConfigApi; #endif /* __nvoc_class_id_VgpuConfigApi */ +typedef struct KERNEL_MIG_GPU_INSTANCE KERNEL_MIG_GPU_INSTANCE; /* vGPU events info lookup node*/ typedef struct VGPU_EVENT_INFO_NODE @@ -122,10 +124,13 @@ typedef struct KERNEL_HOST_VGPU_DEVICE NvHandle hPluginFBAllocationClient; VGPU_DEVICE_GUEST_FB_INFO vgpuDeviceGuestFbInfo; NvU32 *pGuestFbSegment; - NvU32 guestFbSegmentPageSize; + NvU64 guestFbSegmentPageSize; NvBool bOfflinedPageInfoValid; NvU32 offlinedPageCount; /* offlined page count */ NvU64 offlinedPageGpa[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; + MEMORY_DESCRIPTOR *pGspPluginHeapMemDesc; + NvBool bDisableDefaultSmcExecPartRestore; + struct GPUMGR_SAVE_COMPUTE_INSTANCE savedExecPartitions[NVC637_CTRL_MAX_EXEC_PARTITIONS]; } KERNEL_HOST_VGPU_DEVICE; MAKE_LIST(KERNEL_HOST_VGPU_DEVICE_LIST, KERNEL_HOST_VGPU_DEVICE); @@ -204,7 +209,6 @@ struct KernelVgpuMgr { NvU32 user_max_supported_version; struct OBJEHEAP *pHeap; REQUEST_VGPU_INFO_NODE_LIST listRequestVgpuHead; - MEMORY_DESCRIPTOR *pGspPluginHeapMemDesc; }; #ifndef __NVOC_CLASS_KernelVgpuMgr_TYPEDEF__ @@ -264,10 +268,6 @@ kvgpumgrAttachGpu(NvU32 gpuPciId); NV_STATUS kvgpumgrDetachGpu(NvU32 gpuPciId); -NV_STATUS -kvgpumgrRegisterGuestId(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams, - KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, struct OBJGPU *pGpu); - NV_STATUS kvgpumgrGuestRegister(struct OBJGPU *pGpu, NvU32 gfid, @@ -369,6 +369,13 @@ kvgpumgrSendAllVgpuTypesToGsp(struct OBJGPU *pGpu); NvBool kvgpumgrIsHeterogeneousVgpuSupported(void); +NV_STATUS +kvgpumgrGetHostVgpuDeviceFromGfid(NvU32 gpuPciId, NvU32 gfid, + KERNEL_HOST_VGPU_DEVICE** ppHostVgpuDevice); +NV_STATUS +kvgpuMgrRestoreSmcExecPart(struct OBJGPU *pGpu,KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance); + #endif // __kernel_vgpu_mgr_h__ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_mem_desc_nvoc.h b/src/nvidia/generated/g_mem_desc_nvoc.h index 0ae040dc7b..a21ea9144c 100644 --- a/src/nvidia/generated/g_mem_desc_nvoc.h +++ b/src/nvidia/generated/g_mem_desc_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -89,6 +89,7 @@ typedef NvU32 NV_ADDRESS_SPACE; #define ADDR_REGMEM 3 // NV register memory space #define ADDR_VIRTUAL 4 // Virtual address space only #define ADDR_FABRIC_V2 6 // Fabric address space for the FLA based addressing. Will replace ADDR_FABRIC. +#define ADDR_EGM 7 // Extended GPU Memory (EGM) #define ADDR_FABRIC_MC 8 // Multicast fabric address space (MCFLA) // @@ -647,14 +648,12 @@ NvBool memdescGetContiguity(PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION add void memdescSetContiguity(PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation, NvBool isContiguous); NvBool memdescCheckContiguity(PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation); NV_ADDRESS_SPACE memdescGetAddressSpace(PMEMORY_DESCRIPTOR pMemDesc); -NvU32 memdescGetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation); +NvU64 memdescGetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation); void memdescSetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation, NvU64 pageSize); PMEMORY_DESCRIPTOR memdescGetRootMemDesc(PMEMORY_DESCRIPTOR pMemDesc, NvU64 *pRootOffset); void memdescSetCustomHeap(PMEMORY_DESCRIPTOR); NvBool memdescGetCustomHeap(PMEMORY_DESCRIPTOR); - -// Temporary function for 64-bit pageSize transition -NvU64 memdescGetPageSize64(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation); +NV_STATUS memdescSetPageArrayGranularity(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pageArrayGranularity); NvBool memdescAcquireRmExclusiveUse(MEMORY_DESCRIPTOR *pMemDesc); @@ -949,7 +948,7 @@ void memdescUnmapInternal(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags /*! * @brief Set the name of the surface. - * + * * @param[in] pGpu OBJGPU pointer. * @param[in] pMemDesc MEMORY_DESCRIPTOR pointer that the name is to be set for. * @param[in] name const char pointer to the name to be set. @@ -1125,6 +1124,11 @@ void memdescSetName(OBJGPU*, MEMORY_DESCRIPTOR *pMemDesc, const char *name, cons // against RM internal sysmem allocation // #define MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT NVBIT64(44) +// +// Clients (including RM) should set this flag to request allocations in +// unprotected memory. This is required for Confidential Compute cases +// +#define MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY NVBIT64(45) // // The following is a special use case for sharing memory between @@ -1143,7 +1147,7 @@ void memdescSetName(OBJGPU*, MEMORY_DESCRIPTOR *pMemDesc, const char *name, cons // // Specical case to allocate the runlists for Guests from its GPA // In MODS, VM's GPA allocated from subheap so using this define to -// Forcing memdesc to allocated from subheap +// Forcing memdesc to allocated from subheap // #define MEMDESC_FLAGS_FORCE_ALLOC_FROM_SUBHEAP NVBIT64(48) diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.c b/src/nvidia/generated/g_mem_fabric_nvoc.c index 0b0bb57f69..602892b985 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_fabric_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_memoryfabricIsReady(struct MemoryFabric *pM return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_memoryfabricCheckCopyPermissions(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_memoryfabricCheckCopyPermissions(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_memoryfabricPreDestruct(struct MemoryFabric *pResource) { @@ -287,6 +287,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFa /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "memoryfabricCtrlGetAttachedMem" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricCtrlGetPageLevelInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) + /*flags=*/ 0x840u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf80107u, + /*paramSize=*/ sizeof(NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricCtrlGetPageLevelInfo" #endif }, @@ -294,7 +309,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFa const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryFabric = { - /*numEntries=*/ 6, + /*numEntries=*/ 7, /*pExportEntries=*/ __nvoc_exported_method_def_MemoryFabric }; @@ -361,6 +376,10 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricCtrlGetAttachedMem__ = &memoryfabricCtrlGetAttachedMem_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) + pThis->__memoryfabricCtrlGetPageLevelInfo__ = &memoryfabricCtrlGetPageLevelInfo_IMPL; +#endif + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryFabric_resCanCopy; pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryFabric_memControl; diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.h b/src/nvidia/generated/g_mem_fabric_nvoc.h index 5dbdd6deec..9e798ea5ec 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_fabric_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -75,6 +75,7 @@ struct MemoryFabric { NV_STATUS (*__memoryfabricCtrlDetachMem__)(struct MemoryFabric *, NV00F8_CTRL_DETACH_MEM_PARAMS *); NV_STATUS (*__memoryfabricCtrlGetNumAttachedMem__)(struct MemoryFabric *, NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *); NV_STATUS (*__memoryfabricCtrlGetAttachedMem__)(struct MemoryFabric *, NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *); + NV_STATUS (*__memoryfabricCtrlGetPageLevelInfo__)(struct MemoryFabric *, NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS *); NV_STATUS (*__memoryfabricCheckMemInterUnmap__)(struct MemoryFabric *, NvBool); NvBool (*__memoryfabricShareCallback__)(struct MemoryFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memoryfabricMapTo__)(struct MemoryFabric *, RS_RES_MAP_TO_PARAMS *); @@ -92,7 +93,7 @@ struct MemoryFabric { NV_STATUS (*__memoryfabricControlFilter__)(struct MemoryFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricControlSerialization_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricIsReady__)(struct MemoryFabric *, NvBool); - NV_STATUS (*__memoryfabricCheckCopyPermissions__)(struct MemoryFabric *, struct OBJGPU *, NvHandle); + NV_STATUS (*__memoryfabricCheckCopyPermissions__)(struct MemoryFabric *, struct OBJGPU *, struct Device *); void (*__memoryfabricPreDestruct__)(struct MemoryFabric *); NV_STATUS (*__memoryfabricIsDuplicate__)(struct MemoryFabric *, NvHandle, NvBool *); void (*__memoryfabricControlSerialization_Epilogue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -137,6 +138,7 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric**, Dynamic*, NvU32, CALL_CO #define memoryfabricCtrlDetachMem(pMemoryFabric, pParams) memoryfabricCtrlDetachMem_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCtrlGetNumAttachedMem(pMemoryFabric, pParams) memoryfabricCtrlGetNumAttachedMem_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCtrlGetAttachedMem(pMemoryFabric, pParams) memoryfabricCtrlGetAttachedMem_DISPATCH(pMemoryFabric, pParams) +#define memoryfabricCtrlGetPageLevelInfo(pMemoryFabric, pParams) memoryfabricCtrlGetPageLevelInfo_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memoryfabricCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define memoryfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memoryfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memoryfabricMapTo(pResource, pParams) memoryfabricMapTo_DISPATCH(pResource, pParams) @@ -154,7 +156,7 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric**, Dynamic*, NvU32, CALL_CO #define memoryfabricControlFilter(pResource, pCallContext, pParams) memoryfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricControlSerialization_Prologue(pResource, pCallContext, pParams) memoryfabricControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricIsReady(pMemory, bCopyConstructorContext) memoryfabricIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define memoryfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memoryfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memoryfabricCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memoryfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memoryfabricPreDestruct(pResource) memoryfabricPreDestruct_DISPATCH(pResource) #define memoryfabricIsDuplicate(pMemory, hMemory, pDuplicate) memoryfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define memoryfabricControlSerialization_Epilogue(pResource, pCallContext, pParams) memoryfabricControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -214,6 +216,12 @@ static inline NV_STATUS memoryfabricCtrlGetAttachedMem_DISPATCH(struct MemoryFab return pMemoryFabric->__memoryfabricCtrlGetAttachedMem__(pMemoryFabric, pParams); } +NV_STATUS memoryfabricCtrlGetPageLevelInfo_IMPL(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS *pParams); + +static inline NV_STATUS memoryfabricCtrlGetPageLevelInfo_DISPATCH(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS *pParams) { + return pMemoryFabric->__memoryfabricCtrlGetPageLevelInfo__(pMemoryFabric, pParams); +} + static inline NV_STATUS memoryfabricCheckMemInterUnmap_DISPATCH(struct MemoryFabric *pMemory, NvBool bSubdeviceHandleProvided) { return pMemory->__memoryfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } @@ -282,8 +290,8 @@ static inline NV_STATUS memoryfabricIsReady_DISPATCH(struct MemoryFabric *pMemor return pMemory->__memoryfabricIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS memoryfabricCheckCopyPermissions_DISPATCH(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__memoryfabricCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS memoryfabricCheckCopyPermissions_DISPATCH(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memoryfabricCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void memoryfabricPreDestruct_DISPATCH(struct MemoryFabric *pResource) { diff --git a/src/nvidia/generated/g_mem_list_nvoc.c b/src/nvidia/generated/g_mem_list_nvoc.c index b7eceb3443..33e8764983 100644 --- a/src/nvidia/generated/g_mem_list_nvoc.c +++ b/src/nvidia/generated/g_mem_list_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_memlistIsReady(struct MemoryList *pMemory, return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_memlistCheckCopyPermissions(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_memlistCheckCopyPermissions(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_memlistPreDestruct(struct MemoryList *pResource) { diff --git a/src/nvidia/generated/g_mem_list_nvoc.h b/src/nvidia/generated/g_mem_list_nvoc.h index 8d71604042..e63e6fe8d6 100644 --- a/src/nvidia/generated/g_mem_list_nvoc.h +++ b/src/nvidia/generated/g_mem_list_nvoc.h @@ -73,7 +73,7 @@ struct MemoryList { NV_STATUS (*__memlistControlFilter__)(struct MemoryList *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistControlSerialization_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistIsReady__)(struct MemoryList *, NvBool); - NV_STATUS (*__memlistCheckCopyPermissions__)(struct MemoryList *, struct OBJGPU *, NvHandle); + NV_STATUS (*__memlistCheckCopyPermissions__)(struct MemoryList *, struct OBJGPU *, struct Device *); void (*__memlistPreDestruct__)(struct MemoryList *); NV_STATUS (*__memlistIsDuplicate__)(struct MemoryList *, NvHandle, NvBool *); void (*__memlistControlSerialization_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -128,7 +128,7 @@ NV_STATUS __nvoc_objCreate_MemoryList(MemoryList**, Dynamic*, NvU32, CALL_CONTEX #define memlistControlFilter(pResource, pCallContext, pParams) memlistControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memlistControlSerialization_Prologue(pResource, pCallContext, pParams) memlistControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memlistIsReady(pMemory, bCopyConstructorContext) memlistIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define memlistCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memlistCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memlistCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memlistCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memlistPreDestruct(pResource) memlistPreDestruct_DISPATCH(pResource) #define memlistIsDuplicate(pMemory, hMemory, pDuplicate) memlistIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define memlistControlSerialization_Epilogue(pResource, pCallContext, pParams) memlistControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -212,8 +212,8 @@ static inline NV_STATUS memlistIsReady_DISPATCH(struct MemoryList *pMemory, NvBo return pMemory->__memlistIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS memlistCheckCopyPermissions_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__memlistCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS memlistCheckCopyPermissions_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memlistCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void memlistPreDestruct_DISPATCH(struct MemoryList *pResource) { diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.c b/src/nvidia/generated/g_mem_mgr_nvoc.c index 7a735ec86a..a0b50d5e5c 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.c +++ b/src/nvidia/generated/g_mem_mgr_nvoc.c @@ -82,6 +82,10 @@ static NV_STATUS __nvoc_thunk_MemoryManager_engstateStateLoad(OBJGPU *pGpu, stru return memmgrStateLoad(pGpu, (struct MemoryManager *)(((unsigned char *)pMemoryManager) - __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); } +static NV_STATUS __nvoc_thunk_MemoryManager_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pMemoryManager, NvU32 arg0) { + return memmgrStatePostLoad(pGpu, (struct MemoryManager *)(((unsigned char *)pMemoryManager) - __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); +} + static NV_STATUS __nvoc_thunk_MemoryManager_engstateStatePreUnload(OBJGPU *pGpu, struct OBJENGSTATE *pMemoryManager, NvU32 arg0) { return memmgrStatePreUnload(pGpu, (struct MemoryManager *)(((unsigned char *)pMemoryManager) - __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); } @@ -114,10 +118,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrStatePreInitUnlocked(POBJGPU pGp return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrStatePostLoad(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { - return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); -} - static NvBool __nvoc_thunk_OBJENGSTATE_memmgrIsPresent(POBJGPU pGpu, struct MemoryManager *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset)); } @@ -221,6 +221,17 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p pThis->bAllowNoncontiguousAllocation = ((NvBool)(0 == 0)); } + // Hal field -- bLocalEgmSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bLocalEgmSupported = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bLocalEgmSupported = ((NvBool)(0 != 0)); + } + // Hal field -- bScrubOnFreeEnabled if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { @@ -237,6 +248,28 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p { pThis->bFastScrubberEnabled = ((NvBool)(0 != 0)); } + + // Hal field -- bMonitoredFenceSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->bMonitoredFenceSupported = ((NvBool)(0 == 0)); + } + + // Hal field -- b64BitSemaphoresSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->b64BitSemaphoresSupported = ((NvBool)(0 == 0)); + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->b64BitSemaphoresSupported = ((NvBool)(0 != 0)); + } + + // Hal field -- bGenericKindSupport + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->bGenericKindSupport = ((NvBool)(0 == 0)); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -273,6 +306,8 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrStateLoad__ = &memmgrStateLoad_IMPL; + pThis->__memmgrStatePostLoad__ = &memmgrStatePostLoad_IMPL; + pThis->__memmgrStatePreUnload__ = &memmgrStatePreUnload_IMPL; pThis->__memmgrStateUnload__ = &memmgrStateUnload_IMPL; @@ -284,7 +319,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrMemUtilsCheckMemoryFastScrubEnable__ = &memmgrMemUtilsCheckMemoryFastScrubEnable_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else { pThis->__memmgrMemUtilsCheckMemoryFastScrubEnable__ = &memmgrMemUtilsCheckMemoryFastScrubEnable_491d52; } @@ -294,7 +329,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrAllocDetermineAlignment__ = &memmgrAllocDetermineAlignment_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrAllocDetermineAlignment__ = &memmgrAllocDetermineAlignment_GA100; } @@ -304,63 +339,63 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ - { - pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_GA100; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_AD102; } + else + { + pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_GA100; + } // Hal function -- memmgrScrubRegistryOverrides if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrScrubRegistryOverrides__ = &memmgrScrubRegistryOverrides_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrScrubRegistryOverrides__ = &memmgrScrubRegistryOverrides_GA100; } // Hal function -- memmgrGetPteKindBl - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_GM107; + pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_474d46; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_474d46; + pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_GM107; } // Hal function -- memmgrGetPteKindPitch - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_GM107; + pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_474d46; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_474d46; + pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_GM107; } // Hal function -- memmgrChooseKindCompressC - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_GP100; + pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_474d46; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_474d46; + pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_GP100; } // Hal function -- memmgrGetFlaKind - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_GA100; + pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_46f6a7; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_46f6a7; + pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_GA100; } // Hal function -- memmgrIsApertureSupportedByFla @@ -379,7 +414,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_13cd8d; } @@ -400,7 +435,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrReadMmuLock__ = &memmgrReadMmuLock_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrReadMmuLock__ = &memmgrReadMmuLock_e133c0; } @@ -410,7 +445,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrBlockMemLockedMemory__ = &memmgrBlockMemLockedMemory_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrBlockMemLockedMemory__ = &memmgrBlockMemLockedMemory_56cd7a; } @@ -420,19 +455,19 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_56cd7a; } // Hal function -- memmgrGetDisablePlcKind - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { - pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_GA100; + pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_b3696a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_b3696a; + pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_GA100; } // Hal function -- memmgrEnableDynamicPageOfflining @@ -440,21 +475,21 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA102; - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_b3696a; } + else + { + pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA102; + } // Hal function -- memmgrGetBlackListPages if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GA100; } @@ -467,6 +502,8 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_MemoryManager_engstateStateLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_MemoryManager_engstateStatePostLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_MemoryManager_engstateStatePreUnload; pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_MemoryManager_engstateStateUnload; @@ -483,8 +520,6 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePreInitUnlocked; - pThis->__memmgrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePostLoad; - pThis->__memmgrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_memmgrIsPresent; } diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.h b/src/nvidia/generated/g_mem_mgr_nvoc.h index 2ce44d7a76..d6e9f0519e 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_mem_mgr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,6 +52,19 @@ extern "C" { #include "gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h" +struct CeUtils; + +#ifndef __NVOC_CLASS_CeUtils_TYPEDEF__ +#define __NVOC_CLASS_CeUtils_TYPEDEF__ +typedef struct CeUtils CeUtils; +#endif /* __NVOC_CLASS_CeUtils_TYPEDEF__ */ + +#ifndef __nvoc_class_id_CeUtils +#define __nvoc_class_id_CeUtils 0x8b8bae +#endif /* __nvoc_class_id_CeUtils */ + + + typedef volatile struct _cl906f_tag1 Nv906fControl; typedef struct KERNEL_MIG_GPU_INSTANCE KERNEL_MIG_GPU_INSTANCE; @@ -260,7 +273,7 @@ typedef struct OBJCHANNEL // NvBool bManageBAR2; OBJGPU *pGpu; - struct KernelCE *pKCe; + NvU32 ceId; // Used by Partition Scrubber KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; @@ -407,6 +420,7 @@ struct MemoryManager { NV_STATUS (*__memmgrStatePreInitLocked__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrStateInitLocked__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrStateLoad__)(OBJGPU *, struct MemoryManager *, NvU32); + NV_STATUS (*__memmgrStatePostLoad__)(OBJGPU *, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStatePreUnload__)(OBJGPU *, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStateUnload__)(OBJGPU *, struct MemoryManager *, NvU32); void (*__memmgrStateDestroy__)(OBJGPU *, struct MemoryManager *); @@ -432,7 +446,6 @@ struct MemoryManager { NV_STATUS (*__memmgrStateInitUnlocked__)(POBJGPU, struct MemoryManager *); void (*__memmgrInitMissing__)(POBJGPU, struct MemoryManager *); NV_STATUS (*__memmgrStatePreInitUnlocked__)(POBJGPU, struct MemoryManager *); - NV_STATUS (*__memmgrStatePostLoad__)(POBJGPU, struct MemoryManager *, NvU32); NvBool (*__memmgrIsPresent__)(POBJGPU, struct MemoryManager *); NvBool bFbsrWddmModeEnabled; NvBool bFbRegionsSupported; @@ -459,11 +472,17 @@ struct MemoryManager { NvBool bVgpuPmaSupport; NvBool bEnableDynamicGranularityPageArrays; NvBool bAllowNoncontiguousAllocation; + NvBool bLocalEgmSupported; + NvBool bLocalEgmEnabled; + NvU32 localEgmPeerId; + NvS32 localEgmNodeId; + NvU64 localEgmBasePhysAddr; + NvU64 localEgmSize; NvBool bEccInterleavedVidmemScrub; NvBool bScrubberInitialized; NvBool bAllowSysmemHugePages; NvBool bEccScrubOverride; - NvU32 sysmemPageSize; + NvU64 sysmemPageSize; struct Heap *pHeap; NvBool bScrubOnFreeEnabled; NvBool bFastScrubberEnabled; @@ -474,6 +493,7 @@ struct MemoryManager { NvU64 heapStartOffset; NvU64 rsvdMemoryBase; NvU32 rsvdMemorySize; + struct CeUtils *pCeUtils; OBJSCRUB eccScrubberState; struct __nvoc_inner_struc_MemoryManager_1__ Ram; NvU32 PteKindOverride; @@ -495,6 +515,9 @@ struct MemoryManager { NvHandle hDevice; NvHandle hSubdevice; NvHandle hThirdPartyP2P; + NvBool bMonitoredFenceSupported; + NvBool b64BitSemaphoresSupported; + NvBool bGenericKindSupport; }; #ifndef __NVOC_CLASS_MemoryManager_TYPEDEF__ @@ -531,6 +554,7 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrStatePreInitLocked(pGpu, pMemoryManager) memmgrStatePreInitLocked_DISPATCH(pGpu, pMemoryManager) #define memmgrStateInitLocked(pGpu, pMemoryManager) memmgrStateInitLocked_DISPATCH(pGpu, pMemoryManager) #define memmgrStateLoad(pGpu, pMemoryManager, arg0) memmgrStateLoad_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrStatePostLoad(pGpu, pMemoryManager, arg0) memmgrStatePostLoad_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStatePreUnload(pGpu, pMemoryManager, arg0) memmgrStatePreUnload_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStateUnload(pGpu, pMemoryManager, arg0) memmgrStateUnload_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStateDestroy(pGpu, pMemoryManager) memmgrStateDestroy_DISPATCH(pGpu, pMemoryManager) @@ -573,7 +597,6 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrStateInitUnlocked(pGpu, pEngstate) memmgrStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define memmgrInitMissing(pGpu, pEngstate) memmgrInitMissing_DISPATCH(pGpu, pEngstate) #define memmgrStatePreInitUnlocked(pGpu, pEngstate) memmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define memmgrStatePostLoad(pGpu, pEngstate, arg0) memmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define memmgrIsPresent(pGpu, pEngstate) memmgrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS memmgrSavePowerMgmtState_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); @@ -1066,19 +1089,19 @@ static inline NV_STATUS memmgrFinishHandleSizeOverrides(OBJGPU *pGpu, struct Mem #define memmgrFinishHandleSizeOverrides_HAL(pGpu, pMemoryManager) memmgrFinishHandleSizeOverrides(pGpu, pMemoryManager) -NV_STATUS memmgrGetBAR1InfoForClient_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, PGETBAR1INFO bar1Info); +NV_STATUS memmgrGetBAR1InfoForDevice_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Device *pDevice, PGETBAR1INFO bar1Info); #ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrGetBAR1InfoForClient(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, PGETBAR1INFO bar1Info) { +static inline NV_STATUS memmgrGetBAR1InfoForDevice(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Device *pDevice, PGETBAR1INFO bar1Info) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrGetBAR1InfoForClient(pGpu, pMemoryManager, arg0, bar1Info) memmgrGetBAR1InfoForClient_GM107(pGpu, pMemoryManager, arg0, bar1Info) +#define memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, bar1Info) memmgrGetBAR1InfoForDevice_GM107(pGpu, pMemoryManager, pDevice, bar1Info) #endif //__nvoc_mem_mgr_h_disabled -#define memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, arg0, bar1Info) memmgrGetBAR1InfoForClient(pGpu, pMemoryManager, arg0, bar1Info) +#define memmgrGetBAR1InfoForDevice_HAL(pGpu, pMemoryManager, pDevice, bar1Info) memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, bar1Info) static inline NvU64 memmgrGetFbTaxSize_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { return 0; @@ -1773,6 +1796,36 @@ static inline NV_STATUS memmgrReserveVgaWorkspaceMemDescForFbsr(OBJGPU *pGpu, st #define memmgrReserveVgaWorkspaceMemDescForFbsr_HAL(pGpu, pMemoryManager) memmgrReserveVgaWorkspaceMemDescForFbsr(pGpu, pMemoryManager) +static inline NV_STATUS memmgrCalculateHeapOffsetWithGSP_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *offset) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrCalculateHeapOffsetWithGSP(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *offset) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrCalculateHeapOffsetWithGSP(pGpu, pMemoryManager, offset) memmgrCalculateHeapOffsetWithGSP_46f6a7(pGpu, pMemoryManager, offset) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrCalculateHeapOffsetWithGSP_HAL(pGpu, pMemoryManager, offset) memmgrCalculateHeapOffsetWithGSP(pGpu, pMemoryManager, offset) + +NvBool memmgrIsGspOwnedMemory_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NvBool memmgrIsGspOwnedMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_FALSE; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrIsGspOwnedMemory(pGpu, pMemoryManager, pMemDesc) memmgrIsGspOwnedMemory_KERNEL(pGpu, pMemoryManager, pMemDesc) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrIsGspOwnedMemory_HAL(pGpu, pMemoryManager, pMemDesc) memmgrIsGspOwnedMemory(pGpu, pMemoryManager, pMemDesc) + NV_STATUS memmgrConstructEngine_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, ENGDESCRIPTOR arg0); static inline NV_STATUS memmgrConstructEngine_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, ENGDESCRIPTOR arg0) { @@ -1797,6 +1850,12 @@ static inline NV_STATUS memmgrStateLoad_DISPATCH(OBJGPU *pGpu, struct MemoryMana return pMemoryManager->__memmgrStateLoad__(pGpu, pMemoryManager, arg0); } +NV_STATUS memmgrStatePostLoad_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0); + +static inline NV_STATUS memmgrStatePostLoad_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0) { + return pMemoryManager->__memmgrStatePostLoad__(pGpu, pMemoryManager, arg0); +} + NV_STATUS memmgrStatePreUnload_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0); static inline NV_STATUS memmgrStatePreUnload_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0) { @@ -2003,14 +2062,18 @@ static inline NV_STATUS memmgrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__memmgrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS memmgrStatePostLoad_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { - return pEngstate->__memmgrStatePostLoad__(pGpu, pEngstate, arg0); -} - static inline NvBool memmgrIsPresent_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate) { return pEngstate->__memmgrIsPresent__(pGpu, pEngstate); } +static inline NvBool memmgrIsLocalEgmSupported(struct MemoryManager *pMemoryManager) { + return pMemoryManager->bLocalEgmSupported; +} + +static inline NvBool memmgrIsLocalEgmEnabled(struct MemoryManager *pMemoryManager) { + return pMemoryManager->bLocalEgmEnabled; +} + static inline NvBool memmgrIsScrubOnFreeEnabled(struct MemoryManager *pMemoryManager) { return pMemoryManager->bScrubOnFreeEnabled; } @@ -2554,6 +2617,27 @@ static inline NV_STATUS memmgrPmaRegisterRegions(OBJGPU *pGpu, struct MemoryMana #define memmgrPmaRegisterRegions(pGpu, pMemoryManager, pHeap, pPma) memmgrPmaRegisterRegions_IMPL(pGpu, pMemoryManager, pHeap, pPma) #endif //__nvoc_mem_mgr_h_disabled +NV_STATUS memmgrInitCeUtils_IMPL(struct MemoryManager *pMemoryManager, NvBool bFifoLite); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrInitCeUtils(struct MemoryManager *pMemoryManager, NvBool bFifoLite) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrInitCeUtils(pMemoryManager, bFifoLite) memmgrInitCeUtils_IMPL(pMemoryManager, bFifoLite) +#endif //__nvoc_mem_mgr_h_disabled + +void memmgrDestroyCeUtils_IMPL(struct MemoryManager *pMemoryManager); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline void memmgrDestroyCeUtils(struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrDestroyCeUtils(pMemoryManager) memmgrDestroyCeUtils_IMPL(pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + NV_STATUS memmgrSetMIGPartitionableBAR1Range_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); #ifdef __nvoc_mem_mgr_h_disabled @@ -2675,6 +2759,16 @@ static inline void memmgrGetFreeMemoryForAllMIGGPUInstances(OBJGPU *pGpu, struct #define memmgrGetFreeMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, pBytes) memmgrGetFreeMemoryForAllMIGGPUInstances_IMPL(pGpu, pMemoryManager, pBytes) #endif //__nvoc_mem_mgr_h_disabled +void memmgrGetTotalMemoryForAllMIGGPUInstances_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pBytes); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline void memmgrGetTotalMemoryForAllMIGGPUInstances(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pBytes) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrGetTotalMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, pBytes) memmgrGetTotalMemoryForAllMIGGPUInstances_IMPL(pGpu, pMemoryManager, pBytes) +#endif //__nvoc_mem_mgr_h_disabled + void memmgrGetTopLevelScrubberStatus_IMPL(OBJGPU *arg0, struct MemoryManager *arg1, NvBool *pbTopLevelScrubberEnabled, NvBool *pbTopLevelScrubberConstructed); #ifdef __nvoc_mem_mgr_h_disabled @@ -2707,6 +2801,17 @@ static inline NV_STATUS memmgrInitSavedTopLevelScrubber(OBJGPU *arg0, struct Mem #define memmgrInitSavedTopLevelScrubber(arg0, arg1) memmgrInitSavedTopLevelScrubber_IMPL(arg0, arg1) #endif //__nvoc_mem_mgr_h_disabled +NV_STATUS memmgrVerifyGspDmaOps_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrVerifyGspDmaOps(OBJGPU *arg0, struct MemoryManager *arg1) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrVerifyGspDmaOps(arg0, arg1) memmgrVerifyGspDmaOps_IMPL(arg0, arg1) +#endif //__nvoc_mem_mgr_h_disabled + NV_STATUS memmgrReserveMemoryForFsp_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); #ifdef __nvoc_mem_mgr_h_disabled diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c index a63e606324..609fed6e16 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_RmResource_memorymulticastfabricControlSerializati return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_memorymulticastfabricPreDestruct(struct MemoryMulticastFabric *pResource) { diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h index b3fd251347..19353539a4 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -179,7 +179,7 @@ struct MemoryMulticastFabric { NV_STATUS (*__memorymulticastfabricGetMemoryMappingDescriptor__)(struct MemoryMulticastFabric *, MEMORY_DESCRIPTOR **); NV_STATUS (*__memorymulticastfabricControlFilter__)(struct MemoryMulticastFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricControlSerialization_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memorymulticastfabricCheckCopyPermissions__)(struct MemoryMulticastFabric *, struct OBJGPU *, NvHandle); + NV_STATUS (*__memorymulticastfabricCheckCopyPermissions__)(struct MemoryMulticastFabric *, struct OBJGPU *, struct Device *); void (*__memorymulticastfabricPreDestruct__)(struct MemoryMulticastFabric *); NV_STATUS (*__memorymulticastfabricIsDuplicate__)(struct MemoryMulticastFabric *, NvHandle, NvBool *); void (*__memorymulticastfabricControlSerialization_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -241,7 +241,7 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric**, Dynami #define memorymulticastfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memorymulticastfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define memorymulticastfabricControlFilter(pResource, pCallContext, pParams) memorymulticastfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memorymulticastfabricControlSerialization_Prologue(pResource, pCallContext, pParams) memorymulticastfabricControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define memorymulticastfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memorymulticastfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memorymulticastfabricCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memorymulticastfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memorymulticastfabricPreDestruct(pResource) memorymulticastfabricPreDestruct_DISPATCH(pResource) #define memorymulticastfabricIsDuplicate(pMemory, hMemory, pDuplicate) memorymulticastfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define memorymulticastfabricControlSerialization_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -371,8 +371,8 @@ static inline NV_STATUS memorymulticastfabricControlSerialization_Prologue_DISPA return pResource->__memorymulticastfabricControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memorymulticastfabricCheckCopyPermissions_DISPATCH(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__memorymulticastfabricCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS memorymulticastfabricCheckCopyPermissions_DISPATCH(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memorymulticastfabricCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void memorymulticastfabricPreDestruct_DISPATCH(struct MemoryMulticastFabric *pResource) { @@ -404,8 +404,8 @@ void memorymulticastfabricDestruct_IMPL(struct MemoryMulticastFabric *pMemoryMul #undef PRIVATE_FIELD -void memorymulticastfabricTeamSetupResponseCallback(NvU32 gpuInstance, - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); +NV_STATUS memorymulticastfabricTeamSetupResponseCallback(NvU32 gpuInstance, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); #endif // _MEMORYMULTICASTFABRIC_H_ diff --git a/src/nvidia/generated/g_mem_nvoc.h b/src/nvidia/generated/g_mem_nvoc.h index 5105051bbe..e4c2cc3258 100644 --- a/src/nvidia/generated/g_mem_nvoc.h +++ b/src/nvidia/generated/g_mem_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -156,7 +156,7 @@ struct Memory { NV_STATUS (*__memGetMemInterMapParams__)(struct Memory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memCheckMemInterUnmap__)(struct Memory *, NvBool); NV_STATUS (*__memGetMemoryMappingDescriptor__)(struct Memory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__memCheckCopyPermissions__)(struct Memory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__memCheckCopyPermissions__)(struct Memory *, struct OBJGPU *, struct Device *); NV_STATUS (*__memIsReady__)(struct Memory *, NvBool); NvBool (*__memIsGpuMapAllowed__)(struct Memory *, struct OBJGPU *); NV_STATUS (*__memCtrlCmdGetSurfaceCompressionCoverageLvm__)(struct Memory *, NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS *); @@ -244,7 +244,7 @@ NV_STATUS __nvoc_objCreate_Memory(Memory**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define memGetMemInterMapParams(pMemory, pParams) memGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define memGetMemoryMappingDescriptor(pMemory, ppMemDesc) memGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define memCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memIsReady(pMemory, bCopyConstructorContext) memIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define memIsGpuMapAllowed(pMemory, pGpu) memIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define memCtrlCmdGetSurfaceCompressionCoverageLvm(pMemory, pParams) memCtrlCmdGetSurfaceCompressionCoverageLvm_DISPATCH(pMemory, pParams) @@ -317,12 +317,12 @@ static inline NV_STATUS memGetMemoryMappingDescriptor_DISPATCH(struct Memory *pM return pMemory->__memGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS memCheckCopyPermissions_ac1694(struct Memory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { +static inline NV_STATUS memCheckCopyPermissions_ac1694(struct Memory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { return NV_OK; } -static inline NV_STATUS memCheckCopyPermissions_DISPATCH(struct Memory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__memCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS memCheckCopyPermissions_DISPATCH(struct Memory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } NV_STATUS memIsReady_IMPL(struct Memory *pMemory, NvBool bCopyConstructorContext); diff --git a/src/nvidia/generated/g_mig_config_session_nvoc.h b/src/nvidia/generated/g_mig_config_session_nvoc.h index 37b322e858..37ccabe9b0 100644 --- a/src/nvidia/generated/g_mig_config_session_nvoc.h +++ b/src/nvidia/generated/g_mig_config_session_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -86,7 +86,7 @@ struct MIGConfigSession { NV_STATUS (*__migconfigsessionControlLookup__)(struct MIGConfigSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__migconfigsessionMap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__migconfigsessionAccessCallback__)(struct MIGConfigSession *, struct RsClient *, void *, RsAccessRight); - NvU64 dupedCapDescriptor; + NvU64 PRIVATE_FIELD(dupedCapDescriptor); }; #ifndef __NVOC_CLASS_MIGConfigSession_TYPEDEF__ diff --git a/src/nvidia/generated/g_mig_monitor_session_nvoc.h b/src/nvidia/generated/g_mig_monitor_session_nvoc.h index 5de2a94c92..6792bef246 100644 --- a/src/nvidia/generated/g_mig_monitor_session_nvoc.h +++ b/src/nvidia/generated/g_mig_monitor_session_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -87,7 +87,7 @@ struct MIGMonitorSession { NV_STATUS (*__migmonitorsessionControlLookup__)(struct MIGMonitorSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__migmonitorsessionMap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__migmonitorsessionAccessCallback__)(struct MIGMonitorSession *, struct RsClient *, void *, RsAccessRight); - NvU64 dupedCapDescriptor; + NvU64 PRIVATE_FIELD(dupedCapDescriptor); }; #ifndef __NVOC_CLASS_MIGMonitorSession_TYPEDEF__ diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.c b/src/nvidia/generated/g_no_device_mem_nvoc.c index 1c9b1569bf..0f235883f3 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.c +++ b/src/nvidia/generated/g_no_device_mem_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_nodevicememIsReady(struct NoDeviceMemory *p return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_nodevicememCheckCopyPermissions(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_nodevicememCheckCopyPermissions(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_nodevicememPreDestruct(struct NoDeviceMemory *pResource) { diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.h b/src/nvidia/generated/g_no_device_mem_nvoc.h index c6bea742c6..928ac7c0aa 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.h +++ b/src/nvidia/generated/g_no_device_mem_nvoc.h @@ -74,7 +74,7 @@ struct NoDeviceMemory { NV_STATUS (*__nodevicememControlSerialization_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nodevicememCanCopy__)(struct NoDeviceMemory *); NV_STATUS (*__nodevicememIsReady__)(struct NoDeviceMemory *, NvBool); - NV_STATUS (*__nodevicememCheckCopyPermissions__)(struct NoDeviceMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__nodevicememCheckCopyPermissions__)(struct NoDeviceMemory *, struct OBJGPU *, struct Device *); void (*__nodevicememPreDestruct__)(struct NoDeviceMemory *); NV_STATUS (*__nodevicememIsDuplicate__)(struct NoDeviceMemory *, NvHandle, NvBool *); void (*__nodevicememControlSerialization_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -129,7 +129,7 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory**, Dynamic*, NvU32, CAL #define nodevicememControlSerialization_Prologue(pResource, pCallContext, pParams) nodevicememControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nodevicememCanCopy(pResource) nodevicememCanCopy_DISPATCH(pResource) #define nodevicememIsReady(pMemory, bCopyConstructorContext) nodevicememIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define nodevicememCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) nodevicememCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define nodevicememCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) nodevicememCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define nodevicememPreDestruct(pResource) nodevicememPreDestruct_DISPATCH(pResource) #define nodevicememIsDuplicate(pMemory, hMemory, pDuplicate) nodevicememIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define nodevicememControlSerialization_Epilogue(pResource, pCallContext, pParams) nodevicememControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -213,8 +213,8 @@ static inline NV_STATUS nodevicememIsReady_DISPATCH(struct NoDeviceMemory *pMemo return pMemory->__nodevicememIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS nodevicememCheckCopyPermissions_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__nodevicememCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS nodevicememCheckCopyPermissions_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__nodevicememCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void nodevicememPreDestruct_DISPATCH(struct NoDeviceMemory *pResource) { diff --git a/src/nvidia/generated/g_nv_debug_dump_nvoc.h b/src/nvidia/generated/g_nv_debug_dump_nvoc.h index bbf9014471..8fbf1d99a8 100644 --- a/src/nvidia/generated/g_nv_debug_dump_nvoc.h +++ b/src/nvidia/generated/g_nv_debug_dump_nvoc.h @@ -59,7 +59,7 @@ typedef enum #define NV_NVD_ERROR_CODE_MAJOR 31:16 #define NV_NVD_ERROR_CODE_MINOR 15:0 -#define NVD_ERROR_CODE(Major, Minor) \ +#define NVD_ERROR_CODE(Major, Minor) \ (DRF_NUM(_NVD, _ERROR_CODE, _MAJOR, Major) | \ DRF_NUM(_NVD, _ERROR_CODE, _MINOR, Minor)) @@ -86,7 +86,7 @@ typedef enum #define NV_NVD_ENGINE_STEP_MAJOR 31:16 #define NV_NVD_ENGINE_STEP_MINOR 15:0 -#define NVD_ENGINE_STEP(Major, Minor) \ +#define NVD_ENGINE_STEP(Major, Minor) \ (DRF_NUM(_NVD, _ENGINE_STEP, _MAJOR, Major) | \ DRF_NUM(_NVD, _ENGINE_STEP, _MINOR, Minor)) diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index 44a309cd06..64b04c6bc3 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -918,6 +918,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x24B9, 0x0000, 0x0000, "NVIDIA RTX A3000 12GB Laptop GPU" }, { 0x24BA, 0x0000, 0x0000, "NVIDIA RTX A4500 Laptop GPU" }, { 0x24BB, 0x0000, 0x0000, "NVIDIA RTX A3000 12GB Laptop GPU" }, + { 0x24C7, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060" }, { 0x24C9, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" }, { 0x24DC, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Laptop GPU" }, { 0x24DD, 0x0000, 0x0000, "NVIDIA GeForce RTX 3070 Laptop GPU" }, @@ -963,6 +964,8 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25B9, 0x0000, 0x0000, "NVIDIA RTX A1000 Laptop GPU" }, { 0x25BA, 0x0000, 0x0000, "NVIDIA RTX A2000 8GB Laptop GPU" }, { 0x25BB, 0x0000, 0x0000, "NVIDIA RTX A500 Laptop GPU" }, + { 0x25BC, 0x0000, 0x0000, "NVIDIA RTX A1000 6GB Laptop GPU" }, + { 0x25BD, 0x0000, 0x0000, "NVIDIA RTX A500 Laptop GPU" }, { 0x25E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Ti Laptop GPU" }, { 0x25E2, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Laptop GPU" }, { 0x25E5, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Laptop GPU" }, @@ -980,8 +983,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B5, 0x17da, 0x10de, "NVIDIA L40" }, { 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" }, { 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" }, + { 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" }, { 0x2757, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" }, { 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" }, + { 0x2786, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070" }, { 0x27A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" }, { 0x27B0, 0x16fa, 0x1028, "NVIDIA RTX 4000 SFF Ada Generation" }, { 0x27B0, 0x16fa, 0x103c, "NVIDIA RTX 4000 SFF Ada Generation" }, @@ -989,11 +994,16 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x27B0, 0x16fa, 0x17aa, "NVIDIA RTX 4000 SFF Ada Generation" }, { 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" }, { 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" }, + { 0x27BA, 0x0000, 0x0000, "NVIDIA RTX 4000 Ada Generation Laptop GPU" }, + { 0x27BB, 0x0000, 0x0000, "NVIDIA RTX 3500 Ada Generation Laptop GPU" }, { 0x27E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" }, + { 0x2803, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Ti" }, { 0x2820, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" }, + { 0x2838, 0x0000, 0x0000, "NVIDIA RTX 3000 Ada Generation Laptop GPU" }, { 0x2860, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" }, { 0x28A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" }, { 0x28A1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" }, + { 0x28B8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Laptop GPU" }, { 0x28E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" }, { 0x28E1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" }, { 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" }, @@ -1003,6 +1013,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13BD, 0x11d0, 0x10DE, "GRID M10-2Q" }, { 0x13BD, 0x11d1, 0x10DE, "GRID M10-4Q" }, { 0x13BD, 0x11d2, 0x10DE, "GRID M10-8Q" }, + { 0x13BD, 0x11d3, 0x10DE, "GRID M10-1A" }, + { 0x13BD, 0x11d4, 0x10DE, "GRID M10-2A" }, + { 0x13BD, 0x11d5, 0x10DE, "GRID M10-4A" }, + { 0x13BD, 0x11d6, 0x10DE, "GRID M10-8A" }, { 0x13BD, 0x1286, 0x10DE, "GRID M10-2B" }, { 0x13BD, 0x12ee, 0x10DE, "GRID M10-2B4" }, { 0x13BD, 0x1339, 0x10DE, "GRID M10-1B4" }, @@ -1014,6 +1028,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13F2, 0x1176, 0x10DE, "GRID M60-0B" }, { 0x13F2, 0x1177, 0x10DE, "GRID M60-1B" }, { 0x13F2, 0x117d, 0x10DE, "GRID M60-2B" }, + { 0x13F2, 0x11ae, 0x10DE, "GRID M60-1A" }, + { 0x13F2, 0x11af, 0x10DE, "GRID M60-2A" }, + { 0x13F2, 0x11b0, 0x10DE, "GRID M60-4A" }, + { 0x13F2, 0x11b1, 0x10DE, "GRID M60-8A" }, { 0x13F2, 0x12ec, 0x10DE, "GRID M60-2B4" }, { 0x13F2, 0x1337, 0x10DE, "GRID M60-1B4" }, { 0x13F3, 0x117c, 0x10DE, "GRID M6-2B" }, @@ -1024,6 +1042,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13F3, 0x1182, 0x10DE, "GRID M6-2Q" }, { 0x13F3, 0x1183, 0x10DE, "GRID M6-4Q" }, { 0x13F3, 0x1184, 0x10DE, "GRID M6-8Q" }, + { 0x13F3, 0x11aa, 0x10DE, "GRID M6-1A" }, + { 0x13F3, 0x11ab, 0x10DE, "GRID M6-2A" }, + { 0x13F3, 0x11ac, 0x10DE, "GRID M6-4A" }, + { 0x13F3, 0x11ad, 0x10DE, "GRID M6-8A" }, { 0x13F3, 0x12ed, 0x10DE, "GRID M6-2B4" }, { 0x13F3, 0x1338, 0x10DE, "GRID M6-1B4" }, { 0x15F7, 0x1265, 0x10DE, "GRID P100C-1B" }, @@ -1032,6 +1054,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F7, 0x1268, 0x10DE, "GRID P100C-4Q" }, { 0x15F7, 0x1269, 0x10DE, "GRID P100C-6Q" }, { 0x15F7, 0x126a, 0x10DE, "GRID P100C-12Q" }, + { 0x15F7, 0x126b, 0x10DE, "GRID P100C-1A" }, + { 0x15F7, 0x126c, 0x10DE, "GRID P100C-2A" }, + { 0x15F7, 0x126d, 0x10DE, "GRID P100C-4A" }, + { 0x15F7, 0x126e, 0x10DE, "GRID P100C-6A" }, + { 0x15F7, 0x126f, 0x10DE, "GRID P100C-12A" }, { 0x15F7, 0x128d, 0x10DE, "GRID P100C-2B" }, { 0x15F7, 0x12f4, 0x10DE, "GRID P100C-2B4" }, { 0x15F7, 0x133f, 0x10DE, "GRID P100C-1B4" }, @@ -1044,6 +1071,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F8, 0x1224, 0x10DE, "GRID P100-4Q" }, { 0x15F8, 0x1225, 0x10DE, "GRID P100-8Q" }, { 0x15F8, 0x1226, 0x10DE, "GRID P100-16Q" }, + { 0x15F8, 0x1227, 0x10DE, "GRID P100-1A" }, + { 0x15F8, 0x1228, 0x10DE, "GRID P100-2A" }, + { 0x15F8, 0x1229, 0x10DE, "GRID P100-4A" }, + { 0x15F8, 0x122a, 0x10DE, "GRID P100-8A" }, + { 0x15F8, 0x122b, 0x10DE, "GRID P100-16A" }, { 0x15F8, 0x128c, 0x10DE, "GRID P100-2B" }, { 0x15F8, 0x12f2, 0x10DE, "GRID P100-2B4" }, { 0x15F8, 0x133d, 0x10DE, "GRID P100-1B4" }, @@ -1056,6 +1088,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F9, 0x122f, 0x10DE, "GRID P100X-4Q" }, { 0x15F9, 0x1230, 0x10DE, "GRID P100X-8Q" }, { 0x15F9, 0x1231, 0x10DE, "GRID P100X-16Q" }, + { 0x15F9, 0x1232, 0x10DE, "GRID P100X-1A" }, + { 0x15F9, 0x1233, 0x10DE, "GRID P100X-2A" }, + { 0x15F9, 0x1234, 0x10DE, "GRID P100X-4A" }, + { 0x15F9, 0x1235, 0x10DE, "GRID P100X-8A" }, + { 0x15F9, 0x1236, 0x10DE, "GRID P100X-16A" }, { 0x15F9, 0x128b, 0x10DE, "GRID P100X-2B" }, { 0x15F9, 0x12f3, 0x10DE, "GRID P100X-2B4" }, { 0x15F9, 0x133e, 0x10DE, "GRID P100X-1B4" }, @@ -1071,6 +1108,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1B38, 0x11ed, 0x10DE, "GRID P40-8Q" }, { 0x1B38, 0x11ee, 0x10DE, "GRID P40-12Q" }, { 0x1B38, 0x11ef, 0x10DE, "GRID P40-24Q" }, + { 0x1B38, 0x11f0, 0x10DE, "GRID P40-1A" }, + { 0x1B38, 0x11f1, 0x10DE, "GRID P40-2A" }, + { 0x1B38, 0x11f2, 0x10DE, "GRID P40-3A" }, + { 0x1B38, 0x11f3, 0x10DE, "GRID P40-4A" }, + { 0x1B38, 0x11f4, 0x10DE, "GRID P40-6A" }, + { 0x1B38, 0x11f5, 0x10DE, "GRID P40-8A" }, + { 0x1B38, 0x11f6, 0x10DE, "GRID P40-12A" }, + { 0x1B38, 0x11f7, 0x10DE, "GRID P40-24A" }, { 0x1B38, 0x1287, 0x10DE, "GRID P40-2B" }, { 0x1B38, 0x12b1, 0x10DE, "GeForce GTX P40-24" }, { 0x1B38, 0x12b2, 0x10DE, "GeForce GTX P40-12" }, @@ -1091,6 +1136,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1BB3, 0x1205, 0x10DE, "GRID P4-2Q" }, { 0x1BB3, 0x1206, 0x10DE, "GRID P4-4Q" }, { 0x1BB3, 0x1207, 0x10DE, "GRID P4-8Q" }, + { 0x1BB3, 0x1208, 0x10DE, "GRID P4-1A" }, + { 0x1BB3, 0x1209, 0x10DE, "GRID P4-2A" }, + { 0x1BB3, 0x120a, 0x10DE, "GRID P4-4A" }, + { 0x1BB3, 0x120b, 0x10DE, "GRID P4-8A" }, { 0x1BB3, 0x1288, 0x10DE, "GRID P4-2B" }, { 0x1BB3, 0x12f1, 0x10DE, "GRID P4-2B4" }, { 0x1BB3, 0x133c, 0x10DE, "GRID P4-1B4" }, @@ -1105,6 +1154,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1BB4, 0x11fb, 0x10DE, "GRID P6-4Q" }, { 0x1BB4, 0x11fc, 0x10DE, "GRID P6-8Q" }, { 0x1BB4, 0x11fd, 0x10DE, "GRID P6-16Q" }, + { 0x1BB4, 0x11fe, 0x10DE, "GRID P6-1A" }, + { 0x1BB4, 0x11ff, 0x10DE, "GRID P6-2A" }, + { 0x1BB4, 0x1200, 0x10DE, "GRID P6-4A" }, + { 0x1BB4, 0x1201, 0x10DE, "GRID P6-8A" }, + { 0x1BB4, 0x1202, 0x10DE, "GRID P6-16A" }, { 0x1BB4, 0x1289, 0x10DE, "GRID P6-2B" }, { 0x1BB4, 0x12f0, 0x10DE, "GRID P6-2B4" }, { 0x1BB4, 0x133b, 0x10DE, "GRID P6-1B4" }, @@ -1117,6 +1171,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB1, 0x125c, 0x10DE, "GRID V100X-4Q" }, { 0x1DB1, 0x125d, 0x10DE, "GRID V100X-8Q" }, { 0x1DB1, 0x125e, 0x10DE, "GRID V100X-16Q" }, + { 0x1DB1, 0x125f, 0x10DE, "GRID V100X-1A" }, + { 0x1DB1, 0x1260, 0x10DE, "GRID V100X-2A" }, + { 0x1DB1, 0x1261, 0x10DE, "GRID V100X-4A" }, + { 0x1DB1, 0x1262, 0x10DE, "GRID V100X-8A" }, + { 0x1DB1, 0x1263, 0x10DE, "GRID V100X-16A" }, { 0x1DB1, 0x128e, 0x10DE, "GRID V100X-2B" }, { 0x1DB1, 0x12f6, 0x10DE, "GRID V100X-2B4" }, { 0x1DB1, 0x1341, 0x10DE, "GRID V100X-1B4" }, @@ -1130,6 +1189,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB3, 0x1294, 0x10DE, "GRID V100L-4Q" }, { 0x1DB3, 0x1295, 0x10DE, "GRID V100L-8Q" }, { 0x1DB3, 0x1296, 0x10DE, "GRID V100L-16Q" }, + { 0x1DB3, 0x1297, 0x10DE, "GRID V100L-1A" }, + { 0x1DB3, 0x1298, 0x10DE, "GRID V100L-2A" }, + { 0x1DB3, 0x1299, 0x10DE, "GRID V100L-4A" }, + { 0x1DB3, 0x129a, 0x10DE, "GRID V100L-8A" }, + { 0x1DB3, 0x129b, 0x10DE, "GRID V100L-16A" }, { 0x1DB3, 0x12f9, 0x10DE, "GRID V100L-2B4" }, { 0x1DB3, 0x1344, 0x10DE, "GRID V100L-1B4" }, { 0x1DB3, 0x137a, 0x10DE, "GRID V100L-16C" }, @@ -1141,6 +1205,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB4, 0x1251, 0x10DE, "GRID V100-4Q" }, { 0x1DB4, 0x1252, 0x10DE, "GRID V100-8Q" }, { 0x1DB4, 0x1253, 0x10DE, "GRID V100-16Q" }, + { 0x1DB4, 0x1254, 0x10DE, "GRID V100-1A" }, + { 0x1DB4, 0x1255, 0x10DE, "GRID V100-2A" }, + { 0x1DB4, 0x1256, 0x10DE, "GRID V100-4A" }, + { 0x1DB4, 0x1257, 0x10DE, "GRID V100-8A" }, + { 0x1DB4, 0x1258, 0x10DE, "GRID V100-16A" }, { 0x1DB4, 0x128f, 0x10DE, "GRID V100-2B" }, { 0x1DB4, 0x12f5, 0x10DE, "GRID V100-2B4" }, { 0x1DB4, 0x1340, 0x10DE, "GRID V100-1B4" }, @@ -1155,6 +1224,12 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB5, 0x12d0, 0x10DE, "GRID V100DX-8Q" }, { 0x1DB5, 0x12d1, 0x10DE, "GRID V100DX-16Q" }, { 0x1DB5, 0x12d2, 0x10DE, "GRID V100DX-32Q" }, + { 0x1DB5, 0x12d3, 0x10DE, "GRID V100DX-1A" }, + { 0x1DB5, 0x12d4, 0x10DE, "GRID V100DX-2A" }, + { 0x1DB5, 0x12d5, 0x10DE, "GRID V100DX-4A" }, + { 0x1DB5, 0x12d6, 0x10DE, "GRID V100DX-8A" }, + { 0x1DB5, 0x12d7, 0x10DE, "GRID V100DX-16A" }, + { 0x1DB5, 0x12d8, 0x10DE, "GRID V100DX-32A" }, { 0x1DB5, 0x12f8, 0x10DE, "GRID V100DX-2B4" }, { 0x1DB5, 0x1343, 0x10DE, "GRID V100DX-1B4" }, { 0x1DB5, 0x1376, 0x10DE, "GRID V100DX-32C" }, @@ -1169,6 +1244,12 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB6, 0x12c2, 0x10DE, "GRID V100D-8Q" }, { 0x1DB6, 0x12c3, 0x10DE, "GRID V100D-16Q" }, { 0x1DB6, 0x12c4, 0x10DE, "GRID V100D-32Q" }, + { 0x1DB6, 0x12c5, 0x10DE, "GRID V100D-1A" }, + { 0x1DB6, 0x12c6, 0x10DE, "GRID V100D-2A" }, + { 0x1DB6, 0x12c7, 0x10DE, "GRID V100D-4A" }, + { 0x1DB6, 0x12c8, 0x10DE, "GRID V100D-8A" }, + { 0x1DB6, 0x12c9, 0x10DE, "GRID V100D-16A" }, + { 0x1DB6, 0x12ca, 0x10DE, "GRID V100D-32A" }, { 0x1DB6, 0x12f7, 0x10DE, "GRID V100D-2B4" }, { 0x1DB6, 0x1342, 0x10DE, "GRID V100D-1B4" }, { 0x1DB6, 0x1377, 0x10DE, "GRID V100D-32C" }, @@ -1186,6 +1267,12 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DF6, 0x13e8, 0x10DE, "GRID V100S-8Q" }, { 0x1DF6, 0x13e9, 0x10DE, "GRID V100S-16Q" }, { 0x1DF6, 0x13ea, 0x10DE, "GRID V100S-32Q" }, + { 0x1DF6, 0x13eb, 0x10DE, "GRID V100S-1A" }, + { 0x1DF6, 0x13ec, 0x10DE, "GRID V100S-2A" }, + { 0x1DF6, 0x13ed, 0x10DE, "GRID V100S-4A" }, + { 0x1DF6, 0x13ee, 0x10DE, "GRID V100S-8A" }, + { 0x1DF6, 0x13ef, 0x10DE, "GRID V100S-16A" }, + { 0x1DF6, 0x13f0, 0x10DE, "GRID V100S-32A" }, { 0x1DF6, 0x13f1, 0x10DE, "GRID V100S-4C" }, { 0x1DF6, 0x13f2, 0x10DE, "GRID V100S-8C" }, { 0x1DF6, 0x13f3, 0x10DE, "GRID V100S-16C" }, @@ -1230,8 +1317,26 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E30, 0x13cc, 0x10DE, "GRID RTX8000-16" }, { 0x1E30, 0x1437, 0x10DE, "GRID RTX6000-1B" }, { 0x1E30, 0x1438, 0x10DE, "GRID RTX6000-2B" }, + { 0x1E30, 0x1439, 0x10DE, "GRID RTX6000-1A" }, + { 0x1E30, 0x143a, 0x10DE, "GRID RTX6000-2A" }, + { 0x1E30, 0x143b, 0x10DE, "GRID RTX6000-3A" }, + { 0x1E30, 0x143c, 0x10DE, "GRID RTX6000-4A" }, + { 0x1E30, 0x143d, 0x10DE, "GRID RTX6000-6A" }, + { 0x1E30, 0x143e, 0x10DE, "GRID RTX6000-8A" }, + { 0x1E30, 0x143f, 0x10DE, "GRID RTX6000-12A" }, + { 0x1E30, 0x1440, 0x10DE, "GRID RTX6000-24A" }, { 0x1E30, 0x1441, 0x10DE, "GRID RTX8000-1B" }, { 0x1E30, 0x1442, 0x10DE, "GRID RTX8000-2B" }, + { 0x1E30, 0x1443, 0x10DE, "GRID RTX8000-1A" }, + { 0x1E30, 0x1444, 0x10DE, "GRID RTX8000-2A" }, + { 0x1E30, 0x1445, 0x10DE, "GRID RTX8000-3A" }, + { 0x1E30, 0x1446, 0x10DE, "GRID RTX8000-4A" }, + { 0x1E30, 0x1447, 0x10DE, "GRID RTX8000-6A" }, + { 0x1E30, 0x1448, 0x10DE, "GRID RTX8000-8A" }, + { 0x1E30, 0x1449, 0x10DE, "GRID RTX8000-12A" }, + { 0x1E30, 0x144a, 0x10DE, "GRID RTX8000-16A" }, + { 0x1E30, 0x144b, 0x10DE, "GRID RTX8000-24A" }, + { 0x1E30, 0x144c, 0x10DE, "GRID RTX8000-48A" }, { 0x1E37, 0x1347, 0x10DE, "GeForce RTX T10x-8" }, { 0x1E37, 0x1348, 0x10DE, "GeForce RTX T10x-4" }, { 0x1E37, 0x1349, 0x10DE, "GeForce RTX T10x-2" }, @@ -1244,11 +1349,8 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E37, 0x13a7, 0x10DE, "GRID RTX T10x-2" }, { 0x1E37, 0x13a8, 0x10DE, "GRID RTX T10x-4" }, { 0x1E37, 0x13a9, 0x10DE, "GRID RTX T10x-8" }, - { 0x1E37, 0x148a, 0x10DE, "GRID RTX T10-2" }, - { 0x1E37, 0x148b, 0x10DE, "GRID RTX T10-1" }, - { 0x1E37, 0x148c, 0x10DE, "GRID RTX T10-0" }, { 0x1E37, 0x180d, 0x10DE, "NVIDIA GeForce GTX 1060" }, - { 0x1E37, 0x1820, 0x10DE, "GeForce RTX 2080" }, + { 0x1E37, 0x1820, 0x10DE, "NVIDIA GeForce RTX 2080" }, { 0x1E78, 0x13f7, 0x10DE, "GRID RTX6000P-1B" }, { 0x1E78, 0x13f8, 0x10DE, "GRID RTX6000P-2B" }, { 0x1E78, 0x13f9, 0x10DE, "GRID RTX6000P-1Q" }, @@ -1259,6 +1361,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x13fe, 0x10DE, "GRID RTX6000P-8Q" }, { 0x1E78, 0x13ff, 0x10DE, "GRID RTX6000P-12Q" }, { 0x1E78, 0x1400, 0x10DE, "GRID RTX6000P-24Q" }, + { 0x1E78, 0x1401, 0x10DE, "GRID RTX6000P-1A" }, + { 0x1E78, 0x1402, 0x10DE, "GRID RTX6000P-2A" }, + { 0x1E78, 0x1403, 0x10DE, "GRID RTX6000P-3A" }, + { 0x1E78, 0x1404, 0x10DE, "GRID RTX6000P-4A" }, + { 0x1E78, 0x1405, 0x10DE, "GRID RTX6000P-6A" }, + { 0x1E78, 0x1406, 0x10DE, "GRID RTX6000P-8A" }, + { 0x1E78, 0x1407, 0x10DE, "GRID RTX6000P-12A" }, + { 0x1E78, 0x1408, 0x10DE, "GRID RTX6000P-24A" }, { 0x1E78, 0x1409, 0x10DE, "GRID RTX6000P-6" }, { 0x1E78, 0x140a, 0x10DE, "GRID RTX6000P-8" }, { 0x1E78, 0x140b, 0x10DE, "GRID RTX6000P-12" }, @@ -1280,6 +1390,15 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x141b, 0x10DE, "GRID RTX8000P-16Q" }, { 0x1E78, 0x141c, 0x10DE, "GRID RTX8000P-24Q" }, { 0x1E78, 0x141d, 0x10DE, "GRID RTX8000P-48Q" }, + { 0x1E78, 0x141e, 0x10DE, "GRID RTX8000P-1A" }, + { 0x1E78, 0x141f, 0x10DE, "GRID RTX8000P-2A" }, + { 0x1E78, 0x1420, 0x10DE, "GRID RTX8000P-3A" }, + { 0x1E78, 0x1421, 0x10DE, "GRID RTX8000P-4A" }, + { 0x1E78, 0x1422, 0x10DE, "GRID RTX8000P-6A" }, + { 0x1E78, 0x1423, 0x10DE, "GRID RTX8000P-8A" }, + { 0x1E78, 0x1424, 0x10DE, "GRID RTX8000P-12A" }, + { 0x1E78, 0x1425, 0x10DE, "GRID RTX8000P-24A" }, + { 0x1E78, 0x1426, 0x10DE, "GRID RTX8000P-48A" }, { 0x1E78, 0x1427, 0x10DE, "GRID RTX8000P-12" }, { 0x1E78, 0x1428, 0x10DE, "GRID RTX8000P-16" }, { 0x1E78, 0x1429, 0x10DE, "GRID RTX8000P-24" }, @@ -1291,6 +1410,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x142f, 0x10DE, "GRID RTX8000P-16C" }, { 0x1E78, 0x1430, 0x10DE, "GRID RTX8000P-24C" }, { 0x1E78, 0x1431, 0x10DE, "GRID RTX8000P-48C" }, + { 0x1E78, 0x1436, 0x10DE, "GRID RTX8000P-16A" }, { 0x1EB8, 0x1309, 0x10DE, "GRID T4-1B" }, { 0x1EB8, 0x130a, 0x10DE, "GRID T4-2B" }, { 0x1EB8, 0x130b, 0x10DE, "GRID T4-2B4" }, @@ -1299,6 +1419,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1EB8, 0x130e, 0x10DE, "GRID T4-4Q" }, { 0x1EB8, 0x130f, 0x10DE, "GRID T4-8Q" }, { 0x1EB8, 0x1310, 0x10DE, "GRID T4-16Q" }, + { 0x1EB8, 0x1311, 0x10DE, "GRID T4-1A" }, + { 0x1EB8, 0x1312, 0x10DE, "GRID T4-2A" }, + { 0x1EB8, 0x1313, 0x10DE, "GRID T4-4A" }, + { 0x1EB8, 0x1314, 0x10DE, "GRID T4-8A" }, + { 0x1EB8, 0x1315, 0x10DE, "GRID T4-16A" }, { 0x1EB8, 0x1345, 0x10DE, "GRID T4-1B4" }, { 0x1EB8, 0x1367, 0x10DE, "GRID RTX T4-4" }, { 0x1EB8, 0x1368, 0x10DE, "GRID RTX T4-8" }, @@ -1306,9 +1431,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1EB8, 0x1375, 0x10DE, "GRID T4-16C" }, { 0x1EB8, 0x139a, 0x10DE, "GRID T4-4C" }, { 0x1EB8, 0x139b, 0x10DE, "GRID T4-8C" }, - { 0x1EB8, 0x148d, 0x10DE, "GRID RTX T4-2" }, - { 0x1EB8, 0x148e, 0x10DE, "GRID RTX T4-1" }, - { 0x1EB8, 0x148f, 0x10DE, "GRID RTX T4-0" }, { 0x20B0, 0x146f, 0x10DE, "GRID A100X-1-5C" }, { 0x20B0, 0x1470, 0x10DE, "GRID A100X-2-10C" }, { 0x20B0, 0x1471, 0x10DE, "GRID A100X-3-20C" }, @@ -1321,6 +1443,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B0, 0x1478, 0x10DE, "GRID A100X-20C" }, { 0x20B0, 0x1479, 0x10DE, "GRID A100X-40C" }, { 0x20B0, 0x160c, 0x10DE, "GRID A100X-1-5CME" }, + { 0x20B0, 0x1840, 0x10DE, "GRID A100X-1-10C" }, { 0x20B2, 0x1523, 0x10DE, "GRID A100DX-1-10C" }, { 0x20B2, 0x1524, 0x10DE, "GRID A100DX-2-20C" }, { 0x20B2, 0x1525, 0x10DE, "GRID A100DX-3-40C" }, @@ -1334,6 +1457,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B2, 0x152d, 0x10DE, "GRID A100DX-40C" }, { 0x20B2, 0x152e, 0x10DE, "GRID A100DX-80C" }, { 0x20B2, 0x160d, 0x10DE, "GRID A100DX-1-10CME" }, + { 0x20B2, 0x1841, 0x10DE, "GRID A100DX-1-20C" }, { 0x20B5, 0x1591, 0x10DE, "GRID A100D-1-10C" }, { 0x20B5, 0x1592, 0x10DE, "GRID A100D-2-20C" }, { 0x20B5, 0x1593, 0x10DE, "GRID A100D-3-40C" }, @@ -1347,6 +1471,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B5, 0x159b, 0x10DE, "GRID A100D-40C" }, { 0x20B5, 0x159c, 0x10DE, "GRID A100D-80C" }, { 0x20B5, 0x160f, 0x10DE, "GRID A100D-1-10CME" }, + { 0x20B5, 0x183e, 0x10DE, "GRID A100D-1-20C" }, { 0x20B7, 0x1589, 0x10DE, "NVIDIA A30-1-6C" }, { 0x20B7, 0x158a, 0x10DE, "NVIDIA A30-2-12C" }, { 0x20B7, 0x158b, 0x10DE, "NVIDIA A30-4-24C" }, @@ -1356,6 +1481,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B7, 0x158f, 0x10DE, "NVIDIA A30-12C" }, { 0x20B7, 0x1590, 0x10DE, "NVIDIA A30-24C" }, { 0x20B7, 0x1610, 0x10DE, "NVIDIA A30-1-6CME" }, + { 0x20B7, 0x183c, 0x10DE, "NVIDIA A30-2-12CME" }, { 0x20BF, 0x4450, 0x10DE, "GRID A100B-4C" }, { 0x20BF, 0x4451, 0x10DE, "GRID A100B-5C" }, { 0x20BF, 0x4452, 0x10DE, "GRID A100B-8C" }, @@ -1379,6 +1505,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20F1, 0x149c, 0x10DE, "GRID A100-20C" }, { 0x20F1, 0x149d, 0x10DE, "GRID A100-40C" }, { 0x20F1, 0x160e, 0x10DE, "GRID A100-1-5CME" }, + { 0x20F1, 0x183d, 0x10DE, "GRID A100-1-10C" }, { 0x20F3, 0x17b2, 0x10DE, "GRID A800DX-1-10CME" }, { 0x20F3, 0x17b3, 0x10DE, "GRID A800DX-1-10C" }, { 0x20F3, 0x17b4, 0x10DE, "GRID A800DX-2-20C" }, @@ -1392,6 +1519,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20F3, 0x17bc, 0x10DE, "GRID A800DX-20C" }, { 0x20F3, 0x17bd, 0x10DE, "GRID A800DX-40C" }, { 0x20F3, 0x17be, 0x10DE, "GRID A800DX-80C" }, + { 0x20F3, 0x1842, 0x10DE, "GRID A800DX-1-20C" }, { 0x20F5, 0x17bf, 0x10DE, "GRID A800D-1-10CME" }, { 0x20F5, 0x17c0, 0x10DE, "GRID A800D-1-10C" }, { 0x20F5, 0x17c1, 0x10DE, "GRID A800D-2-20C" }, @@ -1405,6 +1533,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20F5, 0x17c9, 0x10DE, "GRID A800D-20C" }, { 0x20F5, 0x17ca, 0x10DE, "GRID A800D-40C" }, { 0x20F5, 0x17cb, 0x10DE, "GRID A800D-80C" }, + { 0x20F5, 0x183f, 0x10DE, "GRID A800D-1-20C" }, { 0x2230, 0x14fa, 0x10DE, "NVIDIA RTXA6000-1B" }, { 0x2230, 0x14fb, 0x10DE, "NVIDIA RTXA6000-2B" }, { 0x2230, 0x14fc, 0x10DE, "NVIDIA RTXA6000-1Q" }, @@ -1417,6 +1546,16 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2230, 0x1503, 0x10DE, "NVIDIA RTXA6000-16Q" }, { 0x2230, 0x1504, 0x10DE, "NVIDIA RTXA6000-24Q" }, { 0x2230, 0x1505, 0x10DE, "NVIDIA RTXA6000-48Q" }, + { 0x2230, 0x1506, 0x10DE, "NVIDIA RTXA6000-1A" }, + { 0x2230, 0x1507, 0x10DE, "NVIDIA RTXA6000-2A" }, + { 0x2230, 0x1508, 0x10DE, "NVIDIA RTXA6000-3A" }, + { 0x2230, 0x1509, 0x10DE, "NVIDIA RTXA6000-4A" }, + { 0x2230, 0x150a, 0x10DE, "NVIDIA RTXA6000-6A" }, + { 0x2230, 0x150b, 0x10DE, "NVIDIA RTXA6000-8A" }, + { 0x2230, 0x150c, 0x10DE, "NVIDIA RTXA6000-12A" }, + { 0x2230, 0x150d, 0x10DE, "NVIDIA RTXA6000-16A" }, + { 0x2230, 0x150e, 0x10DE, "NVIDIA RTXA6000-24A" }, + { 0x2230, 0x150f, 0x10DE, "NVIDIA RTXA6000-48A" }, { 0x2230, 0x1510, 0x10DE, "NVIDIA RTXA6000-12" }, { 0x2230, 0x1511, 0x10DE, "NVIDIA RTXA6000-16" }, { 0x2230, 0x1512, 0x10DE, "NVIDIA RTXA6000-24" }, @@ -1438,6 +1577,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2231, 0x1569, 0x10DE, "NVIDIA RTXA5000-8Q" }, { 0x2231, 0x156a, 0x10DE, "NVIDIA RTXA5000-12Q" }, { 0x2231, 0x156b, 0x10DE, "NVIDIA RTXA5000-24Q" }, + { 0x2231, 0x156c, 0x10DE, "NVIDIA RTXA5000-1A" }, + { 0x2231, 0x156d, 0x10DE, "NVIDIA RTXA5000-2A" }, + { 0x2231, 0x156e, 0x10DE, "NVIDIA RTXA5000-3A" }, + { 0x2231, 0x156f, 0x10DE, "NVIDIA RTXA5000-4A" }, + { 0x2231, 0x1570, 0x10DE, "NVIDIA RTXA5000-6A" }, + { 0x2231, 0x1571, 0x10DE, "NVIDIA RTXA5000-8A" }, + { 0x2231, 0x1572, 0x10DE, "NVIDIA RTXA5000-12A" }, + { 0x2231, 0x1573, 0x10DE, "NVIDIA RTXA5000-24A" }, { 0x2231, 0x1574, 0x10DE, "NVIDIA RTXA5000-6" }, { 0x2231, 0x1575, 0x10DE, "NVIDIA RTXA5000-8" }, { 0x2231, 0x1576, 0x10DE, "NVIDIA RTXA5000-12" }, @@ -1457,6 +1604,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2233, 0x1663, 0x10DE, "NVIDIA RTXA5500-8Q" }, { 0x2233, 0x1664, 0x10DE, "NVIDIA RTXA5500-12Q" }, { 0x2233, 0x1665, 0x10DE, "NVIDIA RTXA5500-24Q" }, + { 0x2233, 0x1666, 0x10DE, "NVIDIA RTXA5500-1A" }, + { 0x2233, 0x1667, 0x10DE, "NVIDIA RTXA5500-2A" }, + { 0x2233, 0x1668, 0x10DE, "NVIDIA RTXA5500-3A" }, + { 0x2233, 0x1669, 0x10DE, "NVIDIA RTXA5500-4A" }, + { 0x2233, 0x166a, 0x10DE, "NVIDIA RTXA5500-6A" }, + { 0x2233, 0x166b, 0x10DE, "NVIDIA RTXA5500-8A" }, + { 0x2233, 0x166c, 0x10DE, "NVIDIA RTXA5500-12A" }, + { 0x2233, 0x166d, 0x10DE, "NVIDIA RTXA5500-24A" }, { 0x2233, 0x166e, 0x10DE, "NVIDIA RTXA5500-6" }, { 0x2233, 0x166f, 0x10DE, "NVIDIA RTXA5500-8" }, { 0x2233, 0x1670, 0x10DE, "NVIDIA RTXA5500-12" }, @@ -1478,6 +1633,16 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2235, 0x14de, 0x10DE, "NVIDIA A40-16Q" }, { 0x2235, 0x14df, 0x10DE, "NVIDIA A40-24Q" }, { 0x2235, 0x14e0, 0x10DE, "NVIDIA A40-48Q" }, + { 0x2235, 0x14e1, 0x10DE, "NVIDIA A40-1A" }, + { 0x2235, 0x14e2, 0x10DE, "NVIDIA A40-2A" }, + { 0x2235, 0x14e3, 0x10DE, "NVIDIA A40-3A" }, + { 0x2235, 0x14e4, 0x10DE, "NVIDIA A40-4A" }, + { 0x2235, 0x14e5, 0x10DE, "NVIDIA A40-6A" }, + { 0x2235, 0x14e6, 0x10DE, "NVIDIA A40-8A" }, + { 0x2235, 0x14e7, 0x10DE, "NVIDIA A40-12A" }, + { 0x2235, 0x14e8, 0x10DE, "NVIDIA A40-16A" }, + { 0x2235, 0x14e9, 0x10DE, "NVIDIA A40-24A" }, + { 0x2235, 0x14ea, 0x10DE, "NVIDIA A40-48A" }, { 0x2235, 0x14eb, 0x10DE, "NVIDIA A40-12" }, { 0x2235, 0x14ec, 0x10DE, "NVIDIA A40-16" }, { 0x2235, 0x14ed, 0x10DE, "NVIDIA A40-24" }, @@ -1505,6 +1670,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2236, 0x14bd, 0x10DE, "NVIDIA A10-8Q" }, { 0x2236, 0x14be, 0x10DE, "NVIDIA A10-12Q" }, { 0x2236, 0x14bf, 0x10DE, "NVIDIA A10-24Q" }, + { 0x2236, 0x14c0, 0x10DE, "NVIDIA A10-1A" }, + { 0x2236, 0x14c1, 0x10DE, "NVIDIA A10-2A" }, + { 0x2236, 0x14c2, 0x10DE, "NVIDIA A10-3A" }, + { 0x2236, 0x14c3, 0x10DE, "NVIDIA A10-4A" }, + { 0x2236, 0x14c4, 0x10DE, "NVIDIA A10-6A" }, + { 0x2236, 0x14c5, 0x10DE, "NVIDIA A10-8A" }, + { 0x2236, 0x14c6, 0x10DE, "NVIDIA A10-12A" }, + { 0x2236, 0x14c7, 0x10DE, "NVIDIA A10-24A" }, { 0x2236, 0x14c8, 0x10DE, "NVIDIA A10-6" }, { 0x2236, 0x14c9, 0x10DE, "NVIDIA A10-8" }, { 0x2236, 0x14ca, 0x10DE, "NVIDIA A10-12" }, @@ -1536,6 +1709,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2237, 0x1631, 0x10DE, "NVIDIA A10G-8Q" }, { 0x2237, 0x1632, 0x10DE, "NVIDIA A10G-12Q" }, { 0x2237, 0x1633, 0x10DE, "NVIDIA A10G-24Q" }, + { 0x2237, 0x1634, 0x10DE, "NVIDIA A10G-1A" }, + { 0x2237, 0x1635, 0x10DE, "NVIDIA A10G-2A" }, + { 0x2237, 0x1636, 0x10DE, "NVIDIA A10G-3A" }, + { 0x2237, 0x1637, 0x10DE, "NVIDIA A10G-4A" }, + { 0x2237, 0x1638, 0x10DE, "NVIDIA A10G-6A" }, + { 0x2237, 0x1639, 0x10DE, "NVIDIA A10G-8A" }, + { 0x2237, 0x163a, 0x10DE, "NVIDIA A10G-12A" }, + { 0x2237, 0x163b, 0x10DE, "NVIDIA A10G-24A" }, { 0x2237, 0x1810, 0x10DE, "NVIDIA GeForce RTX 3050" }, { 0x2237, 0x1811, 0x10DE, "NVIDIA GeForce RTX 3060" }, { 0x2238, 0x16a3, 0x10DE, "NVIDIA A10M-1B" }, @@ -1546,6 +1727,12 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2238, 0x16a8, 0x10DE, "NVIDIA A10M-5Q" }, { 0x2238, 0x16a9, 0x10DE, "NVIDIA A10M-10Q" }, { 0x2238, 0x16aa, 0x10DE, "NVIDIA A10M-20Q" }, + { 0x2238, 0x16ab, 0x10DE, "NVIDIA A10M-1A" }, + { 0x2238, 0x16ac, 0x10DE, "NVIDIA A10M-2A" }, + { 0x2238, 0x16ad, 0x10DE, "NVIDIA A10M-4A" }, + { 0x2238, 0x16ae, 0x10DE, "NVIDIA A10M-5A" }, + { 0x2238, 0x16af, 0x10DE, "NVIDIA A10M-10A" }, + { 0x2238, 0x16b0, 0x10DE, "NVIDIA A10M-20A" }, { 0x2238, 0x16b1, 0x10DE, "NVIDIA A10M-2" }, { 0x2238, 0x16b2, 0x10DE, "NVIDIA A10M-4" }, { 0x2238, 0x16b3, 0x10DE, "NVIDIA A10M-5" }, @@ -1556,6 +1743,21 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" }, { 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" }, { 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" }, + { 0x2322, 0x17e2, 0x10DE, "NVIDIA H800-1-10CME" }, + { 0x2322, 0x17e3, 0x10DE, "NVIDIA H800-1-10C" }, + { 0x2322, 0x17e4, 0x10DE, "NVIDIA H800-2-20C" }, + { 0x2322, 0x17e5, 0x10DE, "NVIDIA H800-3-40C" }, + { 0x2322, 0x17e6, 0x10DE, "NVIDIA H800-4-40C" }, + { 0x2322, 0x17e7, 0x10DE, "NVIDIA H800-7-80C" }, + { 0x2322, 0x17e8, 0x10DE, "NVIDIA H800-4C" }, + { 0x2322, 0x17e9, 0x10DE, "NVIDIA H800-5C" }, + { 0x2322, 0x17ea, 0x10DE, "NVIDIA H800-8C" }, + { 0x2322, 0x17eb, 0x10DE, "NVIDIA H800-10C" }, + { 0x2322, 0x17ec, 0x10DE, "NVIDIA H800-16C" }, + { 0x2322, 0x17ed, 0x10DE, "NVIDIA H800-20C" }, + { 0x2322, 0x17ee, 0x10DE, "NVIDIA H800-40C" }, + { 0x2322, 0x17ef, 0x10DE, "NVIDIA H800-80C" }, + { 0x2322, 0x1845, 0x10DE, "NVIDIA H800-1-20C" }, { 0x2331, 0x16d3, 0x10DE, "NVIDIA H100-1-10C" }, { 0x2331, 0x16d4, 0x10DE, "NVIDIA H100-2-20C" }, { 0x2331, 0x16d5, 0x10DE, "NVIDIA H100-3-40C" }, @@ -1570,6 +1772,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2331, 0x16de, 0x10DE, "NVIDIA H100-80C" }, { 0x2331, 0x1798, 0x10DE, "NVIDIA H100-5C" }, { 0x2331, 0x17f0, 0x10DE, "NVIDIA H100-1-10CME" }, + { 0x2331, 0x1844, 0x10DE, "NVIDIA H100-1-20C" }, { 0x25B6, 0x159d, 0x10DE, "NVIDIA A16-1B" }, { 0x25B6, 0x159e, 0x10DE, "NVIDIA A16-2B" }, { 0x25B6, 0x159f, 0x10DE, "NVIDIA A16-1Q" }, @@ -1577,6 +1780,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25B6, 0x1601, 0x10DE, "NVIDIA A16-4Q" }, { 0x25B6, 0x1602, 0x10DE, "NVIDIA A16-8Q" }, { 0x25B6, 0x1603, 0x10DE, "NVIDIA A16-16Q" }, + { 0x25B6, 0x1604, 0x10DE, "NVIDIA A16-1A" }, + { 0x25B6, 0x1605, 0x10DE, "NVIDIA A16-2A" }, + { 0x25B6, 0x1606, 0x10DE, "NVIDIA A16-4A" }, + { 0x25B6, 0x1607, 0x10DE, "NVIDIA A16-8A" }, + { 0x25B6, 0x1608, 0x10DE, "NVIDIA A16-16A" }, { 0x25B6, 0x1609, 0x10DE, "NVIDIA A16-4C" }, { 0x25B6, 0x160a, 0x10DE, "NVIDIA A16-8C" }, { 0x25B6, 0x160b, 0x10DE, "NVIDIA A16-16C" }, @@ -1587,6 +1795,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25B6, 0x164a, 0x10DE, "NVIDIA A2-4Q" }, { 0x25B6, 0x164b, 0x10DE, "NVIDIA A2-8Q" }, { 0x25B6, 0x164c, 0x10DE, "NVIDIA A2-16Q" }, + { 0x25B6, 0x164d, 0x10DE, "NVIDIA A2-1A" }, + { 0x25B6, 0x164e, 0x10DE, "NVIDIA A2-2A" }, + { 0x25B6, 0x164f, 0x10DE, "NVIDIA A2-4A" }, + { 0x25B6, 0x1650, 0x10DE, "NVIDIA A2-8A" }, + { 0x25B6, 0x1651, 0x10DE, "NVIDIA A2-16A" }, { 0x25B6, 0x1652, 0x10DE, "NVIDIA A2-4" }, { 0x25B6, 0x1653, 0x10DE, "NVIDIA A2-8" }, { 0x25B6, 0x1654, 0x10DE, "NVIDIA A2-16" }, @@ -1605,6 +1818,16 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B1, 0x1711, 0x10DE, "NVIDIA RTX6000-Ada-16Q" }, { 0x26B1, 0x1712, 0x10DE, "NVIDIA RTX6000-Ada-24Q" }, { 0x26B1, 0x1713, 0x10DE, "NVIDIA RTX6000-Ada-48Q" }, + { 0x26B1, 0x1714, 0x10DE, "NVIDIA RTX6000-Ada-1A" }, + { 0x26B1, 0x1715, 0x10DE, "NVIDIA RTX6000-Ada-2A" }, + { 0x26B1, 0x1716, 0x10DE, "NVIDIA RTX6000-Ada-3A" }, + { 0x26B1, 0x1717, 0x10DE, "NVIDIA RTX6000-Ada-4A" }, + { 0x26B1, 0x1718, 0x10DE, "NVIDIA RTX6000-Ada-6A" }, + { 0x26B1, 0x1719, 0x10DE, "NVIDIA RTX6000-Ada-8A" }, + { 0x26B1, 0x171a, 0x10DE, "NVIDIA RTX6000-Ada-12A" }, + { 0x26B1, 0x171b, 0x10DE, "NVIDIA RTX6000-Ada-16A" }, + { 0x26B1, 0x171c, 0x10DE, "NVIDIA RTX6000-Ada-24A" }, + { 0x26B1, 0x171d, 0x10DE, "NVIDIA RTX6000-Ada-48A" }, { 0x26B1, 0x171e, 0x10DE, "NVIDIA RTX6000-Ada-1" }, { 0x26B1, 0x171f, 0x10DE, "NVIDIA RTX6000-Ada-2" }, { 0x26B1, 0x1720, 0x10DE, "NVIDIA RTX6000-Ada-3" }, @@ -1634,6 +1857,16 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B5, 0x1776, 0x10DE, "NVIDIA L40-16Q" }, { 0x26B5, 0x1777, 0x10DE, "NVIDIA L40-24Q" }, { 0x26B5, 0x1778, 0x10DE, "NVIDIA L40-48Q" }, + { 0x26B5, 0x1779, 0x10DE, "NVIDIA L40-1A" }, + { 0x26B5, 0x177a, 0x10DE, "NVIDIA L40-2A" }, + { 0x26B5, 0x177b, 0x10DE, "NVIDIA L40-3A" }, + { 0x26B5, 0x177c, 0x10DE, "NVIDIA L40-4A" }, + { 0x26B5, 0x177d, 0x10DE, "NVIDIA L40-6A" }, + { 0x26B5, 0x177e, 0x10DE, "NVIDIA L40-8A" }, + { 0x26B5, 0x177f, 0x10DE, "NVIDIA L40-12A" }, + { 0x26B5, 0x1780, 0x10DE, "NVIDIA L40-16A" }, + { 0x26B5, 0x1781, 0x10DE, "NVIDIA L40-24A" }, + { 0x26B5, 0x1782, 0x10DE, "NVIDIA L40-48A" }, { 0x26B5, 0x1783, 0x10DE, "NVIDIA L40-1" }, { 0x26B5, 0x1784, 0x10DE, "NVIDIA L40-2" }, { 0x26B5, 0x1785, 0x10DE, "NVIDIA L40-3" }, @@ -1663,6 +1896,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B8, 0x1755, 0x10DE, "NVIDIA L40G-8Q" }, { 0x26B8, 0x1756, 0x10DE, "NVIDIA L40G-12Q" }, { 0x26B8, 0x1757, 0x10DE, "NVIDIA L40G-24Q" }, + { 0x26B8, 0x1758, 0x10DE, "NVIDIA L40G-1A" }, + { 0x26B8, 0x1759, 0x10DE, "NVIDIA L40G-2A" }, + { 0x26B8, 0x175a, 0x10DE, "NVIDIA L40G-3A" }, + { 0x26B8, 0x175b, 0x10DE, "NVIDIA L40G-4A" }, + { 0x26B8, 0x175c, 0x10DE, "NVIDIA L40G-6A" }, + { 0x26B8, 0x175d, 0x10DE, "NVIDIA L40G-8A" }, + { 0x26B8, 0x175e, 0x10DE, "NVIDIA L40G-12A" }, + { 0x26B8, 0x175f, 0x10DE, "NVIDIA L40G-24A" }, { 0x26B8, 0x1760, 0x10DE, "NVIDIA L40G-1" }, { 0x26B8, 0x1761, 0x10DE, "NVIDIA L40G-2" }, { 0x26B8, 0x1762, 0x10DE, "NVIDIA L40G-3" }, @@ -1688,6 +1929,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x27B8, 0x1736, 0x10DE, "NVIDIA L4-8Q" }, { 0x27B8, 0x1737, 0x10DE, "NVIDIA L4-12Q" }, { 0x27B8, 0x1738, 0x10DE, "NVIDIA L4-24Q" }, + { 0x27B8, 0x1739, 0x10DE, "NVIDIA L4-1A" }, + { 0x27B8, 0x173a, 0x10DE, "NVIDIA L4-2A" }, + { 0x27B8, 0x173b, 0x10DE, "NVIDIA L4-3A" }, + { 0x27B8, 0x173c, 0x10DE, "NVIDIA L4-4A" }, + { 0x27B8, 0x173d, 0x10DE, "NVIDIA L4-6A" }, + { 0x27B8, 0x173e, 0x10DE, "NVIDIA L4-8A" }, + { 0x27B8, 0x173f, 0x10DE, "NVIDIA L4-12A" }, + { 0x27B8, 0x1740, 0x10DE, "NVIDIA L4-24A" }, { 0x27B8, 0x1741, 0x10DE, "NVIDIA L4-1" }, { 0x27B8, 0x1742, 0x10DE, "NVIDIA L4-2" }, { 0x27B8, 0x1743, 0x10DE, "NVIDIA L4-3" }, diff --git a/src/nvidia/generated/g_object_nvoc.h b/src/nvidia/generated/g_object_nvoc.h index 6b1f5ebb40..c4b4fb49d8 100644 --- a/src/nvidia/generated/g_object_nvoc.h +++ b/src/nvidia/generated/g_object_nvoc.h @@ -166,10 +166,10 @@ static inline struct Object *objGetDirectParent(struct Object *pObj) { #undef PRIVATE_FIELD -// -// IP versioning definitions are temporary until NVOC halspec support is -// finished. -// +// +// IP versioning definitions are temporary until NVOC halspec support is +// finished. +// // IP_VERSION format as defined by the hardware engines. // A _MAJOR value of 0 means the object has no version number. // diff --git a/src/nvidia/generated/g_objgpumon_nvoc.h b/src/nvidia/generated/g_objgpumon_nvoc.h index b9ed79ebb6..c6c7e246b2 100644 --- a/src/nvidia/generated/g_objgpumon_nvoc.h +++ b/src/nvidia/generated/g_objgpumon_nvoc.h @@ -42,6 +42,7 @@ extern "C" { #include "gpu/gpu.h" #include "gpu/eng_state.h" +#include "kernel/gpu/fifo/kernel_fifo.h" #include "ctrl/ctrl2080/ctrl2080perf.h" @@ -118,18 +119,18 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON**, Dynamic*, NvU32); #define gpumonStatePostLoad(pGpu, pEngstate, arg0) gpumonStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define gpumonConstructEngine(pGpu, pEngstate, arg0) gpumonConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define gpumonIsPresent(pGpu, pEngstate) gpumonIsPresent_DISPATCH(pGpu, pEngstate) -void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3); +void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName); #ifdef __nvoc_objgpumon_h_disabled -static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3) { +static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName) { NV_ASSERT_FAILED_PRECOMP("OBJGPUMON was disabled!"); } #else //__nvoc_objgpumon_h_disabled -#define gpumonGetContextProcessInfo(pGpu, pGpumon, arg0, arg1, arg2, arg3) gpumonGetContextProcessInfo_GM107(pGpu, pGpumon, arg0, arg1, arg2, arg3) +#define gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo_GM107(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) #endif //__nvoc_objgpumon_h_disabled -#define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, arg0, arg1, arg2, arg3) gpumonGetContextProcessInfo(pGpu, pGpumon, arg0, arg1, arg2, arg3) +#define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) static inline NV_STATUS gpumonStateLoad_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return pEngstate->__gpumonStateLoad__(pGpu, pEngstate, arg0); diff --git a/src/nvidia/generated/g_objtmr_nvoc.c b/src/nvidia/generated/g_objtmr_nvoc.c index 833f660114..0a40a369d8 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.c +++ b/src/nvidia/generated/g_objtmr_nvoc.c @@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTMR = /*pExportInfo=*/ &__nvoc_export_info_OBJTMR }; -static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[166]) { +static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[167]) { tmrRegisterIntrService(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_IntrService.offset), pRecords); } @@ -247,10 +247,7 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__tmrClearInterrupt__ = &tmrClearInterrupt_IMPL; // Hal function -- tmrServiceInterrupt - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_56cd7a; - } + pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_56cd7a; pThis->__tmrConstructEngine__ = &tmrConstructEngine_IMPL; @@ -265,59 +262,53 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__tmrStateDestroy__ = &tmrStateDestroy_IMPL; // Hal function -- tmrSetCurrentTime - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GH100; - } + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GV100; } // Hal function -- tmrGetTimeEx - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GH100; + } + else { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GH100; - } + pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GM107; } // Hal function -- tmrSetCountdownIntrDisable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_GM200; + pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_56cd7a; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_56cd7a; + pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_GM200; } // Hal function -- tmrSetCountdown - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__tmrSetCountdown__ = &tmrSetCountdown_TU102; + pThis->__tmrSetCountdown__ = &tmrSetCountdown_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__tmrSetCountdown__ = &tmrSetCountdown_GH100; + pThis->__tmrSetCountdown__ = &tmrSetCountdown_TU102; } // Hal function -- tmrGrTickFreqChange - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_GM107; + pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_46f6a7; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_46f6a7; + pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_GM107; } // Hal function -- tmrGetGpuPtimerOffset @@ -325,7 +316,7 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal { pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else { pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_GA100; } diff --git a/src/nvidia/generated/g_objtmr_nvoc.h b/src/nvidia/generated/g_objtmr_nvoc.h index 2958647ffe..6cd1dcef98 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.h +++ b/src/nvidia/generated/g_objtmr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -58,16 +58,26 @@ extern "C" { // Callback scheduled without any explicit flags set. #define TMR_FLAGS_NONE 0x00000000 +// // Automatically reschedule the callback, so that it repeats. // Otherwise, callback is scheduled for one-shot execution. +// #define TMR_FLAG_RECUR NVBIT(0) +// // Indicate that the implementation of the callback function will/can release // a GPU semaphore. This allows fifoIdleChannels to query this information, // and hence not bail out early if channels are blocked on semaphores that // will in fact be released. - // !!NOTE: This is OBSOLETE, it should be moved directly to FIFO, where it's needed +// !!NOTE: This is OBSOLETE, it should be moved directly to FIFO, where it's needed +// #define TMR_FLAG_RELEASE_SEMAPHORE NVBIT(1) #define TMR_FLAG_OS_TIMER_QUEUED NVBIT(2) +// +// Normally, it should not be necessary to use the TMR_FLAG_USE_OS_TIMER flag, +// because the OS timer is selected automatically by the default +// PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS setting. +// Note that the OS timer is not supported in all environments (such as GSP-RM). +// #define TMR_FLAG_USE_OS_TIMER NVBIT(3) #define TMR_GET_GPU(p) ENG_GET_GPU(p) @@ -235,6 +245,7 @@ struct OBJTMR { NvBool bAlarmIntrEnabled; PENG_INFO_LINK_NODE infoList; struct OBJREFCNT *pGrTickFreqRefcnt; + NvU64 sysTimerOffsetNs; }; #ifndef __NVOC_CLASS_OBJTMR_TYPEDEF__ @@ -676,19 +687,19 @@ static inline NV_STATUS tmrEventCreateOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pE #define tmrEventCreateOSTimer_HAL(pTmr, pEvent) tmrEventCreateOSTimer(pTmr, pEvent) -NV_STATUS tmrEventScheduleAbsOSTimer_OSTIMER(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeAbs); +NV_STATUS tmrEventScheduleRelOSTimer_OSTIMER(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeRelNs); #ifdef __nvoc_objtmr_h_disabled -static inline NV_STATUS tmrEventScheduleAbsOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeAbs) { +static inline NV_STATUS tmrEventScheduleRelOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeRelNs) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_objtmr_h_disabled -#define tmrEventScheduleAbsOSTimer(pTmr, pEvent, timeAbs) tmrEventScheduleAbsOSTimer_OSTIMER(pTmr, pEvent, timeAbs) +#define tmrEventScheduleRelOSTimer(pTmr, pEvent, timeRelNs) tmrEventScheduleRelOSTimer_OSTIMER(pTmr, pEvent, timeRelNs) #endif //__nvoc_objtmr_h_disabled -#define tmrEventScheduleAbsOSTimer_HAL(pTmr, pEvent, timeAbs) tmrEventScheduleAbsOSTimer(pTmr, pEvent, timeAbs) +#define tmrEventScheduleRelOSTimer_HAL(pTmr, pEvent, timeRelNs) tmrEventScheduleRelOSTimer(pTmr, pEvent, timeRelNs) NV_STATUS tmrEventServiceOSTimerCallback_OSTIMER(OBJGPU *pGpu, struct OBJTMR *pTmr, PTMR_EVENT pEvent); @@ -732,9 +743,9 @@ static inline NV_STATUS tmrEventDestroyOSTimer(struct OBJTMR *pTmr, PTMR_EVENT p #define tmrEventDestroyOSTimer_HAL(pTmr, pEvent) tmrEventDestroyOSTimer(pTmr, pEvent) -void tmrRegisterIntrService_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[166]); +void tmrRegisterIntrService_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[167]); -static inline void tmrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[166]) { +static inline void tmrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[167]) { pTmr->__tmrRegisterIntrService__(pGpu, pTmr, pRecords); } diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.c b/src/nvidia/generated/g_os_desc_mem_nvoc.c index 7ab3b2ee36..fc4d7eee0b 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.c +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_osdescIsReady(struct OsDescMemory *pMemory, return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_osdescCheckCopyPermissions(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_osdescCheckCopyPermissions(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_osdescPreDestruct(struct OsDescMemory *pResource) { diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.h b/src/nvidia/generated/g_os_desc_mem_nvoc.h index 163206d01a..2aee14bf66 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.h +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.h @@ -72,7 +72,7 @@ struct OsDescMemory { NV_STATUS (*__osdescControlFilter__)(struct OsDescMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescControlSerialization_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescIsReady__)(struct OsDescMemory *, NvBool); - NV_STATUS (*__osdescCheckCopyPermissions__)(struct OsDescMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__osdescCheckCopyPermissions__)(struct OsDescMemory *, struct OBJGPU *, struct Device *); void (*__osdescPreDestruct__)(struct OsDescMemory *); NV_STATUS (*__osdescIsDuplicate__)(struct OsDescMemory *, NvHandle, NvBool *); void (*__osdescControlSerialization_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -127,7 +127,7 @@ NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory**, Dynamic*, NvU32, CALL_CO #define osdescControlFilter(pResource, pCallContext, pParams) osdescControlFilter_DISPATCH(pResource, pCallContext, pParams) #define osdescControlSerialization_Prologue(pResource, pCallContext, pParams) osdescControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define osdescIsReady(pMemory, bCopyConstructorContext) osdescIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define osdescCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) osdescCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define osdescCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) osdescCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define osdescPreDestruct(pResource) osdescPreDestruct_DISPATCH(pResource) #define osdescIsDuplicate(pMemory, hMemory, pDuplicate) osdescIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define osdescControlSerialization_Epilogue(pResource, pCallContext, pParams) osdescControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -211,8 +211,8 @@ static inline NV_STATUS osdescIsReady_DISPATCH(struct OsDescMemory *pMemory, NvB return pMemory->__osdescIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS osdescCheckCopyPermissions_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__osdescCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS osdescCheckCopyPermissions_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__osdescCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void osdescPreDestruct_DISPATCH(struct OsDescMemory *pResource) { diff --git a/src/nvidia/generated/g_os_nvoc.h b/src/nvidia/generated/g_os_nvoc.h index abc5ce83b3..80dbe2e615 100644 --- a/src/nvidia/generated/g_os_nvoc.h +++ b/src/nvidia/generated/g_os_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -69,19 +69,19 @@ typedef struct OBJOS OBJOS; -// -// The OS module should NOT depend on RM modules. The only exception is +// +// The OS module should NOT depend on RM modules. The only exception is // core/core.h. -// -// DO NOT ADD INCLUDES TO RM MODULE HEADERS FROM THIS FILE. OS module should be -// a leaf module. Dependencies on RM headers in this files results in circular +// +// DO NOT ADD INCLUDES TO RM MODULE HEADERS FROM THIS FILE. OS module should be +// a leaf module. Dependencies on RM headers in this files results in circular // dependencies as most modules depend on the OS module. -// -// Ideally, all types used by the OS module's interface are from the SDK, -// resman/interface or self-contained within the OS module header. For now, +// +// Ideally, all types used by the OS module's interface are from the SDK, +// resman/interface or self-contained within the OS module header. For now, // since the OS module depends on a few RM internal types we forward declare to -// avoid the need to pull in headers from across RM. -// +// avoid the need to pull in headers from across RM. +// typedef struct SYS_STATIC_CONFIG SYS_STATIC_CONFIG; typedef struct MEMORY_DESCRIPTOR MEMORY_DESCRIPTOR; typedef struct IOVAMAPPING *PIOVAMAPPING; @@ -95,10 +95,10 @@ typedef struct _GUID *LPGUID; // // Forward declare OS_GPU_INFO type -// +// // TODO - We shouldn't need a special definition per-OS. OS implementations // should use a consistent type -// +// typedef struct nv_state_t OS_GPU_INFO; /* ------------------------ OS Interface ------------------------------------ */ @@ -198,7 +198,7 @@ typedef enum _OS_PEX_RECOVERY_STATUS #define OS_BUG_CHECK_BUGCODE_ECC_DBE (3) #define OS_BUG_CHECK_BUGCODE_NVLINK_TL_ERR (4) #define OS_BUG_CHECK_BUGCODE_PAGED_SEGMENT (5) -#define OS_BUG_CHECK_BUGCODE_BDOD_ON_ASSERT (6) +#define OS_BUG_CHECK_BUGCODE_BSOD_ON_ASSERT (6) #define OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW (7) #define OS_BUG_CHECK_BUGCODE_LAST OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW @@ -216,7 +216,7 @@ typedef enum _OS_PEX_RECOVERY_STATUS // Flags needed by OSAllocPagesNode #define OS_ALLOC_PAGES_NODE_NONE 0x0 -#define OS_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1 +#define OS_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1 // // Structures for osPackageRegistry and osUnpackageRegistry @@ -276,7 +276,6 @@ typedef NV_STATUS NV_FORCERESULTCHECK OSLockMem(MEMORY_DESCRIPTOR *); typedef NV_STATUS OSUnlockMem(MEMORY_DESCRIPTOR *); typedef NV_STATUS NV_FORCERESULTCHECK OSMapGPU(OBJGPU *, RS_PRIV_LEVEL, NvU64, NvU64, NvU32, NvP64 *, NvP64 *); typedef void OSUnmapGPU(OS_GPU_INFO *, RS_PRIV_LEVEL, NvP64, NvU64, NvP64); -typedef NV_STATUS NV_FORCERESULTCHECK OSDeviceClassToDeviceName(NvU32, NvU8 *); typedef NV_STATUS NV_FORCERESULTCHECK OSNotifyEvent(OBJGPU *, PEVENTNOTIFICATION, NvU32, NvU32, NV_STATUS); typedef NV_STATUS OSReadRegistryString(OBJGPU *, const char *, NvU8 *, NvU32 *); typedef NV_STATUS OSWriteRegistryBinary(OBJGPU *, const char *, NvU8 *, NvU32); @@ -299,7 +298,7 @@ typedef NV_STATUS OSAllocAcquirePage(NvU64); typedef NV_STATUS OSAllocReleasePage(NvU64); typedef NvU32 OSGetPageRefcount(NvU64); typedef NvU32 OSCountTailPages(NvU64); -typedef NvU32 OSGetPageSize(void); +typedef NvU64 OSGetPageSize(void); // We use osAcquireRmSema to catch "unported" sema code to new lock model @@ -392,17 +391,17 @@ typedef NV_STATUS OSQueueSystemWorkItem(OSSystemWorkItemFunction, void *); // MXM ACPI calls NV_STATUS osCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *); NV_STATUS osCallACPI_DDC(OBJGPU *, NvU32, NvU8*,NvU32*, NvBool); -typedef NV_STATUS OSCallACPI_BCL(OBJGPU *, NvU32, NvU32 *, NvU16 *); +NV_STATUS osCallACPI_BCL(OBJGPU *, NvU32, NvU32 *, NvU16 *); // Display MUX ACPI calls NV_STATUS osCallACPI_MXDS(OBJGPU *, NvU32, NvU32 *); NV_STATUS osCallACPI_MXDM(OBJGPU *, NvU32, NvU32 *); NV_STATUS osCallACPI_MXID(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_LRST(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_LRST(OBJGPU *, NvU32, NvU32 *); // Hybrid GPU ACPI calls -typedef NV_STATUS OSCallACPI_NVHG_GPUON(OBJGPU *, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_GPUOFF(OBJGPU *, NvU32 *); +NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *, NvU32 *); +NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_GPUSTA(OBJGPU *, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_MXDS(OBJGPU *, NvU32, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_MXMX(OBJGPU *, NvU32, NvU32 *); @@ -412,16 +411,11 @@ typedef NV_STATUS OSCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *); NV_STATUS osCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *); // Tegra ACPI calls -typedef NV_STATUS OSCallACPI_SUB(OBJGPU *, NvU8 *, NvU32 *); -typedef NV_STATUS OSCallACPI_ON(OBJGPU *, NvU32); -typedef NV_STATUS OSCallACPI_OFF(OBJGPU *, NvU32); - -// Notebook Power Balancing ACPI calls -typedef NV_STATUS OSCallACPI_NBPS(OBJGPU *, NvU8 *, NvU32 *); -typedef NV_STATUS OSCallACPI_NBSL(OBJGPU *, NvU32); +NV_STATUS osCallACPI_ON(OBJGPU *, NvU32); +NV_STATUS osCallACPI_OFF(OBJGPU *, NvU32); // Optimus WMI ACPI calls -typedef NV_STATUS OSCallACPI_OPTM_GPUON(OBJGPU *); +NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *); // Generic ACPI _DSM call NV_STATUS osCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, @@ -631,24 +625,14 @@ struct OBJOS { OSSimEscapeReadBuffer *osSimEscapeReadBuffer; OSRmInitRm *osRmInitRm; OSGetSimulationMode *osGetSimulationMode; - OSCallACPI_BCL *osCallACPI_BCL; - OSCallACPI_LRST *osCallACPI_LRST; - OSCallACPI_NVHG_GPUON *osCallACPI_NVHG_GPUON; - OSCallACPI_NVHG_GPUOFF *osCallACPI_NVHG_GPUOFF; OSCallACPI_NVHG_GPUSTA *osCallACPI_NVHG_GPUSTA; OSCallACPI_NVHG_MXDS *osCallACPI_NVHG_MXDS; OSCallACPI_NVHG_MXMX *osCallACPI_NVHG_MXMX; OSCallACPI_NVHG_DOS *osCallACPI_NVHG_DOS; OSCallACPI_NVHG_DCS *osCallACPI_NVHG_DCS; - OSCallACPI_SUB *osCallACPI_SUB; - OSCallACPI_ON *osCallACPI_ON; - OSCallACPI_OFF *osCallACPI_OFF; OSGetUefiVariable *osGetUefiVariable; OSCheckCallback *osCheckCallback; OSRCCallback *osRCCallback; - OSCallACPI_NBPS *osCallACPI_NBPS; - OSCallACPI_NBSL *osCallACPI_NBSL; - OSCallACPI_OPTM_GPUON *osCallACPI_OPTM_GPUON; OSSetupVBlank *osSetupVBlank; OSPexRecoveryCallback *osPexRecoveryCallback; OSInternalReserveAllocCallback *osInternalReserveAllocCallback; @@ -735,6 +719,14 @@ OSDeleteRecordForCrashLog osDeleteRecordForCrashLog; NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo); NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo); NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo); +NV_STATUS osTegraSocBpmpSendMrq(OS_GPU_INFO *pOsGpuInfo, + NvU32 mrq, + const void *pRequestData, + NvU32 requestDataSize, + void *pResponseData, + NvU32 responseDataSize, + NvS32 *pRet, + NvS32 *pApiRet); NV_STATUS osTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *pTegraImpImportData); NV_STATUS osTegraSocEnableDisableRfl(OS_GPU_INFO *pOsGpuInfo, NvBool bEnable); NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo, @@ -813,6 +805,10 @@ NV_STATUS osGetAtsTargetAddressRange(OBJGPU *pGpu, NV_STATUS osGetFbNumaInfo(OBJGPU *pGpu, NvU64 *pAddrPhys, NvS32 *pNodeId); +NV_STATUS osGetEgmInfo(OBJGPU *pGpu, + NvU64 *pPhysAddr, + NvU64 *pSize, + NvS32 *pNodeId); NV_STATUS osGetForcedNVLinkConnection(OBJGPU *pGpu, NvU32 maxLinks, NvU32 *pLinkConnection); @@ -832,6 +828,7 @@ NV_STATUS osVgpuVfioWake(void *waitQueue); NV_STATUS osVgpuInjectInterrupt(void *pArg1); NV_STATUS osVgpuRegisterMdev(OS_GPU_INFO *pArg1); NV_STATUS osIsVgpuVfioPresent(void); +NV_STATUS osIsVfioPciCorePresent(void); NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1); NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection); NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection); @@ -894,7 +891,7 @@ NV_STATUS osTegraDceUnregisterIpcClient(NvU32 clientId); // CLKWHICH, avoids upwards dependency from OS interface on higher level // RM modules // -typedef NvU32 OS_CLKWHICH; +typedef NvU32 OS_CLKWHICH; NV_STATUS osTegraSocEnableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM); NV_STATUS osTegraSocDisableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM); @@ -1102,6 +1099,18 @@ NV_STATUS osGetTegraNumDpAuxInstances(OS_GPU_INFO *pArg1, NvU32 osTegraSocFuseRegRead(NvU32 addr); +typedef void (*osTegraTsecCbFunc)(void*, void*); + +NvU32 osTegraSocTsecSendCmd(void* cmd, osTegraTsecCbFunc cbFunc, void* cbContext); + +NvU32 osTegraSocTsecEventRegister(osTegraTsecCbFunc cbFunc, void* cbContext, NvBool isInitEvent); + +NvU32 osTegraSocTsecEventUnRegister(NvBool isInitEvent); + +void* osTegraSocTsecAllocMemDesc(NvU32 numBytes, NvU32 *flcnAddr); + +void osTegraSocTsecFreeMemDesc(void *memDesc); + NV_STATUS osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout); NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pArg1, NvU32, NvU32); @@ -1117,6 +1126,8 @@ NV_STATUS osGetTegraBrightnessLevel(OS_GPU_INFO *pArg1, NV_STATUS osSetTegraBrightnessLevel(OS_GPU_INFO *pArg1, NvU32 arg2); +NvBool osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo); + NvBool osIsVga(OS_GPU_INFO *pArg1, NvBool bIsGpuPrimaryDevice); @@ -1240,6 +1251,8 @@ NV_STATUS osNumaAddGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, void osNumaRemoveGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, NvU64 size, NvU32 numaNodeId); +NV_STATUS osOfflinePageAtAddress(NvU64 address); + // Os 1Hz timer callback functions NV_STATUS osInit1HzCallbacks(OBJTMR *pTmr); NV_STATUS osDestroy1HzCallbacks(OBJTMR *pTmr); @@ -1284,7 +1297,6 @@ OSEventNotificationWithInfo osEventNotificationWithInfo; OSObjectEventNotification osObjectEventNotification; OSNotifyEvent osNotifyEvent; OSFlushCpuWriteCombineBuffer osFlushCpuWriteCombineBuffer; -OSDeviceClassToDeviceName osDeviceClassToDeviceName; OSDelay osDelay; OSSpinLoop osSpinLoop; OSDelayUs osDelayUs; @@ -1460,16 +1472,16 @@ extern OSGetSimulationMode osGetSimulationMode; // Notify callback action #define NV_OS_WRITE_THEN_AWAKEN 0x00000001 -// -// Include per-OS definitions -// -// #ifdef out for nvoctrans, this hides include to system headers which +// +// Include per-OS definitions +// +// #ifdef out for nvoctrans, this hides include to system headers which // breaks the tool. -// -// TODO - we should delete the per-OS os_custom.h files exposed to -// OS-agnostic code. Cross-OS code shouldn't pull in per-OS headers or -// per-OS definitions. -// +// +// TODO - we should delete the per-OS os_custom.h files exposed to +// OS-agnostic code. Cross-OS code shouldn't pull in per-OS headers or +// per-OS definitions. +// #include "os_custom.h" #define NV_SEMA_RELEASE_SUCCEED 0 // lock released, no waiting thread to notify diff --git a/src/nvidia/generated/g_p2p_api_nvoc.h b/src/nvidia/generated/g_p2p_api_nvoc.h index 7abf23d77a..c33a4bd35b 100644 --- a/src/nvidia/generated/g_p2p_api_nvoc.h +++ b/src/nvidia/generated/g_p2p_api_nvoc.h @@ -31,6 +31,7 @@ extern "C" { #include "g_p2p_api_nvoc.h" + #ifndef _P2P_API_H_ #define _P2P_API_H_ @@ -51,6 +52,9 @@ extern "C" { #define NV_P2PAPI_ATTRIBUTES_LINK_TYPE 4:4 #define NV_P2PAPI_ATTRIBUTES_LINK_TYPE_GPA 0x0 #define NV_P2PAPI_ATTRIBUTES_LINK_TYPE_SPA 0x1 +#define NV_P2PAPI_ATTRIBUTES_REMOTE_EGM 5:5 +#define NV_P2PAPI_ATTRIBUTES_REMOTE_EGM_NO 0x0 +#define NV_P2PAPI_ATTRIBUTES_REMOTE_EGM_YES 0x1 #ifdef NVOC_P2P_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x @@ -92,6 +96,8 @@ struct P2PApi { NvU32 remoteGfid; NvU32 peerId1; NvU32 peerId2; + NvU32 egmPeerId1; + NvU32 egmPeerId2; NvU32 attributes; }; diff --git a/src/nvidia/generated/g_phys_mem_nvoc.c b/src/nvidia/generated/g_phys_mem_nvoc.c index dc561b2e74..139e5a4048 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.c +++ b/src/nvidia/generated/g_phys_mem_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_physmemIsReady(struct PhysicalMemory *pMemo return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_physmemCheckCopyPermissions(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_physmemCheckCopyPermissions(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_physmemPreDestruct(struct PhysicalMemory *pResource) { diff --git a/src/nvidia/generated/g_phys_mem_nvoc.h b/src/nvidia/generated/g_phys_mem_nvoc.h index c4b463a8fb..77c9ce4881 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.h +++ b/src/nvidia/generated/g_phys_mem_nvoc.h @@ -74,7 +74,7 @@ struct PhysicalMemory { NV_STATUS (*__physmemControlFilter__)(struct PhysicalMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemControlSerialization_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemIsReady__)(struct PhysicalMemory *, NvBool); - NV_STATUS (*__physmemCheckCopyPermissions__)(struct PhysicalMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__physmemCheckCopyPermissions__)(struct PhysicalMemory *, struct OBJGPU *, struct Device *); void (*__physmemPreDestruct__)(struct PhysicalMemory *); NV_STATUS (*__physmemIsDuplicate__)(struct PhysicalMemory *, NvHandle, NvBool *); void (*__physmemControlSerialization_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -129,7 +129,7 @@ NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory**, Dynamic*, NvU32, CAL #define physmemControlFilter(pResource, pCallContext, pParams) physmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define physmemControlSerialization_Prologue(pResource, pCallContext, pParams) physmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define physmemIsReady(pMemory, bCopyConstructorContext) physmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define physmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) physmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define physmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) physmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define physmemPreDestruct(pResource) physmemPreDestruct_DISPATCH(pResource) #define physmemIsDuplicate(pMemory, hMemory, pDuplicate) physmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define physmemControlSerialization_Epilogue(pResource, pCallContext, pParams) physmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -213,8 +213,8 @@ static inline NV_STATUS physmemIsReady_DISPATCH(struct PhysicalMemory *pMemory, return pMemory->__physmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS physmemCheckCopyPermissions_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__physmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS physmemCheckCopyPermissions_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__physmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void physmemPreDestruct_DISPATCH(struct PhysicalMemory *pResource) { diff --git a/src/nvidia/generated/g_platform_request_handler_nvoc.c b/src/nvidia/generated/g_platform_request_handler_nvoc.c new file mode 100644 index 0000000000..a3244305d8 --- /dev/null +++ b/src/nvidia/generated/g_platform_request_handler_nvoc.c @@ -0,0 +1,162 @@ +#define NVOC_PLATFORM_REQUEST_HANDLER_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_platform_request_handler_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x641a7f = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_PlatformRequestHandler; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_PlatformRequestHandler(PlatformRequestHandler*); +void __nvoc_init_funcTable_PlatformRequestHandler(PlatformRequestHandler*); +NV_STATUS __nvoc_ctor_PlatformRequestHandler(PlatformRequestHandler*); +void __nvoc_init_dataField_PlatformRequestHandler(PlatformRequestHandler*); +void __nvoc_dtor_PlatformRequestHandler(PlatformRequestHandler*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_PlatformRequestHandler; + +static const struct NVOC_RTTI __nvoc_rtti_PlatformRequestHandler_PlatformRequestHandler = { + /*pClassDef=*/ &__nvoc_class_def_PlatformRequestHandler, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_PlatformRequestHandler, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_PlatformRequestHandler_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(PlatformRequestHandler, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_PlatformRequestHandler = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_PlatformRequestHandler_PlatformRequestHandler, + &__nvoc_rtti_PlatformRequestHandler_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_PlatformRequestHandler = +{ + /*classInfo=*/ { + /*size=*/ sizeof(PlatformRequestHandler), + /*classId=*/ classId(PlatformRequestHandler), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "PlatformRequestHandler", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_PlatformRequestHandler, + /*pCastInfo=*/ &__nvoc_castinfo_PlatformRequestHandler, + /*pExportInfo=*/ &__nvoc_export_info_PlatformRequestHandler +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_PlatformRequestHandler = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_PlatformRequestHandler(PlatformRequestHandler *pThis) { + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_PlatformRequestHandler(PlatformRequestHandler *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_PlatformRequestHandler(PlatformRequestHandler *pThis) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_PlatformRequestHandler_fail_Object; + __nvoc_init_dataField_PlatformRequestHandler(pThis); + + status = __nvoc_pfmreqhndlrConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_PlatformRequestHandler_fail__init; + goto __nvoc_ctor_PlatformRequestHandler_exit; // Success + +__nvoc_ctor_PlatformRequestHandler_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_PlatformRequestHandler_fail_Object: +__nvoc_ctor_PlatformRequestHandler_exit: + + return status; +} + +static void __nvoc_init_funcTable_PlatformRequestHandler_1(PlatformRequestHandler *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_PlatformRequestHandler(PlatformRequestHandler *pThis) { + __nvoc_init_funcTable_PlatformRequestHandler_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_PlatformRequestHandler(PlatformRequestHandler *pThis) { + pThis->__nvoc_pbase_PlatformRequestHandler = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_PlatformRequestHandler(pThis); +} + +NV_STATUS __nvoc_objCreate_PlatformRequestHandler(PlatformRequestHandler **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + PlatformRequestHandler *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PlatformRequestHandler), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(PlatformRequestHandler)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PlatformRequestHandler); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_PlatformRequestHandler(pThis); + status = __nvoc_ctor_PlatformRequestHandler(pThis); + if (status != NV_OK) goto __nvoc_objCreate_PlatformRequestHandler_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_PlatformRequestHandler_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(PlatformRequestHandler)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_PlatformRequestHandler(PlatformRequestHandler **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_PlatformRequestHandler(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_platform_request_handler_nvoc.h b/src/nvidia/generated/g_platform_request_handler_nvoc.h index 76f77a91d2..74f817530a 100644 --- a/src/nvidia/generated/g_platform_request_handler_nvoc.h +++ b/src/nvidia/generated/g_platform_request_handler_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -49,12 +49,13 @@ extern "C" { #include "platform/platform_request_handler_utils.h" #include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrl2080/ctrl2080internal.h" +#include "nvfixedtypes.h" /* ------------------------ Macros ----------------------------------------- */ // // Macro to check if SW ACPI version 2X or not // -#define PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler) \ +#define PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler) \ (pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.acpiVersionSw == \ NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_2X) @@ -89,12 +90,22 @@ extern "C" { #define PFM_REQ_HNDLR_PM1_STATE_AVAIL (74U) #define PFM_REQ_HNDLR_TDP_IDX (96U) #define PFM_REQ_HNDLR_VPS_PS20_SUPPORT (97U) -#define PFM_REQ_HNDLR_RESERVED_COUNTER (100U) // This should be the last counter, update as needed. +#define PFM_REQ_HNDLR_RESERVED_COUNTER (100U) // This should be the last counter, update as needed. #define PFM_REQ_HNDLR_NUM_COUNTERS (PFM_REQ_HNDLR_RESERVED_COUNTER + 1) #define PFM_REQ_HNDLR_DEFAULT_COUNTER_HOLD_PERIOD_MS (20U) +// +// PRH internal handling of a temp 0C from a platform request. +// +#define PFM_REQ_HNDLR_TEMP_0_C NV_TYPES_CELSIUS_TO_NV_TEMP(0) + +// +// PRH handling for an invalid VP state index. +// +#define PFM_REQ_HNDLR_VPSTATE_INDEX_INVALID NV_U8_MAX + // Header to sensor structure typedef struct { @@ -133,6 +144,7 @@ typedef struct NvBool bPlatformUserConfigTGPSupport; // reflects SBIOS static requests to override power delta for User Configurable TGP mode NvU32 platformLimitDeltamW; // Cached limit from platform custimization NvU32 prevSbiosVPStateLimit; // reflects previous VPState requested to be set by SBIOS. + NvU32 platformEdppLimit; // Cached last EDPp limit request from platform NvU32 acpiVersionSw; // mapping between spec and supported sw state } PFM_REQ_HNDLR_ACPI_CACHE; @@ -185,6 +197,32 @@ typedef struct NvU8 ppmIdxRequested; } PFM_REQ_HNDLR_PPM_DATA; +/*! + * EDPPeak control data + */ +typedef struct +{ + /*! + * Set while OS workitem is pending execution. + */ + NvBool bWorkItemPending; + + /*! + * EDPpeak limit info data status. + */ + NvBool bDifferPlatformEdppLimit; + + /*! + * EDPpeak limit info data status. + */ + NV_STATUS status; + + /*! + * EDPpeak info data. + */ + NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1 edppLimitInfo; +} PFM_REQ_HNDLR_EDPP_DATA; + /*! * Control tracking and cache limits from SBIOS */ @@ -202,6 +240,9 @@ typedef struct // Current status of platform customized and applied user configurable TGP delta NvBool bPlatformUserConfigTGPmodeEnabled; + + // Current EDPPeak limit control + PFM_REQ_HNDLR_EDPP_DATA edppLimit; } PFM_REQ_HNDLR_CONTROL_DATA; /*! @@ -407,6 +448,39 @@ static inline NV_STATUS pfmreqhndlrHandleEdppeakLimitUpdate(struct PlatformReque #define pfmreqhndlrHandleEdppeakLimitUpdate(pPlatformRequestHandler, pGpu, bEnable) pfmreqhndlrHandleEdppeakLimitUpdate_IMPL(pPlatformRequestHandler, pGpu, bEnable) #endif //__nvoc_platform_request_handler_h_disabled +NV_STATUS pfmreqhndlrHandlePlatformEdppLimitUpdate_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvU32 platformEdppLimit); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandlePlatformEdppLimitUpdate(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvU32 platformEdppLimit) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandlePlatformEdppLimitUpdate(pPlatformRequestHandler, pGpu, platformEdppLimit) pfmreqhndlrHandlePlatformEdppLimitUpdate_IMPL(pPlatformRequestHandler, pGpu, platformEdppLimit) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrHandlePlatformGetEdppLimit_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvU32 *pPlatformEdppLimit); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandlePlatformGetEdppLimit(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvU32 *pPlatformEdppLimit) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandlePlatformGetEdppLimit(pPlatformRequestHandler, pGpu, pPlatformEdppLimit) pfmreqhndlrHandlePlatformGetEdppLimit_IMPL(pPlatformRequestHandler, pGpu, pPlatformEdppLimit) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrHandlePlatformSetEdppLimitInfo_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandlePlatformSetEdppLimitInfo(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandlePlatformSetEdppLimitInfo(pPlatformRequestHandler, pGpu) pfmreqhndlrHandlePlatformSetEdppLimitInfo_IMPL(pPlatformRequestHandler, pGpu) +#endif //__nvoc_platform_request_handler_h_disabled + NV_STATUS pfmreqhndlrHandleUserConfigurableTgpMode_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool bEnable); #ifdef __nvoc_platform_request_handler_h_disabled diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.c b/src/nvidia/generated/g_profiler_v2_nvoc.c index 65f74fd564..15948201dc 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.c +++ b/src/nvidia/generated/g_profiler_v2_nvoc.c @@ -200,12 +200,12 @@ static NvBool __nvoc_thunk_RmResource_profilerBaseAccessCallback(struct Profiler static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_ProfilerBase[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReserveHwpmLegacy_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) + /*flags=*/ 0x2010u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0101u, /*paramSize=*/ sizeof(NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS), @@ -335,12 +335,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [9] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdExecRegops_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc010au, /*paramSize=*/ sizeof(NVB0CC_CTRL_EXEC_REG_OPS_PARAMS), @@ -557,6 +557,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "profilerBaseCtrlCmdInternalReserveHwpmLegacy" +#endif + }, + { /* [24] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdRequestCgControls_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0301u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdRequestCgControls" +#endif + }, + { /* [25] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReleaseCgControls_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0302u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdReleaseCgControls" #endif }, @@ -564,7 +594,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler const struct NVOC_EXPORT_INFO __nvoc_export_info_ProfilerBase = { - /*numEntries=*/ 24, + /*numEntries=*/ 26, /*pExportEntries=*/ __nvoc_exported_method_def_ProfilerBase }; @@ -611,7 +641,7 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) pThis->__profilerBaseCtrlCmdReserveHwpmLegacy__ = &profilerBaseCtrlCmdReserveHwpmLegacy_IMPL; #endif @@ -667,7 +697,7 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdPmaStreamUpdateGetPut__ = &profilerBaseCtrlCmdPmaStreamUpdateGetPut_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__profilerBaseCtrlCmdExecRegops__ = &profilerBaseCtrlCmdExecRegops_IMPL; #endif @@ -707,6 +737,14 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdReleaseHes__ = &profilerBaseCtrlCmdReleaseHes_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdRequestCgControls__ = &profilerBaseCtrlCmdRequestCgControls_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdReleaseCgControls__ = &profilerBaseCtrlCmdReleaseCgControls_IMPL; +#endif + pThis->__profilerBaseShareCallback__ = &__nvoc_thunk_GpuResource_profilerBaseShareCallback; pThis->__profilerBaseCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap; diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.h b/src/nvidia/generated/g_profiler_v2_nvoc.h index 3dcec63c0c..d84a9a4918 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.h +++ b/src/nvidia/generated/g_profiler_v2_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -90,6 +90,8 @@ struct ProfilerBase { NV_STATUS (*__profilerBaseCtrlCmdSetHsCredits__)(struct ProfilerBase *, NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReserveHes__)(struct ProfilerBase *, NVB0CC_CTRL_RESERVE_HES_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReleaseHes__)(struct ProfilerBase *, NVB0CC_CTRL_RELEASE_HES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdRequestCgControls__)(struct ProfilerBase *, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdReleaseCgControls__)(struct ProfilerBase *, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *); NvBool (*__profilerBaseShareCallback__)(struct ProfilerBase *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__profilerBaseCheckMemInterUnmap__)(struct ProfilerBase *, NvBool); NV_STATUS (*__profilerBaseMapTo__)(struct ProfilerBase *, RS_RES_MAP_TO_PARAMS *); @@ -176,6 +178,8 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseCtrlCmdSetHsCredits(pProfiler, pParams) profilerBaseCtrlCmdSetHsCredits_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReserveHes(pProfiler, pParams) profilerBaseCtrlCmdReserveHes_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReleaseHes(pProfiler, pParams) profilerBaseCtrlCmdReleaseHes_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdRequestCgControls(pProfiler, pParams) profilerBaseCtrlCmdRequestCgControls_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdReleaseCgControls(pProfiler, pParams) profilerBaseCtrlCmdReleaseCgControls_DISPATCH(pProfiler, pParams) #define profilerBaseShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerBaseShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define profilerBaseCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerBaseCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define profilerBaseMapTo(pResource, pParams) profilerBaseMapTo_DISPATCH(pResource, pParams) @@ -376,6 +380,18 @@ static inline NV_STATUS profilerBaseCtrlCmdReleaseHes_DISPATCH(struct ProfilerBa return pProfiler->__profilerBaseCtrlCmdReleaseHes__(pProfiler, pParams); } +NV_STATUS profilerBaseCtrlCmdRequestCgControls_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdRequestCgControls_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdRequestCgControls__(pProfiler, pParams); +} + +NV_STATUS profilerBaseCtrlCmdReleaseCgControls_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdReleaseCgControls_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdReleaseCgControls__(pProfiler, pParams); +} + static inline NvBool profilerBaseShareCallback_DISPATCH(struct ProfilerBase *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__profilerBaseShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } diff --git a/src/nvidia/generated/g_reg_mem_nvoc.c b/src/nvidia/generated/g_reg_mem_nvoc.c index 4e6b405b5a..03b247d8b7 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.c +++ b/src/nvidia/generated/g_reg_mem_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_regmemIsReady(struct RegisterMemory *pMemor return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_regmemCheckCopyPermissions(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_regmemCheckCopyPermissions(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_regmemPreDestruct(struct RegisterMemory *pResource) { diff --git a/src/nvidia/generated/g_reg_mem_nvoc.h b/src/nvidia/generated/g_reg_mem_nvoc.h index ff373cbe5d..6156a0fda1 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.h +++ b/src/nvidia/generated/g_reg_mem_nvoc.h @@ -74,7 +74,7 @@ struct RegisterMemory { NV_STATUS (*__regmemControlFilter__)(struct RegisterMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemControlSerialization_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemIsReady__)(struct RegisterMemory *, NvBool); - NV_STATUS (*__regmemCheckCopyPermissions__)(struct RegisterMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__regmemCheckCopyPermissions__)(struct RegisterMemory *, struct OBJGPU *, struct Device *); void (*__regmemPreDestruct__)(struct RegisterMemory *); NV_STATUS (*__regmemIsDuplicate__)(struct RegisterMemory *, NvHandle, NvBool *); void (*__regmemControlSerialization_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -129,7 +129,7 @@ NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory**, Dynamic*, NvU32, CAL #define regmemControlFilter(pResource, pCallContext, pParams) regmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define regmemControlSerialization_Prologue(pResource, pCallContext, pParams) regmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define regmemIsReady(pMemory, bCopyConstructorContext) regmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define regmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) regmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define regmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) regmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define regmemPreDestruct(pResource) regmemPreDestruct_DISPATCH(pResource) #define regmemIsDuplicate(pMemory, hMemory, pDuplicate) regmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define regmemControlSerialization_Epilogue(pResource, pCallContext, pParams) regmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -213,8 +213,8 @@ static inline NV_STATUS regmemIsReady_DISPATCH(struct RegisterMemory *pMemory, N return pMemory->__regmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS regmemCheckCopyPermissions_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__regmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS regmemCheckCopyPermissions_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__regmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void regmemPreDestruct_DISPATCH(struct RegisterMemory *pResource) { diff --git a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h index bc0926b1e9..37ce899a95 100644 --- a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h +++ b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h @@ -310,6 +310,17 @@ typedef struct EventBuffer EventBuffer; #define __nvoc_class_id_EventBuffer 0x63502b #endif /* __nvoc_class_id_EventBuffer */ +struct SemaphoreSurface; + +#ifndef __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +#define __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +typedef struct SemaphoreSurface SemaphoreSurface; +#endif /* __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SemaphoreSurface +#define __nvoc_class_id_SemaphoreSurface 0xeabc69 +#endif /* __nvoc_class_id_SemaphoreSurface */ + struct P2PApi; #ifndef __NVOC_CLASS_P2PApi_TYPEDEF__ @@ -508,6 +519,17 @@ typedef struct VideoMemory VideoMemory; #define __nvoc_class_id_VideoMemory 0xed948f #endif /* __nvoc_class_id_VideoMemory */ +struct ExtendedGpuMemory; + +#ifndef __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ +#define __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ +typedef struct ExtendedGpuMemory ExtendedGpuMemory; +#endif /* __NVOC_CLASS_ExtendedGpuMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ExtendedGpuMemory +#define __nvoc_class_id_ExtendedGpuMemory 0xeffa5c +#endif /* __nvoc_class_id_ExtendedGpuMemory */ + struct PhysicalMemory; #ifndef __NVOC_CLASS_PhysicalMemory_TYPEDEF__ @@ -1036,6 +1058,17 @@ typedef struct MsencContext MsencContext; #define __nvoc_class_id_MsencContext 0x88c92a #endif /* __nvoc_class_id_MsencContext */ +struct Sec2Context; + +#ifndef __NVOC_CLASS_Sec2Context_TYPEDEF__ +#define __NVOC_CLASS_Sec2Context_TYPEDEF__ +typedef struct Sec2Context Sec2Context; +#endif /* __NVOC_CLASS_Sec2Context_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Sec2Context +#define __nvoc_class_id_Sec2Context 0x4c3439 +#endif /* __nvoc_class_id_Sec2Context */ + struct KernelGraphicsObject; #ifndef __NVOC_CLASS_KernelGraphicsObject_TYPEDEF__ @@ -1069,6 +1102,17 @@ typedef struct Event Event; #define __nvoc_class_id_Event 0xa4ecfc #endif /* __nvoc_class_id_Event */ +struct ConfidentialComputeApi; + +#ifndef __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ +#define __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ +typedef struct ConfidentialComputeApi ConfidentialComputeApi; +#endif /* __NVOC_CLASS_ConfidentialComputeApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConfidentialComputeApi +#define __nvoc_class_id_ConfidentialComputeApi 0xea5cb0 +#endif /* __nvoc_class_id_ConfidentialComputeApi */ + struct KernelCcuApi; #ifndef __NVOC_CLASS_KernelCcuApi_TYPEDEF__ @@ -1091,6 +1135,7 @@ struct NVOCFwdDeclHack { struct FmSessionApi *PRIVATE_FIELD(FmSessionApi_FABRIC_MANAGER_SESSION); struct GpuManagementApi *PRIVATE_FIELD(GpuManagementApi_NV0020_GPU_MANAGEMENT); struct EventBuffer *PRIVATE_FIELD(EventBuffer_NV_EVENT_BUFFER); + struct SemaphoreSurface *PRIVATE_FIELD(SemaphoreSurface_NV_SEMAPHORE_SURFACE); struct P2PApi *PRIVATE_FIELD(P2PApi_NV50_P2P); struct SyncGpuBoost *PRIVATE_FIELD(SyncGpuBoost_NV0060_SYNC_GPU_BOOST); struct Device *PRIVATE_FIELD(Device_NV01_DEVICE_0); @@ -1118,6 +1163,7 @@ struct NVOCFwdDeclHack { struct KernelChannelGroupApi *PRIVATE_FIELD(KernelChannelGroupApi_KEPLER_CHANNEL_GROUP_A); struct RegisterMemory *PRIVATE_FIELD(RegisterMemory_NV01_MEMORY_LOCAL_PRIVILEGED); struct VideoMemory *PRIVATE_FIELD(VideoMemory_NV01_MEMORY_LOCAL_USER); + struct ExtendedGpuMemory *PRIVATE_FIELD(ExtendedGpuMemory_NV_MEMORY_EXTENDED_USER); struct PhysicalMemory *PRIVATE_FIELD(PhysicalMemory_NV01_MEMORY_LOCAL_PHYSICAL); struct VirtualMemory *PRIVATE_FIELD(VirtualMemory_NV50_MEMORY_VIRTUAL); struct SystemMemory *PRIVATE_FIELD(SystemMemory_NV01_MEMORY_SYSTEM); @@ -1205,6 +1251,7 @@ struct NVOCFwdDeclHack { struct MsencContext *PRIVATE_FIELD(MsencContext_NVB4B7_VIDEO_ENCODER); struct MsencContext *PRIVATE_FIELD(MsencContext_NVC7B7_VIDEO_ENCODER); struct MsencContext *PRIVATE_FIELD(MsencContext_NVC9B7_VIDEO_ENCODER); + struct Sec2Context *PRIVATE_FIELD(Sec2Context_HOPPER_SEC2_WORK_LAUNCH_A); struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_A); struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_COMPUTE_A); struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_B); @@ -1222,6 +1269,7 @@ struct NVOCFwdDeclHack { struct Event *PRIVATE_FIELD(Event_NV01_EVENT_OS_EVENT); struct Event *PRIVATE_FIELD(Event_NV01_EVENT_KERNEL_CALLBACK); struct Event *PRIVATE_FIELD(Event_NV01_EVENT_KERNEL_CALLBACK_EX); + struct ConfidentialComputeApi *PRIVATE_FIELD(ConfidentialComputeApi_NV_CONFIDENTIAL_COMPUTE); struct KernelCcuApi *PRIVATE_FIELD(KernelCcuApi_NV_COUNTER_COLLECTION_UNIT); }; diff --git a/src/nvidia/generated/g_resserv_nvoc.h b/src/nvidia/generated/g_resserv_nvoc.h index 4ef0b2acf4..a68bb80139 100644 --- a/src/nvidia/generated/g_resserv_nvoc.h +++ b/src/nvidia/generated/g_resserv_nvoc.h @@ -231,7 +231,7 @@ typedef void *PUID_TOKEN; #define RS_LOCK_RELEASE_SESSION_LOCK NVBIT(5) /// API enumerations used for locking knobs -typedef enum +typedef enum { RS_LOCK_CLIENT =0, RS_LOCK_TOP =1, @@ -239,7 +239,7 @@ typedef enum RS_LOCK_CUSTOM_3 =3, } RS_LOCK_ENUM; -typedef enum +typedef enum { RS_API_ALLOC_CLIENT = 0, RS_API_ALLOC_RESOURCE = 1, @@ -324,7 +324,7 @@ struct CALL_CONTEXT NvU32 serializedSize; ///< Serialized size NvU32 deserializedSize; ///< Deserialized size NvBool bReserialize; ///< Reserialize before calling into GSP - NvBool bRestoreParams; ///< Need to restore pParams + NvBool bLocalSerialization; ///< Serialized internally }; typedef enum { @@ -403,7 +403,7 @@ struct ACCESS_CONTROL } while(0) #else -#define RS_LOCK_VALIDATOR_INIT(lock, lockClass, inst) +#define RS_LOCK_VALIDATOR_INIT(lock, lockClass, inst) #define RS_RWLOCK_ACQUIRE_READ(lock, validator) do { portSyncRwLockAcquireRead((lock)); } while(0) #define RS_RWLOCK_ACQUIRE_WRITE(lock, validator) do { portSyncRwLockAcquireWrite((lock)); } while(0) #define RS_RWLOCK_RELEASE_READ_EXT(lock, validator, bOutOfOrder) do { portSyncRwLockReleaseRead((lock)); } while(0) diff --git a/src/nvidia/generated/g_rpc-structures.h b/src/nvidia/generated/g_rpc-structures.h index 3afbb3cc71..306b202aac 100644 --- a/src/nvidia/generated/g_rpc-structures.h +++ b/src/nvidia/generated/g_rpc-structures.h @@ -233,6 +233,8 @@ typedef struct rpc_gsp_rm_alloc_v03_00 NvU32 hClass; NvU32 status; NvU32 paramsSize; + NvU32 flags; + NvU8 reserved[4]; NvU8 params[]; } rpc_gsp_rm_alloc_v03_00; @@ -245,9 +247,7 @@ typedef struct rpc_gsp_rm_control_v03_00 NvU32 cmd; NvU32 status; NvU32 paramsSize; - NvBool serialized; - NvBool copyOutOnError; - NvU8 reserved[2]; + NvU32 flags; NvU8 params[]; } rpc_gsp_rm_control_v03_00; @@ -282,6 +282,7 @@ typedef struct rpc_post_event_v17_00 NvHandle hEvent; NvU32 notifyIndex; NvU32 data; + NvU16 info16; NvU32 status; NvU32 eventDataSize; NvBool bNotifyList; @@ -513,6 +514,16 @@ typedef struct rpc_pfm_req_hndlr_state_sync_callback_v21_04 typedef rpc_pfm_req_hndlr_state_sync_callback_v21_04 rpc_pfm_req_hndlr_state_sync_callback_v; +typedef struct rpc_vgpu_gsp_mig_ci_config_v21_03 +{ + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NvU32 gfid; + NvBool bDelete; +} rpc_vgpu_gsp_mig_ci_config_v21_03; + +typedef rpc_vgpu_gsp_mig_ci_config_v21_03 rpc_vgpu_gsp_mig_ci_config_v; + typedef struct rpc_gsp_lockdown_notice_v17_00 { NvBool bLockdownEngaging; @@ -599,7 +610,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00 = { .name = "rpc_set_guest_system_info", - .header_length = NV_SIZEOF32(rpc_set_guest_system_info_v03_00), + .header_length = sizeof(rpc_set_guest_system_info_v03_00), .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00 }; #endif @@ -663,7 +674,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_memory_v13_01[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_memory_v13_01 = { .name = "rpc_alloc_memory", - .header_length = NV_SIZEOF32(rpc_alloc_memory_v13_01), + .header_length = sizeof(rpc_alloc_memory_v13_01), .fdesc = vmiopd_fdesc_t_rpc_alloc_memory_v13_01 }; #endif @@ -682,7 +693,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_free_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_free_v03_00 = { .name = "rpc_free", - .header_length = NV_SIZEOF32(rpc_free_v03_00), + .header_length = sizeof(rpc_free_v03_00), .fdesc = vmiopd_fdesc_t_rpc_free_v03_00 }; #endif @@ -701,7 +712,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_map_memory_dma_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_map_memory_dma_v03_00 = { .name = "rpc_map_memory_dma", - .header_length = NV_SIZEOF32(rpc_map_memory_dma_v03_00), + .header_length = sizeof(rpc_map_memory_dma_v03_00), .fdesc = vmiopd_fdesc_t_rpc_map_memory_dma_v03_00 }; #endif @@ -720,7 +731,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00 = { .name = "rpc_unmap_memory_dma", - .header_length = NV_SIZEOF32(rpc_unmap_memory_dma_v03_00), + .header_length = sizeof(rpc_unmap_memory_dma_v03_00), .fdesc = vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00 }; #endif @@ -739,7 +750,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dup_object_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dup_object_v03_00 = { .name = "rpc_dup_object", - .header_length = NV_SIZEOF32(rpc_dup_object_v03_00), + .header_length = sizeof(rpc_dup_object_v03_00), .fdesc = vmiopd_fdesc_t_rpc_dup_object_v03_00 }; #endif @@ -775,7 +786,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_idle_channels_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_idle_channels_v03_00 = { .name = "rpc_idle_channels", - .header_length = NV_SIZEOF32(rpc_idle_channels_v03_00), + .header_length = sizeof(rpc_idle_channels_v03_00), .fdesc = vmiopd_fdesc_t_rpc_idle_channels_v03_00 }; #endif @@ -817,7 +828,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07 = { .name = "rpc_unloading_guest_driver", - .header_length = NV_SIZEOF32(rpc_unloading_guest_driver_v1F_07), + .header_length = sizeof(rpc_unloading_guest_driver_v1F_07), .fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07 }; #endif @@ -846,7 +857,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01 = { .name = "rpc_gpu_exec_reg_ops", - .header_length = NV_SIZEOF32(rpc_gpu_exec_reg_ops_v12_01), + .header_length = sizeof(rpc_gpu_exec_reg_ops_v12_01), .fdesc = vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01 }; #endif @@ -880,7 +891,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v1E_05[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v1E_05 = { .name = "rpc_set_page_directory", - .header_length = NV_SIZEOF32(rpc_set_page_directory_v1E_05), + .header_length = sizeof(rpc_set_page_directory_v1E_05), .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v1E_05 }; #endif @@ -909,7 +920,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v03_00 = { .name = "rpc_set_page_directory", - .header_length = NV_SIZEOF32(rpc_set_page_directory_v03_00), + .header_length = sizeof(rpc_set_page_directory_v03_00), .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v03_00 }; #endif @@ -938,7 +949,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05 = { .name = "rpc_unset_page_directory", - .header_length = NV_SIZEOF32(rpc_unset_page_directory_v1E_05), + .header_length = sizeof(rpc_unset_page_directory_v1E_05), .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05 }; #endif @@ -967,7 +978,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v03_00 = { .name = "rpc_unset_page_directory", - .header_length = NV_SIZEOF32(rpc_unset_page_directory_v03_00), + .header_length = sizeof(rpc_unset_page_directory_v03_00), .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v03_00 }; #endif @@ -986,7 +997,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00 = { .name = "rpc_get_gsp_static_info", - .header_length = NV_SIZEOF32(rpc_get_gsp_static_info_v14_00), + .header_length = sizeof(rpc_get_gsp_static_info_v14_00), .fdesc = vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00 }; #endif @@ -1005,7 +1016,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_update_bar_pde_v15_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_update_bar_pde_v15_00 = { .name = "rpc_update_bar_pde", - .header_length = NV_SIZEOF32(rpc_update_bar_pde_v15_00), + .header_length = sizeof(rpc_update_bar_pde_v15_00), .fdesc = vmiopd_fdesc_t_rpc_update_bar_pde_v15_00 }; #endif @@ -1034,7 +1045,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00 = { .name = "rpc_vgpu_pf_reg_read32", - .header_length = NV_SIZEOF32(rpc_vgpu_pf_reg_read32_v15_00), + .header_length = sizeof(rpc_vgpu_pf_reg_read32_v15_00), .fdesc = vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00 }; #endif @@ -1053,7 +1064,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02[] = static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 = { .name = "rpc_ctrl_subdevice_get_p2p_caps", - .header_length = NV_SIZEOF32(rpc_ctrl_subdevice_get_p2p_caps_v21_02), + .header_length = sizeof(rpc_ctrl_subdevice_get_p2p_caps_v21_02), .fdesc = vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 }; #endif @@ -1082,7 +1093,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 = { .name = "rpc_ctrl_bus_set_p2p_mapping", - .header_length = NV_SIZEOF32(rpc_ctrl_bus_set_p2p_mapping_v21_03), + .header_length = sizeof(rpc_ctrl_bus_set_p2p_mapping_v21_03), .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 }; #endif @@ -1111,7 +1122,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 = { .name = "rpc_ctrl_bus_unset_p2p_mapping", - .header_length = NV_SIZEOF32(rpc_ctrl_bus_unset_p2p_mapping_v21_03), + .header_length = sizeof(rpc_ctrl_bus_unset_p2p_mapping_v21_03), .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 }; #endif @@ -1130,7 +1141,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_init_v15_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_init_v15_00 = { .name = "rpc_rmfs_init", - .header_length = NV_SIZEOF32(rpc_rmfs_init_v15_00), + .header_length = sizeof(rpc_rmfs_init_v15_00), .fdesc = vmiopd_fdesc_t_rpc_rmfs_init_v15_00 }; #endif @@ -1190,7 +1201,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_test_v15_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_test_v15_00 = { .name = "rpc_rmfs_test", - .header_length = NV_SIZEOF32(rpc_rmfs_test_v15_00), + .header_length = sizeof(rpc_rmfs_test_v15_00), .fdesc = vmiopd_fdesc_t_rpc_rmfs_test_v15_00 }; #endif @@ -1209,7 +1220,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00 = { .name = "rpc_gsp_set_system_info", - .header_length = NV_SIZEOF32(rpc_gsp_set_system_info_v17_00), + .header_length = sizeof(rpc_gsp_set_system_info_v17_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00 }; #endif @@ -1259,6 +1270,17 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00[] = { .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, paramsSize), .name = "paramsSize" }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, flags), + .name = "flags" + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, reserved), + .array_length = 4, + .name = "reserved" + }, { .vtype = vtype_NvU8_array, .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, params), @@ -1272,7 +1294,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00 = { .name = "rpc_gsp_rm_alloc", - .header_length = NV_SIZEOF32(rpc_gsp_rm_alloc_v03_00), + .header_length = sizeof(rpc_gsp_rm_alloc_v03_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00 }; #endif @@ -1305,20 +1327,9 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = { .name = "paramsSize" }, { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, serialized), - .name = "serialized" - }, - { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, copyOutOnError), - .name = "copyOutOnError" - }, - { - .vtype = vtype_NvU8_array, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, reserved), - .array_length = 2, - .name = "reserved" + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, flags), + .name = "flags" }, { .vtype = vtype_NvU8_array, @@ -1333,7 +1344,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00 = { .name = "rpc_gsp_rm_control", - .header_length = NV_SIZEOF32(rpc_gsp_rm_control_v03_00), + .header_length = sizeof(rpc_gsp_rm_control_v03_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00 }; #endif @@ -1383,7 +1394,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12 = { .name = "rpc_dump_protobuf_component", - .header_length = NV_SIZEOF32(rpc_dump_protobuf_component_v18_12), + .header_length = sizeof(rpc_dump_protobuf_component_v18_12), .fdesc = vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12 }; #endif @@ -1419,7 +1430,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00 = { .name = "rpc_run_cpu_sequencer", - .header_length = NV_SIZEOF32(rpc_run_cpu_sequencer_v17_00), + .header_length = sizeof(rpc_run_cpu_sequencer_v17_00), .fdesc = vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00 }; #endif @@ -1446,6 +1457,11 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_post_event_v17_00[] = { .offset = NV_OFFSETOF(rpc_post_event_v17_00, data), .name = "data" }, + { + .vtype = vtype_NvU16, + .offset = NV_OFFSETOF(rpc_post_event_v17_00, info16), + .name = "info16" + }, { .vtype = vtype_NvU32, .offset = NV_OFFSETOF(rpc_post_event_v17_00, status), @@ -1474,7 +1490,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_post_event_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_post_event_v17_00 = { .name = "rpc_post_event", - .header_length = NV_SIZEOF32(rpc_post_event_v17_00), + .header_length = sizeof(rpc_post_event_v17_00), .fdesc = vmiopd_fdesc_t_rpc_post_event_v17_00 }; #endif @@ -1513,7 +1529,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rc_triggered_v17_02[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rc_triggered_v17_02 = { .name = "rpc_rc_triggered", - .header_length = NV_SIZEOF32(rpc_rc_triggered_v17_02), + .header_length = sizeof(rpc_rc_triggered_v17_02), .fdesc = vmiopd_fdesc_t_rpc_rc_triggered_v17_02 }; #endif @@ -1548,7 +1564,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_os_error_log_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_os_error_log_v17_00 = { .name = "rpc_os_error_log", - .header_length = NV_SIZEOF32(rpc_os_error_log_v17_00), + .header_length = sizeof(rpc_os_error_log_v17_00), .fdesc = vmiopd_fdesc_t_rpc_os_error_log_v17_00 }; #endif @@ -1572,7 +1588,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rg_line_intr_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rg_line_intr_v17_00 = { .name = "rpc_rg_line_intr", - .header_length = NV_SIZEOF32(rpc_rg_line_intr_v17_00), + .header_length = sizeof(rpc_rg_line_intr_v17_00), .fdesc = vmiopd_fdesc_t_rpc_rg_line_intr_v17_00 }; #endif @@ -1601,7 +1617,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_display_modeset_v01_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_display_modeset_v01_00 = { .name = "rpc_display_modeset", - .header_length = NV_SIZEOF32(rpc_display_modeset_v01_00), + .header_length = sizeof(rpc_display_modeset_v01_00), .fdesc = vmiopd_fdesc_t_rpc_display_modeset_v01_00 }; #endif @@ -1620,7 +1636,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00[] = static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00 = { .name = "rpc_gpuacct_perfmon_util_samples", - .header_length = NV_SIZEOF32(rpc_gpuacct_perfmon_util_samples_v17_00), + .header_length = sizeof(rpc_gpuacct_perfmon_util_samples_v17_00), .fdesc = vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00 }; #endif @@ -1644,7 +1660,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 = { .name = "rpc_vgpu_gsp_plugin_triggered", - .header_length = NV_SIZEOF32(rpc_vgpu_gsp_plugin_triggered_v17_00), + .header_length = sizeof(rpc_vgpu_gsp_plugin_triggered_v17_00), .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 }; #endif @@ -1663,7 +1679,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00 = { .name = "rpc_vgpu_config_event", - .header_length = NV_SIZEOF32(rpc_vgpu_config_event_v17_00), + .header_length = sizeof(rpc_vgpu_config_event_v17_00), .fdesc = vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00 }; #endif @@ -1682,7 +1698,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dce_rm_init_v01_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dce_rm_init_v01_00 = { .name = "rpc_dce_rm_init", - .header_length = NV_SIZEOF32(rpc_dce_rm_init_v01_00), + .header_length = sizeof(rpc_dce_rm_init_v01_00), .fdesc = vmiopd_fdesc_t_rpc_dce_rm_init_v01_00 }; #endif @@ -1712,7 +1728,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_read_v1E_01[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_read_v1E_01 = { .name = "rpc_sim_read", - .header_length = NV_SIZEOF32(rpc_sim_read_v1E_01), + .header_length = sizeof(rpc_sim_read_v1E_01), .fdesc = vmiopd_fdesc_t_rpc_sim_read_v1E_01 }; #endif @@ -1747,7 +1763,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_write_v1E_01[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_write_v1E_01 = { .name = "rpc_sim_write", - .header_length = NV_SIZEOF32(rpc_sim_write_v1E_01), + .header_length = sizeof(rpc_sim_write_v1E_01), .fdesc = vmiopd_fdesc_t_rpc_sim_write_v1E_01 }; #endif @@ -1777,7 +1793,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08 = { .name = "rpc_ucode_libos_print", - .header_length = NV_SIZEOF32(rpc_ucode_libos_print_v1E_08), + .header_length = sizeof(rpc_ucode_libos_print_v1E_08), .fdesc = vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08 }; #endif @@ -1796,7 +1812,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_init_done_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_init_done_v17_00 = { .name = "rpc_init_done", - .header_length = NV_SIZEOF32(rpc_init_done_v17_00), + .header_length = sizeof(rpc_init_done_v17_00), .fdesc = vmiopd_fdesc_t_rpc_init_done_v17_00 }; #endif @@ -1845,7 +1861,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00[] = static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00 = { .name = "rpc_semaphore_schedule_callback", - .header_length = NV_SIZEOF32(rpc_semaphore_schedule_callback_v17_00), + .header_length = sizeof(rpc_semaphore_schedule_callback_v17_00), .fdesc = vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00 }; #endif @@ -1889,7 +1905,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00 = { .name = "rpc_timed_semaphore_release", - .header_length = NV_SIZEOF32(rpc_timed_semaphore_release_v01_00), + .header_length = sizeof(rpc_timed_semaphore_release_v01_00), .fdesc = vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00 }; #endif @@ -1908,7 +1924,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 = { .name = "rpc_perf_gpu_boost_sync_limits_callback", - .header_length = NV_SIZEOF32(rpc_perf_gpu_boost_sync_limits_callback_v17_00), + .header_length = sizeof(rpc_perf_gpu_boost_sync_limits_callback_v17_00), .fdesc = vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 }; #endif @@ -1927,7 +1943,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00[] = static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = { .name = "rpc_perf_bridgeless_info_update", - .header_length = NV_SIZEOF32(rpc_perf_bridgeless_info_update_v17_00), + .header_length = sizeof(rpc_perf_bridgeless_info_update_v17_00), .fdesc = vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00 }; #endif @@ -1946,7 +1962,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00 = { .name = "rpc_nvlink_fault_up", - .header_length = NV_SIZEOF32(rpc_nvlink_fault_up_v17_00), + .header_length = sizeof(rpc_nvlink_fault_up_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00 }; #endif @@ -1965,7 +1981,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00[ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00 = { .name = "rpc_nvlink_inband_received_data_256", - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_256_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_256_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00 }; #endif @@ -1984,7 +2000,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00[ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00 = { .name = "rpc_nvlink_inband_received_data_512", - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_512_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_512_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00 }; #endif @@ -2003,7 +2019,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 = { .name = "rpc_nvlink_inband_received_data_1024", - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_1024_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_1024_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 }; #endif @@ -2022,7 +2038,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 = { .name = "rpc_nvlink_inband_received_data_2048", - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_2048_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_2048_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 }; #endif @@ -2041,7 +2057,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 = { .name = "rpc_nvlink_inband_received_data_4096", - .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_4096_v17_00), + .header_length = sizeof(rpc_nvlink_inband_received_data_4096_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 }; #endif @@ -2060,7 +2076,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 = { .name = "rpc_nvlink_is_gpu_degraded", - .header_length = NV_SIZEOF32(rpc_nvlink_is_gpu_degraded_v17_00), + .header_length = sizeof(rpc_nvlink_is_gpu_degraded_v17_00), .fdesc = vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 }; #endif @@ -2079,7 +2095,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00 = { .name = "rpc_gsp_send_user_shared_data", - .header_length = NV_SIZEOF32(rpc_gsp_send_user_shared_data_v17_00), + .header_length = sizeof(rpc_gsp_send_user_shared_data_v17_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00 }; #endif @@ -2108,7 +2124,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 = { .name = "rpc_set_sysmem_dirty_page_tracking_buffer", - .header_length = NV_SIZEOF32(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00), + .header_length = sizeof(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00), .fdesc = vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 }; #endif @@ -2142,7 +2158,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00 = { .name = "rpc_extdev_intr_service", - .header_length = NV_SIZEOF32(rpc_extdev_intr_service_v17_00), + .header_length = sizeof(rpc_extdev_intr_service_v17_00), .fdesc = vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00 }; #endif @@ -2161,11 +2177,46 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_0 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 = { .name = "rpc_pfm_req_hndlr_state_sync_callback", - .header_length = NV_SIZEOF32(rpc_pfm_req_hndlr_state_sync_callback_v21_04), + .header_length = sizeof(rpc_pfm_req_hndlr_state_sync_callback_v21_04), .fdesc = vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 }; #endif +#ifndef SKIP_PRINT_rpc_vgpu_gsp_mig_ci_config_v21_03 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartCount), + .name = "execPartCount" + }, + { + .vtype = vtype_NvU32_array, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartId), + .array_length = NVC637_CTRL_MAX_EXEC_PARTITIONS, + .name = "execPartId" + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, gfid), + .name = "gfid" + }, + { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, bDelete), + .name = "bDelete" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 = { + .name = "rpc_vgpu_gsp_mig_ci_config", + .header_length = sizeof(rpc_vgpu_gsp_mig_ci_config_v21_03), + .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 +}; +#endif + #ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00[] = { { @@ -2180,7 +2231,7 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00[] = { static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_lockdown_notice_v17_00 = { .name = "rpc_gsp_lockdown_notice", - .header_length = NV_SIZEOF32(rpc_gsp_lockdown_notice_v17_00), + .header_length = sizeof(rpc_gsp_lockdown_notice_v17_00), .fdesc = vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00 }; #endif @@ -2605,6 +2656,13 @@ vmiopd_mdesc_t *rpcdebugPfmReqHndlrStateSyncCallback_v21_04(void) } #endif +#ifndef SKIP_PRINT_rpc_vgpu_gsp_mig_ci_config_v21_03 +vmiopd_mdesc_t *rpcdebugVgpuGspMigCiConfig_v21_03(void) +{ + return &vmiopd_mdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03; +} +#endif + #ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00 vmiopd_mdesc_t *rpcdebugGspLockdownNotice_v17_00(void) { @@ -2724,6 +2782,8 @@ typedef union rpc_generic_union { rpc_extdev_intr_service_v extdev_intr_service_v; rpc_pfm_req_hndlr_state_sync_callback_v21_04 pfm_req_hndlr_state_sync_callback_v21_04; rpc_pfm_req_hndlr_state_sync_callback_v pfm_req_hndlr_state_sync_callback_v; + rpc_vgpu_gsp_mig_ci_config_v21_03 vgpu_gsp_mig_ci_config_v21_03; + rpc_vgpu_gsp_mig_ci_config_v vgpu_gsp_mig_ci_config_v; rpc_gsp_lockdown_notice_v17_00 gsp_lockdown_notice_v17_00; rpc_gsp_lockdown_notice_v gsp_lockdown_notice_v; } rpc_generic_union; @@ -2750,7 +2810,6 @@ static NV_STATUS get_array_length_rpc_idle_channels_v03_00_channel_list(void *ms if ((NvS32)(NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels) + sizeof(param->nchannels)) > bytes_remaining) return NV_ERR_BUFFER_TOO_SMALL; - *length = param->nchannels; return NV_OK; } diff --git a/src/nvidia/generated/g_rpc_private.h b/src/nvidia/generated/g_rpc_private.h index fc7e64c2d0..bded95bda2 100644 --- a/src/nvidia/generated/g_rpc_private.h +++ b/src/nvidia/generated/g_rpc_private.h @@ -2368,6 +2368,40 @@ static void rpc_iGrp_ipVersions_Install_v22_01(IGRP_IP_VERSIONS_TABLE_INFO *pInf #endif // } +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v23_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v23_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + @@ -2880,6 +2914,12 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v22_01[] = { { 0x22010000, 0xFFFFFFFF, }, // }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_02[] = { + { 0x23020000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_03[] = { + { 0x23030000, 0xFFFFFFFF, }, // + }; #define _RPC_HAL_IGRP_ENTRY_INIT(v) \ { RPC_IGRP_IP_VERSIONS_RANGES_##v, NV_ARRAY_ELEMENTS(RPC_IGRP_IP_VERSIONS_RANGES_##v), rpc_iGrp_ipVersions_Install_##v, } @@ -3017,6 +3057,8 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) _RPC_HAL_IGRP_ENTRY_INIT(v21_0A), // _RPC_HAL_IGRP_ENTRY_INIT(v21_0B), // _RPC_HAL_IGRP_ENTRY_INIT(v22_01), // + _RPC_HAL_IGRP_ENTRY_INIT(v23_02), // + _RPC_HAL_IGRP_ENTRY_INIT(v23_03), // }; #undef _RPC_HAL_IGRP_ENTRY_INIT diff --git a/src/nvidia/generated/g_rs_resource_nvoc.h b/src/nvidia/generated/g_rs_resource_nvoc.h index 433cb46326..ff1abe6e02 100644 --- a/src/nvidia/generated/g_rs_resource_nvoc.h +++ b/src/nvidia/generated/g_rs_resource_nvoc.h @@ -109,6 +109,7 @@ struct RS_RES_ALLOC_PARAMS_INTERNAL API_SECURITY_INFO *pSecInfo; void *pAllocParams; ///< [in] Copied-in allocation parameters + NvU32 paramsSize; ///< [in] Copied-in allocation parameters size // ... Dupe alloc struct RsClient *pSrcClient; ///< The client that is sharing the resource @@ -838,7 +839,7 @@ NV_STATUS refAddDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependant /** * Remove the dependency between this resource reference and a dependent resource reference. */ -NV_STATUS refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRef); +void refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRef); /** * Find, Add, or Remove an inter-mapping between two resources to the Mapper's list of inter-mappings diff --git a/src/nvidia/generated/g_rs_server_nvoc.h b/src/nvidia/generated/g_rs_server_nvoc.h index 5b32c882c3..b5cb3cf3ae 100644 --- a/src/nvidia/generated/g_rs_server_nvoc.h +++ b/src/nvidia/generated/g_rs_server_nvoc.h @@ -422,7 +422,7 @@ NV_STATUS serverFreeClient(RsServer *pServer, RS_CLIENT_FREE_PARAMS* pParams); NV_STATUS serverMarkClientListDisabled(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); /** - * Frees all currently disabled clients. All resources references owned by + * Frees all currently disabled clients. All resources references owned by * any of the clients will be freed. * All priority resources will be freed first across all listed clients. * @@ -516,44 +516,44 @@ NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); * * @param[in] pCallContext * @param[in] cmd - * @param[in] pParams - * @param[in] paramsSize + * @param[in/out] ppParams + * @param[in/out] pParamsSize * @param[in] flags */ -NV_STATUS serverDeserializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); +NV_STATUS serverDeserializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); /** * Serialize parameters for servicing command * * @param[in] pCallContext * @param[in] cmd - * @param[in] pParams - * @param[in] paramsSize + * @param[in/out] ppParams + * @param[in/out] pParamsSize * @param[in] flags */ -NV_STATUS serverSerializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); +NV_STATUS serverSerializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); /** * Deserialize parameters for returning from command * * @param[in] pCallContext * @param[in] cmd - * @param[in] pParams - * @param[in] paramsSize + * @param[out] ppParams + * @param[out] pParamsSize * @param[in] flags */ -NV_STATUS serverDeserializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); +NV_STATUS serverDeserializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); /** * Serialize parameters for returning from command * * @param[in] pCallContext * @param[in] cmd - * @param[in] pParams - * @param[in] paramsSize + * @param[out] ppParams + * @param[out] pParamsSize * @param[in] flags */ -NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); +NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); /** * Unset flag for reserializing control before going to GSP @@ -563,6 +563,50 @@ NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pPa */ void serverDisableReserializeControl(CALL_CONTEXT *pCallContext); +/** + * Serialize parameters for allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[in/out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeAllocDown(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[in/out] ppParams + * @param[in/out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeAllocDown(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Serialize parameters for returning from allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeAllocUp(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for returning from allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeAllocUp(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + /** * Free finn structures allocated for serializing/deserializing * diff --git a/src/nvidia/generated/g_sdk-structures.h b/src/nvidia/generated/g_sdk-structures.h index ecef5154d5..b4883d0783 100644 --- a/src/nvidia/generated/g_sdk-structures.h +++ b/src/nvidia/generated/g_sdk-structures.h @@ -510,33 +510,33 @@ typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 NV2080_CTRL_ #endif #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS -// Union member name functions for NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type -static char* _get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type(NvU32 cmd) +// Union member index functions for NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type +uint32_t _get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(NvU32 cmd) { switch (cmd) { case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI: - return "smbpbi"; + return 0; // "smbpbi" default: return UNION_UNKNOWN_FIELD_PRINT; } } -#define _get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(cmd) _get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type(cmd) + + #endif #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD -static NV_STATUS get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04_data(void *msg, NvS32 bytes_remaining, char** name) +static NV_STATUS get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04_data(void *msg, NvS32 bytes_remaining, uint32_t* index) { NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 *param = msg; if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04, type) + sizeof(param->type)) > bytes_remaining) return NV_ERR_BUFFER_TOO_SMALL; - - *name = _get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(param->type); + *index = _get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(param->type); return NV_OK; } @@ -551,7 +551,6 @@ static NV_STATUS get_array_length_gpu_exec_reg_ops_v03_00_operations(void *msg, if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v03_00, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining) return NV_ERR_BUFFER_TOO_SMALL; - *length = param->reg_op_params.regOpCount; return NV_OK; } @@ -561,7 +560,6 @@ static NV_STATUS get_array_length_gpu_exec_reg_ops_v12_01_operations(void *msg, if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v12_01, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining) return NV_ERR_BUFFER_TOO_SMALL; - *length = param->reg_op_params.regOpCount; return NV_OK; } diff --git a/src/nvidia/generated/g_sec2_context_nvoc.c b/src/nvidia/generated/g_sec2_context_nvoc.c new file mode 100644 index 0000000000..47572b83f6 --- /dev/null +++ b/src/nvidia/generated/g_sec2_context_nvoc.c @@ -0,0 +1,442 @@ +#define NVOC_SEC2_CONTEXT_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_sec2_context_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x4c3439 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Context; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ChannelDescendant; + +void __nvoc_init_Sec2Context(Sec2Context*, RmHalspecOwner* ); +void __nvoc_init_funcTable_Sec2Context(Sec2Context*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_Sec2Context(Sec2Context*, RmHalspecOwner* , struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_Sec2Context(Sec2Context*, RmHalspecOwner* ); +void __nvoc_dtor_Sec2Context(Sec2Context*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Sec2Context; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_Sec2Context = { + /*pClassDef=*/ &__nvoc_class_def_Sec2Context, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_Sec2Context, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_GpuResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_INotifier = { + /*pClassDef=*/ &__nvoc_class_def_INotifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_Notifier.__nvoc_base_INotifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_Notifier = { + /*pClassDef=*/ &__nvoc_class_def_Notifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant.__nvoc_base_Notifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_Sec2Context_ChannelDescendant = { + /*pClassDef=*/ &__nvoc_class_def_ChannelDescendant, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Sec2Context, __nvoc_base_ChannelDescendant), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_Sec2Context = { + /*numRelatives=*/ 9, + /*relatives=*/ { + &__nvoc_rtti_Sec2Context_Sec2Context, + &__nvoc_rtti_Sec2Context_ChannelDescendant, + &__nvoc_rtti_Sec2Context_Notifier, + &__nvoc_rtti_Sec2Context_INotifier, + &__nvoc_rtti_Sec2Context_GpuResource, + &__nvoc_rtti_Sec2Context_RmResource, + &__nvoc_rtti_Sec2Context_RmResourceCommon, + &__nvoc_rtti_Sec2Context_RsResource, + &__nvoc_rtti_Sec2Context_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Context = +{ + /*classInfo=*/ { + /*size=*/ sizeof(Sec2Context), + /*classId=*/ classId(Sec2Context), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "Sec2Context", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_Sec2Context, + /*pCastInfo=*/ &__nvoc_castinfo_Sec2Context, + /*pExportInfo=*/ &__nvoc_export_info_Sec2Context +}; + +static NV_STATUS __nvoc_thunk_ChannelDescendant_sec2ctxCheckMemInterUnmap(struct Sec2Context *pChannelDescendant, NvBool bSubdeviceHandleProvided) { + return chandesCheckMemInterUnmap((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_Sec2Context_ChannelDescendant.offset), bSubdeviceHandleProvided); +} + +static NvBool __nvoc_thunk_GpuResource_sec2ctxShareCallback(struct Sec2Context *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NvBool __nvoc_thunk_RmResource_sec2ctxAccessCallback(struct Sec2Context *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxMapTo(struct Sec2Context *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxGetMapAddrSpace(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static void __nvoc_thunk_Notifier_sec2ctxSetNotificationShare(struct Sec2Context *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_sec2ctxGetRefCount(struct Sec2Context *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_sec2ctxAddAdditionalDependants(struct RsClient *pClient, struct Sec2Context *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_sec2ctxControl_Prologue(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxGetRegBaseOffsetAndSize(struct Sec2Context *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxInternalControlForward(struct Sec2Context *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxUnmapFrom(struct Sec2Context *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_sec2ctxControl_Epilogue(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxControlLookup(struct Sec2Context *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_ChannelDescendant_sec2ctxGetSwMethods(struct Sec2Context *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { + return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_Sec2Context_ChannelDescendant.offset), ppMethods, pNumMethods); +} + +static NvHandle __nvoc_thunk_GpuResource_sec2ctxGetInternalObjectHandle(struct Sec2Context *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxControl(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxUnmap(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_sec2ctxGetMemInterMapParams(struct Sec2Context *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_sec2ctxGetMemoryMappingDescriptor(struct Sec2Context *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Sec2Context_RmResource.offset), ppMemDesc); +} + +static NvBool __nvoc_thunk_ChannelDescendant_sec2ctxIsSwMethodStalling(struct Sec2Context *pChannelDescendant, NvU32 hHandle) { + return chandesIsSwMethodStalling((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_Sec2Context_ChannelDescendant.offset), hHandle); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxControlFilter(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_sec2ctxUnregisterEvent(struct Sec2Context *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static NV_STATUS __nvoc_thunk_RmResource_sec2ctxControlSerialization_Prologue(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_sec2ctxCanCopy(struct Sec2Context *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_sec2ctxPreDestruct(struct Sec2Context *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_sec2ctxIsDuplicate(struct Sec2Context *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_sec2ctxControlSerialization_Epilogue(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); +} + +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_sec2ctxGetNotificationListPtr(struct Sec2Context *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset)); +} + +static struct NotifShare *__nvoc_thunk_Notifier_sec2ctxGetNotificationShare(struct Sec2Context *pNotifier) { + return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_sec2ctxMap(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Sec2Context_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Notifier_sec2ctxGetOrAllocNotifShare(struct Sec2Context *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Sec2Context_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_Sec2Context = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_ChannelDescendant(ChannelDescendant*); +void __nvoc_dtor_Sec2Context(Sec2Context *pThis) { + __nvoc_sec2ctxDestruct(pThis); + __nvoc_dtor_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_ChannelDescendant(ChannelDescendant* , RmHalspecOwner* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *, PARAM_TO_ENGDESC_FUNCTION *); +NV_STATUS __nvoc_ctor_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant, pRmhalspecowner, arg_pCallContext, arg_pParams, ((void *)0)); + if (status != NV_OK) goto __nvoc_ctor_Sec2Context_fail_ChannelDescendant; + __nvoc_init_dataField_Sec2Context(pThis, pRmhalspecowner); + + status = __nvoc_sec2ctxConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_Sec2Context_fail__init; + goto __nvoc_ctor_Sec2Context_exit; // Success + +__nvoc_ctor_Sec2Context_fail__init: + __nvoc_dtor_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant); +__nvoc_ctor_Sec2Context_fail_ChannelDescendant: +__nvoc_ctor_Sec2Context_exit: + + return status; +} + +static void __nvoc_init_funcTable_Sec2Context_1(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + + pThis->__sec2ctxCheckMemInterUnmap__ = &__nvoc_thunk_ChannelDescendant_sec2ctxCheckMemInterUnmap; + + pThis->__sec2ctxShareCallback__ = &__nvoc_thunk_GpuResource_sec2ctxShareCallback; + + pThis->__sec2ctxAccessCallback__ = &__nvoc_thunk_RmResource_sec2ctxAccessCallback; + + pThis->__sec2ctxMapTo__ = &__nvoc_thunk_RsResource_sec2ctxMapTo; + + pThis->__sec2ctxGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_sec2ctxGetMapAddrSpace; + + pThis->__sec2ctxSetNotificationShare__ = &__nvoc_thunk_Notifier_sec2ctxSetNotificationShare; + + pThis->__sec2ctxGetRefCount__ = &__nvoc_thunk_RsResource_sec2ctxGetRefCount; + + pThis->__sec2ctxAddAdditionalDependants__ = &__nvoc_thunk_RsResource_sec2ctxAddAdditionalDependants; + + pThis->__sec2ctxControl_Prologue__ = &__nvoc_thunk_RmResource_sec2ctxControl_Prologue; + + pThis->__sec2ctxGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_sec2ctxGetRegBaseOffsetAndSize; + + pThis->__sec2ctxInternalControlForward__ = &__nvoc_thunk_GpuResource_sec2ctxInternalControlForward; + + pThis->__sec2ctxUnmapFrom__ = &__nvoc_thunk_RsResource_sec2ctxUnmapFrom; + + pThis->__sec2ctxControl_Epilogue__ = &__nvoc_thunk_RmResource_sec2ctxControl_Epilogue; + + pThis->__sec2ctxControlLookup__ = &__nvoc_thunk_RsResource_sec2ctxControlLookup; + + pThis->__sec2ctxGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_sec2ctxGetSwMethods; + + pThis->__sec2ctxGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_sec2ctxGetInternalObjectHandle; + + pThis->__sec2ctxControl__ = &__nvoc_thunk_GpuResource_sec2ctxControl; + + pThis->__sec2ctxUnmap__ = &__nvoc_thunk_GpuResource_sec2ctxUnmap; + + pThis->__sec2ctxGetMemInterMapParams__ = &__nvoc_thunk_RmResource_sec2ctxGetMemInterMapParams; + + pThis->__sec2ctxGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_sec2ctxGetMemoryMappingDescriptor; + + pThis->__sec2ctxIsSwMethodStalling__ = &__nvoc_thunk_ChannelDescendant_sec2ctxIsSwMethodStalling; + + pThis->__sec2ctxControlFilter__ = &__nvoc_thunk_RsResource_sec2ctxControlFilter; + + pThis->__sec2ctxUnregisterEvent__ = &__nvoc_thunk_Notifier_sec2ctxUnregisterEvent; + + pThis->__sec2ctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_sec2ctxControlSerialization_Prologue; + + pThis->__sec2ctxCanCopy__ = &__nvoc_thunk_RsResource_sec2ctxCanCopy; + + pThis->__sec2ctxPreDestruct__ = &__nvoc_thunk_RsResource_sec2ctxPreDestruct; + + pThis->__sec2ctxIsDuplicate__ = &__nvoc_thunk_RsResource_sec2ctxIsDuplicate; + + pThis->__sec2ctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_sec2ctxControlSerialization_Epilogue; + + pThis->__sec2ctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_sec2ctxGetNotificationListPtr; + + pThis->__sec2ctxGetNotificationShare__ = &__nvoc_thunk_Notifier_sec2ctxGetNotificationShare; + + pThis->__sec2ctxMap__ = &__nvoc_thunk_GpuResource_sec2ctxMap; + + pThis->__sec2ctxGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_sec2ctxGetOrAllocNotifShare; +} + +void __nvoc_init_funcTable_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_Sec2Context_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_ChannelDescendant(ChannelDescendant*, RmHalspecOwner* ); +void __nvoc_init_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_Sec2Context = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource; + pThis->__nvoc_pbase_INotifier = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_Notifier.__nvoc_base_INotifier; + pThis->__nvoc_pbase_Notifier = &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_Notifier; + pThis->__nvoc_pbase_ChannelDescendant = &pThis->__nvoc_base_ChannelDescendant; + __nvoc_init_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant, pRmhalspecowner); + __nvoc_init_funcTable_Sec2Context(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + Sec2Context *pThis; + RmHalspecOwner *pRmhalspecowner; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Sec2Context), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(Sec2Context)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Sec2Context); + + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_Sec2Context(pThis, pRmhalspecowner); + status = __nvoc_ctor_Sec2Context(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_Sec2Context_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_Sec2Context_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Sec2Context)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_Sec2Context(Sec2Context **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_Sec2Context(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_sec2_context_nvoc.h b/src/nvidia/generated/g_sec2_context_nvoc.h new file mode 100644 index 0000000000..315d3fd463 --- /dev/null +++ b/src/nvidia/generated/g_sec2_context_nvoc.h @@ -0,0 +1,327 @@ +#ifndef _G_SEC2_CONTEXT_NVOC_H_ +#define _G_SEC2_CONTEXT_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_sec2_context_nvoc.h" + +#ifndef SEC2_CONTEXT_H +#define SEC2_CONTEXT_H + +#include "core/bin_data.h" +#include "core/core.h" +#include "kernel/gpu/fifo/channel_descendant.h" + +/*! + * RM internal class representing NVXXXX_TSEC. Class is used for channel work + * submission. + */ +#ifdef NVOC_SEC2_CONTEXT_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct Sec2Context { + const struct NVOC_RTTI *__nvoc_rtti; + struct ChannelDescendant __nvoc_base_ChannelDescendant; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct INotifier *__nvoc_pbase_INotifier; + struct Notifier *__nvoc_pbase_Notifier; + struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; + struct Sec2Context *__nvoc_pbase_Sec2Context; + NV_STATUS (*__sec2ctxCheckMemInterUnmap__)(struct Sec2Context *, NvBool); + NvBool (*__sec2ctxShareCallback__)(struct Sec2Context *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NvBool (*__sec2ctxAccessCallback__)(struct Sec2Context *, struct RsClient *, void *, RsAccessRight); + NV_STATUS (*__sec2ctxMapTo__)(struct Sec2Context *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__sec2ctxGetMapAddrSpace__)(struct Sec2Context *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + void (*__sec2ctxSetNotificationShare__)(struct Sec2Context *, struct NotifShare *); + NvU32 (*__sec2ctxGetRefCount__)(struct Sec2Context *); + void (*__sec2ctxAddAdditionalDependants__)(struct RsClient *, struct Sec2Context *, RsResourceRef *); + NV_STATUS (*__sec2ctxControl_Prologue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sec2ctxGetRegBaseOffsetAndSize__)(struct Sec2Context *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__sec2ctxInternalControlForward__)(struct Sec2Context *, NvU32, void *, NvU32); + NV_STATUS (*__sec2ctxUnmapFrom__)(struct Sec2Context *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__sec2ctxControl_Epilogue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sec2ctxControlLookup__)(struct Sec2Context *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__sec2ctxGetSwMethods__)(struct Sec2Context *, const METHOD **, NvU32 *); + NvHandle (*__sec2ctxGetInternalObjectHandle__)(struct Sec2Context *); + NV_STATUS (*__sec2ctxControl__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sec2ctxUnmap__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__sec2ctxGetMemInterMapParams__)(struct Sec2Context *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__sec2ctxGetMemoryMappingDescriptor__)(struct Sec2Context *, struct MEMORY_DESCRIPTOR **); + NvBool (*__sec2ctxIsSwMethodStalling__)(struct Sec2Context *, NvU32); + NV_STATUS (*__sec2ctxControlFilter__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sec2ctxUnregisterEvent__)(struct Sec2Context *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__sec2ctxControlSerialization_Prologue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__sec2ctxCanCopy__)(struct Sec2Context *); + void (*__sec2ctxPreDestruct__)(struct Sec2Context *); + NV_STATUS (*__sec2ctxIsDuplicate__)(struct Sec2Context *, NvHandle, NvBool *); + void (*__sec2ctxControlSerialization_Epilogue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + PEVENTNOTIFICATION *(*__sec2ctxGetNotificationListPtr__)(struct Sec2Context *); + struct NotifShare *(*__sec2ctxGetNotificationShare__)(struct Sec2Context *); + NV_STATUS (*__sec2ctxMap__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NV_STATUS (*__sec2ctxGetOrAllocNotifShare__)(struct Sec2Context *, NvHandle, NvHandle, struct NotifShare **); +}; + +#ifndef __NVOC_CLASS_Sec2Context_TYPEDEF__ +#define __NVOC_CLASS_Sec2Context_TYPEDEF__ +typedef struct Sec2Context Sec2Context; +#endif /* __NVOC_CLASS_Sec2Context_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Sec2Context +#define __nvoc_class_id_Sec2Context 0x4c3439 +#endif /* __nvoc_class_id_Sec2Context */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Sec2Context; + +#define __staticCast_Sec2Context(pThis) \ + ((pThis)->__nvoc_pbase_Sec2Context) + +#ifdef __nvoc_sec2_context_h_disabled +#define __dynamicCast_Sec2Context(pThis) ((Sec2Context*)NULL) +#else //__nvoc_sec2_context_h_disabled +#define __dynamicCast_Sec2Context(pThis) \ + ((Sec2Context*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(Sec2Context))) +#endif //__nvoc_sec2_context_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_Sec2Context(Sec2Context**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_Sec2Context(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_Sec2Context((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define sec2ctxCheckMemInterUnmap(pChannelDescendant, bSubdeviceHandleProvided) sec2ctxCheckMemInterUnmap_DISPATCH(pChannelDescendant, bSubdeviceHandleProvided) +#define sec2ctxShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) sec2ctxShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define sec2ctxAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) sec2ctxAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define sec2ctxMapTo(pResource, pParams) sec2ctxMapTo_DISPATCH(pResource, pParams) +#define sec2ctxGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) sec2ctxGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define sec2ctxSetNotificationShare(pNotifier, pNotifShare) sec2ctxSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define sec2ctxGetRefCount(pResource) sec2ctxGetRefCount_DISPATCH(pResource) +#define sec2ctxAddAdditionalDependants(pClient, pResource, pReference) sec2ctxAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define sec2ctxControl_Prologue(pResource, pCallContext, pParams) sec2ctxControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) sec2ctxGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define sec2ctxInternalControlForward(pGpuResource, command, pParams, size) sec2ctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define sec2ctxUnmapFrom(pResource, pParams) sec2ctxUnmapFrom_DISPATCH(pResource, pParams) +#define sec2ctxControl_Epilogue(pResource, pCallContext, pParams) sec2ctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxControlLookup(pResource, pParams, ppEntry) sec2ctxControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define sec2ctxGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) sec2ctxGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) +#define sec2ctxGetInternalObjectHandle(pGpuResource) sec2ctxGetInternalObjectHandle_DISPATCH(pGpuResource) +#define sec2ctxControl(pGpuResource, pCallContext, pParams) sec2ctxControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define sec2ctxUnmap(pGpuResource, pCallContext, pCpuMapping) sec2ctxUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define sec2ctxGetMemInterMapParams(pRmResource, pParams) sec2ctxGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define sec2ctxGetMemoryMappingDescriptor(pRmResource, ppMemDesc) sec2ctxGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define sec2ctxIsSwMethodStalling(pChannelDescendant, hHandle) sec2ctxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) +#define sec2ctxControlFilter(pResource, pCallContext, pParams) sec2ctxControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) sec2ctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define sec2ctxControlSerialization_Prologue(pResource, pCallContext, pParams) sec2ctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxCanCopy(pResource) sec2ctxCanCopy_DISPATCH(pResource) +#define sec2ctxPreDestruct(pResource) sec2ctxPreDestruct_DISPATCH(pResource) +#define sec2ctxIsDuplicate(pResource, hMemory, pDuplicate) sec2ctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define sec2ctxControlSerialization_Epilogue(pResource, pCallContext, pParams) sec2ctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define sec2ctxGetNotificationListPtr(pNotifier) sec2ctxGetNotificationListPtr_DISPATCH(pNotifier) +#define sec2ctxGetNotificationShare(pNotifier) sec2ctxGetNotificationShare_DISPATCH(pNotifier) +#define sec2ctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) sec2ctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define sec2ctxGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) sec2ctxGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +NV_STATUS sec2ctxConstructHal_KERNEL(struct Sec2Context *pSec2Context, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + + +#ifdef __nvoc_sec2_context_h_disabled +static inline NV_STATUS sec2ctxConstructHal(struct Sec2Context *pSec2Context, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + NV_ASSERT_FAILED_PRECOMP("Sec2Context was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_sec2_context_h_disabled +#define sec2ctxConstructHal(pSec2Context, pCallContext, pParams) sec2ctxConstructHal_KERNEL(pSec2Context, pCallContext, pParams) +#endif //__nvoc_sec2_context_h_disabled + +#define sec2ctxConstructHal_HAL(pSec2Context, pCallContext, pParams) sec2ctxConstructHal(pSec2Context, pCallContext, pParams) + +void sec2ctxDestructHal_KERNEL(struct Sec2Context *pSec2Context); + + +#ifdef __nvoc_sec2_context_h_disabled +static inline void sec2ctxDestructHal(struct Sec2Context *pSec2Context) { + NV_ASSERT_FAILED_PRECOMP("Sec2Context was disabled!"); +} +#else //__nvoc_sec2_context_h_disabled +#define sec2ctxDestructHal(pSec2Context) sec2ctxDestructHal_KERNEL(pSec2Context) +#endif //__nvoc_sec2_context_h_disabled + +#define sec2ctxDestructHal_HAL(pSec2Context) sec2ctxDestructHal(pSec2Context) + +static inline NV_STATUS sec2ctxCheckMemInterUnmap_DISPATCH(struct Sec2Context *pChannelDescendant, NvBool bSubdeviceHandleProvided) { + return pChannelDescendant->__sec2ctxCheckMemInterUnmap__(pChannelDescendant, bSubdeviceHandleProvided); +} + +static inline NvBool sec2ctxShareCallback_DISPATCH(struct Sec2Context *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__sec2ctxShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NvBool sec2ctxAccessCallback_DISPATCH(struct Sec2Context *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__sec2ctxAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +static inline NV_STATUS sec2ctxMapTo_DISPATCH(struct Sec2Context *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__sec2ctxMapTo__(pResource, pParams); +} + +static inline NV_STATUS sec2ctxGetMapAddrSpace_DISPATCH(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__sec2ctxGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline void sec2ctxSetNotificationShare_DISPATCH(struct Sec2Context *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__sec2ctxSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 sec2ctxGetRefCount_DISPATCH(struct Sec2Context *pResource) { + return pResource->__sec2ctxGetRefCount__(pResource); +} + +static inline void sec2ctxAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Sec2Context *pResource, RsResourceRef *pReference) { + pResource->__sec2ctxAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS sec2ctxControl_Prologue_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sec2ctxControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sec2ctxGetRegBaseOffsetAndSize_DISPATCH(struct Sec2Context *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__sec2ctxGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS sec2ctxInternalControlForward_DISPATCH(struct Sec2Context *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__sec2ctxInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS sec2ctxUnmapFrom_DISPATCH(struct Sec2Context *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__sec2ctxUnmapFrom__(pResource, pParams); +} + +static inline void sec2ctxControl_Epilogue_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__sec2ctxControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sec2ctxControlLookup_DISPATCH(struct Sec2Context *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__sec2ctxControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS sec2ctxGetSwMethods_DISPATCH(struct Sec2Context *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { + return pChannelDescendant->__sec2ctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); +} + +static inline NvHandle sec2ctxGetInternalObjectHandle_DISPATCH(struct Sec2Context *pGpuResource) { + return pGpuResource->__sec2ctxGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS sec2ctxControl_DISPATCH(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__sec2ctxControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS sec2ctxUnmap_DISPATCH(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__sec2ctxUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS sec2ctxGetMemInterMapParams_DISPATCH(struct Sec2Context *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__sec2ctxGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS sec2ctxGetMemoryMappingDescriptor_DISPATCH(struct Sec2Context *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__sec2ctxGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NvBool sec2ctxIsSwMethodStalling_DISPATCH(struct Sec2Context *pChannelDescendant, NvU32 hHandle) { + return pChannelDescendant->__sec2ctxIsSwMethodStalling__(pChannelDescendant, hHandle); +} + +static inline NV_STATUS sec2ctxControlFilter_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sec2ctxControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sec2ctxUnregisterEvent_DISPATCH(struct Sec2Context *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__sec2ctxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static inline NV_STATUS sec2ctxControlSerialization_Prologue_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sec2ctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool sec2ctxCanCopy_DISPATCH(struct Sec2Context *pResource) { + return pResource->__sec2ctxCanCopy__(pResource); +} + +static inline void sec2ctxPreDestruct_DISPATCH(struct Sec2Context *pResource) { + pResource->__sec2ctxPreDestruct__(pResource); +} + +static inline NV_STATUS sec2ctxIsDuplicate_DISPATCH(struct Sec2Context *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__sec2ctxIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void sec2ctxControlSerialization_Epilogue_DISPATCH(struct Sec2Context *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__sec2ctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline PEVENTNOTIFICATION *sec2ctxGetNotificationListPtr_DISPATCH(struct Sec2Context *pNotifier) { + return pNotifier->__sec2ctxGetNotificationListPtr__(pNotifier); +} + +static inline struct NotifShare *sec2ctxGetNotificationShare_DISPATCH(struct Sec2Context *pNotifier) { + return pNotifier->__sec2ctxGetNotificationShare__(pNotifier); +} + +static inline NV_STATUS sec2ctxMap_DISPATCH(struct Sec2Context *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__sec2ctxMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NV_STATUS sec2ctxGetOrAllocNotifShare_DISPATCH(struct Sec2Context *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return pNotifier->__sec2ctxGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); +} + +static inline NV_STATUS __nvoc_sec2ctxConstruct(struct Sec2Context *arg_pSec2Context, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams) { + return sec2ctxConstructHal(arg_pSec2Context, arg_pCallContext, arg_pParams); +} + +static inline void __nvoc_sec2ctxDestruct(struct Sec2Context *pSec2Context) { + sec2ctxDestructHal(pSec2Context); +} + +#undef PRIVATE_FIELD + + +#endif // SEC2_CONTEXT_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_SEC2_CONTEXT_NVOC_H_ diff --git a/src/nvidia/generated/g_sem_surf_nvoc.c b/src/nvidia/generated/g_sem_surf_nvoc.c new file mode 100644 index 0000000000..5e44ae444d --- /dev/null +++ b/src/nvidia/generated/g_sem_surf_nvoc.c @@ -0,0 +1,461 @@ +#define NVOC_SEM_SURF_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_sem_surf_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xeabc69 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_SemaphoreSurface; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_SemaphoreSurface(SemaphoreSurface*); +void __nvoc_init_funcTable_SemaphoreSurface(SemaphoreSurface*); +NV_STATUS __nvoc_ctor_SemaphoreSurface(SemaphoreSurface*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_SemaphoreSurface(SemaphoreSurface*); +void __nvoc_dtor_SemaphoreSurface(SemaphoreSurface*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_SemaphoreSurface; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_SemaphoreSurface = { + /*pClassDef=*/ &__nvoc_class_def_SemaphoreSurface, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_SemaphoreSurface, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SemaphoreSurface_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SemaphoreSurface, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_SemaphoreSurface = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_SemaphoreSurface_SemaphoreSurface, + &__nvoc_rtti_SemaphoreSurface_GpuResource, + &__nvoc_rtti_SemaphoreSurface_RmResource, + &__nvoc_rtti_SemaphoreSurface_RmResourceCommon, + &__nvoc_rtti_SemaphoreSurface_RsResource, + &__nvoc_rtti_SemaphoreSurface_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_SemaphoreSurface = +{ + /*classInfo=*/ { + /*size=*/ sizeof(SemaphoreSurface), + /*classId=*/ classId(SemaphoreSurface), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "SemaphoreSurface", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_SemaphoreSurface, + /*pCastInfo=*/ &__nvoc_castinfo_SemaphoreSurface, + /*pExportInfo=*/ &__nvoc_export_info_SemaphoreSurface +}; + +static NvBool __nvoc_thunk_SemaphoreSurface_resCanCopy(struct RsResource *pSemSurf) { + return semsurfCanCopy((struct SemaphoreSurface *)(((unsigned char *)pSemSurf) - __nvoc_rtti_SemaphoreSurface_RsResource.offset)); +} + +static NvBool __nvoc_thunk_GpuResource_semsurfShareCallback(struct SemaphoreSurface *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfCheckMemInterUnmap(struct SemaphoreSurface *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfMapTo(struct SemaphoreSurface *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfGetMapAddrSpace(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_semsurfGetRefCount(struct SemaphoreSurface *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_semsurfAddAdditionalDependants(struct RsClient *pClient, struct SemaphoreSurface *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfControl_Prologue(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfGetRegBaseOffsetAndSize(struct SemaphoreSurface *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfInternalControlForward(struct SemaphoreSurface *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfUnmapFrom(struct SemaphoreSurface *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_semsurfControl_Epilogue(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfControlLookup(struct SemaphoreSurface *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_semsurfGetInternalObjectHandle(struct SemaphoreSurface *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfControl(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfUnmap(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfGetMemInterMapParams(struct SemaphoreSurface *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfGetMemoryMappingDescriptor(struct SemaphoreSurface *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfControlFilter(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_semsurfControlSerialization_Prologue(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_semsurfPreDestruct(struct SemaphoreSurface *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_semsurfIsDuplicate(struct SemaphoreSurface *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_semsurfControlSerialization_Epilogue(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_semsurfMap(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_semsurfAccessCallback(struct SemaphoreSurface *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_SemaphoreSurface[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdRefMemory_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0001u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdRefMemory" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdBindChannel_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0002u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdBindChannel" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdRegisterWaiter_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0003u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdRegisterWaiter" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdSetValue_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0004u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdSetValue" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) semsurfCtrlCmdUnregisterWaiter_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xda0005u, + /*paramSize=*/ sizeof(NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_SemaphoreSurface.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "semsurfCtrlCmdUnregisterWaiter" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_SemaphoreSurface = +{ + /*numEntries=*/ 5, + /*pExportEntries=*/ __nvoc_exported_method_def_SemaphoreSurface +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_SemaphoreSurface(SemaphoreSurface *pThis) { + __nvoc_semsurfDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_SemaphoreSurface(SemaphoreSurface *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_SemaphoreSurface(SemaphoreSurface *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_SemaphoreSurface_fail_GpuResource; + __nvoc_init_dataField_SemaphoreSurface(pThis); + + status = __nvoc_semsurfConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_SemaphoreSurface_fail__init; + goto __nvoc_ctor_SemaphoreSurface_exit; // Success + +__nvoc_ctor_SemaphoreSurface_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_SemaphoreSurface_fail_GpuResource: +__nvoc_ctor_SemaphoreSurface_exit: + + return status; +} + +static void __nvoc_init_funcTable_SemaphoreSurface_1(SemaphoreSurface *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__semsurfCanCopy__ = &semsurfCanCopy_0c883b; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__semsurfCtrlCmdRefMemory__ = &semsurfCtrlCmdRefMemory_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + pThis->__semsurfCtrlCmdBindChannel__ = &semsurfCtrlCmdBindChannel_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__semsurfCtrlCmdRegisterWaiter__ = &semsurfCtrlCmdRegisterWaiter_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__semsurfCtrlCmdSetValue__ = &semsurfCtrlCmdSetValue_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__semsurfCtrlCmdUnregisterWaiter__ = &semsurfCtrlCmdUnregisterWaiter_IMPL; +#endif + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_SemaphoreSurface_resCanCopy; + + pThis->__semsurfShareCallback__ = &__nvoc_thunk_GpuResource_semsurfShareCallback; + + pThis->__semsurfCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_semsurfCheckMemInterUnmap; + + pThis->__semsurfMapTo__ = &__nvoc_thunk_RsResource_semsurfMapTo; + + pThis->__semsurfGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_semsurfGetMapAddrSpace; + + pThis->__semsurfGetRefCount__ = &__nvoc_thunk_RsResource_semsurfGetRefCount; + + pThis->__semsurfAddAdditionalDependants__ = &__nvoc_thunk_RsResource_semsurfAddAdditionalDependants; + + pThis->__semsurfControl_Prologue__ = &__nvoc_thunk_RmResource_semsurfControl_Prologue; + + pThis->__semsurfGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_semsurfGetRegBaseOffsetAndSize; + + pThis->__semsurfInternalControlForward__ = &__nvoc_thunk_GpuResource_semsurfInternalControlForward; + + pThis->__semsurfUnmapFrom__ = &__nvoc_thunk_RsResource_semsurfUnmapFrom; + + pThis->__semsurfControl_Epilogue__ = &__nvoc_thunk_RmResource_semsurfControl_Epilogue; + + pThis->__semsurfControlLookup__ = &__nvoc_thunk_RsResource_semsurfControlLookup; + + pThis->__semsurfGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_semsurfGetInternalObjectHandle; + + pThis->__semsurfControl__ = &__nvoc_thunk_GpuResource_semsurfControl; + + pThis->__semsurfUnmap__ = &__nvoc_thunk_GpuResource_semsurfUnmap; + + pThis->__semsurfGetMemInterMapParams__ = &__nvoc_thunk_RmResource_semsurfGetMemInterMapParams; + + pThis->__semsurfGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_semsurfGetMemoryMappingDescriptor; + + pThis->__semsurfControlFilter__ = &__nvoc_thunk_RsResource_semsurfControlFilter; + + pThis->__semsurfControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_semsurfControlSerialization_Prologue; + + pThis->__semsurfPreDestruct__ = &__nvoc_thunk_RsResource_semsurfPreDestruct; + + pThis->__semsurfIsDuplicate__ = &__nvoc_thunk_RsResource_semsurfIsDuplicate; + + pThis->__semsurfControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_semsurfControlSerialization_Epilogue; + + pThis->__semsurfMap__ = &__nvoc_thunk_GpuResource_semsurfMap; + + pThis->__semsurfAccessCallback__ = &__nvoc_thunk_RmResource_semsurfAccessCallback; +} + +void __nvoc_init_funcTable_SemaphoreSurface(SemaphoreSurface *pThis) { + __nvoc_init_funcTable_SemaphoreSurface_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_SemaphoreSurface(SemaphoreSurface *pThis) { + pThis->__nvoc_pbase_SemaphoreSurface = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_SemaphoreSurface(pThis); +} + +NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + SemaphoreSurface *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SemaphoreSurface), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(SemaphoreSurface)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SemaphoreSurface); + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_SemaphoreSurface(pThis); + status = __nvoc_ctor_SemaphoreSurface(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_SemaphoreSurface_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_SemaphoreSurface_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SemaphoreSurface)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_SemaphoreSurface(SemaphoreSurface **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_SemaphoreSurface(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_sem_surf_nvoc.h b/src/nvidia/generated/g_sem_surf_nvoc.h new file mode 100644 index 0000000000..f39f9edec7 --- /dev/null +++ b/src/nvidia/generated/g_sem_surf_nvoc.h @@ -0,0 +1,363 @@ +#ifndef _G_SEM_SURF_NVOC_H_ +#define _G_SEM_SURF_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_sem_surf_nvoc.h" + +#ifndef SEM_SURF_H +#define SEM_SURF_H + +#include "gpu/gpu_resource.h" // GpuResource +#include "mem_mgr/mem.h" +#include "rmapi/event.h" // EVENTNOTIFICATION + +#include "class/cl00da.h" // NV_SEMAPHORE_SURFACE +#include "ctrl/ctrl00da.h" // NV_SEMAPHORE_SURFACE_CTRL_* +#include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS + +typedef struct { + /* Value being waited for by pListeners list */ + NvU64 value; + + /* Value to set the semaphore to after wait value is reached */ + NvU64 newValue; + + /* Index of this value listener in the semaphore surface */ + NvU64 index; + + /* List of listeners waiting for the value */ + EVENTNOTIFICATION *pListeners; + + ListNode valueListEntry; + ListNode pendingNotificationsEntry; +} SEM_VALUE_LISTENERS_NODE; + +MAKE_INTRUSIVE_LIST(SEM_VALUE_LISTENERS, SEM_VALUE_LISTENERS_NODE, valueListEntry); +MAKE_INTRUSIVE_LIST(SEM_PENDING_NOTIFICATIONS, SEM_VALUE_LISTENERS_NODE, pendingNotificationsEntry); + +typedef struct { + /* List of values being listened for at this index, ordered by value. */ + SEM_VALUE_LISTENERS listeners; + + MapNode node; +} SEM_INDEX_LISTENERS_NODE; + +MAKE_INTRUSIVE_MAP(SEM_INDEX_LISTENERS, + SEM_INDEX_LISTENERS_NODE, + node); + +typedef struct { + PORT_SPINLOCK *pSpinlock; + + /* Internal interrupt handler callback data */ + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubDevice; + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; + NvHandle hEvent; + NVOS10_EVENT_KERNEL_CALLBACK_EX callback; + + /* The client-mappable semaphore memory region and associated data */ + NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS layout; + struct Memory* pSemaphoreMem; + struct Memory* pMaxSubmittedMem; + NvP64 semKernAddr; + NvP64 maxSubmittedKernAddr; + NvU8 *pSem; + NvU8 *pMaxSubmitted; + + /* Client active CPU waiters list XXX Should be per (offset,value) pair */ + SEM_INDEX_LISTENERS listenerMap; + + /* Number of semaphore surface objects sharing this data */ + NvU32 refCount; + + /* True if this semaphore surface supports 64-bit semaphores */ + NvBool bIs64Bit; + + /* True if the GPU supports conditional traps/monitored fence */ + NvBool bHasMonitoredFence; +} SEM_SHARED_DATA; + +#ifdef NVOC_SEM_SURF_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct SemaphoreSurface { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct SemaphoreSurface *__nvoc_pbase_SemaphoreSurface; + NvBool (*__semsurfCanCopy__)(struct SemaphoreSurface *); + NV_STATUS (*__semsurfCtrlCmdRefMemory__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS *); + NV_STATUS (*__semsurfCtrlCmdBindChannel__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS *); + NV_STATUS (*__semsurfCtrlCmdRegisterWaiter__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS *); + NV_STATUS (*__semsurfCtrlCmdSetValue__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS *); + NV_STATUS (*__semsurfCtrlCmdUnregisterWaiter__)(struct SemaphoreSurface *, NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS *); + NvBool (*__semsurfShareCallback__)(struct SemaphoreSurface *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__semsurfCheckMemInterUnmap__)(struct SemaphoreSurface *, NvBool); + NV_STATUS (*__semsurfMapTo__)(struct SemaphoreSurface *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__semsurfGetMapAddrSpace__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__semsurfGetRefCount__)(struct SemaphoreSurface *); + void (*__semsurfAddAdditionalDependants__)(struct RsClient *, struct SemaphoreSurface *, RsResourceRef *); + NV_STATUS (*__semsurfControl_Prologue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfGetRegBaseOffsetAndSize__)(struct SemaphoreSurface *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__semsurfInternalControlForward__)(struct SemaphoreSurface *, NvU32, void *, NvU32); + NV_STATUS (*__semsurfUnmapFrom__)(struct SemaphoreSurface *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__semsurfControl_Epilogue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfControlLookup__)(struct SemaphoreSurface *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__semsurfGetInternalObjectHandle__)(struct SemaphoreSurface *); + NV_STATUS (*__semsurfControl__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfUnmap__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__semsurfGetMemInterMapParams__)(struct SemaphoreSurface *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__semsurfGetMemoryMappingDescriptor__)(struct SemaphoreSurface *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__semsurfControlFilter__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfControlSerialization_Prologue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__semsurfPreDestruct__)(struct SemaphoreSurface *); + NV_STATUS (*__semsurfIsDuplicate__)(struct SemaphoreSurface *, NvHandle, NvBool *); + void (*__semsurfControlSerialization_Epilogue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__semsurfMap__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__semsurfAccessCallback__)(struct SemaphoreSurface *, struct RsClient *, void *, RsAccessRight); + SEM_SHARED_DATA *pShared; +}; + +#ifndef __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +#define __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +typedef struct SemaphoreSurface SemaphoreSurface; +#endif /* __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SemaphoreSurface +#define __nvoc_class_id_SemaphoreSurface 0xeabc69 +#endif /* __nvoc_class_id_SemaphoreSurface */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_SemaphoreSurface; + +#define __staticCast_SemaphoreSurface(pThis) \ + ((pThis)->__nvoc_pbase_SemaphoreSurface) + +#ifdef __nvoc_sem_surf_h_disabled +#define __dynamicCast_SemaphoreSurface(pThis) ((SemaphoreSurface*)NULL) +#else //__nvoc_sem_surf_h_disabled +#define __dynamicCast_SemaphoreSurface(pThis) \ + ((SemaphoreSurface*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(SemaphoreSurface))) +#endif //__nvoc_sem_surf_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_SemaphoreSurface(SemaphoreSurface**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_SemaphoreSurface(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_SemaphoreSurface((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define semsurfCanCopy(pSemSurf) semsurfCanCopy_DISPATCH(pSemSurf) +#define semsurfCtrlCmdRefMemory(pSemaphoreSurf, pParams) semsurfCtrlCmdRefMemory_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfCtrlCmdBindChannel(pSemaphoreSurf, pParams) semsurfCtrlCmdBindChannel_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfCtrlCmdRegisterWaiter(pSemaphoreSurf, pParams) semsurfCtrlCmdRegisterWaiter_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfCtrlCmdSetValue(pSemaphoreSurf, pParams) semsurfCtrlCmdSetValue_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfCtrlCmdUnregisterWaiter(pSemaphoreSurf, pParams) semsurfCtrlCmdUnregisterWaiter_DISPATCH(pSemaphoreSurf, pParams) +#define semsurfShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) semsurfShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define semsurfCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) semsurfCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define semsurfMapTo(pResource, pParams) semsurfMapTo_DISPATCH(pResource, pParams) +#define semsurfGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) semsurfGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define semsurfGetRefCount(pResource) semsurfGetRefCount_DISPATCH(pResource) +#define semsurfAddAdditionalDependants(pClient, pResource, pReference) semsurfAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define semsurfControl_Prologue(pResource, pCallContext, pParams) semsurfControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) semsurfGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define semsurfInternalControlForward(pGpuResource, command, pParams, size) semsurfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define semsurfUnmapFrom(pResource, pParams) semsurfUnmapFrom_DISPATCH(pResource, pParams) +#define semsurfControl_Epilogue(pResource, pCallContext, pParams) semsurfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfControlLookup(pResource, pParams, ppEntry) semsurfControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define semsurfGetInternalObjectHandle(pGpuResource) semsurfGetInternalObjectHandle_DISPATCH(pGpuResource) +#define semsurfControl(pGpuResource, pCallContext, pParams) semsurfControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define semsurfUnmap(pGpuResource, pCallContext, pCpuMapping) semsurfUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define semsurfGetMemInterMapParams(pRmResource, pParams) semsurfGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define semsurfGetMemoryMappingDescriptor(pRmResource, ppMemDesc) semsurfGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define semsurfControlFilter(pResource, pCallContext, pParams) semsurfControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define semsurfControlSerialization_Prologue(pResource, pCallContext, pParams) semsurfControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfPreDestruct(pResource) semsurfPreDestruct_DISPATCH(pResource) +#define semsurfIsDuplicate(pResource, hMemory, pDuplicate) semsurfIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define semsurfControlSerialization_Epilogue(pResource, pCallContext, pParams) semsurfControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfMap(pGpuResource, pCallContext, pParams, pCpuMapping) semsurfMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define semsurfAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) semsurfAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +static inline NvBool semsurfCanCopy_0c883b(struct SemaphoreSurface *pSemSurf) { + return ((NvBool)(0 == 0)); +} + +static inline NvBool semsurfCanCopy_DISPATCH(struct SemaphoreSurface *pSemSurf) { + return pSemSurf->__semsurfCanCopy__(pSemSurf); +} + +NV_STATUS semsurfCtrlCmdRefMemory_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdRefMemory_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdRefMemory__(pSemaphoreSurf, pParams); +} + +NV_STATUS semsurfCtrlCmdBindChannel_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdBindChannel_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdBindChannel__(pSemaphoreSurf, pParams); +} + +NV_STATUS semsurfCtrlCmdRegisterWaiter_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdRegisterWaiter_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdRegisterWaiter__(pSemaphoreSurf, pParams); +} + +NV_STATUS semsurfCtrlCmdSetValue_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdSetValue_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdSetValue__(pSemaphoreSurf, pParams); +} + +NV_STATUS semsurfCtrlCmdUnregisterWaiter_IMPL(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS *pParams); + +static inline NV_STATUS semsurfCtrlCmdUnregisterWaiter_DISPATCH(struct SemaphoreSurface *pSemaphoreSurf, NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS *pParams) { + return pSemaphoreSurf->__semsurfCtrlCmdUnregisterWaiter__(pSemaphoreSurf, pParams); +} + +static inline NvBool semsurfShareCallback_DISPATCH(struct SemaphoreSurface *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__semsurfShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS semsurfCheckMemInterUnmap_DISPATCH(struct SemaphoreSurface *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__semsurfCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS semsurfMapTo_DISPATCH(struct SemaphoreSurface *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__semsurfMapTo__(pResource, pParams); +} + +static inline NV_STATUS semsurfGetMapAddrSpace_DISPATCH(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__semsurfGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 semsurfGetRefCount_DISPATCH(struct SemaphoreSurface *pResource) { + return pResource->__semsurfGetRefCount__(pResource); +} + +static inline void semsurfAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct SemaphoreSurface *pResource, RsResourceRef *pReference) { + pResource->__semsurfAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS semsurfControl_Prologue_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__semsurfControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfGetRegBaseOffsetAndSize_DISPATCH(struct SemaphoreSurface *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__semsurfGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS semsurfInternalControlForward_DISPATCH(struct SemaphoreSurface *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__semsurfInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS semsurfUnmapFrom_DISPATCH(struct SemaphoreSurface *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__semsurfUnmapFrom__(pResource, pParams); +} + +static inline void semsurfControl_Epilogue_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__semsurfControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfControlLookup_DISPATCH(struct SemaphoreSurface *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__semsurfControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle semsurfGetInternalObjectHandle_DISPATCH(struct SemaphoreSurface *pGpuResource) { + return pGpuResource->__semsurfGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS semsurfControl_DISPATCH(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__semsurfControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfUnmap_DISPATCH(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__semsurfUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS semsurfGetMemInterMapParams_DISPATCH(struct SemaphoreSurface *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__semsurfGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS semsurfGetMemoryMappingDescriptor_DISPATCH(struct SemaphoreSurface *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__semsurfGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS semsurfControlFilter_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__semsurfControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfControlSerialization_Prologue_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__semsurfControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void semsurfPreDestruct_DISPATCH(struct SemaphoreSurface *pResource) { + pResource->__semsurfPreDestruct__(pResource); +} + +static inline NV_STATUS semsurfIsDuplicate_DISPATCH(struct SemaphoreSurface *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__semsurfIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void semsurfControlSerialization_Epilogue_DISPATCH(struct SemaphoreSurface *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__semsurfControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS semsurfMap_DISPATCH(struct SemaphoreSurface *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__semsurfMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool semsurfAccessCallback_DISPATCH(struct SemaphoreSurface *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__semsurfAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS semsurfConstruct_IMPL(struct SemaphoreSurface *arg_semaphoreSurf, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_semsurfConstruct(arg_semaphoreSurf, arg_pCallContext, arg_pParams) semsurfConstruct_IMPL(arg_semaphoreSurf, arg_pCallContext, arg_pParams) +void semsurfDestruct_IMPL(struct SemaphoreSurface *pSemSurf); + +#define __nvoc_semsurfDestruct(pSemSurf) semsurfDestruct_IMPL(pSemSurf) +#undef PRIVATE_FIELD + + +#endif // SEM_SURF_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_SEM_SURF_NVOC_H_ diff --git a/src/nvidia/generated/g_spdm_nvoc.c b/src/nvidia/generated/g_spdm_nvoc.c new file mode 100644 index 0000000000..d3e7b667fb --- /dev/null +++ b/src/nvidia/generated/g_spdm_nvoc.c @@ -0,0 +1,266 @@ +#define NVOC_SPDM_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_spdm_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x261ee8 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Spdm; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_Spdm(Spdm*, RmHalspecOwner* ); +void __nvoc_init_funcTable_Spdm(Spdm*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_Spdm(Spdm*, RmHalspecOwner* ); +void __nvoc_init_dataField_Spdm(Spdm*, RmHalspecOwner* ); +void __nvoc_dtor_Spdm(Spdm*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Spdm; + +static const struct NVOC_RTTI __nvoc_rtti_Spdm_Spdm = { + /*pClassDef=*/ &__nvoc_class_def_Spdm, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_Spdm, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_Spdm_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(Spdm, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_Spdm = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_Spdm_Spdm, + &__nvoc_rtti_Spdm_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_Spdm = +{ + /*classInfo=*/ { + /*size=*/ sizeof(Spdm), + /*classId=*/ classId(Spdm), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "Spdm", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_Spdm, + /*pCastInfo=*/ &__nvoc_castinfo_Spdm, + /*pExportInfo=*/ &__nvoc_export_info_Spdm +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_Spdm = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_Spdm(Spdm *pThis) { + __nvoc_spdmDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_Spdm_fail_Object; + __nvoc_init_dataField_Spdm(pThis, pRmhalspecowner); + + status = __nvoc_spdmConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_Spdm_fail__init; + goto __nvoc_ctor_Spdm_exit; // Success + +__nvoc_ctor_Spdm_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_Spdm_fail_Object: +__nvoc_ctor_Spdm_exit: + + return status; +} + +static void __nvoc_init_funcTable_Spdm_1(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + // Hal function -- spdmGetCertChains + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmGetCertChains__ = &spdmGetCertChains_GH100; + } + // default + else + { + pThis->__spdmGetCertChains__ = &spdmGetCertChains_46f6a7; + } + + // Hal function -- spdmGetAttestationReport + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmGetAttestationReport__ = &spdmGetAttestationReport_GH100; + } + // default + else + { + pThis->__spdmGetAttestationReport__ = &spdmGetAttestationReport_46f6a7; + } + + // Hal function -- spdmDeviceInit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmDeviceInit__ = &spdmDeviceInit_GH100; + } + // default + else + { + pThis->__spdmDeviceInit__ = &spdmDeviceInit_46f6a7; + } + + // Hal function -- spdmDeviceDeinit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmDeviceDeinit__ = &spdmDeviceDeinit_GH100; + } + // default + else + { + pThis->__spdmDeviceDeinit__ = &spdmDeviceDeinit_46f6a7; + } + + // Hal function -- spdmDeviceSecuredSessionSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmDeviceSecuredSessionSupported__ = &spdmDeviceSecuredSessionSupported_GH100; + } + // default + else + { + pThis->__spdmDeviceSecuredSessionSupported__ = &spdmDeviceSecuredSessionSupported_46f6a7; + } + + // Hal function -- spdmCheckConnection + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmCheckConnection__ = &spdmCheckConnection_GH100; + } + // default + else + { + pThis->__spdmCheckConnection__ = &spdmCheckConnection_46f6a7; + } + + // Hal function -- spdmMessageProcess + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmMessageProcess__ = &spdmMessageProcess_GH100; + } + // default + else + { + pThis->__spdmMessageProcess__ = &spdmMessageProcess_46f6a7; + } + + // Hal function -- spdmGetCertificates + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmGetCertificates__ = &spdmGetCertificates_GH100; + } + // default + else + { + pThis->__spdmGetCertificates__ = &spdmGetCertificates_46f6a7; + } +} + +void __nvoc_init_funcTable_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_Spdm_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_Spdm = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_Spdm(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_Spdm(Spdm **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + Spdm *pThis; + RmHalspecOwner *pRmhalspecowner; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Spdm), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(Spdm)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Spdm); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_Spdm(pThis, pRmhalspecowner); + status = __nvoc_ctor_Spdm(pThis, pRmhalspecowner); + if (status != NV_OK) goto __nvoc_objCreate_Spdm_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_Spdm_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Spdm)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_Spdm(Spdm **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_Spdm(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_spdm_nvoc.h b/src/nvidia/generated/g_spdm_nvoc.h new file mode 100644 index 0000000000..00fa820764 --- /dev/null +++ b/src/nvidia/generated/g_spdm_nvoc.h @@ -0,0 +1,291 @@ +#ifndef _G_SPDM_NVOC_H_ +#define _G_SPDM_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_spdm_nvoc.h" + +#ifndef NV_SPDM_H +#define NV_SPDM_H +// SPDM_H may conflict with libspdm headers. + +#include "gpu/gpu.h" +#include "nvport/nvport.h" + +/****************************************************************************\ + * * + * SPDM module header. * + * * + ****************************************************************************/ + +/* ------------------------ Macros ----------------------------------------- */ +#define HAL_MAPPING_ONLY_IF_SPDM_SUPPORTED_IMPL \ + { \ + default: _IMPL; \ + } +#define HAL_MAPPING_ONLY_IF_SPDM_SUPPORTED_HAL \ + { \ + GH100 : _GH100; \ + default : return NV_ERR_NOT_SUPPORTED; \ + } +#define HAL_MAPPING_ONLY_IF_SPDM_SUPPORTED_VOID \ + { \ + default: _IMPL; \ + } + +#ifdef NVOC_SPDM_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct Spdm { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct Spdm *__nvoc_pbase_Spdm; + NV_STATUS (*__spdmGetCertChains__)(struct OBJGPU *, struct Spdm *, void *, NvU32 *, void *, NvU32 *); + NV_STATUS (*__spdmGetAttestationReport__)(struct OBJGPU *, struct Spdm *, NvU8 *, void *, NvU32 *, NvBool *, void *, NvU32 *); + NV_STATUS (*__spdmDeviceInit__)(struct OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmDeviceDeinit__)(struct OBJGPU *, struct Spdm *, NvBool); + NV_STATUS (*__spdmDeviceSecuredSessionSupported__)(struct OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmCheckConnection__)(struct OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmMessageProcess__)(struct OBJGPU *, struct Spdm *, NvU32, NvU8 *, NvU32, NvU8 *, NvU32 *); + NV_STATUS (*__spdmGetCertificates__)(struct OBJGPU *, struct Spdm *); + void *pLibspdmContext; + NvU32 libspdmContextSize; + void *pLibspdmScratch; + NvU32 libspdmScratchSize; + NvU32 sessionId; + NvU32 guestId; + NvU32 endpointId; + NvU8 *pAttestationCertChain; + size_t attestationCertChainSize; + void *pDeviceIOContext; + void *pLastExchange; + size_t lastExchangeSize; + NvBool bExportSecretCleared; +}; + +#ifndef __NVOC_CLASS_Spdm_TYPEDEF__ +#define __NVOC_CLASS_Spdm_TYPEDEF__ +typedef struct Spdm Spdm; +#endif /* __NVOC_CLASS_Spdm_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Spdm +#define __nvoc_class_id_Spdm 0x261ee8 +#endif /* __nvoc_class_id_Spdm */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Spdm; + +#define __staticCast_Spdm(pThis) \ + ((pThis)->__nvoc_pbase_Spdm) + +#ifdef __nvoc_spdm_h_disabled +#define __dynamicCast_Spdm(pThis) ((Spdm*)NULL) +#else //__nvoc_spdm_h_disabled +#define __dynamicCast_Spdm(pThis) \ + ((Spdm*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(Spdm))) +#endif //__nvoc_spdm_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_Spdm(Spdm**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_Spdm(Spdm**, Dynamic*, NvU32); +#define __objCreate_Spdm(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_Spdm((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define spdmGetCertChains(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) spdmGetCertChains_DISPATCH(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) +#define spdmGetCertChains_HAL(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) spdmGetCertChains_DISPATCH(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) +#define spdmGetAttestationReport(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) spdmGetAttestationReport_DISPATCH(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) +#define spdmGetAttestationReport_HAL(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) spdmGetAttestationReport_DISPATCH(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) +#define spdmDeviceInit(pGpu, pSpdm) spdmDeviceInit_DISPATCH(pGpu, pSpdm) +#define spdmDeviceInit_HAL(pGpu, pSpdm) spdmDeviceInit_DISPATCH(pGpu, pSpdm) +#define spdmDeviceDeinit(pGpu, pSpdm, bForceClear) spdmDeviceDeinit_DISPATCH(pGpu, pSpdm, bForceClear) +#define spdmDeviceDeinit_HAL(pGpu, pSpdm, bForceClear) spdmDeviceDeinit_DISPATCH(pGpu, pSpdm, bForceClear) +#define spdmDeviceSecuredSessionSupported(pGpu, pSpdm) spdmDeviceSecuredSessionSupported_DISPATCH(pGpu, pSpdm) +#define spdmDeviceSecuredSessionSupported_HAL(pGpu, pSpdm) spdmDeviceSecuredSessionSupported_DISPATCH(pGpu, pSpdm) +#define spdmCheckConnection(pGpu, pSpdm) spdmCheckConnection_DISPATCH(pGpu, pSpdm) +#define spdmCheckConnection_HAL(pGpu, pSpdm) spdmCheckConnection_DISPATCH(pGpu, pSpdm) +#define spdmMessageProcess(pGpu, pSpdm, ctrlCode, pRequest, requestSize, pResponse, pResponseSize) spdmMessageProcess_DISPATCH(pGpu, pSpdm, ctrlCode, pRequest, requestSize, pResponse, pResponseSize) +#define spdmMessageProcess_HAL(pGpu, pSpdm, ctrlCode, pRequest, requestSize, pResponse, pResponseSize) spdmMessageProcess_DISPATCH(pGpu, pSpdm, ctrlCode, pRequest, requestSize, pResponse, pResponseSize) +#define spdmGetCertificates(pGpu, pSpdm) spdmGetCertificates_DISPATCH(pGpu, pSpdm) +#define spdmGetCertificates_HAL(pGpu, pSpdm) spdmGetCertificates_DISPATCH(pGpu, pSpdm) +NV_STATUS spdmConstruct_IMPL(struct Spdm *arg_pSpdm); + + +#define __nvoc_spdmConstruct(arg_pSpdm) spdmConstruct_IMPL(arg_pSpdm) +void spdmDestruct_IMPL(struct Spdm *pSpdm); + + +#define __nvoc_spdmDestruct(pSpdm) spdmDestruct_IMPL(pSpdm) +NV_STATUS spdmContextInit_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmContextInit(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmContextInit(pGpu, pSpdm) spdmContextInit_IMPL(pGpu, pSpdm) +#endif //__nvoc_spdm_h_disabled + +#define spdmContextInit_HAL(pGpu, pSpdm) spdmContextInit(pGpu, pSpdm) + +NV_STATUS spdmContextDeinit_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmContextDeinit(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmContextDeinit(pGpu, pSpdm, bForceClear) spdmContextDeinit_IMPL(pGpu, pSpdm, bForceClear) +#endif //__nvoc_spdm_h_disabled + +#define spdmContextDeinit_HAL(pGpu, pSpdm, bForceClear) spdmContextDeinit(pGpu, pSpdm, bForceClear) + +NV_STATUS spdmStart_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmStart(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmStart(pGpu, pSpdm) spdmStart_IMPL(pGpu, pSpdm) +#endif //__nvoc_spdm_h_disabled + +#define spdmStart_HAL(pGpu, pSpdm) spdmStart(pGpu, pSpdm) + +NV_STATUS spdmRetrieveExportSecret_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keySize, NvU8 *pKeyOut); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmRetrieveExportSecret(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keySize, NvU8 *pKeyOut) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmRetrieveExportSecret(pGpu, pSpdm, keySize, pKeyOut) spdmRetrieveExportSecret_IMPL(pGpu, pSpdm, keySize, pKeyOut) +#endif //__nvoc_spdm_h_disabled + +#define spdmRetrieveExportSecret_HAL(pGpu, pSpdm, keySize, pKeyOut) spdmRetrieveExportSecret(pGpu, pSpdm, keySize, pKeyOut) + +NV_STATUS spdmGetCertChains_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize); + +static inline NV_STATUS spdmGetCertChains_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmGetCertChains_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize) { + return pSpdm->__spdmGetCertChains__(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize); +} + +NV_STATUS spdmGetAttestationReport_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize); + +static inline NV_STATUS spdmGetAttestationReport_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmGetAttestationReport_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize) { + return pSpdm->__spdmGetAttestationReport__(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize); +} + +NV_STATUS spdmDeviceInit_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmDeviceInit_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmDeviceInit_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmDeviceInit__(pGpu, pSpdm); +} + +NV_STATUS spdmDeviceDeinit_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear); + +static inline NV_STATUS spdmDeviceDeinit_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmDeviceDeinit_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { + return pSpdm->__spdmDeviceDeinit__(pGpu, pSpdm, bForceClear); +} + +NV_STATUS spdmDeviceSecuredSessionSupported_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmDeviceSecuredSessionSupported_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmDeviceSecuredSessionSupported_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmDeviceSecuredSessionSupported__(pGpu, pSpdm); +} + +NV_STATUS spdmCheckConnection_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmCheckConnection_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmCheckConnection_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmCheckConnection__(pGpu, pSpdm); +} + +NV_STATUS spdmMessageProcess_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 ctrlCode, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize); + +static inline NV_STATUS spdmMessageProcess_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 ctrlCode, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmMessageProcess_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 ctrlCode, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize) { + return pSpdm->__spdmMessageProcess__(pGpu, pSpdm, ctrlCode, pRequest, requestSize, pResponse, pResponseSize); +} + +NV_STATUS spdmGetCertificates_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmGetCertificates_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmGetCertificates_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmGetCertificates__(pGpu, pSpdm); +} + +#undef PRIVATE_FIELD + + +#endif // NV_SPDM_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_SPDM_NVOC_H_ diff --git a/src/nvidia/generated/g_standard_mem_nvoc.c b/src/nvidia/generated/g_standard_mem_nvoc.c index 5a572934db..c97b29ce32 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.c +++ b/src/nvidia/generated/g_standard_mem_nvoc.c @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_stdmemIsReady(struct StandardMemory *pMemor return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_stdmemCheckCopyPermissions(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_stdmemCheckCopyPermissions(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_stdmemPreDestruct(struct StandardMemory *pResource) { diff --git a/src/nvidia/generated/g_standard_mem_nvoc.h b/src/nvidia/generated/g_standard_mem_nvoc.h index a7bfad91d0..2984c5d46b 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.h +++ b/src/nvidia/generated/g_standard_mem_nvoc.h @@ -88,7 +88,7 @@ struct StandardMemory { NV_STATUS (*__stdmemControlFilter__)(struct StandardMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemControlSerialization_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemIsReady__)(struct StandardMemory *, NvBool); - NV_STATUS (*__stdmemCheckCopyPermissions__)(struct StandardMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__stdmemCheckCopyPermissions__)(struct StandardMemory *, struct OBJGPU *, struct Device *); void (*__stdmemPreDestruct__)(struct StandardMemory *); NV_STATUS (*__stdmemIsDuplicate__)(struct StandardMemory *, NvHandle, NvBool *); void (*__stdmemControlSerialization_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -143,17 +143,17 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory**, Dynamic*, NvU32, CAL #define stdmemControlFilter(pResource, pCallContext, pParams) stdmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define stdmemControlSerialization_Prologue(pResource, pCallContext, pParams) stdmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define stdmemIsReady(pMemory, bCopyConstructorContext) stdmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define stdmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) stdmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define stdmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) stdmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define stdmemPreDestruct(pResource) stdmemPreDestruct_DISPATCH(pResource) #define stdmemIsDuplicate(pMemory, hMemory, pDuplicate) stdmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define stdmemControlSerialization_Epilogue(pResource, pCallContext, pParams) stdmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define stdmemMap(pMemory, pCallContext, pParams, pCpuMapping) stdmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define stdmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) stdmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NvU32 stdmemGetSysmemPageSize_IMPL(struct OBJGPU *pGpu, struct StandardMemory *pMemory); +NvU64 stdmemGetSysmemPageSize_IMPL(struct OBJGPU *pGpu, struct StandardMemory *pMemory); #ifdef __nvoc_standard_mem_h_disabled -static inline NvU32 stdmemGetSysmemPageSize(struct OBJGPU *pGpu, struct StandardMemory *pMemory) { +static inline NvU64 stdmemGetSysmemPageSize(struct OBJGPU *pGpu, struct StandardMemory *pMemory) { NV_ASSERT_FAILED_PRECOMP("StandardMemory was disabled!"); return 0; } @@ -241,8 +241,8 @@ static inline NV_STATUS stdmemIsReady_DISPATCH(struct StandardMemory *pMemory, N return pMemory->__stdmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS stdmemCheckCopyPermissions_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__stdmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS stdmemCheckCopyPermissions_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__stdmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void stdmemPreDestruct_DISPATCH(struct StandardMemory *pResource) { diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index 16564f3502..b6536a0029 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -343,12 +343,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [7] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuExecRegOps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800122u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS), @@ -628,12 +628,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800145u, /*paramSize=*/ 0, @@ -643,12 +643,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [27] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuReleaseComputeModeReservation_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800146u, /*paramSize=*/ 0, @@ -868,12 +868,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [42] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuHandleGpuSR_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) + /*flags=*/ 0x3u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800167u, /*paramSize=*/ 0, @@ -1348,6 +1348,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [74] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800199u, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuSetEgmGpaFabricAddr" +#endif + }, + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1362,7 +1377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetEngineLoadTimes" #endif }, - { /* [75] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1377,7 +1392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetP2pCaps" #endif }, - { /* [76] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1392,13 +1407,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetComputeProfiles" #endif }, - { /* [77] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + { /* [78] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) - /*flags=*/ 0x50u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x208001a3u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS), @@ -1407,7 +1422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetGpuFabricProbeInfo" #endif }, - { /* [78] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1422,13 +1437,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetChipDetails" #endif }, - { /* [79] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [80] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuMigratableOps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x208001a6u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS), @@ -1437,7 +1452,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuMigratableOps" #endif }, - { /* [80] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1452,7 +1467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetResetStatus" #endif }, - { /* [81] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1467,7 +1482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetDrainAndResetStatus" #endif }, - { /* [82] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1482,7 +1497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2" #endif }, - { /* [83] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1497,7 +1512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetNotification" #endif }, - { /* [84] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1512,7 +1527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetTrigger" #endif }, - { /* [85] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1527,7 +1542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetMemoryNotifies" #endif }, - { /* [86] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1542,7 +1557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetSemaphoreMemory" #endif }, - { /* [87] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1557,7 +1572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetSemaMemValidation" #endif }, - { /* [88] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1572,7 +1587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetTriggerFifo" #endif }, - { /* [89] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1587,7 +1602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerSchedule" #endif }, - { /* [90] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1602,7 +1617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerCancel" #endif }, - { /* [91] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1617,7 +1632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetTime" #endif }, - { /* [92] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1632,7 +1647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetRegisterOffset" #endif }, - { /* [93] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1647,7 +1662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo" #endif }, - { /* [94] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1662,7 +1677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerSetGrTickFreq" #endif }, - { /* [95] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1677,7 +1692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cReadBuffer" #endif }, - { /* [96] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1692,7 +1707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cWriteBuffer" #endif }, - { /* [97] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1707,7 +1722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cReadReg" #endif }, - { /* [98] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1722,7 +1737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cWriteReg" #endif }, - { /* [99] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1737,7 +1752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetSKUInfo" #endif }, - { /* [100] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1752,7 +1767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetPostTime" #endif }, - { /* [101] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1767,7 +1782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetUefiSupport" #endif }, - { /* [102] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1782,7 +1797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetNbsiV2" #endif }, - { /* [103] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1797,7 +1812,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetInfoV2" #endif }, - { /* [104] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1812,7 +1827,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetStaticInfo" #endif }, - { /* [105] */ + { /* [106] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1827,7 +1842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysGetStaticConfig" #endif }, - { /* [106] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1842,7 +1857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer" #endif }, - { /* [107] */ + { /* [108] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1851,40 +1866,25 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*flags=*/ 0x600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a1eu, - /*paramSize=*/ 0, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer" #endif }, - { /* [108] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [109] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102600u) + /*flags=*/ 0x102600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a1fu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetCaps" -#endif - }, - { /* [109] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a21u, - /*paramSize=*/ 0, - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer" #endif }, { /* [110] */ @@ -1948,21 +1948,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [114] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a29u, - /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize" -#endif - }, - { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1977,7 +1962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetInfo" #endif }, - { /* [116] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1992,7 +1977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetZcullInfo" #endif }, - { /* [117] */ + { /* [116] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2007,7 +1992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetRopInfo" #endif }, - { /* [118] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2022,7 +2007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPpcMasks" #endif }, - { /* [119] */ + { /* [118] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2037,7 +2022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo" #endif }, - { /* [120] */ + { /* [119] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2052,7 +2037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier" #endif }, - { /* [121] */ + { /* [120] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2067,7 +2052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetChipInfo" #endif }, - { /* [122] */ + { /* [121] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2082,7 +2067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize" #endif }, - { /* [123] */ + { /* [122] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2097,7 +2082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines" #endif }, - { /* [124] */ + { /* [123] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2112,7 +2097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetDeviceInfoTable" #endif }, - { /* [125] */ + { /* [124] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2127,7 +2112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetUserRegisterAccessMap" #endif }, - { /* [126] */ + { /* [125] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2142,7 +2127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetConstructedFalconInfo" #endif }, - { /* [127] */ + { /* [126] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2157,7 +2142,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPdbProperties" #endif }, - { /* [128] */ + { /* [127] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2172,7 +2157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayWriteInstMem" #endif }, - { /* [129] */ + { /* [128] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2187,7 +2172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRecoverAllComputeContexts" #endif }, - { /* [130] */ + { /* [129] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2202,7 +2187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetIpVersion" #endif }, - { /* [131] */ + { /* [130] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2217,7 +2202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetSmcMode" #endif }, - { /* [132] */ + { /* [131] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2232,7 +2217,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetupRgLineIntr" #endif }, - { /* [133] */ + { /* [132] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2247,7 +2232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysSetPartitionableMem" #endif }, - { /* [134] */ + { /* [133] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2262,7 +2247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers" #endif }, - { /* [135] */ + { /* [134] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2277,7 +2262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetImportedImpData" #endif }, - { /* [136] */ + { /* [135] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2292,7 +2277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries" #endif }, - { /* [137] */ + { /* [136] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2307,7 +2292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetChannelPushbuffer" #endif }, - { /* [138] */ + { /* [137] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2322,7 +2307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGmmuGetStaticInfo" #endif }, - { /* [139] */ + { /* [138] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2337,7 +2322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetHeapReservationSize" #endif }, - { /* [140] */ + { /* [139] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2352,7 +2337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdIntrGetKernelTable" #endif }, - { /* [141] */ + { /* [140] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2367,13 +2352,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetDisplayMask" #endif }, - { /* [142] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + { /* [141] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2e50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalFifoGetNumChannels_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) - /*flags=*/ 0x2610u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2e50u) + /*flags=*/ 0x2e50u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a61u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS), @@ -2382,7 +2367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumChannels" #endif }, - { /* [143] */ + { /* [142] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2397,7 +2382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles" #endif }, - { /* [144] */ + { /* [143] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2412,7 +2397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetPartitionableEngines" #endif }, - { /* [145] */ + { /* [144] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2427,7 +2412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges" #endif }, - { /* [146] */ + { /* [145] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2442,7 +2427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKMemSysGetMIGMemoryConfig" #endif }, - { /* [147] */ + { /* [146] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2457,7 +2442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetZbcReferenced" #endif }, - { /* [148] */ + { /* [147] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2472,7 +2457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRcWatchdogTimeout" #endif }, - { /* [149] */ + { /* [148] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2487,7 +2472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysGetMIGMemoryPartitionTable" #endif }, - { /* [150] */ + { /* [149] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2502,7 +2487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysL2InvalidateEvict" #endif }, - { /* [151] */ + { /* [150] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2517,7 +2502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysFlushL2AllRamsAndCaches" #endif }, - { /* [152] */ + { /* [151] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2532,7 +2517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysDisableNvlinkPeers" #endif }, - { /* [153] */ + { /* [152] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2547,7 +2532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysProgramRawCompressionMode" #endif }, - { /* [154] */ + { /* [153] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2562,7 +2547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusFlushWithSysmembar" #endif }, - { /* [155] */ + { /* [154] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2577,7 +2562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal" #endif }, - { /* [156] */ + { /* [155] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2592,7 +2577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote" #endif }, - { /* [157] */ + { /* [156] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2607,7 +2592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusDestroyP2pMailbox" #endif }, - { /* [158] */ + { /* [157] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2622,7 +2607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusCreateC2cPeerMapping" #endif }, - { /* [159] */ + { /* [158] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2637,41 +2622,71 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping" #endif }, - { /* [160] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + { /* [159] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfCudaLimitDisable_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - /*flags=*/ 0x610u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayUnixConsole_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a7au, - /*paramSize=*/ 0, + /*methodId=*/ 0x20800a76u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalPerfCudaLimitDisable" + /*func=*/ "subdeviceCtrlCmdDisplayUnixConsole" #endif }, - { /* [161] */ + { /* [160] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayPostVgaRestore_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a7bu, - /*paramSize=*/ 0, + /*methodId=*/ 0x20800a77u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit" + /*func=*/ "subdeviceCtrlCmdDisplayPostVgaRestore" #endif }, - { /* [162] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [161] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfOptpCliClear_IMPL, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfCudaLimitDisable_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a7au, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfCudaLimitDisable" +#endif + }, + { /* [162] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a7bu, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit" +#endif + }, + { /* [163] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfOptpCliClear_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, @@ -2682,7 +2697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfOptpCliClear" #endif }, - { /* [163] */ + { /* [164] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2697,7 +2712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncSetControl" #endif }, - { /* [164] */ + { /* [165] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2712,7 +2727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfSyncGpuBoostSetLimits" #endif }, - { /* [165] */ + { /* [166] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2727,7 +2742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncGetInfo" #endif }, - { /* [166] */ + { /* [167] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2742,7 +2757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGetAuxPowerState" #endif }, - { /* [167] */ + { /* [168] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2757,7 +2772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubPeerConnConfig" #endif }, - { /* [168] */ + { /* [169] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2772,7 +2787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubFirstLinkPeerId" #endif }, - { /* [169] */ + { /* [170] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2787,7 +2802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubGetHshubIdForLinks" #endif }, - { /* [170] */ + { /* [171] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2802,7 +2817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubGetNumUnits" #endif }, - { /* [171] */ + { /* [172] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2817,7 +2832,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubNextHshubId" #endif }, - { /* [172] */ + { /* [173] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdHshubEgmConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a8du, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdHshubEgmConfig" +#endif + }, + { /* [174] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2832,7 +2862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationCheck" #endif }, - { /* [173] */ + { /* [175] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2847,7 +2877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet" #endif }, - { /* [174] */ + { /* [176] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2862,7 +2892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_2x" #endif }, - { /* [175] */ + { /* [177] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2877,7 +2907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer" #endif }, - { /* [176] */ + { /* [178] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2892,7 +2922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer" #endif }, - { /* [177] */ + { /* [179] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2907,7 +2937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer" #endif }, - { /* [178] */ + { /* [180] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2922,7 +2952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer" #endif }, - { /* [179] */ + { /* [181] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2937,7 +2967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer" #endif }, - { /* [180] */ + { /* [182] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2952,7 +2982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_3x" #endif }, - { /* [181] */ + { /* [183] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2967,7 +2997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostClear_3x" #endif }, - { /* [182] */ + { /* [184] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2982,7 +3012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance" #endif }, - { /* [183] */ + { /* [185] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2997,7 +3027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance" #endif }, - { /* [184] */ + { /* [186] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3012,7 +3042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifGetStaticInfo" #endif }, - { /* [185] */ + { /* [187] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3027,7 +3057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr" #endif }, - { /* [186] */ + { /* [188] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3042,13 +3072,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr" #endif }, - { /* [187] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [189] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBifGetAspmL1Flags_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) + /*flags=*/ 0xe40u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800ab0u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS), @@ -3057,7 +3087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifGetAspmL1Flags" #endif }, - { /* [188] */ + { /* [190] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3072,7 +3102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount" #endif }, - { /* [189] */ + { /* [191] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3087,7 +3117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuMap" #endif }, - { /* [190] */ + { /* [192] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3102,7 +3132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuUnmap" #endif }, - { /* [191] */ + { /* [193] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3117,7 +3147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalSetP2pCaps" #endif }, - { /* [192] */ + { /* [194] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3132,7 +3162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRemoveP2pCaps" #endif }, - { /* [193] */ + { /* [195] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3147,7 +3177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetPcieP2pCaps" #endif }, - { /* [194] */ + { /* [196] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3162,7 +3192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifSetPcieRo" #endif }, - { /* [195] */ + { /* [197] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3177,7 +3207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles" #endif }, - { /* [196] */ + { /* [198] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3192,7 +3222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuSetStreamState" #endif }, - { /* [197] */ + { /* [199] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3207,7 +3237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalInitGpuIntr" #endif }, - { /* [198] */ + { /* [200] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3222,7 +3252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncOptimizeTiming" #endif }, - { /* [199] */ + { /* [201] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3237,7 +3267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncGetDisplayIds" #endif }, - { /* [200] */ + { /* [202] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3252,7 +3282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncSetStereoSync" #endif }, - { /* [201] */ + { /* [203] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3267,7 +3297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFbsrInit" #endif }, - { /* [202] */ + { /* [204] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3282,7 +3312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFbsrSendRegionInfo" #endif }, - { /* [203] */ + { /* [205] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3297,7 +3327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncGetVactiveLines" #endif }, - { /* [204] */ + { /* [206] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3312,7 +3342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb" #endif }, - { /* [205] */ + { /* [207] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3327,13 +3357,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPostInitBrightcStateLoad" #endif }, - { /* [206] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [208] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) + /*flags=*/ 0x100600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800ac7u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS), @@ -3342,13 +3372,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl" #endif }, - { /* [207] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [209] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) + /*flags=*/ 0x100600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800ac8u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS), @@ -3357,7 +3387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl" #endif }, - { /* [208] */ + { /* [210] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3372,7 +3402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncIsDisplayIdValid" #endif }, - { /* [209] */ + { /* [211] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3387,7 +3417,187 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync" #endif }, - { /* [210] */ + { /* [212] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800acbu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate" +#endif + }, + { /* [213] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800accu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync" +#endif + }, + { /* [214] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800acdu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync" +#endif + }, + { /* [215] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800aceu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State" +#endif + }, + { /* [216] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800acfu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State" +#endif + }, + { /* [217] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad0u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit" +#endif + }, + { /* [218] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad1u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit" +#endif + }, + { /* [219] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad2u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode" +#endif + }, + { /* [220] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad3u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2" +#endif + }, + { /* [221] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad4u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo" +#endif + }, + { /* [222] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad5u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping" +#endif + }, + { /* [223] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad6u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate" +#endif + }, + { /* [224] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3402,7 +3612,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumSecureChannels" #endif }, - { /* [211] */ + { /* [225] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdSpdmPartition_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad9u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdSpdmPartition" +#endif + }, + { /* [226] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3417,7 +3642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetCoherentFbApertureSize" #endif }, - { /* [212] */ + { /* [227] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3432,7 +3657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifDisableSystemMemoryAccess" #endif }, - { /* [213] */ + { /* [228] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3447,7 +3672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayPinsetsToLockpins" #endif }, - { /* [214] */ + { /* [229] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3462,22 +3687,157 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalDetectHsVideoBridge" #endif }, - { /* [215] */ + { /* [230] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adeu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl" +#endif + }, + { /* [231] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalSetStaticEdidData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adfu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalSetStaticEdidData" +#endif + }, + { /* [232] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800af0u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated" +#endif + }, + { /* [233] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalDisplayPreModeSet_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800af1u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalDisplayPreModeSet" +#endif + }, + { /* [234] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalDisplayPostModeSet_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800af2u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalDisplayPostModeSet" +#endif + }, + { /* [235] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalConfComputeGetStaticInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800af3u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalConfComputeGetStaticInfo" +#endif + }, + { /* [236] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800afau, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp" +#endif + }, + { /* [237] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGetLocalAtsConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800afbu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGetLocalAtsConfig" +#endif + }, + { /* [238] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalSetPeerAtsConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800afcu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalSetPeerAtsConfig" +#endif + }, + { /* [239] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_IMPL, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20800adeu, - /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS), + /*methodId=*/ 0x20800afdu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl" + /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo" #endif }, - { /* [216] */ + { /* [240] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3492,7 +3852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetGpfifo" #endif }, - { /* [217] */ + { /* [241] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3507,7 +3867,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoBindEngines" #endif }, - { /* [218] */ + { /* [242] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3522,13 +3882,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetOperationalProperties" #endif }, - { /* [219] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [243] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGetPhysicalChannelCount_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801108u, /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS), @@ -3537,7 +3897,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetPhysicalChannelCount" #endif }, - { /* [220] */ + { /* [244] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3552,13 +3912,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetInfo" #endif }, - { /* [221] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [245] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoDisableChannels_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080110bu, /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS), @@ -3567,7 +3927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableChannels" #endif }, - { /* [222] */ + { /* [246] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3582,7 +3942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetChannelMemInfo" #endif }, - { /* [223] */ + { /* [247] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3597,7 +3957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetUserdLocation" #endif }, - { /* [224] */ + { /* [248] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3612,7 +3972,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetDeviceInfoTable" #endif }, - { /* [225] */ + { /* [249] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3627,7 +3987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoClearFaultedBit" #endif }, - { /* [226] */ + { /* [250] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2310u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3642,7 +4002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoRunlistSetSchedPolicy" #endif }, - { /* [227] */ + { /* [251] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3657,7 +4017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoUpdateChannelInfo" #endif }, - { /* [228] */ + { /* [252] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3672,7 +4032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableUsermodeChannels" #endif }, - { /* [229] */ + { /* [253] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3687,7 +4047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb" #endif }, - { /* [230] */ + { /* [254] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3702,7 +4062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetAllocatedChannels" #endif }, - { /* [231] */ + { /* [255] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3717,7 +4077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfo" #endif }, - { /* [232] */ + { /* [256] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3732,7 +4092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullMode" #endif }, - { /* [233] */ + { /* [257] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3747,7 +4107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullInfo" #endif }, - { /* [234] */ + { /* [258] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3762,7 +4122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmMode" #endif }, - { /* [235] */ + { /* [259] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3777,7 +4137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullBind" #endif }, - { /* [236] */ + { /* [260] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3792,7 +4152,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmBind" #endif }, - { /* [237] */ + { /* [261] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3807,7 +4167,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetGpcTileMap" #endif }, - { /* [238] */ + { /* [262] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3822,7 +4182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswSmpcMode" #endif }, - { /* [239] */ + { /* [263] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3837,7 +4197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmToGpcTpcMappings" #endif }, - { /* [240] */ + { /* [264] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3852,7 +4212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetCtxswPreemptionMode" #endif }, - { /* [241] */ + { /* [265] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3867,7 +4227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPreemptionBind" #endif }, - { /* [242] */ + { /* [266] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3882,7 +4242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrPcSamplingMode" #endif }, - { /* [243] */ + { /* [267] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3897,7 +4257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetROPInfo" #endif }, - { /* [244] */ + { /* [268] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3912,7 +4272,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswStats" #endif }, - { /* [245] */ + { /* [269] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3927,7 +4287,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferSize" #endif }, - { /* [246] */ + { /* [270] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3942,7 +4302,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferInfo" #endif }, - { /* [247] */ + { /* [271] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3957,7 +4317,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGlobalSmOrder" #endif }, - { /* [248] */ + { /* [272] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3972,7 +4332,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCurrentResidentChannel" #endif }, - { /* [249] */ + { /* [273] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3987,7 +4347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetVatAlarmData" #endif }, - { /* [250] */ + { /* [274] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4002,7 +4362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetAttributeBufferSize" #endif }, - { /* [251] */ + { /* [275] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4017,7 +4377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolQuerySize" #endif }, - { /* [252] */ + { /* [276] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4032,7 +4392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolInitialize" #endif }, - { /* [253] */ + { /* [277] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4047,7 +4407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolAddSlots" #endif }, - { /* [254] */ + { /* [278] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4062,7 +4422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolRemoveSlots" #endif }, - { /* [255] */ + { /* [279] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4077,7 +4437,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [256] */ + { /* [280] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4092,7 +4452,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [257] */ + { /* [281] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4107,7 +4467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcMask" #endif }, - { /* [258] */ + { /* [282] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4122,7 +4482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetTpcMask" #endif }, - { /* [259] */ + { /* [283] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4137,7 +4497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [260] */ + { /* [284] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4152,7 +4512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetEngineContextProperties" #endif }, - { /* [261] */ + { /* [285] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4167,7 +4527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmIssueRateModifier" #endif }, - { /* [262] */ + { /* [286] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4182,7 +4542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUid" #endif }, - { /* [263] */ + { /* [287] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4197,7 +4557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPhysGpcMask" #endif }, - { /* [264] */ + { /* [288] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4212,7 +4572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPpcMask" #endif }, - { /* [265] */ + { /* [289] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4227,7 +4587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetNumTpcsForGpc" #endif }, - { /* [266] */ + { /* [290] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4242,7 +4602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswModes" #endif }, - { /* [267] */ + { /* [291] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4257,7 +4617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcTileMap" #endif }, - { /* [268] */ + { /* [292] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4272,7 +4632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullMask" #endif }, - { /* [269] */ + { /* [293] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4287,7 +4647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2" #endif }, - { /* [270] */ + { /* [294] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4302,7 +4662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo" #endif }, - { /* [271] */ + { /* [295] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4317,7 +4677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfo" #endif }, - { /* [272] */ + { /* [296] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4332,7 +4692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfoV2" #endif }, - { /* [273] */ + { /* [297] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4347,7 +4707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCarveoutAddressInfo" #endif }, - { /* [274] */ + { /* [298] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4362,7 +4722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCalibrationLockFailed" #endif }, - { /* [275] */ + { /* [299] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4377,7 +4737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbFlushGpuCache" #endif }, - { /* [276] */ + { /* [300] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4392,7 +4752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicy" #endif }, - { /* [277] */ + { /* [301] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4407,7 +4767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetBar1Offset" #endif }, - { /* [278] */ + { /* [302] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4422,7 +4782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicy" #endif }, - { /* [279] */ + { /* [303] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4437,7 +4797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbIsKind" #endif }, - { /* [280] */ + { /* [304] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4452,7 +4812,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheInfo" #endif }, - { /* [281] */ + { /* [305] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4467,7 +4827,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicyV2" #endif }, - { /* [282] */ + { /* [306] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4482,7 +4842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2" #endif }, - { /* [283] */ + { /* [307] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4497,7 +4857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFBRegionInfo" #endif }, - { /* [284] */ + { /* [308] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4512,7 +4872,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetOfflinedPages" #endif }, - { /* [285] */ + { /* [309] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4527,7 +4887,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetLTCInfoForFBP" #endif }, - { /* [286] */ + { /* [310] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4542,7 +4902,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbCBCOp" #endif }, - { /* [287] */ + { /* [311] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4557,7 +4917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCtagsForCbcEviction" #endif }, - { /* [288] */ + { /* [312] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4572,7 +4932,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetupVprRegion" #endif }, - { /* [289] */ + { /* [313] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4587,7 +4947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCliManagedOfflinedPages" #endif }, - { /* [290] */ + { /* [314] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4602,7 +4962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCompBitCopyConstructInfo" #endif }, - { /* [291] */ + { /* [315] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4617,7 +4977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetRrd" #endif }, - { /* [292] */ + { /* [316] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4632,7 +4992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetReadLimit" #endif }, - { /* [293] */ + { /* [317] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4647,7 +5007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetWriteLimit" #endif }, - { /* [294] */ + { /* [318] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4662,7 +5022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbPatchPbrForMining" #endif }, - { /* [295] */ + { /* [319] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4677,7 +5037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetMemAlignment" #endif }, - { /* [296] */ + { /* [320] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4692,7 +5052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRemappedRows" #endif }, - { /* [297] */ + { /* [321] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4707,7 +5067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFsInfo" #endif }, - { /* [298] */ + { /* [322] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4722,7 +5082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRowRemapperHistogram" #endif }, - { /* [299] */ + { /* [323] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4737,7 +5097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetDynamicOfflinedPages" #endif }, - { /* [300] */ + { /* [324] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4752,7 +5112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbUpdateNumaStatus" #endif }, - { /* [301] */ + { /* [325] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4767,7 +5127,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetNumaInfo" #endif }, - { /* [302] */ + { /* [326] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801352u, + /*paramSize=*/ sizeof(NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout" +#endif + }, + { /* [327] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4782,7 +5157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetArchInfo" #endif }, - { /* [303] */ + { /* [328] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4797,7 +5172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcServiceInterrupts" #endif }, - { /* [304] */ + { /* [329] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4812,7 +5187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetManufacturer" #endif }, - { /* [305] */ + { /* [330] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4827,7 +5202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcQueryHostclkSlowdownStatus" #endif }, - { /* [306] */ + { /* [331] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4842,7 +5217,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcSetHostclkSlowdownStatus" #endif }, - { /* [307] */ + { /* [332] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4857,7 +5232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcChangeReplayableFaultOwnership" #endif }, - { /* [308] */ + { /* [333] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4872,7 +5247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciInfo" #endif }, - { /* [309] */ + { /* [334] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4887,7 +5262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfo" #endif }, - { /* [310] */ + { /* [335] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4902,7 +5277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciBarInfo" #endif }, - { /* [311] */ + { /* [336] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4917,7 +5292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLinkWidth" #endif }, - { /* [312] */ + { /* [337] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4932,7 +5307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieSpeed" #endif }, - { /* [313] */ + { /* [338] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4947,7 +5322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetHwbcUpstreamPcieSpeed" #endif }, - { /* [314] */ + { /* [339] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4962,7 +5337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetHwbcUpstreamPcieSpeed" #endif }, - { /* [315] */ + { /* [340] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4977,7 +5352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusHWBCGetUpstreamBAR0" #endif }, - { /* [316] */ + { /* [341] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4992,7 +5367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusServiceGpuMultifunctionState" #endif }, - { /* [317] */ + { /* [342] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5007,7 +5382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexCounters" #endif }, - { /* [318] */ + { /* [343] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5022,7 +5397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexCounters" #endif }, - { /* [319] */ + { /* [344] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5037,7 +5412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusFreezePexCounters" #endif }, - { /* [320] */ + { /* [345] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5052,7 +5427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexLaneCounters" #endif }, - { /* [321] */ + { /* [346] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5067,7 +5442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieLtrLatency" #endif }, - { /* [322] */ + { /* [347] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5082,7 +5457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLtrLatency" #endif }, - { /* [323] */ + { /* [348] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5097,7 +5472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexUtilCounters" #endif }, - { /* [324] */ + { /* [349] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5112,7 +5487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexUtilCounters" #endif }, - { /* [325] */ + { /* [350] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5127,13 +5502,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetBFD" #endif }, - { /* [326] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [351] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetAspmDisableFlags_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801822u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS), @@ -5142,7 +5517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetAspmDisableFlags" #endif }, - { /* [327] */ + { /* [352] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5157,7 +5532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfoV2" #endif }, - { /* [328] */ + { /* [353] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5172,13 +5547,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusControlPublicAspmBits" #endif }, - { /* [329] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [354] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetNvlinkPeerIdMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801825u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS), @@ -5187,7 +5562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkPeerIdMask" #endif }, - { /* [330] */ + { /* [355] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5202,7 +5577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetEomParameters" #endif }, - { /* [331] */ + { /* [356] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5217,7 +5592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetUphyDlnCfgSpace" #endif }, - { /* [332] */ + { /* [357] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5232,7 +5607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetEomStatus" #endif }, - { /* [333] */ + { /* [358] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5247,7 +5622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieReqAtomicsCaps" #endif }, - { /* [334] */ + { /* [359] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5262,7 +5637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics" #endif }, - { /* [335] */ + { /* [360] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5277,7 +5652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetC2CInfo" #endif }, - { /* [336] */ + { /* [361] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5292,7 +5667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSysmemAccess" #endif }, - { /* [337] */ + { /* [362] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5307,7 +5682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetC2CErrorInfo" #endif }, - { /* [338] */ + { /* [363] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5322,7 +5697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetP2pMapping" #endif }, - { /* [339] */ + { /* [364] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5337,7 +5712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusUnsetP2pMapping" #endif }, - { /* [340] */ + { /* [365] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5352,7 +5727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKPerfBoost" #endif }, - { /* [341] */ + { /* [366] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5367,7 +5742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfSetPowerstate" #endif }, - { /* [342] */ + { /* [367] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5382,7 +5757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpGetControl" #endif }, - { /* [343] */ + { /* [368] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5397,7 +5772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpSetControl" #endif }, - { /* [344] */ + { /* [369] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5412,7 +5787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfSetAuxPowerState" #endif }, - { /* [345] */ + { /* [370] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5427,7 +5802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfReservePerfmonHw" #endif }, - { /* [346] */ + { /* [371] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5442,7 +5817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2" #endif }, - { /* [347] */ + { /* [372] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5457,7 +5832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReadVirtualMem" #endif }, - { /* [348] */ + { /* [373] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5472,7 +5847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorCount" #endif }, - { /* [349] */ + { /* [374] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5487,13 +5862,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSetCleanErrorHistory" #endif }, - { /* [350] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [375] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcGetWatchdogInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802209u, /*paramSize=*/ sizeof(NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS), @@ -5502,13 +5877,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetWatchdogInfo" #endif }, - { /* [351] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [376] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcDisableWatchdog_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080220au, /*paramSize=*/ 0, @@ -5517,13 +5892,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcDisableWatchdog" #endif }, - { /* [352] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [377] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcEnableWatchdog_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080220bu, /*paramSize=*/ 0, @@ -5532,13 +5907,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcEnableWatchdog" #endif }, - { /* [353] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [378] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcReleaseWatchdogRequests_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080220cu, /*paramSize=*/ 0, @@ -5547,7 +5922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReleaseWatchdogRequests" #endif }, - { /* [354] */ + { /* [379] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5562,7 +5937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcRecovery" #endif }, - { /* [355] */ + { /* [380] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5577,13 +5952,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcRecovery" #endif }, - { /* [356] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [381] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdRcSoftDisableWatchdog_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802210u, /*paramSize=*/ 0, @@ -5592,7 +5967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSoftDisableWatchdog" #endif }, - { /* [357] */ + { /* [382] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5607,7 +5982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcInfo" #endif }, - { /* [358] */ + { /* [383] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5622,7 +5997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcInfo" #endif }, - { /* [359] */ + { /* [384] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5637,7 +6012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorV2" #endif }, - { /* [360] */ + { /* [385] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5652,7 +6027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioProgramDirection" #endif }, - { /* [361] */ + { /* [386] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5667,7 +6042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioProgramOutput" #endif }, - { /* [362] */ + { /* [387] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5682,7 +6057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioReadInput" #endif }, - { /* [363] */ + { /* [388] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5697,7 +6072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioActivateHwFunction" #endif }, - { /* [364] */ + { /* [389] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5712,7 +6087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDumpSize" #endif }, - { /* [365] */ + { /* [390] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5727,7 +6102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDump" #endif }, - { /* [366] */ + { /* [391] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5742,7 +6117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetNocatJournalRpt" #endif }, - { /* [367] */ + { /* [392] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5757,7 +6132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdSetNocatJournalData" #endif }, - { /* [368] */ + { /* [393] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5772,7 +6147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [369] */ + { /* [394] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5787,7 +6162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaGetInfo" #endif }, - { /* [370] */ + { /* [395] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5802,7 +6177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPmgrGetModuleInfo" #endif }, - { /* [371] */ + { /* [396] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5817,7 +6192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLpwrDifrCtrl" #endif }, - { /* [372] */ + { /* [397] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5832,7 +6207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLpwrDifrPrefetchResponse" #endif }, - { /* [373] */ + { /* [398] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5847,7 +6222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCaps" #endif }, - { /* [374] */ + { /* [399] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5862,7 +6237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCePceMask" #endif }, - { /* [375] */ + { /* [400] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5877,7 +6252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCapsV2" #endif }, - { /* [376] */ + { /* [401] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5892,7 +6267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdatePceLceMappings" #endif }, - { /* [377] */ + { /* [402] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5907,7 +6282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdateClassDB" #endif }, - { /* [378] */ + { /* [403] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100e40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5922,7 +6297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetPhysicalCaps" #endif }, - { /* [379] */ + { /* [404] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5937,7 +6312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetFaultMethodBufferSize" #endif }, - { /* [380] */ + { /* [405] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5952,13 +6327,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetHubPceMask" #endif }, - { /* [381] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + { /* [406] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetAllCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) - /*flags=*/ 0x2850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2810u) + /*flags=*/ 0x2810u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a0au, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS), @@ -5967,7 +6342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllCaps" #endif }, - { /* [382] */ + { /* [407] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5982,7 +6357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllPhysicalCaps" #endif }, - { /* [383] */ + { /* [408] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5997,7 +6372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkCaps" #endif }, - { /* [384] */ + { /* [409] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6012,7 +6387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkStatus" #endif }, - { /* [385] */ + { /* [410] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6027,7 +6402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkErrInfo" #endif }, - { /* [386] */ + { /* [411] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6042,7 +6417,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetNvlinkCounters" #endif }, - { /* [387] */ + { /* [412] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6057,7 +6432,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdClearNvlinkCounters" #endif }, - { /* [388] */ + { /* [413] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6072,7 +6447,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts" #endif }, - { /* [389] */ + { /* [414] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6087,7 +6462,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupEom" #endif }, - { /* [390] */ + { /* [415] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6102,7 +6477,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetPowerState" #endif }, - { /* [391] */ + { /* [416] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6117,7 +6492,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinGetLinkFomValues" #endif }, - { /* [392] */ + { /* [417] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6132,7 +6507,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkEccErrors" #endif }, - { /* [393] */ + { /* [418] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6147,7 +6522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkReadTpCounters" #endif }, - { /* [394] */ + { /* [419] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6162,7 +6537,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableNvlinkPeer" #endif }, - { /* [395] */ + { /* [420] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6177,7 +6552,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLpCounters" #endif }, - { /* [396] */ + { /* [421] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6192,7 +6567,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkCoreCallback" #endif }, - { /* [397] */ + { /* [422] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6207,7 +6582,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetAliEnabled" #endif }, - { /* [398] */ + { /* [423] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6222,7 +6597,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid" #endif }, - { /* [399] */ + { /* [424] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6237,7 +6612,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateHshubMux" #endif }, - { /* [400] */ + { /* [425] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6252,7 +6627,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreSetupNvlinkPeer" #endif }, - { /* [401] */ + { /* [426] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6267,7 +6642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostSetupNvlinkPeer" #endif }, - { /* [402] */ + { /* [427] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6282,7 +6657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkRemoveNvlinkMapping" #endif }, - { /* [403] */ + { /* [428] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6297,7 +6672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSaveRestoreHshubState" #endif }, - { /* [404] */ + { /* [429] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6312,7 +6687,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramBufferready" #endif }, - { /* [405] */ + { /* [430] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6327,7 +6702,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateCurrentConfig" #endif }, - { /* [406] */ + { /* [431] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6342,7 +6717,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetLoopbackMode" #endif }, - { /* [407] */ + { /* [432] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6357,7 +6732,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdatePeerLinkMask" #endif }, - { /* [408] */ + { /* [433] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6372,7 +6747,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateLinkConnection" #endif }, - { /* [409] */ + { /* [434] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6387,7 +6762,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinksPostTopology" #endif }, - { /* [410] */ + { /* [435] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6402,7 +6777,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreLinkTrainAli" #endif }, - { /* [411] */ + { /* [436] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6417,7 +6792,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetRefreshCounters" #endif }, - { /* [412] */ + { /* [437] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6432,13 +6807,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkClearRefreshCounters" #endif }, - { /* [413] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) + { /* [438] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) - /*flags=*/ 0x201u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) + /*flags=*/ 0x100201u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080302au, /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS), @@ -6447,7 +6822,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet" #endif }, - { /* [414] */ + { /* [439] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6462,7 +6837,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkLinkTrainAli" #endif }, - { /* [415] */ + { /* [440] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6477,7 +6852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo" #endif }, - { /* [416] */ + { /* [441] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6492,7 +6867,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo" #endif }, - { /* [417] */ + { /* [442] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6507,7 +6882,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramLinkSpeed" #endif }, - { /* [418] */ + { /* [443] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6522,7 +6897,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkAreLinksTrained" #endif }, - { /* [419] */ + { /* [444] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6537,7 +6912,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkResetLinks" #endif }, - { /* [420] */ + { /* [445] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6552,7 +6927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDisableDlInterrupts" #endif }, - { /* [421] */ + { /* [446] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6567,7 +6942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkAndClockInfo" #endif }, - { /* [422] */ + { /* [447] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6582,7 +6957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupNvlinkSysmem" #endif }, - { /* [423] */ + { /* [448] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6597,7 +6972,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessForcedConfigs" #endif }, - { /* [424] */ + { /* [449] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6612,7 +6987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLaneShutdownProps" #endif }, - { /* [425] */ + { /* [450] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6627,7 +7002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableSysmemNvlinkAts" #endif }, - { /* [426] */ + { /* [451] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6642,7 +7017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkHshubGetSysmemNvlinkMask" #endif }, - { /* [427] */ + { /* [452] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6657,7 +7032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr" #endif }, - { /* [428] */ + { /* [453] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6672,7 +7047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo" #endif }, - { /* [429] */ + { /* [454] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6687,7 +7062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinks" #endif }, - { /* [430] */ + { /* [455] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6702,7 +7077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessInitDisabledLinks" #endif }, - { /* [431] */ + { /* [456] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6717,7 +7092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEomControl" #endif }, - { /* [432] */ + { /* [457] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6732,7 +7107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetL1Threshold" #endif }, - { /* [433] */ + { /* [458] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6747,7 +7122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetL1Threshold" #endif }, - { /* [434] */ + { /* [459] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1240u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6762,7 +7137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkInbandSendData" #endif }, - { /* [435] */ + { /* [460] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6777,7 +7152,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDirectConnectCheck" #endif }, - { /* [436] */ + { /* [461] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6792,7 +7167,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostFaultUp" #endif }, - { /* [437] */ + { /* [462] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdIsNvlinkReducedConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803044u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdIsNvlinkReducedConfig" +#endif + }, + { /* [463] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6807,7 +7197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [438] */ + { /* [464] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6822,7 +7212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [439] */ + { /* [465] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6837,7 +7227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [440] */ + { /* [466] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6852,7 +7242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [441] */ + { /* [467] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6867,13 +7257,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [442] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + { /* [468] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnGetCtxBufferInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) - /*flags=*/ 0x200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803124u, /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS), @@ -6882,13 +7272,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [443] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [469] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlcnGetCtxBufferSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803125u, /*paramSize=*/ sizeof(NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS), @@ -6897,7 +7287,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [444] */ + { /* [470] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6912,7 +7302,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [445] */ + { /* [471] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6927,7 +7317,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [446] */ + { /* [472] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6942,7 +7332,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [447] */ + { /* [473] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6957,7 +7347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [448] */ + { /* [474] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6972,7 +7362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [449] */ + { /* [475] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6987,7 +7377,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [450] */ + { /* [476] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGspGetRmHeapStats_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803602u, + /*paramSize=*/ sizeof(NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGspGetRmHeapStats" +#endif + }, + { /* [477] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7002,7 +7407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [451] */ + { /* [478] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7017,7 +7422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [452] */ + { /* [479] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7032,7 +7437,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [453] */ + { /* [480] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7047,7 +7452,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [454] */ + { /* [481] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7062,7 +7467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [455] */ + { /* [482] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7077,7 +7482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [456] */ + { /* [483] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7092,7 +7497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" #endif }, - { /* [457] */ + { /* [484] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7107,7 +7512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" #endif }, - { /* [458] */ + { /* [485] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7122,7 +7527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" #endif }, - { /* [459] */ + { /* [486] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7137,7 +7542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" #endif }, - { /* [460] */ + { /* [487] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7152,7 +7557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" #endif }, - { /* [461] */ + { /* [488] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7167,7 +7572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" #endif }, - { /* [462] */ + { /* [489] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7182,7 +7587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" #endif }, - { /* [463] */ + { /* [490] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7197,7 +7602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" #endif }, - { /* [464] */ + { /* [491] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7212,7 +7617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" #endif }, - { /* [465] */ + { /* [492] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7227,7 +7632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" #endif }, - { /* [466] */ + { /* [493] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7242,7 +7647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" #endif }, - { /* [467] */ + { /* [494] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7257,7 +7662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [468] */ + { /* [495] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7270,6 +7675,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples" +#endif + }, + { /* [496] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080a7d7u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGc6EntryPrerequisite" #endif }, @@ -7277,7 +7697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 469, + /*numEntries=*/ 497, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -7437,7 +7857,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusGetBFD__ = &subdeviceCtrlCmdBusGetBFD_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdBusGetAspmDisableFlags__ = &subdeviceCtrlCmdBusGetAspmDisableFlags_IMPL; #endif @@ -7473,7 +7893,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusSetPcieLtrLatency__ = &subdeviceCtrlCmdBusSetPcieLtrLatency_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__subdeviceCtrlCmdBusGetNvlinkPeerIdMask__ = &subdeviceCtrlCmdBusGetNvlinkPeerIdMask_IMPL; #endif @@ -7637,7 +8057,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkClearRefreshCounters__ = &subdeviceCtrlCmdNvlinkClearRefreshCounters_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) pThis->__subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet__ = &subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet_IMPL; #endif @@ -7733,6 +8153,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkGetL1Threshold__ = &subdeviceCtrlCmdNvlinkGetL1Threshold_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__subdeviceCtrlCmdIsNvlinkReducedConfig__ = &subdeviceCtrlCmdIsNvlinkReducedConfig_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdI2cReadBuffer__ = &subdeviceCtrlCmdI2cReadBuffer_IMPL; #endif @@ -7762,28 +8186,16 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #endif // Hal function -- subdeviceCtrlCmdPerfRatedTdpSetControl - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__subdeviceCtrlCmdPerfRatedTdpSetControl__ = &subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL; - } + pThis->__subdeviceCtrlCmdPerfRatedTdpSetControl__ = &subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL; // Hal function -- subdeviceCtrlCmdPerfReservePerfmonHw - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL; - } + pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL; // Hal function -- subdeviceCtrlCmdPerfSetAuxPowerState - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__subdeviceCtrlCmdPerfSetAuxPowerState__ = &subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL; - } + pThis->__subdeviceCtrlCmdPerfSetAuxPowerState__ = &subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL; // Hal function -- subdeviceCtrlCmdPerfSetPowerstate - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__subdeviceCtrlCmdPerfSetPowerstate__ = &subdeviceCtrlCmdPerfSetPowerstate_KERNEL; - } + pThis->__subdeviceCtrlCmdPerfSetPowerstate__ = &subdeviceCtrlCmdPerfSetPowerstate_KERNEL; #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKPerfBoost__ = &subdeviceCtrlCmdKPerfBoost_IMPL; @@ -7813,6 +8225,13 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__ = &subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout__ = &subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL; +#endif + + // Hal function -- subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp + pThis->__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__ = &subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_46f6a7; + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdFbGetInfo__ = &subdeviceCtrlCmdFbGetInfo_IMPL; #endif @@ -7969,7 +8388,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFifoBindEngines__ = &subdeviceCtrlCmdFifoBindEngines_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGetPhysicalChannelCount__ = &subdeviceCtrlCmdGetPhysicalChannelCount_IMPL; #endif @@ -7977,7 +8396,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFifoGetInfo__ = &subdeviceCtrlCmdFifoGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__subdeviceCtrlCmdFifoDisableChannels__ = &subdeviceCtrlCmdFifoDisableChannels_IMPL; #endif @@ -8017,7 +8436,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers__ = &subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2e50u) pThis->__subdeviceCtrlCmdInternalFifoGetNumChannels__ = &subdeviceCtrlCmdInternalFifoGetNumChannels_IMPL; #endif @@ -8197,7 +8616,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrInternalStaticGetInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetCaps__ = &subdeviceCtrlCmdKGrInternalStaticGetCaps_IMPL; #endif @@ -8301,6 +8720,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuSetFabricAddr__ = &subdeviceCtrlCmdGpuSetFabricAddr_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdGpuSetEgmGpaFabricAddr__ = &subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuSetPower__ = &subdeviceCtrlCmdGpuSetPower_IMPL; #endif @@ -8349,11 +8772,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetPesInfo__ = &subdeviceCtrlCmdGpuGetPesInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuExecRegOps__ = &subdeviceCtrlCmdGpuExecRegOps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuMigratableOps__ = &subdeviceCtrlCmdGpuMigratableOps_IMPL; #endif @@ -8372,6 +8795,15 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuQueryInforomEccSupport__ = &subdeviceCtrlCmdGpuQueryInforomEccSupport_IMPL; #endif +} + +static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) pThis->__subdeviceCtrlCmdGpuQueryEccStatus__ = &subdeviceCtrlCmdGpuQueryEccStatus_IMPL; @@ -8388,17 +8820,8 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) pThis->__subdeviceCtrlCmdGpuGetOEMInfo__ = &subdeviceCtrlCmdGpuGetOEMInfo_IMPL; #endif -} - -static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) pThis->__subdeviceCtrlCmdGpuHandleGpuSR__ = &subdeviceCtrlCmdGpuHandleGpuSR_IMPL; #endif @@ -8410,11 +8833,11 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuQueryComputeModeRules__ = &subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuAcquireComputeModeReservation__ = &subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuReleaseComputeModeReservation__ = &subdeviceCtrlCmdGpuReleaseComputeModeReservation_IMPL; #endif @@ -8530,7 +8953,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGetP2pCaps__ = &subdeviceCtrlCmdGetP2pCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGetGpuFabricProbeInfo__ = &subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL; #endif @@ -8606,23 +9029,23 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdRcSetCleanErrorHistory__ = &subdeviceCtrlCmdRcSetCleanErrorHistory_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdRcGetWatchdogInfo__ = &subdeviceCtrlCmdRcGetWatchdogInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdRcDisableWatchdog__ = &subdeviceCtrlCmdRcDisableWatchdog_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdRcSoftDisableWatchdog__ = &subdeviceCtrlCmdRcSoftDisableWatchdog_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdRcEnableWatchdog__ = &subdeviceCtrlCmdRcEnableWatchdog_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdRcReleaseWatchdogRequests__ = &subdeviceCtrlCmdRcReleaseWatchdogRequests_IMPL; #endif @@ -8690,7 +9113,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCeGetCapsV2__ = &subdeviceCtrlCmdCeGetCapsV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2810u) pThis->__subdeviceCtrlCmdCeGetAllCaps__ = &subdeviceCtrlCmdCeGetAllCaps_IMPL; #endif @@ -8714,11 +9137,11 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFlcnUstreamerControlSet__ = &subdeviceCtrlCmdFlcnUstreamerControlSet_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) pThis->__subdeviceCtrlCmdFlcnGetCtxBufferInfo__ = &subdeviceCtrlCmdFlcnGetCtxBufferInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdFlcnGetCtxBufferSize__ = &subdeviceCtrlCmdFlcnGetCtxBufferSize_IMPL; #endif @@ -8758,6 +9181,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGspGetFeatures__ = &subdeviceCtrlCmdGspGetFeatures_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGspGetRmHeapStats__ = &subdeviceCtrlCmdGspGetRmHeapStats_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdGpuGetActivePartitionIds__ = &subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL; #endif @@ -8886,24 +9313,36 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalGpioActivateHwFunction__ = &subdeviceCtrlCmdInternalGpioActivateHwFunction_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) - pThis->__subdeviceCtrlCmdMsencGetCaps__ = &subdeviceCtrlCmdMsencGetCaps_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated__ = &subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL; + pThis->__subdeviceCtrlCmdInternalDisplayPreModeSet__ = &subdeviceCtrlCmdInternalDisplayPreModeSet_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL; + pThis->__subdeviceCtrlCmdInternalDisplayPostModeSet__ = &subdeviceCtrlCmdInternalDisplayPostModeSet_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdDisplayUnixConsole__ = &subdeviceCtrlCmdDisplayUnixConsole_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdDisplayPostVgaRestore__ = &subdeviceCtrlCmdDisplayPostVgaRestore_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) + pThis->__subdeviceCtrlCmdMsencGetCaps__ = &subdeviceCtrlCmdMsencGetCaps_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_IMPL; + pThis->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize__ = &subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_IMPL; + pThis->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) @@ -9055,10 +9494,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdBifGetStaticInfo__ = &subdeviceCtrlCmdBifGetStaticInfo_IMPL; + pThis->__subdeviceCtrlCmdInternalGc6EntryPrerequisite__ = &subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdBifGetStaticInfo__ = &subdeviceCtrlCmdBifGetStaticInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) pThis->__subdeviceCtrlCmdBifGetAspmL1Flags__ = &subdeviceCtrlCmdBifGetAspmL1Flags_IMPL; #endif @@ -9090,6 +9533,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdHshubNextHshubId__ = &subdeviceCtrlCmdHshubNextHshubId_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdHshubEgmConfig__ = &subdeviceCtrlCmdHshubEgmConfig_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr__ = &subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_IMPL; #endif @@ -9098,11 +9545,11 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__ = &subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) pThis->__subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl__ = &subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) pThis->__subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl__ = &subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_IMPL; #endif @@ -9122,6 +9569,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__ = &subdeviceCtrlCmdInternalGetCoherentFbApertureSize_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGetLocalAtsConfig__ = &subdeviceCtrlCmdInternalGetLocalAtsConfig_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalSetPeerAtsConfig__ = &subdeviceCtrlCmdInternalSetPeerAtsConfig_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalInitGpuIntr__ = &subdeviceCtrlCmdInternalInitGpuIntr_IMPL; #endif @@ -9162,6 +9617,62 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__ = &subdeviceCtrlCmdInternalPostInitBrightcStateLoad_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalSetStaticEdidData__ = &subdeviceCtrlCmdInternalSetStaticEdidData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate__ = &subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync__ = &subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit__ = &subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2__ = &subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__ = &subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL; #endif @@ -9170,6 +9681,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalDetectHsVideoBridge__ = &subdeviceCtrlCmdInternalDetectHsVideoBridge_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalConfComputeGetStaticInfo__ = &subdeviceCtrlCmdInternalConfComputeGetStaticInfo_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__ = &subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL; #endif @@ -9230,6 +9745,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCcuSetStreamState__ = &subdeviceCtrlCmdCcuSetStreamState_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdSpdmPartition__ = &subdeviceCtrlCmdSpdmPartition_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resPreDestruct__ = &__nvoc_thunk_Subdevice_resPreDestruct; pThis->__nvoc_base_GpuResource.__gpuresInternalControlForward__ = &__nvoc_thunk_Subdevice_gpuresInternalControlForward; @@ -9285,6 +9804,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceGetNotificationListPtr__ = &__nvoc_thunk_Notifier_subdeviceGetNotificationListPtr; pThis->__subdeviceGetNotificationShare__ = &__nvoc_thunk_Notifier_subdeviceGetNotificationShare; +} + +static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); pThis->__subdeviceMap__ = &__nvoc_thunk_GpuResource_subdeviceMap; @@ -9294,6 +9822,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_Subdevice_1(pThis, pRmhalspecowner); __nvoc_init_funcTable_Subdevice_2(pThis, pRmhalspecowner); + __nvoc_init_funcTable_Subdevice_3(pThis, pRmhalspecowner); } void __nvoc_init_GpuResource(GpuResource*); diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 0e89fa8703..7b747a4e31 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -218,6 +218,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkSetL1Threshold__)(struct Subdevice *, NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkDirectConnectCheck__)(struct Subdevice *, NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetL1Threshold__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdIsNvlinkReducedConfig__)(struct Subdevice *, NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cWriteBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadReg__)(struct Subdevice *, NV2080_CTRL_I2C_RW_REG_PARAMS *); @@ -236,6 +237,8 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdFbGetMemAlignment__)(struct Subdevice *, NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetHeapReservationSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout__)(struct Subdevice *, NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetInfo__)(struct Subdevice *, NV2080_CTRL_FB_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetInfoV2__)(struct Subdevice *, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetCarveoutAddressInfo__)(struct Subdevice *, NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO *); @@ -358,6 +361,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGpuGetNvfbcSwSessionStats__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetFabricAddr__)(struct Subdevice *, NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuSetEgmGpaFabricAddr__)(struct Subdevice *, NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetPower__)(struct Subdevice *, NV2080_CTRL_GPU_SET_POWER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetSdm__)(struct Subdevice *, NV2080_CTRL_GPU_GET_SDM_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetSdm__)(struct Subdevice *, NV2080_CTRL_GPU_SET_SDM_PARAMS *); @@ -470,6 +474,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdFlaGetRange__)(struct Subdevice *, NV2080_CTRL_FLA_GET_RANGE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlaGetFabricMemStats__)(struct Subdevice *, NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGspGetFeatures__)(struct Subdevice *, NV2080_CTRL_GSP_GET_FEATURES_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGspGetRmHeapStats__)(struct Subdevice *, NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetActivePartitionIds__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetPartitionCapacity__)(struct Subdevice *, NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuDescribePartitions__)(struct Subdevice *, NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS *); @@ -502,11 +507,14 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalGpioProgramOutput__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGpioReadInput__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGpioActivateHwFunction__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalDisplayPreModeSet__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalDisplayPostModeSet__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdDisplayUnixConsole__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdDisplayPostVgaRestore__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdMsencGetCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__)(struct Subdevice *); - NV_STATUS (*__subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer__)(struct Subdevice *); - NV_STATUS (*__subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetChipInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetUserRegisterAccessMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetDeviceInfoTable__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *); @@ -544,6 +552,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPerfGetAuxPowerState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGc6EntryPrerequisite__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetAspmL1Flags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifSetPcieRo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS *); @@ -553,6 +562,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdHshubGetHshubIdForLinks__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubGetNumUnits__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubNextHshubId__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdHshubEgmConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS *); @@ -561,6 +571,8 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalRemoveP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetPcieP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGetLocalAtsConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalSetPeerAtsConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalInitGpuIntr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGsyncOptimizeTiming__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGsyncGetDisplayIds__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS *); @@ -571,8 +583,23 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalFbsrInit__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalFbsrSendRegionInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__)(struct Subdevice *, NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalSetStaticEdidData__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate__)(struct Subdevice *, NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalDetectHsVideoBridge__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *); @@ -588,6 +615,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdCcuMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuUnmap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuSetStreamState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdSpdmPartition__)(struct Subdevice *, NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *); NvBool (*__subdeviceShareCallback__)(struct Subdevice *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__subdeviceCheckMemInterUnmap__)(struct Subdevice *, NvBool); NV_STATUS (*__subdeviceGetOrAllocNotifShare__)(struct Subdevice *, NvHandle, NvHandle, struct NotifShare **); @@ -620,7 +648,7 @@ struct Subdevice { struct Device *pDevice; NvBool bMaxGrTickFreqRequested; NvU64 P2PfbMappedBytes; - NvU32 notifyActions[179]; + NvU32 notifyActions[180]; NvHandle hNotifierMemory; struct Memory *pNotifierMemory; NvHandle hSemMemory; @@ -775,6 +803,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkSetL1Threshold(pSubdevice, pParams) subdeviceCtrlCmdNvlinkSetL1Threshold_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkDirectConnectCheck(pSubdevice, pParams) subdeviceCtrlCmdNvlinkDirectConnectCheck_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetL1Threshold(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetL1Threshold_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdIsNvlinkReducedConfig(pSubdevice, pParams) subdeviceCtrlCmdIsNvlinkReducedConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdI2cReadBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cWriteBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cWriteBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cReadReg(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadReg_DISPATCH(pSubdevice, pI2cParams) @@ -797,6 +826,9 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdFbGetMemAlignment(pSubdevice, pParams) subdeviceCtrlCmdFbGetMemAlignment_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbGetHeapReservationSize(pSubdevice, pParams) subdeviceCtrlCmdFbGetHeapReservationSize_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout(pSubdevice, pParams) subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_HAL(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbGetInfo(pSubdevice, pFbInfoParams) subdeviceCtrlCmdFbGetInfo_DISPATCH(pSubdevice, pFbInfoParams) #define subdeviceCtrlCmdFbGetInfoV2(pSubdevice, pFbInfoParams) subdeviceCtrlCmdFbGetInfoV2_DISPATCH(pSubdevice, pFbInfoParams) #define subdeviceCtrlCmdFbGetCarveoutAddressInfo(pSubdevice, pParams) subdeviceCtrlCmdFbGetCarveoutAddressInfo_DISPATCH(pSubdevice, pParams) @@ -919,6 +951,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetNvfbcSwSessionStats(pSubdevice, params) subdeviceCtrlCmdGpuGetNvfbcSwSessionStats_DISPATCH(pSubdevice, params) #define subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo(pSubdevice, params) subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo_DISPATCH(pSubdevice, params) #define subdeviceCtrlCmdGpuSetFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdGpuSetFabricAddr_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuSetEgmGpaFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuSetPower(pSubdevice, pSetPowerParams) subdeviceCtrlCmdGpuSetPower_DISPATCH(pSubdevice, pSetPowerParams) #define subdeviceCtrlCmdGpuGetSdm(pSubdevice, pSdmParams) subdeviceCtrlCmdGpuGetSdm_DISPATCH(pSubdevice, pSdmParams) #define subdeviceCtrlCmdGpuSetSdm(pSubdevice, pSdmParams) subdeviceCtrlCmdGpuSetSdm_DISPATCH(pSubdevice, pSdmParams) @@ -1031,6 +1064,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdFlaGetRange(pSubdevice, pParams) subdeviceCtrlCmdFlaGetRange_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlaGetFabricMemStats(pSubdevice, pParams) subdeviceCtrlCmdFlaGetFabricMemStats_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGspGetFeatures(pSubdevice, pGspFeaturesParams) subdeviceCtrlCmdGspGetFeatures_DISPATCH(pSubdevice, pGspFeaturesParams) +#define subdeviceCtrlCmdGspGetRmHeapStats(pSubdevice, pGspRmHeapStatsParams) subdeviceCtrlCmdGspGetRmHeapStats_DISPATCH(pSubdevice, pGspRmHeapStatsParams) #define subdeviceCtrlCmdGpuGetActivePartitionIds(pSubdevice, pParams) subdeviceCtrlCmdGpuGetActivePartitionIds_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetPartitionCapacity(pSubdevice, pParams) subdeviceCtrlCmdGpuGetPartitionCapacity_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuDescribePartitions(pSubdevice, pParams) subdeviceCtrlCmdGpuDescribePartitions_DISPATCH(pSubdevice, pParams) @@ -1063,11 +1097,14 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalGpioProgramOutput(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioProgramOutput_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGpioReadInput(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioReadInput_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGpioActivateHwFunction(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioActivateHwFunction_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated(pSubdevice) subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalDisplayPreModeSet(pSubdevice) subdeviceCtrlCmdInternalDisplayPreModeSet_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalDisplayPostModeSet(pSubdevice) subdeviceCtrlCmdInternalDisplayPostModeSet_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdDisplayUnixConsole(pSubdevice, pParams) subdeviceCtrlCmdDisplayUnixConsole_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdDisplayPostVgaRestore(pSubdevice, pParams) subdeviceCtrlCmdDisplayPostVgaRestore_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdMsencGetCaps(pSubdevice, pParams) subdeviceCtrlCmdMsencGetCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer(pSubdevice) subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(pSubdevice) -#define subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer(pSubdevice) subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_DISPATCH(pSubdevice) -#define subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetChipInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalGetChipInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetUserRegisterAccessMap(pSubdevice, pParams) subdeviceCtrlCmdInternalGetUserRegisterAccessMap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetDeviceInfoTable(pSubdevice, pParams) subdeviceCtrlCmdInternalGetDeviceInfoTable_DISPATCH(pSubdevice, pParams) @@ -1105,6 +1142,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPerfGetAuxPowerState(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfGetAuxPowerState_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGc6EntryPrerequisite(pSubdevice, pG6EntryPrerequisite) subdeviceCtrlCmdInternalGc6EntryPrerequisite_DISPATCH(pSubdevice, pG6EntryPrerequisite) #define subdeviceCtrlCmdBifGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetAspmL1Flags(pSubdevice, pParams) subdeviceCtrlCmdBifGetAspmL1Flags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifSetPcieRo(pSubdevice, pParams) subdeviceCtrlCmdBifSetPcieRo_DISPATCH(pSubdevice, pParams) @@ -1114,6 +1152,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdHshubGetHshubIdForLinks(pSubdevice, pParams) subdeviceCtrlCmdHshubGetHshubIdForLinks_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubGetNumUnits(pSubdevice, pParams) subdeviceCtrlCmdHshubGetNumUnits_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubNextHshubId(pSubdevice, pParams) subdeviceCtrlCmdHshubNextHshubId_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdHshubEgmConfig(pSubdevice, pParams) subdeviceCtrlCmdHshubEgmConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr(pSubdevice) subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_DISPATCH(pSubdevice, pParams) @@ -1122,6 +1161,8 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalRemoveP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalRemoveP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetPcieP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalGetPcieP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetCoherentFbApertureSize(pSubdevice, pParams) subdeviceCtrlCmdInternalGetCoherentFbApertureSize_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGetLocalAtsConfig(pSubdevice, pParams) subdeviceCtrlCmdInternalGetLocalAtsConfig_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalSetPeerAtsConfig(pSubdevice, pParams) subdeviceCtrlCmdInternalSetPeerAtsConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalInitGpuIntr(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalInitGpuIntr_DISPATCH(pSubdevice, pAttachParams) #define subdeviceCtrlCmdInternalGsyncOptimizeTiming(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncOptimizeTiming_DISPATCH(pSubdevice, pAttachParams) #define subdeviceCtrlCmdInternalGsyncGetDisplayIds(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncGetDisplayIds_DISPATCH(pSubdevice, pAttachParams) @@ -1132,8 +1173,23 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalFbsrInit(pSubdevice, pParams) subdeviceCtrlCmdInternalFbsrInit_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalFbsrSendRegionInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalFbsrSendRegionInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPostInitBrightcStateLoad(pSubdevice, pParams) subdeviceCtrlCmdInternalPostInitBrightcStateLoad_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalSetStaticEdidData(pSubdevice, pParams) subdeviceCtrlCmdInternalSetStaticEdidData_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate(pSubdevice, pParams) subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync(pSubdevice, pParams) subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit(pSubdevice, pParams) subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2(pSubdevice, pParams) subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit(pSubdevice) subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalDetectHsVideoBridge(pSubdevice) subdeviceCtrlCmdInternalDetectHsVideoBridge_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalConfComputeGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_DISPATCH(pSubdevice, pParams) @@ -1149,6 +1205,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdCcuMap(pSubdevice, pParams) subdeviceCtrlCmdCcuMap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuUnmap(pSubdevice, pParams) subdeviceCtrlCmdCcuUnmap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuSetStreamState(pSubdevice, pParams) subdeviceCtrlCmdCcuSetStreamState_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdSpdmPartition(pSubdevice, pSpdmPartitionParams) subdeviceCtrlCmdSpdmPartition_DISPATCH(pSubdevice, pSpdmPartitionParams) #define subdeviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) subdeviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define subdeviceCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) subdeviceCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define subdeviceGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) subdeviceGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) @@ -1788,6 +1845,12 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkGetL1Threshold_DISPATCH(struct Sub return pSubdevice->__subdeviceCtrlCmdNvlinkGetL1Threshold__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdIsNvlinkReducedConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdIsNvlinkReducedConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdIsNvlinkReducedConfig__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdI2cReadBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams); static inline NV_STATUS subdeviceCtrlCmdI2cReadBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams) { @@ -1896,6 +1959,20 @@ static inline NV_STATUS subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_DI return pSubdevice->__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout__(pSubdevice, pParams); +} + +static inline NV_STATUS subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_46f6a7(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS *pParams) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdFbGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams); static inline NV_STATUS subdeviceCtrlCmdFbGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams) { @@ -2630,6 +2707,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuSetFabricAddr_DISPATCH(struct Subdevi return pSubdevice->__subdeviceCtrlCmdGpuSetFabricAddr__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuSetEgmGpaFabricAddr__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuSetPower_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_POWER_PARAMS *pSetPowerParams); static inline NV_STATUS subdeviceCtrlCmdGpuSetPower_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_POWER_PARAMS *pSetPowerParams) { @@ -3302,6 +3385,12 @@ static inline NV_STATUS subdeviceCtrlCmdGspGetFeatures_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdGspGetFeatures__(pSubdevice, pGspFeaturesParams); } +NV_STATUS subdeviceCtrlCmdGspGetRmHeapStats_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS *pGspRmHeapStatsParams); + +static inline NV_STATUS subdeviceCtrlCmdGspGetRmHeapStats_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS *pGspRmHeapStatsParams) { + return pSubdevice->__subdeviceCtrlCmdGspGetRmHeapStats__(pSubdevice, pGspRmHeapStatsParams); +} + NV_STATUS subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGpuGetActivePartitionIds_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS *pParams) { @@ -3494,34 +3583,52 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGpioActivateHwFunction_DISPATCH( return pSubdevice->__subdeviceCtrlCmdInternalGpioActivateHwFunction__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdMsencGetCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_IMPL(struct Subdevice *pSubdevice); -static inline NV_STATUS subdeviceCtrlCmdMsencGetCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdMsencGetCaps__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated__(pSubdevice); } -NV_STATUS subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdInternalDisplayPreModeSet_IMPL(struct Subdevice *pSubdevice); -static inline NV_STATUS subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdInternalDisplayPreModeSet_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalDisplayPreModeSet__(pSubdevice); +} + +NV_STATUS subdeviceCtrlCmdInternalDisplayPostModeSet_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdInternalDisplayPostModeSet_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalDisplayPostModeSet__(pSubdevice); +} + +NV_STATUS subdeviceCtrlCmdDisplayUnixConsole_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdDisplayUnixConsole_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplayUnixConsole__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice); +NV_STATUS subdeviceCtrlCmdDisplayPostVgaRestore_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdDisplayPostVgaRestore_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplayPostVgaRestore__(pSubdevice, pParams); +} -static inline NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice) { - return pSubdevice->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__(pSubdevice); +NV_STATUS subdeviceCtrlCmdMsencGetCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdMsencGetCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdMsencGetCaps__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice); +NV_STATUS subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice) { - return pSubdevice->__subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer__(pSubdevice); +static inline NV_STATUS subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__(pSubdevice, pParams); } NV_STATUS subdeviceCtrlCmdInternalGetChipInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *pParams); @@ -3746,6 +3853,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalPerfGetAuxPowerState_DISPATCH(st return pSubdevice->__subdeviceCtrlCmdInternalPerfGetAuxPowerState__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *pG6EntryPrerequisite); + +static inline NV_STATUS subdeviceCtrlCmdInternalGc6EntryPrerequisite_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *pG6EntryPrerequisite) { + return pSubdevice->__subdeviceCtrlCmdInternalGc6EntryPrerequisite__(pSubdevice, pG6EntryPrerequisite); +} + NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams) { @@ -3800,6 +3913,12 @@ static inline NV_STATUS subdeviceCtrlCmdHshubNextHshubId_DISPATCH(struct Subdevi return pSubdevice->__subdeviceCtrlCmdHshubNextHshubId__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdHshubEgmConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdHshubEgmConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdHshubEgmConfig__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_DISPATCH(struct Subdevice *pSubdevice) { @@ -3848,6 +3967,18 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGetCoherentFbApertureSize_DISPAT return pSubdevice->__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalGetLocalAtsConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGetLocalAtsConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGetLocalAtsConfig__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalSetPeerAtsConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalSetPeerAtsConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalSetPeerAtsConfig__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalInitGpuIntr_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *pAttachParams); static inline NV_STATUS subdeviceCtrlCmdInternalInitGpuIntr_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *pAttachParams) { @@ -3908,6 +4039,90 @@ static inline NV_STATUS subdeviceCtrlCmdInternalPostInitBrightcStateLoad_DISPATC return pSubdevice->__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalSetStaticEdidData_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalSetStaticEdidData_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalSetStaticEdidData__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPATCH(struct Subdevice *pSubdevice) { @@ -3920,6 +4135,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalDetectHsVideoBridge_DISPATCH(str return pSubdevice->__subdeviceCtrlCmdInternalDetectHsVideoBridge__(pSubdevice); } +NV_STATUS subdeviceCtrlCmdInternalConfComputeGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeGetStaticInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalConfComputeGetStaticInfo__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams) { @@ -4010,6 +4231,12 @@ static inline NV_STATUS subdeviceCtrlCmdCcuSetStreamState_DISPATCH(struct Subdev return pSubdevice->__subdeviceCtrlCmdCcuSetStreamState__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdSpdmPartition_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *pSpdmPartitionParams); + +static inline NV_STATUS subdeviceCtrlCmdSpdmPartition_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *pSpdmPartitionParams) { + return pSubdevice->__subdeviceCtrlCmdSpdmPartition__(pSubdevice, pSpdmPartitionParams); +} + static inline NvBool subdeviceShareCallback_DISPATCH(struct Subdevice *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__subdeviceShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -4211,33 +4438,6 @@ struct Subdevice *CliGetSubDeviceInfoFromGpu(NvHandle, struct OBJGPU*); * RES_GET_HANDLE */ NV_STATUS CliGetSubDeviceHandleFromGpu(NvHandle, struct OBJGPU*, NvHandle *); - -/** - * WARNING: This function is deprecated and use is *strongly* discouraged - * (especially for new code!) - * - * From the function name (CliSetSubDeviceContext) it appears as a simple - * accessor but violates expectations by modifying the SLI BC threadstate (calls - * to GPU_RES_SET_THREAD_BC_STATE). This can be dangerous if not carefully - * managed by the caller. - * - * Instead of using this routine, please use subdeviceGetByHandle then call - * GPU_RES_GET_GPU, RES_GET_HANDLE, GPU_RES_SET_THREAD_BC_STATE as needed. - * - * Note that GPU_RES_GET_GPU supports returning a pGpu for both pDevice, - * pSubdevice, the base pResource type, and any resource that inherits from - * GpuResource. That is, instead of using CliSetGpuContext or - * CliSetSubDeviceContext, please use following pattern to look up the pGpu: - * - * OBJGPU *pGpu = GPU_RES_GET_GPU(pResource or pResourceRef->pResource) - * - * To set the threadstate, please use: - * - * GPU_RES_SET_THREAD_BC_STATE(pResource or pResourceRef->pResource); - */ -NV_STATUS CliSetSubDeviceContext(NvHandle hClient, NvHandle hSubdevice, NvHandle *phDevice, - struct OBJGPU **ppGpu); - #endif #ifdef __cplusplus diff --git a/src/nvidia/generated/g_swintr_nvoc.c b/src/nvidia/generated/g_swintr_nvoc.c index 611bc93c3d..b23c9cd131 100644 --- a/src/nvidia/generated/g_swintr_nvoc.c +++ b/src/nvidia/generated/g_swintr_nvoc.c @@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_SwIntr = /*pExportInfo=*/ &__nvoc_export_info_SwIntr }; -static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[166]) { +static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[167]) { swintrRegisterIntrService(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pRecords); } diff --git a/src/nvidia/generated/g_swintr_nvoc.h b/src/nvidia/generated/g_swintr_nvoc.h index 421e15f387..d7e87f28e4 100644 --- a/src/nvidia/generated/g_swintr_nvoc.h +++ b/src/nvidia/generated/g_swintr_nvoc.h @@ -125,9 +125,9 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr**, Dynamic*, NvU32); #define swintrStatePostLoad(pGpu, pEngstate, arg0) swintrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define swintrConstructEngine(pGpu, pEngstate, arg0) swintrConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define swintrIsPresent(pGpu, pEngstate) swintrIsPresent_DISPATCH(pGpu, pEngstate) -void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[166]); +void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[167]); -static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[166]) { +static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[167]) { pSwIntr->__swintrRegisterIntrService__(pGpu, pSwIntr, pRecords); } diff --git a/src/nvidia/generated/g_system_mem_nvoc.c b/src/nvidia/generated/g_system_mem_nvoc.c index bc19451868..f27e958af0 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.c +++ b/src/nvidia/generated/g_system_mem_nvoc.c @@ -178,8 +178,8 @@ static NV_STATUS __nvoc_thunk_Memory_sysmemIsReady(struct SystemMemory *pMemory, return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_sysmemCheckCopyPermissions(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_sysmemCheckCopyPermissions(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_sysmemPreDestruct(struct SystemMemory *pResource) { diff --git a/src/nvidia/generated/g_system_mem_nvoc.h b/src/nvidia/generated/g_system_mem_nvoc.h index f8b90e4450..ddf1747372 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.h +++ b/src/nvidia/generated/g_system_mem_nvoc.h @@ -73,7 +73,7 @@ struct SystemMemory { NV_STATUS (*__sysmemControlSerialization_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__sysmemCanCopy__)(struct SystemMemory *); NV_STATUS (*__sysmemIsReady__)(struct SystemMemory *, NvBool); - NV_STATUS (*__sysmemCheckCopyPermissions__)(struct SystemMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__sysmemCheckCopyPermissions__)(struct SystemMemory *, struct OBJGPU *, struct Device *); void (*__sysmemPreDestruct__)(struct SystemMemory *); NV_STATUS (*__sysmemIsDuplicate__)(struct SystemMemory *, NvHandle, NvBool *); void (*__sysmemControlSerialization_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -130,7 +130,7 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory**, Dynamic*, NvU32, CALL_CO #define sysmemControlSerialization_Prologue(pResource, pCallContext, pParams) sysmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define sysmemCanCopy(pStandardMemory) sysmemCanCopy_DISPATCH(pStandardMemory) #define sysmemIsReady(pMemory, bCopyConstructorContext) sysmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define sysmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) sysmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define sysmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) sysmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define sysmemPreDestruct(pResource) sysmemPreDestruct_DISPATCH(pResource) #define sysmemIsDuplicate(pMemory, hMemory, pDuplicate) sysmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define sysmemControlSerialization_Epilogue(pResource, pCallContext, pParams) sysmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -238,8 +238,8 @@ static inline NV_STATUS sysmemIsReady_DISPATCH(struct SystemMemory *pMemory, NvB return pMemory->__sysmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS sysmemCheckCopyPermissions_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__sysmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS sysmemCheckCopyPermissions_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__sysmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void sysmemPreDestruct_DISPATCH(struct SystemMemory *pResource) { diff --git a/src/nvidia/generated/g_system_nvoc.h b/src/nvidia/generated/g_system_nvoc.h index b59afc8784..5cd2e74da3 100644 --- a/src/nvidia/generated/g_system_nvoc.h +++ b/src/nvidia/generated/g_system_nvoc.h @@ -332,7 +332,7 @@ typedef struct NvU32 l1DataCacheSize; // L1 data (or unified) cache size (KB) NvU32 l2DataCacheSize; // L2 data (or unified) cache size (KB) NvU32 dataCacheLineSize; // Bytes per line in the L1 data cache - NvU32 hostPageSize; // Native host os page size (4k/64k/etc) + NvU64 hostPageSize; // Native host os page size (4k/64k/etc) NvU32 numPhysicalCpus; // Number of physical cpus NvU32 numLogicalCpus; // Total number of logical cpus NvU32 maxLogicalCpus; // Max Number of Cores on the System diff --git a/src/nvidia/generated/g_third_party_p2p_nvoc.h b/src/nvidia/generated/g_third_party_p2p_nvoc.h index 74f1ca3ce7..b4237f7f17 100644 --- a/src/nvidia/generated/g_third_party_p2p_nvoc.h +++ b/src/nvidia/generated/g_third_party_p2p_nvoc.h @@ -561,15 +561,6 @@ typedef struct ThirdPartyP2P *PCLI_THIRD_PARTY_P2P_INFO; // RS-TODO: Remove // Functions prototypes // **************************************************************************** -// Create and add/register a third-party P2P object -NV_STATUS CliAddThirdPartyP2P (NvHandle, NvHandle, struct Subdevice *, NvU32, NvU64); - -// Delete the specified third-party P2P object -NV_STATUS CliDelThirdPartyP2P (NvHandle, NvHandle); - -// Get third-party P2P info given client/object handles -NV_STATUS CliGetThirdPartyP2PInfo (NvHandle, NvHandle, PCLI_THIRD_PARTY_P2P_INFO *); - // Get registered third-party P2P info from pid. Also match the provided client handle if provided. NV_STATUS CliNextThirdPartyP2PInfoWithPid (struct OBJGPU *, NvU32, NvHandle, struct RmClient**, PCLI_THIRD_PARTY_P2P_INFO *); @@ -577,13 +568,13 @@ NV_STATUS CliNextThirdPartyP2PInfoWithPid (struct OBJGPU *, NvU32, NvH NV_STATUS CliGetThirdPartyP2PInfoFromToken (NvU64, PCLI_THIRD_PARTY_P2P_INFO *); // Register an address space with a third-party P2P object -NV_STATUS CliAddThirdPartyP2PVASpace (NvHandle, NvHandle, NvHandle, NvU32 *); +NV_STATUS CliAddThirdPartyP2PVASpace (struct ThirdPartyP2P*, NvHandle, NvU32 *); // Unregister an address space from a third-party P2P object NV_STATUS CliDelThirdPartyP2PVASpace (struct ThirdPartyP2P*, NvHandle); // Register video memory with a third-party P2P object -NV_STATUS CliAddThirdPartyP2PVidmemInfo (NvHandle, NvHandle, NvHandle, NvU64, NvU64, NvU64, struct Memory *); +NV_STATUS CliAddThirdPartyP2PVidmemInfo (struct ThirdPartyP2P*, NvHandle, NvU64, NvU64, NvU64, struct Memory *); // Unregister video memory from a third-party P2P object NV_STATUS CliDelThirdPartyP2PVidmemInfo (struct ThirdPartyP2P*, NvHandle); @@ -592,19 +583,19 @@ NV_STATUS CliDelThirdPartyP2PVidmemInfo (struct ThirdPartyP2P*, NvHand void CliDelThirdPartyP2PVidmemInfoPersistent (struct ThirdPartyP2P*, CLI_THIRD_PARTY_P2P_VIDMEM_INFO*); // Find registered video memory given an address -NV_STATUS CliGetThirdPartyP2PVidmemInfoFromAddress (NvHandle, NvHandle, NvU64, NvU64, NvU64 *, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO *); +NV_STATUS CliGetThirdPartyP2PVidmemInfoFromAddress (struct ThirdPartyP2P*, NvU64, NvU64, NvU64 *, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO *); // Find registered video memory given a VidmemInfo ID -NV_STATUS CliGetThirdPartyP2PVidmemInfoFromId(NvHandle, NvHandle, NvU64, CLI_THIRD_PARTY_P2P_VIDMEM_INFO **); +NV_STATUS CliGetThirdPartyP2PVidmemInfoFromId(struct ThirdPartyP2P*, NvU64, CLI_THIRD_PARTY_P2P_VIDMEM_INFO **); // Find platformData given a P2PInfo object NV_STATUS CliGetThirdPartyP2PPlatformData (PCLI_THIRD_PARTY_P2P_INFO, void *); // Associate a P2P mapping with registered video memory -NV_STATUS CliAddThirdPartyP2PMappingInfo (NvHandle, NvHandle, NvHandle, void *, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *, void *, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *); +NV_STATUS CliAddThirdPartyP2PMappingInfo (struct ThirdPartyP2P*, NvHandle, void *, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *, void *, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *); // Find a P2P mapping given its platform specific data -NV_STATUS CliGetThirdPartyP2PMappingInfoFromKey (NvHandle, NvHandle, NvHandle, void *, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *); +NV_STATUS CliGetThirdPartyP2PMappingInfoFromKey (struct ThirdPartyP2P*, NvHandle, void *, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *); // Register pid & client with a third-party P2P Info object NV_STATUS CliAddThirdPartyP2PClientPid (NvHandle, NvHandle, NvU32, NvU32); @@ -616,7 +607,7 @@ NV_STATUS CliDelThirdPartyP2PClientPid (struct RmClient*, NvHandle, Nv NV_STATUS CliUnregisterFromThirdPartyP2P (struct RmClient*); // Register a free callback -NV_STATUS CliRegisterThirdPartyP2PMappingCallback (NvHandle, NvHandle, NvHandle, void *, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *, void *); +NV_STATUS CliRegisterThirdPartyP2PMappingCallback (struct ThirdPartyP2P*, NvHandle, void *, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *, void *); // Unregister memory from a third-party P2P Info object void CliUnregisterMemoryFromThirdPartyP2P(struct Memory *pMemory); diff --git a/src/nvidia/generated/g_timed_sema_nvoc.h b/src/nvidia/generated/g_timed_sema_nvoc.h index 85418732ba..a97cb9ed21 100644 --- a/src/nvidia/generated/g_timed_sema_nvoc.h +++ b/src/nvidia/generated/g_timed_sema_nvoc.h @@ -182,11 +182,11 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject**, Dynamic*, NvU3 #define tsemaGetNotificationShare(pNotifier) tsemaGetNotificationShare_DISPATCH(pNotifier) #define tsemaMap(pGpuResource, pCallContext, pParams, pCpuMapping) tsemaMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define tsemaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) tsemaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS tsemaRelease_KERNEL(struct OBJGPU *pGpu, NvU64 semaphoreVA, NvU64 notifierVA, NvU32 hVASpace, NvU32 releasevalue, NvU32 completionStatus, NvHandle hClient); +NV_STATUS tsemaRelease_KERNEL(struct OBJGPU *pGpu, NvU64 semaphoreVA, NvU64 notifierVA, NvU32 hVASpace, NvU32 releasevalue, NvU32 completionStatus, struct RsClient *pClient); -#define tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) tsemaRelease_KERNEL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) -#define tsemaRelease_HAL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) +#define tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) tsemaRelease_KERNEL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) +#define tsemaRelease_HAL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) NV_STATUS tsemaGetSwMethods_IMPL(struct TimedSemaSwObject *pTimedSemSw, const METHOD **ppMethods, NvU32 *pNumMethods); diff --git a/src/nvidia/generated/g_usermode_api_nvoc.c b/src/nvidia/generated/g_usermode_api_nvoc.c index f753e3051f..6006392faa 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.c +++ b/src/nvidia/generated/g_usermode_api_nvoc.c @@ -23,10 +23,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; -void __nvoc_init_UserModeApi(UserModeApi*, RmHalspecOwner* ); -void __nvoc_init_funcTable_UserModeApi(UserModeApi*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi*, RmHalspecOwner* , CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); -void __nvoc_init_dataField_UserModeApi(UserModeApi*, RmHalspecOwner* ); +void __nvoc_init_UserModeApi(UserModeApi*); +void __nvoc_init_funcTable_UserModeApi(UserModeApi*); +NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_UserModeApi(UserModeApi*); void __nvoc_dtor_UserModeApi(UserModeApi*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_UserModeApi; @@ -169,8 +169,8 @@ static NV_STATUS __nvoc_thunk_Memory_usrmodeIsReady(struct UserModeApi *pMemory, return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeCheckCopyPermissions(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_usrmodeCheckCopyPermissions(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_usrmodePreDestruct(struct UserModeApi *pResource) { @@ -205,21 +205,16 @@ void __nvoc_dtor_UserModeApi(UserModeApi *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +void __nvoc_init_dataField_UserModeApi(UserModeApi *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } NV_STATUS __nvoc_ctor_Memory(Memory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); -NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; status = __nvoc_ctor_Memory(&pThis->__nvoc_base_Memory, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_UserModeApi_fail_Memory; - __nvoc_init_dataField_UserModeApi(pThis, pRmhalspecowner); + __nvoc_init_dataField_UserModeApi(pThis); status = __nvoc_usrmodeConstruct(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_UserModeApi_fail__init; @@ -233,23 +228,8 @@ NV_STATUS __nvoc_ctor_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspec return status; } -static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - - // Hal function -- usrmodeConstructHal - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__usrmodeConstructHal__ = &usrmodeConstructHal_GV100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__usrmodeConstructHal__ = &usrmodeConstructHal_GH100; - } pThis->__usrmodeCanCopy__ = &usrmodeCanCopy_IMPL; @@ -304,12 +284,12 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwn pThis->__usrmodeAccessCallback__ = &__nvoc_thunk_RmResource_usrmodeAccessCallback; } -void __nvoc_init_funcTable_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner) { - __nvoc_init_funcTable_UserModeApi_1(pThis, pRmhalspecowner); +void __nvoc_init_funcTable_UserModeApi(UserModeApi *pThis) { + __nvoc_init_funcTable_UserModeApi_1(pThis); } void __nvoc_init_Memory(Memory*); -void __nvoc_init_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner) { +void __nvoc_init_UserModeApi(UserModeApi *pThis) { pThis->__nvoc_pbase_UserModeApi = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; @@ -317,14 +297,13 @@ void __nvoc_init_UserModeApi(UserModeApi *pThis, RmHalspecOwner *pRmhalspecowner pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource; pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_Memory; __nvoc_init_Memory(&pThis->__nvoc_base_Memory); - __nvoc_init_funcTable_UserModeApi(pThis, pRmhalspecowner); + __nvoc_init_funcTable_UserModeApi(pThis); } NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status; Object *pParentObj; UserModeApi *pThis; - RmHalspecOwner *pRmhalspecowner; status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UserModeApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) @@ -346,12 +325,8 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi **ppThis, Dynamic *pParent, N pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; } - if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) - pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); - NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); - - __nvoc_init_UserModeApi(pThis, pRmhalspecowner); - status = __nvoc_ctor_UserModeApi(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); + __nvoc_init_UserModeApi(pThis); + status = __nvoc_ctor_UserModeApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_UserModeApi_cleanup; *ppThis = pThis; diff --git a/src/nvidia/generated/g_usermode_api_nvoc.h b/src/nvidia/generated/g_usermode_api_nvoc.h index 19b4cb8602..f031dacd82 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.h +++ b/src/nvidia/generated/g_usermode_api_nvoc.h @@ -58,7 +58,6 @@ struct UserModeApi { struct RmResource *__nvoc_pbase_RmResource; struct Memory *__nvoc_pbase_Memory; struct UserModeApi *__nvoc_pbase_UserModeApi; - NV_STATUS (*__usrmodeConstructHal__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NvBool (*__usrmodeCanCopy__)(struct UserModeApi *); NV_STATUS (*__usrmodeCheckMemInterUnmap__)(struct UserModeApi *, NvBool); NvBool (*__usrmodeShareCallback__)(struct UserModeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); @@ -78,7 +77,7 @@ struct UserModeApi { NV_STATUS (*__usrmodeControlFilter__)(struct UserModeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeControlSerialization_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeIsReady__)(struct UserModeApi *, NvBool); - NV_STATUS (*__usrmodeCheckCopyPermissions__)(struct UserModeApi *, struct OBJGPU *, NvHandle); + NV_STATUS (*__usrmodeCheckCopyPermissions__)(struct UserModeApi *, struct OBJGPU *, struct Device *); void (*__usrmodePreDestruct__)(struct UserModeApi *); NV_STATUS (*__usrmodeIsDuplicate__)(struct UserModeApi *, NvHandle, NvBool *); void (*__usrmodeControlSerialization_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -114,8 +113,6 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT #define __objCreate_UserModeApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_UserModeApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define usrmodeConstructHal(pUserModeApi, pCallContext, pParams) usrmodeConstructHal_DISPATCH(pUserModeApi, pCallContext, pParams) -#define usrmodeConstructHal_HAL(pUserModeApi, pCallContext, pParams) usrmodeConstructHal_DISPATCH(pUserModeApi, pCallContext, pParams) #define usrmodeCanCopy(pUserModeApi) usrmodeCanCopy_DISPATCH(pUserModeApi) #define usrmodeCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) usrmodeCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define usrmodeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) usrmodeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) @@ -135,20 +132,12 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT #define usrmodeControlFilter(pResource, pCallContext, pParams) usrmodeControlFilter_DISPATCH(pResource, pCallContext, pParams) #define usrmodeControlSerialization_Prologue(pResource, pCallContext, pParams) usrmodeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define usrmodeIsReady(pMemory, bCopyConstructorContext) usrmodeIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define usrmodeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) usrmodeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define usrmodeCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) usrmodeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define usrmodePreDestruct(pResource) usrmodePreDestruct_DISPATCH(pResource) #define usrmodeIsDuplicate(pMemory, hMemory, pDuplicate) usrmodeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define usrmodeControlSerialization_Epilogue(pResource, pCallContext, pParams) usrmodeControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define usrmodeMap(pMemory, pCallContext, pParams, pCpuMapping) usrmodeMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define usrmodeAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) usrmodeAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS usrmodeConstructHal_GV100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); - -NV_STATUS usrmodeConstructHal_GH100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); - -static inline NV_STATUS usrmodeConstructHal_DISPATCH(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - return pUserModeApi->__usrmodeConstructHal__(pUserModeApi, pCallContext, pParams); -} - NvBool usrmodeCanCopy_IMPL(struct UserModeApi *pUserModeApi); static inline NvBool usrmodeCanCopy_DISPATCH(struct UserModeApi *pUserModeApi) { @@ -227,8 +216,8 @@ static inline NV_STATUS usrmodeIsReady_DISPATCH(struct UserModeApi *pMemory, NvB return pMemory->__usrmodeIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS usrmodeCheckCopyPermissions_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__usrmodeCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS usrmodeCheckCopyPermissions_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__usrmodeCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void usrmodePreDestruct_DISPATCH(struct UserModeApi *pResource) { diff --git a/src/nvidia/generated/g_uvm_nvoc.c b/src/nvidia/generated/g_uvm_nvoc.c index 46a8898874..1b98e06338 100644 --- a/src/nvidia/generated/g_uvm_nvoc.c +++ b/src/nvidia/generated/g_uvm_nvoc.c @@ -83,7 +83,7 @@ static NV_STATUS __nvoc_thunk_OBJUVM_engstateStateInitUnlocked(OBJGPU *pGpu, str return uvmStateInitUnlocked(pGpu, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_OBJENGSTATE.offset)); } -static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[166]) { +static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[167]) { uvmRegisterIntrService(arg0, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_IntrService.offset), arg1); } diff --git a/src/nvidia/generated/g_uvm_nvoc.h b/src/nvidia/generated/g_uvm_nvoc.h index 14fef58fc2..c2fa870658 100644 --- a/src/nvidia/generated/g_uvm_nvoc.h +++ b/src/nvidia/generated/g_uvm_nvoc.h @@ -61,23 +61,33 @@ typedef enum * Contains the Unified Virtual Memory (UVM) feature related data. */ +struct AccessCounterBuffer; + +#ifndef __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ +#define __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ +typedef struct AccessCounterBuffer AccessCounterBuffer; +#endif /* __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_AccessCounterBuffer +#define __nvoc_class_id_AccessCounterBuffer 0x1f0074 +#endif /* __nvoc_class_id_AccessCounterBuffer */ + + /* * This structure is used to store all the necessary information concerning the access counter buffer. * It is contained within the UVM object. */ -struct ACCESS_CNTR_BUFFER +typedef struct { + // kernel fields + struct AccessCounterBuffer *pAccessCounterBuffer; // AccessCounterBuffer object + + // physical fields NvU64 bar2UvmAccessCntrBufferAddr; //This is the bar2 VA that is used by the gpu in // order to access the buffer - NvP64 hAccessCntrBufferCpuMapping; //This is a handle to the CPU mapping - MEMORY_DESCRIPTOR *pUvmAccessCntrAllocMemDesc; // Memory descriptor of the access counter buffer allocation MEMORY_DESCRIPTOR *pUvmAccessCntrMemDesc; // Memory descriptor of the reconstructed access counter buffer - NvHandle hAccessCntrBufferObject; // This is a unique object handle - NvHandle hAccessCntrBufferClient; // This is a unique client handle - NvU32 accessCntrBufferSize; //This represents the size of the buffer (the maximum size that - // can be used before the buffer gets full) -}; +} ACCESS_CNTR_BUFFER; typedef enum { @@ -119,7 +129,8 @@ struct OBJUVM { NV_STATUS (*__uvmStatePostLoad__)(POBJGPU, struct OBJUVM *, NvU32); NV_STATUS (*__uvmConstructEngine__)(POBJGPU, struct OBJUVM *, ENGDESCRIPTOR); NvBool (*__uvmIsPresent__)(POBJGPU, struct OBJUVM *); - struct ACCESS_CNTR_BUFFER accessCntrBuffer; + ACCESS_CNTR_BUFFER *pAccessCounterBuffers; + NvU32 accessCounterBufferCount; NvHandle hClient; NvHandle hSubdevice; RM_API *pRmApi; @@ -173,261 +184,261 @@ NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM**, Dynamic*, NvU32); #define uvmStatePostLoad(pGpu, pEngstate, arg0) uvmStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define uvmConstructEngine(pGpu, pEngstate, arg0) uvmConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define uvmIsPresent(pGpu, pEngstate) uvmIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmInitializeAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmInitializeAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmInitializeAccessCntrBuffer(pGpu, pUvm) uvmInitializeAccessCntrBuffer_IMPL(pGpu, pUvm) +#define uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmInitializeAccessCntrBuffer_IMPL(pGpu, pUvm, pAccessCounterBuffer) #endif //__nvoc_uvm_h_disabled -#define uvmInitializeAccessCntrBuffer_HAL(pGpu, pUvm) uvmInitializeAccessCntrBuffer(pGpu, pUvm) +#define uvmInitializeAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -NV_STATUS uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmTerminateAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmTerminateAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmTerminateAccessCntrBuffer(pGpu, pUvm) uvmTerminateAccessCntrBuffer_IMPL(pGpu, pUvm) +#define uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmTerminateAccessCntrBuffer_IMPL(pGpu, pUvm, pAccessCounterBuffer) #endif //__nvoc_uvm_h_disabled -#define uvmTerminateAccessCntrBuffer_HAL(pGpu, pUvm) uvmTerminateAccessCntrBuffer(pGpu, pUvm) +#define uvmTerminateAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -NV_STATUS uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmInitAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmInitAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmInitAccessCntrBuffer(pGpu, pUvm) uvmInitAccessCntrBuffer_GV100(pGpu, pUvm) +#define uvmInitAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmInitAccessCntrBuffer_GV100(pGpu, pUvm, pAccessCounterBuffer) #endif //__nvoc_uvm_h_disabled -#define uvmInitAccessCntrBuffer_HAL(pGpu, pUvm) uvmInitAccessCntrBuffer(pGpu, pUvm) +#define uvmInitAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmInitAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -NV_STATUS uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmDestroyAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmDestroyAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmDestroyAccessCntrBuffer(pGpu, pUvm) uvmDestroyAccessCntrBuffer_GV100(pGpu, pUvm) +#define uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer_GV100(pGpu, pUvm, pAccessCounterBuffer) #endif //__nvoc_uvm_h_disabled -#define uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm) uvmDestroyAccessCntrBuffer(pGpu, pUvm) +#define uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1) { +static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { return NV_OK; } #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrBufferUnregister(OBJGPU *arg0, struct OBJUVM *arg1) { +static inline NV_STATUS uvmAccessCntrBufferUnregister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferUnregister(arg0, arg1) uvmAccessCntrBufferUnregister_ac1694(arg0, arg1) +#define uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister_ac1694(arg0, arg1, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferUnregister_HAL(arg0, arg1) uvmAccessCntrBufferUnregister(arg0, arg1) +#define uvmAccessCntrBufferUnregister_HAL(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) -static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 arg2, RmPhysAddr *arg3) { +static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { return NV_OK; } #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrBufferRegister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 arg2, RmPhysAddr *arg3) { +static inline NV_STATUS uvmAccessCntrBufferRegister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferRegister(arg0, arg1, arg2, arg3) uvmAccessCntrBufferRegister_ac1694(arg0, arg1, arg2, arg3) +#define uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister_ac1694(arg0, arg1, accessCounterIndex, arg2, arg3) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferRegister_HAL(arg0, arg1, arg2, arg3) uvmAccessCntrBufferRegister(arg0, arg1, arg2, arg3) +#define uvmAccessCntrBufferRegister_HAL(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) -NV_STATUS uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmUnloadAccessCntrBuffer(pGpu, pUvm) uvmUnloadAccessCntrBuffer_GV100(pGpu, pUvm) +#define uvmUnloadAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) uvmUnloadAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm) uvmUnloadAccessCntrBuffer(pGpu, pUvm) +#define uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex) uvmUnloadAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) -NV_STATUS uvmSetupAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); +NV_STATUS uvmSetupAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmSetupAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NV_STATUS uvmSetupAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmSetupAccessCntrBuffer(pGpu, pUvm) uvmSetupAccessCntrBuffer_GV100(pGpu, pUvm) +#define uvmSetupAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) uvmSetupAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm) uvmSetupAccessCntrBuffer(pGpu, pUvm) +#define uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex) uvmSetupAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) -NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0); +NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmReadAccessCntrBufferPutPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0) { +static inline NV_STATUS uvmReadAccessCntrBufferPutPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, arg0) uvmReadAccessCntrBufferPutPtr_TU102(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferPutPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, arg0) uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0); +NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmReadAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0) { +static inline NV_STATUS uvmReadAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, arg0) uvmReadAccessCntrBufferGetPtr_TU102(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferGetPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, arg0) uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool *arg0); +NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool *arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmReadAccessCntrBufferFullPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool *arg0) { +static inline NV_STATUS uvmReadAccessCntrBufferFullPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, arg0) uvmReadAccessCntrBufferFullPtr_TU102(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferFullPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, arg0) uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, arg0) +#define uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); +NV_STATUS uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmResetAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { +static inline NV_STATUS uvmResetAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmResetAccessCntrBuffer(pGpu, pUvm, arg0) uvmResetAccessCntrBuffer_GV100(pGpu, pUvm, arg0) +#define uvmResetAccessCntrBuffer(pGpu, pUvm, accessCounterIndex, arg0) uvmResetAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, arg0) uvmResetAccessCntrBuffer(pGpu, pUvm, arg0) +#define uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmResetAccessCntrBuffer(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, ACCESS_CNTR_TYPE arg0, NvU32 arg1); +NV_STATUS uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, ACCESS_CNTR_TYPE arg0, NvU32 arg1); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrSetGranularity(OBJGPU *pGpu, struct OBJUVM *pUvm, ACCESS_CNTR_TYPE arg0, NvU32 arg1) { +static inline NV_STATUS uvmAccessCntrSetGranularity(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, ACCESS_CNTR_TYPE arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetGranularity(pGpu, pUvm, arg0, arg1) uvmAccessCntrSetGranularity_TU102(pGpu, pUvm, arg0, arg1) +#define uvmAccessCntrSetGranularity(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetGranularity_TU102(pGpu, pUvm, accessCounterIndex, arg0, arg1) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, arg0, arg1) uvmAccessCntrSetGranularity(pGpu, pUvm, arg0, arg1) +#define uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetGranularity(pGpu, pUvm, accessCounterIndex, arg0, arg1) -NV_STATUS uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); +NV_STATUS uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrSetThreshold(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { +static inline NV_STATUS uvmAccessCntrSetThreshold(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetThreshold(pGpu, pUvm, arg0) uvmAccessCntrSetThreshold_TU102(pGpu, pUvm, arg0) +#define uvmAccessCntrSetThreshold(pGpu, pUvm, accessCounterIndex, arg0) uvmAccessCntrSetThreshold_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, arg0) uvmAccessCntrSetThreshold(pGpu, pUvm, arg0) +#define uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmAccessCntrSetThreshold(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0, NvU32 arg1); +NV_STATUS uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0, NvU32 arg1); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrSetCounterLimit(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0, NvU32 arg1) { +static inline NV_STATUS uvmAccessCntrSetCounterLimit(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetCounterLimit(pGpu, pUvm, arg0, arg1) uvmAccessCntrSetCounterLimit_GV100(pGpu, pUvm, arg0, arg1) +#define uvmAccessCntrSetCounterLimit(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetCounterLimit_GV100(pGpu, pUvm, accessCounterIndex, arg0, arg1) #endif //__nvoc_uvm_h_disabled -#define uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, arg0, arg1) uvmAccessCntrSetCounterLimit(pGpu, pUvm, arg0, arg1) +#define uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetCounterLimit(pGpu, pUvm, accessCounterIndex, arg0, arg1) -NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); +NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmWriteAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { +static inline NV_STATUS uvmWriteAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, arg0) uvmWriteAccessCntrBufferGetPtr_TU102(pGpu, pUvm, arg0) +#define uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmWriteAccessCntrBufferGetPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, arg0) uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, arg0) +#define uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmEnableAccessCntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0); +NV_STATUS uvmEnableAccessCntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmEnableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0) { +static inline NV_STATUS uvmEnableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmEnableAccessCntr(pGpu, pUvm, arg0) uvmEnableAccessCntr_TU102(pGpu, pUvm, arg0) +#define uvmEnableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) uvmEnableAccessCntr_TU102(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmEnableAccessCntr_HAL(pGpu, pUvm, arg0) uvmEnableAccessCntr(pGpu, pUvm, arg0) +#define uvmEnableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmEnableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) -NV_STATUS uvmDisableAccessCntr_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0); +NV_STATUS uvmDisableAccessCntr_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmDisableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0) { +static inline NV_STATUS uvmDisableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmDisableAccessCntr(pGpu, pUvm, arg0) uvmDisableAccessCntr_GV100(pGpu, pUvm, arg0) +#define uvmDisableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) uvmDisableAccessCntr_GV100(pGpu, pUvm, accessCounterIndex, arg0) #endif //__nvoc_uvm_h_disabled -#define uvmDisableAccessCntr_HAL(pGpu, pUvm, arg0) uvmDisableAccessCntr(pGpu, pUvm, arg0) +#define uvmDisableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmDisableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) NV_STATUS uvmEnableAccessCntrIntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); @@ -457,19 +468,19 @@ static inline NV_STATUS uvmDisableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pU #define uvmDisableAccessCntrIntr_HAL(pGpu, pUvm) uvmDisableAccessCntrIntr(pGpu, pUvm) -NV_STATUS uvmGetAccessCntrRegisterMappings_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6); +NV_STATUS uvmGetAccessCntrRegisterMappings_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6); #ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmGetAccessCntrRegisterMappings(OBJGPU *pGpu, struct OBJUVM *pUvm, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6) { +static inline NV_STATUS uvmGetAccessCntrRegisterMappings(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_uvm_h_disabled -#define uvmGetAccessCntrRegisterMappings(pGpu, pUvm, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings_TU102(pGpu, pUvm, arg0, arg1, arg2, arg3, arg4, arg5, arg6) +#define uvmGetAccessCntrRegisterMappings(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings_TU102(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) #endif //__nvoc_uvm_h_disabled -#define uvmGetAccessCntrRegisterMappings_HAL(pGpu, pUvm, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings(pGpu, pUvm, arg0, arg1, arg2, arg3, arg4, arg5, arg6) +#define uvmGetAccessCntrRegisterMappings_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) NV_STATUS uvmAccessCntrService_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); @@ -485,73 +496,171 @@ static inline NV_STATUS uvmAccessCntrService(OBJGPU *pGpu, struct OBJUVM *pUvm) #define uvmAccessCntrService_HAL(pGpu, pUvm) uvmAccessCntrService(pGpu, pUvm) -NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); +NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NvU32 uvmGetAccessCounterBufferSize(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NvU32 uvmGetAccessCounterBufferSize(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return 0; } #else //__nvoc_uvm_h_disabled -#define uvmGetAccessCounterBufferSize(pGpu, pUvm) uvmGetAccessCounterBufferSize_TU102(pGpu, pUvm) +#define uvmGetAccessCounterBufferSize(pGpu, pUvm, accessCounterIndex) uvmGetAccessCounterBufferSize_TU102(pGpu, pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm) uvmGetAccessCounterBufferSize(pGpu, pUvm) +#define uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm, accessCounterIndex) uvmGetAccessCounterBufferSize(pGpu, pUvm, accessCounterIndex) -void uvmProgramWriteAccessCntrBufferAddress_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU64 addr); +void uvmProgramWriteAccessCntrBufferAddress_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU64 addr); #ifdef __nvoc_uvm_h_disabled -static inline void uvmProgramWriteAccessCntrBufferAddress(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU64 addr) { +static inline void uvmProgramWriteAccessCntrBufferAddress(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU64 addr) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); } #else //__nvoc_uvm_h_disabled -#define uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, addr) uvmProgramWriteAccessCntrBufferAddress_TU102(pGpu, pUvm, addr) +#define uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, accessCounterIndex, addr) uvmProgramWriteAccessCntrBufferAddress_TU102(pGpu, pUvm, accessCounterIndex, addr) #endif //__nvoc_uvm_h_disabled -#define uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, addr) uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, addr) +#define uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, accessCounterIndex, addr) uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, accessCounterIndex, addr) -void uvmProgramAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool bEn); +void uvmProgramAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool bEn); #ifdef __nvoc_uvm_h_disabled -static inline void uvmProgramAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool bEn) { +static inline void uvmProgramAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool bEn) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); } #else //__nvoc_uvm_h_disabled -#define uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, bEn) uvmProgramAccessCntrBufferEnabled_TU102(pGpu, pUvm, bEn) +#define uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex, bEn) uvmProgramAccessCntrBufferEnabled_TU102(pGpu, pUvm, accessCounterIndex, bEn) #endif //__nvoc_uvm_h_disabled -#define uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, bEn) uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, bEn) +#define uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, bEn) uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex, bEn) -NvBool uvmIsAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); +NvBool uvmIsAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NvBool uvmIsAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NvBool uvmIsAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_FALSE; } #else //__nvoc_uvm_h_disabled -#define uvmIsAccessCntrBufferEnabled(pGpu, pUvm) uvmIsAccessCntrBufferEnabled_TU102(pGpu, pUvm) +#define uvmIsAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferEnabled_TU102(pGpu, pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm) uvmIsAccessCntrBufferEnabled(pGpu, pUvm) +#define uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex) -NvBool uvmIsAccessCntrBufferPushed_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); +NvBool uvmIsAccessCntrBufferPushed_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); #ifdef __nvoc_uvm_h_disabled -static inline NvBool uvmIsAccessCntrBufferPushed(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NvBool uvmIsAccessCntrBufferPushed(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); return NV_FALSE; } #else //__nvoc_uvm_h_disabled -#define uvmIsAccessCntrBufferPushed(pGpu, pUvm) uvmIsAccessCntrBufferPushed_TU102(pGpu, pUvm) +#define uvmIsAccessCntrBufferPushed(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferPushed_TU102(pGpu, pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferPushed(pGpu, pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferPut_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferPut(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferPut(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferPut_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferPut_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferPut(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferGet_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferGet(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferGet(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferGet_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferGet(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferHi_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferHi(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferHi(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferHi_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferHi_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferHi(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferLo_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferLo(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferLo(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferLo_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferLo(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferConfig_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferConfig(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferConfig(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferConfig_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferConfig_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferConfig(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferInfo_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferInfo(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferInfo(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferInfo_TU102(pUvm, accessCounterIndex) +#endif //__nvoc_uvm_h_disabled + +#define uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferInfo(pUvm, accessCounterIndex) + +NvU32 uvmGetRegOffsetAccessCntrBufferSize_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); + + +#ifdef __nvoc_uvm_h_disabled +static inline NvU32 uvmGetRegOffsetAccessCntrBufferSize(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); + return 0; +} +#else //__nvoc_uvm_h_disabled +#define uvmGetRegOffsetAccessCntrBufferSize(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferSize_TU102(pUvm, accessCounterIndex) #endif //__nvoc_uvm_h_disabled -#define uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm) uvmIsAccessCntrBufferPushed(pGpu, pUvm) +#define uvmGetRegOffsetAccessCntrBufferSize_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferSize(pUvm, accessCounterIndex) void uvmStateDestroy_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); @@ -565,9 +674,9 @@ static inline NV_STATUS uvmStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct OBJUV return pUvm->__uvmStateInitUnlocked__(pGpu, pUvm); } -void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[166]); +void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[167]); -static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[166]) { +static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[167]) { pUvm->__uvmRegisterIntrService__(arg0, pUvm, arg1); } diff --git a/src/nvidia/generated/g_uvm_sw_nvoc.c b/src/nvidia/generated/g_uvm_sw_nvoc.c index 465f13f118..f8d3622479 100644 --- a/src/nvidia/generated/g_uvm_sw_nvoc.c +++ b/src/nvidia/generated/g_uvm_sw_nvoc.c @@ -298,10 +298,7 @@ static void __nvoc_init_funcTable_UvmSwObject_1(UvmSwObject *pThis, RmHalspecOwn PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- uvmswGetSwMethods - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__uvmswGetSwMethods__ = &uvmswGetSwMethods_56cd7a; - } + pThis->__uvmswGetSwMethods__ = &uvmswGetSwMethods_56cd7a; pThis->__nvoc_base_ChannelDescendant.__chandesGetSwMethods__ = &__nvoc_thunk_UvmSwObject_chandesGetSwMethods; diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.h b/src/nvidia/generated/g_vaspace_api_nvoc.h index 743eff4fa1..45c2946b2c 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.h +++ b/src/nvidia/generated/g_vaspace_api_nvoc.h @@ -28,7 +28,7 @@ extern "C" { * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - + #include "g_vaspace_api_nvoc.h" #ifndef VASPACE_API_H diff --git a/src/nvidia/generated/g_vaspace_nvoc.h b/src/nvidia/generated/g_vaspace_nvoc.h index 34120e8bf6..a7e651183d 100644 --- a/src/nvidia/generated/g_vaspace_nvoc.h +++ b/src/nvidia/generated/g_vaspace_nvoc.h @@ -256,7 +256,7 @@ struct OBJVASPACE { NV_STATUS (*__vaspaceReserveMempool__)(struct OBJVASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); struct OBJEHEAP *(*__vaspaceGetHeap__)(struct OBJVASPACE *); NvU64 (*__vaspaceGetMapPageSize__)(struct OBJVASPACE *, struct OBJGPU *, EMEMBLOCK *); - NvU32 (*__vaspaceGetBigPageSize__)(struct OBJVASPACE *); + NvU64 (*__vaspaceGetBigPageSize__)(struct OBJVASPACE *); NvBool (*__vaspaceIsMirrored__)(struct OBJVASPACE *); NvBool (*__vaspaceIsFaultCapable__)(struct OBJVASPACE *); NvBool (*__vaspaceIsExternallyOwned__)(struct OBJVASPACE *); @@ -435,12 +435,12 @@ static inline NvU64 vaspaceGetMapPageSize_DISPATCH(struct OBJVASPACE *pVAS, stru return pVAS->__vaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } -static inline NvU32 vaspaceGetBigPageSize_07238a(struct OBJVASPACE *pVAS) { +static inline NvU64 vaspaceGetBigPageSize_07238a(struct OBJVASPACE *pVAS) { NV_ASSERT_PRECOMP(((NvBool)(0 != 0))); return 0U; } -static inline NvU32 vaspaceGetBigPageSize_DISPATCH(struct OBJVASPACE *pVAS) { +static inline NvU64 vaspaceGetBigPageSize_DISPATCH(struct OBJVASPACE *pVAS) { return pVAS->__vaspaceGetBigPageSize__(pVAS); } diff --git a/src/nvidia/generated/g_video_mem_nvoc.c b/src/nvidia/generated/g_video_mem_nvoc.c index a8ea3e24a4..89f301eedf 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.c +++ b/src/nvidia/generated/g_video_mem_nvoc.c @@ -102,8 +102,8 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_VideoMemory = /*pExportInfo=*/ &__nvoc_export_info_VideoMemory }; -static NV_STATUS __nvoc_thunk_VideoMemory_memCheckCopyPermissions(struct Memory *pVideoMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return vidmemCheckCopyPermissions((struct VideoMemory *)(((unsigned char *)pVideoMemory) - __nvoc_rtti_VideoMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_VideoMemory_memCheckCopyPermissions(struct Memory *pVideoMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return vidmemCheckCopyPermissions((struct VideoMemory *)(((unsigned char *)pVideoMemory) - __nvoc_rtti_VideoMemory_Memory.offset), pDstGpu, pDstDevice); } static NV_STATUS __nvoc_thunk_Memory_vidmemCheckMemInterUnmap(struct VideoMemory *pMemory, NvBool bSubdeviceHandleProvided) { diff --git a/src/nvidia/generated/g_video_mem_nvoc.h b/src/nvidia/generated/g_video_mem_nvoc.h index 4b409885da..a47926ae01 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.h +++ b/src/nvidia/generated/g_video_mem_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,6 +38,18 @@ extern "C" { #include "gpu/mem_mgr/heap_base.h" typedef struct PMA_ALLOC_INFO PMA_ALLOC_INFO; +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + + #ifdef NVOC_VIDEO_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x @@ -54,7 +66,7 @@ struct VideoMemory { struct Memory *__nvoc_pbase_Memory; struct StandardMemory *__nvoc_pbase_StandardMemory; struct VideoMemory *__nvoc_pbase_VideoMemory; - NV_STATUS (*__vidmemCheckCopyPermissions__)(struct VideoMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__vidmemCheckCopyPermissions__)(struct VideoMemory *, struct OBJGPU *, struct Device *); NV_STATUS (*__vidmemCheckMemInterUnmap__)(struct VideoMemory *, NvBool); NvBool (*__vidmemShareCallback__)(struct VideoMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__vidmemMapTo__)(struct VideoMemory *, RS_RES_MAP_TO_PARAMS *); @@ -109,7 +121,7 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory**, Dynamic*, NvU32, CALL_CONT #define __objCreate_VideoMemory(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_VideoMemory((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define vidmemCheckCopyPermissions(pVideoMemory, pDstGpu, hDstClientNvBool) vidmemCheckCopyPermissions_DISPATCH(pVideoMemory, pDstGpu, hDstClientNvBool) +#define vidmemCheckCopyPermissions(pVideoMemory, pDstGpu, pDstDevice) vidmemCheckCopyPermissions_DISPATCH(pVideoMemory, pDstGpu, pDstDevice) #define vidmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) vidmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define vidmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vidmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define vidmemMapTo(pResource, pParams) vidmemMapTo_DISPATCH(pResource, pParams) @@ -134,10 +146,10 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory**, Dynamic*, NvU32, CALL_CONT #define vidmemControlSerialization_Epilogue(pResource, pCallContext, pParams) vidmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vidmemMap(pMemory, pCallContext, pParams, pCpuMapping) vidmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define vidmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vidmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS vidmemCheckCopyPermissions_IMPL(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool); +NV_STATUS vidmemCheckCopyPermissions_IMPL(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice); -static inline NV_STATUS vidmemCheckCopyPermissions_DISPATCH(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pVideoMemory->__vidmemCheckCopyPermissions__(pVideoMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS vidmemCheckCopyPermissions_DISPATCH(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pVideoMemory->__vidmemCheckCopyPermissions__(pVideoMemory, pDstGpu, pDstDevice); } static inline NV_STATUS vidmemCheckMemInterUnmap_DISPATCH(struct VideoMemory *pMemory, NvBool bSubdeviceHandleProvided) { @@ -242,9 +254,9 @@ NV_STATUS vidmemConstruct_IMPL(struct VideoMemory *arg_pVideoMemory, CALL_CONTEX void vidmemDestruct_IMPL(struct VideoMemory *pVideoMemory); #define __nvoc_vidmemDestruct(pVideoMemory) vidmemDestruct_IMPL(pVideoMemory) -struct Heap *vidmemGetHeap_IMPL(struct OBJGPU *pGpu, NvHandle hClient, NvBool bSubheap); +struct Heap *vidmemGetHeap_IMPL(struct OBJGPU *pGpu, struct Device *pDevice, NvBool bSubheap); -#define vidmemGetHeap(pGpu, hClient, bSubheap) vidmemGetHeap_IMPL(pGpu, hClient, bSubheap) +#define vidmemGetHeap(pGpu, pDevice, bSubheap) vidmemGetHeap_IMPL(pGpu, pDevice, bSubheap) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c index 41410c4b9e..e84daf6234 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c @@ -231,10 +231,7 @@ static void __nvoc_init_funcTable_VirtMemAllocator_1(VirtMemAllocator *pThis, Rm } // Hal function -- dmaStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__dmaStatePostLoad__ = &dmaStatePostLoad_GM107; - } + pThis->__dmaStatePostLoad__ = &dmaStatePostLoad_GM107; pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_VirtMemAllocator_engstateConstructEngine; diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h index 4808b695e2..26ad67f51f 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h @@ -491,7 +491,6 @@ static inline NV_STATUS dmaFreeMap(struct OBJGPU *pGpu, struct VirtMemAllocator #define VAS_PAGESIZE_IDX_BIG 1 #define VAS_PAGESIZE_IDX_HUGE 2 #define VAS_PAGESIZE_IDX_512M 3 -#define VAS_PAGESIZE_IDX_MAX 4 // VMM-TODO Used by old VAS Object #define VAS_NUM_PAGESIZE_TYPES VAS_PAGESIZE_IDX_BIG+1 @@ -576,7 +575,7 @@ RmPhysAddr dmaPageArrayGetPhysAddr(DMA_PAGE_ARRAY *pPageArray, NvU32 pageIndex); #define DMA_VA_LIMIT_49B NVBIT(0) #define DMA_VA_LIMIT_57B NVBIT(1) #define DMA_ALLOC_VASPACE_SIZE_ALIGNED NVBIT(9) -// +// // Bug 3610538 For unlinked SLI, clients want to restrict internal buffers to // Internal VA range, so that SLI vaspaces can mirror each other. // diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.c b/src/nvidia/generated/g_virt_mem_range_nvoc.c index 2884982aed..d77ed8a79a 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.c @@ -187,8 +187,8 @@ static NV_STATUS __nvoc_thunk_Memory_vmrangeIsReady(struct VirtualMemoryRange *p return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeCheckCopyPermissions(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_vmrangeCheckCopyPermissions(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_vmrangePreDestruct(struct VirtualMemoryRange *pResource) { diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.h b/src/nvidia/generated/g_virt_mem_range_nvoc.h index 47ac972ac0..7263e8f6b1 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.h @@ -77,7 +77,7 @@ struct VirtualMemoryRange { NV_STATUS (*__vmrangeControlSerialization_Prologue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vmrangeCanCopy__)(struct VirtualMemoryRange *); NV_STATUS (*__vmrangeIsReady__)(struct VirtualMemoryRange *, NvBool); - NV_STATUS (*__vmrangeCheckCopyPermissions__)(struct VirtualMemoryRange *, struct OBJGPU *, NvHandle); + NV_STATUS (*__vmrangeCheckCopyPermissions__)(struct VirtualMemoryRange *, struct OBJGPU *, struct Device *); void (*__vmrangePreDestruct__)(struct VirtualMemoryRange *); NV_STATUS (*__vmrangeIsDuplicate__)(struct VirtualMemoryRange *, NvHandle, NvBool *); void (*__vmrangeControlSerialization_Epilogue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -132,7 +132,7 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange**, Dynamic*, Nv #define vmrangeControlSerialization_Prologue(pResource, pCallContext, pParams) vmrangeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vmrangeCanCopy(pStandardMemory) vmrangeCanCopy_DISPATCH(pStandardMemory) #define vmrangeIsReady(pMemory, bCopyConstructorContext) vmrangeIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define vmrangeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) vmrangeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define vmrangeCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) vmrangeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define vmrangePreDestruct(pResource) vmrangePreDestruct_DISPATCH(pResource) #define vmrangeIsDuplicate(pMemory, hMemory, pDuplicate) vmrangeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define vmrangeControlSerialization_Epilogue(pResource, pCallContext, pParams) vmrangeControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -214,8 +214,8 @@ static inline NV_STATUS vmrangeIsReady_DISPATCH(struct VirtualMemoryRange *pMemo return pMemory->__vmrangeIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS vmrangeCheckCopyPermissions_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__vmrangeCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS vmrangeCheckCopyPermissions_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__vmrangeCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void vmrangePreDestruct_DISPATCH(struct VirtualMemoryRange *pResource) { diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.c b/src/nvidia/generated/g_virtual_mem_nvoc.c index be5ba6244e..5773015bcb 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.c +++ b/src/nvidia/generated/g_virtual_mem_nvoc.c @@ -178,8 +178,8 @@ static NV_STATUS __nvoc_thunk_Memory_virtmemIsReady(struct VirtualMemory *pMemor return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), bCopyConstructorContext); } -static NV_STATUS __nvoc_thunk_Memory_virtmemCheckCopyPermissions(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pDstGpu, hDstClientNvBool); +static NV_STATUS __nvoc_thunk_Memory_virtmemCheckCopyPermissions(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pDstGpu, pDstDevice); } static void __nvoc_thunk_RsResource_virtmemPreDestruct(struct VirtualMemory *pResource) { diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.h b/src/nvidia/generated/g_virtual_mem_nvoc.h index cb02cb7e39..e582e57981 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.h +++ b/src/nvidia/generated/g_virtual_mem_nvoc.h @@ -79,7 +79,7 @@ struct VirtualMemory { NV_STATUS (*__virtmemControlSerialization_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__virtmemCanCopy__)(struct VirtualMemory *); NV_STATUS (*__virtmemIsReady__)(struct VirtualMemory *, NvBool); - NV_STATUS (*__virtmemCheckCopyPermissions__)(struct VirtualMemory *, struct OBJGPU *, NvHandle); + NV_STATUS (*__virtmemCheckCopyPermissions__)(struct VirtualMemory *, struct OBJGPU *, struct Device *); void (*__virtmemPreDestruct__)(struct VirtualMemory *); NV_STATUS (*__virtmemIsDuplicate__)(struct VirtualMemory *, NvHandle, NvBool *); void (*__virtmemControlSerialization_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -141,7 +141,7 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory**, Dynamic*, NvU32, CALL_ #define virtmemControlSerialization_Prologue(pResource, pCallContext, pParams) virtmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define virtmemCanCopy(pStandardMemory) virtmemCanCopy_DISPATCH(pStandardMemory) #define virtmemIsReady(pMemory, bCopyConstructorContext) virtmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) -#define virtmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) virtmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define virtmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) virtmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define virtmemPreDestruct(pResource) virtmemPreDestruct_DISPATCH(pResource) #define virtmemIsDuplicate(pMemory, hMemory, pDuplicate) virtmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define virtmemControlSerialization_Epilogue(pResource, pCallContext, pParams) virtmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -227,8 +227,8 @@ static inline NV_STATUS virtmemIsReady_DISPATCH(struct VirtualMemory *pMemory, N return pMemory->__virtmemIsReady__(pMemory, bCopyConstructorContext); } -static inline NV_STATUS virtmemCheckCopyPermissions_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__virtmemCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +static inline NV_STATUS virtmemCheckCopyPermissions_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__virtmemCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } static inline void virtmemPreDestruct_DISPATCH(struct VirtualMemory *pResource) { diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index 88d3ad973f..53bbd1f551 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -229,6 +229,7 @@ #define RMCFG_FEATURE_PLATFORM_GSP 0 // Running as part of GSP Firmware #define RMCFG_FEATURE_PLATFORM_MODS_WINDOWS 0 // Running as part of MODS on Windows #define RMCFG_FEATURE_PLATFORM_MODS_UNIX 0 // Running as part of MODS on UNIX +#define RMCFG_FEATURE_PLATFORM_VMWARE 0 // Running on VMware #define RMCFG_FEATURE_ARCH_UNKNOWN 0 // unknown arch #define RMCFG_FEATURE_ARCH_X86 0 // Intel x86, 32bit #define RMCFG_FEATURE_ARCH_X64 0 // Intel 64bit @@ -269,6 +270,7 @@ #define RMCFG_FEATURE_PAGE_RETIREMENT 1 // Offlining bad memory pages from the FB heap #define RMCFG_FEATURE_PMA 1 // Physical memory allocator #define RMCFG_FEATURE_DEVINIT_SCRIPT 0 // VBIOS scripting engine for sharing register sequences +#define RMCFG_FEATURE_UNIX_CONSOLE_STATE 1 // Unix console state management and display programming #define RMCFG_FEATURE_OLD_DAC 1 // Legacy display support with dac code #define RMCFG_FEATURE_CRC_POLLING 1 // GPU supports CRC Polling #define RMCFG_FEATURE_DSI_INFO 0 // DSI information structures support @@ -289,8 +291,10 @@ #define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY 0 // Tegra SOC NvDisplay Driver #define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY_MINIMAL 0 // Enable only those parts of display code which are needed for Tegra SOC NvDisplay Driver #define RMCFG_FEATURE_HEAD_REGIONAL_CRC 0 // Display Head Regional CRC support +#define RMCFG_FEATURE_FEATURE_GH180 1 // RMconfig to encapsulate GH180 features #define RMCFG_FEATURE_MULTICAST_FABRIC 1 // Support for MULTICAST_FABRIC #define RMCFG_FEATURE_NVLINK_ERROR_THRESHOLD 1 // Support for NVLINK_ERROR_THRESHOLD +#define RMCFG_FEATURE_FABRIC_LINEAR_ADDRESSING 1 // Unicast fabric memory management @@ -322,6 +326,7 @@ #define RMCFG_CLASS_NV1_MEMORY_LOCAL_USER 1 // aka NV01_MEMORY_LOCAL_USER #define RMCFG_CLASS_NV01_MEMORY_USER 1 // aka NV01_MEMORY_LOCAL_USER #define RMCFG_CLASS_NV1_MEMORY_USER 1 // aka NV01_MEMORY_LOCAL_USER +#define RMCFG_CLASS_NV_MEMORY_EXTENDED_USER 1 // Extended GPU Memory #define RMCFG_CLASS_NV01_MEMORY_VIRTUAL 1 #define RMCFG_CLASS_NV01_MEMORY_SYSTEM_DYNAMIC 1 // aka NV01_MEMORY_VIRTUAL #define RMCFG_CLASS_NV1_MEMORY_SYSTEM_DYNAMIC 1 // aka NV01_MEMORY_VIRTUAL @@ -338,6 +343,7 @@ #define RMCFG_CLASS_NV_IMEX_SESSION 0 #define RMCFG_CLASS_NV01_MEMORY_FLA 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORT_V2 0 +#define RMCFG_CLASS_NV_CE_UTILS 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORT_V2 0 #define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORTED_REF 0 @@ -415,6 +421,7 @@ #define RMCFG_CLASS_NV50_THIRD_PARTY_P2P 1 #define RMCFG_CLASS_FERMI_TWOD_A 1 // FERMI Graphics 2D #define RMCFG_CLASS_FERMI_VASPACE_A 1 // FERMI virtual address space +#define RMCFG_CLASS_HOPPER_SEC2_WORK_LAUNCH_A 1 // Confidential Computing Work Launch #define RMCFG_CLASS_GF100_HDACODEC 1 #define RMCFG_CLASS_NVB8B0_VIDEO_DECODER 1 // Decoder Class for Hopper #define RMCFG_CLASS_NVC4B0_VIDEO_DECODER 1 // Decoder Class for Turing @@ -469,7 +476,9 @@ #define RMCFG_CLASS_NV0060_SYNC_GPU_BOOST 1 // Synchronized GPU Boost Class. Defines a set of GPUs for Synchronized Boost #define RMCFG_CLASS_GP100_UVM_SW 1 // UVM SW class to support SW methods for fault cancel #define RMCFG_CLASS_NV_EVENT_BUFFER 1 // Event buffer class used to share event data with UMD +#define RMCFG_CLASS_NV_CONFIDENTIAL_COMPUTE 1 // Confidential Computing Class #define RMCFG_CLASS_NV_COUNTER_COLLECTION_UNIT 1 // Counter Collection Unit Class +#define RMCFG_CLASS_NV_SEMAPHORE_SURFACE 1 // GPU Semaphore encapsulation class @@ -567,7 +576,7 @@ #define RMCFG_MODULE_KERNEL_CE 1 // Kernel Copy Engine #define RMCFG_MODULE_PMU 0 // PMU peregrine core #define RMCFG_MODULE_KERNEL_PMU 1 // PMU peregrine core on Kernel(CPU) RM -#define RMCFG_MODULE_PLATFORM_REQUEST_HANDLER 0 // Platform Request Handler on Kernel(CPU) RM +#define RMCFG_MODULE_PLATFORM_REQUEST_HANDLER 1 // Platform Request Handler on Kernel(CPU) RM #define RMCFG_MODULE_MSENC 0 // Video Encoder (MSENC) Engine #define RMCFG_MODULE_KERNEL_NVENC 1 #define RMCFG_MODULE_HDA 0 // High Definition Audio (HDA) Engine @@ -663,9 +672,11 @@ #define RMCFG_MODULE_DCECLIENTRM 0 // DCE Client RM #define RMCFG_MODULE_DCB 0 // Display Control Block for all display related data in VBIOS/DCB Image #define RMCFG_MODULE_DISPMACRO 0 // DispMacro RM infrastructure for IED removal from VBIOS +#define RMCFG_MODULE_CONF_COMPUTE 1 // Confidential Compute #define RMCFG_MODULE_DISP_MGR 0 // Lid- and dock-related disp code for NOTEBOOK #define RMCFG_MODULE_PLATFORM 1 // Object for platform related features #define RMCFG_MODULE_KERNEL_CCU 1 // Counter Collection Unit Kernel(CPU) RM +#define RMCFG_MODULE_SPDM 1 // Secure Protocol and Data Management (SPDM) on Kernel(CPU) RM diff --git a/src/nvidia/inc/kernel/core/locks.h b/src/nvidia/inc/kernel/core/locks.h index 2c373137c4..7e6948f409 100644 --- a/src/nvidia/inc/kernel/core/locks.h +++ b/src/nvidia/inc/kernel/core/locks.h @@ -79,17 +79,17 @@ typedef struct NvU32 index; } LOCK_TRACE_INFO; -#define INSERT_LOCK_TRACE(plti, ra, t, d16, d32, ti, irql, pr, ts) \ -{ \ - (plti)->entries[(plti)->index].callerRA = (NvUPtr)ra; \ - (plti)->entries[(plti)->index].type = t; \ - (plti)->entries[(plti)->index].data16.value = d16; \ - (plti)->entries[(plti)->index].data32.value = d32; \ - (plti)->entries[(plti)->index].threadId = ti; \ - (plti)->entries[(plti)->index].timestamp = ts; \ - (plti)->entries[(plti)->index].bHighIrql = irql; \ - (plti)->entries[(plti)->index].priority = pr; \ - (plti)->index = ((plti)->index + 1) % MAX_TRACE_LOCK_CALLS; \ +#define INSERT_LOCK_TRACE(plti, ra, t, d16, d32, ti, irql, pr, ts) \ +{ \ + (plti)->entries[(plti)->index].callerRA = (NvUPtr)ra; \ + (plti)->entries[(plti)->index].type = t; \ + (plti)->entries[(plti)->index].data16.value = d16; \ + (plti)->entries[(plti)->index].data32.value = d32; \ + (plti)->entries[(plti)->index].threadId = ti; \ + (plti)->entries[(plti)->index].timestamp = ts; \ + (plti)->entries[(plti)->index].bHighIrql = irql; \ + (plti)->entries[(plti)->index].priority = pr; \ + (plti)->index = ((plti)->index + 1) % MAX_TRACE_LOCK_CALLS; \ } // diff --git a/src/nvidia/inc/kernel/core/prelude.h b/src/nvidia/inc/kernel/core/prelude.h index 7ae35a75c8..02c746a69d 100644 --- a/src/nvidia/inc/kernel/core/prelude.h +++ b/src/nvidia/inc/kernel/core/prelude.h @@ -81,11 +81,7 @@ typedef struct THREAD_STATE_NODE THREAD_STATE_NODE; // FW declare thread state #define NV_ROUNDUP(a,b) ((NV_CEIL(a,b))*(b)) #define NV_ROUND_TO_QUANTA(a, quanta) (((quanta) == 0) ? (a): ((((a) + ((quanta) >> 1)) / (quanta)) * (quanta))) #define NV_FLOOR_TO_QUANTA(a, quanta) (((a) / (quanta)) * (quanta)) -#ifndef NV_SIZEOF32 -#define NV_SIZEOF32(x) (sizeof(x)) -#endif #define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) -#define NV_ARRAY_ELEMENTS32(x) ((NV_SIZEOF32(x)/NV_SIZEOF32((x)[0]))) #define NV_BYTESWAP16(a) ((((a) & 0xff00)>>8) | \ (((a) & 0x00ff)<<8)) #define NV_BYTESWAP32(a) ((((a) & 0xff000000)>>24) | \ diff --git a/src/nvidia/inc/kernel/core/printf.h b/src/nvidia/inc/kernel/core/printf.h index d4db226848..612620d0fc 100644 --- a/src/nvidia/inc/kernel/core/printf.h +++ b/src/nvidia/inc/kernel/core/printf.h @@ -118,12 +118,12 @@ void osFlushLog(void); #if !NVCPU_IS_RISCV64 -#define DBG_BREAKPOINT_EX(PGPU, LEVEL) \ - do \ - { \ - NV_PRINTF(LEVEL_ERROR, "bp @ " NV_FILE_FMT ":%d\n", NV_FILE, __LINE__);\ - osFlushLog(); \ - DBG_ROUTINE(); \ +#define DBG_BREAKPOINT_EX(PGPU, LEVEL) \ + do \ + { \ + NV_PRINTF(LEVEL_ERROR, "bp @ " NV_FILE_FMT ":%d\n", NV_FILE, __LINE__); \ + osFlushLog(); \ + DBG_ROUTINE(); \ } while (0) #else // !NVCPU_IS_RISCV64 @@ -247,48 +247,48 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length); // and return NOT_FULL_POWER. See bug 1679965. // // -#define API_GPU_FULL_POWER_SANITY_CHECK(pGpu, bGpuAccess, bAllowWithoutSysmemAccess) \ - if ((!gpuIsGpuFullPower(pGpu)) && \ - (!(pGpu)->getProperty((pGpu), \ - PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ - { \ - DBG_BREAKPOINT(); \ - if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ - } \ - else if (gpuIsSurpriseRemovalSupported(pGpu) && \ - (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ - } \ - } \ - if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ +#define API_GPU_FULL_POWER_SANITY_CHECK(pGpu, bGpuAccess, bAllowWithoutSysmemAccess) \ + if ((!gpuIsGpuFullPower(pGpu)) && \ + (!(pGpu)->getProperty((pGpu), \ + PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ + { \ + DBG_BREAKPOINT(); \ + if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ + } \ + else if (gpuIsSurpriseRemovalSupported(pGpu) && \ + (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ + } \ + } \ + if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ } #define API_GPU_FULL_POWER_SANITY_CHECK_OR_GOTO(pGpu, bGpuAccess, bAllowWithoutSysmemAccess, status, tag) \ - if ((!gpuIsGpuFullPower(pGpu)) && \ - (!(pGpu)->getProperty((pGpu), \ - PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ - { \ - DBG_BREAKPOINT(); \ - if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ - { \ - status = NV_ERR_GPU_NOT_FULL_POWER; \ - goto tag; \ - } \ - else if (gpuIsSurpriseRemovalSupported(pGpu) && \ - (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ - { \ - status = NV_ERR_GPU_NOT_FULL_POWER; \ - goto tag; \ - } \ - } \ - if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ + if ((!gpuIsGpuFullPower(pGpu)) && \ + (!(pGpu)->getProperty((pGpu), \ + PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ + { \ + DBG_BREAKPOINT(); \ + if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ + { \ + status = NV_ERR_GPU_NOT_FULL_POWER; \ + goto tag; \ + } \ + else if (gpuIsSurpriseRemovalSupported(pGpu) && \ + (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ + { \ + status = NV_ERR_GPU_NOT_FULL_POWER; \ + goto tag; \ + } \ + } \ + if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ } diff --git a/src/nvidia/inc/kernel/core/thread_state.h b/src/nvidia/inc/kernel/core/thread_state.h index 6567989fe4..27d0880a95 100644 --- a/src/nvidia/inc/kernel/core/thread_state.h +++ b/src/nvidia/inc/kernel/core/thread_state.h @@ -149,7 +149,7 @@ typedef struct THREAD_STATE_DB // // The normal power transition requirement for Windows is 4 seconds. -// Use longer time to let OS fire timeout and ask recovery. +// Use longer time to let OS fire timeout and ask recovery. // #define TIMEOUT_WDDM_POWER_TRANSITION_INTERVAL_MS 9800 @@ -207,7 +207,7 @@ NV_STATUS threadStateInitTimeout(OBJGPU *pGpu, NvU32 timeoutUs, NvU32 flags); NV_STATUS threadStateCheckTimeout(OBJGPU *pGpu, NvU64 *pElapsedTimeUs); NV_STATUS threadStateResetTimeout(OBJGPU *pGpu); void threadStateLogTimeout(OBJGPU *pGpu, NvU64 funcAddr, NvU32 lineNum); -void threadStateYieldCpuIfNecessary(OBJGPU *pGpu); +void threadStateYieldCpuIfNecessary(OBJGPU *pGpu, NvBool bQuiet); void threadStateSetTimeoutOverride(THREAD_STATE_NODE *, NvU64); NV_STATUS threadStateEnqueueCallbackOnFree(THREAD_STATE_NODE *pThreadNode, diff --git a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h index 3804fe7747..cc843e8b6e 100644 --- a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h +++ b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h @@ -39,7 +39,7 @@ * @return NV_OK if the conversion is successful. */ static NV_INLINE -NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, RM_ENGINE_TYPE rmEngineType, NvU32 *ceIdx) +NV_STATUS ceIndexFromType(OBJGPU *pGpu, Device *pDevice, RM_ENGINE_TYPE rmEngineType, NvU32 *ceIdx) { NV_STATUS status = NV_OK; RM_ENGINE_TYPE localRmEngType = rmEngineType; @@ -56,7 +56,7 @@ NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, RM_ENGINE_TYPE rmEngin KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); if (status != NV_OK) return status; diff --git a/src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h b/src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h new file mode 100644 index 0000000000..75b9be876e --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h @@ -0,0 +1,224 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CCSL_H +#define CCSL_H + +#include "nvstatus.h" +#include "nvmisc.h" +#include "kernel/gpu/conf_compute/conf_compute.h" + +typedef struct ccslContext_t *pCcslContext; + +/* + * Initializes a context by providing client and channel information. + * + * ccslContext [in / out] + * hClient [in] + * hChannel [in] + */ +NV_STATUS +ccslContextInitViaChannel +( + pCcslContext *ppCtx, + NvHandle hClient, + NvHandle hChannel +); + +/* + * Initializes a context by providing key ID information. + * + * ConfidentialCompute [in] + * ccslContext [in / out] + * globalKeyId [in] + */ +NV_STATUS +ccslContextInitViaKeyId +( + ConfidentialCompute *pConfCompute, + pCcslContext *ppCtx, + NvU32 globalKeyId +); + +/* + * Clears the context and erases sensitive material such as keys. + * + * ccslContext [in / out] + */ +void +ccslContextClear +( + pCcslContext ctx +); + +/* To be called before library client triggers a Device-side encryption. + * Attempts to increment the library's Device-side message counter and returns an error if it will overflow. + * + * ccslContext [in] + * decryptIv [in] + * + * Returns NV_ERR_INSUFFICIENT_RESOURCES if the next Device-side encryption will overflow. + * Returns NV_OK otherwise. + */ +NV_STATUS +ccslLogDeviceEncryption +( + pCcslContext ctx, + NvU8 *decryptIv +); + +/* Request the next IV to be used in encryption. Storing it explicitly enables the caller + * to perform encryption out of order using EncryptWithIv + * + * ccslContext [in / out] + * encryptIv [out] + * + * Returns NV_ERR_INSUFFICIENT_RESOURCES if the next encryption will overflow. + * Returns NV_OK otherwise. + */ +NV_STATUS +ccslAcquireEncryptionIv +( + pCcslContext ctx, + NvU8 *encryptIv +); + +/* Rotate the IV for the given direction. + * + * ccslContext [in / out] + * direction [in] + */ +NV_STATUS +ccslRotateIv +( + pCcslContext ctx, + NvU8 direction +); + +/* + * Encrypt and sign data using provided IV + * + * ccslContext [in] + * bufferSize [in] - Size of buffer to be encrypted in units of bytes. + * inputBuffer [in] - Address of plaintext input buffer. For performance it should be 16-byte aligned. + * encryptionIv [in/out] - IV to use for encryption. The IV will be "dirtied" after this operation. + * outputBuffer [in/out] - Address of ciphertext output buffer. + * authTagBuffer [in/out] - Address of authentication tag. In APM it is 32 bytes. In HCC it is 16 bytes. + * + * Returns NV_OK. + */ +NV_STATUS +ccslEncryptWithIv +( + pCcslContext ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer +); + +/* + * If message counter will not overflow then encrypt and sign data. + * + * ccslContext [in] + * bufferSize [in] - Size of buffer to be encrypted in units of bytes. + * inputBuffer [in] - Address of plaintext input buffer. For performance it should be 16-byte aligned. + * outputBuffer [in/out] - Address of ciphertext output buffer. + * authTagBuffer [in/out] - Address of authentication tag. In APM it is 32 bytes. In HCC it is 16 bytes. + * + * Returns NV_ERR_INSUFFICIENT_RESOURCES if message counter will overflow. + * Returns NV_OK otherwise. + */ +NV_STATUS +ccslEncrypt +( + pCcslContext ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagBuffer +); + +/* + * First verify authentication tag. If authentication passes then the data is decrypted. + * + * ccslContext [in] + * bufferSize [in] - Size of buffer to be decrypted in units of bytes. + * inputBuffer [in] - Address of ciphertext input buffer. For performance it should be 16-byte aligned. + * outputBuffer [in/out] - Address of plaintext output buffer. + * authTagBuffer [in] - Address of authentication tag. In APM it is 32 bytes. In HCC it is 16 bytes. + * + * Returns NV_ERR_INVALID_DATA if verification of the authentication tag fails. + * Returns NV_OK otherwise. + */ +NV_STATUS +ccslDecrypt +( + pCcslContext ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *authTagBuffer +); + +/* + * Sign the plaintext message. + * + * ccslContext [in] + * bufferSize [in] - Size of buffer to be signed in units of bytes. + * inputBuffer [in] - Address of input buffer. For performance it should be 16-byte aligned. + * authTagBuffer [in/out] - Address of authentication tag. In HCC it is 32 bytes. + * + * Returns NV_OK + */ +NV_STATUS +ccslSign +( + pCcslContext ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer +); + +#define CCSL_DIR_HOST_TO_DEVICE 0 +#define CCSL_DIR_DEVICE_TO_HOST 1 + +/* + * Returns the number of messages that can be encrypted by the CPU (CCSL_DIR_HOST_TO_DEVICE) + * or encrypted by the GPU (CCSL_DIR_DEVICE_TO_HOST) before the message counter will overflow. + * + * ccslContext [in] + * direction [in] - Either CCSL_DIR_HOST_TO_DEVICE or CCSL_DIR_DEVICE_TO_HOST. + * messageNum [out] - Number of messages that can be encrypted before overflow. + */ +NV_STATUS +ccslQueryMessagePool +( + pCcslContext ctx, + NvU8 direction, + NvU64 *messageNum +); + +#endif // CCSL_H diff --git a/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute.h b/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute.h new file mode 100644 index 0000000000..3d607f8373 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute.h @@ -0,0 +1,3 @@ + +#include "g_conf_compute_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_api.h b/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_api.h new file mode 100644 index 0000000000..d6c030d4b5 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_api.h @@ -0,0 +1,3 @@ + +#include "g_conf_compute_api_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h b/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h new file mode 100644 index 0000000000..b7741b784d --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CONF_COMPUTE_KEYSTORE_H +#define CONF_COMPUTE_KEYSTORE_H + +#include "nvtypes.h" +#include "nvstatus.h" +#include "cc_drv.h" +#include "kernel/gpu/fifo/kernel_channel.h" + +// Named values for ccKeyStoreDeposit()'s slotNumber parameter. +#define KEYSTORE_SLOT_GSP 0 +#define KEYSTORE_SLOT_SEC2 1 +// LCE index can range from 0 to 7 inclusive. +#define KEYSTORE_SLOT_LCE_UMD(index) (2 + (index) * 3) +#define KEYSTORE_SLOT_LCE_KMD(index) (3 + (index) * 3) +#define KEYSTORE_SLOT_LCE_MGPU(index) (4 + (index) * 3) + +/*! + * @brief Initialize the keystore. + * + * @param[in] pGpu Pointer to GPU object. + * + * @return NV_ERR_INVALID_STATE if system is not in Confidential Compute mode. + */ +NV_STATUS +ccKeyStoreInit (OBJGPU *pGpu); + +/*! + * @brief Deposits a KMB into a keystore slot. + * + * @param[in] slotNumber Slot number into which the KMB will be deposited. + * @param[in] keyMaterialBundle Pair of key / IV / IV mask tuples. IV will be set to 0 by function. + * + * @return NV_ERR_INVALID_INDEX if slotNumber is illegal, NV_OK otherwise. + */ +NV_STATUS +ccKeyStoreDeposit +( + NvU32 slotNumber, + CC_KMB keyMaterialBundle +); + +/*! + * @brief Retrieves a KMB based on the channel. The keystore uses channel + information such as engine type and the associated privilege mode + to determine which KMB to fetch. + * The IV's channel counter for the given direction is pre-incremented. + * + * @param[in] pKernelChannel + * @param[in] rotateOperation Either: + ROTATE_IV_ENCRYPT + ROTATE_IV_DECRYPT + ROTATE_IV_ALL_VALID + * @param[out] keyMaterialBundle The KMB for the given channel. + * + * @return NV_ERR_INSUFFICIENT_RESOURCES if channel counter overflow would occur. + NV_ERR_GENERIC for other errors. + * NV_OK otherwise. + */ +NV_STATUS +ccKeyStoreRetrieveViaChannel +( + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + PCC_KMB keyMaterialBundle +); + +/*! + * @brief Clears the contents of the keystore. + */ +void +cckeyStoreClear (void); + +#endif // CONF_COMPUTE_KEYSTORE_H diff --git a/src/nvidia/inc/kernel/gpu/falcon/falcon_common.h b/src/nvidia/inc/kernel/gpu/falcon/falcon_common.h index 63b5ca42ee..239bac7790 100644 --- a/src/nvidia/inc/kernel/gpu/falcon/falcon_common.h +++ b/src/nvidia/inc/kernel/gpu/falcon/falcon_common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-202 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -58,4 +58,9 @@ */ #define FLCN_CTX_ENG_BUFFER_SIZE_HW 4096 +/*! + * Number of register read needed for reset signal propagation + */ +#define FLCN_RESET_PROPAGATION_DELAY_COUNT 10 + #endif // FALCON_COMMON_H diff --git a/src/nvidia/inc/kernel/gpu/gpu_child_class_defs.h b/src/nvidia/inc/kernel/gpu/gpu_child_class_defs.h new file mode 100644 index 0000000000..aa069eaa05 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gpu_child_class_defs.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GPU_CHILD_CLASS_DEFS_H +#define GPU_CHILD_CLASS_DEFS_H + +/*! + * @file + * @details Provides the class definitions for every GPU child class without the + * need to include every individual header. + */ + +#include "core/prelude.h" + +#define GPU_CHILD_CLASS_DEFS_GPU_CHILD(className, accessorName, numInstances, bConstructEarly, gpuField) \ + extern const struct NVOC_CLASS_DEF NV_CONCATENATE(__nvoc_class_def_, className); + +#define GPU_CHILD \ + GPU_CHILD_CLASS_DEFS_GPU_CHILD +#include "gpu/gpu_child_list.h" + +// Sub-classes of GPU children +// Pmu sub-classes +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Pmu10; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Pmu20; + +#endif // GPU_CHILD_CLASS_DEFS_H diff --git a/src/nvidia/inc/kernel/gpu/gpu_child_list.h b/src/nvidia/inc/kernel/gpu/gpu_child_list.h index 73ec4aa0f7..13ac242d72 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_child_list.h +++ b/src/nvidia/inc/kernel/gpu/gpu_child_list.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -105,12 +105,12 @@ #if GPU_CHILD_MODULE(KERNEL_DISPLAY) GPU_CHILD_SINGLE_INST( KernelDisplay, GPU_GET_KERNEL_DISPLAY, 1, NV_FALSE, pKernelDisplay ) #endif -#if GPU_CHILD_MODULE(DISP) - GPU_CHILD_SINGLE_INST( OBJDISP, GPU_GET_DISP, 1, NV_FALSE, pDisp ) -#endif #if GPU_CHILD_MODULE(TMR) GPU_CHILD_SINGLE_INST( OBJTMR, GPU_GET_TIMER, 1, NV_TRUE, pTmr ) #endif +#if GPU_CHILD_MODULE(DISP) + GPU_CHILD_SINGLE_INST( OBJDISP, GPU_GET_DISP, 1, NV_FALSE, pDisp ) +#endif #if GPU_CHILD_MODULE(BUS) GPU_CHILD_SINGLE_INST( OBJBUS, GPU_GET_BUS, 1, NV_FALSE, pBus ) #endif @@ -297,8 +297,11 @@ #if GPU_CHILD_MODULE(OFA) GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, pOfa ) #endif +#if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE) + GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute ) +#endif #if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU) - GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, pKernelCcu ) + GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, pKernelCcu ) #endif // Undefine the entry macros to simplify call sites diff --git a/src/nvidia/inc/kernel/gpu/gpu_engine_type.h b/src/nvidia/inc/kernel/gpu/gpu_engine_type.h index d91daab953..39030a8280 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_engine_type.h +++ b/src/nvidia/inc/kernel/gpu/gpu_engine_type.h @@ -99,6 +99,7 @@ typedef enum #define RM_ENGINE_TYPE_NVENC_SIZE 3 #define RM_ENGINE_TYPE_NVJPEG_SIZE 8 #define RM_ENGINE_TYPE_NVDEC_SIZE 8 +#define RM_ENGINE_TYPE_OFA_SIZE 1 #define RM_ENGINE_TYPE_GR_SIZE 8 // Indexed engines @@ -118,6 +119,15 @@ typedef enum #define RM_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= RM_ENGINE_TYPE_NVJPEG0) && ((i) < RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE))) #define RM_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - RM_ENGINE_TYPE_NVJPEG0) +#define RM_ENGINE_TYPE_OFA(i) (RM_ENGINE_TYPE_OFA+(i)) +#define RM_ENGINE_TYPE_IS_OFA(i) (((i) >= RM_ENGINE_TYPE_OFA) && ((i) < RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE))) +#define RM_ENGINE_TYPE_OFA_IDX(i) ((i) - RM_ENGINE_TYPE_OFA) + +#define RM_ENGINE_TYPE_IS_VIDEO(i) (RM_ENGINE_TYPE_IS_NVENC(i) | \ + RM_ENGINE_TYPE_IS_NVDEC(i) | \ + RM_ENGINE_TYPE_IS_NVJPEG(i) | \ + RM_ENGINE_TYPE_IS_OFA(i)) + #define RM_ENGINE_TYPE_GR(i) (RM_ENGINE_TYPE_GR0 + (i)) #define RM_ENGINE_TYPE_IS_GR(i) (((i) >= RM_ENGINE_TYPE_GR0) && ((i) < RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE))) #define RM_ENGINE_TYPE_GR_IDX(i) ((i) - RM_ENGINE_TYPE_GR0) diff --git a/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h b/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h index 880355394b..79642b3ee8 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h +++ b/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -33,28 +33,31 @@ #define GPU_FABRIC_PROBE_DEFAULT_PROBE_SLOWDOWN_THRESHOLD 10 -typedef struct GPU_FABRIC_PROBE_INFO GPU_FABRIC_PROBE_INFO; +typedef struct GPU_FABRIC_PROBE_INFO_KERNEL GPU_FABRIC_PROBE_INFO_KERNEL; NV_STATUS gpuFabricProbeStart(OBJGPU *pGpu, - GPU_FABRIC_PROBE_INFO **ppGpuFabricProbeInfo); -void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); - -void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); -NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); - -NV_STATUS gpuFabricProbeGetGpuFabricHandle(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pHandle); -NV_STATUS gpuFabricProbeGetGfId(GPU_FABRIC_PROBE_INFO *pInfo, NvU32 *pGfId); -NV_STATUS gpuFabricProbeGetfmCaps(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFmCaps); -NV_STATUS gpuFabricProbeGetClusterUuid(GPU_FABRIC_PROBE_INFO *pInfo, NvUuid *pClusterUuid); -NV_STATUS gpuFabricProbeGetFabricPartitionId(GPU_FABRIC_PROBE_INFO *pInfo, NvU16 *pFabricPartitionId); -NV_STATUS gpuFabricProbeGetGpaAddress(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pGpaAddress); -NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pGpaAddressRange); -NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFlaAddress); -NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFlaAddressRange); -NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *numProbes); - -NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); -NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); -NV_STATUS gpuFabricProbeGetFmStatus(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); + GPU_FABRIC_PROBE_INFO_KERNEL **ppGpuFabricProbeInfoKernel); +void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); + +void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); +NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); + +NV_STATUS gpuFabricProbeGetGpuFabricHandle(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pHandle); +NV_STATUS gpuFabricProbeGetGfId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pGfId); +NV_STATUS gpuFabricProbeGetfmCaps(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFmCaps); +NV_STATUS gpuFabricProbeGetClusterUuid(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvUuid *pClusterUuid); +NV_STATUS gpuFabricProbeGetFabricPartitionId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU16 *pFabricPartitionId); +NV_STATUS gpuFabricProbeGetGpaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pGpaAddress); +NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pGpaAddressRange); +NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddress); +NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddressRange); +NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes); + +NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); +NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); +NV_STATUS gpuFabricProbeGetFmStatus(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); NvBool gpuFabricProbeIsSupported(OBJGPU *pGpu); +NV_STATUS gpuFabricProbeSetBwMode(NvU8 mode); +NV_STATUS gpuFabricProbeGetlinkMaskToBeReduced(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, + NvU32 *linkMaskToBeReduced); #endif // GPU_FABRIC_PROBE_H diff --git a/src/nvidia/inc/kernel/gpu/gpu_timeout.h b/src/nvidia/inc/kernel/gpu/gpu_timeout.h index 037602b31a..315d8802ca 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_timeout.h +++ b/src/nvidia/inc/kernel/gpu/gpu_timeout.h @@ -139,6 +139,10 @@ static NV_INLINE NvU32 timeoutApplyScale(TIMEOUT_DATA *pTD, NvU32 timeout) #define gpuScaleTimeout(g,a) timeoutApplyScale(&(g)->timeoutData, a) #define gpuTimeoutCondWait(g,a,b,t) timeoutCondWait(&(g)->timeoutData, t, a, b, __LINE__) -#define GPU_ENG_RESET_TIMEOUT_VALUE(g, t) (t) +// +// In SCSIM simulation platform, both CPU and GPU are simulated and the reg write/read itself +// takes more time. This helper macro handles it with increased timeout value. +// +#define GPU_ENG_RESET_TIMEOUT_VALUE(g, t) ((gpuIsSelfHosted(g) && IS_SIMULATION(g)) ? 1000 : (t)) #endif // _GPU_TIMEOUT_H_ diff --git a/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h b/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h index 60ed630f14..3fda944adb 100644 --- a/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h +++ b/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h @@ -34,7 +34,7 @@ * * Not all buffer types are supported on every GPU. */ -#define GR_GLOBALCTX_BUFFER_DEF(x) \ +#define GR_GLOBALCTX_BUFFER_DEF(x) \ NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_BUNDLE_CB, 0x00000000) \ NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_PAGEPOOL, 0x00000001) \ NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB, 0x00000002) \ @@ -50,7 +50,7 @@ NV_ENUM_DEF(GR_GLOBALCTX_BUFFER, GR_GLOBALCTX_BUFFER_DEF) #define GR_GLOBALCTX_BUFFER_COUNT NV_ENUM_SIZE(GR_GLOBALCTX_BUFFER) -#define GR_CTX_BUFFER_DEF(x) \ +#define GR_CTX_BUFFER_DEF(x) \ NV_ENUM_ENTRY(x, GR_CTX_BUFFER_MAIN, 0x00000000) \ NV_ENUM_ENTRY(x, GR_CTX_BUFFER_ZCULL, 0x00000001) \ NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PM, 0x00000002) \ diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h index 11d2ec2202..57538db5af 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,8 +25,55 @@ #define GSP_FW_HEAP_H // Static defines for the GSP FW WPR Heap -#define GSP_FW_HEAP_SIZE_LIBOS2 (64u << 20) -#define GSP_FW_HEAP_SIZE_LIBOS3_BAREMETAL (84u << 20) -#define GSP_FW_HEAP_SIZE_LIBOS3_VGPU (549u << 20) +#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2 (0 << 20) // No FB heap usage +#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3 (20 << 20) + +// +// Calibrated by observing RM init heap usage - the amount of GSP-RM heap memory +// used during GSP-RM boot and Kernel RM initialization, up to and including the +// first client subdevice allocation. +// +#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X (8 << 20) // Turing thru Ada +#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100 (14 << 20) // Hopper+ + +// +// Calibrated by observing RM init heap usage on GPUs with various FB sizes. +// This seems to fit the data fairly well, but is likely inaccurate (differences +// in heap usage are more likely correlate with GPU architecture than FB size). +// TODO: this requires more detailed profiling and tuning. +// +#define GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB (96 << 10) // All architectures + +// +// This number is calibrated by profiling the WPR heap usage of a single +// client channel allocation. In practice, channel allocations on newer +// architectures are around 44KB-46KB (depending on internal memory +// tracking overhead configured in GSP-RM). +// +// Note: Turing supports 4096 channels vs 2048 on Ampere+, but the heap is +// sized to support only 2048 channels - otherwise the Turing heap balloons +// to 176MB+ on already small-FB parts. +// +// Note: The 2048 channel limit is per-runlist. GSP-RM currently uses only +// a single ChID space across all engines, because per-runlist channel RAM is +// disabled by default in most configurations. If/once per-runlist ChID spaces +// are used on GSP-RM, this will likely no longer be sufficient/relevant as +// the memory that could be needed for client channel allocations will far +// exceed the amount we can carve out for GSP-RM's heap (max ChID will no longer +// be the limiter). +// +#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE ((48 << 10) * 2048) // Support 2048 channels + +#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (549 << 20) // Default for all VGPU configs + +// Min/max bounds for heap size override by regkey +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB (64u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB (256u) + +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (84u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (276u) + +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (549u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1024u) #endif // GSP_FW_HEAP_H diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h index 6e27a7e4b4..7f22383d95 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h @@ -53,6 +53,12 @@ typedef struct MESSAGE_QUEUE_INIT_ARGUMENTS messageQueueInitArguments; GSP_SR_INIT_ARGUMENTS srInitArguments; NvU32 gpuInstance; + + struct + { + NvU64 pa; + NvU64 size; + } profilerArgs; } GSP_ARGUMENTS_CACHED; #endif // GSP_INIT_ARGS_H diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h index a1e625204f..fea2a47b4c 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -75,7 +75,7 @@ typedef struct GspStaticConfigInfo_t GspSMInfo SM_info; NvBool poisonFuseEnabled; - + NvU64 fb_length; NvU32 fbio_mask; NvU32 fb_bus_width; @@ -100,6 +100,7 @@ typedef struct GspStaticConfigInfo_t NvBool bIsMobile; NvBool bIsGc6Rtd3Allowed; NvBool bIsGcOffRtd3Allowed; + NvBool bIsGcoffLegacyAllowed; NvU64 bar1PdeBase; NvU64 bar2PdeBase; @@ -127,7 +128,10 @@ typedef struct GspStaticConfigInfo_t // Subdevice handle for internal RMAPI control. NvHandle hInternalSubdevice; + NvBool bSelfHostedMode; NvBool bAtsSupported; + + NvBool bIsGpuUefi; } GspStaticConfigInfo; // Pushed from CPU-RM to GSP-RM @@ -147,6 +151,7 @@ typedef struct GspSystemInfo NvU64 clPdbProperties; NvU32 Chipset; NvBool bGpuBehindBridge; + NvBool bMnocAvailable; NvBool bUpstreamL0sUnsupported; NvBool bUpstreamL1Unsupported; NvBool bUpstreamL1PorSupported; @@ -155,6 +160,9 @@ typedef struct GspSystemInfo BUSINFO FHBBusInfo; BUSINFO chipsetIDInfo; ACPI_METHOD_DATA acpiMethodData; + NvU32 hypervisorType; + NvBool bIsPassthru; + NvU64 sysTimerOffsetNs; } GspSystemInfo; diff --git a/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h b/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h index 4319e71c6b..e2d0861845 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h +++ b/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h @@ -65,6 +65,7 @@ typedef struct _message_queue_info msgqHandle hQueue; // Do not allow requests when hQueue is null. NvU32 txSeqNum; // Next sequence number for tx. NvU32 rxSeqNum; // Next sequence number for rx. + NvU32 txBufferFull; NvU32 queueIdx; // QueueIndex used to identify which task the message is supposed to be sent to. } MESSAGE_QUEUE_INFO; diff --git a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h index 1490585d59..f8e1e5b3c2 100644 --- a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h +++ b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -61,6 +61,7 @@ #define MC_ENGINE_IDX_CE7 22 #define MC_ENGINE_IDX_CE8 23 #define MC_ENGINE_IDX_CE9 24 +#define MC_ENGINE_IDX_CE_MAX MC_ENGINE_IDX_CE9 #define MC_ENGINE_IDX_VIC 35 #define MC_ENGINE_IDX_ISOHUB 36 #define MC_ENGINE_IDX_VGPU 37 @@ -136,7 +137,8 @@ #define MC_ENGINE_IDX_DISP_GSP 163 #define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 164 #define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 165 -#define MC_ENGINE_IDX_MAX 166 // This must be kept as the max bit if +#define MC_ENGINE_IDX_PXUC 166 +#define MC_ENGINE_IDX_MAX 167 // This must be kept as the max bit if // we need to add more engines #define MC_ENGINE_IDX_INVALID 0xFFFFFFFF @@ -159,6 +161,9 @@ // Index ESCHED reference #define MC_ENGINE_IDX_ESCHEDn(x) (MC_ENGINE_IDX_ESCHED + (x)) +#define MC_ENGINE_IDX_IS_CE(x) \ + ((MC_ENGINE_IDX_CE(0) <= (x)) && ((x) <= MC_ENGINE_IDX_CE_MAX)) + MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX); typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR; diff --git a/src/nvidia/inc/kernel/gpu/intr/intr_common.h b/src/nvidia/inc/kernel/gpu/intr/intr_common.h new file mode 100644 index 0000000000..877e5ac9e0 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/intr/intr_common.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef INTR_COMMON_H +#define INTR_COMMON_H 1 +/*! Common defines used by both Intr and OBJINTRABLE */ + + +/*! Kinds of interrupts that a unit can have. */ +typedef enum { + /*! + * Legacy concept of "stalling" interrupts. + * + * These may have a RETRIGGER mechanism. + */ + INTR_KIND_INTERRUPT, + /*! Notification "non-stalling" interrupts. */ + INTR_KIND_NOTIFICATION, + INTR_KIND_COUNT +} INTR_KIND; + + +#endif /* ifndef INTR_COMMON_H */ diff --git a/src/nvidia/inc/kernel/gpu/kern_gpu_power.h b/src/nvidia/inc/kernel/gpu/kern_gpu_power.h new file mode 100644 index 0000000000..bb5fc742fb --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/kern_gpu_power.h @@ -0,0 +1,92 @@ + /* + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef KERN_GPU_POWER_H +#define KERN_GPU_POWER_H + +#include "ctrl/ctrl2080/ctrl2080power.h" // NV2080_CTRL_GC6_FLAVOR_ID_MAX +#include "diagnostics/profiler.h" + +typedef enum +{ + GPU_GC6_STATE_POWERED_ON = 0 , + GPU_GC6_STATE_EXITED = GPU_GC6_STATE_POWERED_ON , + GPU_GC6_STATE_ENTERING , + GPU_GC6_STATE_ENTERING_FAILED , + GPU_GC6_STATE_ENTERED , + GPU_GC6_STATE_EXITING , + GPU_GC6_STATE_EXITING_FAILED , +} GPU_GC6_STATE; + +// TODO-SC use mask for the bool variables +typedef struct +{ + GPU_GC6_STATE currentState; + NvU32 executedStepMask; // step mask executed during entry sequence + NvU32 stepMask[NV2080_CTRL_GC6_FLAVOR_ID_MAX]; // step mask cache +} _GPU_GC6_STATE; + +// GPU event mask operation +#define GC6_REFCOUNT_MASK_SET(pGpu, refCountBit) \ + do \ + { \ + if (pGpu != NULL) \ + { \ + ((pGpu->gc6State.refCountMask) |= (NVBIT(refCountBit))); \ + } \ + } while(0) + +#define GC6_REFCOUNT_MASK_CLEAR(pGpu, refCountBit) \ + do \ + { \ + if (pGpu != NULL) \ + { \ + ((pGpu->gc6State.refCountMask) &= ~(NVBIT(refCountBit))); \ + } \ + } while(0) + +#define GC6_REFCOUNT_MASK_GET_FROM_EVENT(event) ((event / 2)) + +// GC6 related defines +#define GC6_FB_CLAMP_TIMEOUT_MS 10 + +// Macros for GPU_GC6_STATE +#define IS_GPU_GC6_STATE_POWERED_ON(obj) (obj->gc6State.currentState == GPU_GC6_STATE_POWERED_ON) +#define IS_GPU_GC6_STATE_EXITED(obj) (obj->gc6State.currentState == GPU_GC6_STATE_EXITED) +#define IS_GPU_GC6_STATE_ENTERING(obj) (obj->gc6State.currentState == GPU_GC6_STATE_ENTERING) +#define IS_GPU_GC6_STATE_ENTERED(obj) (obj->gc6State.currentState == GPU_GC6_STATE_ENTERED) +#define IS_GPU_GC6_STATE_EXITING(obj) (obj->gc6State.currentState == GPU_GC6_STATE_EXITING) + +#define SET_GPU_GC6_STATE(obj, state) (obj->gc6State.currentState = state) +#define SET_GPU_GC6_STATE_AND_LOG(obj, state) \ + do { \ + SET_GPU_GC6_STATE(obj, state); \ + RMTRACE_GPU(_GC6_STATE, obj->gpuId, state, 0, 0, 0, 0, 0, 0); \ + } while(0) + +//Macro to check is a given GC6 step id is set +#define GPU_IS_GC6_STEP_ID_SET(stepId, stepMask) \ + ((NVBIT(NV2080_CTRL_GC6_STEP_ID_##stepId) & (stepMask)) != 0) + + +#endif // KERN_GPU_POWER_H diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h b/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h new file mode 100644 index 0000000000..b1eb84f774 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_ce_utils_nvoc.h" + +#ifndef CE_UTILS_H +#define CE_UTILS_H + +#include "gpu/gpu_resource.h" // GpuResource +#include "class/cl0050.h" +#include "ctrl/ctrl0050.h" + +#include "kernel/gpu/mem_mgr/channel_utils.h" + +typedef struct +{ + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 offset; + NvU64 length; + NvU32 pattern; + NvU64 flags; + NvU64 submittedWorkId; // Payload to poll for async completion +} CEUTILS_MEMSET_PARAMS; + +typedef struct +{ + MEMORY_DESCRIPTOR *pSrcMemDesc; + MEMORY_DESCRIPTOR *pDstMemDesc; + NvU64 dstOffset; + NvU64 srcOffset; + NvU64 length; + NvU64 flags; + NvU64 submittedWorkId; // Payload to poll for async completion +} CEUTILS_MEMCOPY_PARAMS; + + +NVOC_PREFIX(ceutils) class CeUtils : Object +{ +public: + NV_STATUS ceutilsConstruct(CeUtils *pCeUtils, OBJGPU *pGpu, NV0050_ALLOCATION_PARAMETERS *pAllocParams); + + void ceutilsDestruct(CeUtils *pCeUtils); + + NV_STATUS ceutilsInitialize(CeUtils *pCeUtils, OBJGPU *pGpu, NV0050_ALLOCATION_PARAMETERS *pAllocParams); + void ceutilsDeinit(CeUtils *pCeUtils); + void ceutilsRegisterGPUInstance(CeUtils *pCeUtils, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance); + + NV_STATUS ceutilsMemset(CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams); + NV_STATUS ceutilsMemcopy(CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams); + + NvU64 ceutilsUpdateProgress(CeUtils *pCeUtils); + void ceutilsServiceInterrupts(CeUtils *pCeUtils); + + // + // Internal states + // + + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + + OBJCHANNEL *pChannel; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance; + OBJGPU *pGpu; + + KernelCE *pKCe; + NvBool bUseVasForCeCopy; + NvU32 hTdCopyClass; + NvU64 lastSubmittedPayload; + NvU64 lastCompletedPayload; +}; + + +#if defined(DEBUG) || defined (DEVELOP) +NVOC_PREFIX(ceutilsapi) class CeUtilsApi : GpuResource +{ +public: + NV_STATUS ceutilsapiConstruct(CeUtilsApi *pCeUtilsApi, CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams) + : GpuResource(pCallContext, pParams); + + void ceutilsapiDestruct(CeUtilsApi *pCeUtilsApi); + + // + // Below APIs are only provided for SRT testing, thus only available for debug or + // develop driver builds + // + // + RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMSET, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdMemset(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams); + + RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMCOPY, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdMemcopy(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams); + + RMCTRL_EXPORT(NV0050_CTRL_CMD_CHECK_PROGRESS, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) + NV_STATUS ceutilsapiCtrlCmdCheckProgress(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams); + + CeUtils *pCeUtils; +}; +#endif + +#endif // CE_UTILS_H diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h b/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h new file mode 100644 index 0000000000..be132334b7 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CE_UTILS_SIZES_H +#define _CE_UTILS_SIZES_H + +#define CE_MAX_BYTES_PER_LINE 0xffffffffULL +#define CE_NUM_COPY_BLOCKS 4096 +#define CE_CHANNEL_SEMAPHORE_SIZE 8 +#define CE_GPFIFO_SIZE NV906F_GP_ENTRY__SIZE * CE_NUM_COPY_BLOCKS +#define CE_CHANNEL_NOTIFIER_SIZE (sizeof(NvNotification) * \ + NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1) +#define CE_METHOD_SIZE_PER_BLOCK 0x64 +#define FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK 0x78 + +#endif // _CE_UTILS_SIZES_H diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h b/src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h new file mode 100644 index 0000000000..11f9f04089 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h @@ -0,0 +1,157 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CHANNEL_UTILS_H_ +#define _CHANNEL_UTILS_H_ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/ce/kernel_ce.h" +#include "gpu/bus/kern_bus.h" +#include "core/prelude.h" +#include "rmapi/rs_utils.h" +#include "nvos.h" + +#include "class/cl906f.h" +#include "class/cl906f.h" +#include "class/cl906fsw.h" + +#include "class/clb0b5.h" // MAXWELL_DMA_COPY_A +#include "class/clc0b5.h" // PASCAL_DMA_COPY_A +#include "class/clc1b5.h" // PASCAL_DMA_COPY_B +#include "class/clc3b5.h" // VOLTA_DMA_COPY_A +#include "class/clc5b5.h" // TURING_DMA_COPY_A +#include "class/clc6b5.h" // AMPERE_DMA_COPY_A +#include "class/clc7b5.h" // AMPERE_DMA_COPY_B + +#include "class/clc8b5.h" // HOPPER_DMA_COPY_A + +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A + +#include "nvctassert.h" +#include "vgpu/vgpu_guest_pma_scrubber.h" + +#define RM_SUBCHANNEL 0x0 + +#define NV_PUSH_METHOD(OpType, SubCh, Method, Count) \ + (DRF_DEF(906F, _DMA, _SEC_OP, OpType) | \ + DRF_NUM(906F, _DMA, _METHOD_ADDRESS, (Method) >> 2) | \ + DRF_NUM(906F, _DMA, _METHOD_SUBCHANNEL, (SubCh)) | \ + DRF_NUM(906F, _DMA, _METHOD_COUNT, (Count))) + +#define _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2) NV_ASSERT((a2) - (a1) == 4) + +#define NV_PUSH_DATA(Data) MEM_WR32(pPtr++, (Data)) + +#define _NV_PUSH_INC_1U(SubCh, a1, d1, Count) \ + do \ + { \ + NV_PUSH_DATA(NV_PUSH_METHOD(_INC_METHOD, SubCh, a1, Count)); \ + NV_PUSH_DATA(d1); \ + } while (0) + +#define NV_PUSH_INC_1U(SubCh, a1, d1) \ + do \ + { \ + _NV_PUSH_INC_1U (SubCh, a1, d1, 1); \ + } while (0) + +#define NV_PUSH_INC_2U(SubCh, a1, d1, a2, d2) \ + do \ + { \ + _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \ + _NV_PUSH_INC_1U(SubCh, a1, d1, 2); \ + NV_PUSH_DATA(d2); \ + } while (0) + +#define NV_PUSH_INC_3U(SubCh, a1, d1, a2, d2, a3, d3) \ + do \ + { \ + _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \ + _NV_ASSERT_CONTIGUOUS_METHOD(a2, a3); \ + _NV_PUSH_INC_1U(SubCh, a1, d1, 3); \ + NV_PUSH_DATA(d2); \ + NV_PUSH_DATA(d3); \ + } while (0) + +#define NV_PUSH_INC_4U(SubCh, a1, d1, a2, d2, a3, d3, a4, d4) \ + do \ + { \ + _NV_ASSERT_CONTIGUOUS_METHOD(a1, a2); \ + _NV_ASSERT_CONTIGUOUS_METHOD(a2, a3); \ + _NV_ASSERT_CONTIGUOUS_METHOD(a3, a4); \ + _NV_PUSH_INC_1U(SubCh, a1, d1, 4); \ + NV_PUSH_DATA(d2); \ + NV_PUSH_DATA(d3); \ + NV_PUSH_DATA(d4); \ + } while (0) + +#define READ_CHANNEL_PAYLOAD_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA + \ + channel->finishPayloadOffset) + +#define READ_CHANNEL_PB_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA + \ + channel->semaOffset) + +#define WRITE_CHANNEL_PB_SEMA(channel, val) MEM_WR32((NvU8*)channel->pbCpuVA + \ + channel->semaOffset, val); + +#define WRITE_CHANNEL_PAYLOAD_SEMA(channel,val) MEM_WR32((NvU8*)channel->pbCpuVA + \ + channel->finishPayloadOffset, val); + +// +// This struct contains parameters needed to send a pushbuffer for a CE +// operation. This interface only supports contiguous operations. +// +typedef struct +{ + NvBool bCeMemcopy; // Whether this is a CE memcopy; + // If set to false, this will be a memset operation + NvU64 dstAddr; // Physical address of the source address + NvU64 srcAddr; // Physical address of the source address; only valid for memcopy + NvU32 size; + NvU32 pattern; // Fixed pattern to memset to. Only valid for memset + NvU32 payload; // Payload value used to release semaphore + NvU64 clientSemaAddr; + NV_ADDRESS_SPACE dstAddressSpace; + NV_ADDRESS_SPACE srcAddressSpace; + NvU32 dstCpuCacheAttrib; + NvU32 srcCpuCacheAttrib; +} CHANNEL_PB_INFO; + +NV_STATUS channelSetupIDs(OBJCHANNEL *pChannel, OBJGPU *pGpu, NvBool bUseVasForCeCopy, NvBool bMIGInUse); +void channelSetupChannelBufferSizes(OBJCHANNEL *pChannel); + +// Needed for pushbuffer management +NV_STATUS channelWaitForFreeEntry(OBJCHANNEL *pChannel, NvU32 *pPutIndex); +NV_STATUS channelFillGpFifo(OBJCHANNEL *pChannel, NvU32 putIndex, NvU32 methodsLength); +NvU32 channelFillPb(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined, + NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo); +NvU32 channelFillPbFastScrub(OBJCHANNEL *pChannel, NvU32 putIndex, NvBool bPipelined, + NvBool bInsertFinishPayload, CHANNEL_PB_INFO *pChannelPbInfo); + +// Needed for work tracking +NV_STATUS channelWaitForFinishPayload(OBJCHANNEL *pChannel, NvU64 targetPayload); +NvU64 channelGetFinishPayload(OBJCHANNEL *pChannel); + +#endif // _CHANNEL_UTILS_H_ diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h b/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h index c0f3eb1322..6a5b4eaab0 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/heap_base.h @@ -125,7 +125,7 @@ typedef struct PMA_ALLOC_INFO { NvBool bContig; NvU32 pageCount; - NvU32 pageSize; + NvU64 pageSize; NvU32 refCount; NvU64 allocSize; NvU32 flags; diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h index f111309813..f98d80d537 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h @@ -34,16 +34,18 @@ #include "nvctassert.h" #include "vgpu/vgpu_guest_pma_scrubber.h" +#if !defined(SRT_BUILD) +#include "gpu/mem_mgr/ce_utils.h" +#endif struct OBJGPU; struct Heap; struct OBJCHANNEL; -#define RM_SUBCHANNEL 0x0 #define MEMSET_PATTERN 0x00000000 #define SCRUBBER_NUM_PAYLOAD_SEMAPHORES (2) #define SCRUBBER_SEMAPHORE_SIZE_INBYTES (4) -#define SCRUBBER_CHANNEL_SEMAPHORE_SIZE (SCRUBBER_SEMAPHORE_SIZE_INBYTES *\ +#define SCRUBBER_CHANNEL_SEMAPHORE_SIZE (SCRUBBER_SEMAPHORE_SIZE_INBYTES * \ SCRUBBER_NUM_PAYLOAD_SEMAPHORES) #define SCRUBBER_CHANNEL_NOTIFIER_SIZE (sizeof(NvNotification) * NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1) @@ -52,67 +54,6 @@ struct OBJCHANNEL; #define SCRUB_MAX_BYTES_PER_LINE 0xffffffffULL #define MAX_SCRUB_ITEMS 4096 // 4K scrub items -#define READ_SCRUBBER_PAYLOAD_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA +\ - channel->finishPayloadOffset) - -#define READ_SCRUBBER_PB_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA +\ - channel->semaOffset) - -#define WRITE_SCRUBBER_PB_SEMA(channel, val) MEM_WR32((NvU8*)channel->pbCpuVA +\ - channel->semaOffset, val); - -#define WRITE_SCRUBBER_PAYLOAD_SEMA(channel,val) MEM_WR32((NvU8*)channel->pbCpuVA +\ - channel->finishPayloadOffset, val); -// Use Incrementing Methods to save the PB Space -#define _NV_ASSERT_CONTIGUOUS_METHODS(a1, a2) NV_ASSERT((a2) - (a1) == 4) - -#define NV_PUSH_METHOD(OpType, SubCh, Method, Count) \ - (DRF_DEF(906F, _DMA, _SEC_OP, OpType) |\ - DRF_NUM(906F, _DMA, _METHOD_ADDRESS, (Method) >> 2) |\ - DRF_NUM(906F, _DMA, _METHOD_SUBCHANNEL, (SubCh)) |\ - DRF_NUM(906F, _DMA, _METHOD_COUNT, (Count))) - -#define NV_PUSH_DATA(Data) MEM_WR32(pPtr++, (Data)) - -#define _NV_PUSH_INC_1U(SubCh, a1,d1, Count) \ - do{ \ - NV_PUSH_DATA(NV_PUSH_METHOD(_INC_METHOD, SubCh, a1, Count));\ - NV_PUSH_DATA(d1); \ - } while(0) - -#define NV_PUSH_INC_1U(SubCh, a1,d1) \ - do{ \ - _NV_PUSH_INC_1U (SubCh, a1,d1, 1);\ - } while(0) - -#define NV_PUSH_INC_2U(SubCh, a1,d1, a2,d2) \ - do{ \ - _NV_ASSERT_CONTIGUOUS_METHODS(a1, a2);\ - _NV_PUSH_INC_1U(SubCh, a1,d1, 2); \ - NV_PUSH_DATA(d2); \ - } while(0) - -#define NV_PUSH_INC_3U(SubCh, a1,d1, a2,d2, a3,d3) \ - do{ \ - _NV_ASSERT_CONTIGUOUS_METHODS(a1,a2);\ - _NV_ASSERT_CONTIGUOUS_METHODS(a2,a3);\ - _NV_PUSH_INC_1U(SubCh, a1,d1, 3); \ - NV_PUSH_DATA(d2); \ - NV_PUSH_DATA(d3); \ - } while(0) - -#define NV_PUSH_INC_4U(SubCh, a1,d1, a2,d2, a3,d3, a4,d4) \ - do{ \ - _NV_ASSERT_CONTIGUOUS_METHODS(a1,a2);\ - _NV_ASSERT_CONTIGUOUS_METHODS(a2,a3);\ - _NV_ASSERT_CONTIGUOUS_METHODS(a3,a4);\ - _NV_PUSH_INC_1U(SubCh, a1,d1, 4); \ - NV_PUSH_DATA(d2); \ - NV_PUSH_DATA(d3); \ - NV_PUSH_DATA(d4); \ - } while(0) - - // structure to store the details of a scrubbing work typedef struct SCRUB_NODE { // The 64 bit ID assigned to each work @@ -144,8 +85,10 @@ typedef struct OBJMEMSCRUB { NvLength scrubListSize; // Pre-allocated Free Scrub List PSCRUB_NODE pScrubList; - // Scrubber Channel - struct OBJCHANNEL *pChannel; +#if !defined(SRT_BUILD) + // Scrubber uses ceUtils to manage CE channel + CeUtils ceUtilsObject; +#endif struct OBJGPU *pGpu; VGPU_GUEST_PMA_SCRUB_BUFFER_RING vgpuScrubBuffRing; NvBool bVgpuScrubberEnabled; diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h index c3d7feaab4..ca15a1b525 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h @@ -26,12 +26,12 @@ #include "core/prelude.h" -#define CLEAR_HAL_ATTR(a) \ +#define CLEAR_HAL_ATTR(a) \ a = (a &~(DRF_NUM(OS32, _ATTR, _COMPR, 0x3) | \ DRF_NUM(OS32, _ATTR, _TILED, 0x3) | \ DRF_NUM(OS32, _ATTR, _ZCULL, 0x3))); -#define CLEAR_HAL_ATTR2(a) \ +#define CLEAR_HAL_ATTR2(a) \ a = (a & ~(DRF_SHIFTMASK(NVOS32_ATTR2_ZBC) | \ DRF_SHIFTMASK(NVOS32_ATTR2_GPU_CACHEABLE))); diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h index 9ed743385e..581b905c96 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h @@ -127,12 +127,12 @@ void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess); */ NV_STATUS pmaAddrtreeScanContiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); NV_STATUS pmaAddrtreeScanDiscontiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); void pmaAddrtreePrintTree(void *pMap, const char* str); @@ -154,7 +154,7 @@ void pmaAddrtreePrintTree(void *pMap, const char* str); void pmaAddrtreeChangeState(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState); void pmaAddrtreeChangeStateAttrib(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, NvBool writeAttrib); void pmaAddrtreeChangeStateAttribEx(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState,PMA_PAGESTATUS newStateMask); -void pmaAddrtreeChangePageStateAttrib(void * pMap, NvU64 startFrame, NvU32 pageSize, +void pmaAddrtreeChangePageStateAttrib(void * pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, NvBool writeAttrib); /*! diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h index 0817d24d1d..cd70f63c14 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h @@ -90,7 +90,7 @@ typedef NvU32 PMA_PAGESTATUS; #define ATTRIB_PERSISTENT NVBIT(MAP_IDX_PERSISTENT) #define ATTRIB_NUMA_REUSE NVBIT(MAP_IDX_NUMA_REUSE) #define ATTRIB_BLACKLIST NVBIT(MAP_IDX_BLACKLIST) -#define ATTRIB_MASK (ATTRIB_EVICTING | ATTRIB_SCRUBBING \ +#define ATTRIB_MASK (ATTRIB_EVICTING | ATTRIB_SCRUBBING \ | ATTRIB_PERSISTENT | ATTRIB_NUMA_REUSE \ | ATTRIB_BLACKLIST) @@ -114,6 +114,9 @@ typedef struct _PMA_STATS NvU64 numFreeFrames; // PMA-wide free 64KB frame count NvU64 numFree2mbPages; // PMA-wide free 2MB pages count #if !defined(NVWATCH) + NvU64 num2mbPagesProtected; // PMA-wide total number of 2MB pages in protected memory + NvU64 numFreeFramesProtected; // PMA-wide free 64KB frame count in protected memory + NvU64 numFree2mbPagesProtected; // PMA-wide free 2MB pages count in protected memory #endif // !defined(NVWATCH) } PMA_STATS; diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/numa.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/numa.h index 5fa78dbbf1..7d011935a5 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/numa.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/numa.h @@ -59,7 +59,7 @@ extern "C" { * is used for allocations coming from the Linux kernel. * The perf implication is under further study. See bug #1999793. */ -NV_STATUS pmaNumaAllocate(PMA *pPma, NvLength allocationCount, NvU32 pageSize, +NV_STATUS pmaNumaAllocate(PMA *pPma, NvLength allocationCount, NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages); /*! diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h index 36f489016d..692d7abf5b 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,6 +73,7 @@ typedef struct SCRUB_NODE SCRUB_NODE; #define PMA_INIT_INTERNAL NVBIT(3) // Used after heap is removed #define PMA_INIT_FORCE_PERSISTENCE NVBIT(4) #define PMA_INIT_ADDRTREE NVBIT(5) +#define PMA_INIT_NUMA_AUTO_ONLINE NVBIT(6) // These flags are used for querying PMA's config and/or state. #define PMA_QUERY_SCRUB_ENABLED NVBIT(0) @@ -166,7 +167,7 @@ typedef enum /*! * @brief Callbacks to UVM for eviction */ -typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU32 pageSize, NvU64 *pPages, +typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU64 pageSize, NvU64 *pPages, NvU32 count, NvU64 physBegin, NvU64 physEnd, MEMORY_PROTECTION prot); typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 physEnd, @@ -180,13 +181,13 @@ typedef void (*pmaMapDestroy_t)(void *pMap); typedef void (*pmaMapChangeState_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState); typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, NvBool writeAttrib); typedef void (*pmaMapChangeStateAttribEx_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); -typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU32 pageSize, PMA_PAGESTATUS newState, NvBool writeAttrib); +typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, NvBool writeAttrib); typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib); typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); typedef NV_STATUS (*pmaMapScanDiscontiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); typedef void (*pmaMapGetSize_t)(void *pMap, NvU64 *pBytesTotal); typedef void (*pmaMapGetLargestFree_t)(void *pMap, NvU64 *pLargestFree); @@ -251,6 +252,7 @@ struct _PMA NvU64 coherentCpuFbBase; // Used to calculate FB offset from bus address NvU64 coherentCpuFbSize; // Used for error checking only NvU32 numaReclaimSkipThreshold; // percent value below which __GFP_RECLAIM will not be used. + NvBool bNumaAutoOnline; // If NUMA memory is auto-onlined // Blacklist related states PMA_BLACKLIST_CHUNK *pBlacklistChunks; // Tracking for blacklist pages @@ -433,12 +435,12 @@ NV_STATUS pmaRegisterRegion(PMA *pPma, NvU32 id, NvBool bAsyncEccScrub, * code,because it is not very informative. * */ -NV_STATUS pmaAllocatePages(PMA *pPma, NvLength pageCount, NvU32 pageSize, +NV_STATUS pmaAllocatePages(PMA *pPma, NvLength pageCount, NvU64 pageSize, PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages); // allocate on multiple GPU, thus pmaCount NV_STATUS pmaAllocatePagesBroadcast(PMA **pPma, NvU32 pmaCount, NvLength allocationCount, - NvU32 pageSize, PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages); + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *pAllocationOptions, NvU64 *pPages); /*! @@ -472,7 +474,7 @@ NV_STATUS pmaAllocatePagesBroadcast(PMA **pPma, NvU32 pmaCount, NvLength allocat * TODO some error for rollback * */ -NV_STATUS pmaPinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU32 pageSize); +NV_STATUS pmaPinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize); /*! @@ -498,7 +500,7 @@ NV_STATUS pmaPinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU32 pageSi * TODO some error for rollback * */ -NV_STATUS pmaUnpinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU32 pageSize); +NV_STATUS pmaUnpinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize); /*! @@ -815,7 +817,7 @@ void pmaNumaOfflined(PMA *pPma); * @return * void */ -void pmaGetClientBlacklistedPages(PMA *pPma, NvU64 *pChunks, NvU32 *pPageSize, NvU32 *pNumChunks); +void pmaGetClientBlacklistedPages(PMA *pPma, NvU64 *pChunks, NvU64 *pPageSize, NvU32 *pNumChunks); /*! * @brief Returns the PMA blacklist size in bytes for @@ -865,6 +867,54 @@ void pmaPrintMapState(PMA *pPma); */ NV_STATUS pmaAddToBlacklistTracking(PMA *pPma, NvU64 physBase); +/*! + * @brief Returns total protected video memory. + * + * @param[in] pPma PMA pointer + * @param[in] pBytesTotal Pointer that will return the total FB memory size. + * + * @return + * void + */ +void pmaGetTotalProtectedMemory(PMA *pPma, NvU64 *pBytesTotal); + +/*! + * @brief Returns total unprotected video memory. + * + * @param[in] pPma PMA pointer + * @param[in] pBytesTotal Pointer that will return the total FB memory size. + * + * @return + * void + */ +void pmaGetTotalUnprotectedMemory(PMA *pPma, NvU64 *pBytesTotal); + +/*! + * @brief Returns information about the total free protected FB memory. + * In confidential compute use cases, memory will be split into + * protected and unprotected regions + * + * @param[in] pPma PMA pointer + * @param[in] pBytesFree Pointer that will return the free protected memory size. + * + * @return + * void + */ +void pmaGetFreeProtectedMemory(PMA *pPma, NvU64 *pBytesFree); + +/*! + * @brief Returns information about the total free unprotected FB memory. + * In confidential compute use cases, memory will be split into + * protected and unprotected regions + * + * @param[in] pPma PMA pointer + * @param[in] pBytesFree Pointer that will return the free unprotected memory size. + * + * @return + * void + */ +void pmaGetFreeUnprotectedMemory(PMA *pPma, NvU64 *pBytesFree); + #ifdef __cplusplus } #endif diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h index 23f013c636..d81430e3de 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h @@ -45,11 +45,11 @@ NvBool pmaStateCheck(PMA *pPma); NV_STATUS _pmaEvictContiguous(PMA *pPma, void *pMap, NvU64 evictStart, NvU64 evictEnd, MEMORY_PROTECTION prot); NV_STATUS _pmaEvictPages(PMA *pPma, void *pMap, NvU64 *evictPages, NvU64 evictPageCount, - NvU64 *allocPages, NvU64 allocPageCount, NvU32 pageSize, + NvU64 *allocPages, NvU64 allocPageCount, NvU64 pageSize, NvU64 physBegin, NvU64 physEnd, MEMORY_PROTECTION prot); void _pmaClearScrubBit(PMA *pPma, SCRUB_NODE *pPmaScrubList, NvU64 count); NV_STATUS _pmaCheckScrubbedPages(PMA *pPma, NvU64 chunkSize, NvU64 *pPages, NvU32 pageCount); -NV_STATUS _pmaPredictOutOfMemory(PMA *pPma, NvLength allocationCount, NvU32 pageSize, +NV_STATUS _pmaPredictOutOfMemory(PMA *pPma, NvLength allocationCount, NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions); NV_STATUS pmaSelector(PMA *pPma, PMA_ALLOCATION_OPTIONS *allocationOptions, NvS32 *regionList); void _pmaReallocBlacklistPages (PMA *pPma, NvU32 regId, NvU64 rangeBegin, NvU64 rangeSize); diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h index 1bb49ea35e..1e3a5605d5 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h @@ -131,7 +131,7 @@ void pmaRegmapChangeStateAttrib(void *pMap, NvU64 frameNum, * * @return void */ -void pmaRegmapChangePageStateAttrib(void * pMap, NvU64 frameNumStart, NvU32 pageSize, +void pmaRegmapChangePageStateAttrib(void * pMap, NvU64 frameNumStart, NvU64 pageSize, PMA_PAGESTATUS newState, NvBool writeAttrib); /*! @@ -188,7 +188,7 @@ PMA_PAGESTATUS pmaRegmapRead(void *pMap, NvU64 frameNum, NvBool readAttrib); */ NV_STATUS pmaRegmapScanContiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); /*! @@ -215,7 +215,7 @@ NV_STATUS pmaRegmapScanContiguous( */ NV_STATUS pmaRegmapScanDiscontiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, + NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); /*! diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h b/src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h new file mode 100644 index 0000000000..ad4acbbbdb --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RM_PAGE_SIZE_H +#define RM_PAGE_SIZE_H + + + +//--------------------------------------------------------------------------- +// +// Memory page defines. +// +// These correspond to the granularity understood by the hardware +// for address mapping; the system page size can be larger. +// +//--------------------------------------------------------------------------- +#define RM_PAGE_SIZE_INVALID 0 +#define RM_PAGE_SIZE 4096 +#define RM_PAGE_SIZE_64K (64 * 1024) +#define RM_PAGE_SIZE_128K (128 * 1024) +#define RM_PAGE_MASK 0x0FFF +#define RM_PAGE_SHIFT 12 +#define RM_PAGE_SHIFT_64K 16 +#define RM_PAGE_SHIFT_128K 17 +#define RM_PAGE_SHIFT_2M 21 +#define RM_PAGE_SIZE_2M (1 << RM_PAGE_SHIFT_2M) + +// Huge page size is 2 MB +#define RM_PAGE_SHIFT_HUGE RM_PAGE_SHIFT_2M +#define RM_PAGE_SIZE_HUGE (1ULL << RM_PAGE_SHIFT_HUGE) +#define RM_PAGE_MASK_HUGE ((1ULL << RM_PAGE_SHIFT_HUGE) - 1) + +// 512MB page size +#define RM_PAGE_SHIFT_512M 29 +#define RM_PAGE_SIZE_512M (1ULL << RM_PAGE_SHIFT_512M) +#define RM_PAGE_MASK_512M (RM_PAGE_SIZE_512M - 1) + +//--------------------------------------------------------------------------- +// +// Memory page attributes. +// +// These attributes are used by software for page size mapping; +// Big pages can be of 64/128KB[Fermi/Kepler/Pascal] +// Huge page is 2 MB[Pascal+] +// 512MB page is Ampere+ +// Default page attribute lets driver decide the optimal page size +// +//--------------------------------------------------------------------------- +typedef enum +{ + RM_ATTR_PAGE_SIZE_DEFAULT, + RM_ATTR_PAGE_SIZE_4KB, + RM_ATTR_PAGE_SIZE_BIG, + RM_ATTR_PAGE_SIZE_HUGE, + RM_ATTR_PAGE_SIZE_512MB, + RM_ATTR_PAGE_SIZE_INVALID +} +RM_ATTR_PAGE_SIZE; + +#endif // RM_PAGE_SIZE_H diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/sem_surf.h b/src/nvidia/inc/kernel/gpu/mem_mgr/sem_surf.h new file mode 100644 index 0000000000..160cbe4bcd --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/sem_surf.h @@ -0,0 +1,3 @@ + +#include "g_sem_surf_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h b/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h index adee05c30d..0180cf80d5 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -33,60 +33,14 @@ #include "nvtypes.h" #include "nvgputypes.h" #include "nvstatus.h" +#include "resserv/rs_client.h" +#include "gpu/mem_mgr/rm_page_size.h" typedef struct OBJGPU OBJGPU; typedef struct ChannelDescendant ChannelDescendant; typedef struct ContextDma ContextDma; typedef struct Memory Memory; typedef struct EVENTNOTIFICATION EVENTNOTIFICATION; -//--------------------------------------------------------------------------- -// -// Memory page defines. -// -// These correspond to the granularity understood by the hardware -// for address mapping; the system page size can be larger. -// -//--------------------------------------------------------------------------- -#define RM_PAGE_SIZE_INVALID 0 -#define RM_PAGE_SIZE 4096 -#define RM_PAGE_SIZE_64K (64 * 1024) -#define RM_PAGE_SIZE_128K (128 * 1024) -#define RM_PAGE_MASK 0x0FFF -#define RM_PAGE_SHIFT 12 -#define RM_PAGE_SHIFT_64K 16 -#define RM_PAGE_SHIFT_128K 17 - -// Huge page size is 2 MB -#define RM_PAGE_SHIFT_HUGE 21 -#define RM_PAGE_SIZE_HUGE (1 << RM_PAGE_SHIFT_HUGE) -#define RM_PAGE_MASK_HUGE ((1 << RM_PAGE_SHIFT_HUGE) - 1) - -// 512MB page size -#define RM_PAGE_SHIFT_512M 29 -#define RM_PAGE_SIZE_512M (1 << RM_PAGE_SHIFT_512M) -#define RM_PAGE_MASK_512M (RM_PAGE_SIZE_512M - 1) - -//--------------------------------------------------------------------------- -// -// Memory page attributes. -// -// These attributes are used by software for page size mapping; -// Big pages can be of 64/128KB[Fermi/Kepler/Pascal] -// Huge page is 2 MB[Pascal+] -// 512MB page is Ampere+ -// Default page attribute lets driver decide the optimal page size -// -//--------------------------------------------------------------------------- -typedef enum -{ - RM_ATTR_PAGE_SIZE_DEFAULT = 0x0, - RM_ATTR_PAGE_SIZE_4KB = 0x1, - RM_ATTR_PAGE_SIZE_BIG = 0x2, - RM_ATTR_PAGE_SIZE_HUGE = 0x3, - RM_ATTR_PAGE_SIZE_512MB = 0x4, - RM_ATTR_PAGE_SIZE_INVALID = 0x5 -} -RM_ATTR_PAGE_SIZE; //--------------------------------------------------------------------------- // @@ -133,8 +87,8 @@ void notifyFillNOTIFICATION(OBJGPU *pGpu, NV_STATUS CompletionStatus, NvBool TimeSupplied, NvU64 Time); -NV_STATUS notifyFillNotifierGPUVA (OBJGPU*, NvHandle, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32); -NV_STATUS notifyFillNotifierGPUVATimestamp (OBJGPU*, NvHandle, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32, NvU64); +NV_STATUS notifyFillNotifierGPUVA (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32); +NV_STATUS notifyFillNotifierGPUVATimestamp (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32, NvU64); NV_STATUS notifyFillNotifierMemory (OBJGPU*, Memory *, NvV32, NvV16, NV_STATUS, NvU32); NV_STATUS notifyFillNotifierMemoryTimestamp(OBJGPU*, Memory *, NvV32, NvV16, NV_STATUS, NvU32, NvU64); void notifyFillNvNotification(OBJGPU *pGpu, @@ -145,8 +99,8 @@ void notifyFillNvNotification(OBJGPU *pGpu, NvBool TimeSupplied, NvU64 Time); -NV_STATUS semaphoreFillGPUVA (OBJGPU*, NvHandle, NvHandle, NvU64, NvV32, NvV32, NvBool); -NV_STATUS semaphoreFillGPUVATimestamp(OBJGPU*, NvHandle, NvHandle, NvU64, NvV32, NvV32, NvBool, NvU64); +NV_STATUS semaphoreFillGPUVA (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV32, NvBool); +NV_STATUS semaphoreFillGPUVATimestamp(OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV32, NvBool, NvU64); RM_ATTR_PAGE_SIZE dmaNvos32ToPageSizeAttr(NvU32 attr, NvU32 attr2); diff --git a/src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h b/src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h index 8972a61b01..29d846c17c 100644 --- a/src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h +++ b/src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h @@ -67,7 +67,7 @@ typedef struct NvU32 flags; /*! - * Specifies number of clients who requested + * Specifies number of clients who requested * CUDA boost. This is used only in case of the CUDA clients. */ NvU32 refCount; diff --git a/src/nvidia/inc/kernel/gpu/perf/kern_perf_gpuboostsync.h b/src/nvidia/inc/kernel/gpu/perf/kern_perf_gpuboostsync.h index 4c38cd1faa..d47c5265c9 100644 --- a/src/nvidia/inc/kernel/gpu/perf/kern_perf_gpuboostsync.h +++ b/src/nvidia/inc/kernel/gpu/perf/kern_perf_gpuboostsync.h @@ -50,7 +50,7 @@ struct KERNEL_PERF_GPU_BOOST_SYNC */ NvBool bHystersisEnable; - /*! + /*! * SLI GPU Boost feature is enabled. */ NvBool bSliGpuBoostSyncEnable; diff --git a/src/nvidia/inc/kernel/gpu/sec2/sec2_context.h b/src/nvidia/inc/kernel/gpu/sec2/sec2_context.h new file mode 100644 index 0000000000..3b092e381c --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/sec2/sec2_context.h @@ -0,0 +1,3 @@ + +#include "g_sec2_context_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h b/src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h new file mode 100644 index 0000000000..d279de0957 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef LIBSPDM_INCLUDES_H +#define LIBSPDM_INCLUDES_H + +// +// Dedicated header file to centralize all libspdm-related includes and defines. +// This allows us to minimize the amount of headers (and sources) that have direct +// libspdm dependency, and allowing shared macros & types for dependent source. +// + +/* ------------------------ Includes --------------------------------------- */ +#include "internal/libspdm_common_lib.h" +#include "internal/libspdm_secured_message_lib.h" +#include "library/spdm_requester_lib.h" + +/* ------------------------ Macros and Defines ----------------------------- */ +// +// As libspdm has its own RETURN_STATUS define, we need to ensure we do not +// accidentally compare it against NV_STATUS. Use macro for consistent libspdm +// error handling. +// +#define CHECK_SPDM_STATUS(expr) do { \ + libspdm_return_t __spdmStatus; \ + __spdmStatus = (expr); \ + if (LIBSPDM_STATUS_IS_ERROR(__spdmStatus)) \ + { \ + NV_PRINTF(LEVEL_INFO, "SPDM failed with status 0x%0x\n", \ + __spdmStatus); \ + status = NV_ERR_GENERIC; \ + goto ErrorExit; \ + } \ + } while (NV_FALSE) + +// Check for any critical issues caused by data size mismatches. +ct_assert(sizeof(NvU8) == sizeof(uint8_t)); +ct_assert(sizeof(NvU16) == sizeof(uint16_t)); +ct_assert(sizeof(NvU32) == sizeof(uint32_t)); +ct_assert(sizeof(NvU64) == sizeof(uint64_t)); + +typedef struct _SPDM_ALGO_CHECK_ENTRY +{ + libspdm_data_type_t dataType; + uint32_t expectedAlgo; +} SPDM_ALGO_CHECK_ENTRY, *PSPDM_ALGO_CHECK_ENTRY; + +// +// Check for assert in libspdm code, indicating a fatal condition. +// Returns false if assert was hit. +// +bool nvspdm_check_and_clear_libspdm_assert(void); + +#endif // LIBSPDM_INCLUDES_H diff --git a/src/nvidia/inc/kernel/gpu/spdm/spdm.h b/src/nvidia/inc/kernel/gpu/spdm/spdm.h new file mode 100644 index 0000000000..3f9037df27 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/spdm/spdm.h @@ -0,0 +1,3 @@ + +#include "g_spdm_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h b/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h index 41cb26a767..ee8ce71e9f 100644 --- a/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h +++ b/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h @@ -51,24 +51,24 @@ NV_STATUS subdeviceCtrlCmdRcSetCleanErrorHistory(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY, API_LOCK_READONLY)) NV_STATUS subdeviceCtrlCmdRcGetWatchdogInfo(Subdevice *pSubdevice, NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS *pWatchdogInfoParams); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY)) NV_STATUS subdeviceCtrlCmdRcDisableWatchdog(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY)) NV_STATUS subdeviceCtrlCmdRcSoftDisableWatchdog(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY)) NV_STATUS subdeviceCtrlCmdRcEnableWatchdog(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS, - RMCTRL_FLAGS(NON_PRIVILEGED)) + RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY)) NV_STATUS subdeviceCtrlCmdRcReleaseWatchdogRequests(Subdevice *pSubdevice); RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT, diff --git a/src/nvidia/inc/kernel/mem_mgr/egm_mem.h b/src/nvidia/inc/kernel/mem_mgr/egm_mem.h new file mode 100644 index 0000000000..b0eae12eab --- /dev/null +++ b/src/nvidia/inc/kernel/mem_mgr/egm_mem.h @@ -0,0 +1,3 @@ + +#include "g_egm_mem_nvoc.h" + diff --git a/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h b/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h index 8f9e36f57a..13efb289d7 100644 --- a/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h +++ b/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h @@ -46,13 +46,13 @@ typedef enum { - POOL_CONFIG_GMMU_FMT_1 = 0, // configure pool for client page tables with version = GMMU_FMT_VERSION_1 - POOL_CONFIG_GMMU_FMT_2 = 1, // configure pool for client page tables with version = GMMU_FMT_VERSION_2 - POOL_CONFIG_CTXBUF_512M = 2, // configure pool for RM internal allocations like ctx buffers with 512MB page size - POOL_CONFIG_CTXBUF_2M = 3, // configure pool for RM internal allocations like ctx buffers with 2MB page size - POOL_CONFIG_CTXBUF_64K = 4, // configure pool for RM internal allocations like ctx buffers with 64KB page size - POOL_CONFIG_CTXBUF_4K = 5, // configure pool for RM internal allocations like ctx buffers with 4KB page size - POOL_CONFIG_MAX_SUPPORTED = 6 + POOL_CONFIG_GMMU_FMT_1, // configure pool for client page tables with version = GMMU_FMT_VERSION_1 + POOL_CONFIG_GMMU_FMT_2, // configure pool for client page tables with version = GMMU_FMT_VERSION_2 + POOL_CONFIG_CTXBUF_512M, // configure pool for RM internal allocations like ctx buffers with 512MB page size + POOL_CONFIG_CTXBUF_2M, // configure pool for RM internal allocations like ctx buffers with 2MB page size + POOL_CONFIG_CTXBUF_64K, // configure pool for RM internal allocations like ctx buffers with 64KB page size + POOL_CONFIG_CTXBUF_4K, // configure pool for RM internal allocations like ctx buffers with 4KB page size + POOL_CONFIG_MAX_SUPPORTED }POOL_CONFIG_MODE; /* ------------------------------------ Datatypes ---------------------------------- */ diff --git a/src/nvidia/inc/kernel/os/os_stub.h b/src/nvidia/inc/kernel/os/os_stub.h index 4ddcf9faa9..2d8a590268 100644 --- a/src/nvidia/inc/kernel/os/os_stub.h +++ b/src/nvidia/inc/kernel/os/os_stub.h @@ -53,11 +53,6 @@ OSSimEscapeWriteBuffer stubOsSimEscapeWriteBuffer; OSSimEscapeRead stubOsSimEscapeRead; OSSimEscapeReadBuffer stubOsSimEscapeReadBuffer; OSSetSurfaceName stubOsSetSurfaceName; -OSCallACPI_BCL stubOsCallACPI_BCL; -OSCallACPI_ON stubOsCallACPI_ON; -OSCallACPI_OFF stubOsCallACPI_OFF; -OSCallACPI_NVHG_GPUON stubOsCallWMI_NVHG_GPUON; -OSCallACPI_NVHG_GPUOFF stubOsCallWMI_NVHG_GPUOFF; OSCallACPI_NVHG_GPUSTA stubOsCallWMI_NVHG_GPUSTA; OSCallACPI_NVHG_MXDS stubOsCallWMI_NVHG_MXDS; OSCallACPI_NVHG_MXMX stubOsCallWMI_NVHG_MXMX; @@ -66,15 +61,11 @@ OSCallACPI_NVHG_DCS stubOsCallWMI_NVHG_DCS; OSCheckCallback stubOsCheckCallback; OSRCCallback stubOsRCCallback; -OSCallACPI_NBPS stubOsCallACPI_NBPS; -OSCallACPI_NBSL stubOsCallACPI_NBSL; -OSCallACPI_OPTM_GPUON stubOsCallWMI_OPTM_GPUON; OSSetupVBlank stubOsSetupVBlank; OSObjectEventNotification stubOsObjectEventNotification; OSPageArrayGetPhysAddr stubOsPageArrayGetPhysAddr; OSInternalReserveFreeCallback stubOsInternalReserveFreeCallback; OSInternalReserveAllocCallback stubOsInternalReserveAllocCallback; OSGetUefiVariable stubOsGetUefiVariable; -OSCallACPI_LRST stubOsCallACPI_LRST; #endif // OS_STUB_H diff --git a/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h b/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h index a4a560ad1d..cdbfc28c08 100644 --- a/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h +++ b/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h @@ -47,9 +47,9 @@ typedef enum _NBSI_TBL_SOURCES // keep in sync with nvapi.spec #define NBSI_TBL_SOURCE_MAX 6 // number of NBSI_TBL_SOURCES entries (not including BEST FIT) #define NBSI_TBL_SOURCE_ALL (NBSI_TBL_SOURCE_REGISTRY | \ - NBSI_TBL_SOURCE_VBIOS | \ - NBSI_TBL_SOURCE_SBIOS | \ - NBSI_TBL_SOURCE_ACPI | \ + NBSI_TBL_SOURCE_VBIOS | \ + NBSI_TBL_SOURCE_SBIOS | \ + NBSI_TBL_SOURCE_ACPI | \ NBSI_TBL_SOURCE_UEFI) #define NBSI_TBL_SOURCE_NONE 0 diff --git a/src/nvidia/inc/kernel/platform/pci_exp_table.h b/src/nvidia/inc/kernel/platform/pci_exp_table.h index 185bd69787..cac54aa318 100644 --- a/src/nvidia/inc/kernel/platform/pci_exp_table.h +++ b/src/nvidia/inc/kernel/platform/pci_exp_table.h @@ -31,7 +31,7 @@ #define PCI_EXP_ROM_SIGNATURE 0xaa55 #define PCI_EXP_ROM_SIGNATURE_NV 0x4e56 // "VN" in word format #define PCI_EXP_ROM_SIGNATURE_NV2 0xbb77 -#define IS_VALID_PCI_ROM_SIG(sig) ((sig == PCI_EXP_ROM_SIGNATURE) || \ +#define IS_VALID_PCI_ROM_SIG(sig) ((sig == PCI_EXP_ROM_SIGNATURE) || \ (sig == PCI_EXP_ROM_SIGNATURE_NV) || \ (sig == PCI_EXP_ROM_SIGNATURE_NV2)) @@ -68,7 +68,7 @@ typedef union _PCI_EXP_ROM { #define PCI_DATA_STRUCT_SIGNATURE 0x52494350 // "PCIR" in dword format #define PCI_DATA_STRUCT_SIGNATURE_NV 0x5344504E // "NPDS" in dword format #define PCI_DATA_STRUCT_SIGNATURE_NV2 0x53494752 // "RGIS" in dword format -#define IS_VALID_PCI_DATA_SIG(sig) ((sig == PCI_DATA_STRUCT_SIGNATURE) || \ +#define IS_VALID_PCI_DATA_SIG(sig) ((sig == PCI_DATA_STRUCT_SIGNATURE) || \ (sig == PCI_DATA_STRUCT_SIGNATURE_NV) || \ (sig == PCI_DATA_STRUCT_SIGNATURE_NV2)) diff --git a/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h b/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h index d9c594df24..8d6b6dff80 100644 --- a/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h +++ b/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -54,6 +54,42 @@ #define NV_PB_PFM_REQ_HNDLR_PCTRL_BIT_31 31:31 #define NV_PB_PFM_REQ_HNDLR_PCTRL_BIT_31_ZERO (0) +/* + * NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO + * + * GPU EDPpeak Limit information for platform + * + * ulVersion + * (Major(16 bits):Minor(16 bits), current v1.0) + * Little endian format 0x00, 0x00, 0x01, 0x00 + * limitLast + * last requested platform limit + * limitMin + * Minimum allowed limit value on EDPp policy on both AC and DC + * limitRated + * Rated/default allowed limit value on EDPp policy on AC + * limitMax + * Maximum allowed limit value on EDPp policy on AC + * limitCurr + * Current resultant limit effective on EDPp policy on AC and DC + * limitBattRated + * Default/rated allowed limit on EDPp policy on DC + * limitBattMax + * Maximum allowed limit on EDPp policy on DC + * rsvd + * Reserved + */ +typedef struct NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1 { + NvU32 ulVersion; + NvU32 limitLast; + NvU32 limitMin; + NvU32 limitRated; + NvU32 limitMax; + NvU32 limitCurr; + NvU32 limitBattRated; + NvU32 limitBattMax; + NvU32 rsvd; +} NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1, *PNV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1; /* * NV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA @@ -181,6 +217,8 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPM (GPS_FUNC_GETPPM) #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPM (GPS_FUNC_SETPPM) #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS (GPS_FUNC_PSHAREPARAMS) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETEDPPLIMITINFO (GPS_FUNC_SETEDPPLIMITINFO) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETEDPPLIMIT (GPS_FUNC_GETEDPPLIMIT) // PFM_REQ_HNDLR_SUPPORT output #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SUPPORT_AVAIL 0:0 @@ -193,6 +231,8 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPM_AVAIL 40:40 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPM_AVAIL 41:41 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHAREPARAMS_AVAIL 42:42 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_INFOEDPPLIMIT_AVAIL 43:43 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETEDPPLIMIT_AVAIL 44:44 // PFM_REQ_HNDLR_PCONTROL #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE 3:0 @@ -221,7 +261,12 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE 22:22 // output only #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_DISABLE (0) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_ENABLE (1) - +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET 25:25 // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET_FALSE (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET_TRUE (1U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET 26:26 // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET_FALSE (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET_TRUE (1U) // Shared by GETPPL, SETPPL #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT (3) @@ -250,6 +295,9 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_INDEX 7:0 // output #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_AVAILABLE_MASK 15:8 // output +// Shared by INFOEDPPLIMIT and SETEDPPLIMIT +#define NV0000_CTRL_PFM_REQ_HNDLR_EDPP_VERSION_V10 (0x10000U) // input & output + // // PFM_REQ_HNDLR_PSHARE_PARAMS // status bits diff --git a/src/nvidia/inc/kernel/rmapi/control.h b/src/nvidia/inc/kernel/rmapi/control.h index fb64b6fe13..c1f6c0e32e 100644 --- a/src/nvidia/inc/kernel/rmapi/control.h +++ b/src/nvidia/inc/kernel/rmapi/control.h @@ -99,20 +99,20 @@ typedef struct #define RMCTRL_CLEAR_CAP(tbl,cap,field) ((tbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) &= ~(0?cap##field)) // macros to AND/OR caps between two tables -#define RMCTRL_AND_CAP(finaltbl,tmptbl,tmp,cap,field) \ +#define RMCTRL_AND_CAP(finaltbl,tmptbl,tmp,cap,field) \ tmp = ((finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] & tmptbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) & (0?cap##field)); \ - finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] &= ~(0?cap##field); \ + finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] &= ~(0?cap##field); \ finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] |= tmp; -#define RMCTRL_OR_CAP(finaltbl,tmptbl,tmp,cap,field) \ +#define RMCTRL_OR_CAP(finaltbl,tmptbl,tmp,cap,field) \ tmp = ((finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] | tmptbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) & (0?cap##field)); \ - finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] &= ~(0?cap##field); \ + finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] &= ~(0?cap##field); \ finaltbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)] |= tmp; // Whether the command ID is a NULL command? // We allow NVXXXX_CTRL_CMD_NULL (0x00000000) as well as the // per-class NULL cmd ( _CATEGORY==0x00 and _INDEX==0x00 ) -#define RMCTRL_IS_NULL_CMD(cmd) ((cmd == NVXXXX_CTRL_CMD_NULL) || \ +#define RMCTRL_IS_NULL_CMD(cmd) ((cmd == NVXXXX_CTRL_CMD_NULL) || \ (FLD_TEST_DRF_NUM(XXXX, _CTRL_CMD, _CATEGORY, 0x00, cmd) && \ FLD_TEST_DRF_NUM(XXXX, _CTRL_CMD, _INDEX, 0x00, cmd))) @@ -141,11 +141,8 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC #define _RMCTRL_PREP_ACCESS_ARG(x) | NVBIT(NV_CONCATENATE(RS_ACCESS_, x)) #define ACCESS_RIGHTS(...) (0 NV_FOREACH_ARG_NOCOMMA(_RMCTRL_PREP_ACCESS_ARG, __VA_ARGS__)) -#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(ctrlFlags) \ - ( \ - (ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) && \ - !RMCFG_FEATURE_PHYSICAL_RM \ - ) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(ctrlFlags) \ + (ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) // // 'FLAGS' Attribute diff --git a/src/nvidia/inc/kernel/rmapi/mapping_list.h b/src/nvidia/inc/kernel/rmapi/mapping_list.h index fb15d680d6..c3ba29a911 100644 --- a/src/nvidia/inc/kernel/rmapi/mapping_list.h +++ b/src/nvidia/inc/kernel/rmapi/mapping_list.h @@ -163,7 +163,7 @@ NV_STATUS intermapDelDmaMapping (RsClient *, VirtualMemory * void intermapFreeDmaMapping (PCLI_DMA_MAPPING_INFO); CLI_DMA_MAPPING_INFO *intermapGetDmaMapping (VirtualMemory *pVirtualMemory, NvU64 dmaOffset, NvU32 gpuMask); -NvBool CliGetDmaMappingInfo (NvHandle, NvHandle, NvHandle, NvU64, NvU32, PCLI_DMA_MAPPING_INFO*); +NvBool CliGetDmaMappingInfo (RsClient *, NvHandle, NvHandle, NvU64, NvU32, PCLI_DMA_MAPPING_INFO*); void CliGetDmaMappingIterator (PCLI_DMA_MAPPING_INFO *, PCLI_DMA_MAPPING_INFO_ITERATOR, PNODE pDmaMappingList); void CliGetDmaMappingNext (PCLI_DMA_MAPPING_INFO *, PCLI_DMA_MAPPING_INFO_ITERATOR); diff --git a/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h b/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h index 1d80205ef7..7d272a39ea 100644 --- a/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h +++ b/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,6 +39,7 @@ typedef struct gpuSession *gpuSessionHandle; typedef struct gpuDevice *gpuDeviceHandle; typedef struct gpuAddressSpace *gpuAddressSpaceHandle; +typedef struct gpuTsg *gpuTsgHandle; typedef struct gpuChannel *gpuChannelHandle; typedef struct gpuObject *gpuObjectHandle; @@ -97,7 +98,11 @@ NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, NvLength pageCount, NvU64 pageSize); -NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace, +NV_STATUS nvGpuOpsTsgAllocate(gpuAddressSpaceHandle vaSpace, + const gpuTsgAllocParams *params, + gpuTsgHandle *tsgHandle); + +NV_STATUS nvGpuOpsChannelAllocate(const gpuTsgHandle tsgHandle, const gpuChannelAllocParams *params, gpuChannelHandle *channelHandle, gpuChannelInfo *channelInfo); @@ -105,6 +110,8 @@ NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace, NV_STATUS nvGpuOpsMemoryReopen(struct gpuAddressSpace *vaSpace, NvHandle hSrcClient, NvHandle hSrcAllocation, NvLength length, NvU64 *gpuOffset); +void nvGpuOpsTsgDestroy(struct gpuTsg *tsg); + void nvGpuOpsChannelDestroy(struct gpuChannel *channel); void nvGpuOpsMemoryFree(gpuAddressSpaceHandle vaSpace, @@ -196,7 +203,7 @@ NV_STATUS nvGpuOpsGetPmaObject(struct gpuDevice *device, void **pPma, const UvmPmaStatistics **pPmaPubStats); -NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo); +NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo, NvU32 accessCntrIndex); NV_STATUS nvGpuOpsDestroyAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo); @@ -272,4 +279,40 @@ NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel, NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device); +// Interface used for CCSL + +NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx, + gpuChannelHandle channel); +NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx); +NV_STATUS nvGpuOpsCcslLogDeviceEncryption(struct ccslContext_t *ctx, + NvU8 *decryptIv); +NV_STATUS nvGpuOpsCcslAcquireEncryptionIv(struct ccslContext_t *ctx, + NvU8 *encryptIv); +NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, + NvU8 direction); +NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsCcslEncryptWithIv(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsCcslDecrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *authTagBuffer); +NV_STATUS nvGpuOpsCcslSign(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer); +NV_STATUS nvGpuOpsQueryMessagePool(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum); + #endif /* _NV_GPU_OPS_H_*/ diff --git a/src/nvidia/inc/kernel/rmapi/param_copy.h b/src/nvidia/inc/kernel/rmapi/param_copy.h index 06c9aaa0c9..27115aa20b 100644 --- a/src/nvidia/inc/kernel/rmapi/param_copy.h +++ b/src/nvidia/inc/kernel/rmapi/param_copy.h @@ -77,12 +77,12 @@ typedef struct API_STATE RMAPI_PARAM_COPY; // this initialization, there is no need to make it return a status and // duplicate error checking. // -#define RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, theUserParams, numElems, sizeOfElem) \ - do { \ - RMAPI_PARAM_COPY_SET_MSG_TAG((paramCopy), __FUNCTION__); \ - (paramCopy).ppKernelParams = (void **) &(pKernelParams); \ - (paramCopy).pUserParams = (theUserParams); \ - (paramCopy).flags = RMAPI_PARAM_COPY_FLAGS_NONE; \ +#define RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, theUserParams, numElems, sizeOfElem) \ + do { \ + RMAPI_PARAM_COPY_SET_MSG_TAG((paramCopy), __FUNCTION__); \ + (paramCopy).ppKernelParams = (void **) &(pKernelParams); \ + (paramCopy).pUserParams = (theUserParams); \ + (paramCopy).flags = RMAPI_PARAM_COPY_FLAGS_NONE; \ (paramCopy).bSizeValid = portSafeMulU32((numElems), (sizeOfElem), &(paramCopy).paramsSize); \ } while(0) diff --git a/src/nvidia/inc/kernel/rmapi/rmapi.h b/src/nvidia/inc/kernel/rmapi/rmapi.h index 9930189bd3..8482a6ab2b 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi.h @@ -114,10 +114,16 @@ RM_API *rmapiGetInterface(RMAPI_TYPE rmapiType); // Flags for RM_API::Alloc #define RMAPI_ALLOC_FLAGS_NONE 0 #define RMAPI_ALLOC_FLAGS_SKIP_RPC NVBIT(0) +#define RMAPI_ALLOC_FLAGS_SERIALIZED NVBIT(1) // Flags for RM_API::Free #define RMAPI_FREE_FLAGS_NONE 0 +// Flags for RM_API RPC's +#define RMAPI_RPC_FLAGS_NONE 0 +#define RMAPI_RPC_FLAGS_COPYOUT_ON_ERROR NVBIT(0) +#define RMAPI_RPC_FLAGS_SERIALIZED NVBIT(1) + /** * Interface for performing operations through the RM API exposed to client * drivers. Interface provides consistent view to the RM API while abstracting @@ -129,16 +135,16 @@ struct _RM_API { // Allocate a resource with default security attributes and local pointers (no NvP64) NV_STATUS (*Alloc)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, void *pAllocParams); + NvHandle *phObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize); // Allocate a resource with default security attributes and local pointers (no NvP64) // and client assigned handle NV_STATUS (*AllocWithHandle)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle hObject, NvU32 hClass, void *pAllocParams); + NvHandle hObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize); // Allocate a resource NV_STATUS (*AllocWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequested, API_SECURITY_INFO *pSecInfo); // Free a resource with default security attributes @@ -303,7 +309,7 @@ rmapiEpilogue RM_API_CONTEXT *pContext ); -void +void rmapiInitLockInfo ( RM_API *pRmApi, @@ -315,7 +321,7 @@ rmapiInitLockInfo // RM locking modules: 24-bit group bitmask, 8-bit subgroup id // // Lock acquires are tagged with a RM_LOCK_MODULE_* in order to partition -// the acquires into groups, which allows read-only locks to be +// the acquires into groups, which allows read-only locks to be // enabled / disabled on a per-group basis (via apiLockMask and gpuLockMask // in OBJSYS.) // diff --git a/src/nvidia/inc/kernel/rmapi/rs_utils.h b/src/nvidia/inc/kernel/rmapi/rs_utils.h index 203d11b9eb..ab1a580ca8 100644 --- a/src/nvidia/inc/kernel/rmapi/rs_utils.h +++ b/src/nvidia/inc/kernel/rmapi/rs_utils.h @@ -46,11 +46,11 @@ MAKE_LIST(ClientHandlesList, NvHandle); #define serverutilGetDerived(pRmClient, hResource, ppBaseRes, type) \ - (clientGetResource(staticCast((pRmClient), RsClient), \ - (hResource), \ - classId(type), \ - (ppBaseRes)) != NV_OK) \ - ? NULL \ + (clientGetResource(staticCast((pRmClient), RsClient), \ + (hResource), \ + classId(type), \ + (ppBaseRes)) != NV_OK) \ + ? NULL \ : dynamicCast(*(ppBaseRes), type) /** @@ -119,9 +119,8 @@ NV_STATUS serverutilGenResourceHandle(NvHandle, NvHandle*); * Get a client pointer from a client handle without taking any locks. * * @param[in] hClient The client to acquire - * @param[out] ppClient Pointer to the RmClient */ -NV_STATUS serverutilGetClientUnderLock(NvHandle hClient, RmClient **ppClient); +RmClient *serverutilGetClientUnderLock(NvHandle hClient); /** * Get a client pointer from a client handle and lock it. diff --git a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h index fb5f5a25e5..2e55c178ad 100644 --- a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h +++ b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,8 +36,20 @@ #define VGPU_UUID_SIZE NVA081_VM_UUID_SIZE #define VGPU_MAX_GFID 64 #define VGPU_SIGNATURE_SIZE NVA081_VGPU_SIGNATURE_SIZE +#define VGPU_MAX_PLUGIN_CHANNELS 5 #define MAX_VGPU_DEVICES_PER_PGPU NVA081_MAX_VGPU_PER_PGPU +#define SET_GUEST_ID_ACTION_SET 0 +#define SET_GUEST_ID_ACTION_UNSET 1 + +typedef struct +{ + NvU8 action; + NvU32 vmPid; + VM_ID_TYPE vmIdType; + VM_ID guestVmId; +} SET_GUEST_ID_PARAMS; + /* This structure represents the vGPU type's attributes */ typedef struct { diff --git a/src/nvidia/inc/libraries/containers/btree.h b/src/nvidia/inc/libraries/containers/btree.h index a463e06081..a46caa7010 100644 --- a/src/nvidia/inc/libraries/containers/btree.h +++ b/src/nvidia/inc/libraries/containers/btree.h @@ -43,7 +43,7 @@ typedef struct NODE NvU64 keyStart; NvU64 keyEnd; - // private: + // private: NvBool isRed; // !IsRed == IsBlack struct NODE *parent; // tree links struct NODE *left; diff --git a/src/nvidia/inc/libraries/containers/list.h b/src/nvidia/inc/libraries/containers/list.h index 575c318564..5c95512568 100644 --- a/src/nvidia/inc/libraries/containers/list.h +++ b/src/nvidia/inc/libraries/containers/list.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -288,9 +288,11 @@ NvU32 listCount_IMPL(ListBase *pList); void *listInsertNew_IMPL(NonIntrusiveList *pList, void *pNext); void *listAppendNew_IMPL(NonIntrusiveList *pList); void *listPrependNew_IMPL(NonIntrusiveList *pList); -void *listInsertValue_IMPL(NonIntrusiveList *pList, void *pNext, void *pValue); -void *listAppendValue_IMPL(NonIntrusiveList *pList, void *pValue); -void *listPrependValue_IMPL(NonIntrusiveList *pList, void *pValue); +void *listInsertValue_IMPL(NonIntrusiveList *pList, + void *pNext, + const void *pValue); +void *listAppendValue_IMPL(NonIntrusiveList *pList, const void *pValue); +void *listPrependValue_IMPL(NonIntrusiveList *pList, const void *pValue); void listInsertExisting_IMPL(IntrusiveList *pList, void *pNext, void *pValue); void listAppendExisting_IMPL(IntrusiveList *pList, void *pValue); void listPrependExisting_IMPL(IntrusiveList *pList, void *pValue); diff --git a/src/nvidia/inc/libraries/containers/map.h b/src/nvidia/inc/libraries/containers/map.h index d7cccbee07..868b3bb36e 100644 --- a/src/nvidia/inc/libraries/containers/map.h +++ b/src/nvidia/inc/libraries/containers/map.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -261,7 +261,7 @@ NvU32 mapCount_IMPL(MapBase *pMap); NvU64 mapKey_IMPL(MapBase *pMap, void *pValue); void *mapInsertNew_IMPL(NonIntrusiveMap *pMap, NvU64 key); -void *mapInsertValue_IMPL(NonIntrusiveMap *pMap, NvU64 key, void *pValue); +void *mapInsertValue_IMPL(NonIntrusiveMap *pMap, NvU64 key, const void *pValue); NvBool mapInsertExisting_IMPL(IntrusiveMap *pMap, NvU64 key, void *pValue); void mapRemove_IMPL(NonIntrusiveMap *pMap, void *pValue); void mapRemoveIntrusive_IMPL(MapBase *pMap, void *pValue); diff --git a/src/nvidia/inc/libraries/containers/multimap.h b/src/nvidia/inc/libraries/containers/multimap.h index 004208ba23..c6c961c419 100644 --- a/src/nvidia/inc/libraries/containers/multimap.h +++ b/src/nvidia/inc/libraries/containers/multimap.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -60,33 +60,33 @@ extern "C" { * */ -#define MAKE_MULTIMAP(multimapTypeName, dataType) \ - typedef struct multimapTypeName##Leaf \ - { \ - dataType data; \ - MultimapNode node; \ - } multimapTypeName##Leaf; \ - MAKE_INTRUSIVE_MAP(multimapTypeName##Submap, multimapTypeName##Leaf, \ - node.submapNode); \ - MAKE_MAP(multimapTypeName##Supermap, multimapTypeName##Submap); \ - typedef union multimapTypeName##Iter \ - { \ - dataType *pValue; \ - MultimapIterBase iter; \ - } multimapTypeName##Iter; \ - typedef union multimapTypeName \ - { \ - CONT_TAG_TYPE(MultimapBase, dataType, multimapTypeName##Iter); \ - struct { MultimapBase base; } real; \ - struct \ - { \ - /* This field simply aligns map with the one in MultimapBase */ \ - CONT_VTABLE_FIELD(MultimapBase); \ - multimapTypeName##Supermap map; \ - } type; \ - CONT_TAG_NON_INTRUSIVE(dataType); \ +#define MAKE_MULTIMAP(multimapTypeName, dataType) \ + typedef struct multimapTypeName##Leaf \ + { \ + dataType data; \ + MultimapNode node; \ + } multimapTypeName##Leaf; \ + MAKE_INTRUSIVE_MAP(multimapTypeName##Submap, multimapTypeName##Leaf, \ + node.submapNode); \ + MAKE_MAP(multimapTypeName##Supermap, multimapTypeName##Submap); \ + typedef union multimapTypeName##Iter \ + { \ + dataType *pValue; \ + MultimapIterBase iter; \ + } multimapTypeName##Iter; \ + typedef union multimapTypeName \ + { \ + CONT_TAG_TYPE(MultimapBase, dataType, multimapTypeName##Iter); \ + struct { MultimapBase base; } real; \ + struct \ + { \ + /* This field simply aligns map with the one in MultimapBase */ \ + CONT_VTABLE_FIELD(MultimapBase); \ + multimapTypeName##Supermap map; \ + } type; \ + CONT_TAG_NON_INTRUSIVE(dataType); \ struct {char _[NV_OFFSETOF(multimapTypeName##Leaf, node)];} *nodeOffset; \ - struct {char _[sizeof(multimapTypeName##Submap)];} *submapSize; \ + struct {char _[sizeof(multimapTypeName##Submap)];} *submapSize; \ } multimapTypeName; #define DECLARE_MULTIMAP(multimapTypeName) \ @@ -214,7 +214,7 @@ struct MultimapBase multimapItemIterRange(pMultimap, \ multimapFirstItem(pMultimap), multimapLastItem(pMultimap)) -#define multimapItemIterRange(pMultimap, pFirst, pLast) \ +#define multimapItemIterRange(pMultimap, pFirst, pLast) \ CONT_ITER_RANGE(pMultimap, multimapItemIterRange_IMPL, \ CONT_CHECK_ARG(pMultimap, pFirst), CONT_CHECK_ARG(pMultimap, pLast), multimapIsValid_IMPL) @@ -254,8 +254,10 @@ void *multimapFindSubmapGEQ_IMPL(MultimapBase *pBase, NvU64 submapKey); void *multimapInsertItemNew_IMPL(MultimapBase *pBase, NvU64 submapKey, NvU64 itemKey); -void *multimapInsertItemValue_IMPL(MultimapBase *pBase, NvU64 submapKey, - NvU64 itemKey, void *pValue); +void *multimapInsertItemValue_IMPL(MultimapBase *pBase, + NvU64 submapKey, + NvU64 itemKey, + const void *pValue); void *multimapFindItem_IMPL(MultimapBase *pBase, NvU64 submapKey, NvU64 itemKey); diff --git a/src/nvidia/inc/libraries/containers/queue.h b/src/nvidia/inc/libraries/containers/queue.h index 4488cd80b9..bd234099be 100644 --- a/src/nvidia/inc/libraries/containers/queue.h +++ b/src/nvidia/inc/libraries/containers/queue.h @@ -26,7 +26,7 @@ #include "containers/type_safety.h" #include "nvtypes.h" #include "nvmisc.h" -#include "nvport/nvport.h" +#include "nvport/nvport.h" #include "utils/nvassert.h" #ifdef __cplusplus @@ -96,7 +96,7 @@ typedef enum circularQueueCapacity_IMPL(&((pQueue)->real)) #define queueIsEmpty(pQueue) \ - circularQueueIsEmpty_IMPL(&((pQueue)->real)) + circularQueueIsEmpty_IMPL(&((pQueue)->real)) #define queuePush(pQueue, pElements, numElements) \ circularQueuePush_IMPL(&(pQueue)->real, \ diff --git a/src/nvidia/inc/libraries/containers/ringbuf.h b/src/nvidia/inc/libraries/containers/ringbuf.h new file mode 100644 index 0000000000..60fa7a34b9 --- /dev/null +++ b/src/nvidia/inc/libraries/containers/ringbuf.h @@ -0,0 +1,169 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NV_CONTAINERS_RINGBUF_H +#define NV_CONTAINERS_RINGBUF_H + +#include "nvtypes.h" +#include "nvstatus.h" +#include "nvmisc.h" +#include "nvctassert.h" +#include "utils/nvassert.h" +#include "nvport/nvport.h" +#include "containers/type_safety.h" + +typedef struct RingBufBase +{ + NvU64 head; + NvU64 tail; + NvU64 logSz; + NvU8 *arr; +} RingBufBase; + +#define RINGBUF_ARRAY_SIZE(pBuf) (1llu << ((pBuf)->logSz)) + +#define RINGBUF_ARRAY_MASK(pBuf) (RINGBUF_ARRAY_SIZE(pBuf) - 1llu) + +#define MAKE_RINGBUF(containedType, outputType, logSz) \ + typedef struct outputType { \ + union { \ + RingBufBase base; \ + PORT_MEM_ALLOCATOR *pAllocator; \ + }; \ + union { \ + containedType elem[1llu << (logSz)]; \ + NvU8 lgSz[((logSz) < 64) ? (logSz) : -1]; /* Ternary to ensure we get CT error when logSz >= 64 */ \ + }; \ + } outputType + +#define MAKE_RINGBUF_DYNAMIC(containedType, outputType) \ + typedef union outputType { \ + struct { \ + RingBufBase base; \ + PORT_MEM_ALLOCATOR *pAllocator; \ + }; \ + containedType *elem; \ + } outputType + +#if NV_TYPEOF_SUPPORTED + +#define FOR_EACH_IN_RINGBUF(pBuf, idx, ptr) \ + { \ + (idx) = (pBuf)->base.tail; \ + while((idx) != (pBuf)->base.head) \ + { \ + (ptr) = (typeof(&((pBuf)->elem)[0])) &(pBuf)->base.arr[((idx) & RINGBUF_ARRAY_MASK(&((pBuf)->base))) * \ + sizeof(*((pBuf)->elem))]; \ + (idx)++; + +#else + +#define FOR_EACH_IN_RINGBUF(pBuf, idx, ptr) \ + { \ + (idx) = (pBuf)->base.tail; \ + while((idx) != (pBuf)->base.head) \ + { \ + (ptr) = (void *)&(pBuf)->base.arr[((idx) & RINGBUF_ARRAY_MASK(&((pBuf)->base))) * \ + sizeof(*((pBuf)->elem))]; \ + (idx)++; + +#endif // NV_TYPEOF_SUPPORTED + +#define FOR_EACH_END_RINGBUF() \ + } \ + } + + +#define ringbufConstructDynamic(pBuf, logSz, pAlloc) \ + (pBuf->pAllocator = pAlloc, ringbufConstructDynamic_IMPL(&((pBuf)->base), logSz, sizeof(*((pBuf)->elem)), pAlloc)) + +#define ringbufConstruct(pBuf) \ + ringbufConstruct_IMPL(&((pBuf)->base), sizeof((pBuf)->lgSz), (void*)((pBuf)->elem)) + +#define ringbufDestruct(pBuf) \ + ringbufDestruct_IMPL(&((pBuf)->base), ((void*)&((pBuf)->pAllocator)) == ((void*)&((pBuf)->base)) ? NULL : ((pBuf)->pAllocator) ) + +#if NV_TYPEOF_SUPPORTED + +#define ringbufPopN(pBuf, pMax) \ + (typeof(&((pBuf)->elem)[0])) ringbufPopN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), pMax) + +#define ringbufPeekN(pBuf, pMax) \ + (typeof(&((pBuf)->elem)[0])) ringbufPeekN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), pMax) + +#define ringbufAppendN(pBuf, pEles, num, bOver) \ + ringbufAppendN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), (NvU8*)pEles, num, bOver) + +#define ringbufPop(pBuf) \ + (typeof(&((pBuf)->elem)[0])) ringbufPop_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem))) + +#define ringbufPeek(pBuf) \ + (typeof(&((pBuf)->elem)[0])) ringbufPeek_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem))) + +#else + +#define ringbufPopN(pBuf, pMax) \ + (void *)ringbufPopN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), pMax) + +#define ringbufPeekN(pBuf, pMax) \ + (void *)ringbufPeekN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), pMax) + +#define ringbufAppendN(pBuf, pEles, num, bOver) \ + ringbufAppendN_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), (NvU8*)pEles, num, bOver) + +#define ringbufPop(pBuf) \ + (void *)ringbufPop_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem))) + +#define ringbufPeek(pBuf) \ + (void *)ringbufPeek_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem))) + +#endif // NV_TYPEOF_SUPPORTED + +#define ringbufAppend(pBuf, pEle, bOver) \ + ringbufAppend_IMPL(&((pBuf)->base), sizeof(*((pBuf)->elem)), (NvU8*)pEle, bOver) + +#define ringbufCurrentSize(pBuf) \ + ringbufCurrentSize_IMPL(&((pBuf)->base)) + +NvBool ringbufConstructDynamic_IMPL(RingBufBase *pBase, NvU64 logSz, NvU64 eleSz, PORT_MEM_ALLOCATOR *pAlloc); +NvBool ringbufConstruct_IMPL(RingBufBase *pBase, NvU64 logSz, void *arr); +void ringbufDestruct_IMPL(RingBufBase *pBase, void *alloc); +void *ringbufPopN_IMPL(RingBufBase *pBase, NvU64 eleSz, NvU64 *pMax); +void *ringbufPeekN_IMPL(RingBufBase *pBase, NvU64 eleSz, NvU64 *pMax); +NvBool ringbufAppendN_IMPL(RingBufBase *pBase, NvU64 eleSz, NvU8 *pEle, NvU64 num, NvBool bOverwrite); +NvU64 ringbufCurrentSize_IMPL(RingBufBase *pBase); + +static inline void *ringbufPeek_IMPL(RingBufBase *pBase, NvU64 eleSz) +{ + NvU64 max = 1; + return ringbufPeekN_IMPL(pBase, eleSz, &max); +} +static inline void *ringbufPop_IMPL(RingBufBase *pBase, NvU64 eleSz) +{ + NvU64 max = 1; + return ringbufPopN_IMPL(pBase, eleSz, &max); +} +static inline NvBool ringbufAppend_IMPL(RingBufBase *pBase, NvU64 eleSz, NvU8 *pEle, NvBool bOverwrite) +{ + return ringbufAppendN_IMPL(pBase, eleSz, pEle, 1, bOverwrite); +} +#endif diff --git a/src/nvidia/inc/libraries/containers/type_safety.h b/src/nvidia/inc/libraries/containers/type_safety.h index 1c847c3a9d..f5296be846 100644 --- a/src/nvidia/inc/libraries/containers/type_safety.h +++ b/src/nvidia/inc/libraries/containers/type_safety.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -147,9 +147,15 @@ typename T::IterType CONT_ITER_RANGE_INDEX elemType *elem; \ iterType *iter -// Argument check uses sizeof to get error message without runtime overhead. +// +// sizeof forces this expression to be evaluated at compile-time only. +// +// The ternary will always evalute true and passthrough the original pValue. +// However, the pointer comparison will generate a compile time warning if +// pValue type differs from the container's element type +// #define CONT_CHECK_ARG(pCont, pValue) \ - (sizeof((pCont)->elem = (pValue)) ? (pValue) : NULL) + (sizeof((pCont)->elem == (pValue)) ? (pValue) : NULL) // // Return checks are more problematic, but typeof is perfect when available. @@ -207,13 +213,13 @@ typename T::IterType CONT_ITER_RANGE_INDEX #else -#define CONT_VTABLE_DECL(contType, iterType) \ - typedef struct \ - { \ - void *(*checkRet)(void *pValue); \ - iterType (*iterRange)(contType *pCont, void *pFirst, void *pLast); \ - iterType (*iterRangeIndex)(contType *pCont, NvU64 first, NvU64 last);\ - } contType##_VTABLE; \ +#define CONT_VTABLE_DECL(contType, iterType) \ + typedef struct \ + { \ + void *(*checkRet)(void *pValue); \ + iterType (*iterRange)(contType *pCont, void *pFirst, void *pLast); \ + iterType (*iterRangeIndex)(contType *pCont, NvU64 first, NvU64 last); \ + } contType##_VTABLE; \ #define CONT_VTABLE_DEFN(contType, contIterRange, contIterRangeIndex) \ static const contType##_VTABLE g_##contType##_VTABLE = \ @@ -223,12 +229,12 @@ typename T::IterType CONT_ITER_RANGE_INDEX contIterRangeIndex, \ } -#define CONT_VTABLE_TAG(contType, elemType, iterType) \ - const struct \ - { \ - elemType *(*checkRet)(void *pValue); \ - iterType (*iterRange)(contType *pCont, void *pFirst, void *pLast); \ - iterType (*iterRangeIndex)(contType *pCont, NvU64 first, NvU64 last);\ +#define CONT_VTABLE_TAG(contType, elemType, iterType) \ + const struct \ + { \ + elemType *(*checkRet)(void *pValue); \ + iterType (*iterRange)(contType *pCont, void *pFirst, void *pLast); \ + iterType (*iterRangeIndex)(contType *pCont, NvU64 first, NvU64 last); \ } *vtable #define CONT_VTABLE_FIELD(contType) const contType##_VTABLE *vtable diff --git a/src/nvidia/inc/libraries/containers/vector.h b/src/nvidia/inc/libraries/containers/vector.h new file mode 100644 index 0000000000..039dcf7c3c --- /dev/null +++ b/src/nvidia/inc/libraries/containers/vector.h @@ -0,0 +1,201 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NV_CONTAINERS_VECTOR_H +#define NV_CONTAINERS_VECTOR_H 1 + +#include "containers/type_safety.h" +#include "nvtypes.h" +#include "nvmisc.h" +#include "nvport/nvport.h" +#include "utils/nvassert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup NV_CONTAINERS_VECTOR Vector + * + * @brief Sequence of user-defined values. + * + * @details Order of values is not necessarily increasing or sorted, but order is + * preserved across mutation. Please see + * https://en.wikipedia.org/wiki/Sequence for a formal definition. + * + * - Time Complexity: + * * Operations are \b O(1), + * * Unless stated otherwise. + * + * - Memory Usage: + * * \b O(N) memory is required for N values. + * * See @ref mem-ownership for further details. + * + * - Synchronization: + * * \b None. The container is not thread-safe. + * * Locking must be handled by the user if required. + * + */ + +#define MAKE_VECTOR(vectTypeName, dataType) \ + typedef union vectTypeName##Iter \ + { \ + dataType *pValue; \ + VectorIterBase iter; \ + } vectTypeName##Iter; \ + typedef union vectTypeName \ + { \ + VectorWrapper real; \ + CONT_TAG_TYPE(Vector, dataType, vectTypeName##Iter); \ + CONT_TAG_NON_INTRUSIVE(dataType); \ + } vectTypeName + +#define DECLARE_VECTOR(vectTypeName) \ + typedef union vectTypeName##Iter vectTypeName##Iter; \ + typedef union vectTypeName vectTypeName + +typedef struct Vector Vector; +typedef struct VectorIterBase VectorIterBase; +typedef struct VectorWrapper VectorWrapper; + +/** + * Note that the vector values are NvU32 and Iterator values are NvS32, + * so in case there is a need for a vector with over ~2 billion entries + * this might not work. + */ +struct VectorIterBase +{ + void *pValue; + Vector *pVector; + NvS32 nextIndex; + NvS32 prevIndex; + NvS32 firstIndex; + NvS32 lastIndex; + NvBool bForward; +#if PORT_IS_CHECKED_BUILD + NvU32 versionNumber; +#endif +}; + +VectorIterBase vectIterRange_IMPL(Vector *pVector, void *pFirst, void *pLast); +CONT_VTABLE_DECL(Vector, VectorIterBase); + +struct Vector +{ + CONT_VTABLE_FIELD(Vector); + void *pHead; + PORT_MEM_ALLOCATOR *pAllocator; + NvU32 valueSize; + NvU32 capacity; + NvU32 size; +#if PORT_IS_CHECKED_BUILD + NvU32 versionNumber; +#endif +}; + +struct VectorWrapper +{ + Vector base; +}; + +#define vectInit(pVector, pAllocator, capacity) \ + vectInit_IMPL(&((pVector)->real.base), \ + pAllocator, \ + capacity, \ + sizeof(*(pVector)->valueSize)) +#define vectDestroy(pVector) vectDestroy_IMPL(&((pVector)->real.base)) +#define vectCount(pVector) vectCount_IMPL(&((pVector)->real.base)) +#define vectCapacity(pVector) vectCapacity_IMPL(&((pVector)->real.base)) +#define vectIsEmpty(pVector) vectIsEmpty_IMPL(&((pVector)->real.base)) +#define vectAt(pVector, index) \ + CONT_CAST_ELEM((pVector), \ + vectAt_IMPL(&((pVector)->real.base), index), \ + vectIsValid_IMPL) +#define vectInsert(pVector, index, pValue) \ + CONT_CAST_ELEM((pVector), \ + vectInsert_IMPL(&(pVector)->real.base, \ + index, \ + CONT_CHECK_ARG(pVector, pValue)), \ + vectIsValid_IMPL) +#define vectRemove(pVector, index) \ + vectRemove_IMPL(&((pVector)->real.base), index) +#define vectClear(pVector) vectDestroy(pVector) +#define vectAppend(pVector, pValue) \ + CONT_CAST_ELEM((pVector), \ + vectAppend_IMPL(&(pVector)->real.base, \ + CONT_CHECK_ARG(pVector, pValue)), \ + vectIsValid_IMPL) +#define vectPrepend(pVector, pValue) \ + CONT_CAST_ELEM((pVector), \ + vectPrepend_IMPL(&(pVector)->real.base, \ + CONT_CHECK_ARG(pVector, pValue)), \ + vectIsValid_IMPL) +#define vectReserve(pVector, size) \ + vectReserve_IMPL(&((pVector)->real.base), size) +#define vectTrim(pVector, size) vectTrim_IMPL(&((pVector)->real.base), size) + +#define vectIterAll(pVector) \ + vectIterRangeIndex(pVector, 0, vectCount(pVector) - 1) +#define vectIterRangeIndex(pVector, firstIndex, lastIndex) \ + vectIterRange(pVector, \ + vectAt(pVector, firstIndex), \ + vectAt(pVector, lastIndex)) +#define vectIterRange(pVector, pFirst, pLast) \ + CONT_ITER_RANGE(pVector, \ + &vectIterRange_IMPL, \ + CONT_CHECK_ARG(pVector, pFirst), \ + CONT_CHECK_ARG(pVector, pLast), \ + vectIsValid_IMPL) +#define vectIterNext(pIterator) \ + vectIterNext_IMPL(&((pIterator)->iter), (void **)&(pIterator)->pValue) +#define vectIterPrev(pIterator) \ + vectIterPrev_IMPL(&((pIterator)->iter), (void **)&(pIterator)->pValue) + +NV_STATUS vectInit_IMPL(Vector *pVector, + PORT_MEM_ALLOCATOR *pAllocator, + NvU32 capacity, + NvU32 valueSize); +void vectDestroy_IMPL(Vector *pVector); +NvU32 vectCount_IMPL(Vector *pVector); +NvU32 vectCapacity_IMPL(Vector *pVector); +NvBool vectIsEmpty_IMPL(Vector *pVector); + +void *vectAt_IMPL(Vector *pVector, NvU32 index); +void *vectInsert_IMPL(Vector *pVector, NvU32 index, const void *pData); +void vectRemove_IMPL(Vector *pVector, NvU32 index); +void *vectAppend_IMPL(Vector *pVector, const void *pData); +void *vectPrepend_IMPL(Vector *pvector, const void *pData); + +NV_STATUS vectReserve_IMPL(Vector *pVector, NvU32 n); +NV_STATUS vectTrim_IMPL(Vector *pvector, NvU32 n); + +VectorIterBase vectIterRange_IMPL(Vector *pVector, void *pFirst, void *pLast); +NvBool vectIterNext_IMPL(VectorIterBase *pIter, void **ppValue); +NvBool vectIterPrev_IMPL(VectorIterBase *pIter, void **ppValue); + +NvBool vectIsValid_IMPL(void *pVect); + +#ifdef __cplusplus +} +#endif + +#endif // NV_CONTAINERS_VECTOR_H diff --git a/src/nvidia/inc/libraries/field_desc.h b/src/nvidia/inc/libraries/field_desc.h index 92b7ed7ab8..47d689228d 100644 --- a/src/nvidia/inc/libraries/field_desc.h +++ b/src/nvidia/inc/libraries/field_desc.h @@ -175,17 +175,17 @@ struct NV_FIELD_BOOL #define BEGIN_DISCONTIG_FIELD_DESC64(pField) \ pField->regionCount = 0; -#define DRF_DISCONTIG_FIELD_DESC64(pField, drf) \ - do { \ +#define DRF_DISCONTIG_FIELD_DESC64(pField, drf) \ + do { \ NV_ASSERT_CHECKED_PRECOMP(pField->regionCount < NV_FIELD_DESC64_MAX_DISCONTIG_REGIONS); \ - (pField)->regions[pField->regionCount].maskPos = DRF_SHIFTMASK64(drf); \ - (pField)->regions[pField->regionCount].width = (1?drf) - (0?drf) + 1; \ - (pField)->regions[pField->regionCount].shift = DRF_SHIFT64(drf); \ - (pField)->regions[pField->regionCount].offset = DRF_OFFSET64(drf); \ - pField->regionCount ++; \ + (pField)->regions[pField->regionCount].maskPos = DRF_SHIFTMASK64(drf); \ + (pField)->regions[pField->regionCount].width = (1?drf) - (0?drf) + 1; \ + (pField)->regions[pField->regionCount].shift = DRF_SHIFT64(drf); \ + (pField)->regions[pField->regionCount].offset = DRF_OFFSET64(drf); \ + pField->regionCount ++; \ } while(0); -#define END_FIELD_DESC64_DISCONTIGUOUS(pField) +#define END_FIELD_DESC64_DISCONTIGUOUS(pField) #define INIT_FIELD_ENUM(pEnum, drf, count, pEntries) \ diff --git a/src/nvidia/inc/libraries/mmu/gmmu_fmt.h b/src/nvidia/inc/libraries/mmu/gmmu_fmt.h index 59d7bbb8f6..31ec42498c 100644 --- a/src/nvidia/inc/libraries/mmu/gmmu_fmt.h +++ b/src/nvidia/inc/libraries/mmu/gmmu_fmt.h @@ -411,7 +411,7 @@ struct GMMU_FMT_PDE * Should be always the same as version in GMMU_FMT above. */ NvU32 version; - + /*! * Aperture field indicating which physical address space the sublevel resides. */ @@ -441,7 +441,7 @@ struct GMMU_FMT_PDE * TODO: Wiki link to explain arch differences. */ NV_FIELD_BOOL fldVolatile; - + /*! * PDE_PCF field for V3 format. */ diff --git a/src/nvidia/inc/libraries/mmu/mmu_fmt.h b/src/nvidia/inc/libraries/mmu/mmu_fmt.h index c7c52c2fa1..6b687eb6b4 100644 --- a/src/nvidia/inc/libraries/mmu/mmu_fmt.h +++ b/src/nvidia/inc/libraries/mmu/mmu_fmt.h @@ -41,7 +41,7 @@ extern "C" { // // Separate files for the types as they're included by CTRL definitions -// +// #include "mmu_fmt_types.h" /*! @@ -105,7 +105,7 @@ const MMU_FMT_LEVEL *mmuFmtGetNextLevel( /*! * Return a level description from the format. Used for Verif. - * + * * @returns const char* string description of the level. */ const char* diff --git a/src/nvidia/inc/libraries/mmu/mmu_walk.h b/src/nvidia/inc/libraries/mmu/mmu_walk.h index 0c64027e45..7aba34f0a4 100644 --- a/src/nvidia/inc/libraries/mmu/mmu_walk.h +++ b/src/nvidia/inc/libraries/mmu/mmu_walk.h @@ -152,7 +152,7 @@ typedef enum /** * No valid aligned 4K PTE state for a 64K PTE * 64K big PTE state indicating that there is no valid 4K aligned PTEs - * + * * @note This is not supported pre Volta. */ MMU_WALK_FILL_NV4K, @@ -376,7 +376,7 @@ MmuWalkCBCopyEntries * copied. * @param[in] tableSize Size of the current level of PD/PT, in * entries. The offsets into the staging - * buffer are the entry indices taken + * buffer are the entry indices taken * modulo tableSize. * @param[in] entrySize Size of each entry, in bytes */ @@ -509,7 +509,7 @@ struct MMU_MAP_TARGET * Callback to map the batch of entries. */ MmuWalkCBMapNextEntries *MapNextEntries; - + /*! * Page array granularity of the physical target memory */ @@ -669,7 +669,7 @@ mmuWalkReleaseEntries * * Traverse the walker and rewrite the PDEs from the SW state. * This won't trigger any new PDE allocations or state change. - * + * * This call won't affect the PTEs. If needed, support can be added later. * * The VA range must be aligned to the MMU's smallest page size and @@ -750,11 +750,11 @@ mmuWalkGetPageLevelInfo NvU32 *pMemSize ); -/*! +/*! * Force frees all page level instances. We may have to force free page levels - * in case of surprise removal. In the surprise removal case, we may end up + * in case of surprise removal. In the surprise removal case, we may end up * with many failed unmappings once the GPU is off the bus. This might leave - * some of the MMU_WALK_LEVEL and MMU_WALK_LEVEL_INST objects to be in an + * some of the MMU_WALK_LEVEL and MMU_WALK_LEVEL_INST objects to be in an * allocated state. This function just iterates over the level instances at * each level and force frees everything ignoring any outstanding valid, sparse * and reserved entries.. diff --git a/src/nvidia/inc/libraries/nvlog/nvlog.h b/src/nvidia/inc/libraries/nvlog/nvlog.h index c7be921198..6983d44cb2 100644 --- a/src/nvidia/inc/libraries/nvlog/nvlog.h +++ b/src/nvidia/inc/libraries/nvlog/nvlog.h @@ -188,7 +188,7 @@ NV_STATUS nvlogGetBufferSnapshot(NVLOG_BUFFER_HANDLE hBuffer, NvU8 *pDest, NvU32 /** * @brief Dumps all logs into the the kernel print log * - * @note this will write to the log even if all other prints are disabled, + * @note this will write to the log even if all other prints are disabled, * including external release builds. The output will be base64 encoded and * not decodable without the database, and pollute the logs. Use with caution. * diff --git a/src/nvidia/inc/libraries/nvlog/nvlog_printf.h b/src/nvidia/inc/libraries/nvlog/nvlog_printf.h index aa5fb9bc60..43a8fac19a 100644 --- a/src/nvidia/inc/libraries/nvlog/nvlog_printf.h +++ b/src/nvidia/inc/libraries/nvlog/nvlog_printf.h @@ -60,12 +60,12 @@ extern "C" { * * @param tag - An identifier to help with offline filtering. Doesn't need to * be defined anywhere. - * @param route - 8bit mask of buffers the print will be routed to. + * @param route - 8bit mask of buffers the print will be routed to. * Use NVLOG_BUFFER_XXX constants * @param level - Level at which to print. Calls with level < NVLOG_LEVEL will * be compiled out. * @param format - printf-like format string - * @param ... - printf arguments + * @param ... - printf arguments */ #define NVLOG_PRINTF(tag, route, level, format, ...) _NVLOG_PRINTF(tag, route, level, format, __VA_ARGS__) diff --git a/src/nvidia/inc/libraries/nvoc/object.h b/src/nvidia/inc/libraries/nvoc/object.h index cd1231b1e0..8a45254b6b 100644 --- a/src/nvidia/inc/libraries/nvoc/object.h +++ b/src/nvidia/inc/libraries/nvoc/object.h @@ -107,10 +107,10 @@ NVOC_PREFIX(obj) class Object Object *objGetDirectParent(Object *pObj); }; -// -// IP versioning definitions are temporary until NVOC halspec support is -// finished. -// +// +// IP versioning definitions are temporary until NVOC halspec support is +// finished. +// // IP_VERSION format as defined by the hardware engines. // A _MAJOR value of 0 means the object has no version number. // diff --git a/src/nvidia/inc/libraries/nvoc/prelude.h b/src/nvidia/inc/libraries/nvoc/prelude.h index a76ba16157..74f16e2bc9 100644 --- a/src/nvidia/inc/libraries/nvoc/prelude.h +++ b/src/nvidia/inc/libraries/nvoc/prelude.h @@ -170,7 +170,7 @@ __nvoc_objCreateDynamic((ppNewObj), staticCast((pParent), Dynamic), \ (pClassInfo), (NVOC_OBJ_CREATE_FLAGS_NONE), ##__VA_ARGS__) #define objCreateDynamicWithFlags(ppNewObj, pParent, pClassInfo, flags, ...) \ - __nvoc_objCreateDynamic((ppNewObj), staticCast((pParent), Dynamic), \ + __nvoc_objCreateDynamic((ppNewObj), staticCast((pParent), Dynamic), \ (pClassInfo), (flags), ##__VA_ARGS__) /*! diff --git a/src/nvidia/inc/libraries/nvport/cpu.h b/src/nvidia/inc/libraries/nvport/cpu.h index ac95ec023e..556df1df81 100644 --- a/src/nvidia/inc/libraries/nvport/cpu.h +++ b/src/nvidia/inc/libraries/nvport/cpu.h @@ -107,7 +107,7 @@ typedef struct PORT_CPU_INTEL_X86_FEATURES NvU32 SDBG : 1; /**< IA32_DEBUG_INTERFACE MSR for silicon debug.*/ NvU32 FMA : 1; /**< FMA extensions using YMM state.*/ NvU32 CMPXCHG16B : 1; /**< CMPXCHG8B/CMPXCHG16B Compare and Exchange Bytes*/ - NvU32 xTPRUpdateControl : 1; /** supports changing + NvU32 xTPRUpdateControl : 1; /** supports changing IA32_MISC_ENABLE[bit 23].*/ NvU32 PDCM : 1; /**< Perfmon and Debug Capability: supports the performance and debug feature indication MSR IA32_PERF_CAPABILITIES.*/ @@ -139,7 +139,7 @@ typedef struct PORT_CPU_INTEL_X86_FEATURES NvU32 DE : 1; /**< Debugging Extensions.*/ NvU32 PSE : 1; /**< Page Size Extension.*/ NvU32 TSC : 1; /**< Time Stamp Counter.*/ - NvU32 MSR : 1; /**< Model Specific Registers RDMSR and WRMSR + NvU32 MSR : 1; /**< Model Specific Registers RDMSR and WRMSR Instructions.*/ NvU32 PAE : 1; /**< Physical Address Extension.*/ NvU32 MCE : 1; /**< Machine Check Exception.*/ @@ -180,7 +180,7 @@ typedef enum PORT_CPU_INTEL_FAMILY /** * @brief Enum representing Intel family 6 processor model information. - * + * */ typedef enum PORT_CPU_INTEL_FAMILY_6_MODEL { @@ -237,19 +237,19 @@ typedef struct PORT_CPU_INTEL_TPM_FEATURES /// @{ NvU32 DTS : 1; /**< Digital Temperature Sensor is supported if set.*/ NvU32 IntelTurboBoost : 1; /**< Intel Turbo Boost Technology available.*/ - NvU32 ARAT : 1; /**< APIC-Timer-always-running feature is supported + NvU32 ARAT : 1; /**< APIC-Timer-always-running feature is supported if set.*/ - NvU32 PLN : 1; /**< Power limit notification controls are supported + NvU32 PLN : 1; /**< Power limit notification controls are supported if set.*/ - NvU32 ECMD : 1; /**< Clock modulation duty cycle extension is supported + NvU32 ECMD : 1; /**< Clock modulation duty cycle extension is supported if set.*/ NvU32 PTM : 1; /**< Package thermal management is supported if set.*/ - NvU32 HWP : 1; /**< HWP base registers (IA32_PM_ENABLE[bit 0], - IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) + NvU32 HWP : 1; /**< HWP base registers (IA32_PM_ENABLE[bit 0], + IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.*/ - NvU32 HWPNotification : 1; /**< IA32_HWP_INTERRUPT MSR is supported + NvU32 HWPNotification : 1; /**< IA32_HWP_INTERRUPT MSR is supported if set.*/ - NvU32 HWPActivityWindow : 1; /**< IA32_HWP_REQUEST[bits 41:32] is + NvU32 HWPActivityWindow : 1; /**< IA32_HWP_REQUEST[bits 41:32] is supported if set.*/ NvU32 HWPEPP : 1; /**< HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.*/ @@ -263,13 +263,13 @@ typedef struct PORT_CPU_INTEL_TPM_FEATURES if set.*/ NvU32 HWPPECI : 1; /**< HWP PECI override is supported if set.*/ NvU32 FLEXHWP : 1; /**< Flexible HWP is supported if set.*/ - NvU32 FAM : 1; /**< Fast access mode for the IA32_HWP_REQUEST MSR is + NvU32 FAM : 1; /**< Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.*/ NvU32 ILPHWPRequest : 1; /**< Ignoring Idle Logical Processor HWP request is supported if set.*/ NvU32 NoOfInterruptThresholdsInDTS : 4; /**< Number of Interrupt Thresholds in Digital Thermal Sensor.*/ - NvU32 HCFC : 1; /**< Hardware Coordination Feedback Capability + NvU32 HCFC : 1; /**< Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of the @@ -283,7 +283,7 @@ typedef struct PORT_CPU_INTEL_TPM_FEATURES } PORT_CPU_INTEL_TPM_FEATURES; /** - * @brief Structure representing Intel Processor's Architecture Performance + * @brief Structure representing Intel Processor's Architecture Performance * monitering features broken down into individual bit fields. */ typedef struct PORT_CPU_INTEL_ARCH_PERF_MONITOR @@ -296,10 +296,10 @@ typedef struct PORT_CPU_INTEL_ARCH_PERF_MONITOR NvU32 bitWidthOfGPCounters; /** Bit width of general-purpose, performance monitoring counter.*/ NvU32 coreCycleEvent : 1; /**< Core cycle event available if 1.*/ - NvU32 instructionRetiredEvent : 1; /**< Instruction retired event + NvU32 instructionRetiredEvent : 1; /**< Instruction retired event available if 1.*/ NvU32 referenceCycelEvent : 1; /**< Reference cycles event available if 1.*/ - NvU32 lastLevelCacheRefEvent : 1; /**< Last-level cache reference event + NvU32 lastLevelCacheRefEvent : 1; /**< Last-level cache reference event available if 1.*/ NvU32 lastLevelCacheMissEvent : 1; /**< Last-level cache misses event not available if 1.*/ @@ -309,8 +309,8 @@ typedef struct PORT_CPU_INTEL_ARCH_PERF_MONITOR not available if 1.*/ NvU32 noOfFixedFuncPerfCounters; /**< Number of fixed-function performance counters (if Version ID > 1).*/ - NvU32 bitWidthOfFixedFuncPerfCounters; /**< Bit width of fixed-function - performance counters + NvU32 bitWidthOfFixedFuncPerfCounters; /**< Bit width of fixed-function + performance counters (if Version ID > 1).*/ /// @} } PORT_CPU_INTEL_ARCH_PERF_MONITOR; @@ -335,7 +335,7 @@ typedef struct PORT_CPU_INTEL PORT_CPU_INTEL_X86_FEATURES features; /**< General Features.*/ PORT_CPU_INTEL_TPM_FEATURES tpmFeatures; /**< Thermal and Power Management Features.*/ - PORT_CPU_INTEL_ARCH_PERF_MONITOR archPerfMonitor; /**< Architecture + PORT_CPU_INTEL_ARCH_PERF_MONITOR archPerfMonitor; /**< Architecture Performance Monitoring Features.*/ /// @} @@ -526,7 +526,7 @@ NV_STATUS portCpuExCpuId(NvU32* pCpuInfo, NvU32 functionId, /** * @brief Retrieve the current value and frequency of the performance counter * - * @param[out] pFreq A pointer to a variable to which this routine writes the + * @param[out] pFreq A pointer to a variable to which this routine writes the * performance counter frequency, in ticks per second. * This parameter is optional and can be NULL if the caller * does not need the counter frequency value. diff --git a/src/nvidia/inc/libraries/nvport/crypto.h b/src/nvidia/inc/libraries/nvport/crypto.h index 28c4bc079f..adda6c9c77 100644 --- a/src/nvidia/inc/libraries/nvport/crypto.h +++ b/src/nvidia/inc/libraries/nvport/crypto.h @@ -46,21 +46,21 @@ * * True random numbers are generated from hardware, and as such are completely * nondeterministic. There is no support for setting a seed, and you can expect - * the output to always be different. Unlike pseudorandom numbers, true random + * the output to always be different. Unlike pseudorandom numbers, true random * output will always vary across different platforms. * * These numbers are suitable for security sensitive and cryptography operations. * * In case of kernelmode code, the entropy pool will contain bits that are not * available to usermode clients. As a consequence, a usermode client cannot - * deplete the entropy pool to lower the security + * deplete the entropy pool to lower the security * - * @note Unless ending with the "-Blocking" suffix, all functions are - * non-blocking. With regards to True Random numbers, this has a consequence + * @note Unless ending with the "-Blocking" suffix, all functions are + * non-blocking. With regards to True Random numbers, this has a consequence * that if there are insufficient bits in the entropy pool, they will be used - * to seed a custom PRNG which will provide the final output. A blocking + * to seed a custom PRNG which will provide the final output. A blocking * version of some functions may be available as an extended function. - * + * * @note As a general rule, you should always use the non-blocking version of a * function, unless ALL the following conditions are satisfied: * - First time booting a clean OS @@ -114,8 +114,8 @@ typedef struct PORT_CRYPTO_PRNG PORT_CRYPTO_PRNG; * @warning These objects are not Cryptographically Secure, and thus not * appropriate for any security sensitive operations. Use "True" random instead. * - * The same seed will always result in the same sequence returned by - * @ref portCryptoPseudoRandomGeneratorGetU32, + * The same seed will always result in the same sequence returned by + * @ref portCryptoPseudoRandomGeneratorGetU32, * @ref portCryptoPseudoRandomGeneratorGetU64 and * @ref portCryptoPseudoRandomGeneratorFillBuffer. This behavior is consistent * across all platforms. The following code will always print the same thing: @@ -131,10 +131,10 @@ typedef struct PORT_CRYPTO_PRNG PORT_CRYPTO_PRNG; * * @return NULL if the construction failed, a PRNG object otherwise. * - */ -PORT_CRYPTO_PRNG *portCryptoPseudoRandomGeneratorCreate(NvU64 seed); + */ +PORT_CRYPTO_PRNG *portCryptoPseudoRandomGeneratorCreate(NvU64 seed); /** - * @brief Destroys an object created with + * @brief Destroys an object created with * @ref portCryptoPseudoRandomGeneratorCreate * */ @@ -153,7 +153,7 @@ NvU32 portCryptoPseudoRandomGeneratorGetU32(PORT_CRYPTO_PRNG *pPrng); * @brief Returns a 64bit pseudorandom number from a given PRNG. * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomGetU64 instead. + * sensitive operations. Use @ref portCryptoExTrueRandomGetU64 instead. * * @param [in] pPrng - Generator object. If NULL, the default one will be used * @@ -164,7 +164,7 @@ NvU64 portCryptoPseudoRandomGeneratorGetU64(PORT_CRYPTO_PRNG *pPrng); * PRNG * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomFillBuffer instead. + * sensitive operations. Use @ref portCryptoExTrueRandomFillBuffer instead. * * @param [in] pPrng - Generator object. If NULL, the default one will be used * @@ -177,7 +177,7 @@ NV_STATUS portCryptoPseudoRandomGeneratorFillBuffer(PORT_CRYPTO_PRNG *pPrng, NvU /** * @brief Sets the PRNG seed of the global generator * - * The same seed will always result in the same sequence returned by + * The same seed will always result in the same sequence returned by * @ref portCryptoPseudoRandomGetU32, @ref portCryptoPseudoRandomGetU64 and * @ref portCryptoPseudoRandomFillBuffer. This behavior is consistent across * all platforms. The following code will print the same thing on all platforms: @@ -197,7 +197,7 @@ void portCryptoPseudoRandomSetSeed(NvU64 seed); * a NULL generator object. * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomGetU32 instead. + * sensitive operations. Use @ref portCryptoExTrueRandomGetU32 instead. * */ NvU32 portCryptoPseudoRandomGetU32(void); @@ -208,7 +208,7 @@ NvU32 portCryptoPseudoRandomGetU32(void); * a NULL generator object. * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomGetU64 instead. + * sensitive operations. Use @ref portCryptoExTrueRandomGetU64 instead. * */ NvU64 portCryptoPseudoRandomGetU64(void); @@ -219,7 +219,7 @@ NvU64 portCryptoPseudoRandomGetU64(void); * with a NULL generator object. * * @warning The numbers generated in this way are not appropriate for security - * sensitive operations. Use @ref portCryptoExTrueRandomFillBuffear instead. + * sensitive operations. Use @ref portCryptoExTrueRandomFillBuffear instead. * * @return NV_OK if successful; * NV_ERR_INVALID_POINTER if pBuffer is NULL; @@ -276,8 +276,8 @@ NV_STATUS portCryptoHashMD5HexStringToBinary(const char *pHexStr, NvU8 pBinary[1 * * @note This function does not block, but rather combines the bits from the * entropy pool with a PRNG to produce a random output of desired width. - * This is considered safe for most cryptographic applications. You can use - * @ref portCryptoExTrueRandomGetU32Blocking for a guaranteed high entropy output. + * This is considered safe for most cryptographic applications. You can use + * @ref portCryptoExTrueRandomGetU32Blocking for a guaranteed high entropy output. */ NvU32 portCryptoExTrueRandomGetU32(void); #define portCryptoExTrueRandomGetU32_SUPPORTED 0 @@ -285,9 +285,9 @@ NvU32 portCryptoExTrueRandomGetU32(void); * @brief Returns a 64bit random number * * @note This function does not block, but rather combines the bits from the - * entropy pool with a PRNG to produce a random output of desired width. + * entropy pool with a PRNG to produce a random output of desired width. * This is considered safe for most cryptographic applications. You can use - * @ref portCryptoExTrueRandomGetU64Blocking for a guaranteed high entropy output. + * @ref portCryptoExTrueRandomGetU64Blocking for a guaranteed high entropy output. */ NvU64 portCryptoExTrueRandomGetU64(void); #define portCryptoExTrueRandomGetU64_SUPPORTED 0 @@ -296,9 +296,9 @@ NvU64 portCryptoExTrueRandomGetU64(void); * * @note This function does not block, but rather combines the bits from the * entropy pool with a PRNG to produce a random output of desired width. This is - * considered safe for most cryptographic applications. You can use + * considered safe for most cryptographic applications. You can use * @ref portCryptoExTrueRandomFillBufferBlocking for a guaranteed high entropy - * output. + * output. * * @return NV_OK if successful; * NV_ERR_INVALID_POINTER if pBuffer is NULL; diff --git a/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h b/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h index de7a2a445d..94bbe43114 100644 --- a/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h +++ b/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,24 @@ #ifndef _NVPORT_MEMORY_INTERNAL_H_ #define _NVPORT_MEMORY_INTERNAL_H_ +#define portMemExTrackingGetActiveStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER +#define portMemExTrackingGetTotalStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER +#define portMemExTrackingGetPeakStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER +#define portMemExTrackingGetNext_SUPPORTED \ + (PORT_MEM_TRACK_USE_FENCEPOSTS & PORT_MEM_TRACK_USE_ALLOCLIST) +#define portMemExTrackingGetHeapSize_SUPPORTED (NVOS_IS_LIBOS) +// +// portMemExTrackingGetAllocUsableSize provides higher-fidelity tracking at the +// expense of higher runtime overhead, due to additional function calls in the +// portMemAlloc path. It is only enabled by default in debug ("checked") builds for +// this reason. +// +#define portMemExTrackingGetAllocUsableSize_SUPPORTED (PORT_IS_CHECKED_BUILD && NVOS_IS_LIBOS) + +#define portMemExValidate_SUPPORTED 0 +#define portMemExValidateAllocations_SUPPORTED 0 +#define portMemExFreeAll_SUPPORTED 0 + /** @brief Untracked paged memory allocation, platform specific */ void *_portMemAllocPagedUntracked(NvLength lengthBytes); /** @brief Untracked nonpaged memory allocation, platform specific */ @@ -45,7 +63,7 @@ void _portMemAllocatorFree(PORT_MEM_ALLOCATOR *pAlloc, void *pMem); #if PORT_MEM_TRACK_USE_LIMIT /** @brief Initialize per VF tracking limit **/ -void portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvU64 heapSize, NvBool bLimitEnabled); +void portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvLength limit, NvBool bLimitEnabled); #endif typedef struct PORT_MEM_COUNTER @@ -61,7 +79,6 @@ typedef struct PORT_MEM_COUNTER typedef struct PORT_MEM_FENCE_HEAD { PORT_MEM_ALLOCATOR *pAllocator; - NvLength blockSize; NvU32 magic; } PORT_MEM_FENCE_HEAD; @@ -80,8 +97,8 @@ typedef struct PORT_MEM_LIST #if PORT_MEM_TRACK_USE_CALLERINFO_IP -typedef NvU64 PORT_MEM_CALLERINFO; -#define PORT_MEM_CALLERINFO_MAKE ((NvU64)portUtilGetIPAddress()) +typedef NvUPtr PORT_MEM_CALLERINFO; +#define PORT_MEM_CALLERINFO_MAKE portUtilGetIPAddress() #else // PORT_MEM_TRACK_USE_CALLERINFO_IP @@ -141,8 +158,8 @@ PORT_MEM_ALLOCATOR *portMemExAllocatorCreateLockedOnExistingBlock_CallerInfo(voi #define portMemAllocatorCreateOnExistingBlock(pMem, size) \ portMemAllocatorCreateOnExistingBlock_CallerInfo(pMem, size, PORT_MEM_CALLERINFO_MAKE) #if portMemExAllocatorCreateLockedOnExistingBlock_SUPPORTED -#define portMemExAllocatorCreateLockedOnExistingBlock(pMem, size, pLock) \ - portMemExAllocatorCreateLockedOnExistingBlock_CallerInfo(pMem, size, pLock,\ +#define portMemExAllocatorCreateLockedOnExistingBlock(pMem, size, pLock) \ + portMemExAllocatorCreateLockedOnExistingBlock_CallerInfo(pMem, size, pLock, \ PORT_MEM_CALLERINFO_MAKE) #endif //portMemExAllocatorCreateLockedOnExistingBlock_SUPPORTED #else @@ -151,8 +168,30 @@ PORT_MEM_ALLOCATOR *portMemExAllocatorCreateLockedOnExistingBlock_CallerInfo(voi #if PORT_MEM_TRACK_USE_FENCEPOSTS || PORT_MEM_TRACK_USE_ALLOCLIST || PORT_MEM_TRACK_USE_CALLERINFO || PORT_MEM_TRACK_USE_LIMIT + +// +// The blockSize of the allocation can be tracked in 1 of 2 places, +// depending on build configuration. To reduce per-alloc memory waste in +// allocating multiple fields for the same data, the following is the +// order in which they are preferred at compile time: +// +// 1. portMemExTrackingGetAllocUsableSize - the underlying malloc +// implementation has a function to get the allocation size from allocated +// pointer. No memory will be allocated in the PORT_MEM_HEADER to track the +// block size. +// 2. PORT_MEM_HEADER::blockSize - used when fenceposts or per-GFID limit +// tracking is enabled and portMemExTrackingGetAllocUsableSize is not +// available. +// +#define PORT_MEM_HEADER_HAS_BLOCK_SIZE \ + !PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetAllocUsableSize) && \ + (PORT_MEM_TRACK_USE_FENCEPOSTS || PORT_MEM_TRACK_USE_LIMIT) + typedef struct PORT_MEM_HEADER { +#if PORT_MEM_HEADER_HAS_BLOCK_SIZE + NvLength blockSize; +#endif #if PORT_MEM_TRACK_USE_CALLERINFO PORT_MEM_CALLERINFO callerInfo; #endif @@ -163,8 +202,7 @@ typedef struct PORT_MEM_HEADER PORT_MEM_FENCE_HEAD fence; #endif #if PORT_MEM_TRACK_USE_LIMIT - NvU64 blockSize; - NvU32 pid; + NV_DECLARE_ALIGNED(NvU32 pid, 8); #endif } PORT_MEM_HEADER; @@ -178,13 +216,18 @@ typedef struct PORT_MEM_FOOTER #define PORT_MEM_ADD_HEADER_PTR(p) ((PORT_MEM_HEADER*)p + 1) #define PORT_MEM_SUB_HEADER_PTR(p) ((PORT_MEM_HEADER*)p - 1) #define PORT_MEM_STAGING_SIZE (sizeof(PORT_MEM_HEADER)+sizeof(PORT_MEM_FOOTER)) - #else -#define PORT_MEM_ADD_HEADER_PTR(p) p -#define PORT_MEM_SUB_HEADER_PTR(p) p -#define PORT_MEM_STAGING_SIZE 0 +#define PORT_MEM_ADD_HEADER_PTR(p) p +#define PORT_MEM_SUB_HEADER_PTR(p) p +#define PORT_MEM_STAGING_SIZE 0 +#define PORT_MEM_HEADER_HAS_BLOCK_SIZE 0 #endif +#define PORT_MEM_TRACK_ALLOC_SIZE \ + PORT_MEM_TRACK_USE_COUNTER && \ + (PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetAllocUsableSize) || \ + PORT_MEM_HEADER_HAS_BLOCK_SIZE) + struct PORT_MEM_ALLOCATOR_TRACKING { PORT_MEM_ALLOCATOR *pAllocator; @@ -203,17 +246,6 @@ struct PORT_MEM_ALLOCATOR_TRACKING #endif }; - -#define portMemExTrackingGetActiveStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER -#define portMemExTrackingGetTotalStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER -#define portMemExTrackingGetPeakStats_SUPPORTED PORT_MEM_TRACK_USE_COUNTER -#define portMemExTrackingGetNext_SUPPORTED \ - (PORT_MEM_TRACK_USE_FENCEPOSTS & PORT_MEM_TRACK_USE_ALLOCLIST) - -#define portMemExValidate_SUPPORTED 0 -#define portMemExValidateAllocations_SUPPORTED 0 -#define portMemExFreeAll_SUPPORTED 0 - /// @brief Actual size of an allocator structure, including internals #define PORT_MEM_ALLOCATOR_SIZE \ (sizeof(PORT_MEM_ALLOCATOR) + sizeof(PORT_MEM_ALLOCATOR_TRACKING)) @@ -282,11 +314,11 @@ typedef struct #define _PORT_CEIL_NO_UNDERFLOW(a, b) (NV_DIV_AND_CEIL(b + a, b) - 1) /// @brief Required additional size for a given number of chunks -#define PORT_MEM_PREALLOCATED_BLOCK_SIZE_FOR_NONGRATIS_CHUNKS(num_chunks) \ - ((num_chunks > PORT_MEM_PREALLOCATED_BLOCK_CHUNKS_GRATIS) \ - ? _PORT_CEIL_NO_UNDERFLOW(num_chunks - PORT_MEM_PREALLOCATED_BLOCK_CHUNKS_GRATIS,\ - 4*PORT_MEM_BITVECTOR_CHUNK_SIZE) \ - * PORT_MEM_BITVECTOR_CHUNK_SIZE \ +#define PORT_MEM_PREALLOCATED_BLOCK_SIZE_FOR_NONGRATIS_CHUNKS(num_chunks) \ + ((num_chunks > PORT_MEM_PREALLOCATED_BLOCK_CHUNKS_GRATIS) \ + ? _PORT_CEIL_NO_UNDERFLOW(num_chunks - PORT_MEM_PREALLOCATED_BLOCK_CHUNKS_GRATIS, \ + 4*PORT_MEM_BITVECTOR_CHUNK_SIZE) \ + * PORT_MEM_BITVECTOR_CHUNK_SIZE \ : 0) /// @brief Total required bookkeeping size for a block of given useful size diff --git a/src/nvidia/inc/libraries/nvport/inline/safe_generic.h b/src/nvidia/inc/libraries/nvport/inline/safe_generic.h index e851b77031..e701c2cecd 100644 --- a/src/nvidia/inc/libraries/nvport/inline/safe_generic.h +++ b/src/nvidia/inc/libraries/nvport/inline/safe_generic.h @@ -138,20 +138,20 @@ #define PORT_SAFE_CAST(a, b, t) \ ((a < PORT_SAFE_MIN(t) || a > PORT_SAFE_MAX(t)) ? \ - NV_FALSE : \ + NV_FALSE : \ ((b = (Nv##t) a), NV_TRUE)) -#define PORT_SAFE_DEFINE_MATH_FUNC(_op_, _US_, _size_) \ - PORT_SAFE_INLINE NvBool \ - portSafe##_op_##_US_##_size_ \ - ( \ - Nv##_US_##_size_ x, \ - Nv##_US_##_size_ y, \ - Nv##_US_##_size_ *pRes \ - ) \ - { \ - return PORT_EXPAND(PORT_SAFE_##_op_##_IMPL_##_US_)(x, y, pRes, _size_);\ +#define PORT_SAFE_DEFINE_MATH_FUNC(_op_, _US_, _size_) \ + PORT_SAFE_INLINE NvBool \ + portSafe##_op_##_US_##_size_ \ + ( \ + Nv##_US_##_size_ x, \ + Nv##_US_##_size_ y, \ + Nv##_US_##_size_ *pRes \ + ) \ + { \ + return PORT_EXPAND(PORT_SAFE_##_op_##_IMPL_##_US_)(x, y, pRes, _size_); \ } diff --git a/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h b/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h index be23a99a36..7c40db716a 100644 --- a/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h +++ b/src/nvidia/inc/libraries/nvport/inline/sync_tracking.h @@ -56,18 +56,18 @@ #else -#define portSyncInitialize() \ - do { \ +#define portSyncInitialize() \ + do { \ portDbgPrintf("SYNC-DBG (%s:%d): portSyncInitialize() ", __FILE__, __LINE__); \ - portSyncInitialize(); \ - portDbgPrintf(" - Done;\n"); \ + portSyncInitialize(); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncShutdown() \ - do { \ +#define portSyncShutdown() \ + do { \ portDbgPrintf("SYNC-DBG (%s:%d): portSyncShutdown() ", __FILE__, __LINE__); \ - portSyncShutdown(); \ - portDbgPrintf(" - Done;\n"); \ + portSyncShutdown(); \ + portDbgPrintf(" - Done;\n"); \ } while (0) @@ -85,125 +85,125 @@ static NV_INLINE void *_syncPrintReturnPtr(void *ptr) } -#define portSyncSpinlockInitialize(pSpinlock) \ +#define portSyncSpinlockInitialize(pSpinlock) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockInitialize(%p) - ", \ - __FILE__, __LINE__, pSpinlock),\ + __FILE__, __LINE__, pSpinlock), \ _syncPrintReturnStatus(portSyncSpinlockInitialize(pSpinlock))) -#define portSyncSpinlockCreate(pAllocator) \ +#define portSyncSpinlockCreate(pAllocator) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockCreate(%p) - ", \ - __FILE__, __LINE__, pAllocator),\ + __FILE__, __LINE__, pAllocator), \ _syncPrintReturnPtr(portSyncSpinlockCreate(pAllocator))) -#define portSyncSpinlockDestroy(pSpinlock) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockDestroy(%p) ",\ - __FILE__, __LINE__, pSpinlock); \ - portSyncSpinlockDestroy(pSpinlock); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSpinlockDestroy(pSpinlock) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockDestroy(%p) ", \ + __FILE__, __LINE__, pSpinlock); \ + portSyncSpinlockDestroy(pSpinlock); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncSpinlockAcquire(pSpinlock) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockAcquire(%p) ",\ - __FILE__, __LINE__, pSpinlock); \ - portSyncSpinlockAcquire(pSpinlock); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSpinlockAcquire(pSpinlock) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockAcquire(%p) ", \ + __FILE__, __LINE__, pSpinlock); \ + portSyncSpinlockAcquire(pSpinlock); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncSpinlockRelease(pSpinlock) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockRelease(%p) ",\ - __FILE__, __LINE__, pSpinlock); \ - portSyncSpinlockRelease(pSpinlock); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSpinlockRelease(pSpinlock) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSpinlockRelease(%p) ", \ + __FILE__, __LINE__, pSpinlock); \ + portSyncSpinlockRelease(pSpinlock); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncMutexInitialize(pMutex) \ +#define portSyncMutexInitialize(pMutex) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexInitialize(%p) - ", \ - __FILE__, __LINE__, pMutex),\ + __FILE__, __LINE__, pMutex), \ _syncPrintReturnStatus(portSyncMutexInitialize(pMutex))) -#define portSyncMutexCreate(pAllocator) \ +#define portSyncMutexCreate(pAllocator) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexCreate(%p) - ", \ - __FILE__, __LINE__, pAllocator),\ + __FILE__, __LINE__, pAllocator), \ _syncPrintReturnPtr(portSyncMutexCreate(pAllocator))) -#define portSyncMutexDestroy(pMutex) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexDestroy(%p) ",\ - __FILE__, __LINE__, pMutex); \ - portSyncMutexDestroy(pMutex); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncMutexDestroy(pMutex) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexDestroy(%p) ", \ + __FILE__, __LINE__, pMutex); \ + portSyncMutexDestroy(pMutex); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncMutexAcquire(pMutex) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexAcquire(%p) ",\ - __FILE__, __LINE__, pMutex); \ - portSyncMutexAcquire(pMutex); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncMutexAcquire(pMutex) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexAcquire(%p) ", \ + __FILE__, __LINE__, pMutex); \ + portSyncMutexAcquire(pMutex); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncMutexRelease(pMutex) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexRelease(%p) ",\ - __FILE__, __LINE__, pMutex); \ - portSyncMutexRelease(pMutex); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncMutexRelease(pMutex) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexRelease(%p) ", \ + __FILE__, __LINE__, pMutex); \ + portSyncMutexRelease(pMutex); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncMutexAcquireConditional(pMutex) \ +#define portSyncMutexAcquireConditional(pMutex) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncMutexAcquireConditional(%p) - ", \ - __FILE__, __LINE__, pMutex),\ - (portSyncMutexAcquireConditional(pMutex) ? \ + __FILE__, __LINE__, pMutex), \ + (portSyncMutexAcquireConditional(pMutex) ? \ (portDbgPrintf("TRUE\n"),NV_TRUE) : (portDbgPrintf("FALSE\n"),NV_FALSE))) -#define portSyncSemaphoreInitialize(pSemaphore, s, l) \ +#define portSyncSemaphoreInitialize(pSemaphore, s, l) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreInitialize(%p, %u, %u) - ", \ - __FILE__, __LINE__, pSemaphore, s, l),\ + __FILE__, __LINE__, pSemaphore, s, l), \ _syncPrintReturnStatus(portSyncSemaphoreInitialize(pSemaphore, s, l))) -#define portSyncSemaphoreCreate(pAllocator, s, l) \ +#define portSyncSemaphoreCreate(pAllocator, s, l) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreCreate(%p, %u, %u) - ", \ - __FILE__, __LINE__, pAllocator, s, l),\ + __FILE__, __LINE__, pAllocator, s, l), \ _syncPrintReturnPtr(portSyncSemaphoreCreate(pAllocator, s, l))) -#define portSyncSemaphoreDestroy(pSemaphore) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreDestroy(%p) ",\ - __FILE__, __LINE__, pSemaphore); \ - portSyncSemaphoreDestroy(pSemaphore); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSemaphoreDestroy(pSemaphore) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreDestroy(%p) ", \ + __FILE__, __LINE__, pSemaphore); \ + portSyncSemaphoreDestroy(pSemaphore); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncSemaphoreAcquire(pSemaphore) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreAcquire(%p) ",\ - __FILE__, __LINE__, pSemaphore); \ - portSyncSemaphoreAcquire(pSemaphore); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSemaphoreAcquire(pSemaphore) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreAcquire(%p) ", \ + __FILE__, __LINE__, pSemaphore); \ + portSyncSemaphoreAcquire(pSemaphore); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncSemaphoreRelease(pSemaphore) \ - do { \ - portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreRelease(%p) ",\ - __FILE__, __LINE__, pSemaphore); \ - portSyncSemaphoreRelease(pSemaphore); \ - portDbgPrintf(" - Done;\n"); \ +#define portSyncSemaphoreRelease(pSemaphore) \ + do { \ + portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreRelease(%p) ", \ + __FILE__, __LINE__, pSemaphore); \ + portSyncSemaphoreRelease(pSemaphore); \ + portDbgPrintf(" - Done;\n"); \ } while (0) -#define portSyncSemaphoreAcquireConditional(pSemaphore) \ +#define portSyncSemaphoreAcquireConditional(pSemaphore) \ (portDbgPrintf("SYNC-DBG (%s:%d): portSyncSemaphoreAcquireConditional(%p) - ", \ - __FILE__, __LINE__, pSemaphore),\ - (portSyncSemaphoreAcquireConditional(pSemaphore) ? \ + __FILE__, __LINE__, pSemaphore), \ + (portSyncSemaphoreAcquireConditional(pSemaphore) ? \ (portDbgPrintf("TRUE\n"),NV_TRUE) : (portDbgPrintf("FALSE\n"),NV_FALSE))) diff --git a/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h b/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h index 9fb20be8c6..d14846ba2c 100644 --- a/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h +++ b/src/nvidia/inc/libraries/nvport/inline/util_gcc_clang.h @@ -49,54 +49,54 @@ #define portUtilGetReturnAddress() (NvUPtr)__builtin_return_address(0) #if NVCPU_IS_X86 || NVCPU_IS_X86_64 -#define NVPORT_DUMMY_LOOP() \ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - \ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - \ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - \ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ - __asm__ __volatile__ ("pause");\ +#define NVPORT_DUMMY_LOOP() \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ + __asm__ __volatile__ ("pause"); \ __asm__ __volatile__ ("pause"); #else -#define NVPORT_DUMMY_LOOP() \ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - \ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - \ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - \ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ - __asm__ __volatile__ ("nop");\ +#define NVPORT_DUMMY_LOOP() \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ + __asm__ __volatile__ ("nop"); \ __asm__ __volatile__ ("nop"); #endif diff --git a/src/nvidia/inc/libraries/nvport/memory.h b/src/nvidia/inc/libraries/nvport/memory.h index a27f6ef4da..8c5531619b 100644 --- a/src/nvidia/inc/libraries/nvport/memory.h +++ b/src/nvidia/inc/libraries/nvport/memory.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -505,12 +505,17 @@ PORT_MEM_ALLOCATOR *portMemAllocatorGetGlobalNonPaged(void); PORT_MEM_ALLOCATOR *portMemAllocatorGetGlobalPaged(void); /** * @brief Prints the memory details gathered by whatever tracking mechanism is - * enabled. If pAllocator is NULL, it will print data for all allocators. + * enabled. If pTracking is NULL, aggregate tracking information from all + * allocators will be printed. * - * @note Printing is done using portDbgPrintString, which prints regardless of + * @note Printing is done using portDbgPrintf, which prints regardless of * build type and debug levels. */ -void portMemPrintTrackingInfo(const PORT_MEM_ALLOCATOR *pAllocator); +void portMemPrintTrackingInfo(const PORT_MEM_ALLOCATOR_TRACKING *pTracking); +/** + * @brief Calls @ref portMemPrintTrackingInfo for all current allocator trackers. + */ +void portMemPrintAllTrackingInfo(void); // @} End core functions @@ -568,12 +573,12 @@ NV_STATUS portMemExTrackingGetTotalStats(const PORT_MEM_ALLOCATOR *pAllocator, P /** * @brief Returns the statistics of peak allocations made with the given * allocator since it was created. - * - * Peak data reports each field independently. For example, if the peak data - * reports 100 allocations and 100000 bytes allocated, those two did not - * necessarily happen *at the same time*. It could also be that the allocator - * created 100 allocations of 1 byte each, then freed them and allocated a - * single 100000 bytes block. + * + * Peak data reports the high-water mark based on the maximum size (the peak + * allocations doesn't report the largest number of allocations, it reports + * the number of allocations at the time the peak size was achieved). This is + * done so that the other peak stats, which are derived from peak size and + * peak allocations, are consistent with each other. * * If pAllocator is NULL, it returns stats for all allocators, as well as the * memory allocated with @ref portMemAllocPaged and @ref portMemAllocNonPaged @@ -597,6 +602,16 @@ NV_STATUS portMemExTrackingGetPeakStats(const PORT_MEM_ALLOCATOR *pAllocator, PO */ NV_STATUS portMemExTrackingGetNext(const PORT_MEM_ALLOCATOR *pAllocator, PORT_MEM_TRACK_ALLOC_INFO *pInfo, void **pIterator); +/** + * @brief Gets the total size of the underlying heap, in bytes. + */ +NvLength portMemExTrackingGetHeapSize(void); + +/** + * @brief Gets the usable size in bytes (sans metadata/padding) of the given allocation. + */ +NvLength portMemExTrackingGetAllocUsableSize(void *pMem); + /** * @brief Copies from user memory to kernel memory. * @@ -918,6 +933,9 @@ void portMemExUnmapIOSpace(void *addr, NvU64 byteSize); #endif #endif // !defined(PORT_MEM_TRACK_USE_LIMIT) +// Memory tracking header can redefine some functions declared here. +#include "nvport/inline/memory_tracking.h" + /** @brief Nothing is printed unless @ref portMemPrintTrackingInfo is called */ #define PORT_MEM_TRACK_PRINT_LEVEL_SILENT 0 /** @brief Print when an error occurs and at shutdown */ @@ -926,16 +944,13 @@ void portMemExUnmapIOSpace(void *addr, NvU64 byteSize); #define PORT_MEM_TRACK_PRINT_LEVEL_VERBOSE 2 #if !defined(PORT_MEM_TRACK_PRINT_LEVEL) -#if PORT_IS_CHECKED_BUILD +#if PORT_IS_CHECKED_BUILD || PORT_MEM_TRACK_ALLOC_SIZE #define PORT_MEM_TRACK_PRINT_LEVEL PORT_MEM_TRACK_PRINT_LEVEL_BASIC #else #define PORT_MEM_TRACK_PRINT_LEVEL PORT_MEM_TRACK_PRINT_LEVEL_SILENT #endif // PORT_IS_CHECKED_BUILD #endif // !defined(PORT_MEM_TRACK_PRINT_LEVEL) -// Memory tracking header can redefine some functions declared here. -#include "nvport/inline/memory_tracking.h" - /** * @brief Single allocation description. * diff --git a/src/nvidia/inc/libraries/nvport/nvport.h b/src/nvidia/inc/libraries/nvport/nvport.h index 3049e4b686..f9cd603d3a 100644 --- a/src/nvidia/inc/libraries/nvport/nvport.h +++ b/src/nvidia/inc/libraries/nvport/nvport.h @@ -158,7 +158,7 @@ extern "C" { * * This switch will define type and method aliases for object types in NvPort. * The current NvPort style object names are PORT_MODULE_OBJECT, while the - * methods are portModuleObjectMethod(). + * methods are portModuleObjectMethod(). * The update proposal dictates these to be PortModuleObject and objectMethod. * * @todo Currently we just alias the new names to the old ones. Once the coding @@ -174,18 +174,18 @@ extern "C" { * * No compilation errors are reported by any compiler when we use * the following definition. - * + * * #define PORT_UNREFERENCED_VARIABLE(x) ((void)sizeof(&(x))) * * But Coverity reports BAD_SIZEOF error with this definition. - * Adding a Coverity annotation "coverity[bad_sizeof]" near + * Adding a Coverity annotation "coverity[bad_sizeof]" near * the definition does not work. The preprocessor ignores all * the comments and the Coverity annotation is also ignored * as a legal comment. As a result, this annotation never ends * up in the source code where this macro is used. Hence, we use * two definitions of this macro - one for Coverity and the other - * for the rest of the targets. - * + * for the rest of the targets. + * * Coverity does not report any warnings for unused variables. * Hence, we do nothing while building for Coverity. */ diff --git a/src/nvidia/inc/libraries/nvport/string.h b/src/nvidia/inc/libraries/nvport/string.h index cdc70dfc4e..82da75ceb1 100644 --- a/src/nvidia/inc/libraries/nvport/string.h +++ b/src/nvidia/inc/libraries/nvport/string.h @@ -48,7 +48,7 @@ /** * @brief Compare two strings, character by character. - * + * * Will only compare lengthBytes bytes. Strings are assumed to be at least that * long. * @@ -64,7 +64,7 @@ NvS32 portStringCompare(const char *str1, const char *str2, NvLength length); /** * @brief Copy a string. - * + * * Will copy at most destSize bytes, stopping early if a null-terminator is found * or if srcSize bytes are read from the source. * @@ -82,13 +82,13 @@ NvS32 portStringCompare(const char *str1, const char *str2, NvLength length); NvLength portStringCopy(char *dest, NvLength destSize, const char *src, NvLength srcSize); /** * @brief Concatenate two strings - * + * * Will copy cat string after the end of str. Will copy only until str buffer is * filled. str is assumed to point to a buffer of at least strSize bytes. * * Null character is always written at the end of the string. * - * @return str if concatenation is succeeded. + * @return str if concatenation is succeeded. * * @par Undefined: * Number of allocated bytes in destination buffer are smaller than destSize.
diff --git a/src/nvidia/inc/libraries/poolalloc.h b/src/nvidia/inc/libraries/poolalloc.h index c1ef41831f..8485ad838e 100644 --- a/src/nvidia/inc/libraries/poolalloc.h +++ b/src/nvidia/inc/libraries/poolalloc.h @@ -48,28 +48,28 @@ extern "C" { typedef struct poolnode POOLNODE; -/*! +/*! * Each node corresponds to one page of upStreamPageSize * The pool allocator sub-allocates from each of these pages. - */ + */ struct poolnode { NvU64 pageAddr; // Address of the page to sub-allocate NvU64 bitmap; // The bit map for this page. Only used if the // node represents a partially allocated node - POOLNODE *pParent; // The upstream pool node in case this node is + POOLNODE *pParent; // The upstream pool node in case this node is // allocated from the upper pool. ListNode node; // For intrusive lists. }; MAKE_INTRUSIVE_LIST(PoolNodeList, POOLNODE, node); -/*! +/*! * The handle contains a generic metadata field that is needed for fast * access. In the case of a linked list implementation of the pool allocator, * the metadata is the pointer to the node that contains the page it was - * sub-allocated from - */ + * sub-allocated from + */ typedef struct poolallocHandle { NvU64 address; // The base address for this chunk @@ -110,7 +110,7 @@ typedef NV_STATUS (*allocCallback_t)(void *ctxPtr, NvU64 pageSize, */ typedef void (*freeCallback_t)(void *ctxPtr, NvU64 pageSize, POOLALLOC_HANDLE *pPage); -/*! +/*! * Structure representing a pool. */ typedef struct poolalloc @@ -128,14 +128,14 @@ typedef struct poolalloc void *pUpstreamCtx; // The context to pass to upstream allocator } callBackInfo; - NvU32 upstreamPageSize; // Page size for upstream allocations - NvU32 allocPageSize; // Page size to give out + NvU64 upstreamPageSize; // Page size for upstream allocations + NvU64 allocPageSize; // Page size to give out NvU32 ratio; // Ratio == upstreamPageSize / allocPageSize NvU32 flags; // POOLALLOC_FLAGS_* } POOLALLOC; -/*! +/*! * Dump the lists maintained by the pools. */ void poolAllocPrint(POOLALLOC *pPool); @@ -169,14 +169,14 @@ void poolAllocPrint(POOLALLOC *pPool); * @param[in] freeFun The free for internal structures * @param[in] pAllocCtxPtr The context pointer for the special * allocator - * @param[in] flags POOLALLOC_FLAGS_* + * @param[in] flags POOLALLOC_FLAGS_* * * @return A pointer to a POOLALLOC structure if the initialization * succeeded; NULL otherwise * */ -POOLALLOC *poolInitialize(NvU32 upstreamPageSize, NvU32 allocPageSize, +POOLALLOC *poolInitialize(NvU64 upstreamPageSize, NvU64 allocPageSize, allocCallback_t allocCb, freeCallback_t freeCb, void *pUpstreamCtxPtr, PORT_MEM_ALLOCATOR *pAllocator, NvU32 flags); @@ -276,10 +276,10 @@ void poolFree(POOLALLOC *pPool, POOLALLOC_HANDLE *pPageHandle); */ void poolDestroy(POOLALLOC *pPool); -/*! +/*! * @briefs Returns the lengths of a pool's lists */ -void poolGetListLength(POOLALLOC *pPool, NvU32 *pFreeListLength, +void poolGetListLength(POOLALLOC *pPool, NvU32 *pFreeListLength, NvU32 *pPartialListLength, NvU32 *pFullListLength); #ifdef __cplusplus diff --git a/src/nvidia/inc/libraries/resserv/resserv.h b/src/nvidia/inc/libraries/resserv/resserv.h index 4091569fba..9b61445b8e 100644 --- a/src/nvidia/inc/libraries/resserv/resserv.h +++ b/src/nvidia/inc/libraries/resserv/resserv.h @@ -190,7 +190,7 @@ typedef void *PUID_TOKEN; #define RS_LOCK_RELEASE_SESSION_LOCK NVBIT(5) /// API enumerations used for locking knobs -typedef enum +typedef enum { RS_LOCK_CLIENT =0, RS_LOCK_TOP =1, @@ -198,7 +198,7 @@ typedef enum RS_LOCK_CUSTOM_3 =3, } RS_LOCK_ENUM; -typedef enum +typedef enum { RS_API_ALLOC_CLIENT = 0, RS_API_ALLOC_RESOURCE = 1, @@ -283,7 +283,7 @@ struct CALL_CONTEXT NvU32 serializedSize; ///< Serialized size NvU32 deserializedSize; ///< Deserialized size NvBool bReserialize; ///< Reserialize before calling into GSP - NvBool bRestoreParams; ///< Need to restore pParams + NvBool bLocalSerialization; ///< Serialized internally }; typedef enum { @@ -362,7 +362,7 @@ struct ACCESS_CONTROL } while(0) #else -#define RS_LOCK_VALIDATOR_INIT(lock, lockClass, inst) +#define RS_LOCK_VALIDATOR_INIT(lock, lockClass, inst) #define RS_RWLOCK_ACQUIRE_READ(lock, validator) do { portSyncRwLockAcquireRead((lock)); } while(0) #define RS_RWLOCK_ACQUIRE_WRITE(lock, validator) do { portSyncRwLockAcquireWrite((lock)); } while(0) #define RS_RWLOCK_RELEASE_READ_EXT(lock, validator, bOutOfOrder) do { portSyncRwLockReleaseRead((lock)); } while(0) diff --git a/src/nvidia/inc/libraries/resserv/rs_resource.h b/src/nvidia/inc/libraries/resserv/rs_resource.h index 6a36f674ab..2be5031505 100644 --- a/src/nvidia/inc/libraries/resserv/rs_resource.h +++ b/src/nvidia/inc/libraries/resserv/rs_resource.h @@ -90,6 +90,7 @@ struct RS_RES_ALLOC_PARAMS_INTERNAL API_SECURITY_INFO *pSecInfo; void *pAllocParams; ///< [in] Copied-in allocation parameters + NvU32 paramsSize; ///< [in] Copied-in allocation parameters size // ... Dupe alloc RsClient *pSrcClient; ///< The client that is sharing the resource @@ -813,7 +814,7 @@ NV_STATUS refAddDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependant /** * Remove the dependency between this resource reference and a dependent resource reference. */ -NV_STATUS refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRef); +void refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRef); /** * Find, Add, or Remove an inter-mapping between two resources to the Mapper's list of inter-mappings diff --git a/src/nvidia/inc/libraries/resserv/rs_server.h b/src/nvidia/inc/libraries/resserv/rs_server.h index 17fa4153ad..d3bc11f3b1 100644 --- a/src/nvidia/inc/libraries/resserv/rs_server.h +++ b/src/nvidia/inc/libraries/resserv/rs_server.h @@ -285,7 +285,7 @@ NV_STATUS serverFreeClient(RsServer *pServer, RS_CLIENT_FREE_PARAMS* pParams); NV_STATUS serverMarkClientListDisabled(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); /** - * Frees all currently disabled clients. All resources references owned by + * Frees all currently disabled clients. All resources references owned by * any of the clients will be freed. * All priority resources will be freed first across all listed clients. * @@ -379,44 +379,44 @@ NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); * * @param[in] pCallContext * @param[in] cmd - * @param[in] pParams - * @param[in] paramsSize + * @param[in/out] ppParams + * @param[in/out] pParamsSize * @param[in] flags */ -NV_STATUS serverDeserializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); +NV_STATUS serverDeserializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); /** * Serialize parameters for servicing command * * @param[in] pCallContext * @param[in] cmd - * @param[in] pParams - * @param[in] paramsSize + * @param[in/out] ppParams + * @param[in/out] pParamsSize * @param[in] flags */ -NV_STATUS serverSerializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); +NV_STATUS serverSerializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); /** * Deserialize parameters for returning from command * * @param[in] pCallContext * @param[in] cmd - * @param[in] pParams - * @param[in] paramsSize + * @param[out] ppParams + * @param[out] pParamsSize * @param[in] flags */ -NV_STATUS serverDeserializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); +NV_STATUS serverDeserializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); /** * Serialize parameters for returning from command * * @param[in] pCallContext * @param[in] cmd - * @param[in] pParams - * @param[in] paramsSize + * @param[out] ppParams + * @param[out] pParamsSize * @param[in] flags */ -NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); +NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); /** * Unset flag for reserializing control before going to GSP @@ -426,6 +426,50 @@ NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pPa */ void serverDisableReserializeControl(CALL_CONTEXT *pCallContext); +/** + * Serialize parameters for allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[in/out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeAllocDown(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[in/out] ppParams + * @param[in/out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeAllocDown(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Serialize parameters for returning from allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverSerializeAllocUp(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + +/** + * Deserialize parameters for returning from allocating + * + * @param[in] pCallContext + * @param[in] classId + * @param[out] ppParams + * @param[out] pParamsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeAllocUp(CALL_CONTEXT *pCallContext, NvU32 classId, void **ppParams, NvU32 *pParamsSize, NvU32 *flags); + /** * Free finn structures allocated for serializing/deserializing * diff --git a/src/nvidia/inc/libraries/utils/nv_enum.h b/src/nvidia/inc/libraries/utils/nv_enum.h index 873200a495..5662fea262 100644 --- a/src/nvidia/inc/libraries/utils/nv_enum.h +++ b/src/nvidia/inc/libraries/utils/nv_enum.h @@ -130,7 +130,7 @@ * often. There is no such thing as a meta-macro in the c preprocessor, so * we have defined the operations which we use frequently here. * - * @note instead of LISP-style structured lists which are formatted as + * @note instead of LISP-style structured lists which are formatted as * records containing two elements each (e.g. (car, (cdr, ()))), this tool * uses preprocessor argument lists (e.g. (car, cdr, etc)) because the * former require proper recursion to deal with, which this tool does not @@ -149,8 +149,8 @@ #define NV_CAADR(l) NV_ENUM_APPLY(NV_ENUM_A1, NV_ENUM_APPLY(NV_ENUM_A2, l)) #define NV_CADADR(l) NV_ENUM_APPLY(NV_ENUM_A2, NV_ENUM_APPLY(NV_ENUM_A2, l)) #define NV_CADDADR(l) NV_ENUM_APPLY(NV_ENUM_A3, NV_ENUM_APPLY(NV_ENUM_A2, l)) -#define NV_CADDDADR(l) NV_ENUM_APPLY(NV_ENUM_A4, NV_ENUM_APPLY(NV_ENUM_A2, l)) -#define NV_CADDDDADR(l) NV_ENUM_APPLY(NV_ENUM_A5, NV_ENUM_APPLY(NV_ENUM_A2, l)) +#define NV_CADDDADR(l) NV_ENUM_APPLY(NV_ENUM_A4, NV_ENUM_APPLY(NV_ENUM_A2, l)) +#define NV_CADDDDADR(l) NV_ENUM_APPLY(NV_ENUM_A5, NV_ENUM_APPLY(NV_ENUM_A2, l)) /*! * @brief Performs per-entry generation function, and either expands or extinguishes it @@ -160,7 +160,7 @@ * @param value Integer Literal - Value for this entry * * @return the result of the generation function for this table, - * or nothing if this layer is being filtered (i.e. nested enum) + * or nothing if this layer is being filtered (i.e. nested enum) */ #define NV_ENUM_ENTRY(dat__, name, value) \ NV_ENUM_DAT_ENTRY(dat__) (NV_ENUM_DAT_GEN2(dat__) (dat__, name, value)) @@ -175,7 +175,7 @@ * * @param dat__ Data List - Generation data table * @param name Token - String to append to previous enum name - * @param res_lo Integer Literal - Min value of this nested enum + * @param res_lo Integer Literal - Min value of this nested enum * @param res_hi Integer Literal - Max value of this nested enum * @param entries Macro - Nested Enum Specification */ @@ -189,7 +189,7 @@ entries(NV_ENUM_APPLY(NV_ENUM_DL_POP, NV_ENUM_NV_ENUM_REPLACE_1(NV_ENUM_NV_ENUM_REPLACE_1(NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), name), NV_ENUM_APPLY(NV_ENUM_A1, dat__)), dat__))) /*! - * @brief Performs all enum generation for the given nested enum specification + * @brief Performs all enum generation for the given nested enum specification * * @note the Current Enum Name is concatenated with parameter `name` * the Nested Enum Name is updated to match the Current Enum Name @@ -200,29 +200,29 @@ * * @param dat__ Data List - Generation data table * @param name Token - String to append to previous enum name - * @param res_lo Integer Literal - Min value of this nested enum + * @param res_lo Integer Literal - Min value of this nested enum * @param res_hi Integer Literal - Max value of this nested enum * @param entries Macro - Nested Enum Specification */ -#define NV_ENUM_NEST_GEN(dat__, name, res_lo, res_hi, entries) \ - NV_ENUM_DAT_GEN1(dat__)( \ - NV_ENUM_APPLY( \ - NV_ENUM_DL_POP, \ - NV_ENUM_NV_ENUM_REPLACE_1( \ - NV_ENUM_REPLACE_4( \ +#define NV_ENUM_NEST_GEN(dat__, name, res_lo, res_hi, entries) \ + NV_ENUM_DAT_GEN1(dat__)( \ + NV_ENUM_APPLY( \ + NV_ENUM_DL_POP, \ + NV_ENUM_NV_ENUM_REPLACE_1( \ + NV_ENUM_REPLACE_4( \ NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), name), \ NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), name), \ - res_lo, \ - res_hi, \ - NV_ENUM_APPLY( \ - NV_ENUM_A1, \ - dat__ \ - ) \ - ), \ - dat__ \ - ) \ - ), \ - entries \ + res_lo, \ + res_hi, \ + NV_ENUM_APPLY( \ + NV_ENUM_A1, \ + dat__ \ + ) \ + ), \ + dat__ \ + ) \ + ), \ + entries \ ) /*! @@ -279,37 +279,37 @@ /*! * @brief constructs a data list to be used for generation of the root enum */ -#define NV_ENUM_DEPTH_0(name, prefix, gen1_fn, gen2_fn) \ - ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ +#define NV_ENUM_DEPTH_0(name, prefix, gen1_fn, gen2_fn) \ + ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND0, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND1, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND2, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND3, gen1_fn, gen2_fn, unused, unused) \ - , (unused, unused, unused, unused, unused, unused) \ + , (unused, unused, unused, unused, unused, unused) \ ) /*! * @brief constructs a data list to be used for generation of enums at depth 1 */ -#define NV_ENUM_DEPTH_1(name, prefix, gen1_fn, gen2_fn) \ - ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ - , (NV_DISCARD_ONE, NV_ENUM_NEST_GEN, gen1_fn, gen2_fn, unused, unused) \ +#define NV_ENUM_DEPTH_1(name, prefix, gen1_fn, gen2_fn) \ + ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ + , (NV_DISCARD_ONE, NV_ENUM_NEST_GEN, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND0, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND1, gen1_fn, gen2_fn, unused, unused) \ , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND2, gen1_fn, gen2_fn, unused, unused) \ - , (unused, unused, unused, unused, unused, unused) \ + , (unused, unused, unused, unused, unused, unused) \ ) /*! * @brief constructs a data list to be used for generation of enums at depth 2 */ -#define NV_ENUM_DEPTH_2(name, prefix, gen1_fn, gen2_fn) \ - ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ +#define NV_ENUM_DEPTH_2(name, prefix, gen1_fn, gen2_fn) \ + ( (name, name, prefix, name, NV_ENUM_MIN, NV_ENUM_MAX) \ , (NV_DISCARD_ONE, NV_ENUM_NEST_EXPAND0, gen1_fn, gen2_fn, unused, unused) \ - , (NV_DISCARD_ONE, NV_ENUM_NEST_GEN, gen1_fn, gen2_fn, unused, unused) \ - , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND1, gen1_fn, gen2_fn, unused, unused) \ - , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND2, gen1_fn, gen2_fn, unused, unused) \ - , (unused, unused, unused, unused, unused, unused) \ + , (NV_DISCARD_ONE, NV_ENUM_NEST_GEN, gen1_fn, gen2_fn, unused, unused) \ + , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND1, gen1_fn, gen2_fn, unused, unused) \ + , (NV_EXPAND_ONE, NV_ENUM_NEST_EXPAND2, gen1_fn, gen2_fn, unused, unused) \ + , (unused, unused, unused, unused, unused, unused) \ ) /// @@ -344,47 +344,47 @@ /*! @brief Generates a conversion function from an enum value to string representation. */ -#define NV_ENUM_GEN_STRING(dat__, entries) \ - static inline const char * \ - NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), _TO_STRING) \ - ( \ - enum NV_ENUM_DAT_ROOT_NAME(dat__) in \ - ) \ - { \ - switch (in) \ - { \ - entries(dat__) \ - default: \ - break; \ - } \ +#define NV_ENUM_GEN_STRING(dat__, entries) \ + static inline const char * \ + NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), _TO_STRING) \ + ( \ + enum NV_ENUM_DAT_ROOT_NAME(dat__) in \ + ) \ + { \ + switch (in) \ + { \ + entries(dat__) \ + default: \ + break; \ + } \ return NV_ENUM_STRINGIFY(NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __UNKNOWN)); \ } /*! @brief Generates a case for the given enum entry, and its string representation. */ -#define NV_ENUM_GEN_STRING_FN(dat__, entry_name, value) \ +#define NV_ENUM_GEN_STRING_FN(dat__, entry_name, value) \ case NV_ENUM_CONCATENATE(NV_ENUM_DAT_PREFIX(dat__), entry_name): \ return NV_ENUM_STRINGIFY(NV_ENUM_CONCATENATE(NV_ENUM_DAT_PREFIX(dat__), entry_name)); /*! @brief Generates a conversion function from NvU32 to enum value. */ -#define NV_ENUM_GEN_FROM(dat__, entries) \ - static inline NV_STATUS \ - NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), _FROM32) \ - ( \ - NvU32 in, \ - enum NV_ENUM_DAT_ROOT_NAME(dat__) *out \ - ) \ - { \ - switch (in) \ - { \ - entries(dat__) \ - if (out != NULL) \ +#define NV_ENUM_GEN_FROM(dat__, entries) \ + static inline NV_STATUS \ + NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), _FROM32) \ + ( \ + NvU32 in, \ + enum NV_ENUM_DAT_ROOT_NAME(dat__) *out \ + ) \ + { \ + switch (in) \ + { \ + entries(dat__) \ + if (out != NULL) \ *out = ((enum NV_ENUM_DAT_ROOT_NAME(dat__))in); \ - return NV_OK; \ - default: \ - break; \ - } \ - return NV_ERR_OUT_OF_RANGE; \ + return NV_OK; \ + default: \ + break; \ + } \ + return NV_ERR_OUT_OF_RANGE; \ } /*! @brief Generates a case for the given enum entry. */ @@ -411,11 +411,11 @@ /*! @brief Generates a group of struct constants containing the above generated values. */ -#define NV_ENUM_GEN_META(dat__, entries) \ - typedef struct { char lo[sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __LO) *) NULL)->lo)]; \ - char hi[NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE)];\ - char count[sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __COUNT) *) NULL)->count)]; \ - char size[NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE)]; \ +#define NV_ENUM_GEN_META(dat__, entries) \ + typedef struct { char lo[sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __LO) *) NULL)->lo)]; \ + char hi[NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE)]; \ + char count[sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __COUNT) *) NULL)->count)]; \ + char size[NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE)]; \ char bContiguous[(sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __COUNT) *) NULL)->count) == (NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __SIZE) - sizeof(((NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __LO) *) NULL)->lo) + 1)) + 1]; \ } NV_ENUM_CONCATENATE(NV_ENUM_DAT_CURR_NAME(dat__), __META) ; @@ -463,9 +463,9 @@ * @param entries Macro - Enum Specification */ #define NV_ENUM_GENERATOR(fn1, fn2, enum_name, prefix, entries) \ - fn1(NV_ENUM_DEPTH_0(enum_name, prefix, fn1, fn2), entries) \ - entries(NV_ENUM_DEPTH_1(enum_name, prefix, fn1, fn2)) \ - entries(NV_ENUM_DEPTH_2(enum_name, prefix, fn1, fn2)) \ + fn1(NV_ENUM_DEPTH_0(enum_name, prefix, fn1, fn2), entries) \ + entries(NV_ENUM_DEPTH_1(enum_name, prefix, fn1, fn2)) \ + entries(NV_ENUM_DEPTH_2(enum_name, prefix, fn1, fn2)) \ // // Windows preprocessor crashes with "ran out of heap space" errors if the @@ -482,15 +482,15 @@ * @param enum_name Token - Root Enum Name * @param entries Macro - Enum Specification */ -#define NV_ENUM_DEF_PREFIX(prefix, enum_name, entries) \ +#define NV_ENUM_DEF_PREFIX(prefix, enum_name, entries) \ NV_ENUM_GEN_MAIN(NV_ENUM_DEPTH_0(enum_name, prefix, NV_ENUM_GEN_MAIN, NV_ENUM_GEN_MAIN_FN), entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_TYPEDEF, NV_ENUM_GEN_TYPEDEF_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_SIZE, NV_ENUM_GEN_SIZE_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_STRING, NV_ENUM_GEN_STRING_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_FROM, NV_ENUM_GEN_FROM_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_LO, NV_ENUM_GEN_LO_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_COUNT, NV_ENUM_GEN_COUNT_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_META, NV_ENUM_GEN_META_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_TYPEDEF, NV_ENUM_GEN_TYPEDEF_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_SIZE, NV_ENUM_GEN_SIZE_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_STRING, NV_ENUM_GEN_STRING_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_FROM, NV_ENUM_GEN_FROM_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_LO, NV_ENUM_GEN_LO_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_COUNT, NV_ENUM_GEN_COUNT_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_META, NV_ENUM_GEN_META_FN, enum_name, prefix, entries) \ #else @@ -501,15 +501,15 @@ * @param enum_name Token - Root Enum Name * @param entries Macro - Enum Specification */ -#define NV_ENUM_DEF_PREFIX(prefix, enum_name, entries) \ - NV_ENUM_GEN_MAIN(NV_ENUM_DEPTH_0(enum_name, prefix, NV_ENUM_GEN_MAIN, NV_ENUM_GEN_MAIN_FN), entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_TYPEDEF, NV_ENUM_GEN_TYPEDEF_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_SIZE, NV_ENUM_GEN_SIZE_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_STRING, NV_ENUM_GEN_STRING_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_FROM, NV_ENUM_GEN_FROM_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_LO, NV_ENUM_GEN_LO_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_COUNT, NV_ENUM_GEN_COUNT_FN, enum_name, prefix, entries) \ - NV_ENUM_GENERATOR(NV_ENUM_GEN_META, NV_ENUM_GEN_META_FN, enum_name, prefix, entries) \ +#define NV_ENUM_DEF_PREFIX(prefix, enum_name, entries) \ + NV_ENUM_GEN_MAIN(NV_ENUM_DEPTH_0(enum_name, prefix, NV_ENUM_GEN_MAIN, NV_ENUM_GEN_MAIN_FN), entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_TYPEDEF, NV_ENUM_GEN_TYPEDEF_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_SIZE, NV_ENUM_GEN_SIZE_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_STRING, NV_ENUM_GEN_STRING_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_FROM, NV_ENUM_GEN_FROM_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_LO, NV_ENUM_GEN_LO_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_COUNT, NV_ENUM_GEN_COUNT_FN, enum_name, prefix, entries) \ + NV_ENUM_GENERATOR(NV_ENUM_GEN_META, NV_ENUM_GEN_META_FN, enum_name, prefix, entries) \ NV_ENUM_GENERATOR(NV_ENUM_GEN_ASSERT_MONOTONIC, NV_ENUM_GEN_ASSERT_MONOTONIC_FN, enum_name, prefix, entries) \ NV_ENUM_GENERATOR(NV_ENUM_GEN_ASSERT_IN_RANGE, NV_ENUM_GEN_ASSERT_IN_RANGE_FN, enum_name, prefix, entries) @@ -638,16 +638,16 @@ * @param[in] type identifier - Enum type name * @param[in] value lvalue - iterator holding current enum value */ -#define FOR_EACH_IN_ENUM(type, value) \ -{ \ - NvU32 localValue; \ +#define FOR_EACH_IN_ENUM(type, value) \ +{ \ + NvU32 localValue; \ for (localValue = value = NV_ENUM_LO(type); localValue <= NV_ENUM_HI(type); (value) = (type) (++localValue)) \ - { \ - if (!NV_ENUM_IS_CONTIGUOUS(type) && !NV_ENUM_IS(type, localValue)) \ + { \ + if (!NV_ENUM_IS_CONTIGUOUS(type) && !NV_ENUM_IS(type, localValue)) \ continue; #define FOR_EACH_IN_ENUM_END \ - } \ + } \ } /*! diff --git a/src/nvidia/inc/libraries/utils/nvassert.h b/src/nvidia/inc/libraries/utils/nvassert.h index b575373a69..b3a6e78225 100644 --- a/src/nvidia/inc/libraries/utils/nvassert.h +++ b/src/nvidia/inc/libraries/utils/nvassert.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -823,6 +823,20 @@ void nvCheckOkFailedNoLog(NvU32 level, NvU32 status NV_ASSERT_FAILED_FUNC_COMMA_ #define NV_CHECK_OK_OR_GOTO(status, level, expr, label) \ NV_CHECK_OK_OR_ELSE_STR(status, level, expr, #expr, goto label) +/** + * Check that an expression evaluates to NV_TRUE or else goto a label. + * + * @param[in] status The NV_STATUS variable to capture the status + * @param[in] level NV_PRINTF LEVEL to print at + * @param[in] expr Expression that evaluates to either NV_TRUE or NV_FALSE. + * @param[in] error Error to be reflected in @p status when @p expr evaluates + to NV_FALSE. + * @param[in] label Label to jump to when @p expr evaluates to NV_FALSE. +*/ +#define NV_CHECK_TRUE_OR_GOTO(status, level, expr, error, label) \ + NV_CHECK_OK_OR_ELSE_STR(status, level, ((expr) ? NV_OK : (error)), \ + #expr, goto label); + /** * Check that an expression evaluates to NV_OK or return the status. * diff --git a/src/nvidia/inc/libraries/utils/nvbitvector.h b/src/nvidia/inc/libraries/utils/nvbitvector.h index fccd2880e6..b027c39ad3 100644 --- a/src/nvidia/inc/libraries/utils/nvbitvector.h +++ b/src/nvidia/inc/libraries/utils/nvbitvector.h @@ -67,7 +67,7 @@ extern "C" { * .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. * 0 |1 | * 1 | 1| - * `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + * `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' * * Thus, in order to conceptually model an NV_BITVECTOR horizontally as * a continual ordered list of bits, one would have to write the @@ -240,20 +240,20 @@ struct NV_BITVECTOR } \ } -#define FOR_EACH_IN_BITVECTOR_PAIR(pBitVectorA, indexA, pBitVectorB, indexB)\ - { \ - MAKE_ANON_BITVECTOR(sizeof(((pBitVectorA)->last->_))) localMaskA; \ - bitVectorCopy(&localMaskA, (pBitVectorA)); \ - MAKE_ANON_BITVECTOR(sizeof(((pBitVectorB)->last->_))) localMaskB; \ - bitVectorCopy(&localMaskB, (pBitVectorB)); \ - for ((indexA) = bitVectorCountTrailingZeros(&localMaskA), \ - (indexB) = bitVectorCountTrailingZeros(&localMaskB); \ - !bitVectorTestAllCleared(&localMaskA) && \ - !bitVectorTestAllCleared(&localMaskB); \ - bitVectorClr(&localMaskA, (indexA)), \ - bitVectorClr(&localMaskB, (indexB)), \ - (indexA) = bitVectorCountTrailingZeros(&localMaskA), \ - (indexB) = bitVectorCountTrailingZeros(&localMaskB)) \ +#define FOR_EACH_IN_BITVECTOR_PAIR(pBitVectorA, indexA, pBitVectorB, indexB) \ + { \ + MAKE_ANON_BITVECTOR(sizeof(((pBitVectorA)->last->_))) localMaskA; \ + bitVectorCopy(&localMaskA, (pBitVectorA)); \ + MAKE_ANON_BITVECTOR(sizeof(((pBitVectorB)->last->_))) localMaskB; \ + bitVectorCopy(&localMaskB, (pBitVectorB)); \ + for ((indexA) = bitVectorCountTrailingZeros(&localMaskA), \ + (indexB) = bitVectorCountTrailingZeros(&localMaskB); \ + !bitVectorTestAllCleared(&localMaskA) && \ + !bitVectorTestAllCleared(&localMaskB); \ + bitVectorClr(&localMaskA, (indexA)), \ + bitVectorClr(&localMaskB, (indexB)), \ + (indexA) = bitVectorCountTrailingZeros(&localMaskA), \ + (indexB) = bitVectorCountTrailingZeros(&localMaskB)) \ { #define FOR_EACH_IN_BITVECTOR_PAIR_END() \ diff --git a/src/nvidia/inc/libraries/utils/nvmacro.h b/src/nvidia/inc/libraries/utils/nvmacro.h index b6407eed19..86f670a7aa 100644 --- a/src/nvidia/inc/libraries/utils/nvmacro.h +++ b/src/nvidia/inc/libraries/utils/nvmacro.h @@ -182,7 +182,7 @@ #define _NV_FOREACH_ARG_15(X, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15) \ X(_1), X(_2), X(_3), X(_4), X(_5), X(_6), X(_7), X(_8), X(_9), X(_10), X(_11), X(_12), X(_13), X(_14), X(_15) #define _NV_FOREACH_ARG_16(X, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16) \ - X(_1), X(_2), X(_3), X(_4), X(_5), X(_6), X(_7), X(_8), X(_9), X(_10), X(_11), X(_12), X(_13), X(_14), X(_15), X(_16) + X(_1), X(_2), X(_3), X(_4), X(_5), X(_6), X(_7), X(_8), X(_9), X(_10), X(_11), X(_12), X(_13), X(_14), X(_15), X(_16) // Iterating over empty list is unsupported. Give a semi-readable error. #define _NV_FOREACH_ARG_NOCOMMA_0(X) NV_FOREACH_NOCOMMA_ERROR_argument_list_emtpy @@ -218,16 +218,16 @@ #define _NV_FOREACH_ARG_NOCOMMA_15(X, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15) \ X(_1) X(_2) X(_3) X(_4) X(_5) X(_6) X(_7) X(_8) X(_9) X(_10) X(_11) X(_12) X(_13) X(_14) X(_15) #define _NV_FOREACH_ARG_NOCOMMA_16(X, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16) \ - X(_1) X(_2) X(_3) X(_4) X(_5) X(_6) X(_7) X(_8) X(_9) X(_10) X(_11) X(_12) X(_13) X(_14) X(_15) X(_16) + X(_1) X(_2) X(_3) X(_4) X(_5) X(_6) X(_7) X(_8) X(_9) X(_10) X(_11) X(_12) X(_13) X(_14) X(_15) X(_16) /// @endcond /// @cond NV_MACROS_COMPILE_TIME_TESTS // -// What follows are a couple of compile time smoke tests that will let us know +// What follows are a couple of compile time smoke tests that will let us know // if the given compiler does not properly implement these macros. // These are disabled by default in the interest of compile time. -// +// #if defined(NVMACRO_DO_COMPILETIME_TESTS) #if NV_NUM_ARGS(a) != 1 #error "[NvMacros CT Test] NV_NUM_ARGS fails when given 1 args" diff --git a/src/nvidia/inc/libraries/utils/nvrange.h b/src/nvidia/inc/libraries/utils/nvrange.h index f558e11edb..db9c20e58f 100644 --- a/src/nvidia/inc/libraries/utils/nvrange.h +++ b/src/nvidia/inc/libraries/utils/nvrange.h @@ -33,7 +33,7 @@ extern "C" { * \anchor NV_RANGE_1 * @defgroup NV_RANGE NV_RANGE * - * @brief Range is a sequence of unsigned 64 bit integers, represented by its + * @brief Range is a sequence of unsigned 64 bit integers, represented by its * lower and upper bounds, inclusive. * * @details Range is a general purpose data structure utility. @@ -44,15 +44,15 @@ extern "C" { * * @note If a range is declared like Range r = {0x0, 0x2} it consist * of elements 0x0, 0x1 and 0x2 , i.e. Range = [lo, hi] ! - * + * * > There are 4 possible options * > -# (lo, hi) lo+1 .. hi-1 * > -# [lo, hi) lo .. hi-1 * > -# (lo, hi] lo+1 .. hi * > -# [lo, hi] lo .. hi * - * Notice that only option 4 is capable of describing a full range. - * Full range would be 0x0..NvU64_MAX, where + * Notice that only option 4 is capable of describing a full range. + * Full range would be 0x0..NvU64_MAX, where * NvU64_MAX = 0xFFFFFFFFFFFFFFFF. * * @{ @@ -81,8 +81,8 @@ static NV_INLINE NvBool rangeIsEmpty(NV_RANGE range) /** * @brief Calculate range length in bytes. * - * @warning If the range is max, i.e. from 0 to NvU64_MAX, calling this - * function would result in overflow since range length is calculated + * @warning If the range is max, i.e. from 0 to NvU64_MAX, calling this + * function would result in overflow since range length is calculated * as hi-lo+1. * * @par Example: @@ -96,12 +96,12 @@ static NV_INLINE NvU64 rangeLength(NV_RANGE range) /** * @brief Creates a range * - * @details This is useful since on some compilers the following code won't + * @details This is useful since on some compilers the following code won't * work: `rangeLength({0, 100})`. * However, `rangeLength(rangeMake(0, 100))` will always work. - * - * @Returns Range of elements from and including \a lo to and - * including \a hi, i.e. [lo, hi] + * + * @Returns Range of elements from and including \a lo to and + * including \a hi, i.e. [lo, hi] */ static NV_INLINE NV_RANGE rangeMake(NvU64 lo, NvU64 hi) { @@ -124,7 +124,7 @@ static NV_INLINE NvBool rangeEquals(NV_RANGE range1, NV_RANGE range2) /** * @brief Check if \a range1 contains \a range2. - * + * * @param[in] range1 Container. * @param[in] range2 Containee. * @@ -144,8 +144,8 @@ static NV_INLINE NvBool rangeContains(NV_RANGE range1, NV_RANGE range2) */ static NV_INLINE NvBool rangeOverlaps(NV_RANGE range1, NV_RANGE range2) { - return (range1.lo <= range2.lo && range2.lo <= range1.hi) - || + return (range1.lo <= range2.lo && range2.lo <= range1.hi) + || (range1.lo <= range2.hi && range2.hi <= range1.hi) || (range2.lo <= range1.lo && range1.lo <= range2.hi) @@ -180,7 +180,7 @@ static NV_INLINE NV_RANGE rangeIntersection(NV_RANGE range1, NV_RANGE range2) * <0 - \a range1's lower bound is less than \a range2's lower bound, * >0 - \a range2's lower bound is greater than \a range2's lower bound. * - * @warning If function returns 0 that does not mean that ranges are equal, + * @warning If function returns 0 that does not mean that ranges are equal, * just that their lower bounds are equal! * * @par Example: @@ -198,14 +198,14 @@ static NV_INLINE NvS32 rangeCompare(NV_RANGE range1, NV_RANGE range2) /** * @brief Merge two ranges into one. - * - * @returns Merged range. If two ranges have no intersection + * + * @returns Merged range. If two ranges have no intersection * the returned range will be empty. * * @note Empty range is range with lo > hi. * * @par Example: - * @snippet nv_range-test.cpp rangeMergeExample + * @snippet nv_range-test.cpp rangeMergeExample */ static NV_INLINE NV_RANGE rangeMerge(NV_RANGE range1, NV_RANGE range2) { @@ -232,11 +232,11 @@ static NV_INLINE NV_RANGE rangeMerge(NV_RANGE range1, NV_RANGE range2) } /** - * @brief Checks if \a range1 borders with \a range2, i.e. \a range1.lo == + * @brief Checks if \a range1 borders with \a range2, i.e. \a range1.lo == * \a range2.hi+1 or \a range2.lo == \a range1.hi+1 - * + * * @note [a,b] borders with [b+1,c] where a < b < c - * + * */ static NV_INLINE NvBool rangeBorders(NV_RANGE range1, NV_RANGE range2) { @@ -249,7 +249,7 @@ static NV_INLINE NvBool rangeBorders(NV_RANGE range1, NV_RANGE range2) } /** - * @brief Splits \a pBigRange + * @brief Splits \a pBigRange * * @param[in] pBigRange Pointer to starting range. * @param[in] rangeToSplit Range to split the first range over. @@ -258,10 +258,10 @@ static NV_INLINE NvBool rangeBorders(NV_RANGE range1, NV_RANGE range2) * @par Example: * @snippet nv_range-test.cpp rangeSplitExample */ -static NV_INLINE NV_STATUS rangeSplit(NV_RANGE *pBigRange, +static NV_INLINE NV_STATUS rangeSplit(NV_RANGE *pBigRange, NV_RANGE rangeToSplit, NV_RANGE *pSecondPartAfterSplit) { - if (rangeIsEmpty(*pBigRange) || rangeIsEmpty(rangeToSplit) || + if (rangeIsEmpty(*pBigRange) || rangeIsEmpty(rangeToSplit) || !rangeContains(*pBigRange, rangeToSplit)) { return NV_ERR_INVALID_ARGUMENT; diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated.h b/src/nvidia/interface/deprecated/rmapi_deprecated.h index 78281d3468..7ff005a38f 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated.h +++ b/src/nvidia/interface/deprecated/rmapi_deprecated.h @@ -65,7 +65,7 @@ typedef enum typedef struct _DEPRECATED_CONTEXT { NV_STATUS (*RmAlloc)(struct _DEPRECATED_CONTEXT *pContext, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, void *pAllocParams); + NvHandle *phObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize); NV_STATUS (*RmControl)(struct _DEPRECATED_CONTEXT *pContext, NvHandle hClient, NvHandle hObject, NvU32 cmd, void *pParams, NvU32 paramsSize); diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c b/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c index 12bc7e0eb1..0a72ac2cc5 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c @@ -36,6 +36,8 @@ #include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_INFO +#include + typedef NV_STATUS RmAllocMemoryFunc( DEPRECATED_CONTEXT *pContext, NvHandle hClient, @@ -165,7 +167,7 @@ _rmAllocMemorySystem *pAddress = NvP64_NULL; - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams, sizeof(allocParams)); if (status != NV_OK) return status; @@ -214,7 +216,7 @@ _rmAllocMemorySystemDynamic // Try with NV01_MEMORY_SYSTEM_DYNAMIC for NV01_DEVICE_0 parents status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, - NV01_MEMORY_SYSTEM_DYNAMIC, &allocParams); + NV01_MEMORY_SYSTEM_DYNAMIC, &allocParams, sizeof(allocParams)); *pLimit = allocParams.limit; @@ -255,7 +257,7 @@ _rmAllocMemorySystemOsDescriptor return NV_ERR_INVALID_FLAGS; } - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams, sizeof(allocParams)); return status; } @@ -324,7 +326,7 @@ _rmAllocMemoryLocalUser // // First attempt: try to allocate NV01_MEMORY_LOCAL_PHYSICAL - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, NV01_MEMORY_LOCAL_PHYSICAL, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, NV01_MEMORY_LOCAL_PHYSICAL, &allocParams, sizeof(allocParams)); if (status == NV_OK) { @@ -357,7 +359,7 @@ _rmAllocMemoryLocalUser // user-mode clients previously received hMemory of entire FB) // status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, - NV01_MEMORY_SYSTEM_DYNAMIC, &virtAllocParams); + NV01_MEMORY_SYSTEM_DYNAMIC, &virtAllocParams, sizeof(virtAllocParams)); } return status; @@ -381,7 +383,7 @@ _rmAllocMemoryLocalPrivileged *pLimit = 0xFFFFFFFF; // not used by clients - return pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, 0); + return pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, NULL, 0); } static NV_STATUS @@ -456,7 +458,7 @@ _rmAllocMemoryList COPY_FIELD(size); COPY_FIELD(align); - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams, sizeof(allocParams)); done: if (pPageArray) @@ -513,7 +515,7 @@ _rmAllocMemoryFromFlaObject COPY_FLA_FIELD(hExportHandle); COPY_FLA_FIELD(hExportClient); - status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams); + status = pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, &allocParams, sizeof(allocParams)); done: if (pMemoryFla) @@ -541,5 +543,5 @@ _rmAllocMemoryFramebufferConsole NvU64 *pLimit ) { - return pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, 0); + return pContext->RmAlloc(pContext, hClient, hParent, &hMemory, hClass, NULL, 0); } diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c b/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c index 9d70e68e6e..ddad2fcb8b 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c @@ -40,7 +40,7 @@ RmDeprecatedAllocObject ) { pArgs->status = pContext->RmAlloc(pContext, pArgs->hRoot, pArgs->hObjectParent, - &pArgs->hObjectNew, pArgs->hClass, 0); + &pArgs->hObjectNew, pArgs->hClass, NULL, 0); } void @@ -62,7 +62,7 @@ RmDeprecatedAddVblankCallback vblankArgs.pParm2 = pArgs->pParm2; status = pContext->RmAlloc(pContext, pArgs->hClient, pArgs->hDevice, - &pArgs->hVblank, NV9010_VBLANK_CALLBACK, &vblankArgs); + &pArgs->hVblank, NV9010_VBLANK_CALLBACK, &vblankArgs, sizeof(vblankArgs)); } else { @@ -113,7 +113,8 @@ RmDeprecatedAllocContextDma status = pContext->RmAlloc(pContext, hClient, hCtxDmaParent, &pArgs->hObjectNew, NV01_MEMORY_VIRTUAL, - &allocVirtualParams); + &allocVirtualParams, + sizeof(allocVirtualParams)); goto done; } @@ -124,7 +125,7 @@ RmDeprecatedAllocContextDma allocParams.limit = pArgs->limit; status = pContext->RmAlloc(pContext, hClient, hCtxDmaParent, - &pArgs->hObjectNew, pArgs->hClass, &allocParams); + &pArgs->hObjectNew, pArgs->hClass, &allocParams, sizeof(allocParams)); done: pArgs->status = status; diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c b/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c index 024a27495d..a7d6fb073e 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c @@ -28,6 +28,8 @@ #include "ctrl/ctrl0080/ctrl0080gpu.h" // NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE #include "nvos.h" +#include + NV_STATUS RmDeprecatedGetHandleParent ( @@ -135,7 +137,7 @@ RmDeprecatedFindOrCreateSubDeviceHandle *pHSubDevice = 0; - status = pContext->RmAlloc(pContext, hClient, hDeviceOrSubDevice, pHSubDevice, NV20_SUBDEVICE_0, 0); + status = pContext->RmAlloc(pContext, hClient, hDeviceOrSubDevice, pHSubDevice, NV20_SUBDEVICE_0, NULL, 0); return status; } @@ -163,10 +165,12 @@ NV_STATUS RmDeprecatedGetOrAllocObject } else { + // // Object does not exist yet, allocate. - void *pAllocParams = (void*)0; // TODO: Fill for classes that need them + // TODO: Fill alloc params for classes that need them + // status = pContext->RmAlloc(pContext, hClient, *pHObject, - pHObject, classId, pAllocParams); + pHObject, classId, NULL, 0); } return status; } diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c b/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c index a191d3886d..c18384e92d 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c @@ -29,6 +29,7 @@ #include "class/cl0071.h" // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR #include "class/cl50a0.h" // NV50_MEMORY_VIRTUAL #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER +#include "class/cl0042.h" // NV_MEMORY_EXTENDED_USER #include "ctrl/ctrl0041.h" // NV04_MEMORY #include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_INFO @@ -142,7 +143,7 @@ _rmVidHeapControlAllocCommon externalClassId = NV01_MEMORY_SYSTEM; status = pContext->RmAlloc(pContext, hClient, hDevice, phMemory, externalClassId, - pUserParams); + pUserParams, sizeof(*pUserParams)); pArgs->free = 0; pArgs->total = 0; @@ -539,7 +540,8 @@ _nvos32FunctionHwAlloc pArgs->hObjectParent, &pArgs->data.HwAlloc.allochMemory, NV01_MEMORY_HW_RESOURCES, - &allocParams); + &allocParams, + sizeof(allocParams)); pArgs->data.HwAlloc.hResourceHandle = pArgs->data.HwAlloc.allochMemory; @@ -590,7 +592,8 @@ _nvos32FunctionAllocOsDesc pArgs->hObjectParent, &pArgs->data.AllocOsDesc.hMemory, NV01_MEMORY_SYSTEM_OS_DESCRIPTOR, - &allocParams); + &allocParams, + sizeof(allocParams)); return status; } diff --git a/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c b/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c index d44fd9c6f0..58287f0377 100644 --- a/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c +++ b/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,6 +44,7 @@ NV_STATUS RmGssLegacyRpcCmd NV_STATUS status = NV_OK; GPU_MASK gpuMaskRelease = 0; void *pKernelParams = NULL; + NvBool bApiLockTaken = NV_FALSE; NV_ASSERT_OR_RETURN((pArgs->cmd & RM_GSS_LEGACY_MASK), NV_ERR_INVALID_STATE); @@ -54,18 +55,6 @@ NV_STATUS RmGssLegacyRpcCmd return NV_ERR_INSUFFICIENT_PERMISSIONS; } - NV_CHECK_OK_OR_ELSE(status, - LEVEL_ERROR, - serverGetClientUnderLock(&g_resServ, pArgs->hClient, &pClient), - return NV_ERR_INVALID_ARGUMENT); - - NV_CHECK_OK_OR_ELSE(status, - LEVEL_ERROR, - gpuGetByHandle(pClient, pArgs->hObject, NULL, &pGpu), - return NV_ERR_INVALID_ARGUMENT); - - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - if (pSecInfo->paramLocation == PARAM_LOCATION_USER) { pKernelParams = portMemAllocNonPaged(pArgs->paramsSize); @@ -84,6 +73,24 @@ NV_STATUS RmGssLegacyRpcCmd pKernelParams = (void*)pArgs->params; } + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_CLIENT); + if (status != NV_OK) + goto done; + + bApiLockTaken = NV_TRUE; + + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, pArgs->hClient, &pClient), + done); + + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + gpuGetByHandle(pClient, pArgs->hObject, NULL, &pGpu), + done); + + osRefGpuAccessNeeded(pGpu->pOsGpuInfo); + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, GPUS_LOCK_FLAGS_NONE, @@ -92,6 +99,7 @@ NV_STATUS RmGssLegacyRpcCmd if (status != NV_OK) goto done; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); status = pRmApi->Control(pRmApi, pArgs->hClient, pArgs->hObject, @@ -105,6 +113,16 @@ NV_STATUS RmGssLegacyRpcCmd rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); } + if (bApiLockTaken) + { + if (pGpu != NULL) + { + osUnrefGpuAccessNeeded(pGpu->pOsGpuInfo); + } + + rmapiLockRelease(); + } + if (pSecInfo->paramLocation == PARAM_LOCATION_USER) { if (status == NV_OK) diff --git a/src/nvidia/interface/nv-firmware-registry.h b/src/nvidia/interface/nv-firmware-registry.h new file mode 100644 index 0000000000..ab8b405031 --- /dev/null +++ b/src/nvidia/interface/nv-firmware-registry.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +// +// This file holds GPU firmware related registry key definitions that are +// shared between Windows and Unix +// + +#ifndef NV_FIRMWARE_REGISTRY_H +#define NV_FIRMWARE_REGISTRY_H + +// +// Registry key that when enabled, will enable use of GPU firmware. +// +// Possible mode values: +// 0 - Do not enable GPU firmware +// 1 - Enable GPU firmware +// 2 - (Default) Use the default enablement policy for GPU firmware +// +// Setting this to anything other than 2 will alter driver firmware- +// enablement policies, possibly disabling GPU firmware where it would +// have otherwise been enabled by default. +// +// Policy bits: +// +// POLICY_ALLOW_FALLBACK: +// As the normal behavior is to fail GPU initialization if this registry +// entry is set in such a way that results in an invalid configuration, if +// instead the user would like the driver to automatically try to fallback +// to initializing the failing GPU with firmware disabled, then this bit can +// be set (ex: 0x11 means try to enable GPU firmware but fall back if needed). +// Note that this can result in a mixed mode configuration (ex: GPU0 has +// firmware enabled, but GPU1 does not). +// +#define NV_REG_STR_ENABLE_GPU_FIRMWARE "EnableGpuFirmware" + +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK 0x0000000F +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_MODE_DEFAULT 0x00000002 + +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_MASK 0x000000F0 +#define NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK 0x00000010 + +#define NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE 0x00000012 + +// +// Registry key that when enabled, will send GPU firmware logs +// to the system log, when possible. +// +// Possible values: +// 0 - Do not send GPU firmware logs to the system log +// 1 - Enable sending of GPU firmware logs to the system log +// 2 - (Default) Enable sending of GPU firmware logs to the system log for +// the debug kernel driver build only +// +#define NV_REG_STR_ENABLE_GPU_FIRMWARE_LOGS "EnableGpuFirmwareLogs" + +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_DISABLE 0x00000000 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE 0x00000001 +#define NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG 0x00000002 + +#endif // NV_FIRMWARE_REGISTRY_H diff --git a/src/nvidia/interface/nv_sriov_defines.h b/src/nvidia/interface/nv_sriov_defines.h index 07746f3501..3d144780be 100644 --- a/src/nvidia/interface/nv_sriov_defines.h +++ b/src/nvidia/interface/nv_sriov_defines.h @@ -58,12 +58,18 @@ // Host PF interrupts +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_REQUEST 3:3 +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_REQUEST) + #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST 16:16 #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_EN (0x1) #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_DIS (0x0) #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST) -#define NV_DOORBELL_NOTIFY_LEAF_HOST_PF_MASK NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE) +#define NV_DOORBELL_NOTIFY_LEAF_HOST_PF_MASK (NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE) | \ + NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_TMR_HANDLE)) // Host VF interrupts diff --git a/src/nvidia/interface/nv_uvm_types.h b/src/nvidia/interface/nv_uvm_types.h index 96b68979cd..760b71c158 100644 --- a/src/nvidia/interface/nv_uvm_types.h +++ b/src/nvidia/interface/nv_uvm_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -92,6 +92,7 @@ typedef unsigned long long UvmGpuPointer; typedef struct uvmGpuSession_tag *uvmGpuSessionHandle; // gpuSessionHandle typedef struct uvmGpuDevice_tag *uvmGpuDeviceHandle; // gpuDeviceHandle typedef struct uvmGpuAddressSpace_tag *uvmGpuAddressSpaceHandle; // gpuAddressSpaceHandle +typedef struct uvmGpuTsg_tag *uvmGpuTsgHandle; // gpuTsgHandle typedef struct uvmGpuChannel_tag *uvmGpuChannelHandle; // gpuChannelHandle typedef struct uvmGpuCopyEngine_tag *uvmGpuCopyEngineHandle; // gpuObjectHandle @@ -280,6 +281,15 @@ typedef struct UvmGpuChannelInfo_tag // to kick off the new work. // volatile NvU32 *pWorkSubmissionToken; + + // GPU VAs of both GPFIFO and GPPUT are needed in Confidential Computing + // so a channel can be controlled via another channel (SEC2 or WLC/LCIC) + NvU64 gpFifoGpuVa; + NvU64 gpPutGpuVa; + // GPU VA of work submission offset is needed in Confidential Computing + // so CE channels can ring doorbell of other channels as required for + // WLC/LCIC work submission + NvU64 workSubmissionOffsetGpuVa; } UvmGpuChannelInfo; typedef enum @@ -292,6 +302,17 @@ typedef enum UVM_BUFFER_LOCATION_VID = 2, } UVM_BUFFER_LOCATION; +typedef struct UvmGpuTsgAllocParams_tag +{ + // Interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE + NvU32 engineType; + + // Index of the engine the TSG is bound to. + // Ignored if engineType is anything other than + // UVM_GPU_CHANNEL_ENGINE_TYPE_CE. + NvU32 engineIndex; +} UvmGpuTsgAllocParams; + typedef struct UvmGpuChannelAllocParams_tag { NvU32 numGpFifoEntries; @@ -300,13 +321,9 @@ typedef struct UvmGpuChannelAllocParams_tag NvU32 gpFifoLoc; NvU32 gpPutLoc; - // Index of the engine the channel will be bound to - // ignored if engineType is anything other than UVM_GPU_CHANNEL_ENGINE_TYPE_CE - NvU32 engineIndex; - - // interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE - NvU32 engineType; - + // Allocate the channel as secure. This flag should only be set when + // Confidential Compute is enabled. + NvBool secure; } UvmGpuChannelAllocParams; typedef struct UvmGpuPagingChannelAllocParams_tag @@ -350,6 +367,9 @@ typedef struct // True if the CE can be used for P2P transactions NvBool p2p:1; + // True if the CE supports encryption + NvBool secure:1; + // Mask of physical CEs assigned to this LCE // // The value returned by RM for this field may change when a GPU is @@ -372,39 +392,16 @@ typedef enum UVM_LINK_TYPE_NVLINK_2, UVM_LINK_TYPE_NVLINK_3, UVM_LINK_TYPE_NVLINK_4, + UVM_LINK_TYPE_C2C, } UVM_LINK_TYPE; typedef struct UvmGpuCaps_tag { - NvU32 sysmemLink; // UVM_LINK_TYPE - NvU32 sysmemLinkRateMBps; // See UvmGpuP2PCapsParams::totalLinkLineRateMBps + // If numaEnabled is NV_TRUE, then the system address of allocated GPU + // memory can be converted to struct pages. See + // UvmGpuInfo::systemMemoryWindowStart. NvBool numaEnabled; NvU32 numaNodeId; - - // On ATS systems, GPUs connected to different CPU sockets can have peer - // traffic. They are called indirect peers. However, indirect peers are - // mapped using sysmem aperture. In order to disambiguate the location of a - // specific memory address, each GPU maps its memory to a different window - // in the System Physical Address (SPA) space. The following fields contain - // the base + size of such window for the GPU. systemMemoryWindowSize - // different than 0 indicates that the window is valid. - // - // - If the window is valid, then we can map GPU memory to the CPU as - // cache-coherent by adding the GPU address to the window start. - // - If numaEnabled is NV_TRUE, then we can also convert the system - // addresses of allocated GPU memory to struct pages. - // - // TODO: Bug 1986868: fix window start computation for SIMICS - NvU64 systemMemoryWindowStart; - NvU64 systemMemoryWindowSize; - - // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch - // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, - // nvswitchMemoryWindowStart tells the base address for the GPU in the - // NVSwitch address space. It is used when creating PTEs of memory mappings - // to NVSwitch peers. - NvBool connectedToSwitch; - NvU64 nvswitchMemoryWindowStart; } UvmGpuCaps; typedef struct UvmGpuAddressSpaceInfo_tag @@ -436,6 +433,8 @@ typedef struct UvmGpuAllocInfo_tag NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved + NvBool bUnprotected; // Allocation to be made in unprotected memory whenever + // SEV or GPU CC modes are enabled. Ignored otherwise } UvmGpuAllocInfo; typedef enum @@ -584,6 +583,20 @@ typedef struct UvmGpuClientInfo_tag NvHandle hSmcPartRef; } UvmGpuClientInfo; +typedef enum +{ + UVM_GPU_CONF_COMPUTE_MODE_NONE, + UVM_GPU_CONF_COMPUTE_MODE_APM, + UVM_GPU_CONF_COMPUTE_MODE_HCC, + UVM_GPU_CONF_COMPUTE_MODE_COUNT +} UvmGpuConfComputeMode; + +typedef struct UvmGpuConfComputeCaps_tag +{ + // Out: GPU's confidential compute mode + UvmGpuConfComputeMode mode; +} UvmGpuConfComputeCaps; + #define UVM_GPU_NAME_LENGTH 0x40 typedef struct UvmGpuInfo_tag @@ -648,6 +661,31 @@ typedef struct UvmGpuInfo_tag UvmGpuClientInfo smcUserClientInfo; + // Confidential Compute capabilities of this GPU + UvmGpuConfComputeCaps gpuConfComputeCaps; + + // UVM_LINK_TYPE + NvU32 sysmemLink; + + // See UvmGpuP2PCapsParams::totalLinkLineRateMBps + NvU32 sysmemLinkRateMBps; + + // On coherent systems each GPU maps its memory to a window in the System + // Physical Address (SPA) space. The following fields describe that window. + // + // systemMemoryWindowSize > 0 indicates that the window is valid. meaning + // that GPU memory can be mapped by the CPU as cache-coherent by adding the + // GPU address to the window start. + NvU64 systemMemoryWindowStart; + NvU64 systemMemoryWindowSize; + + // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch + // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, + // nvswitchMemoryWindowStart tells the base address for the GPU in the + // NVSwitch address space. It is used when creating PTEs of memory mappings + // to NVSwitch peers. + NvBool connectedToSwitch; + NvU64 nvswitchMemoryWindowStart; } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag @@ -690,6 +728,9 @@ typedef struct UvmPmaStatistics_tag volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions + volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory + volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory + volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory } UvmPmaStatistics; /******************************************************************************* @@ -768,24 +809,80 @@ struct UvmOpsUvmEvents uvmEventIsrTopHalf_t isrTopHalf; }; +#define UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES 32 +#define UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES 16 + +typedef union UvmFaultMetadataPacket_tag +{ + struct { + NvU8 authTag[UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES]; + NvBool valid; + }; + // padding to 32Bytes + NvU8 _padding[32]; +} UvmFaultMetadataPacket; + typedef struct UvmGpuFaultInfo_tag { struct { - // Register mappings obtained from RM + // Fault buffer GET register mapping. + // + // When Confidential Computing is enabled, GET refers to the shadow + // buffer (see bufferAddress below), and not to the actual HW buffer. + // In this setup, writes of GET (by UVM) do not result on re-evaluation + // of any interrupt condition. volatile NvU32* pFaultBufferGet; + + // Fault buffer PUT register mapping. + // + // When Confidential Computing is enabled, PUT refers to the shadow + // buffer (see bufferAddress below), and not to the actual HW buffer. + // In this setup, writes of PUT (by GSP-RM) do not result on + // re-evaluation of any interrupt condition. volatile NvU32* pFaultBufferPut; - // Note: this variable is deprecated since buffer overflow is not a separate - // register from future chips. + + // Note: this variable is deprecated since buffer overflow is not a + // separate register from future chips. volatile NvU32* pFaultBufferInfo; + + // Register mapping used to clear a replayable fault interrupt in + // Turing+ GPUs. volatile NvU32* pPmcIntr; + + // Register mapping used to enable replayable fault interrupts. volatile NvU32* pPmcIntrEnSet; + + // Register mapping used to disable replayable fault interrupts. volatile NvU32* pPmcIntrEnClear; + + // Register used to enable, or disable, faults on prefetches. volatile NvU32* pPrefetchCtrl; + + // Replayable fault interrupt mask identifier. NvU32 replayableFaultMask; - // fault buffer cpu mapping and size - void* bufferAddress; + + // Fault buffer CPU mapping + void* bufferAddress; + // + // When Confidential Computing is disabled, the mapping points to the + // actual HW fault buffer. + // + // When Confidential Computing is enabled, the mapping points to a + // copy of the HW fault buffer. This "shadow buffer" is maintained + // by GSP-RM. + + // Size, in bytes, of the fault buffer pointed by bufferAddress. NvU32 bufferSize; + // Mapping pointing to the start of the fault buffer metadata containing + // a 16Byte authentication tag and a valid byte. Always NULL when + // Confidential Computing is disabled. + UvmFaultMetadataPacket *bufferMetadata; + + // Indicates whether UVM owns the replayable fault buffer. + // The value of this field is always NV_TRUE When Confidential Computing + // is disabled. + NvBool bUvmOwnsHwFaultBuffer; } replayable; struct { @@ -805,8 +902,19 @@ typedef struct UvmGpuFaultInfo_tag // Preallocated stack for functions called from the UVM isr bottom half void *isr_bh_sp; + // Used only when Hopper Confidential Compute is enabled + // Register mappings obtained from RM + volatile NvU32* pFaultBufferPut; + + // Used only when Hopper Confidential Compute is enabled + // Cached get index of the non-replayable shadow buffer + NvU32 shadowBufferGet; + + // See replayable.bufferMetadata + UvmFaultMetadataPacket *shadowBufferMetadata; } nonReplayable; NvHandle faultBufferHandle; + struct Device *pDevice; } UvmGpuFaultInfo; struct Device; @@ -842,12 +950,6 @@ typedef struct UvmGpuAccessCntrInfo_tag void* bufferAddress; NvU32 bufferSize; NvHandle accessCntrBufferHandle; - - // The Notification address in the access counter notification msg does not - // contain the correct upper bits 63-47 for GPA-based notifications. RM - // provides us with the correct offset to be added. - // See Bug 1803015 - NvU64 baseDmaSysmemAddr; } UvmGpuAccessCntrInfo; typedef enum @@ -890,6 +992,7 @@ typedef enum UvmPmaGpuMemoryType_tag } UVM_PMA_GPU_MEMORY_TYPE; typedef UvmGpuChannelInfo gpuChannelInfo; +typedef UvmGpuTsgAllocParams gpuTsgAllocParams; typedef UvmGpuChannelAllocParams gpuChannelAllocParams; typedef UvmGpuCaps gpuCaps; typedef UvmGpuCopyEngineCaps gpuCeCaps; @@ -914,4 +1017,24 @@ typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo; typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams; typedef UvmPmaAllocationOptions gpuPmaAllocationOptions; +// This struct shall not be accessed nor modified directly by UVM as it is +// entirely managed by the RM layer +typedef struct UvmCslContext_tag +{ + struct ccslContext_t *ctx; + void *nvidia_stack; +} UvmCslContext; + +typedef struct UvmCslIv +{ + NvU8 iv[12]; + NvU8 fresh; +} UvmCslIv; + +typedef enum UvmCslDirection +{ + UVM_CSL_DIR_CPU_TO_GPU, + UVM_CSL_DIR_GPU_TO_CPU +} UvmCslDirection; + #endif // _NV_UVM_TYPES_H_ diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index 367e18e30e..7c1b1de54c 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +// +// This file holds NVIDIA Resource Manager registry key definitions that are +// shared between Windows and Unix +// + #ifndef NVRM_REGISTRY_H #define NVRM_REGISTRY_H @@ -471,17 +476,6 @@ // 1 - Enable RM event tracing -#define NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA "AllocCtxBuffersFromPMA" -#define NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA_DISABLE 0 -#define NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA_DEFAULT 0 -#define NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA_ENABLE 1 -// Type DWORD -// Encoding boolean -// Enable/Disable context buffers from being allocated in PMA -// 0 - Disable PMA allocation for context buffers and allocate from reserved memory -// 1 - Enable PMA allocation for context buffers and do not allocate from reserved memory - - #define NV_REG_STR_RM_COMPUTE_MODE_RULES "RmComputeModeRules" // Type DWORD // Saves the last compute mode rule set by the client. @@ -1821,4 +1815,104 @@ #define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_NO 0 #define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_YES 1 +// +// Add the conditions to exclude these macros from Orin build, as CONFIDENTIAL_COMPUTE +// is a guardword. The #if could be removed when nvRmReg.h file is trimmed from Orin build. +// +// Enable Disable Confidential Compute and control its various modes of operation +// 0 - Feature Disable +// 1 - Feature Enable +// +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE "RmConfidentialCompute" +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED 0:0 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED_NO 0x00000000 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_ENABLED_YES 0x00000001 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED 1:1 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED_NO 0x00000000 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_DEV_MODE_ENABLED_YES 0x00000001 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK 2:2 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK_DISABLED 0x00000000 +#define NV_REG_STR_RM_CONFIDENTIAL_COMPUTE_GPUS_READY_CHECK_ENABLED 0x00000001 + +#define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT "RmConfComputeEarlyInit" +#define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT_DISABLED 0x00000000 +#define NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT_ENABLED 0x00000001 + +// +// Enable/disable SPDM feature in Confidential Compute. SPDM-capable profiles +// may not be loaded by default. This regkey allows us to override the default +// behavior and force SPDM to enabled/disabled. +// +// 0 - Feature disable +// 1 - Feature enable +// +#define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY "RmConfComputeSpdmPolicy" +#define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED 0:0 +#define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED_NO 0x00000000 +#define NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY_ENABLED_YES 0x00000001 + +// TYPE Dword +// Encoding boolean +// Regkey based solution to serialize VBlank Aggressive Handling in Top Half using spinlock +// 2 - Enable serialization of aggressive vblank callbacks when HMD is active +// +// +// 1 - Enable serialization of aggressive vblank callbacks in all scenarios +// (even when a HMD is not active) +// +// 0 - (default) Disable WAR +// This regkey settings are enabled when Aggressive Vblanks are enabled, +// if RmDisableAggressiveVblank is set to disable then these regkeys do not have any affect +#define NV_REG_STR_RM_BUG_2089053_WAR "RmBug2089053War" +#define NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ON_HMD_ACTIVE_ONLY 0x00000002 +#define NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS 0x00000001 +#define NV_REG_STR_RM_BUG_2089053_WAR_DISABLE 0x00000000 +#define NV_REG_STR_RM_BUG_2089053_WAR_DEFAULT (NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS) + +// +// Controls whether GSP-RM profiling is enabled. +// 0 (default): disabled +// 1: enabled +// +#define NV_REG_STR_RM_GSPRM_PROFILING "RmGspRmProfiling" +#define NV_REG_STR_RM_GSPRM_PROFILING_DISABLE 0 +#define NV_REG_STR_RM_GSPRM_PROFILING_ENABLE 1 + +// +// Enable Local EGM HW verification using RM/SW stack. +// Must be specified with a peerID corresponding to local EGM +// +#define NV_REG_STR_RM_ENABLE_LOCAL_EGM_PEER_ID "RMEnableLocalEgmPeerId" + +// +// Overrides the size of the GSP-RM firmware heap in GPU memory. +// The GSP-RM firmware heap is reserved for system use and is not available to +// applications. This regkey can be used to optimize the amount of memory +// reserved for system use for targeted use cases. The default value for this +// regkey is determined to support certain worst case resource allocation +// patterns, but many use cases do not exhibit such resource allocation patterns +// and could benefit from the lesser reserved GPU memory. Other use cases may +// exhibit an even more pathological/stressful resource allocation pattern, +// which can be enabled (up to a limit) with this regkey. +// +// However, NVIDIA does not support setting this registry key, and will require +// that any bugs observed with it set be reproducible with the default setting +// as well. +// +// The value of this regkey is specified in megabytes. A value of 0 indicates to +// use the default value. Values less than the minimum or greater than the +// maximum will be clamped to the nearest optimum. The default values are +// are dynamically computed for each GPU prior to booting GSP-RM. +// +#define NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB "RmGspFirmwareHeapSizeMB" +#define NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB_DEFAULT 0 + +// +// Type DWORD +// This regkey can be used to enable GSP owned fault buffers +// +#define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE "RmGspOwnedFaultBuffersEnable" +#define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_NO 0x00000000 +#define NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_YES 0x00000001 + #endif // NVRM_REGISTRY_H diff --git a/src/nvidia/interface/rmapi/src/g_finn_rm_api.c b/src/nvidia/interface/rmapi/src/g_finn_rm_api.c index 6d752d925e..835910cd45 100644 --- a/src/nvidia/interface/rmapi/src/g_finn_rm_api.c +++ b/src/nvidia/interface/rmapi/src/g_finn_rm_api.c @@ -27,7 +27,13 @@ #elif defined(NV_LIBOS) /* LIBOS */ #include #include "nvport/nvport.h" -#else /* User Mode */ +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#include +#include +#include +extern void *rmapi_import_malloc(size_t size); +extern void rmapi_import_free(void *ptr); +#else /* Default */ #include #include #include @@ -52,7 +58,10 @@ #elif defined(NV_LIBOS) /* LIBOS */ #define FINN_MALLOC(size) portMemAllocNonPaged(size) -#else /* User Mode */ +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#define FINN_MALLOC(size) rmapi_import_malloc(size) + +#else /* Default */ #define FINN_MALLOC(size) malloc(size) #endif @@ -64,7 +73,10 @@ #elif defined(NV_LIBOS) /* LIBOS */ #define FINN_FREE(buf) portMemFree(buf) -#else /* User Mode */ +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#define FINN_FREE(buf) rmapi_import_free(buf) + +#else /* Default */ #define FINN_FREE(buf) free(buf) #endif @@ -76,7 +88,10 @@ #elif defined(NV_LIBOS) /* LIBOS */ #define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) -#else /* User Mode */ +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#define FINN_MEMZERO(buf, size) memset(buf, 0, size) + +#else /* Default */ #define FINN_MEMZERO(buf, size) memset(buf, 0, size) #endif @@ -88,19 +103,16 @@ #elif defined(NV_LIBOS) /* LIBOS */ #define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) -#else /* User Mode */ +#elif defined(USE_CUSTOM_MALLOC) /* OpenGL */ +#define FINN_MEMCPY(dst, src, size) memcpy(dst, src, size) + +#else /* Default */ #define FINN_MEMCPY(dst, src, size) memcpy(dst, src, size) #endif // Report an error. #if defined(FINN_ERROR) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_ERROR(err) /* No-op */ - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_ERROR(err) /* No-op */ - -#else /* User Mode */ +#else /* Default */ #define FINN_ERROR(err) /* No-op */ #endif @@ -115,7 +127,6 @@ typedef struct finn_bit_pump_for_read finn_bit_pump_for_read; struct finn_bit_pump_for_read { uint64_t accumulator; // Bits not yet read from the data buffer - uint64_t checksum; // Checksum of data const uint64_t *buffer_position; // Next word within data buffer to be read const uint64_t *end_of_data; // End of data within buffer uint8_t remaining_bit_count; // Number of bits remaining in the accumulator @@ -135,7 +146,6 @@ struct finn_bit_pump_for_read static inline void finn_open_buffer_for_read(finn_bit_pump_for_read *bp, const uint64_t *sod, const uint64_t *eod) { bp->accumulator = 0U; - bp->checksum = 0U; bp->buffer_position = sod; bp->end_of_data = eod; bp->remaining_bit_count = 0U; @@ -155,7 +165,7 @@ static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) uint64_t value; // Boundary crossing - // Accumulator does not have enough to satisfy the request, + // Accumulator does not have enough to satisfy the request. if (bit_size > bp->remaining_bit_count) { // Number of bits not yet satisfied @@ -172,9 +182,6 @@ static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) else bp->accumulator = *(bp->buffer_position++); - // Update the checksum. - bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; - // // This is the special case where we are reading an entire 64-bit word // without crossing a boundary (when the accumulator is empty). The @@ -186,6 +193,9 @@ static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) // would exceed the 64-bit capacity. However, the needed logic is simple. // // 64 is the largest legal value for `bit_size`, so `>=` is equivalent to `==`. + // Furthermore, if `bit_size == 64`, then `bp->remaining_bit_count` must + // have been zero when subtracted above. That's how we know that there is + // no boundary crossing. // if (bit_size >= 64) { @@ -231,22 +241,7 @@ static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) } -// Close the read buffer. -// Postcondition: `bp->checksum` is updated to end-of-data. -static inline void finn_close_buffer_for_read(finn_bit_pump_for_read *bp) -{ - // No need to update the bit pump buffer position, - // so use a local for optimal performance. - const uint64_t *p = bp->buffer_position; - - // Apply any unread words to the checksum. - while (p < bp->end_of_data) - bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ (*(p++)); -} - - typedef struct finn_bit_pump_for_write finn_bit_pump_for_write; - struct finn_bit_pump_for_write { uint64_t accumulator; // Bits not yet written to the data buffer @@ -394,7 +389,10 @@ static inline void finn_close_buffer_for_write(finn_bit_pump_for_write *bp) static NV_STATUS finnSerializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *api, NvLength dst_size, NvBool deser_up); +#if (defined(NVRM)) NvBool finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(NV402C_CTRL_I2C_TRANSACTION_TYPE value); +#endif // (defined(NVRM)) + static NV_STATUS finnSerializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *api_intf, NvLength api_size, NvBool deser_up); static NvU64 finnUnserializedInterfaceSize_FINN_GT200_DEBUGGER_DEBUG(NvU64 message); @@ -453,6 +451,7 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 me static NV_STATUS finnSerializeInterface_FINN_NV40_I2C_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeInterface_FINN_NV40_I2C_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *api_intf, NvLength api_size, NvBool deser_up); static NvU64 finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(NvU64 message); +#if (defined(NVRM)) static NV_STATUS finnSerializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up); static NV_STATUS finnSerializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); @@ -463,8 +462,11 @@ static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(const NV0 static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) + static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, NvLength api_size, NvBool deser_up); +#if (defined(NVRM)) static NV_STATUS finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up); static NV_STATUS finnSerializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(const NV0080_CTRL_GR_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); @@ -487,7 +489,9 @@ static NV_STATUS finnSerializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(const NV20 static NV_STATUS finnDeserializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up); static NV_STATUS finnSerializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) +#if (defined(NVRM)) static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(const NV402C_CTRL_I2C_INDEXED_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *api, NvLength api_size, NvBool deser_up); static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); @@ -504,11 +508,16 @@ static NV_STATUS finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(co static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up); static NV_STATUS finnSerializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) + static NV_STATUS finnSerializeRecord_NV0080_CTRL_FIFO_CHANNEL(const NV0080_CTRL_FIFO_CHANNEL *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeRecord_NV0080_CTRL_FIFO_CHANNEL(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *api, NvLength api_size, NvBool deser_up); +#if (defined(NVRM)) static NV_STATUS finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES(const NV2080_CTRL_GPUMON_SAMPLES *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) +#if (defined(NVRM)) static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, NvLength api_size, NvBool deser_up); static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); @@ -531,12 +540,16 @@ static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUIC static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, NvLength api_size, NvBool deser_up); static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, NvLength api_size, NvBool deser_up); +#endif // (defined(NVRM)) +#if (defined(NVRM)) static NV_STATUS finnSerializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(const NV402C_CTRL_I2C_TRANSACTION_DATA *api, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); static NV_STATUS finnDeserializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *api, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); +#endif // (defined(NVRM)) + // Serialize this API. -NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char **dst, NvLength dst_size, NvBool seri_up) +NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char *dst, NvLength dst_size, NvBool seri_up) { // Header FINN_RM_API *header; @@ -554,17 +567,17 @@ NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, cons // Input validation // Null pointers are not permitted. // Buffer must begin on an 8-byte boundary. - if (!api || !dst || !(*dst) || !dst_size || (uintptr_t) dst & 0x7u) + if (!api || !dst || !dst_size || (uintptr_t) dst & 0x7u) { FINN_ERROR(NV_ERR_INVALID_ARGUMENT); return NV_ERR_INVALID_ARGUMENT; } // Header is at the start of the buffer. - header = (FINN_RM_API *) *dst; + header = (FINN_RM_API *) dst; // Buffer must end on an 8-byte boundary, so round down. - dst_end = (const char *) ((uintptr_t) (*dst + dst_size) & ~ (uintptr_t) 0x7); + dst_end = (const char *) ((uintptr_t) (dst + dst_size) & ~ (uintptr_t) 0x7); // Set header data. header->version = FINN_SERIALIZATION_VERSION; @@ -573,10 +586,10 @@ NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, cons header->message = message; // Advance past header. - (*dst) += sizeof(FINN_RM_API); + dst += sizeof(FINN_RM_API); // Open the bit pump. - finn_open_buffer_for_write(&bp, (uint64_t *) *dst, (const uint64_t *) dst_end); + finn_open_buffer_for_write(&bp, (uint64_t *) dst, (const uint64_t *) dst_end); // Call the serializer. error_code = finnSerializeRoot_FINN_RM_API(interface, message, api, &bp, seri_up); @@ -588,9 +601,6 @@ NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, cons if (error_code == NV_OK) header->payloadSize = (NvU64) (((const char *) bp.buffer_position) - ((const char *) header)); - // Indicate the ending location. - *dst = (char *) bp.buffer_position; - // Done return error_code; } @@ -652,7 +662,7 @@ static NV_STATUS finnSerializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, c // Deserialize this API. -NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up) +NV_STATUS finnDeserializeInternal_FINN_RM_API(const char *src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up) { // Header const FINN_RM_API *header; @@ -669,14 +679,14 @@ NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_siz // Input validation // Null pointers are not permitted. // Buffer must begin on an 8-byte boundary. - if (!src || !(*src) || !src_size || !api || !api_size || (uintptr_t) *src & 0x7u) + if (!src || !src_size || !api || !api_size || (uintptr_t) src & 0x7u) { FINN_ERROR(NV_ERR_INVALID_ARGUMENT); return NV_ERR_INVALID_ARGUMENT; } // Header data comes first. - header = (const FINN_RM_API *) *src; + header = (const FINN_RM_API *) src; // Check the version. if (header->version != FINN_SERIALIZATION_VERSION) @@ -686,36 +696,27 @@ NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_siz } // Set src_max for buffer bounds checking. - src_max = *src + src_size; + src_max = src + src_size; // Check that source buffer is large enough. if (sizeof(FINN_RM_API) > src_size || header->payloadSize > src_size || header->payloadSize < sizeof(FINN_RM_API)) { - *src = (const char *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); return NV_ERR_BUFFER_TOO_SMALL; } // Open the bit punp, skipping past the header. - finn_open_buffer_for_read(&bp, (const uint64_t *) (*src + sizeof(FINN_RM_API)), (const uint64_t *) (src_max)); + finn_open_buffer_for_read(&bp, (const uint64_t *) (src + sizeof(FINN_RM_API)), (const uint64_t *) (src_max)); // Dispatch to interface-specific routine status = finnDeserializeRoot_FINN_RM_API(header->interface, header->message, &bp, api, api_size, deser_up); - // Update the buffer position, error or not. - *(src) = (const char *) bp.buffer_position; - // Nothing more to do if there was an error. if (status != NV_OK) return status; - // Update the checksum. - finn_close_buffer_for_read(&bp); - - // TODO: Check the checksum - // Check that the declared size matches the serialization outcome. if (header->payloadSize != (NvU64) (((const char *) bp.buffer_position) - ((const char *) header))) { @@ -857,6 +858,7 @@ NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message) return 0; } } // end FINN_RM_APIGetUnserializedSize +#if (defined(NVRM)) // Validate the enum value. NvBool finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(NV402C_CTRL_I2C_TRANSACTION_TYPE value) { switch(value) @@ -879,16 +881,21 @@ NvBool finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(NV402C_CTRL_I2C_TRANSACTION_ } } +#endif // (defined(NVRM)) + // Serialize this interface. static NV_STATUS finnSerializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) { // Serialize one of 2 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): return finnSerializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS((const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) api_intf, bp, seri_up); case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): return finnSerializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS((const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -906,10 +913,13 @@ static NV_STATUS finnDeserializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 messag // Deerialize one of 2 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): return finnDeserializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(bp, (NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) api_intf, api_size, deser_up); case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): return finnDeserializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(bp, (NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -927,10 +937,13 @@ static NvU64 finnUnserializedInterfaceSize_FINN_GT200_DEBUGGER_DEBUG(NvU64 messa // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): return sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS); case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): return sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -944,12 +957,15 @@ static NV_STATUS finnSerializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU // Serialize one of 3 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): return finnSerializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS((const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) api_intf, bp, seri_up); case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): return finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS((const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) api_intf, bp, seri_up); case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): return finnSerializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS((const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -967,12 +983,15 @@ static NV_STATUS finnDeserializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(N // Deerialize one of 3 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): return finnDeserializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(bp, (NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) api_intf, api_size, deser_up); case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): return finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(bp, (NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) api_intf, api_size, deser_up); case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): return finnDeserializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(bp, (NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -990,12 +1009,15 @@ static NvU64 finnUnserializedInterfaceSize_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO( // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): return sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS); case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): return sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS); case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): return sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1009,8 +1031,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, co // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): return finnSerializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS((const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1028,8 +1053,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): return finnDeserializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(bp, (NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1047,8 +1075,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_DMA(NvU64 message) // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): return sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1062,8 +1093,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, con // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): return finnSerializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS((const NV0080_CTRL_FB_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1081,8 +1115,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, f // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): return finnDeserializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(bp, (NV0080_CTRL_FB_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1100,8 +1137,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FB(NvU64 message) // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): return sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1115,12 +1155,18 @@ static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, c // Serialize one of 3 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): return finnSerializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS((const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): return finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS((const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) api_intf, bp, seri_up); +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): return finnSerializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS((const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1138,12 +1184,18 @@ static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, // Deerialize one of 3 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): return finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(bp, (NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): return finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(bp, (NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) api_intf, api_size, deser_up); +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): return finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(bp, (NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1161,12 +1213,18 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FIFO(NvU64 message // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): return sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): return sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS); +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): return sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1180,8 +1238,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, co // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): return finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS((const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1199,8 +1260,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): return finnDeserializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(bp, (NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1218,8 +1282,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GPU(NvU64 message) // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): return sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1233,8 +1300,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, con // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): return finnSerializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS((const NV0080_CTRL_GR_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1252,8 +1322,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, f // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): return finnDeserializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(bp, (NV0080_CTRL_GR_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1271,8 +1344,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GR(NvU64 message) // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): return sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1286,8 +1362,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, c // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): return finnSerializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS((const NV0080_CTRL_HOST_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1305,8 +1384,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): return finnDeserializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(bp, (NV0080_CTRL_HOST_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1324,8 +1406,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_HOST(NvU64 message // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): return sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1339,8 +1424,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): return finnSerializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS((const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1358,8 +1446,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): return finnDeserializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(bp, (NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1377,8 +1468,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_MSENC(NvU64 messag // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): return sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1392,8 +1486,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, const // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): return finnSerializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS((const NV0000_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1411,8 +1508,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, finn // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): return finnDeserializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(bp, (NV0000_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1430,8 +1530,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV01_ROOT_NVD(NvU64 message) // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): return sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1445,8 +1548,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): return finnSerializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS((const NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1464,8 +1570,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 messa // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): return finnDeserializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(bp, (NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1483,8 +1592,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 mess // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): return sizeof(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1498,8 +1610,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): return finnSerializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS((const NV2080_CTRL_CE_GET_CAPS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1517,8 +1632,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): return finnDeserializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(bp, (NV2080_CTRL_CE_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1536,8 +1654,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_CE(NvU64 messag // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): return sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1551,10 +1672,13 @@ static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, // Serialize one of 2 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): return finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS((const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) api_intf, bp, seri_up); case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): return finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS((const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1572,10 +1696,13 @@ static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 messag // Deerialize one of 2 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): return finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(bp, (NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) api_intf, api_size, deser_up); case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): return finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(bp, (NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1593,10 +1720,13 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_GPU(NvU64 messa // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): return sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS); case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): return sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1610,8 +1740,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): return finnSerializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS((const NV2080_CTRL_I2C_ACCESS_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1629,8 +1762,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 messag // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): return finnDeserializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(bp, (NV2080_CTRL_I2C_ACCESS_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1648,8 +1784,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_I2C(NvU64 messa // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): return sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1663,8 +1802,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): return finnSerializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS((const NV2080_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1682,8 +1824,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 messag // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): return finnDeserializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(bp, (NV2080_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1701,8 +1846,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_NVD(NvU64 messa // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): return sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1716,8 +1864,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ return finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES((const NV2080_CTRL_GPUMON_SAMPLES *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1735,8 +1886,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 messa // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ return finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(bp, (NV2080_CTRL_GPUMON_SAMPLES *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1754,8 +1908,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_PERF(NvU64 mess // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ return sizeof(NV2080_CTRL_GPUMON_SAMPLES); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1769,8 +1926,11 @@ static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, // Serialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): return finnSerializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS((const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1788,8 +1948,11 @@ static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message // Deerialize one of 1 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): return finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(bp, (NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1807,8 +1970,11 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_RC(NvU64 messag // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): return sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1872,10 +2038,13 @@ static NV_STATUS finnSerializeInterface_FINN_NV40_I2C_I2C(NvU64 message, const c // Serialize one of 2 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): return finnSerializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS((const NV402C_CTRL_I2C_INDEXED_PARAMS *) api_intf, bp, seri_up); case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): return finnSerializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS((const NV402C_CTRL_I2C_TRANSACTION_PARAMS *) api_intf, bp, seri_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1893,10 +2062,13 @@ static NV_STATUS finnDeserializeInterface_FINN_NV40_I2C_I2C(NvU64 message, finn_ // Deerialize one of 2 messages in this interface. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): return finnDeserializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(bp, (NV402C_CTRL_I2C_INDEXED_PARAMS *) api_intf, api_size, deser_up); case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): return finnDeserializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(bp, (NV402C_CTRL_I2C_TRANSACTION_PARAMS *) api_intf, api_size, deser_up); +#endif // (defined(NVRM)) + // Everything else is unsupported. default: @@ -1914,10 +2086,13 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(NvU64 message) // Forward to message-specific routine. switch (message) { +#if (defined(NVRM)) case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): return sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS); case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): return sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS); +#endif // (defined(NVRM)) + // Zero indicates an unsupported message (or interface). default: @@ -1925,6 +2100,7 @@ static NvU64 finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(NvU64 message) } } +#if (defined(NVRM)) // Serialize each of the 3 field(s). // 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). @@ -2927,6 +3103,8 @@ static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS( return NV_OK; } +#endif // (defined(NVRM)) + // Serialize each of the 3 field(s). static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) @@ -3115,6 +3293,7 @@ static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS return NV_OK; } +#if (defined(NVRM)) // Serialize each of the 2 field(s). static NV_STATUS finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) @@ -5195,6 +5374,9 @@ static NV_STATUS finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(f return NV_OK; } +#endif // (defined(NVRM)) + +#if (defined(NVRM)) // Serialize each of the 8 field(s). // 1 out of 6 independent field(s) are reordered to be before 2 dependent field(s). @@ -6489,6 +6671,8 @@ static NV_STATUS finnDeserializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_P return NV_OK; } +#endif // (defined(NVRM)) + // Serialize each of the 1 field(s). static NV_STATUS finnSerializeRecord_NV0080_CTRL_FIFO_CHANNEL(const NV0080_CTRL_FIFO_CHANNEL *api, finn_bit_pump_for_write *bp, NvBool seri_up) @@ -6537,6 +6721,7 @@ static NV_STATUS finnDeserializeRecord_NV0080_CTRL_FIFO_CHANNEL(finn_bit_pump_fo return NV_OK; } +#if (defined(NVRM)) // Serialize each of the 5 field(s). static NV_STATUS finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES(const NV2080_CTRL_GPUMON_SAMPLES *api, finn_bit_pump_for_write *bp, NvBool seri_up) @@ -6753,6 +6938,9 @@ static NV_STATUS finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(finn_bit_pump_ return NV_OK; } +#endif // (defined(NVRM)) + +#if (defined(NVRM)) // Serialize each of the 3 field(s). static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) @@ -8431,6 +8619,9 @@ static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WO return NV_OK; } +#endif // (defined(NVRM)) + +#if (defined(NVRM)) // Serialize selected field from 11 possible values. static NV_STATUS finnSerializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(const NV402C_CTRL_I2C_TRANSACTION_DATA *api, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) @@ -8885,3 +9076,4 @@ static NV_STATUS finnDeserializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(finn_bit_ } +#endif // (defined(NVRM)) diff --git a/src/nvidia/kernel/inc/objrpc.h b/src/nvidia/kernel/inc/objrpc.h index d94330c91a..95e1dbbc3b 100644 --- a/src/nvidia/kernel/inc/objrpc.h +++ b/src/nvidia/kernel/inc/objrpc.h @@ -45,7 +45,11 @@ typedef struct _object_vgpu OBJVGPU, *POBJVGPU; #include "g_rpc_hal.h" // For RPC_HAL_IFACES #include "g_rpc_odb.h" // For RPC_HAL_IFACES +#define RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH 3 // rate limit after 3 prints +#define RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP 29 // skip 29 of 30 prints + #define RPC_HISTORY_DEPTH 8 + typedef struct RpcHistoryEntry { NvU32 function; @@ -75,6 +79,8 @@ struct OBJRPC{ RpcHistoryEntry rpcHistory[RPC_HISTORY_DEPTH]; NvU32 rpcHistoryCurrent; + NvU32 timeoutCount; + NvBool bQuietPrints; }; diff --git a/src/nvidia/kernel/inc/vgpu/rpc.h b/src/nvidia/kernel/inc/vgpu/rpc.h index 58a9db77c6..b790dbfbc9 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc.h +++ b/src/nvidia/kernel/inc/vgpu/rpc.h @@ -83,6 +83,7 @@ static inline void NV_RM_RPC_GSP_MSG_TIMING(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_VGPU_PF_REG_READ32(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION(OBJGPU *pGpu, ...) { return; } +static inline void NV_RM_RPC_INVALIDATE_TLB(OBJGPU *pGpu, ...) { return; } // RPC free stubs static inline void NV_RM_RPC_SIM_FREE_INFRA(OBJGPU *pGpu, ...) { return; } @@ -108,10 +109,10 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r \ if (!IsT234DorBetter(pGpu)) \ { \ - RmClient *pClient = NULL; \ + RmClient *pClient = serverutilGetClientUnderLock(hclient); \ \ /* Get process ID from the client database */ \ - if (NV_OK == serverutilGetClientUnderLock(hclient, &pClient)) \ + if (pClient != NULL) \ { \ CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); \ NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); \ @@ -132,7 +133,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r \ status = pRmApi->AllocWithHandle(pRmApi, hclient, NV01_NULL_OBJECT, \ NV01_NULL_OBJECT, NV01_ROOT, \ - &root_alloc_params); \ + &root_alloc_params, sizeof(root_alloc_params)); \ \ if (status == NV_OK) \ { \ @@ -145,7 +146,8 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r device_alloc_params.vaSpaceSize = vasize; \ \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hclient, hdevice, \ - hclass, &device_alloc_params); \ + hclass, &device_alloc_params, \ + sizeof(device_alloc_params)); \ } \ else \ NV_ASSERT(0); \ @@ -180,7 +182,8 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r DRF_DEF(OS02,_FLAGS,_PHYSICALITY,_NONCONTIGUOUS) | \ (flags & DRF_SHIFTMASK(NVOS02_FLAGS_COHERENCY))); \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hdevice, \ - hmemory, NV01_MEMORY_LIST_SYSTEM, &listAllocParams); \ + hmemory, NV01_MEMORY_LIST_SYSTEM, &listAllocParams, \ + sizeof(listAllocParams)); \ } \ else \ { \ @@ -279,13 +282,14 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hparent, hchannel, \ - hclass, pGpfifoAllocParams); \ + hclass, pGpfifoAllocParams, \ + sizeof(*pGpfifoAllocParams)); \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } \ while (0) -#define NV_RM_RPC_ALLOC_OBJECT(pGpu, hclient, hchannel, hobject, hclass, params, status)\ +#define NV_RM_RPC_ALLOC_OBJECT(pGpu, hclient, hchannel, hobject, hclass, params, paramsSize, status) \ do \ { \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ @@ -295,7 +299,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hchannel, hobject, \ - hclass, params); \ + hclass, params, paramsSize); \ } \ } while (0) @@ -348,7 +352,8 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r allocParams.data = 0; \ status = pRmApi->AllocWithHandle(pRmApi, hclient, \ hobject, hevent, \ - hclass, &allocParams); \ + hclass, &allocParams, \ + sizeof(allocParams)); \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) @@ -368,7 +373,8 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r alloc_params.subDeviceId = subDeviceInst; \ \ status = pRmApi->AllocWithHandle(pRmApi, hclient, hdevice, hsubdevice, \ - hclass, &alloc_params); \ + hclass, &alloc_params, \ + sizeof(alloc_params)); \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while (0) diff --git a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h index a065ea900b..527163be15 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h @@ -206,6 +206,7 @@ enum { X(RM, CTRL_GET_HS_CREDITS) // 197 X(RM, CTRL_SET_HS_CREDITS) // 198 X(RM, CTRL_PM_AREA_PC_SAMPLER) // 199 + X(RM, INVALIDATE_TLB) // 200 X(RM, NUM_FUNCTIONS) //END #ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H }; @@ -249,6 +250,7 @@ enum { E(GSP_SEND_USER_SHARED_DATA) // 0x101b E(NVLINK_FAULT_UP) // 0x101c E(GSP_LOCKDOWN_NOTICE) // 0x101d + E(MIG_CI_CONFIG_UPDATE) // 0x101e E(NUM_EVENTS) // END #ifdef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H }; diff --git a/src/nvidia/kernel/inc/vgpu/rpc_headers.h b/src/nvidia/kernel/inc/vgpu/rpc_headers.h index bff16d54d0..4f355095f6 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_headers.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_headers.h @@ -135,6 +135,7 @@ #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_RM_ERROR 0xFF100005 /* RW--V */ #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_VMIOP_ERROR 0xFF100006 /* RW--V */ #define NV_VGPU_MSG_RESULT_RPC_RESERVED_HANDLE 0xFF100007 /* RW--V */ +#define NV_VGPU_MSG_RESULT_RPC_CUDA_PROFILING_DISABLED 0xFF100008 /* RW--V */ /* RPC-specific code in result for incomplete request */ #define NV_VGPU_MSG_RESULT_RPC_PENDING 0xFFFFFFFF /* RW--V */ /* shared union field */ diff --git a/src/nvidia/kernel/inc/vgpu/sdk-structures.h b/src/nvidia/kernel/inc/vgpu/sdk-structures.h index 76e3708251..1d4cfea884 100644 --- a/src/nvidia/kernel/inc/vgpu/sdk-structures.h +++ b/src/nvidia/kernel/inc/vgpu/sdk-structures.h @@ -123,6 +123,7 @@ typedef struct vmiopd_SM_info { #define NV0080_CTRL_GR_INFO_MAX_SIZE_1E_02 (0x00000032) #define NV0080_CTRL_GR_INFO_MAX_SIZE_21_01 (0x00000033) #define NV0080_CTRL_GR_INFO_MAX_SIZE_22_02 (0x00000034) +#define NV0080_CTRL_GR_INFO_MAX_SIZE_23_00 (0x00000035) #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240 @@ -137,7 +138,6 @@ typedef struct vmiopd_SM_info { #define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50 #define NV2080_CTRL_MAX_PCES_v21_0A 32 #define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2 -#define NV2080_ENGINE_TYPE_COPY_SIZE_v21_0A 10 // Defined this intermediate RM-RPC structure for making RPC call from Guest as // we have the restriction of passing max 4kb of data to plugin and the @@ -182,8 +182,7 @@ struct pte_desc */ #define VGPU_CACHED_RMCTRL_LIST \ - VGPU_CACHED_RMCTRL_ENTRY(NV2080_CTRL_CMD_PERF_VPSTATES_GET_INFO, NV2080_CTRL_PERF_VPSTATES_INFO) \ - VGPU_CACHED_RMCTRL_ENTRY(NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS) + VGPU_CACHED_RMCTRL_ENTRY(NV2080_CTRL_CMD_PERF_VPSTATES_GET_INFO, NV2080_CTRL_PERF_VPSTATES_INFO) enum VGPU_CACHED_RMCTRL_INDICES { @@ -222,6 +221,11 @@ typedef struct VGPU_BSP_CAPS #define NV2080_ENGINE_TYPE_LAST_v18_01 (0x0000002a) #define NV2080_ENGINE_TYPE_LAST_v1C_09 (0x00000034) +#define NV2080_ENGINE_TYPE_LAST_v1A_00 (0x2a) + +#define NV2080_ENGINE_TYPE_COPY_SIZE_v1A_0D (10) +#define NV2080_ENGINE_TYPE_COPY_SIZE_v22_00 (10) + #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1A_0F (0x00000033) #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09 (0x00000034) diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_guest_pma_scrubber.h b/src/nvidia/kernel/inc/vgpu/vgpu_guest_pma_scrubber.h index adca3c1377..fa0b915b91 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_guest_pma_scrubber.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_guest_pma_scrubber.h @@ -34,7 +34,7 @@ #ifndef __vgpu_pma_guest_scrubber_h__ #define __vgpu_pma_guest_scrubber_h__ -#include "gpu/mem_mgr/virt_mem_allocator_common.h" +#include "gpu/mem_mgr/rm_page_size.h" #define VGPU_GUEST_PMA_MAX_SCRUB_ITEMS 4096 #define VGPU_GUEST_PMA_SCRUBBER_SHARED_BUFFER_SIZE ((sizeof(VGPU_SCRUB_NODE) * VGPU_GUEST_PMA_MAX_SCRUB_ITEMS) + RM_PAGE_SIZE) diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_version.h b/src/nvidia/kernel/inc/vgpu/vgpu_version.h index 6a73571bdf..640585fa27 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_version.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_version.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,8 +30,8 @@ #define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \ DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor)) -#define VGX_MAJOR_VERSION_NUMBER 0x22 -#define VGX_MINOR_VERSION_NUMBER 0x02 +#define VGX_MAJOR_VERSION_NUMBER 0x23 +#define VGX_MINOR_VERSION_NUMBER 0x03 #define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A #define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18 @@ -49,6 +49,7 @@ * 2. This is the first break in migration compatibility after a release. */ #define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \ + {{0x23, 0x0}, {0x23, 0x03}, {0x12, 0x1}}, \ {{0x22, 0x0}, {0x22, 0x02}, {0x11, 0x1}}, \ {{0x21, 0x0}, {0x21, 0x0C}, {0x10, 0x1}}, \ {{0x20, 0x0}, {0x20, 0x04}, {0xF, 0x1}}, \ @@ -94,7 +95,7 @@ /* WARNING: Should be updated with each vGPU release, if there is a break in * migration compatibility during the development of that release. */ -#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x11 +#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x12 #define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1 /* WARNING: Should be updated with each vGPU release, if minimum supported diff --git a/src/nvidia/kernel/nvd/nv/nvdctrl.c b/src/nvidia/kernel/nvd/nv/nvdctrl.c index 7f154d94b6..5a6f697abb 100644 --- a/src/nvidia/kernel/nvd/nv/nvdctrl.c +++ b/src/nvidia/kernel/nvd/nv/nvdctrl.c @@ -213,9 +213,9 @@ subdeviceCtrlCmdNvdGetNocatJournalRpt_IMPL pReportParams->nocatOutstandingRecordCount = rcdbGetNocatOutstandingCount(pRcdb); // add in the activity counters. - portMemCopy(pReportParams->activityCounters, NV_SIZEOF32(pReportParams->activityCounters), + portMemCopy(pReportParams->activityCounters, sizeof(pReportParams->activityCounters), pRcdb->nocatJournalDescriptor.nocatEventCounters, - NV_SIZEOF32(pRcdb->nocatJournalDescriptor.nocatEventCounters)); + sizeof(pRcdb->nocatJournalDescriptor.nocatEventCounters)); } return status; } diff --git a/src/nvidia/kernel/vgpu/nv/rpc.c b/src/nvidia/kernel/vgpu/nv/rpc.c index a977039078..73d626224a 100644 --- a/src/nvidia/kernel/vgpu/nv/rpc.c +++ b/src/nvidia/kernel/vgpu/nv/rpc.c @@ -28,6 +28,9 @@ // //****************************************************************************** +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/system.h" #include "core/locks.h" @@ -52,6 +55,8 @@ #include "vgpu/vgpu_events.h" #include "virtualization/hypervisor/hypervisor.h" #include "os/os.h" +#include "objtmr.h" +#include "lib/base_utils.h" #define SDK_ALL_CLASSES_INCLUDE_FULL_HEADER #include "g_allclasses.h" @@ -101,6 +106,7 @@ typedef struct rpc_vgx_version } RPC_VGX_VERSION; static RPC_VGX_VERSION rpcVgxVersion; +static NvBool bSkipRpcVersionHandshake = NV_FALSE; void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion) { @@ -177,9 +183,9 @@ static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc) status = rpcSendMessage(pGpu, pRpc); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "rpcSendMessage failed with status 0x%08x for fn %d!\n", - status, vgpu_rpc_message_header_v->function); - NV_ASSERT(0); + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "rpcSendMessage failed with status 0x%08x for fn %d!\n", + status, vgpu_rpc_message_header_v->function); // // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC // buffers full and not being serviced) can make things worse, i.e. turn RPC @@ -194,15 +200,16 @@ static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc) { if (status == NV_ERR_TIMEOUT) { - NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll timedout for fn %d!\n", - vgpu_rpc_message_header_v->function); + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "rpcRecvPoll timedout for fn %d!\n", + vgpu_rpc_message_header_v->function); } else { - NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll failed with status 0x%08x for fn %d!\n", - status, vgpu_rpc_message_header_v->function); + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "rpcRecvPoll failed with status 0x%08x for fn %d!\n", + status, vgpu_rpc_message_header_v->function); } - NV_ASSERT(0); return status; } @@ -270,11 +277,8 @@ static NV_STATUS _issueRpcLarge // should not be called in broadcast mode NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); - // // Copy the initial buffer - // Temporary black magic WAR for bug 3594082: reducing the size by 2 - // - entryLength = NV_MIN(bufSize, pRpc->maxRpcSize - 2); + entryLength = NV_MIN(bufSize, pRpc->maxRpcSize); if ((NvU8 *)vgpu_rpc_message_header_v != pBuf8) portMemCopy(vgpu_rpc_message_header_v, entryLength, pBuf8, entryLength); @@ -299,11 +303,8 @@ static NV_STATUS _issueRpcLarge remainingSize -= entryLength; pBuf8 += entryLength; - // // Copy the remaining buffers - // Temporary black magic WAR for bug 3594082: reducing the size by 2 - // - entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v) - 2; + entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v); while (remainingSize != 0) { if (entryLength > remainingSize) @@ -362,7 +363,8 @@ static NV_STATUS _issueRpcLarge pBuf8 = (NvU8 *)pBuffer; remainingSize = bufSize; - entryLength = NV_MIN(bufSize, pRpc->maxRpcSize); + entryLength = NV_MIN(bufSize, vgpu_rpc_message_header_v->length); + NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE); if (((NvU8 *)vgpu_rpc_message_header_v != pBuf8) && bBidirectional) portMemCopy(pBuf8, entryLength, vgpu_rpc_message_header_v, entryLength); @@ -393,8 +395,11 @@ static NV_STATUS _issueRpcLarge NV_ASSERT(0); return nvStatus; } - entryLength = vgpu_rpc_message_header_v->length - sizeof(rpc_message_header_v); + + entryLength = vgpu_rpc_message_header_v->length; NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE); + NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength >= sizeof(rpc_message_header_v), NV_ERR_INVALID_STATE); + entryLength -= sizeof(rpc_message_header_v); if (entryLength > remainingSize) entryLength = remainingSize; @@ -672,10 +677,17 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) { if (rpcVgxVersion.majorNum != 0) { - NV_PRINTF(LEVEL_INFO, - "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", - gpuGetInstance(pGpu)); - goto skip_ver_handshake; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && !bSkipRpcVersionHandshake) + { + bSkipRpcVersionHandshake = NV_TRUE; + } + else + { + NV_PRINTF(LEVEL_INFO, + "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", + gpuGetInstance(pGpu)); + goto skip_ver_handshake; + } } else { @@ -1241,6 +1253,8 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 if (IS_GSP_CLIENT(pGpu)) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); GspSystemInfo *rpcInfo = (GspSystemInfo *)&rpc_message->gsp_set_system_info_v17_00.data; const NvU32 messageLength = sizeof(rpc_message_header_v) + sizeof(*rpcInfo); @@ -1272,6 +1286,9 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 NV_ASSERT_OK(kbifGetPciConfigSpacePriMirror_HAL(pGpu, pKernelBif, &rpcInfo->pciConfigMirrorBase, &rpcInfo->pciConfigMirrorSize)); + + // Cache MNOC interface support + rpcInfo->bMnocAvailable = pKernelBif->bMnocAvailable; } if (IS_SIMULATION(pGpu)) @@ -1305,6 +1322,12 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 rpcInfo->bUpstreamL1PorMobileOnly = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY); rpcInfo->upstreamAddressValid = pGpu->gpuClData.upstreamPort.addr.valid; + rpcInfo->hypervisorType = hypervisorGetHypervisorType(pHypervisor); + rpcInfo->bIsPassthru = pGpu->bIsPassthru; + + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + rpcInfo->sysTimerOffsetNs = pTmr->sysTimerOffsetNs; + status = _issueRpcAsync(pGpu, pRpc); } @@ -1519,7 +1542,6 @@ NV_STATUS rpcRmApiControl_GSP NvU32 rpc_params_size; NvU32 total_size; - NvU32 origParamsSize = paramsSize; NvU32 gpuMaskRelease = 0; NvU32 ctrlFlags = 0; NvU32 ctrlAccessRight = 0; @@ -1528,7 +1550,8 @@ NV_STATUS rpcRmApiControl_GSP CALL_CONTEXT *pCallContext; CALL_CONTEXT newContext; NvU32 resCtrlFlags = NVOS54_FLAGS_NONE; - NvBool preSerialized = NV_FALSE; + NvBool bPreSerialized = NV_FALSE; + void *pOriginalParams = pParamStructPtr; if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) { @@ -1560,11 +1583,11 @@ NV_STATUS rpcRmApiControl_GSP if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) { - preSerialized = NV_TRUE; + bPreSerialized = NV_TRUE; } else { - status = serverSerializeCtrlDown(pCallContext, cmd, pParamStructPtr, paramsSize, &resCtrlFlags); + status = serverSerializeCtrlDown(pCallContext, cmd, &pParamStructPtr, ¶msSize, &resCtrlFlags); if (status != NV_OK) goto done; } @@ -1573,7 +1596,6 @@ NV_STATUS rpcRmApiControl_GSP // otherwise this is a flat API and paramsSize is the param struct size if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) { - paramsSize = pCallContext->serializedSize; NV_ASSERT_OR_RETURN(!bCacheable, NV_ERR_INVALID_STATE); } @@ -1598,7 +1620,13 @@ NV_STATUS rpcRmApiControl_GSP rpc_params->hObject = hObject; rpc_params->cmd = cmd; rpc_params->paramsSize = paramsSize; - rpc_params->copyOutOnError = !!(ctrlFlags & RMCTRL_FLAGS_COPYOUT_ON_ERROR); + rpc_params->flags = RMAPI_RPC_FLAGS_NONE; + + if (ctrlFlags & RMCTRL_FLAGS_COPYOUT_ON_ERROR) + rpc_params->flags |= RMAPI_RPC_FLAGS_COPYOUT_ON_ERROR; + + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) + rpc_params->flags |= RMAPI_RPC_FLAGS_SERIALIZED; // If we have a big payload control, we need to make a local copy... if (message_buffer_remaining < paramsSize) @@ -1610,52 +1638,40 @@ NV_STATUS rpcRmApiControl_GSP message_buffer_remaining = total_size - fixed_param_size; } - if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) - { - // Copy in serialized buffer from the call context - rpc_params->serialized = NV_TRUE; - portMemCopy(rpc_params->params, message_buffer_remaining, pCallContext->pSerializedParams, pCallContext->serializedSize); - } - else + if (paramsSize != 0) { - rpc_params->serialized = NV_FALSE; - - if (paramsSize != 0) + if (pParamStructPtr == NULL) { - if (pParamStructPtr == NULL) - { - status = NV_ERR_INVALID_ARGUMENT; - goto done; - } - else - { - // Serialize RM control - for now a simple memcpy, could be more when FINN comes - if (portMemCopy(rpc_params->params, message_buffer_remaining, pParamStructPtr, paramsSize) == NULL) - { - status = NV_ERR_BUFFER_TOO_SMALL; - goto done; - } - } - } - else if (pParamStructPtr != NULL) - { - NV_PRINTF(LEVEL_ERROR, "Bad params: ptr " NvP64_fmt " size: 0x%x\n", - pParamStructPtr, paramsSize); status = NV_ERR_INVALID_ARGUMENT; goto done; } else { - // - // paramsSize = 0 and pParamStructPtr == NULL - // rpc_params->params is static, cannot be set to NULL. - // We will allow rpc_params->paramsSize = 0 and - // rpc_params->params != NULL from here, but in - // _rpcGspRmControl() have the logic that - // pc_params->paramsSize = 0 means no params. - // + if (portMemCopy(rpc_params->params, message_buffer_remaining, pParamStructPtr, paramsSize) == NULL) + { + status = NV_ERR_BUFFER_TOO_SMALL; + goto done; + } } } + else if (pParamStructPtr != NULL) + { + NV_PRINTF(LEVEL_ERROR, "Bad params: ptr " NvP64_fmt " size: 0x%x\n", + pParamStructPtr, paramsSize); + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + else + { + // + // paramsSize = 0 and pParamStructPtr == NULL + // rpc_params->params is static, cannot be set to NULL. + // We will allow rpc_params->paramsSize = 0 and + // rpc_params->params != NULL from here, but in + // _rpcGspRmControl() have the logic that + // pc_params->paramsSize = 0 means no params. + // + } // Issue RPC if (large_message_copy) @@ -1675,7 +1691,7 @@ NV_STATUS rpcRmApiControl_GSP if (status == NV_OK) { // Skip copyout if we got an error from the GSP control handler - if (rpc_params->status != NV_OK && !rpc_params->copyOutOnError) + if (rpc_params->status != NV_OK && !(rpc_params->flags & RMAPI_RPC_FLAGS_COPYOUT_ON_ERROR)) { status = rpc_params->status; goto done; @@ -1687,13 +1703,13 @@ NV_STATUS rpcRmApiControl_GSP // If it was preserialized, copy it to call context for deserialization by caller // Otherwise deserialize it because it was serialized here // - if (preSerialized) + if (bPreSerialized) { portMemCopy(pCallContext->pSerializedParams, pCallContext->serializedSize, rpc_params->params, rpc_params->paramsSize); } else { - status = serverDeserializeCtrlUp(pCallContext, cmd, pParamStructPtr, origParamsSize, &resCtrlFlags); + status = serverDeserializeCtrlUp(pCallContext, cmd, &pParamStructPtr, ¶msSize, &resCtrlFlags); if (status != NV_OK) goto done; } @@ -1714,16 +1730,15 @@ NV_STATUS rpcRmApiControl_GSP if (status != NV_OK) { - NvBool bSilentErrorReport = NV_FALSE; + NvBool bQuiet = NV_FALSE; switch (status) { case NV_ERR_NOT_SUPPORTED: case NV_ERR_OBJECT_NOT_FOUND: - bSilentErrorReport = NV_TRUE; + bQuiet = NV_TRUE; break; } - - NV_PRINTF_COND(bSilentErrorReport, LEVEL_INFO, LEVEL_WARNING, + NV_PRINTF_COND((pRpc->bQuietPrints || bQuiet), LEVEL_INFO, LEVEL_WARNING, "GspRmControl failed: hClient=0x%08x; hObject=0x%08x; cmd=0x%08x; paramsSize=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", hClient, hObject, cmd, paramsSize, rpc_params->status, status); } @@ -1740,9 +1755,9 @@ NV_STATUS rpcRmApiControl_GSP // Free data structures if we serialized/deserialized here // Also check for serialized flag here as we may be called directly from within another control call // - if ((resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) && !preSerialized) + if ((resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) && !bPreSerialized) { - serverFreeSerializeStructures(pCallContext, pParamStructPtr); + serverFreeSerializeStructures(pCallContext, pOriginalParams); } return status; @@ -1755,7 +1770,8 @@ NV_STATUS rpcRmApiAlloc_GSP NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 allocParamsSize ) { NV_STATUS status = NV_ERR_NOT_SUPPORTED; @@ -1764,7 +1780,10 @@ NV_STATUS rpcRmApiAlloc_GSP OBJRPC *pRpc = GPU_GET_RPC(pGpu); rpc_gsp_rm_alloc_v03_00 *rpc_params = &rpc_message->gsp_rm_alloc_v03_00; + CALL_CONTEXT callContext = {0}; + NvU32 flags = RMAPI_ALLOC_FLAGS_NONE; NvU32 paramsSize; + void *pOriginalParams = pAllocParams; NvBool bNullAllowed; const NvU32 fixed_param_size = sizeof(rpc_message_header_v) + sizeof(*rpc_params); @@ -1809,33 +1828,49 @@ NV_STATUS rpcRmApiAlloc_GSP rpc_params->hParent = hParent; rpc_params->hObject = hObject; rpc_params->hClass = hClass; - rpc_params->paramsSize = pAllocParams ? paramsSize : 0; + rpc_params->flags = RMAPI_RPC_FLAGS_NONE; - // Serialize RM alloc - for now a simple memcpy, could be more when FINN comes + // Serialize RM alloc if (paramsSize > 0) { - if (portMemCopy(rpc_params->params, message_buffer_remaining, pAllocParams, paramsSize) == NULL) + void *memCopyResult; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_INFO, serverSerializeAllocDown(&callContext, hClass, &pAllocParams, ¶msSize, &flags), done); + if (flags & RMAPI_ALLOC_FLAGS_SERIALIZED) + { + rpc_params->flags |= RMAPI_RPC_FLAGS_SERIALIZED; + } + + memCopyResult = portMemCopy(rpc_params->params, message_buffer_remaining, pAllocParams, paramsSize); + rpc_params->paramsSize = paramsSize; + + if (memCopyResult == NULL) { status = NV_ERR_BUFFER_TOO_SMALL; goto done; } } + else + { + rpc_params->paramsSize = 0; + } status = _issueRpcAndWait(pGpu, pRpc); if (status == NV_OK) { - // Deserialize - if (paramsSize > 0) + // Deserialize. pAllocParams will be populated correctly if deserialized + NV_CHECK_OK_OR_GOTO(status, LEVEL_INFO, serverDeserializeAllocUp(&callContext, hClass, &pAllocParams, ¶msSize, &flags), done); + if (!(flags & RMAPI_ALLOC_FLAGS_SERIALIZED) && (paramsSize > 0)) { portMemCopy(pAllocParams, paramsSize, rpc_params->params, paramsSize); } } else { - NV_PRINTF(LEVEL_ERROR, - "GspRmAlloc failed: hClient=0x%08x; hParent=0x%08x; hObject=0x%08x; hClass=0x%08x; paramsSize=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", - hClient, hParent, hObject, hClass, paramsSize, rpc_params->status, status); + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "GspRmAlloc failed: hClient=0x%08x; hParent=0x%08x; hObject=0x%08x; hClass=0x%08x; paramsSize=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", + hClient, hParent, hObject, hClass, paramsSize, rpc_params->status, status); status = rpc_params->status; } @@ -1844,6 +1879,8 @@ NV_STATUS rpcRmApiAlloc_GSP { rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); } + serverFreeSerializeStructures(&callContext, pOriginalParams); + return status; } @@ -1887,9 +1924,9 @@ NV_STATUS rpcRmApiDupObject_GSP status = _issueRpcAndWait(pGpu, pRpc); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "GspRmDupObject failed: hClient=0x%08x; hParent=0x%08x; hObject=0x%08x; hClientSrc=0x%08x; hObjectSrc=0x%08x; flags=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", - hClient, hParent, *phObject, hClientSrc, hObjectSrc, flags, rpc_params->status, status); + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "GspRmDupObject failed: hClient=0x%08x; hParent=0x%08x; hObject=0x%08x; hClientSrc=0x%08x; hObjectSrc=0x%08x; flags=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", + hClient, hParent, *phObject, hClientSrc, hObjectSrc, flags, rpc_params->status, status); } done: if (gpuMaskRelease != 0) @@ -1932,9 +1969,9 @@ NV_STATUS rpcRmApiFree_GSP status = _issueRpcAndWait(pGpu, pRpc); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "GspRmFree failed: hClient=0x%08x; hObject=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", - hClient, hObject, rpc_params->status, status); + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "GspRmFree failed: hClient=0x%08x; hObject=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", + hClient, hObject, rpc_params->status, status); } done: if (gpuMaskRelease != 0) diff --git a/src/nvidia/src/kernel/compute/fabric.c b/src/nvidia/src/kernel/compute/fabric.c index be7aae7ab3..e1e11dfa7f 100644 --- a/src/nvidia/src/kernel/compute/fabric.c +++ b/src/nvidia/src/kernel/compute/fabric.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -97,7 +97,8 @@ _fabricCacheDelete FabricCacheEntry *pEntry; pEntry = multimapFindItem(pCache, key1, key2); - NV_ASSERT_OR_RETURN_VOID(pEntry != NULL); + if (pEntry == NULL) + return; mapRemoveByKey(&pEntry->map, key3); if (mapCount(&pEntry->map) > 0) diff --git a/src/nvidia/src/kernel/core/hal_mgr.c b/src/nvidia/src/kernel/core/hal_mgr.c index 65b7272ef3..7be422a9f0 100644 --- a/src/nvidia/src/kernel/core/hal_mgr.c +++ b/src/nvidia/src/kernel/core/hal_mgr.c @@ -214,7 +214,7 @@ _halmgrGetStringRepForHalImpl } halImplNames[] = { HAL_IMPL_NAME_LIST }; // generated by rmconfig into g_hal.h NvU32 i; - for (i = 0; i < NV_ARRAY_ELEMENTS32(halImplNames); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(halImplNames); i++) { if (halImplNames[i].halImpl == halImpl) { diff --git a/src/nvidia/src/kernel/core/locks.c b/src/nvidia/src/kernel/core/locks.c index 6261274454..0a013ea474 100644 --- a/src/nvidia/src/kernel/core/locks.c +++ b/src/nvidia/src/kernel/core/locks.c @@ -39,6 +39,7 @@ #include #include "kernel/gpu/intr/intr.h" #include +#include "gpu/disp/kern_disp.h" // // GPU lock @@ -563,12 +564,11 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG // If we own a higher order lock than one of the needed ones, we are // violating the locking order and need to do a conditional acquire // clz32(0) == ctz(0) == 32: - // owned=0b00110000, needed=0b00001100: (4 < (32-28)), bCond=FALSE - // owned=0b00110010, needed=0b00001100: (1 < (32-28)), bCond=TRUE - // owned=0b00010000, needed=0b11000011: (4 < (32-24)), bCond=TRUE - // owned=0b00000000, needed=0b00001100: (32 < (32-28)), bCond=FALSE - // owned=0b00000001, needed=0b00000000: (0 < (32-32)), bCond=FALSE - if (portUtilCountTrailingZeros32(ownedMask) < (32-portUtilCountLeadingZeros32(gpuMask))) + // owned=0b00001100, needed=0b00110000: ((32-28) > 4), bCond=FALSE + // owned=0b00001100, needed=0b00110010: ((32-28) > 1), bCond=TRUE + // owned=0b11000011, needed=0b00010000: ((32-24) > 4), bCond=TRUE + // owned=0b00000000, needed=0b00000001: ((32-32) > 0), bCond=FALSE + if ((32-portUtilCountLeadingZeros32(ownedMask)) > portUtilCountTrailingZeros32(gpuMask)) { bCondAcquireCheck = NV_TRUE; } @@ -1487,6 +1487,9 @@ rmGpuGroupLockRelease(GPU_MASK gpuMask, NvU32 flags) OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPU *pDpcGpu = NULL; + if (gpuMask == 0) + return NV_SEMA_RELEASE_SUCCEED; + // // QuadroSync (previously known as GSync) is a cross GPU feature that // synchronizes display across multiple GPUs. See changelist 16809243. If diff --git a/src/nvidia/src/kernel/core/system.c b/src/nvidia/src/kernel/core/system.c index 8f34ee4bdb..5c6e10dde6 100644 --- a/src/nvidia/src/kernel/core/system.c +++ b/src/nvidia/src/kernel/core/system.c @@ -47,6 +47,7 @@ #include "platform/cpu.h" #include "platform/platform.h" #include "diagnostics/gpu_acct.h" +#include "platform/platform_request_handler.h" #include "gpu/external_device/gsync.h" #include "virtualization/kernel_vgpu_mgr.h" #include "mem_mgr/virt_mem_mgr.h" @@ -83,6 +84,7 @@ static sysChildObject sysChildObjects[] = { NV_OFFSETOF(OBJSYS, pGpuMgr), classInfo(OBJGPUMGR), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pGsyncMgr), classInfo(OBJGSYNCMGR), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pGpuAcct), classInfo(GpuAccounting), NV_TRUE }, + { NV_OFFSETOF(OBJSYS, pPlatformRequestHandler), classInfo(PlatformRequestHandler), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pRcDB), classInfo(OBJRCDB), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pVmm), classInfo(OBJVMM), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pKernelVgpuMgr), classInfo(KernelVgpuMgr), NV_TRUE }, @@ -200,7 +202,7 @@ _sysCreateChildObjects(OBJSYS *pSys) NV_STATUS status = NV_OK; NvU32 i, n; - n = NV_ARRAY_ELEMENTS32(sysChildObjects); + n = NV_ARRAY_ELEMENTS(sysChildObjects); for (i = 0; i < n; i++) { @@ -252,7 +254,7 @@ _sysDeleteChildObjects(OBJSYS *pSys) osRmCapUnregister(&pSys->pOsRmCaps); - for (i = NV_ARRAY_ELEMENTS32(sysChildObjects) - 1; i >= 0; i--) + for (i = NV_ARRAY_ELEMENTS(sysChildObjects) - 1; i >= 0; i--) { NvLength offset = sysChildObjects[i].childOffset; Dynamic **ppChild = reinterpretCast(reinterpretCast(pSys, NvU8*) + offset, Dynamic**); diff --git a/src/nvidia/src/kernel/core/thread_state.c b/src/nvidia/src/kernel/core/thread_state.c index 6da8d1b328..fb7b37829f 100644 --- a/src/nvidia/src/kernel/core/thread_state.c +++ b/src/nvidia/src/kernel/core/thread_state.c @@ -252,7 +252,7 @@ static void _threadStateSetNextCpuYieldTime(THREAD_STATE_NODE *pThreadNode) (TIMEOUT_DEFAULT_OS_RESCHEDULE_INTERVAL_SECS) * 1000000 * 1000; } -void threadStateYieldCpuIfNecessary(OBJGPU *pGpu) +void threadStateYieldCpuIfNecessary(OBJGPU *pGpu, NvBool bQuiet) { NV_STATUS rmStatus; THREAD_STATE_NODE *pThreadNode = NULL; @@ -266,7 +266,7 @@ void threadStateYieldCpuIfNecessary(OBJGPU *pGpu) { if (NV_OK == osSchedule()) { - NV_PRINTF(LEVEL_WARNING, "Yielding\n"); + NV_PRINTF_COND(bQuiet, LEVEL_INFO, LEVEL_WARNING, "Yielding\n"); } _threadStateSetNextCpuYieldTime(pThreadNode); @@ -1135,7 +1135,7 @@ void threadStateLogTimeout(OBJGPU *pGpu, NvU64 funcAddr, NvU32 lineNum) // Log the Timeout in the RM Journal RmRC2GpuTimeout3_RECORD* pRec = NULL; - rcdbAddAssertJournalRecWithLine(pGpu, lineNum, (void**)&pRec, + rcdbAddAssertJournalRecWithLine(pGpu, lineNum, (void**)&pRec, RmGroup, RmRC2GpuTimeout_V3, sizeof(RmRC2GpuTimeout3_RECORD), DRF_DEF(_RM, _ASSERT, _TYPE, _INFO), diff --git a/src/nvidia/src/kernel/diagnostics/journal.c b/src/nvidia/src/kernel/diagnostics/journal.c index 47d596115e..3dfa2192e8 100644 --- a/src/nvidia/src/kernel/diagnostics/journal.c +++ b/src/nvidia/src/kernel/diagnostics/journal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,6 +45,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "nvdevid.h" #include "nvop.h" +#include "jt.h" @@ -254,8 +255,8 @@ rcdbConstruct_IMPL(Journal *pRcDB) pRcDB->rcErrorCounterArray[RC_ERROR_COUNTER_OTHER_INDEX].rcErrorType = RC_ERROR_COUNTER_OTHER_TYPE; // clear the Nocat Queue descriptors & counters - portMemSet(&pRcDB->nocatJournalDescriptor, 0x00, NV_SIZEOF32(pRcDB->nocatJournalDescriptor)); - portMemSet(pRcDB->nocatJournalDescriptor.lastRecordId, 0xff, NV_SIZEOF32(pRcDB->nocatJournalDescriptor.lastRecordId)); + portMemSet(&pRcDB->nocatJournalDescriptor, 0x00, sizeof(pRcDB->nocatJournalDescriptor)); + portMemSet(pRcDB->nocatJournalDescriptor.lastRecordId, 0xff, sizeof(pRcDB->nocatJournalDescriptor.lastRecordId)); pRcDB->nocatJournalDescriptor.nocatLastRecordType = NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN; pRcDB->nocatJournalDescriptor.cacheFreshnessPeriodticks = NOCAT_CACHE_FRESHNESS_PERIOD_MS; pRcDB->nocatJournalDescriptor.cacheFreshnessPeriodticks *= osGetTimestampFreq(); @@ -529,7 +530,40 @@ NV_STATUS rcdbAddAssertJournalRec(void *pVoidGpu, void** ppRec, NvU8 jGroup, NvU // Populate stateMask with flags that represent the power state and other useful things. static NvU64 _getCommonJournalStateMask(OBJGPU *pGpu) { - return 0; + NvU64 stateMask = REF_NUM(NV_RM_JOURNAL_STATE_MASK_GC6_STATE, + pGpu->gc6State.currentState); + + if (!gpuIsGpuFullPower(pGpu)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_NOT_FULL_POWER; + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_NOT_CONNECTED; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_STANDBY)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_STANDBY; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_HIBERNATE)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_HIBERNATE; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_PM_CODEPATH; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_GC6_RESET)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_GC6_RESET; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_FULLCHIP_RESET)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_FULLCHIP_RESET; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_SECONDARY_BUS_RESET)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_SEC_BUS_RESET; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TIMEOUT_RECOVERY)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_IN_TIMEOUT_RECOVERY; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST)) + stateMask |= NV_RM_JOURNAL_STATE_MASK_IS_LOST; + + return stateMask; } // Fill in the common portion of the journal structure. @@ -1655,7 +1689,7 @@ rcdbDumpCommonAssertRecord if (pRec->count != 1) prbEncAddUInt32(pPrbEnc, JOURNAL_ASSERT_COUNT, pRec->count); - for (i = 0; i < NV_ARRAY_ELEMENTS32(pRec->callStack); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pRec->callStack); i++) { if (pRec->callStack[i] == 0) break; @@ -2301,7 +2335,7 @@ static void _rcdbDbgBreakEx(void *pGpu, NvU32 lineNum, NvU32 level, NvU64 ip) // Add assert to NvLog. But skip when nvLog asserts to avoid stack overflow. if (portAtomicIncrementS32(&nvLogRecursion) == 1) { - NV_PRINTF(LEVEL_ERROR, "Breakpoint at 0x%llx.\n", ip); + NV_PRINTF(LEVEL_NOTICE, "Breakpoint at 0x%llx.\n", ip); } portAtomicDecrementS32(&nvLogRecursion); @@ -3075,6 +3109,8 @@ _rcdbNocatCollectContext(OBJGPU *pGpu, Journal* pRcdb, NV2080_NOCAT_JOURNAL_GPU_ pContextCache->subsystemId = (NvU16)(DRF_VAL(_PCI, _SUBID, _DEVICE, pGpu->idInfo.PCISubDeviceID)); pContextCache->revision = pGpu->idInfo.PCIRevisionID; pContextCache->type = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE); + pContextCache->bMsHybrid = FLD_TEST_DRF(_JT_FUNC, _CAPS, _MSHYB_ENABLED, _TRUE, + pGpu->acpiMethodData.jtMethodData.jtCaps); portStringCopy((char *)pContextCache->vbiosProject, NV2080_NOCAT_JOURNAL_MAX_STR_LEN, NOCAT_UNKNOWN_STR, portStringLength(NOCAT_UNKNOWN_STR) + 1); @@ -3215,10 +3251,10 @@ RM_NOCAT_JOURNAL_ENTRY* _rcdbAllocNocatJournalRecord if (pCommon != NULL) { // advance the pointer past the common header. - pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + NV_SIZEOF32(RmRCCommonJournal_RECORD)); + pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + sizeof(RmRCCommonJournal_RECORD)); // clear the record & assign an id. - portMemSet(pNocatEntry, 0, NV_SIZEOF32(*pNocatEntry)); + portMemSet(pNocatEntry, 0, sizeof(*pNocatEntry)); pNocatEntry->id = pDesc->nextRecordId++; pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX]++; } @@ -3344,7 +3380,7 @@ _rcdbGetNocatJournalRecord pCommon = (RmRCCommonJournal_RECORD*)(((NvU8*)pRingBuffer->pBuffer) + (_rcdbGetOcaRecordSizeWithHeader(pRcdb, RmNocatReport) * idx)); // get a pointer to the data that follows the common header, that is the record data. - pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + NV_SIZEOF32(RmRCCommonJournal_RECORD)); + pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + sizeof(RmRCCommonJournal_RECORD)); // pass the record along if (ppReturnedCommon != NULL) @@ -3455,7 +3491,7 @@ rcdbReportNextNocatJournalEntry pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX]++; return NV_ERR_INVALID_ARGUMENT; } - portMemSet(pReturnedNocatEntry, 0, NV_SIZEOF32(*pReturnedNocatEntry)); + portMemSet(pReturnedNocatEntry, 0, sizeof(*pReturnedNocatEntry)); if (portAtomicIncrementS32(&concurrentRingBufferAccess) == 1) { @@ -3835,7 +3871,7 @@ rcdbNocatInsertNocatError( diagBufferLen = NV_ARRAY_ELEMENTS(pNocatEntry->nocatJournalEntry.diagBuffer); } portMemCopy(pNocatEntry->nocatJournalEntry.diagBuffer, - NV_SIZEOF32(pNocatEntry->nocatJournalEntry.diagBuffer), + sizeof(pNocatEntry->nocatJournalEntry.diagBuffer), pNewEntry->pDiagBuffer, diagBufferLen); } pNocatEntry->nocatJournalEntry.diagBufferLen = diagBufferLen; @@ -3849,7 +3885,7 @@ rcdbNocatInsertNocatError( _rcdbSetTdrReason(pRcdb, pNewEntry->tdrReason, (char*)pNocatEntry->nocatJournalEntry.tdrReason, - NV_SIZEOF32(pNocatEntry->nocatJournalEntry.tdrReason)); + sizeof(pNocatEntry->nocatJournalEntry.tdrReason)); } else { @@ -4093,7 +4129,7 @@ _rcdbNocatReportAssert // put the line number in the upper 32 bits. newEntry.errorCode |= ((NvU64)pAssertRec->lineNum) << 32; - for (idx = 0; idx < NV_ARRAY_ELEMENTS32(pAssertRec->callStack); idx++) + for (idx = 0; idx < NV_ARRAY_ELEMENTS(pAssertRec->callStack); idx++) { diagBuffer.callStack[idx] = (NvU32)((pAssertRec->callStack[idx] - pRcdb->nocatJournalDescriptor.loadAddress) @@ -4105,14 +4141,14 @@ _rcdbNocatReportAssert // setup the pointer to our diag buffer & its length newEntry.pDiagBuffer = (NvU8 *)&diagBuffer; - newEntry.diagBufferLen = NV_SIZEOF32(diagBuffer); + newEntry.diagBufferLen = sizeof(diagBuffer); // is the last thing we logged an assert, & is this the same assert? if ((pRcdb->nocatJournalDescriptor.lastRecordId[NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT] == pRcdb->nocatJournalDescriptor.lastRecordId[NV2080_NOCAT_JOURNAL_REC_TYPE_ANY]) && (0 == portMemCmp(&pRcdb->nocatJournalDescriptor.lastAssertData, diagBuffer.callStack, // same stack - NV_SIZEOF32(diagBuffer.callStack)))) + sizeof(diagBuffer.callStack)))) { // it is the same as the last assert we logged. so don't log it again. // but see if we can increment the counter in an unreported assert. @@ -4145,8 +4181,8 @@ _rcdbNocatReportAssert // we are logging this assert, save off the stack so we can use it to // compare against future asserts. portMemCopy(&pRcdb->nocatJournalDescriptor.lastAssertData, - NV_SIZEOF32(pRcdb->nocatJournalDescriptor.lastAssertData), - &diagBuffer, NV_SIZEOF32(diagBuffer)); + sizeof(pRcdb->nocatJournalDescriptor.lastAssertData), + &diagBuffer, sizeof(diagBuffer)); rcdbNocatInsertNocatError(pGpu, &newEntry); } @@ -4220,7 +4256,7 @@ NV_STATUS rcdbSetNocatTdrReason // there is, set the reason. _rcdbSetTdrReason(pRcdb, pReasonData->reasonCode, (char *)pNocatEntry->nocatJournalEntry.tdrReason, - NV_SIZEOF32(pNocatEntry->nocatJournalEntry.tdrReason)); + sizeof(pNocatEntry->nocatJournalEntry.tdrReason)); pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX]++; } } diff --git a/src/nvidia/src/kernel/disp/disp_sw.c b/src/nvidia/src/kernel/disp/disp_sw.c index f9ec5e7eb3..1787e6b00f 100644 --- a/src/nvidia/src/kernel/disp/disp_sw.c +++ b/src/nvidia/src/kernel/disp/disp_sw.c @@ -128,13 +128,13 @@ dispswDestruct_IMPL NV_STATUS dispswReleaseSemaphoreAndNotifierFill ( - OBJGPU *pGpu, + OBJGPU *pGpu, NvU64 gpuVA, NvU32 vaSpace, NvU32 releasevalue, NvU32 flags, NvU32 completionStatus, - NvHandle hClient, + RsClient *pClient, NvHandle hEvent ) { @@ -144,7 +144,7 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill if (flags & F_SEMAPHORE_ADDR_VALID) { - bFound = CliGetDmaMappingInfo(hClient, + bFound = CliGetDmaMappingInfo(pClient, hEvent, vaSpace, gpuVA, @@ -153,10 +153,10 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill if (!bFound) return NV_ERR_INVALID_ADDRESS; } - else if (flags & F_SEMAPHORE_RELEASE) + else if (flags & F_SEMAPHORE_RELEASE) { status = semaphoreFillGPUVA(pGpu, - hClient, + pClient, vaSpace, gpuVA, releasevalue, @@ -164,10 +164,10 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill NV_TRUE); return status; } - else if (flags & F_NOTIFIER_FILL) + else if (flags & F_NOTIFIER_FILL) { status = notifyFillNotifierGPUVA(pGpu, - hClient, + pClient, vaSpace, gpuVA, releasevalue, /* Info32 */ diff --git a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c index f95a5c45da..8c288c1328 100644 --- a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c +++ b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,6 +29,7 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "gpu/eng_desc.h" // @@ -46,90 +47,39 @@ static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = { - { classId(OBJFUSE), 1, }, - { classId(OBJSEQ), 1, }, - { classId(GpuMutexMgr), 1, }, - { classId(OBJTMR), 1, }, - { classId(GraphicsManager), 1, }, - { classId(MIGManager), 1, }, - { classId(KernelMIGManager), 1, }, - { classId(KernelGraphicsManager), 1, }, - { classId(OBJVBIOS), 1, }, - { classId(OBJDCB), 1, }, - { classId(OBJGPIO), 1, }, - { classId(I2c), 1, }, - { classId(Spi), 1, }, - { classId(KernelRc), 1, }, - { classId(OBJRC), 1, }, - { classId(OBJSTEREO), 1, }, - { classId(Intr), 1, }, - { classId(OBJINFOROM), 1, }, - { classId(NvDebugDump), 1, }, - { classId(SMDebugger), 1, }, - { classId(OBJGPULOG), 1, }, - { classId(OBJGPUMON), 1, }, - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(Nne), 1}, - {classId(OBJBSP), 4}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 5}, - {classId(KernelCE), 5}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1}, - {classId(Hshub), 2 }, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1 }, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJNVJPG), 4}, - {classId(OBJMSENC), 3}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJVMMU), 1}, - {classId(OBJOFA), 1 }, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 5), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), + GPU_CHILD_PRESENT(ConfidentialCompute, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_AD102(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_AD102); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_AD102); return gpuChildrenPresent_AD102; } diff --git a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c index 6726a7ded8..3e7c75d7d7 100644 --- a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +++ b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,11 +22,13 @@ */ #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "kernel/gpu/intr/intr.h" #include "gpu/mem_mgr/mem_mgr.h" #include "published/ampere/ga100/dev_fb.h" #include "published/ampere/ga100/dev_vm.h" #include "published/ampere/ga100/dev_fuse.h" +#include "virtualization/hypervisor/hypervisor.h" /*! * @brief Read fuse for display supported status. @@ -115,6 +117,25 @@ gpuGetFlaVasSize_GA100 } } +/*! + * @brief Is ctx buffer allocation in PMA supported + */ +NvBool +gpuIsCtxBufAllocInPmaSupported_GA100 +( + OBJGPU *pGpu +) +{ + // + // This is supported by default on baremetal RM. + // This has no impact in guest-RM since ctxBufPools are disabled on guest. + // We leave this disabled on host-RM. TODO: Bug 4066846 + // + if (!hypervisorIsVgxHyper()) + return NV_TRUE; + return NV_FALSE; +} + // // List of GPU children that present for the chip. List entries contain$ // {CLASS-ID, # of instances} pairs, e.g.: {CE, 2} is 2 instance of OBJCE. This$ @@ -130,88 +151,39 @@ gpuGetFlaVasSize_GA100 static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { - { classId(OBJFUSE), 1, }, - { classId(OBJSEQ), 1, }, - { classId(GpuMutexMgr), 1, }, - { classId(OBJTMR), 1, }, - { classId(GraphicsManager), 1, }, - { classId(MIGManager), 1, }, - { classId(KernelMIGManager), 1, }, - { classId(KernelGraphicsManager), 1, }, - { classId(OBJVBIOS), 1, }, - { classId(OBJDCB), 1, }, - { classId(OBJGPIO), 1, }, - { classId(I2c), 1, }, - { classId(Spi), 1, }, - { classId(KernelRc), 1, }, - { classId(OBJRC), 1, }, - { classId(OBJSTEREO), 1, }, - { classId(Intr), 1, }, - { classId(OBJINFOROM), 1, }, - { classId(NvDebugDump), 1, }, - { classId(SMDebugger), 1, }, - { classId(OBJGPULOG), 1, }, - { classId(OBJGPUMON), 1, }, - { classId(OBJSWENG), 1 }, - { classId(OBJUVM), 1 }, - { classId(OBJACR), 1 }, - { classId(OBJBIF), 1 }, - { classId(KernelBif), 1 }, - { classId(OBJBSP), 5 }, - { classId(OBJBUS), 1 }, - { classId(KernelBus), 1 }, - { classId(OBJCE), 10 }, - { classId(KernelCE), 10 }, - { classId(OBJCIPHER), 1 }, - { classId(ClockManager), 1 }, - { classId(OBJDISP), 1 }, - { classId(KernelDisplay), 1 }, - { classId(VirtMemAllocator), 1 }, - { classId(OBJDPAUX), 1 }, - { classId(Fan), 1 }, - { classId(OBJHSHUBMANAGER), 1 }, - { classId(Hshub), 2 }, - { classId(MemorySystem), 1 }, - { classId(KernelMemorySystem), 1 }, - { classId(MemoryManager), 1 }, - { classId(OBJFBFLCN), 1 }, - { classId(KernelFifo), 1 }, - { classId(OBJFIFO), 1 }, - { classId(OBJGMMU), 1 }, - { classId(KernelGmmu), 1}, - { classId(Graphics), 8 }, - { classId(KernelGraphics), 8 }, - { classId(OBJHDACODEC), 1 }, - { classId(OBJHWPM), 1 }, - { classId(Lpwr ), 1 }, - { classId(OBJLSFM), 1 }, - { classId(OBJMC), 1 }, - { classId(KernelMc), 1 }, - { classId(PrivRing), 1 }, - { classId(SwIntr), 1 }, - { classId(OBJNVJPG), 1 }, - { classId(KernelNvlink), 1 }, - { classId(Nvlink), 1 }, - { classId(Perf), 1 }, - { classId(KernelPerf), 1 }, - { classId(Pmgr), 1 }, - { classId(Pmu), 1 }, - { classId(KernelPmu), 1 }, - { classId(OBJSEC2), 1 }, - { classId(Gsp), 1 }, - { classId(Therm), 1 }, - { classId(OBJVOLT), 1 }, - { classId(OBJGRIDDISPLAYLESS), 1 }, - { classId(OBJVMMU), 1 }, - { classId(OBJOFA), 1 }, - { classId(KernelSec2), 1 }, - { classId(KernelGsp), 1 }, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 10), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 8), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), + GPU_CHILD_PRESENT(ConfidentialCompute, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_GA100(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GA100); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_GA100); return gpuChildrenPresent_GA100; } @@ -229,89 +201,39 @@ gpuGetChildrenPresent_GA100(OBJGPU *pGpu, NvU32 *pNumEntries) // static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = { - { classId(OBJFUSE), 1, }, - { classId(OBJSEQ), 1, }, - { classId(GpuMutexMgr), 1, }, - { classId(OBJTMR), 1, }, - { classId(GraphicsManager), 1, }, - { classId(MIGManager), 1, }, - { classId(KernelMIGManager), 1, }, - { classId(KernelGraphicsManager), 1, }, - { classId(OBJVBIOS), 1, }, - { classId(OBJDCB), 1, }, - { classId(OBJGPIO), 1, }, - { classId(I2c), 1, }, - { classId(Spi), 1, }, - { classId(KernelRc), 1, }, - { classId(OBJRC), 1, }, - { classId(OBJSTEREO), 1, }, - { classId(Intr), 1, }, - { classId(OBJINFOROM), 1, }, - { classId(NvDebugDump), 1, }, - { classId(SMDebugger), 1, }, - { classId(OBJGPULOG), 1, }, - { classId(OBJGPUMON), 1, }, - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(Nne), 1}, - {classId(OBJBSP), 2}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 5}, - {classId(KernelCE), 5}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1 }, - {classId(Hshub), 2 }, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1 }, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1 }, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJVMMU), 1}, - {classId(OBJOFA), 1 }, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 5), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), + GPU_CHILD_PRESENT(ConfidentialCompute, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_GA102(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GA102); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_GA102); return gpuChildrenPresent_GA102; } diff --git a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c index d0accba9d8..681c0dc340 100644 --- a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c +++ b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,11 +22,13 @@ */ #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "os/os.h" #include "nverror.h" #include "published/hopper/gh100/hwproject.h" #include "published/hopper/gh100/dev_gc6_island.h" +#include "published/hopper/gh100/dev_gc6_island_addendum.h" #include "published/hopper/gh100/dev_pmc.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" @@ -148,6 +150,15 @@ NvU32 gpuGetPhysAddrWidth_GH100 */ NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(OBJGPU *pGpu) { + // + // ATS is supported only on self-hosted Hopper. + // Also enable it for simulation platforms for fmodel/RTL verification + // with CPU model. + // + if (gpuIsSelfHosted(pGpu)) + { + return NV_TRUE; + } if (IS_SIMULATION(pGpu)) { @@ -359,91 +370,121 @@ gpuGetFlaVasSize_GH100 static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = { - { classId(OBJFUSE), 1, }, - { classId(OBJSEQ), 1, }, - { classId(GpuMutexMgr), 1, }, - { classId(OBJTMR), 1, }, - { classId(GraphicsManager), 1, }, - { classId(MIGManager), 1, }, - { classId(KernelMIGManager), 1, }, - { classId(KernelGraphicsManager), 1, }, - { classId(OBJVBIOS), 1, }, - { classId(OBJDCB), 1, }, - { classId(OBJGPIO), 1, }, - { classId(I2c), 1, }, - { classId(Spi), 1, }, - { classId(KernelRc), 1, }, - { classId(OBJRC), 1, }, - { classId(OBJSTEREO), 1, }, - { classId(Intr), 1, }, - { classId(OBJINFOROM), 1, }, - { classId(NvDebugDump), 1, }, - { classId(SMDebugger), 1, }, - { classId(OBJGPULOG), 1, }, - { classId(OBJGPUMON), 1, }, - { classId(OBJSWENG), 1 }, - { classId(OBJUVM), 1 }, - { classId(OBJACR), 1 }, - { classId(OBJBIF), 1 }, - { classId(KernelBif), 1 }, - { classId(OBJBSP), 8 }, - { classId(OBJBUS), 1 }, - { classId(KernelBus), 1 }, - { classId(OBJCE), 10 }, - { classId(KernelCE), 10 }, - { classId(OBJCIPHER), 1 }, - { classId(ClockManager), 1 }, - { classId(OBJDISP), 1 }, - { classId(KernelDisplay), 1 }, - { classId(VirtMemAllocator), 1 }, - { classId(OBJDPAUX), 1 }, - { classId(Fan), 1 }, - { classId(OBJHSHUBMANAGER), 1 }, - { classId(Hshub), 5 }, - { classId(MemorySystem), 1 }, - { classId(KernelMemorySystem), 1 }, - { classId(MemoryManager), 1 }, - { classId(OBJFBFLCN), 1 }, - {classId(KernelFifo), 1}, - { classId(OBJFIFO), 1 }, - { classId(OBJGMMU), 1 }, - { classId(KernelGmmu), 1}, - { classId(Graphics), 8 }, - { classId(KernelGraphics), 8 }, - { classId(OBJHDACODEC), 1 }, - { classId(OBJHWPM), 1 }, - { classId(Lpwr ), 1 }, - { classId(OBJLSFM), 1 }, - { classId(OBJMC), 1 }, - { classId(KernelMc), 1 }, - { classId(PrivRing), 1 }, - { classId(SwIntr), 1 }, - { classId(OBJNVJPG), 8 }, - { classId(KernelNvlink), 1 }, - { classId(Nvlink), 1 }, - { classId(Perf), 1 }, - { classId(KernelPerf), 1 }, - { classId(Pmgr), 1 }, - { classId(Pmu), 1 }, - { classId(KernelPmu), 1 }, - { classId(OBJSEC2), 1 }, - { classId(Gsp), 1 }, - { classId(OBJFSP), 1 }, - { classId(KernelFsp), 1 }, - { classId(Therm), 1 }, - { classId(OBJVOLT), 1 }, - { classId(OBJGRIDDISPLAYLESS), 1 }, - { classId(OBJVMMU), 1 }, - { classId(OBJOFA), 1 }, - { classId(KernelGsp), 1}, - { classId(KernelSec2), 1}, - { classId(KernelCcu), 1 }, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 10), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 8), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelFsp, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(ConfidentialCompute, 1), + GPU_CHILD_PRESENT(KernelCcu, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_GH100(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GH100); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_GH100); return gpuChildrenPresent_GH100; } +/*! + * @brief Determine if GPU is configured in Self Hosted mode. + * In Hopper+, GPU can be configured to work in Self Hosted, + * Externally Hosted and Endpoint mode. + * + * @param[in] pGpu OBJGPU pointer + * + * @return void + */ +void +gpuDetermineSelfHostedMode_KERNEL_GH100 +( + OBJGPU *pGpu +) +{ + if (IS_GSP_CLIENT(pGpu)) + { + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + if (pGSCI->bSelfHostedMode) + { + pGpu->bIsSelfHosted = NV_TRUE; + NV_PRINTF(LEVEL_INFO, "SELF HOSTED mode detected after reading GSP static info.\n"); + } + } +} + +/*! + * @brief Determine if MIG can be supported. + * In self hosted hopper, MIG can be supported only from specific + * GH100 revisions. + * + * @param[in] pGpu OBJGPU pointer + * + * @return void + */ +void +gpuDetermineMIGSupport_GH100 +( + OBJGPU *pGpu +) +{ + if (gpuIsSelfHosted(pGpu) && + (gpuGetChipSubRev_HAL(pGpu) < NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R)) + { + NV_PRINTF(LEVEL_ERROR, "Disabling MIG Support. MIG can be supported on self hosted hopper " + "only from revision R onwards\n"); + pGpu->setProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED, NV_FALSE); + } +} + +/*! + * Check if CC bit has been set in the scratch register + * + * @param[in] pGpu GPU object pointer + */ +NvBool +gpuIsCCEnabledInHw_GH100 +( + OBJGPU *pGpu +) +{ + NvU32 val = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC); + return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_20_CC, _MODE_ENABLED, _TRUE, val); +} + +/*! + * Check if dev mode bit has been set in the scratch register + * + * @param[in] pGpu GPU object pointer + */ +NvBool +gpuIsDevModeEnabledInHw_GH100 +( + OBJGPU *pGpu +) +{ + NvU32 val = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC); + return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_20_CC, _DEV_ENABLED, _TRUE, val); +} + diff --git a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c index bfd299320e..f9435dc09d 100644 --- a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c +++ b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c @@ -22,6 +22,7 @@ */ #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "gpu_mgr/gpu_mgr_sli.h" #include "gpu/bif/kernel_bif.h" #include "jt.h" @@ -376,6 +377,7 @@ gpuGetIdInfo_GM107(OBJGPU *pGpu) static const GPUCHILDORDER gpuChildOrderList_GM200[] = { + {classId(ConfidentialCompute), GCO_ALL}, {classId(Pxuc), GCO_ALL}, {classId(OBJBIF), GCO_ALL}, {classId(KernelBif), GCO_ALL}, @@ -471,7 +473,7 @@ gpuChildOrderList_GM200[] = const GPUCHILDORDER * gpuGetChildrenOrder_GM200(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildOrderList_GM200); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildOrderList_GM200); return gpuChildOrderList_GM200; } @@ -489,80 +491,34 @@ gpuGetChildrenOrder_GM200(OBJGPU *pGpu, NvU32 *pNumEntries) // static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = { - { classId(OBJFUSE), 1, }, - { classId(OBJSEQ), 1, }, - { classId(GpuMutexMgr), 1, }, - { classId(OBJTMR), 1, }, - { classId(GraphicsManager), 1, }, - { classId(MIGManager), 1, }, - { classId(KernelMIGManager), 1, }, - { classId(KernelGraphicsManager), 1, }, - { classId(OBJVBIOS), 1, }, - { classId(OBJDCB), 1, }, - { classId(OBJGPIO), 1, }, - { classId(I2c), 1, }, - { classId(Spi), 1, }, - { classId(KernelRc), 1, }, - { classId(OBJRC), 1, }, - { classId(OBJSTEREO), 1, }, - { classId(Intr), 1, }, - { classId(OBJINFOROM), 1, }, - { classId(NvDebugDump), 1, }, - { classId(SMDebugger), 1, }, - { classId(OBJGPULOG), 1, }, - { classId(OBJGPUMON), 1, }, - {classId(OBJSWENG), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJBSP), 1}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 3}, - {classId(KernelCE), 3}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1}, - {classId(Hshub), 1}, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(KernelFifo), 1}, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDA), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 2}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Therm), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 3), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_GM200(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_GM200); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_GM200); return gpuChildrenPresent_GM200; } diff --git a/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c b/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c index 117e2b506c..81e1eb7e78 100644 --- a/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c +++ b/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c @@ -24,6 +24,7 @@ #include "core/core.h" #include "gpu/gpu.h" #include "gpu/eng_desc.h" +#include "gpu/gpu_child_class_defs.h" #include "gpu/nvlink/kernel_nvlink.h" #include "gpu_mgr/gpu_mgr_sli.h" diff --git a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c index a5c7ef6ed3..8ad221cb06 100644 --- a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ #include "gpu/gpu.h" +#include "gpu/gpu_child_class_defs.h" #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/hwproject.h" #include "jt.h" @@ -112,257 +113,112 @@ NvU32 gpuGetPhysAddrWidth_TU102 // static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = { - { classId(OBJFUSE), 1, }, - { classId(OBJSEQ), 1, }, - { classId(GpuMutexMgr), 1, }, - { classId(OBJTMR), 1, }, - { classId(GraphicsManager), 1, }, - { classId(MIGManager), 1, }, - { classId(KernelMIGManager), 1, }, - { classId(KernelGraphicsManager), 1, }, - { classId(OBJVBIOS), 1, }, - { classId(OBJDCB), 1, }, - { classId(OBJGPIO), 1, }, - { classId(I2c), 1, }, - { classId(Spi), 1, }, - { classId(KernelRc), 1, }, - { classId(OBJRC), 1, }, - { classId(OBJSTEREO), 1, }, - { classId(Intr), 1, }, - { classId(OBJINFOROM), 1, }, - { classId(NvDebugDump), 1, }, - { classId(SMDebugger), 1, }, - { classId(OBJGPULOG), 1, }, - { classId(OBJGPUMON), 1, }, - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJBSP), 1}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 9}, - {classId(KernelCE), 9}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1}, - {classId(Hshub), 1}, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1}, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJVMMU), 1}, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 9), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), }; static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = { - { classId(OBJFUSE), 1, }, - { classId(OBJSEQ), 1, }, - { classId(GpuMutexMgr), 1, }, - { classId(OBJTMR), 1, }, - { classId(GraphicsManager), 1, }, - { classId(MIGManager), 1, }, - { classId(KernelMIGManager), 1, }, - { classId(KernelGraphicsManager), 1, }, - { classId(OBJVBIOS), 1, }, - { classId(OBJDCB), 1, }, - { classId(OBJGPIO), 1, }, - { classId(I2c), 1, }, - { classId(Spi), 1, }, - { classId(KernelRc), 1, }, - { classId(OBJRC), 1, }, - { classId(OBJSTEREO), 1, }, - { classId(Intr), 1, }, - { classId(OBJINFOROM), 1, }, - { classId(NvDebugDump), 1, }, - { classId(SMDebugger), 1, }, - { classId(OBJGPULOG), 1, }, - { classId(OBJGPUMON), 1, }, - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJBSP), 2}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 9}, - {classId(KernelCE), 9}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(OBJHSHUBMANAGER), 1}, - {classId(Hshub), 1}, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1}, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJVMMU), 1}, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 9), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), }; static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = { - { classId(OBJFUSE), 1, }, - { classId(OBJSEQ), 1, }, - { classId(GpuMutexMgr), 1, }, - { classId(OBJTMR), 1, }, - { classId(GraphicsManager), 1, }, - { classId(MIGManager), 1, }, - { classId(KernelMIGManager), 1, }, - { classId(KernelGraphicsManager), 1, }, - { classId(OBJVBIOS), 1, }, - { classId(OBJDCB), 1, }, - { classId(OBJGPIO), 1, }, - { classId(I2c), 1, }, - { classId(Spi), 1, }, - { classId(KernelRc), 1, }, - { classId(OBJRC), 1, }, - { classId(OBJSTEREO), 1, }, - { classId(Intr), 1, }, - { classId(OBJINFOROM), 1, }, - { classId(NvDebugDump), 1, }, - { classId(SMDebugger), 1, }, - { classId(OBJGPULOG), 1, }, - { classId(OBJGPUMON), 1, }, - {classId(OBJSWENG), 1}, - {classId(OBJUVM), 1}, - {classId(OBJACR), 1}, - {classId(OBJBIF), 1}, - {classId(KernelBif), 1}, - {classId(OBJBSP), 3}, - {classId(OBJBUS), 1}, - {classId(KernelBus), 1}, - {classId(OBJCE), 9}, - {classId(KernelCE), 9}, - {classId(OBJCIPHER), 1}, - {classId(ClockManager), 1}, - {classId(OBJDISP), 1}, - {classId(KernelDisplay), 1}, - {classId(VirtMemAllocator), 1}, - {classId(OBJDPAUX), 1}, - {classId(Fan), 1}, - {classId(MemorySystem), 1}, - {classId(KernelMemorySystem), 1}, - {classId(MemoryManager), 1}, - {classId(OBJFBFLCN), 1}, - {classId(KernelFifo), 1}, - {classId(OBJFIFO), 1}, - {classId(OBJGMMU), 1}, - {classId(KernelGmmu), 1}, - {classId(Graphics), 1}, - {classId(KernelGraphics), 1}, - {classId(OBJHDACODEC), 1}, - {classId(OBJHWPM), 1}, - {classId(Lpwr ), 1}, - {classId(OBJLSFM), 1}, - {classId(OBJMC), 1}, - {classId(KernelMc), 1}, - {classId(PrivRing), 1}, - {classId(SwIntr), 1}, - {classId(OBJMSENC), 1}, - {classId(KernelNvlink), 1}, - {classId(Nvlink), 1}, - {classId(Perf), 1}, - {classId(KernelPerf), 1}, - {classId(Pmgr), 1}, - {classId(Pmu), 1}, - {classId(KernelPmu), 1}, - {classId(OBJSEC2), 1}, - {classId(Gsp), 1}, - {classId(Therm), 1}, - {classId(OBJVOLT), 1}, - {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJVMMU), 1}, - {classId(KernelSec2), 1}, - {classId(KernelGsp), 1}, + GPU_CHILD_PRESENT(OBJTMR, 1), + GPU_CHILD_PRESENT(KernelMIGManager, 1), + GPU_CHILD_PRESENT(KernelGraphicsManager, 1), + GPU_CHILD_PRESENT(KernelRc, 1), + GPU_CHILD_PRESENT(Intr, 1), + GPU_CHILD_PRESENT(NvDebugDump, 1), + GPU_CHILD_PRESENT(OBJGPUMON, 1), + GPU_CHILD_PRESENT(OBJSWENG, 1), + GPU_CHILD_PRESENT(OBJUVM, 1), + GPU_CHILD_PRESENT(KernelBif, 1), + GPU_CHILD_PRESENT(KernelBus, 1), + GPU_CHILD_PRESENT(KernelCE, 9), + GPU_CHILD_PRESENT(KernelDisplay, 1), + GPU_CHILD_PRESENT(VirtMemAllocator, 1), + GPU_CHILD_PRESENT(KernelMemorySystem, 1), + GPU_CHILD_PRESENT(MemoryManager, 1), + GPU_CHILD_PRESENT(KernelFifo, 1), + GPU_CHILD_PRESENT(KernelGmmu, 1), + GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelMc, 1), + GPU_CHILD_PRESENT(SwIntr, 1), + GPU_CHILD_PRESENT(KernelNvlink, 1), + GPU_CHILD_PRESENT(KernelPerf, 1), + GPU_CHILD_PRESENT(KernelPmu, 1), + GPU_CHILD_PRESENT(KernelSec2, 1), + GPU_CHILD_PRESENT(KernelGsp, 1), }; const GPUCHILDPRESENT * gpuGetChildrenPresent_TU102(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_TU102); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU102); return gpuChildrenPresent_TU102; } const GPUCHILDPRESENT * gpuGetChildrenPresent_TU104(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_TU104); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU104); return gpuChildrenPresent_TU104; } const GPUCHILDPRESENT * gpuGetChildrenPresent_TU106(OBJGPU *pGpu, NvU32 *pNumEntries) { - *pNumEntries = NV_ARRAY_ELEMENTS32(gpuChildrenPresent_TU106); + *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU106); return gpuChildrenPresent_TU106; } diff --git a/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c b/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c index 29fe907f5f..e1228afb5f 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ +/* ------------------------ Includes ---------------------------------------- */ #include "os/os.h" #include "gpu/bif/kernel_bif.h" @@ -84,3 +85,4 @@ _kbifPreOsCheckErotGrantAllowed_AD102 return FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _ALLOW, _YES, reg); } + diff --git a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c index 453adde3a4..c39288fb82 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,7 @@ #include "nverror.h" #include "gpu/bif/kernel_bif.h" +#include "gpu/fsp/kern_fsp.h" #include "platform/chipset/chipset.h" #include "ctrl/ctrl2080/ctrl2080bus.h" @@ -660,7 +661,7 @@ kbifProbePcieReqAtomicCaps_GH100 * * @param[in] pGpu GPU object pointer * @param[in] pKernelBif Kernel BIF object pointer - * + * */ void kbifEnablePcieAtomics_GH100 diff --git a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c index e94870e2ca..cb717b6567 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c @@ -663,3 +663,4 @@ kbifDisableSysmemAccess_GM107 return status; } + diff --git a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c index 909cfbcde7..e906f49700 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c @@ -31,8 +31,6 @@ #include "virtualization/kernel_vgpu_mgr.h" #include "virtualization/hypervisor/hypervisor.h" -#define NUM_VF_SPARSE_MMAP_REGIONS 2 - #include "published/turing/tu102/dev_nv_xve.h" #include "published/turing/tu102/dev_vm.h" @@ -92,136 +90,112 @@ kbifDisableP2PTransactions_TU102 } } -/*! - * @brief Get the number of sparse mmap regions - * - * @param[in] pGpu GPU object pointer - * @param[in] pKernelBif BIF object pointer - * @param[out] numAreas Number of sparse mmap regions - * - * @returns NV_OK If all args are proper - * NV_ERR_INVALID_ARGUMENT In case of erroneous args - */ - NV_STATUS -kbifGetNumVFSparseMmapRegions_TU102 +kbifGetVFSparseMmapRegions_TU102 ( OBJGPU *pGpu, KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, - NvU32 *numAreas + NvU64 osPageSize, + NvU32 *pNumAreas, + NvU64 *pOffsets, + NvU64 *pSizes ) { - if (numAreas && pKernelHostVgpuDevice != NULL) - { - NvU32 maxInstance = 0; - NV_STATUS status; + NvU64 offsetStart = 0; + NvU64 offsetEnd = 0; + NvU32 idx = 0; + NvU32 maxInstance; + NvU32 i; + NvBool bDryRun; - status = kvgpumgrGetMaxInstanceOfVgpu(pKernelHostVgpuDevice->vgpuType, &maxInstance); - if (status != NV_OK) - goto exit; + NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelHostVgpuDevice != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pNumAreas != NULL, NV_ERR_INVALID_ARGUMENT); - if (maxInstance != 1 && pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE)) - *numAreas = NUM_VF_SPARSE_MMAP_REGIONS + 1; // +1 for TLB invalidation - else - *numAreas = NUM_VF_SPARSE_MMAP_REGIONS; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kvgpumgrGetMaxInstanceOfVgpu(pKernelHostVgpuDevice->vgpuType, + &maxInstance)); - return NV_OK; + // Dry run to calculate the total number of areas + bDryRun = ((pOffsets == NULL) || (pSizes == NULL)); + if (bDryRun) + { + pOffsets = portMemAllocStackOrHeap(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES * sizeof(pOffsets[0])); + pSizes = portMemAllocStackOrHeap(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES * sizeof(pSizes[0])); } -exit: - return NV_ERR_INVALID_ARGUMENT; -} - -NV_STATUS -kbifGetVFSparseMmapRegions_TU102 -( - OBJGPU *pGpu, - KernelBif *pKernelBif, - KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, - NvU64 os_page_size, - NvU64 *offsets, - NvU64 *sizes) -{ - NvBool bEmulateVfTlbInvalidation = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE); - NvU64 offsetStart = 0; - NvU64 offsetEnd = 0; - int idx = 0; + // For SRIOV heavy, trap BOOT_0 page + if (gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + { + offsetStart = osPageSize; + } - if (offsets && sizes && pKernelHostVgpuDevice != NULL) + // For VF TLB emulation, trap MMU FAULT BUFFER page + if ((maxInstance > 1) && pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE)) { - NvU32 maxInstance = 0; - NV_STATUS status; + offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0); + pOffsets[idx] = offsetStart; + pSizes[idx] = offsetEnd - offsetStart; + idx++; - status = kvgpumgrGetMaxInstanceOfVgpu(pKernelHostVgpuDevice->vgpuType, &maxInstance); - if (status != NV_OK) - return NV_ERR_INVALID_ARGUMENT; + offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + osPageSize; + } - // For SRIOV heavy, trap BOOT_0 page - if (gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) - { - offsetStart = os_page_size; - } + // For non-GSP, trap VGPU_EMU page + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + offsetEnd = DRF_BASE(NV_VGPU_EMU); + pOffsets[idx] = offsetStart; + pSizes[idx] = offsetEnd - offsetStart; + idx++; - // For VF TLB emulation, trap MMU FAULT BUFFER page - if ((maxInstance > 1) && bEmulateVfTlbInvalidation) - { - offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0); - offsets[idx] = offsetStart; - sizes[idx] = offsetEnd - offsetStart; - idx++; + offsetStart = DRF_BASE(NV_VGPU_EMU) + osPageSize; + } - offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size; - } + // For non-HyperV, trap MSI-X table page + if (!hypervisorIsType(OS_HYPERVISOR_HYPERV)) + { + // Assert whenever the MSI-X table page is not immediately after + // the NV_VGPU_EMU page, as it will break the current assumption. + ct_assert((DRF_BASE(NV_VGPU_EMU) + DRF_SIZE(NV_VGPU_EMU)) == NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0)); - // For non-GSP, trap VGPU_EMU page - if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0); + + // Since MSI-X page is immediately after VGPU_EMU, if both are + // trapped, skip creating a 0 size region in between + if (offsetEnd > offsetStart) { - offsetEnd = DRF_BASE(NV_VGPU_EMU); - offsets[idx] = offsetStart; - sizes[idx] = offsetEnd - offsetStart; + pOffsets[idx] = offsetStart; + pSizes[idx] = offsetEnd - offsetStart; idx++; - - offsetStart = DRF_BASE(NV_VGPU_EMU) + os_page_size; } - // For non-HyperV, trap MSI-X table page - if (!hypervisorIsType(OS_HYPERVISOR_HYPERV)) - { - // Assert whenever the MSI-X table page is not immediately after - // the NV_VGPU_EMU page, as it will break the current assumption. - NV_ASSERT((DRF_BASE(NV_VGPU_EMU) + DRF_SIZE(NV_VGPU_EMU)) == - NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0)); - - offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0); - - // Since MSI-X page is immediately after VGPU_EMU, if both are - // trapped, skip creating a 0 size region in between - if (offsetEnd > offsetStart) - { - offsets[idx] = offsetStart; - sizes[idx] = offsetEnd - offsetStart; - idx++; - } - - offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size; - } + offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + osPageSize; + } - offsetEnd = pGpu->sriovState.vfBarSize[0]; - offsets[idx] = offsetStart; - sizes[idx] = offsetEnd - offsetStart; - idx++; + offsetEnd = pGpu->sriovState.vfBarSize[0]; + pOffsets[idx] = offsetStart; + pSizes[idx] = offsetEnd - offsetStart; + idx++; + + if (bDryRun) + { + portMemFreeStackOrHeap(pOffsets); + portMemFreeStackOrHeap(pSizes); } else { - return NV_ERR_INVALID_ARGUMENT; - } + // It might be too late to check if the passed arrays are big enough, + // but better late than never + NV_ASSERT_OR_RETURN(idx <= *pNumAreas, NV_ERR_FATAL_ERROR); - for (int i = 0; i < idx; i++) - { - NV_PRINTF(LEVEL_INFO, "VF Sparse Mmap Region[%u] range 0x%llx - 0x%llx, size 0x%llx\n", - i, offsets[i], offsets[i] + sizes[i], sizes[i]); + for (i = 0; i < idx; i++) + { + NV_PRINTF(LEVEL_INFO, "VF Sparse Mmap Region[%u] range 0x%llx - 0x%llx, size 0x%llx\n", + i, pOffsets[i], pOffsets[i] + pSizes[i], pSizes[i]); + } } + *pNumAreas = idx; return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c index f1071457d4..80464e5f3c 100644 --- a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c +++ b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,6 +73,9 @@ kbifConstructEngine_IMPL // Disables P2P on VF kbifDisableP2PTransactions_HAL(pGpu, pKernelBif); + // Cache MNOC interface support + kbifIsMnocSupported_HAL(pGpu, pKernelBif); + // Used to track when the link has gone into Recovery, which can cause CEs. pKernelBif->EnteredRecoverySinceErrorsLastChecked = NV_FALSE; @@ -245,6 +248,7 @@ kbifStateUnload_IMPL NvU32 flags ) { + return NV_OK; } @@ -372,7 +376,7 @@ kbifInitPcieDeviceControlStatus kbifPcieConfigDisableRelaxedOrdering_HAL(pGpu, pKernelBif); } - // + // // WAR for bug 3661529. All GH100 SKUs will need the NoSnoop WAR. // But currently GSP-RM does not detect this correctly, // @@ -515,7 +519,7 @@ kbifIsMSIXEnabled_IMPL } /*! - * @brief Clear PCIe HW PCIe config space error counters. + * @brief Clear PCIe HW PCIe config space error counters. * All of these should be cleared using config cycles. * * @param[in] pGpu GPU object pointer @@ -704,6 +708,7 @@ _kbifInitRegistryOverrides NV_PRINTF(LEVEL_INFO, "allow peermapping reg key = %d\n", data32); pKernelBif->peerMappingOverride = !!data32; } + } /*! @@ -728,8 +733,8 @@ _kbifCheckIfGpuExists } } -static NvU32 -kbifGetGpuLinkCapabilities +NvU32 +kbifGetGpuLinkCapabilities_IMPL ( OBJGPU *pGpu, KernelBif *pKernelBif @@ -752,8 +757,8 @@ kbifGetGpuLinkCapabilities return data; } -static NvU32 -kbifGetGpuLinkControlStatus +NvU32 +kbifGetGpuLinkControlStatus_IMPL ( OBJGPU *pGpu, KernelBif *pKernelBif @@ -808,8 +813,8 @@ kbifControlGetPCIEInfo_IMPL if (kbifGetBusIntfType_HAL(pKernelBif) != NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS) { - // KMD cannot handle error codes for this ctrl call, hence returning - // NV_OK, once KMD fixes the bug:3545197, RM can return NV_ERR_NOT_SUPPORTED + // KMD cannot handle error codes for this ctrl call, hence returning + // NV_OK, once KMD fixes the bug:3545197, RM can return NV_ERR_NOT_SUPPORTED return NV_OK; } @@ -935,7 +940,7 @@ kbifControlGetPCIEInfo_IMPL { NV2080_CTRL_BUS_INFO busInfo = {0}; NV_STATUS rmStatus = NV_OK; - + busInfo.index = NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO; if ((rmStatus = kbusSendBusInfo(pGpu, GPU_GET_KERNEL_BUS(pGpu), &busInfo)) != NV_OK) @@ -1130,7 +1135,6 @@ kbifPollDeviceOnBus_IMPL KernelBif *pKernelBif ) { - NV_STATUS status = NV_OK; RMTIMEOUT timeout; gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); @@ -1141,13 +1145,13 @@ kbifPollDeviceOnBus_IMPL { if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) { - status = NV_ERR_TIMEOUT; NV_PRINTF(LEVEL_ERROR, "Timeout polling GPU back on bus\n"); DBG_BREAKPOINT(); + return NV_ERR_TIMEOUT; } osDelayUs(100); } - return status; + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c index ccae855e44..54f76ab295 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c @@ -21,6 +21,9 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" @@ -30,6 +33,7 @@ #include "gpu/mmu/kern_gmmu.h" #include "gpu/device/device.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/bus/p2p_api.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "rmapi/rmapi.h" @@ -74,7 +78,7 @@ kbusAllocateLegacyFlaVaspace_GA100 //Allocate the client in RM which owns the FLAVASpace status = pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_NULL_OBJECT, - NV01_ROOT, &pKernelBus->flaInfo.hClient); + NV01_ROOT, &pKernelBus->flaInfo.hClient, sizeof(pKernelBus->flaInfo.hClient)); NV_ASSERT_OR_RETURN(status == NV_OK, status); status = serverGetClientUnderLock(&g_resServ, pKernelBus->flaInfo.hClient, &pClient); @@ -87,7 +91,7 @@ kbusAllocateLegacyFlaVaspace_GA100 nv0080AllocParams.deviceId = gpuGetDeviceInstance(pGpu); status = pRmApi->AllocWithHandle(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hDevice, NV01_DEVICE_0, - &nv0080AllocParams); + &nv0080AllocParams, sizeof(nv0080AllocParams)); if (status != NV_OK) { @@ -104,7 +108,7 @@ kbusAllocateLegacyFlaVaspace_GA100 status = pRmApi->AllocWithHandle(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hDevice, pKernelBus->flaInfo.hSubDevice, NV20_SUBDEVICE_0, - &nv2080AllocParams); + &nv2080AllocParams, sizeof(nv2080AllocParams)); if (status != NV_OK) { @@ -138,7 +142,7 @@ kbusAllocateLegacyFlaVaspace_GA100 // Allocate a FERMI_VASPACE_A object and associate it with hFlaVASpace status = pRmApi->AllocWithHandle(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hDevice, pKernelBus->flaInfo.hFlaVASpace, FERMI_VASPACE_A, - &vaParams); + &vaParams, sizeof(vaParams)); if (bAcquireLock) { NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, @@ -325,7 +329,7 @@ kbusAllocateFlaVaspace_GA100 if (pGpu->pFabricVAS != NULL) { NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( - dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, base, size), free_instblk); } @@ -516,7 +520,7 @@ kbusAllocateHostManagedFlaVaspace_GA100 if (pGpu->pFabricVAS != NULL) { NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( - dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, base, size), free_instblk); } @@ -548,8 +552,8 @@ kbusAllocateHostManagedFlaVaspace_GA100 return status; } -/*! - * Top level function to check if the platform supports FLA, and initialize if +/*! + * Top level function to check if the platform supports FLA, and initialize if * supported. This function gets called in all the platforms where Nvlink is enabled. * * @param[in] base VASpace base @@ -604,7 +608,7 @@ kbusCheckFlaSupportedAndInit_GA100 } /*! - * @brief Determine FLA Base and Size for NvSwitch Virtualization systems + * @brief Determine FLA Base and Size for NvSwitch Virtualization systems * from reading the scratch registers. This determines FLA base and size * GA100 direct connected systems as well as skip allocation of FLA Vaspace * for vgpu host. @@ -1012,11 +1016,13 @@ kbusGetNvlinkP2PPeerId_GA100 KernelBus *pKernelBus0, OBJGPU *pGpu1, KernelBus *pKernelBus1, - NvU32 *nvlinkPeer + NvU32 *nvlinkPeer, + NvU32 attributes ) { KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); NV_STATUS status = NV_OK; + NvBool bEgmPeer = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES, attributes); if (nvlinkPeer == NULL) { @@ -1035,8 +1041,8 @@ kbusGetNvlinkP2PPeerId_GA100 // If NVLINK topology is forced and the forced configuration has peer links, // get the peer ID from the table // - if (knvlinkIsForcedConfig(pGpu0, pKernelNvlink0) || - pKernelNvlink0->bRegistryLinkOverride) + if ((knvlinkIsForcedConfig(pGpu0, pKernelNvlink0) || + pKernelNvlink0->bRegistryLinkOverride) && !bEgmPeer) { if (knvlinkGetPeersNvlinkMaskFromHshub(pGpu0, pKernelNvlink0) != 0) { @@ -1064,7 +1070,15 @@ kbusGetNvlinkP2PPeerId_GA100 } // Return if a peer ID is already allocated for P2P from pGpu0 to pGpu1 - *nvlinkPeer = kbusGetPeerId_HAL(pGpu0, pKernelBus0, pGpu1); + if (bEgmPeer) + { + *nvlinkPeer = kbusGetEgmPeerId_HAL(pGpu0, pKernelBus0, pGpu1); + } + else + { + *nvlinkPeer = kbusGetPeerId_HAL(pGpu0, pKernelBus0, pGpu1); + } + if (*nvlinkPeer != BUS_INVALID_PEER) { return NV_OK; @@ -1080,8 +1094,7 @@ kbusGetNvlinkP2PPeerId_GA100 // 2. Mix of direct NVLink and NVSwitch connections is supported // None of the above hold true currently // - if ((pGpu0 == pGpu1) || - knvlinkIsGpuConnectedToNvswitch(pGpu0, pKernelNvlink0)) + if (((pGpu0 == pGpu1) && !bEgmPeer) || knvlinkIsGpuConnectedToNvswitch(pGpu0, pKernelNvlink0)) { *nvlinkPeer = 0; @@ -1110,6 +1123,12 @@ kbusGetNvlinkP2PPeerId_GA100 // Reserve the peer ID for NVLink use status = kbusReserveP2PPeerIds_HAL(pGpu0, pKernelBus0, NVBIT(*nvlinkPeer)); + if ((status == NV_OK) && + !knvlinkIsGpuConnectedToNvswitch(pGpu0, pKernelNvlink0)) + { + pKernelBus0->p2p.bEgmPeer[*nvlinkPeer] = bEgmPeer; + } + return status; } @@ -1375,3 +1394,36 @@ kbusGetFlaRange_GA100 return NV_OK; } + +/*! + * @brief Returns the Nvlink specific peer number from pGpu (Local) to pGpuPeer. + * Used only by VF. + * + * @param[in] pGpu Local + * @param[in] pKernelBus Local + * @param[in] pGpuPeer Remote + * + * @returns NvU32 bus peer number + */ +NvU32 +kbusGetNvlinkPeerId_GA100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + OBJGPU *pGpuPeer +) +{ + NvU32 gpuPeerInst = gpuGetInstance(pGpuPeer); + NvU32 peerId = pKernelBus->p2p.busNvlinkPeerNumberMask[gpuPeerInst]; + + if (peerId == 0) + { + NV_PRINTF(LEVEL_INFO, + "NVLINK P2P not set up between GPU%u and GPU%u, checking for PCIe P2P...\n", + gpuGetInstance(pGpu), gpuPeerInst); + return BUS_INVALID_PEER; + } + + LOWESTBITIDX_32(peerId); + return peerId; +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c index 0b7591728f..8710bb7114 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c @@ -32,6 +32,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_sys/kern_mem_sys.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/mem_mgr/virt_mem_allocator_common.h" #include "mem_mgr/fabric_vaspace.h" #include "mem_mgr/virt_mem_mgr.h" #include "vgpu/rpc.h" @@ -56,6 +57,9 @@ ((HOPPER_WRITE_MAILBOX_SIZE << kbusGetP2PWriteMailboxAddressSize_HAL(pGpu)) - \ HOPPER_WRITE_MAILBOX_SIZE) +// RM reserved memory region is mapped separately as it is not added to the kernel +#define COHERENT_CPU_MAPPING_RM_RESV_REGION COHERENT_CPU_MAPPING_REGION_1 + /*! * @brief Gets the P2P write mailbox address size (NV_XAL_EP_P2P_WMBOX_ADDR_ADDR) * @@ -118,7 +122,7 @@ kbusReadBAR0WindowBase_GH100 NvBool kbusValidateBAR0WindowBase_GH100 ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 base ) @@ -134,6 +138,12 @@ kbusSetBAR0WindowVidOffset_GH100 NvU64 vidOffset ) { + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + NV_ASSERT_FAILED("kbusSetBAR0WindowVidOffset_HAL call in coherent path\n"); + return NV_ERR_INVALID_STATE; + } + NV_ASSERT((vidOffset & 0xffff)==0); NV_ASSERT(kbusValidateBAR0WindowBase_HAL(pGpu, pKernelBus, vidOffset >> NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT)); @@ -230,7 +240,7 @@ kbusVerifyBar2_GH100 NvU32 flagsClean = 0; NvU64 bar2VirtualAddr = 0; - NV_ASSERT_OR_RETURN(pGpu->getProperty(pGPU, PDB_PROP_GPU_COHERENT_CPU_MAPPING) == NV_FALSE, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) == NV_FALSE, NV_ERR_INVALID_STATE); // // kbusVerifyBar2 will test BAR0 against sysmem on Tegra; otherwise skip @@ -571,7 +581,8 @@ kbusTeardownBar2CpuAperture_GH100 } else { - if (pKernelBus->virtualBar2[gfid].pPageLevels) + if (pKernelBus->virtualBar2[gfid].pPageLevels != NULL && + pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc != NULL) { memmgrMemDescEndTransfer(GPU_GET_MEMORY_MANAGER(pGpu), pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, @@ -856,6 +867,508 @@ kbusIsPeerIdValid_GH100 return kbusIsPeerIdValid_GP100(pGpu, pKernelBus, peerId); } +/*! + * @brief Create C2C mappings for FB memory + * When this is called, we should not have any BAR1/BAR2 mappings + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] numaOnlineMemorySize Size of FB memory to online in + * kernel as a NUMA node + * @param[in] bFlush Flush CPU cache or not + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbusCreateCoherentCpuMapping_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 numaOnlineMemorySize, + NvBool bFlush +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NV_STATUS status = NV_OK; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + NvP64 pCpuMapping = NvP64_NULL; + NvU64 fbSize; + NvU64 busAddrStart; + NvU64 busAddrSize; + NvU32 i; + NvU64 memblockSize; + NvU32 cachingMode[COHERENT_CPU_MAPPING_TOTAL_REGIONS]; + + NV_ASSERT_OR_RETURN(gpuIsSelfHosted(pGpu) && pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP), NV_ERR_INVALID_STATE); + + // Assert no BAR1/BAR2 mappings + NV_ASSERT_OR_RETURN(kbusGetBar1VASpace_HAL(pGpu, pKernelBus) == NULL, + NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(listCount(&pKernelBus->virtualBar2[GPU_GFID_PF].usedMapList) == 0, + NV_ERR_INVALID_STATE); + + fbSize = (pMemoryManager->Ram.fbTotalMemSizeMb << 20); + + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + + pKernelBus->coherentCpuMapping.nrMapping = 2; + + pKernelBus->coherentCpuMapping.physAddr[COHERENT_CPU_MAPPING_REGION_0] = pMemoryManager->Ram.fbRegion[0].base; + pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_REGION_0] = numaOnlineMemorySize; + cachingMode[COHERENT_CPU_MAPPING_REGION_0] = NV_MEMORY_CACHED; + + pKernelBus->coherentCpuMapping.physAddr[COHERENT_CPU_MAPPING_RM_RESV_REGION] = + pKernelBus->coherentCpuMapping.physAddr[COHERENT_CPU_MAPPING_REGION_0] + + pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_REGION_0]; + pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_RM_RESV_REGION] = + fbSize - pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_REGION_0]; + + if (pKernelMemorySystem->bBug3656943WAR) + { + // + // RM reserved region should be mapped as Normal Non-cacheable as a SW WAR + // for the bug 3656943. NV_MEMORY_WRITECOMBINED translates to linux + // kernel ioremap_wc which actually uses the normal non-cacheable type + // PROT_NORMAL_NC + // + cachingMode[COHERENT_CPU_MAPPING_RM_RESV_REGION] = NV_MEMORY_WRITECOMBINED; + } + else + { + cachingMode[COHERENT_CPU_MAPPING_RM_RESV_REGION] = NV_MEMORY_CACHED; + } + + for (i = COHERENT_CPU_MAPPING_REGION_0; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) + { + busAddrStart = pKernelMemorySystem->coherentCpuFbBase + pKernelBus->coherentCpuMapping.physAddr[i]; + busAddrSize = pKernelBus->coherentCpuMapping.size[i]; + + // In SHH, CPU uses coherent C2C link to access GPU memory and hence it can be accessed cached. + status = osMapPciMemoryKernel64(pGpu, + (NvUPtr)busAddrStart, + (NvU64)busAddrSize, + NV_PROTECT_READ_WRITE, + &(pCpuMapping), + cachingMode[i]); + + NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_GENERIC); + + pKernelBus->coherentCpuMapping.pCpuMapping[i] = (NvP64)pCpuMapping; + pKernelBus->coherentCpuMapping.size[i] = busAddrSize; + + NV_ASSERT_OR_RETURN(bFlush == NV_FALSE, NV_ERR_NOT_SUPPORTED); + + // Counts the number of outstanding mappings in FB. + pKernelBus->coherentCpuMapping.refcnt[i] = 0; + } + + pKernelBus->coherentCpuMapping.bCoherentCpuMapping = NV_TRUE; + + NV_PRINTF(LEVEL_INFO, "Enabling CPU->C2C->FBMEM path\n"); + + return status; +} + +/*! + * @brief Sanity test coherent link between CPU and GPU. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus Kernel bus pointer + * + * @returns NV_OK on success. + */ +NV_STATUS +kbusVerifyCoherentLink_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU64 size = BUS_COHERENT_LINK_TEST_BUFFER_SIZE; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvU8 *pOffset = NULL; + const NvU32 sampleData = 0x12345678; + NV_STATUS status = NV_OK; + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvU32 index = 0; + NvU32 flagsClean = 0; + MEMORY_DESCRIPTOR memDesc; + + // Skip the test if 0FB configuration is used. + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + { + NV_PRINTF(IS_EMULATION(pGpu) ? LEVEL_ERROR : LEVEL_INFO, + "Skipping Coherent link test\n"); + return NV_OK; + } + + NV_ASSERT_OR_RETURN(pKernelBus->coherentLinkTestBufferBase != 0, NV_ERR_INVALID_STATE); + memdescCreateExisting(&memDesc, pGpu, size, ADDR_FBMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE); + memdescDescribe(&memDesc, ADDR_FBMEM, pKernelBus->coherentLinkTestBufferBase, size); + + pOffset = kbusMapRmAperture_HAL(pGpu, &memDesc); + if (pOffset == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto busVerifyCoherentLink_failed; + } + pMemDesc = &memDesc; + + for(index = 0; index < size; index += 4) + { + MEM_WR32(pOffset + index, sampleData); + } + + // Ensure the writes are flushed out of the CPU caches. + osFlushGpuCoherentCpuCacheRange(pGpu->pOsGpuInfo, (NvUPtr)pOffset, size); + + flagsClean = NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL | + NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN; + if (kmemsysIsL2CleanFbPull(pKernelMemorySystem)) + { + flagsClean |= NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL; + } + status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flagsClean); + if (NV_OK != status) + { + NV_PRINTF(LEVEL_ERROR, "L2 evict failed\n"); + goto busVerifyCoherentLink_failed; + } + + for(index = 0; index < size; index += 4) + { + NvU32 readbackData = MEM_RD32(pOffset + index); + + if (readbackData != sampleData) + { + NV_PRINTF(LEVEL_ERROR, + "Coherent Link test readback VA = 0x%llx returned garbage 0x%x\n", + (NvUPtr)(pOffset + index), readbackData); + + DBG_BREAKPOINT_REASON(NV_ERR_MEMORY_ERROR); + status = NV_ERR_GENERIC; + } + } + +busVerifyCoherentLink_failed: + if (pOffset != NULL) + { + kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pOffset, NV_TRUE); + } + memdescDestroy(pMemDesc); + + if (status == NV_OK) + { + NV_PRINTF(IS_EMULATION(pGpu) ? LEVEL_ERROR : LEVEL_INFO, + "Coherent link test passes\n"); + } + + return status; + +} + +/** + * @brief Setup BAR1 P2P capability property. + * All Hopper+ are BAR1 P2P capable. + * + * @param pGpu + * @param pBus + * + * @return void + */ +void kbusSetupBar1P2PCapability_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU64 bar1Size = kbusGetPciBarSize(pKernelBus, 1); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 fbSize = pMemoryManager->Ram.fbUsableMemSize; + + // Make sure the BAR1 size is big enough to cover all FB + if((bar1Size >= fbSize) && (fbSize != 0)) + { + NV_PRINTF(LEVEL_INFO, "The gpu %d is BAR1 P2P capable.\n", pGpu->gpuInstance); + kbusSetBar1P2pCapable(pKernelBus, NV_TRUE); + } + else + { + NV_PRINTF(LEVEL_INFO, "The gpu %d is not BAR1 P2P capable.\n", pGpu->gpuInstance); + kbusSetBar1P2pCapable(pKernelBus, NV_FALSE); + } +} + +/*! + * @brief check if it can support BAR1 P2P between the GPUs + * At the point this function is called, the system do not support C2C and + * NVLINK P2P and the BAR1 P2P is the preferred option. + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * + * return NV_TRUE if the GPU support BAR1 P2P + */ +NvBool +kbusIsPcieBar1P2PMappingSupported_GH100 +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1 +) +{ + NvU32 gpuInst0 = gpuGetInstance(pGpu0); + NvU32 gpuInst1 = gpuGetInstance(pGpu1); + KernelBif *pKernelBif0 = GPU_GET_KERNEL_BIF(pGpu0); + NvU32 gpu0Gfid; + NvU32 gpu1Gfid; + NV_STATUS status = NV_OK; + + // Check if BAR1 P2P is disabled by a regkey + if ((pKernelBif0->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_DEFAULT) && + (pKernelBif0->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P)) + { + return NV_FALSE; + } + + // Not loopback support + if (pGpu0 == pGpu1) + { + return NV_FALSE; + } + + // Both of GPUs need to support BAR1P2P + if (!kbusIsBar1P2PCapable(pKernelBus0) || + !kbusIsBar1P2PCapable(pKernelBus1)) + { + return NV_FALSE; + } + + // + // TODO: To move this check to kbusSetupBar1P2PCapability. It should check bStaticBar1Enabled + // to determine if the GPU is Bar1P2P Capable. + // + NV_ASSERT_OK_OR_ELSE(status, vgpuGetCallingContextGfid(pGpu0, &gpu0Gfid), return NV_FALSE); + NV_ASSERT_OK_OR_ELSE(status, vgpuGetCallingContextGfid(pGpu1, &gpu1Gfid), return NV_FALSE); + if (!pKernelBus0->bar1[gpu0Gfid].bStaticBar1Enabled || + !pKernelBus1->bar1[gpu1Gfid].bStaticBar1Enabled) + { + return NV_FALSE; + } + + // + // RM only supports one type of PCIE P2P protocol, either BAR1 P2P or mailbox P2P, between + // two GPUs at a time. For more info on this topic, please check bug 3274549 comment 10 + // + // Check if there is p2p mailbox connection between the GPUs. + // + if ((pKernelBus0->p2pPcie.peerNumberMask[gpuInst1] != 0) || + (pKernelBus1->p2pPcie.peerNumberMask[gpuInst0] != 0)) + { + return NV_FALSE; + } + + return NV_TRUE; +} + +/*! + * @brief Remove source GPU IOMMU mapping for the peer GPU + * + * @param[in] pSrcGpu The source GPU + * @param[in] pSrcKernelBus The source Kernel Bus + * @param[in] pPeerGpu The peer GPU + * + * @returns void + */ +static void +_kbusRemoveStaticBar1IOMMUMapping +( + OBJGPU *pSrcGpu, + KernelBus *pSrcKernelBus, + OBJGPU *pPeerGpu, + KernelBus *pPeerKernelBus +) +{ + NvU32 peerGfid; + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + vgpuGetCallingContextGfid(pPeerGpu, &peerGfid) == NV_OK); + + NV_ASSERT_OR_RETURN_VOID(pPeerKernelBus->bar1[peerGfid].staticBar1.pDmaMemDesc != NULL); + + memdescUnmapIommu(pPeerKernelBus->bar1[peerGfid].staticBar1.pDmaMemDesc, + pSrcGpu->busInfo.iovaspaceId); +} + +/*! + * @brief Remove GPU IOMMU mapping between the pair of GPUs + * + * @param[in] pGpu0 + * @param[in] pKernelBus0 + * @param[in] pGpu1 + * @param[in] pKernelBus0 + * + * @returns void + */ +static void +_kbusRemoveStaticBar1IOMMUMappingForGpuPair +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1 +) +{ + _kbusRemoveStaticBar1IOMMUMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1); + _kbusRemoveStaticBar1IOMMUMapping(pGpu1, pKernelBus1, pGpu0, pKernelBus0); +} + +/*! + * @brief Create source GPU IOMMU mapping for the peer GPU + * + * @param[in] pSrcGpu The source GPU + * @param[in] pSrcKernelBus The source Kernel Bus + * @param[in] pPeerGpu The peer GPU + * @param[in] pPeerKernelBus The peer Kernel Bus + * + * @returns NV_OK on success + */ +static NV_STATUS +_kbusCreateStaticBar1IOMMUMapping +( + OBJGPU *pSrcGpu, + KernelBus *pSrcKernelBus, + OBJGPU *pPeerGpu, + KernelBus *pPeerKernelBus +) +{ + NvU32 peerGpuGfid; + MEMORY_DESCRIPTOR *pPeerDmaMemDesc = NULL; + RmPhysAddr peerDmaAddr; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pPeerGpu, &peerGpuGfid)); + + pPeerDmaMemDesc = pPeerKernelBus->bar1[peerGpuGfid].staticBar1.pDmaMemDesc; + + NV_ASSERT_OR_RETURN(pPeerDmaMemDesc != NULL, NV_ERR_INVALID_STATE); + + // Create the source GPU IOMMU mapping on the peer static bar1 + NV_ASSERT_OK_OR_RETURN(memdescMapIommu(pPeerDmaMemDesc, + pSrcGpu->busInfo.iovaspaceId)); + + // To get the peer DMA address of the memory for the GPU was mapped to + memdescGetPhysAddrsForGpu(pPeerDmaMemDesc, pSrcGpu, + AT_GPU, 0, 0, 1, &peerDmaAddr); + + // Check the if it is aligned to max RM_PAGE_SIZE 512M. + if (!NV_IS_ALIGNED64(peerDmaAddr, RM_PAGE_SIZE_512M)) + { + NV_PRINTF(LEVEL_ERROR, "The peer DMA address 0x%llx is not aligned at 0x%llx\n", + peerDmaAddr, RM_PAGE_SIZE_512M); + + memdescUnmapIommu(pPeerDmaMemDesc, pSrcGpu->busInfo.iovaspaceId); + + return NV_ERR_INVALID_ADDRESS; + } + + return NV_OK; +} + +/*! + * @brief To create IOMMU mapping between the pair of GPUs + * + * @param[in] pGpu0 + * @param[in] pKernelBus0 + * @param[in] pGpu1 + * @param[in] pKernelBus0 + * + * @returns NV_OK on success + */ +static NV_STATUS +_kbusCreateStaticBar1IOMMUMappingForGpuPair +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1 +) +{ + NvU32 gpuInst0 = gpuGetInstance(pGpu0); + NvU32 gpuInst1 = gpuGetInstance(pGpu1); + NV_STATUS status; + + // Create GPU0 IOMMU mapping to GPU1 BAR1 + status = _kbusCreateStaticBar1IOMMUMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "IOMMU mapping failed from GPU%u to GPU%u\n", + gpuInst0, gpuInst1); + return status; + } + + // Create GPU1 IOMMU mapping to GPU0 BAR1 + status = _kbusCreateStaticBar1IOMMUMapping(pGpu1, pKernelBus1, pGpu0, pKernelBus0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "IOMMU mapping failed from GPU%u to GPU%u\n", + gpuInst1, gpuInst0); + + // Remove the previous created IOMMU mapping + _kbusRemoveStaticBar1IOMMUMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1); + } + + return status; +} + +/*! + * @brief To get the DMA information from the source GPU to the peer GPU + * + * @param[in] pSrcGpu The source GPU + * @param[in] pPeerGpu The peer GPU + * @param[in] pPeerKernelBus The peer Kernel Bus + * @param[out] pDmaAddress The start DMA address for the source GPU + * to access the peer GPU + * @param[out] pDmaSize The size of the DMA transfer range + * + * @returns NV_OK on success + */ +NV_STATUS kbusGetBar1P2PDmaInfo_GH100 +( + OBJGPU *pSrcGpu, + OBJGPU *pPeerGpu, + KernelBus *pPeerKernelBus, + NvU64 *pDmaAddress, + NvU64 *pDmaSize +) +{ + NvU32 peerGfid; + MEMORY_DESCRIPTOR *pPeerDmaMemDesc; + + NV_ASSERT_OR_RETURN((pDmaAddress != NULL) && (pDmaSize != NULL), + NV_ERR_INVALID_ARGUMENT); + + // Set the default value + *pDmaAddress = NV_U64_MAX; + *pDmaSize = 0; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pPeerGpu, &peerGfid)); + + pPeerDmaMemDesc = pPeerKernelBus->bar1[peerGfid].staticBar1.pDmaMemDesc; + NV_ASSERT_OR_RETURN(pPeerDmaMemDesc != NULL, NV_ERR_NOT_SUPPORTED); + + // Get the peer GPU DMA address for the source GPU + memdescGetPhysAddrsForGpu(pPeerDmaMemDesc, pSrcGpu, + AT_GPU, 0, 0, 1, pDmaAddress); + + *pDmaSize = memdescGetSize(pPeerDmaMemDesc); + + return NV_OK; +} + /*! * @brief check if there is BAR1 P2P mapping between given GPUs * @@ -875,8 +1388,8 @@ kbusHasPcieBar1P2PMapping_GH100 KernelBus *pKernelBus1 ) { - return (pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu1)] != 0 && - pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu0)] != 0); + return ((pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu1)] != 0) && + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuGetInstance(pGpu0)] != 0)); } /*! @@ -903,6 +1416,7 @@ kbusCreateP2PMappingForBar1P2P_GH100 { NvU32 gpuInst0 = gpuGetInstance(pGpu0); NvU32 gpuInst1 = gpuGetInstance(pGpu1); + NV_STATUS status = NV_OK; if (IS_VIRTUAL(pGpu0) || IS_VIRTUAL(pGpu1)) { @@ -914,13 +1428,21 @@ kbusCreateP2PMappingForBar1P2P_GH100 return NV_ERR_NOT_SUPPORTED; } + // Only create IOMMU mapping between the pair of GPUs at the first time. + if ((pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) && + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0)) + { + NV_ASSERT_OK_OR_RETURN(_kbusCreateStaticBar1IOMMUMappingForGpuPair(pGpu0, pKernelBus0, + pGpu1, pKernelBus1)); + } + pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1]++; pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0]++; NV_PRINTF(LEVEL_INFO, "added PCIe BAR1 P2P mapping between GPU%u and GPU%u\n", gpuInst0, gpuInst1); - return NV_OK; + return status; } /*! @@ -954,8 +1476,8 @@ kbusRemoveP2PMappingForBar1P2P_GH100 gpuInst0 = gpuGetInstance(pGpu0); gpuInst1 = gpuGetInstance(pGpu1); - if ( (pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) || - (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0) ) + if ((pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) || + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0)) { return NV_ERR_INVALID_STATE; } @@ -963,9 +1485,15 @@ kbusRemoveP2PMappingForBar1P2P_GH100 pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1]--; pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0]--; - NV_PRINTF(LEVEL_INFO, - "removed PCIe BAR1 P2P mapping between GPU%u and GPU%u\n", - gpuInst0, gpuInst1); + // Only remove the IOMMU mapping between the pair of GPUs when it is the last mapping. + if ((pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1] == 0) && + (pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0] == 0)) + { + _kbusRemoveStaticBar1IOMMUMappingForGpuPair(pGpu0, pKernelBus0, pGpu1, pKernelBus1); + } + + NV_PRINTF(LEVEL_INFO, "removed PCIe BAR1 P2P mapping between GPU%u and GPU%u\n", + gpuInst0, gpuInst1); return NV_OK; } @@ -1231,6 +1759,419 @@ kbusRemoveP2PMappingForC2C_GH100 return status; } +NvBool +kbusNeedStaticBar1Mapping_GH100(OBJGPU *pGpu, KernelBus *pKernelBus) +{ + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + // Check if BAR1 P2P is enabled by a regkey + if (pKernelBif->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P) + { + return NV_FALSE; + } + + // We need static Bar1 only when the GPU is BAR1 P2P capable. + return kbusIsBar1P2PCapable(pKernelBus); +} + +/*! + * @brief Setup static Bar1 mapping. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] reservedFbSize The size to reserve in FB from the address 0 + * @param[in] gfid The GFID + * + * @returns NV_OK on success, or rm_status from called functions on failure. + */ +NV_STATUS +kbusEnableStaticBar1Mapping_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 reservedFbSize, + NvU32 gfid +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + MEMORY_DESCRIPTOR *pMemDesc = NULL; + MEMORY_DESCRIPTOR *pDmaMemDesc = NULL; + NvU64 bar1Size = kbusGetPciBarSize(pKernelBus, 1); + NV_STATUS status = NV_OK; + OBJEHEAP *pVASpaceHeap = vaspaceGetHeap(pKernelBus->bar1[gfid].pVAS); + NvU64 bar1Offset = RM_ALIGN_UP(reservedFbSize, RM_PAGE_SIZE_2M); + NvU64 bar1MapSize; + NvU64 staticBar1PhyAddr; + + if (!kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus)) + { + return NV_ERR_INVALID_STATE; + } + + NV_PRINTF(LEVEL_INFO, "Static bar1 size 0x%llx fb size 0x%llx\n", + bar1Size, pMemoryManager->Ram.fbUsableMemSize); + + // BAR1 VA size can be smaller than BAR1 size + bar1MapSize = NV_MIN(bar1Size, pVASpaceHeap->rangeHi); + bar1MapSize = NV_MIN(bar1MapSize, pMemoryManager->Ram.fbUsableMemSize); + + NV_ASSERT_OR_RETURN(bar1MapSize > bar1Offset, NV_ERR_INVALID_STATE); + + // Adjust the offset + bar1MapSize -= bar1Offset; + + // + // GPU BAR1 VA also supports the SYSMEM mapping, we need to reserve some + // spaces for such cases, like doorbell mapping which is not backed by + // FBMEM. + // + if ((bar1Size - (bar1MapSize + bar1Offset)) < (4 * RM_PAGE_SIZE_2M)) + { + // + // When BAR1 size much bigger than FB, then there are plenty of + // VA space left for other type of mapping. + // When BAR1 size is slightly bigger or equal FB, the available + // BAR1 VA is very limited. + // Here reserves 4 * 2MB blocks. + // !!! NOTE: Not sure how big Rm need to reserve + // TODO: Need to find a better solution, bug 3869651 + // + bar1MapSize -= 4 * RM_PAGE_SIZE_2M; + + NV_PRINTF(LEVEL_INFO, "Static bar1 reserved 8 MB from the top of FB\n"); + } + + // align to 2MB page size + bar1MapSize = RM_ALIGN_UP(bar1MapSize, RM_PAGE_SIZE_2M); + + // + // The static mapping is not backed by an allocated physical FB. + // Here RM describes the memory for the static mapping. + // + NV_ASSERT_OK_OR_RETURN(memdescCreate(&pMemDesc, pGpu, bar1MapSize, 0, + NV_MEMORY_CONTIGUOUS, ADDR_FBMEM, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE)); + + memdescDescribe(pMemDesc, ADDR_FBMEM, bar1Offset, bar1MapSize); + + // Set to use RM_PAGE_SIZE_HUGE, 2MB + memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE_HUGE); + + // Setup GMK PTE type for this memory + memdescSetPteKind(pMemDesc, NV_MMU_PTE_KIND_GENERIC_MEMORY); + + // Deploy the static mapping. + NV_ASSERT_OK_OR_GOTO(status, + kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, 0, + &bar1Offset, &bar1MapSize, + BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED, + NV01_NULL_OBJECT), + cleanup_mem); + + // Get the system physical address the base address of staticBar1 + staticBar1PhyAddr = gpumgrGetGpuPhysFbAddr(pGpu) + bar1Offset; + + // + // Create a memory descriptor to describe a SYSMEM target of the GPU + // BAR1 region. This memDesc will be used for P2P DMA related mapping. + // + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pDmaMemDesc, + pGpu, + bar1MapSize, + 0, + NV_MEMORY_CONTIGUOUS, + ADDR_SYSMEM, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE), + cleanup_bus_map); + + memdescDescribe(pDmaMemDesc, ADDR_SYSMEM, staticBar1PhyAddr, bar1MapSize); + + pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_TRUE; + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = pMemDesc; + pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = pDmaMemDesc; + pKernelBus->bar1[gfid].staticBar1.base = bar1Offset; + pKernelBus->bar1[gfid].staticBar1.size = bar1MapSize; + + NV_PRINTF(LEVEL_INFO, "Static bar1 mapped offset 0x%llx size 0x%llx\n", + bar1Offset, bar1MapSize); + + return NV_OK; + +cleanup_bus_map: + NV_ASSERT_OK(kbusUnmapFbAperture_HAL(pGpu, pKernelBus, + pMemDesc, bar1Offset, bar1MapSize, + BUS_MAP_FB_FLAGS_MAP_UNICAST | + BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED)); + +cleanup_mem: + NV_PRINTF(LEVEL_ERROR, "Failed to create the static bar1 mapping offset" + "0x%llx size 0x%llx\n", bar1Offset, bar1MapSize); + + pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_FALSE; + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = NULL; + pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = NULL; + + memdescDestroy(pDmaMemDesc); + memdescDestroy(pMemDesc); + + return status; +} + +/*! + * @brief tear down static Bar1 mapping. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] gfid The GFID + * + * @returns NV_OK on success, or rm_status from called functions on failure. + */ +NV_STATUS +kbusDisableStaticBar1Mapping_GH100(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) +{ + if (pKernelBus->bar1[gfid].bStaticBar1Enabled) + { + if (pKernelBus->bar1[gfid].staticBar1.pVidMemDesc != NULL) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusUnmapFbAperture_HAL(pGpu, pKernelBus, + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc, + pKernelBus->bar1[gfid].staticBar1.base, + pKernelBus->bar1[gfid].staticBar1.size, + BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED)); + + memdescDestroy(pKernelBus->bar1[gfid].staticBar1.pVidMemDesc); + + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = NULL; + } + + memdescDestroy(pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc); + pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = NULL; + + pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_FALSE; + } + + return NV_OK; +} + +/*! + * @brief To update the StaticBar1 PTE kind for the specified memory. + * + * The staticbar1 only support GMK (generic memory kind) and other compressed kind. + * By default, the bar1 is statically mapped with GMK at boot when the static bar1 is enabled. + * + * When to map a uncompressed kind memory, RM just return the static bar1 address which is mapped + * to the specified memory. + * + * When to map a compressed kind memory, RM must call this function to change the static mapped + * bar1 range to the specified memory from GMK to the compressed kind. And RM needs to + * call this function to change it back to GMK from the compressed kind after this mapping is released. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] pMemDesc The memory to update + * @param[in] offset The offset of the memory to update + * @param[in] length The length of the memory to update + * @param[in] bRelease Call to release the mapping + * @param[in] gfid The GFID + * + * return NV_OK on success + */ +NV_STATUS +_kbusUpdateStaticBAR1VAMapping_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 offset, + NvU64 length, + NvBool bRelease, + NvU32 gfid +) +{ + NV_STATUS status = NV_OK; + VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + OBJVASPACE *pVAS = pKernelBus->bar1[gfid].pVAS; + NvU32 kind; + MEMORY_DESCRIPTOR *pTempMemDesc; + NvU64 vAddr; + NvU64 vaLo; + NvU64 vaHi; + NvU64 physAddr; + NvU64 pageOffset; + NvU64 mapLength; + NvU64 pageSize; + DMA_PAGE_ARRAY pageArray = {0}; + COMPR_INFO comprInfo; + NvBool bCompressed; + + NV_ASSERT_OR_RETURN(pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + + NV_ASSERT_OR_RETURN(memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM, NV_ERR_INVALID_ARGUMENT); + + // It only support contiguous memory + NV_ASSERT_OR_RETURN(memdescGetPteArraySize(pMemDesc, AT_GPU) == 1, NV_ERR_INVALID_ARGUMENT); + + pTempMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); + + pageSize = memdescGetPageSize(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); + + NV_ASSERT_OK_OR_RETURN(memmgrGetKindComprFromMemDesc(pMemoryManager, pTempMemDesc, 0, &kind, &comprInfo)); + bCompressed = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, kind); + + // Static BAR1 mapping only support >=2MB page size for compressed memory + NV_CHECK_OR_RETURN(LEVEL_WARNING, bCompressed && (pageSize >= RM_PAGE_SIZE_HUGE), NV_ERR_INVALID_STATE); + + if (bRelease) + { + // update the PTE kind to be the uncompressed kind + comprInfo.kind = memmgrGetUncompressedKind_HAL(pGpu, pMemoryManager, kind, NV_FALSE); + } + + // Under static BAR1 mapping, BAR1 VA equal to physAddr + physAddr = memdescGetPhysAddr(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), offset); + vAddr = RM_ALIGN_DOWN(physAddr, pageSize); + + pageOffset = physAddr & (pageSize - 1); + mapLength = RM_ALIGN_UP(pageOffset + length, pageSize); + + vaLo = vAddr; + vaHi = vaLo + mapLength - 1; + + pageArray.count = 1; + pageArray.pData = &physAddr; + + status = dmaUpdateVASpace_HAL(pGpu, pDma, pVAS, + pTempMemDesc, NULL, + vaLo, vaHi, + DMA_UPDATE_VASPACE_FLAGS_UPDATE_KIND, // only change KIND + &pageArray, 0, + &comprInfo, 0, + NV_MMU_VER3_PTE_VALID_TRUE, + NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY, + BUS_INVALID_PEER, + NVLINK_INVALID_FABRIC_ADDR, + DMA_TLB_INVALIDATE, + NV_FALSE, + pageSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "error updating static bar1 VA space.\n"); + } + + return status; +} + +/*! + * @brief To unmap FB aperture for the specified memory under the static mapping. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] pMemDesc The memory to update + * @param[in] gfid The GFID + * + * return NV_OK on success + */ +NV_STATUS +kbusStaticUnmapFbAperture_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + MEMORY_DESCRIPTOR *pMemDesc, + NvU32 gfid +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvBool bCompressedkind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, + memdescGetPteKind(pMemDesc)); + + // + // For uncompressed type, nothing to do + // For compressed type, restore PTE kind to GMK + // + if (bCompressedkind) + { + NV_ASSERT_OK_OR_RETURN(_kbusUpdateStaticBAR1VAMapping_GH100(pGpu, pKernelBus, + pMemDesc, 0, memdescGetSize(pMemDesc), NV_TRUE, gfid)); + } + + // Nothing else to do on static mapping mode + NV_PRINTF(LEVEL_INFO, + "StaticBar1 unmapped at 0x%llx size 0x%llx%s\n", + memdescGetPhysAddr(pMemDesc, AT_GPU, 0), + memdescGetSize(pMemDesc), + bCompressedkind ? " [compressed]" : ""); + + return NV_OK; +} + +/*! + * @brief To map FB aperture for the specified memory under the static mapping. + * + * @param[in] pGpu GPU pointer + * @param[in] pKernelBus Kernel bus pointer + * @param[in] pMemDesc The memory to update + * @param[in] offset The offset of the memory to map + * @param[out] pAperOffset The Fb Aperture(BAR1) offset of the mapped vidmem + * @param[in] pLength The size of vidmem to map + * @param[in] gfid The GFID + * + * return NV_OK on success + */ +NV_STATUS +kbusStaticMapFbAperture_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 offset, + NvU64 *pAperOffset, + NvU64 *pLength, + NvU32 gfid +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 physAddr; + NvU32 status = NV_OK; + NvBool bCompressedkind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, memdescGetPteKind(pMemDesc)); + + // It only support contiguous memory + NV_ASSERT_OR_RETURN(memdescGetPteArraySize(pMemDesc, AT_GPU) == 1, NV_ERR_INVALID_ARGUMENT); + + physAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, offset); + + if (physAddr < pKernelBus->bar1[gfid].staticBar1.base || + physAddr + *pLength >= pKernelBus->bar1[gfid].staticBar1.size) + { + NV_PRINTF(LEVEL_ERROR, + "0x%llx + 0x%llx is out of the range of the StaticBar1 map [0x%llx, 0x%llx]\n", + physAddr, *pLength, pKernelBus->bar1[gfid].staticBar1.base, + pKernelBus->bar1[gfid].staticBar1.base + pKernelBus->bar1[gfid].staticBar1.size); + + return NV_ERR_INVALID_ARGUMENT; + } + + if (bCompressedkind) + { + // Update PTE to be the compressed kind + NV_ASSERT_OK_OR_RETURN(_kbusUpdateStaticBAR1VAMapping_GH100(pGpu, pKernelBus, pMemDesc, + offset, *pLength, NV_FALSE, gfid)); + } + + // When the static bar1 enabled, the Fb aperture offset is the physical address. + *pAperOffset = physAddr; + + NV_PRINTF(LEVEL_INFO, "StaticBar1 mapped at 0x%llx size 0x%llx%s\n", + physAddr, *pLength, + bCompressedkind ? " [compressed]" : ""); + + return status; +} + void kbusWriteP2PWmbTag_GH100 ( @@ -1398,11 +2339,11 @@ kbusAllocateFlaVaspace_GH100 if (GPU_GET_KERNEL_NVLINK(pGpu) != NULL) { NVLINK_INBAND_MSG_CALLBACK inbandMsgCbParams; - + inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP; inbandMsgCbParams.pCallback = &memorymulticastfabricTeamSetupResponseCallback; inbandMsgCbParams.wqItemFlags = OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW; + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW; status = knvlinkRegisterInbandCallback(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), @@ -1420,10 +2361,10 @@ kbusAllocateFlaVaspace_GH100 if (!GPU_IS_NVSWITCH_DETECTED(pGpu)) { size = gpuGetFlaVasSize_HAL(pGpu, NV_FALSE); - base = pGpu->gpuInstance * size; + base = pGpu->gpuInstance * size; NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( - dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, base, size), free_instblk); } @@ -1486,7 +2427,7 @@ kbusDestroyFla_GH100 vmmDestroyVaspace(pVmm, pGpu->pFabricVAS); pGpu->pFabricVAS = NULL; - // TODO: Remove this once legacy FLA VAS support is deprecated + // TODO: Remove this once legacy FLA VAS support is deprecated pRmApi->Free(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hClient); portMemSet(&pKernelBus->flaInfo, 0, sizeof(pKernelBus->flaInfo)); if (GPU_GET_KERNEL_NVLINK(pGpu) != NULL) @@ -1623,3 +2564,47 @@ kbusGetFlaRange_GH100 return NV_OK; } + +/*! + * @brief Returns the EGM peer ID of pRemoteGpu if it was + * reserved already. + * + * @param[in] pLocalGpu local OBJGPU pointer + * @param[in] pLocalBus local OBJBUS pointer + * @param[in] pRemoteGpu remote OBJGPU pointer + * + * return NV_OK on success + * BUS_INVALID_PEER otherwise + * + */ +NvU32 +kbusGetEgmPeerId_GH100 +( + OBJGPU *pLocalGpu, + KernelBus *pLocalKernelBus, + OBJGPU *pRemoteGpu +) +{ + NvU32 gpuPeerInst = gpuGetInstance(pRemoteGpu); + NvU32 peerMask = pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpuPeerInst]; + NvU32 peerId; + + if (peerMask == 0) + { + NV_PRINTF(LEVEL_INFO, + "NVLINK P2P not set up between GPU%u and GPU%u\n", + gpuGetInstance(pLocalGpu), gpuPeerInst); + return BUS_INVALID_PEER; + } + + FOR_EACH_INDEX_IN_MASK(32, peerId, peerMask) + { + if (pLocalKernelBus->p2p.bEgmPeer[peerId]) + { + return peerId; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return BUS_INVALID_PEER; +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index ebd867eb66..e4ffe087b8 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #include "core/core.h" +#include "gpu/conf_compute/conf_compute.h" #include "gpu/gpu.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" @@ -57,10 +58,11 @@ static void _kbusLinkP2P_GM107(OBJGPU *, KernelBus *); static NvU32 _kbusGetSizeOfBar2PageDir_GM107(NvU64 vaBase, NvU64 vaLimit, NvU64 vaPerEntry, NvU32 entrySize); static NV_STATUS _kbusBar0TunnelCb_GM107(void *pPrivData, NvU64 addr, void *pData, NvU64 size, NvBool bRead); +static NV_STATUS _kbusUpdateDebugStatistics(OBJGPU *pGpu); -NV_STATUS _kbusMapAperture_GM107(OBJGPU *, PMEMORY_DESCRIPTOR, OBJVASPACE *, NvU64, NvU64 *, - NvU64 *, NvU32 mapFlags, NvHandle hClient); -NV_STATUS _kbusUnmapAperture_GM107(OBJGPU *, OBJVASPACE *, PMEMORY_DESCRIPTOR, NvU64); +NV_STATUS _kbusMapAperture_GM107(OBJGPU *, KernelBus *, PMEMORY_DESCRIPTOR, OBJVASPACE *, NvU64, NvU64 *, + NvU64 *, NvU32 mapFlags, Device *pDevice); +NV_STATUS _kbusUnmapAperture_GM107(OBJGPU *, KernelBus *, OBJVASPACE *, PMEMORY_DESCRIPTOR, NvU64); MEMORY_DESCRIPTOR* kbusCreateStagingMemdesc(OBJGPU *pGpu); // This is the peer number assignment for SLI with @@ -293,7 +295,14 @@ kbusStateInitLockedKernel_GM107 // rather than BAR0 to set up the BAR1 page table. This is faster because // BAR2 can be write-combined // - NV_ASSERT_OK_OR_RETURN(kbusInitBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + if (IS_GSP_CLIENT(pGpu) && KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "For GSP client with C2C enabled, skip BAR2 init\n"); + } + else + { + NV_ASSERT_OK_OR_RETURN(kbusInitBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + } if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) { @@ -328,6 +337,24 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) return NV_OK; } + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + if (IS_GSP_CLIENT(pGpu) && (pConfCompute != NULL) && + !(pConfCompute->ccStaticInfo.bIsBar1Trusted && pConfCompute->ccStaticInfo.bIsPcieTrusted)) + { + pKernelBus->bBarAccessBlocked = NV_TRUE; + pKernelBus->bBar2TestSkipped = NV_TRUE; + NV_PRINTF(LEVEL_INFO, "BARs will be blocked for CC\n"); + } + else + { + pKernelBus->bBarAccessBlocked = NV_FALSE; + } + + // Verify GSP-DMA functionality before it is used for bootstrapping BAR2 + NV_ASSERT_OK_OR_RETURN( + memmgrVerifyGspDmaOps(pGpu, GPU_GET_MEMORY_MANAGER(pGpu))); + if (KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) { NV_PRINTF(LEVEL_INFO, "C2C is being used, so disable CPU visible BAR1/2 now before they are setup\n"); @@ -339,18 +366,29 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) pKernelBus->bar2[GPU_GFID_PF].physAddr = 0; pKernelBus->bar1[GPU_GFID_PF].apertureLength = 0; - pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit = 0; pKernelBus->bar2[GPU_GFID_PF].rmApertureLimit = 0; // // For C2C case, there is no CPU visible BAR2. So CPU visible BAR2 - // window is removed and appended to CPU invisible BAR2 window. + // window is removed. In MONOLITHIC RM, where CPU visible and invisible + // BAR2 windows are contiguous, just shift CPU invisible BAR2 down to + // CPU invisible BAR2 base (0). // Only need to handle PF, since VF BAR1/2 is disabled for C2C case. // - NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase == 0); - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase = pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase; - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase = 0; - + if (!RMCFG_FEATURE_PLATFORM_GSP) // contiguous BAR2 + { + NV_PRINTF(LEVEL_INFO, "C2C is being used (contiguous/MONOLITHIC), update BAR2 cpuInvisibleBase: 0x%llX to 0, and cpuInvisibleLimit: 0x%llX to 0x%llX. Setting cpuVisibleLimit: 0x%llX to 0\n", + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit, + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, + pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit); + + NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase == 0); + NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit >= pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase); + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit -= pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase; + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase = pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase; + } + pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit = 0; pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; } @@ -382,11 +420,14 @@ kbusStateLoad_GM107 // FB address space may not be available on Tegra (see fbInitFbRegions) if (pMemoryManager->Ram.fbAddrSpaceSizeMb != 0) { - // Bind the BAR0 window to its default location - // note: we can't move the window for all intents and purposes since VBIOS - // will also use the window at arbitrary locations (eg during an SMI event - NvU64 offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); - kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + // Bind the BAR0 window to its default location + // note: we can't move the window for all intents and purposes since VBIOS + // will also use the window at arbitrary locations (eg during an SMI event + NvU64 offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + } } else { @@ -455,6 +496,8 @@ kbusStatePostLoad_GM107 _kbusLinkP2P_GM107(pGpu, pKernelBus); } + _kbusUpdateDebugStatistics(pGpu); + return status; } @@ -492,6 +535,9 @@ kbusStateUnload_GM107 NV_STATUS status = NV_OK; KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + if (IS_VIRTUAL(pGpu) && !(flags & GPU_STATE_FLAGS_PRESERVING)) + return NV_OK; + if ((pKernelBif != NULL) && (!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || @@ -508,9 +554,12 @@ kbusStateUnload_GM107 { if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) { - status = kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); - // Do not use BAR2 physical mode for bootstrapping BAR2 across S/R. - pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; + status = kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); + if (!IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + // Do not use BAR2 physical mode for bootstrapping BAR2 across S/R. + pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; + } } } else @@ -547,12 +596,13 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) NvU64 vaRangeMax; NvU32 vaflags; KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); - NvU32 vaSpaceBigPageSize = 0; + NvU64 vaSpaceBigPageSize = 0; OBJSYS *pSys = SYS_GET_INSTANCE(); OBJVMM *pVmm = SYS_GET_VMM(pSys); NvU32 gpuMask = 0; NvBool bSmoothTransitionEnabled = ((pGpu->uefiScanoutSurfaceSizeInMB != 0) && RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM); + NvU32 bar1ReservedSize = 0; vaRangeMax = pKernelBus->bar1[gfid].apertureLength - 1; @@ -607,10 +657,10 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) } else { - NV_PRINTF(LEVEL_ERROR, - "Arch doesnt support BAR1 Big page Override- Using defaults\n"); - NV_ASSERT(0); - vaSpaceBigPageSize = 0; + NV_PRINTF(LEVEL_ERROR, + "Arch doesnt support BAR1 Big page Override- Using defaults\n"); + NV_ASSERT(0); + vaSpaceBigPageSize = 0; } } } @@ -699,7 +749,6 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) // Restrict normal BAR1 alloc to be within the aperture pVASpaceHeap = vaspaceGetHeap(pKernelBus->bar1[gfid].pVAS); - // // Reduce BAR1 VA space by FERMI_SMALL_PAGESIZE for host overfetch bug // WAR (Bug 529932/525381). (FERMI_SMALL_PAGESIZE is sufficient to @@ -765,7 +814,7 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) rmStatus = kbusMapFbAperture_HAL(pGpu, pKernelBus, pConsoleMemDesc, fbPhysOffset, &bar1VAOffset, &consoleSize, BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED, - NV01_NULL_OBJECT); + NULL); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -793,6 +842,7 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) } pKernelBus->bBar1ConsolePreserved = NV_TRUE; + bar1ReservedSize += consoleSize; } else { @@ -803,19 +853,29 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) } } - // Reserve space for max number of peers regardless of SLI config - if ((!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || - !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) - && - IS_GFID_PF(gfid) - && - !kbusIsP2pMailboxClientAllocated(pKernelBus)) + if (kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus)) { - rmStatus = kbusAllocP2PMailboxBar1_HAL(pGpu, pKernelBus, gfid, vaRangeMax); - - if (NV_OK != rmStatus) + // Enable the static BAR1 mapping for the BAR1 P2P + NV_ASSERT_OK_OR_GOTO(rmStatus, + kbusEnableStaticBar1Mapping_HAL(pGpu, pKernelBus, bar1ReservedSize, gfid), + kbusInitBar1_failed); + } + else + { + // Reserve space for max number of peers for the mailbox p2p regardless of SLI config + if ((!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || + !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) + && + IS_GFID_PF(gfid) + && + !kbusIsP2pMailboxClientAllocated(pKernelBus)) { - goto kbusInitBar1_failed; + rmStatus = kbusAllocP2PMailboxBar1_HAL(pGpu, pKernelBus, gfid, vaRangeMax); + + if (NV_OK != rmStatus) + { + goto kbusInitBar1_failed; + } } } @@ -941,6 +1001,11 @@ kbusDestroyBar1_GM107 pKernelBus->bBar1ConsolePreserved = NV_FALSE; } + if (pKernelBus->bar1[gfid].bStaticBar1Enabled) + { + status = kbusDisableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid); + } + vmmDestroyVaspace(pVmm, pKernelBus->bar1[gfid].pVAS); pKernelBus->bar1[gfid].pVAS = NULL; @@ -995,11 +1060,8 @@ kbusInitBar2_GM107 NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); } - if (KBUS_BAR2_ENABLED(pKernelBus)) - { - status = kbusSetupBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid); - NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); - } + status = kbusSetupBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); status = kbusCommitBar2_HAL(pGpu, pKernelBus, GPU_STATE_DEFAULT); NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); @@ -1076,8 +1138,11 @@ kbusDestroyBar2_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) if (gpuIsCacheOnlyModeEnabled(pGpu) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) { - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); + // + // Send 2 explicit sysmembars. Bug 557124 + // + kbusSendSysmembar(pGpu, pKernelBus); + kbusSendSysmembar(pGpu, pKernelBus); } return status; @@ -1478,7 +1543,8 @@ kbusSetupBar2GpuVaSpace_GM107 // if (pKernelBus->bar2[gfid].pWalkStagingBuffer == NULL && pKernelBus->PTEBAR2Aperture == ADDR_FBMEM && - pKernelBus->bar2[gfid].bBootstrap) + pKernelBus->bar2[gfid].bBootstrap && + !RMCFG_FEATURE_PLATFORM_GSP) { bUseStagingBuffer = NV_TRUE; pKernelBus->bar2[gfid].pWalkStagingBuffer = kbusCreateStagingMemdesc(pGpu); @@ -1552,7 +1618,9 @@ kbusSetupBar2GpuVaSpace_GM107 cleanup: - if (IS_GFID_VF(gfid) && (pKernelBus->virtualBar2[gfid].pPageLevels != NULL)) + if (IS_GFID_VF(gfid) && + (pKernelBus->virtualBar2[gfid].pPageLevels != NULL) && + (pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc != NULL)) { kbusUnmapRmAperture_HAL(pGpu, pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, @@ -1745,6 +1813,9 @@ kbusSetupBar0WindowBeforeBar2Bootstrap_GM107 { NV_STATUS status = NV_OK; + if (kbusIsBarAccessBlocked(pKernelBus)) + return NV_OK; + NV_ASSERT_OR_RETURN(!KBUS_BAR0_PRAMIN_DISABLED(pGpu), NV_ERR_INVALID_STATE); // Check that Bar2 Page Dir starts at or after bar0 window vid offset @@ -1792,6 +1863,9 @@ kbusRestoreBar0WindowAfterBar2Bootstrap_GM107 NvU64 origVidOffset ) { + if (kbusIsBarAccessBlocked(pKernelBus)) + return; + NV_ASSERT_OR_RETURN_VOID(!KBUS_BAR0_PRAMIN_DISABLED(pGpu)); NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].bBootstrap); @@ -1934,7 +2008,40 @@ _kbusWalkCBMapNextEntries_RmAperture if (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) { - if (pKernelBus->virtualBar2[gfid].pPageLevels != NULL) + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + NvU32 sizeOfEntries; + NvU32 index; + + NV_ASSERT_OR_RETURN_VOID(pKernelBus->virtualBar2[gfid].pPageLevels == NULL); + + surf.pMemDesc = pMemDesc; + surf.offset = entryIndexLo * pLevelFmt->entrySize; + + sizeOfEntries = (entryIndexHi - entryIndexLo + 1) * pLevelFmt->entrySize; + + pMap = memmgrMemBeginTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC); + + for (entryIndex = entryIndexLo; entryIndex <= entryIndexHi; entryIndex++) + { + // Update the PTE with the physical address. + _busWalkCBMapNextEntries_UpdatePhysAddr(pGpu, + &entryValue, + pIter, + pageSize); + + index = (entryIndex - entryIndexLo) * pLevelFmt->entrySize; + portMemCopy(&pMap[index], pLevelFmt->entrySize, + entryValue.v8, pLevelFmt->entrySize); + } + + memmgrMemEndTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC); + } + else if (pKernelBus->virtualBar2[gfid].pPageLevels != NULL) { // // Determine the start of the desired page level offset from @@ -2146,7 +2253,7 @@ kbusUpdateRmAperture_GM107 NvU64 vaLo; NvU64 vaHi; NvU32 gfid; - const NvU32 pageSize = FERMI_SMALL_PAGESIZE; + const NvU64 pageSize = FERMI_SMALL_PAGESIZE; const GMMU_FMT *pFmt; ADDRESS_TRANSLATION addressTranslation; NvBool bCallingContextPlugin; @@ -2224,7 +2331,7 @@ kbusUpdateRmAperture_GM107 { // MMU_MAP_CTX mapTarget.pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, - BIT_IDX_32(pageSize)); + BIT_IDX_64(pageSize)); mapTarget.pIter = &mapIter; mapTarget.MapNextEntries = _kbusWalkCBMapNextEntries_RmAperture; @@ -2371,23 +2478,34 @@ static NV_STATUS _kbusUpdateDebugStatistics(OBJGPU *pGpu) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - OBJVASPACE *pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); + OBJVASPACE *pBar1VAS; OBJEHEAP *pVASHeap; NV00DE_SHARED_DATA *pSharedData = gpushareddataWriteStart(pGpu); NV_RANGE bar1VARange = NV_RANGE_EMPTY; - pVASHeap = vaspaceGetHeap(pBar1VAS); - bar1VARange = rangeMake(vaspaceGetVaStart(pBar1VAS), vaspaceGetVaLimit(pBar1VAS)); + if (!KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_RETURN(pBar1VAS != NULL, NV_ERR_INVALID_STATE); + pVASHeap = vaspaceGetHeap(pBar1VAS); + bar1VARange = rangeMake(vaspaceGetVaStart(pBar1VAS), vaspaceGetVaLimit(pBar1VAS)); - pSharedData->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); - pSharedData->bar1AvailSize = 0; + pSharedData->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); + pSharedData->bar1AvailSize = 0; - if (pVASHeap != NULL) - { - NvU64 freeSize = 0; + if (pVASHeap != NULL) + { + NvU64 freeSize = 0; - pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, NULL, NULL, &freeSize); - pSharedData->bar1AvailSize = (NvU32)(freeSize / 1024); + pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, NULL, NULL, &freeSize); + pSharedData->bar1AvailSize = (NvU32)(freeSize / 1024); + } + } + else + { + // When coherent C2C path is enabled, BAR1 is disabled + pSharedData->bar1Size = 0; + pSharedData->bar1AvailSize = 0; } gpushareddataWriteFinish(pGpu); @@ -2405,7 +2523,7 @@ kbusMapFbAperture_GM107 NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, - NvHandle hClient + Device *pDevice ) { NvBool bBcState = gpumgrGetBcEnabledStatus(pGpu); @@ -2419,8 +2537,6 @@ kbusMapFbAperture_GM107 NV_ASSERT((flags & BUS_MAP_FB_FLAGS_FERMI_INVALID) == 0); - pVAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); - // Set BC to enabled in UC flag not passed if ((IsSLIEnabled(pGpu) && ((flags & BUS_MAP_FB_FLAGS_MAP_UNICAST) == 0)) && ((flags & BUS_MAP_FB_FLAGS_PRE_INIT) == 0)) @@ -2440,9 +2556,14 @@ kbusMapFbAperture_GM107 pLoopGpu = pGpu; pVAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); - rmStatus = _kbusMapAperture_GM107(pGpu, pMemDesc, + if (pVAS == NULL) + { + rmStatus = NV_ERR_GENERIC; + SLI_LOOP_BREAK; + } + rmStatus = _kbusMapAperture_GM107(pGpu, pKernelBus, pMemDesc, pVAS, offset, pAperOffset, - pLength, flags, hClient); + pLength, flags, pDevice); // // Ensure that all returned VA offsets are the same on each GPU @@ -2554,7 +2675,7 @@ kbusUnmapFbAperture_GM107 SLI_LOOP_BREAK; } memdescFlushCpuCaches(pGpu, pMemDesc); - rmStatus = _kbusUnmapAperture_GM107(pGpu, pVAS, pMemDesc, aperOffset); + rmStatus = _kbusUnmapAperture_GM107(pGpu, pKernelBus, pVAS, pMemDesc, aperOffset); if (rmStatus != NV_OK) { @@ -2638,6 +2759,12 @@ kbusFlushSingle_GM107 return NV_OK; } + if (kbusIsBarAccessBlocked(pKernelBus)) + { + // If BAR has been blocked, there's nothing to flush for vidmem + return NV_OK; + } + if (flags & BUS_FLUSH_VIDEO_MEMORY) { // @@ -2745,13 +2872,14 @@ NV_STATUS _kbusMapAperture_GM107 ( OBJGPU *pGpu, + KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, OBJVASPACE *pVAS, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 mapFlags, - NvHandle hClient + Device *pDevice ) { NV_STATUS rmStatus = NV_ERR_GENERIC; @@ -2760,6 +2888,9 @@ _kbusMapAperture_GM107 NvU32 flags = DRF_DEF(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, _FALSE); MEMORY_DESCRIPTOR *pTempMemDesc; NvU32 swizzId = KMIGMGR_SWIZZID_INVALID; + NvU32 gfid; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); // Ensure that the BAR1 VA space is the same across all subdevices if (IsSLIEnabled(pGpu) && ((mapFlags & BUS_MAP_FB_FLAGS_MAP_UNICAST) == 0)) @@ -2768,6 +2899,14 @@ _kbusMapAperture_GM107 gpumgrSetBcEnabledStatus(pGpu, NV_TRUE); } + if (pKernelBus->bar1[gfid].bStaticBar1Enabled && + (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM)) + { + return kbusStaticMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, + offset, pAperOffset, + pLength, gfid); + } + if (mapFlags & BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED) { flags = FLD_SET_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE, flags); @@ -2775,23 +2914,37 @@ _kbusMapAperture_GM107 pDma = GPU_GET_DMA(pGpu); - // - // Valid client handle should be associated with a BAR1 mapping request if SMC memory - // partitioning is enabled. That's because BAR1 VA space is split among SMC partitions. - // - // Internal allocations like RM allocated USERD which require BAR1 mapping are done during RM init - // before SMC is enabled and BAR1 VA space is split. So they should work despite not having - // an associated hClient and also such BAR VA space allocations should happen before BAR1 is split. - // if (IS_MIG_IN_USE(pGpu)) { - MIG_INSTANCE_REF ref; - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + if (pDevice != NULL) + { + MIG_INSTANCE_REF ref; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - NV_ASSERT_OR_RETURN(hClient != NV01_NULL_OBJECT, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, &ref)); - swizzId = ref.pKernelMIGGpuInstance->swizzId; + NV_ASSERT_OR_RETURN(pDevice != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); + swizzId = ref.pKernelMIGGpuInstance->swizzId; + } + else if (pMemDesc->pHeap != NULL) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + KERNEL_MIG_GPU_INSTANCE *pCurrKernelMIGGPUInstance = NULL; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance = NULL; + + FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pCurrKernelMIGGPUInstance) + { + if (pCurrKernelMIGGPUInstance->pMemoryPartitionHeap == pMemDesc->pHeap) + { + pKernelMIGGPUInstance = pCurrKernelMIGGPUInstance; + break; + } + } + FOR_EACH_VALID_GPU_INSTANCE_END(); + + NV_ASSERT_OR_RETURN(pKernelMIGGPUInstance != NULL, NV_ERR_INVALID_STATE); + swizzId = pKernelMIGGPUInstance->swizzId; + } } if (memdescGetCpuCacheAttrib(pMemDesc) == NV_MEMORY_CACHED) @@ -2851,6 +3004,7 @@ NV_STATUS _kbusUnmapAperture_GM107 ( OBJGPU *pGpu, + KernelBus *pKernelBus, OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU64 aperOffset @@ -2858,6 +3012,15 @@ _kbusUnmapAperture_GM107 { NV_STATUS rmStatus = NV_OK; VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); + NvU32 gfid; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + if (pKernelBus->bar1[gfid].bStaticBar1Enabled && + (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM)) + { + return kbusStaticUnmapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, gfid); + } rmStatus = dmaFreeMapping_HAL(pGpu, pDma, pVAS, aperOffset, pMemDesc, 0, NULL); @@ -3335,8 +3498,11 @@ kbusStateDestroy_GM107 // will also use the window at arbitrary locations (eg during an SMI event if (pMemoryManager->Ram.fbAddrSpaceSizeMb) { - offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); - (void)kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); + (void)kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + } } // Unmap BAR0 Writecombined Window @@ -3707,7 +3873,9 @@ NV_STATUS kbusSetBarsApertureSize_GM107 NvU32 gfid ) { - NvU32 data32; + NvU32 data32; + NvU32 maxRmAddressibleBar2SizeMb = pKernelBus->bIsEntireBar2RegionVirtuallyAddressible ? + BUS_BAR2_APERTURE_MB : BUS_BAR2_RM_APERTURE_MB; // // Setup BAR1 aperture size only for GFID_VF @@ -3723,7 +3891,7 @@ NV_STATUS kbusSetBarsApertureSize_GM107 // Check to see if a BAR2 aperture size override has been specified. // if (((NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB, - &data32))) && data32 && data32 <= BUS_BAR2_RM_APERTURE_MB) + &data32))) && data32 && data32 <= maxRmAddressibleBar2SizeMb) { // Set the BAR2 aperture size based on the override pKernelBus->bar2[gfid].rmApertureLimit = (data32 << 20) - 1; @@ -3744,21 +3912,17 @@ NV_STATUS kbusSetBarsApertureSize_GM107 // if ((IS_SIM_MODS(GPU_GET_OS(pGpu)) && IS_SILICON(pGpu) == 0) || (!RMCFG_FEATURE_MODS_FEATURES && IS_SIMULATION(pGpu))) { + // Temporarily increasing the RM aperture size to 16MB - Bug 3317956 + if (gpuIsCCFeatureEnabled(pGpu)) + pKernelBus->bar2[gfid].rmApertureLimit = (BUS_BAR2_RM_APERTURE_MB << 20) - 1; // 16MB + else pKernelBus->bar2[gfid].rmApertureLimit = ((BUS_BAR2_RM_APERTURE_MB >> 1) << 20) - 1; // 8MB pKernelBus->bar2[gfid].cpuVisibleLimit = pKernelBus->bar2[gfid].rmApertureLimit; // No VESA space } else { pKernelBus->bar2[gfid].cpuVisibleLimit = (BUS_BAR2_APERTURE_MB << 20) - 1; - - if (pKernelBus->bIsEntireBar2RegionVirtuallyAddressible) - { - pKernelBus->bar2[gfid].rmApertureLimit = pKernelBus->bar2[gfid].cpuVisibleLimit; - } - else - { - pKernelBus->bar2[gfid].rmApertureLimit = (BUS_BAR2_RM_APERTURE_MB << 20) - 1; - } + pKernelBus->bar2[gfid].rmApertureLimit = (maxRmAddressibleBar2SizeMb << 20) - 1; } } @@ -4284,6 +4448,12 @@ kbusMemAccessBar0Window_GM107 // The following code assumes aperture to be VID_MEM (or that vidmem/sysmem are same). NV_ASSERT(gpuIsUnifiedMemorySpaceEnabled(pGpu) || (addrSpace == ADDR_FBMEM)); + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + NV_ASSERT_FAILED("kbusMemAccessBar0Window_HAL call in coherent path\n"); + return NV_ERR_INVALID_STATE; + } + bar0WindowOrig = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); bar0WindowOffset = physAddr - bar0WindowOrig; @@ -4384,7 +4554,6 @@ kbusMemCopyBar0Window_GM107 NvBool bRead ) { - NV_STATUS ret = NV_ERR_NOT_SUPPORTED; NvLength copied = 0; NvU8 *pSysmemBuf = pSysmem; NvU64 fbCopyOffset = physAddr; @@ -4401,8 +4570,7 @@ kbusMemCopyBar0Window_GM107 NvU8 *pSource = bRead ? pPramin : pSysmemBuf; NvU8 *pDest = bRead ? pSysmemBuf : pPramin; - ret = kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, praminFbBase); - NV_ASSERT_OK(ret); + NV_ASSERT_OK_OR_RETURN(kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, praminFbBase)); // TODO: use MMIO-safe memcopy abstraction if provided portMemCopy(pDest, copySize, pSource, copySize); @@ -4414,7 +4582,7 @@ kbusMemCopyBar0Window_GM107 } while (copied < size); - return ret; + return NV_OK; } /*! @@ -4596,7 +4764,8 @@ kbusBar1InstBlkVasUpdate_GM107 // (Re-)bind instance block so host fetches the new VAS state. // Flush to ensure host sees the latest. // - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); + kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + kbusSendSysmembar(pGpu, pKernelBus); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c index 9a7f381b53..260707d99e 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c @@ -882,7 +882,7 @@ kbusAllocP2PMailboxBar1_GM200 OBJGPU *pParentGpu; NvU64 vaAllocMax; NV_STATUS status = NV_OK; - + VAS_ALLOC_FLAGS flags = {0}; pParentGpu = gpumgrGetParentGPU(pGpu); diff --git a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c index 3be71c4152..2339539833 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,11 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" #include "mem_mgr/vaspace.h" #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" /*! @@ -155,6 +159,7 @@ _kbusCreateNvlinkPeerMapping portMemSet(¶ms, 0, sizeof(params)); params.connectionType = NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK; params.peerId = peerId; + params.bEgmPeer = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES, attributes); params.bUseUuid = NV_FALSE; params.remoteGpuId = pGpu1->gpuId; params.bSpaAccessOnly = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, attributes); @@ -184,7 +189,7 @@ _kbusCreateNvlinkPeerMapping * @param[out] peer0 Peer ID (local to remote) * @param[out] peer1 Peer ID (remote to local) * @param[in] attributes Sepcial attributes for the mapping - * + * * return NV_OK on success */ NV_STATUS @@ -203,6 +208,7 @@ kbusCreateP2PMappingForNvlink_GP100 NvU32 gpu1Instance = gpuGetInstance(pGpu1); NvBool bLoopback = (pGpu0 == pGpu1); NV_STATUS status = NV_OK; + NvBool bEgmPeer = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES, attributes); if (peer0 == NULL || peer1 == NULL) { @@ -212,7 +218,7 @@ kbusCreateP2PMappingForNvlink_GP100 // Set the default RM mapping if peer id's are not explicitly provided if (*peer0 == BUS_INVALID_PEER || *peer1 == BUS_INVALID_PEER) { - if (bLoopback) + if (bLoopback && !bEgmPeer) { if (pKernelBus0->p2pMapSpecifyId) { @@ -222,22 +228,33 @@ kbusCreateP2PMappingForNvlink_GP100 { // If no static mapping is found, set peer id as 0 for loopback *peer0 = *peer1 = 0; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pGpu0, pKernelBus0, NVBIT(0))); } + } else { // Get the peer ID pGpu0 should use for P2P over NVLINK to pGpu1 if ((status = kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, - peer0)) != NV_OK) + peer0, attributes)) != NV_OK) { return status; } + // EGM loopback + if (bLoopback) + { + // The loopback check here becomes true only in the EGM case + NV_ASSERT_OR_RETURN(bEgmPeer, NV_ERR_INVALID_STATE); + *peer1 = *peer0; + } + else // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 if ((status = kbusGetNvlinkP2PPeerId_HAL(pGpu1, pKernelBus1, pGpu0, pKernelBus0, - peer1)) != NV_OK) + peer1, attributes)) != NV_OK) { return status; } @@ -251,6 +268,11 @@ kbusCreateP2PMappingForNvlink_GP100 NV_PRINTF(LEVEL_INFO, "- P2P: Using Default RM mapping for P2P.\n"); } + + if (bEgmPeer) + { + NV_PRINTF(LEVEL_INFO, "EGM peer\n"); + } // // Does the mapping already exist between the given pair of GPUs using the peerIDs // *peer0 and *peer1 respectively ? @@ -295,7 +317,7 @@ kbusCreateP2PMappingForNvlink_GP100 // // If we're in loopback mode check for specified peer ID arg from RM or MODS - if (bLoopback && pKernelBus0->p2pMapSpecifyId) + if (!bEgmPeer && bLoopback && pKernelBus0->p2pMapSpecifyId) { if ((pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[pKernelBus0->p2pMapPeerId] == 0) && (pKernelBus1->p2p.busNvlinkMappingRefcountPerPeerId[pKernelBus1->p2pMapPeerId] == 0)) @@ -452,7 +474,20 @@ _kbusRemoveNvlinkPeerMapping // If mapping refcount to remote GPU1 is 0, this implies the peerID is no // longer used for P2P from GPU0 to GPU1. Update busNvlinkPeerNumberMask // - if (pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst] == 0) + // Special case: + // Peers connected through NvSwitch in which case all the peers use + // peer id 0 and the refcount for peer id 0 wouldn't reach 0 until + // P2P between all the peers is destroyed. + // busNvlinkMappingRefcountPerGpu == 0 check is done in this case to remove + // the peer id from busNvlinkPeerNumberMask[peerGpuInst] + // Two peer ids are used to reach the same GPU, one for HBM and one for + // EGM. In that case busNvlinkMappingRefcountPerGpu isn't going to + // reach 0 until both the peer ids are removed. In this case, + // busNvlinkMappingRefcountPerPeerId[peerId] == 0 check is required to + // remove the peer id from busNvlinkPeerNumberMask[peerGpuInst]. + // + if (pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst] == 0 || + pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId] == 0) { NV_PRINTF(LEVEL_INFO, "Removing mapping for GPU%u peer %u (GPU%u)\n", @@ -754,7 +789,8 @@ kbusGetNvlinkP2PPeerId_GP100 KernelBus *pKernelBus0, OBJGPU *pGpu1, KernelBus *pKernelBus1, - NvU32 *nvlinkPeer + NvU32 *nvlinkPeer, + NvU32 attributes ) { KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); @@ -870,6 +906,7 @@ kbusUnreserveP2PPeerIds_GP100 return NV_ERR_IN_USE; } + pKernelBus->p2p.bEgmPeer[peerId] = NV_FALSE; pKernelBus->p2pPcie.busPeer[peerId].bReserved = NV_FALSE; } FOR_EACH_INDEX_IN_MASK_END; diff --git a/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c b/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c index 05807cfb78..4203346082 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c @@ -50,12 +50,12 @@ kbusGetUnusedPciePeerId_TU102 PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING))) { // - // Get the mask of NvLink peerIds, to exclude them from the + // Get the mask of NvLink peerIds, to exclude them from the // peerIds PCIE P2P is using. // Pre-Ampere GPUs use a static peerId assignment reserved in - // busGetNvlinkP2PPeerId_GP100() and we need to make sure the - // PCIE and nvLink P2P assignments do not collide. - // Make this Windows + Turing only until bug 3471679 is fixed. + // busGetNvlinkP2PPeerId_GP100() and we need to make sure the + // PCIE and nvLink P2P assignments do not collide. + // Make this Windows + Turing only until bug 3471679 is fixed. // nvlinkIdMask = knvlinkGetUniquePeerIdMask_HAL(pGpu, pKernelNvlink); } @@ -63,7 +63,7 @@ kbusGetUnusedPciePeerId_TU102 for (peerId = 0; peerId < pKernelBus->numPeers; peerId++) { if ((pKernelBus->p2pPcie.busPeer[peerId].refCount == 0) && - (!pKernelBus->p2pPcie.busPeer[peerId].bReserved) && + (!pKernelBus->p2pPcie.busPeer[peerId].bReserved) && ((BIT(peerId) & nvlinkIdMask) == 0)) { return peerId; diff --git a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c index bb11707773..1d9b2bee3c 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c @@ -50,13 +50,15 @@ kbusSetupCpuPointerForBusFlush_GV100 { NV_STATUS status = NV_OK; - // Nothing to be done in paravirtualized guest or if we don't want to do CPU reads for flushing. + // Nothing to be done in paravirtualized guest (or CC) or if we don't want to do CPU reads for flushing. if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || !kbusIsReadCpuPointerToFlushEnabled(pKernelBus)) { return NV_OK; } + NV_ASSERT_OR_RETURN(!kbusIsBarAccessBlocked(pKernelBus), NV_ERR_INVALID_STATE); + status = memdescCreate(&pKernelBus->pFlushMemDesc, pGpu, RM_PAGE_SIZE, RM_PAGE_SIZE, @@ -212,7 +214,7 @@ kbusUnmapCoherentCpuMapping_GV100 } // Flush the memory since caller writes to the FB - kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BUS_FLUSH_VIDEO_MEMORY); + kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); return; } diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus.c b/src/nvidia/src/kernel/gpu/bus/kern_bus.c index 26f0caa6aa..24e28d7397 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus.c @@ -393,7 +393,9 @@ kbusCommitBar2_KERNEL NvU32 flags ) { - if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu) && + !kbusIsBarAccessBlocked(pKernelBus) && + !(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) { // we will initialize bar2 to the default big page size of the system NV_ASSERT_OK_OR_RETURN(kbusInitVirtualBar2_HAL(pGpu, pKernelBus)); @@ -717,10 +719,14 @@ kbusPatchBar2Pdb_GSPCLIENT KernelBus *pKernelBus ) { - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; PMEMORY_DESCRIPTOR pMemDesc; - GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + const MMU_FMT_LEVEL *pRootFmt = pKernelBus->bar2[GPU_GFID_PF].pFmt->pRoot; NvU64 entryValue; + MEMORY_DESCRIPTOR *pOldPdb; + + pOldPdb = pKernelBus->virtualBar2[GPU_GFID_PF].pPDB; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescCreate(&pMemDesc, pGpu, pKernelBus->bar2[GPU_GFID_PF].pageDirSize, RM_PAGE_SIZE, NV_TRUE, @@ -733,16 +739,32 @@ kbusPatchBar2Pdb_GSPCLIENT // // BAR2 page table is not yet working at this point, so retrieving the - // PDE3[0] of BAR2 page table via BAR0_WINDOW + // PDE3[0] of BAR2 page table via BAR0_WINDOW or GSP-DMA (in case BARs + // are blocked) // - entryValue = GPU_REG_RD32(pGpu, (NvU32)pKernelBus->bar2[GPU_GFID_PF].bar2OffsetInBar0Window) | + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + + surf.pMemDesc = pOldPdb; + surf.offset = 0; + + NV_ASSERT_OK_OR_RETURN( + memmgrMemRead(pMemoryManager, &surf, &entryValue, + pRootFmt->entrySize, TRANSFER_FLAGS_NONE)); + } + else + { + entryValue = GPU_REG_RD32(pGpu, (NvU32)pKernelBus->bar2[GPU_GFID_PF].bar2OffsetInBar0Window) | ((NvU64)GPU_REG_RD32(pGpu, (NvU32)pKernelBus->bar2[GPU_GFID_PF].bar2OffsetInBar0Window + 4) << 32); + } // // Provide the PDE3[0] value to GSP-RM so that GSP-RM can merge CPU-RM's // page table to GSP-RM's page table // - NV_RM_RPC_UPDATE_BAR_PDE(pGpu, NV_RPC_UPDATE_PDE_BAR_2, entryValue, pKernelBus->bar2[GPU_GFID_PF].pFmt->pRoot->virtAddrBitLo, status); + NV_RM_RPC_UPDATE_BAR_PDE(pGpu, NV_RPC_UPDATE_PDE_BAR_2, entryValue, pRootFmt->virtAddrBitLo, status); return NV_OK; } @@ -951,7 +973,7 @@ kbusGetDeviceCaps_IMPL bExplicitCacheFlushRequired = NVCPU_IS_ARM && (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_MODS_UNIX); if (bExplicitCacheFlushRequired || - (!pCl->getProperty(pCL, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT))) + (!pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT))) RMCTRL_SET_CAP(tempCaps, NV0080_CTRL_HOST_CAPS, _EXPLICIT_CACHE_FLUSH_REQD); if ((pCl->FHBBusInfo.vendorID == PCI_VENDOR_ID_NVIDIA) && @@ -1019,7 +1041,8 @@ kbusMapFbApertureByHandle_IMPL NvHandle hMemory, NvU64 offset, NvU64 size, - NvU64 *pBar1Va + NvU64 *pBar1Va, + Device *pDevice ) { NV_STATUS status; @@ -1053,7 +1076,7 @@ kbusMapFbApertureByHandle_IMPL status = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, offset, &fbApertureOffset, &fbApertureLength, - BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient); + BUS_MAP_FB_FLAGS_MAP_UNICAST, pDevice); if (status != NV_OK) { return status; @@ -1185,9 +1208,16 @@ kbusGetNvlinkP2PPeerId_VGPU KernelBus *pKernelBus0, OBJGPU *pGpu1, KernelBus *pKernelBus1, - NvU32 *nvlinkPeer + NvU32 *nvlinkPeer, + NvU32 flags ) { + *nvlinkPeer = kbusGetPeerId_HAL(pGpu0, pKernelBus0, pGpu1); + if (*nvlinkPeer != BUS_INVALID_PEER) + { + return NV_OK; + } + *nvlinkPeer = kbusGetUnusedPeerId_HAL(pGpu0, pKernelBus0); // If could not find a free peer ID, return error @@ -1218,3 +1248,12 @@ kbusIsGpuP2pAlive_IMPL { return (pKernelBus->totalP2pObjectsAliveRefCount > 0); } + +/** + * @brief Setup VF BAR2 during hibernate resume + * + * @param[in] pGpu + * @param[in] pKernelBus + * @param[in] flags + */ + diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c index 5f484c1674..5eeb27dd5b 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c @@ -83,8 +83,8 @@ _kbusGetHostCaps(OBJGPU *pGpu, NvU8 *pHostCaps) static NV_STATUS _getAspmL1FlagsSendRpc ( - OBJGPU *pGpu, - NvBool *bCyaMaskL1, + OBJGPU *pGpu, + NvBool *bCyaMaskL1, NvBool *bEnableAspmDtL1 ) { diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c index 1434691326..3360e17058 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -384,7 +384,7 @@ kbusInitVirtualBar2_VBAR2 pMemDesc = pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc; - if (KBUS_BAR2_TUNNELLED(pKernelBus)) + if (KBUS_BAR2_TUNNELLED(pKernelBus) || kbusIsBarAccessBlocked(pKernelBus)) { return NV_OK; } @@ -441,7 +441,7 @@ kbusPreInitVirtualBar2_VBAR2 pMemDesc = pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap; - if (KBUS_BAR2_TUNNELLED(pKernelBus)) + if (KBUS_BAR2_TUNNELLED(pKernelBus) || kbusIsBarAccessBlocked(pKernelBus)) { return NV_OK; } @@ -897,6 +897,18 @@ kbusMapBar2Aperture_VBAR2 NvU32 flags ) { + // + // Fail the mapping when BAR2 access to CPR vidmem is blocked (for HCC) + // It is however legal to allow non-CPR vidmem to be mapped to BAR2 + // + if (kbusIsBarAccessBlocked(pKernelBus) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)) + { + os_dump_stack(); + NV_PRINTF(LEVEL_ERROR, "Cannot map/unmap CPR vidmem into/from BAR2\n"); + return NULL; + } + if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) { // @@ -976,7 +988,7 @@ kbusUnmapBar2ApertureWithFlags_SCRATCH ) { portMemFree(*pCpuPtr); - kbusFlush_HAL(pGpu, pKernelBus, kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pMemDesc))); + kbusFlush_HAL(pGpu, pKernelBus, kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pMemDesc)) | BUS_FLUSH_USE_PCIE_READ); } /*! @@ -1006,6 +1018,18 @@ kbusUnmapBar2ApertureWithFlags_VBAR2 NvU32 flags ) { + // + // Fail the mapping when BAR2 access to CPR vidmem is blocked (for HCC) + // It is however legal to allow non-CPR vidmem to be mapped to BAR2 + // + if (kbusIsBarAccessBlocked(pKernelBus) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)) + { + NV_ASSERT(0); + NV_PRINTF(LEVEL_ERROR, "Cannot map/unmap CPR vidmem into/from BAR2\n"); + return; + } + // // Free the dummy data we allocated for handling a reset GPU. // Let a map created before the reset go through the normal path diff --git a/src/nvidia/src/kernel/gpu/bus/p2p.c b/src/nvidia/src/kernel/gpu/bus/p2p.c index 20eff5e63d..81eae841ef 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,13 +32,14 @@ #include "mem_mgr/vaspace.h" #include "gpu/bus/third_party_p2p.h" #include "gpu/device/device.h" +#include "rmapi/rs_utils.h" #include "vgpu/rpc.h" #include "vgpu/vgpu_events.h" #include "gpu/bus/kern_bus.h" #include "class/cl503c.h" -static NvBool _isSpaceAvailableForBar1P2PMapping(OBJGPU *, Subdevice *, NvHandle, NvU64); +static NvBool _isSpaceAvailableForBar1P2PMapping(OBJGPU *, Subdevice *, RsClient *, NvU64); static NV_STATUS RmP2PValidateSubDevice @@ -139,7 +140,7 @@ NV_STATUS _createThirdPartyP2PMappingExtent NvU64 address, NvU64 length, NvU64 offset, - NvHandle hClient, + RsClient *pClient, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo, CLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO_LIST *pList, MEMORY_DESCRIPTOR *pMemDesc, @@ -155,14 +156,10 @@ NV_STATUS _createThirdPartyP2PMappingExtent NV_STATUS status; KernelBus *pKernelBus; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfoTmp; - RsClient *pClient; Device *pDevice; NvBool bGpuLockTaken = (rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)) || rmGpuLockIsOwner()); - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_ARGUMENT); - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_STATE); @@ -194,7 +191,7 @@ NV_STATUS _createThirdPartyP2PMappingExtent if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) { - NV_RM_RPC_MAP_MEMORY(pGpu, hClient, + NV_RM_RPC_MAP_MEMORY(pGpu, pClient->hClient, RES_GET_HANDLE(pDevice), pVidmemInfo->hMemory, offset, @@ -216,7 +213,7 @@ NV_STATUS _createThirdPartyP2PMappingExtent &fbApertureOffset, &fbApertureMapLength, BUS_MAP_FB_FLAGS_MAP_UNICAST, - hClient); + pDevice); if (!bGpuLockTaken) { @@ -256,7 +253,7 @@ NV_STATUS _createThirdPartyP2PMappingExtent { if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) { - NV_RM_RPC_UNMAP_MEMORY(pGpu, hClient, + NV_RM_RPC_UNMAP_MEMORY(pGpu, pClient->hClient, RES_GET_HANDLE(pDevice), pVidmemInfo->hMemory, 0, @@ -307,7 +304,6 @@ NV_STATUS _reuseThirdPartyP2PMappingExtent ( NvU64 address, NvU64 length, - NvHandle hClient, CLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO_LIST *pList, MEMORY_DESCRIPTOR *pMemDesc, OBJGPU *pGpu, @@ -353,7 +349,7 @@ NV_STATUS _reuseThirdPartyP2PMappingExtent static NV_STATUS RmThirdPartyP2PMappingFree ( - NvHandle hClient, + RsClient *pClient, OBJGPU *pGpu, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo, PCLI_THIRD_PARTY_P2P_INFO pThirdPartyP2PInfo, @@ -369,7 +365,6 @@ NV_STATUS RmThirdPartyP2PMappingFree NvU64 startOffset; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfo = NULL; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfoNext = NULL; - RsClient *pClient; Device *pDevice; NvBool bGpuLockTaken; NvBool bVgpuRpc; @@ -382,9 +377,6 @@ NV_STATUS RmThirdPartyP2PMappingFree NV_ASSERT_OR_RETURN((pSubDevice != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((pThirdPartyP2PInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_ARGUMENT); - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_STATE); @@ -418,7 +410,7 @@ NV_STATUS RmThirdPartyP2PMappingFree { if (bVgpuRpc) { - NV_RM_RPC_UNMAP_MEMORY(pGpu, hClient, + NV_RM_RPC_UNMAP_MEMORY(pGpu, pClient->hClient, RES_GET_HANDLE(pDevice), pVidmemInfo->hMemory, 0, @@ -469,7 +461,7 @@ NV_STATUS RmThirdPartyP2PBAR1GetPages NvU64 address, NvU64 length, NvU64 offset, - NvHandle hClient, + RsClient *pClient, PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo, NvU64 **ppPhysicalAddresses, NvU32 **ppWreqMbH, @@ -543,7 +535,7 @@ NV_STATUS RmThirdPartyP2PBAR1GetPages if (!bFound) { // Check if there is still space in BAR1 to map this length - if (!_isSpaceAvailableForBar1P2PMapping(pGpu, pSubDevice, hClient, lengthReq)) + if (!_isSpaceAvailableForBar1P2PMapping(pGpu, pSubDevice, pClient, lengthReq)) { NV_PRINTF(LEVEL_ERROR, "no space for BAR1 mappings, length: 0x%llx \n", lengthReq); @@ -554,7 +546,7 @@ NV_STATUS RmThirdPartyP2PBAR1GetPages pMemDesc = pVidmemInfo->pMemDesc; status = _createThirdPartyP2PMappingExtent( - address, lengthReq, offset, hClient, + address, lengthReq, offset, pClient, pVidmemInfo, &pVidmemInfo->mappingExtentList, pMemDesc, pGpu, pSubDevice, &pExtentInfo, @@ -568,10 +560,8 @@ NV_STATUS RmThirdPartyP2PBAR1GetPages { pMemDesc = pExtentInfo->pMemDesc; status = _reuseThirdPartyP2PMappingExtent( - address, lengthReq, hClient, - &pVidmemInfo->mappingExtentList, pMemDesc, pGpu, - pSubDevice, &pExtentInfo, - &mappingOffset, &mappingLength); + address, lengthReq, &pVidmemInfo->mappingExtentList, pMemDesc, + pGpu, pSubDevice, &pExtentInfo, &mappingOffset, &mappingLength); if (NV_OK != status) { goto out; @@ -611,7 +601,7 @@ NV_STATUS RmThirdPartyP2PBAR1GetPages out: if (status != NV_OK) { - RmThirdPartyP2PMappingFree(hClient, pGpu, pVidmemInfo, pThirdPartyP2PInfo, + RmThirdPartyP2PMappingFree(pClient, pGpu, pVidmemInfo, pThirdPartyP2PInfo, pSubDevice, pMappingInfo); } return status; @@ -624,7 +614,6 @@ static NV_STATUS RmThirdPartyP2PNVLinkGetPages ( OBJGPU *pGpu, - OBJVASPACE *pVAS, NvU64 address, NvU64 length, NvU64 offset, @@ -647,10 +636,13 @@ NV_STATUS RmThirdPartyP2PNVLinkGetPages lastAddress = (address + length - 1); while (address < lastAddress) { - physAddr = memdescGetPhysAddr(pMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), offset); + physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, offset); - (*ppWreqMbH)[entries] = 0; - (*ppRreqMbH)[entries] = 0; + if ((ppWreqMbH != NULL) && (ppRreqMbH != NULL)) + { + (*ppWreqMbH)[entries] = 0; + (*ppRreqMbH)[entries] = 0; + } (*ppPhysicalAddresses)[entries] = pKernelMemorySystem->coherentCpuFbBase + physAddr; @@ -673,8 +665,7 @@ NV_STATUS RmP2PGetPagesUsingVidmemInfo NvU64 address, NvU64 length, NvU64 offset, - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvU64 **ppPhysicalAddresses, NvU32 **ppWreqMbH, NvU32 **ppRreqMbH, @@ -691,33 +682,17 @@ NV_STATUS RmP2PGetPagesUsingVidmemInfo { NV_STATUS status; MEMORY_DESCRIPTOR *pMemDesc; - Device *pDevice; - RsClient *pClient; - OBJVASPACE *pVAS; + RsClient *pClient = RES_GET_CLIENT(pThirdPartyP2P); CLI_THIRD_PARTY_P2P_MAPPING_INFO *pMappingInfo = NULL; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_ARGUMENT); - - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_STATE); - - if (pVASpaceInfo != NULL) - { - NV_ASSERT_OK_OR_RETURN( - vaspaceGetByHandleOrDeviceDefault(pClient, RES_GET_HANDLE(pDevice), - pVASpaceInfo->hVASpace, &pVAS)); - } - pMemDesc = pVidmemInfo->pMemDesc; - status = CliGetThirdPartyP2PMappingInfoFromKey(hClient, - hThirdPartyP2P, pVidmemInfo->hMemory, - pPlatformData, &pMappingInfo); + status = CliGetThirdPartyP2PMappingInfoFromKey(pThirdPartyP2P, + pVidmemInfo->hMemory, pPlatformData, &pMappingInfo); if (status == NV_ERR_OBJECT_NOT_FOUND) { - status = CliAddThirdPartyP2PMappingInfo(hClient, hThirdPartyP2P, - pVidmemInfo->hMemory, pPlatformData, pFreeCallback, pData, &pMappingInfo); + status = CliAddThirdPartyP2PMappingInfo(pThirdPartyP2P, pVidmemInfo->hMemory, + pPlatformData, pFreeCallback, pData, &pMappingInfo); } if (status != NV_OK) { @@ -727,14 +702,14 @@ NV_STATUS RmP2PGetPagesUsingVidmemInfo switch(pThirdPartyP2PInfo->type) { case CLI_THIRD_PARTY_P2P_TYPE_BAR1: - status = RmThirdPartyP2PBAR1GetPages(address, length, offset, hClient, + status = RmThirdPartyP2PBAR1GetPages(address, length, offset, pClient, pVidmemInfo, ppPhysicalAddresses, ppWreqMbH, ppRreqMbH, pEntries, pGpu, pSubDevice, pMappingInfo, pThirdPartyP2PInfo); break; case CLI_THIRD_PARTY_P2P_TYPE_NVLINK: - status = RmThirdPartyP2PNVLinkGetPages(pGpu, pVAS, address, length, + status = RmThirdPartyP2PNVLinkGetPages(pGpu, address, length, offset, pMemDesc, ppWreqMbH, ppRreqMbH, ppPhysicalAddresses, pEntries); @@ -756,19 +731,18 @@ NV_STATUS RmP2PGetPagesUsingVidmemInfo static NV_STATUS RmP2PValidateAddressRangeOrGetPages ( - NvU64 address, - NvU64 length, - NvHandle hClient, - NvHandle hThirdPartyP2P, - NvU64 **ppPhysicalAddresses, - NvU32 **ppWreqMbH, - NvU32 **ppRreqMbH, - NvU32 *pEntries, - void *pPlatformData, - void (*pFreeCallback)(void *pData), - void *pData, - OBJGPU *pGpu, - Subdevice *pSubDevice, + NvU64 address, + NvU64 length, + ThirdPartyP2P *pThirdPartyP2P, + NvU64 **ppPhysicalAddresses, + NvU32 **ppWreqMbH, + NvU32 **ppRreqMbH, + NvU32 *pEntries, + void *pPlatformData, + void (*pFreeCallback)(void *pData), + void *pData, + OBJGPU *pGpu, + Subdevice *pSubDevice, PCLI_THIRD_PARTY_P2P_VASPACE_INFO pVASpaceInfo, PCLI_THIRD_PARTY_P2P_INFO pThirdPartyP2PInfo ) @@ -777,9 +751,8 @@ NV_STATUS RmP2PValidateAddressRangeOrGetPages NV_STATUS status; NvU64 offset; - status = CliGetThirdPartyP2PVidmemInfoFromAddress(hClient, - hThirdPartyP2P, address, length, &offset, - &pVidmemInfo); + status = CliGetThirdPartyP2PVidmemInfoFromAddress(pThirdPartyP2P, + address, length, &offset, &pVidmemInfo); if (status != NV_OK) { return status; @@ -791,10 +764,9 @@ NV_STATUS RmP2PValidateAddressRangeOrGetPages return NV_OK; } - status = RmP2PGetPagesUsingVidmemInfo(address, length, offset, hClient, - hThirdPartyP2P, ppPhysicalAddresses, - ppWreqMbH, ppRreqMbH, pEntries, - pPlatformData, pFreeCallback, + status = RmP2PGetPagesUsingVidmemInfo(address, length, offset, pThirdPartyP2P, + ppPhysicalAddresses, ppWreqMbH, ppRreqMbH, + pEntries, pPlatformData, pFreeCallback, pData, pGpu, pSubDevice, pVASpaceInfo, pThirdPartyP2PInfo, pVidmemInfo); if (status != NV_OK) @@ -820,12 +792,9 @@ NV_STATUS RmP2PGetVASpaceInfoWithoutToken NV_STATUS status; PCLI_THIRD_PARTY_P2P_VASPACE_INFO pVASpaceInfo = NULL; NvBool bFound = NV_FALSE; - NvHandle hClient, hThirdPartyP2P; Subdevice *pSubdevice; OBJGPU *pGpu; - hClient = pThirdPartyP2P->hClient; - hThirdPartyP2P = pThirdPartyP2P->hThirdPartyP2P; pSubdevice = pThirdPartyP2P->pSubdevice; status = RmP2PValidateSubDevice(pThirdPartyP2P, &pGpu); @@ -856,12 +825,11 @@ NV_STATUS RmP2PGetVASpaceInfoWithoutToken // Passing NULL for arguments to prevent looking up or // updating mapping info in range validation. // - status = RmP2PValidateAddressRangeOrGetPages(address, length, hClient, - hThirdPartyP2P, NULL, NULL, - NULL, NULL, pPlatformData, - pFreeCallback, pData, pGpu, - pSubdevice, pVASpaceInfo, - pThirdPartyP2P); + status = RmP2PValidateAddressRangeOrGetPages(address, length, pThirdPartyP2P, + NULL, NULL, NULL, NULL, + pPlatformData, pFreeCallback, + pData, pGpu, pSubdevice, + pVASpaceInfo, pThirdPartyP2P); if ((NV_OK == status) && bFound) { return NV_ERR_GENERIC; @@ -967,7 +935,7 @@ NV_STATUS RmP2PGetInfoWithoutToken static NvBool _isSpaceAvailableForBar1P2PMapping( OBJGPU *pGpu, Subdevice *pSubDevice, - NvHandle hClient, + RsClient *pClient, NvU64 length ) { @@ -977,7 +945,9 @@ static NvBool _isSpaceAvailableForBar1P2PMapping( NV_STATUS status; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, + GPU_RES_GET_DEVICE(pSubDevice), + &bar1Info); if (status != NV_OK) return NV_FALSE; @@ -1010,7 +980,6 @@ static NV_STATUS _rmP2PGetPages( ) { NV_STATUS status; - NvHandle hClient, hThirdPartyP2P; OBJGPU *pGpu; ThirdPartyP2P *pThirdPartyP2P; Subdevice *pSubdevice; @@ -1038,12 +1007,12 @@ static NV_STATUS _rmP2PGetPages( &pVASpaceInfo, NULL); } + if (status != NV_OK) { return status; } - hClient = pThirdPartyP2P->hClient; - hThirdPartyP2P = pThirdPartyP2P->hThirdPartyP2P; + pSubdevice = pThirdPartyP2P->pSubdevice; if ((pThirdPartyP2P->type == CLI_THIRD_PARTY_P2P_TYPE_PROPRIETARY) && @@ -1074,11 +1043,10 @@ static NV_STATUS _rmP2PGetPages( goto failed; } - status = RmP2PValidateAddressRangeOrGetPages(address, length, hClient, - hThirdPartyP2P, &pPhysicalAddresses, - &pWreqMbH, &pRreqMbH, pEntries, - pPlatformData, pFreeCallback, - pData, pGpu, pSubdevice, + status = RmP2PValidateAddressRangeOrGetPages(address, length, pThirdPartyP2P, + &pPhysicalAddresses, &pWreqMbH, + &pRreqMbH, pEntries, pPlatformData, + pFreeCallback, pData, pGpu, pSubdevice, pVASpaceInfo, pThirdPartyP2P); if (status != NV_OK) { @@ -1132,8 +1100,7 @@ CLI_THIRD_PARTY_P2P_VIDMEM_INFO* _createOrReuseVidmemInfoPersistent // Get user client's ThirdPartyP2P's VidmemInfo // Needed to get user's offset and hMemory // - status = CliGetThirdPartyP2PVidmemInfoFromAddress(pThirdPartyP2P->hClient, - pThirdPartyP2P->hThirdPartyP2P, + status = CliGetThirdPartyP2PVidmemInfoFromAddress(pThirdPartyP2P, address, length, &offset, @@ -1152,8 +1119,7 @@ CLI_THIRD_PARTY_P2P_VIDMEM_INFO* _createOrReuseVidmemInfoPersistent // of the VA. This is because the VA could have been reassigned to another // phys allocation. // - status = CliGetThirdPartyP2PVidmemInfoFromId(pThirdPartyP2PInternal->hClient, - pThirdPartyP2PInternal->hThirdPartyP2P, + status = CliGetThirdPartyP2PVidmemInfoFromId(pThirdPartyP2PInternal, pVidmemInfo->id, &pVidmemInfoInternal); if (status == NV_OK) @@ -1202,8 +1168,7 @@ CLI_THIRD_PARTY_P2P_VIDMEM_INFO* _createOrReuseVidmemInfoPersistent // and length = 1. This is because keyStart and keyEnd for internal // AddressRangeTree should be the user's VidmemInfo ID. // - status = CliAddThirdPartyP2PVidmemInfo(pMemoryManager->hClient, - pThirdPartyP2PInternal->hThirdPartyP2P, + status = CliAddThirdPartyP2PVidmemInfo(pThirdPartyP2PInternal, hMemoryDuped, pVidmemInfo->id, 1, @@ -1215,8 +1180,7 @@ CLI_THIRD_PARTY_P2P_VIDMEM_INFO* _createOrReuseVidmemInfoPersistent } // Fetch the newly added VidmemInfo to return. - status = CliGetThirdPartyP2PVidmemInfoFromId(pThirdPartyP2PInternal->hClient, - pThirdPartyP2PInternal->hThirdPartyP2P, + status = CliGetThirdPartyP2PVidmemInfoFromId(pThirdPartyP2PInternal, pVidmemInfo->id, &pVidmemInfoInternal); if (status != NV_OK) @@ -1245,6 +1209,7 @@ NV_STATUS RmP2PGetPagesPersistent( void *pGpuInfo ) { + RsResourceRef *pResourceRef; OBJGPU *pGpu = (OBJGPU *) pGpuInfo; ThirdPartyP2P *pThirdPartyP2P = NULL; ThirdPartyP2P *pThirdPartyP2PInternal = NULL; @@ -1261,14 +1226,21 @@ NV_STATUS RmP2PGetPagesPersistent( return status; } - status = CliGetThirdPartyP2PInfo(pMemoryManager->hClient, - pMemoryManager->hThirdPartyP2P, - &pThirdPartyP2PInternal); + status = serverutilGetResourceRef(pMemoryManager->hClient, + pMemoryManager->hThirdPartyP2P, + &pResourceRef); if (status != NV_OK) { return status; } + pThirdPartyP2PInternal = dynamicCast(pResourceRef->pResource, ThirdPartyP2P); + + if (status != NV_OK) + { + return NV_ERR_INVALID_OBJECT_HANDLE; + } + pVidmemInfo = _createOrReuseVidmemInfoPersistent(pGpu, address, length, &offset, pThirdPartyP2P, pThirdPartyP2PInternal); @@ -1278,8 +1250,7 @@ NV_STATUS RmP2PGetPagesPersistent( } status = RmP2PGetPagesUsingVidmemInfo(address, length, offset, - pMemoryManager->hClient, - pThirdPartyP2PInternal->hThirdPartyP2P, + pThirdPartyP2PInternal, &pPhysicalAddresses, NULL, NULL, pEntries, pPlatformData, NULL, NULL, pGpu, pThirdPartyP2PInternal->pSubdevice, @@ -1387,6 +1358,7 @@ NV_STATUS RmP2PGetGpuByAddress( // Unsupported configs/platforms for persistent mappings if (IS_MIG_ENABLED(pGpu) || + gpuIsApmFeatureEnabled(pGpu) || IS_VIRTUAL(pGpu) || NVCPU_IS_PPC64LE || pMemoryManager->hThirdPartyP2P == 0) @@ -1409,7 +1381,6 @@ NV_STATUS RmP2PRegisterCallback( ) { NV_STATUS status; - NvHandle hClient, hThirdPartyP2P; ThirdPartyP2P *pThirdPartyP2P; PCLI_THIRD_PARTY_P2P_VASPACE_INFO pVASpaceInfo = NULL; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; @@ -1434,21 +1405,14 @@ NV_STATUS RmP2PRegisterCallback( return status; } - hClient = pThirdPartyP2P->hClient; - hThirdPartyP2P = pThirdPartyP2P->hThirdPartyP2P; - - status = CliGetThirdPartyP2PVidmemInfoFromAddress(hClient, hThirdPartyP2P, - address, length, &offset, - &pVidmemInfo); + status = CliGetThirdPartyP2PVidmemInfoFromAddress(pThirdPartyP2P, address, + length, &offset, &pVidmemInfo); if (status != NV_OK) { return status; } - hClient = pThirdPartyP2P->hClient; - hThirdPartyP2P = pThirdPartyP2P->hThirdPartyP2P; - - return CliRegisterThirdPartyP2PMappingCallback(hClient, hThirdPartyP2P, + return CliRegisterThirdPartyP2PMappingCallback(pThirdPartyP2P, pVidmemInfo->hMemory, pPlatformData, pFreeCallback, pData); diff --git a/src/nvidia/src/kernel/gpu/bus/p2p_api.c b/src/nvidia/src/kernel/gpu/bus/p2p_api.c index 9d7ef9796a..f3296a96cf 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p_api.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p_api.c @@ -26,6 +26,7 @@ #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" #include "gpu/bus/third_party_p2p.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "platform/p2p/p2p_caps.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "nvRmReg.h" @@ -51,6 +52,7 @@ _p2papiReservePeerID P2PApi *pP2PApi, NvU32 *peer1, NvU32 *peer2, + NvBool bEgmPeer, NvBool bSpaAccessOnly ) { @@ -58,17 +60,34 @@ _p2papiReservePeerID NvU32 gpu1Instance = gpuGetInstance(pRemoteGpu); // loopback request - if ((pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice)) + if ( + !bEgmPeer && + (pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice)) { *peer1 = *peer2 = 0; + + // Reserve the peer1 ID for NVLink use + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(*peer1))); } else { - // Check if a peer ID is already allocated for P2P from pLocalGpu to pRemoteGpu - *peer1 = kbusGetPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu); + if (bEgmPeer) + { + // Check if a peer ID is already allocated for P2P from pLocalGpu to pRemoteGpu + *peer1 = kbusGetEgmPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu); - // Check if a peer ID is already allocated for P2P from pRemoteGpu to pLocalGpu - *peer2 = kbusGetPeerId_HAL(pRemoteGpu, pRemoteKernelBus, pLocalGpu); + // Check if a peer ID is already allocated for P2P from pRemoteGpu to pLocalGpu + *peer2 = kbusGetEgmPeerId_HAL(pRemoteGpu, pRemoteKernelBus, pLocalGpu); + } + else + { + // Check if a peer ID is already allocated for P2P from pLocalGpu to pRemoteGpu + *peer1 = kbusGetPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu); + + // Check if a peer ID is already allocated for P2P from pRemoteGpu to pLocalGpu + *peer2 = kbusGetPeerId_HAL(pRemoteGpu, pRemoteKernelBus, pLocalGpu); + } } if (*peer1 != BUS_INVALID_PEER && *peer2 != BUS_INVALID_PEER) @@ -92,20 +111,29 @@ _p2papiReservePeerID NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(*peer1))); - // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 - *peer2 = kbusGetUnusedPeerId_HAL(pRemoteGpu, pRemoteKernelBus); - // If could not find a free peer ID, return error - if (*peer2 == BUS_INVALID_PEER) + if (pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice) { - NV_PRINTF(LEVEL_ERROR, - "GPU%d: peerID not available for NVLink P2P\n", - gpu1Instance); - return NV_ERR_GENERIC; + // The loopback check here becomes true only in the EGM case + NV_ASSERT_OR_RETURN(bEgmPeer, NV_ERR_INVALID_STATE); + *peer2 = *peer1; } + else + { + // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 + *peer2 = kbusGetUnusedPeerId_HAL(pRemoteGpu, pRemoteKernelBus); + // If could not find a free peer ID, return error + if (*peer2 == BUS_INVALID_PEER) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d: peerID not available for NVLink P2P\n", + gpu1Instance); + return NV_ERR_GENERIC; + } - // Reserve the peer ID for NVLink use - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kbusReserveP2PPeerIds_HAL(pRemoteGpu, pRemoteKernelBus, NVBIT(*peer2))); + // Reserve the peer ID for NVLink use + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pRemoteGpu, pRemoteKernelBus, NVBIT(*peer2))); + } } else { @@ -115,6 +143,10 @@ _p2papiReservePeerID } update_mask: + if (bEgmPeer) + { + NV_PRINTF(LEVEL_INFO, "EGM peer\n"); + } // // Does the mapping already exist between the given pair of GPUs using the peerIDs // peer1 and peer2 respectively ? @@ -161,6 +193,9 @@ _p2papiReservePeerID pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] |= NVBIT(*peer1); pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] |= NVBIT(*peer2); + pLocalKernelBus->p2p.bEgmPeer[*peer1] = bEgmPeer; + pRemoteKernelBus->p2p.bEgmPeer[*peer2] = bEgmPeer; + // // Increment the mapping refcount per peerID - since there is a new mapping that // will use this peerID @@ -186,8 +221,16 @@ _p2papiReservePeerID gpu0Instance, *peer1, gpu1Instance, *peer2); update_params: - pNv503bAllocParams->subDevicePeerIdMask = NVBIT(*peer1); - pNv503bAllocParams->peerSubDevicePeerIdMask = NVBIT(*peer2); + if (bEgmPeer) + { + pNv503bAllocParams->subDeviceEgmPeerIdMask = NVBIT(*peer1); + pNv503bAllocParams->peerSubDeviceEgmPeerIdMask = NVBIT(*peer2); + } + else + { + pNv503bAllocParams->subDevicePeerIdMask = NVBIT(*peer1); + pNv503bAllocParams->peerSubDevicePeerIdMask = NVBIT(*peer2); + } // Update connection type for SRIOV. pP2PApi->attributes = FLD_SET_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK, pP2PApi->attributes); @@ -204,12 +247,12 @@ p2papiConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - NvHandle hClient; Subdevice *pSubDevice; Subdevice *pPeerSubDevice; NvU32 subDevicePeerIdMask; NvU32 peerSubDevicePeerIdMask; RsClient *pClient; + RmClient *pRmClient; NvU32 peer1; NvU32 peer2; NvHandle hDevice; @@ -234,14 +277,23 @@ p2papiConstruct_IMPL NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *pP2pCapsParams; NvU32 p2pCaps; - hClient = pParams->hClient; subDevicePeerIdMask = pNv503bAllocParams->subDevicePeerIdMask; peerSubDevicePeerIdMask = pNv503bAllocParams->peerSubDevicePeerIdMask; + NvU32 egmPeer1; + NvU32 egmPeer2; + NvU32 subDeviceEgmPeerIdMask; + NvU32 peerSubDeviceEgmPeerIdMask; + NvBool bEgmPeer; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) + subDeviceEgmPeerIdMask = pNv503bAllocParams->subDeviceEgmPeerIdMask; + peerSubDeviceEgmPeerIdMask = pNv503bAllocParams->peerSubDeviceEgmPeerIdMask; + + pRmClient = dynamicCast(pCallContext->pClient, RmClient); + if (pRmClient == NULL) return NV_ERR_INVALID_ARGUMENT; + pClient = staticCast(pRmClient, RsClient); + status = subdeviceGetByHandle(pClient, pNv503bAllocParams->hSubDevice, &pSubDevice); if (status != NV_OK) return NV_ERR_INVALID_ARGUMENT; @@ -266,6 +318,22 @@ p2papiConstruct_IMPL } } + if (pNv503bAllocParams->subDeviceEgmPeerIdMask) + { + if (!ONEBITSET(pNv503bAllocParams->subDeviceEgmPeerIdMask)) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + + if (pNv503bAllocParams->peerSubDeviceEgmPeerIdMask) + { + if (!ONEBITSET(pNv503bAllocParams->peerSubDeviceEgmPeerIdMask)) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + // Ensure any loopback requests match if (pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice) { @@ -273,31 +341,22 @@ p2papiConstruct_IMPL { return NV_ERR_INVALID_ARGUMENT; } + if (pNv503bAllocParams->subDeviceEgmPeerIdMask != pNv503bAllocParams->peerSubDeviceEgmPeerIdMask) + { + return NV_ERR_INVALID_ARGUMENT; + } } - // validate client - if (dynamicCast(pClient, RmClient) == NULL) - return NV_ERR_INVALID_CLIENT; - hSubDevice = RES_GET_HANDLE(pSubDevice); hPeerSubDevice = RES_GET_HANDLE(pPeerSubDevice); // Find the gpu for the subdevices passed to us - if (CliSetSubDeviceContext(hClient, hSubDevice, &hDevice, &pLocalGpu) != NV_OK || - NULL == pLocalGpu) - { - NV_PRINTF(LEVEL_ERROR, "Failed to find GPU for hSubDevice (0x%08x)\n", - hSubDevice); - return NV_ERR_INVALID_ARGUMENT; - } + pLocalGpu = GPU_RES_GET_GPU(pSubDevice); + pRemoteGpu = GPU_RES_GET_GPU(pPeerSubDevice); - if (CliSetSubDeviceContext(hClient, hPeerSubDevice, &hPeerDevice, &pRemoteGpu) != NV_OK || - NULL == pRemoteGpu) - { - NV_PRINTF(LEVEL_ERROR, "Failed to find GPU for hSubDevice (0x%08x)\n", - hPeerSubDevice); - return NV_ERR_INVALID_ARGUMENT; - } + // Get device handles + hDevice = RES_GET_HANDLE(pSubDevice->pDevice); + hPeerDevice = RES_GET_HANDLE(pPeerSubDevice->pDevice); API_GPU_FULL_POWER_SANITY_CHECK(pLocalGpu, NV_TRUE, NV_FALSE); API_GPU_FULL_POWER_SANITY_CHECK(pRemoteGpu, NV_TRUE, NV_FALSE); @@ -329,7 +388,7 @@ p2papiConstruct_IMPL pP2pCapsParams->gpuIds[1] = pRemoteGpu->gpuId; NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, hClient, hClient, + pRmApi->Control(pRmApi, pClient->hClient, pClient->hClient, NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2, pP2pCapsParams, sizeof(*pP2pCapsParams)), portMemFreeStackOrHeap(pP2pCapsParams); @@ -362,7 +421,7 @@ p2papiConstruct_IMPL // // Allocate P2P PCIE Mailbox areas if all of the following conditions occur: // - P2P reads or/and writes are supported - // - The P2P connection is PCIE Mailbox based + // - The P2P connection is PCIE Mailbox based // if ((bP2PWriteCapable || bP2PReadCapable) && @@ -372,7 +431,7 @@ p2papiConstruct_IMPL pNv503bAllocParams->mailboxBar1Addr, pNv503bAllocParams->mailboxTotalSize); NV_ASSERT_OK_OR_RETURN(status); - + status = kbusSetP2PMailboxBar1Area_HAL(pRemoteGpu, pRemoteKernelBus, pNv503bAllocParams->mailboxBar1Addr, pNv503bAllocParams->mailboxTotalSize); @@ -399,6 +458,26 @@ p2papiConstruct_IMPL peer2 = BUS_INVALID_PEER; } + // Process any specific peer id requests for EGM peer 1 + if (subDeviceEgmPeerIdMask) + { + egmPeer1 = BIT_IDX_32(subDeviceEgmPeerIdMask); + } + else + { + egmPeer1 = BUS_INVALID_PEER; + } + + // Process any specific peer id requests for EGM peer 2 + if (peerSubDeviceEgmPeerIdMask) + { + egmPeer2 = BIT_IDX_32(peerSubDeviceEgmPeerIdMask); + } + else + { + egmPeer2 = BUS_INVALID_PEER; + } + if (!IS_VIRTUAL(pLocalGpu)) { if (!(bP2PWriteCapable || bP2PReadCapable)) @@ -466,14 +545,60 @@ p2papiConstruct_IMPL pP2PApi->attributes = DRF_NUM(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, p2pConnectionType); pP2PApi->attributes |= bSpaAccessOnly ? DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA) : DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _GPA); + bEgmPeer = (!bSpaAccessOnly && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pLocalGpu)) && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pRemoteGpu))); + if (bSpaAccessOnly && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pLocalGpu)) && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pRemoteGpu))) + { + NV_PRINTF(LEVEL_INFO, "EGM P2P not setup because of SPA only P2P flag!\n"); + } + + // Set the default Bar1 P2P DMA Info + pNv503bAllocParams->l2pBar1P2PDmaInfo.dma_address = \ + pNv503bAllocParams->p2lBar1P2PDmaInfo.dma_address = NV_U64_MAX; + pNv503bAllocParams->l2pBar1P2PDmaInfo.dma_size = \ + pNv503bAllocParams->p2lBar1P2PDmaInfo.dma_size = 0; if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pLocalGpu) || !IS_VIRTUAL(pLocalGpu)) { + // + // TODO: This function need to have a cleanup path when this function + // fails after kbusCreateP2PMaping(), busBindLocalGfidForP2P() + // and busBindRemoteGfidForP2P(). The current state, the + // function just returns an error. Bug 4016670 filed to track + // the effort. + // + // setup the p2p resources NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kbusCreateP2PMapping_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu, pRemoteKernelBus, &peer1, &peer2, pP2PApi->attributes)); + if (bEgmPeer) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusCreateP2PMapping_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu, + pRemoteKernelBus, &egmPeer1, &egmPeer2, + pP2PApi->attributes | + DRF_DEF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES))); + } + + if (p2pConnectionType == P2P_CONNECTIVITY_PCIE_BAR1) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusGetBar1P2PDmaInfo_HAL(pLocalGpu, pRemoteGpu, + pRemoteKernelBus, + &pNv503bAllocParams->l2pBar1P2PDmaInfo.dma_address, + &pNv503bAllocParams->l2pBar1P2PDmaInfo.dma_size)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusGetBar1P2PDmaInfo_HAL(pRemoteGpu, pLocalGpu, + pLocalKernelBus, + &pNv503bAllocParams->p2lBar1P2PDmaInfo.dma_address, + &pNv503bAllocParams->p2lBar1P2PDmaInfo.dma_size)); + } } pGpu = pLocalGpu; @@ -485,11 +610,20 @@ p2papiConstruct_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _p2papiReservePeerID(pLocalGpu, pLocalKernelBus, pRemoteGpu, pRemoteKernelBus, pNv503bAllocParams, pP2PApi, - &peer1, &peer2, bSpaAccessOnly)); + &peer1, &peer2, NV_FALSE, bSpaAccessOnly)); + if (bEgmPeer) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _p2papiReservePeerID(pLocalGpu, pLocalKernelBus, pRemoteGpu, + pRemoteKernelBus, pNv503bAllocParams, pP2PApi, + &egmPeer1, &egmPeer2, NV_TRUE, bSpaAccessOnly)); + } } pP2PApi->peerId1 = peer1; pP2PApi->peerId2 = peer2; + pP2PApi->egmPeerId1 = egmPeer1; + pP2PApi->egmPeerId2 = egmPeer2; pP2PApi->localGfid = GPU_GFID_PF; pP2PApi->remoteGfid = GPU_GFID_PF; @@ -501,6 +635,7 @@ p2papiConstruct_IMPL pParams->hResource, pParams->externalClassId, pNv503bAllocParams, + sizeof(*pNv503bAllocParams), status); if (status != NV_OK) return status; @@ -541,7 +676,7 @@ p2papiConstruct_IMPL { NV_ASSERT_OK_OR_RETURN(refAddDependant(RES_GET_REF(pPeerSubDevice), pCallContext->pResourceRef)); } - + if (status == NV_OK) { NV_CHECK_OR_RETURN(LEVEL_ERROR, pLocalKernelBus->totalP2pObjectsAliveRefCount < NV_U32_MAX, NV_ERR_INSUFFICIENT_RESOURCES); @@ -594,10 +729,21 @@ p2papiDestruct_IMPL if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pLocalGpu) || !IS_VIRTUAL(pLocalGpu)) { // remove any resources associated with this mapping - status = kbusRemoveP2PMapping_HAL(pLocalGpu, pLocalKernelBus, - pRemoteGpu, pRemoteKernelBus, - pP2PApi->peerId1, pP2PApi->peerId2, - pP2PApi->attributes); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kbusRemoveP2PMapping_HAL(pLocalGpu, pLocalKernelBus, + pRemoteGpu, pRemoteKernelBus, + pP2PApi->peerId1, pP2PApi->peerId2, + pP2PApi->attributes), end); + if (!FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, pP2PApi->attributes) && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pLocalGpu)) && + memmgrIsLocalEgmEnabled(GPU_GET_MEMORY_MANAGER(pRemoteGpu))) + { + status = kbusRemoveP2PMapping_HAL(pLocalGpu, pLocalKernelBus, + pRemoteGpu, pRemoteKernelBus, + pP2PApi->egmPeerId1, pP2PApi->egmPeerId2, + pP2PApi->attributes | + DRF_DEF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES)); + } } pP2PApi->peer1 = NULL; diff --git a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c index 8f30aa6ff6..fc5a83255d 100644 --- a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c @@ -223,29 +223,6 @@ thirdpartyp2pDestruct_IMPL pParams->status = status; } -NV_STATUS CliGetThirdPartyP2PInfo -( - NvHandle hClient, - NvHandle hThirdPartyP2P, - ThirdPartyP2P **ppThirdPartyP2P -) -{ - RsResourceRef *pThirdPartyP2PRef; - RsClient *pRsClient; - NV_ASSERT_OR_RETURN((ppThirdPartyP2P != NULL), NV_ERR_INVALID_ARGUMENT); - - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, hThirdPartyP2P, &pThirdPartyP2PRef)); - *ppThirdPartyP2P = dynamicCast(pThirdPartyP2PRef->pResource, ThirdPartyP2P); - - if (*ppThirdPartyP2P == NULL) - { - return NV_ERR_INVALID_OBJECT_HANDLE; - } - - return NV_OK; -} - NV_STATUS CliGetThirdPartyP2PInfoFromToken ( NvU64 p2pToken, @@ -359,28 +336,18 @@ NV_STATUS CliNextThirdPartyP2PInfoWithPid NV_STATUS CliAddThirdPartyP2PVASpace ( - NvHandle hClient, - NvHandle hThirdPartyP2P, - NvHandle hVASpace, - NvU32 *pVASpaceToken + ThirdPartyP2P *pThirdPartyP2P, + NvHandle hVASpace, + NvU32 *pVASpaceToken ) { - RsClient *pRsClient; - ThirdPartyP2P *pThirdPartyP2P; + NvHandle hThirdPartyP2P = RES_GET_HANDLE(pThirdPartyP2P); + RsClient *pClient = RES_GET_CLIENT(pThirdPartyP2P); CLI_THIRD_PARTY_P2P_VASPACE_INFO vaSpaceInfo; NvU32 vaSpaceToken; - NV_STATUS status; - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); NV_ASSERT_OR_RETURN((pVASpaceToken != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK || pThirdPartyP2P == NULL) - { - return NV_ERR_INVALID_OBJECT; - } - portMemSet(&vaSpaceInfo, 0, sizeof(CLI_THIRD_PARTY_P2P_VASPACE_INFO)); for (vaSpaceToken = 0xfe00; vaSpaceToken < 0xff00; vaSpaceToken++) @@ -393,7 +360,7 @@ NV_STATUS CliAddThirdPartyP2PVASpace return NV_ERR_INSUFFICIENT_RESOURCES; } - vaSpaceInfo.hClient = hClient; + vaSpaceInfo.hClient = pClient->hClient; vaSpaceInfo.hThirdPartyP2P = hThirdPartyP2P; vaSpaceInfo.hVASpace = hVASpace; vaSpaceInfo.vaSpaceToken = vaSpaceToken; @@ -414,8 +381,8 @@ NV_STATUS CliAddThirdPartyP2PVASpace { RsResourceRef *pP2PRef; RsResourceRef *pVASpaceRef; - if ((clientGetResourceRef(pRsClient, hThirdPartyP2P, &pP2PRef) == NV_OK) && - (clientGetResourceRef(pRsClient, hVASpace, &pVASpaceRef) == NV_OK)) + if ((clientGetResourceRef(pClient, hThirdPartyP2P, &pP2PRef) == NV_OK) && + (clientGetResourceRef(pClient, hVASpace, &pVASpaceRef) == NV_OK)) { refAddDependant(pVASpaceRef, pP2PRef); } @@ -499,27 +466,19 @@ NV_STATUS thirdpartyp2pGetVASpaceInfoFromToken_IMPL NV_STATUS CliAddThirdPartyP2PVidmemInfo ( - NvHandle hClient, - NvHandle hThirdPartyP2P, - NvHandle hMemory, - NvU64 address, - NvU64 size, - NvU64 offset, - Memory *pMemory + ThirdPartyP2P *pThirdPartyP2P, + NvHandle hMemory, + NvU64 address, + NvU64 size, + NvU64 offset, + Memory *pMemory ) { NV_STATUS status; - ThirdPartyP2P *pThirdPartyP2P; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; NV_ASSERT_OR_RETURN((pMemory != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - pVidmemInfo = portMemAllocNonPaged(sizeof(CLI_THIRD_PARTY_P2P_VIDMEM_INFO)); if (pVidmemInfo == NULL) { @@ -559,8 +518,8 @@ NV_STATUS CliAddThirdPartyP2PVidmemInfo return status; } - pVidmemInfo->hClient = hClient; - pVidmemInfo->hThirdPartyP2P = hThirdPartyP2P; + pVidmemInfo->hClient = RES_GET_CLIENT_HANDLE(pThirdPartyP2P); + pVidmemInfo->hThirdPartyP2P = RES_GET_HANDLE(pThirdPartyP2P); pVidmemInfo->hMemory = hMemory; pVidmemInfo->pMemDesc = pMemory->pMemDesc; pVidmemInfo->id = portAtomicExIncrementU64(&vidmemInfoId); @@ -644,8 +603,7 @@ NV_STATUS CliDelThirdPartyP2PVidmemInfo NV_STATUS CliGetThirdPartyP2PVidmemInfoFromAddress ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvU64 address, NvU64 length, NvU64 *pOffset, @@ -654,19 +612,11 @@ NV_STATUS CliGetThirdPartyP2PVidmemInfoFromAddress { NV_STATUS status; PNODE pNode; - ThirdPartyP2P *pThirdPartyP2P; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; NV_ASSERT_OR_RETURN((pOffset != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((ppVidmemInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - status = btreeSearch(address, &pNode, pThirdPartyP2P->pAddressRangeTree); if (status != NV_OK) @@ -693,25 +643,16 @@ NV_STATUS CliGetThirdPartyP2PVidmemInfoFromAddress NV_STATUS CliGetThirdPartyP2PVidmemInfoFromId ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvU64 id, CLI_THIRD_PARTY_P2P_VIDMEM_INFO **ppVidmemInfo ) { NV_STATUS status; PNODE pNode; - ThirdPartyP2P *pThirdPartyP2P; NV_ASSERT_OR_RETURN((ppVidmemInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - status = btreeSearch(id, &pNode, pThirdPartyP2P->pAddressRangeTree); if (status != NV_OK) { @@ -725,8 +666,7 @@ NV_STATUS CliGetThirdPartyP2PVidmemInfoFromId NV_STATUS CliRegisterThirdPartyP2PMappingCallback ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvHandle hMemory, void *pKey, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *pFreeCallback, @@ -738,8 +678,8 @@ NV_STATUS CliRegisterThirdPartyP2PMappingCallback NV_ASSERT_OR_RETURN((pFreeCallback != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PMappingInfoFromKey(hClient, hThirdPartyP2P, - hMemory, pKey, &pMappingInfo); + status = CliGetThirdPartyP2PMappingInfoFromKey(pThirdPartyP2P, hMemory, pKey, + &pMappingInfo); if (status != NV_OK) { return status; @@ -755,8 +695,7 @@ NV_STATUS CliRegisterThirdPartyP2PMappingCallback NV_STATUS CliAddThirdPartyP2PMappingInfo ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvHandle hMemory, void *pKey, THIRD_PARTY_P2P_VIDMEM_FREE_CALLBACK *pFreeCallback, @@ -765,20 +704,12 @@ NV_STATUS CliAddThirdPartyP2PMappingInfo ) { NV_STATUS status; - ThirdPartyP2P *pThirdPartyP2P; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; PCLI_THIRD_PARTY_P2P_MAPPING_INFO pMappingInfo; NV_ASSERT_OR_RETURN((pKey != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((ppMappingInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - pVidmemInfo = mapFind(&pThirdPartyP2P->vidmemInfoMap, hMemory); if (pVidmemInfo == NULL) { @@ -814,28 +745,19 @@ NV_STATUS CliAddThirdPartyP2PMappingInfo NV_STATUS CliGetThirdPartyP2PMappingInfoFromKey ( - NvHandle hClient, - NvHandle hThirdPartyP2P, + ThirdPartyP2P *pThirdPartyP2P, NvHandle hMemory, void *pKey, PCLI_THIRD_PARTY_P2P_MAPPING_INFO *ppMappingInfo ) { NV_STATUS status; - ThirdPartyP2P *pThirdPartyP2P; PNODE pNode; PCLI_THIRD_PARTY_P2P_VIDMEM_INFO pVidmemInfo; NV_ASSERT_OR_RETURN((pKey != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((ppMappingInfo != NULL), NV_ERR_INVALID_ARGUMENT); - status = CliGetThirdPartyP2PInfo(hClient, hThirdPartyP2P, - &pThirdPartyP2P); - if (status != NV_OK) - { - return status; - } - pVidmemInfo = mapFind(&pThirdPartyP2P->vidmemInfoMap, hMemory); if (pVidmemInfo == NULL) { @@ -1156,7 +1078,7 @@ CliUnregisterFromThirdPartyP2P return status; } -NV_STATUS +NV_STATUS shrp2pConstruct_IMPL(P2PTokenShare *pP2PTokenShare) { return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c b/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c index fda6b63a8a..e721cf663f 100644 --- a/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c +++ b/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c @@ -37,8 +37,6 @@ thirdpartyp2pCtrlCmdRegisterVaSpace_IMPL NV503C_CTRL_REGISTER_VA_SPACE_PARAMS *pRegisterVaSpaceParams ) { - NvHandle hClient = RES_GET_CLIENT_HANDLE(pThirdPartyP2P); - NvHandle hObject = RES_GET_HANDLE(pThirdPartyP2P); NvU32 vaSpaceToken; NV_STATUS status; OBJGPU *pGpu; @@ -48,8 +46,7 @@ thirdpartyp2pCtrlCmdRegisterVaSpace_IMPL return NV_ERR_INVALID_OBJECT_PARENT; - status = CliAddThirdPartyP2PVASpace(hClient, - hObject, + status = CliAddThirdPartyP2PVASpace(pThirdPartyP2P, pRegisterVaSpaceParams->hVASpace, &vaSpaceToken); if (status == NV_OK) @@ -91,7 +88,6 @@ thirdpartyp2pCtrlCmdRegisterVidmem_IMPL { Memory *pMemory; RsClient *pClient = RES_GET_CLIENT(pThirdPartyP2P); - NvHandle hObject = RES_GET_HANDLE(pThirdPartyP2P); NvHandle hDevice; NvU64 address = pRegisterVidmemParams->address; NvU64 size = pRegisterVidmemParams->size; @@ -138,8 +134,7 @@ thirdpartyp2pCtrlCmdRegisterVidmem_IMPL if (memdescGetSize(pMemory->pMemDesc) < offset + size) return NV_ERR_INVALID_ARGUMENT; - status = CliAddThirdPartyP2PVidmemInfo(pClient->hClient, - hObject, + status = CliAddThirdPartyP2PVidmemInfo(pThirdPartyP2P, pRegisterVidmemParams->hMemory, address, size, @@ -185,7 +180,9 @@ thirdpartyp2pCtrlCmdRegisterPid_IMPL NvU32 pid; NV_STATUS status; - NV_ASSERT_OK_OR_RETURN(serverutilGetClientUnderLock(pRegisterPidParams->hClient, &pClient)); + pClient = serverutilGetClientUnderLock(pRegisterPidParams->hClient); + NV_ASSERT_OR_RETURN(pClient != NULL, NV_ERR_INVALID_CLIENT); + pid = pClient->ProcID; status = CliAddThirdPartyP2PClientPid(hClient, diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c index cd79d3b875..056b4ac9c5 100644 --- a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c @@ -230,7 +230,7 @@ _kccuUnmapAndFreeMemory NvU32 i = 0; NV_STATUS status = NV_OK; NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS params = { 0 }; - + NV_PRINTF(LEVEL_INFO, "KernelCcu: Unmap and free shared buffer\n"); // Internal RM api ctrl call to physical RM to unmap dev & mig shared buffer memdesc @@ -556,7 +556,7 @@ NvU32 kccuCounterBlockSizeGet_IMPL ( OBJGPU *pGpu, KernelCcu *pKernelCcu, - NvBool bDevCounter + NvBool bDevCounter ) { NV_PRINTF(LEVEL_INFO, "KernelCcu: Get counter block size \n"); @@ -583,7 +583,7 @@ NV_STATUS kccuStreamStateSet_IMPL ( OBJGPU *pGpu, KernelCcu *pKernelCcu, - NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams + NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams ) { NV_STATUS status = NV_OK; diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c index a759782fcf..a10a0c03de 100644 --- a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c @@ -82,7 +82,7 @@ _kccuapiMemdescGet { return kccuMemDescGetForShrBufId(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, pMemDesc); } - + // In case of MIG status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); if (status != NV_OK) @@ -175,7 +175,7 @@ kccuapiUnmap_IMPL MEMORY_DESCRIPTOR *pMemDesc = NULL; NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: memdesc unmap\n"); - + status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), pCpuMapping->flags, &bKernel); diff --git a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c index 0cb4ff43ac..a25ab96374 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c @@ -596,7 +596,7 @@ kceMapPceLceForSysmemLinks_GA100 NV_STATUS status = NV_OK; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - + NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS paramsNvlinkMask; NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS *pParamsHshubId = NULL; @@ -1021,7 +1021,7 @@ kceGetGrceSupportedLceMask_GA100 * * @param[in] pGpu OBJGPU pointer * @param[in] pKCe KernelCE pointer - * @param[in] checkGen genX for query + * @param[in] checkGen genX for query */ NvBool kceIsGenXorHigherSupported_GA100 diff --git a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c index ff43b58342..5deb203ede 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,8 @@ #include "published/hopper/gh100/dev_ce.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" +#define NV_CE_INVALID_TOPO_IDX 0xFFFF + // Defines for PCE-LCE mapping algorithm #define NV_CE_MAX_HSHUBS 5 #define NV_CE_LCE_MASK_INIT 0xFFFFFFFF @@ -44,7 +46,103 @@ #define NV_CE_NUM_PCES_NO_LINK_CASE 12 #define NV_CE_MAX_PCE_PER_GRCE 2 - +/* + * Table for setting the PCE2LCE mapping for WAR configs that cannot be implemented + * using the algorithm because the config does not conform to the algorithm's set + * of requirements/assumptions + */ +static NVLINK_CE_AUTO_CONFIG_TABLE nvLinkCeAutoConfigTable_GH100[] = +{ + // + // #systmem #max #peers Symmetric Switch PCE-LCE GRCE exposeCe + // links (links/peer) Config? Config Map Config Mask + + // Default minimal configuration - NOTE: do not add entrys before this + // Default is for CG1 + {0x0, 0x0, 0x0, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x0, 0x0, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + + // Switch cases - Ranger mapping + {0x0, 0x12, 0x1, NV_TRUE, NV_TRUE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + {0x0, 0x6, 0x1, NV_TRUE, NV_TRUE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x6,0x4,0x6,0x4,0x6}, {0x4,0x6}, 0x53}, + // CG4 mapping + {0x0, 0x6, 0x3, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x6, 0x3, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x6, 0x2, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x6, 0x2, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x6, 0x1, NV_TRUE, NV_FALSE, {0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x6, 0x1, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x5, 0x3, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x5, 0x3, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x5, 0x2, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x5, 0x2, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x5, 0x1, NV_TRUE, NV_FALSE, {0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x5, 0x1, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x4, 0x3, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x4, 0x3, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x4, 0x2, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x4, 0x2, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x4, 0x1, NV_TRUE, NV_FALSE, {0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x4, 0x1, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x3, 0x3, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x3, 0x3, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x3, 0x2, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x3, 0x2, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x3, 0x1, NV_TRUE, NV_FALSE, {0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x3, 0x1, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x2, 0x3, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x2, 0x3, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x2, 0x2, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x2, 0x2, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x2, 0x1, NV_TRUE, NV_FALSE, {0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x2, 0x1, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x1, 0x3, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x1, 0x3, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0x8,0x4,0x8,0x4,0x8}, {0x4,0x6}, 0x153}, + {0x0, 0x1, 0x2, NV_TRUE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x1, 0x2, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0x6,0x4,0x6,0x4,0x6, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0x6}, 0x53}, + {0x0, 0x1, 0x1, NV_TRUE, NV_FALSE, {0x4,0xF,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13}, + {0x0, 0x1, 0x1, NV_FALSE, NV_FALSE, {0x4,0x6,0x4,0xF,0x4,0xF,0x4,0xF, + 0x4,0x4,0x4,0xF,0x4,0xF,0x4,0xF}, {0x4,0xF}, 0x13} +}; /*! * @brief Returns the size of the PCE2LCE register array @@ -92,6 +190,63 @@ kceGetNumPceRequired } } +/* + * Look up entry in NVLINK_CE_AUTO_CONFIG_TABLE + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pCe OBJCE pointer + * @param[in] pCurrentTopo NVLINK_TOPOLOGY_INFO pointer + * @param[in] pAutoConfigTable NVLINK_CE_AUTO_CONFIG_TABLE pointer + * @param[in] autoConfigNumEntries NvU32 num entries within pAutoConfigTable + * @param[out] pIdx NvU32 pointer + * @param[out] pExposeCeMask NvU32 pointer + * + * Returns: NV_TRUE if entry is found + * NV_FALSE otheriwse +*/ +NvBool +kceGetAutoConfigTableEntry_GH100 +( + OBJGPU *pGpu, + KernelCE *pKCe, + NVLINK_TOPOLOGY_PARAMS *pCurrentTopo, + NVLINK_CE_AUTO_CONFIG_TABLE *pTable, + NvU32 autoConfigNumEntries, + NvU32 *pIdx, + NvU32 *pExposeCeMask +) +{ + NvU32 i; + + // + // The auto config table entries will only be applicable + // from this function in SHH cases. Rather than + // introduced a new entry in the table to note SHH, + // in order to preserve backwards compatibility this + // function will only attempt to map if we are confirmed + // to be in SHH path. + // + if (!gpuIsSelfHosted(pGpu)) + { + return NV_FALSE; + } + + for (i = 0; i < autoConfigNumEntries; i++) + { + if ((pTable[i].sysmemLinks == pCurrentTopo->sysmemLinks ) && + (pTable[i].maxLinksPerPeer == pCurrentTopo->maxLinksPerPeer) && + (pTable[i].bSymmetric == pCurrentTopo->bSymmetric ) && + (pTable[i].bSwitchConfig == pCurrentTopo->bSwitchConfig ) && + (pTable[i].numPeers == pCurrentTopo->numPeers )) + { + *pIdx = i; + *pExposeCeMask = pTable[i].exposeCeMask; + return NV_TRUE; + } + } + return NV_FALSE; +} + /** * @brief This function returns the pceIndex for a particular link ID * Must always be called with the hshub ID for the calling link ID @@ -695,6 +850,46 @@ kceGetMappings_GH100 NV_STATUS status = NV_OK; NV_STATUS statusC2C = NV_OK; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NvU32 topoIdx = NV_CE_INVALID_TOPO_IDX; + NvBool bEntryExists = NV_FALSE; + NvU32 pce2lceConfigSize1 = kceGetPce2lceConfigSize1_HAL(pKCe); + NvU32 grceConfigSize1 = kceGetGrceConfigSize1_HAL(pKCe); + NvU32 pceIdx, grceIdx; + + // + // In the self hosted case, utilize table entries + // with pre defined mappings. Calling from the parent would result in + // using the incorrect autoconfig table so instead set the necessary + // values here if config is found in the table. + // + if (gpuIsSelfHosted(pGpu) && !(pGpu->getProperty(pGpu, PDB_PROP_GPU_SKIP_TABLE_CE_MAP))) + { + bEntryExists = kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, pTopoParams, nvLinkCeAutoConfigTable_GH100, + NV_ARRAY_ELEMENTS(nvLinkCeAutoConfigTable_GH100), + &topoIdx, pExposeCeMask); + if (bEntryExists) + { + // Since entry exists, fill local variables with the associated table entry + for (pceIdx = 0; pceIdx < pce2lceConfigSize1; pceIdx++) + { + pLocalPceLceMap[pceIdx] = nvLinkCeAutoConfigTable_GH100[topoIdx].pceLceMap[pceIdx]; + } + for (grceIdx = 0; grceIdx < grceConfigSize1; grceIdx++) + { + pLocalGrceMap[grceIdx] = nvLinkCeAutoConfigTable_GH100[topoIdx].grceConfig[grceIdx]; + } + + pTopoParams->maxTopoIdx = topoIdx; + pTopoParams->sysmemLinks = nvLinkCeAutoConfigTable_GH100[topoIdx].sysmemLinks; + pTopoParams->maxLinksPerPeer = nvLinkCeAutoConfigTable_GH100[topoIdx].maxLinksPerPeer; + pTopoParams->numPeers = nvLinkCeAutoConfigTable_GH100[topoIdx].numPeers; + pTopoParams->bSymmetric = nvLinkCeAutoConfigTable_GH100[topoIdx].bSymmetric; + pTopoParams->bSwitchConfig = nvLinkCeAutoConfigTable_GH100[topoIdx].bSwitchConfig; + + return NV_OK; + } + + } //Prepare the per-HSHUB/FBHUB available PCE mask kceGetAvailableHubPceMask(pGpu, pTopoParams); diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c index 419aa7d62d..a6773fa723 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -104,6 +104,7 @@ static void printCaps(OBJGPU *pGpu, KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, PRINT_CAP(_CE_SUPPORTS_NONPIPELINED_BL); PRINT_CAP(_CE_SUPPORTS_PIPELINED_BL); + PRINT_CAP(_CE_CC_SECURE); } void kceGetNvlinkCaps(OBJGPU *pGpu, KernelCE *pKCe, NvU8 *pKCeCaps) @@ -335,7 +336,7 @@ NV_STATUS kceTopLevelPceLceMappingsUpdate_IMPL(OBJGPU *pGpu, KernelCE *pKCe) // Set bUpdateNvlinkPceLce to auto-config status bUpdateNvlinkPceLce = pKCe->bIsAutoConfigEnabled; - if (bUpdateNvlinkPceLce) + if (bUpdateNvlinkPceLce || IS_SILICON(pGpu)) { status = kceGetNvlinkAutoConfigCeValues_HAL(pGpu, pKCe, pceLceMap, grceConfig, &exposeCeMask); diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c index 58d2561fce..63ddca25a8 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c @@ -24,6 +24,7 @@ #include "gpu/ce/kernel_ce_context.h" #include "gpu/ce/kernel_ce_private.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/device/device.h" #include "os/os.h" #include "resserv/rs_client.h" @@ -58,6 +59,16 @@ kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllo { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); NvU32 engineIndex = 0; + RsResourceRef *pDeviceRef; + NV_STATUS status = NV_OK; + Device *pDevice; + + NV_ASSERT_OK_OR_ELSE(status, + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef), + return ENG_INVALID; ); + + pDevice = dynamicCast(pDeviceRef->pResource, Device); NV_ASSERT(pAllocParams); @@ -72,9 +83,8 @@ kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllo MIG_INSTANCE_REF ref; NV_ASSERT_OK( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pCallContext->pClient->hClient, - &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, @@ -158,11 +168,13 @@ kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllo } } - NV_STATUS status = ceIndexFromType(pGpu, pCallContext->pClient->hClient, - RM_ENGINE_TYPE_COPY(engineIndex), &engineIndex); + status = ceIndexFromType(pGpu, pDevice, + RM_ENGINE_TYPE_COPY(engineIndex), &engineIndex); if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "Class %d, CE%d\n", externalClassId, engineIndex); + // confirm that engine is valid + NV_ASSERT_OR_RETURN(GPU_GET_KCE(pGpu, engineIndex), ENG_INVALID); return ENG_CE(engineIndex); } else @@ -179,20 +191,7 @@ kcectxConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - ChannelDescendant *pChannelDescendant = staticCast(pKCeContext, ChannelDescendant); - OBJGPU *pGpu = GPU_RES_GET_GPU(pChannelDescendant); - NvU32 ceIdx = GET_CE_IDX(pChannelDescendant->resourceDesc.engDesc); - - // - // Don't do anything for AMODEL - // - if (IsAMODEL(pGpu)) - { - return NV_OK; - } - - NV_ASSERT_OR_RETURN(GPU_GET_KCE(pGpu, ceIdx), NV_ERR_INVALID_PARAMETER); - + // stub, initialization done in chandesConstruct return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c index 053537d12d..f3b4976555 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c @@ -52,7 +52,7 @@ subdeviceCtrlCmdCeGetCaps_IMPL KernelCE *pKCe; NvU32 ceNumber; NV_STATUS status = NV_OK; - RM_ENGINE_TYPE rmEngineType; + RM_ENGINE_TYPE rmEngineType; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -103,7 +103,8 @@ subdeviceCtrlCmdCeGetCaps_IMPL return status; } - NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), rmEngineType, &ceNumber)); + NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, GPU_RES_GET_DEVICE(pSubdevice), + rmEngineType, &ceNumber)); pKCe = GPU_GET_KCE(pGpu, ceNumber); diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c index f6786cd010..41a94cf8e7 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c @@ -139,7 +139,7 @@ subdeviceCtrlCmdCeGetCapsV2_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvU32 ceNumber; - RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -150,7 +150,9 @@ subdeviceCtrlCmdCeGetCapsV2_IMPL return NV_ERR_NOT_SUPPORTED; } - NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), rmEngineType, &ceNumber)); + NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, + GPU_RES_GET_DEVICE(pSubdevice), + rmEngineType, &ceNumber)); { KernelCE *pKCe = GPU_GET_KCE(pGpu, ceNumber); @@ -177,7 +179,7 @@ subdeviceCtrlCmdCeGetAllCaps_IMPL { RM_API *pRmApi; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); ct_assert(ENG_CE__SIZE_1 <= sizeof(pCeCapsParams->capsTbl) / sizeof(pCeCapsParams->capsTbl[0])); @@ -210,7 +212,7 @@ subdeviceCtrlCmdCeGetAllCaps_IMPL KernelCE *pKCe; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - KCE_ITER_CLIENT_BEGIN(pGpu, pKCe, hClient) + KCE_ITER_DEVICE_BEGIN(pGpu, pKCe, pDevice) if (pKCe->bStubbed) continue; diff --git a/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c b/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c new file mode 100644 index 0000000000..f06f728a55 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c @@ -0,0 +1,239 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * Confidential Compute HALs * + * * + \**************************************************************************/ + +#define NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED + +#include "gpu/conf_compute/conf_compute.h" +#include "published/hopper/gh100/dev_fuse.h" + +/*! + * check if debug mode is enabled. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +NvBool +confComputeIsDebugModeEnabled_GH100 +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NvU32 fuseStat = GPU_REG_RD32(pGpu, NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS); + + return !FLD_TEST_DRF(_FUSE_OPT, _SECURE_GSP_DEBUG_DIS, _DATA, _YES, fuseStat); +} + +/*! + * @brief confComputeIsGpuCcCapable + * Checks if Gpu can handle ConfCompute workloads. + * + * @param[in] pGpu : OBJGPU Pointer + * @param[in] pConfCompute : ConfidentialCompute pointer + */ +NvBool +confComputeIsGpuCcCapable_GH100 +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NvU32 reg; + + if (confComputeIsDebugModeEnabled_HAL(pGpu, pConfCompute)) + { + NV_PRINTF(LEVEL_ERROR, "Not checking if GPU is capable of accepting conf compute workloads\n"); + return NV_TRUE; + } + + reg = GPU_REG_RD32(pGpu, NV_FUSE_SPARE_BIT_0); + if (FLD_TEST_DRF(_FUSE, _SPARE_BIT_0, _DATA, _ENABLE, reg)) + { + if (FLD_TEST_DRF(_FUSE, _SPARE_BIT_1, _DATA, _ENABLE, GPU_REG_RD32(pGpu, NV_FUSE_SPARE_BIT_1)) + && FLD_TEST_DRF(_FUSE, _SPARE_BIT_2, _DATA, _DISABLE, GPU_REG_RD32(pGpu, NV_FUSE_SPARE_BIT_2))) + { + return NV_TRUE; + } + } + return NV_FALSE; +} + +NV_STATUS +confComputeDeriveSecrets_GH100(ConfidentialCompute *pConfCompute, + NvU32 engine) +{ + switch (engine) + { + case MC_ENGINE_IDX_GSP: + // GSP automatically derives these keys so no need for CPU-RM to trigger it. + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_LOCKED_RPC)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_LOCKED_RPC)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_DMA)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_DMA)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT)); + break; + case MC_ENGINE_IDX_SEC2: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_HMAC_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_HMAC_KERN)); + break; + case MC_ENGINE_IDX_CE2: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_H2D_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_D2H_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_H2D_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE0, CC_LKEYID_LCE_D2H_KERN)); + break; + case MC_ENGINE_IDX_CE3: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_H2D_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_D2H_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_H2D_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE1, CC_LKEYID_LCE_D2H_KERN)); + break; + case MC_ENGINE_IDX_CE4: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_H2D_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_D2H_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_H2D_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE2, CC_LKEYID_LCE_D2H_KERN)); + break; + case MC_ENGINE_IDX_CE5: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_H2D_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_D2H_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_H2D_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE3, CC_LKEYID_LCE_D2H_KERN)); + break; + case MC_ENGINE_IDX_CE6: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_H2D_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_D2H_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_H2D_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE4, CC_LKEYID_LCE_D2H_KERN)); + break; + case MC_ENGINE_IDX_CE7: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_H2D_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_D2H_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_H2D_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE5, CC_LKEYID_LCE_D2H_KERN)); + break; + case MC_ENGINE_IDX_CE8: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_H2D_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_D2H_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_H2D_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE6, CC_LKEYID_LCE_D2H_KERN)); + break; + case MC_ENGINE_IDX_CE9: + // TODO (CONFCOMP-1577) + // Add calls to GSP to derive keys and retrieve IV masks. + // IV masks are then placed into the keystore via confComputeKeyStoreDepositIvMask. + + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_H2D_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_D2H_USER)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_H2D_KERN)); + confComputeKeyStoreDeriveKey_HAL(pConfCompute, + CC_GKEYID_GEN(CC_KEYSPACE_LCE7, CC_LKEYID_LCE_D2H_KERN)); + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c b/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c new file mode 100644 index 0000000000..2a9b34618b --- /dev/null +++ b/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c @@ -0,0 +1,599 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED + +#include "kernel/gpu/conf_compute/conf_compute.h" +#include "class/cl2080.h" +#include "libraries/nvport/nvport.h" +#include "kernel/gpu/spdm/libspdm_includes.h" +#include "hal/library/cryptlib.h" + +// +// The keystore holds keys, IV masks, and IVs for the LCE, SEC2, and GSP channels. It owns the channel +// counter for each key and helps prevent IV reuse. The keystore is comprised of key slots. A key +// slot holds either AES (key, IV mask, IV) or HMAC (key, nonce) secrets. Key slots are paired +// so that the even-numbered key slot typically holds the host-to-device secrets and the subsequent +// odd-numbered key slot typically holds the device-to-host secrets. The flow for accessing +// the keystore is: +// +// 1. confComputeKeyStoreInit() +// 2. confComputeKeyStoreGetExportMasterKey() +// a. Caller copies the Export Master Key into the keystore. +// 4. confComputeKeyStoreDeriveKey() as needed. +// a. Caller retrieves IV masks from GSP and calls confComputeKeyStoreDepositIvMask() as needed. +// 5. confComputeKeyStoreClearExportMasterKey() once all keys have been derived. +// 6. confComputeKeyStoreRetrieveVia*() as needed. +// 7. confComputeKeyStoreUpdateKey() as needed. +// 8. confComputeKeyStoreDeinit() at the end of the confidential compute session. +// + +#define CONCAT64(hi, low) ((((NvU64)(hi) << 32)) | ((NvU64)(low))) + +typedef struct cryptoBundle_t +{ + union + { + CC_AES_CRYPTOBUNDLE cryptBundle; + CC_HMAC_CRYPTOBUNDLE hmacBundle; + }; + enum {NO_CHAN_COUNTER, CRYPT_COUNTER, HMAC_COUNTER} type; +} cryptoBundle_t; + +typedef cryptoBundle_t keySlot_t[CC_KEYSPACE_TOTAL_SIZE]; + +static NV_STATUS checkSlot(ConfidentialCompute *pConfCompute, NvU32 slotNumber); +static void incrementChannelCounter(ConfidentialCompute *pConfCompute, NvU32 slotNumber); +static NvU64 getChannelCounter(ConfidentialCompute *pConfCompute, NvU32 slotNumber); +static NV_STATUS getKeyIdLce(KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, + NvU16 *keyId); +static NV_STATUS getKeyIdSec2(KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, + NvU16 *keyId); +static NV_STATUS getKeyspaceLce(KernelChannel *pKernelChannel, NvU16 *keyspace); +static NvU32 getKeySlotFromGlobalKeyId (NvU32 globalKeyId); +static NvU32 getKeyspaceSize(NvU16 keyspace); + +NV_STATUS +confComputeKeyStoreInit_GH100(ConfidentialCompute *pConfCompute) +{ + NvU32 index; + cryptoBundle_t (*keySlotLocalPtr)[]; + + NV_PRINTF(LEVEL_INFO, "Initializing keystore.\n"); + + pConfCompute->m_keySlot = portMemAllocNonPaged((NvLength) sizeof(keySlot_t)); + + if (pConfCompute->m_keySlot == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pConfCompute->m_keySlot, 0, (NvLength) sizeof(keySlot_t)); + + keySlotLocalPtr = pConfCompute->m_keySlot; + + // GSP key slots don't have a channel counter. + for (index = 0; index < CC_KEYSPACE_GSP_SIZE; index++) + { + (*keySlotLocalPtr)[index].type = NO_CHAN_COUNTER; + } + + // SEC2 key slots are a mix of encryption / decryption with channel counter and HMAC. + ct_assert(CC_KEYSPACE_SEC2_SIZE == 4); + + (*keySlotLocalPtr)[index++].type = CRYPT_COUNTER; + (*keySlotLocalPtr)[index++].type = HMAC_COUNTER; + (*keySlotLocalPtr)[index++].type = CRYPT_COUNTER; + (*keySlotLocalPtr)[index++].type = HMAC_COUNTER; + + // The remaining LCE key slots are all encryption / decryption with channel counter. + for (; index < CC_KEYSPACE_TOTAL_SIZE; index++) + { + (*keySlotLocalPtr)[index].type = CRYPT_COUNTER; + } + + return NV_OK; +} + +void +confComputeKeyStoreDeinit_GH100(ConfidentialCompute *pConfCompute) +{ + NV_PRINTF(LEVEL_INFO, "Deinitializing keystore.\n"); + + portMemSet(pConfCompute->m_keySlot, 0, (NvLength) sizeof(keySlot_t)); + confComputeKeyStoreClearExportMasterKey_HAL(pConfCompute); + portMemFree(pConfCompute->m_keySlot); +} + +void +*confComputeKeyStoreGetExportMasterKey_GH100 +( + ConfidentialCompute *pConfCompute +) +{ + return pConfCompute->m_exportMasterKey; +} + +NV_STATUS +confComputeKeyStoreDeriveKey_GH100(ConfidentialCompute *pConfCompute, NvU32 globalKeyId) +{ + NvU32 slotIndex = getKeySlotFromGlobalKeyId(globalKeyId); + cryptoBundle_t (*keySlotLocalPtr)[]; + + keySlotLocalPtr = pConfCompute->m_keySlot; + + NV_PRINTF(LEVEL_INFO, "Deriving key for global key ID %x.\n", globalKeyId); + + if (!libspdm_hkdf_sha256_expand(pConfCompute->m_exportMasterKey, sizeof(pConfCompute->m_exportMasterKey), + (const uint8_t *)(CC_GKEYID_GET_STR(globalKeyId)), + (NvLength)portStringLength(CC_GKEYID_GET_STR(globalKeyId)), + (uint8_t *)(*keySlotLocalPtr)[slotIndex].cryptBundle.key, + sizeof((*keySlotLocalPtr)[slotIndex].cryptBundle.key))) + { + return NV_ERR_FATAL_ERROR; + } + + // LCEs will return an error / interrupt if the key is all 0s. + if ((CC_GKEYID_GET_KEYSPACE(globalKeyId) >= CC_KEYSPACE_LCE0) && + (CC_GKEYID_GET_KEYSPACE(globalKeyId) <= CC_KEYSPACE_LCE7)) + { + for (NvU32 index = 0; index < CC_AES_256_GCM_KEY_SIZE_DWORD; index++) + { + if ((*keySlotLocalPtr)[slotIndex].cryptBundle.key[index] != 0) + { + return NV_OK; + } + } + + return NV_ERR_FATAL_ERROR; + } + + return NV_OK; + return NV_ERR_NOT_SUPPORTED; +} + +void +confComputeKeyStoreDepositIvMask_GH100 +( + ConfidentialCompute *pConfCompute, + NvU32 globalKeyId, + void *ivMask +) +{ + NvU32 slotNumber = getKeySlotFromGlobalKeyId(globalKeyId); + cryptoBundle_t (*keySlotLocalPtr)[]; + + keySlotLocalPtr = pConfCompute->m_keySlot; + + NV_PRINTF(LEVEL_INFO, "Depositing IV mask for global key ID %x.\n", globalKeyId); + + portMemCopy((*keySlotLocalPtr)[slotNumber].cryptBundle.ivMask, + sizeof((*keySlotLocalPtr)[slotNumber].cryptBundle.ivMask), + ivMask, CC_AES_256_GCM_IV_SIZE_BYTES); +} + +void +confComputeKeyStoreClearExportMasterKey_GH100(ConfidentialCompute *pConfCompute) +{ + NV_PRINTF(LEVEL_INFO, "Clearing the Export Master Key.\n"); + + portMemSet(pConfCompute->m_exportMasterKey, 0, (NvLength) sizeof(pConfCompute->m_exportMasterKey)); +} + +NV_STATUS +confComputeKeyStoreRetrieveViaChannel_GH100 +( + ConfidentialCompute *pConfCompute, + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + NvBool includeSecrets, + CC_KMB *keyMaterialBundle +) +{ + NvU32 globalKeyId; + NvU16 keyId; + + if (RM_ENGINE_TYPE_IS_COPY(kchannelGetEngineType(pKernelChannel))) + { + NvU16 keyspace; + + if (getKeyspaceLce(pKernelChannel, &keyspace) != NV_OK) + { + return NV_ERR_INVALID_PARAMETER; + } + + if (getKeyIdLce(pKernelChannel, rotateOperation, &keyId) != NV_OK) + { + return NV_ERR_INVALID_PARAMETER; + } + + globalKeyId = CC_GKEYID_GEN(keyspace, keyId); + } + else if (kchannelGetEngineType(pKernelChannel) == RM_ENGINE_TYPE_SEC2) + { + if (getKeyIdSec2(pKernelChannel, rotateOperation, &keyId) != NV_OK) + { + return NV_ERR_INVALID_PARAMETER; + } + + globalKeyId = CC_GKEYID_GEN(CC_KEYSPACE_SEC2, keyId); + } + else + { + return NV_ERR_INVALID_PARAMETER; + } + + return confComputeKeyStoreRetrieveViaKeyId_GH100(pConfCompute, globalKeyId, rotateOperation, + includeSecrets, keyMaterialBundle); +} + +NV_STATUS +confComputeKeyStoreRetrieveViaKeyId_GH100 +( + ConfidentialCompute *pConfCompute, + NvU32 globalKeyId, + ROTATE_IV_TYPE rotateOperation, + NvBool includeSecrets, + CC_KMB *keyMaterialBundle +) +{ + NvU32 slotNumber = getKeySlotFromGlobalKeyId(globalKeyId); + cryptoBundle_t (*keySlotLocalPtr)[]; + + keySlotLocalPtr = pConfCompute->m_keySlot; + + NV_PRINTF(LEVEL_INFO, "Retrieving KMB from slot number = %d and type is %d.\n", + slotNumber, (*keySlotLocalPtr)[slotNumber].type); + + if ((slotNumber % 2) == 1) + { + slotNumber--; + } + + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + if (checkSlot(pConfCompute, slotNumber) != NV_OK) + { + // Right now returns error to caller. Depending on how the re-keying flow is designed + // this may initiate re-keying. + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + if ((rotateOperation == ROTATE_IV_DECRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID) || + (rotateOperation == ROTATE_IV_HMAC)) + { + if (checkSlot(pConfCompute, slotNumber + 1) != NV_OK) + { + // Right now returns error to caller. Depending on how the re-keying flow is designed + // this may initiate re-keying. + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + incrementChannelCounter(pConfCompute, slotNumber); + + if (includeSecrets) + { + keyMaterialBundle->encryptBundle = (*keySlotLocalPtr)[slotNumber].cryptBundle; + } + else + { + portMemCopy(keyMaterialBundle->encryptBundle.iv, sizeof(keyMaterialBundle->encryptBundle.iv), + (*keySlotLocalPtr)[slotNumber].cryptBundle.iv, CC_AES_256_GCM_IV_SIZE_BYTES); + } + } + + if ((rotateOperation == ROTATE_IV_DECRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID) || + (rotateOperation == ROTATE_IV_HMAC)) + { + incrementChannelCounter(pConfCompute, slotNumber + 1); + + switch ((*keySlotLocalPtr)[slotNumber + 1].type) + { + case NO_CHAN_COUNTER: + case CRYPT_COUNTER: + if (includeSecrets) + { + keyMaterialBundle->decryptBundle = (*keySlotLocalPtr)[slotNumber + 1].cryptBundle; + } + else + { + portMemCopy(keyMaterialBundle->decryptBundle.iv, sizeof(keyMaterialBundle->decryptBundle.iv), + (*keySlotLocalPtr)[slotNumber].cryptBundle.iv, CC_AES_256_GCM_IV_SIZE_BYTES); + } + keyMaterialBundle->bIsWorkLaunch = NV_FALSE; + break; + case HMAC_COUNTER: + if (includeSecrets) + { + keyMaterialBundle->hmacBundle = (*keySlotLocalPtr)[slotNumber + 1].hmacBundle; + } + else + { + portMemCopy(keyMaterialBundle->hmacBundle.nonce, sizeof(keyMaterialBundle->hmacBundle.nonce), + (*keySlotLocalPtr)[slotNumber].hmacBundle.nonce, CC_AES_256_GCM_IV_SIZE_BYTES); + } + keyMaterialBundle->bIsWorkLaunch = NV_TRUE; + break; + + } + } + + return NV_OK; +} + +NV_STATUS +confComputeKeyStoreUpdateKey_GH100(ConfidentialCompute *pConfCompute, NvU32 globalKeyId) +{ + return NV_ERR_NOT_SUPPORTED; +} + +// +// Return the key ID for a given LCE channel and rotation operation. +// If rotateOperation is ROTATE_IV_ALL_VALID then it will return the least +// key ID of the key pair; ie the one that corresponds to an even numbered slot. +// +static NV_STATUS +getKeyIdLce +( + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + NvU16 *keyId +) +{ + if (kchannelCheckIsUserMode(pKernelChannel)) + { + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + *keyId = CC_LKEYID_LCE_H2D_USER; + } + else + { + *keyId = CC_LKEYID_LCE_D2H_USER; + } + + return NV_OK; + } + else if (kchannelCheckIsKernel(pKernelChannel)) + { + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + *keyId = CC_LKEYID_LCE_H2D_KERN; + } + else + { + *keyId = CC_LKEYID_LCE_D2H_KERN; + } + + return NV_OK; + } + + return NV_ERR_GENERIC; +} + +// +// Return the key ID for a given SEC2 channel and rotation operation. +// If rotateOperation is ROTATE_IV_ALL_VALID then it will return the least +// key ID of the key pair; ie the one that corresponds to an even numbered slot. +// +static NV_STATUS +getKeyIdSec2 +( + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + NvU16 *keyId +) +{ + if (kchannelCheckIsUserMode(pKernelChannel)) + { + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + *keyId = CC_LKEYID_CPU_SEC2_DATA_USER; + } + else + { + *keyId = CC_LKEYID_CPU_SEC2_HMAC_USER; + } + + return NV_OK; + } + else if (kchannelCheckIsKernel(pKernelChannel)) + { + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + *keyId = CC_LKEYID_CPU_SEC2_DATA_KERN; + } + else + { + *keyId = CC_LKEYID_CPU_SEC2_HMAC_KERN; + } + + return NV_OK; + } + + return NV_ERR_GENERIC; +} + +static NV_STATUS +getKeyspaceLce +( + KernelChannel *pKernelChannel, + NvU16 *keyspace +) +{ + // The actual copy engine (2 through 9) is normalized to start at 0. + switch (kchannelGetEngineType(pKernelChannel)) + { + case RM_ENGINE_TYPE_COPY2: + *keyspace = CC_KEYSPACE_LCE0; + break; + case RM_ENGINE_TYPE_COPY3: + *keyspace = CC_KEYSPACE_LCE1; + break; + case RM_ENGINE_TYPE_COPY4: + *keyspace = CC_KEYSPACE_LCE2; + break; + case RM_ENGINE_TYPE_COPY5: + *keyspace = CC_KEYSPACE_LCE3; + break; + case RM_ENGINE_TYPE_COPY6: + *keyspace = CC_KEYSPACE_LCE4; + break; + case RM_ENGINE_TYPE_COPY7: + *keyspace = CC_KEYSPACE_LCE5; + break; + case RM_ENGINE_TYPE_COPY8: + *keyspace = CC_KEYSPACE_LCE6; + break; + case RM_ENGINE_TYPE_COPY9: + *keyspace = CC_KEYSPACE_LCE7; + break; + default: + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +static NvU32 +getKeySlotFromGlobalKeyId +( + NvU32 globalKeyId +) +{ + NvU16 keyspace = CC_GKEYID_GET_KEYSPACE(globalKeyId); + NvU32 keySlotIndex = 0; + + for (NvU16 index = 0; index < CC_KEYSPACE_SIZE; index++) + { + if (index == keyspace) + { + break; + } + else + { + keySlotIndex += getKeyspaceSize(index); + } + } + + return keySlotIndex + CC_GKEYID_GET_LKEYID(globalKeyId); +} + +static NV_STATUS +checkSlot +( + ConfidentialCompute *pConfCompute, + NvU32 slotNumber +) +{ + if (getChannelCounter(pConfCompute, slotNumber) == NV_U64_MAX) + { + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +static void +incrementChannelCounter +( + ConfidentialCompute *pConfCompute, + NvU32 slotNumber +) +{ + NvU64 channelCounter = getChannelCounter(pConfCompute, slotNumber); + cryptoBundle_t (*keySlotLocalPtr)[]; + + keySlotLocalPtr = pConfCompute->m_keySlot; + + channelCounter++; + + switch ((*keySlotLocalPtr)[slotNumber].type) + { + case NO_CHAN_COUNTER: + break; + case CRYPT_COUNTER: + (*keySlotLocalPtr)[slotNumber].cryptBundle.iv[2] = NvU64_HI32(channelCounter); + (*keySlotLocalPtr)[slotNumber].cryptBundle.iv[1] = NvU64_LO32(channelCounter); + break; + case HMAC_COUNTER: + (*keySlotLocalPtr)[slotNumber].hmacBundle.nonce[7] = NvU64_HI32(channelCounter); + (*keySlotLocalPtr)[slotNumber].hmacBundle.nonce[6] = NvU64_LO32(channelCounter); + break; + } +} + +static NvU32 +getKeyspaceSize +( + NvU16 keyspace +) +{ + switch (keyspace) + { + case CC_KEYSPACE_GSP: + return CC_KEYSPACE_GSP_SIZE; + case CC_KEYSPACE_SEC2: + return CC_KEYSPACE_SEC2_SIZE; + case CC_KEYSPACE_LCE0: + case CC_KEYSPACE_LCE1: + case CC_KEYSPACE_LCE2: + case CC_KEYSPACE_LCE3: + case CC_KEYSPACE_LCE4: + case CC_KEYSPACE_LCE5: + case CC_KEYSPACE_LCE6: + case CC_KEYSPACE_LCE7: + return CC_KEYSPACE_LCE_SIZE; + default: + NV_ASSERT_OR_RETURN(NV_FALSE, 0); + } +} + +static NvU64 +getChannelCounter +( + ConfidentialCompute *pConfCompute, + NvU32 slotNumber +) +{ + cryptoBundle_t (*keySlotLocalPtr)[]; + + keySlotLocalPtr = pConfCompute->m_keySlot; + + switch ((*keySlotLocalPtr)[slotNumber].type) + { + case NO_CHAN_COUNTER: + return 0; + case CRYPT_COUNTER: + return CONCAT64((*keySlotLocalPtr)[slotNumber].cryptBundle.iv[2], + (*keySlotLocalPtr)[slotNumber].cryptBundle.iv[1]); + case HMAC_COUNTER: + return CONCAT64((*keySlotLocalPtr)[slotNumber].hmacBundle.nonce[7], + (*keySlotLocalPtr)[slotNumber].hmacBundle.nonce[6]); + default: + NV_ASSERT_OR_RETURN(NV_FALSE, 0); + } +} diff --git a/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c b/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c new file mode 100644 index 0000000000..116a2ce2a6 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c @@ -0,0 +1,672 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/prelude.h" +#include "rmconfig.h" +#include "kernel/gpu/conf_compute/ccsl.h" +#include "kernel/gpu/fifo/kernel_channel.h" +#include "nvport/nvport.h" +#include "rmapi/rmapi.h" +#include "ctrl/ctrlc56f.h" +#include +// This guard is here until we fix CONF_COMPUTE and SPDM guards across whole RM +#include "kernel/gpu/spdm/libspdm_includes.h" +#include +#include "cc_drv.h" + +struct ccslContext_t +{ + NvHandle hClient; + NvHandle hChannel; + + enum {CSL_MSG_CTR_32, CSL_MSG_CTR_64} msgCounterSize; + + NvU8 keyIn[CC_AES_256_GCM_KEY_SIZE_BYTES]; + union + { + struct + { + NvU8 ivIn[CC_AES_256_GCM_IV_SIZE_BYTES]; + NvU8 ivMaskIn[CC_AES_256_GCM_IV_SIZE_BYTES]; + }; + NvU8 nonce[CC_HMAC_NONCE_SIZE_BYTES]; + }; + + NvU8 keyOut[CC_AES_256_GCM_KEY_SIZE_BYTES]; + NvU8 ivOut[CC_AES_256_GCM_IV_SIZE_BYTES]; + NvU8 ivMaskOut[CC_AES_256_GCM_IV_SIZE_BYTES]; + + NvU64 keyHandleIn; + NvU64 keyHandleOut; +}; + +static void ccslSplit32(NvU8 *dst, NvU32 num) +{ + dst[3] = (NvU8) (num >> 24); + dst[2] = (NvU8) (num >> 16); + dst[1] = (NvU8) (num >> 8); + dst[0] = (NvU8) (num); +} + +static void ccslSplit64(NvU8 *dst, NvU64 num) +{ + dst[7] = (NvU8) (num >> 56); + dst[6] = (NvU8) (num >> 48); + dst[5] = (NvU8) (num >> 40); + dst[4] = (NvU8) (num >> 32); + dst[3] = (NvU8) (num >> 24); + dst[2] = (NvU8) (num >> 16); + dst[1] = (NvU8) (num >> 8); + dst[0] = (NvU8) (num); +} + +static NV_STATUS incrementCounter(pCcslContext pCtx, NvU8 *ctr) +{ + NvU32 msgCounterLo = NvU32_BUILD(ctr[3], ctr[2], ctr[1], ctr[0]); + + switch (pCtx->msgCounterSize) + { + case CSL_MSG_CTR_32: + if (msgCounterLo == NV_U32_MAX) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + ++msgCounterLo; + ccslSplit32(ctr, msgCounterLo); + break; + case CSL_MSG_CTR_64: + { + NvU32 msgCounterhi = NvU32_BUILD(ctr[7], ctr[6], ctr[5], ctr[4]); + NvU64 msgCounter = ((NvU64) msgCounterhi << 32) | msgCounterLo; + + if (msgCounter == NV_U64_MAX) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + ++msgCounter; + ccslSplit64(ctr, msgCounter); + break; + } + } + + return NV_OK; +} + +static void writeKmbToContext +( + pCcslContext pCtx, + CC_KMB *kmb +) +{ + for (NvU32 index = 0; index < CC_AES_256_GCM_KEY_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->keyOut + 4 * index, kmb->encryptBundle.key[index]); + } + + for (NvU32 index = 0; index < CC_AES_256_GCM_IV_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->ivOut + 4 * index, kmb->encryptBundle.iv[index]); + ccslSplit32(pCtx->ivMaskOut + 4 * index, kmb->encryptBundle.ivMask[index]); + } + + if (kmb->bIsWorkLaunch) + { + for (NvU32 index = 0; index < CC_AES_256_GCM_KEY_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->keyIn + 4 * index, kmb->hmacBundle.key[index]); + } + + for (NvU32 index = 0; index < CC_HMAC_NONCE_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->nonce + 4 * index, kmb->hmacBundle.nonce[index]); + } + } + else + { + for (NvU32 index = 0; index < CC_AES_256_GCM_KEY_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->keyIn + 4 * index, kmb->decryptBundle.key[index]); + } + + for (NvU32 index = 0; index < CC_AES_256_GCM_IV_SIZE_DWORD; index++) + { + ccslSplit32(pCtx->ivMaskIn + 4 * index, kmb->decryptBundle.ivMask[index]); + ccslSplit32(pCtx->ivIn + 4 * index, kmb->decryptBundle.iv[index]); + } + } +} + +NV_STATUS +ccslContextInitViaChannel +( + pCcslContext *ppCtx, + NvHandle hClient, + NvHandle hChannel +) +{ + CC_KMB *kmb; + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + OBJGPU *pGpu; + NvU32 gpuMask; + NvU32 gpuInstance = 0; + RM_API *pRmApi = NULL; + + NVC56F_CTRL_CMD_GET_KMB_PARAMS getKmbParams; + + NV_PRINTF(LEVEL_INFO, "Initializing CCSL context via channel.\n"); + + // This function must be redesigned for multi-gpu + if(!pGpuMgr->ccCaps.bHccFeatureCapable) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (ppCtx == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + pCcslContext pCtx = portMemAllocNonPaged(sizeof(*pCtx)); + if (pCtx == NULL) + { + return NV_ERR_NO_MEMORY; + } + *ppCtx = pCtx; + + pCtx->hClient = hClient; + pCtx->hChannel = hChannel; + + (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); + + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (IS_GSP_CLIENT(pGpu)) + { + pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + } + else + { + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + } + portMemSet(&getKmbParams, 0, sizeof(getKmbParams)); + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + hClient, + hChannel, + NVC56F_CTRL_CMD_GET_KMB, + &getKmbParams, + sizeof(getKmbParams))); + + pCtx->msgCounterSize = CSL_MSG_CTR_32; + + kmb = &getKmbParams.kmb; + + writeKmbToContext(pCtx, kmb); + } + + return NV_OK; +} + +NV_STATUS +ccslContextInitViaKeyId +( + ConfidentialCompute *pConfCompute, + pCcslContext *ppCtx, + NvU32 globalKeyId +) +{ + NV_STATUS status; + CC_KMB kmb; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + NV_PRINTF(LEVEL_INFO, "Initializing CCSL context via globak key ID.\n"); + + // This function must be redesigned for multi-gpu + if(!pGpuMgr->ccCaps.bHccFeatureCapable) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (ppCtx == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + pCcslContext pCtx = portMemAllocNonPaged(sizeof(*pCtx)); + if (pCtx == NULL) + { + return NV_ERR_NO_MEMORY; + } + *ppCtx = pCtx; + + status = confComputeKeyStoreRetrieveViaKeyId_HAL(pConfCompute, + globalKeyId, + ROTATE_IV_ALL_VALID, + NV_TRUE, + &kmb); + if (status != NV_OK) + { + return status; + } + + // For now assume any call to this function uses a 64-bit message counter. + pCtx->msgCounterSize = CSL_MSG_CTR_64; + writeKmbToContext(pCtx, &kmb); + + return NV_OK; +} + +void +ccslContextClear +( + pCcslContext pCtx +) +{ + NV_PRINTF(LEVEL_INFO, "Clearing the CCSL context.\n"); + + if (pCtx == NULL) + { + return; + } + + portMemFree(pCtx); +} + +NV_STATUS +ccslLogDeviceEncryption +( + pCcslContext pCtx, + NvU8 *decryptIv +) +{ + NV_STATUS status; + + status = incrementCounter(pCtx, pCtx->ivIn); + + if (status != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + portMemCopy(decryptIv, CC_AES_256_GCM_IV_SIZE_BYTES, pCtx->ivIn, CC_AES_256_GCM_IV_SIZE_BYTES); + + return NV_OK; +} + +NV_STATUS +ccslAcquireEncryptionIv +( + pCcslContext pCtx, + NvU8 *encryptIv +) +{ + NV_STATUS status; + + status = incrementCounter(pCtx, pCtx->ivOut); + + if (status != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + portMemCopy(encryptIv, CC_AES_256_GCM_IV_SIZE_BYTES, pCtx->ivOut, CC_AES_256_GCM_IV_SIZE_BYTES); + + // The "freshness" bit is right after the IV. + encryptIv[CC_AES_256_GCM_IV_SIZE_BYTES] = 1; + + return NV_OK; +} + +NV_STATUS +ccslRotateIv +( + pCcslContext pCtx, + NvU8 direction +) +{ + OBJGPU *pGpu; + NvU32 gpuMask; + NvU32 gpuInstance = 0; + RM_API *pRmApi = NULL; + + NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS rotateIvParams; + + if ((direction != CCSL_DIR_HOST_TO_DEVICE) && (direction != CCSL_DIR_DEVICE_TO_HOST)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + portMemSet(&rotateIvParams, 0, sizeof(rotateIvParams)); + + if (direction == CCSL_DIR_HOST_TO_DEVICE) + { + rotateIvParams.rotateIvType = ROTATE_IV_ENCRYPT; + } + else + { + rotateIvParams.rotateIvType = ROTATE_IV_DECRYPT; + } + + (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (IS_GSP_CLIENT(pGpu)) + { + pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + } + else + { + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + } + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pCtx->hClient, + pCtx->hChannel, + NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV, + &rotateIvParams, + sizeof(rotateIvParams))); + } + + switch (direction) + { + case CCSL_DIR_HOST_TO_DEVICE: + portMemCopy(pCtx->keyOut, sizeof(pCtx->keyOut), + &rotateIvParams.updatedKmb.encryptBundle.key, + sizeof(rotateIvParams.updatedKmb.encryptBundle.key)); + portMemCopy(pCtx->ivMaskOut, sizeof(pCtx->ivMaskOut), + &rotateIvParams.updatedKmb.encryptBundle.ivMask, + sizeof(rotateIvParams.updatedKmb.encryptBundle.ivMask)); + portMemCopy(pCtx->ivOut, sizeof(pCtx->ivOut), + &rotateIvParams.updatedKmb.encryptBundle.iv, + sizeof(rotateIvParams.updatedKmb.encryptBundle.iv)); + break; + + case CCSL_DIR_DEVICE_TO_HOST: + portMemCopy(pCtx->keyIn, sizeof(pCtx->keyIn), + &rotateIvParams.updatedKmb.decryptBundle.key, + sizeof(rotateIvParams.updatedKmb.decryptBundle.key)); + portMemCopy(pCtx->ivMaskIn, sizeof(pCtx->ivMaskIn), + &rotateIvParams.updatedKmb.decryptBundle.ivMask, + sizeof(rotateIvParams.updatedKmb.decryptBundle.ivMask)); + portMemCopy(pCtx->ivIn, sizeof(pCtx->ivIn), + &rotateIvParams.updatedKmb.decryptBundle.iv, + sizeof(rotateIvParams.updatedKmb.decryptBundle.iv)); + break; + } + + return NV_OK; +} + +NV_STATUS +ccslEncryptWithIv +( + pCcslContext pCtx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer +) +{ + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; + size_t outputBufferSize = bufferSize; + + // The "freshness" bit is right after the IV + if (encryptIv[CC_AES_256_GCM_IV_SIZE_BYTES] != 1) + { + return NV_ERR_INVALID_ARGUMENT; + } + + encryptIv[CC_AES_256_GCM_IV_SIZE_BYTES] = 0; + + for (NvU64 i = 0; i < CC_AES_256_GCM_IV_SIZE_BYTES; i++) + { + iv[i] = encryptIv[i] ^ pCtx->ivMaskOut[i]; + } + + if(!libspdm_aead_aes_gcm_encrypt( + (NvU8 *)pCtx->keyOut, CC_AES_256_GCM_KEY_SIZE_BYTES, + iv, CC_AES_256_GCM_IV_SIZE_BYTES, NULL, 0, + inputBuffer, bufferSize, authTagBuffer, 16, + outputBuffer, &outputBufferSize)) + { + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +NV_STATUS +ccslEncrypt +( + pCcslContext pCtx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagBuffer +) +{ + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; + size_t outputBufferSize = bufferSize; + + if (incrementCounter(pCtx, pCtx->ivOut) != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + for (NvU64 i = 0; i < CC_AES_256_GCM_IV_SIZE_BYTES; i++) + { + iv[i] = pCtx->ivOut[i] ^ pCtx->ivMaskOut[i]; + } + + if(!libspdm_aead_aes_gcm_encrypt( + (NvU8 *)pCtx->keyOut, CC_AES_256_GCM_KEY_SIZE_BYTES, + iv, CC_AES_256_GCM_IV_SIZE_BYTES, NULL, 0, + inputBuffer, bufferSize, authTagBuffer, 16, + outputBuffer, &outputBufferSize)) + { + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +NV_STATUS +ccslDecrypt +( + pCcslContext pCtx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *authTagBuffer +) +{ + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; + size_t outputBufferSize = bufferSize; + + if (decryptIv == NULL) + { + if (incrementCounter(pCtx, pCtx->ivIn) != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + for (NvU64 i = 0; i < CC_AES_256_GCM_IV_SIZE_BYTES; i++) + { + iv[i] = pCtx->ivIn[i] ^ pCtx->ivMaskIn[i]; + } + } + else + { + for (NvU64 i = 0; i < CC_AES_256_GCM_IV_SIZE_BYTES; i++) + { + iv[i] = decryptIv[i] ^ pCtx->ivMaskIn[i]; + } + } + + if(!libspdm_aead_aes_gcm_decrypt( + (NvU8 *)pCtx->keyIn, CC_AES_256_GCM_KEY_SIZE_BYTES, + iv, CC_AES_256_GCM_IV_SIZE_BYTES, NULL, 0, + inputBuffer, bufferSize, authTagBuffer, 16, + outputBuffer, &outputBufferSize)) + { + return NV_ERR_INVALID_DATA; + } + + return NV_OK; +} + +static NV_STATUS incrementCounter192(NvU8 *ctr) +{ + NvU8 carry = 1; + NvU64 i; + NvBool overflow = NV_TRUE; + + for (i = 0; i < 192 / 8; ++i) + { + if (ctr[i] != 0xFF) + { + overflow = NV_FALSE; + break; + } + } + if (overflow) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + for (i = 0; i < 192 / 8; ++i) + { + ctr[i] += carry; + carry = (ctr[i] == 0) && (carry == 1); + } + + return NV_OK; +} + +NV_STATUS +ccslSign +( + pCcslContext pCtx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer +) +{ + void *hmac_ctx; + + if (bufferSize == 0) + { + return NV_ERR_INVALID_PARAMETER; + } + + if (incrementCounter192(pCtx->nonce) != NV_OK) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + hmac_ctx = libspdm_hmac_sha256_new(); + if (hmac_ctx == NULL) + { + return NV_ERR_GENERIC; + } + + if (!libspdm_hmac_sha256_set_key(hmac_ctx, pCtx->keyIn, CC_AES_256_GCM_KEY_SIZE_BYTES)) + { + libspdm_hmac_sha256_free(hmac_ctx); + return NV_ERR_GENERIC; + } + + if (!libspdm_hmac_sha256_update(hmac_ctx, inputBuffer, bufferSize)) + { + libspdm_hmac_sha256_free(hmac_ctx); + return NV_ERR_GENERIC; + } + + if (!libspdm_hmac_sha256_update(hmac_ctx, pCtx->nonce, CC_HMAC_NONCE_SIZE_BYTES)) + { + libspdm_hmac_sha256_free(hmac_ctx); + return NV_ERR_GENERIC; + } + + if (!libspdm_hmac_sha256_final(hmac_ctx, authTagBuffer)) + { + libspdm_hmac_sha256_free(hmac_ctx); + return NV_ERR_GENERIC; + } + + libspdm_hmac_sha256_free(hmac_ctx); + + return NV_OK; +} + +static NvU64 getMessageCounterAndLimit (pCcslContext pCtx, NvU8 *iv, NvU64 *limit) +{ + NvU32 msgCounterLo = NvU32_BUILD(iv[3], iv[2], iv[1], iv[0]); + NvU32 msgCounterHi = NvU32_BUILD(iv[7], iv[6], iv[5], iv[4]); + + switch (pCtx->msgCounterSize) + { + case CSL_MSG_CTR_32: + *limit = NV_U32_MAX; + return msgCounterLo; + case CSL_MSG_CTR_64: + *limit = NV_U64_MAX; + return ((((NvU64) msgCounterHi) << 32) | msgCounterLo); + default: + return 0; + } +} + +NV_STATUS +ccslQueryMessagePool +( + pCcslContext pCtx, + NvU8 direction, + NvU64 *messageNum +) +{ + NvU64 limit; + NvU64 messageCounter; + + switch (direction) + { + case CCSL_DIR_HOST_TO_DEVICE: + messageCounter = getMessageCounterAndLimit(pCtx, pCtx->ivOut, &limit); + break; + case CCSL_DIR_DEVICE_TO_HOST: + messageCounter = getMessageCounterAndLimit(pCtx, pCtx->ivIn, &limit); + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + + *messageNum = limit - messageCounter; + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c new file mode 100644 index 0000000000..69c8c3b361 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c @@ -0,0 +1,400 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * Confidential Compute Object Module * + * * + \**************************************************************************/ + +#define NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED + +#include "nvrm_registry.h" +#include "gpu/conf_compute/conf_compute.h" +#include "gpu/conf_compute/conf_compute_keystore.h" +#include "spdm/rmspdmvendordef.h" +#include "gsp/gsp_proxy_reg.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu/gpu.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" + +/*! + * Local object related functions + */ +static void _confComputeInitRegistryOverrides(OBJGPU *, ConfidentialCompute*); + + +NV_STATUS +confComputeConstructEngine_IMPL(OBJGPU *pGpu, + ConfidentialCompute *pConfCompute, + ENGDESCRIPTOR engDesc) +{ + pConfCompute->pSpdm = NULL; + portMemSet(&pConfCompute->ccStaticInfo, 0, sizeof(pConfCompute->ccStaticInfo)); + pConfCompute->gspProxyRegkeys = 0; + + if (gpuIsCCEnabledInHw_HAL(pGpu)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED, NV_TRUE); + } + + if (gpuIsDevModeEnabledInHw_HAL(pGpu)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, NV_TRUE); + } + + _confComputeInitRegistryOverrides(pGpu, pConfCompute); + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) + { + NV_CHECK_OR_RETURN(LEVEL_ERROR, confComputeIsGpuCcCapable_HAL(pGpu, pConfCompute), NV_ERR_INVALID_OPERATION); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_APM_FEATURE_CAPABLE)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED, NV_TRUE); + + // Forcing DEV_MODE to False for APM + NV_PRINTF(LEVEL_INFO, "Confidential Compute devtools mode DISABLED in APM.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, NV_FALSE); + pConfCompute->gspProxyRegkeys |= DRF_DEF(GSP, _PROXY_REG, _CONF_COMPUTE_DEV_MODE, _DISABLE); + } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED, NV_TRUE); + } + else + { + NV_PRINTF(LEVEL_ERROR, "GPU does not support confidential compute"); + NV_ASSERT(0); + return NV_ERR_INVALID_OPERATION; + } + } + + return NV_OK; +} + +/*! + * Initialize all registry overrides for this object + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +static void +_confComputeInitRegistryOverrides +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NvU32 data = 0; + + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_CONFIDENTIAL_COMPUTE, &data) == NV_OK) && + FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _ENABLED, _YES, data)) + { + NV_PRINTF(LEVEL_INFO, "Confidential Compute enabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED, NV_TRUE); + pConfCompute->gspProxyRegkeys |= DRF_DEF(GSP, _PROXY_REG, _CONFIDENTIAL_COMPUTE, _ENABLE); + + if (FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _GPUS_READY_CHECK, _ENABLED, data)) + { + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED, NV_TRUE); + } + + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT, &data) + == NV_OK) && (data == NV_REG_STR_RM_CONF_COMPUTE_EARLY_INIT_ENABLED)) + { + NV_PRINTF(LEVEL_INFO, "Confidential Compute early init enabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT, NV_TRUE); + pConfCompute->gspProxyRegkeys |= DRF_DEF(GSP, _PROXY_REG, _CONF_COMPUTE_EARLY_INIT, _ENABLE); + } + + if (FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _DEV_MODE_ENABLED, _YES, data)) + { + NV_PRINTF(LEVEL_INFO, "Confidential Compute dev mode enabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, NV_TRUE); + pConfCompute->gspProxyRegkeys |= DRF_DEF(GSP, _PROXY_REG, _CONF_COMPUTE_DEV_MODE, _ENABLE); + } + } + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) + { + if (confComputeIsSpdmEnabled(pGpu, pConfCompute)) + { + NV_PRINTF(LEVEL_INFO, "SPDM is enabled by default.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, NV_TRUE); + } + + // Allow override of whatever default settings are. + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CONF_COMPUTE_SPDM_POLICY, &data) == NV_OK) + { + if (FLD_TEST_DRF(_REG_STR, _RM_CONF_COMPUTE_SPDM_POLICY, _ENABLED, _YES, data)) + { + NV_PRINTF(LEVEL_INFO, "Confidential Compute SPDM enabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, NV_TRUE); + } + else if (FLD_TEST_DRF(_REG_STR, _RM_CONF_COMPUTE_SPDM_POLICY, _ENABLED, _NO, data)) + { + // OPENRM-TODO: Always enable SPDM for debug. + NV_PRINTF(LEVEL_INFO, "Confidential Compute SPDM disabled via regkey override.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, NV_FALSE); + } + } + } + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) + { + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE, &data) == NV_OK) + { + pGpu->bIsGspOwnedFaultBuffersEnabled = data; + } + else + { + pGpu->bIsGspOwnedFaultBuffersEnabled = NV_REG_STR_RM_GSP_OWNED_FAULT_BUFFERS_ENABLE_YES; + } + } +} + +/*! + * Establish the SPDM session with the GPU Responder. + * After establishing the session, initialize all keys required + * for the Confidential Compute session. + * + * Note: This assumes that Confidential Compute is the first object + * to be initialized in the GPU child order list, and therefore + * SPDM session establishment is the first thing to happen. If another + * object precedes Confidential Compute - it will be initialized before + * SPDM session establishment. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +static NV_STATUS +_confComputeEstablishSpdmSessionAndKeys +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + NV_STATUS status = NV_OK; + + + if (IS_FMODEL(pGpu)) + { + // Skip SPDM support on fmodel due to bugs 3553627 and 3556621. + return NV_OK; + } + + // + // Initialize SPDM session between Guest RM and SPDM Responder on GPU. + // The session lifetime will track Confidential Compute object state lifetime. + // + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + status = objCreate(&pConfCompute->pSpdm, pConfCompute, Spdm); + if (status != NV_OK) + { + return status; + } + + NV_ASSERT(pConfCompute->pSpdm); + + // Initialize SPDM context & begin session. + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + spdmContextInit(pGpu, pConfCompute->pSpdm), + ErrorExit); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + spdmStart(pGpu, pConfCompute->pSpdm), + ErrorExit); + + // + // Now that SPDM session is established, we must initialize + // keystore for any session-derived keys. + // + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + confComputeKeyStoreInit_HAL(pConfCompute), + ErrorExit); + + // Store the export master secret in the keystore. + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + spdmRetrieveExportSecret(pGpu, pConfCompute->pSpdm, + CC_EXPORT_MASTER_KEY_SIZE_BYTES, + confComputeKeyStoreGetExportMasterKey(pConfCompute)), + ErrorExit); + } +ErrorExit: + + return status; +} + +/*! + * Perform any work that must be done before GPU initialization. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + */ +NV_STATUS +confComputeStatePreInitLocked_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + if (!IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Skipping Confidential Compute PreInit.\n"); + return NV_OK; + } + + return _confComputeEstablishSpdmSessionAndKeys(pGpu, pConfCompute); +} + +/*! + * Perform any init that must occur after GPU state load. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + * @param[in] flags Optional flags describing state load conditions + */ +NV_STATUS +confComputeStatePostLoad_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute, + NvU32 flags +) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV_ASSERT_OK_OR_RETURN(status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO, + &pConfCompute->ccStaticInfo, + sizeof(pConfCompute->ccStaticInfo))); + + if (!IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Performing late SPDM initialization!\n"); + status = _confComputeEstablishSpdmSessionAndKeys(pGpu, pConfCompute); + } + + return status; +} + +/*! + * Perform any deinit that must occur before GPU state unload. + * + * @param[in] pGpu GPU object pointer + * @param[in] pConfCompute ConfidentialCompute pointer + * @param[in] flags Optional flags describing state unload conditions + */ +NV_STATUS +confComputeStatePreUnload_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute, + NvU32 flags +) +{ + NV_STATUS status = NV_OK; + + if (IS_FMODEL(pGpu)) + { + // Skip SPDM support on fmodel due to bugs 3553627 and 3556621. + return NV_OK; + } + + // + // Tear down SPDM session between Guest RM and SPDM Responder on GPU. + // We must do in pre-unload, before Responder is torn down entirely. + // + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + confComputeKeyStoreDeinit_HAL(pConfCompute); + + if (pConfCompute->pSpdm == NULL) + { + // + // If SPDM object doesn't exist, we must have failed earlier. + // Alert in logs and move on. + // + NV_PRINTF(LEVEL_ERROR, "SPDM teardown did not occur, as SPDM object is null!\n"); + return NV_OK; + } + + status = spdmContextDeinit(pGpu, pConfCompute->pSpdm, NV_TRUE); + if (status != NV_OK) + { + return status; + } + + objDelete(pConfCompute->pSpdm); + pConfCompute->pSpdm = NULL; + } + + return status; +} + +NvBool +confComputeAcceptClientRequest_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED)) + { + return pGpuMgr->ccCaps.bAcceptClientRequest; + } + else + { + return NV_TRUE; + } +} + +NV_STATUS +confComputeStateInitLocked_IMPL +( + OBJGPU *pGpu, + ConfidentialCompute *pConfCompute +) +{ + RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) : + rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO, + &pConfCompute->ccStaticInfo, + sizeof(pConfCompute->ccStaticInfo))); + + NV_PRINTF(LEVEL_INFO, "BAR1 Trusted: 0x%x PCIE Trusted: 0x%x\n", + pConfCompute->ccStaticInfo.bIsBar1Trusted, pConfCompute->ccStaticInfo.bIsPcieTrusted); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c new file mode 100644 index 0000000000..df0668076b --- /dev/null +++ b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c @@ -0,0 +1,313 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * Confidential Compute API Object Module * + * * + \**************************************************************************/ + +#include "core/locks.h" +#include "rmapi/rs_utils.h" +#include "core/system.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/heap.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "gpu/conf_compute/conf_compute_api.h" +#include "gpu/subdevice/subdevice.h" +#include "class/clcb33.h" // NV_CONFIDENTIAL_COMPUTE + +NV_STATUS +confComputeApiConstruct_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + pConfComputeApi->pCcCaps = &pGpuMgr->ccCaps; + + return NV_OK; +} + +void +confComputeApiDestruct_IMPL +( + ConfidentialComputeApi *pConfComputeApi +) +{ +} + +NV_STATUS +confComputeApiCtrlCmdSystemGetCapabilities_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + CONF_COMPUTE_CAPS *pCcCaps = pConfComputeApi->pCcCaps; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + pParams->cpuCapability = NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE; + if (pSys->cpuInfo.bSEVCapable) + { + pParams->cpuCapability = NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV; + } + + pParams->gpusCapability = NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE; + pParams->environment = NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE; + pParams->ccFeature = NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED; + pParams->devToolsMode = NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED; + + if (pCcCaps->bApmFeatureCapable) + { + pParams->gpusCapability = NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM; + } + else if (pCcCaps->bHccFeatureCapable) + { + pParams->gpusCapability = NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC; + } + + if (pCcCaps->bCCFeatureEnabled) + { + if (pCcCaps->bApmFeatureCapable) + { + pParams->ccFeature = NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED; + } + else if (pCcCaps->bHccFeatureCapable) + { + pParams->ccFeature = NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED; + } + } + + if (pCcCaps->bDevToolsModeEnabled) + { + pParams->devToolsMode = NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED; + } + + if (pParams->ccFeature != NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED) + { + pParams->environment = NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM; + } + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdSystemGetGpusState_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + pParams->bAcceptClientRequest = pConfComputeApi->pCcCaps->bAcceptClientRequest; + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdSystemSetGpusState_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + pConfComputeApi->pCcCaps->bAcceptClientRequest = pParams->bAcceptClientRequest; + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdGpuGetVidmemSize_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS *pParams +) +{ + Subdevice *pSubdevice = NULL; + OBJGPU *pGpu = NULL; + Heap *pHeap = NULL; + Heap *pMemoryPartitionHeap = NULL; + KernelMIGManager *pKernelMIGManager = NULL; + NvU64 totalProtectedBytes = 0; + NvU64 totalUnprotectedBytes = 0; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + subdeviceGetByHandle(RES_GET_CLIENT(pConfComputeApi), + pParams->hSubDevice, &pSubdevice)); + + pGpu = GPU_RES_GET_GPU(pSubdevice); + pHeap = GPU_GET_HEAP(pGpu); + pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + // + // If MIG-GPU-Instancing is enabled, we check for GPU instance subscription + // and provide GPU instance local info + // + if (IS_MIG_IN_USE(pGpu)) + { + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pSubdevice), + &pMemoryPartitionHeap)); + // + // If client is associated with a GPU instance then point pHeap + // to client's memory partition heap + // + if (pMemoryPartitionHeap != NULL) + pHeap = pMemoryPartitionHeap; + } + + pmaGetTotalProtectedMemory(&pHeap->pmaObject, &totalProtectedBytes); + pmaGetTotalUnprotectedMemory(&pHeap->pmaObject, &totalUnprotectedBytes); + + pParams->protectedMemSizeInKb = totalProtectedBytes >> 10; + pParams->unprotectedMemSizeInKb = totalUnprotectedBytes >> 10; + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdGpuSetVidmemSize_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + return NV_OK; +} + +NV_STATUS +confComputeApiCtrlCmdGetGpuCertificate_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *pParams +) +{ + Subdevice *pSubdevice = NULL; + OBJGPU *pGpu = NULL; + ConfidentialCompute *pConfCompute = NULL; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + subdeviceGetByHandle(RES_GET_CLIENT(pConfComputeApi), + pParams->hSubDevice, &pSubdevice)); + pGpu = GPU_RES_GET_GPU(pSubdevice); + pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + if (pConfCompute != NULL) + { + // Set max size of certificate buffers before calling SPDM. + pParams->certChainSize = NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE; + pParams->attestationCertChainSize = NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE; + + return spdmGetCertChains_HAL(pGpu, + pConfCompute->pSpdm, + pParams->certChain, + &pParams->certChainSize, + pParams->attestationCertChain, + &pParams->attestationCertChainSize); + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +confComputeApiCtrlCmdGetGpuAttestationReport_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *pParams +) +{ + Subdevice *pSubdevice = NULL; + OBJGPU *pGpu = NULL; + ConfidentialCompute *pConfCompute = NULL; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + subdeviceGetByHandle(RES_GET_CLIENT(pConfComputeApi), + pParams->hSubDevice, &pSubdevice)); + pGpu = GPU_RES_GET_GPU(pSubdevice); + pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + + if (pConfCompute != NULL) + { + // Set max size of report buffers before calling SPDM. + pParams->attestationReportSize = NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE; + pParams->cecAttestationReportSize = NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE; + + return spdmGetAttestationReport(pGpu, + pConfCompute->pSpdm, + pParams->nonce, + pParams->attestationReport, + &pParams->attestationReportSize, + &pParams->isCecAttestationReportPresent, + pParams->cecAttestationReport, + &pParams->cecAttestationReportSize); + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *pParams +) +{ + Subdevice *pSubdevice; + OBJGPU *pGpu; + KernelFifo *pKernelFifo; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + subdeviceGetByHandle(RES_GET_CLIENT(pConfComputeApi), + pParams->hSubDevice, &pSubdevice)); + + pGpu = GPU_RES_GET_GPU(pSubdevice); + pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + + pParams->maxSec2Channels = pKernelFifo->maxSec2SecureChannels; + pParams->maxCeChannels = pKernelFifo->maxCeSecureChannels; + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_keystore.c b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_keystore.c new file mode 100644 index 0000000000..8bad6d00e2 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_keystore.c @@ -0,0 +1,350 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/conf_compute/conf_compute_keystore.h" +#include "class/cl2080.h" +#include "libraries/nvport/nvport.h" + +#define NUM_SLOTS (KEYSTORE_SLOT_LCE_MGPU(7) + 1) + +#define CONCAT64(hi, low) ((((NvU64)(hi) << 32)) | ((NvU64)(low))) + +// TODO: Remove once key slots are populated by SPDM module. +#define lceBundle \ +{\ + .encryptBundle =\ + {\ + .key = {0x38782F41, 0x3F442847, 0x2B4B6250, 0x65536756, 0x6B597033, 0x73367639, 0x79244226, 0x45294840},\ + .iv = {0x00000000, 0x00000000, 0x00000000},\ + .ivMask = {0x00000000, 0x00000000, 0x00000000}\ + },\ + .decryptBundle =\ + {\ + .key = {0x566B5970, 0x33733676, 0x39792442, 0x26452948, 0x404D6251, 0x65546857, 0x6D5A7134, 0x74377721},\ + .iv = {0x00000000, 0x00000000, 0x00000000},\ + .ivMask = {0x00000000, 0x00000000, 0x00000000}\ + },\ + .bIsWorkLaunch = NV_FALSE\ +} + +static enum {HCC, APM} ccMode; + +// TODO: Remove initialization once key slots are populated by SPDM module. +// Currently the APM Requester will populate the SEC2 slots. +// HCC still relies on hardcoded keys. +static CC_KMB keySlot[NUM_SLOTS] = +{ + lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle, + lceBundle, lceBundle, lceBundle +}; + +static NV_STATUS checkSlot (NvU32 slotNumber, ROTATE_IV_TYPE rotateOperation); +static void incrementChannelCounter (NvU32 slotNumber, ROTATE_IV_TYPE rotateOperation); +static NvU64 getChannelCounter (NvU32 slotNumber, ROTATE_IV_TYPE rotateOperation); +static NV_STATUS checkAndIncrementSlot (NvU32 slotNumber, ROTATE_IV_TYPE rotateOperation); +static NV_STATUS getSlotNumberLce (KernelChannel *pKernelChannel, NvU32 *slotNumber); +static NvU64 getChannelMaxValue (void); + +NV_STATUS +ccKeyStoreInit (OBJGPU *pGpu) +{ + if (gpuIsApmFeatureEnabled(pGpu)) + { + ccMode = APM; + } + else if (gpuIsCCFeatureEnabled(pGpu)) + { + ccMode = HCC; + } + else + { + return NV_ERR_INVALID_STATE; + } + + return NV_OK; +} + +NV_STATUS +ccKeyStoreDeposit +( + NvU32 slotNumber, + CC_KMB keyMaterialBundle +) +{ + if (slotNumber >= NUM_SLOTS) + { + return NV_ERR_INVALID_INDEX; + } + + keySlot[slotNumber] = keyMaterialBundle; + + for (NvU32 index = 0; index < CC_AES_256_GCM_IV_SIZE_DWORD; index++) + { + keySlot[slotNumber].encryptBundle.iv[index] = 0; + keySlot[slotNumber].decryptBundle.iv[index] = 0; + } + + return NV_OK; +} + +NV_STATUS +ccKeyStoreRetrieveViaChannel +( + KernelChannel *pKernelChannel, + ROTATE_IV_TYPE rotateOperation, + PCC_KMB keyMaterialBundle +) +{ + NvU32 slotNumber; + + if (RM_ENGINE_TYPE_IS_COPY(kchannelGetEngineType(pKernelChannel))) + { + if (getSlotNumberLce (pKernelChannel, &slotNumber) != NV_OK) + { + return NV_ERR_INVALID_PARAMETER; + } + } + else if (kchannelGetEngineType(pKernelChannel) == RM_ENGINE_TYPE_SEC2) + { + slotNumber = KEYSTORE_SLOT_SEC2; + } + else + { + return NV_ERR_INVALID_PARAMETER; + } + + if ((rotateOperation == ROTATE_IV_ENCRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + if (checkAndIncrementSlot (slotNumber, ROTATE_IV_ENCRYPT) != NV_OK) + { + // Right now returns error to caller. Depending on how the re-keying flow is designed + // this may initiate re-keying. + + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + if ((rotateOperation == ROTATE_IV_DECRYPT) || (rotateOperation == ROTATE_IV_ALL_VALID)) + { + if (checkAndIncrementSlot (slotNumber, ROTATE_IV_DECRYPT) != NV_OK) + { + // Right now returns error to caller. Depending on how the re-keying flow is designed + // this may initiate re-keying. + + return NV_ERR_INSUFFICIENT_RESOURCES; + } + } + + *keyMaterialBundle = keySlot[slotNumber]; + + return NV_OK; +} + +void +cckeyStoreClear (void) +{ + portMemSet (keySlot, 0, sizeof(keySlot)); +} + +static NV_STATUS +getSlotNumberLce +( + KernelChannel *pKernelChannel, + NvU32 *slotNumber +) +{ + NvU8 index; + + // TODO: Get actual privilege level of channel. For now assume + // all channels have user mode privilege. + switch (kchannelGetEngineType(pKernelChannel)) + { + case RM_ENGINE_TYPE_COPY0: + index = 0; + break; + case RM_ENGINE_TYPE_COPY1: + index = 1; + break; + case RM_ENGINE_TYPE_COPY2: + index = 2; + break; + case RM_ENGINE_TYPE_COPY3: + index = 3; + break; + case RM_ENGINE_TYPE_COPY4: + index = 4; + break; + case RM_ENGINE_TYPE_COPY5: + index = 5; + break; + case RM_ENGINE_TYPE_COPY6: + index = 6; + break; + case RM_ENGINE_TYPE_COPY7: + index = 7; + break; + default: + return NV_ERR_GENERIC; + } + + *slotNumber = KEYSTORE_SLOT_LCE_UMD(index); + + return NV_OK; +} + +static NV_STATUS +checkAndIncrementSlot +( + NvU32 slotNumber, + ROTATE_IV_TYPE rotateOperation // Will only be ROTATE_IV_ENCRYPT or ROTATE_IV_DECRYPT. +) +{ + if (checkSlot (slotNumber, rotateOperation) != NV_OK) + { + return NV_ERR_GENERIC; + } + + // TODO: Unconditionally increment channel counter once HCC supports it. + if (ccMode == APM) + { + incrementChannelCounter (slotNumber, rotateOperation); + } + + return NV_OK; +} + +static NV_STATUS +checkSlot +( + NvU32 slotNumber, + ROTATE_IV_TYPE rotateOperation // Will only be ROTATE_IV_ENCRYPT or ROTATE_IV_DECRYPT. +) +{ + if (getChannelCounter (slotNumber, rotateOperation) == getChannelMaxValue()) + { + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +static void +incrementChannelCounter +( + NvU32 slotNumber, + ROTATE_IV_TYPE rotateOperation // Will only be ROTATE_IV_ENCRYPT or ROTATE_IV_DECRYPT. +) +{ + NvU64 channelCounter = getChannelCounter (slotNumber, rotateOperation); + + channelCounter++; + + switch (rotateOperation) + { + case ROTATE_IV_ENCRYPT: + if (ccMode == HCC) + { + keySlot[slotNumber].encryptBundle.iv[2] = (NvU32) (channelCounter >> 32); + keySlot[slotNumber].encryptBundle.iv[1] = (NvU32) (channelCounter); + } + else if (ccMode == APM) + { + keySlot[slotNumber].encryptBundle.iv[2] = (NvU32) (channelCounter); + } + break; + case ROTATE_IV_DECRYPT: + if (ccMode == HCC) + { + keySlot[slotNumber].decryptBundle.iv[2] = (NvU32) (channelCounter >> 32); + keySlot[slotNumber].decryptBundle.iv[1] = (NvU32) (channelCounter); + } + else if (ccMode == APM) + { + keySlot[slotNumber].decryptBundle.iv[2] = (NvU32) (channelCounter); + } + break; + default: + break; + } +} + +static NvU64 +getChannelCounter +( + NvU32 slotNumber, + ROTATE_IV_TYPE rotateOperation // Will only be ROTATE_IV_ENCRYPT or ROTATE_IV_DECRYPT. +) +{ + NvU64 channelCounter = 0; + + switch (rotateOperation) + { + case ROTATE_IV_ENCRYPT: + if (ccMode == HCC) + { + channelCounter = CONCAT64(keySlot[slotNumber].encryptBundle.iv[2], + keySlot[slotNumber].encryptBundle.iv[1]); + } + else if (ccMode == APM) + { + channelCounter = keySlot[slotNumber].encryptBundle.iv[2]; + } + break; + case ROTATE_IV_DECRYPT: + if (ccMode == HCC) + { + channelCounter = CONCAT64(keySlot[slotNumber].decryptBundle.iv[2], + keySlot[slotNumber].decryptBundle.iv[1]); + } + else if (ccMode == APM) + { + channelCounter = keySlot[slotNumber].decryptBundle.iv[2]; + } + break; + default: + break; + } + + return channelCounter; +} + +static NvU64 +getChannelMaxValue (void) +{ + switch (ccMode) + { + case HCC: + return NV_U64_MAX; + case APM: + return NV_U32_MAX; + default: + return 0; + } +} diff --git a/src/nvidia/src/kernel/gpu/deferred_api.c b/src/nvidia/src/kernel/gpu/deferred_api.c index bb7c55489e..880fa7ddd1 100644 --- a/src/nvidia/src/kernel/gpu/deferred_api.c +++ b/src/nvidia/src/kernel/gpu/deferred_api.c @@ -477,7 +477,6 @@ _class5080DeferredApiV2 NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApi; NV_STATUS rmStatus = NV_OK; NvU32 paramSize = 0; - NvHandle hDevice; NvBool bIsCtrlCall = NV_TRUE; rmStatus = _Class5080GetDeferredApiInfo(pDeferredApiObject, @@ -508,28 +507,36 @@ _class5080DeferredApiV2 { OBJGPU *pTgtGpu; RsClient *pClientVA; + Subdevice *pSubdevice; bIsCtrlCall = NV_FALSE; - rmStatus = serverGetClientUnderLock(&g_resServ, pDeferredApi->hClientVA, &pClientVA); + rmStatus = serverGetClientUnderLock(&g_resServ, pDeferredApi->hClientVA, + &pClientVA); if (rmStatus != NV_OK) break; - if (CliSetSubDeviceContext( - pDeferredApi->hClientVA, - pDeferredApi->hDeviceVA, - &hDevice, - &pTgtGpu) != NV_OK) + rmStatus = subdeviceGetByHandle(pClientVA, pDeferredApi->hDeviceVA, + &pSubdevice); + + if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to find target gpu from hClient(%x), hDevice(%x)\n", pDeferredApi->hClientVA, pDeferredApi->hDeviceVA); - - rmStatus = NV_ERR_INVALID_ARGUMENT; } else { + NvHandle hDevice; OBJVASPACE *pVAS = NULL; + + // Fetch target GPU and set threadstate + pTgtGpu = GPU_RES_GET_GPU(pSubdevice); + + hDevice = RES_GET_HANDLE(pSubdevice->pDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + rmStatus = vaspaceGetByHandleOrDeviceDefault(pClientVA, hDevice, pDeferredApi->api_bundle.InvalidateTlb.hVASpace, @@ -714,7 +721,7 @@ NV_STATUS defapiGetSwMethods_IMPL ) { *ppMethods = Nv50DeferredApi; - *pNumMethods = NV_ARRAY_ELEMENTS32(Nv50DeferredApi); + *pNumMethods = NV_ARRAY_ELEMENTS(Nv50DeferredApi); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/device.c b/src/nvidia/src/kernel/gpu/device.c index 97e4c74158..62d56d5863 100644 --- a/src/nvidia/src/kernel/gpu/device.c +++ b/src/nvidia/src/kernel/gpu/device.c @@ -516,29 +516,6 @@ deviceGetByGpu_IMPL // Deprecated Functions // **************************************************************************** -/** - * WARNING: This function is deprecated! Please use deviceGetByHandle. - */ -Device * -CliGetDeviceInfo -( - NvHandle hClient, - NvHandle hDevice -) -{ - RsClient *pClient; - NV_STATUS status; - Device *pDevice; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return NULL; - - status = deviceGetByHandle(pClient, hDevice, &pDevice); - - return (status == NV_OK) ? pDevice : NULL; -} - /** * WARNING: This function is deprecated and use is *strongly* discouraged * (especially for new code!) diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c b/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c index bc0dfe1995..0226183dc8 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c b/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c index df869b7742..c6ad61a718 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c @@ -33,7 +33,7 @@ #include "gpu/gpu.h" #include "gpu/disp/kern_disp.h" -#include "published/disp/v04_00/dev_disp.h" +#include "disp/v04_00/dev_disp.h" #include "ctrl/ctrl2080/ctrl2080gpio.h" #include "core/locks.h" diff --git a/src/nvidia/src/kernel/gpu/disp/disp_channel.c b/src/nvidia/src/kernel/gpu/disp/disp_channel.c index 6ea87af444..9a2afb11fe 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_channel.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_channel.c @@ -126,7 +126,7 @@ dispchnConstruct_IMPL if (pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_USER_ROOT) { NV_PRINTF(LEVEL_ERROR, - "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", + "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", pParams->externalClassId); // @@ -182,7 +182,7 @@ dispchnConstruct_IMPL { rmStatus = kdispSetPushBufferParamsToPhysical_HAL(pGpu, pKernelDisplay, - pDispChannel, + pDispChannel, hObjectBuffer, pBufferContextDma, hClass, @@ -301,7 +301,7 @@ dispchnGrabChannel_IMPL { rmStatus = kdispSetPushBufferParamsToPhysical_HAL(pGpu, pKernelDisplay, - pDispChannel, + pDispChannel, hObjectBuffer, pBufferContextDma, hClass, diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c index d8a41f10f2..70c64f6f45 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -62,6 +62,7 @@ dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL staticCast(pDispCommon, DisplayApi), DISPAPI_GET_GPUGRP(pDispCommon), &pGpu, + NULL, pParams->mapTable[acpiIdx].subDeviceInstance); if (status != NV_OK) return status; @@ -97,6 +98,48 @@ dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL return status; } +NV_STATUS +dispcmnCtrlCmdSystemAcpiSubsystemActivated_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS *pParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + OBJOS *pOs = NULL; + NV_STATUS status = NV_OK; + + // client gave us a subdevice #: get right pGpu/pDisp for it + status = dispapiSetUnicastAndSynchronize_HAL( + staticCast(pDispCommon, DisplayApi), + DISPAPI_GET_GPUGRP(pDispCommon), + &pGpu, + NULL, + pParams->subDeviceInstance); + if (status != NV_OK) + { + return status; + } + + pOs = GPU_GET_OS(pGpu); + + pOs->setProperty(pOs, PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM, NV_FALSE); + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED, + NULL, 0); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "ERROR: NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED control call failed. " + "Should be rmapi ctrl call which is failed"); + } + + return status; +} + // // This rmctrl MUST NOT touch hw since it's tagged as NO_GPUS_ACCESS in ctrl0073.def // RM allow this type of rmctrl to go through when GPU is not available. @@ -200,7 +243,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_GPUON(pGpu, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_GPUON(pGpu, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF: @@ -212,7 +255,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_GPUOFF(pGpu, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_GPUOFF(pGpu, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA: @@ -327,8 +370,8 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET, sizeof(NvU32)); + outStatus = osCallACPI_LRST(pGpu, acpiId, (NvU32*) pInOutData); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_LRST(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID: @@ -685,7 +728,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON: { - outStatus = pOS->osCallACPI_OPTM_GPUON(pGpu); + outStatus = osCallACPI_OPTM_GPUON(pGpu); break; } default: diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c b/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c index 92a8bd6b80..969f525770 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -116,6 +116,7 @@ dispcmnCtrlCmdSystemAllocateDisplayBandwidth_IMPL staticCast(pDispCommon, DisplayApi), DISPAPI_GET_GPUGRP(pDispCommon), &pGpu, + NULL, pParams->subDeviceInstance); if (status != NV_OK) { @@ -147,6 +148,7 @@ dispcmnCtrlCmdDpGenerateFakeInterrupt_IMPL staticCast(pDispCommon, DisplayApi), DISPAPI_GET_GPUGRP(pDispCommon), &pGpu, + NULL, pParams->subDeviceInstance); if (status != NV_OK) { @@ -208,3 +210,57 @@ dispcmnCtrlCmdDpGenerateFakeInterrupt_IMPL return NV_OK; } + +NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams +) +{ + POBJGPU pGpu = DISPAPI_GET_GPU(pDispCommon); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pDispCommon); + NvHandle hParent = RES_GET_PARENT_HANDLE(pDispCommon); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(DISPAPI_GET_GPU(pDispCommon)); + NV_STATUS status = NV_OK; + + // Get the right pGpu from subdevice instance given by client + status = dispapiSetUnicastAndSynchronize_HAL( + staticCast(pDispCommon, DisplayApi), + DISPAPI_GET_GPUGRP(pDispCommon), + &pGpu, + NULL, + pParams->subDeviceInstance); + + if (status != NV_OK) + { + return status; + } + + if (pParams->bEnable) + { + status = memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemory); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memdescRegisterToGSP failed %d\n", status); + return status; + } + } + + status = pRmApi->Control(pRmApi, + hClient, + RES_GET_HANDLE(pDispCommon), + NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE, + pParams, + sizeof(*pParams)); + + if (!pParams->bEnable) + { + status = memdescDeregisterFromGSP(pGpu, hClient, hParent, pParams->hMemory); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memdescDeRegisterFromGSP failed %d\n", status); + } + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_objs.c b/src/nvidia/src/kernel/gpu/disp/disp_objs.c index 075b09d66b..bbd728101a 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_objs.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_objs.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -289,6 +289,7 @@ dispapiSetUnicastAndSynchronize_KERNEL DisplayApi *pDisplayApi, OBJGPUGRP *pGpuGroup, OBJGPU **ppGpu, + OBJDISP **ppDisp, NvU32 subDeviceInstance ) { @@ -300,6 +301,19 @@ dispapiSetUnicastAndSynchronize_KERNEL gpumgrSetBcEnabledStatus(*ppGpu, NV_FALSE); + // + // The _KERNEL version of this function is only called from Kernel RM, but + // in Kernel RM, OBJDISP is not available, so ppDisp must be NULL. If the + // caller needs to access OBJDISP, either the caller code must remove the + // OBJDISP dependency, or the caller code must be changed so that + // dispapiSetUnicastAndSynchronize is called only from physical or + // monolithic RM, never Kernel RM. + // + if (ppDisp != NULL) + { + return NV_ERR_INVALID_STATE; + } + return nvStatus; } @@ -375,6 +389,7 @@ dispapiControl_Prologue_IMPL status = dispapiSetUnicastAndSynchronize_HAL(pDisplayApi, pRmCtrlParams->pGpuGrp, &pRmCtrlParams->pGpu, + NULL, subdeviceIndex); if (status == NV_OK) @@ -469,7 +484,7 @@ dispcmnConstruct_IMPL ) { DisplayApi *pDisplayApi = staticCast(pDispCommon, DisplayApi); - + // // Not adding the priv-level check for this class // as it is being used by OpenGL from userspace.Once the Cleanup is done from the OpenGL diff --git a/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c b/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c similarity index 53% rename from src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c rename to src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c index 3988906e3e..598f9d3461 100644 --- a/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c +++ b/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c @@ -24,36 +24,84 @@ #include "gpu/disp/head/kernel_head.h" #include "published/disp/v04_00/dev_disp.h" -void kheadResetPendingVblank_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) +void kheadResetPendingVblank_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) { - NvU32 writeIntr = 0; + NvU32 writeIntr = GPU_REG_RD32(pGpu, NV_PDISP_FE_EVT_STAT_HEAD_TIMING(pKernelHead->PublicId)); writeIntr = DRF_DEF(_PDISP, _FE_EVT_STAT_HEAD_TIMING, _LAST_DATA, _RESET); GPU_REG_WR32(pGpu, NV_PDISP_FE_EVT_STAT_HEAD_TIMING(pKernelHead->PublicId), writeIntr); } -NvU32 kheadReadPendingVblank_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, NvU32 headIntrMask) +NvBool kheadReadPendingVblank_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, NvU32 *pCachedIntr, THREAD_STATE_NODE *pThreadState) { - NvU32 intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_DISPATCH); if (!FLD_IDX_TEST_DRF(_PDISP, _FE_RM_INTR_DISPATCH, _HEAD_TIMING, pKernelHead->PublicId, _PENDING, intr)) { - return headIntrMask; + return NV_FALSE; } intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(pKernelHead->PublicId)); if (FLD_TEST_DRF(_PDISP, _FE_EVT_STAT_HEAD_TIMING, _LAST_DATA, _PENDING, intr)) { - headIntrMask |= headIntr_vblank; + return NV_TRUE; } - if (headIntrMask & headIntr_vblank) + + return NV_FALSE; +} + +NvBool kheadGetDisplayInitialized_KERNEL +( + OBJGPU *pGpu, + KernelHead *pKernelHead +) +{ + NvU32 intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_CORE_HEAD_STATE(pKernelHead->PublicId)); + + if (DRF_VAL(_PDISP, _FE_CORE_HEAD_STATE, _OPERATING_MODE, intr)) { - return NVBIT(pKernelHead->PublicId); + return NV_TRUE; } - return headIntr_none; + return NV_FALSE; } +NvBool kheadReadVblankIntrEnable_KERNEL +( + OBJGPU *pGpu, + KernelHead *pKernelHead +) +{ + NvU32 intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(pKernelHead->PublicId)); + if (FLD_TEST_DRF(_PDISP, _FE_RM_INTR_EN_HEAD_TIMING, _LAST_DATA, _ENABLE, intr)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +void kheadWriteVblankIntrEnable_KERNEL +( + OBJGPU *pGpu, + KernelHead *pKernelHead, + NvBool bEnable +) +{ + NvU32 intrEn = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(pKernelHead->PublicId)); + + kheadResetPendingVblank_HAL(pGpu, pKernelHead, NULL); + + if (bEnable) + { + intrEn = FLD_SET_DRF(_PDISP, _FE_RM_INTR_EN_HEAD_TIMING, _LAST_DATA, _ENABLE, intrEn); + } + else + { + intrEn = FLD_SET_DRF(_PDISP, _FE_RM_INTR_EN_HEAD_TIMING, _LAST_DATA, _DISABLE, intrEn); + } + + GPU_REG_WR32(pGpu, NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(pKernelHead->PublicId), intrEn); +} diff --git a/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c b/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c index 6b8bfc1775..903e4913e8 100644 --- a/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c +++ b/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c @@ -25,9 +25,10 @@ #include "gpu/disp/head/kernel_head.h" #include "objtmr.h" -NV_STATUS +NV_STATUS kheadConstruct_IMPL(KernelHead *pKernelHead) { + pKernelHead->Vblank.IntrState = NV_HEAD_VBLANK_INTR_UNAVAILABLE; return NV_OK; } @@ -215,7 +216,7 @@ kheadCheckVblankCallbacksQueued_IMPL { if (kheadIsVblankCallbackDue(pCallback, state, time, vblankCount)) { - *expiring |= VBLANK_STATE_PROCESS_NORMAL_LATENCY; + *expiring |= VBLANK_STATE_PROCESS_NORMAL_LATENCY; } pCallback = pCallback->Next; @@ -239,10 +240,6 @@ kheadReadVblankIntrState_IMPL // HW is enabled, check if SW state is not enabled if (pKernelHead->Vblank.IntrState != NV_HEAD_VBLANK_INTR_ENABLED) { - NV_PRINTF(LEVEL_ERROR, - "Head %d: HW: %d != SW: %d! Fixing SW State...\n", - pKernelHead->PublicId, NV_HEAD_VBLANK_INTR_ENABLED, - pKernelHead->Vblank.IntrState); pKernelHead->Vblank.IntrState = NV_HEAD_VBLANK_INTR_ENABLED; } } @@ -272,9 +269,6 @@ kheadReadVblankIntrState_IMPL if (state != pKernelHead->Vblank.IntrState) { - NV_PRINTF(LEVEL_ERROR, - "Head %d: HW: %d != SW: %d! Fixing SW State...\n", - pKernelHead->PublicId, state, pKernelHead->Vblank.IntrState); pKernelHead->Vblank.IntrState = state; } } @@ -286,9 +280,6 @@ kheadReadVblankIntrState_IMPL // if (!kheadGetDisplayInitialized_HAL(pGpu, pKernelHead)) { - NV_PRINTF(LEVEL_ERROR, - "Head %d: HW: %d != SW: %d! Fixing SW State...\n", - pKernelHead->PublicId, NV_HEAD_VBLANK_INTR_UNAVAILABLE, pKernelHead->Vblank.IntrState); pKernelHead->Vblank.IntrState = NV_HEAD_VBLANK_INTR_UNAVAILABLE; } } diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index 7af80569a2..7b2730c8a8 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -46,6 +46,7 @@ #include "core/locks.h" #include "ctrl/ctrl402c.h" #include "platform/acpi_common.h" +#include "nvrm_registry.h" #include "kernel/gpu/intr/engine_idx.h" @@ -78,6 +79,9 @@ #include "gpu/disp/rg_line_callback/rg_line_callback.h" +#include "rmapi/rmapi_utils.h" +#include "class/cl0073.h" + NV_STATUS kdispConstructEngine_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay, @@ -204,6 +208,61 @@ kdispDestructKhead_IMPL } } +NV_STATUS +kdispAllocateCommonHandle_IMPL +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay +) +{ + NV_STATUS rmStatus; + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + NvHandle hSubscription = NV01_NULL_OBJECT; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + rmStatus = rmapiutilAllocClientAndDeviceHandles(pRmApi, pGpu, &hClient, + &hDevice, &hSubdevice); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); + + rmStatus = pRmApi->AllocWithSecInfo(pRmApi, hClient, hDevice, &hSubscription, + NV04_DISPLAY_COMMON, NULL, 0, RMAPI_ALLOC_FLAGS_NONE, + NULL, &pRmApi->defaultSecInfo); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); + + pKernelDisplay->hInternalClient = hClient; + pKernelDisplay->hInternalDevice = hDevice; + pKernelDisplay->hInternalSubdevice = hSubdevice; + pKernelDisplay->hDispCommonHandle = hSubscription; + + return NV_OK; +} + +void +kdispDestroyCommonHandle_IMPL +( + KernelDisplay *pKernelDisplay +) +{ + NV_STATUS rmStatus; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + rmStatus = pRmApi->FreeWithSecInfo(pRmApi, pKernelDisplay->hInternalClient, + pKernelDisplay->hDispCommonHandle, + RMAPI_ALLOC_FLAGS_NONE, &pRmApi->defaultSecInfo); + NV_ASSERT(rmStatus == NV_OK); + + rmapiutilFreeClientAndDeviceHandles(pRmApi, &pKernelDisplay->hInternalClient, + &pKernelDisplay->hInternalDevice, + &pKernelDisplay->hInternalSubdevice); + + pKernelDisplay->hInternalClient = 0; + pKernelDisplay->hInternalDevice = 0; + pKernelDisplay->hInternalSubdevice = 0; + pKernelDisplay->hDispCommonHandle = 0; +} + NV_STATUS kdispStatePreInitLocked_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay) @@ -216,7 +275,7 @@ kdispStatePreInitLocked_IMPL(OBJGPU *pGpu, if (!gpuFuseSupportsDisplay_HAL(pGpu)) return NV_ERR_NOT_SUPPORTED; - + status = pRmApi->Control(pRmApi, hClient, hSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION, &ctrlParams, sizeof(ctrlParams)); @@ -231,6 +290,10 @@ kdispStatePreInitLocked_IMPL(OBJGPU *pGpu, // NOTE: KernelDisplay IpVersion _HAL functions can only be called after this point. status = gpuInitDispIpHal(pGpu, ctrlParams.ipVersion); + kdispInitRegistryOverrides_HAL(pGpu, pKernelDisplay); + + kdispAllocateCommonHandle(pGpu, pKernelDisplay); + return status; } @@ -270,6 +333,78 @@ kdispInitBrightcStateLoad_IMPL(OBJGPU *pGpu, return status; } +NV_STATUS +kdispSetupAcpiEdid_IMPL +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay +) +{ + NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS *pEdidParams = NULL; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU32 status = NV_ERR_GENERIC; + NvU32 index; + + pEdidParams = portMemAllocNonPaged(sizeof(NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS)); + if (pEdidParams == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Could not allocate memory for pEdidParams\n"); + return NV_ERR_NO_MEMORY; + } + portMemSet(pEdidParams, 0, sizeof(*pEdidParams)); + + pEdidParams->tableLen = pGpu->acpiMethodData.dodMethodData.acpiIdListLen / sizeof(NvU32); + + for (index = 0; index < pEdidParams->tableLen; index++) + { + pEdidParams->edidTable[index].bufferSize = MAX_EDID_SIZE_FROM_SBIOS; + status = osCallACPI_DDC(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[index], + pEdidParams->edidTable[index].edidBuffer, + &pEdidParams->edidTable[index].bufferSize, NV_TRUE); + pEdidParams->edidTable[index].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[index]; + pEdidParams->edidTable[index].status = status; + } + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA, + pEdidParams, sizeof(*pEdidParams)); + + portMemFree(pEdidParams); + + return status; +} + +void +kdispInitRegistryOverrides_IMPL(OBJGPU *pGpu, + KernelDisplay *pKernelDisplay) +{ + NvU32 data32 = 0; + + if (pKernelDisplay == NULL) + { + return; + } + + if (NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_BUG_2089053_WAR, &data32)) + { + if (data32 == NV_REG_STR_RM_BUG_2089053_WAR_DISABLE) + { + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS, NV_FALSE); + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE, NV_FALSE); + } + else if (data32 == NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ALWAYS) + { + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS, NV_TRUE); + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE, NV_FALSE); + } + else if (data32 == NV_REG_STR_RM_BUG_2089053_WAR_ENABLE_ON_HMD_ACTIVE_ONLY) + { + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE, NV_TRUE); + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANK_ALWAYS, NV_FALSE); + } + } +} + NV_STATUS kdispStateInitLocked_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay) @@ -305,6 +440,14 @@ kdispStateInitLocked_IMPL(OBJGPU *pGpu, goto exit; } + // Set up ACPI DDC data in Physical RM for future usage + status = kdispSetupAcpiEdid_HAL(pGpu, pKernelDisplay); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, "rmapi control call for acpi child device init failed\n"); + goto exit; + } + if (pKernelDisplay->pInst != NULL) { NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -354,6 +497,8 @@ kdispStateDestroy_IMPL(OBJGPU *pGpu, portMemFree((void*) pKernelDisplay->pStaticInfo); pKernelDisplay->pStaticInfo = NULL; + + kdispDestroyCommonHandle(pKernelDisplay); } NV_STATUS @@ -407,7 +552,7 @@ kdispImportImpData_IMPL(KernelDisplay *pKernelDisplay) simulationMode = osGetSimulationMode(); if (simulationMode == NV_SIM_MODE_TEGRA_FPGA) { - pKernelDisplay->setProperty(pDisp, PDB_PROP_KDISP_IMP_ENABLE, NV_FALSE); + pKernelDisplay->setProperty(pKernelDisplay, PDB_PROP_KDISP_IMP_ENABLE, NV_FALSE); return NV_OK; } @@ -900,7 +1045,10 @@ kdispServiceVblank_KERNEL if (!unionNonEmptyQueues) { // all queues (belonging to heads with pending vblank ints) are empty. - kheadResetPendingVblankForKernel_HAL(pGpu, pKernelHead, pThreadState); + if (IS_GSP_CLIENT(pGpu)) + { + kheadResetPendingVblank_HAL(pGpu, pKernelHead, pThreadState); + } return; } @@ -939,7 +1087,10 @@ kdispServiceVblank_KERNEL for(i=0; i< OBJ_MAX_HEADS; i++) { pKernelHead = KDISP_GET_HEAD(pKernelDisplay, i); - kheadResetPendingVblankForKernel_HAL(pGpu, pKernelHead, pThreadState); + if (IS_GSP_CLIENT(pGpu)) + { + kheadResetPendingVblank_HAL(pGpu, pKernelHead, pThreadState); + } } } else @@ -958,19 +1109,21 @@ kdispServiceVblank_KERNEL return; } -NvU32 kdispReadPendingVblank_KERNEL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay, THREAD_STATE_NODE *pThreadState) +NvU32 kdispReadPendingVblank_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay, THREAD_STATE_NODE *pThreadState) { - KernelHead *pKernelHead; - NvU32 headIntrMask; - NvU32 pending = 0; - NvU8 headIdx; + KernelHead *pKernelHead; + NvU32 headIdx, pending = 0; - for(headIdx = 0; headIdx < OBJ_MAX_HEADS; headIdx++) + for (headIdx = 0; headIdx < kdispGetNumHeads(pKernelDisplay); headIdx++) { pKernelHead = KDISP_GET_HEAD(pKernelDisplay, headIdx); - headIntrMask = headIntr_none; - pending |= kheadReadPendingVblank_HAL(pGpu, pKernelHead, headIntrMask); + + if (kheadReadPendingVblank_HAL(pGpu, pKernelHead, NULL, pThreadState)) + { + pending |= NVBIT(headIdx); + } } + return pending; } diff --git a/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c b/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c index 4189d0a81b..a88042d639 100644 --- a/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c +++ b/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -55,6 +55,7 @@ _registerRgLineCallback status = dispapiSetUnicastAndSynchronize_HAL(staticCast(pRgLineCallback->pDispCommon, DisplayApi), DISPAPI_GET_GPUGRP(pRgLineCallback->pDispCommon), &pGpu, + NULL, pRgLineCallback->subDeviceInstance); if (status != NV_OK) return status; diff --git a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c index beda245796..a6ad53320f 100644 --- a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c +++ b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c @@ -286,7 +286,7 @@ kheadDeleteVblankCallback_IMPL } // Disable VBlank (if it is even on) while we scan/process the callback list - enabled = kheadReadVblankIntrEnable(pGpu, pKernelHead); + enabled = kheadReadVblankIntrEnable_HAL(pGpu, pKernelHead); if (enabled) { diff --git a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c index be59ebe099..b25363ac50 100644 --- a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c +++ b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -349,7 +349,7 @@ extdevSaveI2cHandles_P2060 NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); rmStatus = pRmApi->Alloc(pRmApi, hClient, hSubdevice, - &hSubscription, NV40_I2C, NULL); + &hSubscription, NV40_I2C, NULL, 0); NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); @@ -683,12 +683,12 @@ gsyncAttachExternalDevice_P2060 connector = iface + 1; // - // If adding a check before the gsyncAttachGpu call and returning before + // If adding a check before the gsyncAttachGpu call and returning before // that please add the following code: // pThis->gpuAttachMask &= ~NVBIT(pGpu->gpuInstance); // (*ppExtdevs)->ReferenceCount--; - // before returning NV_FALSE so that the caller can destroy the - // ext device structure. The destroy funciton only decrements the ref count + // before returning NV_FALSE so that the caller can destroy the + // ext device structure. The destroy funciton only decrements the ref count // if the gpu has already been attached. // (*ppExtdevs)->ReferenceCount++; @@ -2073,15 +2073,11 @@ gsyncReadHouseSignalPresent_P2060 /* * This function returns whether there is a sync source present. * - * SYNC_LOSS bit in STATUS register is true by default, i.e when there - * is no incoming sync source. This bit is unset when a stable sync - * source is detected. + * If framelock is not enabled, the only sync source possible is an external signal. * - * Whenever framelock is enabled, NV_TRUE is returned only when the incoming - * sync source is stable. Therefore it is sent based on the software state. - * - * When framelock is not enabled, return value totally depends on the value - * of the gsync STATUS register. + * If framelock is enabled, a local master may be providing the sync signal, or + * housesync may be providing a signal via a local master, or we may need to + * poll for an external signal. */ static NV_STATUS gsyncReadIsSyncDetected_P2060 @@ -2092,8 +2088,11 @@ gsyncReadIsSyncDetected_P2060 ) { PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; - NV_STATUS rmStatus = NV_OK; - NvU32 iface; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + + // Assume we are not synced, unless we match one of the cases below + *pVal = NV_FALSE; NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); @@ -2101,30 +2100,90 @@ gsyncReadIsSyncDetected_P2060 { NvU8 regStatus; - // framelock is not enabled, read the NV_P2060_STATUS register to get the SYNC status - rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, (NvU8)NV_P2060_STATUS, ®Status); - - if (rmStatus == NV_OK) - { - *pVal = (NV_P2060_STATUS_SYNC_LOSS_TRUE != DRF_VAL(_P2060, _STATUS, _SYNC_LOSS, regStatus)); - } + // + // Framelock is not enabled; read the NV_P2060_STATUS register to get + // the external sync status + // + NV_ASSERT_OK_OR_RETURN( + readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS, ®Status)); + *pVal = FLD_TEST_DRF(_P2060, _STATUS, _SYNC_LOSS, _FALSE, regStatus); } else { - rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); - if (NV_OK != rmStatus) + NvU32 iface, head, tempIface, tempHead; + + NV_ASSERT_OK_OR_RETURN(GetP2060GpuLocation(pGpu, pThis, &iface)); + + + for (head = 0; head < numHeads; head++) { - return rmStatus; - } + // Check if we're slaved to another master head in the same system + if (pThis->Iface[iface].Sync.LocalSlave[head]) + { + for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) + { + for (tempHead = 0; tempHead < numHeads; tempHead++) + { + if (pThis->Iface[tempIface].Sync.Master[tempHead]) + { + // + // If we're slaved to another local head, we are + // receiving a sync signal from it. (But if it uses + // housesync, then it must also be receiving housesync.) + // + if (!pThis->Iface[tempIface].Sync.Slaved[tempHead]) + { + *pVal = NV_TRUE; + } + else + { + NV_ASSERT_OK_OR_RETURN( + gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, + NV_TRUE, pVal)); + } + } + } + } + break; + } - // - // Sync gain should only be derived from our internal tracking variable. - // The gsync status variables are reporting more transient data than desired. - // - *pVal = pThis->Iface[iface].gainedSync; + if (pThis->Iface[iface].Sync.Master[head]) + { + // + // A master head with no house signal has its own sync signal. + // A master head with house signal has a sync signal if the + // house signal is present. + // + if (pThis->Iface[iface].Sync.Slaved[head]) + { + NV_ASSERT_OK_OR_RETURN( + gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, NV_TRUE, pVal)); + break; + } + else + { + *pVal = NV_TRUE; + break; + } + } + + if (pThis->Iface[iface].Sync.Slaved[head]) + { + NvU8 regStatus; + + // + // A slaved head with external master signal must poll + // NV_P2060_STATUS_SYNC_LOSS for sync status. + // + NV_ASSERT_OK_OR_RETURN( + readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS, ®Status)); + *pVal = FLD_TEST_DRF(_P2060, _STATUS, _SYNC_LOSS, _FALSE, regStatus); + break; + } + } } - return rmStatus; + return NV_OK; } /* @@ -2191,41 +2250,12 @@ gsyncReadStereoLocked_P2060 return rmStatus; } -/* - * Check if VCXO is locked or not. - */ -static NV_STATUS -gsyncReadVCXOLocked_P2060 -( - OBJGPU *pGpu, - PDACEXTERNALDEVICE pExtDev, - NvU32 *pVal -) -{ - PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; - NV_STATUS rmStatus = NV_OK; - NvU32 regStatus = GetP2060GpuSnapshot(pGpu,pThis); - - // Status1 only needs to be read if the shapshot shows recent error or no vcxo lock - if (!FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _LOCK, regStatus)) - { - rmStatus = gsyncUpdateGsyncStatusSnapshot_P2060(pGpu, pExtDev); - if ( NV_OK == rmStatus ) - { - *pVal = FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _LOCK, GetP2060GpuSnapshot(pGpu,pThis)); - } - } - else - { - *pVal = 1; //VCXO is locked. - } - - return rmStatus; -} - -/* - * Check if timing is present or not. - */ +// +// Check if we are in sync, i.e. we supply the master sync signal or are servoed +// to the master sync signal. The servo should be stable for about 5 seconds if +// the signal is external (i.e. use the gainedSync value which already maintains +// this.) +// static NV_STATUS gsyncReadIsTiming_P2060 ( @@ -2235,73 +2265,15 @@ gsyncReadIsTiming_P2060 ) { PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; - NV_STATUS rmStatus = NV_OK; - KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); - NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); - NvU32 bHouse, bLock = 0, bSync; - NvU32 iface, head, tempIface, tempHead; - - rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); - if (NV_OK != rmStatus) - { - return rmStatus; - } - - // assume no, unless we find something below - *pVal = (NvU32)NV_FALSE; + NvU32 iface; - for (head = 0; head < numHeads; head++) - { - // check if we're slaved to another master head in the same system - if (pThis->Iface[iface].Sync.LocalSlave[head]) - { - for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) - { - for (tempHead = 0; tempHead < numHeads; tempHead++) - { - if (pThis->Iface[tempIface].Sync.Master[tempHead]) - { - // assume that if we're slaved to another local head - // that we're in sync. there's no easy way to verify - // this, short of trying to compare raster scanlines - *pVal = (NvU32)NV_TRUE; - } - } - } - break; - } + *pVal = NV_FALSE; - // check if we have a master, connected to a house sync - if (pThis->Iface[iface].Sync.Master[head] && pThis->Iface[iface].Sync.Slaved[head]) - { - rmStatus |= gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, NV_TRUE, &bHouse); - if ( NV_OK == rmStatus ) - { - *pVal = (NvU32)(bHouse); - } - break; - } + NV_ASSERT_OK_OR_RETURN(GetP2060GpuLocation(pGpu, pThis, &iface)); - // check if we have a master head, not connected to house sync - if (pThis->Iface[iface].Sync.Master[head]) - { - // a master is by definition always in sync - *pVal = (NvU32)NV_TRUE; - break; - } + *pVal = pThis->Iface[iface].gainedSync; - if (pThis->Iface[iface].Sync.Slaved[head]) - { - rmStatus |= gsyncReadIsSyncDetected_P2060(pGpu, pExtDev, &bSync); - rmStatus |= gsyncReadVCXOLocked_P2060(pGpu, pExtDev, &bLock); - if ( NV_OK == rmStatus ) - { - *pVal = (NvU32)(bSync && bLock); - } - break; - } - } - return rmStatus; + return NV_OK; } @@ -5431,7 +5403,7 @@ isFirmwareRevMismatch /* * Nvlink and QSync can both transmit inter-GPU Display sync signals. - * Contention in these signals is observed on some boards, if both Nvlink and + * Contention in these signals is observed on some boards, if both Nvlink and * QSync are present between the boards. * * Returns TRUE if contention in transmission of sync signals possible on the diff --git a/src/nvidia/src/kernel/gpu/external_device/gsync.c b/src/nvidia/src/kernel/gpu/external_device/gsync.c index 0b4a008ab4..015ddeea52 100644 --- a/src/nvidia/src/kernel/gpu/external_device/gsync.c +++ b/src/nvidia/src/kernel/gpu/external_device/gsync.c @@ -241,7 +241,7 @@ gsyncP2060StartupProvider(OBJGSYNC *pGsync) // Constants to be returned in NV30F1_CTRL_GSYNC_GET_CAPS p2060->syncSkewResolutionInNs = NV_P2060_SYNC_SKEW_RESOLUTION; - p2060->syncSkewMax = gsyncSupportsLargeSyncSkew_P2060(pExtDev) ? + p2060->syncSkewMax = gsyncSupportsLargeSyncSkew_P2060(pExtDev) ? NV_P2060_SYNC_SKEW_MAX_UNITS_FULL_SUPPORT : NV_P2060_SYNC_SKEW_MAX_UNITS_LIMITED_SUPPORT; diff --git a/src/nvidia/src/kernel/gpu/external_device/gsync_api.c b/src/nvidia/src/kernel/gpu/external_device/gsync_api.c index d2508e45cc..7d0c3ccb07 100644 --- a/src/nvidia/src/kernel/gpu/external_device/gsync_api.c +++ b/src/nvidia/src/kernel/gpu/external_device/gsync_api.c @@ -159,7 +159,7 @@ CliNotifyGsyncEvent // Syncloss could also be a notifcation to reset the // event notification tracking when enabling framelock. // - if ((NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS == oldEventFlags) && + if ((NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS == oldEventFlags) && (pEventNotification == NULL)) { // update smart event notification tracking when diff --git a/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c b/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c index f9b11a8bdd..4490443ddd 100644 --- a/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c +++ b/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c @@ -227,7 +227,7 @@ writeregu008_extdevice NvU8 Data ) { - + NV_STATUS status = NV_ERR_GENERIC; NvU32 i2cPort = (pGpu->i2cPortForExtdev < NV402C_CTRL_NUM_I2C_PORTS) ? pGpu->i2cPortForExtdev : pThis->I2CPort; @@ -282,7 +282,7 @@ readregu008_extdevice NvU8 *pData ) { - + NV_STATUS status = NV_ERR_GENERIC; NvU32 i2cPort = (pGpu->i2cPortForExtdev < NV402C_CTRL_NUM_I2C_PORTS) ? pGpu->i2cPortForExtdev : pThis->I2CPort; diff --git a/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c b/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c index 437c1a70d8..02b30e18df 100644 --- a/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c +++ b/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -173,7 +173,7 @@ kflcnSecureReset_TU102 KernelFalcon *pKernelFlcn ) { - NV_ASSERT_OR_RETURN_VOID(kflcnPreResetWait(pGpu, pKernelFlcn) == NV_OK); + NV_ASSERT_OR_RETURN_VOID(kflcnPreResetWait_HAL(pGpu, pKernelFlcn) == NV_OK); NV_ASSERT_OK(kflcnResetHw(pGpu, pKernelFlcn)); kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn); @@ -207,7 +207,7 @@ kflcnEnable_TU102 } else { - kflcnSecureReset(pGpu, pKernelFlcn); + kflcnSecureReset_HAL(pGpu, pKernelFlcn); } } else @@ -223,7 +223,7 @@ kflcnEnable_TU102 } else { - kflcnSecureReset(pGpu, pKernelFlcn); + kflcnSecureReset_HAL(pGpu, pKernelFlcn); } kflcnSwitchToFalcon_HAL(pGpu, pKernelFlcn); diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c index 5c595b9080..4a347c436b 100644 --- a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,6 +30,7 @@ #include "gpu/fifo/kernel_channel_group_api.h" #include "gpu/intr/intr.h" #include "gpu/subdevice/subdevice.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" #include "mem_mgr/gpu_vaspace.h" #include "mem_mgr/ctx_buf_pool.h" @@ -96,7 +97,6 @@ static NV_STATUS _kflcnAllocAndMapCtxBuffer CTX_BUF_POOL_INFO *pCtxBufPool = NULL; KernelChannelGroup *pKernelChannelGroup = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup; OBJGVASPACE *pGVAS = dynamicCast(pKernelChannel->pVAS, OBJGVASPACE); - NvU8 *pInstMem; NV_STATUS status = NV_OK; NvU64 flags = MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE; @@ -135,22 +135,10 @@ static NV_STATUS _kflcnAllocAndMapCtxBuffer memdescAllocList(pCtxMemDesc, memdescU32ToAddrSpaceList(pKernelFalcon->addrSpaceList)), done); - pInstMem = memdescMapInternal(pGpu, pCtxMemDesc, 0); - if (pInstMem != NULL) - { - // Clear the engine context buffer - NvU32 i; - for (i = 0; i < pKernelFalcon->ctxBufferSize; i += 4) - { - MEM_WR32(pInstMem + i, 0); - } - memdescUnmapInternal(pGpu, pCtxMemDesc, 0); - } - else - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto done; - } + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemDescMemSet(GPU_GET_MEMORY_MANAGER(pGpu), pCtxMemDesc, 0, + TRANSFER_FLAGS_NONE), + done); NV_ASSERT_OK_OR_GOTO(status, kchannelSetEngineContextMemDesc(pGpu, pKernelChannel, pKernelFalcon->physEngDesc, pCtxMemDesc), @@ -183,17 +171,16 @@ static NV_STATUS _kflcnPromoteContext RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); RsClient *pClient = RES_GET_CLIENT(pKernelChannel); Subdevice *pSubdevice; - NvU64 addr; RM_ENGINE_TYPE rmEngineType; ENGINE_CTX_DESCRIPTOR *pEngCtx; NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS rmCtrlParams = {0}; + OBJGVASPACE *pGVAS = dynamicCast(pKernelChannel->pVAS, OBJGVASPACE); NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); NV_ASSERT_OR_RETURN(gpumgrGetSubDeviceInstanceFromGpu(pGpu) == 0, NV_ERR_INVALID_STATE); pEngCtx = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->ppEngCtxDesc[0]; NV_ASSERT_OR_RETURN(pEngCtx != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OK_OR_RETURN(vaListFindVa(&pEngCtx->vaList, pKernelChannel->pVAS, &addr)); NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), ENGINE_INFO_TYPE_ENG_DESC, pKernelFalcon->physEngDesc, @@ -202,11 +189,65 @@ static NV_STATUS _kflcnPromoteContext rmCtrlParams.hClient = pClient->hClient; rmCtrlParams.hObject = RES_GET_HANDLE(pKernelChannel); rmCtrlParams.hChanClient = pClient->hClient; - rmCtrlParams.virtAddress = addr; rmCtrlParams.size = pKernelFalcon->ctxBufferSize; rmCtrlParams.engineType = gpuGetNv2080EngineType(rmEngineType); rmCtrlParams.ChID = pKernelChannel->ChID; + // Promote physical address only. VA will be promoted later as part of nvgpuBindChannelResources + if (gvaspaceIsExternallyOwned(pGVAS)) + { + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvU32 physAttr = 0x0; + + NV_ASSERT_OK_OR_RETURN(kchangrpGetEngineContextMemDesc(pGpu, + pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup, &pMemDesc)); + NV_ASSERT_OR_RETURN(memdescGetContiguity(pMemDesc, AT_GPU), NV_ERR_INVALID_STATE); + + switch (memdescGetAddressSpace(pMemDesc)) + { + case ADDR_FBMEM: + physAttr = FLD_SET_DRF(2080, _CTRL_GPU_INITIALIZE_CTX, + _APERTURE, _VIDMEM, physAttr); + break; + + case ADDR_SYSMEM: + if (memdescGetCpuCacheAttrib(pMemDesc) == NV_MEMORY_CACHED) + { + physAttr = FLD_SET_DRF(2080, _CTRL_GPU_INITIALIZE_CTX, + _APERTURE, _COH_SYS, physAttr); + } + else if (memdescGetCpuCacheAttrib(pMemDesc) == NV_MEMORY_UNCACHED) + { + physAttr = FLD_SET_DRF(2080, _CTRL_GPU_INITIALIZE_CTX, + _APERTURE, _NCOH_SYS, physAttr); + } + else + { + return NV_ERR_INVALID_STATE; + } + break; + + default: + return NV_ERR_INVALID_STATE; + } + + physAttr = FLD_SET_DRF(2080, _CTRL_GPU_INITIALIZE_CTX, _GPU_CACHEABLE, _NO, physAttr); + + rmCtrlParams.entryCount = 1; + rmCtrlParams.promoteEntry[0].gpuPhysAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + rmCtrlParams.promoteEntry[0].size = pMemDesc->Size; + rmCtrlParams.promoteEntry[0].physAttr = physAttr; + rmCtrlParams.promoteEntry[0].bufferId = 0; // unused for flcn + rmCtrlParams.promoteEntry[0].bInitialize = NV_TRUE; + rmCtrlParams.promoteEntry[0].bNonmapped = NV_TRUE; + } + else + { + NvU64 addr; + NV_ASSERT_OK_OR_RETURN(vaListFindVa(&pEngCtx->vaList, pKernelChannel->pVAS, &addr)); + rmCtrlParams.virtAddress = addr; + } + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pClient->hClient, RES_GET_HANDLE(pSubdevice), NV2080_CTRL_CMD_GPU_PROMOTE_CTX, &rmCtrlParams, sizeof(rmCtrlParams))); diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c new file mode 100644 index 0000000000..16a7fdd7b8 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c @@ -0,0 +1,243 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "gpu/falcon/kernel_falcon.h" +#include "gpu/nvlink/kernel_nvlink.h" +#include "gpu/fifo/kernel_fifo.h" +#include "gpu/fifo/kernel_channel.h" +#include "gpu/fifo/kernel_channel_group.h" +#include "gpu/fifo/kernel_channel_group_api.h" +#include "gpu/subdevice/subdevice.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "vgpu/rpc.h" +#include "ctrl/ctrl2080/ctrl2080flcn.h" + +NV_STATUS subdeviceCtrlCmdFlcnGetCtxBufferInfo_IMPL +( Subdevice *pSubdevice, + NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *pParams +) +{ + POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + PMEMORY_DESCRIPTOR pMemDesc, pRootMemDesc; + RsClient *pUserClient; + KernelChannel *pKernelChannel = NULL; + NV_STATUS status = NV_OK; + NvU64 pageSize; + NvU8 *pUuid = NULL; + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to get context buffers information. + // + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + serverGetClientUnderLock(&g_resServ, pParams->hUserClient, &pUserClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + CliGetKernelChannel(pUserClient, pParams->hChannel, &pKernelChannel)); + NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); + + switch (kchannelGetEngineType(pKernelChannel)) + { + case RM_ENGINE_TYPE_SEC2: + { + break; + } + default: + { + return NV_ERR_NOT_SUPPORTED; + } + } + + NV_ASSERT_OK_OR_RETURN(kchangrpGetEngineContextMemDesc(pGpu, pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup, &pMemDesc)); + pRootMemDesc = memdescGetRootMemDesc(pMemDesc, NULL); + + pParams->bufferHandle = NV_PTR_TO_NvP64(pMemDesc); + pParams->bIsContigous = memdescGetContiguity(pMemDesc, AT_GPU); + pParams->aperture = memdescGetAddressSpace(pMemDesc); + pParams->pageCount = pMemDesc->PageCount; + pParams->kind = memdescGetPteKindForGpu(pMemDesc, pMemDesc->pGpu); + + { + NvU64 physAddr; + GMMU_APERTURE aperture = kgmmuGetExternalAllocAperture(pParams->aperture); + + memdescGetPhysAddrsForGpu(pMemDesc, pMemDesc->pGpu, + AT_GPU, 0, 0, 1, + &physAddr); + + pParams->physAddr = + kgmmuEncodePhysAddr(GPU_GET_KERNEL_GMMU(pMemDesc->pGpu), aperture, physAddr, NVLINK_INVALID_FABRIC_ADDR); + } + + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + if (pageSize == 0) + { + status = memmgrSetMemDescPageSize_HAL(pMemDesc->pGpu, + GPU_GET_MEMORY_MANAGER(pMemDesc->pGpu), + pMemDesc, + AT_GPU, + RM_ATTR_PAGE_SIZE_DEFAULT); + if (status != NV_OK) + return status; + + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NV_ASSERT(pageSize != 0); + } + + // + // Alignment is used to adjust the mapping VA. Hence, we need to make sure + // that it is at least pageSize to make mapping calculation work correctly. + // + pParams->alignment = (pMemDesc->Alignment != 0) ? + NV_ALIGN_UP(pMemDesc->Alignment, pageSize) : pageSize; + + pParams->size = pMemDesc->ActualSize; + + NV_ASSERT_OR_RETURN(pageSize <= NV_U32_MAX, NV_ERR_INVALID_STATE); + pParams->pageSize = (NvU32)pageSize; + + pParams->bDeviceDescendant = pRootMemDesc->pGpu != NULL; + + if (pParams->bDeviceDescendant) + { + NvU32 flags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY); + NvU32 uuidLength; + // allocates memory for pUuid on success + NV_ASSERT_OK_OR_RETURN(gpuGetGidInfo(pGpu, &pUuid, &uuidLength, flags)); + if (uuidLength == sizeof(pParams->uuid)) + portMemCopy(pParams->uuid, uuidLength, pUuid, uuidLength); + else + { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } + +done: + portMemFree(pUuid); + return status; +} + +NV_STATUS +subdeviceCtrlCmdFlcnGetCtxBufferSize_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *pParams +) +{ + POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + PMEMORY_DESCRIPTOR pMemDesc; + KernelChannel *pKernelChannel = NULL; + NV_STATUS status = NV_OK; + NvU64 alignment; + NvU64 pageSize; + NvU64 totalBufferSize; + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to fetch the engine context buffer size. + // + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + CliGetKernelChannel(RES_GET_CLIENT(pSubdevice), pParams->hChannel, + &pKernelChannel)); + NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); + + switch (kchannelGetEngineType(pKernelChannel)) + { + case RM_ENGINE_TYPE_SEC2: + { + break; + } + default: + { + return NV_ERR_NOT_SUPPORTED; + } + } + + NV_ASSERT_OK_OR_RETURN(kchangrpGetEngineContextMemDesc(pGpu, pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup, &pMemDesc)); + + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + if (pageSize == 0) + { + status = memmgrSetMemDescPageSize_HAL(pMemDesc->pGpu, + GPU_GET_MEMORY_MANAGER(pMemDesc->pGpu), + pMemDesc, + AT_GPU, + RM_ATTR_PAGE_SIZE_DEFAULT); + if (status != NV_OK) + return status; + + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NV_ASSERT(pageSize != 0); + } + + // + // Adjust the total size by adding the alignment so that the mapping VA can + // be adjusted. + // + alignment = (pMemDesc->Alignment != 0) ? NV_ALIGN_UP(pMemDesc->Alignment, pageSize) : pageSize; + totalBufferSize = 0; + totalBufferSize += alignment; + totalBufferSize += (alignment != 0) ? NV_ALIGN_UP(pMemDesc->ActualSize, alignment) : pMemDesc->ActualSize; + pParams->totalBufferSize = totalBufferSize; + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c index de66191eff..7e3a888df0 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,9 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/fifo/kernel_channel_group_api.h" #include "kernel/gpu/fifo/kernel_channel_group.h" diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c index cd534d93be..0c9872ad46 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c @@ -24,6 +24,7 @@ #include "kernel/gpu/fifo/kernel_fifo.h" #include "published/hopper/gh100/dev_vm.h" #include "kernel/gpu/mem_mgr/virt_mem_allocator.h" +#include "gpu/mem_mgr/mem_mgr.h" /*! * Checks the USERD and GPFIFO/PushBuffer location attributes @@ -77,38 +78,49 @@ kfifoGetCtxBufferMapFlags_GH100 return; } -/*! - * @brief Get offset to create GMMU internal MMIO mapping with for access to VF Pages. +/* + * Allocate Memory Descriptors for BAR1 VF pages * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelFifo KernelFifo pointer - * @param[in] bPriv Whether PRIV offset or regular VF offset is desired + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFifo KernelFifo pointer */ -NvU64 -kfifoGetMmioUsermodeOffset_GH100 +NV_STATUS +kfifoConstructUsermodeMemdescs_GH100 ( OBJGPU *pGpu, - KernelFifo *pKernelFifo, - NvBool bPriv + KernelFifo *pKernelFifo ) { - return bPriv ? DRF_BASE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_BASE(NV_VIRTUAL_FUNCTION); -} + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU32 attr = 0; + NvU32 attr2 = 0; + NvU32 i = 0; + NV_STATUS status = NV_OK; -/*! - * @brief Get size of either one of the VF pages, for use with GMMU internal MMIO mapping. - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelFifo KernelFifo pointer - * @param[in] bPriv Whether PRIV size or regular VF size is desired - */ -NvU64 -kfifoGetMmioUsermodeSize_GH100 -( - OBJGPU *pGpu, - KernelFifo *pKernelFifo, - NvBool bPriv -) -{ - return bPriv ? DRF_SIZE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_SIZE(NV_VIRTUAL_FUNCTION); + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); + + attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2 ); + + for(i = 0; i < 2; i++) + { + NvBool bPriv = (i==0); + NvU64 offset = bPriv ? DRF_BASE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_BASE(NV_VIRTUAL_FUNCTION); + NvU64 size = bPriv ? DRF_SIZE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_SIZE(NV_VIRTUAL_FUNCTION); + MEMORY_DESCRIPTOR **ppMemDesc = bPriv ? &(pKernelFifo->pBar1PrivVF) : &(pKernelFifo->pBar1VF); + NV_ASSERT_OK_OR_GOTO(status, + memCreateMemDesc(pGpu, ppMemDesc, ADDR_SYSMEM, offset, size, attr, attr2), + err); + memdescSetPteKind(*ppMemDesc, memmgrGetMessageKind_HAL(pGpu, pMemoryManager)); + memdescSetFlag(*ppMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1, NV_TRUE); + } + + NV_ASSERT_OK_OR_GOTO(status, + kfifoConstructUsermodeMemdescs_GV100(pGpu, pKernelFifo), + err); + return NV_OK; +err: + memdescDestroy(pKernelFifo->pBar1VF); + memdescDestroy(pKernelFifo->pBar1PrivVF); + return status; } diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c deleted file mode 100644 index 43f8ea4511..0000000000 --- a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gpu/mem_mgr/mem_mgr.h" -#include "kernel/gpu/fifo/usermode_api.h" -#include "kernel/gpu/fifo/kernel_fifo.h" -#include "kernel/gpu/bus/kern_bus.h" - -#include "class/clc661.h" // HOPPER_USERMODE_A -#include "class/cl003e.h" // NV01_MEMORY_SYSTEM -#include "class/cl003f.h" // NV01_MEMORY_LOCAL_PRIVILEGED - -NV_STATUS -usrmodeConstructHal_GH100 -( - UserModeApi *pUserModeApi, - CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams -) -{ - Memory *pMemory = staticCast(pUserModeApi, Memory); - NvU32 hClass = pCallContext->pResourceRef->externalClassId; - NvBool bBar1Mapping = NV_FALSE; - NvBool bPriv = NV_FALSE; - NV_HOPPER_USERMODE_A_PARAMS *pAllocParams = (NV_HOPPER_USERMODE_A_PARAMS*)pParams->pAllocParams; - NV_STATUS status = NV_OK; - MEMORY_DESCRIPTOR *pMemDesc = NULL; - OBJGPU *pGpu = pMemory->pGpu; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU64 offset = 0; - NvU32 size = 0; - NvU32 attr = 0; - NvU32 attr2 = 0; - - attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); - attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); - - attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2 ); - - if (hClass >= HOPPER_USERMODE_A && pAllocParams != NULL) - { - bBar1Mapping = pAllocParams->bBar1Mapping; - bPriv = pAllocParams->bPriv; - } - - // BAR1/2 is not used on coherent platforms like SHH, so use BAR0 path instead - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) - { - bBar1Mapping = NV_FALSE; - } - - // - // If we are in inst_in_sys mode, BAR1 page tables are not used so we cannot - // support internal MMIO for work submission. - // It is safe to return BAR0 mapping here because USERD cannot be in vidmem - // anyway so UMDs can use this mapping transparently. - // TODO: we should rename bBar1Mapping to accommodate cases where RM - // transparently gives out BAR0 mappings instead. - // - if (bBar1Mapping && pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) - { - NV_ASSERT_OR_RETURN(kbusIsBar1PhysicalModeEnabled(pKernelBus), - NV_ERR_INVALID_STATE); - bBar1Mapping = NV_FALSE; - } - - if (bPriv && pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - { - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - - NV_ASSERT_OK_OR_RETURN(kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, &offset, &size)); - - if (bBar1Mapping) - { - offset = kfifoGetMmioUsermodeOffset_HAL(pGpu, pKernelFifo, bPriv); - size = kfifoGetMmioUsermodeSize_HAL(pGpu, pKernelFifo, bPriv); - } - - status = memCreateMemDesc(pGpu, &pMemDesc, bBar1Mapping ? ADDR_SYSMEM : ADDR_REGMEM, - offset, size, attr, attr2); - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); - - if (bBar1Mapping) - { - memdescSetPteKind(pMemDesc, memmgrGetMessageKind_HAL(pGpu, pMemoryManager)); - memdescSetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1, NV_TRUE); - } - else - { - memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK, NV_TRUE); - } - - status = memConstructCommon(pMemory, bBar1Mapping? NV01_MEMORY_SYSTEM : NV01_MEMORY_LOCAL_PRIVILEGED, - 0, pMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL); - - return status; -} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c index d05d4bf764..44908b7c84 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c @@ -1290,7 +1290,7 @@ kfifoPreAllocUserD_GM107 // Now BAR1 map it status = kbusMapFbAperture_HAL(pGpu, pKernelBus, pUserdInfo->userdPhysDesc[currentGpuInst], 0, &pUserdInfo->userdBar1MapStartOffset, - &temp, mapFlags | BUS_MAP_FB_FLAGS_PRE_INIT, NV01_NULL_OBJECT); + &temp, mapFlags | BUS_MAP_FB_FLAGS_PRE_INIT, NULL); } if (status != NV_OK) diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c index 9051685d5e..f370a58c99 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,14 +43,15 @@ kchangrpAllocFaultMethodBuffers_GV100 NV_STATUS status = NV_OK; NvU32 bufSizeInBytes = 0; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU32 runQueues = kfifoGetNumRunqueues_HAL(pGpu, pKernelFifo); NvU32 index = 0; NvU32 faultBufApert = ADDR_SYSMEM; NvU32 faultBufAttr = NV_MEMORY_CACHED; - NvU8 *pRmMapAddr = NULL; NvU64 memDescFlags = MEMDESC_FLAGS_LOST_ON_SUSPEND; HW_ENG_FAULT_METHOD_BUFFER *pFaultMthdBuf = NULL; NvU32 gfid = pKernelChannelGroup->gfid; + TRANSFER_SURFACE surf = {0}; // // Allocate method buffer if applicable @@ -122,21 +123,12 @@ kchangrpAllocFaultMethodBuffers_GV100 memdescSetName(pGpu, pFaultMthdBuf->pMemDesc, NV_RM_SURF_NAME_CE_FAULT_METHOD_BUFFER, NULL); - // Map the buffer to RM - pRmMapAddr = kbusMapRmAperture_HAL(pGpu, pFaultMthdBuf->pMemDesc); - if (!pRmMapAddr) - { - status = NV_ERR_INVALID_ADDRESS; - goto fail; - } - - // Memset to 0 - portMemSet(pRmMapAddr, 0, bufSizeInBytes); + surf.pMemDesc = pFaultMthdBuf->pMemDesc; + surf.offset = 0; - // Unmap the buffer from RM - kbusUnmapRmAperture_HAL(pGpu, pFaultMthdBuf->pMemDesc, &(pRmMapAddr), - NV_TRUE); - pRmMapAddr = NULL; + NV_ASSERT_OK_OR_RETURN( + memmgrMemSet(pMemoryManager, &surf, 0, bufSizeInBytes, + TRANSFER_FLAGS_NONE)); pFaultMthdBuf->bar2Addr = 0; } diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c index 4188a9ff2b..c6d02ecb48 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c @@ -170,7 +170,7 @@ kchannelCreateUserdMemDesc_GV100 NvU32 userdAddrLo; NvU32 userdAddrHi; NvU32 userdAlignment; - NvU32 pageSize; + NvU64 pageSize; NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); pKernelChannel->pUserdSubDeviceMemDesc[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] = NULL; diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c index eab81f5b02..ba52fdd3df 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c @@ -28,6 +28,7 @@ #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/rmapi/rmapi.h" #include "kernel/gpu/gpu.h" +#include "kernel/mem_mgr/mem.h" #include "nvRmReg.h" @@ -336,3 +337,36 @@ kfifoGetMaxCeChannelGroups_GV100 return numChannels; } + +/* + * Allocate Memory Descriptors for Regmem VF page + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFifo KernelFifo pointer + */ +NV_STATUS +kfifoConstructUsermodeMemdescs_GV100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo +) +{ + NvU32 attr = 0; + NvU32 attr2 = 0; + NvU64 offset = 0; + NvU32 size = 0; + + attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); + attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); + + attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2); + + NV_ASSERT_OK_OR_RETURN(kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, &offset, &size)); + + NV_ASSERT_OK_OR_RETURN(memCreateMemDesc(pGpu, &(pKernelFifo->pRegVF), ADDR_REGMEM, + offset, size, attr, attr2)); + + memdescSetFlag(pKernelFifo->pRegVF, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK, NV_TRUE); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c deleted file mode 100644 index 5d30b7d4e9..0000000000 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "kernel/gpu/fifo/usermode_api.h" -#include "kernel/gpu/fifo/kernel_fifo.h" - -#include "class/cl003e.h" // NV01_MEMORY_SYSTEM -#include "class/cl003f.h" // NV01_MEMORY_LOCAL_PRIVILEGED - -NV_STATUS -usrmodeConstructHal_GV100 -( - UserModeApi *pUserModeApi, - CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams -) -{ - Memory *pMemory = staticCast(pUserModeApi, Memory); - NV_STATUS status = NV_OK; - MEMORY_DESCRIPTOR *pMemDesc = NULL; - OBJGPU *pGpu = pMemory->pGpu; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NvU64 offset = 0; - NvU32 size = 0; - NvU32 attr = 0; - NvU32 attr2 = 0; - - attr = FLD_SET_DRF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS, attr); - attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, attr); - - attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, attr2 ); - - NV_ASSERT_OK_OR_RETURN(kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, &offset, &size)); - - status = memCreateMemDesc(pGpu, &pMemDesc, ADDR_REGMEM, - offset, size, attr, attr2); - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); - - memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK, NV_TRUE); - - status = memConstructCommon(pMemory, NV01_MEMORY_LOCAL_PRIVILEGED, - 0, pMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL); - - return status; -} diff --git a/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c b/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c index 2cd991a04b..9dba975728 100644 --- a/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c +++ b/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c @@ -141,7 +141,7 @@ chandesConstruct_IMPL partnerParams.runqueue = kchannelGetRunqueue(pKernelChannel); NV_ASSERT_OK_OR_RETURN(kfifoGetEnginePartnerList_HAL(pGpu, pKernelFifo, &partnerParams)); NV_ASSERT_OR_RETURN(partnerParams.numPartners == 1, NV_ERR_INVALID_STATE); - rmEngineType = gpuGetRmEngineType(partnerParams.partnerList[0]); + rmEngineType = gpuGetRmEngineType(partnerParams.partnerList[0]); } // Get the engDesc from engineType @@ -164,7 +164,7 @@ chandesConstruct_IMPL // ENGDESCRIPTOR engDesc = pParamToEngDescFn(pGpu, pParams->externalClassId, pParams->pAllocParams); - + if (rmapiutilIsExternalClassIdInternalOnly(pParams->externalClassId)) { // @@ -213,25 +213,25 @@ chandesConstruct_IMPL // engDesc = MKENGDESC(classId(KernelGraphics), GET_GR_IDX(engDesc)); } - else if (IS_CE(engDesc) && gpuGetEngstate(pGpu, engDesc) == NULL) - { - // If CE is missing, check for KCE instead - engDesc = MKENGDESC(classId(KernelCE), GET_CE_IDX(engDesc)); - } - - void *pEngObject = gpuGetEngstate(pGpu, engDesc); // - // In a kernel-only config, falcons are represented by KernelFalcons and do not have an - // engstate. + // skip checking engstate for CE, engine guaranteed to exist if pParamToEngDescFn is succesful // - if (pEngObject == NULL) - pEngObject = kflcnGetKernelFalconForEngine(pGpu, engDesc); - - if (pEngObject == NULL) + if (!IS_CE(engDesc)) { - NV_PRINTF(LEVEL_ERROR, "engine is missing for class 0x%x\n", - pParams->externalClassId); - return NV_ERR_INVALID_CLASS; + void *pEngObject = gpuGetEngstate(pGpu, engDesc); + // + // In a kernel-only config, falcons are represented by KernelFalcons and do not have an + // engstate. + // + if (pEngObject == NULL) + pEngObject = kflcnGetKernelFalconForEngine(pGpu, engDesc); + + if (pEngObject == NULL) + { + NV_PRINTF(LEVEL_ERROR, "engine is missing for class 0x%x\n", + pParams->externalClassId); + return NV_ERR_INVALID_CLASS; + } } pChannelDescendant->pKernelChannel = pKernelChannel; diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c index de9e10062d..775109e64c 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,10 +21,14 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/core/locks.h" #include "kernel/diagnostics/gpu_acct.h" +#include "kernel/gpu/conf_compute/conf_compute_keystore.h" #include "kernel/gpu/device/device.h" #include "kernel/gpu/fifo/kernel_ctxshare.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -42,6 +46,7 @@ #include "kernel/virtualization/hypervisor/hypervisor.h" #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/virt_mem_allocator.h" +#include "objtmr.h" #include "class/cl0090.h" // KERNEL_GRAPHICS_CONTEXT #include "class/cl906fsw.h" // GF100_GPFIFO @@ -162,6 +167,7 @@ kchannelConstruct_IMPL NvBool bFullSriov = IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu); NvBool bAddedToGroup = NV_FALSE; NvU32 callingContextGfid; + Device *pDevice; // We only support physical channels. NV_ASSERT_OR_RETURN(FLD_TEST_DRF(OS04, _FLAGS, _CHANNEL_TYPE, _PHYSICAL, flags), @@ -180,6 +186,8 @@ kchannelConstruct_IMPL NV_ASSERT_OK_OR_GOTO(status, refFindAncestorOfType(pResourceRef, classId(Device), &pDeviceRef), cleanup); NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &callingContextGfid)); + pDevice = dynamicCast(pDeviceRef->pResource, Device); + // Internal fields must be cleared when RMAPI call is from client if (!hypervisorIsVgxHyper() || IS_GSP_CLIENT(pGpu)) pChannelGpfifoParams->hPhysChannelGroup = NV01_NULL_OBJECT; @@ -336,6 +344,7 @@ kchannelConstruct_IMPL &pChannelGpfifoParams->hPhysChannelGroup, KEPLER_CHANNEL_GROUP_A, NV_PTR_TO_NvP64(&tsgParams), + sizeof(tsgParams), RMAPI_ALLOC_FLAGS_SKIP_RPC, NvP64_NULL, &pRmApi->defaultSecInfo); @@ -647,7 +656,8 @@ kchannelConstruct_IMPL NV_CHECK_OK_OR_GOTO( status, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref), cleanup); NV_CHECK_OK_OR_GOTO( @@ -684,8 +694,8 @@ kchannelConstruct_IMPL // Set TLS state and BAR0 window if we are working with Gr if (bMIGInUse && RM_ENGINE_TYPE_IS_GR(pKernelChannel->engineType)) { - NV_ASSERT_OK(kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pRsClient->hClient, - &pKernelChannel->partitionRef)); + NV_ASSERT_OK(kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &pKernelChannel->partitionRef)); } // Allocate the ChId (except legacy VGPU which allocates ChID on the host) @@ -1280,13 +1290,12 @@ kchannelGetIter NV_STATUS CliGetKernelChannelWithDevice ( - NvHandle hClient, + RsClient *pClient, NvHandle hParent, NvHandle hKernelChannel, KernelChannel **ppKernelChannel ) { - RsClient *pRsClient; RsResourceRef *pParentRef; RsResourceRef *pResourceRef; KernelChannel *pKernelChannel; @@ -1296,8 +1305,7 @@ CliGetKernelChannelWithDevice *ppKernelChannel = NULL; - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, hKernelChannel, &pResourceRef)); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pClient, hKernelChannel, &pResourceRef)); pKernelChannel = dynamicCast(pResourceRef->pResource, KernelChannel); NV_CHECK_OR_RETURN(LEVEL_INFO, pKernelChannel != NULL, NV_ERR_OBJECT_NOT_FOUND); @@ -1516,12 +1524,12 @@ NV_STATUS kchannelGetNextKernelChannel } /** - * @brief Finds the corresponding KernelChannel given client and channel handle + * @brief Finds the corresponding KernelChannel given client object and channel handle * * Looks in client object store for the channel handle. Scales with total * number of registered objects in the client, not just the number of channels. * - * @param[in] hClient + * @param[in] pClient * @param[in] hKernelChannel a KernelChannel Channel handle * @param[out] ppKernelChannel * @@ -1530,21 +1538,17 @@ NV_STATUS kchannelGetNextKernelChannel NV_STATUS CliGetKernelChannel ( - NvHandle hClient, + RsClient *pClient, NvHandle hKernelChannel, KernelChannel **ppKernelChannel ) { NV_STATUS status; - RsClient *pRsClient; RsResourceRef *pResourceRef; *ppKernelChannel = NULL; - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - - status = clientGetResourceRef(pRsClient, hKernelChannel, &pResourceRef); + status = clientGetResourceRef(pClient, hKernelChannel, &pResourceRef); if (status != NV_OK) { return status; @@ -1766,7 +1770,7 @@ kchannelGetNotifierInfo NvBool bFound; bFound = CliGetDmaMappingInfo( - pRsClient->hClient, + pRsClient, RES_GET_HANDLE(pDevice), RES_GET_HANDLE(pMemory), notifyGpuVA, @@ -1827,6 +1831,27 @@ kchannelGetNotifierInfo return NV_ERR_OBJECT_NOT_FOUND; } +/*! + * @brief Check if the client that owns this channel is in user mode. + * + * This replaces using call context for privilege checking, + * and is callable from both CPU and GSP. + * + * @param[in] pGpu + * @param[in] pKernelChannel + * + * @returns NV_TRUE if owned by user mode or NV_FALSE. + */ +NvBool +kchannelCheckIsUserMode_IMPL +( + KernelChannel *pKernelChannel +) +{ + return (pKernelChannel->privilegeLevel == NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_USER) || + (pKernelChannel->privilegeLevel == NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_ADMIN); +} + /*! * @brief Check if the client that owns this channel is kernel. * @@ -2066,7 +2091,7 @@ _kchannelAllocOrDescribeInstMem || ((memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_FBMEM) && bFullSriov))) { kfifoSetupUserD_HAL(pGpu, pKernelFifo, pUserdSubDeviceMemDesc); - } + } } return NV_OK; @@ -2247,9 +2272,11 @@ _kchannelDescribeMemDescsHeavySriov NV_STATUS status = NV_OK; FIFO_INSTANCE_BLOCK *pInstanceBlock = NULL; NvU32 subDevInst; + Subdevice *pSubDevice; NvHandle hSubDevice = 0; NvU32 apert = ADDR_UNKNOWN; NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS memInfoParams; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannel); NV_ASSERT_OR_RETURN(IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu), NV_ERR_INVALID_STATE); @@ -2271,15 +2298,21 @@ _kchannelDescribeMemDescsHeavySriov portMemSet(&memInfoParams, 0, sizeof(NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS)); memInfoParams.hChannel = RES_GET_HANDLE(pKernelChannel); - - if ((status = CliGetSubDeviceHandleFromGpu(RES_GET_CLIENT_HANDLE(pKernelChannel), - pGpu, &hSubDevice)) != NV_OK) + status = subdeviceGetByInstance(RES_GET_CLIENT(pKernelChannel), + RES_GET_HANDLE(pDevice), + subDevInst, + &pSubDevice); + if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Unable to get subdevice handle.\n"); + NV_PRINTF(LEVEL_ERROR, "Unable to get subdevice object.\n"); DBG_BREAKPOINT(); SLI_LOOP_RETURN(status); } + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + + hSubDevice = RES_GET_HANDLE(pSubDevice); + NV_RM_RPC_CONTROL(pGpu, RES_GET_CLIENT_HANDLE(pKernelChannel), hSubDevice, @@ -2696,8 +2729,8 @@ kchannelCtrlCmdGetClassEngineid_IMPL RM_ENGINE_TYPE localRmEngineType; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - RES_GET_CLIENT_HANDLE(pKernelChannel), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pKernelChannel), &ref)); NV_ASSERT_OK_OR_RETURN( @@ -2859,19 +2892,9 @@ kchannelCtrlCmdSetErrorNotifier_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); - Device *pDevice; - RsClient *pClient = RES_GET_CLIENT(pKernelChannel); RC_NOTIFIER_SCOPE scope; NV_STATUS rmStatus = NV_OK; - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Cannot find device for client 0x%x\n", - pClient->hClient); - return NV_ERR_INVALID_DEVICE; - } - NV_PRINTF(LEVEL_INFO, "calling setErrorNotifier on channel: 0x%x, broadcast to TSG: %s\n", kchannelGetDebugTag(pKernelChannel), @@ -2899,7 +2922,6 @@ kchannelCtrlCmdBind_IMPL RM_ENGINE_TYPE globalRmEngineType; RM_ENGINE_TYPE localRmEngineType; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelChannel); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); NV_STATUS rmStatus = NV_OK; ENGDESCRIPTOR engineDesc; @@ -2928,7 +2950,9 @@ kchannelCtrlCmdBind_IMPL MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pKernelChannel), + &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, localRmEngineType, @@ -3135,13 +3159,11 @@ kchannelRegisterChild_IMPL if (pObject->resourceDesc.engDesc == ENG_SW) { RS_ORDERED_ITERATOR it; - RsClient *pClient; + RsClient *pClient = RES_GET_CLIENT(pKernelChannel); ChannelDescendant *pMatchingObject = NULL; firstObjectClassID = pKernelChannel->nextObjectClassID; - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, RES_GET_CLIENT_HANDLE(pKernelChannel), &pClient)); - do { if (++pKernelChannel->nextObjectClassID == firstObjectClassID) @@ -3696,12 +3718,11 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL { NvHandle hNotifier; RsClient *pClient = RES_GET_CLIENT(pKernelChannel); - Device *pDevice; Memory *pMemory; ContextDma *pContextDma; NvU32 addressSpace; NvU64 notificationBufferSize; - NV_STATUS status; + Device *pDevice; hNotifier = pKernelChannel->hErrorContext; @@ -3716,9 +3737,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL return NV_ERR_OUT_OF_RANGE; } - status = deviceGetByInstance(pClient, gpuGetDeviceInstance(pGpu), &pDevice); - if (status != NV_OK) - return NV_ERR_INVALID_DEVICE; + pDevice = GPU_RES_GET_DEVICE(pKernelChannel); if (NV_OK == memGetByHandleAndDevice(pClient, hNotifier, RES_GET_HANDLE(pDevice), &pMemory)) { @@ -3734,7 +3753,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL PCLI_DMA_MAPPING_INFO pDmaMappingInfo; NV_CHECK_OR_RETURN(LEVEL_INFO, - CliGetDmaMappingInfo(pClient->hClient, + CliGetDmaMappingInfo(pClient, RES_GET_HANDLE(pDevice), RES_GET_HANDLE(pMemory), physAddr, @@ -3791,87 +3810,75 @@ kchannelNotifyWorkSubmitToken_IMPL NvU32 token ) { - NV_STATUS status = NV_OK; - NvHandle hNotifier; - RsClient *pClient = RES_GET_CLIENT(pKernelChannel); - Device *pDevice; - Memory *pMemory; - ContextDma *pContextDma; - NvU32 addressSpace; + MEMORY_DESCRIPTOR *pNotifierMemDesc = pKernelChannel->pErrContextMemDesc; + NV_ADDRESS_SPACE addressSpace; NvU16 notifyStatus = 0x0; NvU32 index; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU64 time; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + TRANSFER_SURFACE surf = {0}; + NvNotification *pNotifier = NULL; + NvBool bMemEndTransfer = NV_FALSE; + + if (pNotifierMemDesc == NULL) + return NV_OK; - hNotifier = pKernelChannel->hErrorContext; index = pKernelChannel->notifyIndex[NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN]; - status = deviceGetByInstance(pClient, gpuGetDeviceInstance(pGpu), &pDevice); - if (status != NV_OK) - return NV_ERR_INVALID_DEVICE; - notifyStatus = FLD_SET_DRF(_CHANNELGPFIFO, _NOTIFICATION_STATUS, _IN_PROGRESS, _TRUE, notifyStatus); notifyStatus = FLD_SET_DRF_NUM(_CHANNELGPFIFO, _NOTIFICATION_STATUS, _VALUE, 0xFFFF, notifyStatus); - if (NV_OK == memGetByHandleAndDevice(pClient, hNotifier, RES_GET_HANDLE(pDevice), &pMemory)) - { - addressSpace = memdescGetAddressSpace(pMemory->pMemDesc); - - // - // If clients did not allocate enough memory for the doorbell - // notifier, return NV_OK so as not to regress older clients - // - NV_CHECK_OR_RETURN(LEVEL_INFO, pMemory->Length >= ((index + 1) * sizeof(NvNotification)), NV_OK); - switch (addressSpace) - { - case ADDR_VIRTUAL: - { - NvU64 physAddr = memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU_VA, 0); - PCLI_DMA_MAPPING_INFO pDmaMappingInfo; + addressSpace = memdescGetAddressSpace(pNotifierMemDesc); + if (RMCFG_FEATURE_PLATFORM_GSP) + NV_ASSERT_OR_RETURN(addressSpace == ADDR_FBMEM, NV_ERR_INVALID_STATE); - NV_CHECK_OR_RETURN(LEVEL_INFO, - CliGetDmaMappingInfo(pClient->hClient, - RES_GET_HANDLE(pDevice), - RES_GET_HANDLE(pMemory), - physAddr, - gpumgrGetDeviceGpuMask(pGpu->deviceInstance), - &pDmaMappingInfo), - NV_OK); + // + // If clients did not allocate enough memory for the doorbell + // notifier, return NV_OK so as not to regress older clients + // + NV_CHECK_OR_RETURN(LEVEL_INFO, memdescGetSize(pNotifierMemDesc) >= (index + 1) * sizeof(NvNotification), NV_OK); - // - // If clients did not map enough memory for the doorbell - // notifier, return NV_OK so as not to regress older clients - // - NV_CHECK_OR_RETURN(LEVEL_INFO, pDmaMappingInfo->pMemDesc->Size >= ((index + 1) * sizeof(NvNotification)), NV_OK); + pNotifier = (NvNotification *)memdescGetKernelMapping(pNotifierMemDesc); + if (pNotifier == NULL) + { + surf.pMemDesc = pNotifierMemDesc; + surf.offset = index * sizeof(NvNotification); - status = notifyFillNotifierGPUVA(pGpu, pClient->hClient, RES_GET_HANDLE(pMemory), physAddr, - token, 0x0U, notifyStatus, index); - break; - } - case ADDR_FBMEM: - // fall through - case ADDR_SYSMEM: - status = notifyFillNotifierMemory(pGpu, pMemory, token, 0x0U, notifyStatus, index); - break; - default: - status = NV_ERR_NOT_SUPPORTED; - break; - } + pNotifier = + (NvNotification *) memmgrMemBeginTransfer(pMemoryManager, &surf, + sizeof(NvNotification), + TRANSFER_FLAGS_SHADOW_ALLOC); + NV_ASSERT_OR_RETURN(pNotifier != NULL, NV_ERR_INVALID_STATE); + bMemEndTransfer = NV_TRUE; } - else if (NV_OK == ctxdmaGetByHandle(pClient, hNotifier, &pContextDma)) + else { // - // If clients did not allocate enough memory for the doorbell - // notifier, return NV_OK so as not to regress older clients + // If a CPU pointer has been passed by caller ensure that the notifier + // is in sysmem or in case it in vidmem, BAR access to the same is not + // blocked (for HCC) // - NV_CHECK_OR_RETURN(LEVEL_INFO, pContextDma->Limit >= (((index + 1) * sizeof(NvNotification)) - 1), NV_OK); + NV_ASSERT_OR_RETURN( + memdescGetAddressSpace(pNotifierMemDesc) == ADDR_SYSMEM || + !kbusIsBarAccessBlocked(pKernelBus), NV_ERR_INVALID_ARGUMENT); + pNotifier = &pNotifier[index]; + } + + tmrGetCurrentTime(pTmr, &time); - status = notifyFillNotifierOffset(pGpu, pContextDma, token, 0x0U, notifyStatus, - (sizeof(NvNotification) * index)); + notifyFillNvNotification(pGpu, pNotifier, token, 0, + notifyStatus, NV_TRUE, time); + if (bMemEndTransfer) + { + memmgrMemEndTransfer(pMemoryManager, &surf, sizeof(NvNotification), 0); } - return status; + return NV_OK; } /** @@ -4196,14 +4203,14 @@ _kchannelGetUserMemDesc * @brief Retrieve a KernelChannel from either a KernelChannel or TSG handle. KernelChannel is * checked first. If TSG is provided, the head of the TSG is returned. * - * @param[in] hClient Client + * @param[in] pClient Client object * @param[in] hDual NvHandle either to TSG or to KernelChannel * @param[out] ppKernelChannel Referenced KernelChannel */ NV_STATUS kchannelGetFromDualHandle_IMPL ( - NvHandle hClient, + RsClient *pClient, NvHandle hDual, KernelChannel **ppKernelChannel ) @@ -4215,13 +4222,13 @@ kchannelGetFromDualHandle_IMPL *ppKernelChannel = NULL; - if (CliGetKernelChannel(hClient, hDual, &pKernelChannel) == NV_OK) + if (CliGetKernelChannel(pClient, hDual, &pKernelChannel) == NV_OK) { *ppKernelChannel = pKernelChannel; return NV_OK; } - if (CliGetChannelGroup(hClient, hDual, &pChanGrpRef, NULL) == NV_OK) + if (CliGetChannelGroup(pClient->hClient, hDual, &pChanGrpRef, NULL) == NV_OK) { KernelChannelGroupApi *pKernelChannelGroupApi = dynamicCast( pChanGrpRef->pResource, @@ -4250,20 +4257,20 @@ kchannelGetFromDualHandle_IMPL * checked first. If TSG is provided, the head of the TSG is returned. If * KernelChannel handle is provided, it must not be part of a client-allocated TSG. * - * @param[in] hClient Client + * @param[in] pClient Client object * @param[in] hDual NvHandle either to TSG or to bare Channel * @param[out] ppKernelChannel Referenced KernelChannel */ NV_STATUS kchannelGetFromDualHandleRestricted_IMPL ( - NvHandle hClient, + RsClient *pClient, NvHandle hDual, KernelChannel **ppKernelChannel ) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kchannelGetFromDualHandle(hClient, hDual, ppKernelChannel)); + kchannelGetFromDualHandle(pClient, hDual, ppKernelChannel)); if ((RES_GET_HANDLE(*ppKernelChannel) == hDual) && (((*ppKernelChannel)->pKernelChannelGroupApi->pKernelChannelGroup != NULL) && !(*ppKernelChannel)->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm)) diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c index 84af1d4f6f..55f83e912f 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c @@ -186,7 +186,8 @@ kchangrpapiConstruct_IMPL NV_CHECK_OK_OR_GOTO( rmStatus, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pParams->hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref), failed); NV_CHECK_OK_OR_GOTO( @@ -201,6 +202,15 @@ kchangrpapiConstruct_IMPL pKernelChannelGroup->engineType = rmEngineType; pHeap = ref.pKernelMIGGpuInstance->pMemoryPartitionHeap; } + else + { + // Only GR0 is allowed without MIG + if ((RM_ENGINE_TYPE_IS_GR(rmEngineType)) && (rmEngineType != RM_ENGINE_TYPE_GR0)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + } if((pDevice->vaMode != NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES) || (hVASpace != 0)) { @@ -274,7 +284,7 @@ kchangrpapiConstruct_IMPL // // - // Size of memory that will be calculated for ctxBufPool reservation if ctxBufPool is enabled and MIG is disabled + // Size of memory that will be calculated for ctxBufPool reservation if ctxBufPool is enabled and MIG is disabled // or current engine belongs to this MIG instance and MIG is enabled // if (pKernelChannelGroup->pCtxBufPool != NULL && @@ -358,6 +368,7 @@ kchangrpapiConstruct_IMPL &pKernelChannelGroupApi->hKernelGraphicsContext, KERNEL_GRAPHICS_CONTEXT, NvP64_NULL, + 0, RMAPI_ALLOC_FLAGS_SKIP_RPC, NvP64_NULL, &pRmApi->defaultSecInfo), @@ -376,6 +387,7 @@ kchangrpapiConstruct_IMPL pParams->hResource, pParams->externalClassId, pAllocParams, + sizeof(*pAllocParams), rmStatus); // // Make sure that corresponding RPC occurs when freeing @@ -879,6 +891,7 @@ kchangrpapiSetLegacyMode_IMPL &hkCtxShare, FERMI_CONTEXT_SHARE_A, NV_PTR_TO_NvP64(&kctxshareParams), + sizeof(kctxshareParams), RMAPI_ALLOC_FLAGS_SKIP_RPC, NvP64_NULL, &pRmApi->defaultSecInfo), @@ -903,6 +916,7 @@ kchangrpapiSetLegacyMode_IMPL &hkCtxShare, FERMI_CONTEXT_SHARE_A, NV_PTR_TO_NvP64(&kctxshareParams), + sizeof(kctxshareParams), RMAPI_ALLOC_FLAGS_SKIP_RPC, NvP64_NULL, &pRmApi->defaultSecInfo), @@ -1145,7 +1159,7 @@ kchangrpapiCtrlCmdBind_IMPL { NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannelGroupApi); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelChannelGroupApi); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannelGroupApi); CHANNEL_NODE *pChanNode; RM_ENGINE_TYPE localEngineType; RM_ENGINE_TYPE globalEngineType; @@ -1162,7 +1176,7 @@ kchangrpapiCtrlCmdBind_IMPL MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c b/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c index ac62b16f64..ae9f7bffdb 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c @@ -292,7 +292,7 @@ kctxshareapiCopyConstruct_IMPL if (pKernelChannelGroupApi->hKernelGraphicsContext != NV01_NULL_OBJECT) { RsResourceRef *pKernelGraphicsContextRef; - NV_ASSERT_OK_OR_ELSE(rmStatus, + NV_ASSERT_OK_OR_ELSE(rmStatus, clientGetResourceRef(pCallContext->pClient, pKernelChannelGroupApi->hKernelGraphicsContext, &pKernelGraphicsContextRef), goto done); @@ -300,7 +300,7 @@ kctxshareapiCopyConstruct_IMPL } // - // For legacy internal kctxshares, RPC is handled by the channelgroup object's copy ctor, + // For legacy internal kctxshares, RPC is handled by the channelgroup object's copy ctor, // so we skip the automatic RPC here // if ((IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) && !pKernelCtxShareApi->pShareData->pKernelChannelGroup->bLegacyMode) @@ -311,7 +311,7 @@ kctxshareapiCopyConstruct_IMPL pDstRef, rmStatus); } -done: +done: if (rmStatus != NV_OK) { serverFreeShare(&g_resServ, pShared); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c index b426bbb4c2..19dbe52d4e 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,9 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -600,7 +603,8 @@ kfifoChidMgrAllocChid_IMPL chSize = 1; // Create unique isolation ID for each process - if (serverutilGetClientUnderLock(hClient, &pClient) != NV_OK) + pClient = serverutilGetClientUnderLock(hClient); + if (pClient == NULL) { NV_PRINTF(LEVEL_ERROR, "Invalid client handle %ux\n", hClient); DBG_BREAKPOINT(); @@ -1097,6 +1101,7 @@ kfifoChidMgrReserveSystemChids_IMPL "channel ID heap\n"); goto cleanup; } + portMemSet(pChidMgr->ppVirtualChIDHeap[gfid], 0, sizeof(OBJEHEAP)); // // Construct heap using low as offset and size of numChannels. This heap @@ -1875,7 +1880,7 @@ kfifoGetHostDeviceInfoTable_KERNEL NvHandle hClient = NV01_NULL_OBJECT; NvHandle hObject = NV01_NULL_OBJECT; NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *pParams; - NV2080_CTRL_FIFO_DEVICE_ENTRY *pHostEntries; + NV2080_CTRL_FIFO_DEVICE_ENTRY *pFetchedTable; NvU32 numEntries; NvU32 device; NvU32 entry; @@ -1902,21 +1907,28 @@ kfifoGetHostDeviceInfoTable_KERNEL } else { + RsClient *pClient; + Subdevice *pSubdevice; + hClient = hMigClient; - if ((status = CliGetSubDeviceHandleFromGpu(hClient, pGpu, &hObject)) != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Unable to get subdevice handle.\n"); - return NV_ERR_INVALID_STATE; - } + + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, hClient, &pClient)); + + NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + + hObject = RES_GET_HANDLE(pSubdevice); } } - // Allocate pHostEntries and params on the heap to avoid stack overflow + // Allocate pFetchedTable and params on the heap to avoid stack overflow pLocals = portMemAllocNonPaged(sizeof(*pLocals)); NV_ASSERT_OR_RETURN((pLocals != NULL), NV_ERR_NO_MEMORY); pParams = &pLocals->params; - pHostEntries = pLocals->entries; + pFetchedTable = pLocals->entries; // // Read device info table entries from Host RM until Host indicates that @@ -1950,9 +1962,10 @@ kfifoGetHostDeviceInfoTable_KERNEL goto cleanup; } - portMemCopy(&pHostEntries[device], pParams->numEntries * - sizeof(NV2080_CTRL_FIFO_DEVICE_ENTRY), pParams->entries, pParams->numEntries * - sizeof(NV2080_CTRL_FIFO_DEVICE_ENTRY)); + portMemCopy(&pFetchedTable[device], + pParams->numEntries * (sizeof *pFetchedTable), + pParams->entries, + pParams->numEntries * (sizeof *pParams->entries)); numEntries += pParams->numEntries; @@ -1978,51 +1991,68 @@ kfifoGetHostDeviceInfoTable_KERNEL maxPbdmaId = 0; for (entry = 0; entry < numEntries; ++entry) { - portMemCopy(pEngineInfo->engineInfoList[entry].engineData, - ENGINE_INFO_TYPE_INVALID * sizeof(*(pEngineInfo->engineInfoList[entry].engineData)), - pHostEntries[entry].engineData, - ENGINE_INFO_TYPE_INVALID * sizeof(*(pEngineInfo->engineInfoList[entry].engineData))); - - pEngineInfo->engineInfoList[entry].numPbdmas = pHostEntries[entry].numPbdmas; - portMemCopy(pEngineInfo->engineInfoList[entry].pbdmaIds, - FIFO_ENGINE_MAX_NUM_PBDMA * sizeof(*(pEngineInfo->engineInfoList[entry].pbdmaIds)), - pHostEntries[entry].pbdmaIds, - FIFO_ENGINE_MAX_NUM_PBDMA * sizeof(*(pEngineInfo->engineInfoList[entry].pbdmaIds))); - - portMemCopy(pEngineInfo->engineInfoList[entry].pbdmaFaultIds, - FIFO_ENGINE_MAX_NUM_PBDMA * sizeof(*(pEngineInfo->engineInfoList[entry].pbdmaFaultIds)), - pHostEntries[entry].pbdmaFaultIds, - FIFO_ENGINE_MAX_NUM_PBDMA * sizeof(*(pEngineInfo->engineInfoList[entry].pbdmaFaultIds))); - - portStringCopy((char *)pEngineInfo->engineInfoList[entry].engineName, - sizeof(pEngineInfo->engineInfoList[entry].engineName), - (char *)pHostEntries[entry].engineName, - FIFO_ENGINE_NAME_MAX_SIZE); - - if (pEngineInfo->engineInfoList[entry].engineData[ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE] != 0) + FIFO_ENGINE_LIST *pLocalEntry = &pEngineInfo->engineInfoList[entry]; + NV2080_CTRL_FIFO_DEVICE_ENTRY *pFetchedEntry = &pFetchedTable[entry]; + + ct_assert(sizeof pLocalEntry->engineData <= + sizeof pFetchedEntry->engineData); + portMemCopy(pLocalEntry->engineData, + sizeof pLocalEntry->engineData, + pFetchedEntry->engineData, + NV_ARRAY_ELEMENTS(pLocalEntry->engineData) * + (sizeof *pFetchedEntry->engineData)); + + pLocalEntry->numPbdmas = pFetchedEntry->numPbdmas; + NV_ASSERT_TRUE_OR_GOTO(status, + pLocalEntry->numPbdmas <= + NV_ARRAY_ELEMENTS(pLocalEntry->pbdmaIds) && + pLocalEntry->numPbdmas <= + NV_ARRAY_ELEMENTS(pLocalEntry->pbdmaFaultIds), + NV_ERR_INVALID_STATE, + cleanup); + portMemCopy( + pLocalEntry->pbdmaIds, + pLocalEntry->numPbdmas * (sizeof *(pLocalEntry->pbdmaIds)), + pFetchedEntry->pbdmaIds, + pLocalEntry->numPbdmas * (sizeof *(pFetchedEntry->pbdmaIds))); + portMemCopy( + pLocalEntry->pbdmaFaultIds, + pLocalEntry->numPbdmas * (sizeof *(pLocalEntry->pbdmaFaultIds)), + pFetchedEntry->pbdmaFaultIds, + pLocalEntry->numPbdmas * (sizeof *(pFetchedEntry->pbdmaFaultIds))); + + portStringCopy(pLocalEntry->engineName, + sizeof pLocalEntry->engineName, + pFetchedEntry->engineName, + sizeof pFetchedEntry->engineName); + + if (pLocalEntry->engineData[ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE] != 0) { numRunlists++; } maxRunlistId = NV_MAX(maxRunlistId, - pHostEntries[entry].engineData[ENGINE_INFO_TYPE_RUNLIST]); + pFetchedEntry->engineData[ENGINE_INFO_TYPE_RUNLIST]); - for (i = 0; i < pEngineInfo->engineInfoList[entry].numPbdmas; i++) + for (i = 0; i < pLocalEntry->numPbdmas; i++) { - maxPbdmaId = NV_MAX(maxPbdmaId, pEngineInfo->engineInfoList[entry].pbdmaIds[i]); + maxPbdmaId = NV_MAX(maxPbdmaId, pLocalEntry->pbdmaIds[i]); // // SW engine while being constructed does not populate any PBDMA Fault IDs. // Hence, skipping it. // - if (pEngineInfo->engineInfoList[entry].engineData[ENGINE_INFO_TYPE_ENG_DESC] != ENG_SW) + if (pLocalEntry->engineData[ENGINE_INFO_TYPE_ENG_DESC] != ENG_SW) { - bitVectorSet(&pEngineInfo->validEngineIdsForPbdmas, pEngineInfo->engineInfoList[entry].pbdmaFaultIds[i]); + bitVectorSet(&pEngineInfo->validEngineIdsForPbdmas, pLocalEntry->pbdmaFaultIds[i]); } } } - NV_ASSERT_OR_GOTO(kfifoReservePbdmaFaultIds_HAL(pGpu, pKernelFifo, pEngineInfo->engineInfoList, - pEngineInfo->engineInfoListSize) == NV_OK, cleanup); + NV_ASSERT_OK_OR_GOTO(status, + kfifoReservePbdmaFaultIds_HAL(pGpu, pKernelFifo, + pEngineInfo->engineInfoList, + pEngineInfo->engineInfoListSize), + cleanup); if (IS_VIRTUAL(pGpu)) { @@ -3379,3 +3409,31 @@ kfifoGetGuestEngineLookupTable_IMPL return guestEngineLookupTable; }; +/** + * @brief Fetch the maximum number of secure channels supported by SEC2 + * and secure CEs when confidential compute is enabled + * + */ +NV_STATUS +kfifoGetMaxSecureChannels_KERNEL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS numSecureChannelsParams = {0}; + + NV_ASSERT_OK_OR_RETURN( + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS, + &numSecureChannelsParams, + sizeof(numSecureChannelsParams))); + + pKernelFifo->maxSec2SecureChannels = numSecureChannelsParams.maxSec2SecureChannels; + pKernelFifo->maxCeSecureChannels = numSecureChannelsParams.maxCeSecureChannels; + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c index b5fb057e4a..3b4bb52b4a 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,7 +73,8 @@ deviceCtrlCmdFifoGetChannelList_IMPL NV_STATUS status; // Searching through the rm client db. - status = CliGetKernelChannel(RES_GET_CLIENT_HANDLE(pDevice), pChannelHandleList[counter], &pKernelChannel); + status = CliGetKernelChannel(RES_GET_CLIENT(pDevice), + pChannelHandleList[counter], &pKernelChannel); if (status == NV_OK) { @@ -364,8 +365,6 @@ subdeviceCtrlCmdFifoGetUserdLocation_IMPL NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS *pUserdLocationParams ) { - RsClient *pClient = RES_GET_CLIENT(pSubdevice); - Device *pDevice; NvU32 userdAperture; NvU32 userdAttribute; NV_STATUS rmStatus = NV_OK; @@ -374,10 +373,6 @@ subdeviceCtrlCmdFifoGetUserdLocation_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - return NV_ERR_INVALID_DEVICE; - rmStatus = kfifoGetUserdLocation_HAL(pKernelFifo, &userdAperture, &userdAttribute); @@ -438,7 +433,7 @@ subdeviceCtrlCmdFifoGetChannelMemInfo_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - Device *pDevice; + NvHandle hDevice = RES_GET_PARENT_HANDLE(pSubdevice); RsClient *pClient = RES_GET_CLIENT(pSubdevice); NV_STATUS rmStatus = NV_OK; NvU32 index; @@ -450,12 +445,8 @@ subdeviceCtrlCmdFifoGetChannelMemInfo_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - return NV_ERR_INVALID_DEVICE; - - rmStatus = CliGetKernelChannelWithDevice(pClient->hClient, - RES_GET_HANDLE(pDevice), + rmStatus = CliGetKernelChannelWithDevice(pClient, + hDevice, pChannelMemParams->hChannel, &pKernelChannel); if (rmStatus != NV_OK) @@ -519,18 +510,13 @@ diagapiCtrlCmdFifoEnableVirtualContext_IMPL NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS *pEnableVCParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pDiagApi); - Device *pDevice; NV_STATUS rmStatus = NV_OK; KernelChannel *pKernelChannel = NULL; RsClient *pClient = RES_GET_CLIENT(pDiagApi); - - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - return NV_ERR_INVALID_DEVICE; + Device *pDevice = GPU_RES_GET_DEVICE(pDiagApi); NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannelWithDevice(pClient->hClient, + CliGetKernelChannelWithDevice(pClient, RES_GET_HANDLE(pDevice), pEnableVCParams->hChannel, &pKernelChannel)); @@ -559,6 +545,7 @@ subdeviceCtrlCmdFifoUpdateChannelInfo_IMPL CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + RsClient *pChannelClient; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); KernelChannel *pKernelChannel = NULL; NV_STATUS status = NV_OK; @@ -569,7 +556,12 @@ subdeviceCtrlCmdFifoUpdateChannelInfo_IMPL LOCK_ASSERT_AND_RETURN(pRmCtrlParams->bDeferredApi || rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(pChannelInfo->hClient, + serverGetClientUnderLock(&g_resServ, + pChannelInfo->hClient, + &pChannelClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + CliGetKernelChannel(pChannelClient, pChannelInfo->hChannel, &pKernelChannel)); NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); @@ -629,10 +621,15 @@ diagapiCtrlCmdFifoGetChannelState_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pDiagApi); + RsClient *pChannelClient; KernelChannel *pKernelChannel; NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(pChannelStateParams->hClient, pChannelStateParams->hChannel, &pKernelChannel)); + serverGetClientUnderLock(&g_resServ, pChannelStateParams->hClient, + &pChannelClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + CliGetKernelChannel(pChannelClient, pChannelStateParams->hChannel, &pKernelChannel)); NV_CHECK_OK_OR_RETURN(LEVEL_INFO, kchannelGetChannelPhysicalState(pGpu, pKernelChannel, pChannelStateParams)); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c index a65a0b077c..bb97aaf36e 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c @@ -34,7 +34,7 @@ static void _kfifoPreConstructRegistryOverrides(OBJGPU *pGpu, KernelFifo *pKernelFifo); -NV_STATUS +NV_STATUS kfifoConstructEngine_IMPL ( OBJGPU *pGpu, @@ -144,13 +144,18 @@ kfifoStateInitLocked_IMPL } } + NV_ASSERT_OK_OR_RETURN(kfifoConstructUsermodeMemdescs_HAL(pGpu, pKernelFifo)); + NV_ASSERT_OK_OR_RETURN(kfifoChidMgrConstruct(pGpu, pKernelFifo)); if (pKernelRc != NULL) { krcInitRegistryOverridesDelayed(pGpu, pKernelRc); } - + + // Get maximum number of secure channels when APM/HCC is enabled + NV_ASSERT_OK_OR_RETURN(kfifoGetMaxSecureChannels(pGpu, pKernelFifo)); + return NV_OK; } @@ -209,5 +214,10 @@ kfifoStateDestroy_IMPL // kfifoChidMgrDestruct(pKernelFifo); + // Destroy regardless of NULL, if pointers are null, is just a NOP + memdescDestroy(pKernelFifo->pRegVF); + memdescDestroy(pKernelFifo->pBar1VF); + memdescDestroy(pKernelFifo->pBar1PrivVF); + return; } diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c b/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c index 34e1ae7920..38189cd8ea 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c @@ -141,7 +141,7 @@ RmIdleChannels GpuResource *pGpuResource; // - // Don't allow other clients' resources to be accessed/modified by this + // Don't allow other clients' resources to be accessed/modified by this // control call. // if (hClient != phClients[chanIdx]) diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c b/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c index 4ec3822a57..4d2c220ffe 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,14 +59,25 @@ _kschedmgrGetSchedulerPolicy switch (schedPolicy) { + case SCHED_POLICY_DEFAULT: default: - if (hypervisorIsVgxHyper()) - return "BEST_EFFORT"; - else // For baremetal and PT - return "NONE"; + // For baremetal and PT + return "NONE"; } } +void kschedmgrSetConfigPolicyFromUser_IMPL +( + KernelSchedMgr *pKernelSchedMgr, + OBJGPU *pGpu, + NvU32 schedSwPolicy +) +{ + NvU32 schedSwPolicyLocal = SCHED_POLICY_DEFAULT; + pKernelSchedMgr->configSchedPolicy = schedSwPolicyLocal; + pKernelSchedMgr->bIsSchedSwEnabled = (schedSwPolicyLocal != SCHED_POLICY_DEFAULT); +} + /*! * Configure PDBs related to scheduler policy per RM configuration. */ diff --git a/src/nvidia/src/kernel/gpu/fifo/usermode_api.c b/src/nvidia/src/kernel/gpu/fifo/usermode_api.c index 5819530b46..fa870a1446 100644 --- a/src/nvidia/src/kernel/gpu/fifo/usermode_api.c +++ b/src/nvidia/src/kernel/gpu/fifo/usermode_api.c @@ -22,6 +22,11 @@ */ #include "kernel/gpu/fifo/usermode_api.h" +#include "kernel/gpu/fifo/kernel_fifo.h" + +#include "class/clc661.h" // HOPPER_USERMODE_A +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl003f.h" // NV01_MEMORY_LOCAL_PRIVILEGED NV_STATUS usrmodeConstruct_IMPL @@ -31,7 +36,56 @@ usrmodeConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - return usrmodeConstructHal_HAL(pUserModeApi, pCallContext, pParams); + Memory *pMemory = staticCast(pUserModeApi, Memory); + OBJGPU *pGpu = pMemory->pGpu; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NV_HOPPER_USERMODE_A_PARAMS *pAllocParams = (NV_HOPPER_USERMODE_A_PARAMS*) pParams->pAllocParams; + NvU32 hClass = pCallContext->pResourceRef->externalClassId; + NvBool bBar1Mapping = NV_FALSE; + NvBool bPrivMapping = NV_FALSE; + MEMORY_DESCRIPTOR *pMemDesc = pKernelFifo->pRegVF; + + // Copy-construction has already been done by the base Memory class + if (RS_IS_COPY_CTOR(pParams)) + { + return NV_OK; + } + + // + // We check pKernelFifo->pBar1VF because for some reason RM allows HOPPER_USERMODE_A on ADA. + // This is a WAR until we root cause. + // + if (hClass >= HOPPER_USERMODE_A && pAllocParams != NULL && pKernelFifo->pBar1VF != NULL) + { + bBar1Mapping = pAllocParams->bBar1Mapping; + bPrivMapping = pAllocParams->bPriv; + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + { + bBar1Mapping = NV_FALSE; + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + !bPrivMapping || bBar1Mapping, + NV_ERR_INVALID_PARAMETER); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + !bPrivMapping || pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL, + NV_ERR_INSUFFICIENT_PERMISSIONS); + + if (bBar1Mapping) + { + pMemDesc = bPrivMapping ? pKernelFifo->pBar1PrivVF : pKernelFifo->pBar1VF; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + memConstructCommon(pMemory, + bBar1Mapping? NV01_MEMORY_SYSTEM : NV01_MEMORY_LOCAL_PRIVILEGED, + 0, pMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL)); + memdescAddRef(pMemDesc); + return NV_OK; } NvBool diff --git a/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c b/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c index 093256b652..32098a8cef 100644 --- a/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c +++ b/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,7 +38,7 @@ * * @returns NV_OK on success, specific error code on failure. */ -NV_STATUS +NV_STATUS uvmchanrtnrConstruct_IMPL ( UvmChannelRetainer *pUvmChannelRetainer, @@ -49,11 +49,15 @@ uvmchanrtnrConstruct_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pUvmChannelRetainer); KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); NV_STATUS rmStatus = NV_OK; + RsClient *pChannelClient; KernelChannel *pKernelChannel = NULL; NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS *pUvmChannelRetainerParams = pParams->pAllocParams; CHID_MGR *pChidMgr = NULL; - NV_ASSERT_OK_OR_RETURN(CliGetKernelChannel(pUvmChannelRetainerParams->hClient, pUvmChannelRetainerParams->hChannel, &pKernelChannel)); + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, + pUvmChannelRetainerParams->hClient, &pChannelClient)); + + NV_ASSERT_OK_OR_RETURN(CliGetKernelChannel(pChannelClient, pUvmChannelRetainerParams->hChannel, &pKernelChannel)); if (!uvmchanrtnrIsAllocationAllowed(pUvmChannelRetainer, pCallContext, pKernelChannel)) { @@ -91,7 +95,7 @@ uvmchanrtnrConstruct_IMPL return rmStatus; } -void +void uvmchanrtnrDestruct_IMPL ( UvmChannelRetainer *pUvmChannelRetainer diff --git a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c index 689ccaec06..de030bafa9 100644 --- a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c @@ -32,6 +32,7 @@ #include "gpu/gsp/kernel_gsp.h" #include "published/hopper/gh100/dev_fsp_pri.h" +#include "published/hopper/gh100/dev_fsp_addendum.h" #include "fsp/fsp_nvdm_format.h" #include "published/hopper/gh100/dev_gc6_island_addendum.h" #include "published/hopper/gh100/dev_falcon_v4.h" @@ -41,13 +42,7 @@ #include "os/os.h" #include "nvRmReg.h" -#if RMCFG_MODULE_ENABLED (FSP) -#include "hopper/gh100/dev_gsp.h" -#include "gpu/gsp/gsp.h" -#include "gsp/memmap.h" -#include "objfsp.h" -#include "objflcnable.h" -#endif +#include "gpu/conf_compute/conf_compute.h" /*! * @brief Update command queue head and tail pointers @@ -664,20 +659,35 @@ kfspGetGspUcodeArchive ) { KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + NV_ASSERT(pCC != NULL); if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) { - NV_PRINTF(LEVEL_ERROR, "Loading GSP-RM image using FSP.\n"); + NV_PRINTF(LEVEL_NOTICE, "Loading GSP-RM image using FSP.\n"); if (kgspIsDebugModeEnabled_HAL(pGpu, pKernelGsp)) { + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + NV_PRINTF(LEVEL_ERROR, "GSP-RM image for CC not found\n"); + return NULL; + } + else { return kgspGetBinArchiveGspRmFmcGfwDebugSigned_HAL(pKernelGsp); } } else { - return kgspGetBinArchiveGspRmFmcGfwProdSigned_HAL(pKernelGsp); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + return kgspGetBinArchiveGspRmCcFmcGfwProdSigned_HAL(pKernelGsp); + } + else + { + return kgspGetBinArchiveGspRmFmcGfwProdSigned_HAL(pKernelGsp); + } } } #if RMCFG_MODULE_ENABLED (GSP) @@ -703,6 +713,15 @@ kfspGetGspUcodeArchive // NV_ASSERT_OR_RETURN(gspSetupRMProxyImage(pGpu, pGsp) == NV_OK, NULL); + // For debug board if CC is enabled pick spdm profile of gspcc ucode + if (pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED) == NV_TRUE) + { + + { + return gspGetBinArchiveGspFmcSpdmGfwDebugSigned_HAL(pGsp); + } + } + else { return gspGetBinArchiveGspFmcGfwDebugSigned_HAL(pGsp); } @@ -717,6 +736,11 @@ kfspGetGspUcodeArchive else { NV_ASSERT_OR_RETURN(gspSetupRMProxyImage(pGpu, pGsp) == NV_OK, NULL); + if (pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED) == NV_TRUE) + { + return gspGetBinArchiveGspCcFmcGfwProdSigned_HAL(pGsp); + } + else { return gspGetBinArchiveGspFmcGfwProdSigned_HAL(pGsp); } @@ -742,6 +766,9 @@ kfspGetGspBootArgs { NV_STATUS status = NV_OK; + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + NV_ASSERT(pCC != NULL); + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) { KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); @@ -789,6 +816,7 @@ kfspSetupGspImages // On systems with SEV enabled, the GSP-FMC image has to be accessible // to FSP (an unit inside GPU) and hence placed in unprotected sysmem // + flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; // Detect the mode of operation for GSP and fetch the right image to boot pBinArchive = kfspGetGspUcodeArchive(pGpu, pKernelFsp); @@ -913,93 +941,8 @@ _kfspCheckGspBootStatus KernelFsp *pKernelFsp ) { -#if RMCFG_MODULE_ENABLED (FSP) - NV_STATUS status = NV_OK; - RMTIMEOUT timeout; - Gsp *pGsp = GPU_GET_GSP(pGpu); - Falcon *pFlcn = ENG_GET_FLCN(pGsp); - - pFlcn->bBootstrapped = NV_TRUE; - - // In Inst_in_sys mode GSP-FMC will write status to NV_PGSP_MAILBOX(0). - if (kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp)) - { - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); - while(FLD_TEST_DRF_NUM(_PGSP, _MAILBOX, _DATA, GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS , GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)))) - { - status = gpuCheckTimeout(pGpu, &timeout); - if (status == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP Inst_in_sys ucode to boot\n"); - DBG_BREAKPOINT(); - break; - } - osSpinLoop(); - } - // Read GSP mailbox to check if it is booted successfully. - if (GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)) != GSP_INST_IN_SYS_COMPLETION_STATUS_OK) - { - NV_PRINTF(LEVEL_ERROR, "GSP Inst_in_sys ucode boot failed with GSP status 0x%x\n", GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0))); - DBG_BREAKPOINT(); - } - return status; - } - - // Ensure that for GH100+ TM is released before polling for priv lockdown release - status = kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP's target mask to be released.\n"); - DBG_BREAKPOINT(); - return status; - } - - // Ensure priv lockdown is released before polling interrupts - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); - do - { - if (flcnIsRiscvLockdownReleased_HAL(pGpu, pFlcn)) - { - status = NV_OK; - break; - } - - status = gpuCheckTimeout(pGpu, &timeout); - if (status == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, "Timed out waiting for priv lockdown release.\n"); - DBG_BREAKPOINT(); - break; - } - osSpinLoop(); - } while (1); - - // Ensure GSP can send back init ack interrupt to CPU - do - { - gspServiceEarlyInterrupt_HAL(pGpu, pGsp); - - if (pFlcn->bOSReady) - { - status = NV_OK; - break; - } - - status = gpuCheckTimeout(pGpu, &timeout); - if (status == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP ucode to boot.\n"); - DBG_BREAKPOINT(); - break; - } - osSpinLoop(); - } while (1); - - return status; -#else // On GSP-RM, the kgsp code path will check for GSP boot status return NV_OK; -#endif } /*! @@ -1017,6 +960,18 @@ kfspDumpDebugState_GH100 KernelFsp *pKernelFsp ) { + // + // Older microcodes did not have the version populated in scratch. + // They will report a version of 0. + // + const NvU32 fspUcodeVersion = GPU_REG_RD_DRF(pGpu, _GFW, _FSP_UCODE_VERSION, _FULL); + if (fspUcodeVersion > 0) + { + NV_PRINTF(LEVEL_ERROR, "FSP microcode v%u.%u\n", + DRF_VAL(_GFW, _FSP_UCODE_VERSION, _MAJOR, fspUcodeVersion), + DRF_VAL(_GFW, _FSP_UCODE_VERSION, _MINOR, fspUcodeVersion)); + } + NV_PRINTF(LEVEL_ERROR, "NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0) = 0x%x\n", GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0))); NV_PRINTF(LEVEL_ERROR, "NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1) = 0x%x\n", @@ -1140,6 +1095,7 @@ kfspSendBootCommands_GH100 // On systems with SEV enabled, the FRTS has to be accessible to // FSP (an unit inside GPU) and hence placed in unprotected sysmem // + flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize, 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); @@ -1278,3 +1234,15 @@ kfspGetExtraReservedMemorySize_GH100 // Bug: 3763996 return 4 * 1024; } + +NvBool +kfspRequiresBug3957833WAR_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + const NvU32 FSP_BUG_3957833_FIX_VERSION = 0x44C; + const NvU32 fspUcodeVersion = GPU_REG_RD_DRF(pGpu, _GFW, _FSP_UCODE_VERSION, _FULL); + return fspUcodeVersion < FSP_BUG_3957833_FIX_VERSION; +} diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 4d7aa96f99..89c0192a7b 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,6 +47,7 @@ #include "core/hal_mgr.h" #include "vgpu/rpc.h" #include "jt.h" + #include "gpu/gpu_fabric_probe.h" #include "vgpu/vgpu_events.h" @@ -59,6 +60,7 @@ #include "platform/chipset/chipset.h" #include "kernel/gpu/host_eng/host_eng.h" #include "gpu/ce/kernel_ce.h" +#include "gpu/conf_compute/conf_compute.h" #include "gpu/fifo/kernel_fifo.h" #include "kernel/gpu/intr/intr.h" @@ -136,13 +138,6 @@ static inline void _setPlatformNoHostbridgeDetect(NvBool bValue) pPfm->setProperty(pPfm, PDB_PROP_PFM_NO_HOSTBRIDGE_DETECT, bValue); } -// Forward declare all the class definitions so that we don't need to pull in all the headers -#define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, gpuField) \ - extern const struct NVOC_CLASS_DEF NV_CONCATENATE(__nvoc_class_def_, className); - -#include "gpu/gpu_child_list.h" - - // Describes a child type (e.g.: classId(OBJCE)) struct GPUCHILDTYPE { @@ -151,14 +146,14 @@ struct GPUCHILDTYPE // certain features in bifInitRegistryOverrides NvU32 instances; NvU32 gpuChildPtrOffset; - const NVOC_CLASS_INFO *pClassInfo; + NVOC_CLASS_ID classId; }; // List of all possible GPU offspring static GPUCHILDTYPE gpuChildTypeList[] = { #define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, gpuField) \ - { bConstructEarly, numInstances, NV_OFFSETOF(OBJGPU, gpuField), classInfo(className) }, + { bConstructEarly, numInstances, NV_OFFSETOF(OBJGPU, gpuField), classId(className) }, #include "gpu/gpu_child_list.h" }; @@ -169,23 +164,25 @@ struct GPUCHILDINFO NvBool bConstructEarly; ENGDESCRIPTOR engDesc; NvU32 gpuChildPtrOffset; - const NVOC_CLASS_INFO *pClassInfo; GPUCHILDTYPE *pChildType; }; static PGPUCHILDTYPE gpuGetChildType(NVOC_CLASS_ID classId); static NV_STATUS gpuGetChildInfo(NVOC_CLASS_ID classId, NvU32 instanceID, PGPUCHILDINFO pChildInfoOut); +static NV_STATUS _gpuChildNvocClassInfoGet(OBJGPU *pGpu, NVOC_CLASS_ID classId, const NVOC_CLASS_INFO **ppClassInfo); static Dynamic **gpuGetChildPtr(OBJGPU *pGpu, NvU32 gpuChildPtrOffset); #define GPU_NUM_CHILD_TYPES \ ((sizeof(gpuChildTypeList) / sizeof(GPUCHILDTYPE))) -static void +void _gpuDetectNvswitchSupport ( OBJGPU *pGpu ) { + NvU32 val = pGpu->fabricProbeRegKeyOverride; + // // Slowdown Threshold 0 leads to driver crash with DIVIDE ERROR // Hence setting it to 1 @@ -219,16 +216,21 @@ _gpuDetectNvswitchSupport } } - if (pGpu->fabricProbeRegKeyOverride) + if (val != 0) { - pGpu->fabricProbeSlowdownThreshold = - NV_MAX(DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _SLOWDOWN_THRESHOLD, pGpu->fabricProbeRegKeyOverride), 1); - pGpu->fabricProbeRetryDelay = - DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _DELAY, pGpu->fabricProbeRegKeyOverride); + pGpu->fabricProbeSlowdownThreshold = \ + DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _SLOWDOWN_THRESHOLD, val); + + pGpu->fabricProbeSlowdownThreshold = \ + NV_MAX(pGpu->fabricProbeSlowdownThreshold , 1); - if (pGpu->fabricProbeRetryDelay) + pGpu->fabricProbeRetryDelay = \ + DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _DELAY, val); + + if (pGpu->fabricProbeRetryDelay != 0) { - pGpu->nvswitchSupport = NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED; + pGpu->nvswitchSupport = \ + NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED; } } } @@ -356,6 +358,8 @@ gpuPostConstruct_IMPL if (rmStatus != NV_OK) return rmStatus; + pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, + gpuIsCtxBufAllocInPmaSupported_HAL(pGpu)); // // gpuDetermineVirtualMode inits hPci but only for virtualization case. So if // it does not init it, do here for using it for non-virtualization as well @@ -452,6 +456,19 @@ gpuPostConstruct_IMPL if (rmStatus != NV_OK) return rmStatus; + if (IS_SIMULATION(pGpu) && !IS_VIRTUAL(pGpu)) + { + // + // gpuDetermineSelfHostedMode must be called after gpuDetermineVirtualMode + // and vgpuCreateObject(for VGPU static info) as the self hosted detection mechanism + // in VF depends on them. But in SCSIM(SIM_BUILD) it is required to be called + // before vgpuCreateObject(from where initRpcInfrastructure_VGPU is called) in PF + // so that the correct setting NV_VGPU_SEND_RING_GP_IN_RING_NO is done + // for the SIM escapes. + // + gpuDetermineSelfHostedMode_HAL(pGpu); + } + gpuGetHwDefaults(pGpu); // Handle per-device core logic registry settings @@ -484,6 +501,7 @@ NV_STATUS gpuConstruct_IMPL { pGpu->gpuInstance = gpuInstance; + pGpu->gspRmInitialized = NV_FALSE; // allocate OS-specific GPU extension area osInitOSHwInfo(pGpu); @@ -497,7 +515,8 @@ gpuBindHalLegacy_IMPL ( OBJGPU *pGpu, NvU32 chipId0, - NvU32 chipId1 + NvU32 chipId1, + NvU32 socChipId0 ) { OBJSYS *pSys = SYS_GET_INSTANCE(); @@ -513,7 +532,7 @@ gpuBindHalLegacy_IMPL // The system object will pass PMC_BOOT_0 and PMC_BOOT_42 to all the HAL's and return the // one that claims it supports this chip arch/implementation // - status = halmgrGetHalForGpu(pHalMgr, pGpu->chipId0, pGpu->chipId1, &pGpu->halImpl); + status = halmgrGetHalForGpu(pHalMgr, socChipId0 ? socChipId0 : pGpu->chipId0, pGpu->chipId1, &pGpu->halImpl); if (status != NV_OK) return status; @@ -629,12 +648,13 @@ static NV_STATUS _gpuRmApiAllocWithHandle NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ) { // Simple forwarder for now RM_API *pInternalRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - return pInternalRmApi->AllocWithHandle(pInternalRmApi, hClient, hParent, hObject, hClass, pAllocParams); + return pInternalRmApi->AllocWithHandle(pInternalRmApi, hClient, hParent, hObject, hClass, pAllocParams, paramsSize); } static NV_STATUS _gpuRmApiFree ( @@ -836,7 +856,7 @@ _gpuCreateEngineOrderList ENGLIST_ITER it; ENGDESCRIPTOR engDesc; - ct_assert(NV_ARRAY_ELEMENTS32(ppEngDescriptors) == NV_ARRAY_ELEMENTS32(listTypes)); + ct_assert(NV_ARRAY_ELEMENTS(ppEngDescriptors) == NV_ARRAY_ELEMENTS(listTypes)); #define GPU_CHILD(a, b, numInstances, c, d) +numInstances @@ -853,7 +873,7 @@ _gpuCreateEngineOrderList ct_assert(NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS >= sizeof(((struct ChildList*)(NULL))->children) /* sizeof(ChildList::children) */); - numLists = NV_ARRAY_ELEMENTS32(listTypes); + numLists = NV_ARRAY_ELEMENTS(listTypes); ppEngDescriptors[0] = &pEngineOrder->pEngineInitDescriptors; ppEngDescriptors[1] = &pEngineOrder->pEngineLoadDescriptors; @@ -992,7 +1012,6 @@ gpuGetChildInfo(NVOC_CLASS_ID classId, NvU32 instanceID, PGPUCHILDINFO pChildInf pChildInfoOut->engDesc = MKENGDESC(classId, instanceID); pChildInfoOut->bConstructEarly = pChildType->bConstructEarly; - pChildInfoOut->pClassInfo = pChildType->pClassInfo; pChildInfoOut->pChildType = pChildType; pChildInfoOut->gpuChildPtrOffset = pChildType->gpuChildPtrOffset + sizeof(void *) * instanceID; @@ -1000,6 +1019,58 @@ gpuGetChildInfo(NVOC_CLASS_ID classId, NvU32 instanceID, PGPUCHILDINFO pChildInf return NV_OK; } +/*! + * @brief For a given @ref OBJGPU, given the @ref NVOC_CLASS_ID for an object + * that is a @ref OBJGPU child, this function will return the + * @ref NVOC_CLASS_INFO for the concrete class type that should be + * instantiated for the field with that @ref NVOC_CLASS_ID + * + * @details This function helps support polymorphism of @ref OBJGPU children. + * The provided @ref NVOC_CLASS_ID is the class ID for the base class + * of the pointer field in @ref OBJGPU (e.g., @ref OBJGPU::pPmu), which + * can be made to point at different sub-classes at runtime. This + * function, given that @ref NVOC_CLASS_ID, provides the information + * about which concrete sub-class should actually be constructed. + * + * @param[in] pGpu + * @param[in] classId + * @ref NVOC_CLASS_ID for the class type of the base class pointer in + * @ref OBJGPU + * @param[out] ppClassInfo + * Pointer to location into which to store pointer to the class info for the + * concrete class to be constructed + * + * @return @ref NV_OK + * Success + * @return @ref NV_ERR_INVALID_STATE + * No match for classId found within this @ref OBJGPU's children + */ +static NV_STATUS +_gpuChildNvocClassInfoGet +( + OBJGPU *pGpu, + NVOC_CLASS_ID classId, + const NVOC_CLASS_INFO **ppClassInfo +) +{ + NvU32 numChildPresent; + const GPUCHILDPRESENT *const pChildrenPresent = + gpuGetChildrenPresent_HAL(pGpu, &numChildPresent); + NvU32 i; + + for (i = 0U; i < numChildPresent; i++) + { + if (classId == pChildrenPresent[i].classId) + { + *ppClassInfo = pChildrenPresent[i].pClassInfo; + return NV_OK; + } + } + + DBG_BREAKPOINT(); + return NV_ERR_INVALID_STATE; +} + /*! * @brief Looks up for a class in the table based on class id * @@ -1014,7 +1085,7 @@ gpuGetChildType(NVOC_CLASS_ID classId) for (i = 0; i < GPU_NUM_CHILD_TYPES; i++) { - if (gpuChildTypeList[i].pClassInfo->classId == classId) + if (gpuChildTypeList[i].classId == classId) { return &gpuChildTypeList[i]; } @@ -1058,7 +1129,7 @@ gpuGetNextPossibleEngDescriptor(GPU_CHILD_ITER *pIt, ENGDESCRIPTOR *pEngDesc) // Advance instance # if (pIt->childInst < pChildType->instances) { - NV_STATUS status = gpuGetChildInfo(pChildType->pClassInfo->classId, pIt->childInst, &childInfo); + NV_STATUS status = gpuGetChildInfo(pChildType->classId, pIt->childInst, &childInfo); NV_ASSERT(status == NV_OK); @@ -1217,11 +1288,13 @@ gpuCreateObject_IMPL NvU32 instanceID ) { - NV_STATUS status; - OBJENGSTATE *pEngstate; - GPUCHILDINFO childInfo; - Dynamic **ppChildPtr; - ENGSTATE_TRANSITION_DATA engTransitionData; + NV_STATUS status; + OBJENGSTATE *pEngstate; + GPUCHILDINFO childInfo; + Dynamic **ppChildPtr; + const NVOC_CLASS_INFO *pClassInfo; + Dynamic *pConcreteChild = NULL; + ENGSTATE_TRANSITION_DATA engTransitionData; status = gpuGetChildInfo(classId, instanceID, &childInfo); @@ -1229,14 +1302,27 @@ gpuCreateObject_IMPL ppChildPtr = gpuGetChildPtr(pGpu, childInfo.gpuChildPtrOffset); + NV_ASSERT_OK_OR_RETURN( + _gpuChildNvocClassInfoGet(pGpu, classId, &pClassInfo)); + // Ask the object database utility to create a child object. - status = objCreateDynamic(ppChildPtr, pGpu, childInfo.pClassInfo); + status = objCreateDynamic(&pConcreteChild, pGpu, pClassInfo); if (status != NV_OK) { return status; } - NV_ASSERT_OR_RETURN(*ppChildPtr, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pConcreteChild != NULL, NV_ERR_INVALID_STATE); + + // + // Cast back to a pointer to the base class and assign it into the pointer + // in OBJGPU + // + *ppChildPtr = objDynamicCastById(pConcreteChild, classId); + NV_ASSERT_TRUE_OR_GOTO(status, + (*ppChildPtr != NULL), + NV_ERR_INVALID_STATE, + gpuCreateObject_exit); pEngstate = dynamicCast(*ppChildPtr, OBJENGSTATE); @@ -1262,7 +1348,7 @@ gpuCreateObject_IMPL gpuCreateObject_exit: if (status != NV_OK) { - objDelete(*ppChildPtr); + objDelete(pConcreteChild); *ppChildPtr = NULL; } @@ -1318,6 +1404,12 @@ gpuDestruct_IMPL } } + // Free GPU shared data + memdescUnmap(pGpu->userSharedData.pMemDesc, NV_TRUE, 0, + pGpu->userSharedData.pMapBuffer, pGpu->userSharedData.pMapBufferPriv); + memdescFree(pGpu->userSharedData.pMemDesc); + memdescDestroy(pGpu->userSharedData.pMemDesc); + // Free children in reverse order from construction for (typeNum = GPU_NUM_CHILD_TYPES - 1; typeNum >= 0; typeNum--) { @@ -1327,7 +1419,7 @@ gpuDestruct_IMPL { NV_STATUS status; - status = gpuGetChildInfo(pChildTypeCur->pClassInfo->classId, instNum, &childInfoCur); + status = gpuGetChildInfo(pChildTypeCur->classId, instNum, &childInfoCur); NV_ASSERT(status == NV_OK); @@ -1417,7 +1509,7 @@ gpuCreateChildObjects for (i = 0; i < pChildTypeCur->instances; i++) { - NVOC_CLASS_ID classId = pChildTypeCur->pClassInfo->classId; + NVOC_CLASS_ID classId = pChildTypeCur->classId; rmStatus = gpuGetChildInfo(classId, i, &childInfoCur); @@ -1544,7 +1636,7 @@ static NV_STATUS gspSupportsEngine(OBJGPU *pGpu, ENGDESCRIPTOR engdesc, NvBool * return NV_OK; } -/* +/*! * The engine removal protocol is as follows: * - engines returning an error code from ConstructEngine will be immediately * removed (this happens in gpuCreateObject) @@ -1556,6 +1648,11 @@ static NV_STATUS gspSupportsEngine(OBJGPU *pGpu, ENGDESCRIPTOR engdesc, NvBool * * gpuRemoveMissingEngines takes place before the main loop in gpuStatePreInit * and is responsible for removing engines satisfying the last two bullets * above. + * + * Additionally, note that this function handles engines that were never + * present according to gpuChildrenPresent_HAL; these engines' associated + * classes must be removed from the class DB, and that is handled via this + * function. */ static NV_STATUS gpuRemoveMissingEngines @@ -1567,6 +1664,7 @@ gpuRemoveMissingEngines PENGDESCRIPTOR engDescriptorList = gpuGetInitEngineDescriptors(pGpu); NvU32 numEngDescriptors = gpuGetNumEngDescriptors(pGpu); NV_STATUS rmStatus = NV_OK; + NvU32 curClassDescIdx; // Order is determined by gpuGetChildrenOrder_HAL pulling gpuChildOrderList array for (curEngDescIdx = 0; curEngDescIdx < numEngDescriptors; curEngDescIdx++) @@ -1607,6 +1705,61 @@ gpuRemoveMissingEngines NV_ASSERT(rmStatus == NV_OK || !"Error while trying to remove missing engine"); } + // + // Check the rest of the class descriptors for engines that are not part of + // the present list, and therefore not part of the init list, and ensure + // that those get removed from the class DB. + // + for (curClassDescIdx = 0U; + curClassDescIdx < pGpu->engineOrder.numClassDescriptors; + curClassDescIdx++) + { + const GPU_RESOURCE_DESC *const pCurDesc = + &pGpu->engineOrder.pClassDescriptors[curClassDescIdx]; + NvBool bGspSupportsEngine; + + // + // Skip any classes which: + // 1.) Do not have an engine class ID + // 2.) Have an engine of GPU. ENG_GPU does not correspond to an + // OBJENGSTATE, and it can never be missing. + // 3.) Have an OBJENGSTATE that is present + // + if ((ENGDESC_FIELD(pCurDesc->engDesc, _CLASS) == classId(OBJINVALID)) || + (pCurDesc->engDesc == ENG_GPU) || + gpuGetEngstate(pGpu, pCurDesc->engDesc) != NULL) + { + continue; + } + + // + // If the engstate is NULL, the engine may still be supported on GSP. If + // it is, we can skip removing it. + // + // Note that if the function returns NV_WARN_NOTHING_TO_DO, this means + // GSP-RM is not running and thus the engine cannot be supported within + // GSP. + // + rmStatus = gspSupportsEngine(pGpu, pCurDesc->engDesc, &bGspSupportsEngine); + if (rmStatus == NV_WARN_NOTHING_TO_DO) + { + rmStatus = NV_OK; + bGspSupportsEngine = NV_FALSE; + } + NV_ASSERT_OK_OR_RETURN(rmStatus); + if (bGspSupportsEngine) + { + continue; + } + + NV_ASSERT_OK_OR_RETURN( + gpuDeleteClassFromClassDBByEngTag(pGpu, pCurDesc->engDesc)); + } + + // Update the engine table after deleting any classes from the class DB + NV_ASSERT_OK_OR_RETURN( + gpuUpdateEngineTable(pGpu)); + return rmStatus; } @@ -1885,6 +2038,18 @@ gpuStatePreInit_IMPL // Set PDB properties as per data from GSP. gpuInitProperties(pGpu); + // + // gpuDetermineSelfHostedMode must be called after gpuDetermineVirtualMode/kgspInitRm + // where VGPU/GSP static info is populated as the self hosted detection mechanism + // in VF and Kernel-RM depends on them respectively. + // + // For Kernel-RM, gpuDetermineSelfHostedMode_HAL should be called in + // gpuStatePreInit because GSP static config gets populated only by + // PreInit and also all the gpuIsSelfHosted callers are from PreInit and + // onwards. + // + gpuDetermineSelfHostedMode_HAL(pGpu); + LOCK_ASSERT_AND_RETURN(rmGpuLockIsOwner()); NV_ASSERT_OK_OR_RETURN(_gpuAllocateInternalObjects(pGpu)); @@ -1892,6 +2057,12 @@ gpuStatePreInit_IMPL NV_ASSERT_OK_OR_RETURN(gpuConstructUserRegisterAccessMap(pGpu)); NV_ASSERT_OK_OR_RETURN(gpuBuildGenericKernelFalconList(pGpu)); + // + // Must be called after _gpuInitChipInfo since gpuDetermineMIGSupport_HAL + // reads chip revision and that is available only after _gpuInitChipInfo. + // + gpuDetermineMIGSupport_HAL(pGpu); + rmStatus = gpuRemoveMissingEngines(pGpu); NV_ASSERT(rmStatus == NV_OK); @@ -2160,13 +2331,15 @@ gpuStateLoad_IMPL return status; } - // It is a no-op on baremetal and inside non SRIOV guest. - rmStatus = gpuCreateDefaultClientShare_HAL(pGpu); - if (rmStatus != NV_OK) + if (!(flags & GPU_STATE_FLAGS_PRESERVING)) { - return rmStatus; + // It is a no-op on baremetal and inside non SRIOV guest. + rmStatus = gpuCreateDefaultClientShare_HAL(pGpu); + if (rmStatus != NV_OK) + { + return rmStatus; + } } - NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); rmStatus = gpuStatePreLoad(pGpu, flags); @@ -2371,13 +2544,13 @@ _gpuPropagateP2PCapsToAllGpus NV_ERR_NO_MEMORY); peerGpuIds = portMemAllocNonPaged(sizeof(*peerGpuIds) * - NV_ARRAY_ELEMENTS32(pSetP2PCapsParams->peerGpuInfos)); + NV_ARRAY_ELEMENTS(pSetP2PCapsParams->peerGpuInfos)); NV_CHECK_OR_ELSE(LEVEL_ERROR, peerGpuIds != NULL, status = NV_ERR_NO_MEMORY; goto exit); peerGpuInstances = portMemAllocNonPaged(sizeof(*peerGpuInstances) * - NV_ARRAY_ELEMENTS32(pSetP2PCapsParams->peerGpuInfos)); + NV_ARRAY_ELEMENTS(pSetP2PCapsParams->peerGpuInfos)); NV_CHECK_OR_ELSE(LEVEL_ERROR, peerGpuInstances != NULL, status = NV_ERR_NO_MEMORY; goto exit); @@ -2634,7 +2807,7 @@ gpuStatePostLoad pGpu->boardInfo = NULL; } } - NV_ASSERT_OR_GOTO(gpuFabricProbeStart(pGpu, &pGpu->pGpuFabricProbeInfo) == NV_OK, + NV_ASSERT_OR_GOTO(gpuFabricProbeStart(pGpu, &pGpu->pGpuFabricProbeInfoKernel) == NV_OK, gpuStatePostLoad_exit); gpuStatePostLoad_exit: @@ -2674,7 +2847,7 @@ gpuStatePreUnload rmapiControlCacheFreeAllCacheForGpu(pGpu->gpuInstance); - gpuFabricProbeStop(pGpu->pGpuFabricProbeInfo); + gpuFabricProbeStop(pGpu->pGpuFabricProbeInfoKernel); portMemFree(pGpu->boardInfo); pGpu->boardInfo = NULL; @@ -2834,7 +3007,8 @@ gpuStateUnload_IMPL rmStatus = gpuStatePostUnload(pGpu, flags); NV_ASSERT_OK(rmStatus); - gpuDestroyDefaultClientShare_HAL(pGpu); + if(!(flags & GPU_STATE_FLAGS_PRESERVING)) + gpuDestroyDefaultClientShare_HAL(pGpu); // De-init SRIOV gpuDeinitSriov_HAL(pGpu); @@ -3130,7 +3304,7 @@ gpuInitOptimusSettings_IMPL(OBJGPU *pGpu) if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "SBIOS did not acknowledge cfg space owner change\n"); } @@ -4035,6 +4209,7 @@ gpuSetDisconnectedProperties_IMPL pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_STANDBY, NV_FALSE); pGpu->bInD3Cold = NV_FALSE; pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_HIBERNATE, NV_FALSE); + SET_GPU_GC6_STATE(pGpu, GPU_GC6_STATE_POWERED_ON); } @@ -4568,9 +4743,72 @@ gpuInitDispIpHal_IMPL __nvoc_init_funcTable_DisplayInstanceMemory(KERNEL_DISPLAY_GET_INST_MEM(pKernelDisplay), pRmHalspecOwner); + void __nvoc_init_funcTable_KernelHead(KernelHead *, RmHalspecOwner *); + NvU32 headIdx; + + for (headIdx = 0; headIdx < OBJ_MAX_HEADS; headIdx++) + { + __nvoc_init_funcTable_KernelHead(KDISP_GET_HEAD(pKernelDisplay, headIdx), + pRmHalspecOwner); + } + return NV_OK; } +/*! + *@brief Check if CC feature is enabled + */ +NvBool +gpuIsCCFeatureEnabled_IMPL(OBJGPU *pGpu) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + if (pCC != NULL) + { + return pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED); + } + return NV_FALSE; +} + +/*! + *@brief Check if APM feature is enabled + */ +NvBool +gpuIsApmFeatureEnabled_IMPL(OBJGPU *pGpu) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + if (pCC != NULL) + { + return pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED); + } + return NV_FALSE; +} + +/*! + *@brief Check if either CC or APM feature is enabled + */ +NvBool +gpuIsCCorApmFeatureEnabled_IMPL(OBJGPU *pGpu) +{ + return gpuIsCCFeatureEnabled(pGpu) || gpuIsApmFeatureEnabled(pGpu); +} + +/*! + *@brief Check if CC devtools mode is enabled + */ +NvBool +gpuIsCCDevToolsModeEnabled_IMPL(OBJGPU *pGpu) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + if ((pCC != NULL) && gpuIsCCFeatureEnabled(pGpu)) + { + return pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED); + } + return NV_FALSE; +} + /*! * @brief: Initialize chip related info * This function fills up the chip info structure of OBJGPU. @@ -4867,3 +5105,4 @@ gpuSetGC6SBIOSCapabilities_IMPL(OBJGPU *pGpu) return NV_OK; } + diff --git a/src/nvidia/src/kernel/gpu/gpu_access.c b/src/nvidia/src/kernel/gpu/gpu_access.c index f0a73cd10c..bd1865110c 100644 --- a/src/nvidia/src/kernel/gpu/gpu_access.c +++ b/src/nvidia/src/kernel/gpu/gpu_access.c @@ -1601,7 +1601,7 @@ gpuValidateRegOffset_IMPL { NvU64 maxBar0Size = pGpu->deviceMappings[0].gpuNvLength; - // The register offset should be 4 bytes smaller than the max bar size + // The register offset should be 4 bytes smaller than the max bar size if (offset > (maxBar0Size - 4)) { return NV_ERR_INVALID_ARGUMENT; diff --git a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c index ef8c76b25c..4feb835d35 100644 --- a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c +++ b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,54 +29,47 @@ #include "gpu/gpu.h" #include "os/os.h" -#include "objtmr.h" #include "utils/nvprintf.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" -#include "ctrl/ctrl2080/ctrl2080pmgr.h" #include "gpu/gpu_fabric_probe.h" -#include "compute/fabric.h" #include "nvlink_inband_msg.h" #include "kernel/mem_mgr/fabric_vaspace.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" // Structure to hold gpu probe information -typedef struct GPU_FABRIC_PROBE_INFO +typedef struct GPU_FABRIC_PROBE_INFO_KERNEL { - NvU64 probeRetryDelay; NvBool bProbeRespRcvd; - NvU64 numProbes; + NvU8 bwMode; OBJGPU *pGpu; - TMR_EVENT *pTmrEvent; - - NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS sendDataParams; nvlink_inband_gpu_probe_rsp_msg_t probeResponseMsg; -} GPU_FABRIC_PROBE_INFO; - +} GPU_FABRIC_PROBE_INFO_KERNEL; static NV_STATUS _gpuFabricProbeFullSanityCheck ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_ERR_NOT_SUPPORTED; } LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfo->pGpu))); + gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); - if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) + if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfoKernel)) { return NV_ERR_NOT_READY; } - if (!gpuFabricProbeIsSuccess(pGpuFabricProbeInfo)) + if (!gpuFabricProbeIsSuccess(pGpuFabricProbeInfoKernel)) { - return pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status; + return pGpuFabricProbeInfoKernel->probeResponseMsg.msgHdr.status; } return NV_OK; @@ -85,17 +78,17 @@ _gpuFabricProbeFullSanityCheck NV_STATUS gpuFabricProbeGetGpuFabricHandle ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pHandle ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pHandle = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpuHandle; + *pHandle = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpuHandle; return status; } @@ -103,17 +96,17 @@ gpuFabricProbeGetGpuFabricHandle NV_STATUS gpuFabricProbeGetGfId ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU32 *pGfId ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pGfId = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gfId; + *pGfId = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gfId; return status; } @@ -121,17 +114,17 @@ gpuFabricProbeGetGfId NV_STATUS gpuFabricProbeGetfmCaps ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pFmCaps ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pFmCaps = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps; + *pFmCaps = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fmCaps; return status; } @@ -139,20 +132,20 @@ gpuFabricProbeGetfmCaps NV_STATUS gpuFabricProbeGetClusterUuid ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvUuid *pClusterUuid ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); portMemCopy(&pClusterUuid->uuid[0], sizeof(pClusterUuid->uuid), - &pGpuFabricProbeInfo->probeResponseMsg.probeRsp.clusterUuid.uuid[0], - sizeof(pGpuFabricProbeInfo->probeResponseMsg.probeRsp.clusterUuid.uuid)); + &pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.clusterUuid.uuid[0], + sizeof(pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.clusterUuid.uuid)); return status; } @@ -160,17 +153,17 @@ gpuFabricProbeGetClusterUuid NV_STATUS gpuFabricProbeGetFabricPartitionId ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU16 *pFabricPartitionId ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pFabricPartitionId = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fabricPartitionId; + *pFabricPartitionId = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fabricPartitionId; return status; } @@ -178,17 +171,17 @@ gpuFabricProbeGetFabricPartitionId NV_STATUS gpuFabricProbeGetGpaAddress ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pGpaAddress ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pGpaAddress = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpaAddress; + *pGpaAddress = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpaAddress; return status; } @@ -196,17 +189,17 @@ gpuFabricProbeGetGpaAddress NV_STATUS gpuFabricProbeGetGpaAddressRange ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pGpaAddressRange ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pGpaAddressRange = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpaAddressRange; + *pGpaAddressRange = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpaAddressRange; return status; } @@ -214,17 +207,17 @@ gpuFabricProbeGetGpaAddressRange NV_STATUS gpuFabricProbeGetFlaAddress ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pFlaAddress ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pFlaAddress = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.flaAddress; + *pFlaAddress = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.flaAddress; return status; } @@ -232,17 +225,17 @@ gpuFabricProbeGetFlaAddress NV_STATUS gpuFabricProbeGetFlaAddressRange ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *pFlaAddressRange ) { NV_STATUS status; - status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *pFlaAddressRange = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.flaAddressRange; + *pFlaAddressRange = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.flaAddressRange; return status; } @@ -250,19 +243,34 @@ gpuFabricProbeGetFlaAddressRange NV_STATUS gpuFabricProbeGetNumProbeReqs ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU64 *numProbes ) { - if (pGpuFabricProbeInfo == NULL) + NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS params = { 0 }; + RM_API *pRmApi; + OBJGPU *pGpu; + + if (pGpuFabricProbeInfoKernel == NULL) { return NV_ERR_NOT_SUPPORTED; } + pGpu = pGpuFabricProbeInfoKernel->pGpu; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfo->pGpu))); + gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO, + ¶ms, + sizeof(params))); - *numProbes = pGpuFabricProbeInfo->numProbes; + *numProbes = params.numProbes; return NV_OK; } @@ -270,40 +278,40 @@ gpuFabricProbeGetNumProbeReqs NvBool gpuFabricProbeIsReceived ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_FALSE; } LOCK_ASSERT_AND_RETURN_BOOL(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfo->pGpu)), + gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu)), NV_FALSE); - return pGpuFabricProbeInfo->bProbeRespRcvd; + return pGpuFabricProbeInfoKernel->bProbeRespRcvd; } NvBool gpuFabricProbeIsSuccess ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { nvlink_inband_gpu_probe_rsp_msg_t *pProbeResponseMsg; nvlink_inband_msg_header_t *pProbeRespMsgHdr; - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_FALSE; } LOCK_ASSERT_AND_RETURN_BOOL(rmDeviceGpuLockIsOwner(gpuGetInstance( - pGpuFabricProbeInfo->pGpu)), + pGpuFabricProbeInfoKernel->pGpu)), NV_FALSE); - pProbeResponseMsg = &pGpuFabricProbeInfo->probeResponseMsg; + pProbeResponseMsg = &pGpuFabricProbeInfoKernel->probeResponseMsg; pProbeRespMsgHdr = &pProbeResponseMsg->msgHdr; return pProbeRespMsgHdr->status == NV_OK; @@ -312,188 +320,25 @@ gpuFabricProbeIsSuccess NV_STATUS gpuFabricProbeGetFmStatus ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_ERR_NOT_SUPPORTED; } LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfo->pGpu))); - - return pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status; -} - -static void -_gpuFabricProbeForceCompletionError -( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, - NV_STATUS status -) -{ - NV_ASSERT(!pGpuFabricProbeInfo->bProbeRespRcvd); - pGpuFabricProbeInfo->bProbeRespRcvd = NV_TRUE; - pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status = status; -} - -static NV_STATUS -_gpuFabricProbeSchedule -( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo -) -{ - NV_STATUS status; - OBJGPU *pGpu = pGpuFabricProbeInfo->pGpu; - OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - - NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); - - status = tmrEventScheduleRel(pTmr, pGpuFabricProbeInfo->pTmrEvent, - pGpuFabricProbeInfo->probeRetryDelay); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u tmrEventScheduleRel failed\n", - gpuGetInstance(pGpu)); - return status; - } - - pGpuFabricProbeInfo->numProbes++; - - if ((pGpuFabricProbeInfo->numProbes % - pGpu->fabricProbeSlowdownThreshold) == 0) - { - pGpuFabricProbeInfo->probeRetryDelay += pGpuFabricProbeInfo->probeRetryDelay; - } - - NV_PRINTF(LEVEL_INFO, "GPU%u Num retried probes %lld \n", - gpuGetInstance(pGpu), pGpuFabricProbeInfo->numProbes); - - return NV_OK; -} - -static NV_STATUS -_gpuFabricProbeConstructReq -( - nvlink_inband_gpu_probe_req_t *pProbeReq, - OBJGPU *pGpu -) -{ - NV_STATUS status; - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - NvU8 *pUuid; - NvU32 uuidLength, flags = 0; - - portMemSet(pProbeReq, 0, sizeof(*pProbeReq)); - - flags = FLD_SET_DRF_NUM(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, - NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1, flags); - flags = FLD_SET_DRF_NUM(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, - NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY, flags); - status = gpuGetGidInfo(pGpu, &pUuid, &uuidLength, flags); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Failed to update GPU UUID\n", - gpuGetInstance(pGpu)); - return status; - } - portMemCopy(&pProbeReq->gpuUuid.uuid[0], uuidLength, pUuid, uuidLength); - portMemFree(pUuid); - - pProbeReq->pciInfo = gpuGetDBDF(pGpu); - pProbeReq->moduleId = pGpu->moduleId; - pProbeReq->discoveredLinkMask = pKernelNvlink->discoveredLinks; - pProbeReq->enabledLinkMask = pKernelNvlink->enabledLinks; - pProbeReq->gpuCapMask = (IS_VIRTUAL_WITH_SRIOV(pGpu)) ? - NVLINK_INBAND_GPU_PROBE_CAPS_SRIOV_ENABLED : 0; - return status; -} - -static void -_gpuFabricProbeSend_WORKITEM -( - NvU32 gpuInstance, - void *pArgs -) -{ - OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo = pGpu->pGpuFabricProbeInfo; - NV_STATUS status; - - if (pKernelNvlink->bIsGpuDegraded || - (pKernelNvlink->discoveredLinks == 0)) - { - NV_PRINTF(LEVEL_ERROR, - "GPU%u Degraded. Not sending probe\n", - gpuGetInstance(pGpu)); - _gpuFabricProbeForceCompletionError(pGpuFabricProbeInfo, NV_ERR_NOT_SUPPORTED); - return; - } - - if (pGpuFabricProbeInfo->bProbeRespRcvd) - { - NV_PRINTF(LEVEL_INFO, - "GPU%u Probe Resp rcvd. Not sending probe\n", - gpuGetInstance(pGpu)); - return; - } - - status = knvlinkSendInbandData(pGpu, - pKernelNvlink, - &pGpuFabricProbeInfo->sendDataParams); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Send Inband data failed\n", - gpuGetInstance(pGpu)); - // - // Deliberately ignoring return value as we want probes to be - // retried until success - // - } + gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); - status = _gpuFabricProbeSchedule(pGpuFabricProbeInfo); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Schedule Probe failed\n", - gpuGetInstance(pGpu)); - _gpuFabricProbeForceCompletionError(pGpuFabricProbeInfo, NV_ERR_OPERATING_SYSTEM); - return; - } + return pGpuFabricProbeInfoKernel->probeResponseMsg.msgHdr.status; } -static NV_STATUS -_gpuFabricProbeScheduleWq -( - OBJGPU *pGpu, - OBJTMR *pTmr, - TMR_EVENT *pEvent -) -{ - OBJOS *pOS = GPU_GET_OS(pGpu); - NV_STATUS status = NV_OK; - - NV_ASSERT_OR_RETURN(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)), NV_ERR_INVALID_STATE); - - status = pOS->osQueueWorkItemWithFlags(pGpu, _gpuFabricProbeSend_WORKITEM, NULL, - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u OS Schedule Probe failed\n", - gpuGetInstance(pGpu)); - _gpuFabricProbeForceCompletionError(pGpu->pGpuFabricProbeInfo, NV_ERR_OPERATING_SYSTEM); - } - - return status; -} - - static void _gpuFabricProbeSetupGpaRange ( OBJGPU *pGpu, - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); @@ -503,19 +348,17 @@ _gpuFabricProbeSetupGpaRange NvU64 gpaAddress; NvU64 gpaAddressSize; - NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - gpuFabricProbeGetGpaAddress(pGpuFabricProbeInfo, - &gpaAddress) == NV_OK); + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + gpuFabricProbeGetGpaAddress(pGpuFabricProbeInfoKernel, + &gpaAddress) == NV_OK); + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + gpuFabricProbeGetGpaAddressRange(pGpuFabricProbeInfoKernel, + &gpaAddressSize) == NV_OK); NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - gpuFabricProbeGetGpaAddressRange(pGpuFabricProbeInfo, - &gpaAddressSize) == NV_OK); - - //pKernelNvlink->fabricBaseAddr = gpaAddress; - NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, - pKernelNvlink, - gpaAddress) == NV_OK); + knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, + gpaAddress) == NV_OK); } } @@ -523,7 +366,7 @@ static void _gpuFabricProbeSetupFlaRange ( OBJGPU *pGpu, - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { if (pGpu->pFabricVAS != NULL) @@ -532,19 +375,21 @@ _gpuFabricProbeSetupFlaRange NvU64 flaSize; NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - gpuFabricProbeGetFlaAddress(pGpuFabricProbeInfo, &flaBaseAddress) == NV_OK); + gpuFabricProbeGetFlaAddress(pGpuFabricProbeInfoKernel, + &flaBaseAddress) == NV_OK); NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - gpuFabricProbeGetFlaAddressRange(pGpuFabricProbeInfo, &flaSize) == NV_OK); + gpuFabricProbeGetFlaAddressRange(pGpuFabricProbeInfoKernel, + &flaSize) == NV_OK); NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - fabricvaspaceInitUCRange(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), - pGpu, flaBaseAddress, flaSize) == NV_OK); + fabricvaspaceInitUCRange(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), + pGpu, flaBaseAddress, flaSize) == NV_OK); } } -void -_gpuFabricProbeReceive +static NV_STATUS +_gpuFabricProbeReceiveKernel ( NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams @@ -553,43 +398,38 @@ _gpuFabricProbeReceive OBJGPU *pGpu; NvU32 gpuMaskUnused; nvlink_inband_gpu_probe_rsp_msg_t *pProbeRespMsg; - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; - nvlink_inband_gpu_probe_req_msg_t *pProbeReqMsg = NULL; - NvU8 *pRsvd = NULL; + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; + NV_STATUS status; if ((pGpu = gpumgrGetGpu(gpuInstance)) == NULL) { NV_ASSERT_FAILED("Invalid GPU instance"); - return; + return NV_ERR_INVALID_ARGUMENT; } - NV_ASSERT(rmGpuGroupLockIsOwner(gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskUnused)); - - NV_ASSERT(pInbandRcvParams != NULL); + // + // There is a scenario where _gpuFabricProbeStart fails in the GSP + // and returns failure to kernel ctrl call to start probe. + // This will set the pGpuFabricProbeInfoKernel to NULL. + // GSP also sends a probe response with failure error code. + // Handling this response causes kernel driver to crash since + // pGpuFabricProbeInfoKernel is already cleared in the kernel. + // This check is added to handle this scenario. + // + NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu->pGpuFabricProbeInfoKernel != NULL, NV_OK); - pGpuFabricProbeInfo = pGpu->pGpuFabricProbeInfo; + NV_ASSERT(rmGpuGroupLockIsOwner(gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + &gpuMaskUnused)); - pProbeReqMsg = (nvlink_inband_gpu_probe_req_msg_t *)&pGpuFabricProbeInfo-> - sendDataParams.buffer[0]; - pProbeRespMsg = (nvlink_inband_gpu_probe_rsp_msg_t *)&pInbandRcvParams->data[0]; + NV_ASSERT(pInbandRcvParams != NULL); - if (pProbeRespMsg->msgHdr.requestId != pProbeReqMsg->msgHdr.requestId) - { - NV_PRINTF(LEVEL_INFO, - "GPU%u Probe resp invalid reqId %lld respId %lld\n", - gpuInstance, - pProbeReqMsg->msgHdr.requestId, - pProbeRespMsg->msgHdr.requestId); - return; - } + pGpuFabricProbeInfoKernel = pGpu->pGpuFabricProbeInfoKernel; - // Assert reserved in probeResponse are zero - pRsvd = &pProbeRespMsg->probeRsp.reserved[0]; - NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, - sizeof(pProbeRespMsg->probeRsp.reserved) - 1) == 0); + pProbeRespMsg = \ + (nvlink_inband_gpu_probe_rsp_msg_t *)&pInbandRcvParams->data[0]; - portMemCopy(&pGpuFabricProbeInfo->probeResponseMsg, - sizeof(pGpuFabricProbeInfo->probeResponseMsg), + portMemCopy(&pGpuFabricProbeInfoKernel->probeResponseMsg, + sizeof(pGpuFabricProbeInfoKernel->probeResponseMsg), pProbeRespMsg, sizeof(*pProbeRespMsg)); @@ -597,157 +437,113 @@ _gpuFabricProbeReceive // TODO - Add additional check with versioning to continue with the // timer and send lower version requests // - pGpuFabricProbeInfo->bProbeRespRcvd = NV_TRUE; + pGpuFabricProbeInfoKernel->bProbeRespRcvd = NV_TRUE; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, - _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo) == NV_OK); - _gpuFabricProbeSetupGpaRange(pGpu, pGpuFabricProbeInfo); - _gpuFabricProbeSetupFlaRange(pGpu, pGpuFabricProbeInfo); + _gpuFabricProbeSetupGpaRange(pGpu, pGpuFabricProbeInfoKernel); + _gpuFabricProbeSetupFlaRange(pGpu, pGpuFabricProbeInfoKernel); + + return NV_OK; } void gpuFabricProbeSuspend ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { OBJGPU *pGpu; - OBJTMR *pTmr; + RM_API *pRmApi; + NV_STATUS status; - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return; } - pGpu = pGpuFabricProbeInfo->pGpu; + pGpu = pGpuFabricProbeInfoKernel->pGpu; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - pTmr = GPU_GET_TIMER(pGpu); - - NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); - - if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) - { - tmrEventCancel(pTmr, pGpuFabricProbeInfo->pTmrEvent); - } + NV_CHECK_OK(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE, + NULL, 0)); } NV_STATUS gpuFabricProbeResume ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { OBJGPU *pGpu; - NV_STATUS status = NV_OK; + RM_API *pRmApi; + NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS params = { 0 }; - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return NV_ERR_NOT_SUPPORTED; } - pGpu = pGpuFabricProbeInfo->pGpu; + pGpu = pGpuFabricProbeInfoKernel->pGpu; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); + params.bwMode = pGpuFabricProbeInfoKernel->bwMode; - if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) - { - status = _gpuFabricProbeSchedule(pGpuFabricProbeInfo); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Resume and Sending probe request failed\n", - gpuGetInstance(pGpu)); - } - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE, + ¶ms, sizeof(params))); - return status; + return NV_OK; } NV_STATUS gpuFabricProbeStart ( OBJGPU *pGpu, - GPU_FABRIC_PROBE_INFO **ppGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL **ppGpuFabricProbeInfoKernel ) { NV_STATUS status; - OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - nvlink_inband_gpu_probe_req_msg_t *pProbeReqMsg = NULL; - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; NVLINK_INBAND_MSG_CALLBACK inbandMsgCbParams; KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS params = { 0 }; LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - // - // TODO - probe versioning - // After retrying the latest version probe for a few times, if GPU - // doesn't receive any response, GPU fallsback to the previous - // version of probe request. This process continues until it - // reaches the lowest possible probe request version - // - // Check if NVSwitch based system. If not return without doing anything if (!gpuFabricProbeIsSupported(pGpu)) { return NV_OK; } - *ppGpuFabricProbeInfo = portMemAllocNonPaged(sizeof(*pGpuFabricProbeInfo)); - NV_ASSERT_OR_RETURN(*ppGpuFabricProbeInfo != NULL, NV_ERR_NO_MEMORY); - - pGpuFabricProbeInfo = *ppGpuFabricProbeInfo; - - portMemSet(pGpuFabricProbeInfo, 0, sizeof(*pGpuFabricProbeInfo)); + *ppGpuFabricProbeInfoKernel = portMemAllocNonPaged(sizeof(*pGpuFabricProbeInfoKernel)); + NV_ASSERT_OR_RETURN(*ppGpuFabricProbeInfoKernel != NULL, NV_ERR_NO_MEMORY); - pGpuFabricProbeInfo->pGpu = pGpu; + pGpuFabricProbeInfoKernel = *ppGpuFabricProbeInfoKernel; - status = tmrEventCreate(pTmr, &pGpuFabricProbeInfo->pTmrEvent, - _gpuFabricProbeScheduleWq, NULL, TMR_FLAGS_NONE); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Timer create failure\n", - gpuGetInstance(pGpu)); - goto fail; - } - - pGpuFabricProbeInfo->probeRetryDelay = - pGpu->fabricProbeRetryDelay * GPU_FABRIC_PROBE_SEC_TO_NS; + portMemSet(pGpuFabricProbeInfoKernel, 0, sizeof(*pGpuFabricProbeInfoKernel)); - ct_assert(sizeof(nvlink_inband_gpu_probe_req_msg_t) <= - sizeof(pGpuFabricProbeInfo->sendDataParams.buffer)); - - pProbeReqMsg = (nvlink_inband_gpu_probe_req_msg_t *)&pGpuFabricProbeInfo-> - sendDataParams.buffer[0]; - - status = _gpuFabricProbeConstructReq(&pProbeReqMsg->probeReq, pGpu); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Init Probe request failed\n", - gpuGetInstance(pGpu)); - goto fail; - } - - status = fabricInitInbandMsgHdr(&pProbeReqMsg->msgHdr, - NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REQ, - sizeof(pProbeReqMsg->probeReq)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Init of Inband msg hdr failed\n", - gpuGetInstance(pGpu)); - goto fail; - } - - pGpuFabricProbeInfo->sendDataParams.dataSize = sizeof(*pProbeReqMsg); + pGpuFabricProbeInfoKernel->pGpu = pGpu; // Register the receive callback inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP; - inbandMsgCbParams.pCallback = _gpuFabricProbeReceive; + inbandMsgCbParams.pCallback = _gpuFabricProbeReceiveKernel; inbandMsgCbParams.wqItemFlags = (OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); status = knvlinkRegisterInbandCallback(pGpu, pKernelNvlink, &inbandMsgCbParams); @@ -758,30 +554,23 @@ gpuFabricProbeStart goto fail; } - // - // Queue the probe work item directly (without timer delay). - // A small timer delay is likely to fire and be unable to acquire the lock - // (because we'll still be holding it). The timer event will be used if the - // probe work item needs to be rescheduled with a delay. - // - status = _gpuFabricProbeScheduleWq(pGpu, pTmr, pGpuFabricProbeInfo->pTmrEvent); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u failed to schedule probe work item (status = 0x%x)\n", - gpuGetInstance(pGpu), status); - goto fail; - } + pGpuFabricProbeInfoKernel->bwMode = gpumgrGetGpuNvlinkBwMode(); + params.bwMode = pGpuFabricProbeInfoKernel->bwMode; + + // Send IOCTL to start probe + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE, + ¶ms, sizeof(params)), + fail); return NV_OK; fail: - if (pGpuFabricProbeInfo->pTmrEvent != NULL) - { - tmrEventDestroy(pTmr, pGpuFabricProbeInfo->pTmrEvent); - } - - portMemFree(pGpuFabricProbeInfo); - pGpu->pGpuFabricProbeInfo = NULL; + portMemFree(pGpuFabricProbeInfoKernel); + pGpu->pGpuFabricProbeInfoKernel = NULL; return status; } @@ -789,39 +578,39 @@ gpuFabricProbeStart void gpuFabricProbeStop ( - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel ) { OBJGPU *pGpu; - OBJTMR *pTmr; KernelNvlink *pKernelNvlink; + RM_API *pRmApi; - if (pGpuFabricProbeInfo == NULL) + if (pGpuFabricProbeInfoKernel == NULL) { return; } - pGpu = pGpuFabricProbeInfo->pGpu; + pGpu = pGpuFabricProbeInfoKernel->pGpu; NV_ASSERT_OR_RETURN_VOID(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - pTmr = GPU_GET_TIMER(pGpu); pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - NV_ASSERT(pKernelNvlink != NULL); // Unregister the receive callback NV_ASSERT_OK(knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP)); - if (pGpuFabricProbeInfo->pTmrEvent != NULL) - { - tmrEventDestroy(pTmr, pGpuFabricProbeInfo->pTmrEvent); - } + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - portMemFree(pGpuFabricProbeInfo); + NV_ASSERT_OK(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE, + NULL, 0)); - pGpu->pGpuFabricProbeInfo = NULL; + portMemFree(pGpuFabricProbeInfoKernel); + pGpu->pGpuFabricProbeInfoKernel = NULL; } NvBool @@ -844,3 +633,173 @@ gpuFabricProbeIsSupported return NV_TRUE; } + +static void +_gpuFabricProbeInvalidate +( + OBJGPU *pGpu +) +{ + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel = + pGpu->pGpuFabricProbeInfoKernel; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + + pGpuFabricProbeInfoKernel->bProbeRespRcvd = NV_FALSE; + + if (pKernelNvlink != NULL) + knvlinkClearUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink); + + if (pFabricVAS != NULL) + fabricvaspaceClearUCRange(pFabricVAS); +} + +#define GPU_FABRIC_CHECK_BW_MODE(fmCaps, mode) \ + do \ + { \ + if ((fmCaps & NVLINK_INBAND_FM_CAPS_BW_MODE_##mode) == 0) \ + return NV_ERR_NOT_SUPPORTED; \ + } while (0) + +static NV_STATUS +_gpuFabricProbeUpdateBwMode +( + OBJGPU *pGpu, + NvU8 mode +) +{ + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel = + pGpu->pGpuFabricProbeInfoKernel; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + pGpuFabricProbeInfoKernel->bwMode = mode; + + gpuFabricProbeSuspend(pGpuFabricProbeInfoKernel); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE, + NULL, 0)); + + _gpuFabricProbeInvalidate(pGpu); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gpuFabricProbeResume(pGpuFabricProbeInfoKernel)); + + return NV_OK; +} + +NV_STATUS +gpuFabricProbeSetBwMode +( + NvU8 mode +) +{ + NvU32 attachedGpuCount; + NvU32 attachedGpuMask; + NV_STATUS status; + NvU32 gpuIndex; + OBJGPU *pGpu; + + status = gpumgrGetGpuAttachInfo(&attachedGpuCount, &attachedGpuMask); + if (status != NV_OK) + { + return NV_ERR_INVALID_STATE; + } + + // Check if all GPUs belong to NvSwitch + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + if (!gpuFabricProbeIsSupported(pGpu)) + { + // For directed connected system + return NV_OK; + } + } + + // + // Check if all GPUs received fabric probe and + // if the mode is supported on all GPUs. + // + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + if (!gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfoKernel) || + !gpuFabricProbeIsSuccess(pGpu->pGpuFabricProbeInfoKernel)) + { + return NV_ERR_NOT_READY; + } + + NvU64 fmCaps = pGpu->pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fmCaps; + switch(mode) + { + case GPU_NVLINK_BW_MODE_MIN: + GPU_FABRIC_CHECK_BW_MODE(fmCaps, MIN); + break; + case GPU_NVLINK_BW_MODE_HALF: + GPU_FABRIC_CHECK_BW_MODE(fmCaps, HALF); + break; + case GPU_NVLINK_BW_MODE_3QUARTER: + GPU_FABRIC_CHECK_BW_MODE(fmCaps, 3QUARTER); + break; + case GPU_NVLINK_BW_MODE_OFF: + return NV_OK; // Don't need to ask FM + default: + break; + } + } + + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, + FABRIC_VASPACE); + if (pFabricVAS == NULL) + { + continue; + } + + if (fabricvaspaceIsInUse(pFabricVAS)) + { + return NV_ERR_STATE_IN_USE; + } + } + + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + status = _gpuFabricProbeUpdateBwMode(pGpu, mode); + if (status != NV_OK) + { + return status; + } + } + + return NV_OK; +} + +NV_STATUS +gpuFabricProbeGetlinkMaskToBeReduced +( + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, + NvU32 *linkMaskToBeReduced +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *linkMaskToBeReduced = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.linkMaskToBeReduced; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/gpu_gspclient.c b/src/nvidia/src/kernel/gpu/gpu_gspclient.c index 75b8f7aedc..ce15bdeb4e 100644 --- a/src/nvidia/src/kernel/gpu/gpu_gspclient.c +++ b/src/nvidia/src/kernel/gpu/gpu_gspclient.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,9 @@ * @brief GSP Client (CPU RM) specific GPU routines reside in this file. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" #include "ctrl/ctrl2080.h" @@ -73,7 +76,7 @@ gpuInitSriov_FWCLIENT pGpu->sriovState.b64bitVFBar0 = pGSCI->sriovCaps.b64bitBar0; pGpu->sriovState.b64bitVFBar1 = pGSCI->sriovCaps.b64bitBar1; pGpu->sriovState.b64bitVFBar2 = pGSCI->sriovCaps.b64bitBar2; - + pGpu->sriovState.maxGfid = pGSCI->sriovMaxGfid; // note: pGpu->sriovState.virtualRegPhysOffset is initialized separately @@ -186,6 +189,14 @@ gpuGenGidData_FWCLIENT if (FLD_TEST_DRF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1, gidFlags)) { GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + NvU8 zeroGid[RM_SHA1_GID_SIZE] = { 0 }; + + if (portMemCmp(pGSCI->gidInfo.data, zeroGid, RM_SHA1_GID_SIZE) == 0) + { + NV_PRINTF(LEVEL_ERROR, "GSP Static Info has not been initialized yet for UUID\n"); + return NV_ERR_INVALID_STATE; + } + portMemCopy(pGidData, RM_SHA1_GID_SIZE, pGSCI->gidInfo.data, RM_SHA1_GID_SIZE); return NV_OK; } @@ -207,9 +218,12 @@ NvBool gpuIsGlobalPoisonFuseEnabled_FWCLIENT(OBJGPU *pGpu) void gpuInitProperties_FWCLIENT(OBJGPU *pGpu) { GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_MOBILE, pGSCI->bIsMobile); pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED, pGSCI->bIsGc6Rtd3Allowed); pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED, pGSCI->bIsGcOffRtd3Allowed); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_UEFI, pGSCI->bIsGpuUefi); + pGpu->setProperty(pGpu, PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED, pGSCI->bIsGcoffLegacyAllowed); } /*! @@ -308,7 +322,7 @@ gpuGetLitterValues_FWCLIENT pGrInfo = pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo; NV_ASSERT_OR_RETURN(pGrInfo != NULL, 0); - for (i = 0; i < NV_ARRAY_ELEMENTS32(pGrInfo->infoList); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pGrInfo->infoList); i++) { if (pGrInfo->infoList[i].index == index) return pGrInfo->infoList[i].data; diff --git a/src/nvidia/src/kernel/gpu/gpu_name_kernel.c b/src/nvidia/src/kernel/gpu/gpu_name_kernel.c index 55ed9f0d2c..7fb21052a0 100644 --- a/src/nvidia/src/kernel/gpu/gpu_name_kernel.c +++ b/src/nvidia/src/kernel/gpu/gpu_name_kernel.c @@ -39,7 +39,7 @@ gpuGetNameString_KERNEL NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_GPU_GET_NAME_STRING, ¶ms, sizeof(params))); - + if (type == NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII) { portMemCopy(nameStringBuffer, sizeof(params.gpuNameString.ascii), diff --git a/src/nvidia/src/kernel/gpu/gpu_registry.c b/src/nvidia/src/kernel/gpu/gpu_registry.c index ea1b6c389e..9578dfba70 100644 --- a/src/nvidia/src/kernel/gpu/gpu_registry.c +++ b/src/nvidia/src/kernel/gpu/gpu_registry.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -101,19 +101,6 @@ gpuInitRegistryOverrides_KERNEL } } - if (osReadRegistryDword(pGpu, - NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA, &data32) == NV_OK) - { - if (data32 == NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA_ENABLE) - { - pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, NV_TRUE); - } - else - { - pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, NV_FALSE); - } - } - if (pGpu->bSriovCapable) { if (osReadRegistryDword(pGpu, NV_REG_STR_RM_SET_SRIOV_MODE, &data32) == NV_OK) @@ -140,11 +127,14 @@ gpuInitRegistryOverrides_KERNEL } } } + } if (pGpu->bSriovEnabled && (IS_GSP_CLIENT(pGpu) || RMCFG_FEATURE_PLATFORM_GSP)) { - pGpu->bVgpuGspPluginOffloadEnabled = NV_TRUE; + { + pGpu->bVgpuGspPluginOffloadEnabled = NV_TRUE; + } } if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER, &data32) == NV_OK) @@ -181,12 +171,13 @@ gpuInitRegistryOverrides_KERNEL pGpu->bSplitVasManagementServerClientRm); } - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GPU_FABRIC_PROBE, &pGpu->fabricProbeRegKeyOverride) == NV_OK) + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GPU_FABRIC_PROBE, + &pGpu->fabricProbeRegKeyOverride) == NV_OK) { - pGpu->fabricProbeRegKeyOverride |= DRF_NUM(_REG_STR, _RM_GPU_FABRIC_PROBE, _OVERRIDE, 1); + pGpu->fabricProbeRegKeyOverride |= \ + DRF_NUM(_REG_STR, _RM_GPU_FABRIC_PROBE, _OVERRIDE, 1); } - return NV_OK; } @@ -199,6 +190,25 @@ gpuInitInstLocOverrides_IMPL OBJGPU *pGpu ) { + NvU32 data32 = 0; + // + // If Hopper CC mode is enabled, move all except few buffers to FB + // + if (((osReadRegistryDword(pGpu, NV_REG_STR_RM_CONFIDENTIAL_COMPUTE, &data32) == NV_OK) && + FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _ENABLED, _YES, data32) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE)) || gpuIsCCEnabledInHw_HAL(pGpu)) + { + + pGpu->instLocOverrides = NV_REG_STR_RM_INST_LOC_ALL_VID; + pGpu->instLocOverrides2 = NV_REG_STR_RM_INST_LOC_ALL_VID; + pGpu->instLocOverrides3 = NV_REG_STR_RM_INST_LOC_ALL_VID; + pGpu->instLocOverrides4 = NV_REG_STR_RM_INST_LOC_ALL_VID; + + // Only FW_SEC_LIC & FLCN UCODE buffers are required to be in NCOH now. These will be moved to VIDMEM eventually. + pGpu->instLocOverrides4 = FLD_SET_DRF(_REG_STR, _RM_INST_LOC_4, _FW_SEC_LIC_COMMAND, _NCOH, pGpu->instLocOverrides4); + pGpu->instLocOverrides4 = FLD_SET_DRF(_REG_STR, _RM_INST_LOC_4, _FLCN_UCODE_BUFFERS, _NCOH, pGpu->instLocOverrides4); + } + else { // // The pGpu fields are initialized to zero. Try to fill them from the @@ -235,25 +245,6 @@ gpuInitInstLocOverrides_IMPL pGpu->instLocOverrides2 = NV_REG_STR_RM_INST_LOC_ALL_COH; pGpu->instLocOverrides3 = NV_REG_STR_RM_INST_LOC_ALL_COH; // Leave instLocOverrides4 as _DEFAULT until all flavors are tested. - - if (gpuIsCacheOnlyModeEnabled(pGpu)) - { - // - // If cache only mode is enabled then we will override - // userD and bar page tables to vidmem(l2 cache). - // This is to avoid deadlocks on platforms - // that don't support reflected accesses. - // Such platforms will need to enable cache only mode to - // run test zeroFb - // NOTE: Since this puts USERD in vidmem, you probably also want to - // reduce the number of channels to allocate, or else - // fifoPreAllocUserD_GF100 will fail due to the limited amount of - // L2 available as "vidmem". (Use the RmNumFifos regkey.) - // - pGpu->instLocOverrides = FLD_SET_DRF(_REG, _STR_RM_INST_LOC, _BAR_PTE, _VID, pGpu->instLocOverrides); - pGpu->instLocOverrides = FLD_SET_DRF(_REG, _STR_RM_INST_LOC, _USERD, _VID, pGpu->instLocOverrides); - pGpu->instLocOverrides = FLD_SET_DRF(_REG, _STR_RM_INST_LOC, _BAR_PDE, _VID, pGpu->instLocOverrides); - } } // @@ -300,6 +291,7 @@ gpuInitInstLocOverrides_IMPL // SMs) are fine. // if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM) && + !gpuIsCacheOnlyModeEnabled(pGpu) && !(FLD_TEST_DRF(_REG_STR_RM, _INST_LOC, _BAR_PTE, _DEFAULT, pGpu->instLocOverrides) && FLD_TEST_DRF(_REG_STR_RM, _INST_LOC, _BAR_PDE, _DEFAULT, pGpu->instLocOverrides))) { diff --git a/src/nvidia/src/kernel/gpu/gpu_resource.c b/src/nvidia/src/kernel/gpu/gpu_resource.c index 2623be964d..dc0f358376 100644 --- a/src/nvidia/src/kernel/gpu/gpu_resource.c +++ b/src/nvidia/src/kernel/gpu/gpu_resource.c @@ -457,7 +457,7 @@ gpuresGetByDeviceOrSubdeviceHandle return status; // Must be device or subdevice - if (!dynamicCast(*ppGpuResource, Device) && + if (!dynamicCast(*ppGpuResource, Device) && !dynamicCast(*ppGpuResource, Subdevice)) { return NV_ERR_INVALID_OBJECT_HANDLE; diff --git a/src/nvidia/src/kernel/gpu/gpu_rmapi.c b/src/nvidia/src/kernel/gpu/gpu_rmapi.c index ee6a518530..cdafd2c6fa 100644 --- a/src/nvidia/src/kernel/gpu/gpu_rmapi.c +++ b/src/nvidia/src/kernel/gpu/gpu_rmapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,7 @@ #include "rmapi/client.h" #include "rmapi/resource_fwd_decls.h" #include "core/thread_state.h" +#include "virtualization/hypervisor/hypervisor.h" #include "virtualization/kernel_hostvgpudeviceapi.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_channel.h" @@ -502,9 +503,16 @@ gpuNotifySubDeviceEvent_IMPL for (i = 0; i < pGpu->numSubdeviceBackReferences; i++) { Subdevice *pSubdevice = pGpu->pSubdeviceBackReferences[i]; + + // + // We've seen cases where pSubdevice is NULL implying that the + // pSubdeviceBackReferences[] array is being modified during this loop. + // Adding a NULL pointer check here is only a stopgap. See bug 3892382. + // NV_ASSERT_OR_RETURN_VOID(pSubdevice != NULL); + INotifier *pNotifier = staticCast(pSubdevice, INotifier); - + if (inotifyGetNotificationShare(pNotifier) == NULL) continue; @@ -850,21 +858,43 @@ _gpuCollectMemInfo (bGlobalInfo || (pMemory->pHeap == pTargetedHeap)) && (RES_GET_HANDLE(pMemory->pDevice) == hDevice) && (pMemory->pMemDesc != NULL) && - ((!bIsGuestProcess && (!memdescGetFlag(pMemory->pMemDesc, MEMDESC_FLAGS_LIST_MEMORY))) || + ((!bIsGuestProcess && (!memdescGetFlag(pMemory->pMemDesc, MEMDESC_FLAGS_LIST_MEMORY)) + && !(hypervisorIsVgxHyper() && (pResourceRef->externalClassId == NV01_MEMORY_HW_RESOURCES))) || (bIsGuestProcess && (memdescGetFlag(pMemory->pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) && (pMemory->Type != NVOS32_TYPE_UNUSED)))) { + NvBool bIsMemProtected = NV_FALSE; + + bIsMemProtected = gpuIsCCorApmFeatureEnabled(pMemory->pMemDesc->pGpu) && + (pMemory->Flags & NVOS32_ALLOC_FLAGS_PROTECTED); + if (bIsMemProtected) + { + NV_ASSERT(!memdescGetFlag(pMemory->pMemDesc, + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)); + } if (pMemory->pMemDesc->DupCount == 1) { pData->memPrivate += pMemory->Length; + if (bIsMemProtected) + { + pData->protectedMemPrivate += pMemory->Length; + } } else if (pMemory->isMemDescOwner) { pData->memSharedOwned += pMemory->Length; + if (bIsMemProtected) + { + pData->protectedMemSharedOwned += pMemory->Length; + } } else { pData->memSharedDuped += pMemory->Length; + if (bIsMemProtected) + { + pData->protectedMemSharedDuped += pMemory->Length; + } } } } diff --git a/src/nvidia/src/kernel/gpu/gpu_suspend.c b/src/nvidia/src/kernel/gpu/gpu_suspend.c index 9ef134eb70..25bcb1080e 100644 --- a/src/nvidia/src/kernel/gpu/gpu_suspend.c +++ b/src/nvidia/src/kernel/gpu/gpu_suspend.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,6 +40,7 @@ #include "core/thread_state.h" #include "vgpu/rpc.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include // // Helper functions @@ -71,9 +72,13 @@ gpuPowerManagementEnter(OBJGPU *pGpu, NvU32 newLevel, NvU32 flags) if (IS_GSP_CLIENT(pGpu)) { - NV_ASSERT_OK_OR_GOTO(status, memmgrSavePowerMgmtState(pGpu, pMemoryManager), done); + // FB remains alive for GC6 cycle + if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) + { + NV_ASSERT_OK_OR_GOTO(status, memmgrSavePowerMgmtState(pGpu, pMemoryManager), done); + } - KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, NV_TRUE, IS_GPU_GC6_STATE_ENTERING(pGpu), newLevel); @@ -86,31 +91,38 @@ gpuPowerManagementEnter(OBJGPU *pGpu, NvU32 newLevel, NvU32 flags) // Dump GSP-RM logs before resetting and invoking FWSEC-SB kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE); - // Because of COT, RM cannot reset GSP-RISCV. - if (!(pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_COT_ENABLED))) + if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) { - kflcnReset_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + // Because of COT, RM cannot reset GSP-RISCV. + if (!(pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_COT_ENABLED))) + { + kflcnReset_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + } + + // Invoke FWSEC-SB to load back PreOsApps. + status = kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC-SB for PreOsApps\n"); + goto done; + } + + kpmuFreeLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp), done); + } } - - // Invoke FWSEC-SB to load back PreOsApps. - if (kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode) != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC-SB for PreOsApps\n"); - } - - kpmuFreeLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); - + else { - // Not called when kgspShouldBootWithBooter_HAL() is called and returns NV_FALSE NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp), done); - + kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, 0), done); } - } done: - if (status != NV_OK) + if ((status != NV_OK) && !IS_GPU_GC6_STATE_ENTERING(pGpu)) { memmgrFreeFbsrMemory(pGpu, pMemoryManager); } @@ -161,7 +173,7 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) // kmemsysProgramSysmemFlushBuffer_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); - KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); GSP_SR_INIT_ARGUMENTS gspSrInitArgs; @@ -178,17 +190,29 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) goto done; } - // Not called when kgspShouldBootWithBooter_HAL() is called and returns NV_FALSE + if (!IS_GPU_GC6_STATE_EXITING(pGpu)) { - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp), done); + // Not called when kgspShouldBootWithBooter_HAL() is called and returns NV_FALSE + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp), done); + } + + status = kpmuInitLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "cannot init libOS PMU logging structures: 0x%x\n", status); + goto done; + } } - - status = kpmuInitLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); - if (status != NV_OK) + else { - NV_PRINTF(LEVEL_ERROR, "cannot init libOS PMU logging structures: 0x%x\n", status); - goto done; + status = kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "cannot resume riscv/gsp from GC6: 0x%x\n", status); + goto done; + } } status = kgspWaitForRmInitDone(pGpu, pKernelGsp); @@ -198,6 +222,22 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) goto done; } } + else + { + // Boot GSP-FMC for monolithic RM + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + if ((pKernelFsp != NULL) && !IS_VIRTUAL(pGpu)) + { + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK, NV_FALSE); + + status = kfspSendBootCommands_HAL(pGpu, pKernelFsp); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "FSP boot command failed during resume.\n"); + goto done; + } + } + } // This is a no-op in CPU-RM NV_ASSERT_OK_OR_GOTO(status, gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags), done); @@ -215,7 +255,10 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) NV_PRINTF(LEVEL_NOTICE, "Adapter now in D0 state\n"); done: - memmgrFreeFbsrMemory(pGpu, pMemoryManager); + if (!IS_GPU_GC6_STATE_EXITING(pGpu)) + { + memmgrFreeFbsrMemory(pGpu, pMemoryManager); + } return status; } diff --git a/src/nvidia/src/kernel/gpu/gpu_timeout.c b/src/nvidia/src/kernel/gpu/gpu_timeout.c index 8fbb5e08b9..3fda17f28c 100644 --- a/src/nvidia/src/kernel/gpu/gpu_timeout.c +++ b/src/nvidia/src/kernel/gpu/gpu_timeout.c @@ -430,7 +430,7 @@ timeoutCheck if (!(pTimeout->flags & GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD)) { - threadStateYieldCpuIfNecessary(pGpu); + threadStateYieldCpuIfNecessary(pGpu, !!(pTimeout->flags & GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG)); } // diff --git a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c index e378ab2cf6..e478178698 100644 --- a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c +++ b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c @@ -28,6 +28,7 @@ #include "rmapi/client.h" #include "rmapi/rmapi.h" #include "class/cl00de.h" +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM NV_STATUS gpushareddataConstruct_IMPL @@ -38,187 +39,56 @@ gpushareddataConstruct_IMPL ) { NV_STATUS status = NV_OK; - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - MEMORY_DESCRIPTOR *pMemDesc = NULL; - NV00DE_SHARED_DATA *pSharedData; + Memory *pMemory = staticCast(pData, Memory); - if (pGpu->userSharedData.pMemDesc == NULL) - { - // Create a kernel-side mapping for writing the data if one is not already present - status = memdescCreate(&pMemDesc, pGpu, sizeof(NV00DE_SHARED_DATA), 0, NV_TRUE, ADDR_SYSMEM, - NV_MEMORY_WRITECOMBINED, MEMDESC_FLAGS_USER_READ_ONLY); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "memdescCreate failed - status=0x%08x\n", status); - return NV_ERR_INSUFFICIENT_RESOURCES; - } - - status = memdescAlloc(pMemDesc); - if (status != NV_OK) - { - memdescDestroy(pMemDesc); - NV_PRINTF(LEVEL_ERROR, "memdescAlloc failed - status=0x%08x\n", status); - return status; - } - - status = memdescMap(pMemDesc, 0, pMemDesc->Size, - NV_TRUE, NV_PROTECT_READ_WRITE, - &pGpu->userSharedData.pMapBuffer, - &pGpu->userSharedData.pMapBufferPriv); - if (status != NV_OK) - { - memdescFree(pMemDesc); - memdescDestroy(pMemDesc); - NV_PRINTF(LEVEL_ERROR, "memdescMap failed - status=0x%08x\n", status); - return status; - } - - pGpu->userSharedData.pMemDesc = pMemDesc; - - pSharedData = (NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer); - portMemSet(pSharedData, 0, sizeof(*pSharedData)); - - // Initial write from cached data - gpuUpdateUserSharedData_KERNEL(pGpu); - } - - memdescAddRef(pGpu->userSharedData.pMemDesc); - - return NV_OK; -} - -void -gpushareddataDestruct_IMPL -( - GpuUserSharedData *pData -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - MEMORY_DESCRIPTOR *pMemDesc = pGpu->userSharedData.pMemDesc; - - memdescRemoveRef(pMemDesc); + // pGpu is initialied in the Memory class constructor + OBJGPU *pGpu = pMemory->pGpu; + MEMORY_DESCRIPTOR **ppMemDesc = &(pGpu->userSharedData.pMemDesc); - if (pMemDesc->RefCount == 1) + if (RS_IS_COPY_CTOR(pParams)) { - // Clean up kernel-side mapping if this is the last mapping for this GPU - memdescUnmap(pMemDesc, - NV_TRUE, - pGpu->userSharedData.processId, - pGpu->userSharedData.pMapBuffer, - pGpu->userSharedData.pMapBufferPriv); - - memdescFree(pMemDesc); - memdescDestroy(pMemDesc); - pGpu->userSharedData.pMemDesc = NULL; - pGpu->userSharedData.pMapBuffer = NULL; - pGpu->userSharedData.pMapBufferPriv = NULL; + return NV_OK; } -} - -NV_STATUS -gpushareddataMap_IMPL -( - GpuUserSharedData *pData, - CALL_CONTEXT *pCallContext, - RS_CPU_MAP_PARAMS *pParams, - RsCpuMapping *pCpuMapping -) -{ - NV_STATUS status; - NvBool bKernel; - RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - - status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), - pCpuMapping->flags, - &bKernel); - if (status != NV_OK) - return status; - - // Only support read-only, fail early if flag is unset somehow - if (!(pGpu->userSharedData.pMemDesc->_flags & MEMDESC_FLAGS_USER_READ_ONLY)) - return NV_ERR_INVALID_STATE; - - pCpuMapping->processId = osGetCurrentProcess(); - - // Map entire buffer (no offsets supported) - status = memdescMap(pGpu->userSharedData.pMemDesc, - 0, - pGpu->userSharedData.pMemDesc->Size, - NV_FALSE, - NV_PROTECT_READABLE, - &pCpuMapping->pLinearAddress, - &pCpuMapping->pPrivate->pPriv); - return status; -} - -NV_STATUS -gpushareddataUnmap_IMPL -( - GpuUserSharedData *pData, - CALL_CONTEXT *pCallContext, - RsCpuMapping *pCpuMapping -) -{ - NV_STATUS status; - NvBool bKernel; - RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - - if (pGpu->userSharedData.pMemDesc == NULL) - return NV_ERR_INVALID_OBJECT; - - status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), - pCpuMapping->flags, - &bKernel); - if (status != NV_OK) - return status; - - memdescUnmap(pGpu->userSharedData.pMemDesc, - bKernel, - pCpuMapping->processId, - pCpuMapping->pLinearAddress, - pCpuMapping->pPrivate->pPriv); + if (*ppMemDesc == NULL) + { + // Create a kernel-side mapping for writing the data if one is not already present + NV_ASSERT_OK_OR_RETURN(memdescCreate(ppMemDesc, pGpu, sizeof(NV00DE_SHARED_DATA), 0, NV_TRUE, + ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_USER_READ_ONLY)); - return NV_OK; -} + NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemDesc), err); -NV_STATUS -gpushareddataGetMapAddrSpace_IMPL -( - GpuUserSharedData *pData, - CALL_CONTEXT *pCallContext, - NvU32 mapFlags, - NV_ADDRESS_SPACE *pAddrSpace -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - NV_ADDRESS_SPACE addrSpace; - if (pGpu->userSharedData.pMemDesc == NULL) - return NV_ERR_INVALID_OBJECT; + NV_ASSERT_OK_OR_GOTO(status, + memdescMap(*ppMemDesc, 0, (*ppMemDesc)->Size, + NV_TRUE, NV_PROTECT_READ_WRITE, + &pGpu->userSharedData.pMapBuffer, + &pGpu->userSharedData.pMapBufferPriv), + err); - NV_ASSERT_OK_OR_RETURN(rmapiGetEffectiveAddrSpace(pGpu, pGpu->userSharedData.pMemDesc, mapFlags, &addrSpace)); + portMemSet(pGpu->userSharedData.pMapBuffer, 0, sizeof(NV00DE_SHARED_DATA)); - if (pAddrSpace != NULL) - *pAddrSpace = addrSpace; + // Initial write from cached data + gpuUpdateUserSharedData_KERNEL(pGpu); + } + NV_ASSERT_OK_OR_RETURN(memConstructCommon(pMemory, + NV01_MEMORY_SYSTEM, 0, *ppMemDesc, 0, NULL, 0, 0, 0, 0, + NVOS32_MEM_TAG_NONE, NULL)); + memdescAddRef(pGpu->userSharedData.pMemDesc); return NV_OK; + +err: + memdescFree(*ppMemDesc); + memdescDestroy(*ppMemDesc); + *ppMemDesc = NULL; + return status; } -NV_STATUS -gpushareddataGetMemoryMappingDescriptor_IMPL -( - GpuUserSharedData *pData, - MEMORY_DESCRIPTOR **ppMemDesc -) +NvBool +gpushareddataCanCopy_IMPL(GpuUserSharedData *pData) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pData); - - *ppMemDesc = pGpu->userSharedData.pMemDesc; - - return NV_OK; + return NV_TRUE; } NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu) diff --git a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c index b27f644351..828d0180d9 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" diff --git a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c index 582bea80f9..b539b0f79c 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -65,6 +67,15 @@ kgraphicsInitFecsRegistryOverrides_GP100 kgraphicsSetCtxswLoggingSupported(pGpu, pKernelGraphics, bLog); } + // + // CTXSW logging is not supported when HCC prod settings are enabled. + // However, the same is supported when HCC is enabled in devtools mode + // + if (gpuIsCCFeatureEnabled(pGpu)) + { + kgraphicsSetCtxswLoggingSupported(pGpu, pKernelGraphics, NV_FALSE); + } + fecsSetRecordsPerIntr(pGpu, pKernelGraphics, NV_REG_STR_RM_CTXSW_LOG_RECORDS_PER_INTR_DEFAULT); if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CTXSW_LOG_RECORDS_PER_INTR, &data) == NV_OK) { @@ -91,7 +102,6 @@ kgraphicsAllocGrGlobalCtxBuffers_GP100 { extern NV_STATUS kgraphicsAllocGrGlobalCtxBuffers_GM200(OBJGPU *pGpu, KernelGraphics *pKernelGraphics, NvU32 gfid, KernelGraphicsContext *pKernelGraphicsContext); GR_GLOBALCTX_BUFFERS *pCtxBuffers; - NvU64 allocFlags = MEMDESC_FLAGS_NONE; NV_STATUS status; CTX_BUF_POOL_INFO *pCtxBufPool; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -114,13 +124,6 @@ kgraphicsAllocGrGlobalCtxBuffers_GP100 if (pCtxBuffers->bAllocated) return NV_OK; - // check for allocating local buffers in VPR memory (don't want for global memory) - if ( - pKernelGraphicsContextUnicast->bVprChannel) - allocFlags |= MEMDESC_ALLOC_FLAGS_PROTECTED; - - // If allocated per channel, ensure allocations goes into Suballocator if available - allocFlags |= MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE; } else { @@ -129,12 +132,6 @@ kgraphicsAllocGrGlobalCtxBuffers_GP100 RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &pCtxBufPool)); } - // Don't use context buffer pool for VF allocations managed by host RM. - if (ctxBufPoolIsSupported(pGpu) && (pCtxBufPool != NULL)) - { - allocFlags |= MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL; - } - pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pContextBuffersInfo != NULL, NV_ERR_INVALID_STATE); diff --git a/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c b/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c index b4b305963f..9e80be27ad 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" diff --git a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c index 49b6391a97..f4c09a8696 100644 --- a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c +++ b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c @@ -30,6 +30,9 @@ * * \***************************************************************************/ +// FIXME XXX +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/rmapi/event.h" #include "kernel/rmapi/event_buffer.h" @@ -880,7 +883,7 @@ NV_STATUS fecsAddBindpoint ( OBJGPU *pGpu, - RsClient *pClient, + RmClient *pClient, RsResourceRef *pEventBufferRef, NvHandle hNotifier, NvBool bAllUsers, @@ -891,8 +894,7 @@ fecsAddBindpoint ) { NV_STATUS status; - NvHandle hClient = pClient->hClient; - RmClient *pRmClient = dynamicCast(pClient, RmClient); + NvHandle hClient = staticCast(pClient, RsClient)->hClient; NvHandle hEventBuffer = pEventBufferRef->hResource; EventBuffer *pEventBuffer; NvBool bAdmin = osIsAdministrator(); @@ -977,7 +979,7 @@ fecsAddBindpoint } else { - targetUser = (NvU64)(NvUPtr)pRmClient->pUserInfo; + targetUser = (NvU64)(NvUPtr)pClient->pUserInfo; // Filtering UIDs is not yet implemented in legacy vGPU if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -1015,14 +1017,14 @@ fecsAddBindpoint pBind->hNotifier = hNotifier; pBind->hEventBuffer = hEventBuffer; pBind->pEventBuffer = pEventBuffer; - pBind->pUserInfo = (NvU64)(NvUPtr)pRmClient->pUserInfo; + pBind->pUserInfo = (NvU64)(NvUPtr)pClient->pUserInfo; pBind->bAdmin = bAdmin; pBind->eventMask = eventMask; pBind->bKernel = bKernel; pBind->version = version; status = registerEventNotification(&pEventBuffer->pListeners, - hClient, + staticCast(pClient, RsClient), hNotifier, hEventBuffer, (version == 2 ? @@ -1043,7 +1045,8 @@ fecsAddBindpoint else { GPUInstanceSubscription *pGPUInstanceSubscription; - status = gisubscriptionGetGPUInstanceSubscription(pClient, hNotifier, &pGPUInstanceSubscription); + status = gisubscriptionGetGPUInstanceSubscription( + staticCast(pClient, RsClient), hNotifier, &pGPUInstanceSubscription); if (status != NV_OK) goto done; diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c index 42b812ae0b..410024afcd 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics_manager.h" @@ -544,7 +546,7 @@ _kgraphicsInternalClientAlloc portMemSet(¶ms, 0, sizeof(params)); params.swizzId = swizzId; NV_ASSERT_OK( - pRmApi->AllocWithHandle(pRmApi, *phClient, *phSubdevice, hSubscription, AMPERE_SMC_PARTITION_REF, ¶ms)); + pRmApi->AllocWithHandle(pRmApi, *phClient, *phSubdevice, hSubscription, AMPERE_SMC_PARTITION_REF, ¶ms, sizeof(params))); } } @@ -645,12 +647,28 @@ kgraphicsInitializeDeferredStaticData_IMPL { MIG_INSTANCE_REF ref; RM_ENGINE_TYPE localRmEngineType; + Subdevice *pSubdevice; + RsClient *pClient; + + NV_CHECK_OK_OR_GOTO( + status, + LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), + cleanup); + + NV_CHECK_OK_OR_GOTO( + status, + LEVEL_ERROR, + subdeviceGetByHandle(pClient, hSubdevice, &pSubdevice), + cleanup); // Physical RM will fill with local indices, so localize the index NV_CHECK_OK_OR_GOTO( status, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pSubdevice), + &ref), cleanup); NV_CHECK_OK_OR_GOTO( status, @@ -785,12 +803,26 @@ kgraphicsLoadStaticInfo_KERNEL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE localRmEngineType; + RsClient *pClient; + Device *pDevice; + + NV_CHECK_OK_OR_GOTO( + status, + LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), + cleanup); + + NV_CHECK_OK_OR_GOTO( + status, + LEVEL_ERROR, + deviceGetByHandle(pClient, hDevice, &pDevice), + cleanup); // Physical RM will fill with local indices, so localize the index NV_CHECK_OK_OR_GOTO( status, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref), cleanup); NV_CHECK_OK_OR_GOTO( status, @@ -1346,7 +1378,6 @@ kgraphicsAllocKgraphicsBuffers_KERNEL } if (kgraphicsIsCtxswLoggingSupported(pGpu, pKernelGraphics) && - !pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsTraceUnsupportedInGuest && (kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL)) { if (!gvaspaceIsExternallyOwned(pGVAS) && !IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -1688,6 +1719,7 @@ kgraphicsCreateGoldenImageChannel_IMPL NvU64 gpFifoSize = NVA06F_GP_ENTRY__SIZE * gpFifoEntries; NvU64 chSize = gpFifoSize; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RsClient *pClientId; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bNeedMIGWar; NvBool bBcStatus; @@ -1713,6 +1745,8 @@ kgraphicsCreateGoldenImageChannel_IMPL NV_ASSERT_OK_OR_RETURN( rmapiutilAllocClientAndDeviceHandles(pRmApi, pGpu, &hClientId, &hDeviceId, &hSubdeviceId)); + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClientId, &pClientId)); + gpumgrSetBcEnabledStatus(pGpu, NV_TRUE); // As we have forced here SLI broadcast mode, temporarily reset the reentrancy count @@ -1728,7 +1762,7 @@ kgraphicsCreateGoldenImageChannel_IMPL // Allocate a subDevice NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - serverutilGenResourceHandle(hClientId, &hSecondary), + clientGenResourceHandle(pClientId, &hSecondary), cleanup); portMemSet(&nv2080AllocParams, 0, sizeof(nv2080AllocParams)); @@ -1740,7 +1774,8 @@ kgraphicsCreateGoldenImageChannel_IMPL hDeviceId, hSecondary, NV20_SUBDEVICE_0, - &nv2080AllocParams)); + &nv2080AllocParams, + sizeof(nv2080AllocParams))); } SLI_LOOP_END; @@ -1766,7 +1801,8 @@ kgraphicsCreateGoldenImageChannel_IMPL hSubdeviceId, hPartitionRef, AMPERE_SMC_PARTITION_REF, - &nvC637AllocParams), + &nvC637AllocParams, + sizeof(nvC637AllocParams)), cleanup); if (ref.pMIGComputeInstance != NULL) @@ -1779,7 +1815,8 @@ kgraphicsCreateGoldenImageChannel_IMPL hPartitionRef, hExecPartitionRef, AMPERE_SMC_EXEC_PARTITION_REF, - &nvC638AllocParams), + &nvC638AllocParams, + sizeof(nvC638AllocParams)), cleanup); } } @@ -1797,7 +1834,7 @@ kgraphicsCreateGoldenImageChannel_IMPL // Create a new VAspace for channel portMemSet(&vaParams, 0, sizeof(NV_VASPACE_ALLOCATION_PARAMETERS)); NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hVASpace, FERMI_VASPACE_A, &vaParams), + pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hVASpace, FERMI_VASPACE_A, &vaParams, sizeof(vaParams)), cleanup); // Allocate gpfifo entries @@ -1808,8 +1845,18 @@ kgraphicsCreateGoldenImageChannel_IMPL memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _PCI); memAllocParams.hVASpace = 0; // Physical allocations don't expect vaSpace handles + // + // When APM feature is enabled all RM internal sysmem allocations must + // be in unprotected memory + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // Other sysmem allocations that are not required to be accessed from GPU + // must be in protected memory + // + memAllocParams.attr2 |= DRF_DEF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED); + NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hPBPhysMemId, NV01_MEMORY_SYSTEM, &memAllocParams), + pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hPBPhysMemId, NV01_MEMORY_SYSTEM, &memAllocParams, sizeof(memAllocParams)), cleanup); portMemSet(&memAllocParams, 0, sizeof(NV_MEMORY_ALLOCATION_PARAMS)); @@ -1822,7 +1869,7 @@ kgraphicsCreateGoldenImageChannel_IMPL // 0 handle = allocations on gpu default vaSpace NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hPBVirtMemId, NV50_MEMORY_VIRTUAL, &memAllocParams), + pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hPBVirtMemId, NV50_MEMORY_VIRTUAL, &memAllocParams, sizeof(memAllocParams)), cleanup); // Allocate Userd @@ -1873,9 +1920,23 @@ kgraphicsCreateGoldenImageChannel_IMPL break; } + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // and all vidmem allocations must go to protected memory + // + if (gpuIsApmFeatureEnabled(pGpu) || + FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _PCI, memAllocParams.attr)) + { + memAllocParams.attr2 |= DRF_DEF(OS32, _ATTR2, _MEMORY_PROTECTION, + _UNPROTECTED); + } + NV_ASSERT_OK_OR_GOTO(status, pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hUserdId, - userdMemClass, &memAllocParams), + userdMemClass, &memAllocParams, sizeof(memAllocParams)), cleanup); } @@ -1902,9 +1963,14 @@ kgraphicsCreateGoldenImageChannel_IMPL if (bNeedMIGWar) { RM_ENGINE_TYPE localRmEngineType; + Device *pDevice; NV_ASSERT_OK_OR_GOTO(status, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClientId, &ref), + deviceGetByHandle(pClientId, hDeviceId, &pDevice), + cleanup); + + NV_ASSERT_OK_OR_GOTO(status, + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref), cleanup); NV_ASSERT_OK_OR_GOTO(status, @@ -1920,7 +1986,7 @@ kgraphicsCreateGoldenImageChannel_IMPL NV_ASSERT_OK_OR_GOTO(status, pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, hChannelId, - classNum, &channelGPFIFOAllocParams), + classNum, &channelGPFIFOAllocParams, sizeof(channelGPFIFOAllocParams)), cleanup); // @@ -1937,7 +2003,7 @@ kgraphicsCreateGoldenImageChannel_IMPL const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NvU32 i; - NV_ASSERT_OK(CliGetKernelChannel(hClientId, hChannelId, &pKernelChannel)); + NV_ASSERT_OK(CliGetKernelChannel(pClientId, hChannelId, &pKernelChannel)); NV_ASSERT_OR_ELSE(pKernelGraphicsStaticInfo != NULL, status = NV_ERR_INVALID_STATE; @@ -1984,7 +2050,7 @@ kgraphicsCreateGoldenImageChannel_IMPL // Allocate a GR object on the channel NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, hClientId, hChannelId, hObj3D, classNum, NULL), + pRmApi->AllocWithHandle(pRmApi, hClientId, hChannelId, hObj3D, classNum, NULL, 0), cleanup); cleanup: @@ -2171,7 +2237,7 @@ deviceCtrlCmdKGrGetCaps_IMPL portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); kgrmgrCtrlSetEngineID(0, &grRouteInfo); NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pDevice), &grRouteInfo, &pKernelGraphics), + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics), SLI_LOOP_RETURN(status);); if (!bCapsPopulated) @@ -2219,7 +2285,7 @@ deviceCtrlCmdKGrGetCapsV2_IMPL kgrmgrCtrlSetEngineID(0, &grRouteInfo); NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pDevice), &grRouteInfo, &pKernelGraphics), + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics), SLI_LOOP_RETURN(status);); if (!pParams->bCapsPopulated) @@ -2240,7 +2306,7 @@ static NV_STATUS _kgraphicsCtrlCmdGrGetInfoV2 ( OBJGPU *pGpu, - NvHandle hClient, + Device *pDevice, NV2080_CTRL_GR_GET_INFO_V2_PARAMS *pParams ) { @@ -2264,7 +2330,7 @@ _kgraphicsCtrlCmdGrGetInfoV2 return NV_ERR_INVALID_ARGUMENT; } - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, RES_GET_CLIENT_HANDLE(pDevice))) { NvU32 grIdx; for (grIdx = 0; grIdx < GPU_MAX_GRS; grIdx++) @@ -2279,7 +2345,7 @@ _kgraphicsCtrlCmdGrGetInfoV2 else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); } pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); @@ -2314,7 +2380,6 @@ deviceCtrlCmdKGrGetInfo_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); NV0080_CTRL_GR_GET_INFO_V2_PARAMS grInfoParamsV2; NV0080_CTRL_GR_INFO *pGrInfos = NvP64_VALUE(pParams->grInfoList); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pDevice); NvU32 grInfoListSize = NV_MIN(pParams->grInfoListSize, NV0080_CTRL_GR_INFO_MAX_SIZE); @@ -2328,7 +2393,7 @@ deviceCtrlCmdKGrGetInfo_IMPL grInfoParamsV2.grInfoListSize = grInfoListSize; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, &grInfoParamsV2)); + _kgraphicsCtrlCmdGrGetInfoV2(pGpu, pDevice, &grInfoParamsV2)); portMemCopy(pGrInfos, grInfoListSize * sizeof(*pGrInfos), grInfoParamsV2.grInfoList, grInfoListSize * sizeof(*pGrInfos)); @@ -2349,12 +2414,11 @@ deviceCtrlCmdKGrGetInfoV2_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pDevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, pParams)); + _kgraphicsCtrlCmdGrGetInfoV2(pGpu, pDevice, pParams)); return NV_OK; } @@ -2429,10 +2493,11 @@ subdeviceCtrlCmdKGrGetCapsV2_IMPL KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo = pParams->grRouteInfo; + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); kgrmgrCtrlSetEngineID(0, &grRouteInfo); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pSubdevice), &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -2472,7 +2537,7 @@ subdeviceCtrlCmdKGrGetInfo_IMPL NV2080_CTRL_GR_INFO *pGrInfos = NvP64_VALUE(pParams->grInfoList); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo = pParams->grRouteInfo; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvU32 grInfoListSize = NV_MIN(pParams->grInfoListSize, NV2080_CTRL_GR_INFO_MAX_SIZE); @@ -2493,7 +2558,7 @@ subdeviceCtrlCmdKGrGetInfo_IMPL grInfoParamsV2.grRouteInfo = grRouteInfo; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, &grInfoParamsV2)); + _kgraphicsCtrlCmdGrGetInfoV2(pGpu, pDevice, &grInfoParamsV2)); portMemCopy(pGrInfos, grInfoListSize * sizeof(*pGrInfos), grInfoParamsV2.grInfoList, grInfoListSize * sizeof(*pGrInfos)); @@ -2514,12 +2579,12 @@ subdeviceCtrlCmdKGrGetInfoV2_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, pParams)); + _kgraphicsCtrlCmdGrGetInfoV2(pGpu, pDevice, pParams)); return NV_OK; } @@ -2540,6 +2605,7 @@ subdeviceCtrlCmdKGrGetSmToGpcTpcMappings_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; @@ -2554,7 +2620,7 @@ subdeviceCtrlCmdKGrGetSmToGpcTpcMappings_IMPL else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); } // Verify static info is available @@ -2587,6 +2653,7 @@ subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; @@ -2601,7 +2668,7 @@ subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); } // Verify static info is available @@ -2644,6 +2711,7 @@ subdeviceCtrlCmdKGrGetSmIssueRateModifier_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); @@ -2665,7 +2733,7 @@ subdeviceCtrlCmdKGrGetSmIssueRateModifier_IMPL else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); } // Verify static info is available @@ -2702,6 +2770,7 @@ subdeviceCtrlCmdKGrGetGpcMask_IMPL NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -2717,7 +2786,7 @@ subdeviceCtrlCmdKGrGetGpcMask_IMPL else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2748,6 +2817,7 @@ subdeviceCtrlCmdKGrGetTpcMask_IMPL NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -2764,7 +2834,7 @@ subdeviceCtrlCmdKGrGetTpcMask_IMPL else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2790,7 +2860,7 @@ subdeviceCtrlCmdKGrGetNumTpcsForGpc_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -2799,7 +2869,7 @@ subdeviceCtrlCmdKGrGetNumTpcsForGpc_IMPL portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2831,6 +2901,7 @@ subdeviceCtrlCmdKGrGetPpcMask_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -2845,7 +2916,7 @@ subdeviceCtrlCmdKGrGetPpcMask_IMPL else { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2891,13 +2962,14 @@ subdeviceCtrlCmdKGrFecsBindEvtbufForUid_IMPL NV_ASSERT_OK_OR_RETURN( serverutilGetResourceRefWithType(hClient, pParams->hEventBuffer, classId(EventBuffer), &pEventBufferRef)); - NV_ASSERT_OK_OR_RETURN(serverutilGetClientUnderLock(hClient, &pClient)); + pClient = serverutilGetClientUnderLock(hClient); + NV_ASSERT_OR_RETURN(pClient != NULL, NV_ERR_INVALID_CLIENT); if (bMIGInUse) return NV_ERR_NOT_SUPPORTED; status = fecsAddBindpoint(pGpu, - staticCast(pClient, RsClient), + pClient, pEventBufferRef, hNotifier, pParams->bAllUsers, @@ -2935,10 +3007,11 @@ subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2_IMPL NV_ASSERT_OK_OR_RETURN( serverutilGetResourceRefWithType(hClient, pParams->hEventBuffer, classId(EventBuffer), &pEventBufferRef)); - NV_ASSERT_OK_OR_RETURN(serverutilGetClientUnderLock(hClient, &pClient)); + pClient = serverutilGetClientUnderLock(hClient); + NV_ASSERT_OR_RETURN(pClient != NULL, NV_ERR_INVALID_CLIENT); status = fecsAddBindpoint(pGpu, - staticCast(pClient, RsClient), + pClient, pEventBufferRef, hNotifier, pParams->bAllUsers, @@ -2966,6 +3039,7 @@ subdeviceCtrlCmdKGrGetPhysGpcMask_IMPL KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvU32 grIdx = 0; @@ -2997,9 +3071,8 @@ subdeviceCtrlCmdKGrGetPhysGpcMask_IMPL // valid in defined GPU instance // NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, @@ -3034,6 +3107,7 @@ subdeviceCtrlCmdKGrGetZcullMask_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; @@ -3050,7 +3124,7 @@ subdeviceCtrlCmdKGrGetZcullMask_IMPL { portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -3090,7 +3164,7 @@ subdeviceCtrlCmdKGrGetZcullInfo_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -3104,7 +3178,7 @@ subdeviceCtrlCmdKGrGetZcullInfo_IMPL portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -3143,14 +3217,15 @@ subdeviceCtrlCmdKGrCtxswPmMode_IMPL { kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, - RES_GET_CLIENT_HANDLE(pSubdevice), - &grRouteInfo, - &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, + GPU_RES_GET_DEVICE(pSubdevice), + &grRouteInfo, + &pKernelGraphics)); // Retrieve channel from either bare channel or TSG handle NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kchannelGetFromDualHandleRestricted(RES_GET_CLIENT_HANDLE(pSubdevice), pParams->hChannel, &pKernelChannel)); + kchannelGetFromDualHandleRestricted(RES_GET_CLIENT(pSubdevice), + pParams->hChannel, &pKernelChannel)); NV_ASSERT_OK_OR_RETURN( kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext)); @@ -3188,7 +3263,7 @@ subdeviceCtrlCmdKGrGetROPInfo_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; @@ -3197,7 +3272,7 @@ subdeviceCtrlCmdKGrGetROPInfo_IMPL portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -3231,14 +3306,14 @@ subdeviceCtrlCmdKGrGetAttributeBufferSize_IMPL NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvU32 engineId; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); // Verify static info is available pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); @@ -3275,7 +3350,7 @@ subdeviceCtrlCmdKGrGetEngineContextProperties_IMPL KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvU32 size = 0; NvU32 alignment = RM_PAGE_SIZE; NvU32 engineId; @@ -3290,7 +3365,8 @@ subdeviceCtrlCmdKGrGetEngineContextProperties_IMPL } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, + &pParams->grRouteInfo, &pKernelGraphics)); // Verify static info is available pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); @@ -3341,7 +3417,8 @@ subdeviceCtrlCmdKGrGetCtxBufferSize_IMPL NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + RsClient *pClient = RES_GET_CLIENT(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_CTX_BUFFER_INFO *pCtxBufferInfo; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; @@ -3380,11 +3457,12 @@ subdeviceCtrlCmdKGrGetCtxBufferSize_IMPL portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, + &grRouteInfo, &pKernelGraphics)); // Get channel from provided handle and owner client NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(hClient, pParams->hChannel, &pKernelChannel)); + CliGetKernelChannel(pClient, pParams->hChannel, &pKernelChannel)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext)); @@ -3453,6 +3531,7 @@ subdeviceCtrlCmdKGrGetCtxBufferInfo_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; + RsClient *pUserClient; KernelGraphics *pKernelGraphics; KernelChannel *pKernelChannel; KernelGraphicsContext *pKernelGraphicsContext; @@ -3482,14 +3561,19 @@ subdeviceCtrlCmdKGrGetCtxBufferInfo_IMPL return status; } - portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); - kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, pParams->hUserClient, &grRouteInfo, &pKernelGraphics)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + serverGetClientUnderLock(&g_resServ, pParams->hUserClient, &pUserClient)); // Get channel from provided handle and owner client NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(pParams->hUserClient, pParams->hChannel, &pKernelChannel)); + CliGetKernelChannel(pUserClient, pParams->hChannel, &pKernelChannel)); + + portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); + kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, + GPU_RES_GET_DEVICE(pKernelChannel), + &grRouteInfo, &pKernelGraphics)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext)); @@ -3523,6 +3607,7 @@ subdeviceCtrlCmdKGrGetCtxBufferPtes_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; + RsClient *pUserClient; KernelGraphics *pKernelGraphics; KernelChannel *pKernelChannel; KernelGraphicsContext *pKernelGraphicsContext; @@ -3558,15 +3643,19 @@ subdeviceCtrlCmdKGrGetCtxBufferPtes_IMPL return status; } - portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); - - kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, pParams->hUserClient, &grRouteInfo, &pKernelGraphics)); + serverGetClientUnderLock(&g_resServ, pParams->hUserClient, &pUserClient)); // Get channel from provided handle and owner client NV_CHECK_OK_OR_RETURN(LEVEL_INFO, - CliGetKernelChannel(pParams->hUserClient, pParams->hChannel, &pKernelChannel)); + CliGetKernelChannel(pUserClient, pParams->hChannel, &pKernelChannel)); + + portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); + kgrmgrCtrlSetChannelHandle(pParams->hChannel, &grRouteInfo); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, + GPU_RES_GET_DEVICE(pKernelChannel), + &grRouteInfo, &pKernelGraphics)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext)); @@ -3603,12 +3692,13 @@ subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_IMPL KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, + &pParams->grRouteInfo, &pKernelGraphics)); // Verify static info is available pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c index dedbc45ca1..f860020085 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED + +#define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics_context.h" #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" @@ -385,7 +390,7 @@ kgrctxFillCtxBufferInfo_IMPL NV2080_CTRL_GR_CTX_BUFFER_INFO *pCtxBufferInfo ) { - NvU32 pageSize; + NvU64 pageSize; NV_STATUS status; MEMORY_DESCRIPTOR *pRootMemDesc = memdescGetRootMemDesc(pMemDesc, NULL); @@ -1364,7 +1369,7 @@ kgrctxAllocCtxBuffers_IMPL // Allocate Ctx Buffers that are local to this channel if required // and they have yet to be allocated. // - if ((pKernelGraphicsContextUnicast->bVprChannel + if ((pKernelGraphicsContextUnicast->bVprChannel ) && !pKernelGraphicsContextUnicast->localCtxBuffer.bAllocated) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, @@ -1997,8 +2002,10 @@ kgrctxSetupDeferredPmBuffer_IMPL NV_STATUS status = NV_OK; Subdevice *pSubdevice; - pSubdevice = CliGetSubDeviceInfoFromGpu(RES_GET_CLIENT_HANDLE(pKernelChannel), pGpu); - NV_ASSERT_OR_RETURN(pSubdevice != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN( + subdeviceGetByGpu(RES_GET_CLIENT(pKernelChannel), pGpu, &pSubdevice)); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); NV_ASSERT_OK_OR_RETURN( kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast)); diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c index 08258b8a83..756d8af5ce 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,9 +21,12 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/device/device.h" #include "kernel/gpu/fifo/kernel_channel_group_api.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -379,6 +382,50 @@ kgrmgrCtrlRouteKGR_IMPL const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, KernelGraphics **ppKernelGraphics ) +{ + RsClient *pClient; + Device *pDevice; + + if (!IS_MIG_IN_USE(pGpu)) + { + KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, 0); + + NV_ASSERT_OR_RETURN(pKernelGraphics != NULL, NV_ERR_INVALID_STATE); + + if (ppKernelGraphics != NULL) + *ppKernelGraphics = pKernelGraphics; + + return NV_OK; + } + + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, hClient, &pClient)); + + NV_ASSERT_OK_OR_RETURN( + deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice)); + + return kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, + pGrRouteInfo, ppKernelGraphics); +} + +/*! + * @brief Retrieves associated KernelGraphics engine for given device / route info + * + * @param[in] pGpu + * @param[in] pKernelGraphicsManager + * @param[in] pDevice + * @param[in] grRouteInfo Client-provided info to direct GR accesses + * @param[out] ppKernelGraphics (Optional) Ptr to store appropriate KernelGraphics *, if desired. + */ +NV_STATUS +kgrmgrCtrlRouteKGRWithDevice_IMPL +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager, + Device *pDevice, + const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, + KernelGraphics **ppKernelGraphics +) { MIG_INSTANCE_REF ref; KernelGraphics *pKernelGraphics; @@ -387,6 +434,7 @@ kgrmgrCtrlRouteKGR_IMPL NvU32 grIdx; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo = *pGrRouteInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + RsClient *pClient; if (!IS_MIG_IN_USE(pGpu)) { @@ -394,8 +442,10 @@ kgrmgrCtrlRouteKGR_IMPL goto done; } + pClient = RES_GET_CLIENT(pDevice); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); // // Compute instances always have 1 GR engine, so automatically fill in @@ -408,8 +458,13 @@ kgrmgrCtrlRouteKGR_IMPL } else { - RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilegeByHandle(hClient); - if (!rmclientIsAdminByHandle(hClient, privLevel) && + RmClient *pRmClient = dynamicCast(pClient, RmClient); + + if (pRmClient == NULL) + return NV_ERR_INVALID_OBJECT_HANDLE; + + RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilege(pRmClient); + if (!rmclientIsAdmin(pRmClient, privLevel) && _kgrmgrGPUInstanceHasComputeInstances(pGpu, pKernelGraphicsManager, ref.pKernelMIGGpuInstance)) { return NV_ERR_INSUFFICIENT_PERMISSIONS; @@ -448,7 +503,7 @@ kgrmgrCtrlRouteKGR_IMPL NvHandle hChannel = DRF_VAL64(2080_CTRL_GR, _ROUTE_INFO_DATA, _CHANNEL_HANDLE, grRouteInfo.route); - status = CliGetKernelChannel(hClient, hChannel, &pKernelChannel); + status = CliGetKernelChannel(pClient, hChannel, &pKernelChannel); if (status != NV_OK) { RsResourceRef *pChanGrpRef; @@ -459,12 +514,13 @@ kgrmgrCtrlRouteKGR_IMPL // If retrieving a channel with the given hChannel doesn't work, // try interpreting it as a handle to a channel group instead. // - status = CliGetChannelGroup(hClient, hChannel, &pChanGrpRef, NULL); + status = CliGetChannelGroup(pClient->hClient, hChannel, + &pChanGrpRef, NULL); if (NV_OK != status) { NV_PRINTF(LEVEL_ERROR, "Failed to find a channel or TSG with given handle 0x%08x associated with hClient=0x%08x\n", - hChannel, hClient); + hChannel, pClient->hClient); return NV_ERR_INVALID_ARGUMENT; } @@ -532,6 +588,21 @@ kgrmgrGetLegacyGpcMask_IMPL return pKernelGraphicsManager->legacyKgraphicsStaticInfo.floorsweepingMasks.gpcMask; } +/*! + * @return legacy physical GFX GPC mask enumerated by this chip + */ +NvU32 +kgrmgrGetLegacyPhysGfxGpcMask_IMPL +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + NV_ASSERT_OR_RETURN(pKernelGraphicsManager->legacyKgraphicsStaticInfo.bInitialized, 0); + + return pKernelGraphicsManager->legacyKgraphicsStaticInfo.floorsweepingMasks.physGfxGpcMask; +} + /*! * @return legacy TPC mask for certain GPC * @@ -652,7 +723,7 @@ kgrmgrAllocVeidsForGrIdx_IMPL veidStart = (veidSpanOffset * maxVeidsPerGpc) + pKernelMIGGPUInstance->resourceAllocation.veidOffset; veidEnd = veidStart + veidCount - 1; - + NV_ASSERT_OR_RETURN(veidStart < veidEnd, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(veidStart < 64, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(veidEnd < 64, NV_ERR_INVALID_ARGUMENT); @@ -988,7 +1059,7 @@ kgrmgrCheckVeidsRequest_IMPL NV_PRINTF(LEVEL_ERROR, "veidCount %d is not aligned to maxVeidsPerGpc=%d\n", veidCount, maxVeidsPerGpc); return NV_ERR_INVALID_ARGUMENT; } - + // Create a mask for VEIDs associated with this GPU instance GPUInstanceVeidEnd = pKernelMIGGPUInstance->resourceAllocation.veidOffset + pKernelMIGGPUInstance->resourceAllocation.veidCount - 1; GPUInstanceVeidMask = DRF_SHIFTMASK64(GPUInstanceVeidEnd:pKernelMIGGPUInstance->resourceAllocation.veidOffset); @@ -1007,7 +1078,7 @@ kgrmgrCheckVeidsRequest_IMPL NV_ASSERT_OR_RETURN(veidEnd < 64, NV_ERR_INVALID_ARGUMENT); } else - { + { NvU64 reqVeidMask = DRF_SHIFTMASK64(veidCount - 1:0); NvU32 i; diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c index 80ce778c65..5ca02b98f1 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/core/locks.h" @@ -65,8 +67,10 @@ kgrobjPromoteContext_IMPL if (IS_MODS_AMODEL(pGpu)) return NV_OK; - pSubdevice = CliGetSubDeviceInfoFromGpu(RES_GET_CLIENT_HANDLE(pKernelGraphicsObject), pGpu); - NV_ASSERT_OR_RETURN(pSubdevice != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN( + subdeviceGetByGpu(RES_GET_CLIENT(pKernelGraphicsObject), pGpu, &pSubdevice)); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); kgrobjGetPromoteIds_HAL(pGpu, pKernelGraphicsObject, NV_ARRAY_ELEMENTS(promoteIds), @@ -194,8 +198,6 @@ _kgrAlloc kgraphicsInitializeDeferredStaticData(pGpu, pKernelGraphics, NV01_NULL_OBJECT, NV01_NULL_OBJECT)); } - pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsTraceUnsupportedInGuest = NV_FALSE; - // Allocate FECS buffer in Guest for SRIOV configs. if (kgrctxShouldManageCtxBuffers_HAL(pGpu, pKernelGraphicsObject->pKernelGraphicsContext, gfid) || IS_VIRTUAL_WITH_SRIOV(pGpu)) { @@ -245,7 +247,6 @@ static void _kgrobjDestruct NvHandle hClient = RES_GET_CLIENT_HANDLE(pChannelDescendant); NvHandle hParent = RES_GET_PARENT_HANDLE(pChannelDescendant); NvU32 classNum = pChannelDescendant->resourceDesc.externalClassId; - NvU32 gfid = kchannelGetGfid(pChannelDescendant->pKernelChannel); // If MIG is enabled, perform GR instance routing based upon parent channel handle kgrmgrCtrlSetChannelHandle(hParent, &grRouteInfo); @@ -255,8 +256,6 @@ static void _kgrobjDestruct if (status != NV_OK) SLI_LOOP_CONTINUE; - pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsTraceUnsupportedInGuest = NV_FALSE; - // Free Compute Mmio mapping kgrobjFreeComputeMmio_HAL(pGpu, pKernelGraphicsObject); diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c index 65ec7fc534..45a465ae73 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_SM_DEBUGGER_SESSION_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/os/os.h" #include "kernel/core/locks.h" #include "kernel/gpu/gr/kernel_sm_debugger_session.h" @@ -126,7 +131,8 @@ _ksmdbgssnInitClient NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &pKernelSMDebuggerSession->hInternalClient), + &pKernelSMDebuggerSession->hInternalClient, + sizeof(pKernelSMDebuggerSession->hInternalClient)), failed); // Allocate a device. @@ -143,7 +149,8 @@ _ksmdbgssnInitClient pKernelSMDebuggerSession->hInternalClient, pKernelSMDebuggerSession->hInternalDevice, NV01_DEVICE_0, - &nv0080AllocParams), + &nv0080AllocParams, + sizeof(nv0080AllocParams)), failed); // Allocate a subdevice. @@ -159,7 +166,8 @@ _ksmdbgssnInitClient pKernelSMDebuggerSession->hInternalDevice, pKernelSMDebuggerSession->hInternalSubdevice, NV20_SUBDEVICE_0, - &nv2080AllocParams), + &nv2080AllocParams, + sizeof(nv2080AllocParams)), failed); if (bMIGInUse) @@ -183,7 +191,8 @@ _ksmdbgssnInitClient pKernelSMDebuggerSession->hInternalSubdevice, pKernelSMDebuggerSession->hInternalSubscription, AMPERE_SMC_PARTITION_REF, - &nvC637AllocParams), + &nvC637AllocParams, + sizeof(nvC637AllocParams)), failed); } @@ -219,6 +228,7 @@ ksmdbgssnConstruct_IMPL NvHandle hSubdevice; NV_STATUS status = NV_OK; RsClient *pAppClient; + Subdevice *pSubdevice; RsResourceRef *pGrResourceRef; RsResourceRef *pParentRef; @@ -306,8 +316,11 @@ ksmdbgssnConstruct_IMPL NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu == GPU_RES_GET_GPU(pKernelSMDebuggerSession->pObject), NV_ERR_INVALID_ARGUMENT); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - CliGetSubDeviceHandleFromGpu(pAppClient->hClient, pGpu, &hSubdevice)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, subdeviceGetByGpu(pAppClient, pGpu, &pSubdevice)); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + + hSubdevice = RES_GET_HANDLE(pSubdevice); // Initialize the object info pKernelSMDebuggerSession->hChannelClient = pAppClient->hClient; diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c index 0e03a0a159..e4d42b759c 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,6 +30,11 @@ * * \***************************************************************************/ +#define NVOC_KERNEL_SM_DEBUGGER_SESSION_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/rmapi/control.h" #include "kernel/rmapi/rmapi.h" #include "kernel/os/os.h" @@ -58,14 +63,14 @@ // for the caller to explicitly pass in the handle corresponding to the VaSpaceApi: // static NV_STATUS -_nv83deCtrlCmdFetchVAS(NvU32 hClient, NvU32 hChannel, OBJVASPACE **ppVASpace) +_nv83deCtrlCmdFetchVAS(RsClient *pClient, NvU32 hChannel, OBJVASPACE **ppVASpace) { KernelChannel *pKernelChannel = NULL; NV_ASSERT_OR_RETURN(ppVASpace != NULL, NV_ERR_INVALID_ARGUMENT); // Fetch the corresponding Channel object from our handle - NV_ASSERT_OK_OR_RETURN(CliGetKernelChannel(hClient, hChannel, &pKernelChannel)); + NV_ASSERT_OK_OR_RETURN(CliGetKernelChannel(pClient, hChannel, &pKernelChannel)); NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_ARGUMENT); *ppVASpace = pKernelChannel->pVAS; @@ -148,7 +153,7 @@ _nv8deCtrlCmdReadWriteSurface ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelSMDebuggerSession); + RsClient *pClient = RES_GET_CLIENT(pKernelSMDebuggerSession); OBJVASPACE *pVASpace = NULL; NvU32 count = pParams->count; NvU32 i; @@ -161,7 +166,7 @@ _nv8deCtrlCmdReadWriteSurface // Attempt to retrieve the VAS pointer NV_ASSERT_OK_OR_RETURN( - _nv83deCtrlCmdFetchVAS(hClient, pKernelSMDebuggerSession->hChannel, &pVASpace)); + _nv83deCtrlCmdFetchVAS(pClient, pKernelSMDebuggerSession->hChannel, &pVASpace)); // Validate VA range and fail if invalid NV_ASSERT_OK_OR_RETURN( @@ -169,7 +174,6 @@ _nv8deCtrlCmdReadWriteSurface for (i = 0; i < count; i++) { - NvU8 *pBase; MEMORY_DESCRIPTOR *pMemDesc = NULL; NvU64 virtAddr = pParams->opsBuffer[i].gpuVA; NvP64 bufPtr = pParams->opsBuffer[i].pCpuVA; @@ -191,8 +195,11 @@ _nv8deCtrlCmdReadWriteSurface for (cur4kPage = start4kPage; cur4kPage <= end4kPage; ++cur4kPage) { - MMU_TRACE_PARAM mmuParams = {0}; - MMU_TRACE_ARG traceArg = {0}; + MMU_TRACE_PARAM mmuParams = {0}; + MMU_TRACE_ARG traceArg = {0}; + TRANSFER_SURFACE surf = {0}; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU8 *pKernBuffer = NULL; mmuParams.mode = MMU_TRACE_MODE_TRANSLATE; mmuParams.va = virtAddr; @@ -207,6 +214,12 @@ _nv8deCtrlCmdReadWriteSurface curSize = bufSize; } + pKernBuffer = portMemAllocNonPaged(curSize); + if (pKernBuffer == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + if (traceArg.aperture == ADDR_SYSMEM) { NvP64 physAddr = NV_PTR_TO_NvP64(traceArg.pa); @@ -217,7 +230,7 @@ _nv8deCtrlCmdReadWriteSurface DRF_DEF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS) | DRF_DEF(OS02, _FLAGS, _COHERENCY, _CACHED); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_ASSERT_OK_OR_ELSE(status, osCreateMemFromOsDescriptor(pGpu, physAddr, pKernelSMDebuggerSession->hInternalClient, @@ -225,39 +238,55 @@ _nv8deCtrlCmdReadWriteSurface &limit, &pMemDesc, NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR, - RS_PRIV_LEVEL_KERNEL)); + RS_PRIV_LEVEL_KERNEL), + portMemFree(pKernBuffer); return status; ); } else if (traceArg.aperture == ADDR_FBMEM) { - NV_ASSERT_OK_OR_RETURN(memdescCreate(&pMemDesc, pGpu, curSize, 0, NV_TRUE, - traceArg.aperture, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE)); + NV_ASSERT_OK_OR_ELSE(status, + memdescCreate(&pMemDesc, pGpu, curSize, 0, NV_TRUE, + traceArg.aperture, NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE), + portMemFree(pKernBuffer); return status; ); memdescDescribe(pMemDesc, traceArg.aperture, traceArg.pa, curSize); } - pBase = kbusMapRmAperture_HAL(pGpu, pMemDesc); - NV_ASSERT_OR_ELSE( - pBase != NULL, - memdescDestroy(pMemDesc); - return NV_ERR_INVALID_ARGUMENT; ); + surf.pMemDesc = pMemDesc; + surf.offset = pageStartOffset; if (bWrite) { NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, - portMemExCopyFromUser(bufPtr, pBase + pageStartOffset, curSize)); + portMemExCopyFromUser(bufPtr, pKernBuffer, curSize)); + + // Write out the buffer to memory + if (status == NV_OK) + { + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, + memmgrMemWrite(pMemoryManager, &surf, pKernBuffer, curSize, + TRANSFER_FLAGS_DEFER_FLUSH)); + } } else { + // Read from memory NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, - portMemExCopyToUser(pBase + pageStartOffset, bufPtr, curSize)); + memmgrMemRead(pMemoryManager, &surf, pKernBuffer, curSize, + TRANSFER_FLAGS_DEFER_FLUSH)); + + if (status == NV_OK) + { + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, + portMemExCopyToUser(pKernBuffer, bufPtr, curSize)); + } } - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pBase, NV_FALSE); + portMemFree(pKernBuffer); memdescDestroy(pMemDesc); if (status != NV_OK) return status; - pBase = NULL; pageStartOffset = 0; bufPtr = NvP64_PLUS_OFFSET(bufPtr,curSize); bufSize -= curSize; @@ -297,7 +326,7 @@ ksmdbgssnCtrlCmdGetMappings_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelSMDebuggerSession); + RsClient *pClient = RES_GET_CLIENT(pKernelSMDebuggerSession); OBJVASPACE *pVASpace = NULL; MMU_TRACE_ARG traceArg = {0}; MMU_TRACE_PARAM mmuParams = {0}; @@ -306,7 +335,7 @@ ksmdbgssnCtrlCmdGetMappings_IMPL // Attempt to retrieve the VAS pointer NV_ASSERT_OK_OR_RETURN( - _nv83deCtrlCmdFetchVAS(hClient, pKernelSMDebuggerSession->hChannel, &pVASpace)); + _nv83deCtrlCmdFetchVAS(pClient, pKernelSMDebuggerSession->hChannel, &pVASpace)); traceArg.pMapParams = pParams; diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c index 7a12e97e6a..3c564e37a2 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -78,10 +78,24 @@ _kgspResetIntoRiscv ) { KernelFalcon *pKernelFlcn = staticCast(pKernelGsp, KernelFalcon); - NV_ASSERT_OK_OR_RETURN(kflcnPreResetWait(pGpu, pKernelFlcn)); + NV_ASSERT_OK_OR_RETURN(kflcnPreResetWait_HAL(pGpu, pKernelFlcn)); + GPU_FLD_WR_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET, _TRUE); + + // Reg read cycles needed for signal propagation. + for (NvU32 i = 0; i < FLCN_RESET_PROPAGATION_DELAY_COUNT; i++) + { + GPU_REG_RD32(pGpu, NV_PGSP_FALCON_ENGINE); + } + GPU_FLD_WR_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET, _FALSE); + // Reg read cycles needed for signal propagation. + for (NvU32 i = 0; i < FLCN_RESET_PROPAGATION_DELAY_COUNT; i++) + { + GPU_REG_RD32(pGpu, NV_PGSP_FALCON_ENGINE); + } + NV_ASSERT_OK_OR_RETURN(kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn)); kflcnRiscvProgramBcr_HAL(pGpu, pKernelFlcn, NV_TRUE); @@ -343,7 +357,7 @@ kgspExecuteSequencerCommand_GA102 // Wait for reload to be completed. status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); - // Check SEC mailbox. + // Check SEC mailbox. secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); if ((status != NV_OK) || (secMailbox0 != NV_OK)) diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c index de207c4c3e..f052f33d5d 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,7 @@ */ #include "rmconfig.h" +#include "gpu/conf_compute/conf_compute.h" #include "gpu/fsp/kern_fsp.h" #include "gpu/gsp/kernel_gsp.h" #include "gsp/gspifpub.h" @@ -44,6 +45,9 @@ kgspGetSignatureSectionNamePrefix_GH100 KernelGsp *pKernelGsp ) { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + return GSP_CC_SIGNATURE_SECTION_NAME_PREFIX; return GSP_SIGNATURE_SECTION_NAME_PREFIX; } @@ -144,6 +148,8 @@ kgspAllocBootArgs_GH100 NV_STATUS nvStatus = NV_OK; NvU64 flags = MEMDESC_FLAGS_NONE; + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + // Allocate GSP-FMC arguments NV_ASSERT_OK_OR_GOTO(nvStatus, memdescCreate(&pKernelGsp->pGspFmcArgumentsDescriptor, @@ -200,6 +206,26 @@ kgspFreeBootArgs_GH100 } } +NvBool +kgspIsWpr2Up_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + // + // Due to BAR0 decoupler, we may not be able to read WPR2 MMU regs. + // Assume WPR2 is down. + // + return NV_FALSE; + } + + return kgspIsWpr2Up_TU102(pGpu, pKernelGsp); +} + NV_STATUS kgspWaitForGfwBootOk_GH100 ( @@ -208,7 +234,13 @@ kgspWaitForGfwBootOk_GH100 ) { KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); - return kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); + + if (pKernelFsp != NULL) + { + return kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); + } + + return NV_OK; } /*! @@ -226,7 +258,7 @@ kgspWaitForGfwBootOk_GH100 * ---------------------------- <- vbiosReservedOffset (64K? aligned) * | (potential align. gap) | * ---------------------------- <- gspFwWprEnd (128K aligned) - * | FRTS data | (frtsSize is 0 on GA100) + * | FRTS data | * | ------------------------ | <- frtsOffset * | BOOT BIN (e.g. GSP-FMC) | * ---------------------------- <- bootBinOffset @@ -239,7 +271,6 @@ kgspWaitForGfwBootOk_GH100 * ---------------------------- <- gspFwWprStart (128K aligned) * | GSP FW (non-WPR) HEAP | * ---------------------------- <- nonWprHeapOffset, gspFwRsvdStart - * (GSP_CARVEOUT_SIZE bytes from end of FB) * * @param pGpu GPU object pointer * @param pKernelGsp KernelGsp object pointer @@ -299,9 +330,16 @@ kgspCalculateFbLayout_GH100 // // The WPR heap size (gspFwHeapSize) is variable to also get any padding needed - // in the carveout to align the WPR start. We specify a minimum size here. + // in the carveout to align the WPR start. This is a minimum size request to + // the GSP-FMC. // - pWprMeta->gspFwHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); + // We won't know the exact size of everything that comes after the heap until + // after the GSP-FMC lays it all out during boot. At any rate, this value isn't + // needed on Hopper+, since the GSP-FMC can scrub/unlock anything we would need + // before GSP-RM boots, so we pass 0 to allow the heap to extend outside the + // pre-scrubbed area at the end of FB, if needed. + // + pWprMeta->gspFwHeapSize = kgspGetFwHeapSize(pGpu, pKernelGsp, 0); // Number of VF partitions allocating sub-heaps from the WPR heap pWprMeta->gspFwHeapVfPartitionCount = @@ -347,6 +385,12 @@ kgspSetupGspFmcArgs_GH100 GSP_FMC_BOOT_PARAMS *pGspFmcBootParams = pKernelGsp->pGspFmcArgumentsCached; + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL) + { + pGspFmcBootParams->initParams.regkeys = pCC->gspProxyRegkeys; + } + pGspFmcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0); pGspFmcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta); pGspFmcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor); @@ -398,6 +442,10 @@ _kgspBootstrapGspFmc_GH100 kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0, NvU64_LO32(physAddr)); kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1, NvU64_HI32(physAddr)); + // CC needs additional "regkeys" stuffed in a separate mailbox for the init partition + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + GPU_REG_WR32(pGpu, NV_PGSP_MAILBOX(0), pConfCompute->gspProxyRegkeys); + // Bootstrap the GSP-FMC by pointing the GSP's BootROM at it RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; RmPhysAddr fmcPhysAddr = memdescGetPhysAddr(pKernelGsp->pGspRmBootUcodeMemdesc, AT_GPU, 0); @@ -502,7 +550,7 @@ kgspBootstrapRiscvOSEarly_GH100 if (pKernelFsp != NULL && !pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) { - NV_PRINTF(LEVEL_ERROR, "Starting to boot GSP via FSP.\n"); + NV_PRINTF(LEVEL_NOTICE, "Starting to boot GSP via FSP.\n"); pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM, NV_TRUE); NV_ASSERT_OK_OR_RETURN(kfspSendBootCommands_HAL(pGpu, pKernelFsp)); } @@ -512,20 +560,23 @@ kgspBootstrapRiscvOSEarly_GH100 } // Wait for target mask to be released. - status = kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp); - if (status != NV_OK) + if (pKernelFsp != NULL) { - NV_PRINTF(LEVEL_ERROR, "Timeout waiting for GSP target mask release. " - "This error may be caused by several reasons: Bootrom may have failed, " - "GSP init code may have failed or ACR failed to release target mask. " - "RM does not have access to information on which of those conditions happened.\n"); - - if (pKernelFsp != NULL && pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + status = kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp); + if (status != NV_OK) { - kfspDumpDebugState_HAL(pGpu, pKernelFsp); - } + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for GSP target mask release. " + "This error may be caused by several reasons: Bootrom may have failed, " + "GSP init code may have failed or ACR failed to release target mask. " + "RM does not have access to information on which of those conditions happened.\n"); - return status; + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + kfspDumpDebugState_HAL(pGpu, pKernelFsp); + } + + return status; + } } // Wait for lockdown to be released. @@ -593,5 +644,24 @@ kgspGetGspRmBootUcodeStorage_GH100 BINDATA_STORAGE **ppBinStorageDesc ) { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + const BINDATA_ARCHIVE *pBinArchiveConcatenatedFMCDesc = kgspGetBinArchiveConcatenatedFMCDesc_HAL(pKernelGsp); + const BINDATA_ARCHIVE *pBinArchiveConcatenatedFMC = kgspGetBinArchiveConcatenatedFMC_HAL(pKernelGsp); + + if (kgspIsDebugModeEnabled(pGpu, pKernelGsp)) + { + *ppBinStorageImage = (BINDATA_STORAGE *)bindataArchiveGetStorage(pBinArchiveConcatenatedFMC, "ucode_image_dbg"); + *ppBinStorageDesc = (BINDATA_STORAGE *)bindataArchiveGetStorage(pBinArchiveConcatenatedFMCDesc, "ucode_desc_dbg"); + } + else + { + *ppBinStorageImage = (BINDATA_STORAGE *)bindataArchiveGetStorage(pBinArchiveConcatenatedFMC, "ucode_image_prod"); + *ppBinStorageDesc = (BINDATA_STORAGE *)bindataArchiveGetStorage(pBinArchiveConcatenatedFMCDesc, "ucode_desc_prod"); + } + + return; + } kgspGetGspRmBootUcodeStorage_GA102(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc); } diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c index 3fb9659299..d0aefe7856 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,6 @@ #include "gpu/falcon/kernel_falcon.h" #include "gpu/sec2/kernel_sec2.h" -#include "published/turing/tu102/dev_fb.h" // for NV_PFB_PRI_MMU_WPR2_ADDR_HI #include "published/turing/tu102/dev_falcon_v4.h" @@ -92,18 +91,21 @@ kgspExecuteBooterLoad_TU102 ) { NV_STATUS status; - NvU32 mailbox0, mailbox1; + NvU32 mailbox0 = 0, mailbox1 = 0; KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); NV_ASSERT_OR_RETURN(pKernelGsp->pBooterLoadUcode != NULL, NV_ERR_INVALID_STATE); - // - // sysmemAddrOfData either represents the FW WPR MetaData or the FW SR Data as a physical address in SYSTEM - // Provide that data in falcon SEC mailboxes 0 (low 32 bits) and 1 (high 32 bits) - // - mailbox0 = NvU64_LO32(sysmemAddrOfData); - mailbox1 = NvU64_HI32(sysmemAddrOfData); + if (sysmemAddrOfData != 0) + { + // + // sysmemAddrOfData either represents the FW WPR MetaData or the FW SR Data as a physical address in SYSTEM + // Provide that data in falcon SEC mailboxes 0 (low 32 bits) and 1 (high 32 bits) + // + mailbox0 = NvU64_LO32(sysmemAddrOfData); + mailbox1 = NvU64_HI32(sysmemAddrOfData); + } NV_PRINTF(LEVEL_INFO, "executing Booter Load, sysmemAddrOfData 0x%llx\n", sysmemAddrOfData); @@ -135,12 +137,15 @@ kgspExecuteBooterUnloadIfNeeded_TU102 KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); NvU32 mailbox0 = 0xFF, mailbox1 = 0xFF; + if (IS_GPU_GC6_STATE_ENTERING(pGpu)) + { + mailbox0 = mailbox1 = 0xdeaddead; + } + // skip actually executing Booter Unload if WPR2 is not up - NvU32 data = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_WPR2_ADDR_HI); - NvU32 wpr2HiVal = DRF_VAL(_PFB, _PRI_MMU_WPR2_ADDR_HI, _VAL, data); - if (wpr2HiVal == 0) + if (!kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) { - NV_PRINTF(LEVEL_INFO, "skipping executing Booter Unload as WPR is not up\n"); + NV_PRINTF(LEVEL_INFO, "skipping executing Booter Unload as WPR2 is not up\n"); return NV_OK; } @@ -149,7 +154,7 @@ kgspExecuteBooterUnloadIfNeeded_TU102 kflcnReset_HAL(pGpu, staticCast(pKernelSec2, KernelFalcon)); - // SR code + // SR code if (sysmemAddrOfSuspendResumeData != 0) { mailbox0 = NvU64_LO32(sysmemAddrOfSuspendResumeData); @@ -165,12 +170,23 @@ kgspExecuteBooterUnloadIfNeeded_TU102 return status; } - data = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_WPR2_ADDR_HI); - wpr2HiVal = DRF_VAL(_PFB, _PRI_MMU_WPR2_ADDR_HI, _VAL, data); - if (wpr2HiVal > 0) + if (IS_GPU_GC6_STATE_ENTERING(pGpu)) { - NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Unload: WPR2 is still up\n"); - return NV_ERR_GENERIC; + // For GC6 path, WPR2 should still be up (not torn down) + if (!kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Unload: WPR2 is cleared despite GC6\n"); + return NV_ERR_GENERIC; + } + } + else + { + // For all other unloads (non-GC6), WPR2 should be torn down + if (kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Unload: WPR2 is still up\n"); + return NV_ERR_GENERIC; + } } return status; diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c index 75f2cc7be7..e8e2bfeca9 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,6 +43,7 @@ #include "published/turing/tu102/dev_riscv_pri.h" #include "published/turing/tu102/dev_fbif_v4.h" #include "published/turing/tu102/dev_falcon_v4.h" +#include "published/turing/tu102/dev_fb.h" // for NV_PFB_PRI_MMU_WPR2_ADDR_HI #include "published/turing/tu102/dev_fuse.h" #include "published/turing/tu102/dev_ram.h" #include "published/turing/tu102/dev_gc6_island.h" @@ -109,6 +110,8 @@ kgspAllocBootArgs_TU102 NV_STATUS nvStatus = NV_OK; NvU64 flags = MEMDESC_FLAGS_NONE; + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + // Allocate WPR meta data NV_ASSERT_OK_OR_GOTO(nvStatus, memdescCreate(&pKernelGsp->pWprMetaDescriptor, @@ -568,7 +571,7 @@ kgspCalculateFbLayout_TU102 // pWprMeta->gspFwOffset = NV_ALIGN_DOWN64(pWprMeta->bootBinOffset - pWprMeta->sizeOfRadix3Elf, 0x10000); - const NvU64 wprHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); + const NvU64 wprHeapSize = kgspGetFwHeapSize(pGpu, pKernelGsp, pWprMeta->fbSize - pWprMeta->gspFwOffset); // GSP-RM heap in WPR, align to 1MB pWprMeta->gspFwHeapOffset = NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - wprHeapSize, 0x100000); @@ -731,8 +734,21 @@ kgspResetHw_TU102 ) { GPU_FLD_WR_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET, _TRUE); + + // Reg read cycles needed for signal propagation. + for (NvU32 i = 0; i < FLCN_RESET_PROPAGATION_DELAY_COUNT; i++) + { + GPU_REG_RD32(pGpu, NV_PGSP_FALCON_ENGINE); + } + GPU_FLD_WR_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET, _FALSE); + // Reg read cycles needed for signal propagation. + for (NvU32 i = 0; i < FLCN_RESET_PROPAGATION_DELAY_COUNT; i++) + { + GPU_REG_RD32(pGpu, NV_PGSP_FALCON_ENGINE); + } + return NV_OK; } @@ -797,6 +813,7 @@ kgspService_TU102 // Exit immediately if there is nothing to do if (intrStatus == 0) { + NV_ASSERT_FAILED("KGSP service called when no KGSP interrupt pending\n"); return 0; } @@ -860,7 +877,7 @@ _kgspIsProcessorSuspended // Check for LIBOS_INTERRUPT_PROCESSOR_SUSPENDED in mailbox mailbox = kflcnRegRead_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon), NV_PFALCON_FALCON_MAILBOX0); - return (mailbox & 0x80000000) == 0x80000000; + return (mailbox == 0x80000000); } NV_STATUS @@ -873,6 +890,18 @@ kgspWaitForProcessorSuspend_TU102 return gpuTimeoutCondWait(pGpu, _kgspIsProcessorSuspended, pKernelGsp, NULL); } +NvBool +kgspIsWpr2Up_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + NvU32 data = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_WPR2_ADDR_HI); + NvU32 wpr2HiVal = DRF_VAL(_PFB, _PRI_MMU_WPR2_ADDR_HI, _VAL, data); + return (wpr2HiVal != 0); +} + #define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms #define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s @@ -917,17 +946,20 @@ kgspWaitForGfwBootOk_TU102 } status = gpuCheckTimeout(pGpu, &timeout); - if (status == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, - "Timeout waiting for GFW_BOOT to complete\n"); - } } + // The wait failed if we reach here (as above loop returns upon success). + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: 0x%x (progress 0x%x)\n", + status, GPU_REG_RD_DRF(pGpu, + _PGC6, + _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, + _PROGRESS)); + NV_PRINTF(LEVEL_ERROR, "(the GPU may be in a bad state and may need to be reset)\n"); + return status; } -void +void kgspFreeSuspendResumeData_TU102 ( OBJGPU *pGpu, @@ -969,7 +1001,7 @@ kgspSavePowerMgmtState_TU102 gspfwSRMeta.revision = GSP_FW_SR_META_REVISION; gspfwSRMeta.sizeOfSuspendResumeData = pKernelGsp->pWprMeta->gspFwWprEnd - pKernelGsp->pWprMeta->gspFwWprStart; - + NV_ASSERT_OK_OR_GOTO(nvStatus, kgspCreateRadix3(pGpu, pKernelGsp, @@ -1016,7 +1048,7 @@ kgspSavePowerMgmtState_TU102 NV_ASSERT_OK_OR_GOTO(nvStatus, kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, - pKernelGsp, + pKernelGsp, memdescGetPhysAddr(pKernelGsp->pSRMetaDescriptor,AT_GPU, 0)), exit_fail_cleanup); @@ -1036,6 +1068,8 @@ kgspRestorePowerMgmtState_TU102 { NV_STATUS nvStatus = NV_OK; + NV_ASSERT_TRUE_OR_GOTO(nvStatus, pKernelGsp->pSRMetaDescriptor != NULL, NV_ERR_INVALID_STATE, exit_cleanup); + NV_ASSERT_OK_OR_GOTO(nvStatus, kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index a09729de09..879c253d64 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#include "resserv/rs_server.h" + #include "gpu/gsp/kernel_gsp.h" #include "kernel/core/thread_state.h" @@ -30,15 +32,20 @@ #include "kernel/gpu/intr/engine_idx.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" +#include "kernel/gpu/mem_sys/kern_mem_sys.h" #include "kernel/gpu/rc/kernel_rc.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "virtualization/hypervisor/hypervisor.h" #include "virtualization/vgpuconfigapi.h" #include "kernel/gpu/disp/kern_disp.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "gpu/external_device/external_device.h" +#include "kernel/platform/platform_request_handler.h" #include "class/cl2080.h" // NV20_SUBDEVICE_0 #include "liblogdecode.h" #include "libelf.h" #include "nverror.h" +#include "nvrm_registry.h" #include "nv-firmware.h" #include "nv-firmware-chip-family-select.h" #include "nvtypes.h" @@ -68,8 +75,18 @@ #include "gpu/gsp/message_queue_priv.h" +#include "gpu/conf_compute/conf_compute.h" + #define RPC_HDR ((rpc_message_header_v*)(pRpc->message_buffer)) +struct MIG_CI_UPDATE_CALLBACK_PARAMS +{ + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NvU32 gfid; + NvBool bDelete; +}; + // // RPC_PARAMS defines the rpc_params pointer and initializes it to the correct // sub-structure. @@ -93,6 +110,7 @@ static NV_STATUS _kgspConstructRpcObject(OBJGPU *, KernelGsp *, MESSAGE_QUEUE_IN static NV_STATUS _kgspRpcSendMessage(OBJGPU *, OBJRPC *); static NV_STATUS _kgspRpcRecvPoll(OBJGPU *, OBJRPC *, NvU32); static NV_STATUS _kgspRpcDrainEvents(OBJGPU *, KernelGsp *, NvU32); +static void _kgspRpcIncrementTimeoutCountAndRateLimitPrints(OBJGPU *, OBJRPC *); static NV_STATUS _kgspAllocSimAccessBuffer(OBJGPU *pGpu, KernelGsp *pKernelGsp); static void _kgspFreeSimAccessBuffer(OBJGPU *pGpu, KernelGsp *pKernelGsp); @@ -132,25 +150,32 @@ _kgspGetActiveRpcDebugData { case NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: { - rpc_gsp_rm_control_v03_00 *rpc_params = &rpc_message->gsp_rm_control_v03_00; + RPC_PARAMS(gsp_rm_control, _v03_00); *data0 = rpc_params->cmd; *data1 = rpc_params->paramsSize; break; } case NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC: { - rpc_gsp_rm_alloc_v03_00 *rpc_params = &rpc_message->gsp_rm_alloc_v03_00; + RPC_PARAMS(gsp_rm_alloc, _v03_00); *data0 = rpc_params->hClass; *data1 = rpc_params->paramsSize; break; } case NV_VGPU_MSG_FUNCTION_FREE: { - rpc_free_v03_00 *rpc_params = &rpc_message->free_v03_00; + RPC_PARAMS(free, _v03_00); *data0 = rpc_params->params.hObjectOld; *data1 = rpc_params->params.hObjectParent; break; } + case NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: + { + RPC_PARAMS(gsp_lockdown_notice, _v17_00); + *data0 = rpc_params->bLockdownEngaging; + *data1 = 0; + break; + } default: { *data0 = 0; @@ -177,11 +202,24 @@ _kgspRpcSendMessage NV_ASSERT_OR_RETURN(!osIsGpuShutdown(pGpu), NV_ERR_GPU_IS_LOST); + // Skip queuing RPC if we are in the GPU reset path. + if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Skip queuing RPC in the GPU reset path \n"); + return NV_ERR_GPU_IS_LOST; + } + nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu); if (nvStatus != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GspMsgQueueSendCommand failed on GPU%d: 0x%x\n", - gpuGetInstance(pGpu), nvStatus); + if (nvStatus == NV_ERR_TIMEOUT || + nvStatus == NV_ERR_BUSY_RETRY) + { + _kgspRpcIncrementTimeoutCountAndRateLimitPrints(pGpu, pRpc); + } + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "GspMsgQueueSendCommand failed on GPU%d: 0x%x\n", + gpuGetInstance(pGpu), nvStatus); return nvStatus; } @@ -189,7 +227,7 @@ _kgspRpcSendMessage // Add RPC history entry { - NvU32 func = vgpu_rpc_message_header_v->function; + NvU32 func = RPC_HDR->function; NvU32 entry; entry = pRpc->rpcHistoryCurrent = (pRpc->rpcHistoryCurrent + 1) % RPC_HISTORY_DEPTH; @@ -290,8 +328,8 @@ _kgspRpcPostEvent if (rpc_params->bNotifyList) { // Send notification to all matching events on the list. - nvStatus = osEventNotification(pGpu, pNotifyList, rpc_params->notifyIndex, - rpc_params->eventData, rpc_params->eventDataSize); + nvStatus = osEventNotificationWithInfo(pGpu, pNotifyList, rpc_params->notifyIndex, + rpc_params->data, rpc_params->info16, rpc_params->eventData, rpc_params->eventDataSize); } else { @@ -685,6 +723,12 @@ _kgspRpcSemaphoreScheduleCallback( ) { RPC_PARAMS(semaphore_schedule_callback, _v17_00); + NV_STATUS status; + RsClient *pClient; + + status = serverGetClientUnderLock(&g_resServ, rpc_params->hClient, &pClient); + if (status != NV_OK) + return status; return dispswReleaseSemaphoreAndNotifierFill(pGpu, rpc_params->GPUVA, @@ -692,8 +736,7 @@ _kgspRpcSemaphoreScheduleCallback( rpc_params->ReleaseValue, rpc_params->Flags, rpc_params->completionStatus, - rpc_params->hClient, - rpc_params->hEvent); + pClient, rpc_params->hEvent); } static NV_STATUS @@ -703,6 +746,12 @@ _kgspRpcTimedSemaphoreRelease( ) { RPC_PARAMS(timed_semaphore_release, _v01_00); + NV_STATUS status; + RsClient *pClient; + + status = serverGetClientUnderLock(&g_resServ, rpc_params->hClient, &pClient); + if (status != NV_OK) + return status; return tsemaRelease_HAL(pGpu, rpc_params->semaphoreVA, @@ -710,7 +759,7 @@ _kgspRpcTimedSemaphoreRelease( rpc_params->hVASpace, rpc_params->releaseValue, rpc_params->completionStatus, - rpc_params->hClient); + pClient); } @@ -806,6 +855,62 @@ _kgspRpcGspSendUserSharedData gpushareddataWriteFinish(pGpu); } +static void _kgspRpcMigCiConfigUpdateCallback +( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + struct MIG_CI_UPDATE_CALLBACK_PARAMS * pParams = (struct MIG_CI_UPDATE_CALLBACK_PARAMS *)pArgs; + + kmigmgrUpdateCiConfigForVgpu(pGpu, pKernelMIGManager, + pParams->execPartCount, pParams->execPartId, + pParams->gfid, pParams->bDelete); + + return; +} + +static NV_STATUS +_kgspRpcMigCiConfigUpdate +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + NV_STATUS status; + OBJOS *pOS = GPU_GET_OS(pGpu); + struct MIG_CI_UPDATE_CALLBACK_PARAMS *pParams; + + RPC_PARAMS(vgpu_gsp_mig_ci_config, _v21_03); + + NV_ASSERT_OR_RETURN(rpc_params->execPartCount <= NVC637_CTRL_MAX_EXEC_PARTITIONS, + NV_ERR_INVALID_ARGUMENT); + + pParams = portMemAllocNonPaged(sizeof(struct MIG_CI_UPDATE_CALLBACK_PARAMS)); + if (pParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + + pParams->execPartCount = rpc_params->execPartCount; + portMemCopy(pParams->execPartId, (sizeof(NvU32) * rpc_params->execPartCount), + rpc_params->execPartId, (sizeof(NvU32) * rpc_params->execPartCount)); + pParams->gfid = rpc_params->gfid; + pParams->bDelete = rpc_params->bDelete; + status = pOS->osQueueWorkItemWithFlags(pGpu, + _kgspRpcMigCiConfigUpdateCallback, + (void *)pParams, + OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW | OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW); + if (status != NV_OK) + { + portMemFree(pParams); + } + + return status; +} + static NV_STATUS _kgspRpcRgLineIntr ( @@ -830,6 +935,37 @@ _kgspRpcEventPlatformRequestHandlerStateSyncCallback OBJRPC* pRpc ) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler* pPlatformRequestHandler + = SYS_GET_PFM_REQ_HNDLR(pSys); + + RPC_PARAMS(pfm_req_hndlr_state_sync_callback, _v21_04); + + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 *src = &rpc_params->params; + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS dst = { 0 }; + + dst.flags = src->flags; + dst.syncData.type = src->syncData.type; + + // Copy in the rpc data + switch (src->syncData.type) + { + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI: + { + dst.syncData.data.smbpbi.sensorId = + src->syncData.data.smbpbi.sensorId; + dst.syncData.data.smbpbi.limit = + src->syncData.data.smbpbi.limit; + break; + } + default: + { + // Nothing for now + break; + } + } + + pfmreqhndlrStateSync(pPlatformRequestHandler, pGpu, &dst); return NV_OK; } @@ -1001,6 +1137,10 @@ _kgspProcessRpcEvent nvStatus = _kgspRpcEventPlatformRequestHandlerStateSyncCallback(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE: + nvStatus = _kgspRpcMigCiConfigUpdate(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_GSP_SEND_USER_SHARED_DATA: _kgspRpcGspSendUserSharedData(pGpu, pRpc); break; @@ -1125,21 +1265,16 @@ _kgspLogXid119 NvU32 expectedFunc ) { - KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); NvU32 historyEntry = pRpc->rpcHistoryCurrent; - NvU32 activeData[2]; - if (!pKernelGsp->bXid119Printed) + if (pRpc->timeoutCount == 1) { - NV_PRINTF(LEVEL_NOTICE, + NV_PRINTF(LEVEL_ERROR, "********************************* GSP Failure **********************************\n"); } NV_ASSERT(expectedFunc == pRpc->rpcHistory[historyEntry].function); - _kgspGetActiveRpcDebugData(pRpc, expectedFunc, - &activeData[0], &activeData[1]); - nvErrorLog_va((void*)pGpu, GSP_RPC_TIMEOUT, "Timeout waiting for RPC from GSP%d! Expected function %d (%s) (0x%x 0x%x).", gpuGetInstance(pGpu), @@ -1148,17 +1283,22 @@ _kgspLogXid119 pRpc->rpcHistory[historyEntry].data[0], pRpc->rpcHistory[historyEntry].data[1]); - if (!pKernelGsp->bXid119Printed) + if (pRpc->timeoutCount == 1) { + NvU32 activeData[2]; NvU32 historyIndex; + rpc_message_header_v *pMsgHdr = RPC_HDR; + + _kgspGetActiveRpcDebugData(pRpc, pMsgHdr->function, + &activeData[0], &activeData[1]); - if ((expectedFunc != vgpu_rpc_message_header_v->function) || + if ((expectedFunc != pMsgHdr->function) || (pRpc->rpcHistory[historyEntry].data[0] != activeData[0]) || (pRpc->rpcHistory[historyEntry].data[1] != activeData[1])) { NV_PRINTF(LEVEL_ERROR, "Current RPC function %d (%s) or data (0x%x 0x%x) does not match expected function %d (%s) or data (0x%x 0x%x).\n", - vgpu_rpc_message_header_v->function, _getRpcName(vgpu_rpc_message_header_v->function), + pMsgHdr->function, _getRpcName(pMsgHdr->function), activeData[0], activeData[1], expectedFunc, _getRpcName(expectedFunc), pRpc->rpcHistory[historyEntry].data[0], @@ -1179,14 +1319,42 @@ _kgspLogXid119 pRpc->rpcHistory[historyEntry].data[1]); } - NV_PRINTF(LEVEL_ERROR, "Dumping stack:\n"); osAssertFailed(); - NV_PRINTF(LEVEL_NOTICE, + NV_PRINTF(LEVEL_ERROR, "********************************************************************************\n"); } +} - pKernelGsp->bXid119Printed = NV_TRUE; +static void +_kgspRpcIncrementTimeoutCountAndRateLimitPrints +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + pRpc->timeoutCount++; + + if ((pRpc->timeoutCount == (RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH + 1)) && + (RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP > 0)) + { + // make sure we warn Xid and NV_PRINTF/NVLOG consumers that we are rate limiting prints + if (GPU_GET_KERNEL_RC(pGpu)->bLogEvents) + { + portDbgPrintf( + "NVRM: Rate limiting GSP RPC error prints for GPU at PCI:%04x:%02x:%02x (printing 1 of every %d). The GPU likely needs to be reset.\n", + gpuGetDomain(pGpu), + gpuGetBus(pGpu), + gpuGetDevice(pGpu), + RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP + 1); + } + NV_PRINTF(LEVEL_WARNING, + "Rate limiting GSP RPC error prints (printing 1 of every %d)\n", + RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP + 1); + } + + pRpc->bQuietPrints = ((pRpc->timeoutCount > RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH) && + ((pRpc->timeoutCount % (RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP + 1)) != 0)); } /*! @@ -1203,7 +1371,8 @@ _kgspRpcRecvPoll KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); NV_STATUS nvStatus; RMTIMEOUT timeout; - NvU32 timeoutUs = GPU_TIMEOUT_DEFAULT; + NvU32 timeoutUs; + NvU32 timeoutFlags; NvBool bSlowGspRpc = IS_EMULATION(pGpu) || IS_SIMULATION(pGpu); // @@ -1236,16 +1405,29 @@ _kgspRpcRecvPoll } else { - // We should only ever timeout this when GSP is in really bad state, so if it just - // happens to timeout on default timeout it should be OK for us to give it a little - // more time - make this timeout 1.5 of the default to allow some leeway. NvU32 defaultus = pGpu->timeoutData.defaultus; - timeoutUs = defaultus + defaultus / 2; + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + // Ensure at least 3.1s for vGPU-GSP before adding leeway (Bug 3928607) + timeoutUs = NV_MAX(3100 * 1000, defaultus) + (defaultus / 2); + } + else + { + // We should only ever timeout this when GSP is in really bad state, so if it just + // happens to timeout on default timeout it should be OK for us to give it a little + // more time - make this timeout 1.5 of the default to allow some leeway. + timeoutUs = defaultus + defaultus / 2; + } } NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - gpuSetTimeout(pGpu, timeoutUs, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + + timeoutFlags = GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE; + if (pRpc->bQuietPrints) + timeoutFlags |= GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG; + + gpuSetTimeout(pGpu, timeoutUs, &timeout, timeoutFlags); for (;;) { @@ -1267,7 +1449,13 @@ _kgspRpcRecvPoll nvStatus = gpuCheckTimeout(pGpu, &timeout); if (nvStatus == NV_ERR_TIMEOUT) { - _kgspLogXid119(pGpu, pRpc, expectedFunc); + _kgspRpcIncrementTimeoutCountAndRateLimitPrints(pGpu, pRpc); + + if (!pRpc->bQuietPrints) + { + _kgspLogXid119(pGpu, pRpc, expectedFunc); + } + goto done; } @@ -1278,6 +1466,8 @@ _kgspRpcRecvPoll } } + pRpc->timeoutCount = 0; + done: pKernelGsp->bPollingForRpcResponse = NV_FALSE; @@ -1693,8 +1883,7 @@ static NV_STATUS _kgspInitLibosLoggingStructures ( OBJGPU *pGpu, - KernelGsp *pKernelGsp, - GSP_FIRMWARE *pGspFw + KernelGsp *pKernelGsp ) { static const struct @@ -1725,16 +1914,15 @@ _kgspInitLibosLoggingStructures libosLogCreate(&pKernelGsp->logDecode); + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + for (idx = 0; idx < LOGIDX_SIZE; idx++) { RM_LIBOS_LOG_MEM *pLog = &pKernelGsp->rmLibosLogMem[idx]; NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; - // // Setup logging memory for each task. - // Use MEMDESC_FLAGS_CPU_ONLY -- too early to call memdescMapIommu. - // NV_ASSERT_OK_OR_GOTO(nvStatus, memdescCreate(&pLog->pTaskLogDescriptor, pGpu, @@ -1779,52 +1967,52 @@ _kgspInitLibosLoggingStructures logInitValues[idx].elfSectionName); } - // Setup symbol decoder - if (pGspFw->pLogElf) - { - const void *pLogData = NULL; - NvU64 logSize = 0; +error_cleanup: + if (nvStatus != NV_OK) + _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); - NV_ASSERT_OK_OR_GOTO( - nvStatus, - _kgspFwContainerVerifyVersion(pGpu, pKernelGsp, - pGspFw->pLogElf, - pGspFw->logElfSize, - "GSP firmware log"), - error_cleanup); + return nvStatus; +} - NV_ASSERT_OK_OR_GOTO( - nvStatus, - _kgspFwContainerGetSection(pGpu, pKernelGsp, - pGspFw->pLogElf, - pGspFw->logElfSize, - GSP_LOGGING_SECTION_NAME, - &pLogData, - &logSize), - error_cleanup); +static NV_STATUS +_kgspInitLibosLogDecoder +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw +) +{ + // If there's no log ELF or it's already been wired, skip wiring it now + if ((pGspFw->pLogElf == NULL) || (pKernelGsp->pLogElf != NULL)) + return NV_OK; - pKernelGsp->pLogElf = portMemAllocNonPaged(logSize); - pKernelGsp->logElfDataSize = logSize; + // Setup symbol decoder + const void *pLogData = NULL; + NvU64 logSize = 0; - if (pKernelGsp->pLogElf == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory for log elf"); - nvStatus = NV_ERR_NO_MEMORY; - goto error_cleanup; - } - portMemCopy(pKernelGsp->pLogElf, logSize, pLogData, logSize); + NV_ASSERT_OK_OR_RETURN( + _kgspFwContainerVerifyVersion(pGpu, pKernelGsp, + pGspFw->pLogElf, + pGspFw->logElfSize, + "GSP firmware log")); - if (pKernelGsp->pLogElf) - { - libosLogInit(&pKernelGsp->logDecode, pKernelGsp->pLogElf, logSize); - } - } + NV_ASSERT_OK_OR_RETURN( + _kgspFwContainerGetSection(pGpu, pKernelGsp, + pGspFw->pLogElf, + pGspFw->logElfSize, + GSP_LOGGING_SECTION_NAME, + &pLogData, + &logSize)); -error_cleanup: - if (nvStatus != NV_OK) - _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); + pKernelGsp->pLogElf = portMemAllocNonPaged(logSize); + pKernelGsp->logElfDataSize = logSize; - return nvStatus; + NV_ASSERT_OR_RETURN(pKernelGsp->pLogElf != NULL, NV_ERR_NO_MEMORY); + + portMemCopy(pKernelGsp->pLogElf, logSize, pLogData, logSize); + libosLogInit(&pKernelGsp->logDecode, pKernelGsp->pLogElf, logSize); + + return NV_OK; } static NV_STATUS @@ -1919,6 +2107,14 @@ kgspConstructEngine_IMPL goto done; } + // Init logging memory used by GSP + nvStatus = _kgspInitLibosLoggingStructures(pGpu, pKernelGsp); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "init libos logging structures failed: 0x%x\n", nvStatus); + goto done; + } + // Clear out the gspStaticInfo. We will populate this once GSP-RM is up. portMemSet(&pKernelGsp->gspStaticInfo, 0, sizeof(pKernelGsp->gspStaticInfo)); @@ -1944,6 +2140,7 @@ kgspConstructEngine_IMPL if (nvStatus != NV_OK) { kgspFreeBootArgs_HAL(pGpu, pKernelGsp); + _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); } @@ -2076,9 +2273,6 @@ kgspInitRm_IMPL goto done; } } - - // execute Booter Unload if needed to reset from unclean shutdown - kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, 0); } // Prepare boot binary image. @@ -2132,10 +2326,19 @@ kgspInitRm_IMPL } } - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspInitLogging(pGpu, pKernelGsp, pGspFw), done); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, _kgspInitLibosLogDecoder(pGpu, pKernelGsp, pGspFw), done); // Wait for GFW_BOOT OK status - kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp), done); + + // Fail early if WPR2 is up + if (kgspIsWpr2Up_HAL(pGpu, pKernelGsp)) + { + NV_PRINTF(LEVEL_ERROR, "unexpected WPR2 already up, cannot proceed with booting gsp\n"); + NV_PRINTF(LEVEL_ERROR, "(the GPU is likely in a bad state and may need to be reset)\n"); + status = NV_ERR_INVALID_STATE; + goto done; + } // bring up ucode with RM offload task status = kgspBootstrapRiscvOSEarly_HAL(pGpu, pKernelGsp, pGspFw); @@ -2188,26 +2391,6 @@ kgspInitRm_IMPL return status; } -NV_STATUS -kgspInitLogging_IMPL -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp, - GSP_FIRMWARE *pGspFw -) -{ - NV_STATUS nvStatus; - - nvStatus = _kgspInitLibosLoggingStructures(pGpu, pKernelGsp, pGspFw); - if (nvStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "init LIBOS logging structures failed: 0x%x\n", nvStatus); - return nvStatus; - } - - return nvStatus; -} - /*! * Unload GSP-RM */ @@ -2295,12 +2478,16 @@ kgspDestruct_IMPL kgspFreeFlcnUcode(pKernelGsp->pBooterUnloadUcode); pKernelGsp->pBooterUnloadUcode = NULL; + kgspFreeFlcnUcode(pKernelGsp->pScrubberUcode); + pKernelGsp->pScrubberUcode = NULL; + kgspFreeBootArgs_HAL(pGpu, pKernelGsp); _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); _kgspFreeBootBinaryImage(pGpu, pKernelGsp); _kgspFreeSimAccessBuffer(pGpu, pKernelGsp); + kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); } @@ -2387,6 +2574,15 @@ kgspPopulateGspRmInitArgs_IMPL } pGspArgs->gpuInstance = pGpu->gpuInstance; + + portMemSet(&pGspArgs->profilerArgs, 0, sizeof(pGspArgs->profilerArgs)); + + if (pKernelGsp->pProfilerSamples != NULL && + pKernelGsp->pProfilerSamplesMD != NULL) + { + pGspArgs->profilerArgs.pa = memdescGetPhysAddr(pKernelGsp->pProfilerSamplesMD, AT_GPU, 0); + pGspArgs->profilerArgs.size = memdescGetSize(pKernelGsp->pProfilerSamplesMD); + } } /*! @@ -2422,6 +2618,8 @@ kgspPrepareBootBinaryImage_IMPL bufSize = bindataGetBufferSize(pBinStorageImage); bufSizeAligned = NV_ALIGN_UP(bufSize, 0x1000); + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + NV_ASSERT_OK_OR_GOTO(status, memdescCreate(&pKernelGsp->pGspRmBootUcodeMemdesc, pGpu, @@ -2516,6 +2714,8 @@ _kgspCreateSignatureMemdesc NvU8 *pSignatureVa = NULL; NvU64 flags = MEMDESC_FLAGS_NONE; + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + // NOTE: align to 256 because that's the alignment needed for Booter DMA NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescCreate(&pKernelGsp->pSignatureMemdesc, pGpu, @@ -2772,6 +2972,8 @@ kgspCreateRadix3_IMPL allocSize += radix3[3].nPages << LIBOS_MEMORY_REGION_RADIX_PAGE_LOG2; } + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + NV_ASSERT_OK_OR_GOTO(status, memdescCreate(ppMemdescRadix3, pGpu, allocSize, LIBOS_MEMORY_REGION_RADIX_PAGE_SIZE, @@ -3025,7 +3227,7 @@ kgspWaitForRmInitDone_IMPL KernelGsp *pKernelGsp ) { - NV_STATUS nvStatus = NV_OK; + OBJRPC *pRpc = pKernelGsp->pRpc; // // Kernel RM can timeout when GSP-RM has an error condition. Give GSP-RM @@ -3034,16 +3236,22 @@ kgspWaitForRmInitDone_IMPL threadStateResetTimeout(pGpu); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rpcRecvPoll(pGpu, pKernelGsp->pRpc, NV_VGPU_MSG_EVENT_GSP_INIT_DONE)); + rpcRecvPoll(pGpu, pRpc, NV_VGPU_MSG_EVENT_GSP_INIT_DONE)); + + // + // Now check if RPC really succeeded (NV_VGPU_MSG_RESULT_* are defined to + // equivalent NV_STATUS codes in RM). + // + NV_ASSERT_OK_OR_RETURN(RPC_HDR->rpc_result); - // Now check if RPC really succeeded - NV_ASSERT_OK_OR_RETURN(((rpc_message_header_v *)pKernelGsp->pRpc->message_buffer)->rpc_result); - if (nvStatus != NV_VGPU_MSG_RESULT_SUCCESS) + pGpu->gspRmInitialized = NV_TRUE; + if (hypervisorIsVgxHyper() && pGpu->getProperty(pGpu, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX)) { - NV_ASSERT_OK_FAILED("nvStatus", nvStatus); + // Decrease timeout values for VGX driver + timeoutInitializeGpuDefault(&pGpu->timeoutData, pGpu); } - return nvStatus; + return NV_OK; } /*! @@ -3273,3 +3481,122 @@ kgspServiceInterrupt_IMPL return kgspService_HAL(pGpu, pKernelGsp); } + +/*! + * Calculates the GSP FW heap size based on the GPU's resources. + */ +static NvU64 +_kgspCalculateFwHeapSize +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + NvU32 maxGspFwHeapSizeMB +) +{ + // For VGPU, use the static pre-calculated size + if (pGpu->bVgpuGspPluginOffloadEnabled) + return GSP_FW_HEAP_SIZE_VGPU_DEFAULT; + + // + // The baremetal heap calculation is a function of the architecture, FB + // size, and a chunk for backing client allocations (pre-calibrated for the + // architecture through rough profiling). + // + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvU64 fbSize = 0; + + NV_ASSERT_OK(kmemsysGetUsableFbSize_HAL(pGpu, pKernelMemorySystem, &fbSize)); + const NvU32 fbSizeGB = (NvU32)(NV_ALIGN_UP64(fbSize, 1 << 30) >> 30); + + // + // Reclaimable binary data will end up padding the heap (in some cases, + // significantly), but due to memory fragmentation we can't rely on it to + // linearly reduce the amount needed in the primary heap, so it is not a + // factor here. Instead, it's just extra margin to keep us from exhausting + // the heap at runtime. + // + NvU64 heapSize = pKernelGsp->fwHeapParamOsCarveoutSize + + pKernelGsp->fwHeapParamBaseSize + + NV_ALIGN_UP(GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB * fbSizeGB, 1 << 20) + + NV_ALIGN_UP(GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE, 1 << 20); + + // Clamp to the minimum, even if the calculations say we can do with less + const NvU32 minGspFwHeapSizeMB = kgspGetMinWprHeapSizeMB_HAL(pGpu, pKernelGsp); + heapSize = NV_MAX(heapSize, (NvU64)minGspFwHeapSizeMB << 20); + + // Clamp to the maximum heap size, if necessary + heapSize = NV_MIN(heapSize, (NvU64)maxGspFwHeapSizeMB << 20); + + NV_PRINTF(LEVEL_INFO, "GSP FW heap %lluMB of %uGB\n", + heapSize >> 20, fbSizeGB); + + return heapSize; +} + +/*! + * Returns the size in bytes of the GSP FW heap: + * - the registry override, if present + * - otherwise, calculate the FW heap size for this GPU, limiting it to stay + * within the pre-scrubbed area at the end of FB, if needed + * + * @param[in] posteriorFbSize - size in bytes of the memory reserved between the + * end of the GSP FW heap and the end of FB, or 0 + * to disable limiting of the heap range to within + * the pre-scrubbed area at the end of FB + */ +NvU64 +kgspGetFwHeapSize_IMPL +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + NvU64 posteriorFbSize +) +{ + NvU32 maxScrubbedHeapSizeMB = NV_U32_MAX; + NvU32 heapSizeMB = 0; + + // + // The pre-scrubbed region at the end of FB may limit the heap size, if no + // scrubber ucode is supported to unlock the rest of memory prior to booting + // GSP-RM. + // + if (!pKernelGsp->bScrubberUcodeSupported && (posteriorFbSize != 0)) + { + const NvU64 prescrubbedSize = kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp); + if (prescrubbedSize < NV_U64_MAX) + maxScrubbedHeapSizeMB = (NvU32)((prescrubbedSize - posteriorFbSize) >> 20); + } + + // Get the heap size override from the registry, if any + if ((osReadRegistryDword(pGpu, NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB, &heapSizeMB) == NV_OK) && + (heapSizeMB != NV_REG_STR_GSP_FIRMWARE_HEAP_SIZE_MB_DEFAULT)) + { + const NvU32 minGspFwHeapSizeMB = kgspGetMinWprHeapSizeMB_HAL(pGpu, pKernelGsp); + const NvU32 maxGspFwHeapSizeMB = NV_MIN(kgspGetMaxWprHeapSizeMB_HAL(pGpu, pKernelGsp), + maxScrubbedHeapSizeMB); + + NV_ASSERT(minGspFwHeapSizeMB < maxGspFwHeapSizeMB); + + if (heapSizeMB > maxGspFwHeapSizeMB) + { + NV_PRINTF(LEVEL_WARNING, "Firmware heap size clamped to maximum (%uMB)\n", + maxGspFwHeapSizeMB); + heapSizeMB = maxGspFwHeapSizeMB; + } + else if (heapSizeMB < minGspFwHeapSizeMB) + { + NV_PRINTF(LEVEL_WARNING, "Firmware heap size clamped to minimum (%uMB)\n", + minGspFwHeapSizeMB); + heapSizeMB = minGspFwHeapSizeMB; + } + else + { + NV_PRINTF(LEVEL_WARNING, "Firmware heap size overridden (%uMB)\n", + heapSizeMB); + } + + return ((NvU64)heapSizeMB) << 20; + } + + return _kgspCalculateFwHeapSize(pGpu, pKernelGsp, maxScrubbedHeapSizeMB); +} diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c index bcd357249d..0cd8842066 100644 --- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c +++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c @@ -241,6 +241,8 @@ GspMsgQueuesInit pTaskIsrQueueInfo->commandQueueSize + pTaskIsrQueueInfo->statusQueueSize; + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + // // For now, put all shared queue memory in one block. // @@ -531,8 +533,13 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) for (i = 0; i < nElements; i++) { + NvU32 timeoutFlags = 0; + + if (pMQI->txBufferFull) + timeoutFlags |= GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG; + // Set a timeout of 1 sec - gpuSetTimeout(pGpu, 1000000, &timeout, 0); + gpuSetTimeout(pGpu, 1000000, &timeout, timeoutFlags); // Wait for space to put the next element. Retry for up to 10 ms. for (nRetries = 0; ; nRetries++) @@ -553,10 +560,15 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) if (pNextElement == NULL) { - NV_PRINTF(LEVEL_ERROR, "buffer is full\n"); + pMQI->txBufferFull++; + NV_PRINTF_COND(pMQI->txBufferFull == 1, LEVEL_ERROR, LEVEL_INFO, "buffer is full\n"); nvStatus = NV_ERR_BUSY_RETRY; goto done; } + else + { + pMQI->txBufferFull = 0; + } portMemCopy(pNextElement, GSP_MSG_QUEUE_ELEMENT_SIZE_MIN, pSrc, GSP_MSG_QUEUE_ELEMENT_SIZE_MIN); diff --git a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c index 4fcbe775b1..2ecc213bd4 100644 --- a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c +++ b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c @@ -177,7 +177,7 @@ profilerDevConstructStatePrologue_FWCLIENT NV_STATUS status = NV_OK; NV_RM_RPC_ALLOC_OBJECT(pGpu, hClient, hParent, hObject, class, - pAllocParams->pAllocParams, status); + pAllocParams->pAllocParams, pAllocParams->paramsSize, status); return status; } diff --git a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c index 92ab46b49a..c63a51af6c 100644 --- a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c +++ b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c @@ -29,6 +29,24 @@ #include "ctrl/ctrlb0cc/ctrlb0ccinternal.h" #include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h" #include "mem_mgr/mem.h" +#include "vgpu/rpc.h" + +static NV_STATUS _issueRpcToHost(OBJGPU *pGpu) +{ + NV_STATUS status = NV_OK; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + + return status; +} NV_STATUS profilerBaseCtrlCmdFreePmaStream_IMPL @@ -42,6 +60,13 @@ profilerBaseCtrlCmdFreePmaStream_IMPL portMemSet(&internalParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS)); internalParams.pmaChannelIdx = pParams->pmaChannelIdx; + + // + // The following security checks are valid only if MemPmaBuffer and MemPmaBytesAvailable + // buffers are accessible and are set during PMA alloc + // Those buffers are not accessible on vGpu host (accessible on vGPU Guest and baremetal) + // + if (pProfiler->ppBytesAvailable != NULL && pProfiler->ppStreamBuffers != NULL) { RsResourceRef *pCountRef = NULL; RsResourceRef *pBufferRef = NULL; @@ -64,7 +89,7 @@ profilerBaseCtrlCmdFreePmaStream_IMPL pProfiler->pBoundPmaBuf = NULL; pCntMem->pMemDesc->bRmExclusiveUse = NV_FALSE; pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE; - + } if (pCountRef != NULL) { @@ -95,42 +120,57 @@ profilerBaseCtrlCmdBindPmResources_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler); NvHandle hObject = RES_GET_HANDLE(pProfiler); NV_STATUS status = NV_OK; - RsResourceRef *pCntRef = NULL; - RsResourceRef *pBufRef = NULL; Memory *pCntMem = NULL; Memory *pBufMem = NULL; - NV_CHECK_OR_GOTO(LEVEL_INFO, - !pProfiler->bLegacyHwpm && pProfiler->maxPmaChannels != 0, physical_control); - - if (pProfiler->maxPmaChannels <= pProfiler->pmaVchIdx) + // + // The following security checks are valid only if MemPmaBuffer and MemPmaBytesAvailable + // buffers are accessible and are set during PMA alloc + // Those buffers are not accessible on vGpu host (accessible on vGPU Guest and baremetal) + // + if (pProfiler->ppBytesAvailable != NULL && pProfiler->ppStreamBuffers != NULL) { - return NV_ERR_INVALID_ARGUMENT; - } + RsResourceRef *pCntRef = NULL; + RsResourceRef *pBufRef = NULL; - pCntRef = pProfiler->ppBytesAvailable[pProfiler->pmaVchIdx]; - pBufRef = pProfiler->ppStreamBuffers[pProfiler->pmaVchIdx]; + NV_CHECK_OR_GOTO(LEVEL_INFO, + !pProfiler->bLegacyHwpm && pProfiler->maxPmaChannels != 0, physical_control); - NV_CHECK_OR_GOTO(LEVEL_INFO, - pCntRef != NULL && pBufRef != NULL, physical_control); + if (pProfiler->maxPmaChannels <= pProfiler->pmaVchIdx) + { + return NV_ERR_INVALID_ARGUMENT; + } - pCntMem = dynamicCast(pCntRef->pResource, Memory); - pBufMem = dynamicCast(pBufRef->pResource, Memory); + pCntRef = pProfiler->ppBytesAvailable[pProfiler->pmaVchIdx]; + pBufRef = pProfiler->ppStreamBuffers[pProfiler->pmaVchIdx]; - NV_ASSERT_OR_RETURN(pCntMem != NULL && pBufMem != NULL, NV_ERR_INVALID_STATE); - - if (!memdescAcquireRmExclusiveUse(pCntMem->pMemDesc) || - !memdescAcquireRmExclusiveUse(pBufMem->pMemDesc)) - { - pCntMem->pMemDesc->bRmExclusiveUse = NV_FALSE; - pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE; - return NV_ERR_INVALID_ARGUMENT; + NV_CHECK_OR_GOTO(LEVEL_INFO, + pCntRef != NULL && pBufRef != NULL, physical_control); + + pCntMem = dynamicCast(pCntRef->pResource, Memory); + pBufMem = dynamicCast(pBufRef->pResource, Memory); + + NV_ASSERT_OR_RETURN(pCntMem != NULL && pBufMem != NULL, NV_ERR_INVALID_STATE); + + if (!memdescAcquireRmExclusiveUse(pCntMem->pMemDesc) || + !memdescAcquireRmExclusiveUse(pBufMem->pMemDesc)) + { + pCntMem->pMemDesc->bRmExclusiveUse = NV_FALSE; + pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE; + return NV_ERR_INVALID_ARGUMENT; + } + + pProfiler->pBoundCntBuf = pCntRef; + pProfiler->pBoundPmaBuf = pBufRef; } - pProfiler->pBoundCntBuf = pCntRef; - pProfiler->pBoundPmaBuf = pBufRef; physical_control: + if (IS_VIRTUAL(pGpu)) + { + return _issueRpcToHost(pGpu); + } + status = pRmApi->Control(pRmApi, hClient, hObject, NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES, NULL, 0); @@ -180,6 +220,11 @@ profilerBaseCtrlCmdUnbindPmResources_IMPL pProfiler->pBoundPmaBuf = NULL; } + if (IS_VIRTUAL(pGpu)) + { + return _issueRpcToHost(pGpu); + } + return pRmApi->Control(pRmApi, hClient, hObject, NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES, NULL, 0); @@ -224,12 +269,12 @@ profilerBaseCtrlCmdAllocPmaStream_IMPL // REGISTER MEMDESCs TO GSP // These are no-op with BareMetal/No GSP // - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemPmaBuffer), fail); bMemPmaBufferRegistered = NV_TRUE; - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemPmaBytesAvailable), fail); bMemPmaBytesAvailableRegistered = NV_TRUE; @@ -253,36 +298,41 @@ profilerBaseCtrlCmdAllocPmaStream_IMPL &internalParams, sizeof(internalParams)), fail); pParams->pmaChannelIdx = internalParams.pmaChannelIdx; - if (pProfiler->ppBytesAvailable == NULL) + if (serverutilGetResourceRef(hClient, pParams->hMemPmaBytesAvailable, &pMemoryRef) == NV_OK && + serverutilGetResourceRef(hClient, pParams->hMemPmaBuffer, &pMemoryRef) == NV_OK) { - NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS maxPmaParams; - portMemSet(&maxPmaParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS)); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, hClient, hObject, - NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS, - &maxPmaParams, sizeof(maxPmaParams)), fail); + if (pProfiler->ppBytesAvailable == NULL) + { + NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS maxPmaParams; + portMemSet(&maxPmaParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS)); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, hClient, hObject, + NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS, + &maxPmaParams, sizeof(maxPmaParams)), fail); + + pProfiler->maxPmaChannels = maxPmaParams.maxPmaChannels; + pProfiler->ppBytesAvailable = (RsResourceRef**)portMemAllocNonPaged(maxPmaParams.maxPmaChannels * sizeof(RsResourceRef*)); + pProfiler->ppStreamBuffers = (RsResourceRef**)portMemAllocNonPaged(maxPmaParams.maxPmaChannels * sizeof(RsResourceRef*)); + } - pProfiler->maxPmaChannels = maxPmaParams.maxPmaChannels; - pProfiler->ppBytesAvailable = (RsResourceRef**)portMemAllocNonPaged(maxPmaParams.maxPmaChannels * sizeof(RsResourceRef*)); - pProfiler->ppStreamBuffers = (RsResourceRef**)portMemAllocNonPaged(maxPmaParams.maxPmaChannels * sizeof(RsResourceRef*)); - } - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - serverutilGetResourceRef(hClient, pParams->hMemPmaBytesAvailable, &pMemoryRef), fail); - pProfiler->ppBytesAvailable[pParams->pmaChannelIdx] = pMemoryRef; - refAddDependant(pMemoryRef, RES_GET_REF(pProfiler)); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + serverutilGetResourceRef(hClient, pParams->hMemPmaBytesAvailable, &pMemoryRef), fail); + pProfiler->ppBytesAvailable[pParams->pmaChannelIdx] = pMemoryRef; + refAddDependant(pMemoryRef, RES_GET_REF(pProfiler)); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - serverutilGetResourceRef(hClient, pParams->hMemPmaBuffer, &pMemoryRef), fail); - pProfiler->ppStreamBuffers[pParams->pmaChannelIdx] = pMemoryRef; - refAddDependant(pMemoryRef, RES_GET_REF(pProfiler)); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + serverutilGetResourceRef(hClient, pParams->hMemPmaBuffer, &pMemoryRef), fail); + pProfiler->ppStreamBuffers[pParams->pmaChannelIdx] = pMemoryRef; + refAddDependant(pMemoryRef, RES_GET_REF(pProfiler)); - // Copy output params to external struct. - pProfiler->pmaVchIdx = pParams->pmaChannelIdx; - pProfiler->bLegacyHwpm = NV_FALSE; + // Copy output params to external struct. + pProfiler->pmaVchIdx = pParams->pmaChannelIdx; + pProfiler->bLegacyHwpm = NV_FALSE; + } // Copy output params to external struct. pParams->pmaBufferVA = internalParams.pmaBufferVA; - + return status; fail: diff --git a/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c b/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c index 4cc40bd714..8dcab2ddfe 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c @@ -46,6 +46,7 @@ intrGetPendingStall_GM107 THREAD_STATE_NODE *pThreadState ) { + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); NvU8 i; NV_ASSERT_OR_RETURN(pEngines != NULL, NV_ERR_INVALID_ARGUMENT); @@ -77,6 +78,12 @@ intrGetPendingStall_GM107 if (IS_VIRTUAL(pGpu) && vgpuGetPendingEvent(pGpu, pThreadState)) bitVectorSet(pEngines, MC_ENGINE_IDX_VGPU); + if (pKernelDisplay != NULL && kdispGetDeferredVblankHeadMask(pKernelDisplay)) + { + // Deferred vblank is pending which we need to handle + bitVectorSet(pEngines, MC_ENGINE_IDX_DISP); + } + if (pGpu->fecsCtxswLogConsumerCount > 0) { // diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c index e3c54231a9..5293f7fb71 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -196,12 +196,11 @@ intrGetPendingNonStall_TU102 THREAD_STATE_NODE *pThreadState ) { - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i, j, k; - NvU32 pending; - NvU32 intrVector; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + InterruptTable *pIntrTable; + NvU32 i, j; + NvU32 pending; + NvU32 intrVector; NV_ASSERT_OR_RETURN(pEngines != NULL, NV_ERR_INVALID_ARGUMENT); @@ -227,7 +226,7 @@ intrGetPendingNonStall_TU102 return vgpuIsNonStallPending(pGpu, pEngines); } - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); FOR_EACH_INDEX_IN_MASK(64, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) { @@ -242,6 +241,7 @@ intrGetPendingNonStall_TU102 for (j = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i); j <= NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i); j++) { + InterruptTableIter iter; NvU32 intr = intrReadRegLeaf_HAL(pGpu, pIntr, j, pThreadState) & intrReadRegLeafEnSet_HAL(pGpu, pIntr, j, pThreadState); if (intr == 0) @@ -249,9 +249,10 @@ intrGetPendingNonStall_TU102 continue; } - for (k = 0; k < intrTableSz; k++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - NvU32 intrVector = pIntrTable[k].intrVectorNonStall; + INTR_TABLE_ENTRY *pEntry = iter.pValue; + NvU32 intrVector = pEntry->intrVectorNonStall; if (intrVector == NV_INTR_VECTOR_INVALID) { @@ -267,7 +268,7 @@ intrGetPendingNonStall_TU102 } if (intr & NVBIT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVector))) { - bitVectorSet(pEngines, pIntrTable[k].mcEngine); + bitVectorSet(pEngines, pEntry->mcEngine); } } } @@ -318,23 +319,21 @@ _intrServiceNonStallLeaf_TU102 THREAD_STATE_NODE *pThreadState ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NV_STATUS status = NV_OK; - NV_STATUS tmpStatus; - NvU32 i; - NvU16 mcEngineIdx; + InterruptTable *pIntrTable; + NV_STATUS status = NV_OK; + NV_STATUS tmpStatus; + InterruptTableIter iter; + NvU16 mcEngineIdx; // Don't clear the bitvector pEngines since caller accumulates + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); - - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - NvU32 intrVector; - NvU32 intrPending; + INTR_TABLE_ENTRY *pEntry = iter.pValue; + NvU32 intrVector = pEntry->intrVectorNonStall; + NvU32 intrPending; - intrVector = pIntrTable[i].intrVectorNonStall; if (intrVector == NV_INTR_VECTOR_INVALID) { // This engine does not have a valid nonstall interrupt vector @@ -354,7 +353,7 @@ _intrServiceNonStallLeaf_TU102 continue; } - mcEngineIdx = pIntrTable[i].mcEngine; + mcEngineIdx = pEntry->mcEngine; bitVectorSet(pEngines, mcEngineIdx); // diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c index 37ffb8c1c3..e359edb5f2 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,8 @@ #include "vgpu/vgpu_events.h" #include "vgpu/rpc.h" #include "gpu/mmu/kern_gmmu.h" +#include "libraries/nvport/nvport.h" +#include "gpu/disp/kern_disp.h" #include "published/turing/tu102/dev_ctrl.h" #include "published/turing/tu102/dev_vm.h" @@ -113,10 +115,10 @@ intrStateLoad_TU102 ) { NV_STATUS status = NV_OK; - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz, i; + InterruptTable *pIntrTable; + InterruptTableIter iter; - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); // // Make sure all leaf nodes are disabled before we enable them. Older drivers @@ -135,25 +137,26 @@ intrStateLoad_TU102 // and all the VFs // pGpu->pmcRmOwnsIntrMask = INTERRUPT_MASK_DISABLED; - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - if (pIntrTable[i].pmcIntrMask != NV_PMC_INTR_INVALID_MASK) + INTR_TABLE_ENTRY *pEntry = iter.pValue; + if (pEntry->pmcIntrMask != NV_PMC_INTR_INVALID_MASK) { - pGpu->pmcRmOwnsIntrMask |= pIntrTable[i].pmcIntrMask; + pGpu->pmcRmOwnsIntrMask |= pEntry->pmcIntrMask; - if (pIntrTable[i].mcEngine != MC_ENGINE_IDX_TMR) + if (pEntry->mcEngine != MC_ENGINE_IDX_TMR) continue; } - if (pIntrTable[i].intrVector != NV_INTR_VECTOR_INVALID) + if (pEntry->intrVector != NV_INTR_VECTOR_INVALID) { - intrEnableLeaf_HAL(pGpu, pIntr, pIntrTable[i].intrVector); + intrEnableLeaf_HAL(pGpu, pIntr, pEntry->intrVector); } - if ((pIntrTable[i].intrVectorNonStall != NV_INTR_VECTOR_INVALID) && - !pIntrTable[i].bDisableNonStall) + if ((pEntry->intrVectorNonStall != NV_INTR_VECTOR_INVALID) + ) { - intrEnableLeaf_HAL(pGpu, pIntr, pIntrTable[i].intrVectorNonStall); + intrEnableLeaf_HAL(pGpu, pIntr, pEntry->intrVectorNonStall); } } @@ -248,7 +251,7 @@ intrCacheIntrFields_TU102 } else { - pIntr->replayableFaultIntrVector = NV_INTR_VECTOR_INVALID; + pIntr->replayableFaultIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU, NV_FALSE); } if (pDisp != NULL) { @@ -719,7 +722,7 @@ _intrGetUvmLeafMask_TU102 NvBool bRmOwnsReplayableFault = !!(pKernelGmmu->uvmSharedIntrRmOwnsMask & RM_UVM_SHARED_INTR_MASK_MMU_REPLAYABLE_FAULT_NOTIFY); NvBool bRmOwnsAccessCntr = !!(pKernelGmmu->uvmSharedIntrRmOwnsMask & RM_UVM_SHARED_INTR_MASK_HUB_ACCESS_COUNTER_NOTIFY); - if (bRmOwnsReplayableFault && (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu))) + if (bRmOwnsReplayableFault) { val |= NVBIT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(pIntr->replayableFaultIntrVector)); } @@ -831,9 +834,9 @@ intrGetPendingStallEngines_TU102 THREAD_STATE_NODE *pThreadState ) { - INTR_TABLE_ENTRY *pIntrTable; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - NvU32 intrTableSz, i; + InterruptTable *pIntrTable; + InterruptTableIter iter; NvU64 sanityCheckSubtreeMask = 0; NvU32 numIntrLeaves = intrGetNumLeaves_HAL(pGpu, pIntr); NV_ASSERT(numIntrLeaves <= NV_MAX_INTR_LEAVES); @@ -851,14 +854,15 @@ intrGetPendingStallEngines_TU102 } NV_ASSERT_OK_OR_RETURN(intrGetLeafStatus_HAL(pGpu, pIntr, intrLeafValues, pThreadState)); - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - NvU32 intrVector; - NvU32 leaf, leafIndex, leafBit; - - intrVector = pIntrTable[i].intrVector; + INTR_TABLE_ENTRY *pEntry = iter.pValue; + NvU32 intrVector = pEntry->intrVector; + NvU32 leaf; + NvU32 leafIndex; + NvU32 leafBit; // Check if this engine has a valid stalling interrupt vector in the new tree if (intrVector == NV_INTR_VECTOR_INVALID) @@ -879,7 +883,10 @@ intrGetPendingStallEngines_TU102 if ((sanityCheckSubtreeMask & NVBIT64(NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(leafIndex))) == 0) { - NV_PRINTF(LEVEL_ERROR, "MC_ENGINE_IDX %u has invalid stall intr vector %u\n", pIntrTable[i].mcEngine, intrVector); + NV_PRINTF(LEVEL_ERROR, + "MC_ENGINE_IDX %u has invalid stall intr vector %u\n", + pEntry->mcEngine, + intrVector); DBG_BREAKPOINT(); continue; } @@ -899,7 +906,7 @@ intrGetPendingStallEngines_TU102 } // Add engine to bitvector - bitVectorSet(pEngines, pIntrTable[i].mcEngine); + bitVectorSet(pEngines, pEntry->mcEngine); } if (pKernelGmmu != NULL) @@ -1103,6 +1110,8 @@ intrGetPendingDisplayIntr_TU102 THREAD_STATE_NODE *pThreadState ) { + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + bitVectorClrAll(pEngines); if (IS_GPU_GC6_STATE_ENTERED(pGpu)) @@ -1115,6 +1124,14 @@ intrGetPendingDisplayIntr_TU102 return NV_ERR_GPU_IS_LOST; } + if (pKernelDisplay != NULL && kdispGetDeferredVblankHeadMask(pKernelDisplay)) + { + // Deferred vblank is pending which we need to handle + bitVectorSet(pEngines, MC_ENGINE_IDX_DISP); + // Nothing else to set here, return early + return NV_OK; + } + if (pIntr->displayIntrVector == NV_INTR_VECTOR_INVALID) { return NV_OK; @@ -1186,10 +1203,10 @@ intrDumpState_TU102 Intr *pIntr ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz = 0; - NvU32 i; - NvU32 intrLeafSize = intrGetLeafSize_HAL(pGpu, pIntr); + InterruptTable *pIntrTable; + InterruptTableIter iter; + NvU32 i; + NvU32 intrLeafSize = intrGetLeafSize_HAL(pGpu, pIntr); NV_PRINTF(LEVEL_INFO, "Interrupt registers:\n"); for (i = 0; i < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1; i++) @@ -1205,16 +1222,19 @@ intrDumpState_TU102 } NV_PRINTF(LEVEL_INFO, "MC Interrupt table:\n"); - intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz); + intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable); - for (i = 0; i < intrTableSz; i++) + for (i = 0, iter = vectIterAll(pIntrTable); vectIterNext(&iter); i++) { + INTR_TABLE_ENTRY *pEntry = iter.pValue; + PORT_UNREFERENCED_VARIABLE(pEntry); + NV_PRINTF(LEVEL_INFO, - "%2u: mcEngineIdx=%-4u intrVector=%-10u intrVectorNonStall=%-10u bDisableNonStall=%u\n", i, - pIntrTable[i].mcEngine, - pIntrTable[i].intrVector, - pIntrTable[i].intrVectorNonStall, - pIntrTable[i].bDisableNonStall); + "%2u: mcEngineIdx=%-4u intrVector=%-10u intrVectorNonStall=%-10u\n", + i, + pEntry->mcEngine, + pEntry->intrVector, + pEntry->intrVectorNonStall); } } diff --git a/src/nvidia/src/kernel/gpu/intr/intr.c b/src/nvidia/src/kernel/gpu/intr/intr.c index 59bd8b55de..93383ffd79 100644 --- a/src/nvidia/src/kernel/gpu/intr/intr.c +++ b/src/nvidia/src/kernel/gpu/intr/intr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -156,7 +156,7 @@ subdeviceCtrlCmdMcServiceInterrupts_IMPL Intr *pIntr = GPU_GET_INTR(pGpu); MC_ENGINE_BITVECTOR engines; NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); bitVectorClrAll(&engines); @@ -195,7 +195,7 @@ subdeviceCtrlCmdMcServiceInterrupts_IMPL NvU32 i; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); // Compute instances always contain 1 GR grCount = 1; @@ -543,30 +543,23 @@ intrGetVectorFromEngineId_IMPL NvBool bNonStall ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i; - NV_STATUS status; + InterruptTable *pIntrTable; + InterruptTableIter iter; + NV_STATUS status; - status = intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz); + status = intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable); if (status != NV_OK) { NV_ASSERT_OK_FAILED("Failed to get interrupt table", status); return NV_INTR_VECTOR_INVALID; } - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - if (pIntrTable[i].mcEngine == mcEngineId) + INTR_TABLE_ENTRY *pEntry = iter.pValue; + if (pEntry->mcEngine == mcEngineId) { - if (bNonStall) - { - return pIntrTable[i].intrVectorNonStall; - } - else - { - return pIntrTable[i].intrVector; - } + return bNonStall ? pEntry->intrVectorNonStall : pEntry->intrVector; } } @@ -592,22 +585,22 @@ intrConvertEngineMaskToPmcIntrMask_IMPL PMC_ENGINE_BITVECTOR engineMask ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i; - NvU32 pmcIntrMask = 0; + InterruptTable *pIntrTable; + InterruptTableIter iter; + NvU32 pmcIntrMask = 0; - if (NV_OK != intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)) + if (NV_OK != intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)) { NV_ASSERT(pmcIntrMask); return pmcIntrMask; } - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - if (bitVectorTest(engineMask, pIntrTable[i].mcEngine)) + INTR_TABLE_ENTRY *pEntry = iter.pValue; + if (bitVectorTest(engineMask, pEntry->mcEngine)) { - pmcIntrMask |= pIntrTable[i].pmcIntrMask; + pmcIntrMask |= pEntry->pmcIntrMask; } } @@ -631,24 +624,25 @@ intrConvertPmcIntrMaskToEngineMask_IMPL PMC_ENGINE_BITVECTOR pEngines ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i; + InterruptTable *pIntrTable; + InterruptTableIter iter; NV_ASSERT_OR_RETURN_VOID(pEngines != NULL); - NV_ASSERT_OR_RETURN_VOID(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz) == NV_OK); + NV_ASSERT_OR_RETURN_VOID( + intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable) == NV_OK); bitVectorClrAll(pEngines); - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - if (pIntrTable[i].pmcIntrMask == NV_PMC_INTR_INVALID_MASK) + INTR_TABLE_ENTRY *pEntry = iter.pValue; + if (pEntry->pmcIntrMask == NV_PMC_INTR_INVALID_MASK) { continue; } - if (pIntrTable[i].pmcIntrMask & pmcIntrMask) + if (pEntry->pmcIntrMask & pmcIntrMask) { - bitVectorSet(pEngines, pIntrTable[i].mcEngine); + bitVectorSet(pEngines, pEntry->mcEngine); } } } @@ -661,28 +655,24 @@ intrConvertPmcIntrMaskToEngineMask_IMPL NV_STATUS intrGetSmallestNotificationVector_IMPL ( - OBJGPU *pGpu, - Intr *pIntr, - NvU32 *pSmallestVector + OBJGPU *pGpu, + Intr *pIntr, + NvU32 *pSmallestVector ) { - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; - NvU32 i, leafIdx; - NvU32 val = NV_INTR_VECTOR_INVALID; + InterruptTable *pIntrTable; + InterruptTableIter iter; + NvU32 val = NV_INTR_VECTOR_INVALID; + NV_ASSERT_OR_RETURN(pSmallestVector != NULL, NV_ERR_INVALID_ARGUMENT); *pSmallestVector = val; - NV_ASSERT_OR_RETURN(pSmallestVector != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); + NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { - NvU32 curVector = pIntrTable[i].intrVectorNonStall; - if (curVector < val) - { - val = curVector; - } + val = NV_MIN(val, + ((INTR_TABLE_ENTRY *)iter.pValue)->intrVectorNonStall); } // @@ -690,8 +680,9 @@ intrGetSmallestNotificationVector_IMPL // This should be consistent across all chips even if they have different // floorsweeping configs // - leafIdx = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(val)); - *pSmallestVector = NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(leafIdx); + *pSmallestVector = NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START( + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START( + NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(val))); return NV_OK; } @@ -738,6 +729,7 @@ intrConstructEngine_IMPL return NV_OK; } + void intrDestruct_IMPL ( @@ -753,6 +745,7 @@ intrDestruct_IMPL pNode = intrDequeueDpc(pGpu, pIntr, pDPCQueue); portMemFree(pNode); } + } @@ -796,6 +789,7 @@ intrStateInitLocked_IMPL Intr *pIntr ) { + NV_STATUS status = NV_OK; // Enable interrupts in the HAL pIntr->halIntrEnabled = NV_TRUE; @@ -813,7 +807,7 @@ intrStateInitLocked_IMPL pKernelGmmu->uvmSharedIntrRmOwnsMask = RM_UVM_SHARED_INTR_MASK_ALL; } - NV_ASSERT_OK_OR_RETURN(intrInitInterruptTable_HAL(pGpu, pIntr)); + NV_ASSERT_OK_OR_GOTO(status, intrInitInterruptTable_HAL(pGpu, pIntr), exit); _intrInitServiceTable(pGpu, pIntr); if (pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING)) @@ -832,7 +826,9 @@ intrStateInitLocked_IMPL // Hypervisor will set the intr unblocked mask later at the time of SWRL init. } - return NV_OK; +exit: + + return status; } void @@ -972,65 +968,57 @@ NV_STATUS intrInitInterruptTable_KERNEL ( OBJGPU *pGpu, - Intr *pIntr + Intr *pIntr ) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status = NV_OK; - NvU32 i = 0; - INTR_TABLE_ENTRY *pIntrTable = NULL; + NvU32 i; NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS *pParams; - NV_ASSERT_OR_RETURN(pIntr->pIntrTable == NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(vectIsEmpty(&pIntr->intrTable), NV_ERR_INVALID_STATE); pParams = portMemAllocNonPaged(sizeof(*pParams)); - if (pParams == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Could not allocate params for kernel intr table control"); - status = NV_ERR_NO_MEMORY; - goto exit; - } + NV_ASSERT_TRUE_OR_GOTO(status, pParams != NULL, NV_ERR_NO_MEMORY, exit); NV_ASSERT_OK_OR_GOTO(status, - pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE, - pParams, sizeof(*pParams)), + pParams, + sizeof *pParams), exit); + NV_ASSERT_TRUE_OR_GOTO(status, + pParams->tableLen <= + NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE, + NV_ERR_OUT_OF_RANGE, + exit); - status = NV_ERR_INVALID_PARAMETER; - NV_ASSERT_OR_GOTO(pParams->tableLen <= NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE, exit); - - pIntrTable = portMemAllocNonPaged(sizeof(INTR_TABLE_ENTRY) * pParams->tableLen); - if (pIntrTable == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Could not allocate kernel interrupt table"); - status = NV_ERR_NO_MEMORY; - goto exit; - } - portMemSet(pIntrTable, 0, sizeof(INTR_TABLE_ENTRY) * pParams->tableLen); - + NV_ASSERT_OK_OR_GOTO(status, + vectInit(&pIntr->intrTable, + portMemAllocatorGetGlobalNonPaged(), + pParams->tableLen), + exit); for (i = 0; i < pParams->tableLen; ++i) { - pIntrTable[i].mcEngine = pParams->table[i].engineIdx; - pIntrTable[i].pmcIntrMask = pParams->table[i].pmcIntrMask; - pIntrTable[i].intrVector = pParams->table[i].vectorStall; - pIntrTable[i].intrVectorNonStall = pParams->table[i].vectorNonStall; + INTR_TABLE_ENTRY entry = {0}; + entry.mcEngine = pParams->table[i].engineIdx; + entry.pmcIntrMask = pParams->table[i].pmcIntrMask; + entry.intrVector = pParams->table[i].vectorStall; + entry.intrVectorNonStall = pParams->table[i].vectorNonStall; + NV_ASSERT_TRUE_OR_GOTO(status, + vectAppend(&pIntr->intrTable, &entry) != NULL, + NV_ERR_NO_MEMORY, + exit); } - - // Transfer ownership of allocated table to pIntr and clear local to avoid MemFree - pIntr->pIntrTable = pIntrTable; - pIntr->intrTableSz = pParams->tableLen; - pIntrTable = NULL; + NV_ASSERT_OK_OR_GOTO(status, vectTrim(&pIntr->intrTable, 0), exit); portMemCopy(pIntr->subtreeMap, sizeof pIntr->subtreeMap, pParams->subtreeMap, sizeof pParams->subtreeMap); - status = NV_OK; - exit: portMemFree(pParams); - portMemFree(pIntrTable); - return status; } @@ -1221,43 +1209,26 @@ intrCheckAndServiceFecsEventbuffer_IMPL NV_STATUS intrGetInterruptTable_IMPL ( - OBJGPU *pGpu, - Intr *pIntr, - INTR_TABLE_ENTRY **ppTable, - NvU32 *pTableSz + OBJGPU *pGpu, + Intr *pIntr, + InterruptTable **ppTable ) { NV_ASSERT_OR_RETURN(ppTable != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pTableSz != NULL, NV_ERR_INVALID_ARGUMENT); - - NV_ASSERT_OR_RETURN(pIntr->pIntrTable != NULL, NV_ERR_INVALID_STATE); - - *ppTable = pIntr->pIntrTable; - *pTableSz = pIntr->intrTableSz; - + NV_ASSERT_OR_RETURN(!vectIsEmpty(&pIntr->intrTable), NV_ERR_INVALID_STATE); + *ppTable = &pIntr->intrTable; return NV_OK; } -/** - * @brief Frees memory associated with interrupt table - * - * @param pGpu - * @param pMc - */ + NV_STATUS intrDestroyInterruptTable_IMPL ( - OBJGPU *pGpu, - Intr *pIntr + OBJGPU *pGpu, + Intr *pIntr ) { - if (pIntr->pIntrTable != NULL) - { - portMemFree(pIntr->pIntrTable); - pIntr->pIntrTable = NULL; - pIntr->intrTableSz = 0; - } - + vectDestroy(&pIntr->intrTable); return NV_OK; } @@ -1432,22 +1403,22 @@ _intrServiceStallExactList NvU32 engineIdx; NvU32 intr; - NvU32 i; NvBool bHandled; NvBool bIntrStuck = NV_FALSE; NvBool bPending = NV_FALSE; NvBool bRequiresPossibleErrorNotifier; - INTR_TABLE_ENTRY *pIntrTable; - NvU32 intrTableSz; + InterruptTable *pIntrTable; + InterruptTableIter iter; if (bitVectorTestAllCleared(pEngines)) { return NV_FALSE; } - NV_ASSERT_OK_OR_ELSE(status, intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz), - return NV_FALSE); + NV_ASSERT_OK_OR_ELSE(status, + intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable), + return NV_FALSE); bRequiresPossibleErrorNotifier = intrRequiresPossibleErrorNotifier_HAL(pGpu, pIntr, pEngines); @@ -1463,8 +1434,10 @@ _intrServiceStallExactList gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); } - for (i = 0; i < intrTableSz; i++) + for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { + INTR_TABLE_ENTRY *pEntry = iter.pValue; + // Skip servicing interrupts when GPU is off the bus if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu)) { @@ -1477,7 +1450,7 @@ _intrServiceStallExactList return NV_FALSE; } - engineIdx = pIntrTable[i].mcEngine; + engineIdx = pEntry->mcEngine; if (bitVectorTest(pEngines, engineIdx)) { diff --git a/src/nvidia/src/kernel/gpu/intr/swintr.c b/src/nvidia/src/kernel/gpu/intr/swintr.c index fca2c8bd6d..788a9d9045 100644 --- a/src/nvidia/src/kernel/gpu/intr/swintr.c +++ b/src/nvidia/src/kernel/gpu/intr/swintr.c @@ -62,7 +62,7 @@ swintrServiceInterrupt_IMPL ) { NV_ASSERT_OR_RETURN(pParams != NULL, 0); - + switch (pParams->engineIdx) { case MC_ENGINE_IDX_CPU_DOORBELL: diff --git a/src/nvidia/src/kernel/gpu/kern_gpu_power.c b/src/nvidia/src/kernel/gpu/kern_gpu_power.c new file mode 100644 index 0000000000..fe16c2e34f --- /dev/null +++ b/src/nvidia/src/kernel/gpu/kern_gpu_power.c @@ -0,0 +1,666 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/kern_gpu_power.h" +#include "os/os.h" +#include "nvRmReg.h" +#include "diagnostics/journal.h" +#include "diagnostics/tracer.h" +#include "jt.h" +#include "ctrl/ctrl2080/ctrl2080power.h" + +#include "g_journal_pb.h" + + +// Polling loop delays +#define GC6_PWR_CHECK_DELAY_MS 5 +#define GC6_BUS_CHECK_DELAY_MS 1 + +// +// Static functions +// +static NV_STATUS _gpuGc6EntrySanityCheck(OBJGPU *, NV2080_CTRL_GC6_ENTRY_PARAMS *); +static void _gpuGc6EntrySwStateUpdate(OBJGPU *, NV2080_CTRL_GC6_ENTRY_PARAMS *); +static void _gpuGc6EntryFailed(OBJGPU *); +static NV_STATUS _gpuGc6EntryStateUnload(OBJGPU *); +static NV_STATUS _gpuGc6ExitSanityCheck(OBJGPU *); +static NV_STATUS _gpuGc6ExitGpuPowerOn(OBJGPU *, NV2080_CTRL_GC6_EXIT_PARAMS *); +static NV_STATUS _gpuGc6ExitStateLoad(OBJGPU *, NV2080_CTRL_GC6_EXIT_PARAMS *); +static void _gpuGc6ExitSwStateRestore(OBJGPU *); +static void _gpuForceGc6inD3Hot(OBJGPU *, NV2080_CTRL_GC6_EXIT_PARAMS *); + +/*! + * @brief: This HAL function executes the steps of GC6 exit sequence + * + * @param[in] pGpu GPU object pointer + * @param[in,out] pParams Parameter struct + * + * @return + * NV_OK Success + * NV_ERR_GENERIC Generic error (bad state or stuck) + */ +NV_STATUS +gpuGc6Exit_IMPL( + OBJGPU *pGpu, + NV2080_CTRL_GC6_EXIT_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + + // Check if we need to execute GPU_ON step + if (GPU_IS_GC6_STEP_ID_SET(GPU_OFF, pGpu->gc6State.executedStepMask)) + { + // Sanity error checking + status = _gpuGc6ExitSanityCheck(pGpu); + if (status != NV_OK) + { + goto gpuGc6Exit_IMPL_exit; + } + + // GPU power on + status = _gpuGc6ExitGpuPowerOn(pGpu, pParams); + if (status != NV_OK) + { + goto gpuGc6Exit_IMPL_exit; + } + + // Set the GPU state as GC6_STATE_EXITING + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_EXITING); + + // GPU power on + status = _gpuGc6ExitStateLoad(pGpu, pParams); + if (status != NV_OK) + { + goto gpuGc6Exit_IMPL_exit; + } + + // Set the GPU state as GC6_STATE_EXITED + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_EXITED); + NV_PRINTF(LEVEL_INFO, "GPU is now in D0 state.\n"); + + // Restore SW state + _gpuGc6ExitSwStateRestore(pGpu); + + } + + // Check if we need to execute SR_EXIT step + if (GPU_IS_GC6_STEP_ID_SET(SR_ENTRY, pGpu->gc6State.executedStepMask)) + { + + } + +gpuGc6Exit_IMPL_exit: + // Reset the executed step mask + pGpu->gc6State.executedStepMask = 0; + + return status; +} + +/*! + * @brief: This HAL function executes the steps of GC6 entry sequence + * + * @param[in] pGpu GPU object pointer + * @param[in,out] pParams Parameter struct + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid action + * NV_ERR_NOT_SUPPORTED Chip doesn't support the feature + * NV_ERR_NOT_READY Chip not ready to execute operation + * NV_ERR_INVALID_STATE Chip unable to execute command at current state + * NV_ERR_TIMEOUT RM timed out when trying to complete call + * NV_ERR_GENERIC Generic error (bad state or stuck) + */ +NV_STATUS +gpuGc6Entry_IMPL( + OBJGPU *pGpu, + NV2080_CTRL_GC6_ENTRY_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + + // Check if we need to execute GPU_OFF step + if (GPU_IS_GC6_STEP_ID_SET(GPU_OFF, pParams->stepMask)) + { + // Sanity error checking + status = _gpuGc6EntrySanityCheck(pGpu, pParams); + if (status != NV_OK) + { + goto gpuGc6Entry_IMPL_exit; + } + + // SW state update + _gpuGc6EntrySwStateUpdate(pGpu, pParams); + + // Set the GPU state as GC6_STATE_ENTERING + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_ENTERING); + + // RM state unload + status = _gpuGc6EntryStateUnload(pGpu); + if (status != NV_OK) + { + goto gpuGc6Entry_IMPL_exit; + } + + // Sanity check p-state is in P8 + status = gpuGc6EntryPstateCheck(pGpu); + if (status != NV_OK) + { + _gpuGc6EntryFailed(pGpu); + goto gpuGc6Entry_IMPL_exit; + } + + // GPU power off + status = gpuGc6EntryGpuPowerOff(pGpu); + if (status != NV_OK) + { + goto gpuGc6Entry_IMPL_exit; + } + + // Set the GPU state as GC6_STATE_ENTERED + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_ENTERED); + NV_PRINTF(LEVEL_INFO, "GPU is now in GC6 state.\n"); + + // Add this step in executed step mask + pGpu->gc6State.executedStepMask |= NVBIT(NV2080_CTRL_GC6_STEP_ID_GPU_OFF); + } + +gpuGc6Entry_IMPL_exit: + return status; +} + +/*! + * @brief: Helper function for doing powering down GPU during GC6 entry + * + * @param[in] pGpu OBJGPU pointer + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +NV_STATUS +gpuGc6EntryGpuPowerOff(OBJGPU *pGpu) +{ + NV_STATUS status = NV_OK; + + // SW pre-settings before calling power off. + NV_ASSERT_OK_OR_RETURN(gpuPrePowerOff_HAL(pGpu)); + + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE) && + !pGpu->acpiMethodData.jtMethodData.bSBIOSCaps)) + { + status = NV_OK; + NV_PRINTF(LEVEL_INFO, + "Skip call to power off GPU in OSPM RTD3\n"); + goto _gpuGc6EntryGpuPowerOff_EXIT; + } + + // call on all GC6 systems that contain SBIOS JT caps + status = gpuPowerOff(pGpu); + +_gpuGc6EntryGpuPowerOff_EXIT: + if (status != NV_OK) + { + _gpuGc6EntryFailed(pGpu); + NV_PRINTF(LEVEL_ERROR, "Call to power off GPU failed.\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +/*! + * @brief Power off GPU and enter GC6 state. + * + * This function implements last phase of GC6 entry sequence as defined in + * JT Architecture Specification. + * + * @param[in] pGpu GPU object pointer + * + * @return NV_OK + * If GPU has entered (or is entering) GC6 state. + * + * @return other Bubbles up errors from + * @ref osGC6PowerControl on failure. + */ +NV_STATUS +gpuPowerOff_KERNEL(OBJGPU *pGpu) +{ + + NvU32 deferCmd = 0x134c02; + + if (!pGpu->acpiMethodData.jtMethodData.bSBIOSCaps && + pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE)) + { + return NV_OK; + } + + NV_ASSERT_OK_OR_RETURN( + osGC6PowerControl(pGpu, deferCmd, NULL)); + + return NV_OK; +} + +/*! + * @brief Power on GPU + * + * This function implements first phase of GC6 exit sequence as defined in + * JT Architecture Specification. + * + * @param[in] pGpu GPU object pointer + * + * @return NV_OK + * If GPU showed up on the bus. + * + * @return NV_ERR_TIMEOUT + * If timeout occurred while waiting for GPU to show up on the bus. + * + * @return other Bubbles up errors from @ref osGC6PowerControl on failure. + */ +NV_STATUS +gpuPowerOn_KERNEL(OBJGPU *pGpu) +{ + NV_STATUS status; + NvU32 powerStatus; + RMTIMEOUT timeout; + + // We do not make any _DSM calls for OSPM + RTD3 + if (!pGpu->acpiMethodData.jtMethodData.bSBIOSCaps && + pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE)) + { + return NV_OK; + } + + // + // Pick the correct command to send to the _DSM + // If we are on MsHybrid, the OS has already made the call to power on GPU + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE)) + { + // clear the deferred entry/exit state in the SBIOS + NV_ASSERT_OK_OR_RETURN( + osGC6PowerControl(pGpu, 0x8000, &powerStatus)); + } + + // + // wait for SBIOS to report that GPU is powered on. When the GPU is reported + // as "powered on" both the below conditions are true + // 1. The Pex Link is Powered Up + // 2. EC reports PWR_OK to be asserted. + // + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + while (NV_TRUE) + { + NV_ASSERT_OK_OR_RETURN( + osGC6PowerControl(pGpu, 0x0, &powerStatus)); + + if (FLD_TEST_DRF(_JT_FUNC, _POWERCONTROL, _GPU_POWER_STATE, _PWOK, powerStatus)) + { + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + RMTRACE_GPU(_GC6_POWERON_ERR_TO, pGpu->gpuId, 0, 0, 0, 0, 0, 0, 0); + NV_PRINTF(LEVEL_ERROR, + "Timeout waiting for GPU to enter PWOK/ON state.Current State %x\n", + powerStatus); + DBG_BREAKPOINT(); + return status; + } + + // For same reasons as above, loosen the polling loop. + osDelay(GC6_PWR_CHECK_DELAY_MS); + } + + // + // There is a possibility that GPU hasn't yet appeared on the bus even + // though the link is up. Wait here for the GPU to appear on the bus before + // proceeding. Note, it's not recommended to poll on the device config + // space till the pex link in the root port is restored, but since link + // should be up by the time OS_GC6_GET_GPU_POWER_STATE returns STATUS_ON + // it is safe to do so here. We want to be absolutely sure that the GPU + // is on the bus before we proceed and restore the GPU config space. + // + if (!gpuIsOnTheBus(pGpu)) + { + NV_PRINTF(LEVEL_WARNING, + "GPU is not yet on the bus after GC6 power-up.\n"); + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + while (!gpuIsOnTheBus(pGpu)) + { + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + RMTRACE_GPU(_GC6_POWERON_ERR_BUS_TO, pGpu->gpuId, 0, 0, 0, 0, 0, 0, 0); + NV_PRINTF(LEVEL_ERROR, + "Timeout waiting for GPU to appear on the bus.\n"); + DBG_BREAKPOINT(); + return status; + } + + // For same reasons as above, loosen the polling loop. + osDelay(GC6_BUS_CHECK_DELAY_MS); + } + } + + return NV_OK; +} + +/*! + * @brief Check if GPU is on the bus. + * + * @param[in] pGpu GPU object pointer + * + * @return 'NV_TRUE' if GPU is on the bus; 'NV_FALSE' otherwise. + */ +NvBool +gpuIsOnTheBus_IMPL(OBJGPU *pGpu) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU16 vendorId, deviceId; + void *handle; + + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + return (handle != NULL); +} + +/*! + * @brief: Helper function for sanity error checking during GC6 entry + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pParams Pointer to RmCtrl parameters + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6EntrySanityCheck(OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *pParams) +{ + NV_STATUS status = NV_OK; + + // + // Sanity check RTD3 enablement + // TODO: replace with PDB that indicates system support of RTD3, not just the chip + // + if (pParams->params.bIsRTD3Transition && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF)) + { + NV_PRINTF(LEVEL_ERROR, + "Cannot perform RTD3 as chip does not support.\n"); + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; + } + + if (IS_GPU_GC6_STATE_ENTERED(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "GPU is already in GC6 state or stuck in transition.\n"); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_STATE; + } + + // Wait for GPU to be ready for GC6 + status = gpuWaitGC6Ready_HAL(pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GPU is not ready to transition from D0 to GC6 state.\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +/*! + * @brief: Helper function for updating SW state during GC6 entry + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pParams Pointer to RmCtrl parameters + */ +static void +_gpuGc6EntrySwStateUpdate(OBJGPU *pGpu, NV2080_CTRL_GC6_ENTRY_PARAMS *pParams) +{ + + // set state if we are doing an MsHybrid GC6 cycle OR Fast GC6 cycle + if (pParams->flavorId == NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE, NV_TRUE); + } + + // set state if we are doing a RTD3 GC6 cycle + if (pParams->params.bIsRTD3Transition) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE, NV_TRUE); + + } +} + +/*! + * @brief: Helper function for restoring SW state during failed GC6 entry + * + * @param[in] pGpu OBJGPU pointer + */ +static void +_gpuGc6EntryFailed(OBJGPU *pGpu) +{ + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_ENTERING_FAILED); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_FAST_GC6_ACTIVE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE, NV_FALSE); +} + +/*! + * @brief: Helper function for doing RM state unload during GC6 entry + * + * @param[in] pGpu OBJGPU pointer + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6EntryStateUnload(OBJGPU *pGpu) +{ + NV_STATUS status; + + pGpu->setProperty(pGpu, PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL, NV_TRUE); + status = gpuEnterStandby(pGpu); + pGpu->setProperty(pGpu, PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL, NV_FALSE); + + if (status != NV_OK) + { + _gpuGc6EntryFailed(pGpu); + NV_PRINTF(LEVEL_ERROR, + "GPU is unable to transition from D0 to GC6 state.\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +/*! + * @brief: Helper function for sanity error checking during GC6 exit + * + * @param[in] pGpu OBJGPU pointer + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6ExitSanityCheck(OBJGPU *pGpu) +{ + NV_STATUS status = NV_OK; + + + // Make sure that the current GC6 state is GPU_STATE_ENTERED_GC6 + if (!IS_GPU_GC6_STATE_ENTERED(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "GPU is not in GC6 state.\n"); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_STATE; + } + + return status; +} + +/*! + * @brief: Helper function for doing powering up GPU during GC6 exit + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pParams Pointer to RmCtrl parameters + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6ExitGpuPowerOn(OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *pParams) +{ + NV_STATUS status = NV_OK; + + return status; +} + +/*! + * @brief: Helper function for restoring SW state during GC6 exit + * + * @param[in] pGpu OBJGPU pointer + */ +static void +_gpuGc6ExitSwStateRestore(OBJGPU *pGpu) +{ + pGpu->setProperty(pGpu, PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_FAST_GC6_ACTIVE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE, NV_FALSE); +} + +/*! + * @brief: Helper function to force GC6 cycle in this D3 hot exit + * + * @param[in] pGpu OBJGPU pointer + */ +static void +_gpuForceGc6inD3Hot(OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *pParams) +{ + + pParams->params.bIsRTD3HotTransition = NV_FALSE; + // + // If this was a D3Hot cycle (no power down), force a GC6 cycle + // This is due to instability of some memory types with D3Hot cycles + // Skip this on RTD3 cycles since we won't have the _DSMs to force cycles + // Summarize the scenario that needs to do _DSM reset + // 1. It's OSPM but not RTD3. + // 2. GPU power was not cut. + // 3. The D3Hot WAR is enabled + // Note _FORCE_D3HOT works only on NVPM + // + + // + // Enable BAR0 accesses here for RTLSIM, EMU, and silicon MFG MODS. + // FMODEL will not be reset, so no need to enable. + // Windows will be pci bus driver to restore, but below function will check before enabling. + // Only enable BAR0 accesses here, + // and leave whole restore steps in gpuPowerManagementResumePreLoadPhysical(). + // + if (!IS_FMODEL(pGpu) && IS_GPU_GC6_STATE_EXITING(pGpu)) + { + NV_STATUS tempStatus = kbifPollDeviceOnBus(pGpu, GPU_GET_KERNEL_BIF(pGpu)); + + if (tempStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Enable BAR0 accesses failed.\n"); + } + } + + // The power remains is necessary for d3hot + if (!gpuCompletedGC6PowerOff_HAL(pGpu)) + { + pParams->params.bIsRTD3HotTransition = NV_TRUE; + + NV_PRINTF(LEVEL_ERROR, + "D3Hot detected. Going to recover from D3Hot\n"); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF) + ) + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_ACTIVE)) + { + NV_PRINTF(LEVEL_ERROR, + "D3Hot case for Turing and later but legacy GC6/FGC6 flavor.\n"); + } + } + // none RTD3 D3Hot and none legacy D3Hot WAR + else + { + NV_PRINTF(LEVEL_ERROR, + "D3Hot case for none RTD3 and no WAR enabled.\n"); + } + + } // End of if (!gpuCompletedGC6PowerOff_HAL(pGpu)) +} + +/*! + * @brief: Helper function for doing RM state load during GC6 exit + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pParams Pointer to RmCtrl parameters + * + * @return + * NV_OK Success + * NV_ERR Otherwise + */ +static NV_STATUS +_gpuGc6ExitStateLoad(OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *pParams) +{ + NV_STATUS status = NV_OK; + + pGpu->setProperty(pGpu, PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL, NV_TRUE); + + // Force GC6 cycle if this D3 hot + _gpuForceGc6inD3Hot(pGpu, pParams); + + status = gpuResumeFromStandby(pGpu); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL, NV_FALSE); + + if (status != NV_OK) + { + SET_GPU_GC6_STATE_AND_LOG(pGpu, GPU_GC6_STATE_EXITING_FAILED); + NV_PRINTF(LEVEL_ERROR, + "GPU is unable to transition from GC6 to D0 state.\n"); + DBG_BREAKPOINT(); + } + + return status; +} + diff --git a/src/nvidia/src/kernel/gpu/mc/kernel_mc.c b/src/nvidia/src/kernel/gpu/mc/kernel_mc.c index 8ef4d36307..f21f713885 100644 --- a/src/nvidia/src/kernel/gpu/mc/kernel_mc.c +++ b/src/nvidia/src/kernel/gpu/mc/kernel_mc.c @@ -53,7 +53,7 @@ subdeviceCtrlCmdMcGetArchInfo_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - if (IsTEGRA(pGpu)) + if (IsTEGRA_NVDISP_GPUS(pGpu)) { pArchInfoParams->architecture = pGpu->chipInfo.platformId; pArchInfoParams->implementation = pGpu->chipInfo.implementationId; @@ -61,16 +61,8 @@ subdeviceCtrlCmdMcGetArchInfo_IMPL } else { - if (pGpu->idInfo.ArchitectureExternal && pGpu->idInfo.ImplementationExternal) - { - pArchInfoParams->architecture = pGpu->idInfo.ArchitectureExternal; - pArchInfoParams->implementation = pGpu->idInfo.ImplementationExternal; - } - else - { - pArchInfoParams->architecture = pGpu->chipInfo.pmcBoot0.arch; - pArchInfoParams->implementation = pGpu->chipInfo.pmcBoot0.impl; - } + pArchInfoParams->architecture = pGpu->chipInfo.pmcBoot0.arch; + pArchInfoParams->implementation = pGpu->chipInfo.pmcBoot0.impl; pArchInfoParams->revision = (pGpu->chipInfo.pmcBoot0.majorRev << 4) | pGpu->chipInfo.pmcBoot0.minorRev; pArchInfoParams->subRevision = pGpu->chipInfo.subRevision; } @@ -124,11 +116,6 @@ subdeviceCtrlCmdMcChangeReplayableFaultOwnership_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } - if (pKernelGmmu != NULL) { kgmmuChangeReplayableFaultOwnership_HAL(pGpu, pKernelGmmu, pReplayableFaultOwnrshpParams->bOwnedByRm); @@ -243,7 +230,7 @@ kmcStateLoad_IMPL // Adjust the pci latency timer if needed _kmcSetPciLatencyTimer(pGpu, pKernelMc); } - + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c index d5f865730e..71301acd53 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c @@ -26,11 +26,12 @@ #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/fbsr.h" -static NV_STATUS -fbsrSendMemsysProgramRawCompressionMode +NV_STATUS +fbsrSendMemsysProgramRawCompressionMode_GA100 ( - OBJGPU *pGpu, - NvBool bRawMode + OBJGPU *pGpu, + OBJFBSR *pFbsr, + NvBool bRawMode ) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); @@ -69,7 +70,7 @@ fbsrBegin_GA100(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op) if (pMemorySystemConfig->bUseRawModeComptaglineAllocation) { - NV_ASSERT_OK(fbsrSendMemsysProgramRawCompressionMode(pGpu, NV_FALSE)); + NV_ASSERT_OK(fbsrSendMemsysProgramRawCompressionMode_HAL(pGpu, pFbsr, NV_FALSE)); pFbsr->bRawModeWasEnabled = NV_TRUE; } } @@ -90,13 +91,13 @@ fbsrEnd_GA100(OBJGPU *pGpu, OBJFBSR *pFbsr) { NV_STATUS status = fbsrEnd_GM107(pGpu, pFbsr); - if (pFbsr->op == FBSR_OP_RESTORE && - pFbsr->bRawModeWasEnabled) + if (pFbsr->op == FBSR_OP_RESTORE && pFbsr->bRawModeWasEnabled) { /* * Reenable raw mode if it was disabled by fbsrBegin_GA100. */ - NV_ASSERT_OK(fbsrSendMemsysProgramRawCompressionMode(pGpu, NV_TRUE)); + NV_ASSERT_OK(fbsrSendMemsysProgramRawCompressionMode_HAL(pGpu, pFbsr, NV_TRUE)); + pFbsr->bRawModeWasEnabled = NV_FALSE; } return status; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c index 44917d7b93..475ad45413 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c @@ -110,10 +110,6 @@ memmgrScrubRegistryOverrides_GA100 // Disabling for GSP-RM ucode, since scrubbing is done from CPU-side kernel RM. // Enabling virtual scrubbing mode for SRIOV-HEAVY mode. // - // Temporary: Disabling scrub on free if CC is enabled. Once the - // support for secure work launch is in, this temporary change can be - // reverted. Bug: 3334708 - // if ((RMCFG_FEATURE_PLATFORM_WINDOWS && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) || IS_SIMULATION(pGpu) || IsDFPGA(pGpu) || @@ -121,7 +117,6 @@ memmgrScrubRegistryOverrides_GA100 IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || RMCFG_FEATURE_PLATFORM_GSP || (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) && !gpuIsCacheOnlyModeEnabled(pGpu)) || - gpuIsCCFeatureEnabled(pGpu) || IsSLIEnabled(pGpu)) { pMemoryManager->bScrubOnFreeEnabled = NV_FALSE; @@ -364,20 +359,27 @@ memmgrGetBlackListPages_GA100 return NV_ERR_NOT_SUPPORTED; } + NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS *pBlParams = + portMemAllocNonPaged(sizeof(*pBlParams)); + if (pBlParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + while (baseIndex < NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES) { RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) : rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS blParams = {0}; + portMemSet(pBlParams, 0, sizeof(*pBlParams)); - blParams.baseIndex = baseIndex; + pBlParams->baseIndex = baseIndex; status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES, - &blParams, - sizeof(blParams)); + pBlParams, + sizeof(*pBlParams)); if(NV_OK != status) { if (NV_ERR_NOT_SUPPORTED == status || @@ -395,7 +397,7 @@ memmgrGetBlackListPages_GA100 break; } - for (idx = 0; idx < blParams.validEntries; idx++) + for (idx = 0; idx < pBlParams->validEntries; idx++) { if (entryIdx >= *pCount) @@ -403,12 +405,12 @@ memmgrGetBlackListPages_GA100 status = NV_ERR_BUFFER_TOO_SMALL; goto done; } - pBlAddrs[entryIdx].address = blParams.offlined[idx].pageNumber << RM_PAGE_SHIFT; - pBlAddrs[entryIdx].type = blParams.offlined[idx].source; + pBlAddrs[entryIdx].address = pBlParams->offlined[idx].pageNumber << RM_PAGE_SHIFT; + pBlAddrs[entryIdx].type = pBlParams->offlined[idx].source; entryIdx++; } - if (!blParams.bMore) { + if (!pBlParams->bMore) { break; } @@ -416,6 +418,7 @@ memmgrGetBlackListPages_GA100 } done: + portMemFree(pBlParams); *pCount = entryIdx; return status; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c index d30881ab52..8d4c382a94 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c @@ -28,7 +28,7 @@ /*! - * Function to verify which memory scubber (fast/slow) has to use in Hopper+ for scrubbering + * Function to verify which memory scubber (fast/slow) has to use in Hopper+ for scrubbering * * @param[in] copyClass DMA ccopy class * @param[in] bIsVirtualMemory Memory type @@ -36,7 +36,7 @@ * @param[in] size Size of the region to scrub * @param[in] dstAddressSpace DST address space * - * @returns NV_TRUE - Use memory fast scrbber for scrubbing + * @returns NV_TRUE - Use memory fast scrbber for scrubbing * NV_FALSE - Use slow scrubber */ NvBool @@ -64,7 +64,7 @@ memmgrMemUtilsCheckMemoryFastScrubEnable_GH100 // Address is 4KB aligned // LineLength is 4KB aligned // - return ((copyClass == HOPPER_DMA_COPY_A + return ((copyClass == HOPPER_DMA_COPY_A ) && (!bIsVirtualMemory) && (dstAddressSpace == ADDR_FBMEM) && diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c index 0cccdb1c08..3b0cce20ea 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c @@ -54,7 +54,6 @@ dmaAllocBar1P2PMapping_GH100 NvU64 bar1ApertureLen = 0; // BAR1 aperture mapped lengths OBJGPU *pPeerGpu = NULL; KernelBus *pPeerKernelBus = NULL; - NvHandle hClient = NV01_NULL_OBJECT; NV_STATUS status = NV_OK; if (params == NULL || @@ -89,7 +88,7 @@ dmaAllocBar1P2PMapping_GH100 &phyAddr, &bar1ApertureLen, BUS_MAP_FB_FLAGS_MAP_UNICAST, - hClient); + NULL); if (status != NV_OK) goto cleanup; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c index ce94d7440f..47377a0707 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c @@ -114,9 +114,10 @@ static NV_STATUS _fbsrInitGsp params.fbsrType = pFbsr->type; params.numRegions = pFbsr->numRegions; - params.hClient = pMemoryManager->hClient; + params.hClient = pMemoryManager->hClient; params.hSysMem = hSysMem; params.gspFbAllocsSysOffset = pFbsr->gspFbAllocsSysOffset; + params.bEnteringGcoffState = pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING); // Send S/R init information to GSP NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, @@ -160,7 +161,7 @@ static NV_STATUS _fbsrMemoryCopy portMemSet(¶ms, 0, sizeof(params)); params.fbsrType = pFbsr->type; - params.hClient = pMemoryManager->hClient; + params.hClient = pMemoryManager->hClient; params.hVidMem = hVidMem; params.vidOffset = srcOffset; params.sysOffset = dstOffset; @@ -453,7 +454,7 @@ fbsrBegin_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op) if(bIommuEnabled) { - status = osSrPinSysmem(pGpu->pOsGpuInfo, + status = osSrPinSysmem(pGpu->pOsGpuInfo, pFbsr->length, &pFbsr->pagedBufferInfo.pMdl); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c index bf8f96c786..3a41486b89 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -197,7 +197,7 @@ memmgrAllocDetermineAlignment_GM107 // No offset alignment requirement for 4KB compression. // The size should be aligned to compression pagesize. // - NvU32 comprPageSize = pMemorySystemConfig->comprPageSize; + NvU64 comprPageSize = pMemorySystemConfig->comprPageSize; *pMemSize = ((*pMemSize + alignPad + comprPageSize - 1) / comprPageSize) * comprPageSize; } else @@ -644,11 +644,11 @@ memmgrGetSurfacePhysAttr_GM107 } NV_STATUS -memmgrGetBAR1InfoForClient_GM107 +memmgrGetBAR1InfoForDevice_GM107 ( OBJGPU *pGpu, MemoryManager *pMemoryManager, - NvHandle hClient, + Device *pDevice, PGETBAR1INFO bar1Info ) { @@ -658,6 +658,7 @@ memmgrGetBAR1InfoForClient_GM107 OBJVASPACE *pBar1VAS; OBJEHEAP *pVASHeap; NV_RANGE bar1VARange = NV_RANGE_EMPTY; + RsClient *pClient = RES_GET_CLIENT(pDevice); /* * For legacy vGPU and SRIOV heavy, get BAR1 information from vGPU plugin. @@ -667,11 +668,9 @@ memmgrGetBAR1InfoForClient_GM107 { NV_STATUS status = NV_OK; NV2080_CTRL_FB_GET_INFO_V2_PARAMS fbInfoParams = {0}; - RsClient *pRsClient; Subdevice *pSubdevice; - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice)); + NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); fbInfoParams.fbInfoList[0].index = NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE; fbInfoParams.fbInfoList[1].index = NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE; @@ -680,7 +679,7 @@ memmgrGetBAR1InfoForClient_GM107 fbInfoParams.fbInfoListSize = 4; - NV_RM_RPC_CONTROL(pGpu, hClient, RES_GET_HANDLE(pSubdevice), + NV_RM_RPC_CONTROL(pGpu, pClient->hClient, RES_GET_HANDLE(pSubdevice), NV2080_CTRL_CMD_FB_GET_INFO_V2, &fbInfoParams, sizeof(fbInfoParams), status); @@ -693,20 +692,32 @@ memmgrGetBAR1InfoForClient_GM107 return status; } - pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); - pVASHeap = vaspaceGetHeap(pBar1VAS); + if (!KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_RETURN(pBar1VAS != NULL, NV_ERR_INVALID_STATE); + pVASHeap = vaspaceGetHeap(pBar1VAS); - NV_ASSERT_OK_OR_RETURN(kbusGetBar1VARangeForClient(pGpu, pKernelBus, hClient, &bar1VARange)); - bar1Info->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); - bar1Info->bankSwizzleAlignment = vaspaceGetBigPageSize(pBar1VAS); + NV_ASSERT_OK_OR_RETURN(kbusGetBar1VARangeForClient(pGpu, pKernelBus, pClient->hClient, &bar1VARange)); + bar1Info->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); + bar1Info->bankSwizzleAlignment = vaspaceGetBigPageSize(pBar1VAS); - bar1Info->bar1AvailSize = 0; + bar1Info->bar1AvailSize = 0; - if (pVASHeap != NULL) + if (pVASHeap != NULL) + { + pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, &largestFreeSize, NULL, &freeSize); + bar1Info->bar1AvailSize = (NvU32)(freeSize / 1024); + bar1Info->bar1MaxContigAvailSize = (NvU32)(largestFreeSize / 1024); + } + } + else { - pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, &largestFreeSize, NULL, &freeSize); - bar1Info->bar1AvailSize = (NvU32)(freeSize / 1024); - bar1Info->bar1MaxContigAvailSize = (NvU32)(largestFreeSize / 1024); + // When coherent C2C path is enabled, BAR1 is disabled + bar1Info->bar1Size = 0; + bar1Info->bar1AvailSize = 0; + bar1Info->bar1MaxContigAvailSize = 0; + bar1Info->bankSwizzleAlignment = 0; } return NV_OK; } @@ -820,6 +831,8 @@ memmgrInitReservedMemory_GM107 } } + bMemoryProtectionEnabled = gpuIsCCFeatureEnabled(pGpu); + memmgrStateInitReservedMemory(pGpu, pMemoryManager); // Align reserved memory to 64K granularity @@ -849,6 +862,10 @@ memmgrInitReservedMemory_GM107 // Find the last region in memory which is not already reserved or // protected. RM's reserved memory will then be carved out of it below // (once the final size and address are determined). + // RM internal data like BAR2 page tables, BAR1/2 instance blocks, etc should + // always be in protected memory whenever memory protection is enabled using Hopper + // Confidential Compute. For uses outside Hopper Confidential Compute, RM internal + // data should always be in unprotected video memory. // for (i = 0; i < pMemoryManager->Ram.numFBRegions; i++) { @@ -1070,7 +1087,7 @@ _memmgrGetOptimalSysmemPageSize ( RmPhysAddr physAddr, MEMORY_DESCRIPTOR *pMemDesc, - NvU32 bigPageSize, + NvU64 bigPageSize, NvU64 sysmemPageSize ) { @@ -1233,7 +1250,7 @@ memmgrSetMemDescPageSize_GM107 } // Only update the memory descriptor if it is unset - oldPageSize = memdescGetPageSize64(pMemDesc, addressTranslation); + oldPageSize = memdescGetPageSize(pMemDesc, addressTranslation); if (0 == oldPageSize) { memdescSetPageSize(pMemDesc, addressTranslation, newPageSize); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c index 109c7ac685..19a285d4a8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c @@ -38,7 +38,7 @@ memmgrGetMaxContextSize_GM200 MemoryManager *pMemoryManager ) { - NvU64 size; + NvU64 size = 0; // // This function's original purpose was to estimate how much heap memory RM @@ -89,7 +89,8 @@ memmgrGetMaxContextSize_GM200 } else { - if (memmgrIsPmaInitialized(pMemoryManager)) + if (memmgrIsPmaEnabled(pMemoryManager) && + memmgrIsPmaSupportedOnPlatform(pMemoryManager)) { // // We need to estimate the reserved memory needs before PMA is initialized diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c index 491a1a7d23..fe7ddde364 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,6 +40,7 @@ #include "gpu/subdevice/subdevice.h" #include "vgpu/rpc.h" #include "kernel/gpu/fifo/kernel_channel.h" +#include "platform/chipset/chipset.h" #include "class/clc0b5sw.h" #include "class/cla06fsubch.h" // NVA06F_SUBCHANNEL_COPY_ENGINE @@ -64,7 +65,7 @@ static NV_STATUS _memUtilsAllocateChannel(OBJGPU *pGpu, MemoryManager *pMemoryMa NvHandle hDeviceId, NvHandle hChannelId, NvHandle hObjectError, NvHandle hObjectBuffer, OBJCHANNEL *pChannel); static NV_STATUS _memUtilsAllocCe_GM107(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJCHANNEL *pChannel, - NvHandle hClientId, NvHandle hChannelId, NvHandle hCopyObjectId); + NvHandle hClientId, NvHandle hDeviceId, NvHandle hChannelId, NvHandle hCopyObjectId); static NV_STATUS _memUtilsAllocateUserD(OBJGPU *pGpu, MemoryManager *pMemoryManager, NvHandle hClientId, NvHandle hDeviceId, OBJCHANNEL *pChannel); static NV_STATUS _memUtilsMapUserd_GM107(OBJGPU *pGpu, MemoryManager *pMemoryManager, @@ -117,13 +118,23 @@ _memUtilsAllocateReductionSema memAllocParams.attr2 = NVOS32_ATTR2_NONE; memAllocParams.flags = 0; + // + // When APM feature is enabled all RM internal sysmem allocations must + // be in unprotected memory + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // but those sysmem allocations that are not required to be accessed from + // GPU should be in protected memory. + // + NV_ASSERT_OK_OR_RETURN( pRmApi->AllocWithHandle(pRmApi, pChannel->hClient, pChannel->deviceId, pChannel->bitMapSemPhysId, NV01_MEMORY_SYSTEM, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); // allocate virtual memory for a bit map semaphore portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); @@ -141,7 +152,8 @@ _memUtilsAllocateReductionSema pChannel->deviceId, pChannel->bitMapSemVirtId, NV50_MEMORY_VIRTUAL, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); lockStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM); if(lockStatus != NV_OK) @@ -269,6 +281,14 @@ _memUtilsChannelAllocatePB_GM107 memAllocParams.flags = 0; memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // but all vidmem allocations must go to protected memory + // + NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, pRmApi->AllocWithHandle(pRmApi, @@ -276,7 +296,8 @@ _memUtilsChannelAllocatePB_GM107 hDevice, hPhysMem, hClass, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); // allocate the Virtual memory portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); @@ -295,7 +316,8 @@ _memUtilsChannelAllocatePB_GM107 hDevice, hVirtMem, NV50_MEMORY_VIRTUAL, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); // allocate the physmem for the notifier portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); @@ -307,6 +329,14 @@ _memUtilsChannelAllocatePB_GM107 memAllocParams.flags = 0; memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // but all vidmem allocations must go to protected memory + // + NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, pRmApi->AllocWithHandle(pRmApi, @@ -314,7 +344,8 @@ _memUtilsChannelAllocatePB_GM107 hDevice, pChannel->errNotifierIdPhys, hClass, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); // allocate Virtual Memory for the notifier portMemSet(&memAllocParams, 0, sizeof(memAllocParams)); @@ -333,7 +364,8 @@ _memUtilsChannelAllocatePB_GM107 hDevice, pChannel->errNotifierIdVirt, NV50_MEMORY_VIRTUAL, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); return rmStatus; } @@ -348,6 +380,8 @@ memmgrMemUtilsChannelInitialize_GM107 { NV_STATUS rmStatus; NV_STATUS lockStatus; + RsClient *pRsClient; + NvHandle hClient; NvHandle hDevice; // device handle NvHandle hPhysMem; // memory handle NvU64 size; @@ -355,15 +389,16 @@ memmgrMemUtilsChannelInitialize_GM107 NvHandle hErrNotifierVirt; NvHandle hErrNotifierPhys; NvHandle hPushBuffer; - NvHandle hClient; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - RmClient *pClient; Heap *pHeap = GPU_GET_HEAP(pGpu); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - NvU8 *pErrNotifierCpuVA = NULL; + NvU8 *pErrNotifierCpuVA = NULL; NV_ADDRESS_SPACE userdAddrSpace; NV_ADDRESS_SPACE pushBuffAddrSpace; NV_ADDRESS_SPACE gpFifoAddrSpace; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + NvU32 cacheSnoopFlag = 0 ; // // Heap alloc one chunk of memory to hold all of our alloc parameters to @@ -385,27 +420,25 @@ memmgrMemUtilsChannelInitialize_GM107 hErrNotifierPhys = pChannel->errNotifierIdPhys; hPushBuffer = pChannel->pushBufferId; - if (!pChannel->bClientAllocated) + if (pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT)) { - RsClient *pRsClient; + cacheSnoopFlag = DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE); + } + if (!pChannel->bClientAllocated) + { NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &pChannel->hClient)); + &pChannel->hClient, sizeof(pChannel->hClient))); NV_ASSERT_OK_OR_GOTO( rmStatus, - serverutilGetClientUnderLock(pChannel->hClient, &pClient), + serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pRsClient), exit_free_client); - NV_ASSERT_OK_OR_GOTO( - rmStatus, - serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient), - exit_free_client); - - pRsClient = staticCast(pClient, RsClient); + pChannel->pRsClient = pRsClient; if (IS_VIRTUAL(pGpu)) { @@ -423,8 +456,10 @@ memmgrMemUtilsChannelInitialize_GM107 exit_free_client); } } + else + pRsClient = pChannel->pRsClient; - hClient = pChannel->hClient; + hClient = pRsClient->hClient; pParams = portMemAllocNonPaged(sizeof(*pParams)); if (pParams == NULL) @@ -433,14 +468,13 @@ memmgrMemUtilsChannelInitialize_GM107 goto exit_free_client; } - NV_ASSERT_OK_OR_GOTO( - rmStatus, - serverutilGenResourceHandle(hClient, &pChannel->deviceId), - exit_free_client); - - hDevice = pChannel->deviceId; - + if (pChannel->deviceId == NV01_NULL_OBJECT) { + NV_ASSERT_OK_OR_GOTO( + rmStatus, + clientGenResourceHandle(pRsClient, &pChannel->deviceId), + exit_free_client); + NV0080_ALLOC_PARAMETERS *pNv0080 = &pParams->nv0080; portMemSet(pNv0080, 0, sizeof(*pNv0080)); @@ -451,18 +485,20 @@ memmgrMemUtilsChannelInitialize_GM107 NV_CHECK_OK_OR_GOTO( rmStatus, LEVEL_ERROR, - pRmApi->AllocWithHandle(pRmApi, hClient, hClient, hDevice, - NV01_DEVICE_0, pNv0080), + pRmApi->AllocWithHandle(pRmApi, hClient, hClient, pChannel->deviceId, + NV01_DEVICE_0, pNv0080, sizeof(*pNv0080)), exit_free_client); } - - NV_ASSERT_OK_OR_GOTO( - rmStatus, - serverutilGenResourceHandle(hClient, &pChannel->subdeviceId), - exit_free_client); + hDevice = pChannel->deviceId; // allocate a subdevice + if (pChannel->subdeviceId == NV01_NULL_OBJECT) { + NV_ASSERT_OK_OR_GOTO( + rmStatus, + clientGenResourceHandle(pRsClient, &pChannel->subdeviceId), + exit_free_client); + NV2080_ALLOC_PARAMETERS *pNv2080 = &pParams->nv2080; portMemSet(pNv2080, 0, sizeof(*pNv2080)); pNv2080->subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); @@ -470,10 +506,10 @@ memmgrMemUtilsChannelInitialize_GM107 NV_CHECK_OK_OR_GOTO( rmStatus, LEVEL_ERROR, - pRmApi->AllocWithHandle(pRmApi, hClient, hDevice, - pChannel->subdeviceId, + pRmApi->AllocWithHandle(pRmApi, hClient, hDevice, pChannel->subdeviceId, NV20_SUBDEVICE_0, - pNv2080), + pNv2080, + sizeof(*pNv2080)), exit_free_client); } @@ -484,8 +520,7 @@ memmgrMemUtilsChannelInitialize_GM107 NV_ASSERT_OK_OR_GOTO( rmStatus, - serverutilGenResourceHandle(hClient, - &pChannel->hPartitionRef), + clientGenResourceHandle(pRsClient, &pChannel->hPartitionRef), exit_free_client); portMemSet(pNvC637, 0, sizeof(*pNvC637)); @@ -497,7 +532,8 @@ memmgrMemUtilsChannelInitialize_GM107 pChannel->subdeviceId, pChannel->hPartitionRef, AMPERE_SMC_PARTITION_REF, - pNvC637), + pNvC637, + sizeof(*pNvC637)), exit_free_client); pHeap = pChannel->pKernelMIGGpuInstance->pMemoryPartitionHeap; @@ -553,7 +589,7 @@ memmgrMemUtilsChannelInitialize_GM107 if (pChannel->bUseVasForCeCopy) { NV_ASSERT_OK_OR_GOTO(rmStatus, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->hFbAlias), + clientGenResourceHandle(pRsClient, &pChannel->hFbAlias), exit_free_client); rmStatus = memmgrMemUtilsCreateMemoryAlias_HAL(pGpu, pMemoryManager, pChannel); @@ -601,7 +637,7 @@ memmgrMemUtilsChannelInitialize_GM107 rmStatus = pRmApi->AllocWithHandle(pRmApi, hClient, pChannel->deviceId, pChannel->hVASpaceId, FERMI_VASPACE_A, - pVa); + pVa, sizeof(*pVa)); } if (bAcquireLock) { @@ -617,10 +653,10 @@ memmgrMemUtilsChannelInitialize_GM107 goto exit_free_client; } - rmStatus = vaspaceGetByHandleOrDeviceDefault(pChannel->pRsClient, - pChannel->deviceId, - pChannel->hVASpaceId, - &pChannel->pVAS); + rmStatus = vaspaceGetByHandleOrDeviceDefault(pRsClient, + pChannel->deviceId, + pChannel->hVASpaceId, + &pChannel->pVAS); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -643,7 +679,7 @@ memmgrMemUtilsChannelInitialize_GM107 } NV_ASSERT_OK_OR_GOTO(rmStatus, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->hFbAliasVA), exit_free_client); + clientGenResourceHandle(pRsClient, &pChannel->hFbAliasVA), exit_free_client); } if (gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) @@ -679,11 +715,12 @@ memmgrMemUtilsChannelInitialize_GM107 pMem->hVASpace = pChannel->hVASpaceId; rmStatus = pRmApi->AllocWithHandle(pRmApi, - pChannel->hClient, - pChannel->deviceId, - pChannel->hFbAliasVA, - NV50_MEMORY_VIRTUAL, - pMem); + hClient, + pChannel->deviceId, + pChannel->hFbAliasVA, + NV50_MEMORY_VIRTUAL, + pMem, + sizeof(*pMem)); } if (bAcquireLock) @@ -707,7 +744,7 @@ memmgrMemUtilsChannelInitialize_GM107 rmStatus, LEVEL_ERROR, pRmApi->Map(pRmApi, - pChannel->hClient, + hClient, pChannel->deviceId, pChannel->hFbAliasVA, pChannel->hFbAlias, @@ -792,7 +829,7 @@ memmgrMemUtilsChannelInitialize_GM107 hPhysMem, //hMemory, 0, size, - NV04_MAP_MEMORY_FLAGS_NONE, + cacheSnoopFlag, &pChannel->pbGpuVA); // map the error notifier rmStatus = pRmApi->Map(pRmApi, hClient, hDevice, @@ -800,7 +837,7 @@ memmgrMemUtilsChannelInitialize_GM107 hErrNotifierPhys, //hMemory, 0, pChannel->channelNotifierSize, - DRF_DEF(OS46, _FLAGS, _KERNEL_MAPPING, _ENABLE), + DRF_DEF(OS46, _FLAGS, _KERNEL_MAPPING, _ENABLE) | cacheSnoopFlag, &pChannel->pbGpuNotifierVA); NV_CHECK_OK_OR_GOTO( @@ -916,7 +953,8 @@ memmgrMemUtilsCreateMemoryAlias_GM107 pChannel->deviceId, pChannel->hFbAlias, NV01_MEMORY_LOCAL_PHYSICAL, - &physMemParams); + &physMemParams, + sizeof(physMemParams)); if (status != NV_OK) { NV_CHECK_OK_FAILED(LEVEL_WARNING, "Aliasing FbListMem", status); @@ -945,16 +983,16 @@ memmgrMemUtilsScrubInitRegisterCallback NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS nv2080EventNotificationParams; NV_STATUS rmStatus; NvHandle subDeviceHandle = 0; + Subdevice *pSubDevice; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - if (NV_OK != CliGetSubDeviceHandleFromGpu(pChannel->hClient, - pGpu, - &subDeviceHandle)) + if (NV_OK != subdeviceGetByGpu(pChannel->pRsClient, pGpu, &pSubDevice)) { - NV_PRINTF(LEVEL_WARNING, "Unable to get subdevice handle.\n"); - //Allocate a sub device if we dont have it created before hand NV2080_ALLOC_PARAMETERS nv2080AllocParams; + NV_PRINTF(LEVEL_WARNING, "Unable to get subdevice handle. Allocating subdevice\n"); + + // Allocate a sub device if we dont have it created before hand portMemSet(&nv2080AllocParams, 0, sizeof(NV2080_ALLOC_PARAMETERS)); nv2080AllocParams.subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); @@ -963,12 +1001,22 @@ memmgrMemUtilsScrubInitRegisterCallback pChannel->deviceId, pChannel->subdeviceId, NV20_SUBDEVICE_0, - &nv2080AllocParams); + &nv2080AllocParams, + sizeof(nv2080AllocParams)); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Unable to allocate a subdevice.\n"); return NV_ERR_GENERIC; } + + // Set newly created subdevice's handle + subDeviceHandle = pChannel->subdeviceId; + } + else + { + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + + subDeviceHandle = RES_GET_HANDLE(pSubDevice); } // Register callback @@ -983,7 +1031,8 @@ memmgrMemUtilsScrubInitRegisterCallback subDeviceHandle, pChannel->eventId, NV01_EVENT_KERNEL_CALLBACK_EX, - &nv0005AllocParams); + &nv0005AllocParams, + sizeof(nv0005AllocParams)); if (rmStatus != NV_OK) { @@ -1088,6 +1137,7 @@ memmgrMemUtilsCopyEngineInitialize_GM107 pMemoryManager, pChannel, pChannel->hClient, + pChannel->deviceId, pChannel->channelId, pChannel->copyObjectId), exit_free); @@ -1103,7 +1153,7 @@ memmgrMemUtilsCopyEngineInitialize_GM107 NV_CHECK_OK_OR_GOTO( rmStatus, LEVEL_ERROR, - CliGetKernelChannelWithDevice(pChannel->hClient, + CliGetKernelChannelWithDevice(pChannel->pRsClient, pChannel->deviceId, pChannel->channelId, &pFifoKernelChannel), @@ -1151,6 +1201,7 @@ static NV_STATUS _memUtilsGetCe_GM107 ( OBJGPU *pGpu, NvHandle hClient, + NvHandle hDevice, KernelCE **ppKCe ) { @@ -1163,7 +1214,16 @@ static NV_STATUS _memUtilsGetCe_GM107 if (IS_MIG_IN_USE(pGpu)) { - status = kmigmgrGetGPUInstanceScrubberCe(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu), hClient, &ceInst); + RsClient *pClient; + Device *pDevice; + + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, hClient, &pClient)); + + NV_ASSERT_OK_OR_RETURN( + deviceGetByHandle(pClient, hDevice, &pDevice)); + + status = kmigmgrGetGPUInstanceScrubberCe(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu), pDevice, &ceInst); } else { @@ -1193,6 +1253,7 @@ static NV_STATUS _memUtilsAllocCe_GM107 MemoryManager *pMemoryManager, OBJCHANNEL *pChannel, NvHandle hClientId, + NvHandle hDeviceId, NvHandle hChannelId, NvHandle hCopyObjectId @@ -1204,7 +1265,7 @@ static NV_STATUS _memUtilsAllocCe_GM107 createParams.version = NVC0B5_ALLOCATION_PARAMETERS_VERSION_1; - NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, &pKCe)); + NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, hDeviceId, &pKCe)); NV_ASSERT_OR_RETURN((pKCe != NULL), NV_ERR_INVALID_STATE); createParams.engineType = NV2080_ENGINE_TYPE_COPY(pKCe->publicID); @@ -1224,9 +1285,10 @@ static NV_STATUS _memUtilsAllocCe_GM107 hChannelId, hCopyObjectId, pChannel->hTdCopyClass, - &createParams)); + &createParams, + sizeof(createParams))); - pChannel->pKCe = pKCe; + pChannel->ceId = pKCe->publicID; return NV_OK; } @@ -1303,10 +1365,19 @@ _memUtilsAllocateUserD break; } + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // but all vidmem allocations must go to protected memory + // + NV_ASSERT_OK_OR_RETURN(pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, pChannel->hUserD, userdMemClass, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); return rmStatus; } @@ -1331,7 +1402,7 @@ _memUtilsAllocateChannel KernelCE *pKCe; NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, &pKCe)); + NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, hDeviceId, &pKCe)); NV_ASSERT_OR_RETURN((pKCe != NULL), NV_ERR_INVALID_STATE); portMemSet(&channelGPFIFOAllocParams, 0, sizeof(NV_CHANNEL_ALLOC_PARAMS)); @@ -1352,8 +1423,17 @@ _memUtilsAllocateChannel KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE localCe; + RsClient *pClient; + Device *pDevice; + + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, hClientId, &pClient)); + NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClientId, &ref)); + deviceGetByHandle(pClient, hDeviceId, &pDevice)); + + NV_ASSERT_OK_OR_RETURN( + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); // Clear the Compute instance portion, if present ref = kmigmgrMakeGIReference(ref.pKernelMIGGpuInstance); NV_ASSERT_OK_OR_RETURN( @@ -1401,7 +1481,8 @@ _memUtilsAllocateChannel hDeviceId, hChannelId, hClass, - &channelGPFIFOAllocParams)); + &channelGPFIFOAllocParams, + sizeof(channelGPFIFOAllocParams))); cleanup: NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, @@ -1446,24 +1527,23 @@ memmgrMemUtilsMemSet_GM107 // if progress is checked insert the semaphore with freeToken as payload pChannel->finishPayload = freeToken; _ceChannelScheduleWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - base, ADDR_FBMEM, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + base, ADDR_FBMEM, 0, // dst parameters size, - NV_FALSE, - NV_TRUE, - NV_FALSE /*scrubbing*/); - + NV_FALSE, // blocking + NV_TRUE, // insertFinishPayload + NV_FALSE); // memcopy } else { // issue a standard async scrub blocksPushed = _ceChannelScheduleWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - base, ADDR_FBMEM, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + base, ADDR_FBMEM, 0, // dst parameters size, - NV_FALSE, - NV_FALSE, - NV_FALSE /*scrubbing*/); + NV_FALSE, // blocking + NV_FALSE, // insertFinishPayload + NV_FALSE); // memcopy } *pNumBlocks = blocksPushed; return NV_OK; @@ -1500,12 +1580,12 @@ memmgrMemUtilsMemSetBlocking_GM107 } blocksPushed = _ceChannelScheduleWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - base, ADDR_FBMEM, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + base, ADDR_FBMEM, 0, // dst parameters size, - NV_TRUE, - NV_FALSE, - NV_FALSE /*scrubbing*/); + NV_TRUE, // blocking + NV_FALSE, // insertFinishPayload + NV_FALSE); // memcopy if (blocksPushed > 0) { @@ -1523,7 +1603,7 @@ memmgrMemUtilsMemSetBlocking_GM107 if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out waiting for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore\n"); NV_PRINTF(LEVEL_ERROR, "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", @@ -1565,10 +1645,10 @@ memmgrMemUtilsMemSetBatched_GM107 NvU32 blocksPushed = 0; blocksPushed = _ceChannelScheduleBatchWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - base, ADDR_FBMEM, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + base, ADDR_FBMEM, 0, // dst parameters size, - NV_FALSE); /*scrubbing*/ + NV_FALSE); // memcopy if (blocksPushed > 0) { @@ -1586,7 +1666,7 @@ memmgrMemUtilsMemSetBatched_GM107 if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out waiting for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore!\n"); NV_PRINTF(LEVEL_ERROR, "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", @@ -1641,9 +1721,10 @@ memmgrMemUtilsMemCopyBatched_GM107 ) { NvU32 blocksPushed = _ceChannelScheduleBatchWork_GM107(pGpu, pMemoryManager, pChannel, - src, srcAddressSpace, srcCpuCacheAttrib, /*src parameters*/ - dst, dstAddressSpace, dstCpuCacheAttrib, /*dst parameters*/ - size, NV_TRUE /*memcpy*/); + src, srcAddressSpace, srcCpuCacheAttrib, // src parameters + dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters + size, + NV_TRUE); // memcopy; if (blocksPushed > 0) { @@ -1672,7 +1753,7 @@ memmgrMemUtilsMemCopyBatched_GM107 if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out waiting for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore\n"); NV_PRINTF(LEVEL_ERROR, "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", @@ -1774,7 +1855,8 @@ memmgrMemUtilsAllocateEccAllocScrubber_GM107 pEccSyncChannel->deviceId, pEccSyncChannel->bitMapSemVirtId, NV50_MEMORY_VIRTUAL, - &memAllocParams)); + &memAllocParams, + sizeof(memAllocParams))); lockStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM); @@ -1880,8 +1962,8 @@ _ceChannelScheduleBatchWork_GM107 ptr = (NvU32 *)(pChannel->pbCpuVA + pChannel->channelPutOffset); bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, - src, srcAddressSpace, srcCpuCacheAttrib, /*src parameters*/ - dst, dstAddressSpace, dstCpuCacheAttrib, /*dst parameters*/ + src, srcAddressSpace, srcCpuCacheAttrib, // src parameters + dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters size, &ptr, NV_FALSE, NV_FALSE, NV_FALSE, bMemcopy); pChannel->finishPayload += NvU64_LO32(size); NV_ASSERT(NvU64_HI32(size) == 0); @@ -1901,8 +1983,8 @@ _ceChannelScheduleBatchWork_GM107 ptr = (NvU32 *)(pChannel->pbCpuVA + pChannel->channelPutOffset); bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, /*src parameters*/ - 0, 0, 0, /*dst parameters*/ + 0, 0, 0, // src parameters + 0, 0, 0, // dst parameters 0, &ptr, NV_FALSE, NV_FALSE, NV_TRUE, bMemcopy); NV_ASSERT(bytesPushed != 0); @@ -2025,8 +2107,8 @@ _ceChannelScheduleWork_GM107 if(_checkSynchronization(pGpu, pMemoryManager, pChannel, BLOCK_INDEX_FROM_ADDR(dst, pChannel->blockShift))) { bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, - src, srcAddressSpace, srcCpuCacheAttrib, /*src parameters*/ - dst, dstAddressSpace, dstCpuCacheAttrib, /*dst parameters*/ + src, srcAddressSpace, srcCpuCacheAttrib, // src parameters + dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters blockSize, &ptr, NV_TRUE, (addNonStallIntr && !blocking), addFinishPayload, bMemcopy); spaceInPb = spaceInPb - bytesPushed; @@ -2218,7 +2300,7 @@ _ceChannelUpdateGpFifo_GM107 else { workSubmitToken = pChannel->workSubmitToken; - NV_ASSERT_OR_RETURN_VOID(CliGetKernelChannelWithDevice(pChannel->hClient, + NV_ASSERT_OR_RETURN_VOID(CliGetKernelChannelWithDevice(pChannel->pRsClient, pChannel->deviceId, pChannel->channelId, &pFifoKernelChannel) == NV_OK); } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c index 7092657621..ad9da9d0f8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c @@ -322,7 +322,7 @@ dmaAllocMapping_GM107 addressTranslation = VAS_ADDRESS_TRANSLATION(pVAS); // In SRIOV-heavy plugin may map subheap allocations for itself using BAR1 - NV_ASSERT_OK_OR_RETURN(vgpuIsCallingContextPlugin(pGpu, &bCallingContextPlugin)); + NV_ASSERT_OK_OR_GOTO(status, vgpuIsCallingContextPlugin(pGpu, &bCallingContextPlugin), cleanup); if (bCallingContextPlugin) addressTranslation = FORCE_VMMU_TRANSLATION(pMemDesc, addressTranslation); @@ -338,22 +338,22 @@ dmaAllocMapping_GM107 // Get pageSize pLocals->pTempMemDesc = memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu); - + // Get physical allocation granularity and page size. pLocals->pageArrayGranularity = pLocals->pTempMemDesc->pageArrayGranularity; - pLocals->physPageSize = memdescGetPageSize64(pLocals->pTempMemDesc, addressTranslation); - + pLocals->physPageSize = memdescGetPageSize(pLocals->pTempMemDesc, addressTranslation); + // retrieve mapping page size from flags switch(DRF_VAL(OS46, _FLAGS, _PAGE_SIZE, flags)) { case NVOS46_FLAGS_PAGE_SIZE_DEFAULT: case NVOS46_FLAGS_PAGE_SIZE_BOTH: - pLocals->pageSize = memdescGetPageSize64(pLocals->pTempMemDesc, addressTranslation); + pLocals->pageSize = memdescGetPageSize(pLocals->pTempMemDesc, addressTranslation); break; case NVOS46_FLAGS_PAGE_SIZE_4KB: pLocals->pageSize = RM_PAGE_SIZE; break; - case NVOS46_FLAGS_PAGE_SIZE_BIG: + case NVOS46_FLAGS_PAGE_SIZE_BIG: // case for arch specific 128K pLocals->pageSize = pLocals->vaspaceBigPageSize; break; @@ -362,7 +362,8 @@ dmaAllocMapping_GM107 break; default: NV_PRINTF(LEVEL_ERROR, "Unknown page size flag encountered during mapping\n"); - return NV_ERR_INVALID_ARGUMENT; + status = NV_ERR_INVALID_ARGUMENT; + goto cleanup; } NV_PRINTF(LEVEL_INFO, "Picked Page size based on flags: 0x%llx flagVal: 0x%x\n", @@ -391,7 +392,7 @@ dmaAllocMapping_GM107 if (kgmmuIsVaspaceInteropSupported(pKernelGmmu) && pLocals->bIsBar1) { - if ((pLocals->pageSize > pLocals->vaspaceBigPageSize) && + if ((pLocals->pageSize > pLocals->vaspaceBigPageSize) && kbusIsBar1Force64KBMappingEnabled(pKernelBus)) { pLocals->pageSize = pLocals->vaspaceBigPageSize; @@ -670,7 +671,8 @@ dmaAllocMapping_GM107 if ((pLocals->vaRangeLo >= pGVAS->vaStartInternal && pLocals->vaRangeLo <= pGVAS->vaLimitInternal) || (pLocals->vaRangeHi <= pGVAS->vaLimitInternal && pLocals->vaRangeHi >= pGVAS->vaStartInternal)) { - return NV_ERR_INVALID_PARAMETER; + status = NV_ERR_INVALID_PARAMETER; + goto cleanup; } } } @@ -708,11 +710,11 @@ dmaAllocMapping_GM107 goto cleanup; } - // + // // Bug 3610538 clients can allocate GPU VA, during mapping for ctx dma. - // But if clients enable RM to map internal buffers in a reserved - // range of VA for unlinked SLI in Linux, we want to tag these - // allocations as "client allocated", so that it comes outside of + // But if clients enable RM to map internal buffers in a reserved + // range of VA for unlinked SLI in Linux, we want to tag these + // allocations as "client allocated", so that it comes outside of // RM internal region. // if (gvaspaceIsInternalVaRestricted(pGVAS)) @@ -937,13 +939,23 @@ dmaAllocMapping_GM107 if (pPeerGpu != NULL) { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); - - if ((pKernelNvlink != NULL) && - knvlinkIsNvlinkP2pSupported(pMappingGpu, pKernelNvlink, pPeerGpu)) + if (IS_VIRTUAL_WITH_SRIOV(pMappingGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pMappingGpu)) + { + pLocals->peerNumber = kbusGetNvlinkPeerId_HAL(pMappingGpu, + GPU_GET_KERNEL_BUS(pMappingGpu), + pPeerGpu); + } + else { - pLocals->peerNumber = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), - pPeerGpu); + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); + + if ((pKernelNvlink != NULL) && + knvlinkIsNvlinkP2pSupported(pMappingGpu, pKernelNvlink, pPeerGpu)) + { + pLocals->peerNumber = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), + pPeerGpu); + } } } else @@ -959,6 +971,32 @@ dmaAllocMapping_GM107 SLI_LOOP_BREAK; } } + else if ((memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_EGM)) + { + NV_ASSERT(memdescGetFlag(pLocals->pTempMemDesc, MEMDESC_FLAGS_ALLOC_FROM_EGM)); + + pLocals->aperture = NV_MMU_PTE_APERTURE_PEER_MEMORY; + + if (pLocals->p2p) + { + OBJGPU *pMappingGpu = pGpu; + OBJGPU *pPeerGpu; + + NV_ASSERT_OR_ELSE(pLocals->pMemory != NULL, status = NV_ERR_INVALID_STATE; goto cleanup); + + pPeerGpu = pLocals->pMemory->pGpu; + pLocals->peerNumber = kbusGetEgmPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); + } + else + { + // + // Make sure that we receive a mapping request for EGM memory + // only if local EGM is enabled. + // + NV_ASSERT_OR_ELSE(pMemoryManager->bLocalEgmEnabled, status = NV_ERR_INVALID_STATE; goto cleanup); + pLocals->peerNumber = pMemoryManager->localEgmPeerId; + } + } else { // No P2P for system memory @@ -1145,7 +1183,7 @@ dmaFreeMapping_GM107 SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) // ensure the page size has been set before continuing - NV_ASSERT(memdescGetPageSize64(memdescGetMemDescFromGpu(pMemDesc, pGpu), VAS_ADDRESS_TRANSLATION(pVAS)) != 0); + NV_ASSERT(memdescGetPageSize(memdescGetMemDescFromGpu(pMemDesc, pGpu), VAS_ADDRESS_TRANSLATION(pVAS)) != 0); SLI_LOOP_END if (pCliMapInfo) @@ -1362,39 +1400,37 @@ _gmmuWalkCBMapNextEntries_Direct MMU_MAP_ITERATOR *pIter = pTarget->pIter; NvU8 *pMap = pIter->pMap; const NvU64 pageSize = mmuFmtLevelPageSize(pLevelFmt); - NvU32 bufferAdjust = 0; GMMU_ENTRY_VALUE entry; - NV_ASSERT_OR_RETURN_VOID(NULL != pMap); + NV_ASSERT_OR_RETURN_VOID(pMap != NULL); - if (NULL == pLevelMem) - { - // - // Calculate buffer adjustment to account for entryIndexLo in - // buffered mode. - // RM writes the user-supplied buffer starting at offset 0 - // even if the it is in middle of the page table. - // - bufferAdjust = entryIndexLo * pLevelFmt->entrySize; - } + // + // This function will always write the caller supplied buffer + // at offset 0. The onus of writing the buffer out to the target + // location in memory at the appropriate offset is on the caller. + // for (i = entryIndexLo; i <= entryIndexHi; ++i) { + NvU32 entryOffset = (i - entryIndexLo) * pLevelFmt->entrySize; + // Copy out current PTE if we are overwriting (Read-Modify-Write) if (pIter->bReadPtes) { - portMemCopy(entry.v8, pLevelFmt->entrySize, pMap + (i * pLevelFmt->entrySize), pLevelFmt->entrySize); + portMemCopy(entry.v8, pLevelFmt->entrySize, + &pMap[entryOffset], pLevelFmt->entrySize); } else { // Copy the static fields passed in, if we aren't overwriting a subset of fields. - portMemCopy(entry.v8, pLevelFmt->entrySize, pIter->pteTemplate, pLevelFmt->entrySize); + portMemCopy(entry.v8, pLevelFmt->entrySize, + pIter->pteTemplate, pLevelFmt->entrySize); } if (pIter->bApplyWarForBug2720120) { // Commit to memory. - portMemCopy(pMap + (i * pLevelFmt->entrySize) - bufferAdjust, pLevelFmt->entrySize, + portMemCopy(&pMap[entryOffset], pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); continue; } @@ -1536,7 +1572,7 @@ _gmmuWalkCBMapNextEntries_Direct } // Commit to memory. - portMemCopy(pMap + (i * pLevelFmt->entrySize) - bufferAdjust, pLevelFmt->entrySize, + portMemCopy(&pMap[entryOffset], pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); // @@ -1562,22 +1598,35 @@ _gmmuWalkCBMapNextEntries_RmAperture NvU32 *pProgress ) { - OBJGPU *pGpu = pUserCtx->pGpu; - MMU_MAP_ITERATOR *pIter = pTarget->pIter; - MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR*)pLevelMem; + OBJGPU *pGpu = pUserCtx->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + MMU_MAP_ITERATOR *pIter = pTarget->pIter; + MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR*)pLevelMem; + const MMU_FMT_LEVEL *pLevelFmt = pTarget->pLevelFmt; + TRANSFER_SURFACE surf = {0}; + NvU32 sizeOfEntries; NV_PRINTF(LEVEL_INFO, "[GPU%u]: PA 0x%llX, Entries 0x%X-0x%X\n", pUserCtx->pGpu->gpuInstance, memdescGetPhysAddr(pMemDesc, AT_GPU, 0), entryIndexLo, entryIndexHi); - pIter->pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); + surf.pMemDesc = pMemDesc; + surf.offset = entryIndexLo * pLevelFmt->entrySize; + + sizeOfEntries = (entryIndexHi - entryIndexLo + 1 ) * pLevelFmt->entrySize; + + pIter->pMap = memmgrMemBeginTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); NV_ASSERT_OR_RETURN_VOID(NULL != pIter->pMap); _gmmuWalkCBMapNextEntries_Direct(pUserCtx, pTarget, pLevelMem, entryIndexLo, entryIndexHi, pProgress); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pIter->pMap, NV_TRUE); + memmgrMemEndTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); } static NV_STATUS _dmaGetFabricAddress @@ -1659,9 +1708,10 @@ dmaUpdateVASpace_GF100 NvU32 priv; NvU32 writeDisable; NvU32 readDisable; - NvU32 vaSpaceBigPageSize = 0; + NvU64 vaSpaceBigPageSize = 0; + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); NvU32 alignSize = pMemorySystemConfig->comprPageSize; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); NvBool bFillPteMem = !!(flags & DMA_UPDATE_VASPACE_FLAGS_FILL_PTE_MEM); @@ -1875,6 +1925,13 @@ dmaUpdateVASpace_GF100 vaLo, vaHi)); } + if (kmemsysNeedInvalidateGpuCacheOnMap_HAL(pGpu, pKernelMemorySystem, isVolatile, aperture)) + { + kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, pMemDesc, + (aperture == NV_MMU_PTE_APERTURE_PEER_MEMORY) ? FB_CACHE_PEER_MEMORY : FB_CACHE_SYSTEM_MEMORY, + FB_CACHE_EVICT); + } + // Build PTE template if (pFmt->version == GMMU_FMT_VERSION_3) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c index 6fb047f662..42556840cf 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c @@ -585,3 +585,64 @@ memmgrGetMaxContextSize_TU102 return size; } + + +/*! + * Calculates heap offset based on presence and size of console and CBC regions + * + * When GSP is in use, CBC is placed at the beginning of memory instead of the + * end, which means it must be taken into account when calculating where the + * heap starts. If the offset is successfully calculated, it is placed in the + * offset variable and NV_OK is returned + * + * @returns NV_STATUS + */ +NV_STATUS +memmgrCalculateHeapOffsetWithGSP_TU102 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU32 *offset +) +{ + // The heap will be located after the Console and CBC regions if they are + // present. Zero, one, or both of them may be present. If Console and + // CBC regions are present, they are guaranteed to be in Regions 0 and 1. + // If only one is present, then it is guaranteed to be in Region 0. As an + // extra check, it should be validated that these regions are indeed + // reserved + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + FB_REGION_DESCRIPTOR *pFbRegion0 = &pMemoryManager->Ram.fbRegion[0]; + FB_REGION_DESCRIPTOR *pFbRegion1 = &pMemoryManager->Ram.fbRegion[1]; + + NvBool isConsoleRegionPresent = pMemoryManager->Ram.ReservedConsoleDispMemSize != 0; + NvBool isCbcRegionPresent = !pKernelMemorySystem->pStaticConfig->bDisableCompbitBacking; + + // Both regions in use + if (isCbcRegionPresent && isConsoleRegionPresent && + pFbRegion0->bRsvdRegion && pFbRegion1->bRsvdRegion) + { + // Use Region 1 limit and safely convert to KB + *offset = NvU64_LO32((pFbRegion1->limit + 1) >> 10); + NV_ASSERT_OR_RETURN(((NvU64) *offset << 10ULL) == (pFbRegion1->limit + 1), + NV_ERR_INVALID_DATA); + } + + // One region in use + else if ((isCbcRegionPresent || isConsoleRegionPresent) && + pFbRegion0->bRsvdRegion) + { + // Use Region 0 limit and safely convert to KB + *offset = NvU64_LO32((pFbRegion0->limit + 1) >> 10); + NV_ASSERT_OR_RETURN(((NvU64) *offset << 10ULL) == (pFbRegion0->limit + 1), + NV_ERR_INVALID_DATA); + } + + // Neither region in use, return NOT_SUPPORTED to fall back to default calculation + else + { + return NV_ERR_NOT_SUPPORTED; + } + + return NV_OK; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c index f96ac8448f..d8cd9564c1 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c @@ -50,7 +50,8 @@ memmgrScrubMapDoorbellRegion_GV100 pChannel->subdeviceId, pChannel->doorbellRegionHandle, VOLTA_USERMODE_A, - NULL); + NULL, + 0); if (status != NV_OK) goto exit; @@ -115,8 +116,8 @@ memmgrGetMaxContextSize_GV100 } else { - // TODO: Remove the PMA check after enabling on all chips. - if (memmgrIsPmaInitialized(pMemoryManager)) + if (memmgrIsPmaEnabled(pMemoryManager) && + memmgrIsPmaSupportedOnPlatform(pMemoryManager)) { // // Increase the context size by 120 MB. diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c new file mode 100644 index 0000000000..d4b524be79 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c @@ -0,0 +1,759 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "core/core.h" +#include "gpu/ce/kernel_ce.h" +#include "gpu/bus/kern_bus.h" +#include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/mem_mgr/channel_utils.h" +#include "rmapi/rs_utils.h" +#include "utils/nvassert.h" +#include "core/prelude.h" +#include "core/locks.h" +#include "gpu/mem_mgr/ce_utils.h" +#include "gpu/subdevice/subdevice.h" +#include "kernel/gpu/mem_mgr/ce_utils_sizes.h" + +#include "class/clb0b5.h" // MAXWELL_DMA_COPY_A +#include "class/clc0b5.h" // PASCAL_DMA_COPY_A +#include "class/clc1b5.h" // PASCAL_DMA_COPY_B +#include "class/clc3b5.h" // VOLTA_DMA_COPY_A +#include "class/clc5b5.h" // TURING_DMA_COPY_A +#include "class/clc8b5.h" // HOPPER_DMA_COPY_A +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A + +#include "class/cl0080.h" + +NV_STATUS +ceutilsConstruct_IMPL +( + CeUtils *pCeUtils, + OBJGPU *pGpu, + NV0050_ALLOCATION_PARAMETERS *pParams +) +{ + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_INVALID_STATE); + return ceutilsInitialize(pCeUtils, pGpu, pParams); +} + + +// This is used by internal callsites without resource server +NV_STATUS +ceutilsInitialize +( + CeUtils *pCeUtils, + OBJGPU *pGpu, + NV0050_ALLOCATION_PARAMETERS *pAllocParams +) +{ + NV_STATUS status = NV_OK; + NvU64 allocFlags = pAllocParams->flags; + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_INVALID_STATE); + + NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + // Allocate channel with RM internal client + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RmClient *pClient; + + OBJCHANNEL *pChannel = (OBJCHANNEL *) portMemAllocNonPaged(sizeof(OBJCHANNEL)); + if (pChannel == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + portMemSet(pChannel, 0, sizeof(OBJCHANNEL)); + + if (pCeUtils->hClient == NV01_NULL_OBJECT) + { + // Allocate client + status = pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, + NV01_NULL_OBJECT, NV01_ROOT, &pCeUtils->hClient, + sizeof(pCeUtils->hClient)); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + } + + pChannel->hClient = pCeUtils->hClient; + pClient = serverutilGetClientUnderLock(pChannel->hClient); + NV_ASSERT_OR_GOTO(pClient != NULL, free_client); + + status = serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient); + NV_ASSERT_OR_GOTO(status == NV_OK, free_client); + + status = clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U); + NV_ASSERT_OR_GOTO(status == NV_OK, free_client); + + pChannel->bClientAllocated = NV_TRUE; + pChannel->pGpu = pGpu; + + pChannel->deviceId = pCeUtils->hDevice; + pChannel->subdeviceId = pCeUtils->hSubdevice; + + // We'll allocate new VAS for now. Sharing client VAS will be added later + pChannel->hVASpaceId = NV01_NULL_OBJECT; + pChannel->bUseVasForCeCopy = FLD_TEST_DRF(0050_CEUTILS, _FLAGS, _VIRTUAL_MODE, _TRUE, allocFlags); + + // Detect if we can enable fast scrub on this channel + status = memmgrMemUtilsGetCopyEngineClass_HAL(pGpu, pMemoryManager, &pCeUtils->hTdCopyClass); + NV_ASSERT_OR_GOTO(status == NV_OK, free_channel); + + if (((pCeUtils->hTdCopyClass == HOPPER_DMA_COPY_A) + ) && !pChannel->bUseVasForCeCopy) + { + pChannel->type = FAST_SCRUBBER_CHANNEL; + NV_PRINTF(LEVEL_INFO, "Enabled fast scrubber in construct.\n"); + } + + // Set up various channel resources + status = channelSetupIDs(pChannel, pGpu, pChannel->bUseVasForCeCopy, bMIGInUse); + NV_ASSERT_OR_GOTO(status == NV_OK, free_client); + + channelSetupChannelBufferSizes(pChannel); + + if (pCeUtils->pKernelMIGGPUInstance != NULL) + { + pChannel->pKernelMIGGpuInstance = pCeUtils->pKernelMIGGPUInstance; + } + + status = memmgrMemUtilsChannelInitialize_HAL(pGpu, pMemoryManager, pChannel); + NV_ASSERT_OR_GOTO(status == NV_OK, free_channel); + + NV_PRINTF(LEVEL_INFO, "Channel alloc successful for ceUtils\n"); + pCeUtils->pChannel = pChannel; + + // Allocate CE states + status = memmgrMemUtilsCopyEngineInitialize_HAL(pGpu, pMemoryManager, pChannel); + NV_ASSERT_OR_GOTO(status == NV_OK, free_channel); + + pCeUtils->pGpu = pGpu; + + return status; + +free_channel: + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); + + if (pAllocParams->hVaspace != NV01_NULL_OBJECT) + { + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hVASpaceId); + } +free_client: + if (FLD_TEST_DRF(0050_CEUTILS, _FLAGS, _EXTERNAL, _FALSE, allocFlags)) + { + // If client allocated client, we should not free it in RM + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); + } + +cleanup: + portMemFree(pChannel); + return status; +} + +void +ceutilsDeinit +( + CeUtils *pCeUtils +) +{ + OBJCHANNEL *pChannel = pCeUtils->pChannel; + OBJGPU *pGpu = pCeUtils->pGpu; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + // Sanity checks + if ((pGpu == NULL) || (pChannel == NULL)) + { + NV_PRINTF(LEVEL_WARNING, "Possible double-free of CeUtils!\n"); + return; + } + else if (pGpu != pChannel->pGpu) + { + NV_PRINTF(LEVEL_ERROR, "Bad state during ceUtils teardown!\n"); + return; + } + + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->errNotifierIdPhys); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->pushBufferId); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->errNotifierIdVirt); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hVASpaceId); + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->deviceId); + + // Resource server makes sure no leak can occur + pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); + portMemFree(pChannel); +} + +void +ceutilsDestruct_IMPL +( + CeUtils *pCeUtils +) +{ + ceutilsDeinit(pCeUtils); +} + +void +ceutilsServiceInterrupts(CeUtils *pCeUtils) +{ + OBJCHANNEL *pChannel = pCeUtils->pChannel; + + // + // FIXME: Bug 2463959: objmemscrub is called with the rmDeviceGpuLock in the + // heapFree_IMPL->_stdmemPmaFree->pmaFreePages->scrubSubmitPages path. + // Yielding while holding the rmDeviceGpuLock can lead to deadlock. Instead, + // if the lock is held, service any interrupts on the owned CE to make progress. + // Bug 2527660 is filed to remove this change. + // + // pChannel is null when PMA scrub requests are handled in vGPU plugin. + // In this case vGpu plugin allocates scrubber channel in PF domain so + // above mention deadlock is not present here. + // + if ((pChannel != NULL) && (rmDeviceGpuLockIsOwner(pChannel->pGpu->gpuInstance))) + { + Intr *pIntr = GPU_GET_INTR(pChannel->pGpu); + intrServiceStallSingle_HAL(pChannel->pGpu, pIntr, MC_ENGINE_IDX_CE(pChannel->ceId), NV_FALSE); + } + else + { + osSchedule(); + } +} + + +static NvBool +_ceUtilsFastScrubEnabled +( + POBJCHANNEL pChannel, + CHANNEL_PB_INFO *pChannelPbInfo +) +{ + OBJGPU *pGpu = pChannel->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + if (!memmgrIsFastScrubberEnabled(pMemoryManager)) + { + return NV_FALSE; + } + + // + // Enable the memory fast scrubbing only when + // Channel was allocated as fastScrub channel + // We are doing a memset operation + // Memset pattern is 0 + // DstPhysMode.target == LOCAL_FB + // Address is 4KB aligned + // LineLength is 4KB aligned + // + + return ((pChannel->type == FAST_SCRUBBER_CHANNEL) && + (!pChannelPbInfo->bCeMemcopy) && + (pChannelPbInfo->pattern == 0) && + (pChannelPbInfo->dstAddressSpace == ADDR_FBMEM) && + (NV_IS_ALIGNED64(pChannelPbInfo->dstAddr, MEMUTIL_SCRUB_OFFSET_ALIGNMENT)) && + (NV_IS_ALIGNED(pChannelPbInfo->size, MEMUTIL_SCRUB_LINE_LENGTH_ALIGNMENT))); +} + + +// +// Helper to deal with CE_MAX_BYTES_PER_LINE +// This function may modify some fileds in pChannelPbInfo +// +static NV_STATUS +_ceutilsSubmitPushBuffer +( + POBJCHANNEL pChannel, + NvU64 opLength, + CHANNEL_PB_INFO * pChannelPbInfo + +) +{ + NV_STATUS status = NV_OK; + NvBool bFirstIteration = NV_TRUE; + NvBool bInsertFinishPayload = NV_FALSE; + NvU32 methodsLength, tempSize, putIndex = 0; + NvU64 remainingLength = opLength; + + NV_ASSERT_OR_RETURN(pChannelPbInfo != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(opLength != 0, NV_ERR_INVALID_ARGUMENT); + + do + { + tempSize = (NvU32)NV_MIN(remainingLength, CE_MAX_BYTES_PER_LINE); + pChannelPbInfo->size = tempSize; + bInsertFinishPayload = (remainingLength == tempSize); + NV_PRINTF(LEVEL_INFO, "Actual size of copying to be pushed: %x \n", tempSize); + + status = channelWaitForFreeEntry(pChannel, &putIndex); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot get putIndex.\n"); + return status; + } + + if (_ceUtilsFastScrubEnabled(pChannel, pChannelPbInfo)) + { + methodsLength = channelFillPbFastScrub(pChannel, putIndex, bFirstIteration, bInsertFinishPayload, pChannelPbInfo); + } + else + { + methodsLength = channelFillPb(pChannel, putIndex, bFirstIteration, bInsertFinishPayload, pChannelPbInfo); + } + if (methodsLength == 0) + { + NV_PRINTF(LEVEL_ERROR, "Cannot push methods to channel.\n"); + return NV_ERR_NO_FREE_FIFOS; + } + + status = channelFillGpFifo(pChannel, putIndex, methodsLength); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Channel operation failures during memcopy\n"); + return status; + } + + pChannel->lastSubmittedEntry = putIndex; + remainingLength -= tempSize; + + pChannelPbInfo->dstAddr += tempSize; + pChannelPbInfo->srcAddr += tempSize; + + bFirstIteration = NV_FALSE; + } while (remainingLength > 0); + + return status; +} + + +NV_STATUS +ceutilsMemset_IMPL +( + CeUtils *pCeUtils, + CEUTILS_MEMSET_PARAMS *pParams +) +{ + OBJCHANNEL *pChannel = pCeUtils->pChannel; + NV_STATUS status = NV_OK; + + NvU32 pteArraySize; + NvU64 offset, memsetLength, size, pageGranularity; + NvBool bContiguous; + + MEMORY_DESCRIPTOR *pMemDesc = pParams->pMemDesc; + CHANNEL_PB_INFO channelPbInfo = {0}; + + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memdesc for CeUtils memset.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((memdescGetAddressSpace(pMemDesc) != ADDR_FBMEM) || + (pMemDesc->pGpu != pCeUtils->pChannel->pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memory descriptor passed.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + size = memdescGetSize(pMemDesc); + pteArraySize = memdescGetPteArraySize(pMemDesc, AT_GPU); + bContiguous = (pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) || (pteArraySize == 1); + + if (pParams->offset >= size) + { + NV_PRINTF(LEVEL_ERROR, "Invalid offset passed for the memdesc.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + NV_PRINTF(LEVEL_INFO, "CeUtils Args to memset - offset: %llx, size: %llx \n", + pParams->offset, pParams->length); + + if ((pParams->length == 0) || (pParams->length > (size - pParams->offset))) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memset length passed.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + channelPbInfo.bCeMemcopy = NV_FALSE; + channelPbInfo.payload = pCeUtils->lastSubmittedPayload + 1; + pCeUtils->lastSubmittedPayload = channelPbInfo.payload; + + channelPbInfo.pattern = pParams->pattern; + channelPbInfo.dstAddressSpace = memdescGetAddressSpace(pMemDesc); + channelPbInfo.dstCpuCacheAttrib = pMemDesc->_cpuCacheAttrib; + + pageGranularity = pMemDesc->pageArrayGranularity; + memsetLength = pParams->length; + offset = pParams->offset; + + do + { + NvU64 maxContigSize = bContiguous ? memsetLength : (pageGranularity - offset % pageGranularity); + NvU64 memsetSizeContig = NV_MIN(memsetLength, maxContigSize); + + channelPbInfo.dstAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, offset); + + NV_PRINTF(LEVEL_INFO, "CeUtils Memset dstAddr: %llx, size: %llx\n", + channelPbInfo.dstAddr, memsetSizeContig); + + status = _ceutilsSubmitPushBuffer(pChannel, memsetSizeContig, &channelPbInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot submit push buffer for memset.\n"); + return status; + } + + memsetLength -= memsetSizeContig; + offset += memsetSizeContig; + } while (memsetLength != 0); + + if (pParams->flags & NV0050_CTRL_MEMSET_FLAGS_ASYNC) + { + NV_PRINTF(LEVEL_INFO, "Async memset payload returned: 0x%x\n", channelPbInfo.payload); + pParams->submittedWorkId = channelPbInfo.payload; + } + else + { + // Check semaProgress and then timeout + status = channelWaitForFinishPayload(pChannel, channelPbInfo.payload); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Work was done from RM PoV lastSubmitted = 0x%x\n", channelPbInfo.payload); + } + } + + return status; +} + +NV_STATUS +ceutilsMemcopy_IMPL +( + CeUtils *pCeUtils, + CEUTILS_MEMCOPY_PARAMS *pParams +) +{ + OBJCHANNEL *pChannel = pCeUtils->pChannel; + NV_STATUS status = NV_OK; + + NvU64 srcSize, dstSize, copyLength, srcPageGranularity, dstPageGranularity; + NvBool bSrcContig, bDstContig; + + CHANNEL_PB_INFO channelPbInfo = {0}; + MEMORY_DESCRIPTOR *pDstMemDesc = pParams->pDstMemDesc; + MEMORY_DESCRIPTOR *pSrcMemDesc = pParams->pSrcMemDesc; + + NvU64 length = pParams->length; + NvU64 srcOffset = pParams->srcOffset; + NvU64 dstOffset = pParams->dstOffset; + + // Validate params + if ((pSrcMemDesc == NULL) || (pDstMemDesc == NULL)) + { + NV_PRINTF(LEVEL_ERROR, "Src/Dst Memory descriptor should be valid.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((memdescGetAddressSpace(pSrcMemDesc) != ADDR_FBMEM) && + (memdescGetAddressSpace(pDstMemDesc) != ADDR_FBMEM)) + { + NV_PRINTF(LEVEL_ERROR, "Either Dst or Src memory should be in vidmem.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((pSrcMemDesc->pGpu != pCeUtils->pChannel->pGpu) || + (pDstMemDesc->pGpu != pCeUtils->pChannel->pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "CeUtils does not support p2p copies right now. \n"); + return NV_ERR_INVALID_ARGUMENT; + } + + srcSize = memdescGetSize(pSrcMemDesc); + dstSize = memdescGetSize(pDstMemDesc); + + if ((srcOffset >= srcSize) || (dstOffset >= dstSize)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid offset passed for the src/dst memdesc.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((length == 0) || + (srcOffset + length > srcSize) || (dstOffset + length > dstSize)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid memcopy length.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + channelPbInfo.bCeMemcopy = NV_TRUE; + channelPbInfo.payload = pCeUtils->lastSubmittedPayload + 1; + pCeUtils->lastSubmittedPayload = channelPbInfo.payload; + + channelPbInfo.srcAddressSpace = memdescGetAddressSpace(pSrcMemDesc); + channelPbInfo.dstAddressSpace = memdescGetAddressSpace(pDstMemDesc); + + channelPbInfo.srcCpuCacheAttrib = pSrcMemDesc->_cpuCacheAttrib; + channelPbInfo.dstCpuCacheAttrib = pDstMemDesc->_cpuCacheAttrib; + + srcPageGranularity = pSrcMemDesc->pageArrayGranularity; + dstPageGranularity = pDstMemDesc->pageArrayGranularity; + bSrcContig = memdescGetContiguity(pSrcMemDesc, AT_GPU); + bDstContig = memdescGetContiguity(pDstMemDesc, AT_GPU); + + copyLength = length; + + do + { + // + // This algorithm finds the maximum contig region from both src and dst + // for each copy and iterate until we submitted the whole range to CE + // + NvU64 maxContigSizeSrc = bSrcContig ? copyLength : (srcPageGranularity - srcOffset % srcPageGranularity); + NvU64 maxContigSizeDst = bDstContig ? copyLength : (dstPageGranularity - dstOffset % dstPageGranularity); + NvU64 copySizeContig = NV_MIN(copyLength, NV_MIN(maxContigSizeSrc, maxContigSizeDst)); + + channelPbInfo.srcAddr = memdescGetPhysAddr(pSrcMemDesc, AT_GPU, srcOffset); + channelPbInfo.dstAddr = memdescGetPhysAddr(pDstMemDesc, AT_GPU, dstOffset); + + NV_PRINTF(LEVEL_INFO, "CeUtils Memcopy dstAddr: %llx, srcAddr: %llx, size: %llx\n", + channelPbInfo.dstAddr, channelPbInfo.srcAddr, copySizeContig); + + status = _ceutilsSubmitPushBuffer(pChannel, copySizeContig, &channelPbInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot submit push buffer for memcopy.\n"); + return status; + } + + copyLength -= copySizeContig; + srcOffset += copySizeContig; + dstOffset += copySizeContig; + } while (copyLength != 0); + + if (pParams->flags & NV0050_CTRL_MEMSET_FLAGS_ASYNC) + { + NV_PRINTF(LEVEL_INFO, "Async memset payload returned: 0x%x\n", channelPbInfo.payload); + pParams->submittedWorkId = channelPbInfo.payload; + } + else + { + // Check semaProgress and then timeout + status = channelWaitForFinishPayload(pChannel, channelPbInfo.payload); + if (status == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Work was done from RM PoV lastSubmitted = 0x%x\n", channelPbInfo.payload); + } + } + + return status; +} + + +// This function updates pCeUtils->lastCompletedPayload and handles wrap-around +NvU64 +ceutilsUpdateProgress_IMPL +( + CeUtils *pCeUtils +) +{ + NV_ASSERT((pCeUtils != NULL) && (pCeUtils->pChannel != NULL)); + + NvU32 hwCurrentCompletedPayload = 0; + NvU64 swLastCompletedPayload = pCeUtils->lastCompletedPayload; + + // + // CeUtils uses 64 bit index to track the work submitted. But HW supports + // only 32 bit semaphore. The current completed Id is calculated here, based + // on the lastSubmittedPayload and current HW semaphore value. + // + hwCurrentCompletedPayload = READ_CHANNEL_PAYLOAD_SEMA(pCeUtils->pChannel); + + // No work has been completed since we checked last time + if (hwCurrentCompletedPayload == (NvU32)swLastCompletedPayload) + { + return swLastCompletedPayload; + } + + // Check for wrap around case. Increment the upper 32 bits + if (hwCurrentCompletedPayload < (NvU32)swLastCompletedPayload) + { + swLastCompletedPayload += 0x100000000ULL; + } + + // Update lower 32 bits regardless if wrap-around happened + swLastCompletedPayload &= 0xFFFFFFFF00000000ULL; + swLastCompletedPayload |= (NvU64)hwCurrentCompletedPayload; + + pCeUtils->lastCompletedPayload = swLastCompletedPayload; + return swLastCompletedPayload; +} + + +void +ceutilsRegisterGPUInstance +( + CeUtils *pCeUtils, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance +) +{ + pCeUtils->pKernelMIGGPUInstance = pKernelMIGGPUInstance; +} + +#if defined(DEBUG) || defined (DEVELOP) +NV_STATUS +ceutilsapiCtrlCmdCheckProgress_IMPL +( + CeUtilsApi *pCeUtilsApi, + NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams +) +{ + if (pParams->submittedWorkId <= ceutilsUpdateProgress(pCeUtilsApi->pCeUtils)) + { + pParams->result = NV0050_CTRL_CHECK_PROGRESS_RESULT_FINISHED; + } + + return NV_OK; +} + +NV_STATUS +ceutilsapiConstruct_IMPL +( + CeUtilsApi *pCeUtilsApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV0050_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; + + if (FLD_TEST_DRF(0050_CEUTILS, _FLAGS, _EXTERNAL, _TRUE, pAllocParams->flags)) + { + NV_PRINTF(LEVEL_ERROR, "CeUtils: unsupported flags = 0x%llx\n", pAllocParams->flags); + return NV_ERR_NOT_SUPPORTED; + } + + return objCreate(&pCeUtilsApi->pCeUtils, pCeUtilsApi, CeUtils, GPU_RES_GET_GPU(pCeUtilsApi), pAllocParams); +} + +void +ceutilsapiDestruct_IMPL +( + CeUtilsApi *pCeUtilsApi +) +{ + objDelete(pCeUtilsApi->pCeUtils); +} + +NV_STATUS +ceutilsapiCtrlCmdMemset_IMPL +( + CeUtilsApi *pCeUtilsApi, + NV0050_CTRL_MEMSET_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pCeUtilsApi); + RsResourceRef *pPhysmemRef; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + CEUTILS_MEMSET_PARAMS internalParams = {0}; + + if (pParams->hMemory == 0) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = serverutilGetResourceRef(hClient, pParams->hMemory, &pPhysmemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get resource in resource server for physical memory handle.\n"); + return status; + } + pMemDesc = (dynamicCast(pPhysmemRef->pResource, Memory))->pMemDesc; + + internalParams.pMemDesc = pMemDesc; + internalParams.offset = pParams->offset; + internalParams.length = pParams->length; + internalParams.pattern = pParams->pattern; + internalParams.flags = pParams->flags; + + status = ceutilsMemset(pCeUtilsApi->pCeUtils, &internalParams); + if (status == NV_OK) + { + pParams->submittedWorkId = internalParams.submittedWorkId; + } + + return status; +} + +NV_STATUS +ceutilsapiCtrlCmdMemcopy_IMPL +( + CeUtilsApi *pCeUtilsApi, + NV0050_CTRL_MEMCOPY_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pCeUtilsApi); + RsResourceRef *pSrcPhysmemRef; + RsResourceRef *pDstPhysmemRef; + MEMORY_DESCRIPTOR *pSrcMemDesc = NULL; + MEMORY_DESCRIPTOR *pDstMemDesc = NULL; + CEUTILS_MEMCOPY_PARAMS internalParams = {0}; + + if ((pParams->hSrcMemory == 0) || (pParams->hDstMemory == 0)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = serverutilGetResourceRef(hClient, pParams->hDstMemory, &pDstPhysmemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get resource in resource server for physical memory handle.\n"); + return status; + } + pDstMemDesc = (dynamicCast(pDstPhysmemRef->pResource, Memory))->pMemDesc; + + status = serverutilGetResourceRef(hClient, pParams->hSrcMemory, &pSrcPhysmemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get resource in resource server for physical memory handle.\n"); + return status; + } + pSrcMemDesc = (dynamicCast(pSrcPhysmemRef->pResource, Memory))->pMemDesc; + + internalParams.pSrcMemDesc = pSrcMemDesc; + internalParams.pDstMemDesc = pDstMemDesc; + internalParams.srcOffset = pParams->srcOffset; + internalParams.dstOffset = pParams->dstOffset; + internalParams.length = pParams->length; + internalParams.flags = pParams->flags; + + status = ceutilsMemcopy(pCeUtilsApi->pCeUtils, &internalParams); + if (status == NV_OK) + { + pParams->submittedWorkId = internalParams.submittedWorkId; + } + + return status; +} +#endif // defined(DEBUG) || defined (DEVELOP) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c new file mode 100644 index 0000000000..0b221f7a21 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c @@ -0,0 +1,637 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "utils/nvassert.h" +#include "core/locks.h" + +#include "kernel/gpu/mem_mgr/ce_utils_sizes.h" +#include "kernel/gpu/mem_mgr/channel_utils.h" + + +/* Static helper functions */ +static void channelPushAddress(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, NvU32 **ppPtr); +static NvU32 channelPushMemoryProperties(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, NvU32 **ppPtr); +static void channelPushMethod(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, + NvBool bPipelined, NvBool bInsertFinishPayload, + NvU32 launchType, NvU32 semaValue, NvU32 **ppPtr); + +/* Public APIs */ +NV_STATUS +channelSetupIDs +( + OBJCHANNEL *pChannel, + OBJGPU *pGpu, + NvBool bUseVasForCeCopy, + NvBool bMIGInUse +) +{ + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->physMemId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->channelId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->errNotifierIdVirt)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->errNotifierIdPhys)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->copyObjectId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->eventId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->pushBufferId)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->doorbellRegionHandle)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->hUserD)); + + // For physical CE channels, we will use RM internal VAS to map channel buffers + NV_ASSERT(pChannel->hVASpaceId == NV01_NULL_OBJECT); + + if (bUseVasForCeCopy || (IS_GSP_CLIENT(pGpu) && bMIGInUse)) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGenResourceHandle(pChannel->hClient, &pChannel->hVASpaceId)); + } + + return NV_OK; +} + +void +channelSetupChannelBufferSizes +( + OBJCHANNEL *pChannel +) +{ + NV_ASSERT_OR_RETURN_VOID(pChannel != NULL); + NV_ASSERT_OR_RETURN_VOID(pChannel->type < MAX_CHANNEL_TYPE); + + pChannel->channelNotifierSize = CE_CHANNEL_NOTIFIER_SIZE; + pChannel->channelNumGpFifioEntries = CE_NUM_COPY_BLOCKS; + pChannel->methodSizePerBlock = CE_METHOD_SIZE_PER_BLOCK; + + if (pChannel->type == FAST_SCRUBBER_CHANNEL) + { + pChannel->methodSizePerBlock = FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK; + } + + // These sizes depend on size of each block of pushbuffer methods + pChannel->channelPbSize = pChannel->methodSizePerBlock * CE_NUM_COPY_BLOCKS; + pChannel->channelSize = pChannel->channelPbSize + CE_GPFIFO_SIZE + CE_CHANNEL_SEMAPHORE_SIZE; + pChannel->semaOffset = pChannel->channelPbSize + CE_GPFIFO_SIZE; + pChannel->finishPayloadOffset = pChannel->semaOffset + 4; +} + +NV_STATUS +channelWaitForFinishPayload +( + OBJCHANNEL *pChannel, + NvU64 targetPayload +) +{ + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INVALID_STATE); + + OBJGPU *pGpu = pChannel->pGpu; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + while (1) + { + if (READ_CHANNEL_PAYLOAD_SEMA(pChannel) >= targetPayload) + { + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + break; + } + + if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + { + Intr *pIntr = GPU_GET_INTR(pGpu); + intrServiceStallSingle_HAL(pGpu, pIntr, MC_ENGINE_IDX_CE(pChannel->ceId), NV_FALSE); + } + else + { + osSchedule(); + } + } + + return status; +} + + +/** helper function which waits for a PB & GPFIO entry to be read by HOST. + * After the HOST reads GPFIFO and PB entry, the semaphore will be released. + */ +NV_STATUS +channelWaitForFreeEntry +( + OBJCHANNEL *pChannel, + NvU32 *pPutIndex +) +{ + NV_ASSERT_OR_RETURN(pChannel != NULL, NV_ERR_INVALID_STATE); + + OBJGPU *pGpu = pChannel->pGpu; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + + NvU32 putIndex = 0; + NvU32 getIndex = 0; + + putIndex = (pChannel->lastSubmittedEntry + 1) % pChannel->channelNumGpFifioEntries; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + do + { + getIndex = READ_CHANNEL_PB_SEMA(pChannel); + + NV_PRINTF(LEVEL_INFO, "Get Index: %x, PayloadIndex: %x\n", getIndex, + READ_CHANNEL_PAYLOAD_SEMA(pChannel)); + + if (getIndex != putIndex) + { + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + break; + } + + if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + { + Intr *pIntr = GPU_GET_INTR(pGpu); + intrServiceStallSingle_HAL(pGpu, pIntr, MC_ENGINE_IDX_CE(pChannel->ceId), NV_FALSE); + } + else + { + osSchedule(); + } + } while(1); + + if (status == NV_OK) + { + NV_ASSERT_OR_RETURN(pPutIndex != NULL, NV_ERR_INVALID_STATE); + *pPutIndex = putIndex; + } + + return status; +} + + +/** helper function to fill GPFIFO entry with a pushbuffer segment. and kick + * off the executiion by HOST. + */ +NV_STATUS +channelFillGpFifo +( + OBJCHANNEL *pChannel, + NvU32 putIndex, + NvU32 methodsLength +) +{ + NvU32 *pGpEntry; + NvU32 GpEntry0; + NvU32 GpEntry1; + NvU64 pbPutOffset; + OBJGPU *pGpu; + KernelBus *pKernelBus; + + NV_ASSERT(putIndex < pChannel->channelNumGpFifioEntries); + + pbPutOffset = (pChannel->pbGpuVA + (putIndex * pChannel->methodSizePerBlock)); + + GpEntry0 = DRF_DEF(906F, _GP_ENTRY0, _NO_CONTEXT_SWITCH, _FALSE) | + DRF_NUM(906F, _GP_ENTRY0, _GET, NvU64_LO32(pbPutOffset) >> 2); + + GpEntry1 = DRF_NUM(906F, _GP_ENTRY1, _GET_HI, NvU64_HI32(pbPutOffset)) | + DRF_NUM(906F, _GP_ENTRY1, _LENGTH, methodsLength >> 2) | + DRF_DEF(906F, _GP_ENTRY1, _LEVEL, _MAIN); + + pGpEntry = (NvU32 *)(((NvU8 *)pChannel->pbCpuVA) + pChannel->channelPbSize + + (pChannel->lastSubmittedEntry * NV906F_GP_ENTRY__SIZE)); + + MEM_WR32(&pGpEntry[0], GpEntry0); + MEM_WR32(&pGpEntry[1], GpEntry1); + + // need to flush WRC buffer + osFlushCpuWriteCombineBuffer(); + + // write GP put + MEM_WR32(&pChannel->pControlGPFifo->GPPut, putIndex); + osFlushCpuWriteCombineBuffer(); + + // + // On some architectures, if doorbell is mapped via bar0, we need to send + // an extra flush + // + pGpu = pChannel->pGpu; + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + if (kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Busflush failed in _scrubFillGpFifo\n"); + return NV_ERR_GENERIC; + } + + // + // removing the FIFO Lite Mode handling + // Refer older _ceChannelUpdateGpFifo_GF100 code for implementation + // + if (pChannel->bUseDoorbellRegister) + { + // Use the token from notifier memory for VM migration support. + MEM_WR32(pChannel->pDoorbellRegisterOffset, + MEM_RD32(&(pChannel->pTokenFromNotifier->info32))); + } + + return NV_OK; +} + +NvU32 +channelFillPbFastScrub +( + OBJCHANNEL *pChannel, + NvU32 putIndex, + NvBool bPipelined, + NvBool bInsertFinishPayload, + CHANNEL_PB_INFO *pChannelPbInfo +) +{ + NvU32 pipelinedValue = 0; + NvU32 *pPtr = (NvU32 *)((NvU8*)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); + NvU32 *pStartPtr = pPtr; + NvU32 semaValue = 0; + NvU32 data = 0; + NvU64 pSemaAddr = 0; + + NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, + putIndex * pChannel->methodSizePerBlock); + + // SET OBJECT + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SET_OBJECT, pChannel->classEngineID); + + // Set Pattern for Memset + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_A, pChannelPbInfo->pattern); + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_B, pChannelPbInfo->pattern); + + // Set Component Size to 1 + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_COMPONENTS, + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_B) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | + DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_DST_PHYS_MODE, + DRF_DEF(C8B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB)); + + semaValue = (bInsertFinishPayload) ? + DRF_DEF(C8B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE) : 0; + + if (bPipelined) + pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); + else + pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); + + NV_PUSH_INC_2U(RM_SUBCHANNEL, NVC8B5_OFFSET_OUT_UPPER, + DRF_NUM(C8B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(pChannelPbInfo->dstAddr)), + NVC8B5_OFFSET_OUT_LOWER, + DRF_NUM(C8B5, _OFFSET_OUT_LOWER, _VALUE,NvU64_LO32(pChannelPbInfo->dstAddr))); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LINE_LENGTH_IN, pChannelPbInfo->size); + + if (semaValue) + { + NV_PUSH_INC_3U(RM_SUBCHANNEL, NVC8B5_SET_SEMAPHORE_A, + DRF_NUM(C8B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), + NVC8B5_SET_SEMAPHORE_B, + DRF_NUM(C8B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), + NVC8B5_SET_SEMAPHORE_PAYLOAD, + pChannelPbInfo->payload); + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_MEMORY_SCRUB_PARAMETERS, + DRF_DEF(C8B5, _SET_MEMORY_SCRUB_PARAMETERS, _DISCARDABLE, _FALSE)); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LAUNCH_DMA, + DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(C8B5, _LAUNCH_DMA, _REMAP_ENABLE, _FALSE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _MEMORY_SCRUB_ENABLE, _TRUE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE) | + DRF_DEF(C8B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | + DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL) | + pipelinedValue | + semaValue); + + // + // This should always be at the bottom the push buffer segment, since this + // denotes that HOST has read all the methods needed for this memory operation + // and safely assume that this GPFIFO and PB entry can be reused. + // + data = DRF_DEF(C86F, _SEM_EXECUTE, _OPERATION, _RELEASE) | + DRF_DEF(C86F, _SEM_EXECUTE, _PAYLOAD_SIZE, _32BIT) | + DRF_DEF(C86F, _SEM_EXECUTE, _RELEASE_WFI, _DIS); + + pSemaAddr = (pChannel->pbGpuVA+pChannel->semaOffset); + + NV_PUSH_INC_4U(RM_SUBCHANNEL, NVC86F_SEM_ADDR_LO, + DRF_NUM(C86F, _SEM_ADDR_LO, _OFFSET, NvU64_LO32(pSemaAddr) >> 2), + NVC86F_SEM_ADDR_HI, + DRF_NUM(C86F, _SEM_ADDR_HI, _OFFSET, NvU64_HI32(pSemaAddr)), + NVC86F_SEM_PAYLOAD_LO, putIndex, + NVC86F_SEM_PAYLOAD_HI, 0); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SEM_EXECUTE, data); + + NvU32 methodSize = (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); + NV_ASSERT_OR_RETURN(methodSize <= pChannel->methodSizePerBlock, 0); + return methodSize; +} + +/** single helper function to fill the push buffer with the methods needed for + * memsetting using CE. This function is much more efficient in the sense it + * decouples the mem(set/copy) operation from managing channel resources. + **/ + +NvU32 +channelFillPb +( + OBJCHANNEL *pChannel, + NvU32 putIndex, + NvBool bPipelined, + NvBool bInsertFinishPayload, + CHANNEL_PB_INFO *pChannelPbInfo +) +{ + NvU32 launchType = 0; + NvU32 *pPtr = (NvU32 *)((NvU8 *)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); + NvU32 *pStartPtr = pPtr; + NvU32 semaValue = 0; + NvU32 data = 0; + NvU64 pSemaAddr = 0; + + NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, putIndex * pChannel->methodSizePerBlock); + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NV906F_SET_OBJECT, pChannel->classEngineID); + + // Side effect - pushed target aperture and REMAP method for memset + launchType = channelPushMemoryProperties(pChannel, pChannelPbInfo, &pPtr); + + // Side effect - pushed addresses + channelPushAddress(pChannel, pChannelPbInfo, &pPtr); + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LINE_LENGTH_IN, pChannelPbInfo->size); + + if (bInsertFinishPayload) + { + semaValue = DRF_DEF(B0B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE); + + // Do not support client semaphore for now + NV_ASSERT(pChannelPbInfo->clientSemaAddr == 0); + + NV_PUSH_INC_3U(RM_SUBCHANNEL, NVB0B5_SET_SEMAPHORE_A, + DRF_NUM(B0B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), + NVB0B5_SET_SEMAPHORE_B, + DRF_NUM(B0B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), + NVB0B5_SET_SEMAPHORE_PAYLOAD, + pChannelPbInfo->payload); + } + + // Side effect - pushed LAUNCH_DMA methods + channelPushMethod(pChannel, pChannelPbInfo, bPipelined, bInsertFinishPayload, launchType, semaValue, &pPtr); + + // Release HOST semaphore after work is completed by CE + data = DRF_DEF(906F, _SEMAPHORED, _OPERATION, _RELEASE) | + DRF_DEF(906F, _SEMAPHORED, _RELEASE_SIZE, _4BYTE) | + DRF_DEF(906F, _SEMAPHORED, _RELEASE_WFI, _DIS); + + pSemaAddr = (pChannel->pbGpuVA + pChannel->semaOffset); + + // + // This should always be at the bottom the push buffer segment, since this + // denotes that HOST has read all the methods needed for this memory operation + // and safely assume that this GPFIFO and PB entry can be reused. + // + NV_PUSH_INC_4U(RM_SUBCHANNEL, NV906F_SEMAPHOREA, + DRF_NUM(906F, _SEMAPHOREA_OFFSET, _UPPER, NvU64_HI32(pSemaAddr)), + NV906F_SEMAPHOREB, + DRF_NUM(906F, _SEMAPHOREB_OFFSET, _LOWER, NvU64_LO32(pSemaAddr) >> 2), + NV906F_SEMAPHOREC, + putIndex, + NV906F_SEMAPHORED, + data); + + NvU32 methodSize = (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); + NV_ASSERT_OR_RETURN(methodSize <= pChannel->methodSizePerBlock, 0); + return methodSize; +} + + +/*** Implementation for static methods ***/ +static NvU32 +channelPushMemoryProperties +( + OBJCHANNEL *pChannel, + CHANNEL_PB_INFO *pChannelPbInfo, + NvU32 **ppPtr +) +{ + NV_ADDRESS_SPACE dstAddressSpace = pChannelPbInfo->dstAddressSpace; + NV_ADDRESS_SPACE srcAddressSpace = pChannelPbInfo->srcAddressSpace; + NvU32 dstCpuCacheAttrib = pChannelPbInfo->dstCpuCacheAttrib; + NvU32 srcCpuCacheAttrib = pChannelPbInfo->srcCpuCacheAttrib; + + NvU32 data = 0; + NvU32 retVal = 0; + NvU32 *pPtr = *ppPtr; + + if (!pChannelPbInfo->bCeMemcopy) + { + // If memset, push remap components + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_REMAP_CONST_A, pChannelPbInfo->pattern); + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_REMAP_COMPONENTS, + DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | + DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | + DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); + } + else + { + // If memcopy, push src addr properties + if (srcAddressSpace == ADDR_FBMEM) + { + data = DRF_DEF(B0B5, _SET_SRC_PHYS_MODE, _TARGET, _LOCAL_FB); + } + else if (srcCpuCacheAttrib == NV_MEMORY_CACHED) + { + data = DRF_DEF(B0B5, _SET_SRC_PHYS_MODE, _TARGET, _COHERENT_SYSMEM); + } + else + { + data = DRF_DEF(B0B5, _SET_SRC_PHYS_MODE, _TARGET, _NONCOHERENT_SYSMEM); + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_SRC_PHYS_MODE, data); + } + + // Push dst addr properties + if (dstAddressSpace == ADDR_FBMEM) + { + data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB); + } + else if (dstCpuCacheAttrib == NV_MEMORY_CACHED) + { + data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _COHERENT_SYSMEM); + } + else + { + data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _NONCOHERENT_SYSMEM); + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_DST_PHYS_MODE, data); + + if (pChannel->bUseVasForCeCopy) + { + retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _VIRTUAL) | + DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _VIRTUAL); + } + else + { + retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | + DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL); + } + + *ppPtr = pPtr; + return retVal; +} + + +static void +channelPushAddress +( + OBJCHANNEL *pChannel, + CHANNEL_PB_INFO *pChannelPbInfo, + NvU32 **ppPtr +) +{ + NvU64 dstAddr = pChannelPbInfo->dstAddr; + NvU64 srcAddr = pChannelPbInfo->srcAddr; + NvU32 *pPtr = *ppPtr; + + // Linear translation to map the PA to VA + if (pChannel->bUseVasForCeCopy) + { + dstAddr = dstAddr + pChannel->fbAliasVA - pChannel->startFbOffset; + srcAddr = srcAddr + pChannel->fbAliasVA - pChannel->startFbOffset; + } + + // Set dst addr + NV_PUSH_INC_2U(RM_SUBCHANNEL, NVB0B5_OFFSET_OUT_UPPER, + DRF_NUM(B0B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(dstAddr)), + NVB0B5_OFFSET_OUT_LOWER, + DRF_NUM(B0B5, _OFFSET_OUT_LOWER, _VALUE, NvU64_LO32(dstAddr))); + + // Set src addr if memcopy + if (pChannelPbInfo->bCeMemcopy) + { + NV_PUSH_INC_2U(RM_SUBCHANNEL, NVB0B5_OFFSET_IN_UPPER, + DRF_NUM(B0B5, _OFFSET_IN_UPPER, _UPPER, NvU64_HI32(srcAddr)), + NVB0B5_OFFSET_IN_LOWER, + DRF_NUM(B0B5, _OFFSET_IN_LOWER, _VALUE, NvU64_LO32(srcAddr))); + } + + *ppPtr = pPtr; +} + + +static void +channelPushMethod +( + OBJCHANNEL *pChannel, + CHANNEL_PB_INFO *pChannelPbInfo, + NvBool bPipelined, + NvBool bInsertFinishPayload, + NvU32 launchType, + NvU32 semaValue, + NvU32 **ppPtr +) +{ + NvU32 pipelinedValue = 0; + NvU32 disablePlcKind = 0; + NvU32 launchParams = 0; + NvU32 *pPtr = *ppPtr; + + if (bPipelined) + { + pipelinedValue = DRF_DEF(B0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); + } + else + { + pipelinedValue = DRF_DEF(B0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); + } + + if (!pChannelPbInfo->bCeMemcopy) + { + switch (pChannel->hTdCopyClass) + { + case MAXWELL_DMA_COPY_A: + case PASCAL_DMA_COPY_A: + case PASCAL_DMA_COPY_B: + case VOLTA_DMA_COPY_A: + disablePlcKind = 0; + break; + default: // For anything after Turing, set the kind + disablePlcKind = DRF_DEF(C5B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE); + break; + } + + launchParams = DRF_DEF(B0B5, _LAUNCH_DMA, _REMAP_ENABLE, _TRUE) | disablePlcKind; + } + + NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LAUNCH_DMA, + launchParams | + DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(B0B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(B0B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | + DRF_DEF(B0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE) | + launchType | + pipelinedValue | + semaValue); + *ppPtr = pPtr; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c b/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c index 01dde98f94..22334d09a9 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -83,7 +83,16 @@ _ctxdmaDestroyFBMappings // if (pCpuMapping) { - osUnmapPciMemoryKernelOld(pGpu, pContextDma->KernelVAddr[gpuSubDevInst]); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + if(pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, pContextDma->pMemDesc); + } + else + { + osUnmapPciMemoryKernelOld(pGpu, pContextDma->KernelVAddr[gpuSubDevInst]); + } refRemoveMapping(pMemoryRef, pCpuMapping); /// @@ -96,7 +105,6 @@ _ctxdmaDestroyFBMappings if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu) && (pContextDma->FbApertureLen[gpuSubDevInst] != 0)) { - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); kbusUnmapFbAperture_HAL(pGpu, pKernelBus, pContextDma->pMemDesc, pContextDma->FbAperture[gpuSubDevInst], pContextDma->FbApertureLen[gpuSubDevInst], @@ -194,18 +202,18 @@ ctxdmaConstruct_IMPL pContextDma->Type = type; pContextDma->Limit = limit; - for (i = 0; i < NV_ARRAY_ELEMENTS32(pContextDma->KernelVAddr); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pContextDma->KernelVAddr); i++) pContextDma->KernelVAddr[i] = NULL; pContextDma->KernelPriv = NULL; - for (i = 0; i < NV_ARRAY_ELEMENTS32(pContextDma->FbAperture); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pContextDma->FbAperture); i++) { pContextDma->FbAperture[i] = (NvU64)-1; pContextDma->FbApertureLen[i] = 0; } - for (i = 0; i < NV_ARRAY_ELEMENTS32(pContextDma->Instance); i++) + for (i = 0; i < NV_ARRAY_ELEMENTS(pContextDma->Instance); i++) { pContextDma->Instance[i] = 0; pContextDma->InstRefCount[i] = 0; @@ -577,13 +585,27 @@ _ctxdmaConstruct pContextDma->FbAperture[gpuSubDevInst] - pGpu->busInfo.gpuPhysFbAddr; } } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + NvP64 pMap = kbusMapCoherentCpuMapping_HAL(pGpu, pKernelBus, pMemDesc); + if (pMap == NULL) + { + rmStatus = NV_ERR_GENERIC; + } + else + { + rmStatus = NV_OK; + pMap = NvP64_PLUS_OFFSET(pMap, offset); + } + pContextDma->KernelVAddr[gpuSubDevInst] = pMap; + } else { rmStatus = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, offset, &pContextDma->FbAperture[gpuSubDevInst], &pContextDma->FbApertureLen[gpuSubDevInst], - BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient); + BUS_MAP_FB_FLAGS_MAP_UNICAST, pDevice); } if (rmStatus != NV_OK) { @@ -644,7 +666,7 @@ _ctxdmaConstruct // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), // do an RPC to the host to do the hardware update. // - NV_RM_RPC_ALLOC_CONTEXT_DMA(pGpu, hClient, hDevice, RES_GET_HANDLE(pContextDma), hClass, + NV_RM_RPC_ALLOC_CONTEXT_DMA(pGpu, hClient, hDevice, RES_GET_HANDLE(pContextDma), hClass, flags, RES_GET_HANDLE(pMemory), offset, limit, rmStatus); } } @@ -751,33 +773,6 @@ ctxdmaGetKernelVA_IMPL return NV_OK; } -// **************************************************************************** -// Deprecated Functions -// **************************************************************************** - -/** - * @warning This function is deprecated! Please use ctxdmaGetByHandle. - */ -NV_STATUS -CliGetContextDma -( - NvHandle hClient, - NvHandle hContextDma, - ContextDma **ppContextDma -) -{ - RsClient *pClient; - NV_STATUS status; - - *ppContextDma = NULL; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return NV_ERR_INVALID_CLIENT; - - return ctxdmaGetByHandle(pClient, hContextDma, ppContextDma); -} - NV_STATUS ctxdmaMapTo_IMPL ( @@ -791,7 +786,7 @@ ctxdmaMapTo_IMPL // // For video memory, provide a way to look up the offset of an FB allocation within - // the given context target context dma. still useful for dFPGA. + // the given context target context dma. still useful for dFPGA. // It is used by mods. // if ((memdescGetAddressSpace(memdescGetMemDescFromGpu(pSrcMemDesc, pGpu)) == ADDR_FBMEM) && diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/dma.c b/src/nvidia/src/kernel/gpu/mem_mgr/dma.c index 0b67bf81c3..dc6188a5b6 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/dma.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/dma.c @@ -690,7 +690,7 @@ deviceCtrlCmdDmaFlush_IMPL if (FLD_TEST_DRF(0080, _CTRL_DMA_FLUSH_TARGET_UNIT, _FB, _ENABLE, flushParams->targetUnit)) { - status = kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); + status = kbusSendSysmembar(pGpu, pKernelBus); } return status; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c index bd7f611283..b3a6bc55dd 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c @@ -557,12 +557,12 @@ NV_STATUS heapInitInternal_IMPL } } - // + // // Define PMA-managed regions // This will be moved to memmgr once we refactor SMC partitions // - if (memmgrIsPmaEnabled(pMemoryManager) && - memmgrIsPmaSupportedOnPlatform(pMemoryManager) && + if (memmgrIsPmaEnabled(pMemoryManager) && + memmgrIsPmaSupportedOnPlatform(pMemoryManager) && (heapType != HEAP_TYPE_PARTITION_LOCAL)) { memmgrSetPmaInitialized(pMemoryManager, NV_TRUE); @@ -657,6 +657,7 @@ NV_STATUS heapInitInternal_IMPL MEMORY_DESCRIPTOR *pMemDesc = NULL; NvBool bProtected = NV_FALSE; + bProtected = gpuIsCCFeatureEnabled(pGpu); status = heapReserveRegion( pMemoryManager, pHeap, @@ -2751,7 +2752,7 @@ NV_STATUS heapAllocHint_IMPL NvU8 currentBankInfo = 0; FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvU32 flags; NvU32 owner; NvU32 tiledAttr; @@ -2898,7 +2899,7 @@ NV_STATUS heapAllocHint_IMPL if (pAllocHint->flags & NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE) { OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU32 hostPageSize = pSys->cpuInfo.hostPageSize; + NvU64 hostPageSize = pSys->cpuInfo.hostPageSize; // hostPageSize *should* always be set, but.... if (hostPageSize == 0) @@ -3064,7 +3065,7 @@ NV_STATUS heapHwAlloc_IMPL // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), // do an RPC to the host to do the hardware update. // - if ((status == NV_OK) && (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu))) + if ((status == NV_OK) && IS_VIRTUAL(pGpu)) { { NV_RM_RPC_MANAGE_HW_RESOURCE_ALLOC(pGpu, @@ -3212,7 +3213,7 @@ void heapHwFree_IMPL // do an RPC to the host to do the hardware update. // - if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) + if (IS_VIRTUAL(pGpu)) { { NV_STATUS rmStatus = NV_OK; @@ -3225,8 +3226,7 @@ void heapHwFree_IMPL rmStatus); } } - - if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu)) + else { memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c index 6b6d5a89c0..b0594e4e6c 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c @@ -71,12 +71,18 @@ memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL if (pParams->hSubDevice) { + Subdevice *pSubDevice; + // Alloc operation in unicast mode - NvHandle hDevice; - if ((status = CliSetSubDeviceContext(pRmCtrlParams->hClient, pParams->hSubDevice, &hDevice, &pGpu)) != NV_OK) - { + status = subdeviceGetByHandle(pCallContext->pClient, + pParams->hSubDevice, &pSubDevice); + + if (status != NV_OK) return status; - } + + pGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); } status = memmgrGetSurfacePhysAttr_HAL(pGpu, GPU_GET_MEMORY_MANAGER(pGpu), pMemory, @@ -134,7 +140,7 @@ memCtrlCmdGetSurfaceInfoLvm_IMPL // gets allocated only when ATTR is set to COMPR_REQUIRED // if ((pMemory->pHwResource != NULL) && - pMemory->pHwResource->attr & + pMemory->pHwResource->attr & DRF_DEF(OS32, _ATTR, _COMPR, _REQUIRED)) { zero = 0; @@ -326,7 +332,7 @@ memCtrlCmdGetMemPageSize_IMPL { OBJGPU *pGpu = pMemory->pGpu; PMEMORY_DESCRIPTOR pTempMemDesc = NULL; - NvU32 tempPageSize = 0; + NvU64 tempPageSize = 0; SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { @@ -396,6 +402,6 @@ memCtrlCmdGetTag_IMPL ) { pParams->tag = pMemory->tag; - + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c index 4fe7194929..f957ad2079 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c @@ -789,6 +789,67 @@ _memdescAllocInternal } break; + case ADDR_EGM: + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU64 i; + + + NV_ASSERT_OK_OR_GOTO(status, osAllocPages(pMemDesc), done); + + pMemDesc->Allocated = NV_TRUE; + + // + // EGM address in the GMMU PTE should be zero base address and so + // the EGM base address is subtracted from the allocated EGM + // address. HSHUB later adds the socket local EGM base system physical address(SPA) + // before sending the transaction to TH500. zero-base address is + // required in passthrough virtualization where guest physical address + // is programmed in the GMMU PTE and the SPA is available only in + // the HSHUB registers. + // + // zero-base address is possible only when the EGM base address is + // available. There are platforms(like off-DUT MODS and dGPU MODS) + // where this is not available and full address is populated in + // the GMMU PTE itself and HSHUB is not programmed to add the SPA. + // + if (pMemoryManager->localEgmBasePhysAddr != 0) + { + for (i = 0; i < memdescGetPteArraySize(pMemDesc, AT_GPU); i++) + { + RmPhysAddr addr = memdescGetPhysAddr(pMemDesc, AT_GPU, i * pMemDesc->pageArrayGranularity); + NV_ASSERT_TRUE_OR_GOTO(status, addr > pMemoryManager->localEgmBasePhysAddr, + NV_ERR_INVALID_STATE, done); + memdescSetPte(pMemDesc, AT_GPU, i, addr - pMemoryManager->localEgmBasePhysAddr); + NV_PRINTF(LEVEL_INFO, "EGM allocation. pte index: %lld addr: 0x%llx zero-base addr: 0x%llx\n", + i, addr, addr - pMemoryManager->localEgmBasePhysAddr); + } + } + + if ((pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) && + RMCFG_FEATURE_PLATFORM_MODS) + { + if (pMemDesc->Alignment > RM_PAGE_SIZE) + { + RmPhysAddr addr = memdescGetPhysAddr(pMemDesc, AT_CPU, 0); + NvU64 offset; + + NV_ASSERT((addr & (RM_PAGE_SIZE - 1)) == 0); + + NV_ASSERT((pMemDesc->Alignment & (pMemDesc->Alignment - 1)) == 0); + offset = addr & (pMemDesc->Alignment - 1); + + if (offset) + { + NV_ASSERT((pMemDesc->PageCount * pMemDesc->pageArrayGranularity - pMemDesc->Size) >= offset); + NV_ASSERT(pMemDesc->PteAdjust == 0); + pMemDesc->PteAdjust += NvU64_LO32(pMemDesc->Alignment - offset); + } + } + } + + break; + } case ADDR_FBMEM: { Heap *pHeap = pMemDesc->pHeap; @@ -885,6 +946,28 @@ _memdescAllocInternal allocData.flags |= NVOS32_ALLOC_FLAGS_PROTECTED; } + // + // Assume all RM internal allocations to go into protected (CPR) + // video memory unless specified otherwise explicitly + // + if (gpuIsCCFeatureEnabled(pGpu)) + { + if (pMemDesc->_flags & MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY) + { + // + // CC-TODO: Remove this check after non-CPR region is + // created. Not sure if RM will ever need to use non-CPR + // region for itself + // + NV_PRINTF(LEVEL_ERROR, "Non-CPR region still not created\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + else + { + allocData.flags |= NVOS32_ALLOC_FLAGS_PROTECTED; + } + } + allocData.attr |= DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS); pFbAllocInfo = portMemAllocNonPaged(sizeof(FB_ALLOC_INFO)); @@ -924,7 +1007,7 @@ _memdescAllocInternal // depend on this. In the future we will have the PageCount be accurate. // pMemDesc->Size = requestedSize; - pMemDesc->PageCount = ((pMemDesc->Size + pMemDesc->PteAdjust + pMemDesc->pageArrayGranularity - 1) >> + pMemDesc->PageCount = ((pMemDesc->Size + pMemDesc->PteAdjust + pMemDesc->pageArrayGranularity - 1) >> BIT_IDX_32(pMemDesc->pageArrayGranularity)); } // We now have the memory @@ -982,6 +1065,7 @@ memdescAlloc switch (pMemDesc->_addressSpace) { case ADDR_SYSMEM: + case ADDR_EGM: // Can't alloc sysmem on GSP firmware. if (RMCFG_FEATURE_PLATFORM_GSP && !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) { @@ -994,10 +1078,51 @@ memdescAlloc pMemDesc->_addressSpace = ADDR_FBMEM; pMemDesc->pHeap = GPU_GET_HEAP(pGpu); } + // + // If AMD SEV is enabled but CC or APM is not enabled on the GPU, + // all RM and client allocations must to to unprotected sysmem. + // So, we override any unprotected/protected flag set by either RM + // or client. + // If APM is enabled and RM is allocating sysmem for its internal use + // use such memory has to be unprotected as protected sysmem is not + // accessible to GPU + // + if ((sysGetStaticConfig(pSys))->bOsSevEnabled) + { + if (!gpuIsCCorApmFeatureEnabled(pGpu) || + (gpuIsApmFeatureEnabled(pGpu) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT))) + { + memdescSetFlag(pMemDesc, + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, NV_TRUE); + } + } + else + { + // + // This flag has no meaning on non-SEV systems. So, unset it. The + // OS layer currently honours this flag irrespective of whether + // SEV is enabled or not + // + memdescSetFlag(pMemDesc, + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, NV_FALSE); + } break; case ADDR_FBMEM: { + // + // When APM is enabled, all RM internal vidmem allocations go to + // unprotected memory. There is an underlying assumption that + // memdescAlloc won't be directly called in the client vidmem alloc + // codepath. Note that memdescAlloc still gets called in the client + // sysmem alloc codepath. See CONFCOMP-529 + // + if (gpuIsApmFeatureEnabled(pGpu)) + { + memdescSetFlag(pMemDesc, + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, NV_TRUE); + } // If FB is broken then don't allow the allocation, unless running in L2 cache only mode if (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) && !gpuIsCacheOnlyModeEnabled(pGpu)) @@ -1335,6 +1460,7 @@ _memdescFreeInternal switch (pMemDesc->_addressSpace) { case ADDR_SYSMEM: + case ADDR_EGM: // invalidate if memory is cached in FB L2 cache. if (pMemDesc->_gpuCacheAttrib == NV_MEMORY_CACHED) { @@ -1513,6 +1639,7 @@ memdescFree } if (pMemDesc->_addressSpace != ADDR_FBMEM && + pMemDesc->_addressSpace != ADDR_EGM && pMemDesc->_addressSpace != ADDR_SYSMEM) { return; @@ -1670,22 +1797,12 @@ memdescMap Offset += pMemDesc->PteAdjust; } - // - // Sanity check, the top-level descriptor should be allocated or else - // memDesc must be marked as user allocate memory. This allows mapping of - // memDesc keeping track of PA's for user allocated memory, wherein RM - // marks the corresponding memDesc as not allocated. - // - NV_ASSERT_OR_RETURN(pMemDesc->Allocated || - memdescGetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM) || - memdescGetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM), - NV_ERR_INVALID_OBJECT_BUFFER); - NV_ASSERT_OR_RETURN(!memdescHasSubDeviceMemDescs(pMemDesc), NV_ERR_INVALID_OBJECT_BUFFER); switch (pMemDesc->_addressSpace) { case ADDR_SYSMEM: + case ADDR_EGM: { status = osMapSystemMemory(pMemDesc, Offset, Size, Kernel, Protect, pAddress, pPriv); @@ -1764,15 +1881,6 @@ memdescMap break; } - // Mapping via PCIe BAR - - NvHandle hClient = NV01_NULL_OBJECT; - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - if ((pCallContext != NULL) && (pCallContext->pClient != NULL)) - { - hClient = pCallContext->pClient->hClient; - } - // Determine where in BAR1 the mapping will go pMapping->FbApertureLen = Size; status = kbusMapFbAperture_HAL(pGpu, pKernelBus, @@ -1780,7 +1888,7 @@ memdescMap &pMapping->FbAperture, &pMapping->FbApertureLen, BUS_MAP_FB_FLAGS_MAP_UNICAST, - hClient); + NULL); if (status != NV_OK) { portMemFree(pMapping); @@ -2248,6 +2356,47 @@ memdescDescribe pMemDesc->childDescriptorCnt = 0; } +/*! + * Static helper called from memdescFillPages. + * When dynamic granularity memdescs are enabled. We only need to copy over the pages + * without worrying about converting them to 4K. + * + * @param[in] pMemDesc Memory descriptor to fill + * @param[in] pageIndex Index into memory descriptor to fill from + * @param[in] pPages Array of physical addresses + * @param[in] pageCount Number of entries in pPages + * @param[in] pageSize Size of each page in pPages + * + * @returns None + */ +static void +_memdescFillPagesAtNativeGranularity +( + MEMORY_DESCRIPTOR *pMemDesc, + NvU32 pageIndex, + NvU64 *pPages, + NvU32 pageCount, + NvU64 pageSize +) +{ + NV_STATUS status; + + NV_ASSERT(pageIndex + pageCount < pMemDesc->PageCount); + + status = memdescSetPageArrayGranularity(pMemDesc, pageSize); + if (status != NV_OK) + { + return; + } + + for (NvU32 i = 0; i < pageCount; i++) + { + pMemDesc->_pteArray[pageIndex + i] = pPages[i]; + } + + pMemDesc->ActualSize = pageCount * pageSize; +} + /*! * Fill the PTE array of a memory descriptor with an array of addresses * returned by pmaAllocatePages(). @@ -2277,6 +2426,7 @@ memdescFillPages NvU64 pageSize ) { + OBJGPU *pGpu = gpumgrGetSomeGpu(); NvU32 i, j, k; NvU32 numChunks4k = pageSize / RM_PAGE_SIZE; NvU32 offset4k = numChunks4k * pageIndex; @@ -2286,6 +2436,12 @@ memdescFillPages NV_ASSERT(pMemDesc != NULL); + if (GPU_GET_MEMORY_MANAGER(pGpu)->bEnableDynamicGranularityPageArrays) + { + _memdescFillPagesAtNativeGranularity(pMemDesc, pageIndex, pPages, pageCount, pageSize); + return; + } + NV_ASSERT(offset4k < pMemDesc->PageCount); NV_ASSERT(portSafeAddU32(offset4k, pageCount4k, &result4k)); @@ -3913,7 +4069,7 @@ NV_ADDRESS_SPACE memdescGetAddressSpace(PMEMORY_DESCRIPTOR pMemDesc) * * @returns Current page size. */ -NvU64 memdescGetPageSize64 +NvU64 memdescGetPageSize ( PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation @@ -3923,19 +4079,6 @@ NvU64 memdescGetPageSize64 return pMemDesc->_pageSize; } -NvU32 memdescGetPageSize -( - PMEMORY_DESCRIPTOR pMemDesc, - ADDRESS_TRANSLATION addressTranslation -) -{ - NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); - NV_ASSERT(pMemDesc->_pageSize <= NV_U32_MAX); - if (pMemDesc->_pageSize > NV_U32_MAX) - DBG_BREAKPOINT(); - return (NvU32)pMemDesc->_pageSize; -} - /*! * @brief Set page size * @@ -4232,7 +4375,7 @@ void memdescCheckSubDevicePageSizeConsistency SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) pTempMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); - tempPageSize = memdescGetPageSize64(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); + tempPageSize = memdescGetPageSize(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); tempPageOffset = memdescGetPhysAddr(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), 0) & (tempPageSize - 1); // Assert if inconsistent @@ -4650,7 +4793,8 @@ memdescSendMemDescToGSP(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvHandle *pHa pMemoryManager->hSubdevice, pHandle, hClass, - &listAllocParams), + &listAllocParams, + sizeof(listAllocParams)), end); // Register MemoryList object to GSP @@ -4670,3 +4814,27 @@ memdescSendMemDescToGSP(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvHandle *pHa return status; } + +NV_STATUS +memdescSetPageArrayGranularity +( + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 pageArrayGranularity +) +{ + // Make sure pageArrayGranularity is a power of 2 value. + NV_ASSERT_OR_RETURN((pageArrayGranularity & (pageArrayGranularity - 1)) == 0, NV_ERR_INVALID_ARGUMENT); + + // Allow setting the same granularity. + if (pMemDesc->pageArrayGranularity == pageArrayGranularity) + { + return NV_OK; + } + + // Make sure setting the page array happens before the pteArray is populated. + NV_ASSERT_OR_RETURN(pMemDesc->_pteArray[0] == 0, NV_ERR_INVALID_STATE); + + pMemDesc->pageArrayGranularity = pageArrayGranularity; + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c index 5aead1611d..c0a2211bd1 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,10 +25,12 @@ #include "gpu/mem_mgr/heap.h" #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/mem_utils.h" +#include "gpu/mem_mgr/ce_utils.h" #include "mem_mgr/video_mem.h" #include "gpu/mem_mgr/fbsr.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" +#include "gpu/bif/kernel_bif.h" #include "core/locks.h" #include "virtualization/kernel_vgpu_mgr.h" #include "vgpu/rpc.h" @@ -44,6 +46,10 @@ #include "class/cl503c.h" #include "class/cl906f.h" // GF100_CHANNEL_GPFIFO #include "os/os.h" +#include "gpu/gsp/kernel_gsp.h" +#include "gpu/conf_compute/conf_compute.h" + +#include "class/cl0050.h" static NV_STATUS _memmgrCreateFBSR(MemoryManager *pMemoryManager, NvU32); static NV_STATUS _memmgrCreateChildObjects(MemoryManager *pMemoryManager); @@ -397,6 +403,76 @@ memmgrStateInitLocked_IMPL return NV_OK; } +NV_STATUS +memmgrVerifyGspDmaOps_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc; + NvU8 *pTestBuffer; + NvU32 testData = 0xdeadbeef; + TRANSFER_SURFACE surf = {0}; + + // + // Return early if CPU access to CPR vidmem is allowed as GSP DMA + // is not needed in this case + // + if (!kbusIsBarAccessBlocked(pKernelBus)) + return NV_OK; + + pTestBuffer = portMemAllocNonPaged(4096); + NV_ASSERT_OR_RETURN(pTestBuffer != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + + portMemSet(pTestBuffer, 0, 4096); + + status = memdescCreate(&pMemDesc, pGpu, RM_PAGE_SIZE, RM_PAGE_SIZE, + NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, 0); + NV_ASSERT_OR_RETURN(status == NV_OK, status); + + status = memdescAlloc(pMemDesc); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + surf.pMemDesc = pMemDesc; + surf.offset = sizeof(NvU32); // Choosing a random offset + + // Write test data to FB using GSP + status = memmgrMemWrite(pMemoryManager, &surf, &testData, sizeof(NvU32), + TRANSFER_FLAGS_NONE); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + // Read the same location using GSP and confirm that GSP read is also working fine + status = memmgrMemRead(pMemoryManager, &surf, pTestBuffer, sizeof(NvU32), + TRANSFER_FLAGS_NONE); + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + + if (((NvU32*)pTestBuffer)[0] != testData) + { + NV_PRINTF(LEVEL_ERROR, "####################################################\n"); + NV_PRINTF(LEVEL_ERROR, " Read back of data using GSP shows mismatch\n"); + NV_PRINTF(LEVEL_ERROR, " Test data: 0x%x Read Data: 0x%x\n", testData, ((NvU32*)pTestBuffer)[0]); + NV_PRINTF(LEVEL_ERROR, "####################################################\n"); + status = NV_ERR_INVALID_STATE; + NV_ASSERT_OR_GOTO(status == NV_OK, failed); + } + else + { + NV_PRINTF(LEVEL_INFO, "####################################################\n"); + NV_PRINTF(LEVEL_INFO, " Read back of data using GSP confirms write\n"); + NV_PRINTF(LEVEL_INFO, "####################################################\n"); + } + +failed: + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + portMemFree(pTestBuffer); + + return status; +} + NV_STATUS memmgrStateLoad_IMPL ( @@ -418,6 +494,19 @@ memmgrStateLoad_IMPL memmgrScrubInit_HAL(pGpu, pMemoryManager); } + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + // + // NUMA onlined memory size should not exceed memory size assigned to PMA. + // TODO : Currently in selfhosted and P9+GV100 systems numaOnlined size is less + // than PMA Memory Size. Ideally both of them should be identical. Bug 4051320. + // + NvU64 pmaTotalMemorySize; + NvU64 numaOnlineSize = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->numaOnlineSize; + pmaGetTotalMemory(&GPU_GET_HEAP(pGpu)->pmaObject, &pmaTotalMemorySize); + NV_ASSERT_OR_RETURN(pmaTotalMemorySize >= numaOnlineSize, NV_ERR_INVALID_STATE); + } + // Dump FB regions memmgrDumpFbRegions(pGpu, pMemoryManager); @@ -432,9 +521,18 @@ memmgrStatePreUnload_IMPL NvU32 flags ) { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NV_ASSERT((flags & GPU_STATE_FLAGS_PRESERVING) || pMemoryManager->zbcSurfaces == 0); + if (memmgrIsPmaEnabled(pMemoryManager) && + memmgrIsPmaSupportedOnPlatform(pMemoryManager) && + osNumaOnliningEnabled(pGpu->pOsGpuInfo) && + pKernelMemorySystem->memPartitionNumaInfo[0].bInUse) + { + pmaNumaOfflined(&pMemoryManager->pHeap->pmaObject); + } + return NV_OK; } @@ -518,6 +616,15 @@ memmgrStateDestroy_IMPL fbsrDestroy_HAL(pGpu, pMemoryManager->pFbsr[i]); } } + if (memmgrIsLocalEgmEnabled(pMemoryManager)) + { + if (!IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + kbusUnreserveP2PPeerIds_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), NVBIT(pMemoryManager->localEgmPeerId)); + } + pMemoryManager->localEgmPeerId = BUS_INVALID_PEER; + pMemoryManager->bLocalEgmEnabled = NV_FALSE; + } memmgrScrubDestroy_HAL(pGpu, pMemoryManager); } @@ -752,12 +859,21 @@ _memmgrAllocInternalClientObjects failed); portMemSet(¶ms, 0, sizeof(params)); - params.flags = NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + params.flags = NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK; + } + else + { + params.flags = NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1; + } status = pRmApi->AllocWithHandle(pRmApi, pMemoryManager->hClient, pMemoryManager->hSubdevice, hThirdPartyP2P, - NV50_THIRD_PARTY_P2P, ¶ms); + NV50_THIRD_PARTY_P2P, + ¶ms, + sizeof(params)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Error creating internal ThirdPartyP2P object: %x\n", @@ -815,6 +931,19 @@ memmgrGetUsedRamSize_IMPL *pFbUsedSize = heapTotalSpace - heapFreeSpace; } + // + // GSP's WPR region has its own save/restore mechanism and does not need + // to be accounted for in total FB size used - which is needed to find out + // how much SYSMEM needs to be allocated to save all FB memory + // + if (IS_GSP_CLIENT(pGpu)) + { + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + NvU64 gspWprRegionSize = pKernelGsp->pWprMeta->gspFwWprEnd - pKernelGsp->pWprMeta->gspFwWprStart; + + *pFbUsedSize = *pFbUsedSize - gspWprRegionSize; + } + return NV_OK; } @@ -1038,6 +1167,8 @@ memmgrFillMemdescForPhysAttr_IMPL *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM; else if (memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM; + else if (memdescGetAddressSpace(pMemDesc) == ADDR_EGM) + *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM; else if (memdescGetAddressSpace(pMemDesc) == ADDR_VIRTUAL ) { // @@ -1161,6 +1292,7 @@ memmgrDeterminePageSize_IMPL { NV_PRINTF(LEVEL_ERROR, "Big/Huge/512MB page size not supported in sysmem.\n"); + NV_ASSERT_OR_RETURN(0, 0); } else @@ -1450,6 +1582,8 @@ memmgrCalcReservedFbSpace_IMPL NvU32 idxSlowRegion = 0; NvBool bAllocProtected = NV_FALSE; + bAllocProtected = gpuIsCCFeatureEnabled(pGpu); + // // This is a hack solely for Vista (on Vista the OS controls the majority of heap). // Linux and Mac don't have reserved memory and doesn't use this function. @@ -1525,6 +1659,11 @@ memmgrCalcReservedFbSpace_IMPL NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxFastRegion].bRsvdRegion); NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxSlowRegion].bRsvdRegion); + // + // Whenever Hopper CC is enabled, it is mandatory to put allocations + // like page tables, CBC and fault buffers in CPR region. Cannot put + // reserved memory in protected region in non CC cases + // if (!bAllocProtected) { NV_ASSERT(!pMemoryManager->Ram.fbRegion[idxISORegion].bProtected); @@ -1853,9 +1992,11 @@ memmgrSetPartitionableMem_IMPL // enabling "scrub on free" using virtual CE writes, memory gets consumed by // page tables backing the scrubber channel virtual mappings and hence the // calculation below no longer holds good + // In case of HCC, structures like PB, GPFIFO and USERD for scrubber and golden + // channels are required to be in CPR vidmem. This changes the calculation below + // We can ignore this for the non-MIG case. // - if (!gpuIsApmFeatureEnabled(pGpu) || - !memmgrUseVasForCeMemoryOps(pMemoryManager) || + if (!gpuIsCCorApmFeatureEnabled(pGpu) || IS_MIG_ENABLED(pGpu)) { // @@ -1864,18 +2005,18 @@ memmgrSetPartitionableMem_IMPL // offset argument is not implemented as of this writing, so we // only get the base address of the region that contains it). There // is a known allocation from the top-level scrubber channel that - // is expected to be no larger than 64K. Issue a warning for any + // is expected to be no larger than 128K. Issue a warning for any // other uses. // - if ((size > RM_PAGE_SIZE_64K) && - (freeMem < (size - RM_PAGE_SIZE_64K))) + if ((size > RM_PAGE_SIZE_128K) && + (freeMem < (size - RM_PAGE_SIZE_128K))) { NV_PRINTF(LEVEL_ERROR, "Assumption that PMA is empty (after accounting for the top-level scrubber) is not met!\n"); NV_PRINTF(LEVEL_ERROR, " free space = 0x%llx bytes, total space = 0x%llx bytes\n", freeMem, size); - NV_ASSERT_OR_RETURN(freeMem >= (size - RM_PAGE_SIZE_64K), + NV_ASSERT_OR_RETURN(freeMem >= (size - RM_PAGE_SIZE_128K), NV_ERR_INVALID_STATE); } } @@ -1963,6 +2104,7 @@ memmgrFillComprInfo_IMPL if (!memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, kind)) return NV_OK; + // TODO: We will have to support compression on vGPU HOST for AC NV_ASSERT(compTagStartOffset != ~(NvU32)0); pComprInfo->compPageShift = pMemorySystemConfig->comprPageShift; @@ -2076,6 +2218,7 @@ memmgrSetMIGPartitionableBAR1Range_IMPL if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) return NV_OK; + NV_ASSERT_OR_RETURN(pBar1VAS != NULL, NV_ERR_INVALID_STATE); pVASHeap = vaspaceGetHeap(pBar1VAS); // Get partitionable BAR1 range @@ -2140,6 +2283,7 @@ memmgrAllocMIGGPUInstanceMemory_PF NV_STATUS rmStatus = NV_OK; NvHandle hMemory = 0; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvBool bNumaEnabled = osNumaOnliningEnabled(pGpu->pOsGpuInfo); NV_ASSERT_OR_RETURN(pKernelMIGManager != NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OK_OR_RETURN(kmemsysGetMIGGPUInstanceMemInfo(pGpu, pKernelMemorySystem, swizzId, pAddrRange)); @@ -2153,6 +2297,42 @@ memmgrAllocMIGGPUInstanceMemory_PF // if (kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId)) { + if(bNumaEnabled) + { + NvS32 numaNodeId; + NvU64 partitionBaseAddr = pAddrRange->lo; + NvU64 partitionSize = rangeLength(*pAddrRange); + NvU64 unalignedPartitionBaseAddr = partitionBaseAddr; + NvU64 memblockSize = 0; + + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + // + // Align the partition base and size to memblock size + // Some FB memory is wasted here if it is not already aligned. + // + partitionBaseAddr = NV_ALIGN_UP64(unalignedPartitionBaseAddr, memblockSize); + partitionSize -= (partitionBaseAddr - unalignedPartitionBaseAddr); + partitionSize = NV_ALIGN_DOWN64(partitionSize, memblockSize); + + if (kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager) == 0x0) + { + // Remove swizz Id 0 / baremetal GPU memory NUMA node + pmaNumaOfflined(&GPU_GET_HEAP(pGpu)->pmaObject); + kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, 0); + } + + // + // The memory gets removed in memmgrFreeMIGGPUInstanceMemory if + // there is any failure after adding the memory. + // + NV_ASSERT_OK_OR_RETURN(kmemsysNumaAddMemory_HAL(pGpu, + pKernelMemorySystem, + swizzId, + partitionBaseAddr, + partitionSize, + &numaNodeId)); + } + else { // // Allocate memory using vidHeapControl @@ -2186,7 +2366,8 @@ memmgrAllocMIGGPUInstanceMemory_PF pMemoryManager->MIGMemoryPartitioningInfo.hSubdevice, &hMemory, NV01_MEMORY_LOCAL_USER, - &memAllocParams); + &memAllocParams, + sizeof(memAllocParams)); // Reaquire the GPU locks if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM) != NV_OK) @@ -2239,6 +2420,8 @@ _memmgrInitMIGMemoryPartitionHeap NV_STATUS status = NV_OK; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); Heap *pMemoryPartitionHeap = NULL; + NvBool bNumaEnabled = osNumaOnliningEnabled(pGpu->pOsGpuInfo); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NvU64 partitionBaseAddr = pAddrRange->lo; NvU64 partitionSize = rangeLength(*pAddrRange); @@ -2270,6 +2453,27 @@ _memmgrInitMIGMemoryPartitionHeap memmgrPmaInitialize(pGpu, pMemoryManager, &pMemoryPartitionHeap->pmaObject), fail); + if (bNumaEnabled) + { + NV_ASSERT_OR_GOTO(pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse, fail); + partitionBaseAddr = pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset; + partitionSize = pKernelMemorySystem->memPartitionNumaInfo[swizzId].size; + + // + // The base and size passed here is the FB base and size and + // not the partition's. pmaNumaOnlined requires the FB base and + // size to convert between FB local address and SPA. + // memmgrPmaRegisterRegions is where the partition's base and size + // is reported to PMA. + // + NV_ASSERT_OK_OR_GOTO( + status, + pmaNumaOnlined(&pMemoryPartitionHeap->pmaObject, + pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId, + pKernelMemorySystem->coherentCpuFbBase, + pKernelMemorySystem->numaOnlineSize), + fail); + } } NV_ASSERT_OK_OR_GOTO( @@ -2333,6 +2537,8 @@ memmgrFreeMIGGPUInstanceMemory_IMPL { RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvBool bNumaEnabled = osNumaOnliningEnabled(pGpu->pOsGpuInfo); NV_ASSERT_OR_RETURN(pKernelMIGManager != NULL, NV_ERR_INVALID_STATE); @@ -2343,8 +2549,32 @@ memmgrFreeMIGGPUInstanceMemory_IMPL objDelete(*ppMemoryPartitionHeap); *ppMemoryPartitionHeap = NULL; + if (bNumaEnabled) + { + kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, swizzId); + + if (kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager) == 0x0) + { + NvS32 numaNodeId; + + // Add back the baremetal GPU memory NUMA node. + NV_ASSERT_OK_OR_RETURN(kmemsysNumaAddMemory_HAL(pGpu, + pKernelMemorySystem, + 0, + pKernelMemorySystem->numaOnlineBase, + pKernelMemorySystem->numaOnlineSize, + &numaNodeId)); + // Baremetal NUMA node id should be same as pGpu->numaNodeId + NV_ASSERT_OR_RETURN(numaNodeId == pGpu->numaNodeId, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN(pmaNumaOnlined(&GPU_GET_HEAP(pGpu)->pmaObject, + pGpu->numaNodeId, + pKernelMemorySystem->coherentCpuFbBase, + pKernelMemorySystem->numaOnlineSize)); + } + } + // Free allocated memory - if ((hMemory != NV01_NULL_OBJECT)) + if (!bNumaEnabled && (hMemory != NV01_NULL_OBJECT)) { pRmApi->Free(pRmApi, pMemoryManager->MIGMemoryPartitioningInfo.hClient, hMemory); } @@ -2408,6 +2638,15 @@ memmgrPageLevelPoolsCreate_IMPL NV_ASSERT(NV_OK == status); + // + // Allocate the pool in CPR in case of Confidential Compute + // When Hopper Confidential Compute is enabled, page tables + // cannot be in non-CPR region + // + if (gpuIsCCFeatureEnabled(pGpu) && (status == NV_OK)) + { + rmMemPoolAllocateProtectedMemory(pMemoryManager->pPageLevelReserve, NV_TRUE); + } } return status; } @@ -2532,6 +2771,12 @@ memmgrPmaInitialize_IMPL pmaInitFlags |= PMA_INIT_NUMA; } + if (gpuIsSelfHosted(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Initializing PMA with NUMA_AUTO_ONLINE flag.\n"); + pmaInitFlags |= PMA_INIT_NUMA_AUTO_ONLINE; + } + if (memmgrIsPmaAddrTree(pMemoryManager)) { pmaInitFlags |= PMA_INIT_ADDRTREE; @@ -2546,6 +2791,7 @@ memmgrPmaInitialize_IMPL if (bNumaEnabled) { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NvU32 numaSkipReclaimVal = NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_DEFAULT; @@ -2558,6 +2804,14 @@ memmgrPmaInitialize_IMPL } pmaNumaSetReclaimSkipThreshold(pPma, numaSkipReclaimVal); + // Full FB memory is added and onlined already + if (pKernelMemorySystem->memPartitionNumaInfo[0].bInUse) + { + NV_ASSERT_OK_OR_RETURN(pmaNumaOnlined(pPma, pGpu->numaNodeId, + pKernelMemorySystem->coherentCpuFbBase, + pKernelMemorySystem->numaOnlineSize)); + } + } return NV_OK; @@ -2875,6 +3129,44 @@ memmgrGetFreeMemoryForAllMIGGPUInstances_IMPL FOR_EACH_VALID_GPU_INSTANCE_END(); } +/*! + * @brief Gets total memory for all valid GPU instances + * + * @param pGpu + * @param pMemoryManager + * @param[out] pBytes pointer to the total memory + * + */ +void +memmgrGetTotalMemoryForAllMIGGPUInstances_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU64 *pBytes +) +{ + NvU64 val = 0; + Heap *pHeap = NULL; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance; + + *pBytes = 0; + + FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pKernelMIGGPUInstance) + { + NV_ASSERT(pKernelMIGGPUInstance->pMemoryPartitionHeap != NULL); + pHeap = pKernelMIGGPUInstance->pMemoryPartitionHeap; + + if (memmgrIsPmaInitialized(pMemoryManager)) + pmaGetTotalMemory(&pHeap->pmaObject, &val); + else + heapGetSize(pHeap, &val); + + *pBytes += val; + } + FOR_EACH_VALID_GPU_INSTANCE_END(); +} + void memmgrGetTopLevelScrubberStatus_IMPL ( @@ -3086,3 +3378,133 @@ memmgrGetVgpuHostRmReservedFb_KERNEL sizeof(params))); return params.hostReservedFb; } + +/*! + * @brief Memory Manager State post load + * + * @param[in] pGpu GPU pointer + * @param[in/out] pMemoryManager MemoryManager pointer + * @param[in] flags State transition flags + * + * @returns On success, returns NV_OK. + * On failure, returns error code. + */ +NV_STATUS +memmgrStatePostLoad_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU32 flags +) +{ + if (memmgrIsLocalEgmSupported(pMemoryManager)) + { + NvU64 egmPhysAddr, egmSize; + NvS32 egmNodeId; + NvU32 data32; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + pMemoryManager->localEgmNodeId = -1; + if (gpuIsSelfHosted(pGpu) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP) && // EGM can be enabled only in C2C path. + (osGetEgmInfo(pGpu, &egmPhysAddr, &egmSize, &egmNodeId) == NV_OK) && + (egmSize != 0)) + { + pMemoryManager->localEgmBasePhysAddr = egmPhysAddr; + pMemoryManager->localEgmSize = egmSize; + pMemoryManager->localEgmNodeId = egmNodeId; + // + // Using fixed Peer ID 7 for local EGM so that vGPU + // migration doesn't fail because of peer id conflict in + // the new host system. + // + pMemoryManager->localEgmPeerId = 7; + pMemoryManager->bLocalEgmEnabled = NV_TRUE; + } + + // + // regkey can override the production flow values. + // Note that this could cause an issue with vGPU migration + // if one host system uses regkey to override the EGM peer id + // and other host system doesn't. + // + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_ENABLE_LOCAL_EGM_PEER_ID, &data32) == NV_OK) + { + pMemoryManager->bLocalEgmEnabled = NV_TRUE; + pMemoryManager->localEgmPeerId = data32; + } + } + + // + // Reserve the peerID used for local EGM so that the peerID isn't + // resused for other peer Gpus. + // + if (memmgrIsLocalEgmEnabled(pMemoryManager)) + { + if (kbusReserveP2PPeerIds_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), NVBIT(pMemoryManager->localEgmPeerId)) == NV_OK) + { + { + NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status; + + params.egmPeerId = pMemoryManager->localEgmPeerId; + + // Call physical HSHUB to program the EGM PeerId settings. + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG, + ¶ms, + sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "HSHUB programming failed for EGM Peer ID: %u\n", + pMemoryManager->localEgmPeerId); + pMemoryManager->bLocalEgmEnabled = NV_FALSE; + pMemoryManager->localEgmPeerId = BUS_INVALID_PEER; + return status; + } + } + } + else + { + NV_PRINTF(LEVEL_ERROR, + "Peer ID specified for local EGM already in use!\n"); + pMemoryManager->bLocalEgmEnabled = NV_FALSE; + pMemoryManager->localEgmPeerId = BUS_INVALID_PEER; + return NV_ERR_INVALID_ARGUMENT; + } + } + else + { + pMemoryManager->localEgmPeerId = BUS_INVALID_PEER; + } + return NV_OK; +} + +NV_STATUS +memmgrInitCeUtils_IMPL +( + MemoryManager *pMemoryManager, + NvBool bFifoLite +) +{ + NV0050_ALLOCATION_PARAMETERS ceUtilsParams = {0}; + + NV_ASSERT_OR_RETURN(pMemoryManager->pCeUtils == NULL, NV_ERR_INVALID_STATE); + + ceUtilsParams.flags = bFifoLite ? DRF_DEF(0050_CEUTILS, _FLAGS, _FIFO_LITE, _TRUE) : 0; + return objCreate(&pMemoryManager->pCeUtils, pMemoryManager, CeUtils, ENG_GET_GPU(pMemoryManager), &ceUtilsParams); +} + +void +memmgrDestroyCeUtils_IMPL +( + MemoryManager *pMemoryManager +) +{ + objDelete(pMemoryManager->pCeUtils); + pMemoryManager->pCeUtils = NULL; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c index 4c0260b28f..a58d08a3da 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -105,6 +105,11 @@ memmgrGetDeviceCaps } } + if (pMemoryManager->bGenericKindSupport) + { + RMCTRL_SET_CAP(tempCaps, NV0080_CTRL_FB_CAPS, _GENERIC_PAGE_KIND); + } + if (memmgrIsScrubOnFreeEnabled(pMemoryManager)) { RMCTRL_SET_CAP(tempCaps, NV0080_CTRL_FB_CAPS, _VIDMEM_ALLOCS_ARE_CLEARED); } @@ -153,6 +158,8 @@ memmgrGetDeviceCaps NV0080_CTRL_FB_CAPS, _OS_OWNS_HEAP_NEED_ECC_SCRUB); RMCTRL_OR_CAP(pFbCaps, tempCaps, temp, NV0080_CTRL_FB_CAPS, _DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641); + RMCTRL_AND_CAP(pFbCaps, tempCaps, temp, + NV0080_CTRL_FB_CAPS, _GENERIC_PAGE_KIND); RMCTRL_OR_CAP(pFbCaps, tempCaps, temp, NV0080_CTRL_FB_CAPS, _DISABLE_MSCG_WITH_VR_BUG_1681803); RMCTRL_AND_CAP(pFbCaps, tempCaps, temp, @@ -255,23 +262,14 @@ subdeviceCtrlCmdFbGetBar1Offset_IMPL NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS *pFbMemParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - Device *pDevice; + NvHandle hDevice = RES_GET_PARENT_HANDLE(pSubdevice); NvU64 offset; RsCpuMapping *pCpuMapping = NULL; - NV_STATUS status; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - // Get the device handle - status = deviceGetByInstance(RES_GET_CLIENT(pSubdevice), - gpuGetDeviceInstance(pGpu), - &pDevice); - if (status != NV_OK) - return NV_ERR_INVALID_ARGUMENT; - - pCpuMapping = CliFindMappingInClient(hClient, RES_GET_HANDLE(pDevice), pFbMemParams->cpuVirtAddress); + pCpuMapping = CliFindMappingInClient(hClient, hDevice, pFbMemParams->cpuVirtAddress); if (pCpuMapping == NULL) return NV_ERR_INVALID_ARGUMENT; @@ -353,8 +351,9 @@ subdeviceCtrlCmdFbGetMemAlignment_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); - Heap *pHeap = vidmemGetHeap(pGpu, hClient, NV_FALSE); + Heap *pHeap = vidmemGetHeap(pGpu, pDevice, NV_FALSE); HEAP_ALLOC_HINT_PARAMS AllocHint = {0}; NvU32 i; NvU64 _size, _alignment; @@ -796,3 +795,32 @@ diagapiCtrlCmdFbEccAsyncScrubRegion_IMPL return NV_OK; } + +NV_STATUS +subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *pParams +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(GPU_RES_GET_GPU(pSubdevice)); + + pParams->caps = 0; + + if (pMemoryManager->bMonitoredFenceSupported) + pParams->caps |= NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED; + + if (pMemoryManager->b64BitSemaphoresSupported) + pParams->caps |= NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED; + + // + // Assume semaphore values to always be 64-bit for simplicity + // It is not possible to pack the surface better due to alignment requirements, + // so use the static layout here. But keep the offsets interface for flexibility in the future. + // + pParams->monitoredFenceThresholdOffset = 16; // payload + timestamp + pParams->maxSubmittedSemaphoreValueOffset = 24; + pParams->size = 32; + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c index 676050f276..6ee4470885 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c @@ -152,6 +152,19 @@ memmgrPreInitReservedMemory_FWCLIENT tmpAddr += 0x10000; } + if (gpuIsSelfHosted(pGpu)) + { + // + // Reserve space for the test buffer used in coherent link test + // that is run early when memory allocation is not ready yet. + // + // if Self-Hosted is running in PCIe mode then this space will + // will not be used, this should not cause any issue + // + pKernelBus->coherentLinkTestBufferBase = tmpAddr; + tmpAddr += BUS_COHERENT_LINK_TEST_BUFFER_SIZE; + } + if (KBUS_BAR2_ENABLED(pKernelBus)) { // diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c index a39f43d081..d8df1ef1e1 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,7 @@ #include "vgpu/rpc.h" #include "os/nv_memory_type.h" #include "gpu/gsp/kernel_gsp.h" +#include "gpu/gsp/gsp_static_config.h" static NV_STATUS _memmgrWalkHeap(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJFBSR *pFbsr); static NV_STATUS _memmgrAllocFbsrReservedRanges(OBJGPU *pGpu, MemoryManager *pMemoryManager); @@ -571,18 +572,59 @@ memmgrAddMemNode return rmStatus; } +NvBool +memmgrIsGspOwnedMemory_KERNEL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + RmPhysAddr physAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + NvU64 fbRegionSize = 0; + + NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *pFbRegionInfoParams = &pGSCI->fbRegionInfoParams; + NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO *pFbRegionInfo = NULL; + + // Return NV_TRUE if input MEMORY_DESCRIPTOR corresponds to any GSP managed regions + for (NvU32 i = 0; i < pFbRegionInfoParams->numFBRegions; i++) + { + pFbRegionInfo = &pFbRegionInfoParams->fbRegion[i]; + fbRegionSize = pFbRegionInfo->limit - pFbRegionInfo->base + 1; + + if ((pFbRegionInfo->base == physAddr) && (fbRegionSize == pMemDesc->Size)) + { + NV_PRINTF(LEVEL_INFO, + "Skipping GSP FB Region with addr 0x%llx and size 0x%llx\n", + physAddr, pMemDesc->Size); + return NV_TRUE; + } + } + + return NV_FALSE; +} + NV_STATUS -memmgrAddMemNodes_IMPL(OBJGPU *pGpu, MemoryManager *pMemoryManager, NvBool bSaveAllRmAllocations) +memmgrAddMemNodes_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvBool bSaveAllRmAllocations +) { NV_STATUS status = NV_OK; - Heap *pHeap = GPU_GET_HEAP(pGpu); + Heap *pHeap = GPU_GET_HEAP(pGpu); MEMORY_DESCRIPTOR *pAllocMemDesc; MEM_BLOCK *block; + NvBool bSaveNode = NV_FALSE; block = pHeap->pBlockList; do { pAllocMemDesc = block->pMemDesc; + bSaveNode = NV_FALSE; // // TODO: Bug 1778161: Let memory descriptor lost on suspend be default, @@ -590,17 +632,34 @@ memmgrAddMemNodes_IMPL(OBJGPU *pGpu, MemoryManager *pMemoryManager, NvBool bSave // content of memory descriptor, remove MEMDESC_FLAGS_LOST_ON_SUSPEND // flag. // - if ((pAllocMemDesc != NULL) && - (((block->owner == HEAP_OWNER_RM_RESERVED_REGION) && - (bSaveAllRmAllocations || - memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND))) || - (((block->owner == HEAP_OWNER_RM_CHANNEL_CTX_BUFFER) || - (block->owner == HEAP_OWNER_RM_KERNEL_CLIENT)) && - (bSaveAllRmAllocations || - (!memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_LOST_ON_SUSPEND)))))) + if (pAllocMemDesc != NULL) { - if ((memdescGetAddressSpace(pAllocMemDesc) == ADDR_FBMEM) || - (memdescGetAddressSpace(pAllocMemDesc) == ADDR_SYSMEM)) + // + // Save RM_RESERVED_REGION if it is not GSP managed FB region and + // - bSaveRmAllocations true or + // - MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND is set + // TODO: Use LOST_ON_SUSPEND flag to skip GSP managed FB regions + // + if ((block->owner == HEAP_OWNER_RM_RESERVED_REGION) && + !memmgrIsGspOwnedMemory_HAL(pGpu, pMemoryManager, pAllocMemDesc)) + { + if (bSaveAllRmAllocations || memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND)) + bSaveNode = NV_TRUE; + } + // + // Save RM_CHANNEL_CTX_BUFFER or RM_KERNEL_CLIENT regions if + // - bSaveRmAllocations true or + // - MEMDESC_FLAGS_PRESERVE_LOST_ON_SUSPEND is not set + // + else if ((block->owner == HEAP_OWNER_RM_CHANNEL_CTX_BUFFER) || (block->owner == HEAP_OWNER_RM_KERNEL_CLIENT)) + { + if (bSaveAllRmAllocations || (!memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_LOST_ON_SUSPEND))) + bSaveNode = NV_TRUE; + } + + if (bSaveNode && + ((memdescGetAddressSpace(pAllocMemDesc) == ADDR_FBMEM) || + (memdescGetAddressSpace(pAllocMemDesc) == ADDR_SYSMEM))) { NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c index 698f0d8e41..dafb2d37e2 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c @@ -411,11 +411,11 @@ memmgrRegionSetupCommon_IMPL // if the region has an RM reserved block and is not already reserved, subdivide it. // if ((pMemoryManager->Ram.fbRegion[i].rsvdSize > 0) && + (pMemoryManager->Ram.fbRegion[i].rsvdSize <= pMemoryManager->Ram.fbRegion[i].limit - pMemoryManager->Ram.fbRegion[i].base + 1) && (pMemoryManager->Ram.fbRegion[i].bRsvdRegion == NV_FALSE)) { portMemSet(&rsvdFbRegion, 0, sizeof(rsvdFbRegion)); - NV_ASSERT(pMemoryManager->Ram.fbRegion[i].rsvdSize <= pMemoryManager->Ram.fbRegion[i].limit - pMemoryManager->Ram.fbRegion[i].base + 1); rsvdFbRegion.limit = pMemoryManager->Ram.fbRegion[i].limit; rsvdFbRegion.base = rsvdFbRegion.limit - pMemoryManager->Ram.fbRegion[i].rsvdSize + 1; rsvdFbRegion.rsvdSize = pMemoryManager->Ram.fbRegion[i].rsvdSize; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c index 2c60518d9d..8127454ccb 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c @@ -33,6 +33,7 @@ #include "gpu/mem_mgr/mem_desc.h" #include "kernel/gpu/intr/intr.h" +#include "gpu/mem_mgr/channel_utils.h" #include "gpu/mem_mgr/mem_scrub.h" #include "os/os.h" #include "gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h" @@ -44,6 +45,7 @@ #include "nvstatus.h" #include "rmapi/rs_utils.h" #include "core/locks.h" +#include "class/cl0050.h" #include "class/clb0b5.h" // MAXWELL_DMA_COPY_A #include "class/clc0b5.h" // PASCAL_DMA_COPY_A #include "class/clc1b5.h" // PASCAL_DMA_COPY_B @@ -57,17 +59,15 @@ #include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A static NvU64 _scrubCheckProgress(OBJMEMSCRUB *pScrubber); -static void _scrubSetupChannelBufferSizes(OBJCHANNEL *pChannel, NvU32 numCopyBlocks); static NvU64 _searchScrubList(OBJMEMSCRUB *pScrubber, RmPhysAddr base, NvU64 size); static void _waitForPayload(OBJMEMSCRUB *pScrubber, RmPhysAddr base, RmPhysAddr end); static void _scrubAddWorkToList(OBJMEMSCRUB *pScrubber, RmPhysAddr base, NvU64 size, NvU64 newId); -static NvU32 _scrubMemory(OBJCHANNEL *pChannel, RmPhysAddr base, NvU64 size, NV_ADDRESS_SPACE dstAddrSpace, +static NvU32 _scrubMemory(OBJMEMSCRUB *pScrubber, RmPhysAddr base, NvU64 size, NvU32 dstCpuCacheAttrib, NvU32 freeToken); static void _scrubWaitAndSave(OBJMEMSCRUB *pScrubber, PSCRUB_NODE pList, NvLength itemsToSave); static NvU64 _scrubGetFreeEntries(OBJMEMSCRUB *pScrubber); static NvU64 _scrubCheckAndSubmit(OBJMEMSCRUB *pScrubber, NvU64 chunkSize, NvU64 *pPages, NvU64 pageCount, PSCRUB_NODE pList, NvLength pagesToScrubCheck); -static void _scrubOsSchedule(OBJCHANNEL *pChannel); static void _scrubCopyListItems(OBJMEMSCRUB *pScrubber, PSCRUB_NODE pList, NvLength itemsToSave); static NV_STATUS _scrubCheckLocked(OBJMEMSCRUB *pScrubber, PSCRUB_NODE *ppList, NvU64 *pSize); @@ -90,14 +90,11 @@ scrubberConstruct ) { OBJMEMSCRUB *pScrubber; - OBJCHANNEL *pChannel; - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NV_STATUS status = NV_OK; - PMA *pPma = NULL; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - RmClient *pClient; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NV_STATUS status = NV_OK; + NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); + PMA *pPma = NULL; if (pHeap == NULL) { @@ -135,32 +132,17 @@ scrubberConstruct } portMemSet(pScrubber->pScrubList, 0, sizeof(SCRUB_NODE) * MAX_SCRUB_ITEMS); + pScrubber->pGpu = pGpu; + { - pChannel = (OBJCHANNEL *) portMemAllocNonPaged(sizeof(OBJCHANNEL)); - if (pChannel == NULL) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto destroyscrublist; - } - portMemSet(pChannel, 0, sizeof(OBJCHANNEL)); - pScrubber->pChannel = pChannel; - pChannel->type = SCRUBBER_CHANNEL; - pChannel->pGpu = pGpu; - pChannel->bUseVasForCeCopy = memmgrUseVasForCeMemoryOps(pMemoryManager); - memmgrMemUtilsGetCopyEngineClass_HAL(pGpu, pMemoryManager, &pChannel->hTdCopyClass); - - if (((pChannel->hTdCopyClass == HOPPER_DMA_COPY_A) - ) && !pChannel->bUseVasForCeCopy) + NV_PRINTF(LEVEL_INFO, "Starting to init CeUtils for scrubber.\n"); + NV0050_ALLOCATION_PARAMETERS ceUtilsAllocParams = {0}; + + if (memmgrUseVasForCeMemoryOps(pMemoryManager)) { - pChannel->type = FAST_SCRUBBER_CHANNEL; + ceUtilsAllocParams.flags = DRF_DEF(0050, _CEUTILS_FLAGS, _VIRTUAL_MODE, _TRUE); } - NV_ASSERT_OK_OR_GOTO(status, - pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, - NV01_NULL_OBJECT, NV01_ROOT, &pChannel->hClient), freeChannelObject); - - pChannel->bClientAllocated = NV_TRUE; - if (bMIGInUse) { KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance; @@ -168,96 +150,19 @@ scrubberConstruct { if (pKernelMIGGPUInstance->pMemoryPartitionHeap == pHeap) { - pChannel->pKernelMIGGpuInstance = pKernelMIGGPUInstance; + ceutilsRegisterGPUInstance(&pScrubber->ceUtilsObject, pKernelMIGGPUInstance); break; } } FOR_EACH_VALID_GPU_INSTANCE_END(); } - // set all the unique ID's for the scrubber channel - NV_ASSERT_OK_OR_GOTO(status, - serverutilGetClientUnderLock(pChannel->hClient, &pClient), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U), freechannel); - - // set all the unique ID's for the scrubber channel - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->physMemId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->channelId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->errNotifierIdVirt), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->errNotifierIdPhys), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->copyObjectId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->eventId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->pushBufferId), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->doorbellRegionHandle), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->hUserD), freechannel); - - // - // RM scrubber channel is always created as privileged channels (physical address access) by default - // For MMU Bug: 2739505, we need to switch to use channels in non-privileged mode. - // We also need a (split) VAS for GSP-RM + MIG, to ensure we don't fall back to the device default - // VAS during channel allocation. - // - // TODO: This is temporary, and should be replaced shortly by enabling VAS allocation unilaterally. - // - if (pChannel->bUseVasForCeCopy || - (IS_GSP_CLIENT(pGpu) && bMIGInUse)) - { - NV_ASSERT_OK_OR_GOTO(status, - serverutilGenResourceHandle(pChannel->hClient, &pChannel->hVASpaceId), freechannel); - } - - // set sizes for CE Channel - _scrubSetupChannelBufferSizes(pChannel, MAX_SCRUB_ITEMS); - - // Allocate Scrubber Channel related objects - NV_ASSERT_OK_OR_GOTO(status, - memmgrMemUtilsChannelInitialize_HAL(pGpu, pMemoryManager, pChannel), freechannel); - - NV_ASSERT_OK_OR_GOTO(status, - memmgrMemUtilsCopyEngineInitialize_HAL(pGpu, pMemoryManager, pChannel), freepartitionref); - - // Initialize semaphore location to 0 - WRITE_SCRUBBER_PB_SEMA(pChannel, 0); - WRITE_SCRUBBER_PAYLOAD_SEMA(pChannel, 0); - NV_ASSERT_OK_OR_GOTO(status, pmaRegMemScrub(pPma, pScrubber), freepartitionref); + NV_ASSERT_OK_OR_GOTO(status, ceutilsInitialize(&pScrubber->ceUtilsObject, pGpu, &ceUtilsAllocParams), destroyscrublist); + NV_ASSERT_OK_OR_GOTO(status, pmaRegMemScrub(pPma, pScrubber), destroyscrublist); } return status; -freepartitionref: - if(bMIGInUse) - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hPartitionRef); - -freechannel: - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); - -freeChannelObject: - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); - portMemFree(pScrubber->pChannel); - destroyscrublist: portMemFree(pScrubber->pScrubList); @@ -287,7 +192,7 @@ _isScrubWorkPending( } else { - if (pScrubber->pChannel->lastSubmittedEntry != READ_SCRUBBER_PB_SEMA(pScrubber->pChannel)) + if (pScrubber->lastSubmittedWorkId != ceutilsUpdateProgress(&pScrubber->ceUtilsObject)) workPending = NV_TRUE; } return workPending; @@ -311,9 +216,7 @@ scrubberDestruct OBJMEMSCRUB *pScrubber ) { - OBJCHANNEL *pChannel = NULL; PMA *pPma = NULL; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); PSCRUB_NODE pPmaScrubList = NULL; NvU64 count = 0; NV_STATUS status = NV_OK; @@ -330,8 +233,6 @@ scrubberDestruct pmaUnregMemScrub(pPma); portSyncMutexAcquire(pScrubber->pScrubberMutex); - pChannel = pScrubber->pChannel; - if (!API_GPU_IN_RESET_SANITY_CHECK(pGpu)) { RMTIMEOUT timeout; @@ -365,45 +266,7 @@ scrubberDestruct portMemFree(pScrubber->pScrubList); { - // Freeing channel first as in MODS case we don't wait for work to complete. Freeing VAS first causes MMU faults - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->channelId); - - if (pChannel->bClientUserd) - { - // scrub userd memory of scrubber channel as it may be allocated from PMA - NvU32 userdSize = 0; - - kfifoGetUserdSizeAlign_HAL(GPU_GET_KERNEL_FIFO(pGpu), &userdSize, NULL); - portMemSet((void*)pChannel->pControlGPFifo, 0, userdSize); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hUserD); - } - - if (pChannel->bUseVasForCeCopy) - { - // unmap the Identity mapping - status = pRmApi->Unmap(pRmApi, pChannel->hClient, pChannel->deviceId, - pChannel->hFbAliasVA, pChannel->hFbAlias, 0, pChannel->fbAliasVA); - - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Unmapping scrubber 1:1 Mapping, status: %x\n", status); - } - - // free the Alias memory in host - // this will not trigger scrubber - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hFbAliasVA); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hFbAlias); - } - - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->errNotifierIdPhys); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->pushBufferId); - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->errNotifierIdVirt); - if (pChannel->hVASpaceId) - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hVASpaceId); - - - pRmApi->Free(pRmApi, pChannel->hClient, pChannel->hClient); - portMemFree(pScrubber->pChannel); + ceutilsDeinit(&pScrubber->ceUtilsObject); } portSyncMutexRelease(pScrubber->pScrubberMutex); @@ -525,13 +388,13 @@ scrubSubmitPages { pScrubList = (PSCRUB_NODE) portMemAllocNonPaged((NvLength)(sizeof(SCRUB_NODE) * (pageCount - freeEntriesInList))); - + if (pScrubList == NULL) { status = NV_ERR_NO_MEMORY; goto cleanup; } - + while (freeEntriesInList < pageCount) { if (pageCount > MAX_SCRUB_ITEMS) @@ -767,7 +630,6 @@ _scrubCheckAndSubmit { NvU64 iter = 0; NvU64 newId; - OBJCHANNEL *pChannel; NV_STATUS status; if (pList == NULL && pagesToScrubCheck != 0) @@ -781,7 +643,6 @@ _scrubCheckAndSubmit for (iter = 0; iter < pageCount; iter++) { - pChannel = pScrubber->pChannel; newId = pScrubber->lastSubmittedWorkId + 1; NV_PRINTF(LEVEL_INFO, @@ -789,7 +650,7 @@ _scrubCheckAndSubmit newId, pPages[iter], chunkSize); { - status = _scrubMemory(pChannel, pPages[iter], chunkSize, ADDR_FBMEM, NV_MEMORY_DEFAULT, + status =_scrubMemory(pScrubber, pPages[iter], chunkSize, NV_MEMORY_DEFAULT, (NvU32)newId); } @@ -886,41 +747,13 @@ _scrubWaitAndSave while (currentCompletedId < (pScrubber->lastSeenIdByClient + itemsToSave)) { - _scrubOsSchedule(pScrubber->pChannel); + ceutilsServiceInterrupts(&pScrubber->ceUtilsObject); currentCompletedId = _scrubCheckProgress(pScrubber); } _scrubCopyListItems(pScrubber, pList, itemsToSave); } -/** - * helper function to yield when we wait for the scrubber to complete a work - */ -static void -_scrubOsSchedule(OBJCHANNEL *pChannel) -{ - // - // FIXME: Bug 2463959: objmemscrub is called with the rmDeviceGpuLock in the - // heapFree_IMPL->_stdmemPmaFree->pmaFreePages->scrubSubmitPages path. - // Yielding while holding the rmDeviceGpuLock can lead to deadlock. Instead, - // if the lock is held, service any interrupts on the owned CE to make progress. - // Bug 2527660 is filed to remove this change. - // - // pChannel is null when PMA scrub requests are handled in vGPU plugin. - // In this case vGpu plugin allocates scrubber channel in PF domain so - // above mention deadlock is not present here. - // - if ((pChannel != NULL) && (rmDeviceGpuLockIsOwner(pChannel->pGpu->gpuInstance))) - { - Intr *pIntr = GPU_GET_INTR(pChannel->pGpu); - intrServiceStallSingle_HAL(pChannel->pGpu, pIntr, MC_ENGINE_IDX_CE(pChannel->pKCe->publicID), NV_FALSE); - } - else - { - osSchedule(); - } - -} /** * helper function to find and wait for a specific work to complete @@ -979,76 +812,7 @@ _scrubAddWorkToList NV_ASSERT(_scrubGetFreeEntries(pScrubber) <= MAX_SCRUB_ITEMS); } -/** helper function to return methods size needed for a single operation in a - channel. currently only scrubber channel is supported. - */ -static NvU32 -_getOptimalMethodSizePerBlock -( - OBJCHANNEL *pChannel -) -{ - NvU32 methodSizePerBlock = 0; - switch(pChannel->type) - { - case SCRUBBER_CHANNEL: - { - // - // 6 1U methods -- 6 * 8 bytes = 48 bytes - // 1 2U methods -- 1 * 12 bytes = 12 bytes - // 1 3U methods -- 1 * 16 bytes = 16 bytes - // 1 4U methods -- 1 * 20 bytes = 20 bytes - // - methodSizePerBlock = SIZE_OF_ONE_MEMSET_BLOCK; // 0x60 - break; - } - case FAST_SCRUBBER_CHANNEL: - { - // - // 9 1U methods -- 9 * 8 bytes = 72 bytes - // 1 2U methods -- 1 * 12 bytes = 12 bytes - // 1 3U methods -- 1 * 16 bytes = 16 bytes - // 1 4U methods -- 1 * 20 bytes = 20 bytes - // - methodSizePerBlock = SIZE_OF_ONE_MEMSET_BLOCK + 24; // 0x78 - break; - } - // TODO: add the case for COPY CHANNEL. - default: - NV_ASSERT(NV_TRUE); - } - return methodSizePerBlock; -} - -/** - * helper function to set sizes for CE channel used by memory scrubber. - * Channel PB, GPFIFO and channel offsets are set for the numCopyBlock size - */ - -static void -_scrubSetupChannelBufferSizes -( - OBJCHANNEL *pChannel, - NvU32 numCopyBlocks -) -{ - NV_ASSERT(numCopyBlocks != 0); - NvU32 gpFifoSize = NV906F_GP_ENTRY__SIZE * numCopyBlocks; - - // set channel specific sizes - pChannel->methodSizePerBlock = _getOptimalMethodSizePerBlock(pChannel); - NV_ASSERT(pChannel->methodSizePerBlock != 0); - pChannel->channelPbSize = numCopyBlocks * (pChannel->methodSizePerBlock); - NV_ASSERT(pChannel->channelPbSize <= NV_U32_MAX); - pChannel->channelNotifierSize = SCRUBBER_CHANNEL_NOTIFIER_SIZE; - pChannel->channelNumGpFifioEntries = numCopyBlocks; - pChannel->channelSize = pChannel->channelPbSize + gpFifoSize + SCRUBBER_CHANNEL_SEMAPHORE_SIZE; - // Semaphore used to track PB and GPFIFO offset - pChannel->semaOffset = pChannel->channelPbSize + gpFifoSize; - // Semaphore used in work tracking for clients. - pChannel->finishPayloadOffset = pChannel->semaOffset + 4; -} /** * Scrubber uses 64 bit index to track the work submitted. But HW supports @@ -1063,415 +827,40 @@ _scrubCheckProgress OBJMEMSCRUB *pScrubber ) { - NvU32 hwCurrentCompletedId; - NvU64 lastSWSemaphoreDone; - OBJCHANNEL *pChannel; + NvU32 hwCurrentCompletedId; + NvU64 lastSWSemaphoreDone; NV_ASSERT(pScrubber != NULL); if (pScrubber->bVgpuScrubberEnabled) { hwCurrentCompletedId = pScrubber->vgpuScrubBuffRing.pScrubBuffRingHeader->lastSWSemaphoreDone; - } else - { - NV_ASSERT(pScrubber->pChannel != NULL); - pChannel = pScrubber->pChannel; - hwCurrentCompletedId = READ_SCRUBBER_PAYLOAD_SEMA(pChannel); - } - lastSWSemaphoreDone = pScrubber->lastSWSemaphoreDone; - - if (hwCurrentCompletedId == (NvU32)lastSWSemaphoreDone) - return lastSWSemaphoreDone; - - // check for wrap around case. Increment the upper 32 bits - if (hwCurrentCompletedId < (NvU32)lastSWSemaphoreDone) - { - lastSWSemaphoreDone += 0x100000000ULL; - } - - // update lower 32 bits - lastSWSemaphoreDone &= 0xFFFFFFFF00000000ULL; - lastSWSemaphoreDone |= (NvU64)hwCurrentCompletedId; - - pScrubber->lastSWSemaphoreDone = lastSWSemaphoreDone; - - return lastSWSemaphoreDone; -} - -/** helper function to push destination memory methods - */ -static NvU32 -_memsetPushDstProperties -( - OBJCHANNEL *pChannel, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvU32 **ppPtr -) -{ - NvU32 data = 0; - NvU32 *pPtr = *ppPtr; - NvU32 retVal = 0; - - if (dstAddressSpace == ADDR_FBMEM) - data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB); - else if (dstCpuCacheAttrib == NV_MEMORY_CACHED) - data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _COHERENT_SYSMEM); - else if (dstCpuCacheAttrib == NV_MEMORY_UNCACHED) - data = DRF_DEF(B0B5, _SET_DST_PHYS_MODE, _TARGET, _NONCOHERENT_SYSMEM); + lastSWSemaphoreDone = pScrubber->lastSWSemaphoreDone; - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_DST_PHYS_MODE, data); + if (hwCurrentCompletedId == (NvU32)lastSWSemaphoreDone) + return lastSWSemaphoreDone; - if (pChannel->bUseVasForCeCopy) - { - retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _VIRTUAL) | - DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _VIRTUAL); - } - else - { - retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | - DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL); - } - - *ppPtr = pPtr; - return retVal; -} - - -/** single helper function to fill the push buffer with the methods needed for - memsetting using CE. This function is much more efficient in the sense it - decouples the mem(set/copy) operation from managing channel resources. - TODO: Add support for memcopy here based on channel type. - */ -static NvU32 -_scrubFillPb -( - OBJCHANNEL *pChannel, - RmPhysAddr base, - NvU32 size, - NvU32 payload, - NvBool bPipelined, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvBool bInsertFinishpayload, - NvBool bNonStallInterrupt, - NvU32 putIndex -) -{ - NvU32 launchDestType = 0; - NvU32 semaValue = 0; - NvU32 pipelinedValue = 0; - NvU32 *pPtr =(NvU32 *)((NvU8*)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); - NvU32 *pStartPtr = pPtr; - NvU32 data = 0; - NvU64 pSemaAddr = 0; - NvU32 disablePlcKind = 0; - - NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, - putIndex * pChannel->methodSizePerBlock); - - // SET OBJECT - NV_PUSH_INC_1U(RM_SUBCHANNEL, NV906F_SET_OBJECT, pChannel->classEngineID); - // Set Pattern for Memset - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_REMAP_CONST_A, MEMSET_PATTERN); - // Set Component Size to 1 - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_REMAP_COMPONENTS, - DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | - DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | - DRF_DEF(B0B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); - - launchDestType = _memsetPushDstProperties - (pChannel, dstAddressSpace, dstCpuCacheAttrib, &pPtr); - - semaValue = (bInsertFinishpayload) ? - DRF_DEF(B0B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE) : 0; - - if (bPipelined) - pipelinedValue = DRF_DEF(B0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); - else - pipelinedValue = DRF_DEF(B0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); - - if (pChannel->bUseVasForCeCopy) - { - base = base + pChannel->fbAliasVA - pChannel->startFbOffset; - } - - NV_PUSH_INC_2U(RM_SUBCHANNEL, NVB0B5_OFFSET_OUT_UPPER, - DRF_NUM(B0B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(base)), - NVB0B5_OFFSET_OUT_LOWER, - DRF_NUM(B0B5, _OFFSET_OUT_LOWER, _VALUE,NvU64_LO32(base))); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LINE_LENGTH_IN, size); + // check for wrap around case. Increment the upper 32 bits + if (hwCurrentCompletedId < (NvU32)lastSWSemaphoreDone) + { + lastSWSemaphoreDone += 0x100000000ULL; + } - if (semaValue) - { - NV_PUSH_INC_3U(RM_SUBCHANNEL, NVB0B5_SET_SEMAPHORE_A, - DRF_NUM(B0B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), - NVB0B5_SET_SEMAPHORE_B, - DRF_NUM(B0B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), - NVB0B5_SET_SEMAPHORE_PAYLOAD, - payload); - } + // update lower 32 bits + lastSWSemaphoreDone &= 0xFFFFFFFF00000000ULL; + lastSWSemaphoreDone |= (NvU64)hwCurrentCompletedId; - switch (pChannel->hTdCopyClass) - { - case MAXWELL_DMA_COPY_A: - case PASCAL_DMA_COPY_A: - case PASCAL_DMA_COPY_B: - case VOLTA_DMA_COPY_A: - disablePlcKind = 0; - break; - default: // For anything after Turing, set the kind - disablePlcKind = DRF_DEF(C5B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE); - break; } - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LAUNCH_DMA, - DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | - DRF_DEF(B0B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | - DRF_DEF(B0B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | - DRF_DEF(B0B5, _LAUNCH_DMA, _REMAP_ENABLE, _TRUE) | - DRF_DEF(B0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE) | - disablePlcKind | - launchDestType | - pipelinedValue | - semaValue); - - data = DRF_DEF(906F, _SEMAPHORED, _OPERATION, _RELEASE) | - DRF_DEF(906F, _SEMAPHORED, _RELEASE_SIZE, _4BYTE) | - DRF_DEF(906F, _SEMAPHORED, _RELEASE_WFI, _DIS); - - pSemaAddr = (pChannel->pbGpuVA+pChannel->semaOffset); - // - // This should always be at the bottom the push buffer segment, since this - // denotes that HOST has read all the methods needed for this memory operation - // and safely assume that this GPFIFO and PB entry can be reused. - // - NV_PUSH_INC_4U(RM_SUBCHANNEL, NV906F_SEMAPHOREA, - DRF_NUM(906F, _SEMAPHOREA_OFFSET, _UPPER, NvU64_HI32(pSemaAddr)), - NV906F_SEMAPHOREB, - DRF_NUM(906F, _SEMAPHOREB_OFFSET, _LOWER, NvU64_LO32(pSemaAddr) >> 2), - NV906F_SEMAPHOREC, - putIndex, - NV906F_SEMAPHORED, data - ); - // typecasting to calculate the bytes consumed by this iteration. - return (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); -} - -/** single helper function to fill the push buffer with the methods needed for - memsetting using fast memory scrubber in CE. This function is much more efficient than - normal CE scrubber operation - TODO: Add support for memcopy here based on channel type. - */ -static NvU32 -_fastscrubFillPb -( - OBJCHANNEL *pChannel, - RmPhysAddr base, - NvU32 size, - NvU32 payload, - NvBool bPipelined, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvBool bInsertFinishpayload, - NvBool bNonStallInterrupt, - NvU32 putIndex -) -{ - NvU32 semaValue = 0; - NvU32 pipelinedValue = 0; - NvU32 *pPtr = (NvU32 *)((NvU8*)pChannel->pbCpuVA + (putIndex * pChannel->methodSizePerBlock)); - NvU32 *pStartPtr = pPtr; - NvU32 data = 0; - NvU64 pSemaAddr = 0; - - NV_PRINTF(LEVEL_INFO, "PutIndex: %x, PbOffset: %x\n", putIndex, - putIndex * pChannel->methodSizePerBlock); - - // SET OBJECT - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SET_OBJECT, pChannel->classEngineID); - - // Set Pattern for Memset - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_A, MEMSET_PATTERN); - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_CONST_B, MEMSET_PATTERN); - - // Set Component Size to 1 - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_REMAP_COMPONENTS, - DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | - DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_B) | - DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, _ONE) | - DRF_DEF(C8B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, _ONE)); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_DST_PHYS_MODE, - DRF_DEF(C8B5, _SET_DST_PHYS_MODE, _TARGET, _LOCAL_FB)); - - semaValue = (bInsertFinishpayload) ? - DRF_DEF(C8B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _RELEASE_ONE_WORD_SEMAPHORE) : 0; - - if (bPipelined) - pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED); else - pipelinedValue = DRF_DEF(C8B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _NON_PIPELINED); - - NV_PUSH_INC_2U(RM_SUBCHANNEL, NVC8B5_OFFSET_OUT_UPPER, - DRF_NUM(C8B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(base)), - NVC8B5_OFFSET_OUT_LOWER, - DRF_NUM(C8B5, _OFFSET_OUT_LOWER, _VALUE,NvU64_LO32(base))); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LINE_LENGTH_IN, size); - - if (semaValue) { - NV_PUSH_INC_3U(RM_SUBCHANNEL, NVC8B5_SET_SEMAPHORE_A, - DRF_NUM(C8B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), - NVC8B5_SET_SEMAPHORE_B, - DRF_NUM(C8B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA+pChannel->finishPayloadOffset)), - NVC8B5_SET_SEMAPHORE_PAYLOAD, - payload); + lastSWSemaphoreDone = ceutilsUpdateProgress(&pScrubber->ceUtilsObject); } + + pScrubber->lastSWSemaphoreDone = lastSWSemaphoreDone; - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_MEMORY_SCRUB_PARAMETERS, - DRF_DEF(C8B5, _SET_MEMORY_SCRUB_PARAMETERS, _DISCARDABLE, _FALSE)); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LAUNCH_DMA, - DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | - DRF_DEF(C8B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | - DRF_DEF(C8B5, _LAUNCH_DMA, _REMAP_ENABLE, _FALSE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _FALSE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _MEMORY_SCRUB_ENABLE, _TRUE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _DISABLE_PLC, _TRUE) | - DRF_DEF(C8B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | - DRF_DEF(C8B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL) | - pipelinedValue | - semaValue); - - // - // This should always be at the bottom the push buffer segment, since this - // denotes that HOST has read all the methods needed for this memory operation - // and safely assume that this GPFIFO and PB entry can be reused. - // - data = DRF_DEF(C86F, _SEM_EXECUTE, _OPERATION, _RELEASE) | - DRF_DEF(C86F, _SEM_EXECUTE, _PAYLOAD_SIZE, _32BIT) | - DRF_DEF(C86F, _SEM_EXECUTE, _RELEASE_WFI, _DIS); - - pSemaAddr = (pChannel->pbGpuVA+pChannel->semaOffset); - - NV_PUSH_INC_4U(RM_SUBCHANNEL, NVC86F_SEM_ADDR_LO, - DRF_NUM(C86F, _SEM_ADDR_LO, _OFFSET, NvU64_LO32(pSemaAddr) >> 2), - NVC86F_SEM_ADDR_HI, - DRF_NUM(C86F, _SEM_ADDR_HI, _OFFSET, NvU64_HI32(pSemaAddr)), - NVC86F_SEM_PAYLOAD_LO, putIndex, - NVC86F_SEM_PAYLOAD_HI, 0); - - NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC86F_SEM_EXECUTE, data); - - // typecasting to calculate the bytes consumed by this iteration. - return (NvU32)((NvU8*)pPtr - (NvU8*)pStartPtr); + return lastSWSemaphoreDone; } -/** helper function which waits for a PB & GPFIO entry to be read by HOST. - * After the HOST reads GPFIFO and PB entry, the semaphore will be released. - */ - -static NvU32 -_scrubWaitForFreeEntry -( - OBJCHANNEL *pChannel -) -{ - NvU32 putIndex = 0; - NvU32 getIndex = 0; - - putIndex = (pChannel->lastSubmittedEntry + 1) % MAX_SCRUB_ITEMS; - do - { - getIndex = READ_SCRUBBER_PB_SEMA(pChannel); - NV_PRINTF(LEVEL_INFO, "Get Index: %x, PayloadIndex: %x\n", getIndex, - READ_SCRUBBER_PAYLOAD_SEMA(pChannel)); - if (getIndex != putIndex) - { - break; - } - _scrubOsSchedule(pChannel); - } while(1); - return putIndex; -} - -/** helper function to fill GPFIFO entry with a pushbuffer segment. and kick - off the executiion by HOST. - */ - -static NV_STATUS -_scrubFillGpFifo -( - OBJCHANNEL *pChannel, - NvU32 putIndex, - NvU32 methodsLength -) -{ - NvU32 *pGpEntry; - NvU32 GpEntry0; - NvU32 GpEntry1; - NvU64 pbPutOffset; - OBJGPU *pGpu; - KernelBus *pKernelBus; - - NV_ASSERT(putIndex < pChannel->channelNumGpFifioEntries); - - pbPutOffset = (pChannel->pbGpuVA + (putIndex * pChannel->methodSizePerBlock)); - - - GpEntry0 = - DRF_DEF(906F, _GP_ENTRY0, _NO_CONTEXT_SWITCH, _FALSE) | - DRF_NUM(906F, _GP_ENTRY0, _GET, NvU64_LO32(pbPutOffset) >> 2); - GpEntry1 = - DRF_NUM(906F, _GP_ENTRY1, _GET_HI, NvU64_HI32(pbPutOffset)) | - DRF_NUM(906F, _GP_ENTRY1, _LENGTH, methodsLength >> 2) | - DRF_DEF(906F, _GP_ENTRY1, _LEVEL, _MAIN); - - pGpEntry = (NvU32 *)(((NvU8*)pChannel->pbCpuVA) + pChannel->channelPbSize + - (pChannel->lastSubmittedEntry * NV906F_GP_ENTRY__SIZE)); - - MEM_WR32(&pGpEntry[0], GpEntry0); - MEM_WR32(&pGpEntry[1], GpEntry1); - - // - // need to flush WRC buffer - // - osFlushCpuWriteCombineBuffer(); - - // - // write GP put - // - MEM_WR32(&pChannel->pControlGPFifo->GPPut, putIndex); - osFlushCpuWriteCombineBuffer(); - - // - // On some architectures, if doorbell is mapped via bar0, we need to send - // an extra flush - // - pGpu = pChannel->pGpu; - pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - if (kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus)!= NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Busflush failed in _scrubFillGpFifo\n"); - return NV_ERR_GENERIC; - } - - // - // removing the FIFO Lite Mode handling - // Refer older _ceChannelUpdateGpFifo_GF100 code for implementation - // - if (pChannel->bUseDoorbellRegister) - { - // Use the token from notifier memory for VM migration support. - MEM_WR32(pChannel->pDoorbellRegisterOffset, - MEM_RD32(&(pChannel->pTokenFromNotifier->info32))); - } - return NV_OK; -} /** Single function to memset a surface mapped by GPU. This interface supports both sysmem and vidmem surface, since it uses CE to memset a surface. @@ -1480,63 +869,33 @@ _scrubFillGpFifo static NV_STATUS _scrubMemory ( - OBJCHANNEL *pChannel, - RmPhysAddr base, - NvU64 size, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvU32 payload + OBJMEMSCRUB *pScrubber, + RmPhysAddr base, + NvU64 size, + NvU32 dstCpuCacheAttrib, + NvU32 payload ) { - NvBool bFirstIteration = NV_TRUE; - NvBool bNonStallInterrupt = NV_FALSE; - NvU32 tempMemsetSize = 0; // HW supports copy size 32 bits only - NvU32 putIndex = 0; - NV_STATUS status = NV_OK; - NvU32 methodsLength = 0; - NvBool bFastScrubEnable = NV_FALSE; - - do - { - tempMemsetSize = (NvU32)NV_MIN(size, SCRUB_MAX_BYTES_PER_LINE); - - //poll for free entry - putIndex = _scrubWaitForFreeEntry(pChannel); - NV_PRINTF(LEVEL_INFO, "Put Index: %x\n", putIndex); - - // Fill PB with methods - bFastScrubEnable = memmgrMemUtilsCheckMemoryFastScrubEnable_HAL(pChannel->pGpu, - GPU_GET_MEMORY_MANAGER(pChannel->pGpu), pChannel->hTdCopyClass, - pChannel->bUseVasForCeCopy, base, tempMemsetSize, - dstAddressSpace); - - if (bFastScrubEnable) - { - NV_PRINTF(LEVEL_INFO, "Fast Scrubber enabled!\n"); - methodsLength = _fastscrubFillPb(pChannel, base, tempMemsetSize, payload, - bFirstIteration, dstAddressSpace, - dstCpuCacheAttrib, (tempMemsetSize == size), - bNonStallInterrupt, putIndex); - } - else - { - NV_PRINTF(LEVEL_INFO, "Fast Scrubber not enabled!\n"); - methodsLength = _scrubFillPb(pChannel, base, tempMemsetSize, payload, - bFirstIteration, dstAddressSpace, - dstCpuCacheAttrib, (tempMemsetSize == size), - bNonStallInterrupt, putIndex); - } + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + CEUTILS_MEMSET_PARAMS memsetParams = {0}; + + status = memdescCreate(&pMemDesc, pScrubber->pGpu, size, 0, NV_TRUE, + ADDR_FBMEM, dstCpuCacheAttrib, MEMDESC_FLAGS_NONE); + NV_ASSERT_OR_RETURN(status == NV_OK, status); - NV_PRINTF(LEVEL_INFO, "MethodLength: %x\n", methodsLength); - // Add the PB entry in GP FIFO - status = _scrubFillGpFifo(pChannel, putIndex, methodsLength); + memdescDescribe(pMemDesc, ADDR_FBMEM, base, size); - pChannel->lastSubmittedEntry = putIndex; + memsetParams.pMemDesc = pMemDesc; + memsetParams.length = size; + memsetParams.flags = NV0050_CTRL_MEMSET_FLAGS_ASYNC; - base += tempMemsetSize; - size -= tempMemsetSize; - bFirstIteration = NV_FALSE; - } while (size > 0); + status = ceutilsMemset(&pScrubber->ceUtilsObject, &memsetParams); + if (status == NV_OK) + { + pScrubber->lastSubmittedWorkId = memsetParams.submittedWorkId; + } + memdescDestroy(pMemDesc); return status; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c index 35f4acdd18..c19e7395f1 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,6 +27,7 @@ #include "gpu/mem_mgr/virt_mem_allocator_common.h" #include "os/nv_memory_type.h" #include "core/locks.h" +#include "ctrl/ctrl2080.h" #include "gpu/bus/kern_bus.h" @@ -42,10 +43,364 @@ static TRANSFER_TYPE memmgrGetMemTransferType ( - MemoryManager *pMemoryManager + MemoryManager *pMemoryManager, + TRANSFER_SURFACE *pDst, + TRANSFER_SURFACE *pSrc +) +{ + TRANSFER_TYPE transferType = TRANSFER_TYPE_PROCESSOR; + OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + // + // In case of copy, both dest and src will be passed + // In case of memset/memread/memwrite either dest or src will be passed + // + if ((pDst != NULL) && (pSrc != NULL) && + (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) && + (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM)) + { + transferType = TRANSFER_TYPE_PROCESSOR; + } + else if (((pDst != NULL) && + (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM)) || + ((pSrc != NULL) && + (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM))) + { + transferType = TRANSFER_TYPE_PROCESSOR; + } + else if (kbusIsBarAccessBlocked(pKernelBus)) + { + transferType = TRANSFER_TYPE_GSP_DMA; + } + return transferType; +} + +static NV_STATUS +_memmgrAllocAndMapSurface +( + OBJGPU *pGpu, + NvU64 size, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMap, + void **ppPriv +) +{ + NV_STATUS status; + NvU64 flags = 0; + + NV_ASSERT_OR_RETURN(ppMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(ppMap != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(ppPriv != NULL, NV_ERR_INVALID_ARGUMENT); + + flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + NV_ASSERT_OK_OR_RETURN( + memdescCreate(ppMemDesc, pGpu, size, RM_PAGE_SIZE, NV_TRUE, + ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags)); + + NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemDesc), failed); + + NV_ASSERT_OK_OR_GOTO(status, + memdescMapOld(*ppMemDesc, 0, size, NV_TRUE, NV_PROTECT_READ_WRITE, + ppMap, ppPriv), + failed); + + // Clear surface before use + portMemSet(*ppMap, 0, size); + + return NV_OK; +failed: + memdescFree(*ppMemDesc); + memdescDestroy(*ppMemDesc); + + *ppMemDesc = NULL; + *ppMap = NULL; + *ppPriv = NULL; + + return status; +} + +static void +_memmgrUnmapAndFreeSurface +( + MEMORY_DESCRIPTOR *pMemDesc, + void *pMap, + void *pPriv ) { - return TRANSFER_TYPE_PROCESSOR; + memdescUnmapOld(pMemDesc, NV_TRUE, 0, pMap, pPriv); + + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); +} + +/*! + * @brief This function is used for writing/reading data to/from a client + * provided buffer from/to some source region in vidmem + * + * @param[in] pDst TRANSFER_SURFACE info for destination region + * @param[in] pBuf Client provided buffer + * @param[in] size Size in bytes of the memory transfer + * @param[in] bRead TRUE for read and FALSE for write + */ +static NV_STATUS +_memmgrMemReadOrWriteWithGsp +( + OBJGPU *pGpu, + TRANSFER_SURFACE *pDst, + void *pBuf, + NvU64 size, + NvBool bRead +) +{ + NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS gspParams; + NV_STATUS status; + MEMORY_DESCRIPTOR *pStagingBuf = NULL; + void *pStagingBufMap = NULL; + void *pStagingBufPriv = NULL; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // Do not expect GSP to be used for reading/writing from/to sysmem + if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) + return NV_ERR_NOT_SUPPORTED; + + // Allocate and map the staging buffer + NV_ASSERT_OK_OR_RETURN( + _memmgrAllocAndMapSurface(pGpu, size, &pStagingBuf, &pStagingBufMap, + &pStagingBufPriv)); + + // Copy the data to staging buffer before poking GSP for copying + if (!bRead) + portMemCopy(pStagingBufMap, size, pBuf, size); + + // Setup control call params + portMemSet(&gspParams, 0, sizeof(gspParams)); + + gspParams.memop = NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY; + gspParams.transferSize = size; + + if (bRead) + { + // Source surface in vidmem + gspParams.src.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.src.size = memdescGetSize(pDst->pMemDesc); + gspParams.src.offset = pDst->offset; + gspParams.src.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.src.aperture = memdescGetAddressSpace(pDst->pMemDesc); + + // Destination surface in unprotected sysmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pStagingBuf); + gspParams.dst.offset = 0; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pStagingBuf); + gspParams.dst.aperture = memdescGetAddressSpace(pStagingBuf); + } + else + { + // Source surface in unprotected sysmem + gspParams.src.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); + gspParams.src.size = memdescGetSize(pStagingBuf); + gspParams.src.offset = 0; + gspParams.src.cpuCacheAttrib = memdescGetCpuCacheAttrib(pStagingBuf); + gspParams.src.aperture = memdescGetAddressSpace(pStagingBuf); + + // Destination surface in vidmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pDst->pMemDesc); + gspParams.dst.offset = pDst->offset; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.dst.aperture = memdescGetAddressSpace(pDst->pMemDesc); + } + + // Send the control call + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP, + &gspParams, + sizeof(gspParams)), + failed); + + // Read contents from staging buffer after GSP is done copying + if (bRead) + portMemCopy(pBuf, size, pStagingBufMap, size); + +failed: + _memmgrUnmapAndFreeSurface(pStagingBuf, pStagingBufMap, pStagingBufPriv); + return status; +} + +/*! + * @brief This function is used for copying data b/w two memory regions + * using GSP. + * + * @param[in] pDst TRANSFER_SURFACE info for destination region + * @param[in] pSrc TRANSFER_SURFACE info for source region + * @param[in] size Size in bytes of the memory transfer + */ +static NV_STATUS +_memmgrMemcpyWithGsp +( + OBJGPU *pGpu, + TRANSFER_SURFACE *pDst, + TRANSFER_SURFACE *pSrc, + NvU64 size +) +{ + NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS gspParams; + NV_STATUS status; + MEMORY_DESCRIPTOR *pStagingBuf = NULL; + void *pStagingBufMap = NULL; + void *pStagingBufPriv = NULL; + NvU8 *pMap = NULL; + void *pPriv = NULL; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // + // Do not expect GSP to be used for copying data b/w two surfaces + // in sysmem. For SPT, there is no non-CPR vidmem. So, allow vidmem + // to vidmem copies in plain text. For copies b/w CPR and non-CPR + // vidmem, encryption/decryption needs to happen at the endpoints. + // + if (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM && + memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) + { + return NV_ERR_NOT_SUPPORTED; + } + + // Allocate and map the bounce buffer + NV_ASSERT_OK_OR_RETURN( + _memmgrAllocAndMapSurface(pGpu, size, &pStagingBuf, &pStagingBufMap, + &pStagingBufPriv)); + + // Setup control call params + portMemSet(&gspParams, 0, sizeof(gspParams)); + + gspParams.memop = NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY; + gspParams.transferSize = size; + + if (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM) + { + NV_ASSERT_OK_OR_GOTO(status, + memdescMapOld(pSrc->pMemDesc, 0, size, NV_TRUE, + NV_PROTECT_READ_WRITE, (void**)&pMap, &pPriv), + failed); + + // Copy to staging buffer + portMemCopy(pStagingBufMap, size, pMap + pSrc->offset, size); + + memdescUnmapOld(pSrc->pMemDesc, NV_TRUE, 0, (void*)pMap, pPriv); + + // Source surface in unprotected sysmem + gspParams.src.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); + gspParams.src.size = memdescGetSize(pStagingBuf); + gspParams.src.offset = 0; + gspParams.src.cpuCacheAttrib = memdescGetCpuCacheAttrib(pStagingBuf); + gspParams.src.aperture = memdescGetAddressSpace(pStagingBuf); + + // Destination surface in vidmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pDst->pMemDesc); + gspParams.dst.offset = pDst->offset; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.dst.aperture = memdescGetAddressSpace(pDst->pMemDesc); + } + else + { + // Source surface in vidmem + gspParams.src.baseAddr = memdescGetPhysAddr(pSrc->pMemDesc, AT_GPU, 0); + gspParams.src.size = memdescGetSize(pSrc->pMemDesc); + gspParams.src.offset = pSrc->offset; + gspParams.src.cpuCacheAttrib = memdescGetCpuCacheAttrib(pSrc->pMemDesc); + gspParams.src.aperture = memdescGetAddressSpace(pSrc->pMemDesc); + + if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_FBMEM) + { + // Destination surface in vidmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pDst->pMemDesc); + gspParams.dst.offset = pDst->offset; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.dst.aperture = memdescGetAddressSpace(pDst->pMemDesc); + } + else + { + // Destination surface in unprotected sysmem + gspParams.dst.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pStagingBuf); + gspParams.dst.offset = 0; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pStagingBuf); + gspParams.dst.aperture = memdescGetAddressSpace(pStagingBuf); + } + } + + // Send the control call + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP, + &gspParams, + sizeof(gspParams)), + failed); + + // Copy from staging buffer to destination + if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) + { + NV_ASSERT_OK_OR_GOTO(status, + memdescMapOld(pDst->pMemDesc, 0, size, NV_TRUE, + NV_PROTECT_READ_WRITE, (void**)&pMap, &pPriv), + failed); + + portMemCopy(pMap + pDst->offset, size, pStagingBufMap, size); + + memdescUnmapOld(pDst->pMemDesc, NV_TRUE, 0, (void*)pMap, pPriv); + } + +failed: + _memmgrUnmapAndFreeSurface(pStagingBuf, pStagingBufMap, pStagingBufPriv); + return status; +} + +static NV_STATUS +_memmgrMemsetWithGsp +( + OBJGPU *pGpu, + TRANSFER_SURFACE *pDst, + NvU32 value, + NvU64 size +) +{ + NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS gspParams; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // Do not expect to use GSP to memset surfaces in sysmem + if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) + return NV_ERR_NOT_SUPPORTED; + + portMemSet(&gspParams, 0, sizeof(gspParams)); + + gspParams.memop = NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET; + gspParams.transferSize = size; + gspParams.value = value; + gspParams.dst.baseAddr = memdescGetPhysAddr(pDst->pMemDesc, AT_GPU, 0); + gspParams.dst.size = memdescGetSize(pDst->pMemDesc); + gspParams.dst.offset = pDst->offset; + gspParams.dst.cpuCacheAttrib = memdescGetCpuCacheAttrib(pDst->pMemDesc); + gspParams.dst.aperture = memdescGetAddressSpace(pDst->pMemDesc); + + // Send the control call + NV_ASSERT_OK_OR_RETURN( + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP, + &gspParams, + sizeof(gspParams))); + + return NV_OK; } /*! @@ -100,7 +455,16 @@ memmgrMemCopyWithTransferType memdescUnmapInternal(pGpu, pDstInfo->pMemDesc, flags); break; case TRANSFER_TYPE_GSP_DMA: - NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); + if (IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Calling GSP DMA task\n"); + NV_ASSERT_OK_OR_RETURN( + _memmgrMemcpyWithGsp(pGpu, pDstInfo, pSrcInfo, size)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } break; case TRANSFER_TYPE_CE: NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); @@ -151,7 +515,16 @@ memmgrMemSetWithTransferType memdescUnmapInternal(pGpu, pDstInfo->pMemDesc, flags); break; case TRANSFER_TYPE_GSP_DMA: - NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); + if (IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Calling GSP DMA task\n"); + NV_ASSERT_OK_OR_RETURN( + _memmgrMemsetWithGsp(pGpu, pDstInfo, value, size)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } break; case TRANSFER_TYPE_CE: NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); @@ -179,7 +552,7 @@ memmgrMemWriteMapAndCopy void *pBuf, NvU64 offset, NvU64 size, - NvU32 flags + NvU32 flags ) { NvU8 *pDst = NULL; @@ -231,9 +604,9 @@ memmgrMemWriteInBlocks NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, memdescCreateSubMem(&pSubMemDesc, pMemDesc, pGpu, offset + baseOffset, mapSize)); // Set the offset to 0, as the sub descriptor already starts at the offset - status = memmgrMemWriteMapAndCopy(pMemoryManager, pSubMemDesc, (NvU8 *)pBuf + offset, + status = memmgrMemWriteMapAndCopy(pMemoryManager, pSubMemDesc, (NvU8 *)pBuf + offset, 0, mapSize, flags); - + memdescFree(pSubMemDesc); memdescDestroy(pSubMemDesc); @@ -266,6 +639,7 @@ memmgrMemWriteWithTransferType ) { NvU8 *pMapping = memdescGetKernelMapping(pDstInfo->pMemDesc); + OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); // Sanitize the input NV_ASSERT_OR_RETURN(pDstInfo != NULL, NV_ERR_INVALID_ARGUMENT); @@ -291,7 +665,17 @@ memmgrMemWriteWithTransferType } break; case TRANSFER_TYPE_GSP_DMA: - NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); + if (IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Calling GSP DMA task\n"); + NV_ASSERT_OK_OR_RETURN( + _memmgrMemReadOrWriteWithGsp(pGpu, pDstInfo, pBuf, size, + NV_FALSE /* bRead */)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } break; case TRANSFER_TYPE_CE: NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); @@ -352,7 +736,17 @@ memmgrMemReadWithTransferType memdescUnmapInternal(pGpu, pSrcInfo->pMemDesc, 0); break; case TRANSFER_TYPE_GSP_DMA: - NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); + if (IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Calling GSP DMA task\n"); + NV_ASSERT_OK_OR_RETURN( + _memmgrMemReadOrWriteWithGsp(pGpu, pSrcInfo, pBuf, size, + NV_TRUE /* bRead */)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } break; case TRANSFER_TYPE_CE: NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); @@ -479,7 +873,8 @@ memmgrMemCopy_IMPL NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pDstInfo, pSrcInfo); return memmgrMemCopyWithTransferType(pMemoryManager, pDstInfo, pSrcInfo, size, transferType, flags); @@ -503,7 +898,8 @@ memmgrMemSet_IMPL NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pDstInfo, NULL); return memmgrMemSetWithTransferType(pMemoryManager, pDstInfo, value, size, transferType, flags); @@ -526,7 +922,8 @@ memmgrMemDescMemSet_IMPL ) { TRANSFER_SURFACE transferSurface = {.offset = 0, .pMemDesc = pMemDesc}; - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + &transferSurface, NULL); return memmgrMemSetWithTransferType(pMemoryManager, &transferSurface, value, (NvU32)memdescGetSize(pMemDesc), @@ -552,7 +949,8 @@ memmgrMemWrite_IMPL NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pDstInfo, NULL); return memmgrMemWriteWithTransferType(pMemoryManager, pDstInfo, pBuf, size, transferType, flags); @@ -577,7 +975,8 @@ memmgrMemRead_IMPL NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + NULL, pSrcInfo); return memmgrMemReadWithTransferType(pMemoryManager, pSrcInfo, pBuf, size, transferType, flags); @@ -599,7 +998,8 @@ memmgrMemBeginTransfer_IMPL NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pTransferInfo, NULL); MEMORY_DESCRIPTOR *pMemDesc = pTransferInfo->pMemDesc; NvU64 offset = pTransferInfo->offset; OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); @@ -636,7 +1036,7 @@ memmgrMemBeginTransfer_IMPL } NV_ASSERT_OR_RETURN((pPtr = memdescMapInternal(pGpu, pMemDesc, flags)) != NULL, NULL); pPtr = &pPtr[offset]; - + break; case TRANSFER_TYPE_GSP_DMA: case TRANSFER_TYPE_CE: @@ -672,7 +1072,8 @@ memmgrMemEndTransfer_IMPL NvU32 flags ) { - TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager); + TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, + pTransferInfo, NULL); MEMORY_DESCRIPTOR *pMemDesc = pTransferInfo->pMemDesc; NvU64 offset = pTransferInfo->offset; OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); @@ -910,7 +1311,7 @@ memmgrAllocResources_IMPL (addrSpace == ADDR_FBMEM)) { OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU32 hostPageSize = pSys->cpuInfo.hostPageSize; + NvU64 hostPageSize = pSys->cpuInfo.hostPageSize; // hostPageSize *should* always be set, but.... if (hostPageSize == 0) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c index be05353a7e..68edc4f8cf 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -286,7 +286,7 @@ NV_STATUS notifyFillNotifierArray NV_STATUS notifyFillNotifierGPUVATimestamp ( OBJGPU *pGpu, - NvHandle hClient, + RsClient *pClient, NvHandle hMemoryCtx, NvU64 NotifyGPUVABase, NvV32 Info32, @@ -302,14 +302,9 @@ NV_STATUS notifyFillNotifierGPUVATimestamp NvU64 offset; NvU32 subdeviceInstance; NOTIFICATION *pNotifier; - RsClient *pClient; Device *pDevice; NV_STATUS status; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return status; - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); if (status != NV_OK) return status; @@ -317,7 +312,7 @@ NV_STATUS notifyFillNotifierGPUVATimestamp notifyGPUVA = NotifyGPUVABase + (Index * sizeof(NOTIFICATION)); // Memory context is required for mapping lookup - bFound = CliGetDmaMappingInfo(hClient, + bFound = CliGetDmaMappingInfo(pClient, RES_GET_HANDLE(pDevice), hMemoryCtx, notifyGPUVA, @@ -395,7 +390,7 @@ NV_STATUS notifyFillNotifierGPUVATimestamp NV_STATUS notifyFillNotifierGPUVA ( OBJGPU *pGpu, - NvHandle hClient, + RsClient *pClient, NvHandle hMemoryCtx, NvU64 NotifyGPUVABase, NvV32 Info32, @@ -410,7 +405,7 @@ NV_STATUS notifyFillNotifierGPUVA tmrGetCurrentTime(pTmr, &Time); return notifyFillNotifierGPUVATimestamp(pGpu, - hClient, + pClient, hMemoryCtx, NotifyGPUVABase, Info32, @@ -449,6 +444,9 @@ NV_STATUS notifyFillNotifierMemoryTimestamp ) { NvNotification * pDebugNotifier = NULL; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + TRANSFER_SURFACE surf = {0}; // // Check if there's already a CPU mapping we can use. If not, attempt to @@ -458,21 +456,34 @@ NV_STATUS notifyFillNotifierMemoryTimestamp pDebugNotifier = (NvNotification *)((NvUPtr)pMemory->KernelVAddr); if (pDebugNotifier == NULL) { - pDebugNotifier = (NvNotification *) kbusMapRmAperture_HAL(pGpu, - pMemory->pMemDesc); - if (pDebugNotifier == NULL) - { - return NV_ERR_GENERIC; - } + surf.pMemDesc = pMemory->pMemDesc; + surf.offset = Index * sizeof(NvNotification); + + pDebugNotifier = + (NvNotification *) memmgrMemBeginTransfer(pMemoryManager, &surf, + sizeof(NvNotification), + TRANSFER_FLAGS_SHADOW_ALLOC); + NV_ASSERT_OR_RETURN(pDebugNotifier != NULL, NV_ERR_INVALID_STATE); + } + else + { + // + // If a CPU pointer has been passed by caller ensure that the notifier + // is in sysmem or in case it in vidmem, BAR access to the same is not + // blocked (for HCC) + // + NV_ASSERT_OR_RETURN( + memdescGetAddressSpace(pMemory->pMemDesc) == ADDR_SYSMEM || + !kbusIsBarAccessBlocked(pKernelBus), NV_ERR_INVALID_ARGUMENT); + pDebugNotifier = &pDebugNotifier[Index]; } - notifyFillNvNotification(pGpu, &pDebugNotifier[Index], Info32, Info16, + notifyFillNvNotification(pGpu, pDebugNotifier, Info32, Info16, CompletionStatus, NV_TRUE, Time); if (pMemory->KernelVAddr == NvP64_NULL) { - kbusUnmapRmAperture_HAL(pGpu, pMemory->pMemDesc, - (NvU8 **)&pDebugNotifier, NV_TRUE); + memmgrMemEndTransfer(pMemoryManager, &surf, sizeof(NvNotification), 0); } return NV_OK; @@ -541,7 +552,7 @@ NV_STATUS notifyFillNotifierMemory NV_STATUS semaphoreFillGPUVATimestamp ( OBJGPU *pGpu, - NvHandle hClient, + RsClient *pClient, NvHandle hMemCtx, NvU64 SemaphoreGPUVABase, NvV32 ReleaseValue, @@ -559,14 +570,9 @@ NV_STATUS semaphoreFillGPUVATimestamp NvGpuSemaphore *pSemaphore; NvBool bBcState = gpumgrGetBcEnabledStatus(pGpu); NvBool bFound; - RsClient *pClient; Device *pDevice; NV_STATUS status; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return status; - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); if (status != NV_OK) return status; @@ -581,7 +587,7 @@ NV_STATUS semaphoreFillGPUVATimestamp return NV_ERR_INVALID_ARGUMENT; } - bFound = CliGetDmaMappingInfo(hClient, + bFound = CliGetDmaMappingInfo(pClient, RES_GET_HANDLE(pDevice), hMemCtx, semaphoreGPUVA, @@ -664,7 +670,7 @@ NV_STATUS semaphoreFillGPUVATimestamp NV_STATUS semaphoreFillGPUVA ( OBJGPU *pGpu, - NvHandle hClient, + RsClient *pClient, NvHandle hMemCtx, NvU64 SemaphoreGPUVABase, NvV32 ReleaseValue, @@ -678,7 +684,7 @@ NV_STATUS semaphoreFillGPUVA tmrGetCurrentTime(pTmr, &Time); return semaphoreFillGPUVATimestamp(pGpu, - hClient, + pClient, hMemCtx, SemaphoreGPUVABase, ReleaseValue, diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c index ee66b4ea89..45f1f7c05e 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c @@ -82,8 +82,8 @@ pmaAddrtreePrintLevel(ADDRTREE_LEVEL *pLevel) pNode->seeChild[mapIndex], i, pNode->state[mapIndex]); // In case compiler complains when the above print is compiled out - pNode = pNode; - mapIndex = mapIndex; + (void)pNode; + (void)mapIndex; } } @@ -165,6 +165,13 @@ pmaAddrtreeInit pPmaStats->num2mbPages += num2mbPages; pPmaStats->numFree2mbPages += num2mbPages; + if (bProtected) + { + pPmaStats->numFreeFramesProtected += newTree->totalFrames; + pPmaStats->num2mbPagesProtected += num2mbPages; + pPmaStats->numFree2mbPagesProtected += num2mbPages; + } + newTree->bProtected = bProtected; newTree->pPmaStats = pPmaStats; @@ -311,6 +318,12 @@ void pmaAddrtreeDestroy(void *pMap) pTree->pPmaStats->numFreeFrames -= pTree->totalFrames; pTree->pPmaStats->numFree2mbPages -= num2mbPages; + if (pTree->bProtected) + { + pTree->pPmaStats->numFreeFramesProtected -= pTree->totalFrames; + pTree->pPmaStats->numFree2mbPagesProtected -= num2mbPages; + } + portMemFree(pTree->root); portMemFree(pTree->levels); @@ -1013,7 +1026,7 @@ _pmaAddrtreeScanContiguous NvU64 rangeEnd, NvU64 numPages, NvU64 *freeList, - NvU32 pageSize, + NvU64 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, NvBool bSkipEvict, @@ -1034,7 +1047,7 @@ _pmaAddrtreeScanContiguous level = addrtreeGetTreeLevel(pageSize); if (level == 0) { - NV_PRINTF(LEVEL_ERROR, "address tree cannot handle page size 0x%x\n", + NV_PRINTF(LEVEL_ERROR, "address tree cannot handle page size 0x%llx\n", pageSize); return NV_ERR_INVALID_ARGUMENT; } @@ -1110,7 +1123,7 @@ pmaAddrtreeScanContiguous NvU64 rangeEnd, NvU64 numPages, NvU64 *freeList, - NvU32 pageSize, + NvU64 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, NvBool bSkipEvict, @@ -1224,7 +1237,7 @@ _pmaAddrtreeScanDiscontiguous NvU64 rangeEnd, NvU64 numPages, NvU64 *freeList, - NvU32 pageSize, + NvU64 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, NvBool bSkipEvict, @@ -1244,7 +1257,7 @@ _pmaAddrtreeScanDiscontiguous level = addrtreeGetTreeLevel(pageSize); if (level == 0) { - NV_PRINTF(LEVEL_ERROR, "address tree cannot handle page size 0x%x\n", + NV_PRINTF(LEVEL_ERROR, "address tree cannot handle page size 0x%llx\n", pageSize); return NV_ERR_INVALID_ARGUMENT; } @@ -1315,7 +1328,7 @@ pmaAddrtreeScanDiscontiguous NvU64 rangeEnd, NvU64 numPages, NvU64 *freeList, - NvU32 pageSize, + NvU64 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, NvBool bSkipEvict, @@ -1758,7 +1771,7 @@ __pmaAddrtreeChangePageStateAttribEx ( void *pMap, NvU64 frameNumStart, - NvU32 pageSize, + NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask ) @@ -1816,11 +1829,18 @@ __pmaAddrtreeChangePageStateAttribEx pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPages, num2mbFramesTouched, targetFoundState, updatedState); + if (pTree->bProtected) + { + pmaStatsUpdateState(&pTree->pPmaStats->numFreeFramesProtected, + numFramesTouched, targetFoundState, updatedState); + pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPagesProtected, + num2mbFramesTouched, targetFoundState, updatedState); + } } else { // Do unoptimized case - NvU32 framesPerPage = pageSize >> PMA_PAGE_SHIFT; + NvU32 framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); NvU32 j; for (j = 0; j < framesPerPage; j++) @@ -1842,6 +1862,12 @@ __pmaAddrtreeChangePageStateAttribEx pmaStatsUpdateState(&pTree->pPmaStats->numFreeFrames, 1, oldState, updatedState); + if (pTree->bProtected) + { + pmaStatsUpdateState(&pTree->pPmaStats->numFreeFramesProtected, + 1, oldState, updatedState); + } + updatedState2mb = pmaAddrtreeReadLevel(pTree, levelNum2mb, frameNum2mb, NV_TRUE); if (updatedState2mb != oldState2mb) @@ -1849,6 +1875,11 @@ __pmaAddrtreeChangePageStateAttribEx pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPages, 1, oldState2mb, updatedState2mb); + if (pTree->bProtected) + { + pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPagesProtected, 1, + oldState2mb, updatedState2mb); + } } } @@ -1864,7 +1895,7 @@ _pmaAddrtreeChangePageStateAttribEx ( void *pMap, NvU64 frameNumStart, - NvU32 pageSize, + NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask ) @@ -1930,7 +1961,7 @@ pmaAddrtreeChangePageStateAttrib ( void * pTree, NvU64 frameNumStart, - NvU32 pageSize, + NvU64 pageSize, PMA_PAGESTATUS newState, NvBool writeAttrib ) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c index 66da55152e..a5f3e89b9a 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,7 +47,7 @@ static NV_STATUS _pmaNumaAvailableEvictableRange(PMA *pPma, NvS32 *validRegionLi static NV_STATUS _pmaNumaAllocateRange(PMA *pPma, NvU32 numaNodeId, NvLength actualSize, NvU64 pageSize, NvU64 *pPages, NvBool bScrubOnAlloc, NvBool allowEvict, NvS32 *validRegionList, NvU64 *allocatedCount); -static NV_STATUS _pmaNumaAllocatePages (PMA *pPma, NvU32 numaNodeId, NvU32 pageSize, +static NV_STATUS _pmaNumaAllocatePages (PMA *pPma, NvU32 numaNodeId, NvU64 pageSize, NvLength allocationCount, NvU64 *pPages, NvBool bScrubOnAlloc, NvBool allowEvict, NvS32 *validRegionList, NvU64 *allocatedPages); @@ -163,7 +163,7 @@ NV_STATUS _pmaNumaAvailableEvictableRange */ static NvBool _pmaCheckFreeFramesToSkipReclaim(PMA *pPma) { - return (100 * pPma->pmaStats.numFreeFrames < + return (100 * pPma->pmaStats.numFreeFrames < (pPma->pmaStats.num2mbPages * (_PMA_2MB >> PMA_PAGE_SHIFT) * pPma->numaReclaimSkipThreshold)); } @@ -319,7 +319,7 @@ static NV_STATUS _pmaNumaAllocatePages ( PMA *pPma, NvU32 numaNodeId, - NvU32 pageSize, + NvU64 pageSize, NvLength allocationCount, NvU64 *pPages, NvBool bScrubOnAlloc, @@ -465,7 +465,7 @@ NV_STATUS pmaNumaAllocate ( PMA *pPma, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages ) @@ -493,9 +493,9 @@ NV_STATUS pmaNumaAllocate return NV_ERR_INVALID_ARGUMENT; } - if (pageSize > _PMA_2MB) + if (pageSize > _PMA_512MB) { - NV_PRINTF(LEVEL_FATAL, "Cannot allocate with more than 2MB contiguity.\n"); + NV_PRINTF(LEVEL_FATAL, "Cannot allocate with more than 512MB contiguity.\n"); return NV_ERR_INVALID_ARGUMENT; } @@ -523,7 +523,7 @@ NV_STATUS pmaNumaAllocate // caller does not want to skip scrubber. // Caller may want to skip scrubber when it knows the memory is zero'ed or when we are // initializing RM structures needed by the scrubber itself. - // + // if (pPma->bScrubOnFree && !bSkipScrubFlag) { portSyncMutexAcquire(pPma->pAllocLock); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c index 9f2d89da1e..bfb392bfae 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,7 +45,7 @@ NV_STATUS pmaNumaAllocate ( PMA *pPma, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages ) @@ -70,7 +70,7 @@ void pmaNumaSetReclaimSkipThreshold(PMA *pPma, NvU32 data) } #endif -typedef NV_STATUS (*scanFunc)(void *, NvU64, NvU64, NvU64, NvU64, NvU64*, NvU32, NvU64, NvU64*, NvBool, NvBool); +typedef NV_STATUS (*scanFunc)(void *, NvU64, NvU64, NvU64, NvU64, NvU64*, NvU64, NvU64, NvU64*, NvBool, NvBool); static void _pmaRollback @@ -79,14 +79,14 @@ _pmaRollback NvU64 *pPages, NvU32 failCount, NvU32 failFrame, - NvU32 pageSize, + NvU64 pageSize, PMA_PAGESTATUS oldState ) { NvU32 framesPerPage, regId, i, j; NvU64 frameNum, addrBase; - framesPerPage = pageSize >> PMA_PAGE_SHIFT; + framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); if (failCount != 0) { for(i = 0; i < failCount; i++) @@ -239,6 +239,8 @@ pmaInitialize(PMA *pPma, NvU32 initFlags) } pPma->bNuma = !!(initFlags & PMA_INIT_NUMA); + pPma->bNumaAutoOnline = !!(initFlags & PMA_INIT_NUMA_AUTO_ONLINE); + // If we want to run with address tree instead of regmap if (initFlags & PMA_INIT_ADDRTREE) { @@ -264,6 +266,9 @@ pmaInitialize(PMA *pPma, NvU32 initFlags) pPma->pmaStats.numFreeFrames = 0; pPma->pmaStats.num2mbPages = 0; pPma->pmaStats.numFree2mbPages = 0; + pPma->pmaStats.numFreeFramesProtected = 0; + pPma->pmaStats.num2mbPagesProtected = 0; + pPma->pmaStats.numFree2mbPagesProtected = 0; pPma->regSize = 0; portAtomicSetSize(&pPma->initScrubbing, PMA_SCRUB_INITIALIZE); @@ -552,7 +557,7 @@ pmaAllocatePages ( PMA *pPma, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages ) @@ -573,7 +578,7 @@ pmaAllocatePages scanFunc useFunc; PMA_PAGESTATUS pinOption; NvU64 alignment = pageSize; - NvU32 framesPerPage = pageSize >> PMA_PAGE_SHIFT; + NvU32 framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); // // A boolean indicating if we should try to evict. We at most try eviction once per call @@ -595,7 +600,7 @@ pmaAllocatePages if (allocationCount == 0) NV_PRINTF(LEVEL_ERROR, "count == 0\n"); if (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB) - NV_PRINTF(LEVEL_ERROR, "pageSize=0x%x (not 64K, 128K, 2M, or 512M)\n", pageSize); + NV_PRINTF(LEVEL_ERROR, "pageSize=0x%llx (not 64K, 128K, 2M, or 512M)\n", pageSize); if (allocationOptions == NULL) NV_PRINTF(LEVEL_ERROR, "NULL allocationOptions\n"); return NV_ERR_INVALID_ARGUMENT; @@ -655,7 +660,7 @@ pmaAllocatePages || !NV_IS_ALIGNED((allocationOptions->physEnd + 1), pageSize))) { NV_PRINTF(LEVEL_WARNING, - "base [0x%llx] or limit [0x%llx] not aligned to page size 0x%x\n", + "base [0x%llx] or limit [0x%llx] not aligned to page size 0x%llx\n", allocationOptions->physBegin, allocationOptions->physEnd + 1, pageSize); @@ -681,7 +686,7 @@ pmaAllocatePages if (!contigFlag && alignment > pageSize) { NV_PRINTF(LEVEL_WARNING, - "alignment [%llx] larger than the pageSize [%x] not supported for non-contiguous allocs\n", + "alignment [%llx] larger than the pageSize [%llx] not supported for non-contiguous allocs\n", alignment, pageSize); return NV_ERR_INVALID_ARGUMENT; } @@ -722,7 +727,7 @@ pmaAllocatePages // after checking the scrubber so any pages allocated so far are not guaranteed // to be there any more. Restart from scratch. // - NV_PRINTF(LEVEL_INFO, "Attempt %s allocation of 0x%llx pages of size 0x%x " + NV_PRINTF(LEVEL_INFO, "Attempt %s allocation of 0x%llx pages of size 0x%llx " "(0x%x frames per page)\n", contigFlag ? "contiguous" : "discontiguous", (NvU64)allocationCount, pageSize, framesPerPage); @@ -889,7 +894,7 @@ pmaAllocatePages NvU64 evictStart = *curPages; NvU64 evictEnd = *curPages + (numFramesToAllocateTotal << PMA_PAGE_SHIFT) - 1; - NV_PRINTF(LEVEL_INFO, "Attempt %s eviction of 0x%llx pages of size 0x%x, " + NV_PRINTF(LEVEL_INFO, "Attempt %s eviction of 0x%llx pages of size 0x%llx, " "(0x%x frames per page) in the frame range 0x%llx..0x%llx\n", contigFlag ? "contiguous" : "discontiguous", numPagesLeftToAllocate, @@ -919,7 +924,7 @@ pmaAllocatePages NV_ASSERT(evictPhysBegin <= evictPhysEnd); } - NV_PRINTF(LEVEL_INFO, "Attempt %s eviction of 0x%llx pages of size 0x%x, " + NV_PRINTF(LEVEL_INFO, "Attempt %s eviction of 0x%llx pages of size 0x%llx, " "(0x%x frames per page), in the frame range 0x%llx..0x%llx\n", contigFlag ? "contiguous" : "discontiguous", numPagesLeftToAllocate, @@ -1182,7 +1187,7 @@ pmaAllocatePagesBroadcast PMA **pPma, NvU32 pmaCount, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions, NvU64 *pPages ) @@ -1204,14 +1209,14 @@ pmaPinPages PMA *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize + NvU64 pageSize ) { NV_STATUS status = NV_OK; NvU32 framesPerPage, regId, i, j; NvU64 frameNum, addrBase; PMA_PAGESTATUS state; - framesPerPage = pageSize >> PMA_PAGE_SHIFT; + framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); if (pPma == NULL || pageCount == 0 || pPages == NULL || (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB)) @@ -1280,13 +1285,13 @@ pmaUnpinPages PMA *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize + NvU64 pageSize ) { NvU32 framesPerPage, regId, i, j; NvU64 frameNum, addrBase; PMA_PAGESTATUS state; - framesPerPage = pageSize >> PMA_PAGE_SHIFT; + framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); if (pPma == NULL || pageCount == 0 || pPages == NULL || (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB)) @@ -1310,8 +1315,8 @@ pmaUnpinPages NV_PRINTF(LEVEL_ERROR, "Unpin failed at %dth page %dth frame\n", i, j); _pmaRollback(pPma, pPages, i, j, pageSize, STATE_PIN); + portSyncSpinlockRelease(pPma->pPmaLock); return NV_ERR_INVALID_STATE; - } else { @@ -1350,7 +1355,8 @@ pmaFreePages { NV_ASSERT((size == _PMA_64KB) || (size == _PMA_128KB) || - (size == _PMA_2MB)); + (size == _PMA_2MB) || + (size == _PMA_512MB)); } // Fork out new code path for NUMA sub-allocation from OS @@ -1800,7 +1806,7 @@ pmaGetClientBlacklistedPages ( PMA *pPma, NvU64 *pChunks, - NvU32 *pPageSize, + NvU64 *pPageSize, NvU32 *pNumChunks ) { @@ -1977,7 +1983,11 @@ pmaGetFreeProtectedMemory NvU64 *pBytesFree ) { - *pBytesFree = 0; + portSyncSpinlockAcquire(pPma->pPmaLock); + + *pBytesFree = (pPma->pmaStats.numFreeFramesProtected) << PMA_PAGE_SHIFT; + + portSyncSpinlockRelease(pPma->pPmaLock); } void @@ -1987,6 +1997,10 @@ pmaGetFreeUnprotectedMemory NvU64 *pBytesFree ) { - // When memory protection is not enabled all memory is unprotected - pmaGetFreeMemory(pPma, pBytesFree); + portSyncSpinlockAcquire(pPma->pPmaLock); + + *pBytesFree = (pPma->pmaStats.numFreeFrames - + pPma->pmaStats.numFreeFramesProtected) << PMA_PAGE_SHIFT; + + portSyncSpinlockRelease(pPma->pPmaLock); } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c index 27ff0e76f4..9be843db29 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -46,6 +46,11 @@ static void osAllocReleasePage(NvU64 sysPagePhysAddr) return; } +static NV_STATUS osOfflinePageAtAddress(NvU64 address) +{ + return NV_ERR_GENERIC; +} + NV_STATUS scrubCheck(OBJMEMSCRUB *pScrubber, PSCRUB_NODE *ppList, NvU64 *size) { return NV_ERR_GENERIC; @@ -519,7 +524,7 @@ _pmaEvictPages NvU64 evictPageCount, NvU64 *allocPages, NvU64 allocPageCount, - NvU32 pageSize, + NvU64 pageSize, NvU64 physBegin, NvU64 physEnd, MEMORY_PROTECTION prot @@ -824,7 +829,7 @@ _pmaPredictOutOfMemory ( PMA *pPma, NvLength allocationCount, - NvU32 pageSize, + NvU64 pageSize, PMA_ALLOCATION_OPTIONS *allocationOptions ) { @@ -839,7 +844,15 @@ _pmaPredictOutOfMemory if ((alignFlag && (alignment == _PMA_2MB)) || pageSize == _PMA_2MB) { - free2mbPages = pPma->pmaStats.numFree2mbPages; + if (allocationOptions->flags & PMA_ALLOCATE_PROTECTED_REGION) + { + free2mbPages = pPma->pmaStats.numFree2mbPagesProtected; + } + else + { + free2mbPages = pPma->pmaStats.numFree2mbPages - + pPma->pmaStats.numFree2mbPagesProtected; + } // If we have at least one page free, don't fail a partial allocation if (partialFlag && (free2mbPages > 0)) @@ -854,7 +867,15 @@ _pmaPredictOutOfMemory } // Do a quick check and exit early if we are in OOM case - bytesFree = pPma->pmaStats.numFreeFrames << PMA_PAGE_SHIFT; + if (allocationOptions->flags & PMA_ALLOCATE_PROTECTED_REGION) + { + bytesFree = pPma->pmaStats.numFreeFramesProtected << PMA_PAGE_SHIFT; + } + else + { + bytesFree = (pPma->pmaStats.numFreeFrames - + pPma->pmaStats.numFreeFramesProtected) << PMA_PAGE_SHIFT; + } // If we have at least one page free, don't fail a partial allocation if (partialFlag && (bytesFree >= pageSize)) @@ -1224,6 +1245,32 @@ pmaRegisterBlacklistInfo alignedBlacklistAddr = NV_ALIGN_DOWN64(pBlacklistPageBase[blacklistEntryIn].physOffset, PMA_GRANULARITY); pmaSetBlockStateAttrib(pPma, alignedBlacklistAddr, PMA_GRANULARITY, ATTRIB_BLACKLIST, ATTRIB_BLACKLIST); pBlacklistChunk->bIsValid = NV_TRUE; + + // + // In NUMA systems, memory allocation comes directly from kernel, which + // won't check for ATTRIB_BLACKLIST. So pages need to be blacklisted + // directly through the kernel. + // + // Use physOffset without 64K alignment, because kernel may use a different + // page size. + // + // This is only needed for NUMA systems that auto online NUMA memory. + // Other systems (e.g., P9) already do blacklisting in nvidia-persistenced. + // + if (pPma->bNuma && pPma->bNumaAutoOnline) + { + NV_STATUS status; + + NV_PRINTF(LEVEL_INFO, + "NUMA enabled - blacklisting page through kernel at address 0x%llx (GPA) 0x%llx (SPA)\n", + pBlacklistPageBase[blacklistEntryIn].physOffset, + pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase); + status = osOfflinePageAtAddress(pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "osOfflinePageAtAddress() failed with status: %d\n", status); + } + } blacklistEntryIn++; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c index d5bf38bf22..ca999e5072 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c @@ -317,12 +317,13 @@ pmaRegMapScanContiguousNumaEviction NvU64 alignedAddrBase; NvU64 frameNum; - NvU64 endFrame, frameStart; + NvU64 frameLimit, frameStart; NvU64 alignment = pageSize; NvU64 frameAlignment, frameAlignmentPadding; NvU64 numFrames = actualSize >> PMA_PAGE_SHIFT; + NvU64 numFramesLimit = numFrames - 1; - endFrame = pRegmap->totalFrames - 1; + frameLimit = pRegmap->totalFrames - 1; if (pRegmap->totalFrames < numFrames) return status; @@ -334,14 +335,14 @@ pmaRegMapScanContiguousNumaEviction frameStart = alignUpToMod(0, frameAlignment, frameAlignmentPadding); - for (frameNum = frameStart; frameNum <= endFrame; ) + for (frameNum = frameStart; frameNum <= (frameLimit - numFramesLimit); ) { PMA_PAGESTATUS startFrameAllocState; PMA_PAGESTATUS endFrameAllocState; NvS64 firstUnevictableFrame; startFrameAllocState = pmaRegmapRead(pRegmap, frameNum, NV_TRUE); - endFrameAllocState = pmaRegmapRead(pRegmap, frameNum + numFrames - 1, NV_TRUE); + endFrameAllocState = pmaRegmapRead(pRegmap, frameNum + numFramesLimit, NV_TRUE); if ((endFrameAllocState & STATE_MASK) != STATE_UNPIN) { @@ -359,8 +360,8 @@ pmaRegMapScanContiguousNumaEviction } - // First occurrence of 0 in STATE_UNPIN from frameNum to frameNum + numFrames - 1 - firstUnevictableFrame = _pmaRegmapScanNumaUnevictable(pRegmap, frameNum, frameNum + numFrames - 1); + // First occurrence of 0 in STATE_UNPIN from frameNum to frameNum + numFramesLimit + firstUnevictableFrame = _pmaRegmapScanNumaUnevictable(pRegmap, frameNum, frameNum + numFramesLimit); if (firstUnevictableFrame == -1) { @@ -528,6 +529,13 @@ pmaRegmapInit pPmaStats->num2mbPages += num2mbPages; pPmaStats->numFree2mbPages += num2mbPages; + if (bProtected) + { + pPmaStats->numFreeFramesProtected += newMap->totalFrames; + pPmaStats->num2mbPagesProtected += num2mbPages; + pPmaStats->numFree2mbPagesProtected += num2mbPages; + } + newMap->bProtected = bProtected; newMap->pPmaStats = pPmaStats; newMap->mapLength = PAGE_MAPIDX(numFrames-1) + 1; @@ -562,9 +570,19 @@ pmaRegmapDestroy(void *pMap) pRegmap->pPmaStats->numFreeFrames -= pRegmap->totalFrames; + if (pRegmap->bProtected) + { + pRegmap->pPmaStats->numFreeFramesProtected -= pRegmap->totalFrames; + } + num2mbPages = pRegmap->totalFrames / (_PMA_2MB >> PMA_PAGE_SHIFT); pRegmap->pPmaStats->numFree2mbPages -= num2mbPages; + if (pRegmap->bProtected) + { + pRegmap->pPmaStats->numFree2mbPagesProtected -= num2mbPages; + } + portMemFree(pRegmap); } @@ -631,6 +649,12 @@ pmaRegmapChangeStateAttribEx pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFrames, 1, oldState, updatedState); + if (pRegmap->bProtected) + { + pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFramesProtected, 1, + oldState, updatedState); + } + // // If we are freeing a frame, we should check if we need to update the 2MB // page tracking @@ -641,6 +665,11 @@ pmaRegmapChangeStateAttribEx pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPages, 1, oldState, updatedState); + if (pRegmap->bProtected) + { + pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPagesProtected, 1, + oldState, updatedState); + } } } @@ -696,6 +725,12 @@ pmaRegmapChangeStateAttrib pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFrames, 1, oldState, newState); + if (pRegmap->bProtected) + { + pmaStatsUpdateState(&pRegmap->pPmaStats->numFreeFramesProtected, 1, + oldState, newState); + } + // // If we are freeing a frame, we should check if we need to update the 2MB // page tracking @@ -706,6 +741,11 @@ pmaRegmapChangeStateAttrib pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPages, 1, oldState, newState); + if (pRegmap->bProtected) + { + pmaStatsUpdateState(&pRegmap->pPmaStats->numFree2mbPagesProtected, 1, + oldState, newState); + } } } @@ -722,12 +762,12 @@ pmaRegmapChangePageStateAttrib ( void * pMap, NvU64 startFrame, - NvU32 pageSize, + NvU64 pageSize, PMA_PAGESTATUS newState, NvBool writeAttrib ) { - NvU32 framesPerPage = pageSize >> PMA_PAGE_SHIFT; + NvU32 framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); NvU64 frame; for (frame = startFrame; frame < startFrame + framesPerPage; frame++) { @@ -928,7 +968,7 @@ pmaRegmapScanContiguous NvU64 rangeEnd, NvU64 numPages, NvU64 *freeList, - NvU32 pageSize, + NvU64 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, NvBool bSkipEvict, @@ -1022,7 +1062,7 @@ pmaRegmapScanDiscontiguous NvU64 rangeEnd, NvU64 numPages, NvU64 *freeList, - NvU32 pageSize, + NvU64 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, NvBool bSkipEvict, diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c b/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c new file mode 100644 index 0000000000..31d569f308 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c @@ -0,0 +1,1639 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/mem_mgr/sem_surf.h" +#include "os/os.h" // NV_MEMORY_NONCONTIGUOUS, osEventNotification +#include "gpu/device/device.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "gpu/gpu.h" +#include "rmapi/client.h" +#include "rmapi/rs_utils.h" + +#include "class/cl0080.h" +#include "class/cl2080.h" +#include "class/cl0005.h" +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER + +static void +_semsurfFreeRmClient +( + SEM_SHARED_DATA *pShared +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pShared->hClient != NV01_NULL_OBJECT) + { + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->hClient); + } + + pShared->hClient = NV01_NULL_OBJECT; + pShared->hDevice = NV01_NULL_OBJECT; + pShared->hSubDevice = NV01_NULL_OBJECT; +} + +static void +_semsurfUnregisterCallback +( + SEM_SHARED_DATA *pShared +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if ((pShared->hClient != NV01_NULL_OBJECT) && + (pShared->hEvent != NV01_NULL_OBJECT)) + { + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->hEvent); + } + + pShared->hEvent = NV01_NULL_OBJECT; +} + +static NvU64 +_semsurfGetValue +( + SEM_SHARED_DATA *pShared, + NvU64 index +) +{ + volatile NvU8 *pSem = pShared->pSem; + volatile NvU8 *pMaxSubmitted = pShared->pMaxSubmitted; + volatile NvU8 *pSemBase = pSem + index * pShared->layout.size; + + portAtomicMemoryFenceFull(); + + if (pShared->bIs64Bit) + { + volatile NvU64 *pSemVal = (volatile NvU64 *)pSemBase; + + NV_PRINTF(LEVEL_INFO, " Read semaphore surface value as 64-bit native\n"); + + return *pSemVal; + } + else + { + const volatile NvU32 *pSemVal = (volatile NvU32 *)pSemBase; + volatile NvU8 *pMaxSubmittedBase = pMaxSubmitted + index * pShared->layout.size; + volatile NvU64 *pMaxSubmitted = (volatile NvU64 *)(pMaxSubmittedBase + pShared->layout.maxSubmittedSemaphoreValueOffset); + + // The ordering below is critical. See NvTimeSemFermiGetPayload() for full comment. + // TODO Share this code? + NvU64 semVal = *pSemVal; + + portAtomicMemoryFenceLoad(); + + NvU64 maxSubmitted = portAtomicExAddU64(pMaxSubmitted, 0); + + NV_PRINTF(LEVEL_INFO, " Read maxSubmitted %" NvU64_fmtu " and 32-bit semVal %" + NvU64_fmtu " from semaphore index %" NvU64_fmtu "\n", + maxSubmitted, semVal, index); + + // The value is monotonically increasing, and the max outstanding + // wait and the value can differ by no more than 2^31-1. Hence... + if ((maxSubmitted & 0xFFFFFFFFull) < semVal) + maxSubmitted -= 0x100000000ull; + + return semVal | (maxSubmitted & 0xffffffff00000000ull); + } +} + +static void +_semsurfSetValue +( + SEM_SHARED_DATA *pShared, + NvU64 index, + NvU64 newValue +) +{ + volatile NvU8 *pSem = pShared->pSem; + volatile NvU8 *pMaxSubmitted = pShared->pMaxSubmitted; + volatile NvU8 *pSemBase = pSem + index * pShared->layout.size; + + if (pShared->bIs64Bit) + { + volatile NvU64 *pSemVal = (volatile NvU64 *)pSemBase; + + portAtomicMemoryFenceFull(); + + *pSemVal = newValue; + + NV_PRINTF(LEVEL_INFO, " Updated semaphore surface value as 64-bit " + "native to %" NvU64_fmtu "\n", newValue); + } + else + { + volatile NvU32 *pSemVal = (volatile NvU32 *)pSemBase; + volatile NvU8 *pMaxSubmittedBase = pMaxSubmitted + index * pShared->layout.size; + volatile NvU64 *pMaxSubmitted = (volatile NvU64 *)(pMaxSubmittedBase + pShared->layout.maxSubmittedSemaphoreValueOffset); + NvU64 oldMax, origMax; + + portAtomicMemoryFenceFull(); + origMax = oldMax = portAtomicExAddU64(pMaxSubmitted, 0); + + // First save the actual value to the max submitted slot using + // an atomic max operation + while (oldMax < newValue) + { + NvBool exchanged; + + // XXX Does CompareAndSwap imply any barriers? The comments in + // nvport/atomic.h imply it does, but that this shouldn't be relied + // upon, so include another barrier here. + portAtomicMemoryFenceFull(); + exchanged = portAtomicExCompareAndSwapU64(pMaxSubmitted, + newValue, + oldMax); + + if (exchanged) + break; // The value was set. Exit. + + // The "current" value changed. Update it. + oldMax = portAtomicExAddU64(pMaxSubmitted, 0); + } + + portAtomicMemoryFenceStore(); + + // Now write the low bits to the GPU-accessible semaphore value. + *pSemVal = NvU64_LO32(newValue); + + NV_PRINTF(LEVEL_INFO, " Updated maxSubmitted from %" NvU64_fmtu " to %" + NvU64_fmtu " and 32-bit semVal %u" + " at semaphore index %" NvU64_fmtu "\n", + origMax, newValue, NvU64_LO32(newValue), index); + (void) origMax; + } +} + +static NvBool +_semsurfNotifyCompleted +( + SEM_SHARED_DATA *pShared, + SEM_PENDING_NOTIFICATIONS *notifications +) +{ + OBJGPU *pGpu = pShared->pSemaphoreMem->pGpu; + SEM_PENDING_NOTIFICATIONSIter pendIter; + SEM_VALUE_LISTENERS_NODE *pVNode; + NV_STATUS rmStatus; + NvBool valuesChanged = NV_FALSE; + EVENTNOTIFICATION **ppListeners; + + for (pendIter = listIterAll(notifications); + listIterNext(&pendIter); + pendIter = listIterAll(notifications)) + { + pVNode = pendIter.pValue; + + rmStatus = osEventNotification(pGpu, + pVNode->pListeners, + NV_SEMAPHORE_SURFACE_WAIT_VALUE, + NULL, + 0); + + NV_PRINTF(LEVEL_INFO, + "SemMem(0x%08x, 0x%08x): Delivered OS events for value %" + NvU64_fmtu " at idx %" NvU64_fmtu ". Status: %s (0x%08x)\n", + pShared->hClient, pShared->hSemaphoreMem, + pVNode->value, pVNode->index, + nvstatusToString(rmStatus), + rmStatus); + (void) rmStatus; + + /* + * Auto-remove the event listeners for this value now that they + * have been notified. It makes little sense to keep notifying + * them after this. + */ + ppListeners = &pendIter.pValue->pListeners; + while (*ppListeners) + { + unregisterEventNotificationWithData(ppListeners, + (*ppListeners)->hEventClient, + NV01_NULL_OBJECT, /* hNotifier/subdevice */ + (*ppListeners)->hEvent, + NV_TRUE, /* match data/notificationHandle */ + (*ppListeners)->Data); + } + + if (pVNode->newValue != 0) { + /* + * It is safe to do this operation outside of the spinlock because + * it is the RM client's responsibility to ensure the semaphore + * surface value is monotonically incrementing by explicitly + * ordering all writes to it, including these. This does imply the + * need to manually fence memory operations touching the semaphore + * value though. + */ + _semsurfSetValue(pShared, pVNode->index, pVNode->newValue); + + NV_PRINTF(LEVEL_INFO, + "SemMem(0x%08x, 0x%08x): Value updated by waiter " + " to %" NvU64_fmtu " at idx %" NvU64_fmtu "\n", + pShared->hClient, pShared->hSemaphoreMem, pVNode->newValue, pVNode->index); + + valuesChanged = NV_TRUE; + } + + listRemove(notifications, pendIter.pValue); + portMemFree(pendIter.pValue); + } + + return valuesChanged; +} + +static void +_semsurfSetMonitoredValue +( + SEM_SHARED_DATA *pShared, + NvU64 index, + NvU64 value +) +{ + if (!pShared->bHasMonitoredFence) + return; + + /* + * This function must be called with the spinlock held to avoid a race + * condition where two threads disagree on the current minimum wait value + * for a given slot. + */ + volatile NvU64 *pMonitoredFence = + (volatile NvU64 *)(pShared->pSem + + pShared->layout.size * index + + pShared->layout.monitoredFenceThresholdOffset); + + NV_PRINTF(LEVEL_NOTICE, + "SemMem(0x%08x, 0x%08x): " + "Setting monitored fence value at index %" NvU64_fmtu + " to %" NvU64_fmtu "\n", + pShared->hClient, pShared->hSemaphoreMem, + index, value); + + // Don't care if this races with loads, but ensure it happens in order + // with prior stores. + portAtomicMemoryFenceStore(); + *pMonitoredFence = value; +} + +static void +_semsurfEventCallback +( + void *pArg, + void *pData, + NvHandle hEvent, + NvU32 data, + NvU32 status +) +{ + SEM_SHARED_DATA *pShared = pArg; + SEM_INDEX_LISTENERSIter ilIter; + SEM_VALUE_LISTENERSIter vlIter; + SEM_PENDING_NOTIFICATIONS notifications; + NvU64 index; + NvU64 semValue; + NvU64 minWaitValue; + NvBool removedIndex = NV_FALSE; + NvBool valuesChanged = NV_TRUE; + + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Got a callback\n", pShared->hClient, pShared->hSemaphoreMem); + NV_PRINTF(LEVEL_INFO, " hEvent: 0x%08x surf event: 0x%08x, data 0x%08x, status 0x%08x\n", + hEvent, pShared->hEvent, data, status); + + while (valuesChanged) + { + listInitIntrusive(¬ifications); + + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + pShared->hClient, + pShared->hSemaphoreMem); + portSyncSpinlockAcquire(pShared->pSpinlock); + + for (ilIter = mapIterAll(&pShared->listenerMap); + mapIterNext(&ilIter); + removedIndex ? ilIter = mapIterAll(&pShared->listenerMap) : + ilIter) + { + removedIndex = NV_FALSE; + minWaitValue = NV_U64_MAX; + + /* + * TODO Only notify if vlIter.pValue->value <= the semaphore current + * value at mapKey(&pShared->listenerMap, ilIter->pValue) + */ + index = mapKey(&pShared->listenerMap, ilIter.pValue); + semValue = _semsurfGetValue(pShared, index); + + for (vlIter = listIterAll(&ilIter.pValue->listeners); + listIterNext(&vlIter); + vlIter = listIterAll(&ilIter.pValue->listeners)) + { + NV_PRINTF(LEVEL_SILENT, + " Checking index %" NvU64_fmtu " value waiter %" + NvU64_fmtu " against semaphore value %" NvU64_fmtu "\n", + index, vlIter.pValue->value, semValue); + + if (semValue >= vlIter.pValue->value) + { + listInsertExisting(¬ifications, NULL, vlIter.pValue); + listRemove(&ilIter.pValue->listeners, vlIter.pValue); + } + else + { + /* No other values at this index should be signaled yet. */ + minWaitValue = vlIter.pValue->value; + break; + } + } + + if (listCount(&ilIter.pValue->listeners) == 0) + { + NV_ASSERT(minWaitValue == NV_U64_MAX); + mapRemove(&pShared->listenerMap, ilIter.pValue); + portMemFree(ilIter.pValue); + removedIndex = NV_TRUE; + } + else + { + removedIndex = NV_FALSE; + } + + _semsurfSetMonitoredValue(pShared, index, minWaitValue); + } + + portSyncSpinlockRelease(pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + pShared->hClient, + pShared->hSemaphoreMem); + + // Send notifications outside of spinlock. They have already been removed + // from the object-wide lists, so their existance is private to this + // instance of this function now. Hence, no locking is required for this + // step. + valuesChanged = _semsurfNotifyCompleted(pShared, ¬ifications); + } +} + +static NV_STATUS +_semsurfAllocRmClient +( + SemaphoreSurface *pSemSurf +) +{ + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + NV0080_ALLOC_PARAMETERS nv0080AllocParams; + NV2080_ALLOC_PARAMETERS nv2080AllocParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + // Allocate an internal client, device, and subDevice for the semaphore + // surface. These will be used to allocate the internally-managed memory + // object wrapped by the semaphore surface, and to to register callbacks + // on the GPU for semaphore awaken/notification interrupts. + NV_ASSERT_OK_OR_RETURN( + pRmApi->AllocWithHandle(pRmApi, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_NULL_OBJECT, + NV01_ROOT, + &pShared->hClient, + sizeof(pShared->hClient))); + + portMemSet(&nv0080AllocParams, 0, sizeof(nv0080AllocParams)); + nv0080AllocParams.deviceId = + gpuGetDeviceInstance(GPU_RES_GET_GPU(pSemSurf)); + + NV_ASSERT_OK_OR_RETURN( + pRmApi->Alloc(pRmApi, + pShared->hClient, + pShared->hClient, + &pShared->hDevice, + NV01_DEVICE_0, + &nv0080AllocParams, + sizeof(nv0080AllocParams))); + + // Allocate a subDevice + portMemSet(&nv2080AllocParams, 0, sizeof(nv2080AllocParams)); + nv2080AllocParams.subDeviceId = + gpumgrGetSubDeviceInstanceFromGpu(GPU_RES_GET_GPU(pSemSurf)); + + NV_ASSERT_OK_OR_RETURN( + pRmApi->Alloc(pRmApi, + pShared->hClient, + pShared->hDevice, + &pShared->hSubDevice, + NV20_SUBDEVICE_0, + &nv2080AllocParams, + sizeof(nv2080AllocParams))); + + return NV_OK; +} + +static void +_semsurfFreeMemory +( + SEM_SHARED_DATA *pShared +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pShared->hClient != NV01_NULL_OBJECT) + { + if ((pShared->hMaxSubmittedMem != NV01_NULL_OBJECT) && + (pShared->hMaxSubmittedMem != pShared->hSemaphoreMem)) + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->hMaxSubmittedMem); + + if (pShared->hSemaphoreMem != NV01_NULL_OBJECT) + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->hSemaphoreMem); + } + + pShared->hSemaphoreMem = NV01_NULL_OBJECT; + pShared->hMaxSubmittedMem = NV01_NULL_OBJECT; +} + +static NV_STATUS +_semsurfDupMemory +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS *pAllocParams +) +{ + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + pShared->hClient, + pShared->hDevice, + &pShared->hSemaphoreMem, + RES_GET_CLIENT_HANDLE(pSemSurf), + pAllocParams->hSemaphoreMem, + NV04_DUP_HANDLE_FLAGS_NONE)); + + if (pAllocParams->hMaxSubmittedMem != NV01_NULL_OBJECT) + { + NV_CHECK_OR_RETURN(LEVEL_ERROR, + !pSemSurf->pShared->bIs64Bit, + NV_ERR_INVALID_PARAMETER); + + if (pAllocParams->hMaxSubmittedMem != pAllocParams->hSemaphoreMem) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + pShared->hClient, + pShared->hDevice, + &pShared->hMaxSubmittedMem, + RES_GET_CLIENT_HANDLE(pSemSurf), + pAllocParams->hMaxSubmittedMem, + NV04_DUP_HANDLE_FLAGS_NONE)); + } + else + { + pSemSurf->pShared->hMaxSubmittedMem = + pSemSurf->pShared->hSemaphoreMem; + } + } + else + { + pSemSurf->pShared->hMaxSubmittedMem = NV01_NULL_OBJECT; + } + + return NV_OK; +} + +static NV_STATUS +_semsurfRegisterCallback +( + SemaphoreSurface *pSemSurf +) +{ + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + NV0005_ALLOC_PARAMETERS nv0005AllocParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + pShared->callback.func = _semsurfEventCallback; + pShared->callback.arg = pShared; + + portMemSet(&nv0005AllocParams, 0, sizeof(nv0005AllocParams)); + nv0005AllocParams.hParentClient = pShared->hClient; + nv0005AllocParams.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; + nv0005AllocParams.notifyIndex = NV2080_NOTIFIERS_FIFO_EVENT_MTHD | + NV01_EVENT_NONSTALL_INTR | + NV01_EVENT_WITHOUT_EVENT_DATA | + NV01_EVENT_SUBDEVICE_SPECIFIC | + DRF_NUM(0005, _NOTIFY_INDEX, _SUBDEVICE, + gpumgrGetSubDeviceInstanceFromGpu(GPU_RES_GET_GPU(pSemSurf))); + nv0005AllocParams.data = NV_PTR_TO_NvP64(&pShared->callback); + + return pRmApi->Alloc(pRmApi, + pShared->hClient, + pShared->hSubDevice, + &pShared->hEvent, + NV01_EVENT_KERNEL_CALLBACK_EX, + &nv0005AllocParams, + sizeof(nv0005AllocParams)); +} + +static NV_STATUS +semsurfCopyConstruct +( + SemaphoreSurface *pSemSurf, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + RsResourceRef *pSrcRef = pParams->pSrcRef; + SemaphoreSurface *pSrcSemSurf = dynamicCast(pSrcRef->pResource, + SemaphoreSurface); + + pSemSurf->pShared = pSrcSemSurf->pShared; + NV_ASSERT(pSemSurf->pShared->refCount > 0); + pSemSurf->pShared->refCount++; + + NV_PRINTF(LEVEL_NOTICE, + "SemSurf(0x%08x, 0x%08x): Copied with SemMem(0x%08x, 0x%08x)\n", + RES_GET_CLIENT_HANDLE(pSemSurf), RES_GET_HANDLE(pSemSurf), + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); + + return NV_OK; +} + +static void +_semsurfDestroyShared +( + SEM_SHARED_DATA *pShared +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pShared == NULL) + return; + + _semsurfUnregisterCallback(pShared); + + if (pShared->pMaxSubmittedMem) + { + if (pShared->maxSubmittedKernAddr) + { + pRmApi->UnmapFromCpu(pRmApi, + pShared->hClient, + pShared->hDevice, + pShared->hMaxSubmittedMem, + pShared->maxSubmittedKernAddr, + 0, 0); + + pShared->maxSubmittedKernAddr = 0; + pShared->pMaxSubmitted = NULL; + } + } + + if (pShared->pSemaphoreMem) + { + if (pShared->semKernAddr) + { + pRmApi->UnmapFromCpu(pRmApi, + pShared->hClient, + pShared->hDevice, + pShared->hSemaphoreMem, + pShared->semKernAddr, + 0, 0); + } + + pShared->semKernAddr = 0; + pShared->pSem = NULL; + } + + pShared->pMaxSubmittedMem = NULL; + pShared->pSemaphoreMem = NULL; + + _semsurfFreeMemory(pShared); + _semsurfFreeRmClient(pShared); + + if (pShared->pSpinlock) + portSyncSpinlockDestroy(pShared->pSpinlock); + + portMemFree(pShared); +} + +static NvBool +_semsurfValidateIndex +( + SEM_SHARED_DATA *pShared, + NvU64 index +) +{ + const NvU64 slotSize = pShared->layout.size; + + if (((index * slotSize) + slotSize) <= pShared->pSemaphoreMem->pMemDesc->Size) + return NV_TRUE; + else + return NV_FALSE; +} + +NV_STATUS +semsurfConstruct_IMPL +( + SemaphoreSurface *pSemSurf, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + SEM_SHARED_DATA *pShared; + RmClient *pClient; + RsClient *pRsClient; + NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS *pAllocParams = pParams->pAllocParams; + NvU32 maxSubmittedCoherency; + NV_STATUS status = NV_OK; + NvU64 i; + + if (RS_IS_COPY_CTOR(pParams)) + { + // + // Copy constructor (NvRmDupObject) + // + return semsurfCopyConstruct(pSemSurf, pCallContext, pParams); + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pAllocParams->flags == 0ULL, + NV_ERR_INVALID_ARGUMENT); + + pShared = pSemSurf->pShared = portMemAllocNonPaged(sizeof(*pSemSurf->pShared)); + NV_ASSERT_TRUE_OR_GOTO(status, pShared != NULL, NV_ERR_NO_MEMORY, ctorFailed); + + portMemSet(pShared, 0, sizeof(*pShared)); + pShared->refCount = 1; + mapInitIntrusive(&pShared->listenerMap); + + pShared->pSpinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); + NV_ASSERT_TRUE_OR_GOTO(status, pShared->pSpinlock != NULL, NV_ERR_NO_MEMORY, ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, _semsurfAllocRmClient(pSemSurf), ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pShared->hClient, + pShared->hSubDevice, + NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT, + &pShared->layout, + sizeof pShared->layout), + ctorFailed); + + pShared->bIs64Bit = !!(pShared->layout.caps & NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED); + pShared->bHasMonitoredFence = !!(pShared->layout.caps & NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED); + + pClient = serverutilGetClientUnderLock(pShared->hClient); + NV_ASSERT_TRUE_OR_GOTO(status, pClient != NULL, NV_ERR_INVALID_STATE, ctorFailed); + + pRsClient = staticCast(pClient, RsClient); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + _semsurfDupMemory(pSemSurf, pAllocParams), + ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, memGetByHandle(pRsClient, pShared->hSemaphoreMem, &pShared->pSemaphoreMem), ctorFailed); + + /* + * XXX Limit semaphore surfaces to sysmem for the time being. Vidmem + * access latency may be too high to allow handling semaphore surfaces + * directly in the lockless top-half ISR. + */ + NV_CHECK_OR_ELSE(LEVEL_ERROR, + DRF_VAL(OS32, _ATTR, _LOCATION, + pShared->pSemaphoreMem->Attr) == + NVOS32_ATTR_LOCATION_PCI, + status = NV_ERR_INVALID_PARAMETER; + goto ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->MapToCpu(pRmApi, + pShared->hClient, + pShared->hDevice, + pShared->hSemaphoreMem, + 0, + pShared->pSemaphoreMem->pMemDesc->Size, + &pShared->semKernAddr, + 0), + ctorFailed); + + pShared->pSem = KERNEL_POINTER_FROM_NvP64(NvU8 *, pShared->semKernAddr); + + if (!pShared->bIs64Bit) + { + if (pShared->hSemaphoreMem != pShared->hMaxSubmittedMem) + { + + NV_ASSERT_OK_OR_GOTO(status, + memGetByHandle(pRsClient, pShared->hMaxSubmittedMem, &pShared->pMaxSubmittedMem), + ctorFailed); + + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pShared->pMaxSubmittedMem->pMemDesc->Size >= + pShared->pSemaphoreMem->pMemDesc->Size, + status = NV_ERR_BUFFER_TOO_SMALL; + goto ctorFailed); + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->MapToCpu(pRmApi, + pShared->hClient, + pShared->hDevice, + pShared->hMaxSubmittedMem, + 0, + pShared->pMaxSubmittedMem->pMemDesc->Size, + &pShared->maxSubmittedKernAddr, + 0), + ctorFailed); + + pShared->pMaxSubmitted = + KERNEL_POINTER_FROM_NvP64(NvU8 *, pShared->maxSubmittedKernAddr); + } + else + { + pShared->pMaxSubmitted = pShared->pSem; + pShared->pMaxSubmittedMem = pShared->pSemaphoreMem; + } + + /* + * XXX Limit semaphore surfaces to sysmem for the time being. Vidmem + * access latency may be too high to allow handling semaphore surfaces + * directly in the lockless top-half ISR. + */ + NV_CHECK_OR_ELSE(LEVEL_ERROR, + DRF_VAL(OS32, _ATTR, _LOCATION, + pShared->pMaxSubmittedMem->Attr) == + NVOS32_ATTR_LOCATION_PCI, + status = NV_ERR_INVALID_PARAMETER; + goto ctorFailed); + + /* + * The max submitted value memory must be usable with CPU atomics, + * which at least on ARM architectures requires cached mappings. + */ + maxSubmittedCoherency = DRF_VAL(OS32, _ATTR, _COHERENCY, pShared->pMaxSubmittedMem->Attr); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + (maxSubmittedCoherency != NVOS32_ATTR_COHERENCY_UNCACHED) && + (maxSubmittedCoherency != NVOS32_ATTR_COHERENCY_WRITE_COMBINE), + status = NV_ERR_INVALID_PARAMETER; + goto ctorFailed); + } + + + NV_ASSERT_OK_OR_GOTO(status, _semsurfRegisterCallback(pSemSurf), ctorFailed); + + for (i = 0; _semsurfValidateIndex(pShared, i); i++) + { + _semsurfSetMonitoredValue(pShared, i, NV_U64_MAX); + } + + /* Any failures should have already taken the ctorFailed path */ + NV_ASSERT_OR_GOTO(status == NV_OK, ctorFailed); + + NV_PRINTF(LEVEL_NOTICE, + "SemSurf(0x%08x, 0x%08x): Constructed with SemMem(0x%08x, 0x%08x)\n", + RES_GET_CLIENT_HANDLE(pSemSurf), RES_GET_HANDLE(pSemSurf), + pShared->hClient, pShared->hSemaphoreMem); + + return NV_OK; + +ctorFailed: + _semsurfDestroyShared(pShared); + + return status; +} + +void +semsurfDestruct_IMPL +( + SemaphoreSurface *pSemSurf +) +{ + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + SEM_INDEX_LISTENERS_NODE *pIndexListeners; + SEM_VALUE_LISTENERS_NODE *pValueListeners; + SEM_VALUE_LISTENERS_NODE *pNextValueListeners; + EVENTNOTIFICATION *pListener; + EVENTNOTIFICATION *pNextListener; + NvU64 minWaitValue; + NvU64 curIdx; + NvHandle hSemClient = RES_GET_CLIENT_HANDLE(pSemSurf); + NvHandle hSemSurf = RES_GET_HANDLE(pSemSurf); + NvHandle hSharedClient = pShared->hClient; + NvHandle hSharedMem = pShared->hSemaphoreMem; + + NV_ASSERT_OR_RETURN_VOID(pShared); + NV_ASSERT_OR_GOTO(pShared->pSpinlock, skipRemoveListeners); + + NV_PRINTF(LEVEL_NOTICE, + "SemSurf(0x%08x, 0x%08x): Destructor with SemMem(0x%08x, 0x%08x)\n", + hSemClient, hSemSurf, hSharedClient, hSharedMem); + + /* Remove any pending waiters instantiated via this sibling */ + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + hSharedClient, hSharedMem); + + portSyncSpinlockAcquire(pShared->pSpinlock); + + for (pIndexListeners = mapFindGEQ(&pShared->listenerMap, 0); + pIndexListeners; + pIndexListeners = mapFindGEQ(&pShared->listenerMap, curIdx + 1)) + { + minWaitValue = NV_U64_MAX; + curIdx = mapKey(&pShared->listenerMap, pIndexListeners); + + for (pValueListeners = listHead(&pIndexListeners->listeners); + pValueListeners; + pValueListeners = pNextValueListeners) + { + for (pListener = pValueListeners->pListeners; + pListener; + pListener = pNextListener) + { + pNextListener = pListener->Next; + + if ((pListener->hEventClient == hSemClient) && + (pListener->hEvent == hSemSurf)) + { + NV_PRINTF(LEVEL_WARNING, + "SemSurf(0x%08x, 0x%08x): " + "Deleting active waiter at index %" NvU64_fmtu + " value %" NvU64_fmtu "\n", + hSemClient, + hSemSurf, + curIdx, + pValueListeners->value); + + unregisterEventNotificationWithData(&pValueListeners->pListeners, + hSemClient, + NV01_NULL_OBJECT, /* hNotifier/subdevice */ + hSemSurf, + NV_TRUE, /* match data/notificationHandle */ + pListener->Data); + } + } + + pNextValueListeners = listNext(&pIndexListeners->listeners, + pValueListeners); + + if (!pValueListeners->pListeners) + { + listRemove(&pIndexListeners->listeners, pValueListeners); + portMemFree(pValueListeners); + } + else if (pValueListeners->value < minWaitValue) + { + minWaitValue = pValueListeners->value; + } + } + + _semsurfSetMonitoredValue(pShared, + curIdx, + minWaitValue); + + if (listCount(&pIndexListeners->listeners) == 0) + { + NV_ASSERT(minWaitValue == NV_U64_MAX); + mapRemove(&pShared->listenerMap, pIndexListeners); + portMemFree(pIndexListeners); + } + } + + portSyncSpinlockRelease(pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + hSharedClient, hSharedMem); + +skipRemoveListeners: + NV_ASSERT(pShared->refCount > 0); + --pShared->refCount; + if (pShared->refCount <= 0) + _semsurfDestroyShared(pShared); +} + +NV_STATUS +semsurfCtrlCmdRefMemory_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS *pParams +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + SEM_SHARED_DATA *pShared = pSemSurf->pShared; + NV_STATUS status = NV_OK; + NvHandle hSemMemOut = pParams->hSemaphoreMem; + NvHandle hMaxMemOut = pParams->hMaxSubmittedMem; + NvHandle hDeviceDst = RES_GET_HANDLE(GPU_RES_GET_DEVICE(pSemSurf)); + NvBool bSemMemDuped = NV_FALSE; + NvBool bMaxMemDuped = NV_FALSE; + + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + RES_GET_CLIENT_HANDLE(pSemSurf), + hDeviceDst, + &hSemMemOut, + pShared->hClient, + pShared->hSemaphoreMem, + 0), + error); + + bSemMemDuped = NV_TRUE; + + if (pShared->pMaxSubmittedMem) + { + if (pShared->pMaxSubmittedMem != pShared->pSemaphoreMem) + { + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + RES_GET_CLIENT_HANDLE(pSemSurf), + hDeviceDst, + &hMaxMemOut, + pShared->hClient, + pShared->hMaxSubmittedMem, + 0), + error); + + bMaxMemDuped = NV_TRUE; + } + else + { + if (pParams->hMaxSubmittedMem != pParams->hSemaphoreMem) + { + status = NV_ERR_INVALID_PARAMETER; + goto error; + } + + hMaxMemOut = hSemMemOut; + } + } + else + { + if (pParams->hMaxSubmittedMem != NV01_NULL_OBJECT) + { + return NV_ERR_INVALID_PARAMETER; + } + } + + pParams->hSemaphoreMem = hSemMemOut; + pParams->hMaxSubmittedMem = hMaxMemOut; + + return NV_OK; + +error: + if (bMaxMemDuped) + { + pRmApi->Free(pRmApi, + RES_GET_CLIENT_HANDLE(pSemSurf), + hMaxMemOut); + } + + if (bSemMemDuped) + { + pRmApi->Free(pRmApi, + RES_GET_CLIENT_HANDLE(pSemSurf), + hSemMemOut); + } + + return status; +} + +NV_STATUS +semsurfCtrlCmdBindChannel_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +_semsurfSetValueAndNotify +( + SemaphoreSurface *pSemSurf, + NvU64 index, + NvU64 newValue +) +{ + SEM_INDEX_LISTENERS_NODE *valueNode; + SEM_VALUE_LISTENERSIter vlIter; + SEM_PENDING_NOTIFICATIONS notifications; + NvU64 curValue; + NvU64 minWaitValue; + NvBool valueChanged = NV_TRUE; + + _semsurfSetValue(pSemSurf->pShared, index, newValue); + + while (valueChanged) + { + curValue = newValue; + listInitIntrusive(¬ifications); + + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); + portSyncSpinlockAcquire(pSemSurf->pShared->pSpinlock); + + valueNode = mapFind(&pSemSurf->pShared->listenerMap, index); + + if (valueNode) + { + minWaitValue = NV_U64_MAX; + + for (vlIter = listIterAll(&valueNode->listeners); + listIterNext(&vlIter); + vlIter = listIterAll(&valueNode->listeners)) + { + NV_PRINTF(LEVEL_SILENT, + " Checking index %" NvU64_fmtu " value waiter %" + NvU64_fmtu " against semaphore value %" NvU64_fmtu + " from CPU write\n", + index, vlIter.pValue->value, curValue); + + if (curValue >= vlIter.pValue->value) + { + listInsertExisting(¬ifications, NULL, vlIter.pValue); + listRemove(&valueNode->listeners, vlIter.pValue); + if (vlIter.pValue->newValue != 0) + { + NV_ASSERT(vlIter.pValue->newValue >= newValue); + newValue = vlIter.pValue->newValue; + } + } + else + { + /* No other values at this index should be signaled yet. */ + minWaitValue = vlIter.pValue->value; + break; + } + } + + if (listCount(&valueNode->listeners) == 0) + { + NV_ASSERT(minWaitValue == NV_U64_MAX); + mapRemove(&pSemSurf->pShared->listenerMap, valueNode); + portMemFree(valueNode); + } + + _semsurfSetMonitoredValue(pSemSurf->pShared, index, minWaitValue); + } + + portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); + + // Send notifications outside of spinlock. They have already been removed + // from the object-wide lists, so their existance is private to this + // instance of this function now. Hence, no locking is required for this + // step. + valueChanged = _semsurfNotifyCompleted(pSemSurf->pShared, + ¬ifications); + + NV_ASSERT(!valueChanged || (newValue > curValue)); + } + + return NV_OK; +} + +static NV_STATUS +_semsurfAddWaiter +( + SemaphoreSurface *pSemSurf, + RsClient *pRsClient, + NvU32 hSemaphoreSurf, + NvU64 index, + NvU64 waitValue, + NvU64 newValue, + NvP64 notificationHandle, + NvBool bKernel +) +{ + SEM_INDEX_LISTENERS_NODE *pIndexListeners; + SEM_VALUE_LISTENERSIter vlIter; + SEM_VALUE_LISTENERS_NODE *pValueListeners; + EVENTNOTIFICATION *pListener; + NvHandle hClient = pRsClient->hClient; + NvBool valid; + NV_STATUS rmStatus = NV_OK; + NvU64 semValue; + NvU64 prevMinWaitValue = NV_U64_MAX; + + // The new value must be greater than the wait value to guarantee + // the monotonically incrementing behavior required of semaphore surface + // values. + if ((newValue != 0) && (newValue <= waitValue)) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Requested backwards update from %" NvU64_fmtu "->%" + NvU64_fmtu " at idx %" NvU64_fmtu "\n", + hClient, hSemaphoreSurf, waitValue, newValue, index); + return NV_ERR_INVALID_STATE; + } + + portSyncSpinlockAcquire(pSemSurf->pShared->pSpinlock); + + pIndexListeners = mapFind(&pSemSurf->pShared->listenerMap, index); + + if (pIndexListeners && listCount(&pIndexListeners->listeners) > 0) + { + pValueListeners = listHead(&pIndexListeners->listeners); + prevMinWaitValue = pValueListeners->value; + } + + /* Check if semaphore value has already been reached. This must be done + * inside the spinlock to prevent the following race from dropping + * notifications: + * + * -Enter RM control registering waiter for value 1 + * -RM control read current semaphore value 0 + * -GPU semaphore write land semaphore value 1 + * -GPU conditional TRAP non-stall interrupt. + * -RM interrupt handler walks handlers, finds no registered waiters + * -RM control proceeds, adds waiter for value 1. + * -No further interrupts are generated. + * -FAILURE - client's wait stalls indefinitely. + * + * Placing the value read inside the spinlock forces this deterministic + * ordering of the above events: + * + * -Enter RM control registering waiter for value 1 + * *lock* + * -RM control read current semaphore value 0 + * -GPU semaphore write land semaphore value 1 + * -GPU conditional TRAP non-stall interrupt. + * -RM interrupt handler walks handlers + * *lock* -- Blocks, defers rest of handler + * -RM control proceeds, adds waiter for value 1. + * *unlock + * -RM interrupt handler walks handlers + * *lock* -- Unblocks, defers rest of handler + * --finds the registered waiter, signals it + * *unlock* + * -SUCCESS - client's wait was signaled. + * + * Additionally, note there is a race involving checking the semaphore + * value and updating the monitored fence/conditional trap value here. In + * order for the semaphore surface event handler to have a chance to run + * and queue up a waiter list walk, the monitored fence value must be + * updated before the conditional trap methods execute. These execute + * after the methods to update the semaphore value, but the following + * race is possible if the monitored fence value is updated after the + * check for already-signalled semaphores: + * + * -RM control reads current semaphore value 0 + * *Semaphore not yet signaled. Proceed with registering a waiter* + * -GPU semaphore write land semaphore value 1 + * -GPU conditional TRAP executes: Monitored fence value indicates no waiter + * *Interrupt is not generated* + * -RM control updates monitored fence value to 1 + * -RM control finishes registering waiter on value 1 + * -FAILURE - conditional trap method has already executed, + * so waiter won't signal until something else generate san interrupt! + * + * Hence, enough work must be done to update the monitored fence value + * before checking for an already signalled semaphore, and then the + * monitored fence update, if any, must be undone if an already-signalled + * semaphore is indeed found. If the updated monitored fence value has + * already caused an interrupt to be generated, that's OK, the handler will + * just be a no-op. + */ + if (waitValue < prevMinWaitValue) + { + _semsurfSetMonitoredValue(pSemSurf->pShared, index, waitValue); + } + + semValue = _semsurfGetValue(pSemSurf->pShared, index); + + if (semValue >= waitValue) + { + NV_PRINTF(LEVEL_NOTICE, + "SemSurf(0x%08x, 0x%08x): " + "Detected already signalled wait for %" NvU64_fmtu + " at idx %" NvU64_fmtu " current val %" NvU64_fmtu "\n", + hClient, hSemaphoreSurf, waitValue, index, semValue); + rmStatus = NV_ERR_ALREADY_SIGNALLED; + goto failureUnlock; + } + + if (!pIndexListeners) + { + pIndexListeners = portMemAllocNonPaged(sizeof(*pIndexListeners)); + if (!pIndexListeners) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Failed to allocate a semaphore index listeners node\n", + hClient, hSemaphoreSurf); + rmStatus = NV_ERR_NO_MEMORY; + goto failureUnlock; + } + + listInitIntrusive(&pIndexListeners->listeners); + + if (!mapInsertExisting(&pSemSurf->pShared->listenerMap, + index, + pIndexListeners)) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Duplicate entry found for new index listener list\n", + hClient, hSemaphoreSurf); + portMemFree(pIndexListeners); + rmStatus = NV_ERR_INVALID_STATE; + goto failureUnlock; + } + } + + /* XXX Would be easier/faster if the value listener list was a priority queue */ + vlIter = listIterAll(&pIndexListeners->listeners); + while ((valid = listIterNext(&vlIter)) && vlIter.pValue->value < waitValue); + + if (valid && vlIter.pValue->value == waitValue) + { + pValueListeners = vlIter.pValue; + } + else + { + pValueListeners = portMemAllocNonPaged(sizeof(*pValueListeners)); + + if (!pValueListeners) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Failed to allocate a semaphore value listener node\n", + hClient, hSemaphoreSurf); + rmStatus = NV_ERR_NO_MEMORY; + goto cleanupIndexListener; + } + portMemSet(pValueListeners, 0, sizeof(*pValueListeners)); + + pValueListeners->value = waitValue; + pValueListeners->index = index; + + listInsertExisting(&pIndexListeners->listeners, + valid ? vlIter.pValue : NULL, pValueListeners); + } + + if (newValue) + { + // It is a client error if two waiters request to auto-update the value + // of a semaphore after it reaches the same prerequisite value, as the + // order of those signal two operations is indeterminate. This could be + // handled by taking the max here without violating any forward progress + // rules, but it is better to return an error given the likelyhood there + // is an error in the client's logic. + if ((pValueListeners->newValue != 0)) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Existing value-updating waiter at index %" NvU64_fmtu + " for wait value %" NvU64_fmtu ":\n Existing update " + "value: %" NvU64_fmtu "\n Requested update value: %" + NvU64_fmtu "\n", + hClient, hSemaphoreSurf, index, waitValue, + pValueListeners->newValue, newValue); + rmStatus = NV_ERR_STATE_IN_USE; + goto cleanupValueListener; + + } + pValueListeners->newValue = newValue; + } + + if (notificationHandle) + { + for (pListener = pValueListeners->pListeners; + pListener; + pListener = pListener->Next) + { + if (pListener->Data == notificationHandle) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Notification handle already registered at index %" + NvU64_fmtu " for wait value %" NvU64_fmtu ".\n", + hClient, hSemaphoreSurf, index, waitValue); + /* Back out the auto-update value applied above, if any */ + pValueListeners->newValue = 0; + rmStatus = NV_ERR_STATE_IN_USE; + goto cleanupValueListener; + } + } + + rmStatus = registerEventNotification(&pValueListeners->pListeners, + pRsClient, + NV01_NULL_OBJECT, /* hNotifier/subdevice */ + hSemaphoreSurf, + NV_SEMAPHORE_SURFACE_WAIT_VALUE | + NV01_EVENT_WITHOUT_EVENT_DATA, + /* + * Allow user to pass this in + * explicitly? Doesn't seem to provide + * any added value value and adds more + * parameter validation work + */ + bKernel ? + NV01_EVENT_KERNEL_CALLBACK_EX : + NV01_EVENT_WIN32_EVENT, + notificationHandle, + !bKernel); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "SemSurf(0x%08x, 0x%08x): " + "Failed to register event notification for semaphore surface " + "listener at index %" NvU64_fmtu ", value %" NvU64_fmtu + ". Status: 0x%08x\n", + hClient, hSemaphoreSurf, index, waitValue, rmStatus); + goto cleanupValueListener; + } + } + + portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + + NV_PRINTF(LEVEL_INFO, + "SemSurf(0x%08x, 0x%08x): " + "Registered semaphore surface value listener at index %" + NvU64_fmtu ", value %" NvU64_fmtu " current value %" NvU64_fmtu + " post-wait value %" NvU64_fmtu " notification: %" NvU64_fmtx "\n", + hClient, hSemaphoreSurf, index, waitValue, semValue, newValue, + (NvU64)notificationHandle); + + return rmStatus; + +cleanupValueListener: + if (!pValueListeners->pListeners) + { + listRemove(&pIndexListeners->listeners, pValueListeners); + portMemFree(pValueListeners); + } + +cleanupIndexListener: + if (listCount(&pIndexListeners->listeners) == 0) + { + mapRemove(&pSemSurf->pShared->listenerMap, pIndexListeners); + portMemFree(pIndexListeners); + } + +failureUnlock: + // Must be done with the lock. + if (waitValue < prevMinWaitValue) + { + _semsurfSetMonitoredValue(pSemSurf->pShared, index, prevMinWaitValue); + } + + portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + + // There's no point of going through the trouble of notifying the waiter in + // this case, but it is worth immediately running the auto-update code here + // to avoid the need for the caller to call back in through the whole RMAPI + // framework with the set value control to emulate an auto-update itself. + // Just take care of it here. + if ((rmStatus == NV_ERR_ALREADY_SIGNALLED) && (newValue != 0)) + { + // On success, the ALREADY_SIGNALLED value must be preserved if the + // client also asked to register an OS event/callback. If no event/ + // callback was requested, return success, as there is all requested + // operations have been carried out. + // + // On error, the client must always be notified this call did nothing. + NV_STATUS setValStatus = _semsurfSetValueAndNotify(pSemSurf, + index, + newValue); + + if ((setValStatus != NV_OK) || !notificationHandle) + rmStatus = setValStatus; + } + + return rmStatus; +} + +NV_STATUS +semsurfCtrlCmdRegisterWaiter_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS *pParams +) +{ + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvP64 notificationHandle = 0; + const NvBool bKernel = (pCallContext->secInfo.paramLocation == + PARAM_LOCATION_KERNEL); + NV_STATUS rmStatus = NV_OK; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + _semsurfValidateIndex(pSemSurf->pShared, pParams->index), + NV_ERR_INVALID_INDEX); + + if (pParams->notificationHandle) + { + if (bKernel) + { + notificationHandle = (NvP64)pParams->notificationHandle; + } + else + { + rmStatus = osUserHandleToKernelPtr(pCallContext->pClient->hClient, + (NvP64)pParams->notificationHandle, + ¬ificationHandle); + } + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid semaphore surface notification handle: 0x%016" + NvU64_fmtx ", status: %s (0x%08x)\n", + pParams->notificationHandle, nvstatusToString(rmStatus), + rmStatus); + return rmStatus; + } + + rmStatus = _semsurfAddWaiter(pSemSurf, + staticCast(RES_GET_CLIENT(pSemSurf), RsClient), + RES_GET_HANDLE(pSemSurf), + pParams->index, + pParams->waitValue, + pParams->newValue, + notificationHandle, + bKernel); + + return rmStatus; +} + +NV_STATUS +semsurfCtrlCmdSetValue_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS *pParams +) +{ + NV_CHECK_OR_RETURN(LEVEL_ERROR, + _semsurfValidateIndex(pSemSurf->pShared, pParams->index), + NV_ERR_INVALID_INDEX); + + return _semsurfSetValueAndNotify(pSemSurf, + pParams->index, + pParams->newValue); +} + +static NV_STATUS +_semsurfDelWaiter +( + SemaphoreSurface *pSemSurf, + NvU64 index, + NvU64 waitValue, + NvP64 notificationHandle, + NvBool bKernel +) +{ + SEM_INDEX_LISTENERS_NODE *pIndexListeners; + SEM_VALUE_LISTENERSIter vlIter; + SEM_VALUE_LISTENERS_NODE *pValueListeners; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSemSurf); + NvHandle hSemaphoreSurf = RES_GET_HANDLE(pSemSurf); + NvBool valid; + NV_STATUS rmStatus = NV_ERR_GENERIC; + + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + pSemSurf->pShared->hClient, + pSemSurf->pShared->hSemaphoreMem); + portSyncSpinlockAcquire(pSemSurf->pShared->pSpinlock); + + pIndexListeners = mapFind(&pSemSurf->pShared->listenerMap, index); + + if (!pIndexListeners) + goto unlockReturn; + + vlIter = listIterAll(&pIndexListeners->listeners); + while ((valid = listIterNext(&vlIter)) && vlIter.pValue->value < waitValue); + + if (!valid || (vlIter.pValue->value != waitValue)) + goto unlockReturn; + + pValueListeners = vlIter.pValue; + + rmStatus = unregisterEventNotificationWithData(&pValueListeners->pListeners, + hClient, + /* hNotifier/subdevice */ + NV01_NULL_OBJECT, + hSemaphoreSurf, + /* match notificationHandle */ + NV_TRUE, + notificationHandle); + + if (rmStatus != NVOS_STATUS_SUCCESS) + goto unlockReturn; + + NV_PRINTF(LEVEL_INFO, "SemSurf(0x%08x, 0x%08x): " + "Unregistered event notification " NvP64_fmt + " from semaphore surface listener at index %" NvU64_fmtu + ", value %" NvU64_fmtu ".\n", + hClient, hSemaphoreSurf, notificationHandle, index, waitValue); + + if (!pValueListeners->pListeners) + { + listRemove(&pIndexListeners->listeners, pValueListeners); + portMemFree(pValueListeners); + + if (listCount(&pIndexListeners->listeners) == 0) + { + mapRemove(&pSemSurf->pShared->listenerMap, pIndexListeners); + portMemFree(pIndexListeners); + _semsurfSetMonitoredValue(pSemSurf->pShared, index, NV_U64_MAX); + } + else + { + pValueListeners = listHead(&pIndexListeners->listeners); + _semsurfSetMonitoredValue(pSemSurf->pShared, index, + pValueListeners->value); + } + } + + rmStatus = NV_OK; + +unlockReturn: + portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); + + return rmStatus; +} + +NV_STATUS +semsurfCtrlCmdUnregisterWaiter_IMPL +( + SemaphoreSurface *pSemSurf, + NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS *pParams +) +{ + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvP64 notificationHandle = 0; + const NvBool bKernel = (pCallContext->secInfo.paramLocation == + PARAM_LOCATION_KERNEL); + NV_STATUS rmStatus = NV_OK; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + _semsurfValidateIndex(pSemSurf->pShared, pParams->index), + NV_ERR_INVALID_INDEX); + + if (pParams->notificationHandle) + { + if (bKernel) + { + notificationHandle = (NvP64)pParams->notificationHandle; + } + else + { + rmStatus = osUserHandleToKernelPtr(pCallContext->pClient->hClient, + (NvP64)pParams->notificationHandle, + ¬ificationHandle); + } + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid semaphore surface notification handle: 0x%016" + NvU64_fmtx ", status: %s (0x%08x)\n", + pParams->notificationHandle, nvstatusToString(rmStatus), + rmStatus); + return rmStatus; + } + + rmStatus = _semsurfDelWaiter(pSemSurf, + pParams->index, + pParams->waitValue, + notificationHandle, + bKernel); + + return rmStatus; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c index 5f56ab9ab0..a2124a747d 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c @@ -80,6 +80,8 @@ vaspaceapiConstruct_IMPL NvBool bLockAcquired = NV_FALSE; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvU64 originalVaBase; + NvU64 originalVaSize; if (RS_IS_COPY_CTOR(pParams)) { @@ -115,6 +117,10 @@ vaspaceapiConstruct_IMPL pNvVASpaceAllocParams = pParams->pAllocParams; allocFlags = pNvVASpaceAllocParams->flags; + // These input parameters get overwritten later but original values are needed + originalVaBase = pNvVASpaceAllocParams->vaBase; + originalVaSize = pNvVASpaceAllocParams->vaSize; + // Translate & validate flags NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, translateAllocFlagsToVASpaceFlags(allocFlags, &flags)); @@ -218,7 +224,7 @@ vaspaceapiConstruct_IMPL { // In case of SR-IOV, the BAR1 and FLA is managed by the guest. So, no need // to communicate with the host for BAR1 and FLA VA. - if ((pNvVASpaceAllocParams->index == NV_VASPACE_ALLOCATION_INDEX_GPU_HOST)) + if (pNvVASpaceAllocParams->index == NV_VASPACE_ALLOCATION_INDEX_GPU_HOST) bSendRPC = NV_FALSE; } @@ -236,6 +242,7 @@ vaspaceapiConstruct_IMPL pParams->hResource, pParams->externalClassId, pNvVASpaceAllocParams, + sizeof(*pNvVASpaceAllocParams), status); if (status != NV_OK) { @@ -327,30 +334,29 @@ vaspaceapiConstruct_IMPL // Get flags for the requested big page size flags |= translatePageSizeToVASpaceFlags(pNvVASpaceAllocParams); - if (0 != pNvVASpaceAllocParams->vaSize) + if (0 != originalVaSize) { // FLA VASpace can start from any base (!= 0) if (flags & VASPACE_FLAGS_FLA) { - vasLimit = pNvVASpaceAllocParams->vaBase + - pNvVASpaceAllocParams->vaSize - 1; - if (vasLimit < pNvVASpaceAllocParams->vaBase) + vasLimit = originalVaBase + originalVaSize - 1; + if (vasLimit < originalVaBase) { NV_PRINTF(LEVEL_ERROR, "Integer overflow !!! Invalid parameters for vaBase:%llx, vaSize:%llx\n", - pNvVASpaceAllocParams->vaBase, - pNvVASpaceAllocParams->vaSize); + originalVaBase, + originalVaSize); status = NV_ERR_INVALID_ARGUMENT; NV_ASSERT_OR_GOTO(0, done); } } else { - vasLimit = pNvVASpaceAllocParams->vaSize - 1; + vasLimit = originalVaSize - 1; } } - // + // // Bug 3610538 For unlinked SLI, clients want to restrict internal buffers to // Internal VA range. setting internal va range to match what we use for // windows. @@ -366,7 +372,7 @@ vaspaceapiConstruct_IMPL status = vmmCreateVaspace(pVmm, pParams->externalClassId, pNvVASpaceAllocParams->index, gpuMask, - pNvVASpaceAllocParams->vaBase, + originalVaBase, vasLimit, vaStartInternal, vaLimitInternal, diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c index 4e1f9f509c..f0564549b2 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c @@ -92,6 +92,7 @@ kmemsysInitFlushSysmemBuffer_GA100 { NvU64 flags = MEMDESC_FLAGS_NONE; + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; // // Sysmem flush buffer // The sysmembar flush does a zero byte read of sysmem if there was a @@ -264,14 +265,14 @@ kmemsysSwizzIdToVmmuSegmentsRange_GA100 { case 0: { - numBoundaries = 0; + numBoundaries = 0; partitionDivFactor = 1; break; } case 1: case 2: { - numBoundaries = 1; + numBoundaries = 1; partitionDivFactor = 2; break; } @@ -280,7 +281,7 @@ kmemsysSwizzIdToVmmuSegmentsRange_GA100 case 5: case 6: { - numBoundaries = 3; + numBoundaries = 3; partitionDivFactor = 4; break; } diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c index ef7a768f29..ce11a8fa74 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c @@ -400,6 +400,131 @@ kmemsysAssertSysmemFlushBufferValid_GH100 (GPU_REG_RD_DRF(pGpu, _PFB, _FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI, _ADR) != 0)); } +/*! + * @brief Add GPU memory as a NUMA node. + * + * Add GPU memory as a NUMA node to the OS kernel in platforms where + * GPU is coherently connected to the CPU. + * + * @param[in] pGPU OBJGPU pointer + * @param[in] pKernelMemorySystem KernelMemorySystem pointer + * @param[in] swizzId swizzId of the MIG GPU instance, 0 for full GPU instance/non-MIG. + * @param[in] offset start offset of the GPU instance within FB + * @param[in] size size of the GPU instance + * @param[out] numaNodeId NUMA node id corresponding to the added @swizzId partition memory + * when NV_OK is returned. + * + * @returns NV_OK if all is okay. Otherwise an error-specific value. + * + */ +NV_STATUS +kmemsysNumaAddMemory_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 swizzId, + NvU64 offset, + NvU64 size, + NvS32 *numaNodeId +) +{ + NV_STATUS status; + NvU64 memblockSize = 0; + NvU32 lNumaNodeId; + + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + NV_ASSERT_OR_RETURN(NV_IS_ALIGNED(size, memblockSize), NV_ERR_INVALID_STATE); + + if (pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse) + { + NV_PRINTF(LEVEL_ERROR, "Memory partition: %u is already in use!\n", swizzId); + return NV_ERR_IN_USE; + } + + status = osNumaAddGpuMemory(pGpu->pOsGpuInfo, offset, size, &lNumaNodeId); + if (status == NV_OK) + { + pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse = NV_TRUE; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset = offset; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].size = size; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId = lNumaNodeId; + *numaNodeId = lNumaNodeId; + + pKernelMemorySystem->bNumaNodesAdded = NV_TRUE; + + NV_PRINTF(LEVEL_INFO, "Memory partition: %u added successfully!" + " numa id: %u offset: 0x%llx size: 0x%llx\n", + swizzId, lNumaNodeId, offset, size); + } + + return status; +} + +/*! + * @brief Remove a particular MIG GPU instance GPU memory from OS kernel. + * + * Remove GPU memory from the OS kernel that is earlier added as a NUMA node + * to the kernel in platforms where GPU is coherently connected to the CPU. + * + * @param[in] pGPU OBJGPU pointer + * @param[in] pKernelMemorySystem KernelMemorySystem pointer + * @param[in] swizzId swizzId of the MIG GPU instance, 0 for full partition/non-MIG. + */ +void +kmemsysNumaRemoveMemory_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 swizzId +) +{ + if (pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse == NV_FALSE) + { + return; + } + + osNumaRemoveGpuMemory(pGpu->pOsGpuInfo, + pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset, + pKernelMemorySystem->memPartitionNumaInfo[swizzId].size, + pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId); + pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse = NV_FALSE; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset = 0; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].size = 0; + pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId = NV_U32_MAX; + + NV_PRINTF(LEVEL_INFO, "NVRM: memory partition: %u removed successfully!\n", + swizzId); + return; +} + +/*! + * @brief Remove all GPU memory from OS kernel. + * + * Remove all MIG GPU instances GPU memory from the OS kernel that is earlier added + * as a NUMA node to the kernel in platforms where GPU is coherently + * connected to the CPU. + * + * @param[in] pGPU OBJGPU pointer + * @param[in] pKernelMemorySystem KernelMemorySystem pointer + * + */ +void +kmemsysNumaRemoveAllMemory_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + NvU32 swizzId; + + for (swizzId = 0; swizzId < KMIGMGR_MAX_GPU_SWIZZID; swizzId++) + { + kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, swizzId); + } + + return; +} + /* * @brief Function to map swizzId to VMMU Segments */ @@ -423,9 +548,18 @@ kmemsysSwizzIdToVmmuSegmentsRange_GH100 NV_ASSERT_OR_RETURN(pStaticInfo->pSwizzIdFbMemPageRanges != NULL, NV_ERR_INVALID_STATE); startingVmmuSegment = pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo; - memSizeInVmmuSegment = pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].hi - - pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo; - NV_ASSERT_OR_RETURN((memSizeInVmmuSegment <= totalVmmuSegments), NV_ERR_INVALID_STATE); + memSizeInVmmuSegment = (pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].hi - + pStaticInfo->pSwizzIdFbMemPageRanges->fbMemPageRanges[swizzId].lo + 1); + + if (memSizeInVmmuSegment > totalVmmuSegments) + { + // + // SwizzID-0 should cover only partitionable range, however for AMAP, + // there is no difference between swizzID-0 and no MIG which can result in + // AMAP returning an additional vmmuSegment for swizzID-0 + // + NV_ASSERT_OR_RETURN((swizzId == 0), NV_ERR_INVALID_STATE); + } NV_ASSERT_OK_OR_RETURN( kmemsysInitMIGGPUInstanceMemConfigForSwizzId(pGpu, pKernelMemorySystem, swizzId, startingVmmuSegment, memSizeInVmmuSegment)); diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c index 43b7d3b511..460da991d7 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c @@ -25,6 +25,10 @@ #include "gpu/gpu.h" #include "os/os.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/bus/p2p_api.h" +#include "gpu/nvlink/kernel_nvlink.h" +#include "published/volta/gv100/dev_mmu.h" /*! * @brief Get physical address of the FB memory on systems where GPU memory @@ -32,7 +36,7 @@ * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. - * @param[in] physAddr Physical Address of FB memory + * @param[in] physAddr Physical Address of FB memory * @param[in] numaNodeId NUMA node id where FB memory is added to the * kernel * @@ -58,3 +62,200 @@ kmemsysGetFbNumaInfo_GV100 return status; } + +/*! + * @brief Determine whether RM needs to invalidate GPU L2 cache during map call + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. + * @param[in] bIsVolatile Whether the map call is to create vol mapping + * @param[in] aperture Aperture of the memory being mapped + * + * @return NV_OK on success + */ +NvBool +kmemsysNeedInvalidateGpuCacheOnMap_GV100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvBool bIsVolatile, + NvU32 aperture +) +{ + // + // Only need to invalidate L2 for cached (vol=0) mapping to sys/peer memory + // because GPU's L2 is not coherent with CPU updates to sysmem + // See bug 3342220 for more info + // + return (!bIsVolatile && (aperture == NV_MMU_PTE_APERTURE_PEER_MEMORY || + aperture == NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY || + aperture == NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY)); +} + +/*! + * @brief Configure local GPU's peer ATS config using peer GPU's local + * ATS config. + * + * @param[in] pLocalGpu Local GPU OBJGPU pointer + * @param[in] pLocalKernelMemorySystem Local GPU KernelMemorySystem pointer + * @param[in] pRemoteGpu Remote GPU OBJGPU pointer + * @param[in] peerId peer id from local GPU to remote GPU in + * local GPU + * + * @return NV_OK on success + */ +static +NV_STATUS +_kmemsysConfigureAtsPeers +( + OBJGPU *pLocalGpu, + KernelMemorySystem *pLocalKernelMemorySystem, + OBJGPU *pRemoteGpu, + NvU32 peerId +) +{ + RM_API *pLocalRmApi = GPU_GET_PHYSICAL_RMAPI(pLocalGpu); + RM_API *pRemoteRmApi = GPU_GET_PHYSICAL_RMAPI(pRemoteGpu); + NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS getParams = { 0 }; + NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS setParams = { 0 }; + + NV_ASSERT_OK_OR_RETURN(pRemoteRmApi->Control(pRemoteRmApi, + pRemoteGpu->hInternalClient, + pRemoteGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG, + &getParams, + sizeof(NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS))); + setParams.peerId = peerId; + setParams.addrSysPhys = getParams.addrSysPhys; + setParams.addrWidth = getParams.addrWidth; + setParams.mask = getParams.mask; + setParams.maskWidth = getParams.maskWidth; + + NV_ASSERT_OK_OR_RETURN(pLocalRmApi->Control(pLocalRmApi, + pLocalGpu->hInternalClient, + pLocalGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG, + &setParams, + sizeof(NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS))); + + return NV_OK; +} + + +/** + * @brief Setup one pair of ATS peers (non-chiplib configs) + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelMemorySystem Kernel Memory System pointer + * @param[in] pRemoteGpu OBJGPU pointer for the ATS peer + * + * @return NV_OK on success + */ +static +NV_STATUS +_kmemsysSetupAtsPeers +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + OBJGPU *pRemoteGpu +) +{ + NvU32 peer1 = BUS_INVALID_PEER; + NvU32 peer2 = BUS_INVALID_PEER; + NV_STATUS status = NV_OK; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + KernelMemorySystem *pLocalKernelMs = NULL; + KernelMemorySystem *pRemoteKernelMs = NULL; + NvU32 attributes = DRF_DEF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK) | + DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA); + + // Set up P2P ATS configuration + pLocalKernelMs = pKernelMemorySystem; + pRemoteKernelMs = GPU_GET_KERNEL_MEMORY_SYSTEM(pRemoteGpu); + + if (pKernelNvlink != NULL) + { + // Trigger P2P link training to HS before releasing credits on P9 + knvlinkTrainP2pLinksToActive(pGpu, pRemoteGpu, pKernelNvlink); + } + + status = kbusCreateP2PMapping_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), pRemoteGpu, GPU_GET_KERNEL_BUS(pRemoteGpu), + &peer1, &peer2, attributes); + if (status != NV_OK) + { + return status; + } + + if (pLocalKernelMs && pRemoteKernelMs && + pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED) && + pRemoteGpu->getProperty(pRemoteGpu, PDB_PROP_GPU_ATS_SUPPORTED)) + { + status = _kmemsysConfigureAtsPeers(pGpu, pLocalKernelMs, pRemoteGpu, peer1); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Configuring ATS p2p config between GPU%u and GPU%u " + "failed with status %x\n", pGpu->gpuInstance, + pRemoteGpu->gpuInstance, status); + return status; + } + + status = _kmemsysConfigureAtsPeers(pRemoteGpu, pRemoteKernelMs, pGpu, peer2); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Configuring ATS p2p config between GPU%u and GPU%u " + "failed with status %x\n", pRemoteGpu->gpuInstance, + pGpu->gpuInstance, status); + return status; + } + } + + return NV_OK; +} + +/** + * @brief Setup ATS peer access. On GV100 and GH180, ATS peers use NVLINK. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelMemorySystem Kernel Memory System pointer + * + * @return NV_OK on success + */ +NV_STATUS +kmemsysSetupAllAtsPeers_GV100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NvU32 gpuAttachCnt, gpuAttachMask, gpuInstance = 0; + + NV_STATUS status = NV_OK; + POBJGPU pRemoteGpu = NULL; + + NV_CHECK_OR_RETURN(LEVEL_WARNING, pKernelNvlink != NULL, status); + + // loop over all possible GPU pairs and setup the ATS config + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + while ((pRemoteGpu = gpumgrGetNextGpu(gpuAttachMask, &gpuInstance)) != NULL) + { + if (pRemoteGpu == pGpu) + continue; + + if (gpuIsGpuFullPower(pRemoteGpu) == NV_FALSE) + continue; + + if (!knvlinkIsNvlinkP2pSupported(pGpu, pKernelNvlink, pRemoteGpu)) + continue; + + status = _kmemsysSetupAtsPeers(pGpu, pKernelMemorySystem, pRemoteGpu); + if (status != NV_OK) + return status; + } + + return NV_OK; +} + + diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c index 8cbb874cf4..b52b65f748 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c @@ -78,10 +78,10 @@ kmemsysConstructEngine_IMPL /* * Initialize the Kernel Memory System state. - * + * * @param[in] pGpu pointer to the GPU instance. * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. - * + * * @return NV_OK upon success. */ NV_STATUS kmemsysStateInitLocked_IMPL @@ -105,6 +105,58 @@ NV_STATUS kmemsysStateInitLocked_IMPL pKernelMemorySystem->pStaticConfig = pStaticConfig; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + pKernelMemorySystem->memPartitionNumaInfo = portMemAllocNonPaged(sizeof(MEM_PARTITION_NUMA_INFO) * KMIGMGR_MAX_GPU_SWIZZID); + if (pKernelMemorySystem->memPartitionNumaInfo == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory for numa information.\n"); + status = NV_ERR_NO_MEMORY; + NV_ASSERT_OR_GOTO(0, fail); + } + portMemSet(pKernelMemorySystem->memPartitionNumaInfo, 0, sizeof(MEM_PARTITION_NUMA_INFO) * KMIGMGR_MAX_GPU_SWIZZID); + + if (gpuIsSelfHosted(pGpu) && + (pKernelBif != NULL) && pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP)) + { + // + // memsysSetupCoherentCpuLink should be done only for the self hosted + // configuration(SHH) where the coherent C2C link connects host CPU(TH500) and GPU + // and not in the externally hosted(EHH) case where host CPU(say x86) is connected + // to GPU through PCIe and C2C only connects the TH500 (for EGM memory) and GPU. + // The gpuIsSelfHosted(pGpu) check here is to distinguish between the SHH + // and EHH configuration as C2C link is up in both of these cases. + // + + if (IS_GSP_CLIENT(pGpu)) + { + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + + if (pGSCI->bAtsSupported) + { + NV_PRINTF(LEVEL_INFO, "ATS supported\n"); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED, NV_TRUE); + } + + // + // PDB_PROP_GPU_C2C_SYSMEM is already set in physical RM but not in + // in Kernel-RM where it is actually consumed. setting PDB_PROP_GPU_C2C_SYSMEM + // in Kernel-RM when the platform is self-hosted and the C2C links are up, which + // indicate the C2C is connected to CPU and Physical-RM would have set up the HSHUB + // to route sysmem through C2C. + // + pGpu->setProperty(pGpu, PDB_PROP_GPU_C2C_SYSMEM, NV_TRUE); + } + + // + // kmemesysSetupCoherentCpuLink should not be called from physical RM as + // it is intended to be called on kernel side to update + // KernelMemorySystem for C2C, NUMA functionality. + // + NV_ASSERT_OK_OR_GOTO(status, kmemsysSetupCoherentCpuLink(pGpu, pKernelMemorySystem, NV_FALSE), fail); + } + fail: if (status != NV_OK) { @@ -133,8 +185,30 @@ kmemsysStatePreLoad_IMPL return NV_OK; } +NV_STATUS +kmemsysStatePostLoad_IMPL +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 flags +) +{ + if (IS_SILICON(pGpu) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)) + { + NV_STATUS status = kmemsysSetupAllAtsPeers_HAL(pGpu, pKernelMemorySystem); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ATS peer setup failed.\n"); + return status; + } + } + + return NV_OK; +} + /* - * Release the state accumulated in StateInit. + * Release the state accumulated in StateInit. * @param[in] pGpu pointer to the GPU instance. * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. */ @@ -145,6 +219,15 @@ void kmemsysStateDestroy_IMPL ) { + // Teardown of Coherent Cpu Link is not required on Physical RM + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + if (pKernelBif && pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + kmemsysTeardownCoherentCpuLink(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu), NV_FALSE); + } + portMemFree((void *)pKernelMemorySystem->pStaticConfig); } @@ -171,6 +254,26 @@ kmemsysDestruct_IMPL KernelMemorySystem *pKernelMemorySystem ) { + OBJGPU *pGpu = ENG_GET_GPU(pKernelMemorySystem); + + // + // kmemsysNumaRemoveAllMemory_HAL() is called here in Destruct instead of + // Destroy to guarantee that NUMA memory is removed. This goes against + // Init/Destroy symmetry, but it is necessary because kmemsysStateDestroy + // may not be called for all cases when kmemsysStateInit was called + // (e.g., when kmemsys or another engine afterwards fails Init). + // + // If NUMA memory is not removed, then all subsequent attempts to add NUMA + // memory will fail, which will cause failures in future RM init attempts. + // + if (pKernelMemorySystem->memPartitionNumaInfo != NULL) + { + if (pKernelMemorySystem->bNumaNodesAdded == NV_TRUE) + { + kmemsysNumaRemoveAllMemory_HAL(pGpu, pKernelMemorySystem); + } + portMemFree(pKernelMemorySystem->memPartitionNumaInfo); + } pKernelMemorySystem->sysmemFlushBuffer = 0; memdescFree(pKernelMemorySystem->pSysmemFlushBufferMemDesc); @@ -236,9 +339,9 @@ kmemsysAllocComprResources_KERNEL * @param[in] pGpu pointer to the GPU instance. * @param[in] pKernelMemorySystem pointer to the kernel side KernelMemorySystem instance. * @param[out] pConfig pointer to the static config init on Physical driver. - * + * * @return NV_OK upon success. - * NV_ERR* otherwise. + * NV_ERR* otherwise. */ NV_STATUS kmemsysInitStaticConfig_KERNEL @@ -580,13 +683,17 @@ kmemsysSetupCoherentCpuLink_IMPL { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU64 memblockSize = 0; - NvU64 numaOnlineBase = 0; NvU64 numaOnlineSize = 0; NvU64 fbSize = (pMemoryManager->Ram.fbTotalMemSizeMb << 20); NvU32 data32; NvBool bCpuMapping = NV_TRUE; // Default enable NvS32 numaNodeId = NV0000_CTRL_NO_NUMA_NODE; + NvU64 memblockSize = 0; + NvU64 numaOnlineBase = 0; + NvU64 rsvdFastSize = 0; + NvU64 rsvdSlowSize = 0; + NvU64 rsvdISOSize = 0; + NvU64 totalRsvdBytes = 0; { NV_ASSERT_OK_OR_RETURN(kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, @@ -594,6 +701,16 @@ kmemsysSetupCoherentCpuLink_IMPL &numaNodeId)); if (pKernelMemorySystem->coherentCpuFbBase != 0) { + if (gpuIsSelfHosted(pGpu)) + { + // + // For self-hosted, coherentCpuFbEnd is only till the FB size + // end and NOT till the FB AMAP end since self-hosted doesn't + // support indirect peer and requires GPU nvlink for peer. + // + pKernelMemorySystem->coherentCpuFbEnd = pKernelMemorySystem->coherentCpuFbBase + fbSize; + } + else { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS params = {0}; @@ -639,50 +756,50 @@ kmemsysSetupCoherentCpuLink_IMPL NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + memmgrCalcReservedFbSpaceHal_HAL(pGpu, pMemoryManager, &rsvdFastSize, &rsvdSlowSize, &rsvdISOSize); + + // + // Calculate the size of the memory which can be safely onlined to the + // kernel after accounting for different reserved memory requirements. // - // Online all of FB memory less the unaligned memblock chunk that also - // contains the RM reserved memory. + // Align rsvd memory to 64K granularity. + // TODO : rsvdMemorySize is not finalized at this point of time in + // GH180, currently rsvdMemorySize is not increasing after this + // point. This needs to be fixed. + // + totalRsvdBytes += NV_ALIGN_UP(pMemoryManager->rsvdMemorySize, 0x10000); + totalRsvdBytes += (rsvdFastSize + rsvdSlowSize + rsvdISOSize); + totalRsvdBytes += pMemoryManager->Ram.reservedMemSize; + // // TODO: make sure the onlineable memory is aligned to memblockSize // Currently, if we have leftover memory, it'll just be wasted because no // one can access it. If FB size itself is memblock size unaligned(because // of CBC and row remapper deductions), then the memory wastage is unavoidable. // - numaOnlineSize = NV_ALIGN_UP64(fbSize - memblockSize, memblockSize); - pGpu->numaNodeId = numaNodeId; - - NV_ASSERT_OK_OR_RETURN(kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, bFlush)); + numaOnlineSize = NV_ALIGN_DOWN64(fbSize - totalRsvdBytes, memblockSize); - // Switch the toggle for coherent link mapping only if migration is successful - pGpu->setProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING, NV_TRUE); + pKernelMemorySystem->numaOnlineBase = numaOnlineBase; + pKernelMemorySystem->numaOnlineSize = numaOnlineSize; + NV_PRINTF(LEVEL_INFO, "fbSize: 0x%llx NUMA reserved memory size: 0x%llx online memory size: 0x%llx\n", + fbSize, totalRsvdBytes, numaOnlineSize); // - // TODO clean up with bug 2020982 - // RM: Encapsulate NUMA-specific kernel code and logic in a new object + // Add NUMA nodes now. MODS doesn't support NUMA so skip calling + // kmemsysNumaAddMemory_HAL() for MODS // - if (osNumaMemblockSize(&memblockSize) == NV_OK) - { - NvU64 rsvdFastSize = 0; - NvU64 rsvdSlowSize = 0; - NvU64 rsvdISOSize = 0; - NvU64 totalResvBytes = 0; + // Do not add the last chunk as it could be memblock size unaligned and + // contains RM reserved memory region as well. + // + NV_ASSERT_OK_OR_RETURN(kmemsysNumaAddMemory_HAL(pGpu, pKernelMemorySystem, 0, 0, numaOnlineSize, &numaNodeId)); + pGpu->numaNodeId = numaNodeId; - memmgrCalcReservedFbSpaceHal_HAL(pGpu, pMemoryManager, &rsvdFastSize, &rsvdSlowSize, &rsvdISOSize); - totalResvBytes = (rsvdFastSize + rsvdSlowSize + rsvdISOSize); - totalResvBytes += memmgrGetRsvdMemorySize(pMemoryManager); + NV_ASSERT_OK_OR_RETURN(kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, numaOnlineSize, bFlush)); - // - // Assumption: RM reserved memory fits within the last unaligned memblock - // size chunk and this assert check is to ensure the same. - // - NV_ASSERT_OR_RETURN(totalResvBytes < (fbSize - numaOnlineSize), NV_ERR_INVALID_STATE); - - NV_PRINTF(LEVEL_INFO, "NUMA reserved memory size: 0x%llx online memory size: 0x%llx\n", - totalResvBytes, numaOnlineSize); + // Switch the toggle for coherent link mapping only if migration is successful + pGpu->setProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING, NV_TRUE); - pKernelMemorySystem->numaOnlineBase = numaOnlineBase; - pKernelMemorySystem->numaOnlineSize = numaOnlineSize; - } + NV_ASSERT_OK_OR_RETURN(kbusVerifyCoherentLink_HAL(pGpu, pKernelBus)); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c index 2a830aa2f4..4a317db036 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,7 +41,7 @@ static NV_STATUS -_fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_INFO *pFbInfos, NvU32 fbInfoListSize) +_fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject, NV2080_CTRL_FB_INFO *pFbInfos, NvU32 fbInfoListSize) { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); @@ -70,8 +70,8 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I if (bIsMIGInUse) { - bIsClientMIGMonitor = !RMCFG_FEATURE_PLATFORM_GSP && rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_SMC_MONITOR); - bIsClientMIGProfiler = kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient); + bIsClientMIGMonitor = !RMCFG_FEATURE_PLATFORM_GSP && rmclientIsCapableByHandle(pClient->hClient, NV_RM_CAP_SYS_SMC_MONITOR); + bIsClientMIGProfiler = kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, pClient->hClient); } // @@ -147,8 +147,8 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I !bIsClientMIGProfiler && !bIsClientMIGMonitor) { MIG_INSTANCE_REF ref; - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, &ref); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref); if ((status != NV_OK) && !kmigmgrIsMIGReferenceValid(&ref)) { @@ -169,8 +169,8 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I if (bIsMIGInUse && !bIsClientMIGProfiler && !bIsClientMIGMonitor) { - NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetMemoryPartitionHeapFromClient(pGpu, - pKernelMIGManager, hClient, &pMemoryPartitionHeap) == NV_OK), + NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, + pKernelMIGManager, pDevice, &pMemoryPartitionHeap) == NV_OK), NV_ERR_INSUFFICIENT_PERMISSIONS); // @@ -203,7 +203,7 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I pParams->fbInfoListSize = physIdx; NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, hClient, hObject, + pRmApi->Control(pRmApi, pClient->hClient, hObject, NV2080_CTRL_CMD_FB_GET_INFO_V2, pParams, sizeof(*pParams)), portMemFree(pParams); @@ -243,7 +243,7 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I case NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE: { GETBAR1INFO bar1Info = {0}; - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, &bar1Info); if (status != NV_OK) data = 0; else @@ -254,7 +254,7 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I case NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE: { GETBAR1INFO bar1Info = {0}; - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, &bar1Info); if (status != NV_OK) data = 0; else @@ -265,7 +265,7 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I case NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE: { GETBAR1INFO bar1Info = {0}; - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, &bar1Info); if (status != NV_OK) data = 0; else @@ -276,7 +276,7 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I case NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT: { GETBAR1INFO bar1Info = {0}; - status = memmgrGetBAR1InfoForClient_HAL(pGpu, pMemoryManager, hClient, &bar1Info); + status = memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, &bar1Info); if (status != NV_OK) data = 0; else @@ -415,22 +415,32 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I } else { - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); - if (pMemsysConfig->fbOverrideStartKb != 0) + status = memmgrCalculateHeapOffsetWithGSP_HAL(pGpu, pMemoryManager, &data); + if (status == NV_ERR_NOT_SUPPORTED) { - data = NvU64_LO32(pMemsysConfig->fbOverrideStartKb); - NV_ASSERT(((NvU64) data << 10ULL) == pMemsysConfig->fbOverrideStartKb); - } - else - { - // - // Returns start of heap in kbytes. This is zero unless - // VGA display memory is reserved. - // - heapGetBase(pHeap, &heapBase); - data = NvU64_LO32(heapBase >> 10); - NV_ASSERT(((NvU64) data << 10ULL) == heapBase); + // If GSP is not in use, if neither Console nor CBC + // region are present, or if this calculation is done + // in hardware, then heapGetBase() will give the correct + // value and it just needs to be converted to kbytes. + // It will be zero unless VGA display memory is reserved + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); + if (pMemsysConfig->fbOverrideStartKb != 0) + { + data = NvU64_LO32(pMemsysConfig->fbOverrideStartKb); + NV_ASSERT(((NvU64) data << 10ULL) == pMemsysConfig->fbOverrideStartKb); + } + else + { + // + // Returns start of heap in kbytes. This is zero unless + // VGA display memory is reserved. + // + status = heapGetBase(pHeap, &heapBase); + data = NvU64_LO32(heapBase >> 10); + NV_ASSERT_OR_ELSE(((NvU64) data << 10ULL) == heapBase, + status = NV_ERR_INVALID_DATA); + } } } break; @@ -441,6 +451,13 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I { bytesFree = 0; + if (bIsPmaEnabled) + pmaGetFreeMemory(&pHeap->pmaObject, &val); + else + heapGetFree(pHeap, &val); + + bytesFree = val; + // // Add free memory across the all valid MIG GPU instances and // the global heap. @@ -450,16 +467,33 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I // if (kmigmgrIsMIGMemPartitioningEnabled(pGpu, pKernelMIGManager)) { - memmgrGetFreeMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, &val); - bytesFree = val; - } + NvU64 partTotalBytesFree = 0; + NvU64 partTotalBytes = 0; + NvU32 config = PMA_QUERY_NUMA_ENABLED; - if (bIsPmaEnabled) - pmaGetFreeMemory(&pHeap->pmaObject, &val); - else - heapGetFree(pHeap, &val); - - bytesFree += val; + memmgrGetFreeMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, &partTotalBytesFree); + + // + // In the case of MIG+NUMA case(self hosted GPUs), NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE + // is not supported and hence the partition's memory is not accounted in the global PMA. + // This resulted in more free memory than the total memory resulting in the + // used memory(calculated as total - free) showing very large value. + // Now calculating the global free memory in the NUMA case as: + // partitions' free memory + (global total memory - all created partitions' total memory). + // + if (bIsPmaEnabled && + (pmaQueryConfigs(&pHeap->pmaObject, &config) == NV_OK) && + (config & PMA_QUERY_NUMA_ENABLED)) + { + memmgrGetTotalMemoryForAllMIGGPUInstances(pGpu, pMemoryManager, &partTotalBytes); + pmaGetTotalMemory(&pHeap->pmaObject, &val); + bytesFree = partTotalBytesFree + (val - partTotalBytes); + } + else + { + bytesFree += partTotalBytesFree; + } + } NV_ASSERT(NvU64_HI32(bytesFree >> 10) == 0); data = NvU64_LO32(bytesFree >> 10); @@ -697,6 +731,60 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I kbusGetP2PMailboxAttributes_HAL(pGpu, pKernelBus, NULL, NULL, &data); break; } + case NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB: + { + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + if (bIsPmaEnabled) + { + pmaGetTotalProtectedMemory(&pHeap->pmaObject, &bytesTotal); + NV_ASSERT(NvU64_HI32(bytesTotal >> 10) == 0); + data = NvU64_LO32(bytesTotal >> 10); + } + else + { + // + // We should never reach here given that PMA is enabled + // on all platforms where confidential compute is supported + // + NV_ASSERT(0); + data = 0; + status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + data = 0; + } + break; + } + case NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB: + { + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + if (bIsPmaEnabled) + { + pmaGetFreeProtectedMemory(&pHeap->pmaObject, &bytesFree); + NV_ASSERT(NvU64_HI32(bytesFree >> 10) == 0); + data = NvU64_LO32(bytesFree >> 10); + } + else + { + // + // We should never reach here given that PMA is enabled + // on all platforms where confidential compute is supported + // + NV_ASSERT(0); + data = 0; + status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + data = 0; + } + break; + } default: { data = 0; @@ -728,8 +816,9 @@ subdeviceCtrlCmdFbGetInfo_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + RsClient *pClient = RES_GET_CLIENT(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); @@ -739,7 +828,7 @@ subdeviceCtrlCmdFbGetInfo_IMPL return NV_ERR_INVALID_ARGUMENT; } - return _fbGetFbInfos(pGpu, hClient, hObject, NvP64_VALUE(pFbInfoParams->fbInfoList), pFbInfoParams->fbInfoListSize); + return _fbGetFbInfos(pGpu, pClient, pDevice, hObject, NvP64_VALUE(pFbInfoParams->fbInfoList), pFbInfoParams->fbInfoListSize); } // @@ -756,8 +845,9 @@ subdeviceCtrlCmdFbGetInfoV2_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + RsClient *pClient = RES_GET_CLIENT(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); @@ -767,7 +857,7 @@ subdeviceCtrlCmdFbGetInfoV2_IMPL return NV_ERR_INVALID_ARGUMENT; } - return _fbGetFbInfos(pGpu, hClient, hObject, pFbInfoParams->fbInfoList, pFbInfoParams->fbInfoListSize); + return _fbGetFbInfos(pGpu, pClient, pDevice, hObject, pFbInfoParams->fbInfoList, pFbInfoParams->fbInfoListSize); } // @@ -904,7 +994,7 @@ subdeviceCtrlCmdFbGetCliManagedOfflinedPages_IMPL NvU32 osBlackListCount = 0; NvU32 chunk; NvU64 chunks[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; - NvU32 pageSize; + NvU64 pageSize; NvU32 numChunks = 0; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); @@ -922,7 +1012,7 @@ subdeviceCtrlCmdFbGetCliManagedOfflinedPages_IMPL pOsOfflinedParams->offlinedPages[chunk] = (NvU32)(chunks[chunk] >> RM_PAGE_SHIFT); } pOsOfflinedParams->validEntries = numChunks; - pOsOfflinedParams->pageSize = pageSize; + pOsOfflinedParams->pageSize = (NvU32)pageSize; } else { @@ -1017,6 +1107,8 @@ subdeviceCtrlCmdFbGetNumaInfo_IMPL NvU32 idx; NV_STATUS status; NvU32 count; + NvU64 numaMemOffset = 0; + NvU64 numaMemSize = 0; const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); @@ -1028,9 +1120,37 @@ subdeviceCtrlCmdFbGetNumaInfo_IMPL return NV_ERR_INVALID_ARGUMENT; } - pParams->numaNodeId = pGpu->numaNodeId; - pParams->numaMemAddr = pKernelMemorySystem->coherentCpuFbBase + pKernelMemorySystem->numaOnlineBase; - pParams->numaMemSize = pKernelMemorySystem->numaOnlineSize; + if (gpuIsSelfHosted(pGpu) && IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); + MIG_INSTANCE_REF ref; + NvU32 swizzId; + + pParams->numaNodeId = NV0000_CTRL_NO_NUMA_NODE; + + if (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref) == NV_OK) + { + swizzId = ref.pKernelMIGGpuInstance->swizzId; + + if (pKernelMemorySystem->memPartitionNumaInfo[swizzId].bInUse) + { + pParams->numaNodeId = pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId; + pParams->numaMemAddr = pKernelMemorySystem->coherentCpuFbBase + pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset; + pParams->numaMemSize = pKernelMemorySystem->memPartitionNumaInfo[swizzId].size; + numaMemOffset = pKernelMemorySystem->memPartitionNumaInfo[swizzId].offset; + numaMemSize = pKernelMemorySystem->memPartitionNumaInfo[swizzId].size; + } + } + } + else + { + pParams->numaNodeId = pGpu->numaNodeId; + pParams->numaMemAddr = pKernelMemorySystem->coherentCpuFbBase + pKernelMemorySystem->numaOnlineBase; + pParams->numaMemSize = pKernelMemorySystem->numaOnlineSize; + numaMemOffset = pKernelMemorySystem->numaOnlineBase; + numaMemSize = pKernelMemorySystem->numaOnlineSize; + } if (pParams->numaOfflineAddressesCount == 0) { @@ -1067,9 +1187,9 @@ subdeviceCtrlCmdFbGetNumaInfo_IMPL } // Only tell the caller about Offline pages in the NUMA region. - if (offset < pParams->numaMemSize) + if ((offset >= numaMemOffset) && (offset < (numaMemOffset + numaMemSize))) { - pParams->numaOfflineAddresses[numaOfflineIdx++] = pParams->numaMemAddr + offset; + pParams->numaOfflineAddresses[numaOfflineIdx++] = pKernelMemorySystem->coherentCpuFbBase + offset; } else { @@ -1256,7 +1376,7 @@ subdeviceCtrlCmdFbFlushGpuCache_IMPL _YES, pCacheFlushParams->flags)) { NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY)); + kbusSendSysmembar(pGpu, pKernelBus)); } return status; diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c b/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c index 3b90601e61..e4278e4295 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -112,16 +114,16 @@ kmigmgrCreateGPUInstanceCheck_GA100 // Make sure there are no channels alive on any of these engines if (kfifoEngineListHasChannel(pGpu, pKernelFifo, engines, engineCount)) return NV_ERR_STATE_IN_USE; - + // - // Check for any alive P2P references to this GPU. P2P objects must - // be re-created after disabling MIG. If it is allowed for MIG to - // continue enablement without all P2P objects torn down, there is + // Check for any alive P2P references to this GPU. P2P objects must + // be re-created after disabling MIG. If it is allowed for MIG to + // continue enablement without all P2P objects torn down, there is // the possibility that P2P mappings and state will never be updated. // if (bMemoryPartitioningNeeded || !kmigmgrIsMIGNvlinkP2PSupportOverridden(pGpu, pKernelMIGManager)) { - NV_CHECK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OR_RETURN(LEVEL_ERROR, !kbusIsGpuP2pAlive(pGpu, GPU_GET_KERNEL_BUS(pGpu)), NV_ERR_STATE_IN_USE); } diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c b/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c index 76540847cd..c6058bf5f9 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -106,7 +108,7 @@ kmigmgrIsGPUInstanceCombinationValid_GH100 return NV_FALSE; } } - + switch (computeSizeFlag) { case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL: diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c b/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c index fce0e63160..fdd869e5c3 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,11 @@ * *****************************************************************************/ +#define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" #include "core/system.h" @@ -124,7 +129,7 @@ cisubscriptionCopyConstruct_IMPL ComputeInstanceSubscription *pComputeInstanceSubscriptionSrc = dynamicCast(pSrcRef->pResource, ComputeInstanceSubscription); OBJGPU *pGpu = GPU_RES_GET_GPU(pComputeInstanceSubscription); - // non kernel clients are not allowed to dup MIG instances + // non kernel clients are not allowed to dup MIG instances NV_CHECK_OR_RETURN(LEVEL_SILENT, pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL, NV_ERR_NOT_SUPPORTED); diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c index 9261f11397..35c4d688c8 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,12 @@ * *****************************************************************************/ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "core/system.h" #include "gpu/gpu.h" @@ -649,6 +655,7 @@ gisubscriptionCtrlCmdExecPartitionsGet_IMPL ++pParams->execPartCount; pOutInfo->gpcCount = pMIGComputeInstance->resourceAllocation.gpcCount; + pOutInfo->gfxGpcCount = pMIGComputeInstance->resourceAllocation.gfxGpcCount; pOutInfo->veidCount = pMIGComputeInstance->resourceAllocation.veidCount; pOutInfo->ceCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, RM_ENGINE_TYPE_COPY(0)); @@ -868,7 +875,8 @@ gisubscriptionCtrlCmdExecPartitionsImport_IMPL { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrCreateComputeInstances_HAL(pGpu, pKernelMIGManager, pGPUInstance, NV_FALSE, restore, &pParams->id, NV_FALSE), + kmigmgrCreateComputeInstances_HAL(pGpu, pKernelMIGManager, + pGPUInstance, NV_FALSE, restore, &pParams->id, pParams->bCreateCap), cleanup_rpc); } else diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c index 6afb42b489..efe8b83b6a 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,14 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/rc/kernel_rc.h" @@ -41,6 +49,7 @@ #include "rmapi/rmapi_utils.h" #include "gpu/mem_mgr/mem_scrub.h" #include "vgpu/rpc.h" +#include "virtualization/kernel_vgpu_mgr.h" #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/core/locks.h" @@ -332,13 +341,14 @@ ct_assert((RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE - 1) - * @brief Chooses the engines of the given type to allocate. Supports * shared/exclusive ownership arbitration. * - * @param[IN] pSourceEngines Mask of engines to allocate from - * @param[IN} bShared NV_TRUE if engines should be shared - * @param[IN] engTypeRange NV_RANGE of bit indices for this eng type - * @param[IN] regEngCount Requested number of engines in this exec part - * @param[I/O] pOutEngines Mask of engines already/newly allocated - * @param[I/O] pExclusiveEngines Mask of already exclusively-allocated engines - * @param[I/O] pSharedEngines Mask of engines shared by other instances + * @param[IN] pSourceEngines Mask of engines in an instance + * @param[IN} bShared NV_TRUE if engines should be shared + * @param[IN] engTypeRange NV_RANGE of bit indices for this eng type + * @param[IN] regEngCount Requested number of engines in this CI + * @param[I/O] pOutEngines Mask of engines already/newly allocated + * @param[I/O] pExclusiveEngines Mask of already exclusively-allocated engines + * @param[I/O] pSharedEngines Mask of engines shared by other instances + * @param[IN] pAllocatableEngines Mask of engines that are allocatable */ NV_STATUS kmigmgrAllocateInstanceEngines_IMPL @@ -349,7 +359,8 @@ kmigmgrAllocateInstanceEngines_IMPL NvU32 reqEngCount, ENGTYPE_BIT_VECTOR *pOutEngines, ENGTYPE_BIT_VECTOR *pExclusiveEngines, - ENGTYPE_BIT_VECTOR *pSharedEngines + ENGTYPE_BIT_VECTOR *pSharedEngines, + ENGTYPE_BIT_VECTOR *pAllocatableEngines ) { NvU32 allocated = 0; @@ -357,6 +368,11 @@ kmigmgrAllocateInstanceEngines_IMPL RM_ENGINE_TYPE rmEngineType; NvU32 localIdx; + // Ensure allocatableEngines is subset of sourceEngines + bitVectorClrAll(&engines); + bitVectorAnd(&engines, pAllocatableEngines, pSourceEngines); + NV_ASSERT_OR_RETURN(bitVectorTestEqual(&engines, pAllocatableEngines), NV_ERR_INVALID_STATE); + // If using shared engines, allocate as many from existing shared engines as possible if (bShared) { @@ -369,8 +385,9 @@ kmigmgrAllocateInstanceEngines_IMPL if (allocated == reqEngCount) break; - // Skip engines that aren't in the shared pool already - if (!bitVectorTest(pSharedEngines, rmEngineType)) + // Skip engines that aren't allocatable or aren't in the shared pool already + if (!bitVectorTest(pAllocatableEngines, rmEngineType) || + !bitVectorTest(pSharedEngines, rmEngineType)) { localIdx++; continue; @@ -395,8 +412,9 @@ kmigmgrAllocateInstanceEngines_IMPL if (allocated == reqEngCount) break; - // Skip in-use engines - if (bitVectorTest(pSharedEngines, rmEngineType) || + // Skip non-allocatable or in-use engines + if (!bitVectorTest(pAllocatableEngines, rmEngineType) || + bitVectorTest(pSharedEngines, rmEngineType) || bitVectorTest(pExclusiveEngines, rmEngineType)) { localIdx++; @@ -499,7 +517,7 @@ kmigmgrAllocGPUInstanceHandles_IMPL portMemSet(¶ms, 0, sizeof(params)); params.swizzId = swizzId; NV_ASSERT_OK_OR_RETURN( - pRmApi->Alloc(pRmApi, hClient, hSubdevice, &hSubscription, AMPERE_SMC_PARTITION_REF, ¶ms)); + pRmApi->Alloc(pRmApi, hClient, hSubdevice, &hSubscription, AMPERE_SMC_PARTITION_REF, ¶ms, sizeof(params))); pKernelMIGGpuInstance->instanceHandles.hClient = hClient; pKernelMIGGpuInstance->instanceHandles.hDevice = hDevice; @@ -1493,74 +1511,6 @@ kmigmgrIsEngineInInstance_IMPL &unused) == NV_OK; } -/*! - * @brief Function to allocate N available sys pipes for the given swizzid. - * This function will only retrieve available pipes according to the - * sys pipe free mask in KernelMIGManager, and is not responsible for - * updating that mask. - * - * @param[IN] pGpu - * @param[IN] pKernerlMIGManager - * @param[IN] engineCount Number of engines requested - * @param[IN] engineRange Range of acceptable RM_ENGINE_TYPE to allocate - * @param[IN/OUT] pInstanceEngines Bitmask tracking engines owned by MIG instance - */ -NV_STATUS -kmigmgrGetFreeEngines_IMPL -( - OBJGPU *pGpu, - KernelMIGManager *pKernelMIGManager, - NvU32 engineCount, - NV_RANGE engineRange, - ENGTYPE_BIT_VECTOR *pInstanceEngines -) -{ - const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); - ENGTYPE_BIT_VECTOR partitionableEngines; - ENGTYPE_BIT_VECTOR availableEngines; - NvU32 numAllocated; - RM_ENGINE_TYPE rmEngineType; - - NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(!rangeIsEmpty(engineRange), NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pInstanceEngines != NULL, NV_ERR_INVALID_ARGUMENT); - - if (engineCount == 0) - { - return NV_OK; - } - - bitVectorFromRaw(&partitionableEngines, - &pStaticInfo->partitionableEngineMask, - sizeof(pStaticInfo->partitionableEngineMask)); - - NV_ASSERT_OR_RETURN(!bitVectorTestAllCleared(&partitionableEngines), - NV_ERR_INVALID_STATE); - - // availableEngines = (ENGINE_MASK & partitionableEngines) & ~enginesInUse - bitVectorClrAll(&availableEngines); - bitVectorSetRange(&availableEngines, engineRange); - bitVectorAnd(&availableEngines, &availableEngines, &partitionableEngines); - { - ENGTYPE_BIT_VECTOR enginesNotInUse; - bitVectorComplement(&enginesNotInUse, &pKernelMIGManager->partitionableEnginesInUse); - bitVectorAnd(&availableEngines, &availableEngines, &enginesNotInUse); - } - - numAllocated = 0; - FOR_EACH_IN_BITVECTOR(&availableEngines, rmEngineType) - { - if (numAllocated == engineCount) - break; - - bitVectorSet(pInstanceEngines, rmEngineType); - numAllocated++; - } - FOR_EACH_IN_BITVECTOR_END(); - - return NV_OK; -} - /*! * @brief Trim runlist buffer pools */ @@ -1615,7 +1565,7 @@ kmigmgrCreateGPUInstanceRunlists_FWCLIENT RM_ENGINE_TYPE rmEngineType; NvU32 engDesc; NV_STATUS status = NV_OK; - NvU32 numEngines = kfifoGetNumEngines_HAL(pGpu, pKernelFifo); + NvU32 numEngines = kfifoGetNumEschedDrivenEngines(pKernelFifo); NvU32 maxRunlists = kfifoGetMaxNumRunlists_HAL(pGpu, pKernelFifo); NvU64 runlistAlign; NvU64 allocFlags; @@ -1913,6 +1863,7 @@ kmigmgrRestoreFromPersistence_PF &hSubscription, AMPERE_SMC_PARTITION_REF, &alloc, + sizeof(alloc), RMAPI_ALLOC_FLAGS_NONE, NULL, &pRmApi->defaultSecInfo), @@ -1920,6 +1871,7 @@ kmigmgrRestoreFromPersistence_PF portMemSet(pExecPartImportParams, 0, sizeof(*pExecPartImportParams)); pExecPartImportParams->id = pComputeInstanceSave->id; + pExecPartImportParams->bCreateCap = NV_FALSE; portMemCopy(&pExecPartImportParams->info, sizeof(pExecPartImportParams->info), &pComputeInstanceSave->ciInfo, sizeof(pComputeInstanceSave->ciInfo)); @@ -2032,7 +1984,12 @@ kmigmgrRestoreFromPersistence_VF .type = KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE, .inst.restore.pComputeInstanceSave = pComputeInstanceSave }; - NvU32 id; + // + // This id variable actually doesn't need to be initialized since the callee + // is not referencing to its value. But GCC13 is unhappy with that, thus WAR + // this issue by initializing it. + // + NvU32 id = pComputeInstanceSave->id; if (!pComputeInstanceSave->bValid) continue; @@ -2167,8 +2124,7 @@ kmigmgrIsClientUsingDeviceProfiling_IMPL ) { RsClient *pRsClient; - GPUInstanceSubscription *pGPUInstanceSubscription; - Subdevice *pSubdevice; + Device *pDevice; NV_STATUS status; NV_CHECK_OR_RETURN(LEVEL_SILENT, IS_MIG_ENABLED(pGpu), NV_FALSE); @@ -2183,9 +2139,40 @@ kmigmgrIsClientUsingDeviceProfiling_IMPL return NV_FALSE; ); NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice), + deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice), return NV_FALSE; ); + return kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice); +} + +/*! + * @brief Function to check if specific device is subscribed to DeviceProfiling + */ +NvBool +kmigmgrIsDeviceUsingDeviceProfiling_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + Device *pDevice +) +{ + RsClient *pRsClient; + GPUInstanceSubscription *pGPUInstanceSubscription; + Subdevice *pSubdevice; + NV_STATUS status; + + NV_CHECK_OR_RETURN(LEVEL_SILENT, IS_MIG_ENABLED(pGpu), NV_FALSE); + + if (!kmigmgrIsDeviceProfilingInUse(pGpu, pKernelMIGManager)) + { + return NV_FALSE; + } + + pRsClient = RES_GET_CLIENT(pDevice); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + subdeviceGetByInstance(pRsClient, RES_GET_HANDLE(pDevice), 0, &pSubdevice)); + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription), return NV_FALSE; ); @@ -2230,8 +2217,7 @@ kmigmgrGetInstanceRefFromDevice_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvHandle hClient, - NvHandle hDevice, + Device *pDevice, MIG_INSTANCE_REF *pRef ) { @@ -2250,12 +2236,12 @@ kmigmgrGetInstanceRefFromDevice_IMPL return NV_ERR_INVALID_STATE; } - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + pRsClient = RES_GET_CLIENT(pDevice); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - subdeviceGetByInstance(pRsClient, hDevice, 0, &pSubdevice)); + subdeviceGetByInstance(pRsClient, RES_GET_HANDLE(pDevice), 0, &pSubdevice)); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_RETURN(LEVEL_NOTICE, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription)); @@ -2310,8 +2296,7 @@ kmigmgrGetInstanceRefFromClient_IMPL deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice)); return kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, - hClient, RES_GET_HANDLE(pDevice), - pRef); + pDevice, pRef); } /*! @@ -2322,17 +2307,19 @@ kmigmgrGetMemoryPartitionHeapFromDevice_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvHandle hClient, - NvHandle hDevice, + Device *pDevice, Heap **ppMemoryPartitionHeap ) { MIG_INSTANCE_REF ref; NV_STATUS rmStatus = NV_OK; + NvHandle hClient; NV_ASSERT_OR_RETURN(IS_MIG_IN_USE(pGpu), NV_ERR_INVALID_STATE); - rmStatus = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, hClient, hDevice, &ref); + hClient = RES_GET_CLIENT_HANDLE(pDevice); + + rmStatus = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); if ((rmStatus != NV_OK) || !kmigmgrIsMIGReferenceValid(&ref)) { RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilegeByHandle(hClient); @@ -2365,48 +2352,21 @@ kmigmgrGetMemoryPartitionHeapFromDevice_IMPL return rmStatus; } -/*! - * @brief Retrieves GPU instance heap associated with a client, if applicable - */ -NV_STATUS -kmigmgrGetMemoryPartitionHeapFromClient_IMPL -( - OBJGPU *pGpu, - KernelMIGManager *pKernelMIGManager, - NvHandle hClient, - Heap **ppMemoryPartitionHeap -) -{ - RsClient *pRsClient; - Device *pDevice; - - NV_ASSERT_OR_RETURN(IS_MIG_IN_USE(pGpu), NV_ERR_INVALID_STATE); - - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice)); - - return kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, pKernelMIGManager, - hClient, RES_GET_HANDLE(pDevice), - ppMemoryPartitionHeap); -} - /*! * @brief Retrieves swizzid associated with a client, if applicable */ NV_STATUS -kmigmgrGetSwizzIdFromClient_IMPL +kmigmgrGetSwizzIdFromDevice_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvHandle hClient, + Device *pDevice, NvU32 *pSwizzId ) { MIG_INSTANCE_REF ref; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); *pSwizzId = ref.pKernelMIGGpuInstance->swizzId; return NV_OK; @@ -2595,6 +2555,8 @@ kmigmgrSetGPUInstanceInfo_IMPL pKernelMIGGpuInstance, &pKernelMIGGpuInstance->resourceAllocation)); + pKernelMIGGpuInstance->resourceAllocation.gfxGpcCount = pKernelMIGGpuInstance->pProfile->gfxGpcCount; + // Set assigned engines as in use NV_ASSERT_OK_OR_RETURN( kmigmgrSetEnginesInUse(pGpu, pKernelMIGManager, &pKernelMIGGpuInstance->resourceAllocation.engines)); @@ -3133,7 +3095,7 @@ kmigmgrDetectReducedConfig_KERNEL * * @param[IN] pGpu * @param[IN] pKernelMIGManager - * @param[IN] hClient Client handle subscribed to GI + * @param[IN] pDevice Device subscribed to GI * @param[OUT] ppCe Scrubber CE */ NV_STATUS @@ -3141,7 +3103,7 @@ kmigmgrGetGPUInstanceScrubberCe_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvHandle hClient, + Device *pDevice, NvU32 *ceInst ) { @@ -3149,7 +3111,7 @@ kmigmgrGetGPUInstanceScrubberCe_IMPL ENGTYPE_BIT_VECTOR ces; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); bitVectorClrAll(&ces); bitVectorSetRange(&ces, RM_ENGINE_RANGE_COPY()); @@ -3218,7 +3180,9 @@ kmigmgrDescribeGPUInstances_IMPL pParams->partitionDescs[entryCount].partitionFlag = pStaticInfo->pProfiles->table[i].partitionFlag; pParams->partitionDescs[entryCount].grCount = pStaticInfo->pProfiles->table[i].grCount; + pParams->partitionDescs[entryCount].gfxGrCount = pStaticInfo->pProfiles->table[i].gfxGrCount; pParams->partitionDescs[entryCount].gpcCount = pStaticInfo->pProfiles->table[i].gpcCount; + pParams->partitionDescs[entryCount].gfxGpcCount = pStaticInfo->pProfiles->table[i].gfxGpcCount; pParams->partitionDescs[entryCount].virtualGpcCount = pStaticInfo->pProfiles->table[i].virtualGpcCount; pParams->partitionDescs[entryCount].veidCount = pStaticInfo->pProfiles->table[i].veidCount; pParams->partitionDescs[entryCount].smCount = pStaticInfo->pProfiles->table[i].smCount; @@ -3399,7 +3363,7 @@ kmigmgrAllocComputeInstanceHandles_IMPL portMemSet(¶ms, 0, sizeof(params)); params.swizzId = pKernelMIGGpuInstance->swizzId; NV_ASSERT_OK_OR_GOTO(status, - pRmApi->Alloc(pRmApi, hClient, hSubdevice, &hGPUInstanceSubscription, AMPERE_SMC_PARTITION_REF, ¶ms), + pRmApi->Alloc(pRmApi, hClient, hSubdevice, &hGPUInstanceSubscription, AMPERE_SMC_PARTITION_REF, ¶ms, sizeof(params)), failed); } @@ -3408,7 +3372,7 @@ kmigmgrAllocComputeInstanceHandles_IMPL portMemSet(¶ms, 0, sizeof(params)); params.execPartitionId = pMIGComputeInstance->id; NV_ASSERT_OK_OR_GOTO(status, - pRmApi->Alloc(pRmApi, hClient, hGPUInstanceSubscription, &hComputeInstanceSubscription, AMPERE_SMC_EXEC_PARTITION_REF, ¶ms), + pRmApi->Alloc(pRmApi, hClient, hGPUInstanceSubscription, &hComputeInstanceSubscription, AMPERE_SMC_EXEC_PARTITION_REF, ¶ms, sizeof(params)), failed); } @@ -3459,6 +3423,7 @@ kmigmgrCreateComputeInstances_VF NvU32 i; NvU64 shadowCTSInUseMask; NvU64 shadowVeidInUseMask; + NvU32 maxVeidsPerGpc; KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KMIGMGR_CONFIGURE_INSTANCE_REQUEST *pConfigRequestPerCi = NULL; NvBool bIsCTSRequired = kmigmgrIsCTSAlignmentRequired_HAL(pGpu, pKernelMIGManager); @@ -3483,6 +3448,10 @@ kmigmgrCreateComputeInstances_VF portMemSet(pConfigRequestPerCi, 0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); + NV_ASSERT_OK_OR_GOTO(status, + kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &maxVeidsPerGpc), + done); + // Check that there's enough open compute instance slots, and count used GPCs freeSlots = 0; inUseGpcCount = 0; @@ -3551,10 +3520,17 @@ kmigmgrCreateComputeInstances_VF if (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) { - spanStart = - (FLD_TEST_REF(NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN, _TRUE, params.inst.request.requestFlags)) + spanStart = KMIGMGR_SPAN_OFFSET_INVALID; + if (FLD_TEST_REF(NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN, _TRUE, params.inst.request.requestFlags)) + { + // + // Select spanStart from spanStart field, else calculate the spanStart using the veid offset passed in. + // This is done specifically to accomodate legacy flows which don't have knowledge of the new spanStart field + // + spanStart = (params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart != 0) ? params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart - : KMIGMGR_SPAN_OFFSET_INVALID; + : params.inst.request.pReqComputeInstanceInfo[CIIdx].veidStartOffset / maxVeidsPerGpc; + } } else { @@ -3605,18 +3581,12 @@ kmigmgrCreateComputeInstances_VF } else { - NvU32 maxVeidsPerGpc; - - NV_ASSERT_OK_OR_GOTO(status, - kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &maxVeidsPerGpc), - done); - // If no CI profile was available. Populate one with bare-necessities pCIProfile->computeSize = KMIGMGR_COMPUTE_SIZE_INVALID; pCIProfile->gpcCount = gpcCount; pCIProfile->smCount = gpcCount * (pKernelMIGGpuInstance->pProfile->smCount / pKernelMIGGpuInstance->pProfile->gpcCount); pCIProfile->veidCount = maxVeidsPerGpc * gpcCount; - + // Force non-profile requests to go through VEID allocator pConfigRequestPerCi[CIIdx].veidSpanStart = KMIGMGR_SPAN_OFFSET_INVALID; } @@ -3624,8 +3594,8 @@ kmigmgrCreateComputeInstances_VF pConfigRequestPerCi[CIIdx].ctsId = ctsId; // Perform VEID request checks or use the best fit allocator to find a slot - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, &shadowVeidInUseMask, pCIProfile->veidCount, &pConfigRequestPerCi[CIIdx].veidSpanStart, @@ -3664,7 +3634,7 @@ kmigmgrCreateComputeInstances_VF bitVectorClrAll(&engines); bitVectorAnd(&engines, &pResourceAllocation->engines, &pKernelMIGGpuInstance->resourceAllocation.localEngines); NV_CHECK_OR_ELSE(LEVEL_ERROR, - bitVectorTestEqual(&engines, &pResourceAllocation->engines), + bitVectorTestEqual(&engines, &pResourceAllocation->engines), status = NV_ERR_INVALID_ARGUMENT; goto done;); // Set Shared/Exclusive Engine Masks for GRs restored @@ -3673,7 +3643,7 @@ kmigmgrCreateComputeInstances_VF bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); // Only 1 GR can be requested per compute instance - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, (kmigmgrCountEnginesOfType(&engines, RM_ENGINE_TYPE_GR(0)) == 1), status = NV_ERR_INVALID_ARGUMENT; goto done;); @@ -3685,7 +3655,7 @@ kmigmgrCreateComputeInstances_VF // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3703,7 +3673,7 @@ kmigmgrCreateComputeInstances_VF // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3721,7 +3691,7 @@ kmigmgrCreateComputeInstances_VF // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3739,7 +3709,7 @@ kmigmgrCreateComputeInstances_VF // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3757,7 +3727,7 @@ kmigmgrCreateComputeInstances_VF // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3775,7 +3745,7 @@ kmigmgrCreateComputeInstances_VF // Exclusive engine mask should not intersect with the current exclusive mask bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); - NV_CHECK_OR_ELSE(LEVEL_ERROR, + NV_CHECK_OR_ELSE(LEVEL_ERROR, bitVectorTestAllCleared(&tempVector), status = NV_ERR_STATE_IN_USE; goto done;); bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); @@ -3801,7 +3771,8 @@ kmigmgrCreateComputeInstances_VF grCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the Copy engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3812,7 +3783,8 @@ kmigmgrCreateComputeInstances_VF ceCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the NVDEC engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3823,7 +3795,8 @@ kmigmgrCreateComputeInstances_VF decCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the NVENC engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3834,7 +3807,8 @@ kmigmgrCreateComputeInstances_VF encCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the NVJPG engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3845,7 +3819,8 @@ kmigmgrCreateComputeInstances_VF jpgCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); // Allocate the NVOFA engines for this compute instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3856,7 +3831,8 @@ kmigmgrCreateComputeInstances_VF ofaCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + &shadowSharedEngMask, + &pKernelMIGGpuInstance->resourceAllocation.engines), done); } // Cache local mask of engine IDs for this compute instance @@ -3868,7 +3844,9 @@ kmigmgrCreateComputeInstances_VF if (!bQuery) { NvU32 swizzId = pKernelMIGGpuInstance->swizzId; + KMIGMGR_CONFIGURE_INSTANCE_REQUEST configRequestsPerCiOrdered[KMIGMGR_MAX_COMPUTE_INSTANCES] = {0}; NvU32 updateEngMask; + NvU32 updateEngMaskShadow; // Populate configure GPU instance parameters with compute instance info updateEngMask = 0x0; @@ -3891,9 +3869,38 @@ kmigmgrCreateComputeInstances_VF updateEngMask |= NVBIT32(RM_ENGINE_TYPE_GR_IDX(localEngineType)); } + // + // Reorder the entries in pConfigRequestPerCi per the GR engine assigned to each CI + // (Sorted from lower GR to higer GR), so kmigmgrConfigureGPUInstance can configure + // each CI with correct GR. + // + updateEngMaskShadow = updateEngMask; + i = 0; + while (updateEngMaskShadow != 0) + { + for (CIIdx = 0; CIIdx < count; ++CIIdx) + { + RM_ENGINE_TYPE localRmEngineType; + MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pComputeInstanceInfo[CIIdx]; + MIG_RESOURCE_ALLOCATION *pComputeResourceAllocation = &pMIGComputeInstance->resourceAllocation; + NV_ASSERT_OK( + kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, RM_ENGINE_TYPE_GR(0), + &pComputeResourceAllocation->engines, &localRmEngineType)); + + if (portUtilCountTrailingZeros32(updateEngMaskShadow) == RM_ENGINE_TYPE_GR_IDX(localRmEngineType)) + { + configRequestsPerCiOrdered[i] = pConfigRequestPerCi[CIIdx]; + updateEngMaskShadow &= ~NVBIT32(RM_ENGINE_TYPE_GR_IDX(localRmEngineType)); + i++; + break; + } + } + NV_ASSERT(CIIdx < count); + } + // Configure the GR engines for each compute instance status = kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, swizzId, - pConfigRequestPerCi, + configRequestsPerCiOrdered, updateEngMask); // Do our best to deconfigure the engines we configured so far, then bail @@ -4222,8 +4229,8 @@ kmigmgrCreateComputeInstances_FWCLIENT pConfigRequestPerCi[0].veidSpanStart = info.spanStart; shadowVeidInUseMask = pKernelGraphicsManager->veidInUseMask; - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, &shadowVeidInUseMask, pConfigRequestPerCi[0].profile.veidCount, &pConfigRequestPerCi[0].veidSpanStart, @@ -4248,7 +4255,7 @@ kmigmgrCreateComputeInstances_FWCLIENT } NV_ASSERT(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].id == KMIGMGR_COMPUTE_INSTANCE_ID_INVALID); - + pMIGComputeInstance->spanStart = pConfigRequestPerCi[0].veidSpanStart; portMemCopy(&pKernelMIGGpuInstance->MIGComputeInstance[CIIdx], @@ -5375,7 +5382,7 @@ kmigmgrSetMIGState_FWCLIENT cleanup_createPartitionCheck); // On Nvswitch based systems, suspend gpu fabric probe on nvlink inband - gpuFabricProbeSuspend(pGpu->pGpuFabricProbeInfo); + gpuFabricProbeSuspend(pGpu->pGpuFabricProbeInfoKernel); // Ensure NVLINK is shutdown before enabling MIG if (!kmigmgrIsMIGNvlinkP2PSupportOverridden(pGpu, pKernelMIGManager) || @@ -5495,8 +5502,12 @@ kmigmgrSetMIGState_FWCLIENT NV_ASSERT_OK( gpuDeleteClassFromClassDBByClassId(pGpu, AMPERE_SMC_PARTITION_REF)); + // // Disable ctx buf pool after freeing any resources that uses it. - pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, NV_FALSE); + // Leave enabled on platforms that support it outside MIG. + // + pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, + gpuIsCtxBufAllocInPmaSupported_HAL(pGpu)); // // HACK: GSP-RM always enables/disables LCEs during MIG enable/disable. @@ -5519,9 +5530,9 @@ kmigmgrSetMIGState_FWCLIENT // On Nvswitch based systems, resume the gpu fabric probe // request on nvlink inband to register the GPU with the nvswitch fabric // - if (pGpu->pGpuFabricProbeInfo != NULL) + if (pGpu->pGpuFabricProbeInfoKernel != NULL) { - NV_ASSERT_OK(gpuFabricProbeResume(pGpu->pGpuFabricProbeInfo)); + NV_ASSERT_OK(gpuFabricProbeResume(pGpu->pGpuFabricProbeInfoKernel)); } cleanup_createPartitionCheck: @@ -5743,6 +5754,12 @@ kmigmgrInitGPUInstancePool_IMPL rmMemPoolSetup((void*)&pKernelMIGGpuInstance->pMemoryPartitionHeap->pmaObject, &pKernelMIGGpuInstance->pPageTableMemPool, version)); + // Allocate the pool in CPR in case of Confidential Compute + if (gpuIsCCFeatureEnabled(pGpu)) + { + rmMemPoolAllocateProtectedMemory(pKernelMIGGpuInstance->pPageTableMemPool, NV_TRUE); + } + return NV_OK; } @@ -6023,6 +6040,24 @@ kmigmgrSaveToPersistence_IMPL return NV_OK; } +/*! + * @brief Update MIG CI config for CPU-RM if compute instance is created + * by a guest and RPC is directly handled by GSP-RM + */ +NV_STATUS +kmigmgrUpdateCiConfigForVgpu_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 execPartCount, + NvU32 *pExecPartId, + NvU32 gfid, + NvBool bDelete +) +{ + return NV_ERR_NOT_SUPPORTED; +} + // Control call for getting active gpu instance Ids NV_STATUS subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL @@ -6577,6 +6612,7 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL pParams->queryPartitionInfo[i].ceCount = kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_COPY(0)); pParams->queryPartitionInfo[i].gpcCount = pResourceAllocation->gpcCount; + pParams->queryPartitionInfo[i].gfxGpcCount = pResourceAllocation->gfxGpcCount; pParams->queryPartitionInfo[i].virtualGpcCount = pResourceAllocation->virtualGpcCount; pParams->queryPartitionInfo[i].nvDecCount = kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_NVDEC(0)); @@ -6605,6 +6641,7 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL continue; pParams->queryPartitionInfo[i].gpcsPerGr[j] = pRpcParams->queryPartitionInfo[i].gpcsPerGr[j]; + pParams->queryPartitionInfo[i].gfxGpcPerGr[j] = pRpcParams->queryPartitionInfo[i].gfxGpcPerGr[j]; pParams->queryPartitionInfo[i].veidsPerGr[j] = pRpcParams->queryPartitionInfo[i].veidsPerGr[j]; pParams->queryPartitionInfo[i].virtualGpcsPerGr[j] = pRpcParams->queryPartitionInfo[i].virtualGpcsPerGr[j]; @@ -6723,20 +6760,26 @@ subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_IMPL if (IS_GSP_CLIENT(pGpu)) { - struct GPUMGR_SAVE_GPU_INSTANCE save; + GPUMGR_SAVE_GPU_INSTANCE *pSave = portMemAllocNonPaged(sizeof(*pSave)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pSave != NULL, + status = NV_ERR_NO_MEMORY; + goto cleanup_mig_state;); + KMIGMGR_CREATE_GPU_INSTANCE_PARAMS restore = { .type = KMIGMGR_CREATE_GPU_INSTANCE_PARAMS_TYPE_RESTORE, - .inst.restore.pGPUInstanceSave = &save, + .inst.restore.pGPUInstanceSave = pSave, }; - save.bValid = NV_TRUE; - save.swizzId = pParams->swizzId; - save.pOsRmCaps = NULL; - portMemCopy(&save.giInfo, sizeof(save.giInfo), &pParams->info, sizeof(pParams->info)); + pSave->bValid = NV_TRUE; + pSave->swizzId = pParams->swizzId; + pSave->pOsRmCaps = NULL; + portMemCopy(&(pSave->giInfo), sizeof(pSave->giInfo), &pParams->info, sizeof(pParams->info)); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, &pParams->swizzId, restore, NV_TRUE, NV_FALSE), - cleanup_rpc); + status = kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, &pParams->swizzId, restore, NV_TRUE, NV_FALSE); + + portMemFree(pSave); + NV_CHECK_OR_GOTO(LEVEL_ERROR, status == NV_OK, cleanup_rpc); } return NV_OK; @@ -6877,9 +6920,10 @@ kmigmgrGetNextComputeSize_IMPL for (i = 1; i < NV_ARRAY_ELEMENTS(computeSizeFlags) - 1; i++) if (computeSizeFlags[i] == computeSize) - break; + return (bGetNextSmallest) ? computeSizeFlags[i + 1] : computeSizeFlags[i - 1]; - return (bGetNextSmallest) ? computeSizeFlags[i + 1] : computeSizeFlags[i - 1]; + // Requested input flag was not found + return KMIGMGR_COMPUTE_SIZE_INVALID; } } diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/mig_config_session.c b/src/nvidia/src/kernel/gpu/mig_mgr/mig_config_session.c index 14ab815a88..2c8613b764 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/mig_config_session.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/mig_config_session.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,8 @@ * *****************************************************************************/ +#define NVOC_MIG_CONFIG_SESSION_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/gpu.h" #include "kernel/gpu/mig_mgr/mig_config_session.h" diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/mig_monitor_session.c b/src/nvidia/src/kernel/gpu/mig_mgr/mig_monitor_session.c index f61a91724a..3d602deced 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/mig_monitor_session.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/mig_monitor_session.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,11 +27,13 @@ * * Description: * Upon successful allocation of this class, a client is granted - * permission to query information across the GPU instances + * permission to query information across the GPU instances * irrespective of per-instance MIG subscriptions * *****************************************************************************/ +#define NVOC_MIG_MONITOR_SESSION_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "kernel/gpu/mig_mgr/mig_monitor_session.h" #include "class/clc640.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c index a6abc17fbc..805fa08eef 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c @@ -91,6 +91,7 @@ kgmmuValidateFabricBaseAddress_GA100 OBJGPU *pGpu = ENG_GET_GPU(pKernelGmmu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU64 fbSizeBytes; + NvU64 fbUpperLimit; fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20; @@ -109,8 +110,10 @@ kgmmuValidateFabricBaseAddress_GA100 // Align fbSize to mapslot size. fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(36)); + fbUpperLimit = fabricBaseAddr + fbSizeBytes; + // Make sure the address range doesn't go beyond the limit, (2K * 64GB). - if ((fabricBaseAddr + fbSizeBytes) > NVBIT64(47)) + if (fbUpperLimit > NVBIT64(47)) { return NV_ERR_INVALID_ARGUMENT; } diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c index 31a24888c7..fd239cb644 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c @@ -58,7 +58,7 @@ void kgmmuFmtInitLevels_GH10X(KernelGmmu *pKernelGmmu, { NV_ASSERT_OR_RETURN_VOID(version == GMMU_FMT_VERSION_3); NV_ASSERT_OR_RETURN_VOID(numLevels >= 7); - + // Page directory 4 (root). pLevels[0].virtAddrBitHi = 56; pLevels[0].virtAddrBitLo = 56; diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c index 57b1ae469a..bbc05c1db3 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,10 +27,13 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "vgpu/vgpu_events.h" #include "nv_sriov_defines.h" +#include "kernel/gpu/intr/intr.h" #include "mmu/gmmu_fmt.h" #include "published/hopper/gh100/dev_mmu.h" #include "published/hopper/gh100/dev_fault.h" +#include "published/hopper/gh100/dev_vm.h" +#include "published/hopper/gh100/dev_vm_addendum.h" /*! * Check if a specific GMMU format version is supported. @@ -55,10 +58,10 @@ kgmmuFmtFamiliesInit_GH100(OBJGPU *pGpu, KernelGmmu* pKernelGmmu) // Initialize the sparse encoding in the PDE PCF field for V3 GMMU_FMT_FAMILY *pFam = pKernelGmmu->pFmtFamilies[GMMU_FMT_VERSION_3 - 1]; - + if (pFam != NULL) { - // 1.Initialize sparsePde + // 1.Initialize sparsePde pdePcfSw |= (1 << SW_MMU_PCF_SPARSE_IDX); pdePcfSw |= (1 << SW_MMU_PCF_ATS_ALLOWED_IDX); NV_ASSERT_OR_RETURN((kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, pdePcfSw, &pdePcfHw) == NV_OK), @@ -66,7 +69,7 @@ kgmmuFmtFamiliesInit_GH100(OBJGPU *pGpu, KernelGmmu* pKernelGmmu) gmmuFieldSetAperture(&pFam->pde.fldAperture, GMMU_APERTURE_INVALID, pFam->sparsePde.v8); nvFieldSet32(&pFam->pde.fldPdePcf, pdePcfHw, pFam->sparsePde.v8); - + // 2.Initialize sparsePdeMulti for (i = 0; i < MMU_FMT_MAX_SUB_LEVELS; ++i) { @@ -79,7 +82,7 @@ kgmmuFmtFamiliesInit_GH100(OBJGPU *pGpu, KernelGmmu* pKernelGmmu) nvFieldSet32(&pPdeFmt->fldPdePcf, pdePcfHw, pFam->sparsePdeMulti.v8); } } - + // 3.Initialize nv4kPte ptePcfSw |= (1 << SW_MMU_PCF_NV4K_IDX); nvFieldSetBool(&pFam->pte.fldValid, NV_FALSE, pFam->nv4kPte.v8); @@ -359,11 +362,83 @@ kgmmuGetFaultRegisterMappings_GH100 NvP64 *pPrefetchCtrl ) { - return kgmmuGetFaultRegisterMappings_TU102(pGpu, pKernelGmmu, index, - pFaultBufferGet, pFaultBufferPut, - pFaultBufferInfo, pHubIntr, - pHubIntrEnSet, pHubIntrEnClear, - faultMask, pPrefetchCtrl); + DEVICE_MAPPING *pMapping = gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0); + NvP64 bar0Mapping = NV_PTR_TO_NvP64(pMapping->gpuNvAddr); + + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + + // + // If Hopper CC is not enabled or GSP doesn't entirely own the HW fault buffers + // use the Turing HAL + // + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + return kgmmuGetFaultRegisterMappings_TU102(pGpu, pKernelGmmu, index, + pFaultBufferGet, pFaultBufferPut, + pFaultBufferInfo, pHubIntr, + pHubIntrEnSet, pHubIntrEnClear, + faultMask, pPrefetchCtrl); + } + + *pFaultBufferGet = 0; + *pFaultBufferInfo = 0; + *pHubIntr = 0; + *pHubIntrEnSet = 0; + *pHubIntrEnClear = 0; + *faultMask = 0; + *pPrefetchCtrl = 0; + + // + // When Hopper CC is enabled, we repurpose the access counter registers to + // hold the PUT pointer of the shadow buffers. Only GSP-RM can write the + // PUT pointer to these PRIs. CPU has read-only access to these PRIs + // + if (index == REPLAYABLE_FAULT_BUFFER) + { + Intr *pIntr = GPU_GET_INTR(pGpu); + NvU32 intrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU, NV_FALSE); + struct GMMU_FAULT_BUFFER *pFaultBuffer; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuf; + FAULT_BUFFER_SHARED_MEMORY *pFaultBufSharedMem; + NvU32 leafReg; + NvU32 leafBit; + + leafReg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVector); + leafBit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVector); + + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF]; + pClientShadowFaultBuf = + KERNEL_POINTER_FROM_NvP64(GMMU_CLIENT_SHADOW_FAULT_BUFFER *, + pFaultBuffer->pClientShadowFaultBuffer[index]); + + pFaultBufSharedMem = + KERNEL_POINTER_FROM_NvP64(FAULT_BUFFER_SHARED_MEMORY *, + pClientShadowFaultBuf->pFaultBufferSharedMemoryAddress); + + *pHubIntr = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(leafReg))); + *pHubIntrEnSet = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(leafReg))); + *pHubIntrEnClear = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(leafReg))); + *faultMask = NVBIT(leafBit); + *pFaultBufferGet = (NvU32*) &(pFaultBufSharedMem->swGetIndex); + *pFaultBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI)); + *pPrefetchCtrl = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL)); + } + else if (index == NON_REPLAYABLE_FAULT_BUFFER) + { + *pFaultBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, + GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO)); + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + + return NV_OK; } NV_STATUS @@ -374,7 +449,71 @@ kgmmuFaultBufferAllocSharedMemory_GH100 FAULT_BUFFER_TYPE index ) { + NV_STATUS status; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + MEMORY_DESCRIPTOR *pMemDesc; + NvU64 flags = MEMDESC_FLAGS_NONE; + + if (pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + NV_PRINTF(LEVEL_ERROR, "Fault-Buffer is disabled. Flush Seq memory cannot be created\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + + if (index != REPLAYABLE_FAULT_BUFFER) + { + return NV_OK; + } + + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + return NV_OK; + } + + // + // On systems with SEV enabled, the fault buffer flush sequence memory should be allocated + // in unprotected sysmem as GSP will be writing to this location to let the guest + // know a flush has finished. + // + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; + status = memdescCreate(&pMemDesc, pGpu, + sizeof(FAULT_BUFFER_SHARED_MEMORY), RM_PAGE_SIZE, + NV_FALSE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, + flags); + if (status != NV_OK) + { + return status; + } + + status = memdescAlloc(pMemDesc); + if (status != NV_OK) + { + goto destroy_memdesc; + } + + status = memdescMap(pMemDesc, 0, + memdescGetSize(pMemDesc), + NV_TRUE, NV_PROTECT_READ_WRITE, + &pClientShadowFaultBuffer->pFaultBufferSharedMemoryAddress, + &pClientShadowFaultBuffer->pFaultBufferSharedMemoryPriv); + if (status != NV_OK) + { + goto free_memory; + } + + pClientShadowFaultBuffer->pFaultBufferSharedMemDesc = pMemDesc; + return NV_OK; + +free_memory: + memdescFree(pMemDesc); + +destroy_memdesc: + memdescDestroy(pMemDesc); + + return status; } void @@ -385,6 +524,29 @@ kgmmuFaultBufferFreeSharedMemory_GH100 FAULT_BUFFER_TYPE index ) { + MEMORY_DESCRIPTOR *pMemDesc; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + + if (index != REPLAYABLE_FAULT_BUFFER) + { + return; + } + + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + return; + } + + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; + pMemDesc = pClientShadowFaultBuffer->pFaultBufferSharedMemDesc; + + memdescUnmap(pMemDesc, + NV_TRUE, osGetCurrentProcess(), + pClientShadowFaultBuffer->pFaultBufferSharedMemoryAddress, + pClientShadowFaultBuffer->pFaultBufferSharedMemoryPriv); + + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); return; } @@ -399,6 +561,73 @@ kgmmuIssueReplayableFaultBufferFlush_GH100 KernelGmmu *pKernelGmmu ) { + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + FAULT_BUFFER_SHARED_MEMORY *pFaultBufSharedMem; + NvU32 gfid; + volatile NvU32 *pFlushSeqAddr; + NvU32 replayableFlushSeqValue; + NV_STATUS status; + RMTIMEOUT timeout; + + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu) || !IS_GSP_CLIENT(pGpu)) + { + return NV_OK; + } + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[gfid].clientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; + pFaultBufSharedMem = KERNEL_POINTER_FROM_NvP64(FAULT_BUFFER_SHARED_MEMORY *, + pClientShadowFaultBuffer->pFaultBufferSharedMemoryAddress); + pFlushSeqAddr = (NvU32*) &(pFaultBufSharedMem->flushBufferSeqNum); + replayableFlushSeqValue = *pFlushSeqAddr; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_DOORBELL, NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE); + + while (replayableFlushSeqValue + 1 != *pFlushSeqAddr) + { + status = gpuCheckTimeout(pGpu, &timeout); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "gpuCheckTimeout failed, status = 0x%x\n", status); + return status; + } + osSpinLoop(); + } return NV_OK; } + +/* + * @brief When Hopper Confidential Compute is enabled, the put index of the + * client replayable/non-replayable shadow buffers gets stored in the + * access counter PRIs. This function is used by Kernel RM to read the put index. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] type Replayable/Non-replayable fault buffer + * + * @returns NvU32 + */ +NvU32 +kgmmuReadShadowBufPutIndex_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE type +) +{ + NvU32 val; + if (type == REPLAYABLE_FAULT_BUFFER) + { + val = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT); + } + else + { + val = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT); + val = DRF_VAL(_VIRTUAL_FUNCTION_PRIV, _NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT, _PTR, val); + } + return val; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c index 478f619303..7e8a472e3f 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c @@ -25,6 +25,7 @@ #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" +#include "vgpu/rpc.h" #include "published/maxwell/gm107/dev_fb.h" #include "published/maxwell/gm107/dev_mmu.h" @@ -36,7 +37,7 @@ * * @returns NvU32 */ -NvU32 +NvU64 kgmmuGetBigPageSize_GM107(KernelGmmu *pKernelGmmu) { return pKernelGmmu->defaultBigPageSize; @@ -78,6 +79,7 @@ kgmmuInvalidateTlb_GM107 NV_STATUS status = NV_OK; TLB_INVALIDATE_PARAMS params; NvU32 flushCount = 0; + NvBool bDoVgpuRpc = NV_FALSE; // // Bail out early if @@ -105,26 +107,29 @@ kgmmuInvalidateTlb_GM107 return; } - // - // Originally the flag is 0, but to WAR bug 2909388, add flag - // GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE to bypass using threadStateCheckTimeout, - // GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD to not wait inside timeout with mutex held. - // - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, ¶ms.timeout, - GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE | - GPU_TIMEOUT_FLAGS_DEFAULT | GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD); - - // - // 2. Wait until we can issue an invalidate. On pre-Turing, wait for space - // in the PRI FIFO. On Turing, check if an invalidate is already in progress. - // - // Set the GFID. - params.gfid = gfid; - - status = kgmmuCheckPendingInvalidates_HAL(pGpu, pKernelGmmu, ¶ms.timeout, params.gfid); - if (status != NV_OK) + if (!bDoVgpuRpc) { - return; + // + // Originally the flag is 0, but to WAR bug 2909388, add flag + // GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE to bypass using threadStateCheckTimeout, + // GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD to not wait inside timeout with mutex held. + // + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, ¶ms.timeout, + GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE | + GPU_TIMEOUT_FLAGS_DEFAULT | GPU_TIMEOUT_FLAGS_BYPASS_CPU_YIELD); + + // + // 2. Wait until we can issue an invalidate. On pre-Turing, wait for space + // in the PRI FIFO. On Turing, check if an invalidate is already in progress. + // + // Set the GFID. + params.gfid = gfid; + + status = kgmmuCheckPendingInvalidates_HAL(pGpu, pKernelGmmu, ¶ms.timeout, params.gfid); + if (status != NV_OK) + { + return; + } } // Trigger an invalidate. @@ -133,7 +138,7 @@ kgmmuInvalidateTlb_GM107 // Not using range-based invalidate. params.regVal = FLD_SET_DRF(_PFB_PRI, _MMU_INVALIDATE, _ALL_VA, _TRUE, params.regVal); - if (NULL != pRootPageDir) + if ((NULL != pRootPageDir) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322)) { // Invalidatating only one VAS. params.regVal = FLD_SET_DRF(_PFB_PRI, _MMU_INVALIDATE, _ALL_PDB, _FALSE, params.regVal); @@ -178,16 +183,22 @@ kgmmuInvalidateTlb_GM107 if (!(status == NV_OK || status == NV_ERR_NOT_SUPPORTED)) return; - // 3 and 4. Commit the invalidate and wait for invalidate to complete. - status = kgmmuCommitTlbInvalidate_HAL(pGpu, pKernelGmmu, ¶ms); - if (status != NV_OK) + if (bDoVgpuRpc) { - return; + } + else + { + // 3 and 4. Commit the invalidate and wait for invalidate to complete. + status = kgmmuCommitTlbInvalidate_HAL(pGpu, pKernelGmmu, ¶ms); + if (status != NV_OK) + { + return; + } } while (flushCount--) { - if (kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BUS_FLUSH_VIDEO_MEMORY) == NV_ERR_TIMEOUT) + if (kbusSendSysmembar(pGpu, GPU_GET_KERNEL_BUS(pGpu)) == NV_ERR_TIMEOUT) { break; } @@ -221,7 +232,7 @@ kgmmuDetermineMaxVASize_GM107 maxFmtVersionSupported = maxFmtVersionSupported < ver ? ver : maxFmtVersionSupported; } } - + switch (maxFmtVersionSupported) { case GMMU_FMT_VERSION_1: @@ -284,7 +295,7 @@ kgmmuEncodeSysmemAddrs_GM107 * * @returns The size of a large page in bytes */ -NvU32 +NvU64 kgmmuGetMaxBigPageSize_GM107(KernelGmmu *pKernelGmmu) { if (!kgmmuIsPerVaspaceBigPageEn(pKernelGmmu)) @@ -317,6 +328,7 @@ kgmmuGetHwPteApertureFromMemdesc_GM107 break; case ADDR_FABRIC_V2: case ADDR_FABRIC_MC: + case ADDR_EGM: aperture = NV_MMU_PTE_APERTURE_PEER_MEMORY; break; case ADDR_FBMEM: diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c b/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c index 0c03b582ef..e50bc0bb81 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c @@ -144,7 +144,7 @@ kgmmuInstBlkPageDirBaseGet_GP100 RmPhysAddr physAdd; NvU32 aperture; NvU32 addrLo; - NvU32 bigPageSize = vaspaceGetBigPageSize(pVAS); + NvU64 bigPageSize = vaspaceGetBigPageSize(pVAS); pPDB = (pParams->bIsClientAdmin) ? vaspaceGetKernelPageDirBase(pVAS, pGpu) : vaspaceGetPageDirBase(pVAS, pGpu); diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c index 4952a58095..5f8d1ad4fa 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c @@ -37,7 +37,7 @@ void kgmmuFmtInitPteComptagLine_TU10X(KernelGmmu *pKernelGmmu, GMMU_FMT_PTE *pPt void kgmmuFmtInitPeerPteFld_TU10X(KernelGmmu *pKernelGmmu, GMMU_FMT_PTE *pPte, const NvU32 version) { NV_ASSERT_OR_RETURN_VOID(version == GMMU_FMT_VERSION_2); - + NV_FIELD_DESC64 *pField = &pPte->fldAddrPeer.desc; pPte->fldAddrPeer.shift = NV_MMU_VER2_PTE_ADDRESS_SHIFT; diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c index b65b954706..baa40ff382 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -428,3 +428,22 @@ kgmmuClearNonReplayableFaultIntr_TU102 Intr *pIntr = GPU_GET_INTR(pGpu); intrClearLeafVector_HAL(pGpu, pIntr, NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE, pThreadState); } + +/*! + * @brief Clear replayable fault interrupt. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] pThreadState THREAD_STATE_NODE pointer + */ +void +kgmmuClearReplayableFaultIntr_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + THREAD_STATE_NODE *pThreadState +) +{ + Intr *pIntr = GPU_GET_INTR(pGpu); + intrClearLeafVector_HAL(pGpu, pIntr, NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE, pThreadState); +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c index 1681a864bf..fbe7c6ab88 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c @@ -474,8 +474,12 @@ kgmmuReportFaultBufferOverflow_GV100 MODS_ARCH_ERROR_PRINTF("MMU Fault Buffer overflow detected\n"); rmStatus = notifyEvents(pGpu, *ppEventNotification, NVC369_NOTIFIER_MMU_FAULT_ERROR, 0, 0, NV_OK, NV_OS_WRITE_THEN_AWAKEN); - if (rmStatus != NV_OK) - return rmStatus; + // + // Mods will check the error and clear error status. As Mods uses Async event + // clearing the error in RM will cause a race with Mods + // + if (RMCFG_FEATURE_MODS_FEATURES) + return rmStatus; } krcBreakpoint(GPU_GET_KERNEL_RC(pGpu)); @@ -484,6 +488,8 @@ kgmmuReportFaultBufferOverflow_GV100 faultStatus = FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_STATUS, _NON_REPLAYABLE_OVERFLOW, _RESET, faultStatus); kgmmuWriteMmuFaultStatus_HAL(pGpu, pKernelGmmu, faultStatus); + + gpuMarkDeviceForReset(pGpu); return rmStatus; } diff --git a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c index 9ce9db3f5b..e2c1955acb 100644 --- a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,7 @@ #include "gpu/gpu.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "gpu/nvlink/kernel_nvlink.h" #include "gpu/bus/kern_bus.h" #include "mem_mgr/gpu_vaspace.h" @@ -180,7 +181,33 @@ _bar2WalkCBFillEntries // Determine how to write the entry value. if (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) { - if (pKernelBus->bar2[gfid].bBootstrap) + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + NvU32 sizeOfEntries; + + NV_ASSERT_OR_RETURN_VOID(pKernelBus->virtualBar2[gfid].pPageLevels == NULL); + + surf.pMemDesc = pMemDesc; + surf.offset = entryIndexLo * pLevelFmt->entrySize; + + sizeOfEntries = (entryIndexHi - entryIndexLo + 1) * pLevelFmt->entrySize; + + pMap = memmgrMemBeginTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC); + + for (entryIndex = entryIndexLo; entryIndex <= entryIndexHi; entryIndex++) + { + NvU32 index = (entryIndex - entryIndexLo) * pLevelFmt->entrySize; + portMemCopy(&pMap[index], pLevelFmt->entrySize, + entryValue.v8, pLevelFmt->entrySize); + } + + memmgrMemEndTransfer(pMemoryManager, &surf, sizeOfEntries, + TRANSFER_FLAGS_SHADOW_ALLOC); + } + else if (pKernelBus->bar2[gfid].bBootstrap) { if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) { @@ -357,22 +384,38 @@ _bar2WalkCBUpdatePde entryOffset = entryIndex * pLevelFmt->entrySize; - // If we are setting up BAR2, we need special handling. - if (pKernelBus->bar2[gfid].bBootstrap) + if (pKernelBus->PDEBAR2Aperture == ADDR_FBMEM) { - entryStart = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), entryOffset); - sizeInDWord = (NvU32)NV_CEIL(pLevelFmt->entrySize, sizeof(NvU32)); + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + + NV_ASSERT_OR_RETURN(pKernelBus->virtualBar2[gfid].pPageLevels == NULL, + NV_FALSE); - for (i = 0; i < sizeInDWord; i++) + surf.pMemDesc = pMemDesc; + surf.offset = entryOffset; + + NV_ASSERT_OR_RETURN(memmgrMemWrite(pMemoryManager, &surf, + entry.v8, pLevelFmt->entrySize, + TRANSFER_FLAGS_NONE) == NV_OK, + NV_FALSE); + } + // If we are setting up BAR2, we need special handling. + else if (pKernelBus->bar2[gfid].bBootstrap) { - if (ADDR_FBMEM == pKernelBus->PDEBAR2Aperture) + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) { - if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) - { - pMap = kbusCpuOffsetInBar2WindowGet(pGpu, pKernelBus, pMemDesc); - portMemCopy(pMap + entryOffset, pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); - } - else + pMap = kbusCpuOffsetInBar2WindowGet(pGpu, pKernelBus, pMemDesc); + portMemCopy(pMap + entryOffset, pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); + } + else + { + entryStart = memdescGetPhysAddr(pMemDesc, AT_PA, entryOffset); + sizeInDWord = (NvU32)NV_CEIL(pLevelFmt->entrySize, sizeof(NvU32)); + + for (i = 0; i < sizeInDWord; i++) { status = kbusMemAccessBar0Window_HAL(pGpu, pKernelBus, (entryStart + (sizeof(NvU32) * i)), @@ -383,25 +426,9 @@ _bar2WalkCBUpdatePde NV_ASSERT_OR_RETURN(NV_OK == status, NV_FALSE); } } - else - { - // Plain old memmap. - status = memdescMapOld(pMemDesc, 0, - pMemDesc->Size, - NV_TRUE, // kernel, - NV_PROTECT_READ_WRITE, - (void **)&pMap, - &pPriv); - NV_ASSERT_OR_RETURN(NV_OK == status, NV_FALSE); - portMemCopy(pMap + entryOffset, pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); - memdescUnmapOld(pMemDesc, 1, 0, pMap, pPriv); - } } - } - else if (pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || - KBUS_BAR0_PRAMIN_DISABLED(pGpu)) - { - if (ADDR_FBMEM == pKernelBus->PDEBAR2Aperture) + else if (pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { NV_ASSERT(NULL != pKernelBus->virtualBar2[gfid].pPageLevels); @@ -413,12 +440,25 @@ _bar2WalkCBUpdatePde } else { - NV_ASSERT(0); // Page level instances in sysmem don't need migration. + NV_ASSERT_OR_RETURN(0, NV_FALSE); // Not yet supported. } } + else if (pKernelBus->PDEBAR2Aperture == ADDR_SYSMEM) + { + // Plain old memmap. + status = memdescMapOld(pMemDesc, 0, + pMemDesc->Size, + NV_TRUE, // kernel, + NV_PROTECT_READ_WRITE, + (void **)&pMap, + &pPriv); + NV_ASSERT_OR_RETURN(NV_OK == status, NV_FALSE); + portMemCopy(pMap + entryOffset, pLevelFmt->entrySize, entry.v8, pLevelFmt->entrySize); + memdescUnmapOld(pMemDesc, 1, 0, pMap, pPriv); + } else { - NV_ASSERT(0); // Not yet supported. + NV_ASSERT_OR_RETURN(0, NV_FALSE); // only SYSMEM and FBMEM are supported. } return NV_TRUE; @@ -488,8 +528,9 @@ _bar2WalkCBLevelAlloc } // Specify which Page Level we are initializing. - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || - KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || + IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)) { if (pLevelFmt == pKernelBus->bar2[gfid].pFmt->pRoot) { @@ -524,7 +565,8 @@ _bar2WalkCBLevelAlloc else { NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || - KBUS_BAR0_PRAMIN_DISABLED(pGpu)); + KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)); pdeBase = pKernelBus->bar2[gfid].pdeBase; pteBase = pKernelBus->bar2[gfid].pteBase; } @@ -604,13 +646,15 @@ _bar2WalkCBLevelAlloc else { NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || - KBUS_BAR0_PRAMIN_DISABLED(pGpu)); + KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)); pKernelBus->bar2[gfid].pdeBase = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); pKernelBus->bar2[gfid].pPDEMemDesc = pMemDesc; } } - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || - KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || + IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)) { pKernelBus->bar2[gfid].pageDirInit++; } @@ -686,14 +730,16 @@ _bar2WalkCBLevelAlloc else { NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || - KBUS_BAR0_PRAMIN_DISABLED(pGpu)); + KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)); pKernelBus->bar2[gfid].pteBase = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); } pKernelBus->virtualBar2[gfid].pPTEMemDesc = pMemDesc; } - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || - KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || + IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + kbusIsBarAccessBlocked(pKernelBus)) { pKernelBus->bar2[gfid].pageTblInit++; } @@ -757,7 +803,29 @@ _bar2WalkCBWriteBuffer pStagingBufferMapping = &pStagingDescMapping[firstEntryOffset % tableSize]; - if (pKernelBus->bar2[gfid].bBootstrap) + if (kbusIsBarAccessBlocked(pKernelBus)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + + NV_ASSERT_OR_RETURN_VOID(pKernelBus->virtualBar2[gfid].pPageLevels == NULL); + + surf.pMemDesc = pOutputBufferDesc; + surf.offset = firstEntryOffset; + + pOutputBufferMapping = memmgrMemBeginTransfer(pMemoryManager, &surf, + entryRangeSize, + TRANSFER_FLAGS_SHADOW_ALLOC); + + portMemCopy(pOutputBufferMapping, entryRangeSize, + pStagingBufferMapping, entryRangeSize); + + memmgrMemEndTransfer(pMemoryManager, &surf, entryRangeSize, + TRANSFER_FLAGS_SHADOW_ALLOC); + + goto unmap_and_exit; + } + else if (pKernelBus->bar2[gfid].bBootstrap) { if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) { @@ -814,6 +882,7 @@ _bar2WalkCBWriteBuffer pStagingBufferMapping, entryRangeSize); +unmap_and_exit: memdescUnmapOld(pStagingBufferDesc, NV_TRUE, 0, pStagingDescMapping, pPriv); if (bRestore) diff --git a/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c b/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c index af0ccc56e2..51196d46a2 100644 --- a/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c @@ -285,7 +285,7 @@ _gmmuWalkCBLevelAlloc // Add memList end entry. memPoolList[memPoolListCount++] = ADDR_UNKNOWN; - NV_ASSERT(memPoolListCount <= NV_ARRAY_ELEMENTS32(memPoolList)); + NV_ASSERT(memPoolListCount <= NV_ARRAY_ELEMENTS(memPoolList)); // MEMDESC flags memDescFlags = MEMDESC_FLAGS_LOCKLESS_SYSMEM_ALLOC | diff --git a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c index 701505370b..bb31a9a926 100644 --- a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c +++ b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -928,6 +928,8 @@ kgmmuFaultBufferGetAddressSpace_IMPL NvU32 faultBufferAttr = 0; NvBool bAllocInVidmem = NV_FALSE; + bAllocInVidmem = gpuIsCCFeatureEnabled(pGpu); + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); if (index == NON_REPLAYABLE_FAULT_BUFFER) @@ -944,8 +946,14 @@ kgmmuFaultBufferGetAddressSpace_IMPL memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_4, _UVM_FAULT_BUFFER_REPLAYABLE, pGpu->instLocOverrides4), "UVM replayable fault", &faultBufferAddrSpace, &faultBufferAttr); } + // + // Whenever Hopper CC is enabled, HW requires both replayable and non-replayable + // fault buffers to be in CPR vidmem. It would be illegal to allocate the buffers + // in any other aperture + // if (bAllocInVidmem && (faultBufferAddrSpace == ADDR_SYSMEM)) { + NV_PRINTF(LEVEL_ERROR, "Fault buffers must be in CPR vidmem when HCC is enabled\n"); NV_ASSERT(0); return NV_ERR_INVALID_ARGUMENT; } @@ -990,9 +998,12 @@ kgmmuFaultBufferCreateMemDesc_IMPL } if ((IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + || gpuIsCCFeatureEnabled(pGpu) ) { // Allocate contiguous fault buffers for SR-IOV Heavy + // Fault buffers get allocated in CPR vidmem when Hopper CC is enabled + // We're almost assured to get contiguous allocations in vidmem isContiguous = NV_TRUE; } @@ -1194,6 +1205,7 @@ kgmmuFaultBufferReplayableAllocate_IMPL pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferClient = hClient; pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferObject = hObject; + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].faultBufferGenerationCounter = 0; return NV_OK; } @@ -1372,13 +1384,29 @@ _kgmmuClientShadowFaultBufferQueueAllocate NV_STATUS status; GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pQueueMemDesc; + NvU64 flags = MEMDESC_FLAGS_NONE; + + // + // On systems with SEV enabled, the client shadow buffers should be allocated + // in unprotected sysmem as GSP will be writing the fault packets to these + // buffers. Since GSP will be encrypting the fault packets, we don't risk + // leaking any information + // + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + // + // Shadow fault buffers are not implemented using circular queues when + // Hopper CC is enabled + // + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + return NV_OK; pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; status = memdescCreate(&pQueueMemDesc, pGpu, sizeof(GMMU_SHADOW_FAULT_BUF), RM_PAGE_SIZE, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE); + flags); if (status != NV_OK) { return status; @@ -1422,6 +1450,13 @@ kgmmuClientShadowFaultBufferQueueDestroy_IMPL GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pQueueMemDesc; + // + // Shadow fault buffers are not implemented using circular queues when + // Hopper CC is enabled. So, there is nothing to free here + // + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + return; + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; pQueueMemDesc = pClientShadowFaultBuffer->pQueueMemDesc; @@ -1443,6 +1478,7 @@ _kgmmuClientShadowFaultBufferPagesAllocate OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NvU32 shadowFaultBufferSize, + NvU32 shadowFaultBufferMetadataSize, FAULT_BUFFER_TYPE index ) { @@ -1450,13 +1486,22 @@ _kgmmuClientShadowFaultBufferPagesAllocate GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pMemDesc; NvU64 flags = MEMDESC_FLAGS_NONE; + NvU32 shadowFaultBufferSizeTotal; + + // + // On systems with SEV enabled, the client shadow buffers should be allocated + // in unprotected sysmem as GSP will be writing the fault packets to these + // buffers. Since GSP will be encrypting the fault packets, we don't risk + // leaking any information + // + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; - shadowFaultBufferSize = RM_PAGE_ALIGN_UP(shadowFaultBufferSize); + shadowFaultBufferSizeTotal = RM_PAGE_ALIGN_UP(shadowFaultBufferSize) + RM_PAGE_ALIGN_UP(shadowFaultBufferMetadataSize); status = memdescCreate(&pMemDesc, pGpu, - shadowFaultBufferSize, RM_PAGE_SIZE, + shadowFaultBufferSizeTotal, RM_PAGE_SIZE, NV_FALSE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); if (status != NV_OK) @@ -1483,6 +1528,9 @@ _kgmmuClientShadowFaultBufferPagesAllocate return status; } + pClientShadowFaultBuffer->pFaultBufferMetadataAddress = + ((NvP64)(((NvU64) pClientShadowFaultBuffer->pBufferAddress) + + RM_PAGE_ALIGN_UP(shadowFaultBufferSize))); pClientShadowFaultBuffer->pBufferMemDesc = pMemDesc; return NV_OK; @@ -1544,6 +1592,7 @@ kgmmuClientShadowFaultBufferRegister_IMPL RmPhysAddr shadowFaultBufferQueuePhysAddr; NvU32 queueCapacity, numBufferPages; NvU32 faultBufferSize; + NvU32 shadowFaultBufferMetadataSize; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); NvBool bQueueAllocated = NV_FALSE; @@ -1553,16 +1602,23 @@ kgmmuClientShadowFaultBufferRegister_IMPL if (index == NON_REPLAYABLE_FAULT_BUFFER) { faultBufferSize = pStaticInfo->nonReplayableFaultBufferSize; + shadowFaultBufferMetadataSize = pStaticInfo->nonReplayableShadowFaultBufferMetadataSize; } else if (index == REPLAYABLE_FAULT_BUFFER) { faultBufferSize = pStaticInfo->replayableFaultBufferSize; + shadowFaultBufferMetadataSize = pStaticInfo->replayableShadowFaultBufferMetadataSize; } else { NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); } + // + // We don't use circular queues for shadow fault buffers when Hopper + // CC is enabled + // + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, pClientShadowFaultBuffer->pQueueAddress); @@ -1627,15 +1683,23 @@ kgmmuClientShadowFaultBufferRegister_IMPL 0, RM_PAGE_SIZE, numBufferPages, pParams->shadowFaultBufferPteArray); + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { shadowFaultBufferQueuePhysAddr = memdescGetPhysAddr(pClientShadowFaultBuffer->pQueueMemDesc, AT_GPU, 0); pParams->shadowFaultBufferQueuePhysAddr = shadowFaultBufferQueuePhysAddr; } - pParams->shadowFaultBufferSize = faultBufferSize; - pParams->shadowFaultBufferType = (index == NON_REPLAYABLE_FAULT_BUFFER) ? - NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE : - NV2080_CTRL_FAULT_BUFFER_REPLAYABLE; + pParams->shadowFaultBufferSize = faultBufferSize; + pParams->shadowFaultBufferMetadataSize = shadowFaultBufferMetadataSize; + pParams->shadowFaultBufferType = (index == NON_REPLAYABLE_FAULT_BUFFER) ? + NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE : + NV2080_CTRL_FAULT_BUFFER_REPLAYABLE; + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu) && index == REPLAYABLE_FAULT_BUFFER) + { + pParams->faultBufferSharedMemoryPhysAddr = memdescGetPhysAddr(pClientShadowFaultBuffer->pFaultBufferSharedMemDesc, + AT_GPU, 0); + } status = pRmApi->Control(pRmApi, pGpu->hInternalClient, @@ -1706,6 +1770,7 @@ kgmmuClientShadowFaultBufferUnregister_IMPL pFaultBuffer->pClientShadowFaultBuffer[index] = NULL; } + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer[index]; pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, @@ -1735,6 +1800,7 @@ kgmmuClientShadowFaultBufferAllocate_IMPL NV_STATUS status; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); NvU32 faultBufferSize; + NvU32 shadowFaultBufferMetadataSize; ct_assert((RM_PAGE_SIZE % sizeof(struct GMMU_FAULT_PACKET)) == 0); @@ -1745,10 +1811,12 @@ kgmmuClientShadowFaultBufferAllocate_IMPL if (index == NON_REPLAYABLE_FAULT_BUFFER) { faultBufferSize = pStaticInfo->nonReplayableFaultBufferSize; + shadowFaultBufferMetadataSize = pStaticInfo->nonReplayableShadowFaultBufferMetadataSize; } else if (index == REPLAYABLE_FAULT_BUFFER) { faultBufferSize = pStaticInfo->replayableFaultBufferSize; + shadowFaultBufferMetadataSize = pStaticInfo->replayableShadowFaultBufferMetadataSize; } else { @@ -1763,6 +1831,7 @@ kgmmuClientShadowFaultBufferAllocate_IMPL status = _kgmmuClientShadowFaultBufferPagesAllocate(pGpu, pKernelGmmu, faultBufferSize, + shadowFaultBufferMetadataSize, index); if (status != NV_OK) { @@ -1841,7 +1910,7 @@ kgmmuClientShadowFaultBufferDestroy_IMPL * * @return NvU32 */ -NvU32 +NvU64 kgmmuGetMinBigPageSize_IMPL(KernelGmmu *pKernelGmmu) { // @@ -1888,6 +1957,8 @@ kgmmuInstBlkInit_IMPL NvU32 dirBaseLoData; NvU32 atsOffset; NvU32 atsData; + NvU32 magicValueOffset; + NvU32 magicValueData; NV_STATUS status = NV_OK; NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); @@ -1912,6 +1983,9 @@ kgmmuInstBlkInit_IMPL atsOffset = 0; atsData = 0; } + + status = kgmmuInstBlkMagicValueGet_HAL(pKernelGmmu, &magicValueOffset, &magicValueData); + // Write the fields out pInstBlk = pInstBlkParams->pInstBlk; @@ -1936,10 +2010,16 @@ kgmmuInstBlkInit_IMPL if (atsOffset != 0) MEM_WR32(pInstBlk + atsOffset, atsData); + + if (status == NV_OK) + MEM_WR32(pInstBlk + magicValueOffset, magicValueData); } else { - pInstBlk = kbusMapRmAperture_HAL(pGpu, pInstBlkDesc); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + pInstBlk = memmgrMemDescBeginTransfer(pMemoryManager, pInstBlkDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); if (pInstBlk == NULL) { return NV_ERR_INSUFFICIENT_RESOURCES; @@ -1965,7 +2045,11 @@ kgmmuInstBlkInit_IMPL if (atsOffset != 0) MEM_WR32(pInstBlk + atsOffset, atsData); - kbusUnmapRmAperture_HAL(pGpu, pInstBlkDesc, &pInstBlk, NV_FALSE); + if (status == NV_OK) + MEM_WR32(pInstBlk + magicValueOffset, magicValueData); + + memmgrMemDescEndTransfer(pMemoryManager, pInstBlkDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); } if (!pInstBlkParams->bDeferFlush) @@ -1974,7 +2058,7 @@ kgmmuInstBlkInit_IMPL | kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pInstBlkDesc))); } - return status; + return NV_OK; } GMMU_APERTURE @@ -2046,9 +2130,20 @@ kgmmuRegisterIntrService_IMPL MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR, }; + static NvU16 engineIdxListForCC[] = { + MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU, + MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU, + }; + + if (IS_GSP_CLIENT(pGpu) && gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + pEngineIdxList = engineIdxListForCC; + listSize = NV_ARRAY_ELEMENTS(engineIdxListForCC); + } + else { pEngineIdxList = engineIdxList; - listSize = NV_ARRAY_ELEMENTS32(engineIdxList); + listSize = NV_ARRAY_ELEMENTS(engineIdxList); } for (NvU32 tableIdx = 0; tableIdx < listSize; tableIdx++) @@ -2100,6 +2195,18 @@ kgmmuServiceInterrupt_IMPL } break; } + case MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU: + { + osQueueMMUFaultHandler(pGpu); + status = 0; + break; + } + case MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU: + { + NV_PRINTF(LEVEL_ERROR, "Unexpected replayable interrupt routed to RM. Verify UVM took ownership.\n"); + status = NV_ERR_INVALID_STATE; + break; + } default: { NV_ASSERT_FAILED("Invalid engineIdx"); @@ -2330,3 +2437,14 @@ kgmmuGetHwFaultBufferPtr_IMPL { return &pKernelGmmu->mmuFaultBuffer[gfid].hwFaultBuffers[faultBufferIndex]; } + +NvU64 +kgmmuGetFaultBufferGenCnt_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU8 gfid +) +{ + return pKernelGmmu->mmuFaultBuffer[gfid].faultBufferGenerationCounter; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c index 161def0680..db3faf4bc4 100644 --- a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c @@ -69,9 +69,17 @@ faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf_IMPL pClientShadowFaultBuffer = pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]; + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + pParams->pShadowBuffer = pClientShadowFaultBuffer->pBufferAddress; + pParams->pShadowBufferContext = NvP64_NULL; + pParams->pShadowBufferMetadata = pClientShadowFaultBuffer->pFaultBufferMetadataAddress; + } + else { pParams->pShadowBuffer = pClientShadowFaultBuffer->pQueueAddress; pParams->pShadowBufferContext = (NvP64) &pClientShadowFaultBuffer->queueContext; + pParams->pShadowBufferMetadata = NvP64_NULL; } pParams->bufferSize = pStaticInfo->nonReplayableFaultBufferSize; @@ -99,12 +107,21 @@ faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf_IMPL if ((pParams->pShadowBuffer != pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]->pQueueAddress) + && (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) ) { NV_PRINTF(LEVEL_ERROR, "Given client shadow fault buffer for non-replayable faults does not " "match with the actual\n"); } + else if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu) && + (pParams->pShadowBuffer != + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]->pBufferAddress)) + { + NV_PRINTF(LEVEL_ERROR, + "Given client shadow fault buffer for non-replayable faults does not " + "match with the actual\n"); + } status = kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); if (status != NV_OK) { @@ -128,6 +145,8 @@ faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + NV_ASSERT_OR_RETURN(gpuIsCCFeatureEnabled(pGpu), NV_ERR_NOT_SUPPORTED); + pClientShadowFaultBuffer = pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; @@ -153,6 +172,7 @@ faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; pParams->pShadowBuffer = pClientShadowFaultBuffer->pBufferAddress; + pParams->pShadowBufferMetadata = pClientShadowFaultBuffer->pFaultBufferMetadataAddress; pParams->bufferSize = pStaticInfo->replayableFaultBufferSize; return NV_OK; @@ -169,6 +189,8 @@ faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pMmuFaultBuffer); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NV_ASSERT_OR_RETURN(gpuIsCCFeatureEnabled(pGpu), NV_ERR_NOT_SUPPORTED); + // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them if (pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER] == NULL) { diff --git a/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c b/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c index 9b2b6fc89e..fe940038d9 100644 --- a/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c +++ b/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -461,23 +461,26 @@ _mmuTraceWalk NvBool verbose ) { - const void *pFmt = pLayout->pFmt; - const MMU_TRACE_CALLBACKS *pTraceCb = pLayout->pTraceCb; - NvU32 index = mmuFmtVirtAddrToEntryIndex(pFmtLevel, va); - NvU64 offset = index * pFmtLevel->entrySize; - NV_STATUS status = NV_OK; - MMU_INVALID_RANGE invalidRange = {0}; - NvU64 entryVa = va; - NvBool isPt = NV_FALSE; - NvU8 *pBase = NULL; - MEMORY_DESCRIPTOR *pTempMemDesc = NULL; + const void *pFmt = pLayout->pFmt; + const MMU_TRACE_CALLBACKS *pTraceCb = pLayout->pTraceCb; + NvU32 index = mmuFmtVirtAddrToEntryIndex(pFmtLevel, va); + NvU64 offset = index * pFmtLevel->entrySize; + NV_STATUS status = NV_OK; + MMU_INVALID_RANGE invalidRange = {0}; + NvU64 entryVa = va; + NvBool isPt = NV_FALSE; + NvU8 *pBase = NULL; + MEMORY_DESCRIPTOR *pTempMemDesc = NULL; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); if (pMemDesc == NULL) { return NV_OK; } - pBase = kbusMapRmAperture_HAL(pGpu, pMemDesc); + pBase = memmgrMemDescBeginTransfer(pMemoryManager, pMemDesc, + TRANSFER_FLAGS_SHADOW_ALLOC | + TRANSFER_FLAGS_SHADOW_INIT_MEM); if (pBase == NULL) { return NV_ERR_INSUFFICIENT_RESOURCES; @@ -572,9 +575,10 @@ _mmuTraceWalk continue; } - NV_ASSERT_OK_OR_RETURN( + NV_ASSERT_OK_OR_GOTO(status, mmuWalkGetPageLevelInfo(pWalk, &pFmtLevel->subLevels[i], entryVa, - (const MMU_WALK_MEMDESC**)&pTempMemDesc, &memSize)); + (const MMU_WALK_MEMDESC**)&pTempMemDesc, &memSize), + unmap_and_exit); // Only print out the PDE the first time we know it's a valid PDE if (!valid) @@ -659,7 +663,7 @@ _mmuTraceWalk unmap_and_exit: - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pBase, NV_FALSE); + memmgrMemDescEndTransfer(pMemoryManager, pMemDesc, TRANSFER_FLAGS_DEFER_FLUSH); return status; } diff --git a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c index f286623067..d0e4635cd2 100644 --- a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c @@ -25,6 +25,7 @@ #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/nvdec/kernel_nvdec_ctx.h" +#include "kernel/gpu/device/device.h" #include "class/cla0b0.h" // NVA0B0_VIDEO_DECODER #include "class/clb0b0.h" // NVB0B0_VIDEO_DECODER @@ -97,10 +98,19 @@ nvdecGetEngineDescFromAllocParams KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE rmEngineType; + RsResourceRef *pDeviceRef = NULL; NV_ASSERT_OK( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pCallContext->pClient->hClient, &ref)); + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef)); + + if (pDeviceRef == NULL) + return ENG_INVALID; + + NV_ASSERT_OK( + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + dynamicCast(pDeviceRef->pResource, Device), + &ref)); NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, diff --git a/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c b/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c index cbd600c81b..b329b3f4bc 100644 --- a/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c @@ -24,6 +24,7 @@ #include "os/os.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/gpu/device/device.h" #include "class/clc0b7.h" #include "class/cld0b7.h" @@ -75,8 +76,14 @@ msencGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAl case NVC7B7_VIDEO_ENCODER: case NVC9B7_VIDEO_ENCODER: engineInstance = pMsencAllocParms->engineInstance; + NV_PRINTF(LEVEL_INFO, "Supported msenc class Id (classId = 0x%x / engineInstance = 0x%x)\n", + externalClassId, + engineInstance); break; default: + NV_PRINTF(LEVEL_ERROR, "Not supported msenc class Id (classId = 0x%x / engineInstance = 0x%x)\n", + externalClassId, + pMsencAllocParms->engineInstance); return ENG_INVALID; } @@ -85,10 +92,19 @@ msencGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAl KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE rmEngineType; + RsResourceRef *pDeviceRef = NULL; NV_ASSERT_OK( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pCallContext->pClient->hClient, &ref)); + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef)); + + if (pDeviceRef == NULL) + return ENG_INVALID; + + NV_ASSERT_OK( + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + dynamicCast(pDeviceRef->pResource, Device), + &ref)); NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, diff --git a/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c b/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c index 8eb375c689..d35c34e9bc 100644 --- a/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c @@ -23,6 +23,7 @@ #include "gpu/gpu.h" #include "gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/device/device.h" #include "nvos.h" #include "resserv/rs_server.h" @@ -71,9 +72,16 @@ nvjpgGetEngineDescFromAllocParams case NVB8D1_VIDEO_NVJPG: case NVC9D1_VIDEO_NVJPG: engineInstance = pNvjpgAllocParms->engineInstance; + NV_PRINTF(LEVEL_INFO, "Supported nvjpg class Id (classId = 0x%x / engineInstance = 0x%x)\n", + externalClassId, + engineInstance); break; + default: DBG_BREAKPOINT(); + NV_PRINTF(LEVEL_ERROR, "Not supported nvjpg class Id (classId = 0x%x / engineInstance = 0x%x)\n", + externalClassId, + pNvjpgAllocParms->engineInstance); return ENG_INVALID; } @@ -82,10 +90,19 @@ nvjpgGetEngineDescFromAllocParams KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; RM_ENGINE_TYPE rmEngineType; + RsResourceRef *pDeviceRef = NULL; + + NV_ASSERT_OK( + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef)); + + if (pDeviceRef == NULL) + return ENG_INVALID; NV_ASSERT_OK( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pCallContext->pClient->hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + dynamicCast(pDeviceRef->pResource, Device), + &ref)); NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c index b2bc09b9b5..a80ec9180a 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" @@ -31,7 +33,7 @@ * @brief This routine overrides the nvlink connection topology if chiplib arguments * have been provided. It queries MODS API for the chiplib overrides and based * on that, derives hshub configuration values that are programmed at a later - * stage during nvlink state load. The override values should exist for ALL + * stage during nvlink state load. The override values should exist for ALL * links or NO links. The field encoding can be found in phys_nvlink.h * * @param[in] pGpu OBJGPU pointer @@ -249,3 +251,36 @@ knvlinkValidateFabricBaseAddress_GA100 return NV_OK; } + +/*! + * @brief Checks to see if the GPU is a reduced nvlink config + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * + * @returns On the gpu being a reduced config, NV_TRUE. + * otherwise , returns NV_FALSE. + */ +NvBool +knvlinkIsGpuReducedNvlinkConfig_GA100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS params; + NV_STATUS status; + + portMemSet(¶ms, 0, sizeof(params)); + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to execute GSP-RM GPC to get if the gpu has a reduced Nvlink config\n"); + return NV_FALSE; + } + + return params.bReducedNvlinkConfig; +} diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c index 22fbe7b0ec..cd7b031c29 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" @@ -29,6 +31,7 @@ #include "nverror.h" #include "objtmr.h" #include "gpu_mgr/gpu_mgr.h" +#include "gpu/gpu_fabric_probe.h" /*! * @brief Check if ALI is supported for the given device @@ -210,7 +213,7 @@ knvlinkDiscoverPostRxDetLinks_GH100 // // Initialize Mask of links that have made it past RxDet to 0 then // request to get all links from the given GPU that have gotted past RxDet - // + // pKernelNvlink0->postRxDetLinkMask = 0; status = knvlinkUpdatePostRxDetectLinkMask(pGpu0, pKernelNvlink0); if(status != NV_OK) @@ -441,7 +444,7 @@ knvlinkGetNumLinksToBeReducedPerIoctrl_GH100 * @param[in] pGpu OBJGPU pointer of local GPU * @param[in] pKernelNvlink reference of KernelNvlink * @param[in] pRemoteGpu OBJGPU pointer of remote GPU - * @param[in/out] pPeerLinkMask reference of peerLinkMask + * @param[in/out] pPeerLinkMask reference of peerLinkMask */ void knvlinkGetEffectivePeerLinkMask_GH100 @@ -457,14 +460,20 @@ knvlinkGetEffectivePeerLinkMask_GH100 NvU32 numLinksPerIoctrl, numIoctrls; KernelNvlink *pRemoteKernelNvlink; NvU32 numLinksToBeReduced; + NvU32 linkMaskToBeReduced; NvU32 linkId, count, i; gpuInstance = gpuGetInstance(pGpu); remoteGpuInstance = gpuGetInstance(pRemoteGpu); - // Do not support NVSwitch systems for now. if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) { + if (gpuFabricProbeGetlinkMaskToBeReduced(pGpu->pGpuFabricProbeInfoKernel, + &linkMaskToBeReduced) == NV_OK) + { + *pPeerLinkMask &= (~linkMaskToBeReduced); + } + return; } @@ -481,7 +490,7 @@ knvlinkGetEffectivePeerLinkMask_GH100 // pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); remotePeerLinkMask = pRemoteKernelNvlink->peerLinkMasks[gpuInstance]; - NV_ASSERT(nvPopCount32(remotePeerLinkMask) == nvPopCount32(peerLinkMask)); + NV_ASSERT(nvPopCount32(remotePeerLinkMask) == nvPopCount32(peerLinkMask)); // Find out number of active NVLinks between the two GPUs. numLinksToBeReduced = knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pKernelNvlink); @@ -623,6 +632,22 @@ knvlinkSetUniqueFabricBaseAddress_GH100 return NV_OK; } +/*! + * @brief Clear unique fabric address for NVSwitch enabled systems. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + */ +void +knvlinkClearUniqueFabricBaseAddress_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + pKernelNvlink->fabricBaseAddr = NVLINK_INVALID_FABRIC_ADDR; +} + /*! * @brief Check if system has enough active NVLinks and * enough NVLink bridges @@ -640,10 +665,13 @@ knvlinkDirectConnectCheck_GH100 { NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS params = {0}; - knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + if (knvlinkExecGspRmRpc(pGpu, pKernelNvlink, NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK, (void *)¶ms, - sizeof(params)); + sizeof(params)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Fail to call direct conect check command\n"); + } } /*! diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c index a7a1d4c0ed..adabf13f7f 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" @@ -282,6 +284,7 @@ knvlinkSetupPeerMapping_GP100 portMemSet(&preSetupNvlinkPeerParams, 0, sizeof(preSetupNvlinkPeerParams)); preSetupNvlinkPeerParams.peerId = peerId; preSetupNvlinkPeerParams.peerLinkMask = peerLinkMask; + preSetupNvlinkPeerParams.bEgmPeer = GPU_GET_KERNEL_BUS(pGpu)->p2p.bEgmPeer[peerId]; preSetupNvlinkPeerParams.bNvswitchConn = knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink); status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c b/src/nvidia/src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c index 2c4082793e..536d10ad68 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c index b79b7b11ca..330b6d1b2e 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "nvRmReg.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c index 1db8e82f6b..037de784f8 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "os/os.h" @@ -330,27 +332,32 @@ _knvlinkAreLinksDisconnected NV_ASSERT_OR_RETURN(bLinkDisconnected != NULL, NV_ERR_INVALID_ARGUMENT); - NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS params; + NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS *pParams = + portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + return NV_ERR_NO_MEMORY; + } - portMemSet(¶ms, 0, sizeof(params)); - params.linkMask = pKernelNvlink->enabledLinks; + portMemSet(pParams, 0, sizeof(*pParams)); + pParams->linkMask = pKernelNvlink->enabledLinks; status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO, - (void *)¶ms, sizeof(params)); + (void *)pParams, sizeof(*pParams)); if (status != NV_OK) - return status; + goto cleanup; FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) { - if ((params.linkInfo[linkId].linkState == NVLINK_LINKSTATE_SAFE) && - (params.linkInfo[linkId].txSublinkState == NVLINK_SUBLINK_STATE_TX_OFF) && - (params.linkInfo[linkId].rxSublinkState == NVLINK_SUBLINK_STATE_RX_OFF)) + if ((pParams->linkInfo[linkId].linkState == NVLINK_LINKSTATE_SAFE) && + (pParams->linkInfo[linkId].txSublinkState == NVLINK_SUBLINK_STATE_TX_OFF) && + (pParams->linkInfo[linkId].rxSublinkState == NVLINK_SUBLINK_STATE_RX_OFF)) { // Case 1: Pseudo-clean shutdown bLinkDisconnected[linkId] = NV_TRUE; } - else if (params.linkInfo[linkId].bLinkReset) + else if (pParams->linkInfo[linkId].bLinkReset) { // Case 2: Link reset post shutdown bLinkDisconnected[linkId] = NV_TRUE; @@ -363,6 +370,9 @@ _knvlinkAreLinksDisconnected } FOR_EACH_INDEX_IN_MASK_END; +cleanup: + portMemFree(pParams); + return status; } @@ -500,6 +510,7 @@ knvlinkValidateFabricBaseAddress_GV100 { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU64 fbSizeBytes; + NvU64 fbUpperLimit; fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20; @@ -518,8 +529,10 @@ knvlinkValidateFabricBaseAddress_GV100 // Align fbSize to mapslot size. fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(34)); + fbUpperLimit = fabricBaseAddr + fbSizeBytes; + // Make sure the address range doesn't go beyond the limit, (8K * 16GB). - if ((fabricBaseAddr + fbSizeBytes) > NVBIT64(47)) + if (fbUpperLimit > NVBIT64(47)) { return NV_ERR_INVALID_ARGUMENT; } diff --git a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c index 1db199f560..b543ac9880 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/gpu.h" #include "gpu/subdevice/subdevice.h" #include "vgpu/rpc.h" @@ -622,7 +624,7 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL FOR_EACH_INDEX_IN_MASK(32, i, pParams->enabledLinkMask) { NV2080_CTRL_NVLINK_DEVICE_INFO *pDeviceInfo = &pParams->linkInfo[i].remoteDeviceInfo; - OBJGPU *pLoopGpu = gpumgrGetGpuFromUuid(pDeviceInfo->deviceUUID, + OBJGPU *pLoopGpu = gpumgrGetGpuFromUuid(pDeviceInfo->deviceUUID, DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY)); diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_ioctrl.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_ioctrl.c index febe018ee8..892148b8af 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_ioctrl.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_ioctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c index 985a2a715e..c7b1fd8a8c 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" @@ -643,12 +648,20 @@ knvlinkInbandMsgCallbackDispatcher_WORKITEM pHeader = (nvlink_inband_msg_header_t *)pMessage->data; + if (pKernelNvlink->inbandCallback[pHeader->type].pCallback == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "No Callback Registered for type %d. Dropping the msg\n", + pHeader->type); + return; + } + // Assert reserved in msgHdr are zero pRsvd = &pHeader->reserved[0]; NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, sizeof(pHeader->reserved) - 1) == 0); - pKernelNvlink->inbandCallback[pHeader->type].pCallback(gpuInstance, pData); + (void)pKernelNvlink->inbandCallback[pHeader->type].pCallback(gpuInstance, pData); } NV_STATUS @@ -1057,7 +1070,7 @@ knvlinkPrepareForXVEReset_IMPL // If GFW is booted and running through link-training, then no need to tear-down the // links to reset. Exit out early from the function // - if (!bForceShutdown && pKernelNvlink->getProperty(pNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) + if (!bForceShutdown && pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) { return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c index d2e1d760e4..5a031f8b8d 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2026-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2026-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c index b04dd5a858..104e1e4ed0 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" @@ -211,6 +213,7 @@ knvlinkCoreAddDevice_IMPL dev->numIoctrls = nvPopCount32(pKernelNvlink->ioctrlMask); dev->numActiveLinksPerIoctrl = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); dev->numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); + dev->bReducedNvlinkConfig = knvlinkIsGpuReducedNvlinkConfig_HAL(pGpu, pKernelNvlink); // Register the GPU in nvlink core if (nvlink_lib_register_device(dev) != 0) diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c index 4cefc6e100..9d6be7d1b1 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" @@ -493,7 +498,7 @@ knvlinkCoreSetDlLinkModeCallback OBJGPU *pGpu = NULL; KernelNvlink *pKernelNvlink = NULL; KernelIoctrl *pKernelIoctrl = NULL; - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; NvU8 linkIndex; NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS params; NV2080_CTRL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c index 144d9c414e..5cb6568f38 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/hal.h" #include "core/info_block.h" @@ -1030,7 +1032,7 @@ knvlinkCoreShutdownDeviceLinks_IMPL NvU32 linkId; // Skip link shutdown where fabric manager is present, for nvlink version bellow 4.0 - if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 && + if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 && pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED)) || (pKernelNvlink->pNvlinkDev == NULL)) { @@ -1049,7 +1051,7 @@ knvlinkCoreShutdownDeviceLinks_IMPL return NV_OK; } - if (!bForceShutdown && pKernelNvlink->getProperty(pNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) + if (!bForceShutdown && pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_MINION_GFW_BOOT)) { NV_PRINTF(LEVEL_INFO, "GFW boot is enabled. Link shutdown is not required, skipping\n"); @@ -1068,7 +1070,7 @@ knvlinkCoreShutdownDeviceLinks_IMPL { OBJGPU* pRemoteGpu = gpumgrGetGpuFromBusInfo( pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.domain, - pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bus, + pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bus, pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.device); if (API_GPU_IN_RESET_SANITY_CHECK(pRemoteGpu)) { @@ -1129,7 +1131,7 @@ knvlinkCoreResetDeviceLinks_IMPL NvU32 linkId; // Skip link reset where fabric manager is present, for nvlink version bellow 4.0 - if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 && + if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 && pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED)) || (pKernelNvlink->pNvlinkDev == NULL)) { @@ -1342,6 +1344,12 @@ knvlinkFloorSweep_IMPL } FOR_EACH_INDEX_IN_MASK_END; + // + // This call must be before the floorswept to cache the NVLink bridge + // information in physical RM. + // + knvlinkDirectConnectCheck_HAL(pGpu, pKernelNvlink); + // floorsweeping in corelib will update connection info that RM qill query below (void)nvlink_lib_powerdown_floorswept_links_to_off(pKernelNvlink->pNvlinkDev); @@ -2434,7 +2442,7 @@ _knvlinkPrintTopologySummary } NV_PRINTF(LEVEL_INFO, "GPU%02u cached topology:\n", gpuGetInstance(pGpu)); - + NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS params; portMemSet(¶ms, 0, sizeof(params)); diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c index fcaaa83558..ca243face2 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "nvRmReg.h" diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c index ddb8ab09db..5b425469b7 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,11 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + +// FIXME XXX +#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED + #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "kernel/gpu/mem_sys/kern_mem_sys.h" @@ -193,7 +198,7 @@ knvlinkConstructEngine_IMPL return status; } - // + // // When GSP inform about link error occurs on this GPU // it will updated to NV_TRUE // @@ -1076,15 +1081,15 @@ knvlinkSetDegradedMode_IMPL if (!pKernelNvlink) { NV_PRINTF(LEVEL_ERROR, - "Failed to get Local Nvlink info for linkId %d to update Degraded GPU%d status\n", + "Failed to get Local Nvlink info for linkId %d to update Degraded GPU%d status\n", linkId, pGpu->gpuInstance); - - return; + + return; } if(pKernelNvlink->bIsGpuDegraded) { - return; + return; } //Find the remote GPU/NVLink attached to this link, if any @@ -1096,29 +1101,32 @@ knvlinkSetDegradedMode_IMPL break; } } - + if (pRemoteGpu == NULL) { NV_PRINTF(LEVEL_ERROR, - "Failed to get Remote GPU info for linkId %d to update Degraded GPU%d status\n", + "Failed to get Remote GPU info for linkId %d to update Degraded GPU%d status\n", linkId, pGpu->gpuInstance); - - return; + + return; } pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); if (!pRemoteKernelNvlink) { NV_PRINTF(LEVEL_ERROR, - "Failed to get Remote Nvlink info for linkId %d to update Degraded GPU%d status\n", + "Failed to get Remote Nvlink info for linkId %d to update Degraded GPU%d status\n", linkId, pGpu->gpuInstance); - - return; + + return; } if (pRemoteKernelNvlink->bIsGpuDegraded == NV_FALSE) { pKernelNvlink->bIsGpuDegraded = NV_TRUE; + NV_PRINTF(LEVEL_ERROR, + "GPU%d marked Degraded for error on linkId %d \n", + pGpu->gpuInstance, linkId); // shutdown all the links on this GPU status = knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, NV_TRUE); @@ -1128,7 +1136,7 @@ knvlinkSetDegradedMode_IMPL "failed to shutdown links on degraded GPU%d\n", pGpu->gpuInstance); } } - + return; } @@ -1144,7 +1152,7 @@ knvlinkDestruct_IMPL // Destroy the RM NVLink state _knvlinkPurgeState(pGpu, pKernelNvlink); - + // Free Ioctrls for (ioctrlIdx = 0; ioctrlIdx < NVLINK_MAX_IOCTRLS_SW; ioctrlIdx++) { diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf.c b/src/nvidia/src/kernel/gpu/perf/kern_perf.c index 387ddf29de..55a58d0aa4 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf.c @@ -54,40 +54,49 @@ kperfConstructEngine_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf, ENGDESCRIPTOR e NV_STATUS kperfStateInitLocked_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NV_STATUS status = NV_OK; // Initialize SW state corresponding to SLI GPU Boost synchronization. status = kperfGpuBoostSyncStateInit(pGpu, pKernelPerf); - // Initialize PFM_REQ_HNDLR module which is a child of OBJSYS - if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && pPlatformRequestHandler != NULL) { - pfmreqhndlrStateInit(pPlatformRequestHandler); + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + + // Initialize PFM_REQ_HNDLR module which is a child of OBJSYS + if (pPlatformRequestHandler != NULL) + { + pfmreqhndlrStateInit(pPlatformRequestHandler); + } } return status; } - + /*! * @copydoc kperfStateLoad */ NV_STATUS kperfStateLoad_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf, NvU32 flags) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJCL *pCl = SYS_GET_CL(pSys); - PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); - // Initialize SW state corresponding to SLI GPU Boost synchronization. kperfGpuBoostSyncStateInit(pGpu, pKernelPerf); - // Load PFM_REQ_HNDLR module which is a child of OBJSYS - // Skip pfmreqhndlrStateLoad on eGPU - if (!(pCl->getProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU)) && RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) { - pfmreqhndlrStateLoad(pPlatformRequestHandler); + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + + // Load PFM_REQ_HNDLR module which is a child of OBJSYS + // Skip pfmreqhndlrStateLoad on eGPU + if (!(pCl->getProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU)) && + (pPlatformRequestHandler != NULL)) + { + pfmreqhndlrStateLoad(pPlatformRequestHandler); + } } return NV_OK; @@ -104,13 +113,15 @@ kperfStateUnload_IMPL NvU32 flags ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); - - if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) { - // Unload PFM_REQ_HNDLR module which is a child of OBJSYS - pfmreqhndlrStateUnload(pPlatformRequestHandler); + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + if ((pPlatformRequestHandler != NULL)) + { + // Unload PFM_REQ_HNDLR module which is a child of OBJSYS + pfmreqhndlrStateUnload(pPlatformRequestHandler); + } } return NV_OK; @@ -126,13 +137,15 @@ kperfStateDestroy_IMPL KernelPerf *pKernelPerf ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); - - // destroy PFM_REQ_HNDLR module state - if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) { - pfmreqhndlrStateDestroy(pPlatformRequestHandler); + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + // destroy PFM_REQ_HNDLR module state + if (pPlatformRequestHandler != NULL) + { + pfmreqhndlrStateDestroy(pPlatformRequestHandler); + } } } diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c index 93dec2a6fd..619ceab04f 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c @@ -378,7 +378,7 @@ kperfGpuBoostSyncStateUpdate } } } - // Intentionaly ignoring the status as we want to rollback the algorithm + // Intentionaly ignoring the status as we want to rollback the algorithm // activation and return previously failing status if (pGpuItr == pGpuItr2) diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c index f0a1d9c8ec..da022fde8b 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c @@ -25,7 +25,7 @@ #include "os/os.h" #include "gpu/subdevice/subdevice.h" #include "rmapi/rmapi.h" -#include "rmapi/rs_utils.h" +#include "rmapi/rs_utils.h" #include "gpu/gpu.h" #include "gpu/perf/kern_perf_pm.h" @@ -66,7 +66,8 @@ kPerfPerfmonClientDeviceSet RS_ITERATOR it; NV_STATUS status = NV_OK; - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + pClient = serverutilGetClientUnderLock(hClient); + if (pClient == NULL) { return NV_ERR_INVALID_CLIENT; } @@ -97,7 +98,7 @@ kPerfPerfmonClientDeviceSet NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS params = {0}; params.bReservation = bReservation; - status = pRmApi->Control(pRmApi, + status = pRmApi->Control(pRmApi, hClient, it.pResourceRef->hResource, NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK, @@ -220,7 +221,7 @@ kPerfPerfmonClientDeviceSet NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, + pRmApi->Control(pRmApi, hClient, it.pResourceRef->hResource, NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET, diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perfbuffer.c b/src/nvidia/src/kernel/gpu/perf/kern_perfbuffer.c index 491572e5be..f9e430dfb3 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perfbuffer.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perfbuffer.c @@ -58,7 +58,7 @@ perfbufferConstructHal_KERNEL NV_CHECK_OK_OR_RETURN(LEVEL_NOTICE, perfbufferPrivilegeCheck(pResource)); NV_RM_RPC_ALLOC_OBJECT(pGpu, hClient, hParent, hMemory, class, - pParams->pAllocParams, status); + pParams->pAllocParams, pParams->paramsSize, status); return status; } diff --git a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c index 868d15a56f..fd1849abec 100644 --- a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c +++ b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c index 99824d1fd2..115e29ddbb 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,7 @@ #include "kernel/gpu/mmu/kern_gmmu.h" #include "kernel/os/os.h" #include "rmapi/client.h" +#include "rmapi/rs_utils.h" #include "ctrl/ctrl506f.h" @@ -147,6 +148,7 @@ krcResetCallback if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_RC) == NV_OK) { + RsClient *pClient; KernelChannel *pKernelChannel = NULL; threadStateInitISRAndDeferredIntHandler( @@ -156,11 +158,11 @@ krcResetCallback NV_ASSERT_OK_OR_GOTO( status, - serverGetClientUnderLock(&g_resServ, hClient, NULL), + serverGetClientUnderLock(&g_resServ, hClient, &pClient), error_cleanup); NV_ASSERT_OK_OR_GOTO( status, - CliGetKernelChannel(hClient, hChannel, &pKernelChannel), + CliGetKernelChannel(pClient, hChannel, &pKernelChannel), error_cleanup); NV_ASSERT_OR_ELSE(pKernelChannel != NULL, @@ -233,7 +235,6 @@ krcErrorInvokeCallback_IMPL OBJOS *pOS = SYS_GET_OS(pSys); KernelMIGManager *pKernelMigManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); RmClient *pClient = NULL; - RsClient *pRsClient; RC_CALLBACK_STATUS clientAction; RM_ENGINE_TYPE localRmEngineType = rmEngineType; NvU32 rcDiagRecOwner = RCDB_RCDIAG_DEFAULT_OWNER; @@ -243,13 +244,7 @@ krcErrorInvokeCallback_IMPL NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), bReturn); NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelChannel != NULL, bReturn); - status = serverGetClientUnderLock(&g_resServ, - RES_GET_CLIENT_HANDLE(pKernelChannel), - &pRsClient); - if (status != NV_OK) - return bReturn; - - pClient = dynamicCast(pRsClient, RmClient); + pClient = dynamicCast(RES_GET_CLIENT(pKernelChannel), RmClient); if (pClient == NULL) return bReturn; @@ -263,7 +258,7 @@ krcErrorInvokeCallback_IMPL MIG_INSTANCE_REF ref; status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMigManager, - pRsClient->hClient, + RES_GET_CLIENT_HANDLE(pKernelChannel), &ref); if (status != NV_OK) return bReturn; @@ -293,7 +288,7 @@ krcErrorInvokeCallback_IMPL Device *pDevice; NV_ASSERT_OK_OR_RETURN( - deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice)); + deviceGetByGpu(RES_GET_CLIENT(pKernelChannel), pGpu, NV_TRUE, &pDevice)); hDevice = RES_GET_HANDLE(pDevice); diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_ctrl.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_ctrl.c index 03400ed1d6..3ba2e34add 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_ctrl.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_ctrl.c @@ -49,7 +49,7 @@ subdeviceCtrlCmdRcReadVirtualMem_IMPL return NV_ERR_INVALID_ARGUMENT; } - if (CliGetKernelChannelWithDevice(RES_GET_CLIENT_HANDLE(pSubdevice), + if (CliGetKernelChannelWithDevice(RES_GET_CLIENT(pSubdevice), RES_GET_PARENT_HANDLE(pSubdevice), pReadVirtMemParam->hChannel, &pKernelChannel) == NV_OK) diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_misc.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_misc.c index c165cddc13..8a0fefcb3c 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_misc.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_misc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,6 +43,7 @@ NV_STATUS krcReadVirtMem_IMPL ) { VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); MEMORY_DESCRIPTOR memDesc; NvU32 pageStartOffset; @@ -54,6 +55,7 @@ NV_STATUS krcReadVirtMem_IMPL NvU32 cursize; NvU32 cur4kPage; NV_STATUS status = NV_OK; + TRANSFER_SURFACE surf = {0}; pageStartOffset = NvOffset_LO32(virtAddr) & RM_PAGE_MASK; start4kPage = (NvOffset_LO32(virtAddr) >> 12) & 0x1FFFF; @@ -78,6 +80,10 @@ NV_STATUS krcReadVirtMem_IMPL pMem = (NvU8*) osMapKernelSpace(physaddr, RM_PAGE_SIZE, NV_MEMORY_UNCACHED, NV_PROTECT_READ_WRITE); + if (pMem == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } } else if (memtype == ADDR_FBMEM) { @@ -88,11 +94,20 @@ NV_STATUS krcReadVirtMem_IMPL NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); memdescDescribe(&memDesc, ADDR_FBMEM, physaddr, RM_PAGE_SIZE); - pMem = kbusMapRmAperture_HAL(pGpu, &memDesc); - } - if (pMem == NULL) - { - return NV_ERR_INSUFFICIENT_RESOURCES; + + surf.pMemDesc = &memDesc; + surf.offset = 0; + + pMem = portMemAllocNonPaged(RM_PAGE_SIZE); + if (pMem == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + NV_ASSERT_OK_OR_ELSE(status, + memmgrMemRead(pMemoryManager, &surf, pMem, RM_PAGE_SIZE, + TRANSFER_FLAGS_NONE), + portMemFree(pMem); return status; ); } if (cursize > bufSize) { @@ -110,7 +125,7 @@ NV_STATUS krcReadVirtMem_IMPL } else if (memtype == ADDR_FBMEM) { - kbusUnmapRmAperture_HAL(pGpu, &memDesc, &pMem, NV_TRUE); + portMemFree(pMem); memdescDestroy(&memDesc); } pMem = NULL; diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c index c58f3d9970..6255f73edc 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c @@ -44,7 +44,7 @@ _krcErrorWriteNotifierCpuMemHelper ( OBJGPU *pGpu, Memory *pMemory, - NvHandle hClient, + RsClient *pClient, NvU32 exceptType, RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus @@ -56,7 +56,7 @@ _krcErrorWriteNotifierCpuMemHelper { case ADDR_VIRTUAL: notifyFillNotifierGPUVA(pGpu, - hClient, + pClient, RES_GET_HANDLE(pMemory), memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU_VA, 0), exceptType, @@ -147,7 +147,7 @@ krcErrorWriteNotifier_CPU { status = _krcErrorWriteNotifierCpuMemHelper(pGpu, pMemory, - RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_CLIENT(pKernelChannel), exceptType, localRmEngineType, notifierStatus); @@ -199,7 +199,7 @@ krcErrorWriteNotifier_CPU { status = _krcErrorWriteNotifierCpuMemHelper(pGpu, pMemory, - RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_CLIENT(pKernelChannel), exceptType, localRmEngineType, notifierStatus); @@ -335,7 +335,7 @@ NV_STATUS krcErrorSetNotifier_IMPL } if (flushFlags != 0) { - kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), flushFlags); + kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), flushFlags | BUS_FLUSH_USE_PCIE_READ); } Error: diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c index 5ee59b8a0d..2c437d362d 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -445,8 +445,8 @@ krcWatchdogInit_IMPL NvU32 pushBufBytes; NvU32 allocationSize; NvU32 ctrlSize; - NvU32 flags; NV_STATUS status; + RsClient *pClient; KernelChannel *pKernelChannel; NvBool bCacheSnoop; RM_API *pRmApi = rmGpuLockIsOwner() ? @@ -498,7 +498,8 @@ krcWatchdogInit_IMPL NV01_NULL_OBJECT /* hParent */, NV01_NULL_OBJECT /* hObject */, NV01_ROOT, - &hClient) != NV_OK) + &hClient, + sizeof(hClient)) != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to allocate a watchdog client\n"); return NV_ERR_GENERIC; @@ -525,7 +526,8 @@ krcWatchdogInit_IMPL hClient /* hParent */, WATCHDOG_DEVICE_ID /* hObject */, NV01_DEVICE_0, - pNv0080); + pNv0080, + sizeof(*pNv0080)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to allocate a watchdog device\n"); @@ -548,7 +550,8 @@ krcWatchdogInit_IMPL WATCHDOG_DEVICE_ID /* hParent */, (WATCHDOG_SUB_DEVICE_0_ID + subDeviceInstance) /* hObject */, NV20_SUBDEVICE_0, - pNv2080); + pNv2080, + sizeof(*pNv2080)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, @@ -627,7 +630,8 @@ krcWatchdogInit_IMPL WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_VIRTUAL_CTX_ID /* hObject */, NV01_MEMORY_VIRTUAL, - pVirtual); + pVirtual, + sizeof(*pVirtual)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, @@ -655,45 +659,108 @@ krcWatchdogInit_IMPL bCacheSnoop = FLD_TEST_REF(BIF_DMA_CAPS_SNOOP, _CTXDMA, kbifGetDmaCaps(pGpu, pKernelBif)); - // Allocate memory for the notifiers and pushbuffer. - flags = ((bCacheSnoop ? DRF_DEF(OS02, _FLAGS, _COHERENCY, _CACHED) : - DRF_DEF(OS02, _FLAGS, _COHERENCY, _UNCACHED)) | - DRF_DEF(OS02, _FLAGS, _LOCATION, _PCI) | - DRF_DEF(OS02, _FLAGS, _PHYSICALITY, _NONCONTIGUOUS)); - if ((pKernelRc->watchdog.flags & WATCHDOG_FLAGS_ALLOC_UNCACHED_PCI) != 0) - { - flags = FLD_SET_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, flags); - } - { NV_MEMORY_ALLOCATION_PARAMS *pMem = &pParams->mem; + NvU32 hClass = NV01_MEMORY_SYSTEM; portMemSet(pMem, 0, sizeof *pMem); pMem->owner = HEAP_OWNER_RM_CLIENT_GENERIC; pMem->size = allocationSize; pMem->type = NVOS32_TYPE_IMAGE; - // TODO - migrate to use newer OS32 flags inline JIRA CORERM-4212 - status = RmDeprecatedConvertOs02ToOs32Flags(flags, - &pMem->attr, - &pMem->attr2, - &pMem->flags); - if (status != NV_OK) + pMem->attr2 = DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _NO); + + // Apply registry overrides to channel pushbuffer. + switch (DRF_VAL(_REG_STR_RM, _INST_LOC_4, _CHANNEL_PUSHBUFFER, pGpu->instLocOverrides4)) { - NV_PRINTF(LEVEL_ERROR, "Invalid flags\n"); - goto error; + case NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_VID: + hClass = NV01_MEMORY_LOCAL_USER; + pMem->attr |= DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED); + break; + + case NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_COH: + hClass = NV01_MEMORY_SYSTEM; + pMem->attr |= DRF_DEF(OS32, _ATTR, _LOCATION, _PCI) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _CACHED) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS); + break; + + case NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_NCOH: + hClass = NV01_MEMORY_SYSTEM; + pMem->attr |= DRF_DEF(OS32, _ATTR, _LOCATION, _PCI) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS); + break; + + case NV_REG_STR_RM_INST_LOC_4_CHANNEL_PUSHBUFFER_DEFAULT: + default: + hClass = NV01_MEMORY_SYSTEM; + pMem->attr |= DRF_DEF(OS32, _ATTR, _LOCATION, _PCI) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS); + } + + if (bCacheSnoop && (hClass == NV01_MEMORY_SYSTEM)) + { + pMem->attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _CACHED, + pMem->attr); + } + + if (((pKernelRc->watchdog.flags & WATCHDOG_FLAGS_ALLOC_UNCACHED_PCI) != 0) && + (hClass == NV01_MEMORY_SYSTEM)) + { + pMem->attr = FLD_SET_DRF(OS32, _ATTR, _COHERENCY, _UNCACHED, + pMem->attr); + } + + // + // When Hopper CC is enabled all RM internal sysmem allocations that are + // required to be accessed from GPU should be in unprotected memory + // All video allocations must be in CPR + // + + // + // Allocate memory using vidHeapControl + // + // vidHeapControl calls should happen outside GPU locks. This is a PMA + // requirement as memory allocation calls may invoke eviction which UVM + // could get stuck behind GPU lock + // + if (hClass == NV01_MEMORY_LOCAL_USER && rmGpuLockIsOwner()) + { + bAcquireLock = NV_TRUE; + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); } + // Allocate memory for the notifiers and pushbuffer status = pRmApi->AllocWithHandle(pRmApi, hClient /* hClient */, WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_MEM_ID /* hObject */, - NV01_MEMORY_SYSTEM, - pMem); + hClass, + pMem, + sizeof(*pMem)); + + if (bAcquireLock) + { + // Re-acquire the GPU locks + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_RC) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to grab RM-Lock\n"); + DBG_BREAKPOINT(); + goto error; + } + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + bAcquireLock = NV_FALSE; + } + if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, - "Unable to allocate system memory for watchdog\n"); + "Unable to allocate %s memory for watchdog\n", + (hClass == NV01_MEMORY_LOCAL_USER) ? "video" : "system"); goto error; } @@ -708,7 +775,7 @@ krcWatchdogInit_IMPL if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, - "Unable to map system memory for watchdog\n"); + "Unable to map memory for watchdog\n"); goto error; } @@ -729,7 +796,7 @@ krcWatchdogInit_IMPL if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Unable to map system memory into watchdog's heap\n"); + "Unable to map memory into watchdog's heap\n"); goto error; } } @@ -758,7 +825,8 @@ krcWatchdogInit_IMPL WATCHDOG_DEVICE_ID /* hParent */ , WATCHDOG_ERROR_DMA_ID /* hObject */, NV01_CONTEXT_DMA, - pCtxDma); + pCtxDma, + sizeof(*pCtxDma)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, @@ -792,7 +860,8 @@ krcWatchdogInit_IMPL WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_NOTIFIER_DMA_ID /* hObject */, NV01_CONTEXT_DMA, - pCtxDma); + pCtxDma, + sizeof(*pCtxDma)); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to set up watchdog's notifier\n"); @@ -825,6 +894,14 @@ krcWatchdogInit_IMPL break; } + // + // When APM is enabled all RM internal allocations must to go to + // unprotected memory irrespective of vidmem or sysmem + // When Hopper CC is enabled all RM internal sysmem allocations that + // are required to be accessed from GPU should be in unprotected memory + // and all vidmem allocations must go to protected memory + // + // // Allocate memory using vidHeapControl // @@ -848,7 +925,8 @@ krcWatchdogInit_IMPL WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_USERD_PHYS_MEM_ID /* hObject */, userdMemClass, - pMem); + pMem, + sizeof(*pMem)); if (status != NV_OK) { @@ -894,7 +972,8 @@ krcWatchdogInit_IMPL WATCHDOG_DEVICE_ID /* hParent */, WATCHDOG_PUSHBUFFER_CHANNEL_ID /* hObject */, gpfifoObj, - pChannelGPFifo); + pChannelGPFifo, + sizeof(*pChannelGPFifo)); if (bAcquireLock) { @@ -970,18 +1049,27 @@ krcWatchdogInit_IMPL WATCHDOG_PUSHBUFFER_CHANNEL_ID /* hParent */, WATCHDOG_GROBJ_ID /* hObject */, grObj, - NULL); + NULL, + 0); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to allocate class %x\n", grObj); goto error; } + // Fetch the client object + status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to obtain client object\n"); + goto error; + } + // // Determine the (class + engine) handle the hardware will understand, if // necessary // - if (CliGetKernelChannelWithDevice(hClient, + if (CliGetKernelChannelWithDevice(pClient, WATCHDOG_DEVICE_ID, WATCHDOG_PUSHBUFFER_CHANNEL_ID, &pKernelChannel) != NV_OK) diff --git a/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c b/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c index 14e9391437..7d5d23458f 100644 --- a/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c +++ b/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -67,8 +67,21 @@ ksec2ResetHw_TU102 ) { GPU_FLD_WR_DRF_DEF(pGpu, _PSEC, _FALCON_ENGINE, _RESET, _TRUE); + + // Reg read cycles needed for signal propagation. + for (NvU32 i = 0; i < FLCN_RESET_PROPAGATION_DELAY_COUNT; i++) + { + GPU_REG_RD32(pGpu, NV_PSEC_FALCON_ENGINE); + } + GPU_FLD_WR_DRF_DEF(pGpu, _PSEC, _FALCON_ENGINE, _RESET, _FALSE); + // Reg read cycles needed for signal propagation. + for (NvU32 i = 0; i < FLCN_RESET_PROPAGATION_DELAY_COUNT; i++) + { + GPU_REG_RD32(pGpu, NV_PSEC_FALCON_ENGINE); + } + return NV_OK; } @@ -130,7 +143,7 @@ s_allocateGenericBlUcode goto out; } - NV_ASSERT_OK_OR_GOTO(status, + NV_ASSERT_OK_OR_GOTO(status, bindataWriteToBuffer(pBinImg, pGenericBlUcodeImg, imgSizeAligned), out); *ppDesc = pGenericBlUcodeDesc; diff --git a/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c b/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c index 519db89e20..e7269bd44a 100644 --- a/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c +++ b/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c @@ -55,7 +55,7 @@ ksec2Destruct_IMPL pKernelSec2->pGenericBlUcodeImg = NULL; } -void +void ksec2RegisterIntrService_IMPL ( OBJGPU *pGpu, @@ -79,7 +79,7 @@ ksec2RegisterIntrService_IMPL } -NV_STATUS +NV_STATUS ksec2ServiceNotificationInterrupt_IMPL ( OBJGPU *pGpu, diff --git a/src/nvidia/src/kernel/gpu/sec2/sec2_context.c b/src/nvidia/src/kernel/gpu/sec2/sec2_context.c new file mode 100644 index 0000000000..1c26159ea8 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/sec2/sec2_context.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/sec2/sec2_context.h" +#include "kernel/gpu/fifo/kernel_channel.h" +#include "gpu/falcon/kernel_falcon.h" + +NV_STATUS +sec2ctxConstructHal_KERNEL +( + Sec2Context *pSec2Context, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + ChannelDescendant *pChannelDescendant = staticCast(pSec2Context, ChannelDescendant); + OBJGPU *pGpu = GPU_RES_GET_GPU(pChannelDescendant); + KernelFalcon *pKernelFalcon = kflcnGetKernelFalconForEngine(pGpu, ENG_SEC2); + KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; + + return kflcnAllocContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant)); +} + +void +sec2ctxDestructHal_KERNEL +( + Sec2Context *pSec2Context +) +{ + ChannelDescendant *pChannelDescendant = staticCast(pSec2Context, ChannelDescendant); + OBJGPU *pGpu = GPU_RES_GET_GPU(pChannelDescendant); + KernelFalcon *pKernelFalcon = kflcnGetKernelFalconForEngine(pGpu, ENG_SEC2); + KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; + + NV_ASSERT_OK(kflcnFreeContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant))); +} diff --git a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c new file mode 100644 index 0000000000..83a9191c7d --- /dev/null +++ b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c @@ -0,0 +1,1803 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Provides the implementation for all GH100 specific SPDM HALs + * interfaces. + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "nvRmReg.h" +#include "gpu/spdm/spdm.h" +#include "spdm/rmspdmtransport.h" +#include "spdm/rmspdmvendordef.h" +#include "objtmr.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/spdm/libspdm_includes.h" +#include "rmapi/client_resource.h" +#include "ctrl/ctrl2080/ctrl2080spdm.h" +#include "flcnretval.h" +#include "gpu/conf_compute/conf_compute.h" + +/* ------------------------ Macros ----------------------------------------- */ +#define SPDM_MESSAGE_BUFFER_ADDRESS_ALIGNMENT (256) + +#define SPDM_CAPABILITIES_FLAGS_GH100 \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MAC_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP + +#define DER_LONG_FORM_LENGTH_FIELD_BIT (0x80) +#define DER_CERT_SIZE_FIELD_LENGTH (0x1) + +#define SPDM_PEM_BEGIN_CERTIFICATE "-----BEGIN CERTIFICATE-----\n" +#define SPDM_PEM_END_CERTIFICATE "-----END CERTIFICATE-----\n" + +#define SPDM_L1_CERTIFICATE_PEM "-----BEGIN CERTIFICATE-----\n"\ + "MIICCzCCAZCgAwIBAgIQLTZwscoQBBHB/sDoKgZbVDAKBggqhkjOPQQDAzA1MSIw\n"\ + "IAYDVQQDDBlOVklESUEgRGV2aWNlIElkZW50aXR5IENBMQ8wDQYDVQQKDAZOVklE\n"\ + "SUEwIBcNMjExMTA1MDAwMDAwWhgPOTk5OTEyMzEyMzU5NTlaMDUxIjAgBgNVBAMM\n"\ + "GU5WSURJQSBEZXZpY2UgSWRlbnRpdHkgQ0ExDzANBgNVBAoMBk5WSURJQTB2MBAG\n"\ + "ByqGSM49AgEGBSuBBAAiA2IABA5MFKM7+KViZljbQSlgfky/RRnEQScW9NDZF8SX\n"\ + "gAW96r6u/Ve8ZggtcYpPi2BS4VFu6KfEIrhN6FcHG7WP05W+oM+hxj7nyA1r1jkB\n"\ + "2Ry70YfThX3Ba1zOryOP+MJ9vaNjMGEwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8B\n"\ + "Af8EBAMCAQYwHQYDVR0OBBYEFFeF/4PyY8xlfWi3Olv0jUrL+0lfMB8GA1UdIwQY\n"\ + "MBaAFFeF/4PyY8xlfWi3Olv0jUrL+0lfMAoGCCqGSM49BAMDA2kAMGYCMQCPeFM3\n"\ + "TASsKQVaT+8S0sO9u97PVGCpE9d/I42IT7k3UUOLSR/qvJynVOD1vQKVXf0CMQC+\n"\ + "EY55WYoDBvs2wPAH1Gw4LbcwUN8QCff8bFmV4ZxjCRr4WXTLFHBKjbfneGSBWwA=\n"\ + "-----END CERTIFICATE-----\n" + +#define SPDM_L2_CERTIFICATE_PEM "-----BEGIN CERTIFICATE-----\n"\ + "MIICijCCAhCgAwIBAgIQTCVe3jvQAb8/SjtgX8qJijAKBggqhkjOPQQDAzA1MSIw\n"\ + "IAYDVQQDDBlOVklESUEgRGV2aWNlIElkZW50aXR5IENBMQ8wDQYDVQQKDAZOVklE\n"\ + "SUEwIBcNMjIwMTEyMDAwMDAwWhgPOTk5OTEyMzEyMzU5NTlaMD0xHjAcBgNVBAMM\n"\ + "FU5WSURJQSBHSDEwMCBJZGVudGl0eTEbMBkGA1UECgwSTlZJRElBIENvcnBvcmF0\n"\ + "aW9uMHYwEAYHKoZIzj0CAQYFK4EEACIDYgAE+pg+tDUuILlZILk5wg22YEJ9Oh6c\n"\ + "yPcsv3IvgRWcV4LeZK1pTCoQDIplZ0E4qsLG3G04pxsbMhxbqkiz9pqlTV2rtuVg\n"\ + "SmIqnSYkU1jWXsPS9oVLCGE8VRLl1JvqyOxUo4HaMIHXMA8GA1UdEwEB/wQFMAMB\n"\ + "Af8wDgYDVR0PAQH/BAQDAgEGMDsGA1UdHwQ0MDIwMKAuoCyGKmh0dHA6Ly9jcmwu\n"\ + "bmRpcy5udmlkaWEuY29tL2NybC9sMS1yb290LmNybDA3BggrBgEFBQcBAQQrMCkw\n"\ + "JwYIKwYBBQUHMAGGG2h0dHA6Ly9vY3NwLm5kaXMubnZpZGlhLmNvbTAdBgNVHQ4E\n"\ + "FgQUB0Kg6wOcgGB7oUFhmU2uJffCmx4wHwYDVR0jBBgwFoAUV4X/g/JjzGV9aLc6\n"\ + "W/SNSsv7SV8wCgYIKoZIzj0EAwMDaAAwZQIxAPIQhnveFxYIrPzBqViT2I34SfS4\n"\ + "JGWFnk/1UcdmgJmp+7l6rH/C4qxwntYSgeYrlQIwdjQuofHnhd1RL09OBO34566J\n"\ + "C9bYAosT/86cCojiGjhLnal9hJOH0nS/lrbaoc5a\n"\ + "-----END CERTIFICATE-----\n" + +#define SPDM_L3_CERTIFICATE_PEM "-----BEGIN CERTIFICATE-----\n"\ + "MIICqjCCAi+gAwIBAgIQav5xhPkiMsjfeyQiYXduVjAKBggqhkjOPQQDAzA9MR4w\n"\ + "HAYDVQQDDBVOVklESUEgR0gxMDAgSWRlbnRpdHkxGzAZBgNVBAoMEk5WSURJQSBD\n"\ + "b3Jwb3JhdGlvbjAgFw0yMjAzMDEwMDAwMDBaGA85OTk5MTIzMTIzNTk1OVowUzEn\n"\ + "MCUGA1UEAwweTlZJRElBIEdIMTAwIFByb3Zpc2lvbmVyIElDQSAxMRswGQYDVQQK\n"\ + "DBJOVklESUEgQ29ycG9yYXRpb24xCzAJBgNVBAYTAlVTMHYwEAYHKoZIzj0CAQYF\n"\ + "K4EEACIDYgAEzUdWqjn1OlXhLfFOKAFTghqG+Q3zF4xgSBbZsUEyWYCC3rKjE9Nn\n"\ + "o88ZpBQx85Oo0PkqP2dwoMVNTQMv5cvy9jLaTvSTXZwN2HQHE9u7x7BIYrWi0sG3\n"\ + "5q1IJNSOGO5Lo4HbMIHYMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgEG\n"\ + "MDwGA1UdHwQ1MDMwMaAvoC2GK2h0dHA6Ly9jcmwubmRpcy5udmlkaWEuY29tL2Ny\n"\ + "bC9sMi1naDEwMC5jcmwwNwYIKwYBBQUHAQEEKzApMCcGCCsGAQUFBzABhhtodHRw\n"\ + "Oi8vb2NzcC5uZGlzLm52aWRpYS5jb20wHQYDVR0OBBYEFCloyxYs0HeVcqJ5EAPm\n"\ + "nroMzAqUMB8GA1UdIwQYMBaAFAdCoOsDnIBge6FBYZlNriX3wpseMAoGCCqGSM49\n"\ + "BAMDA2kAMGYCMQDK0BCr49DNJ48Yh5wu388bZifDFxAsiUS4U1fGmpJZFhCbODH6\n"\ + "mRwcMxp6EOayZuYCMQDYKTyNc2FxWFuhHtdCE3ls4S7SInehdErTZNuhFymc4YOM\n"\ + "6VlLWTY/CM+resjjqxQ=\n"\ + "-----END CERTIFICATE-----\n" + +/* ------------------------ Types Definitions ------------------------------ */ +/*! + * Define context structure which tracks all state required for IO between + * RM and GSP. They communicate via a shared memory surface in which SPDM + * payloads are stored, and use the RM<->GSP command queue to alert of payloads. + */ +typedef struct _SPDM_GSP_IO_CONTEXT +{ + /*! + * Buffer to store SPDM response read from memory surface. Required since + * libspdm splits send and receive message across two message calls. + */ + NV_DECLARE_ALIGNED(NvU8 *pResponse, 8); + + /*! The memory descriptor that describes the memory surface */ + NV_DECLARE_ALIGNED(MEMORY_DESCRIPTOR *pMemDesc, 8); + + /*! + * The size of the surface. This information is also contained in + * the surfaces's memory descriptor but is still required since + * surface structures will be allocated and populated before the + * underlying surfaces are allocated themselves (time at which the + * memory descriptors will allocated and populated). + */ + NvU32 surfaceSizeInByte; + + /*! + * Represents the amount by which the actual size of the surface will + * aligned when the surface is allocated. + */ + NvU32 alignSize; + + /*! + * Stores the address that the GSP will use when accessing the surface. + */ + NvU64 dmaAddr; + + /*! + * Address space for memory surface (sysmem or FB). + */ + NvU32 addrSpace; + + /*! + * Sequence number for the memory surface. + */ + NvU32 seqNum; + + /*! + * Region ID for the payload (i.e. unprotected, protected). + */ + NvU32 regionId; + + /*! + * Size allocated for the SPDM message decription header, which + * describes the payload contained in the surface. + */ + NvU32 descHdrSizeInByte; + + /*! + * Size of the surface available to RM for storing SPDM messages. + */ + NvU32 rmBufferSizeInByte; + + /*! + * Size of the above response buffer. + */ + NvU32 responseSize; + +} SPDM_GSP_IO_CONTEXT; + +/* ------------------------ Static Variables ------------------------------- */ +// +// For transport functionality, we require access to the GPU and Spdm objects. +// However, libspdm transport layer currently does not support passing any custom +// parameters, meaning we must use static variables to access these objects. +// If we ever require multiple instances of the Spdm object, this will be an issue. +// +static OBJGPU *g_pGpu = NULL; +static Spdm *g_pSpdm = NULL; + +static SPDM_ALGO_CHECK_ENTRY g_SpdmAlgoCheckTable_GH100[] = +{ + { LIBSPDM_DATA_MEASUREMENT_SPEC, SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF }, + { LIBSPDM_DATA_MEASUREMENT_HASH_ALGO, SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 }, + { LIBSPDM_DATA_BASE_ASYM_ALGO, SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 }, + { LIBSPDM_DATA_BASE_HASH_ALGO, SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 }, + { LIBSPDM_DATA_DHE_NAME_GROUP, SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1 }, + { LIBSPDM_DATA_AEAD_CIPHER_SUITE, SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM }, + { LIBSPDM_DATA_KEY_SCHEDULE, SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH }, + { LIBSPDM_DATA_OTHER_PARAMS_SUPPORT, 0 }, + { LIBSPDM_DATA_REQ_BASE_ASYM_ALG, 0 } +}; + +/* ------------------------ Static Function Prototypes --------------------- */ +static void _spdmReleaseSurfaceGsp(Spdm *pSpdm); + +static NV_STATUS _spdmErrorCheck(RM_GSP_SPDM_MSG *pSpdmMsg, + NvU32 guestIdChk, + NvU32 endpointIdChk, + NvU32 cmdType); + +// +// Static transport layer functions which we pass to libspdm as function pointers. +// The libspdm library will then use these functions to send and receive SPDM messages. +// Function parameters and types must match those expected by libspdm. +// +static uint32_t _spdmGetTransportHeaderSizeGsp(void *spdm_context); + +static libspdm_return_t _spdmEncodeMessageGsp(void *spdm_context, const uint32_t *session_id, + bool is_app_message, bool is_requester, + size_t message_size, void *message, + size_t *transport_message_size, + void **transport_message); + +static libspdm_return_t _spdmDecodeMessageGsp(void *spdm_context, uint32_t **session_id, + bool *is_app_message, bool is_requester, + size_t transport_message_size, void *transport_message, + size_t *message_size, void **message); + +static libspdm_return_t _spdmSendMessageGsp(void *spdm_context, size_t message_size, + const void *message, uint64_t timeout); + +static libspdm_return_t _spdmReceiveMessageGsp(void *spdm_context, size_t *message_size, + void **message, uint64_t timeout); + +static NV_STATUS _spdmSendInitRmDataCommand(OBJGPU *pGpu, Spdm *pSpdm); + +/* ------------------------ Static Functions ------------------------------- */ +/*! + * Frees all memory and state associated with the GSP SPDM-message surface. + */ +void +_spdmReleaseSurfaceGsp +( + Spdm *pSpdm +) +{ + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + + if (pSpdm == NULL || pSpdm->pDeviceIOContext == NULL) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Attempting to release NULL MemDesc, this is BUG!\n"); + DBG_BREAKPOINT(); + return; + } + + pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; + memdescFree(pIOContext->pMemDesc); + memdescDestroy(pIOContext->pMemDesc); + portMemFree(pIOContext->pResponse); + portMemSet(pIOContext, 0, sizeof(SPDM_GSP_IO_CONTEXT)); + portMemFree(pIOContext); + + // Ensure we clear object context pointer. + pSpdm->pDeviceIOContext = NULL; +} + +/*! + * Performs validation of received RPC SPDM message and + * by comparing the message against expected values. Used + * to detect mismatch between attributes of request sent + * and attributes of response received. + * + * @param[in] pSpdmMsg Pointer to SPDM Message structure. + * @param[in] guestIdChk Expected guest ID. + * @param[in] endpointIdChk Expected endpoint ID. + * @param[in] cmdType SPDM command type. + */ +NV_STATUS +_spdmErrorCheck +( + RM_GSP_SPDM_MSG *pSpdmMsg, + NvU32 guestIdChk, + NvU32 endpointIdChk, + NvU32 cmdType +) +{ + // Perform validation of received RPC SPDM message. + if (pSpdmMsg->status != FLCN_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: RPC message error : status = 0x%x.\n", + pSpdmMsg->status); + + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + // Perform validation of received SPDM message description header only if SPDM RPC message status is FLCN_OK. + if (pSpdmMsg->version != NV_SPDM_DESC_HEADER_VERSION_CURRENT) + { + NV_PRINTF(LEVEL_ERROR, + "SPDM: Version mismatch: [Check] version = 0x%x, [SpdmRet] version = 0x%x\n", + NV_SPDM_DESC_HEADER_VERSION_CURRENT, pSpdmMsg->version); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + if (pSpdmMsg->guestId != guestIdChk) + { + NV_PRINTF(LEVEL_ERROR, + "SPDM: Guest ID mismatch: [Check] guestId = 0x%x, [SpdmRet] guestId = 0x%x\n", + guestIdChk, pSpdmMsg->guestId); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + if (cmdType != RM_GSP_SPDM_CMD_ID_CC_INIT) + { + if (pSpdmMsg->endpointId != endpointIdChk) + { + NV_PRINTF(LEVEL_ERROR, + "SPDM: Endpoint ID mismatch: [Check] endpointId = 0x%x, [SpdmRet] endpointId = 0x%x\n", + endpointIdChk, pSpdmMsg->endpointId); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + } + + return NV_OK; +} + +/*! + * Callback to fill out sequence number in expected format. + * The sequence number is for secured message format only and defined in DMTF DSP0277. + * Currently, requester(RM) and responder(GSP-SPDM) doesn't support sequence number. + */ +uint8_t +_spdmGetSequenceNumberGsp +( + uint64_t sequence_number, + uint8_t *sequence_number_buffer +) +{ + // No sequence number included as a part of GSP secured message. + return 0; +} + +/*! + * Callback to fill RNG blob in secured message. + * The random number size is for secured message format only and defined in DMTF DSP0277. + * Currently, requester(RM) and responder(GSP-SPDM) doesn't support random number. + */ +uint32_t +_spdmGetMaxRandomNumberCountGsp +( + void +) +{ + // No RNG in GSP secured message. + return 0; +} + +/*! + * Callback to get allocated space for transport header that is pre-pended + * to the SPDM message. Return the size of the NV_SPDM_MESSAGE_HEADER we prepend. + */ +uint32_t +_spdmGetTransportHeaderSizeGsp +( + void *spdm_context +) +{ + return sizeof(NV_SPDM_DESC_HEADER); +} + +/*! + * Static function libspdm uses as hook to RM<->GSP transport layer. + * If secured, encodes message into SPDM Secured Message format. + */ +libspdm_return_t +_spdmEncodeMessageGsp +( + void *spdm_context, + const uint32_t *session_id, + bool is_app_message, + bool is_requester, + size_t message_size, + void *message, + size_t *transport_message_size, + void **transport_message +) +{ + libspdm_secured_message_callbacks_t securedMessageInfo; + libspdm_return_t status = LIBSPDM_STATUS_SUCCESS; + size_t securedMessageSize = 0; + void *pSecuredMessageContext = NULL; + NV_SPDM_DESC_HEADER *pNvSpdmDescHdr = NULL; + NvU32 payloadSize = 0; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + + pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; + + // Check libspdm parameters. + if (spdm_context == NULL || message == NULL || message_size == 0 || + transport_message == NULL || *transport_message == NULL || + transport_message_size == NULL || pIOContext == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + // Only support sending requester SPDM/Secured messages. + if (!is_requester || is_app_message) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + // The transport buffer must be large enough to fit the transport header and the message. + if (*transport_message_size < (sizeof(NV_SPDM_DESC_HEADER) + message_size)) + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + // Initialize descriptor header. + pNvSpdmDescHdr = (NV_SPDM_DESC_HEADER *)*transport_message; + portMemSet(pNvSpdmDescHdr, 0, sizeof(NV_SPDM_DESC_HEADER)); + + // Determine whether message is secured. + if (session_id != NULL) + { + pNvSpdmDescHdr->msgType = NV_SPDM_MESSAGE_TYPE_SECURED; + + pSecuredMessageContext = + libspdm_get_secured_message_context_via_session_id(spdm_context, *session_id); + + if (pSecuredMessageContext == NULL) + { + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } + + // Calculate max space we have for secured message in transport buffer. + securedMessageSize = *transport_message_size; + securedMessageSize -= sizeof(NV_SPDM_DESC_HEADER); + + // Initialize secured message attributes. + portMemSet(&securedMessageInfo, 0, sizeof(securedMessageInfo)); + securedMessageInfo.version = SPDM_SECURED_MESSAGE_CALLBACKS_VERSION; + securedMessageInfo.get_sequence_number = _spdmGetSequenceNumberGsp; + securedMessageInfo.get_max_random_number_count = _spdmGetMaxRandomNumberCountGsp; + + // Encode secured message into output buffer. + status = libspdm_encode_secured_message(pSecuredMessageContext, *session_id, is_requester, + message_size, message, &securedMessageSize, + (pNvSpdmDescHdr + 1), &securedMessageInfo); + if (status != LIBSPDM_STATUS_SUCCESS) + { + return status; + } + + // Transport message buffer must be large enough to store secured message + NV_SPDM_DESC_HEADER. + NV_ASSERT_OR_RETURN(*transport_message_size > (securedMessageSize + sizeof(NV_SPDM_DESC_HEADER)), + LIBSPDM_STATUS_INVALID_MSG_FIELD); + + pNvSpdmDescHdr->msgSizeByte = (NvU32)securedMessageSize; + *transport_message_size = securedMessageSize + sizeof(NV_SPDM_DESC_HEADER); + } + else + { + // The normal message is not encrypted, it will be sent as NV_SPDM_DESC_HEADER + Message. + payloadSize = sizeof(NV_SPDM_DESC_HEADER) + message_size; + + // + // Check for large enough buffer for payload, as well as for overflow in + // operation above. If no overflow, we know message_size fits in NvU32. + // + if (*transport_message_size < payloadSize || payloadSize < message_size) + { + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + + // + // Fill in SPDM message header. + // The SPDM message is already after the SPDM msg header. + // + pNvSpdmDescHdr->msgType = NV_SPDM_MESSAGE_TYPE_NORMAL; + pNvSpdmDescHdr->msgSizeByte = (NvU32)message_size; + *transport_message_size = payloadSize; + } + + // Record the message in the last exchange transcript. + if (message_size > SPDM_MAX_EXCHANGE_BUFFER_SIZE) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + portMemCopy(g_pSpdm->pLastExchange, SPDM_MAX_EXCHANGE_BUFFER_SIZE, + message, message_size); + g_pSpdm->lastExchangeSize = message_size; + + return LIBSPDM_STATUS_SUCCESS; +} + +/*! + * Static function libspdm uses as hook to RM<->GSP transport layer. + * If secured, decodes the message from the SPDM Secured Message format. + */ +libspdm_return_t +_spdmDecodeMessageGsp +( + void *spdm_context, + uint32_t **session_id, + bool *is_app_message, + bool is_requester, + size_t transport_message_size, + void *transport_message, + size_t *message_size, + void **message +) +{ + libspdm_secured_message_callbacks_t securedMessageInfo; + NV_SPDM_DESC_HEADER *pNvSpdmDescHdr = NULL; + NvU32 payloadSize = 0; + void *pSecuredMessageContext = NULL; + libspdm_return_t status = LIBSPDM_STATUS_SUCCESS; + NvU32 lastExchangeSizeLeft = 0; + spdm_secured_message_a_data_header1_t *pSpdmSecuredMsgHdr = NULL; + + // Check libspdm parameters. + if (spdm_context == NULL || session_id == NULL || is_app_message == NULL || + transport_message_size == 0 || transport_message == NULL || + message_size == NULL || message == NULL || *message == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + // Only support receiving Responder SPDM/Secured messages. + if (is_requester) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + // Retrieve NV-header from message, and perform basic validation. + pNvSpdmDescHdr = (NV_SPDM_DESC_HEADER *)transport_message; + if (transport_message_size < sizeof(NV_SPDM_DESC_HEADER)) + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + payloadSize = NV_SPDM_DESC_HEADER_SIZE_IN_BYTE + pNvSpdmDescHdr->msgSizeByte; + + if (transport_message_size != payloadSize) + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + // Decode message, based on type. + switch (pNvSpdmDescHdr->msgType) + { + case NV_SPDM_MESSAGE_TYPE_SECURED: + { + // + // Double-check the payload fits a secured message header. + // Our implementation of a secure message header only includes + // session ID - no sequence number. + // + if (pNvSpdmDescHdr->msgSizeByte < sizeof(spdm_secured_message_a_data_header1_t)) + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + // Secured message header begins immediately after general NV header. + pSpdmSecuredMsgHdr = (spdm_secured_message_a_data_header1_t *)(pNvSpdmDescHdr + 1); + *session_id = &pSpdmSecuredMsgHdr->session_id; + + pSecuredMessageContext = + libspdm_get_secured_message_context_via_session_id(spdm_context, **session_id); + + if (pSecuredMessageContext == NULL) + { + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } + + // Initialize secured message attributes. + portMemSet(&securedMessageInfo, 0, sizeof(securedMessageInfo)); + securedMessageInfo.version = SPDM_SECURED_MESSAGE_CALLBACKS_VERSION; + securedMessageInfo.get_sequence_number = _spdmGetSequenceNumberGsp; + securedMessageInfo.get_max_random_number_count = _spdmGetMaxRandomNumberCountGsp; + + // Decode and retrieve application payload from secured message. + // We must copy the message to the scratch buffer. + status = libspdm_decode_secured_message(pSecuredMessageContext, + **session_id, is_requester, + transport_message_size - NV_SPDM_DESC_HEADER_SIZE_IN_BYTE, + (pNvSpdmDescHdr + 1), message_size, + message, &securedMessageInfo); + if (status != LIBSPDM_STATUS_SUCCESS) + { + return status; + } + } + break; + + case NV_SPDM_MESSAGE_TYPE_NORMAL: + { + // Indicate the message is unsecured. + *session_id = NULL; + + // + // We both check that the buffer is large enough, and that the + // size_t type is large enough to hold the size of the message. + // + if (*message_size < pNvSpdmDescHdr->msgSizeByte) + { + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + + // The message is already present in the receiver buffer. + // Just use that. + *message = (uint8_t *)(pNvSpdmDescHdr + 1); + *message_size = pNvSpdmDescHdr->msgSizeByte; + } + break; + + default: + { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + } + + // We don't expect app message for any scenario. + *is_app_message = NV_FALSE; + + // Record the message in the last exchange transcript. + lastExchangeSizeLeft = SPDM_MAX_EXCHANGE_BUFFER_SIZE - g_pSpdm->lastExchangeSize; + if (*message_size > lastExchangeSizeLeft || SPDM_MAX_EXCHANGE_BUFFER_SIZE < g_pSpdm->lastExchangeSize) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + portMemCopy((NvU8 *)g_pSpdm->pLastExchange + g_pSpdm->lastExchangeSize, + lastExchangeSizeLeft, *message, *message_size); + g_pSpdm->lastExchangeSize += *message_size; + + return LIBSPDM_STATUS_SUCCESS; +} + +/*! + * Static function libspdm uses as hook to RM<->GSP transport layer. + * Sends SPDM request message to GSP, and stores received response to buffer. + * Response buffer must be freed by corresponding _spdmReceiveMessageGsp(). + */ +libspdm_return_t +_spdmSendMessageGsp +( + void *spdm_context, + size_t message_size, + const void *message, + uint64_t timeout +) +{ + NvU8 *pRequest = NULL; + NvU32 requestSize = 0; + NV_STATUS nvStatus = NV_OK; + libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + + // Check libspdm parameters. + if (message_size == 0 || message == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + if (g_pGpu == NULL || g_pSpdm == NULL || g_pSpdm->pDeviceIOContext == NULL) + { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; + + // Initialize space for SPDM request and response buffers. + requestSize = message_size; + pRequest = (NvU8 *)portMemAllocNonPaged(requestSize); + pIOContext->responseSize = LIBSPDM_MAX_MESSAGE_BUFFER_SIZE; + pIOContext->pResponse = (NvU8 *)portMemAllocNonPaged(pIOContext->responseSize); + + if (pRequest == NULL || pIOContext->pResponse == NULL) + { + spdmStatus = LIBSPDM_STATUS_BUFFER_FULL; + goto ErrorExit; + } + + portMemSet(pRequest, 0, requestSize); + portMemSet(pIOContext->pResponse, 0, pIOContext->responseSize); + portMemCopy(pRequest, requestSize, message, message_size); + + nvStatus = spdmMessageProcess_HAL(g_pGpu, g_pSpdm, + CC_CTRL_CODE_SPDM_MESSAGE_PROCESS, + pRequest, requestSize, + pIOContext->pResponse, + &pIOContext->responseSize); + +ErrorExit: + + portMemFree(pRequest); + if (spdmStatus != LIBSPDM_STATUS_SUCCESS || nvStatus != NV_OK) + { + portMemFree(pIOContext->pResponse); + pIOContext->pResponse = NULL; + pIOContext->responseSize = 0; + spdmStatus = LIBSPDM_STATUS_SEND_FAIL; + } + + return spdmStatus; +} + +/*! + * Static function libspdm uses as hook to RM<->GSP transport layer. + * Copies stored response message back to libspdm buffer. Cannot be retried, + * as must free response message regardless of success or failure. + */ +libspdm_return_t +_spdmReceiveMessageGsp +( + void *spdm_context, + size_t *message_size, + void **message, + uint64_t timeout +) +{ + libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + + // Check libspdm parameters. + if (message_size == NULL || message == NULL || *message == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + if (g_pGpu == NULL || g_pSpdm == NULL || g_pSpdm->pDeviceIOContext == NULL) + { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + // Basic validation to ensure we have a real response. + pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; + if (pIOContext->pResponse == NULL || pIOContext->responseSize == 0) + { + spdmStatus = LIBSPDM_STATUS_RECEIVE_FAIL; + goto ErrorExit; + } + + if (pIOContext->responseSize > *message_size) + { + spdmStatus = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + goto ErrorExit; + } + + portMemCopy(*message, *message_size, pIOContext->pResponse, pIOContext->responseSize); + *message_size = pIOContext->responseSize; + +ErrorExit: + + // Invalidate response message, regardless of success or failure. + portMemFree(pIOContext->pResponse); + pIOContext->pResponse = NULL; + pIOContext->responseSize = 0; + + return spdmStatus; +} + +/*! +* Static function that sends the opaque data from RM to GSP. +*/ +NV_STATUS +_spdmSendInitRmDataCommand +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + portMemSet(¶ms, 0, sizeof(params)); + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + if (status != NV_OK) + { + return NV_ERR_FLCN_ERROR; + } + + // Perform basic validation of header returned, ensuring it matches expected values. + status = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: _spdmErrorCheck() failed in INIT_RM_DATA command \n"); + DBG_BREAKPOINT(); + return status; + } + + return NV_OK; +} + +/*! +* Static function that calculates the length of the X509 certificate in DER/TLV +* format. It assumes that the certificate is valid. +*/ +static NV_STATUS +_calcX509CertSize +( + NvU8 *pCert, + NvU8 *bufferEnd, + NvU32 *pCertLength +) +{ + // The cert is in TLV format. + NvU32 certSize = pCert[1]; + + // Check if the length is in DER longform. + // MSB in the length field is set for long form notation. + // fields. + if (certSize & DER_LONG_FORM_LENGTH_FIELD_BIT) + { + // + // The remaining bits in the length field indicate the + // number of following bytes used to represent the length. + // in base 256, most significant digit first. + // + NvU32 numLenBytes = certSize & 0x3f; + NvU8 *pStart = &pCert[2]; + NvU8 *pEnd = pStart + numLenBytes; + // Checking for buffer overflow. + if (pEnd > bufferEnd) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + certSize = *pStart; + while (++pStart < pEnd) + { + certSize = (certSize << 8) + *pStart ; + } + // Total cert length includes the Tag + length + // Adding it here. + certSize += 2 + numLenBytes; + } + + *pCertLength = certSize; + return NV_OK; +} + +static NV_STATUS +pem_write_buffer +( + NvU8 const *der, + NvU64 derLen, + NvU8 *buffer, + NvU64 bufferLen, + NvU64 *bufferUsed +) +{ + static const NvU8 base64[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/"; + NvU64 i, tmp, size; + NvU64 printed = 0; + NvU8 *ptr = buffer; + + // Base64 encoded size + size = (derLen + 2) / 3 * 4; + + // Add 1 byte per 64 for newline + size = size + (size + 63) / 64; + + // Add header excluding the terminating null and footer including the null + size += sizeof(SPDM_PEM_BEGIN_CERTIFICATE) - 1 + + sizeof(SPDM_PEM_END_CERTIFICATE); + + if (bufferLen < size) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + portMemCopy(ptr, bufferLen - (ptr - buffer), SPDM_PEM_BEGIN_CERTIFICATE, + sizeof(SPDM_PEM_BEGIN_CERTIFICATE) - 1); + ptr += sizeof(SPDM_PEM_BEGIN_CERTIFICATE) - 1; + + for (i = 0; (i + 2) < derLen; i += 3) + { + tmp = (der[i] << 16) | (der[i + 1] << 8) | (der[i + 2]); + *ptr++ = base64[(tmp >> 18) & 63]; + *ptr++ = base64[(tmp >> 12) & 63]; + *ptr++ = base64[(tmp >> 6) & 63]; + *ptr++ = base64[(tmp >> 0) & 63]; + + printed += 4; + if (printed == 64) + { + *ptr++ = '\n'; + printed = 0; + } + } + + if ((i == derLen) && (printed != 0)) + { + *ptr++ = '\n'; + } + + // 1 byte extra + if (i == (derLen - 1)) + { + tmp = der[i] << 4; + *ptr++ = base64[(tmp >> 6) & 63]; + *ptr++ = base64[(tmp >> 0) & 63]; + *ptr++ = '='; + *ptr++ = '='; + *ptr++ = '\n'; + } + + // 2 byte extra + if (i == (derLen - 2)) + { + tmp = ((der[i] << 8) | (der[i + 1])) << 2; + *ptr++ = base64[(tmp >> 12) & 63]; + *ptr++ = base64[(tmp >> 6) & 63]; + *ptr++ = base64[(tmp >> 0) & 63]; + *ptr++ = '='; + *ptr++ = '\n'; + } + + portMemCopy(ptr, bufferLen - (ptr - buffer), SPDM_PEM_END_CERTIFICATE, + sizeof(SPDM_PEM_END_CERTIFICATE)); + ptr += sizeof(SPDM_PEM_END_CERTIFICATE); + + *bufferUsed = size; + return NV_OK; +} + +/*! +* Static function that first converts the IK and AK certificates from DER to +* PEM format. Then it builds the cert chain in PEM format. It is assumed that +* the all the certificates are valid. Also it is assumend that there is a valid +* spdm session already established. +*/ +static NV_STATUS +_spdmBuildCertChain +( + NvU8 *pFirstCert, + NvU32 firstCertSize, + NvU8 *pSecondCert, + NvU32 secondCertSize, + NvU8 *pOutBuffer, + NvU32 *outBufferSize +) +{ + NvU64 firstCertOutputSize = 0; + NvU64 secondCertOutputSize = 0; + NvU64 remainingOutBufferSize = *outBufferSize; + void *pPortMemCopyStatus = NULL; + NV_STATUS status; + + if (pFirstCert == NULL || pSecondCert == NULL || pOutBuffer == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // Write the AK certificate to the output buffer + // + status = pem_write_buffer(pFirstCert, firstCertSize, pOutBuffer, + remainingOutBufferSize, &firstCertOutputSize); + if (status != NV_OK) + { + return status; + } + + // + // Keep track how much space we have left in the output buffer + // and where the next certificate should start. + // Clear the last byte (NULL). + // + remainingOutBufferSize -= firstCertOutputSize - 1; + pOutBuffer += firstCertOutputSize - 1; + + // + // Write the IK certificate to the output buffer + // + status = pem_write_buffer(pSecondCert, secondCertSize, pOutBuffer, + remainingOutBufferSize, &secondCertOutputSize); + if (status != NV_OK) + { + return status; + } + + remainingOutBufferSize -= secondCertOutputSize - 1; + pOutBuffer += secondCertOutputSize - 1; + + // Checking if the available size of buffer is enough to keep the whole + // certificate chain otherwise raise error. + if (remainingOutBufferSize < sizeof(SPDM_L1_CERTIFICATE_PEM) + + sizeof(SPDM_L2_CERTIFICATE_PEM) + + sizeof(SPDM_L3_CERTIFICATE_PEM)) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + // + // Write the L3 certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L3_CERTIFICATE_PEM, + sizeof(SPDM_L3_CERTIFICATE_PEM) - 1); + if (!pPortMemCopyStatus) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + remainingOutBufferSize -= sizeof(SPDM_L3_CERTIFICATE_PEM) - 1; + pOutBuffer += sizeof(SPDM_L3_CERTIFICATE_PEM) - 1; + + // + // Write the L2 certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L2_CERTIFICATE_PEM, + sizeof(SPDM_L2_CERTIFICATE_PEM) - 1); + if (!pPortMemCopyStatus) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + remainingOutBufferSize -= sizeof(SPDM_L2_CERTIFICATE_PEM) - 1; + pOutBuffer += sizeof(SPDM_L2_CERTIFICATE_PEM) - 1; + + // + // Write the L1 certificate to the output buffer + // + pPortMemCopyStatus = portMemCopy(pOutBuffer, + remainingOutBufferSize, + SPDM_L1_CERTIFICATE_PEM, + sizeof(SPDM_L1_CERTIFICATE_PEM) - 1); + if (!pPortMemCopyStatus) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + // + // Output the total certificate chain size + // Do not count the NULL bytes. + // + *outBufferSize = firstCertOutputSize - 1 + + secondCertOutputSize - 1 + + sizeof(SPDM_L3_CERTIFICATE_PEM) - 1 + + sizeof(SPDM_L2_CERTIFICATE_PEM) - 1 + + sizeof(SPDM_L1_CERTIFICATE_PEM) - 1; + + return NV_OK; +} + +/* ------------------------ Public Functions ------------------------------- */ +/*! + * On Hopper, we use GSP as SPDM Responder. To initialize, we must allocate + * a surface for SPDM communication, send initialization command to GSP-SPDM + * partition, and register all transport-layer functionality with library. + */ +NV_STATUS +spdmDeviceInit_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + NV_STATUS descHdrStatus = NV_OK; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + RmPhysAddr physAddr = 0; + NvU64 memDescFlags = MEMDESC_FLAGS_NONE; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + RMTIMEOUT timeout; + TRANSFER_SURFACE surf = {0}; + MemoryManager *pMemoryManager = NULL; + + if (pGpu == NULL || pSpdm == NULL || pSpdm->pLibspdmContext == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + g_pGpu = pGpu; + g_pSpdm = pSpdm; + + // Register transport layer functionality with library. + libspdm_register_transport_layer_func(pSpdm->pLibspdmContext, + _spdmEncodeMessageGsp, + _spdmDecodeMessageGsp, + _spdmGetTransportHeaderSizeGsp); + + libspdm_register_device_io_func(pSpdm->pLibspdmContext, + _spdmSendMessageGsp, + _spdmReceiveMessageGsp); + + + pSpdm->pDeviceIOContext = portMemAllocNonPaged(sizeof(SPDM_GSP_IO_CONTEXT)); + if (pSpdm->pDeviceIOContext == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; + portMemSet(pIOContext, 0, sizeof(SPDM_GSP_IO_CONTEXT)); + + // + // Set default values for IO context. + // TODO CONFCOMP-1463: Generalize command structures. + // + pIOContext->surfaceSizeInByte = NV_SPDM_RM_SURFACE_SIZE_IN_BYTE; + pIOContext->descHdrSizeInByte = NV_SPDM_DESC_HEADER_SIZE_IN_BYTE; + pIOContext->rmBufferSizeInByte = NV_RM_BUFFER_SIZE_IN_BYTE; + pIOContext->alignSize = SPDM_MESSAGE_BUFFER_ADDRESS_ALIGNMENT; + pIOContext->addrSpace = ADDR_SYSMEM; + pIOContext->regionId = NV_SPDM_UNPROTECTED_REGION_ID; + pIOContext->pResponse = NULL; + pIOContext->responseSize = 0; + + // Be sure to allocate in unprotected memory, so GPU can read. + memDescFlags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + // Create memory descriptor. + status = memdescCreate(&pIOContext->pMemDesc, pGpu, + pIOContext->surfaceSizeInByte, + pIOContext->alignSize, + NV_TRUE, pIOContext->addrSpace, + NV_MEMORY_UNCACHED, + memDescFlags); + if (status != NV_OK || pIOContext->pMemDesc == NULL) + { + portMemFree(pIOContext); + pSpdm->pDeviceIOContext = NULL; + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + status = memdescAlloc(pIOContext->pMemDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Cannot allocate SPDM surface!\n"); + memdescDestroy(pIOContext->pMemDesc); + portMemFree(pIOContext); + pSpdm->pDeviceIOContext = NULL; + return status; + } + + // Physical mode with GSP. + if ((pIOContext->addrSpace == ADDR_SYSMEM) || (pIOContext->addrSpace == ADDR_FBMEM)) + { + physAddr = memdescGetPhysAddr(pIOContext->pMemDesc, AT_GPU, 0); + } + else + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Message surface addr space is invalid: (0x%x)\n", + pIOContext->addrSpace); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto ErrorExit; + } + + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + surf.pMemDesc = pIOContext->pMemDesc; + surf.offset = 0; + + // Scrub surface + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemSet(pMemoryManager, &surf, 0, pIOContext->surfaceSizeInByte, + TRANSFER_FLAGS_NONE), + ErrorExit); + + pIOContext->dmaAddr = (NvU64)physAddr; + + // Prepare GSP-CMD and send to GSP-SPDM partition. + portMemSet(¶ms, 0, sizeof(params)); + + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_INIT; + + RM_GSP_SPDM_CMD_CC_INIT *pCcInit = ¶ms.cmd.ccInit; + RM_GSP_SPDM_CC_INIT_CTX *pCcInitCtx = &pCcInit->ccInitCtx; + + // Ucode is responsible for setting DMA index. + pCcInitCtx->dmaIdx = 0; + pCcInitCtx->guestId = pSpdm->guestId; + pCcInitCtx->regionId = pIOContext->regionId; + pCcInitCtx->addrSpace = pIOContext->addrSpace; + pCcInitCtx->rmBufferSizeInByte = NV_RM_BUFFER_SIZE_IN_BYTE; + NvU64_ALIGN32_PACK(&pCcInitCtx->dmaAddr, &pIOContext->dmaAddr); + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + + // + // If successful, copy status received from GSP-SPDM. In case of failure, we will + // unmap memory first before breaking to error handling routine. + // + if (status == NV_OK) + { + descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_INIT); + } + + // Now we check for command success. + if (status != NV_OK || descHdrStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: gspCommandPostBlocking() failed in INIT command, status = 0x%x, descHdrStatus = 0x%x \n", + status, descHdrStatus); + DBG_BREAKPOINT(); + + status = (status == NV_OK ? descHdrStatus : status); + goto ErrorExit; + } + + // If successful, save returned endpoint ID to context. + pSpdm->endpointId = params.msg.endpointId; + + // Sending Rm data for opaque data to GSP. + status = _spdmSendInitRmDataCommand(pGpu, pSpdm); + + SLI_LOOP_END + +ErrorExit: + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: INIT command failed: status 0x%x\n", status); + _spdmReleaseSurfaceGsp(pSpdm); + } + + return status; +} + + +/*! + * To deinitialize the GSP SPDM Responder, we need to release the surface for + * SPDM communcation, and send deinitialization command to GSP-SPDM. + */ +NV_STATUS +spdmDeviceDeinit_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvBool bForceClear +) +{ + NV_STATUS status = NV_OK; + NV_STATUS descHdrStatus = NV_OK; + RM_GSP_SPDM_CMD_CC_DEINIT *pCcDeinit = NULL; + RM_GSP_SPDM_CC_DEINIT_CTX *pCcDeinitCtx = NULL; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + RMTIMEOUT timeout; + + if (pGpu == NULL || pSpdm == NULL || pSpdm->pDeviceIOContext == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + + // Prepare GSP-CMD and send to GSP-SPDM partition. + portMemSet(¶ms, 0, sizeof(params)); + + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_DEINIT; + + // TODO CONFCOMP-1463: Generalize command structures. + pCcDeinit = ¶ms.cmd.ccDeinit; + pCcDeinitCtx = &pCcDeinit->ccDeinitCtx; + pCcDeinitCtx->guestId = pSpdm->guestId; + pCcDeinitCtx->endpointId = pSpdm->endpointId; + + if (bForceClear) + { + pCcDeinitCtx->flags |= DEINIT_FLAGS_FORCE_CLEAR; + } + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + + // + // If successful, copy status received from GSP-SPDM. In case of failure, we will + // unmap memory first before breaking to error handling routine. + // + if (status == NV_OK) + { + descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_DEINIT); + } + + SLI_LOOP_END + + if (status != NV_OK || descHdrStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: DEINIT command failed: status = 0x%x, descHdrStatus = 0x%x\n", + status, descHdrStatus); + DBG_BREAKPOINT(); + + status = (status == NV_OK ? descHdrStatus : status); + goto ErrorExit; + } + + // Only release surface on success, as we may want to retry deinit on failure. + _spdmReleaseSurfaceGsp(pSpdm); + +ErrorExit: + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: DEINIT command failed: status 0x%x\n", status); + } + + return status; +} + +NV_STATUS +spdmMessageProcess_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU32 ctrlCode, + NvU8 *pRequest, + NvU32 requestSize, + NvU8 *pResponse, + NvU32 *pResponseSize +) +{ + NV_STATUS status = NV_OK; + NV_STATUS descHdrStatus = NV_OK; + NvU8 *pMapMem = NULL; + NvU32 transportResponseSize = 0; + SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + RM_GSP_SPDM_CMD_CC_CTRL *pCcCtrl = NULL; + RM_GSP_SPDM_CC_CTRL_CTX *pCcCtrlCtx = NULL; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + RMTIMEOUT timeout; + MemoryManager *pMemoryManager = NULL; + TRANSFER_SURFACE surf = {0}; + NvBool bFreeShadowBuf = NV_FALSE; + + if (pGpu == NULL || pSpdm == NULL || pSpdm->pDeviceIOContext == NULL || + pRequest == NULL || pResponse == NULL || pResponseSize == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; + if (requestSize > pIOContext->rmBufferSizeInByte) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + // + // Map memory for CPU access to copy SPDM message - ensure we unmap + // before returning for any reason. + // + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + pMapMem = memmgrMemDescBeginTransfer(pMemoryManager, pIOContext->pMemDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); + if (pMapMem == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto ErrorExit; + } + + // Copy entire SPDM message to shared memory. + portMemCopy(pMapMem, requestSize, pRequest, requestSize); + + memmgrMemDescEndTransfer(pMemoryManager, pIOContext->pMemDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); + + // Prepare GSP-CMD and send to GSP-SPDM partition + portMemSet(¶ms, 0, sizeof(params)); + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_CTRL; + pCcCtrl = ¶ms.cmd.ccCtrl; + pCcCtrlCtx = &pCcCtrl->ccCtrlCtx; + pCcCtrlCtx->version = NV_SPDM_DESC_HEADER_VERSION_CURRENT; + pCcCtrlCtx->guestId = pSpdm->guestId; + pCcCtrlCtx->endpointId = pSpdm->endpointId; + pCcCtrlCtx->ctrlCode = ctrlCode; + pCcCtrlCtx->ctrlParam = 0; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + + // Retrieve descriptor header and response message, checking header to ensure valid response. + if (status == NV_OK) + { + surf.pMemDesc = pIOContext->pMemDesc; + surf.offset = 0; + + pMapMem = portMemAllocNonPaged(pIOContext->surfaceSizeInByte); + + if (pMapMem == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto ErrorExit; + } + + bFreeShadowBuf = NV_TRUE; + + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemRead(pMemoryManager, &surf, pMapMem, + pIOContext->surfaceSizeInByte, + TRANSFER_FLAGS_NONE), + ErrorExit); + + descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_CTRL); + } + + if (status != NV_OK || descHdrStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Process message failed: status = 0x%x, descHdrStatus = 0x%x\n", + status, descHdrStatus); + DBG_BREAKPOINT(); + + status = (status == NV_OK ? descHdrStatus : status); + goto ErrorExit; + } + + transportResponseSize = (((NV_SPDM_DESC_HEADER *)pMapMem)->msgSizeByte + NV_SPDM_DESC_HEADER_SIZE_IN_BYTE); + + if (transportResponseSize > *pResponseSize) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + NV_PRINTF(LEVEL_ERROR, "SPDM: Error: transportResponseSize = 0x%x, responseSize = 0x%x\n", + transportResponseSize, *pResponseSize); + DBG_BREAKPOINT(); + goto ErrorExit; + } + + portMemCopy(pResponse, *pResponseSize, pMapMem, transportResponseSize); + *pResponseSize = transportResponseSize; + + SLI_LOOP_END + +ErrorExit: + if (bFreeShadowBuf) + { + portMemFree(pMapMem); + bFreeShadowBuf = NV_FALSE; + } + return status; +} + +NV_STATUS +spdmDeviceSecuredSessionSupported_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + + return NV_OK; +} + +NV_STATUS +spdmCheckConnection_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + void *pContext = NULL; + uint32_t expectedFlags = 0; + uint32_t capabilitiesFlags = 0; + libspdm_return_t ret = LIBSPDM_STATUS_SUCCESS; + libspdm_data_parameter_t dataParam; + libspdm_connection_state_t connectionState; + uint8_t ctExponent; + size_t dataSize; + NvU32 i; + NvU32 algoCheckCount; + NvU32 expectedAlgo; + PSPDM_ALGO_CHECK_ENTRY pCheckEntry; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Ensure we have at least negotiated the parameters of the SPDM connection. + pContext = (void *)pSpdm->pLibspdmContext; + + if (pContext == NULL) + { + return NV_ERR_NOT_READY; + } + + dataParam.location = LIBSPDM_DATA_LOCATION_CONNECTION; + dataSize = sizeof(connectionState); + ret = libspdm_get_data(pContext, LIBSPDM_DATA_CONNECTION_STATE, + &dataParam, &connectionState, &dataSize); + + if (ret != LIBSPDM_STATUS_SUCCESS || connectionState < LIBSPDM_CONNECTION_STATE_NEGOTIATED) + { + return NV_ERR_NOT_READY; + } + + // Check version matches expected. + if (libspdm_get_connection_version(pContext) != SPDM_MESSAGE_VERSION_11) + { + return NV_ERR_INVALID_STATE; + } + + dataSize = sizeof(ctExponent); + ret = libspdm_get_data(pContext, LIBSPDM_DATA_CAPABILITY_CT_EXPONENT, + &dataParam, &ctExponent, &dataSize); + + if (ret != LIBSPDM_STATUS_SUCCESS || ctExponent != SPDM_CAPABILITIES_CT_EXPONENT_MAX) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Invalid Responder CT exponent.\n"); + return NV_ERR_INVALID_STATE; + } + + // Check all capabilities match expected. + expectedFlags = SPDM_CAPABILITIES_FLAGS_GH100; + + dataSize = sizeof(capabilitiesFlags); + ret = libspdm_get_data(pContext, LIBSPDM_DATA_CAPABILITY_FLAGS, + &dataParam, &capabilitiesFlags, &dataSize); + + if (ret != LIBSPDM_STATUS_SUCCESS || capabilitiesFlags != expectedFlags) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Invalid Responder capabilities.\n"); + return NV_ERR_INVALID_STATE; + } + + // Check all crypto algorithms match expected. + algoCheckCount = sizeof(g_SpdmAlgoCheckTable_GH100)/sizeof(SPDM_ALGO_CHECK_ENTRY); + + for (i = 0; i < algoCheckCount; i++) + { + pCheckEntry = &g_SpdmAlgoCheckTable_GH100[i]; + + dataSize = sizeof(expectedAlgo); + ret = libspdm_get_data(pContext, pCheckEntry->dataType, + &dataParam, &expectedAlgo, &dataSize); + + if (ret != LIBSPDM_STATUS_SUCCESS || expectedAlgo != pCheckEntry->expectedAlgo) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Invalid crypto algorithms selected.\n"); + NV_PRINTF(LEVEL_ERROR, "SPDM: AlgoCheckCount %d, i is %d, status is %d.\n", (NvU32)algoCheckCount, (NvU32)i, (NvU32)ret); + NV_PRINTF(LEVEL_ERROR, "SPDM: Expected ALgo %d, actual algo %d", (NvU32)expectedAlgo, (NvU32)pCheckEntry->expectedAlgo); + return NV_ERR_INVALID_STATE; + } + } + + return NV_OK; +} + +NV_STATUS +spdmGetCertificates_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pSpdm->pLibspdmContext == NULL) + { + return NV_ERR_NOT_READY; + } + + // Allocate buffer for certificates. + pSpdm->attestationCertChainSize = SPDM_MAX_CERT_CHAIN_SIZE; + pSpdm->pAttestationCertChain = portMemAllocNonPaged(pSpdm->attestationCertChainSize); + + // Ensure data was properly allocated. + if (pSpdm->pAttestationCertChain == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + // We fetch Attestation cert chain only on Hopper. + portMemSet(pSpdm->pAttestationCertChain, 0, pSpdm->attestationCertChainSize); + CHECK_SPDM_STATUS(libspdm_get_certificate(pSpdm->pLibspdmContext, SPDM_CERT_DEFAULT_SLOT_ID, + &pSpdm->attestationCertChainSize, + pSpdm->pAttestationCertChain)); +ErrorExit: + if (status != NV_OK) + { + // portMemFree() handles NULL. + portMemFree(pSpdm->pAttestationCertChain); + pSpdm->pAttestationCertChain = NULL; + pSpdm->attestationCertChainSize = 0; + } + + return status; +} + +NV_STATUS +spdmGetCertChains_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + void *pKeyExCertChain, + NvU32 *pKeyExCertChainSize, + void *pAttestationCertChain, + NvU32 *pAttestationCertChainSize +) +{ + NV_STATUS status = NV_OK; + NvU8 *pIkCertificate = NULL; + NvU32 ikCertificateSize = 0; + NvU8 *pAkCertificate = NULL; + NvU32 akCertificateSize = 0; + NvU8 *pSpdmCertChainBufferEnd = NULL; + libspdm_context_t *pContext = NULL; + uint32_t base_hash_algo = 0; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Ensure we have a valid session, and have retrieved the certificates. + if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId == INVALID_SESSION_ID || + pSpdm->pAttestationCertChain == NULL) + { + return NV_ERR_NOT_READY; + } + + // We don't support multiple cert chains. + if (pKeyExCertChainSize != NULL) + { + *pKeyExCertChainSize = 0; + } + + // Retrieve Attestation Cert Chain, if requested. + if (pAttestationCertChain != NULL && pAttestationCertChainSize != NULL) + { + // Comparison should account for type size mismatch. + if (pSpdm->attestationCertChainSize > (size_t)(*pAttestationCertChainSize)) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + // + // Get context + // + pContext = (libspdm_context_t *)pSpdm->pLibspdmContext; + if (pContext == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // Skip over the certificate chain size, reserved size and the root hash + // + + pSpdmCertChainBufferEnd = pSpdm->pAttestationCertChain + pSpdm->attestationCertChainSize; + base_hash_algo = pContext->connection_info.algorithm.base_hash_algo; + pIkCertificate = (NvU8 *)pSpdm->pAttestationCertChain; + pIkCertificate += sizeof(spdm_cert_chain_t) + libspdm_get_hash_size(base_hash_algo); + + if (pIkCertificate> pSpdmCertChainBufferEnd) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + status = _calcX509CertSize(pIkCertificate, pSpdmCertChainBufferEnd, &ikCertificateSize); + if (status != NV_OK) + { + return status; + } + + if (pIkCertificate + ikCertificateSize > pSpdmCertChainBufferEnd) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + pAkCertificate = (NvU8 *)pIkCertificate + ikCertificateSize; + + if (pAkCertificate + DER_CERT_SIZE_FIELD_LENGTH > pSpdmCertChainBufferEnd) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + status = _calcX509CertSize(pAkCertificate, pSpdmCertChainBufferEnd, &akCertificateSize); + if (status != NV_OK) + { + return status; + } + + if (pAkCertificate + akCertificateSize > pSpdmCertChainBufferEnd) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + status = _spdmBuildCertChain(pAkCertificate, akCertificateSize, + pIkCertificate, (size_t)ikCertificateSize, + pAttestationCertChain, pAttestationCertChainSize); + if (status != NV_OK) + { + return status; + } + } + + return NV_OK; +} + +NV_STATUS +spdmGetAttestationReport_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU8 *pNonce, + void *pAttestationReport, + NvU32 *pAttestationReportSize, + NvBool *pbIsCecAttestationReportPresent, + void *pCecAttestationReport, + NvU32 *pCecAttestationReportSize +) +{ + NV_STATUS status = NV_OK; + uint8_t numBlocks = 0; + uint32_t measurementSize = 0; + void *pMeasurementBuffer = NULL; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Ensure we have a valid session, and have retrieved the certificates. + if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId == INVALID_SESSION_ID) + { + return NV_ERR_NOT_READY; + } + + // Retrieve Attestation Report, if requested. + if (pAttestationReport != NULL && pAttestationReportSize != NULL) + { + // Guarantees the latest transcript will fit inside the Attestation Report buffer. + if (*pAttestationReportSize < SPDM_MAX_EXCHANGE_BUFFER_SIZE) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + numBlocks = LIBSPDM_MAX_MEASUREMENT_BLOCK_COUNT; + + // + // Use Attestation Report buffer temporarily to store measurements, we will replace + // with the full Attestation Report from message transcripts. + // + pMeasurementBuffer = pAttestationReport; + measurementSize = *pAttestationReportSize; + + // Request the Attestation Report using the provided nonce, signed by the AK cert. + CHECK_SPDM_STATUS(libspdm_get_measurement_ex(pSpdm->pLibspdmContext, &pSpdm->sessionId, + SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE, + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS, + SPDM_CERT_DEFAULT_SLOT_ID, NULL, &numBlocks, + &measurementSize, pMeasurementBuffer, pNonce, NULL, NULL)); + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + // libspdm detects assert/error in GET_MEASUREMENT process, need to return error. + NV_PRINTF(LEVEL_ERROR, "SPDM: spdmCheckAndClearLibspdmAssert() failed \n"); + DBG_BREAKPOINT(); + + return NV_ERR_INVALID_STATE; + } + + // + // Last exchange buffer will hold Attestation Report, which is comprised of + // the GET_MEASUREMENTS request concatenated with the MEASUREMENTS response. + // By definition, must be larger than the measurements written above. + // + portMemCopy(pAttestationReport, *pAttestationReportSize, + pSpdm->pLastExchange, pSpdm->lastExchangeSize); + *pAttestationReportSize = pSpdm->lastExchangeSize; + } + + // Retrieve CEC Attestation Report, if requested. + if (pbIsCecAttestationReportPresent != NULL) + { + *pbIsCecAttestationReportPresent = NV_FALSE; + } + +ErrorExit: + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c new file mode 100644 index 0000000000..cb6135a1f8 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Provides the implementation for SPDM module that interacts between RM and SPDM. + */ +/* ------------------------------ Includes ---------------------------------- */ +#include "gpu/spdm/spdm.h" +#include "gpu/conf_compute/conf_compute.h" +#include "core/locks.h" +#include "ctrl/ctrl2080/ctrl2080spdm.h" +#include "rmapi/client_resource.h" + +/* ------------------------- Macros and Defines ----------------------------- */ + +/* ------------------------- Static Functions ------------------------------ */ + +/* ------------------------- Public Functions ------------------------------ */ + +/*! + * @brief spdmCtrlSpdmPartition + * Common function used to call gspCommandPostBlocking based on the platform on which it runs (i.e. vGPU, GSP-RM, Monolithic). + * + * @param[in] pGpu : OBJGPU Pointer + * @param[in] pSpdmPartitionParams : SPDM RPC structure pointer + */ +NV_STATUS spdmCtrlSpdmPartition +( + OBJGPU *pGpu, + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS *pSpdmPartitionParams +) +{ + NV_STATUS status = NV_OK; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + if (IS_VIRTUAL(pGpu)) + { + // The control call currently doesn't support the vGPU environment, therefore return NV_ERR_NOT_SUPPORTED. + return NV_ERR_NOT_SUPPORTED; + } + else if (IS_GSP_CLIENT(pGpu)) + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // Calls the subdeviceCtrlCmdSpdmPartition_IMPL control call in Physical RM mode. + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_INTERNAL_SPDM_PARTITION, + pSpdmPartitionParams, + sizeof(NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS)); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + + return status; +} + diff --git a/src/nvidia/src/kernel/gpu/spdm/spdm.c b/src/nvidia/src/kernel/gpu/spdm/spdm.c new file mode 100644 index 0000000000..2d1ae8a055 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/spdm/spdm.c @@ -0,0 +1,541 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ + * * + * SPDM Object Module * + * * + \**************************************************************************/ + +/* ------------------------ Includes --------------------------------------- */ +#include "gpu/spdm/spdm.h" +#include "spdm/rmspdmtransport.h" +#include "spdm/rmspdmvendordef.h" +#include "gpu/gpu.h" +#include "gpu/gpu_resource.h" + +// +// Libspdm only supported on certain builds, +// take note if you are copying header elsewhere. +// +#include "gpu/spdm/libspdm_includes.h" + +/* ------------------------ Static Function Prototypes --------------------- */ +static void _spdmClearContext(Spdm *pSpdm); +libspdm_return_t _spdmAcquireTransportBuffer(void *context, size_t *max_msg_size, void **msg_buf_ptr); +void _spdmReleaseTransportBuffer(void *context, const void *msg_buf_ptr); +bool _spdmVerifyCertChain(void *spdm_context, uint8_t slot_id, size_t cert_chain_size, + const void *cert_chain, const void **trust_anchor, size_t *trust_anchor_size); + +/* ------------------------ Static Functions ------------------------------- */ +/* + * Helper to clear and free any SPDM object context. + */ +void +_spdmClearContext +( + Spdm *pSpdm +) +{ + NvU32 index = 0; + + if (pSpdm == NULL) + { + return; + } + + // + // If we haven't deinitialized session, not much we can do now. + // Make best effort to free any allocated Requester context, + // ensuring we scrub the libspdm context. + // + if (pSpdm->pLibspdmContext != NULL) + { + + libspdm_reset_message_b(pSpdm->pLibspdmContext); + libspdm_reset_message_c(pSpdm->pLibspdmContext); + libspdm_reset_message_mut_b(pSpdm->pLibspdmContext); + libspdm_reset_message_mut_c(pSpdm->pLibspdmContext); + + libspdm_reset_message_m(pSpdm->pLibspdmContext, NULL); + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) + { + libspdm_reset_message_m(pSpdm->pLibspdmContext, &(((libspdm_context_t *)pSpdm->pLibspdmContext)->session_info[index])); + } + + libspdm_deinit_context(pSpdm->pLibspdmContext); + libspdm_reset_context(pSpdm->pLibspdmContext); + portMemSet((NvU8 *)pSpdm->pLibspdmContext, 0, pSpdm->libspdmContextSize); + } + + if (pSpdm->pLibspdmScratch != NULL) + { + portMemSet((NvU8 *)pSpdm->pLibspdmScratch, 0, pSpdm->libspdmScratchSize); + } + + // portMemFree handles NULL pointers gracefully. + portMemFree(pSpdm->pLibspdmContext); + portMemFree(pSpdm->pLibspdmScratch); + portMemFree(pSpdm->pAttestationCertChain); + portMemFree(pSpdm->pDeviceIOContext); + portMemFree(pSpdm->pLastExchange); + + pSpdm->pLibspdmContext = NULL; + pSpdm->pLibspdmScratch = NULL; + pSpdm->pAttestationCertChain = NULL; + pSpdm->pDeviceIOContext = NULL; + pSpdm->pLastExchange = NULL; + + pSpdm->libspdmContextSize = 0; + pSpdm->libspdmScratchSize = 0; + pSpdm->attestationCertChainSize = 0; + pSpdm->lastExchangeSize = 0; + + pSpdm->guestId = 0; + pSpdm->sessionId = INVALID_SESSION_ID; + pSpdm->endpointId = 0; +} + +/* + * Transport layer helpers for send/receive message buffers. + */ +libspdm_return_t +_spdmAcquireTransportBuffer +( + void *context, + size_t *max_msg_size, + void **msg_buf_ptr +) +{ + if (context == NULL || max_msg_size == NULL || msg_buf_ptr == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + *msg_buf_ptr = portMemAllocNonPaged(SPDM_MAX_MESSAGE_BUFFER_SIZE); + if (*msg_buf_ptr == NULL) + { + return LIBSPDM_STATUS_BUFFER_FULL; + } + + *max_msg_size = SPDM_MAX_MESSAGE_BUFFER_SIZE; + + return LIBSPDM_STATUS_SUCCESS; +} + +void +_spdmReleaseTransportBuffer +( + void *context, + const void *msg_buf_ptr +) +{ + portMemFree((void *)msg_buf_ptr); +} + +bool +_spdmVerifyCertChain +( + void *spdm_context, + uint8_t slot_id, + size_t cert_chain_size, + const void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size +) +{ + return NV_TRUE; +} + +/* ------------------------ Public Functions ------------------------------- */ +/*! + * Constructor + */ +NV_STATUS +spdmConstruct_IMPL +( + Spdm *pSpdm +) +{ + + if (pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pSpdm->pLibspdmContext = NULL; + pSpdm->pLibspdmScratch = NULL; + pSpdm->pAttestationCertChain = NULL; + pSpdm->pDeviceIOContext = NULL; + pSpdm->pLastExchange = NULL; + + pSpdm->libspdmContextSize = 0; + pSpdm->libspdmScratchSize = 0; + pSpdm->attestationCertChainSize = 0; + pSpdm->lastExchangeSize = 0; + + pSpdm->guestId = 0; + pSpdm->sessionId = INVALID_SESSION_ID; + pSpdm->endpointId = 0; + + pSpdm->bExportSecretCleared = NV_FALSE; + + return NV_OK; +} + +/*! + * Destructor + */ +void +spdmDestruct_IMPL +( + Spdm * pSpdm +) +{ + _spdmClearContext(pSpdm); +} + +NV_STATUS +spdmContextInit_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + libspdm_data_parameter_t parameter; + uint8_t ctExponent; + uint32_t capFlags; + uint8_t measSpec; + uint32_t baseAsymAlgo; + uint32_t baseHashAlgo; + uint16_t dheGroup; + uint16_t aeadSuite; + uint16_t keySched; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Allocate and initialize all required memory for context and certificates. + pSpdm->libspdmContextSize = libspdm_get_context_size(); + pSpdm->pLibspdmContext = portMemAllocNonPaged(pSpdm->libspdmContextSize); + + if (pSpdm->libspdmContextSize == 0 || pSpdm->pLibspdmContext == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + portMemSet(pSpdm->pLibspdmContext, 0, pSpdm->libspdmContextSize); + libspdm_init_context(pSpdm->pLibspdmContext); + + // Allocate scratch space required for libspdm processing. + pSpdm->libspdmScratchSize = libspdm_get_sizeof_required_scratch_buffer(pSpdm->pLibspdmContext); + pSpdm->pLibspdmScratch = portMemAllocNonPaged(pSpdm->libspdmScratchSize); + + if (pSpdm->libspdmScratchSize == 0 || pSpdm->pLibspdmScratch == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + portMemSet(pSpdm->pLibspdmScratch, 0, pSpdm->libspdmScratchSize); + libspdm_set_scratch_buffer(pSpdm->pLibspdmContext, pSpdm->pLibspdmScratch, + pSpdm->libspdmScratchSize); + + // Allocate message transcript recording buffer. + pSpdm->pLastExchange = portMemAllocNonPaged(SPDM_MAX_EXCHANGE_BUFFER_SIZE); + pSpdm->lastExchangeSize = 0; + + if (pSpdm->pLastExchange == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + // + // Eventually, owner of Spdm object may want to set their own + // specific configuration. For now, hardcode the only supported configuration. + // + portMemSet(¶meter, 0, sizeof(parameter)); + parameter.location = LIBSPDM_DATA_LOCATION_LOCAL; + + // Requester will not check Responder's timing, set to maximum value. + ctExponent = SPDM_CAPABILITIES_CT_EXPONENT_MAX; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_CAPABILITY_CT_EXPONENT, + ¶meter, &ctExponent, sizeof(ctExponent))); + + capFlags = SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, + LIBSPDM_DATA_CAPABILITY_FLAGS, ¶meter, + &capFlags, sizeof(capFlags))); + + measSpec = SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, + LIBSPDM_DATA_MEASUREMENT_SPEC, ¶meter, + &measSpec, sizeof(measSpec))); + + baseAsymAlgo = SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_BASE_ASYM_ALGO, + ¶meter, &baseAsymAlgo, + sizeof(baseAsymAlgo))); + + baseHashAlgo = SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_BASE_HASH_ALGO, + ¶meter, &baseHashAlgo, + sizeof(baseHashAlgo))); + + dheGroup = SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_DHE_NAME_GROUP, + ¶meter, &dheGroup, sizeof(dheGroup))); + + aeadSuite = SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_AEAD_CIPHER_SUITE, + ¶meter, &aeadSuite, sizeof(aeadSuite))); + + keySched = SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_KEY_SCHEDULE, + ¶meter, &keySched, sizeof(keySched))); + + pSpdm->guestId = 0x01; + + // + // Perform any device-specific initialization. spdmDeviceInit is also + // responsible for registering transport layer functions with libspdm. + // + status = spdmDeviceInit_HAL(pGpu, pSpdm); + if (status != NV_OK) + { + goto ErrorExit; + } + + libspdm_register_device_buffer_func(pSpdm->pLibspdmContext, + _spdmAcquireTransportBuffer, _spdmReleaseTransportBuffer, + _spdmAcquireTransportBuffer, _spdmReleaseTransportBuffer); + + // + // Verifier is responsible for verifying the certificate chain. To avoid concerns + // with libspdm compatibility, override certificate validation function with stub. + // + libspdm_register_verify_spdm_cert_chain_func(pSpdm->pLibspdmContext, _spdmVerifyCertChain); + +ErrorExit: + + // Clear all SPDM state on failure. + if (status != NV_OK) + { + _spdmClearContext(pSpdm); + } + + return status; +} + +NV_STATUS +spdmContextDeinit_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvBool bForceClear +) +{ + NV_STATUS status = NV_OK; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // If no session to end, just wipe state and return. + if (pSpdm->pLibspdmContext == NULL) + { + _spdmClearContext(pSpdm); + return NV_OK; + } + + // + // End the session, then deinitialize the Responder. + // + // TODO CONFCOMP-1490: Formally send END_SESSION, even thouh + // deinitializing Responder will end session regardless. + // + NV_PRINTF(LEVEL_INFO, "SPDM: Tearing down session.\n"); + // CHECK_SPDM_STATUS(libspdm_stop_session(pSpdm->pLibspdmContext, pSpdm->sessionId, 0)); + status = spdmDeviceDeinit_HAL(pGpu, pSpdm, NV_TRUE); + + // Regardless of success or failure, clear any context. + _spdmClearContext(pSpdm); + + // We really shouldn't fail on deinitialization - ASSERT if we do. + NV_ASSERT_OK(status); + return status; +} + +NV_STATUS +spdmStart_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pSpdm->pLibspdmContext == NULL) + { + return NV_ERR_NOT_READY; + } + + // Send GET_VERSION, GET_CAPABILITIES, and NEGOTIATE_ALGORITHMS to Responder. + NV_PRINTF(LEVEL_INFO, "SPDM: Starting new SPDM connection.\n"); + CHECK_SPDM_STATUS(libspdm_init_connection(pSpdm->pLibspdmContext, NV_FALSE)); + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: libspdm_init_connection() assert hit !!!.\n"); + status = NV_ERR_GENERIC; + goto ErrorExit; + } + + // Ensure the connection attributes match expected. + status = spdmCheckConnection_HAL(pGpu, pSpdm); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Connection attributes did not match expected!\n"); + goto ErrorExit; + } + + // Fetch the certificates from the responder + status = spdmGetCertificates_HAL(pGpu, pSpdm); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Certificate retrieval failed!\n"); + goto ErrorExit; + } + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: spdmGetCertificates_HAL() assert hit !!!.\n"); + status = NV_ERR_GENERIC; + goto ErrorExit; + } + + // + // Complete the SPDM handshake and start the secured session. + // Ensure we match type of sessionId parameter with what libspdm expects. + // + if (spdmDeviceSecuredSessionSupported_HAL(pGpu, pSpdm) == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "SPDM: Attempting to establish SPDM session.\n"); + CHECK_SPDM_STATUS(libspdm_start_session(pSpdm->pLibspdmContext, NV_FALSE, + SPDM_KEY_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH, + SPDM_CERT_DEFAULT_SLOT_ID, 0, &pSpdm->sessionId, NULL, NULL)); + + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: libspdm_start_session() assert hit !!!.\n"); + status = NV_ERR_GENERIC; + goto ErrorExit; + } + else + { + NV_PRINTF(LEVEL_INFO, "SPDM: Session establishment successful: sessionId 0x%x.\n", + pSpdm->sessionId); + } + } + +ErrorExit: + + // + // On error, set session as invalid. Don't need to reset context, since + // restarting SPDM exchange is valid scenario. Responder may not support. + // + if (status != NV_OK) + { + pSpdm->sessionId = INVALID_SESSION_ID; + NV_PRINTF(LEVEL_ERROR, "SPDM: Session establishment failed!\n"); + DBG_BREAKPOINT(); + } + + return status; +} + +NV_STATUS +spdmRetrieveExportSecret_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU32 keySize, + NvU8 *pKeyOut +) +{ + size_t keySizeSizeT = 0; + libspdm_secured_message_context_t *pSessionContext = NULL; + + // Basic parameter validation. + if (pGpu == NULL || pSpdm == NULL || keySize == 0 || pKeyOut == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Ensure we are in valid state. Note that export master secret can only be retrieved once. + if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId == INVALID_SESSION_ID || + pSpdm->bExportSecretCleared) + { + return NV_ERR_NOT_READY; + } + + pSessionContext = + libspdm_get_secured_message_context_via_session_id(pSpdm->pLibspdmContext, pSpdm->sessionId); + if (pSessionContext == NULL) + { + return NV_ERR_INVALID_STATE; + } + + // + // Fetch the export master secret. + // Use temporary size variable to handle type differences and avoid overflow. + // + keySizeSizeT = keySize; + if (!libspdm_secured_message_export_master_secret(pSessionContext, pKeyOut, &keySizeSizeT)) + { + return NV_ERR_INVALID_STATE; + } + + // Clear the export master secret from SPDM memory. + libspdm_secured_message_clear_export_master_secret(pSessionContext); + pSpdm->bExportSecretCleared = NV_TRUE; + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c index 87f1a54f8a..0e3082ff99 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -422,124 +422,3 @@ subdeviceRestoreWatchdog_IMPL krcWatchdogChangeState(pKernelRc, pSubdevice, RM_CLIENT_DESTRUCTION); } -// **************************************************************************** -// Deprecated Functions -// **************************************************************************** - -/** - * WARNING: This function is deprecated! Please use subdeviceGetByGpu and - * GPU_RES_SET_THREAD_BC_STATE (if needed to set thread UC state for SLI) - */ -Subdevice * -CliGetSubDeviceInfoFromGpu -( - NvHandle hClient, - OBJGPU *pGpu -) -{ - RsClient *pClient; - NV_STATUS status; - Subdevice *pSubdevice; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return NULL; - - status = subdeviceGetByGpu(pClient, pGpu, &pSubdevice); - if (status != NV_OK) - return NULL; - - GPU_RES_SET_THREAD_BC_STATE(pSubdevice); - - return pSubdevice; -} - -/** - * WARNING: This function is deprecated! Please use subdeviceGetByGpu and - * RES_GET_HANDLE - */ -NV_STATUS -CliGetSubDeviceHandleFromGpu -( - NvHandle hClient, - OBJGPU *pGpu, - NvHandle *phSubDevice -) -{ - Subdevice *pSubdevice; - - if (phSubDevice == NULL) - { - return NV_ERR_INVALID_ARGUMENT; - } - - if ((pSubdevice = CliGetSubDeviceInfoFromGpu(hClient, pGpu)) == NULL) - { - return NV_ERR_INVALID_ARGUMENT; - } - - *phSubDevice = RES_GET_HANDLE(pSubdevice); - - return NV_OK; -} - -/** - * WARNING: This function is deprecated and use is *strongly* discouraged - * (especially for new code!) - * - * From the function name (CliSetSubDeviceContext) it appears as a simple - * accessor but violates expectations by modifying the SLI BC threadstate (calls - * to GPU_RES_SET_THREAD_BC_STATE). This can be dangerous if not carefully - * managed by the caller. - * - * Instead of using this routine, please use subdeviceGetByHandle then call - * GPU_RES_GET_GPU, RES_GET_HANDLE, GPU_RES_SET_THREAD_BC_STATE as needed. - * - * Note that GPU_RES_GET_GPU supports returning a pGpu for both pDevice, - * pSubdevice, the base pResource type, and any resource that inherits from - * GpuResource. That is, instead of using CliSetGpuContext or - * CliSetSubDeviceContext, please use following pattern to look up the pGpu: - * - * OBJGPU *pGpu = GPU_RES_GET_GPU(pResource or pResourceRef->pResource) - * - * To set the threadstate, please use: - * - * GPU_RES_SET_THREAD_BC_STATE(pResource or pResourceRef->pResource); - */ -NV_STATUS -CliSetSubDeviceContext -( - NvHandle hClient, - NvHandle hSubdevice, - NvHandle *phDevice, - OBJGPU **ppGpu -) -{ - Subdevice *pSubdevice; - RsClient *pClient; - NV_STATUS status; - - if (phDevice != NULL) - { - *phDevice = 0; - } - *ppGpu = NULL; - - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return status; - - status = subdeviceGetByHandle(pClient, hSubdevice, &pSubdevice); - if (status != NV_OK) - return status; - - *ppGpu = GPU_RES_GET_GPU(pSubdevice); - if (phDevice != NULL) - { - *phDevice = RES_GET_HANDLE(pSubdevice->pDevice); - } - - GPU_RES_SET_THREAD_BC_STATE(pSubdevice); - - return NV_OK; -} diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c index 6379cfd6f9..17f8122cc4 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c @@ -192,7 +192,7 @@ subdeviceCtrlCmdEventSetMemoryNotifies_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, memGetByHandle(pClient, pSetMemoryNotifiesParams->hMemory, &pMemory)); - if (pMemory->pMemDesc->Size < NV_SIZEOF32(NvNotification) * NV2080_NOTIFIERS_MAXCOUNT) + if (pMemory->pMemDesc->Size < sizeof(NvNotification) * NV2080_NOTIFIERS_MAXCOUNT) { return NV_ERR_INVALID_LIMIT; } diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c index 0dd00837b3..c7e5294639 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c @@ -293,3 +293,4 @@ subdeviceCtrlCmdFlaGetFabricMemStats_IMPL return fabricvaspaceGetFreeHeap(pFabricVAS, &pParams->freeSize); } + diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index fe52daf9a1..913b1d77ec 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,6 +29,9 @@ * File contains ctrls related to general GPU */ +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "core/locks.h" #include "gpu/subdevice/subdevice.h" @@ -196,13 +199,12 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } portMemSet(¶ms, 0x0, sizeof(params)); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE, - ¶ms, - sizeof(params))); + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE, + ¶ms, + sizeof(params)); data = params.smcMode; break; } @@ -319,6 +321,35 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } break; } + case NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY: + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + if (memmgrIsLocalEgmEnabled(pMemoryManager)) + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES; + data = FLD_SET_DRF_NUM(2080_CTRL_GPU_INFO, _INDEX_GPU_LOCAL_EGM, _PEERID, pMemoryManager->localEgmPeerId, data); + } + else + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO; + } + break; + } + case NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY: + { + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + if (gpuIsSelfHosted(pGpu) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP)) + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES; + } + else + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO; + } + break; + } case NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU: { if (gpuGetChipInfo(pGpu) && gpuGetChipInfo(pGpu)->isCmpSku) @@ -337,12 +368,23 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, if (osDmabufIsSupported() && (!IS_VIRTUAL(pGpu)) && + (!gpuIsApmFeatureEnabled(pGpu)) && (!NVCPU_IS_PPC64LE)) { data = NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES; } break; } + case NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED: + { + data = NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED)) + { + data = NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES; + } + break; + } default: { // Only forward to GSP if we're in the HW-access-enabled control @@ -974,7 +1016,7 @@ subdeviceCtrlCmdGpuGetEnginesV2_IMPL if (pKernelMIGManager != NULL) { RM_ENGINE_TYPE rmEngineTypeList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; - + // Filter engines based on current partitioning scheme status = kmigmgrFilterEngineList(pGpu, pKernelMIGManager, @@ -1011,10 +1053,28 @@ subdeviceCtrlCmdGpuGetEngineClasslist_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); ENGDESCRIPTOR engDesc; NV_STATUS status = NV_OK; + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pClassParams->engineType); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); - status = gpuXlateClientEngineIdToEngDesc(pGpu, gpuGetRmEngineType(pClassParams->engineType), &engDesc); + { + if (IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, GPU_RES_GET_DEVICE(pSubdevice), &ref)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, + rmEngineType, + &rmEngineType)); + } + } + + status = gpuXlateClientEngineIdToEngDesc(pGpu, rmEngineType, &engDesc); + NV_ASSERT(status == NV_OK); if (status != NV_OK) @@ -1051,7 +1111,6 @@ subdeviceCtrlCmdGpuGetEnginePartnerList_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); ENGDESCRIPTOR engDesc; NvU32 localNv2080EngineType; @@ -1095,11 +1154,12 @@ subdeviceCtrlCmdGpuGetEnginePartnerList_IMPL // Translate the instance-local engine type to the global engine type in MIG mode if (IS_MIG_IN_USE(pGpu)) { + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, @@ -1191,11 +1251,11 @@ subdeviceCtrlCmdGpuGetEngineFaultInfo_IMPL if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, @@ -1721,13 +1781,14 @@ subdeviceCtrlCmdGpuGetPids_IMPL if (IS_MIG_IN_USE(pGpu) && !rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_SMC_MONITOR)) { + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); // // Check instanceSubscription to limit the scope of the call // Clients with mig-monitor capability are allowed to get full device // info // - NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, pRef) == NV_OK), + NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, pRef) == NV_OK), NV_ERR_INSUFFICIENT_PERMISSIONS); } @@ -1787,13 +1848,14 @@ subdeviceCtrlCmdGpuGetPidInfo_IMPL if (IS_MIG_IN_USE(pGpu) && !rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_SMC_MONITOR)) { + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); // // Check instanceSubscription to limit the scope of the call // Clients with mig-monitor capability are allowed to get full device // info // - NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, pRef) == NV_OK), + NV_CHECK_OR_RETURN(LEVEL_INFO, (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, pRef) == NV_OK), NV_ERR_INSUFFICIENT_PERMISSIONS); bGlobalInfo = NV_FALSE; } @@ -1876,14 +1938,13 @@ subdeviceCtrlCmdGpuGetEngineRunlistPriBase_IMPL if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - MIG_INSTANCE_REF ref; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); + MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, @@ -1948,14 +2009,13 @@ subdeviceCtrlCmdGpuGetHwEngineId_IMPL if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - MIG_INSTANCE_REF ref; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); + MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, @@ -1994,6 +2054,7 @@ subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL pParams->maxSupportedPageSize = RM_PAGE_SIZE; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + if (kgmmuIsPageSize512mbSupported(pKernelGmmu)) { pParams->maxSupportedPageSize = RM_PAGE_SIZE_512M; @@ -2004,10 +2065,12 @@ subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL } else { - pParams->maxSupportedPageSize = kgmmuGetMaxBigPageSize_HAL(pKernelGmmu); + pParams->maxSupportedPageSize = (NvU32)kgmmuGetMaxBigPageSize_HAL(pKernelGmmu); } - if (gpuIsSriovEnabled(pGpu)) + if (gpuIsSriovEnabled(pGpu) + || gpuIsCCFeatureEnabled(pGpu) + ) { NvU64 vmmuSegmentSize = gpuGetVmmuSegmentSize(pGpu); if (vmmuSegmentSize > 0 && @@ -2043,8 +2106,9 @@ subdeviceCtrlCmdGpuGetNumMmusPerGpc_IMPL } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pSubdevice), - &pParams->grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, + GPU_RES_GET_DEVICE(pSubdevice), + &pParams->grRouteInfo, &pKernelGraphics)); pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2449,6 +2513,7 @@ subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL if (pP2PInfo[idx].gfid == INVALID_P2P_GFID) { pP2PInfo[idx].gfid = pParams->gfid; + pGpu->sriovState.p2pFabricPartitionId = pParams->fabricPartitionId; bSetP2PAccess = NV_TRUE; break; } @@ -2458,6 +2523,7 @@ subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL if (pP2PInfo[idx].gfid == pParams->gfid) { pP2PInfo[idx].gfid = INVALID_P2P_GFID; + pGpu->sriovState.p2pFabricPartitionId = INVALID_FABRIC_PARTITION_ID; bSetP2PAccess = NV_TRUE; break; } @@ -2483,6 +2549,19 @@ subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL return NV_OK; } +/* + * Set the EGM fabric base address + */ +NV_STATUS +subdeviceCtrlCmdGpuSetEgmGpaFabricAddr_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS *pParams +) +{ + return NV_OK; +} + /*! * @brief: This command returns the load time (latency) of each engine, * implementing NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES control call. @@ -2611,13 +2690,13 @@ subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - if (pGpu->pGpuFabricProbeInfo == NULL) + if (pGpu->pGpuFabricProbeInfoKernel == NULL) { pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED; return NV_OK; } - status = gpuFabricProbeGetNumProbeReqs(pGpu->pGpuFabricProbeInfo, + status = gpuFabricProbeGetNumProbeReqs(pGpu->pGpuFabricProbeInfoKernel, &numProbeReqs); if (status != NV_OK) { @@ -2629,10 +2708,10 @@ subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED : NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS; - if (gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfo)) + if (gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfoKernel)) { pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE; - pParams->status = gpuFabricProbeGetFmStatus(pGpu->pGpuFabricProbeInfo); + pParams->status = gpuFabricProbeGetFmStatus(pGpu->pGpuFabricProbeInfoKernel); if (pParams->status != NV_OK) { // Nothing needs to be done as probe response status is not success @@ -2641,13 +2720,13 @@ subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL ct_assert(NV2080_GPU_FABRIC_CLUSTER_UUID_LEN == NV_UUID_LEN); - NV_ASSERT_OK(gpuFabricProbeGetClusterUuid(pGpu->pGpuFabricProbeInfo, + NV_ASSERT_OK(gpuFabricProbeGetClusterUuid(pGpu->pGpuFabricProbeInfoKernel, pClusterUuid)); - NV_ASSERT_OK(gpuFabricProbeGetFabricPartitionId(pGpu->pGpuFabricProbeInfo, + NV_ASSERT_OK(gpuFabricProbeGetFabricPartitionId(pGpu->pGpuFabricProbeInfoKernel, &pParams->fabricPartitionId)); - NV_ASSERT_OK(gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps)); + NV_ASSERT_OK(gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps)); pParams->fabricCaps = _convertGpuFabricProbeInfoCaps(fmCaps); } diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c index c544f3f378..6828ebaa76 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -120,7 +120,7 @@ subdeviceCtrlCmdGpuExecRegOps_cmn RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; NvBool bUseMigratableOps; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); NV_PRINTF(LEVEL_INFO, "client 0x%x channel 0x%x\n", hClientTarget, hChannelTarget); diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c index e40d1e45a6..b6c8864c47 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c @@ -292,11 +292,44 @@ subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - NV_ASSERT_OR_RETURN((pParams->sampleCount <= - NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES), - NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_SILENT, + (pParams->sampleCount <= NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES), + NV_ERR_INVALID_ARGUMENT); - switch (pParams->cpuClkId) + if (RMCFG_FEATURE_PLATFORM_GSP) + { + NV_ASSERT_OR_RETURN( + FLD_TEST_DRF(2080, _TIMER_GPU_CPU_TIME_CPU_CLK_ID, _PROCESSOR, _GSP, + pParams->cpuClkId), + NV_ERR_INVALID_ARGUMENT); + } + else if (FLD_TEST_DRF(2080, _TIMER_GPU_CPU_TIME_CPU_CLK_ID, _PROCESSOR, _GSP, + pParams->cpuClkId)) + { + // + // If GSP time is requested, forward the whole request to GSP. + // This can only be supported in GSP-RM offload mode. + // + if (!IS_GSP_CLIENT(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + return pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO, + pParams, sizeof(*pParams)); + } + else + { + NV_CHECK_OR_RETURN(LEVEL_SILENT, + FLD_TEST_DRF(2080, _TIMER_GPU_CPU_TIME_CPU_CLK_ID, _PROCESSOR, _CPU, + pParams->cpuClkId), + NV_ERR_INVALID_ARGUMENT); + } + + switch (DRF_VAL(2080, _TIMER_GPU_CPU_TIME_CPU_CLK_ID, _SOURCE, pParams->cpuClkId)) { case NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME: { diff --git a/src/nvidia/src/kernel/gpu/sw_test.c b/src/nvidia/src/kernel/gpu/sw_test.c index 9e9ba79d93..e167f26ca7 100644 --- a/src/nvidia/src/kernel/gpu/sw_test.c +++ b/src/nvidia/src/kernel/gpu/sw_test.c @@ -58,7 +58,7 @@ NV_STATUS swtestGetSwMethods_IMPL ) { *ppMethods = Nv04SoftwareTestMethods; - *pNumMethods = NV_ARRAY_ELEMENTS32(Nv04SoftwareTestMethods); + *pNumMethods = NV_ARRAY_ELEMENTS(Nv04SoftwareTestMethods); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/timed_semaphore.c b/src/nvidia/src/kernel/gpu/timed_semaphore.c index c66017f01f..ab908c16c6 100644 --- a/src/nvidia/src/kernel/gpu/timed_semaphore.c +++ b/src/nvidia/src/kernel/gpu/timed_semaphore.c @@ -104,7 +104,7 @@ _9074TimedSemRelease ( OBJGPU *pGpu, ChannelDescendant *pObject, - NvHandle hClient, + RsClient *pClient, NvU64 notifierGPUVA, NvU64 semaphoreGPUVA, NvU64 time, @@ -122,7 +122,7 @@ _9074TimedSemRelease pObject->pKernelChannel->hVASpace, releaseValue, notifierStatus, - hClient); + pClient); // timedSemaphoreRelease_HAL will print errors on its own if (status != NV_OK) @@ -183,7 +183,7 @@ _9074TimedSemRequest { status = _9074TimedSemRelease(pGpu, pObject, - RES_GET_CLIENT_HANDLE(pTimedSemSw), + RES_GET_CLIENT(pTimedSemSw), notifierGPUVA, semaphoreGPUVA, currentTime, @@ -568,7 +568,7 @@ static NV_STATUS _class9074TimerCallback status = _9074TimedSemRelease(pGpu, pObject, - RES_GET_CLIENT_HANDLE(pTimedSemSw), + RES_GET_CLIENT(pTimedSemSw), pTimedSemEntry->NotifierGPUVA, pTimedSemEntry->SemaphoreGPUVA, currentTime, @@ -612,7 +612,7 @@ NV_STATUS tsemaGetSwMethods_IMPL ) { *ppMethods = GF100TimedSemSwMethods; - *pNumMethods = NV_ARRAY_ELEMENTS32(GF100TimedSemSwMethods); + *pNumMethods = NV_ARRAY_ELEMENTS(GF100TimedSemSwMethods); return NV_OK; } @@ -625,7 +625,7 @@ tsemaRelease_KERNEL NvU32 hVASpace, NvU32 releaseValue, NvU32 completionStatus, - NvHandle hClient + RsClient *pClient ) { OBJTMR *pTmr = GPU_GET_TIMER(pGpu); @@ -636,7 +636,7 @@ tsemaRelease_KERNEL tmrGetCurrentTime(pTmr, ¤tTime); status = semaphoreFillGPUVATimestamp(pGpu, - hClient, + pClient, hVASpace, semaphoreVA, releaseValue, @@ -652,7 +652,7 @@ tsemaRelease_KERNEL } status = notifyFillNotifierGPUVATimestamp(pGpu, - hClient, + pClient, hVASpace, notifierVA, 0, /* Info32 */ diff --git a/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c b/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c index 9d62346de0..7107ba1d02 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c @@ -29,6 +29,7 @@ /* ------------------------- Includes --------------------------------------- */ #include "gpu/gpu.h" #include "objtmr.h" +#include "gpu/fsp/kern_fsp.h" #include "published/hopper/gh100/dev_vm.h" #include "published/hopper/gh100/dev_timer.h" #include "published/hopper/gh100/dev_gc6_island.h" @@ -36,6 +37,7 @@ /* ------------------------- Macros ----------------------------------------- */ /* ------------------------- Static Function Prototypes --------------------- */ /* ------------------------- Public Functions ------------------------------ */ + /* * @brief Sets the GPU time to the current wall-clock time. * @@ -50,7 +52,9 @@ NV_STATUS tmrSetCurrentTime_GH100 OBJTMR *pTmr ) { - NvU64 ns; + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + NvU64 osTimeNs, secTimerNs, sysTimerOffsetNs; + NvU32 secTimerLo, secTimerHi, secTimerHi2; NvU32 seconds; NvU32 useconds; @@ -60,10 +64,42 @@ NV_STATUS tmrSetCurrentTime_GH100 "osGetCurrentTime returns 0x%x seconds, 0x%x useconds\n", seconds, useconds); - ns = ((NvU64)seconds * 1000000 + useconds) * 1000; + osTimeNs = ((NvU64)seconds * 1000000 + useconds) * 1000; + + // + // Get the current secure timer value to calculate the offset to apply + // Use hi-lo-hi reading to ensure a consistent value. + // + secTimerHi2 = GPU_REG_RD32(pGpu, NV_PGC6_SCI_SEC_TIMER_TIME_1); + do + { + secTimerHi = secTimerHi2; + secTimerLo = GPU_REG_RD32(pGpu, NV_PGC6_SCI_SEC_TIMER_TIME_0); + secTimerHi2 = GPU_REG_RD32(pGpu, NV_PGC6_SCI_SEC_TIMER_TIME_1); + } while (secTimerHi != secTimerHi2); + secTimerNs = secTimerLo | (((NvU64)secTimerHi) << 32); + + NV_ASSERT_OR_RETURN(secTimerNs < osTimeNs, NV_ERR_INVALID_STATE); + sysTimerOffsetNs = osTimeNs - secTimerNs; - GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_1, NvU64_HI32(ns)); - GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_0, NvU64_LO32(ns)); + if ((pKernelFsp == NULL) || !kfspRequiresBug3957833WAR_HAL(pGpu, pKernelFsp)) + { + // + // We can only safely program the timer offset if FSP includes the fix + // for bug 3957833. + // + GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_1, NvU64_HI32(sysTimerOffsetNs)); + GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_0, NvU64_LO32(sysTimerOffsetNs) | + DRF_DEF(_PGC6, _SCI_SYS_TIMER_OFFSET_0, _UPDATE, _TRIGGER)); + } + + // + // PTIMER (the system timer) may need to be manually adjusted by the offset + // everywhere it is supposed to match the host timestamp (for cases where + // the above writes didn't stick, or where the calling code doesn't have + // ready access to NV_PTIMER_TIME). + // + pTmr->sysTimerOffsetNs = sysTimerOffsetNs; return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/timer/timer.c b/src/nvidia/src/kernel/gpu/timer/timer.c index 1fa2641413..d0b480f2e1 100644 --- a/src/nvidia/src/kernel/gpu/timer/timer.c +++ b/src/nvidia/src/kernel/gpu/timer/timer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -556,20 +556,29 @@ NV_STATUS tmrEventScheduleRel_IMPL NvU64 AbsTime, currentTime; NV_STATUS rmStatus; + if ((pEvent != NULL) && tmrIsOSTimer(pTmr, pEvent)) + { + TMR_EVENT_PVT *pEventPvt = (TMR_EVENT_PVT *)pEvent; + + NV_CHECK_OK(rmStatus, LEVEL_ERROR, + tmrEventScheduleRelOSTimer_HAL(pTmr, pEvent, RelTime)); + // + // Capture system time here, this will help in scheduling callbacks + // if there is a state unload before receiving the OS timer callback. + // + osGetCurrentTick(&pEventPvt->startTimeNs); + if (!tmrEventOnList(pTmr, pEvent)) + { + _tmrInsertCallback(pTmr, pEventPvt, RelTime); + } + return rmStatus; + } + rmStatus = tmrGetCurrentTime(pTmr, ¤tTime); if (rmStatus != NV_OK) return rmStatus; - if (tmrIsOSTimer(pTmr, pEvent)) - { - /*HR timer scheduled in relative mode*/ - /*TBD : This condition needs to be moved to OS timer handling functions */ - AbsTime = RelTime; - } - else - { - NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddU64(currentTime, RelTime, &AbsTime), NV_ERR_INVALID_ARGUMENT); - } + NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddU64(currentTime, RelTime, &AbsTime), NV_ERR_INVALID_ARGUMENT); return tmrEventScheduleAbs(pTmr, pEvent, AbsTime); } @@ -635,8 +644,8 @@ NvBool tmrEventOnList_IMPL ) { PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pEventPublic; - PTMR_EVENT_PVT pScan = tmrIsOSTimer(pTmr, pEventPublic) ? - pTmr->pRmActiveOSTimerEventList : + PTMR_EVENT_PVT pScan = tmrIsOSTimer(pTmr, pEventPublic) ? + pTmr->pRmActiveOSTimerEventList : pTmr->pRmActiveEventList; while (pScan != NULL) @@ -770,7 +779,6 @@ _tmrInsertCallbackInList { pEvent->pNext = pTmr->pRmActiveOSTimerEventList; pTmr->pRmActiveOSTimerEventList = pEvent; - pEvent->bInUse = NV_FALSE; return; } @@ -850,29 +858,25 @@ NV_STATUS tmrEventScheduleAbs_IMPL ( OBJTMR *pTmr, PTMR_EVENT pEventPublic, - NvU64 Time + NvU64 timeAbsNs ) { NV_STATUS rmStatus = NV_OK; - PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pEventPublic; + TMR_EVENT_PVT *pEvent = (TMR_EVENT_PVT *)pEventPublic; - if ((pEventPublic != NULL) && (tmrIsOSTimer(pTmr, pEventPublic))) + if ((pEvent != NULL) && tmrIsOSTimer(pTmr, pEventPublic)) { - NV_CHECK_OK(rmStatus, LEVEL_ERROR, - tmrEventScheduleAbsOSTimer_HAL(pTmr, pEventPublic, Time)); // - // Capture system time here, this will help in scheduling callbacks - // if there is a state unload before receiving the OS timer callback. + // OS-Timer is supported only in Relative mode. This assert is to trap + // if someone trying to call tmrEventScheduleAbs for OSTimer // - osGetCurrentTick(&pEvent->startTimeNs); - if (!tmrEventOnList(pTmr, pEventPublic)) - { - _tmrInsertCallback(pTmr, pEvent, Time); - } + NV_ASSERT_FAILED("Attempting to schedule OS-Timer callback with Abs time."); + rmStatus = NV_ERR_INVALID_ARGUMENT; return rmStatus; } - if (pEventPublic->pTimeProc == NULL && pEvent->pTimeProc_OBSOLETE == NULL) + if ((pEvent == NULL) || (pEventPublic->pTimeProc == NULL && + pEvent->pTimeProc_OBSOLETE == NULL)) { // // Bug 372159: Not sure exactly how this is happening, but we are seeing @@ -903,7 +907,7 @@ NV_STATUS tmrEventScheduleAbs_IMPL // removed the 250 ns threshold, so that we will always re-read the // current time after setting the alarm to prevent the wrap-around. // - rmStatus = _tmrInsertCallback(pTmr, pEvent, Time); + rmStatus = _tmrInsertCallback(pTmr, pEvent, timeAbsNs); } return rmStatus; @@ -1067,6 +1071,7 @@ _tmrScanCallbackOSTimer { pTmr->pRmActiveOSTimerEventList = pCurrent->pNext; pEvent->pNext = NULL; + pEvent->bInUse = NV_FALSE; return; } @@ -1076,6 +1081,7 @@ _tmrScanCallbackOSTimer { pCurrent->pNext = pEvent->pNext; pEvent->pNext = NULL; + pEvent->bInUse = NV_FALSE; break; } pCurrent = pCurrent->pNext; @@ -1292,7 +1298,7 @@ _tmrStateLoadCallbacks // if there is a state unload before receiving the OS timer callback. // osGetCurrentTick(&pScan->startTimeNs); - tmrEventScheduleAbsOSTimer_HAL(pTmr, (PTMR_EVENT)pScan, pScan->timens); + tmrEventScheduleRelOSTimer_HAL(pTmr, (PTMR_EVENT)pScan, pScan->timens); pScan = pScan->pNext; } } @@ -1761,6 +1767,7 @@ tmrCtrlCmdEventCreate /*! * Schedules an existing event. Takes in time arguments and a flag to * determine if it should be interpreted as absolute or relative time. + * While using OSTimer, use this api only with relative time. * * @returns NV_STATUS */ @@ -1773,10 +1780,19 @@ tmrCtrlCmdEventSchedule { NV_STATUS rc; OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - PTMR_EVENT pEvent = (PTMR_EVENT)NvP64_VALUE(pParams->pEvent); + TMR_EVENT *pEvent = (PTMR_EVENT)NvP64_VALUE(pParams->pEvent); - if(pParams->bUseTimeAbs) + if (pParams->bUseTimeAbs) { + // + // FIXME: This function is called only from dynamic_power.c file, + // using OSTimer. And OSTimer is always scheduled in relative mode + // + if ((pEvent != NULL) && tmrIsOSTimer(pTmr, pEvent)) + { + NV_ASSERT_FAILED("Attempting to schedule OSTimer with Abs time."); + return NV_ERR_INVALID_ARGUMENT; + } rc = tmrEventScheduleAbs(pTmr, pEvent, pParams->timeNs); } else diff --git a/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c b/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c index f0fa0f449e..86b847b48a 100644 --- a/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c +++ b/src/nvidia/src/kernel/gpu/timer/timer_ostimer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -93,15 +93,15 @@ NV_STATUS tmrEventCreateOSTimer_OSTIMER * * @param[in] pTmr Pointer to Timer Object * @param[in] pEvent pointer to timer event information - * @param[in] absolute time in nano seconds + * @param[in] relative time in nano seconds * * @returns NV_ERR_INVALID_REQUEST failed to create timer */ -NV_STATUS tmrEventScheduleAbsOSTimer_OSTIMER +NV_STATUS tmrEventScheduleRelOSTimer_OSTIMER ( OBJTMR *pTmr, PTMR_EVENT pPublicEvent, - NvU64 timeNs + NvU64 timeRelNs ) { NV_STATUS status= NV_OK; @@ -114,7 +114,7 @@ NV_STATUS tmrEventScheduleAbsOSTimer_OSTIMER return NV_ERR_INVALID_REQUEST; } - status = osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->super.pOSTmrCBdata, timeNs); + status = osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->super.pOSTmrCBdata, timeRelNs); if (status != NV_OK) { diff --git a/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer.c b/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer.c index 92ab2e3c33..2b0b5773f6 100644 --- a/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer.c +++ b/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer.c @@ -30,6 +30,8 @@ #include "gpu/device/device.h" #include "kernel/rmapi/client.h" +#include "alloc/alloc_access_counter_buffer.h" + NV_STATUS accesscntrConstruct_IMPL ( @@ -38,7 +40,7 @@ accesscntrConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - NV_STATUS status; + NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS *pAllocParams = pParams->pAllocParams; OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); @@ -58,17 +60,17 @@ accesscntrConstruct_IMPL NV_ASSERT_OR_RETURN(pUvm != NULL, NV_ERR_NOT_SUPPORTED); - status = uvmInitializeAccessCntrBuffer(pGpu, pUvm); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to initialize UVM Access Counters (status=0x%08x).\n", - status); - return status; - } + pAccessCounterBuffer->accessCounterIndex = (pAllocParams != NULL) ? pAllocParams->accessCounterIndex : 0; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pAccessCounterBuffer->accessCounterIndex < pUvm->accessCounterBufferCount, + NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pUvm->pAccessCounterBuffers[pAccessCounterBuffer->accessCounterIndex].pAccessCounterBuffer == NULL, + NV_ERR_INVALID_STATE); - pUvm->accessCntrBuffer.hAccessCntrBufferClient = pCallContext->pClient->hClient; - pUvm->accessCntrBuffer.hAccessCntrBufferObject = pCallContext->pResourceRef->hResource; + NV_ASSERT_OK_OR_RETURN(uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer)); + pUvm->pAccessCounterBuffers[pAccessCounterBuffer->accessCounterIndex].pAccessCounterBuffer = pAccessCounterBuffer; return NV_OK; } @@ -82,7 +84,11 @@ accesscntrDestruct_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - (void) uvmTerminateAccessCntrBuffer(pGpu, pUvm); + NV_ASSERT(pUvm->pAccessCounterBuffers[pAccessCounterBuffer->accessCounterIndex].pAccessCounterBuffer == pAccessCounterBuffer); + + NV_ASSERT_OK(uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer)); + + pUvm->pAccessCounterBuffers[pAccessCounterBuffer->accessCounterIndex].pAccessCounterBuffer = NULL; } NV_STATUS @@ -96,7 +102,6 @@ accesscntrMap_IMPL { RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); OBJGPU *pGpu; - OBJUVM *pUvm; NV_STATUS rmStatus = NV_OK; NvBool bBroadcast = NV_TRUE; NvBool bKernel; @@ -104,7 +109,6 @@ accesscntrMap_IMPL pGpu = CliGetGpuFromContext(pCpuMapping->pContextRef, &bBroadcast); NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); gpuSetThreadBcState(pGpu, bBroadcast); - pUvm = GPU_GET_UVM(pGpu); rmStatus = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), pCpuMapping->flags, @@ -114,14 +118,13 @@ accesscntrMap_IMPL pCpuMapping->processId = osGetCurrentProcess(); - rmStatus = memdescMap(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc, + rmStatus = memdescMap(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc, 0, - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc->Size, + pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc->Size, bKernel, pCpuMapping->pPrivate->protect, &pCpuMapping->pLinearAddress, &pCpuMapping->pPrivate->pPriv); - pUvm->accessCntrBuffer.hAccessCntrBufferCpuMapping = pCpuMapping->pPrivate->pPriv; return rmStatus; } @@ -137,7 +140,6 @@ accesscntrUnmap_IMPL NV_STATUS rmStatus; RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); OBJGPU *pGpu; - OBJUVM *pUvm; NvBool bBroadcast = NV_TRUE; NvBool bKernel; @@ -145,19 +147,17 @@ accesscntrUnmap_IMPL NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); gpuSetThreadBcState(pGpu, bBroadcast); - pUvm = GPU_GET_UVM(pGpu); - rmStatus = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), pCpuMapping->flags, &bKernel); if (rmStatus != NV_OK) return rmStatus; - memdescUnmap(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc, + memdescUnmap(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc, bKernel, pCpuMapping->processId, pCpuMapping->pLinearAddress, - pUvm->accessCntrBuffer.hAccessCntrBufferCpuMapping); + pCpuMapping->pPrivate->pPriv); return NV_OK; } @@ -173,8 +173,7 @@ accesscntrGetMapAddrSpace_IMPL { NV_ADDRESS_SPACE addrSpace; OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); - OBJUVM *pUvm = GPU_GET_UVM(pGpu); - PMEMORY_DESCRIPTOR pMemDesc = pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc; + PMEMORY_DESCRIPTOR pMemDesc = pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc; if (pMemDesc == NULL) return NV_ERR_INVALID_OBJECT; diff --git a/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c b/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c index af065238f5..b3b8985e2a 100644 --- a/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c +++ b/src/nvidia/src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c @@ -40,7 +40,7 @@ accesscntrCtrlCmdAccessCntrBufferReadGet_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - return uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, &pGetParams->accessCntrBufferGetOffset); + return uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &pGetParams->accessCntrBufferGetOffset); } NV_STATUS @@ -53,7 +53,7 @@ accesscntrCtrlCmdAccessCntrBufferWriteGet_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - return uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, pGetParams->accessCntrBufferGetValue); + return uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, pGetParams->accessCntrBufferGetValue); } NV_STATUS @@ -66,7 +66,7 @@ accesscntrCtrlCmdAccessCntrBufferReadPut_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - return uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, &pGetParams->accessCntrBufferPutOffset); + return uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &pGetParams->accessCntrBufferPutOffset); } NV_STATUS @@ -76,10 +76,7 @@ accesscntrCtrlCmdAccessCntrBufferGetSize_IMPL NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS *pGetParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); - OBJUVM *pUvm = GPU_GET_UVM(pGpu); - - pGetParams->accessCntrBufferSize = pUvm->accessCntrBuffer.accessCntrBufferSize; + pGetParams->accessCntrBufferSize = pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc->Size; return NV_OK; } @@ -114,11 +111,11 @@ accesscntrCtrlCmdAccessCntrBufferEnable_IMPL if (pGetParams->enable) { - return uvmEnableAccessCntr_HAL(pGpu, pUvm, NV_FALSE); + return uvmEnableAccessCntr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, NV_FALSE); } else { - return uvmDisableAccessCntr_HAL(pGpu, pUvm, NV_FALSE); + return uvmDisableAccessCntr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, NV_FALSE); } } @@ -155,13 +152,14 @@ accesscntrCtrlCmdAccessCntrBufferGetRegisterMappings_IMPL OBJUVM *pUvm = GPU_GET_UVM(pGpu); return uvmGetAccessCntrRegisterMappings_HAL(pGpu, pUvm, - &pParams->pAccessCntrBufferGet, - &pParams->pAccessCntrBufferPut, - &pParams->pAccessCntrBufferFull, - &pParams->pHubIntr, - &pParams->pHubIntrEnSet, - &pParams->pHubIntrEnClear, - &pParams->accessCntrMask); + pAccessCounterBuffer->accessCounterIndex, + &pParams->pAccessCntrBufferGet, + &pParams->pAccessCntrBufferPut, + &pParams->pAccessCntrBufferFull, + &pParams->pHubIntr, + &pParams->pHubIntrEnSet, + &pParams->pHubIntrEnClear, + &pParams->accessCntrMask); } NV_STATUS @@ -174,7 +172,7 @@ accesscntrCtrlCmdAccessCntrBufferGetFullInfo_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - return uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, &pParams->fullFlag); + return uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &pParams->fullFlag); } NV_STATUS @@ -187,7 +185,7 @@ accesscntrCtrlCmdAccessCntrBufferResetCounters_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pAccessCounterBuffer); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - NV_STATUS status = uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, pParams->counterType); + NV_STATUS status = uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, pParams->counterType); if (status == NV_OK) { pParams->resetFlag = NV_TRUE; @@ -212,17 +210,20 @@ accesscntrCtrlCmdAccessCntrSetConfig_IMPL NvU32 cmd = pParams->cmd; if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_GRANULARITY) - uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, MIMC, pParams->mimcGranularity); + uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, + MIMC, pParams->mimcGranularity); if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_GRANULARITY) - uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, MOMC, pParams->momcGranularity); + uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, + MOMC, pParams->momcGranularity); if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_MIMC_LIMIT) - uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, + uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT, pParams->mimcLimit); if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_MOMC_LIMIT) - uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, + uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, NVC365_CTRL_ACCESS_COUNTER_MOMC_LIMIT, pParams->momcLimit); if (cmd & NVC365_CTRL_ACCESS_COUNTER_SET_THRESHOLD) - uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, pParams->threshold); + uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, + pParams->threshold); return NV_OK; } @@ -246,6 +247,7 @@ subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL } status = uvmAccessCntrBufferRegister(pGpu, pUvm, + pParams->accessCounterIndex, pParams->bufferSize, pParams->bufferPteArray); return status; @@ -254,41 +256,15 @@ subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL NV_STATUS subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL ( - Subdevice *pSubdevice + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *pParams ) { NV_STATUS status; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); OBJUVM *pUvm = GPU_GET_UVM(pGpu); - status = uvmAccessCntrBufferUnregister(pGpu, pUvm); + status = uvmAccessCntrBufferUnregister(pGpu, pUvm, pParams->accessCounterIndex); return status; } - -NV_STATUS -subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer_IMPL -( - Subdevice *pSubdevice -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - OBJUVM *pUvm = GPU_GET_UVM(pGpu); - - return uvmAccessCntrService_HAL(pGpu, pUvm); -} - -NV_STATUS -subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS *pParams -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - OBJUVM *pUvm = GPU_GET_UVM(pGpu); - - pParams->bufferSize = uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm); - - return NV_OK; -} diff --git a/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c b/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c index faa1dca2be..725f5c4644 100644 --- a/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c +++ b/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c @@ -25,6 +25,7 @@ #include "gpu/gpu.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/uvm/uvm.h" +#include "gpu/uvm/access_cntr_buffer.h" #include "kernel/gpu/intr/intr.h" #include "class/clc365.h" @@ -32,16 +33,100 @@ #include "published/turing/tu102/dev_access_counter.h" #include "published/turing/tu102/dev_vm.h" +NvU32 +uvmGetRegOffsetAccessCntrBufferPut_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferGet_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferHi_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferLo_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferConfig_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferInfo_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO; +} + +NvU32 +uvmGetRegOffsetAccessCntrBufferSize_TU102 +( + OBJUVM *pUvm, + NvU32 accessCounterIndex +) +{ + NV_ASSERT(accessCounterIndex == 0); + + return NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE; +} + NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102 ( OBJGPU *pGpu, OBJUVM *pUvm, - NvU32 *putOffset + NvU32 accessCounterIndex, + NvU32 *pPutOffset ) { - - *putOffset = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT); + *pPutOffset = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferPut_HAL(pUvm, accessCounterIndex)); return NV_OK; } @@ -51,10 +136,11 @@ uvmReadAccessCntrBufferGetPtr_TU102 ( OBJGPU *pGpu, OBJUVM *pUvm, - NvU32 *getOffset + NvU32 accessCounterIndex, + NvU32 *pGetOffset ) { - *getOffset = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET); + *pGetOffset = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex)); return NV_OK; } @@ -64,10 +150,12 @@ uvmWriteAccessCntrBufferGetPtr_TU102 ( OBJGPU *pGpu, OBJUVM *pUvm, - NvU32 getPtrValue + NvU32 accessCounterIndex, + NvU32 getPtrValue ) { - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET, getPtrValue); + GPU_VREG_WR32(pGpu, uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex), getPtrValue); + return NV_OK; } @@ -76,6 +164,7 @@ uvmEnableAccessCntr_TU102 ( OBJGPU *pGpu, OBJUVM *pUvm, + NvU32 accessCounterIndex, NvBool bIsErrorRecovery ) { @@ -97,7 +186,7 @@ uvmEnableAccessCntr_TU102 uvmEnableAccessCntrIntr_HAL(pGpu, pUvm, intr_all); } - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, _TRUE); + uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, NV_TRUE); return NV_OK; } @@ -107,13 +196,14 @@ uvmGetAccessCntrRegisterMappings_TU102 ( OBJGPU *pGpu, OBJUVM *pUvm, + NvU32 accessCounterIndex, NvP64 *pAccessCntrBufferGet, NvP64 *pAccessCntrBufferPut, NvP64 *pAccessCntrBufferFull, NvP64 *pHubIntr, NvP64 *pHubIntrEnSet, NvP64 *pHubIntrEnClear, - NvU32 *accessCntrMask + NvU32 *pAccessCntrMask ) { Intr *pIntr = GPU_GET_INTR(pGpu); @@ -125,13 +215,14 @@ uvmGetAccessCntrRegisterMappings_TU102 leafReg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVector); leafBit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVector); - *pAccessCntrBufferGet = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET)); - *pAccessCntrBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT)); - *pAccessCntrBufferFull = NvP64_PLUS_OFFSET(bar0Mapping,GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO)); + *pAccessCntrBufferGet = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex))); + *pAccessCntrBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, uvmGetRegOffsetAccessCntrBufferPut_HAL(pUvm, accessCounterIndex))); + *pAccessCntrBufferFull = NvP64_PLUS_OFFSET(bar0Mapping,GPU_GET_VREG_OFFSET(pGpu, uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex))); *pHubIntr = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(leafReg))); *pHubIntrEnSet = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(leafReg))); *pHubIntrEnClear = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(leafReg))); - *accessCntrMask = NVBIT(leafBit); + *pAccessCntrMask = NVBIT(leafBit); + return NV_OK; } @@ -140,58 +231,76 @@ uvmReadAccessCntrBufferFullPtr_TU102 ( OBJGPU *pGpu, OBJUVM *pUvm, - NvBool *fullFlag + NvU32 accessCounterIndex, + NvBool *pFullFlag ) { - NvU32 fullPtrValue; + NvU32 info = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex)); + + *pFullFlag = FLD_TEST_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO, _FULL, _TRUE, info); - fullPtrValue = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO); - if (fullPtrValue & NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE) - { - *fullFlag = NV_TRUE; - } - else - { - *fullFlag = NV_FALSE; - } return NV_OK; } NV_STATUS -uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, OBJUVM *pUvm, NvU32 threshold) +uvmAccessCntrSetThreshold_TU102 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 threshold +) { + NvU32 regOffsetConfig = uvmGetRegOffsetAccessCntrBufferConfig_HAL(pUvm, accessCounterIndex); + NvU32 config = GPU_VREG_RD32(pGpu, regOffsetConfig); + + config = FLD_SET_DRF_NUM(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _THRESHOLD, threshold, config); + GPU_VREG_WR32(pGpu, regOffsetConfig, config); - GPU_VREG_FLD_WR_DRF_NUM(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _THRESHOLD, threshold); return NV_OK; } // Note: This function returns zero for chips which do not support the access counter. -NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, OBJUVM *pUvm) +NvU32 +uvmGetAccessCounterBufferSize_TU102 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex +) { - - return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE) * + return GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferSize_HAL(pUvm, accessCounterIndex)) * NV_ACCESS_COUNTER_NOTIFY_BUF_SIZE; } NV_STATUS -uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, OBJUVM *pUvm, ACCESS_CNTR_TYPE accessCntType, NvU32 granularity) +uvmAccessCntrSetGranularity_TU102 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + ACCESS_CNTR_TYPE accessCntType, + NvU32 granularity +) { + NvU32 regOffsetConfig = uvmGetRegOffsetAccessCntrBufferConfig_HAL(pUvm, accessCounterIndex); + NvU32 config = GPU_VREG_RD32(pGpu, regOffsetConfig); if (accessCntType == MIMC) { switch(granularity) { case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _64K); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _64K, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _2M); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _2M, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _16M); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _16M, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _16G); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MIMC_GRANULARITY, _16G, config); break; default: return NV_ERR_INVALID_ARGUMENT; @@ -202,16 +311,16 @@ uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, OBJUVM *pUvm, ACCESS_CNTR_TYPE a switch(granularity) { case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_64K: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _64K); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _64K, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_2M: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _2M); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _2M, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16M: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _16M); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _16M, config); break; case NVC365_CTRL_ACCESS_COUNTER_GRANULARITY_16G: - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _16G); + config = FLD_SET_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_CONFIG, _MOMC_GRANULARITY, _16G, config); break; default: return NV_ERR_INVALID_ARGUMENT; @@ -220,6 +329,8 @@ uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, OBJUVM *pUvm, ACCESS_CNTR_TYPE a else return NV_ERR_INVALID_ARGUMENT; + GPU_VREG_WR32(pGpu, regOffsetConfig, config); + return NV_OK; } @@ -228,11 +339,12 @@ uvmProgramWriteAccessCntrBufferAddress_TU102 ( OBJGPU *pGpu, OBJUVM *pUvm, + NvU32 accessCounterIndex, NvU64 addr ) { - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI, NvU64_HI32(addr)); - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, NvU64_LO32(addr)); + GPU_VREG_WR32(pGpu, uvmGetRegOffsetAccessCntrBufferHi_HAL(pUvm, accessCounterIndex), NvU64_HI32(addr)); + GPU_VREG_WR32(pGpu, uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex), NvU64_LO32(addr)); } void @@ -240,30 +352,41 @@ uvmProgramAccessCntrBufferEnabled_TU102 ( OBJGPU *pGpu, OBJUVM *pUvm, + NvU32 accessCounterIndex, NvBool bEn ) { - GPU_VREG_FLD_WR_DRF_NUM(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, bEn); + NvU32 regOffsetLo = uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex); + NvU32 lo = GPU_VREG_RD32(pGpu, regOffsetLo); + + lo = FLD_SET_DRF_NUM(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, bEn, lo); + GPU_VREG_WR32(pGpu, regOffsetLo, lo); } NvBool uvmIsAccessCntrBufferEnabled_TU102 ( OBJGPU *pGpu, - OBJUVM *pUvm + OBJUVM *pUvm, + NvU32 accessCounterIndex ) { - return (NvBool) GPU_VREG_RD_DRF(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN); + NvU32 lo = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex)); + + return FLD_TEST_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, _TRUE, lo); } NvBool uvmIsAccessCntrBufferPushed_TU102 ( OBJGPU *pGpu, - OBJUVM *pUvm + OBJUVM *pUvm, + NvU32 accessCounterIndex ) { - return GPU_VREG_FLD_TEST_DRF_DEF(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO, _PUSHED, _TRUE); + NvU32 info = GPU_VREG_RD32(pGpu, uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex)); + + return FLD_TEST_DRF(_VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO, _PUSHED, _TRUE, info); } NV_STATUS @@ -306,14 +429,44 @@ uvmAccessCntrService_TU102 OBJUVM *pUvm ) { - NvU64 accessCntrAddress = 0; - PEVENTNOTIFICATION *ppEventNotification = NULL; + NvU32 i; - if (NV_OK == CliGetEventNotificationList(pUvm->accessCntrBuffer.hAccessCntrBufferClient, - pUvm->accessCntrBuffer.hAccessCntrBufferObject, NULL, &ppEventNotification) && ppEventNotification) + for (i = 0; i < pUvm->accessCounterBufferCount; i++) { - NV_ASSERT_OK_OR_RETURN(notifyEvents(pGpu, *ppEventNotification, NVC365_NOTIFIERS_ACCESS_COUNTER, - NvU64_HI32(accessCntrAddress), NvU64_LO32(accessCntrAddress), NV_OK, NV_OS_WRITE_THEN_AWAKEN)); + AccessCounterBuffer *pAccessCounterBuffer = pUvm->pAccessCounterBuffers[i].pAccessCounterBuffer; + EVENTNOTIFICATION **ppEventNotification; + + if (pAccessCounterBuffer == NULL) + continue; + + ppEventNotification = inotifyGetNotificationListPtr(staticCast(pAccessCounterBuffer, INotifier)); + + if (ppEventNotification == NULL) + continue; + + if (pUvm->accessCounterBufferCount > 1) + { + NvU32 get, put; + + NV_ASSERT_OK_OR_RETURN(uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &get)); + NV_ASSERT_OK_OR_RETURN(uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex, &put)); + + // + // We can't know which access counter buffer has the new entries, + // so we send out notifications for each non-empty buffer. + // This can generate extra notifications when interrupts for different counters + // arrive in rapid succession, so client doesn't update get pointer in time. + // + // We could remember the last known put pointer and compare it, but + // theoretically the buffer can wrap around while the interrupt is being handled by client + // + if (get == put) + continue; + } + + NV_ASSERT_OK(notifyEvents(pGpu, *ppEventNotification, NVC365_NOTIFIERS_ACCESS_COUNTER, + 0, 0, NV_OK, NV_OS_WRITE_THEN_AWAKEN)); } + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c b/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c index bcfde68b22..49a569e3e9 100644 --- a/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c +++ b/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c @@ -31,6 +31,7 @@ #include "gpu/gpu.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/uvm/uvm.h" +#include "gpu/uvm/access_cntr_buffer.h" #include "os/os.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" @@ -45,7 +46,8 @@ NV_STATUS uvmSetupAccessCntrBuffer_GV100 ( OBJGPU *pGpu, - OBJUVM *pUvm + OBJUVM *pUvm, + NvU32 accessCounterIndex ) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -59,21 +61,21 @@ uvmSetupAccessCntrBuffer_GV100 return NV_OK; } - if (!pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc) + if (!pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc) { return NV_ERR_INVALID_OBJECT_BUFFER; } - status = kbusMapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc, - &vaddr, pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc->Size, 0, GPU_GFID_PF); + status = kbusMapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc, + &vaddr, pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc->Size, 0, GPU_GFID_PF); if (status != NV_OK) { return status; } - pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr = vaddr; + pUvm->pAccessCounterBuffers[accessCounterIndex].bar2UvmAccessCntrBufferAddr = vaddr; - uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, vaddr); - uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, NV_FALSE); + uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, accessCounterIndex, vaddr); + uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, NV_FALSE); return NV_OK; } @@ -83,6 +85,7 @@ uvmDisableAccessCntr_GV100 ( OBJGPU *pGpu, OBJUVM *pUvm, + NvU32 accessCounterIndex, NvBool bIsErrorRecovery ) { @@ -103,7 +106,7 @@ uvmDisableAccessCntr_GV100 bIsErrorRecovery = NV_TRUE; } - uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, NV_FALSE); + uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, NV_FALSE); // // Check for any pending notifications which might be pending in pipe to ensure @@ -113,9 +116,9 @@ uvmDisableAccessCntr_GV100 // bit to show up for all packets and then reset the buffer // gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - if (!uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm)) + if (!uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex)) { - while (!uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm)) + while (!uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm, accessCounterIndex)) { if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) { @@ -134,13 +137,13 @@ uvmDisableAccessCntr_GV100 goto done; // If PUT pointer is updated, wait for VALID packets to show up and reset the packets - uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, &putPtr); - uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, &getPtr); + uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, accessCounterIndex, &putPtr); + uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, &getPtr); if (getPtr != putPtr) { MEMORY_DESCRIPTOR *pMemDesc = RMCFG_FEATURE_PLATFORM_GSP ? - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc : - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc; + pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc : + pUvm->pAccessCounterBuffers[accessCounterIndex].pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc; NvU8 *pAccessCntrBufferPage; NvU32 entriesPerPage = RM_PAGE_SIZE / NVC365_NOTIFY_BUF_SIZE; NvU32 pageSizeModBufSize = RM_PAGE_SIZE % NVC365_NOTIFY_BUF_SIZE; @@ -186,13 +189,13 @@ uvmDisableAccessCntr_GV100 // Write get progress so far, all entries in [get, put) // are valid or will become valid. - uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, getPtr); + uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, getPtr); return status; } } } - uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, getPtr); + uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, getPtr); memdescUnmap(pMemDesc, NV_TRUE, osGetCurrentProcess(), pAddr, pPriv); } @@ -209,7 +212,12 @@ uvmDisableAccessCntr_GV100 } NV_STATUS -uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) +uvmUnloadAccessCntrBuffer_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex +) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -220,16 +228,21 @@ uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) return NV_OK; } - uvmDisableAccessCntr_HAL(pGpu, pUvm, NV_FALSE); - kbusUnmapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc, - pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr, GPU_GFID_PF); - pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr = 0; + uvmDisableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, NV_FALSE); + kbusUnmapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc, + pUvm->pAccessCounterBuffers[accessCounterIndex].bar2UvmAccessCntrBufferAddr, GPU_GFID_PF); + pUvm->pAccessCounterBuffers[accessCounterIndex].bar2UvmAccessCntrBufferAddr = 0; return NV_OK; } NV_STATUS -uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) +uvmDestroyAccessCntrBuffer_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { if(pUvm == NULL) { @@ -243,19 +256,24 @@ uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) return NV_OK; } - memdescFree(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc); - memdescDestroy(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc); + memdescFree(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc); + memdescDestroy(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc); - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc = NULL; - pUvm->accessCntrBuffer.accessCntrBufferSize = 0; + pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc = NULL; return NV_OK; } NV_STATUS -uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) +uvmInitAccessCntrBuffer_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { NV_STATUS status; + NvU32 accessCntrBufferSize; MEMORY_DESCRIPTOR *pUvmAccessCntrBufferDesc; NvP64 pAddr; NvP64 pPriv; @@ -264,7 +282,6 @@ uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) NvU32 accessCntrBufferAperture = 0; NvU32 accessCntrBufferAttr = 0; - NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS getSizeParams = {0}; // Return if guest RM is with no sriov if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || @@ -273,26 +290,13 @@ uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) return NV_OK; } - // Issue control to fetch buffer size from physical - status = pUvm->pRmApi->Control(pUvm->pRmApi, - pUvm->hClient, - pUvm->hSubdevice, - NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE, - &getSizeParams, - sizeof(getSizeParams)); - if (status != NV_OK) - { - return status; - } - - pUvm->accessCntrBuffer.accessCntrBufferSize = getSizeParams.bufferSize; - + accessCntrBufferSize = uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm, pAccessCounterBuffer->accessCounterIndex); accessCntrBufferAperture = ADDR_SYSMEM; accessCntrBufferAttr = NV_MEMORY_CACHED; memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_4, _UVM_FAULT_BUFFER_REPLAYABLE, pGpu->instLocOverrides4), "UVM access counter", &accessCntrBufferAperture, &accessCntrBufferAttr); - status = memdescCreate(&pUvmAccessCntrBufferDesc, pGpu, pUvm->accessCntrBuffer.accessCntrBufferSize, 0, + status = memdescCreate(&pUvmAccessCntrBufferDesc, pGpu, accessCntrBufferSize, 0, NV_FALSE, accessCntrBufferAperture, accessCntrBufferAttr, MEMDESC_FLAGS_LOST_ON_SUSPEND); if (status != NV_OK) { @@ -333,13 +337,19 @@ uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) memdescUnmap(pUvmAccessCntrBufferDesc, NV_TRUE, osGetCurrentProcess(), pAddr, pPriv); - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc = pUvmAccessCntrBufferDesc; + pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc = pUvmAccessCntrBufferDesc; return status; } NV_STATUS -uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm, NvU32 counterType) +uvmResetAccessCntrBuffer_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 counterType +) { switch(counterType) { @@ -359,7 +369,14 @@ uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm, NvU32 counterType) } NV_STATUS -uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, OBJUVM *pUvm, NvU32 type, NvU32 limit) +uvmAccessCntrSetCounterLimit_GV100 +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 type, + NvU32 limit +) { if (type == NVC365_CTRL_ACCESS_COUNTER_MIMC_LIMIT) { diff --git a/src/nvidia/src/kernel/gpu/uvm/uvm.c b/src/nvidia/src/kernel/gpu/uvm/uvm.c index 40f6e8b197..74ca3b3c3c 100644 --- a/src/nvidia/src/kernel/gpu/uvm/uvm.c +++ b/src/nvidia/src/kernel/gpu/uvm/uvm.c @@ -24,6 +24,8 @@ #include "core/core.h" #include "gpu/gpu.h" #include "gpu/uvm/uvm.h" +#include "gpu/uvm/access_cntr_buffer.h" +#include "gpu/mem_sys/kern_mem_sys.h" #include "nvRmReg.h" #include "rmapi/control.h" #include "rmapi/rmapi_utils.h" @@ -34,12 +36,14 @@ /** * @brief Send the request to set up the buffer to physical RM. - * - * @param pGpu - * @param pUvm */ static NV_STATUS -_uvmSetupAccessCntrBuffer(OBJGPU *pGpu, OBJUVM *pUvm) +_uvmSetupAccessCntrBuffer +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { NvU32 bufferSize; NvU32 numBufferPages; @@ -47,12 +51,12 @@ _uvmSetupAccessCntrBuffer(OBJGPU *pGpu, OBJUVM *pUvm) NV_STATUS status = NV_OK; // Buffer was not allocated, nothing to do - if (pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc == NULL) + if (pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc == NULL) { return NV_OK; } - bufferSize = pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc->Size; + bufferSize = pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc->Size; numBufferPages = NV_ROUNDUP(bufferSize, RM_PAGE_SIZE) / RM_PAGE_SIZE; if (numBufferPages > NV_ARRAY_ELEMENTS(params.bufferPteArray)) @@ -60,11 +64,12 @@ _uvmSetupAccessCntrBuffer(OBJGPU *pGpu, OBJUVM *pUvm) return NV_ERR_BUFFER_TOO_SMALL; } - memdescGetPhysAddrs(pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc, + memdescGetPhysAddrs(pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc, AT_GPU, 0, RM_PAGE_SIZE, numBufferPages, params.bufferPteArray); params.bufferSize = bufferSize; + params.accessCounterIndex = pAccessCounterBuffer->accessCounterIndex; status = pUvm->pRmApi->Control(pUvm->pRmApi, pUvm->hClient, @@ -82,21 +87,29 @@ _uvmSetupAccessCntrBuffer(OBJGPU *pGpu, OBJUVM *pUvm) * @param pUvm */ static NV_STATUS -_uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, OBJUVM *pUvm) +_uvmUnloadAccessCntrBuffer +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { + NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS params = {0}; NV_STATUS status; // Buffer was not allocated, nothing to do - if (pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc == NULL) + if (pAccessCounterBuffer->pUvmAccessCntrAllocMemDesc == NULL) { return NV_OK; } + params.accessCounterIndex = pAccessCounterBuffer->accessCounterIndex; + status = pUvm->pRmApi->Control(pUvm->pRmApi, pUvm->hClient, pUvm->hSubdevice, NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER, - NULL, 0); + ¶ms, sizeof(params)); return status; } @@ -116,6 +129,12 @@ uvmStateInitUnlocked_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) status = rmapiutilAllocClientAndDeviceHandles(pUvm->pRmApi, pGpu, &pUvm->hClient, NULL, &pUvm->hSubdevice); + pUvm->accessCounterBufferCount = 1; + + pUvm->pAccessCounterBuffers = portMemAllocNonPaged(sizeof (*pUvm->pAccessCounterBuffers) * pUvm->accessCounterBufferCount); + NV_ASSERT_OR_RETURN(pUvm->pAccessCounterBuffers != NULL, NV_ERR_NO_MEMORY); + portMemSet(pUvm->pAccessCounterBuffers, 0, sizeof (*pUvm->pAccessCounterBuffers) * pUvm->accessCounterBufferCount); + return status; } @@ -128,6 +147,7 @@ uvmStateInitUnlocked_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) void uvmStateDestroy_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) { + portMemFree(pUvm->pAccessCounterBuffers); rmapiutilFreeClientAndDeviceHandles(pUvm->pRmApi, &pUvm->hClient, NULL, &pUvm->hSubdevice); } @@ -139,20 +159,25 @@ uvmStateDestroy_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) * @param pUvm */ NV_STATUS -uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) +uvmInitializeAccessCntrBuffer_IMPL +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { NV_STATUS status; - status = uvmInitAccessCntrBuffer_HAL(pGpu, pUvm); + status = uvmInitAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer); if (status != NV_OK) { return status; } - status = _uvmSetupAccessCntrBuffer(pGpu, pUvm); + status = _uvmSetupAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer); if (status != NV_OK) { - (void) uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm); + (void) uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer); } return status; @@ -165,11 +190,16 @@ uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) * @param pUvm */ NV_STATUS -uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) +uvmTerminateAccessCntrBuffer_IMPL +( + OBJGPU *pGpu, + OBJUVM *pUvm, + AccessCounterBuffer *pAccessCounterBuffer +) { NV_STATUS status; - status = _uvmUnloadAccessCntrBuffer(pGpu, pUvm); + status = _uvmUnloadAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -177,7 +207,7 @@ uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) status); } - status = uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm); + status = uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -195,8 +225,14 @@ uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) * @param pUvm */ NV_STATUS -uvmAccessCntrBufferRegister_IMPL(OBJGPU *pGpu, OBJUVM *pUvm, - NvU32 bufferSize, NvU64 *pBufferPages) +uvmAccessCntrBufferRegister_IMPL +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex, + NvU32 bufferSize, + NvU64 *pBufferPages +) { NV_STATUS status; MEMORY_DESCRIPTOR *pMemDesc; @@ -221,9 +257,9 @@ uvmAccessCntrBufferRegister_IMPL(OBJGPU *pGpu, OBJUVM *pUvm, NV_ROUNDUP(bufferSize, RM_PAGE_SIZE) / RM_PAGE_SIZE, RM_PAGE_SIZE); - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc = pMemDesc; + pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc = pMemDesc; - status = uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm); + status = uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -232,7 +268,7 @@ uvmAccessCntrBufferRegister_IMPL(OBJGPU *pGpu, OBJUVM *pUvm, memdescDestroy(pMemDesc); - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc = NULL; + pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc = NULL; } return status; @@ -246,11 +282,16 @@ uvmAccessCntrBufferRegister_IMPL(OBJGPU *pGpu, OBJUVM *pUvm, * @param pUvm */ NV_STATUS -uvmAccessCntrBufferUnregister_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) +uvmAccessCntrBufferUnregister_IMPL +( + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU32 accessCounterIndex +) { NV_STATUS status; - status = uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm); + status = uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -258,9 +299,9 @@ uvmAccessCntrBufferUnregister_IMPL(OBJGPU *pGpu, OBJUVM *pUvm) status); } - memdescDestroy(pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc); + memdescDestroy(pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc); - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc = NULL; + pUvm->pAccessCounterBuffers[accessCounterIndex].pUvmAccessCntrMemDesc = NULL; return NV_OK; } @@ -298,11 +339,7 @@ uvmServiceInterrupt_IMPL NV_ASSERT_OR_RETURN(pParams != NULL, 0); NV_ASSERT_OR_RETURN(pParams->engineIdx == MC_ENGINE_IDX_ACCESS_CNTR, 0); - NV_ASSERT_OK(pUvm->pRmApi->Control(pUvm->pRmApi, - pUvm->hClient, - pUvm->hSubdevice, - NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER, - NULL, 0)); + NV_ASSERT_OK(uvmAccessCntrService_HAL(pGpu, pUvm)); return 0; } diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_db.c b/src/nvidia/src/kernel/gpu_mgr/gpu_db.c index 238b9c7c21..bca61ca1f3 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_db.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_db.c @@ -127,7 +127,7 @@ gpudbRegisterGpu(const NvU8 *pUuid, const NBADDR *pUpstreamPortPciInfo, NvU64 pc pNode->upstreamPciPortInfo.bus = pUpstreamPortPciInfo->bus; pNode->upstreamPciPortInfo.device = pUpstreamPortPciInfo->device; pNode->upstreamPciPortInfo.function = pUpstreamPortPciInfo->func; - pNode->upstreamPciPortInfo.bValid = pUpstreamPortPciInfo->valid; + pNode->upstreamPciPortInfo.bValid = pUpstreamPortPciInfo->valid; pNode->bShutdownState = NV_FALSE; diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index 15639c8a35..e795038862 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -35,6 +35,7 @@ #include "nvrm_registry.h" #include "nv_ref.h" #include "nvlimits.h" +#include "nv-firmware-registry.h" #include "kernel/gpu/intr/intr.h" #include "virtualization/hypervisor/hypervisor.h" @@ -42,10 +43,12 @@ #include "published/pcie_switch/pcie_switch_ref.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/conf_compute/conf_compute.h" +#include "gpu/gpu_fabric_probe.h" // local static funcs static void gpumgrSetAttachInfo(OBJGPU *, GPUATTACHARG *); -static void gpumgrGetGpuHalFactor(NvU32 *pChipId0, NvU32 *pChipId1, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg); +static void gpumgrGetGpuHalFactor(NvU32 *pChipId0, NvU32 *pChipId1, NvU32 *pSocChipId0, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg); static NvBool _gpumgrGetPcieP2PCapsFromCache(NvU32 gpuMask, NvU8* pP2PWriteCapsStatus, NvU8* pP2PReadCapsStatus); static void @@ -122,6 +125,60 @@ _gpumgrRegisterRmCapsForGpu(OBJGPU *pGpu) return status; } +static NV_STATUS +_gpumgrDetermineConfComputeCapabilities +( + OBJGPUMGR *pGpuMgr, + OBJGPU *pGpu +) +{ + NvBool bCCFeatureEnabled = NV_FALSE; + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + bCCFeatureEnabled = (pCC != NULL) && + pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED); + + // First GPU + if (ONEBITSET(pGpuMgr->gpuAttachMask)) + { + pGpuMgr->ccCaps.bApmFeatureCapable = NV_FALSE; + pGpuMgr->ccCaps.bHccFeatureCapable = pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE); + pGpuMgr->ccCaps.bCCFeatureEnabled = bCCFeatureEnabled; + pGpuMgr->ccCaps.bDevToolsModeEnabled = gpuIsCCDevToolsModeEnabled(pGpu); + + if (pGpuMgr->ccCaps.bDevToolsModeEnabled) + { + pGpuMgr->ccCaps.bAcceptClientRequest = NV_TRUE; + } + else + { + pGpuMgr->ccCaps.bAcceptClientRequest = NV_FALSE; + } + } + else + { + NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bCCFeatureEnabled == + bCCFeatureEnabled, NV_ERR_INVALID_STATE); + if (pGpuMgr->ccCaps.bCCFeatureEnabled) + { + NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bHccFeatureCapable == + pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE), + NV_ERR_INVALID_STATE); + } + // + // If one of the GPUs is not Hopper CC capable, the system as a whole + // is not Hopper CC capable + // + pGpuMgr->ccCaps.bHccFeatureCapable &= + pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE); + + NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bDevToolsModeEnabled == + gpuIsCCDevToolsModeEnabled(pGpu), + NV_ERR_INVALID_STATE); + } + + return NV_OK; +} + // // ODB functions // @@ -708,6 +765,53 @@ gpumgrGetGpuHalFactorOfVirtual(NvBool *pIsVirtual, GPUATTACHARG *pAttachArg) *pIsVirtual = NV_FALSE; } +NvBool gpumgrGetRmFirmwareLogsEnabled +( + NvU32 enableFirmwareLogsRegVal +) +{ + // Check for logs + if ((enableFirmwareLogsRegVal == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE) +#if defined(DEBUG) || defined(DEVELOP) + || (enableFirmwareLogsRegVal == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG) +#endif // defined(DEBUG) || defined(DEVELOP) + ) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +void gpumgrGetRmFirmwarePolicy +( + NvU32 chipId, + NvU32 pmcBoot42, + NvBool bIsSoc, + NvU32 enableFirmwareRegVal, + NvBool *pbRequestFirmware, + NvBool *pbAllowFallbackToMonolithicRm +) +{ + NvBool bFirmwareCapable = NV_FALSE; + NvBool bEnableByDefault = NV_FALSE; + NvU32 regkeyFirmwareMode; + + regkeyFirmwareMode = + enableFirmwareRegVal & NV_REG_ENABLE_GPU_FIRMWARE_MODE_MASK; + *pbAllowFallbackToMonolithicRm = + !!(enableFirmwareRegVal & NV_REG_ENABLE_GPU_FIRMWARE_POLICY_ALLOW_FALLBACK); + + bFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(chipId, pmcBoot42, + bIsSoc, + &bEnableByDefault); + + *pbRequestFirmware = + (bFirmwareCapable && + ((regkeyFirmwareMode == NV_REG_ENABLE_GPU_FIRMWARE_MODE_ENABLED) || + (bEnableByDefault && (regkeyFirmwareMode != NV_REG_ENABLE_GPU_FIRMWARE_MODE_DISABLED)))); +} + static NvBool _gpumgrIsRmFirmwareCapableChip(NvU32 pmcBoot42) { return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) >= NV_PMC_BOOT_42_ARCHITECTURE_TU100); @@ -739,79 +843,104 @@ NvBool gpumgrIsDeviceRmFirmwareCapable ( NvU16 devId, NvU32 pmcBoot42, + NvBool bIsSoc, NvBool *pbEnabledByDefault ) { - static const NvU16 defaultGspRmGpus[] = { - 0x1E37, // GFN - 0x1E38, // TU102 - 0x1EB4, // T4G - 0x1EB8, // T4 - 0x1EB9, // T4 - - 0x20B0, // A100 - 0x20B1, // A100 - 0x20B2, // A100 - 0x20B3, // A200 - 0x20B5, // A100 80GB - 0x20B6, // A100 - 0x20B7, // A30 - 0x20B8, // A100X SKU230/231 Roy-100 - 0x20B9, // A30X SKU205/206 Roy-30 - 0x20F0, // A100 - 0x20F1, // A100 - 0x20F2, // A100 - 0x2235, // A40 - 0x2236, // A10 SKU215 Pris-24 - 0x2237, // A10G SKU215 Pris-24 - 0x25B6, // A16 - 0x20F5, // A800-80 - 0x20F6, // A800-40 - 0x20FD, // A100T RoyB - - 0x26B5, // L40 - 0x26B8, // L40G - 0x26F5, // L40-CNX - 0x27B7, // L16 - 0x27B8, // L4 (both SKUs) - }; - - *pbEnabledByDefault = NV_FALSE; + NvBool bEnabledByDefault = NV_FALSE; + NvBool bFirmwareCapable = NV_TRUE; - if (!hypervisorIsVgxHyper() && !_gpumgrIsRmFirmwareCapableChip(pmcBoot42)) - return NV_FALSE; - else if (hypervisorIsVgxHyper() && !_gpumgrIsVgxRmFirmwareCapableChip(pmcBoot42)) - return NV_FALSE; + // SoC is treated as always firmware capable and not enabled by default + if (bIsSoc) + goto finish; - if (!hypervisorIsVgxHyper() && _gpumgrIsRmFirmwareDefaultChip(pmcBoot42)) + if (!hypervisorIsVgxHyper() && !_gpumgrIsRmFirmwareCapableChip(pmcBoot42)) { - *pbEnabledByDefault = NV_TRUE; + bFirmwareCapable = NV_FALSE; + goto finish; } - else if (hypervisorIsVgxHyper() && _gpumgrIsVgxRmFirmwareDefaultChip(pmcBoot42)) + else if (hypervisorIsVgxHyper() && !_gpumgrIsVgxRmFirmwareCapableChip(pmcBoot42)) { - *pbEnabledByDefault = NV_TRUE; + bFirmwareCapable = NV_FALSE; + goto finish; } - if (!hypervisorIsVgxHyper() || RMCFG_FEATURE_PLATFORM_GSP) +#if NVCPU_IS_FAMILY_PPC + // Disable default enablement for GSP on PowerPC until it is fully tested + bEnabledByDefault = NV_FALSE; + goto finish; +#else { - for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(defaultGspRmGpus); i++) - { - if (defaultGspRmGpus[i] == devId) + static const NvU16 defaultGspRmGpus[] = { + 0x1E37, // GFN + 0x1E38, // TU102 + 0x1EB4, // T4G + 0x1EB8, // T4 + 0x1EB9, // T4 + + 0x20B0, // A100 + 0x20B1, // A100 + 0x20B2, // A100 + 0x20B3, // A200 + 0x20B5, // A100 80GB + 0x20B6, // A100 + 0x20B7, // A30 + 0x20B8, // A100X SKU230/231 Roy-100 + 0x20B9, // A30X SKU205/206 Roy-30 + 0x20F0, // A100 + 0x20F1, // A100 + 0x20F2, // A100 + 0x2235, // A40 + 0x2236, // A10 SKU215 Pris-24 + 0x2237, // A10G SKU215 Pris-24 + 0x25B6, // A16 + 0x20F5, // A800-80 + 0x20F6, // A800-40 + 0x20FD, // A100T RoyB + + 0x26B5, // L40 + 0x26B8, // L40G + 0x26F5, // L40-CNX + 0x27B7, // L16 + 0x27B8, // L4 (both SKUs) + }; + + if (hypervisorIsVgxHyper() && _gpumgrIsVgxRmFirmwareDefaultChip(pmcBoot42)) + { + bEnabledByDefault = NV_TRUE; + } + else if (!hypervisorIsVgxHyper() && _gpumgrIsRmFirmwareDefaultChip(pmcBoot42)) + { + bEnabledByDefault = NV_TRUE; + } + else if (!hypervisorIsVgxHyper() || RMCFG_FEATURE_PLATFORM_GSP) + { + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(defaultGspRmGpus); i++) { - *pbEnabledByDefault = NV_TRUE; - break; + if (defaultGspRmGpus[i] == devId) + { + bEnabledByDefault = NV_TRUE; + break; + } } } } +#endif - if (*pbEnabledByDefault) +finish: + if (pbEnabledByDefault != NULL) { - NV_PRINTF(LEVEL_INFO, - "DevId 0x%x is GSP-RM enabled by default\n", - devId); + *pbEnabledByDefault = bEnabledByDefault; + + if (bEnabledByDefault) + { + NV_PRINTF(LEVEL_INFO, + "DevId 0x%x is GSP-RM enabled by default\n", + devId); + } } - return NV_TRUE; + return bFirmwareCapable; } static NvBool gpumgrCheckRmFirmwarePolicy @@ -846,6 +975,7 @@ gpumgrGetGpuHalFactor ( NvU32 *pChipId0, NvU32 *pChipId1, + NvU32 *pSocChipId0, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg ) @@ -853,17 +983,21 @@ gpumgrGetGpuHalFactor NvBool isVirtual; NvBool isFwClient; - DEVICE_MAPPING gpuDevMapping = {0}; - gpuDevMapping.gpuNvAddr = pAttachArg->regBaseAddr; - gpuDevMapping.gpuNvLength = pAttachArg->regLength; - // get ChipId0 and ChipId1 if (pAttachArg->socDeviceArgs.specified) { - // This path is taken for T234D+ devices. - *pChipId0 = pAttachArg->socDeviceArgs.socChipId0; + + // iGPU has a PMC_BOOT_0, Display does not + if (pAttachArg->socDeviceArgs.bIsIGPU) + { + DEVICE_MAPPING *pGpuDevMapping = NULL; + pGpuDevMapping = &pAttachArg->socDeviceArgs.deviceMapping[DEVICE_INDEX_GPU]; + *pChipId0 = osDevReadReg032(/*pGpu=*/ NULL, pGpuDevMapping, NV_PMC_BOOT_0); + } + *pChipId1 = 0; + *pSocChipId0 = pAttachArg->socDeviceArgs.socChipId0; isVirtual = NV_FALSE; } else if (pAttachArg->bIsSOC) @@ -872,16 +1006,22 @@ gpumgrGetGpuHalFactor *pChipId0 = pAttachArg->socChipId0; *pChipId1 = 0; + *pSocChipId0 = pAttachArg->socChipId0; isVirtual = NV_FALSE; } else { + DEVICE_MAPPING gpuDevMapping = {0}; + gpuDevMapping.gpuNvAddr = pAttachArg->regBaseAddr; + gpuDevMapping.gpuNvLength = pAttachArg->regLength; + // // PMC_BOOT_42 register is added above G94+ chips which is internal to NVIDIA // Earlier we used PMC_BOOT_0 as Internal ID which is now exposed to customers // *pChipId0 = osDevReadReg032(/*pGpu=*/ NULL, &gpuDevMapping, NV_PMC_BOOT_0); *pChipId1 = osDevReadReg032(/*pGpu=*/ NULL, &gpuDevMapping, NV_PMC_BOOT_42); + *pSocChipId0 = 0; gpumgrGetGpuHalFactorOfVirtual(&isVirtual, pAttachArg); } @@ -918,12 +1058,13 @@ _gpumgrCreateGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) RM_RUNTIME_VARIANT rmVariant; NvU32 chipId0; // 32-bit chipId (pmcBoot0 on GPU) NvU32 chipId1; // 32-bit chipId (pmcBoot42 on GPU) + NvU32 socChipId0; // 32-bit SOC chipId NvU32 hidrev, majorRev; - gpumgrGetGpuHalFactor(&chipId0, &chipId1, &rmVariant, pAttachArg); + gpumgrGetGpuHalFactor(&chipId0, &chipId1, &socChipId0, &rmVariant, pAttachArg); - hidrev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _CHIPID, chipId0); - majorRev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _MAJORREV, chipId0); + hidrev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _CHIPID, socChipId0); + majorRev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _MAJORREV, socChipId0); // WAR: The majorrev of t234 shows 0xa on fmodel instead of 0x4 if ((hidrev == 0x23) && (majorRev == 0xa)) @@ -947,7 +1088,7 @@ _gpumgrCreateGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) } // legacy chip-config Hal registration path - status = gpuBindHalLegacy(pGpu, chipId0, chipId1); + status = gpuBindHalLegacy(pGpu, chipId0, chipId1, socChipId0); if (status != NV_OK) { objDelete(pGpu); @@ -1065,6 +1206,9 @@ gpumgrAttachGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) // Add entry into system partition topo array gpumgrAddSystemMIGInstanceTopo(pAttachArg->nvDomainBusDeviceFunc); + // Determine conf compute params + NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineConfComputeCapabilities(pGpuMgr, pGpu)); + if (!IS_GSP_CLIENT(pGpu)) pGpuMgr->gpuMonolithicRmMask |= NVBIT(gpuInstance); @@ -1335,7 +1479,7 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) { NvU32 idx; NvU32 maxIdx; - // This path is taken for T234D+ SOC devices. + // This path is taken for Tegra Display and iGPU // // TODO: This existing field is specifically used to safeguard @@ -1373,7 +1517,7 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) pGpu->idInfo.PCIDeviceID = pAttachArg->socId; pGpu->idInfo.PCISubDeviceID = pAttachArg->socSubId; pGpu->busInfo.iovaspaceId = pAttachArg->iovaspaceId; - if (RMCFG_FEATURE_PLATFORM_MODS || RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_MODS) { NV_ASSERT(sizeof(pGpu->deviceMappings) == sizeof(pAttachArg->socDeviceMappings)); portMemCopy(pGpu->deviceMappings, sizeof(pGpu->deviceMappings), pAttachArg->socDeviceMappings, sizeof(pGpu->deviceMappings)); @@ -1941,7 +2085,28 @@ gpumgrGetGpuIdInfoV2(NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS *pGpuInfo) { pGpuInfo->gpuFlags |= DRF_NUM(0000, _CTRL_GPU_ID_INFO, _ATS_ENABLED, NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE); - pGpuInfo->numaId = pGpu->numaNodeId; + + if (gpuIsSelfHosted(pGpu) && IS_MIG_IN_USE(pGpu)) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + NvU32 swizzId; + + if (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pRmCtrlParams->hClient, &ref) == NV_OK) + { + swizzId = ref.pKernelMIGGpuInstance->swizzId; + if (GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->memPartitionNumaInfo[swizzId].bInUse) + { + pGpuInfo->numaId = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->memPartitionNumaInfo[swizzId].numaNodeId; + } + } + } + else + { + pGpuInfo->numaId = pGpu->numaNodeId; + } } // is this gpu in use? @@ -1999,20 +2164,6 @@ gpumgrGetGpuIdInfo(NV0000_CTRL_GPU_GET_ID_INFO_PARAMS *pGpuInfo) pGpuInfo->gpuInstance = pGpuInfoV2.gpuInstance; pGpuInfo->numaId = pGpuInfoV2.numaId; - // If we get a non-NULL szName parameter, let os-dependent code - // fill it in from information we already have. - if (NvP64_VALUE(pGpuInfo->szName) != NULL) - { - status = osDeviceClassToDeviceName(pGpuInfo->deviceInstance, - NvP64_VALUE(pGpuInfo->szName)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "gpumgrGetGpuInfo: deviceInstance to szName translation failed\n"); - return status; - } - } - return status; } @@ -2255,7 +2406,7 @@ gpumgrServiceInterrupts_IMPL(NvU32 gpuMask, MC_ENGINE_BITVECTOR *engineMask, NvB if (gpuIsGpuFullPower(pGpu)) { Intr *pIntr = GPU_GET_INTR(pGpu); - + // // On SLI, one OBJGPU's StateInit functions could attempt to service // interrupts on another OBJGPU which has not yet started StateInit. @@ -2263,7 +2414,7 @@ gpumgrServiceInterrupts_IMPL(NvU32 gpuMask, MC_ENGINE_BITVECTOR *engineMask, NvB // intrStateInit. To avoid calling in too early, check that the // interrupt table is initialized. // - if (pIntr->pIntrTable == NULL) + if (vectIsEmpty(&pIntr->intrTable)) { continue; } @@ -3145,21 +3296,9 @@ gpumgrSetGpuNvlinkBwModeFromRegistry_IMPL NV_PRINTF(LEVEL_INFO, "nvlinkBwMode=%d\n", pGpuMgr->nvlinkBwMode); } -/*! - * @brief Set nvlink bandwidth mode - * - * @param[in] mode nvlink bandwidth mode - * - * @return NV_OK on success, appropriate error on failure. - */ -NV_STATUS -gpumgrSetGpuNvlinkBwMode_IMPL -( - NvU8 mode -) +static NvBool +_gpumgrIsP2PObjectPresent(void) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); NvU32 attachedGpuCount; NvU32 attachedGpuMask; KernelBus *pKernelBus; @@ -3170,26 +3309,62 @@ gpumgrSetGpuNvlinkBwMode_IMPL rmStatus = gpumgrGetGpuAttachInfo(&attachedGpuCount, &attachedGpuMask); if (rmStatus != NV_OK) { - return rmStatus; + return NV_FALSE; } gpuIndex = 0; for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); - pGpu != NULL; - pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) { pKernelBus = GPU_GET_KERNEL_BUS(pGpu); if (pKernelBus->totalP2pObjectsAliveRefCount > 0) { - return NV_ERR_IN_USE; + return NV_TRUE; } } + return NV_FALSE; +} + +/*! + * @brief Set nvlink bandwidth mode + * + * @param[in] mode nvlink bandwidth mode + * + * @return NV_OK on success, appropriate error on failure. + */ +NV_STATUS +gpumgrSetGpuNvlinkBwMode_IMPL +( + NvU8 mode +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NV_STATUS status; + + if (mode == pGpuMgr->nvlinkBwMode) + { + return NV_OK; + } + + if (_gpumgrIsP2PObjectPresent()) + { + return NV_ERR_IN_USE; + } + if (mode > GPU_NVLINK_BW_MODE_3QUARTER) { return NV_ERR_INVALID_ARGUMENT; } + status = gpuFabricProbeSetBwMode(mode); + if (status != NV_OK) + { + return status; + } + pGpuMgr->nvlinkBwMode = mode; return NV_OK; } @@ -3223,7 +3398,7 @@ gpumgrAddSystemMIGInstanceTopo_IMPL { pGpuMgr->MIGTopologyInfo[i].bValid = NV_TRUE; pGpuMgr->MIGTopologyInfo[i].domainBusDevice = domainBusDevice; - + // Set MIG enablement to disabled by default pGpuMgr->MIGTopologyInfo[i].bMIGEnabled = NV_FALSE; break; @@ -3325,9 +3500,9 @@ gpumgrIsSystemMIGEnabled_IMPL * @returns NV_TRUE if entry found * NV_FALSE otherwise */ -void +void gpumgrSetSystemMIGEnabled_IMPL -( +( NvU64 domainBusDevice, NvBool bMIGEnabled ) @@ -3443,7 +3618,7 @@ gpumgrGetGpuBridgeType(void) { OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); - + return pGpuMgr->gpuBridgeType; } @@ -3465,7 +3640,7 @@ gpumgrInitPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) /** * @brief Destroy the PCIE P2P info cache */ -void +void gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) { PCIEP2PCAPSINFO *pPcieCapsInfo, *pPcieCapsInfoNext; @@ -3492,7 +3667,7 @@ gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) * @param[in] gpuMask NvU32 value * @param[in] p2pWriteCapsStatus NvU8 value * @param[in] pP2PReadCapsStatus NvU8 value - * + * * @return NV_OK or NV_ERR_NO_MEMORY */ NV_STATUS @@ -3642,7 +3817,7 @@ gpumgrGetPcieP2PCapsFromCache_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); NvBool bFound; - + portSyncMutexAcquire(pGpuMgr->pcieP2PCapsInfoLock); bFound = _gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapsStatus, pP2PReadCapsStatus); diff --git a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c index 8b3297d461..e163a0fc67 100644 --- a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c +++ b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -71,6 +71,13 @@ ctxBufPoolIsSupported return NV_FALSE; } + // TODO remove when bug ID 3922001 for ap_sim_compute_uvm test case resolved + if (!IS_SILICON(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Ctx buffers not supported on simulation/emulation\n"); + return NV_FALSE; + } + if (IS_VIRTUAL(pGpu) || RMCFG_FEATURE_PLATFORM_GSP) { NV_PRINTF(LEVEL_INFO, "Guest RM/GSP don't support ctx buffers in PMA\n"); @@ -155,6 +162,11 @@ ctxBufPoolInit poolConfig), cleanup); + // Allocate the pool in CPR in case of Confidential Compute + if (gpuIsCCFeatureEnabled(pGpu)) + { + rmMemPoolAllocateProtectedMemory(pCtxBufPool->pMemPool[i], NV_TRUE); + } } NV_PRINTF(LEVEL_INFO, "Ctx buf pool successfully initialized\n"); @@ -489,17 +501,16 @@ ctxBufPoolFree if (rmMemPoolIsScrubSkipped(pPool)) { OBJGPU *pGpu = pMemDesc->pGpu; - NvU8 *pMem = kbusMapRmAperture_HAL(pGpu, pMemDesc); - if (pMem == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Failed to BAR2 map memdesc. memory won't be scrubbed\n"); - NV_ASSERT(pMem != NULL); - } - else - { - portMemSet(pMem, 0, (pMemDesc->PageCount * RM_PAGE_SIZE)); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMem, NV_TRUE); - } + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + + surf.pMemDesc = pMemDesc; + surf.offset = 0; + + NV_ASSERT_OK_OR_RETURN( + memmgrMemSet(pMemoryManager, &surf, 0, + pMemDesc->PageCount * RM_PAGE_SIZE, + TRANSFER_FLAGS_NONE)); } rmMemPoolFree(pPool, (RM_POOL_ALLOC_MEMDESC*)pMemDesc, 0); diff --git a/src/nvidia/src/kernel/mem_mgr/egm_mem.c b/src/nvidia/src/kernel/mem_mgr/egm_mem.c new file mode 100644 index 0000000000..b0342665cb --- /dev/null +++ b/src/nvidia/src/kernel/mem_mgr/egm_mem.c @@ -0,0 +1,364 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "mem_mgr/egm_mem.h" + +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/mem_utils.h" +#include "os/os.h" +#include "deprecated/rmapi_deprecated.h" +#include "vgpu/rpc.h" + +#include "class/cl0042.h" // NV_MEMORY_EXTENDED_USER + +NV_STATUS +egmmemConstruct_IMPL +( + ExtendedGpuMemory *pExtendedGpuMemory, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + Memory *pMemory = staticCast(pExtendedGpuMemory, Memory); + OBJGPU *pGpu = pMemory->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvHandle hClient = pCallContext->pClient->hClient; + NvHandle hParent = pCallContext->pResourceRef->pParentRef->hResource; + NV_MEMORY_ALLOCATION_PARAMS *pAllocData = pParams->pAllocParams; + MEMORY_ALLOCATION_REQUEST allocRequest = {0}; + MEMORY_ALLOCATION_REQUEST *pAllocRequest = &allocRequest; + RsResourceRef *pResourceRef = pCallContext->pResourceRef; + NV_STATUS rmStatus = NV_OK; + FB_ALLOC_INFO *pFbAllocInfo = NULL; + FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; + MEMORY_DESCRIPTOR *pMemDesc; + HWRESOURCE_INFO hwResource; + NvU64 sizeOut; + NvU64 offsetOut; + NvU32 flags; + NvU32 gpuCacheAttrib; + NvU32 Cache; + + // Copy-construction has already been done by the base Memory class + if (RS_IS_COPY_CTOR(pParams)) + return NV_OK; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, egmmemValidateParams(pGpu, hClient, pAllocData)); + + // + // For non self-hosted case, we mimic vidmem as EGM and is only used for + // ARCH/MODS verification + // + if (!gpuIsSelfHosted(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + stdmemDumpInputAllocParams(pAllocData, pCallContext); + + NV_PRINTF(LEVEL_ERROR, "EGM Allocation requested\n"); + + pAllocRequest->classNum = NV_MEMORY_EXTENDED_USER; + pAllocRequest->pUserParams = pAllocData; + pAllocRequest->hMemory = pResourceRef->hResource; + pAllocRequest->hClient = hClient; + pAllocRequest->hParent = hParent; + pAllocRequest->pGpu = pGpu; + pAllocRequest->internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC; + pAllocRequest->pHwResource = &hwResource; + + // Unsure if we need to keep separate copies, but keeping old behavior for now. + sizeOut = pAllocData->size; + offsetOut = pAllocData->offset; + + // Allocate and initialize FB_ALLOC_INFO + pFbAllocInfo = portMemAllocNonPaged(sizeof(FB_ALLOC_INFO)); + NV_ASSERT_TRUE_OR_GOTO(rmStatus, pFbAllocInfo != NULL, NV_ERR_NO_MEMORY, free_params_and_return); + + pFbAllocPageFormat = portMemAllocNonPaged(sizeof(FB_ALLOC_PAGE_FORMAT)); + NV_ASSERT_TRUE_OR_GOTO(rmStatus, pFbAllocPageFormat != NULL, NV_ERR_NO_MEMORY, free_params_and_return); + + portMemSet(pFbAllocInfo, 0, sizeof(FB_ALLOC_INFO)); + portMemSet(pFbAllocPageFormat, 0, sizeof(FB_ALLOC_PAGE_FORMAT)); + pFbAllocInfo->pageFormat = pFbAllocPageFormat; + + memUtilsInitFBAllocInfo(pAllocRequest->pUserParams, pFbAllocInfo, + pAllocRequest->hClient, pAllocRequest->hParent); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + memmgrAllocResources(pGpu, pMemoryManager, pAllocRequest, pFbAllocInfo), + free_params_and_return); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + egmmemAllocResources(pGpu, pMemoryManager, pAllocRequest, pFbAllocInfo), + free_params_and_return); + + NV_ASSERT(pAllocRequest->pMemDesc); + pMemDesc = pAllocRequest->pMemDesc; + + offsetOut = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + sizeOut = pMemDesc->Size; + pAllocData->limit = sizeOut - 1; + + if (FLD_TEST_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _DEFAULT, pAllocData->attr2)) + { + pAllocData->attr2 = FLD_SET_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _NO, + pAllocData->attr2); + } + + if (FLD_TEST_DRF(OS32, _ATTR2, _GPU_CACHEABLE, _YES, pAllocData->attr2)) + { + gpuCacheAttrib = NV_MEMORY_CACHED; + } + else + { + gpuCacheAttrib = NV_MEMORY_UNCACHED; + } + + if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _UNCACHED, pAllocData->attr)) + Cache = NV_MEMORY_UNCACHED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _CACHED, pAllocData->attr)) + Cache = NV_MEMORY_CACHED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _WRITE_COMBINE, pAllocData->attr)) + Cache = NV_MEMORY_WRITECOMBINED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _WRITE_THROUGH, pAllocData->attr)) + Cache = NV_MEMORY_CACHED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _WRITE_PROTECT, pAllocData->attr)) + Cache = NV_MEMORY_CACHED; + else if (FLD_TEST_DRF(OS32, _ATTR, _COHERENCY, _WRITE_BACK, pAllocData->attr)) + Cache = NV_MEMORY_CACHED; + else + Cache = 0; + + ct_assert(NVOS32_ATTR_COHERENCY_UNCACHED == NVOS02_FLAGS_COHERENCY_UNCACHED); + ct_assert(NVOS32_ATTR_COHERENCY_CACHED == NVOS02_FLAGS_COHERENCY_CACHED); + ct_assert(NVOS32_ATTR_COHERENCY_WRITE_COMBINE == NVOS02_FLAGS_COHERENCY_WRITE_COMBINE); + ct_assert(NVOS32_ATTR_COHERENCY_WRITE_THROUGH == NVOS02_FLAGS_COHERENCY_WRITE_THROUGH); + ct_assert(NVOS32_ATTR_COHERENCY_WRITE_PROTECT == NVOS02_FLAGS_COHERENCY_WRITE_PROTECT); + ct_assert(NVOS32_ATTR_COHERENCY_WRITE_BACK == NVOS02_FLAGS_COHERENCY_WRITE_BACK); + + flags = DRF_DEF(OS02, _FLAGS, _LOCATION, _PCI) | + DRF_DEF(OS02, _FLAGS, _MAPPING, _NO_MAP) | + DRF_NUM(OS02, _FLAGS, _COHERENCY, DRF_VAL(OS32, _ATTR, _COHERENCY, pAllocData->attr)); + + NV_ASSERT(memdescGetAddressSpace(pMemDesc) == ADDR_EGM); + memdescSetCpuCacheAttrib(pMemDesc, Cache); + + if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_FALSE); + + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT, NV_TRUE); + + memdescSetGpuCacheAttrib(pMemDesc, gpuCacheAttrib); + + NV_ASSERT_OK_OR_GOTO(rmStatus, memdescAlloc(pMemDesc), mem_construct_failed); + + NV_ASSERT_OK_OR_GOTO(rmStatus, memConstructCommon(pMemory, + pAllocRequest->classNum, + flags, pMemDesc, 0, + NULL, pAllocData->attr, + pAllocData->attr2, 0, 0, + pAllocData->tag, &hwResource), + mem_construct_failed); + if (IS_VIRTUAL(pGpu)) + { + NvU32 os02Flags; + NvU32 os32Flags = pAllocData->flags; + + // + // Calculate os02flags as VGPU plugin allocates sysmem with legacy + // RmAllocMemory API + // + NV_ASSERT_OK_OR_GOTO(rmStatus, RmDeprecatedConvertOs32ToOs02Flags(pAllocData->attr, + pAllocData->attr2, + os32Flags, + &os02Flags), + convert_flags_failed); + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to do the hardware update. + // + NV_RM_RPC_ALLOC_MEMORY(pGpu, + hClient, + hParent, + pAllocRequest->hMemory, + pAllocRequest->classNum, + os02Flags, + pMemDesc, + rmStatus); + pMemory->bRpcAlloc = NV_TRUE; + } + + pAllocData->size = sizeOut; + pAllocData->offset = offsetOut; + + stdmemDumpOutputAllocParams(pAllocData); + + goto free_params_and_return; + +convert_flags_failed: + memDestructCommon(pMemory); + +mem_construct_failed: + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + +free_params_and_return: + portMemFree(pFbAllocPageFormat); + portMemFree(pFbAllocInfo); + + return rmStatus; +} + +NV_STATUS +egmmemValidateParams +( + OBJGPU *pGpu, + NvHandle hClient, + NV_MEMORY_ALLOCATION_PARAMS *pAllocData +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, stdmemValidateParams(pGpu, hClient, pAllocData)); + + // Make sure EGM memory is not requested if local EGM is not supported + if (!memmgrIsLocalEgmEnabled(pMemoryManager)) + { + NV_PRINTF(LEVEL_ERROR, + "Allocation requested from EGM when local EGM is not supported\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + // For Self-Hosted platforms which support EGM, EGM pool is the same as sysmem pool + // Make sure _USE_EGM attribute is set only for sysmem allocations for SHH + if (gpuIsSelfHosted(pGpu)) + { + if (!FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _PCI, pAllocData->attr)) + { + NV_PRINTF(LEVEL_ERROR, + "NVOS32_ATTR2_USE_EGM can be set to true only when NVOS32_ATTR_LOCATION_PCI is set for SHH\n"); + return NV_ERR_INVALID_ARGUMENT; + } + } + else + { + // Make sure _USE_EGM attribute is set only for NVOS32_ATTR_LOCATION_VIDMEM for non-SHH platforms + if (!FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _VIDMEM, pAllocData->attr)) + { + NV_PRINTF(LEVEL_ERROR, + "NVOS32_ATTR2_USE_EGM can be set to true only when NVOS32_ATTR_LOCATION_VIDMEM is set\n"); + return NV_ERR_INVALID_ARGUMENT; + } + } + + return NV_OK; +} + +NV_STATUS +egmmemAllocResources +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + MEMORY_ALLOCATION_REQUEST *pAllocRequest, + FB_ALLOC_INFO *pFbAllocInfo +) +{ + NV_STATUS status = NV_OK; + NV_MEMORY_ALLOCATION_PARAMS *pVidHeapAlloc = pAllocRequest->pUserParams; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvBool bAllocedMemDesc = NV_FALSE; + NvBool bContig = FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, + _CONTIGUOUS, pVidHeapAlloc->attr); + + // + // Check for virtual-only parameters used on physical allocs. + // + if (pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY) + { + NV_PRINTF(LEVEL_ERROR, + "Virtual-only flag used with physical allocation\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + if (FLD_TEST_DRF(OS32, _ATTR2, _32BIT_POINTER, _ENABLE, pVidHeapAlloc->attr2)) + { + NV_PRINTF(LEVEL_ERROR, + "Virtual-only 32-bit pointer attr used with physical allocation\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + if (pVidHeapAlloc->hVASpace != 0) + { + NV_PRINTF(LEVEL_ERROR, + "VA space handle used with physical allocation\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + + NV_ASSERT(!(pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_WPR1) && !(pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_WPR2)); + + if (pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) + { + NV_PRINTF(LEVEL_ERROR, + "Expected fixed address allocation\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, memUtilsAllocMemDesc(pGpu, pAllocRequest, pFbAllocInfo, &pMemDesc, NULL, + ADDR_EGM, bContig, &bAllocedMemDesc), failed); + + // get possibly updated surface attributes + pVidHeapAlloc->attr = pFbAllocInfo->retAttr; + pVidHeapAlloc->attr2 = pFbAllocInfo->retAttr2; + + pVidHeapAlloc->offset = pFbAllocInfo->offset; + + if (pAllocRequest->pHwResource != NULL) + { + pAllocRequest->pHwResource->attr = pFbAllocInfo->retAttr; + pAllocRequest->pHwResource->attr2 = pFbAllocInfo->retAttr2; + pAllocRequest->pHwResource->hwResId = pFbAllocInfo->hwResId; + pAllocRequest->pHwResource->comprCovg = pFbAllocInfo->comprCovg; + pAllocRequest->pHwResource->ctagOffset = pFbAllocInfo->ctagOffset; + pAllocRequest->pHwResource->hwResId = pFbAllocInfo->hwResId; + } + + return NV_OK; + +failed: + memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); + + if (bAllocedMemDesc) + { + memdescDestroy(pAllocRequest->pMemDesc); + pAllocRequest->pMemDesc = NULL; + } + + return status; +} diff --git a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c index f2284b8c17..8d96ae9d45 100644 --- a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c @@ -148,7 +148,7 @@ _fabricvaspaceBindInstBlk } // -// TODO: To be removed when legacy FLA VAS (pKernelBus->flaInfo.pFlaVAS) is removed" +// TODO: To be removed when legacy FLA VAS (pKernelBus->flaInfo.pFlaVAS)is removed" // The instance block is unbind during kbusDestroyFla_HAL(). However, we unbind // it here and bind back the instance block for the legacy FLA VAS after the // last NV_FABRIC_MEMORY allocation is freed. @@ -185,12 +185,15 @@ _fabricvaspaceUnbindInstBlk if (pKernelBus->flaInfo.pFlaVAS != NULL) { // Instantiate the instance block for FLA vaspace. - NV_ASSERT(kgmmuInstBlkInit(pKernelGmmu, pKernelBus->flaInfo.pInstblkMemDesc, - pKernelBus->flaInfo.pFlaVAS, FIFO_PDB_IDX_BASE, - &instblkParams) == NV_OK); + NV_ASSERT(kgmmuInstBlkInit(pKernelGmmu, + pKernelBus->flaInfo.pInstblkMemDesc, + pKernelBus->flaInfo.pFlaVAS, + FIFO_PDB_IDX_BASE, + &instblkParams) == NV_OK); // Bind the instance block for FLA vaspace. - NV_ASSERT(kbusSetupBindFla_HAL(pGpu, pKernelBus, pFabricVAS->gfid) == NV_OK); + NV_ASSERT(kbusSetupBindFla_HAL(pGpu, pKernelBus, + pFabricVAS->gfid) == NV_OK); } } @@ -227,7 +230,7 @@ fabricvaspaceConstruct__IMPL status = pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_NULL_OBJECT, - NV01_ROOT, &hClient); + NV01_ROOT, &hClient, sizeof(hClient)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed creating client, status=0x%x\n", status); @@ -237,14 +240,16 @@ fabricvaspaceConstruct__IMPL status = serverutilGenResourceHandle(hClient, &hDevice); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed creating device handle, status=0x%x\n", status); + NV_PRINTF(LEVEL_ERROR, + "failed creating device handle, status=0x%x\n", status); goto cleanup; } // Allocate a device handle devAllocParams.deviceId = gpuGetDeviceInstance(pGpu); status = pRmApi->AllocWithHandle(pRmApi, hClient, hClient, hDevice, - NV01_DEVICE_0, &devAllocParams); + NV01_DEVICE_0, + &devAllocParams, sizeof(devAllocParams)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed creating device, status=0x%x\n", status); @@ -263,7 +268,8 @@ fabricvaspaceConstruct__IMPL pFabricVAS->flags |= VASPACE_FLAGS_ALLOW_PAGES_IN_PHYS_MEM_SUBALLOCATOR; } - pFabricVAS->bRpcAlloc = IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu); + pFabricVAS->bRpcAlloc = IS_VIRTUAL(pGpu) && + gpuIsWarBug200577889SriovHeavyEnabled(pGpu); // Create the GVASPACE object associated with this fabric vaspace. status = vmmCreateVaspace(pVmm, FERMI_VASPACE_A, 0, pVAS->gpuMask, @@ -333,56 +339,11 @@ fabricvaspaceAlloc_IMPL NvU64 *pAddr ) { - NV_STATUS status = NV_OK; - - // Sanity check the input parameters. - NV_ASSERT_OR_RETURN(pFabricVAS->pGVAS != NULL, NV_ERR_OBJECT_NOT_FOUND); - NV_ASSERT_OR_RETURN(pAddr != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pageSize >= RM_PAGE_SIZE_HUGE, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(align != 0, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(size != 0, NV_ERR_INVALID_ARGUMENT); - - // Check the alignment and size are pageSize aligned - NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(align, pageSize), NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(size, pageSize), NV_ERR_INVALID_ARGUMENT); - - status = _fabricvaspaceBindInstBlk(pFabricVAS); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to bind instance block for fabric vaspace." - " Alloc failed\n"); - return status; - } - - // Adjust rangeLo and rangeHi - rangeLo = NV_ALIGN_DOWN(rangeLo, pageSize); - rangeHi = NV_ALIGN_UP(rangeHi, pageSize); - // - // Allocate VA space of the size and alignment requested. - // RM_PAGE_SIZE_HUGE is passed since FLA->PA page size is 2MB or 512MB. + // TODO: If needed, can call into fabricvaspaceAllocNonContiguous_IMPL() + // by forcing contig flag. // - status = vaspaceAlloc(pFabricVAS->pGVAS, size, align, rangeLo, rangeHi, - RM_PAGE_SIZE_HUGE | RM_PAGE_SHIFT_512M, flags, pAddr); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to allocate vaspace\n"); - goto failed; - } - - // Assert that the address returned is pageSize aligned - NV_ASSERT(NV_IS_ALIGNED64(*pAddr, pageSize)); - - pFabricVAS->ucFabricFreeSize -= size; - pFabricVAS->ucFabricInUseSize += size; - - return NV_OK; - -failed: - - _fabricvaspaceUnbindInstBlk(pFabricVAS); - - return status; + return NV_ERR_NOT_SUPPORTED; } NV_STATUS @@ -462,7 +423,9 @@ fabricvaspaceAllocNonContiguous_IMPL // // Attempt to allocate VA space of the size and alignment requested. - // RM_PAGE_SIZE_HUGE is passed since FLA->PA page size is 2MB. + // + // RM_PAGE_SIZE_HUGE is passed since FLA->PA mappings support minimum + // 2MB pagesize. // if (flags.bForceContig || bDefaultAllocMode) { @@ -482,8 +445,10 @@ fabricvaspaceAllocNonContiguous_IMPL // // If size could not be allocated in one memblock, break size into - // multiple pageSize chunks. RM_PAGE_SIZE_HUGE is passed since - // FLA->PA page size is 2MB. + // multiple pageSize chunks. + // + // RM_PAGE_SIZE_HUGE is passed since FLA->PA mappings support minimum + // 2MB pagesize. // if (flags.bForceNonContig || (bDefaultAllocMode && (status != NV_OK))) { @@ -543,7 +508,7 @@ fabricvaspaceFree_IMPL NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, vAddr, &blockSize) == NV_OK); kbusFlush_HAL(pGpu, pKernelBus, (BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | + BUS_FLUSH_SYSTEM_MEMORY | BUS_FLUSH_USE_PCIE_READ)); fabricvaspaceInvalidateTlb(pFabricVAS, pGpu, PTE_DOWNGRADE); @@ -670,7 +635,8 @@ fabricvaspaceBatchFree_IMPL bUcFla = (pAddr[idx] >= fabricvaspaceGetUCFlaStart(pFabricVAS) && pAddr[idx] < fabricvaspaceGetUCFlaLimit(pFabricVAS)); - NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, pAddr[idx], &freeSize) == NV_OK); + NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, + pAddr[idx], &freeSize) == NV_OK); idx += stride; @@ -679,7 +645,7 @@ fabricvaspaceBatchFree_IMPL } kbusFlush_HAL(pGpu, pKernelBus, (BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | + BUS_FLUSH_SYSTEM_MEMORY | BUS_FLUSH_USE_PCIE_READ)); fabricvaspaceInvalidateTlb(pFabricVAS, pGpu, PTE_DOWNGRADE); @@ -721,8 +687,8 @@ fabricvaspaceGetGpaMemdesc_IMPL { bLoopbackSupported = pKernelNvlink != NULL && - (knvlinkIsP2pLoopbackSupported(pMappingGpu, pKernelNvlink) || - knvlinkIsForcedConfig(pMappingGpu, pKernelNvlink)); + (knvlinkIsP2pLoopbackSupported(pMappingGpu, pKernelNvlink) || + knvlinkIsForcedConfig(pMappingGpu, pKernelNvlink)); } if (memdescGetAddressSpace(pFabricMemdesc) != ADDR_FABRIC_V2 || @@ -745,28 +711,34 @@ fabricvaspaceGetGpaMemdesc_IMPL } // - // If the address space is of type ADDR_FABRIC_V2 then determine if the FLA import - // is on the mapping GPU. If FLA import is on the mapping GPU and NVLink P2P over - // loopback is not supported, then map GVA->PA directly. For discontiguous fabric - // memory allocation, searching for the first entry in the pteArray should be fine - // to determine if FLA import is on the mapping GPU. + // If the address space is of type ADDR_FABRIC_V2 then determine if the + // FLA import is on the mapping GPU. If FLA import is on the mapping GPU + // and NVLink P2P over loopback is not supported, then map GVA->PA directly. + // For discontiguous fabric memory allocation, searching for the first entry + // in the pteArray should be fine to determine if FLA import is on the + // mapping GPU. // - NV_ASSERT_OK_OR_RETURN(btreeSearch(pteArray[0], &pNode, pFabricVAS->pFabricVaToGpaMap)); + NV_ASSERT_OK_OR_RETURN(btreeSearch(pteArray[0], &pNode, + pFabricVAS->pFabricVaToGpaMap)); - FABRIC_VA_TO_GPA_MAP_NODE *pFabricNode = (FABRIC_VA_TO_GPA_MAP_NODE *)pNode->Data; + FABRIC_VA_TO_GPA_MAP_NODE *pFabricNode = + (FABRIC_VA_TO_GPA_MAP_NODE *)pNode->Data; // - // Create a sub-memdesc for the offset into the vidMemDesc where the GVA would be - // mapped. Note this includes two offsets: + // Create a sub-memdesc for the offset into the vidMemDesc where the GVA + // would be mapped. Note this includes two offsets: // 1. Offset into the fabric memdesc where the GVA is mapped. - // 2. Offset into the physical vidmem memdesc where the fabric memory is mapped. + // 2. Offset into the physical vidmem memdesc where the fabric memory is + // mapped. // - status = memdescCreateSubMem(ppAdjustedMemdesc, pFabricNode->pVidMemDesc, pMappingGpu, + status = memdescCreateSubMem(ppAdjustedMemdesc, pFabricNode->pVidMemDesc, + pMappingGpu, rootOffset + pFabricNode->offset, memdescGetSize(pFabricMemdesc)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to create submMemdesc for the GVA->PA mapping\n"); + NV_PRINTF(LEVEL_ERROR, + "Failed to create submMemdesc for the GVA->PA mapping\n"); return status; } @@ -869,8 +841,12 @@ fabricvaspaceAllocMulticast_IMPL rangeLo = base; rangeHi = base + size - 1; + // + // RM_PAGE_SIZE_HUGE is passed since MCFLA->PA mappings support minimum + // 2MB pagesize. + // status = vaspaceAlloc(pFabricVAS->pGVAS, size, alignment, rangeLo, - rangeHi, pageSize, flags, &addr); + rangeHi, RM_PAGE_SIZE_HUGE, flags, &addr); NV_ASSERT(addr == base); @@ -1010,9 +986,9 @@ fabricvaspaceUnmapPhysMemdesc_IMPL FABRIC_VASPACE_MAPPING_REGIONS regions; NvU32 numRegions; - fabricPageSize = memdescGetPageSize64(pFabricMemDesc, AT_GPU); + fabricPageSize = memdescGetPageSize(pFabricMemDesc, AT_GPU); - NV_ASSERT_OR_RETURN_VOID(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == \ + NV_ASSERT_OR_RETURN_VOID(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == pFabricVAS); _fabricvaspaceGetMappingRegions(fabricOffset, fabricPageSize, physMapLength, @@ -1021,10 +997,13 @@ fabricvaspaceUnmapPhysMemdesc_IMPL for (i = 0; i < numRegions; i++) { - fabricPageCount = ((memdescGetPteArraySize(pFabricMemDesc, AT_GPU) == 1) || - (regions.r[i].length < fabricPageSize)) ? \ - 1 : (regions.r[i].length / fabricPageSize); + fabricPageCount = + ((memdescGetPteArraySize(pFabricMemDesc, AT_GPU) == 1) || + (regions.r[i].length < fabricPageSize)) ? + 1 : (regions.r[i].length / fabricPageSize); + mapLength = (fabricPageCount == 1) ? regions.r[i].length : fabricPageSize; + fabricOffset = regions.r[i].offset; for (j = 0; j < fabricPageCount; j++) @@ -1035,10 +1014,11 @@ fabricvaspaceUnmapPhysMemdesc_IMPL } else { - fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / pFabricMemDesc->pageArrayGranularity]; + fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / + pFabricMemDesc->pageArrayGranularity]; } - vaspaceUnmap(pFabricVAS->pGVAS, pPhysMemDesc->pGpu, fabricAddr, \ + vaspaceUnmap(pFabricVAS->pGVAS, pPhysMemDesc->pGpu, fabricAddr, fabricAddr + mapLength - 1); fabricOffset = fabricOffset + mapLength; @@ -1090,8 +1070,8 @@ fabricvaspaceMapPhysMemdesc_IMPL NV_ASSERT_OR_RETURN(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == pFabricVAS, NV_ERR_INVALID_ARGUMENT); - physPageSize = memdescGetPageSize64(pPhysMemDesc, AT_GPU); - fabricPageSize = memdescGetPageSize64(pFabricMemDesc, AT_GPU); + physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + fabricPageSize = memdescGetPageSize(pFabricMemDesc, AT_GPU); status = _fabricVaspaceValidateMapAttrs(fabricOffset, memdescGetSize(pFabricMemDesc), @@ -1109,6 +1089,27 @@ fabricvaspaceMapPhysMemdesc_IMPL physOffset, &kind, &comprInfo); NV_ASSERT_OK_OR_RETURN(status); + if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_FBMEM) + { + aperture = NV_MMU_PTE_APERTURE_VIDEO_MEMORY; + } + else if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_SYSMEM) + { + if (memdescGetCpuCacheAttrib(pPhysMemDesc) == NV_MEMORY_CACHED) + { + aperture = NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY; + } + else + { + aperture = NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY; + } + } + else + { + NV_PRINTF(LEVEL_ERROR, "Unsupported aperture\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + _fabricvaspaceGetMappingRegions(fabricOffset, fabricPageSize, physMapLength, ®ions, &numRegions); NV_ASSERT_OR_RETURN(numRegions != 0, NV_ERR_INVALID_ARGUMENT); @@ -1133,7 +1134,8 @@ fabricvaspaceMapPhysMemdesc_IMPL } else { - fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / pFabricMemDesc->pageArrayGranularity]; + fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / + pFabricMemDesc->pageArrayGranularity]; } if (pageArray.count == 1) @@ -1143,7 +1145,8 @@ fabricvaspaceMapPhysMemdesc_IMPL } else { - pageArray.pData = &pPhysMemDesc->_pteArray[physOffset / pPhysMemDesc->pageArrayGranularity]; + pageArray.pData = &pPhysMemDesc->_pteArray[physOffset / + pPhysMemDesc->pageArrayGranularity]; } // @@ -1166,27 +1169,6 @@ fabricvaspaceMapPhysMemdesc_IMPL pTempMemdesc = pPhysMemDesc; } - if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_FBMEM) - { - aperture = NV_MMU_PTE_APERTURE_VIDEO_MEMORY; - } - else if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_SYSMEM) - { - if (memdescGetCpuCacheAttrib(pPhysMemDesc) == NV_MEMORY_CACHED) - { - aperture = NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY; - } - else - { - aperture = NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY; - } - } - else - { - NV_PRINTF(LEVEL_ERROR, "Unsupported aperture\n"); - NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); - } - // Map the memory fabric object at the given physical memory offset. status = dmaUpdateVASpace_HAL(pGpu, pDma, pFabricVAS->pGVAS, pTempMemdesc, NULL, fabricAddr, fabricAddr + mapLength - 1, @@ -1195,7 +1177,7 @@ fabricvaspaceMapPhysMemdesc_IMPL aperture, BUS_INVALID_PEER, NVLINK_INVALID_FABRIC_ADDR, DMA_DEFER_TLB_INVALIDATE, NV_FALSE, - memdescGetPageSize64(pTempMemdesc, AT_GPU)); + memdescGetPageSize(pTempMemdesc, AT_GPU)); if (pTempMemdesc != pPhysMemDesc) memdescDestroy(pTempMemdesc); @@ -1246,3 +1228,37 @@ fabricvaspaceInitUCRange_IMPL return NV_OK; } +void +fabricvaspaceClearUCRange_IMPL +( + FABRIC_VASPACE *pFabricVAS +) +{ + pFabricVAS->ucFabricBase = 0; + pFabricVAS->ucFabricLimit = 0; + pFabricVAS->ucFabricInUseSize = 0; + pFabricVAS->ucFabricFreeSize = 0; +} + +NV_STATUS +fabricvaspaceGetPageLevelInfo_IMPL +( + FABRIC_VASPACE *pFabricVAS, + OBJGPU *pGpu, + NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS *pParams +) +{ + OBJGVASPACE *pGVAS = dynamicCast(pFabricVAS->pGVAS, OBJGVASPACE); + NV_ASSERT_OR_RETURN(pGVAS != NULL, NV_ERR_OBJECT_NOT_FOUND); + + return gvaspaceGetPageLevelInfo(pGVAS, pGpu, pParams); +} + +NvBool +fabricvaspaceIsInUse_IMPL +( + FABRIC_VASPACE *pFabricVAS +) +{ + return gvaspaceIsInUse(dynamicCast(pFabricVAS->pGVAS, OBJGVASPACE)); +} diff --git a/src/nvidia/src/kernel/mem_mgr/fla_mem.c b/src/nvidia/src/kernel/mem_mgr/fla_mem.c index dcd8d830ff..3e540c8afb 100644 --- a/src/nvidia/src/kernel/mem_mgr/fla_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/fla_mem.c @@ -344,12 +344,13 @@ flamemConstruct_IMPL pAllocParams->base = newBase; pAllocParams->limit = flaSize - 1; NV_RM_RPC_ALLOC_OBJECT(pGpu, - pParams->hClient, - pParams->hParent, - pParams->hResource, - pParams->externalClassId, - pAllocParams, - status); + pParams->hClient, + pParams->hParent, + pParams->hResource, + pParams->externalClassId, + pAllocParams, + sizeof(*pAllocParams), + status); if (status != NV_OK) { diff --git a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c index 7898585cba..eedf7ef4d5 100644 --- a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,13 +59,15 @@ #define GMMU_PD1_VADDR_BIT_LO 29 -static const NvU64 pageSizes[VAS_PAGESIZE_IDX_MAX] = { +static const NvU64 pageSizes[] = { RM_PAGE_SIZE, RM_PAGE_SIZE_64K, RM_PAGE_SIZE_HUGE, RM_PAGE_SIZE_512M }; +static const NvU32 pageSizeCount = sizeof (pageSizes) / sizeof (*pageSizes); + static NV_STATUS _gvaspaceGpuStateConstruct ( @@ -441,8 +443,8 @@ gvaspaceReserveSplitVaSpace_IMPL if (pVAS->vasStart > pGVAS->vaStartServerRMOwned) { pGVAS->vaStartServerRMOwned = pVAS->vasStart + SPLIT_VAS_SERVER_RM_MANAGED_VA_START; - } - + } + pGVAS->vaLimitServerRMOwned = pGVAS->vaStartServerRMOwned + SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; @@ -482,31 +484,6 @@ gvaspaceReserveSplitVaSpace_IMPL return status; } - -static NvU32 -_gvaspacePageSizeToIdx -( - NvU64 pageSize -) -{ - switch (pageSize) - { - case RM_PAGE_SIZE: - return VAS_PAGESIZE_IDX_4K; - case RM_PAGE_SIZE_64K: - case RM_PAGE_SIZE_128K: - return VAS_PAGESIZE_IDX_BIG; - case RM_PAGE_SIZE_HUGE: - return VAS_PAGESIZE_IDX_HUGE; - case RM_PAGE_SIZE_512M: - return VAS_PAGESIZE_IDX_512M; - default: - NV_PRINTF(LEVEL_ERROR, "Invalid pageSize=0x%llx!\n", pageSize); - NV_ASSERT(0); - return 0; - } -} - NV_STATUS gvaspaceConstruct__IMPL ( @@ -558,7 +535,7 @@ gvaspaceConstruct__IMPL { pGVAS->bIsAtsEnabled = NV_TRUE; NV_PRINTF(LEVEL_INFO, "ATS Enabled VaSpace\n"); - // + // // Initialize with invalid PASID value for sanity checking later during // PASID programming in HW. // For non-MODS case, PASID is programmed via control call @@ -1103,8 +1080,7 @@ _gvaspaceGpuStateConstruct NvU64 pageSizeMask; NvU64 vaStartMin; NvU64 vaLimitMax; - NvU32 bigPageSize; - NvU64 maxPageSizeSupported; + NvU64 bigPageSize; NvU64 compPageSize; NvU64 extManagedAlign; NvU64 vaLimitExt; @@ -1134,14 +1110,8 @@ _gvaspaceGpuStateConstruct // Determine GPU's page size settings. pageSizeMask = mmuFmtAllPageSizes(pFmt->pRoot); - bigPageSize = (NvU32)(pageSizeMask & (RM_PAGE_SIZE_64K | RM_PAGE_SIZE_128K)); - // - // Set the max page size supported for the system to determine if we need to look into - // 512Mb page or not. - // - maxPageSizeSupported = (kgmmuIsPageSize512mbSupported(pKernelGmmu)? - RM_PAGE_SIZE_512M: (kgmmuIsHugePageSupported(pKernelGmmu) ? - RM_PAGE_SIZE_HUGE : bigPageSize)); + bigPageSize = pageSizeMask & (RM_PAGE_SIZE_64K | RM_PAGE_SIZE_128K); + compPageSize = pMemorySystemConfig->comprPageSize; // Determine externally managed VA alignment from big page table coverage. @@ -1205,7 +1175,6 @@ _gvaspaceGpuStateConstruct if (bFirst) { pGVAS->bigPageSize = bigPageSize; - pGVAS->maxPageSizeSupported = maxPageSizeSupported; pGVAS->compPageSize = compPageSize; pGVAS->extManagedAlign = extManagedAlign; @@ -1383,7 +1352,7 @@ _gvaspaceAllocateFlaDummyPagesForFlaRange status = pRmApi->AllocWithHandle(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hSubDevice, pGpuState->flaDummyPage.hMemory, NV01_MEMORY_LOCAL_USER, - &memAllocParams); + &memAllocParams, sizeof(memAllocParams)); if (bAcquireLock) { @@ -2052,18 +2021,11 @@ gvaspaceGetMapPageSize_IMPL } } - if ((pageSizeMask >> 32) != 0) - { - NV_PRINTF(LEVEL_ERROR, - "Time to update width of variables for page size. PageSizeMask: 0x%llx\n", - pageSizeMask); - } - NV_ASSERT(0); return 0; } -NvU32 +NvU64 gvaspaceGetBigPageSize_IMPL(OBJGVASPACE *pGVAS) { return pGVAS->bigPageSize; @@ -2115,7 +2077,7 @@ gvaspaceGetPasid_IMPL(OBJGVASPACE *pGVAS, NvU32 *pPasid) NV_PRINTF(LEVEL_INFO, "ATS enabled: %u PASID: %u\n", pGVAS->bIsAtsEnabled, pGVAS->processAddrSpaceId); - + NV_ASSERT_OR_RETURN(pGVAS->bIsAtsEnabled, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pGVAS->processAddrSpaceId != NV_U32_MAX, NV_ERR_INVALID_STATE); *pPasid = pGVAS->processAddrSpaceId; @@ -2454,10 +2416,13 @@ gvaspaceGetVasInfo_IMPL NV_ASSERT_OR_RETURN(pBigPageTable, NV_ERR_INVALID_EVENT); pParams->bigPageSize = pGVAS->bigPageSize; - pParams->hugePageSize = kgmmuIsHugePageSupported(pKernelGmmu) ? - RM_PAGE_SIZE_HUGE : 0; - pParams->pageSize512MB = kgmmuIsPageSize512mbSupported(pKernelGmmu) ? - RM_PAGE_SIZE_512M : 0; + pParams->supportedPageSizeMask = RM_PAGE_SIZE | pParams->bigPageSize; + + if (kgmmuIsHugePageSupported(pKernelGmmu)) + pParams->supportedPageSizeMask |= RM_PAGE_SIZE_HUGE; + + if (kgmmuIsPageSize512mbSupported(pKernelGmmu)) + pParams->supportedPageSizeMask |= RM_PAGE_SIZE_512M; // Dual Page Table is supported for all Fermi-and-later chips pParams->dualPageTableSupported = (NvU32)NV_TRUE; @@ -2504,7 +2469,6 @@ gvaspaceGetPageTableInfo_IMPL NvU32 i; NvBool bOrigBcState; NV_STATUS rmStatus; - NvU64 maxPageSizeSupported = pGVAS->maxPageSizeSupported; NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_PARAM_STRUCT); @@ -2531,7 +2495,7 @@ gvaspaceGetPageTableInfo_IMPL NV_ASSERT_OR_RETURN((NV_OK == rmStatus), rmStatus); - for (i = 0; i <= (_gvaspacePageSizeToIdx(maxPageSizeSupported)); i++) + for (i = 0; i < pageSizeCount; i++) { PMEMORY_DESCRIPTOR pMemDesc = NULL; NvU32 memSize = 0; @@ -2568,10 +2532,11 @@ gvaspaceGetPageTableInfo_IMPL pParams->pdeEntrySize = pParentFmt->entrySize; } + NV_ASSERT_OR_RETURN(pteBlockIdx < NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS, NV_ERR_INVALID_STATE); pPteBlock = &pParams->pteBlocks[pteBlockIdx++]; // Page size supported by this page table - pPteBlock->pageSize = (NvU32)pageSize; + pPteBlock->pageSize = pageSize; // Phys addr of the Page Table pPteBlock->ptePhysAddr = memdescGetPhysAddr(pMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), 0); @@ -2657,14 +2622,15 @@ gvaspaceGetPteInfo_IMPL ) { KernelGmmu *pKernelGmmu; + MemoryManager *pMemoryManager; GVAS_GPU_STATE *pGpuState; MMU_WALK *pWalk; const GMMU_FMT *pFmt; NV_STATUS status = NV_OK; NvU32 i; NvU32 pteBlockIndex = 0; - NvU64 maxPageSizeSupported = pGVAS->maxPageSizeSupported; const MMU_FMT_LEVEL *pRootFmt; + TRANSFER_SURFACE surf = {0}; NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_PARAM_STRUCT); @@ -2680,20 +2646,20 @@ gvaspaceGetPteInfo_IMPL pFmt = pGpuState->pFmt; pRootFmt = pFmt->pRoot; pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); // // We will try all available page sizes for valid allocation a the give VA. // Will flag error if mutiple valid allocations exist. // - for (i = 0; i <= (_gvaspacePageSizeToIdx(maxPageSizeSupported)); i++) + for (i = 0; i < pageSizeCount; i++) { NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK *pPteBlock = NULL; const GMMU_FIELD_ADDRESS *pAddrField; const MMU_FMT_LEVEL *pLevelFmt = NULL; PMEMORY_DESCRIPTOR pMemDesc = NULL; NvU32 memSize = 0; - NvU8 *pMap = NULL; NvU32 pteIndex; GMMU_ENTRY_VALUE pte = {{0}}; NvU64 pageSize; @@ -2716,28 +2682,19 @@ gvaspaceGetPteInfo_IMPL pteIndex = mmuFmtVirtAddrToEntryIndex(pLevelFmt, pParams->gpuAddr); - // Map the Page Table to BAR - pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); - NV_ASSERT_OR_RETURN(NULL != pMap, NV_ERR_INSUFFICIENT_RESOURCES); - portMemCopy(pte.v8, pLevelFmt->entrySize, pMap + (pteIndex * pLevelFmt->entrySize), pLevelFmt->entrySize); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_FALSE); + // Read the PTE + surf.pMemDesc = pMemDesc; + surf.offset = pteIndex * pLevelFmt->entrySize; - if (pteBlockIndex <= _gvaspacePageSizeToIdx(maxPageSizeSupported)) - { - pPteBlock = &pParams->pteBlocks[pteBlockIndex++]; - } - else if (nvFieldGetBool(&pFmt->pPte->fldValid, pte.v8)) - { - // Override last block if the PTE is valid. - pPteBlock = &pParams->pteBlocks[pteBlockIndex - 1]; - } - else - { - break; - } + NV_ASSERT_OK_OR_RETURN(memmgrMemRead(pMemoryManager, &surf, pte.v8, + pLevelFmt->entrySize, + TRANSFER_FLAGS_DEFER_FLUSH)); + + NV_ASSERT_OR_RETURN(pteBlockIndex < NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS, NV_ERR_INVALID_STATE); + pPteBlock = &pParams->pteBlocks[pteBlockIndex++]; // Page size supported by this page table - pPteBlock->pageSize = (NvU32)pageSize; + pPteBlock->pageSize = pageSize; // Number of bytes occupied by one PTE pPteBlock->pteEntrySize = pLevelFmt->entrySize; @@ -2810,11 +2767,10 @@ gvaspaceSetPteInfo_IMPL { OBJVASPACE *pVAS = staticCast(pGVAS, OBJVASPACE); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU8 *pMap = NULL; NvU8 i; NV_STATUS status = NV_OK; NvBool bDowngrade = NV_FALSE; - NvU64 maxPageSizeSupported = pGVAS->maxPageSizeSupported; + TRANSFER_SURFACE surf = {0}; NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_PARAM_STRUCT); @@ -2834,7 +2790,7 @@ gvaspaceSetPteInfo_IMPL goto catchGpu; } - for (i = 0; i <= (_gvaspacePageSizeToIdx(maxPageSizeSupported)); i++) + for (i = 0; i < NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS; i++) { NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK *pPteBlock = NULL; const MMU_FMT_LEVEL *pLevelFmt; @@ -2872,7 +2828,7 @@ gvaspaceSetPteInfo_IMPL // Query the Page Tables. pLevelFmt = mmuFmtFindLevelWithPageShift(pRootFmt, - BIT_IDX_32(pParams->pteBlocks[i].pageSize)); + BIT_IDX_64(pParams->pteBlocks[i].pageSize)); if (NULL == pLevelFmt) { status = NV_ERR_INVALID_STATE; @@ -2891,17 +2847,17 @@ gvaspaceSetPteInfo_IMPL pPteBlock = &pParams->pteBlocks[i]; - // Map the Page Table to BAR - pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); - if (NULL == pMap) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - NV_ASSERT_OR_GOTO(0, catchGpu); - } - // Read the PTE pteIndex = mmuFmtVirtAddrToEntryIndex(pLevelFmt, pParams->gpuAddr); - portMemCopy(pte.v8, pLevelFmt->entrySize, pMap + (pteIndex * pLevelFmt->entrySize), pLevelFmt->entrySize); + + surf.pMemDesc = pMemDesc; + surf.offset = pteIndex * pLevelFmt->entrySize; + + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemRead(pMemoryManager, &surf, pte.v8, + pLevelFmt->entrySize, + TRANSFER_FLAGS_NONE), + catchGpu); // // If any of these entries are being downgraded, we need to perform @@ -3001,12 +2957,13 @@ gvaspaceSetPteInfo_IMPL } } - - - // Copy back the overwritten values to the actual PTE memory - portMemCopy(pMap + (pteIndex * pLevelFmt->entrySize), pLevelFmt->entrySize, pte.v8, pLevelFmt->entrySize); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_TRUE); + NV_ASSERT_OK_OR_GOTO(status, + memmgrMemWrite(pMemoryManager, &surf, pte.v8, + pLevelFmt->entrySize, + TRANSFER_FLAGS_NONE), + catchGpu); + } // Invalidate TLB @@ -3580,10 +3537,11 @@ _gmmuWalkCBMapSingleEntry NvU32 *pProgress ) { - OBJGPU *pGpu = pUserCtx->pGpu; - MMU_MAP_ITERATOR *pIter = pTarget->pIter; - MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR*)pLevelMem; - NvU8 *pMap = NULL; + OBJGPU *pGpu = pUserCtx->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + MMU_MAP_ITERATOR *pIter = pTarget->pIter; + MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR*)pLevelMem; + TRANSFER_SURFACE surf = {0}; NV_PRINTF(LEVEL_INFO, "[GPU%u]: PA 0x%llX, Entries 0x%X-0x%X\n", pUserCtx->pGpu->gpuInstance, @@ -3592,15 +3550,13 @@ _gmmuWalkCBMapSingleEntry NV_ASSERT_OR_RETURN_VOID(entryIndexLo == entryIndexHi); - pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); - NV_ASSERT_OR_RETURN_VOID(NULL != pMap); - - portMemCopy(pMap + entryIndexLo * pTarget->pLevelFmt->entrySize, - pTarget->pLevelFmt->entrySize, - pIter->entry.v8, - pTarget->pLevelFmt->entrySize); - - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_TRUE); + surf.pMemDesc = pMemDesc; + surf.offset = entryIndexLo * pTarget->pLevelFmt->entrySize; + + NV_ASSERT_OR_RETURN_VOID(memmgrMemWrite(pMemoryManager, &surf, + pIter->entry.v8, + pTarget->pLevelFmt->entrySize, + TRANSFER_FLAGS_NONE) == NV_OK); *pProgress = entryIndexHi - entryIndexLo + 1; } @@ -3631,7 +3587,7 @@ gvaspaceUpdatePde2_IMPL // Lookup leaf page table formats. pPTBig = mmuFmtFindLevelWithPageShift(pFmt->pRoot, - BIT_IDX_32(gvaspaceGetBigPageSize(pGVAS))); + BIT_IDX_64(gvaspaceGetBigPageSize(pGVAS))); pPT4KB = mmuFmtFindLevelWithPageShift(pFmt->pRoot, 12); NV_ASSERT_OR_RETURN(NULL != pPTBig, NV_ERR_NOT_SUPPORTED); @@ -3689,6 +3645,7 @@ gvaspaceUpdatePde2_IMPL if (GMMU_APERTURE_INVALID != aperture) { KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); gmmuFieldSetAddress(gmmuFmtPdePhysAddrFld(pPdeFmt, aperture), kgmmuEncodePhysAddr(pKernelGmmu, aperture, pPtParams->physAddr, @@ -3701,21 +3658,22 @@ gvaspaceUpdatePde2_IMPL NvU32 pdePcfSw = 0; PMEMORY_DESCRIPTOR pMemDesc = NULL; NvU32 memSize = 0; - NvU8 *pMap = NULL; GMMU_ENTRY_VALUE pde = {{0}}; GMMU_APERTURE currAperture; + TRANSFER_SURFACE surf = {0}; NV_ASSERT_OK_OR_RETURN( mmuWalkGetPageLevelInfo(pGpuState->pWalk, mapTarget.pLevelFmt, (pParams->pdeIndex * mmuFmtLevelPageSize(mapTarget.pLevelFmt)), (const MMU_WALK_MEMDESC**)&pMemDesc, &memSize)); - pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); - NV_ASSERT_OR_RETURN(pMap != NULL, NV_ERR_INSUFFICIENT_RESOURCES); - portMemCopy(pde.v8, mapTarget.pLevelFmt->entrySize, - pMap + (pParams->pdeIndex * mapTarget.pLevelFmt->entrySize), - mapTarget.pLevelFmt->entrySize); - kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_FALSE); + surf.pMemDesc = pMemDesc; + surf.offset = pParams->pdeIndex * mapTarget.pLevelFmt->entrySize; + + NV_ASSERT_OK_OR_RETURN(memmgrMemRead(pMemoryManager, &surf, + pde.v8, + mapTarget.pLevelFmt->entrySize, + TRANSFER_FLAGS_DEFER_FLUSH)); pdePcfHw = nvFieldGet32(&pPdeFmt->fldPdePcf, pde.v8); currAperture = gmmuFieldGetAperture(&pPdeFmt->fldAperture, pde.v8); @@ -4150,6 +4108,7 @@ gvaspaceCopyServerRmReservedPdesToServerRm_IMPL hVASpace, FERMI_VASPACE_A, &vaParams, + sizeof(vaParams), status); NV_ASSERT_OR_RETURN(NV_OK == status, status); @@ -4218,9 +4177,15 @@ _gvaspaceControl_Prolog if (0 != hSubDevice) { - NvHandle hDevice; - NV_ASSERT_OR_RETURN(CliSetSubDeviceContext(RES_GET_CLIENT_HANDLE(pVaspaceApi), hSubDevice, &hDevice, ppGpu) == NV_OK, - NV_ERR_INVALID_OBJECT); + Subdevice *pSubDevice; + + NV_ASSERT_OK_OR_RETURN( + subdeviceGetByHandle(RES_GET_CLIENT(pVaspaceApi), + hSubDevice, &pSubDevice)); + + *ppGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); } else { @@ -5150,7 +5115,7 @@ _gvaspacePopulatePDEentries portMemSet(pPdeCopyParams, 0, sizeof(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS)); // Populate the input params. - pdeInfo.pageSize = NVBIT32(GMMU_PD1_VADDR_BIT_LO); + pdeInfo.pageSize = NVBIT64(GMMU_PD1_VADDR_BIT_LO); pdeInfo.virtAddress = pGVAS->vaStartServerRMOwned; // Fetch the details of the PDEs backing server RM's VA range. @@ -5168,7 +5133,7 @@ _gvaspacePopulatePDEentries pPdeCopyParams->numLevelsToCopy = pdeInfo.numLevels; pPdeCopyParams->subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - pPdeCopyParams->pageSize = NVBIT32(GMMU_PD1_VADDR_BIT_LO); + pPdeCopyParams->pageSize = NVBIT64(GMMU_PD1_VADDR_BIT_LO); pPdeCopyParams->virtAddrLo = pGVAS->vaStartServerRMOwned; pPdeCopyParams->virtAddrHi = pPdeCopyParams->virtAddrLo + SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; diff --git a/src/nvidia/src/kernel/mem_mgr/mem.c b/src/nvidia/src/kernel/mem_mgr/mem.c index a7ed2efad8..6c6af7be96 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem.c +++ b/src/nvidia/src/kernel/mem_mgr/mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -857,7 +857,7 @@ memCopyConstruct_IMPL } NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - memCheckCopyPermissions(pMemorySrc, pDstGpu, pDstClient->hClient), done); + memCheckCopyPermissions(pMemorySrc, pDstGpu, pDstDevice), done); // Initialize Memory pMemoryDst->categoryClassId = pMemorySrc->categoryClassId; @@ -891,7 +891,7 @@ memCopyConstruct_IMPL gpuSetThreadBcState(pDstGpu, NV_TRUE); SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) - if (memdescGetPageSize64(memdescGetMemDescFromGpu(pMemoryDst->pMemDesc, pGpu), AT_GPU) == 0) + if (memdescGetPageSize(memdescGetMemDescFromGpu(pMemoryDst->pMemDesc, pGpu), AT_GPU) == 0) { status = memmgrSetMemDescPageSize_HAL(pGpu, GPU_GET_MEMORY_MANAGER(pGpu), memdescGetMemDescFromGpu(pMemoryDst->pMemDesc, pGpu), diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c index 9fc7fc7796..7ed5c2cfc0 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -64,7 +64,7 @@ _memoryfabricMemDescGetNumAddr NvU64 pageSize = 0; // Get the page size from the memory descriptor. - pageSize = memdescGetPageSize64(pMemDesc, + pageSize = memdescGetPageSize(pMemDesc, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); // Get the number of addresses associated with this memory descriptor. @@ -112,17 +112,19 @@ _memoryfabricValidatePhysMem pPhysMemDesc = (dynamicCast(pPhysmemRef->pResource, Memory))->pMemDesc; - if (!memmgrIsApertureSupportedByFla_HAL(pOwnerGpu, pMemoryManager, memdescGetAddressSpace(pPhysMemDesc)) || - (pOwnerGpu != pPhysMemDesc->pGpu)) + if ((pOwnerGpu != pPhysMemDesc->pGpu) || + !memmgrIsApertureSupportedByFla_HAL(pOwnerGpu, pMemoryManager, + memdescGetAddressSpace(pPhysMemDesc))) { NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle passed\n"); return NV_ERR_INVALID_ARGUMENT; } - physPageSize = memdescGetPageSize64(pPhysMemDesc, AT_GPU); - if ((physPageSize != NV_MEMORY_FABRIC_PAGE_SIZE_2M) && - (physPageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M)) + physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + if ( + (physPageSize != RM_PAGE_SIZE_HUGE) && + (physPageSize != RM_PAGE_SIZE_512M)) { NV_PRINTF(LEVEL_ERROR, "Physmem page size should be 2MB\n"); @@ -222,6 +224,13 @@ _memoryFabricAttachMem return NV_ERR_NOT_SUPPORTED; } + if (gpuIsCCFeatureEnabled(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Unsupported when Confidential Computing is enabled\n"); + return NV_ERR_NOT_SUPPORTED; + } + status = _memoryfabricValidatePhysMem(RES_GET_CLIENT_HANDLE(pMemory), pAttachInfo->hMemory, pGpu, &pPhysMemDesc); @@ -280,7 +289,8 @@ _memoryFabricAttachMem portMemFree(pNode); unmapVas: - fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, pAttachInfo->offset, + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, + pAttachInfo->offset, pPhysMemDesc, pAttachInfo->mapLength); freeDupedMem: @@ -308,10 +318,12 @@ _memoryfabricMemDescDestroyCallback pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pMemDesc); - pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); + pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, + VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); numAddr = _memoryfabricMemDescGetNumAddr(pMemDesc); // Get the page size from the memory descriptor. - pageSize = memdescGetPageSize64(pMemDesc, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); + pageSize = memdescGetPageSize(pMemDesc, + VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); // Remove the fabric memory allocations from the map. fabricvaspaceVaToGpaMapRemove(pFabricVAS, pteArray[0]); @@ -323,10 +335,11 @@ _memoryfabricMemDescDestroyCallback { // // Call fabricvaspaceBatchFree to free the FLA allocations. - // _pteArray in memdesc is RM_PAGE_SIZE whereas page size for memory fabric - // allocations is either 2MB or 512MB. Pass stride accordingly. + // _pteArray in memdesc is RM_PAGE_SIZE whereas page size for memory + // fabric allocations is either 2MB or 512MB. Pass stride accordingly. // - fabricvaspaceBatchFree(pFabricVAS, pteArray, numAddr, (pageSize >> RM_PAGE_SHIFT)); + fabricvaspaceBatchFree(pFabricVAS, pteArray, numAddr, + (pageSize >> RM_PAGE_SHIFT)); } if (pMemdescData != NULL) @@ -398,12 +411,14 @@ _memoryfabricAllocFabricVa_VGPU pParams->hResource, pParams->externalClassId, pAllocParams, + sizeof(*pAllocParams), status); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Alloc NV_MEMORY_FABRIC RPC failed, status: %x\n", - status); + NV_PRINTF(LEVEL_ERROR, + "Alloc NV_MEMORY_FABRIC RPC failed, status: %x\n", + status); return status; } @@ -427,14 +442,16 @@ _memoryfabricAllocFabricVa_VGPU if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "CTRL_CMD_DESCRIBE failed, status: 0x%x, " - "numPfns: 0x%x, totalPfns: 0x%llx, readSoFar: 0x%x \n", - status, pDescribeParams->numPfns, pDescribeParams->totalPfns, idx); + "numPfns: 0x%x, totalPfns: 0x%llx, readSoFar: 0x%x \n", + status, pDescribeParams->numPfns, + pDescribeParams->totalPfns, idx); goto cleanup; } if (pAddr == NULL) { - pAddr = portMemAllocNonPaged(sizeof(NvU64) * pDescribeParams->totalPfns); + pAddr = portMemAllocNonPaged(sizeof(NvU64) * + pDescribeParams->totalPfns); if (pAddr == NULL) { status = NV_ERR_NO_MEMORY; @@ -444,7 +461,8 @@ _memoryfabricAllocFabricVa_VGPU for (i=0; i < pDescribeParams->numPfns; i++) { - pAddr[idx + i] = (NvU64)((NvU64)pDescribeParams->pfnArray[i] << RM_PAGE_SHIFT_HUGE); + pAddr[idx + i] = + (NvU64)((NvU64)pDescribeParams->pfnArray[i] << RM_PAGE_SHIFT_HUGE); } idx += pDescribeParams->numPfns; @@ -504,25 +522,25 @@ memoryfabricConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - Memory *pMemory = staticCast(pMemoryFabric, Memory); - OBJGPU *pGpu = pMemory->pGpu; - FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + Memory *pMemory = staticCast(pMemoryFabric, Memory); + OBJGPU *pGpu = pMemory->pGpu; + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); NV00F8_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - MEMORY_DESCRIPTOR *pPhysMemDesc = NULL; - NV_STATUS status = NV_OK; - MEMORY_DESCRIPTOR *pMemDesc = NULL; - FABRIC_MEMDESC_DATA *pMemdescData = NULL; - MEM_DESC_DESTROY_CALLBACK *pCallback = NULL; - VAS_ALLOC_FLAGS flags = {0}; - NvU64 *pAddr = NULL; - NvU32 numAddr = 0; - NvU32 pteKind = 0; - NvBool bReadOnly = NV_FALSE; - NvHandle hPhysMem; - NvBool bFlexible = NV_FALSE; - NvU32 mapFlags = 0; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + MEMORY_DESCRIPTOR *pPhysMemDesc = NULL; + NV_STATUS status = NV_OK; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + FABRIC_MEMDESC_DATA *pMemdescData = NULL; + MEM_DESC_DESTROY_CALLBACK *pCallback = NULL; + VAS_ALLOC_FLAGS flags = {0}; + NvU64 *pAddr = NULL; + NvU32 numAddr = 0; + NvU32 pteKind = 0; + NvBool bReadOnly = NV_FALSE; + NvHandle hPhysMem; + NvBool bFlexible = NV_FALSE; + NvU32 mapFlags = 0; if (RS_IS_COPY_CTOR(pParams)) { @@ -541,18 +559,19 @@ memoryfabricConstruct_IMPL return NV_ERR_NOT_SUPPORTED; } - // initialize Fabric VAS Unicast range if not already setup + // initialize Fabric VAS Unicast range if not already setup if (fabricvaspaceGetUCFlaLimit(pFabricVAS) == 0) { - NV_PRINTF(LEVEL_ERROR, "UC FLA ranges should be initialized by this time!\n"); + NV_PRINTF(LEVEL_ERROR, + "UC FLA ranges should be initialized by this time!\n"); return NV_ERR_INVALID_STATE; } - // Only page size 512MB and 2MB supported. - if ((pAllocParams->pageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M) && + if ( + (pAllocParams->pageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M) && (pAllocParams->pageSize != NV_MEMORY_FABRIC_PAGE_SIZE_2M)) { - NV_PRINTF(LEVEL_ERROR, "Unsupported pageSize: 0x%x\n", + NV_PRINTF(LEVEL_ERROR, "Unsupported pageSize: 0x%llx\n", pAllocParams->pageSize); return NV_ERR_INVALID_ARGUMENT; @@ -621,7 +640,7 @@ memoryfabricConstruct_IMPL { NV_PRINTF(LEVEL_ERROR, "VA Space alloc failed! Status Code: 0x%x Size: 0x%llx " - "RangeLo: 0x%llx, RangeHi: 0x%llx, page size: 0x%x\n", + "RangeLo: 0x%llx, RangeHi: 0x%llx, page size: 0x%llx\n", status, pAllocParams->allocSize, fabricvaspaceGetUCFlaStart(pFabricVAS), fabricvaspaceGetUCFlaLimit(pFabricVAS), @@ -700,7 +719,7 @@ memoryfabricConstruct_IMPL // Associate the memdescDestroy callback function. pCallback->pObject = (void *)pCallback; pCallback->destroyCallback = - (MemDescDestroyCallBack*) &_memoryfabricMemDescDestroyCallback; + (MemDescDestroyCallBack*) &_memoryfabricMemDescDestroyCallback; memdescAddDestroyCallback(pMemDesc, pCallback); @@ -713,9 +732,11 @@ memoryfabricConstruct_IMPL if (hPhysMem != 0) { // Dup the physical memory handle and cache it in memfabric memdesc. - status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, - &pMemdescData->hDupedPhysMem, pCallContext->pClient->hClient, - hPhysMem, 0); + status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, + pFabricVAS->hDevice, + &pMemdescData->hDupedPhysMem, + pCallContext->pClient->hClient, + hPhysMem, 0); if (status != NV_OK) { @@ -769,7 +790,8 @@ memoryfabricConstruct_IMPL // No need to unmap on failure. Unmap happens implicitly when fabric VA // would be freed. // - status = fabricvaspaceVaToGpaMapInsert(pFabricVAS, pAddr[0], pPhysMemDesc, + status = fabricvaspaceVaToGpaMapInsert(pFabricVAS, pAddr[0], + pPhysMemDesc, pAllocParams->map.offset); if (status != NV_OK) goto freeDupedMem; @@ -923,8 +945,8 @@ memoryfabricCtrlCmdDescribe_IMPL if (pParams->offset >= pParams->totalPfns) { - NV_PRINTF(LEVEL_ERROR, "offset: %llx is out of range: %llx \n", pParams->offset, - pParams->totalPfns); + NV_PRINTF(LEVEL_ERROR, "offset: %llx is out of range: %llx \n", + pParams->offset, pParams->totalPfns); return NV_ERR_OUT_OF_RANGE; } @@ -937,8 +959,8 @@ memoryfabricCtrlCmdDescribe_IMPL return NV_ERR_NO_MEMORY; offset = pParams->offset * pageSize; - memdescGetPhysAddrsForGpu(pMemory->pMemDesc, pMemory->pMemDesc->pGpu, AT_GPU, offset, - pageSize, pParams->numPfns, + memdescGetPhysAddrsForGpu(pMemory->pMemDesc, pMemory->pMemDesc->pGpu, + AT_GPU, offset, pageSize, pParams->numPfns, pFabricArray); for (i = 0; i < pParams->numPfns; i++) @@ -1029,7 +1051,9 @@ memoryfabricCtrlGetNumAttachedMem_IMPL pParams->numMemInfos = 0; - btreeEnumStart(pParams->offsetStart, &pNode, pMemdescData->pAttachMemInfoTree); + btreeEnumStart(pParams->offsetStart, &pNode, + pMemdescData->pAttachMemInfoTree); + while ((pNode != NULL) && (pNode->keyStart <= pParams->offsetEnd)) { pParams->numMemInfos++; @@ -1062,7 +1086,9 @@ memoryfabricCtrlGetAttachedMem_IMPL (pParams->numMemInfos > NV00F8_MAX_ATTACHED_MEM_INFOS)) return NV_ERR_INVALID_ARGUMENT; - btreeEnumStart(pParams->offsetStart, &pNode, pMemdescData->pAttachMemInfoTree); + btreeEnumStart(pParams->offsetStart, &pNode, + pMemdescData->pAttachMemInfoTree); + while (count < pParams->numMemInfos) { if (pNode == NULL) @@ -1106,3 +1132,103 @@ memoryfabricCtrlGetAttachedMem_IMPL return status; } + +static NV_STATUS +_memoryfabricGetPhysAttrsUsingFabricMemdesc +( + OBJGPU *pGpu, + FABRIC_VASPACE *pFabricVAS, + MEMORY_DESCRIPTOR *pFabricMemDesc, + NvU64 offset, + NvU64 *pPhysPageSize +) +{ + NV_STATUS status; + MEMORY_DESCRIPTOR *pPhysMemDesc; + FABRIC_MEMDESC_DATA *pMemdescData; + NODE *pNode = NULL; + FABRIC_ATTCH_MEM_INFO_NODE *pAttachMemInfoNode; + + if ((pFabricMemDesc == NULL) || (pPhysPageSize == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = fabricvaspaceGetGpaMemdesc(pFabricVAS, pFabricMemDesc, pGpu, + &pPhysMemDesc); + if (status == NV_OK) + { + *pPhysPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + memdescDestroy(pPhysMemDesc); + return NV_OK; + } + + if (status != NV_ERR_OBJECT_NOT_FOUND) + return status; + + // If the object is flexible, check the attach mem info tree. + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, btreeSearch(offset, &pNode, + pMemdescData->pAttachMemInfoTree)); + pAttachMemInfoNode = (FABRIC_ATTCH_MEM_INFO_NODE*)pNode->Data; + + *pPhysPageSize = memdescGetPageSize(pAttachMemInfoNode->pPhysMemDesc, + AT_GPU); + + return NV_OK; +} + +NV_STATUS +memoryfabricCtrlGetPageLevelInfo_IMPL +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS *pParams +) +{ + Memory *pMemory = staticCast(pMemoryFabric, Memory); + OBJGPU *pGpu = pMemory->pGpu; + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS pageLevelInfoParams = {0}; + MEMORY_DESCRIPTOR *pFabricMemDesc = pMemory->pMemDesc; + NvU64 fabricAddr; + NvU64 mappingPageSize; + NvU64 physPageSize; + NvU32 i; + + NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _memoryfabricGetPhysAttrsUsingFabricMemdesc(pGpu, + pFabricVAS, pFabricMemDesc, pParams->offset, + &physPageSize)); + + mappingPageSize = NV_MIN(physPageSize, + memdescGetPageSize(pFabricMemDesc, AT_GPU)); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + NV_IS_ALIGNED64(pParams->offset, mappingPageSize), + NV_ERR_INVALID_ARGUMENT); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pParams->offset < memdescGetSize(pFabricMemDesc), + NV_ERR_INVALID_ARGUMENT); + + memdescGetPhysAddrsForGpu(pFabricMemDesc, pGpu, AT_GPU, pParams->offset, + mappingPageSize, 1, &fabricAddr); + + pageLevelInfoParams.virtAddress = fabricAddr; + pageLevelInfoParams.pageSize = mappingPageSize; + + NV_ASSERT_OK_OR_RETURN(fabricvaspaceGetPageLevelInfo(pFabricVAS, pGpu, + &pageLevelInfoParams)); + + pParams->numLevels = pageLevelInfoParams.numLevels; + for (i = 0; i < pParams->numLevels; i++) + { + portMemCopy(&pParams->levels[i], sizeof(pParams->levels[i]), + &pageLevelInfoParams.levels[i], + sizeof(pageLevelInfoParams.levels[i])); + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/mem_mgr/mem_list.c b/src/nvidia/src/kernel/mem_mgr/mem_list.c index f8e49bb051..03a73fbd9a 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_list.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_list.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -419,15 +419,23 @@ memlistConstruct_IMPL NvU64 baseOffset = 0; NvU64 trueLength; NvU32 hwResId = 0; - NvU32 pageSize = 0; + NvU64 pageSize = 0; RM_ATTR_PAGE_SIZE pageSizeAttr; FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; HWRESOURCE_INFO *pHwResource = NULL; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - Heap *pHeap = vidmemGetHeap(pGpu, hClient, NV_FALSE); + Heap *pHeap; NvBool bCallingContextPlugin; + RsResourceRef *pDeviceRef; + + NV_ASSERT_OK_OR_RETURN( + refFindAncestorOfType(pResourceRef, classId(Device), &pDeviceRef)); + + pHeap = vidmemGetHeap(pGpu, + dynamicCast(pDeviceRef->pResource, Device), + NV_FALSE); // // When guest RM client doesn't subscribe to MIG partition and requests for vidmem allocation @@ -580,6 +588,12 @@ memlistConstruct_IMPL // only a kernel client can request for a protected allocation if (pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED) { + if (privLevel < RS_PRIV_LEVEL_KERNEL) + { + status = NV_ERR_INSUFFICIENT_PERMISSIONS; + NV_PRINTF(LEVEL_ERROR, "only kernel clients may request for a protected allocation\n"); + goto done_fbmem; + } pFbAllocInfo->bIsKernelAlloc = NV_TRUE; } diff --git a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c index c27242bcbe..b1ab93afd2 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -434,7 +434,7 @@ _memMulticastFabricSendInbandTeamSetupRequestUnderlock NvU64 fmCaps; NV_STATUS status = NV_OK; - status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps); + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps); if (status != NV_OK) return status; @@ -455,7 +455,7 @@ _memMulticastFabricSendInbandTeamReleaseRequestUnderLock NvU64 fmCaps; NV_STATUS status = NV_OK; - status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps); + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps); if (status != NV_OK) return status; @@ -727,6 +727,82 @@ _memMulticastFabricInstallMemDescUnderLock _memMulticastFabricDescriptorFlushClientsUnderLock(pMulticastFabricDesc); } +static NV_STATUS +_memorymulticastFabricAllocVasUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEMORY_DESCRIPTOR *pFabricMemDesc +) +{ + NV_STATUS status = NV_OK; + FABRIC_VASPACE *pFabricVAS; + MEM_MULTICAST_FABRIC_GPU_INFO *pGpuInfo; + VAS_ALLOC_FLAGS flags = { 0 }; + NvU64 gpuProbeHandle; + + for (pGpuInfo = listHead(&pMulticastFabricDesc->gpuInfoList); + pGpuInfo != NULL; + pGpuInfo = listNext(&pMulticastFabricDesc->gpuInfoList, pGpuInfo)) + { + OBJGPU *pGpu = pGpuInfo->pGpu; + + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + if (pFabricVAS == NULL) + { + status = NV_ERR_INVALID_STATE; + goto cleanup; + } + + // + // The fabric handle might not be available or have changed, if fabric + // state was ever invalidated while MCFLA allocation was in progress. + // + status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfoKernel, + &gpuProbeHandle); + if ((status != NV_OK) || (pGpuInfo->gpuProbeHandle != gpuProbeHandle)) + { + NV_PRINTF(LEVEL_ERROR, "Attached GPU's probe handle is stale\n"); + status = NV_ERR_INVALID_DEVICE; + goto cleanup; + } + + status = fabricvaspaceAllocMulticast(pFabricVAS, + memdescGetPageSize(pFabricMemDesc, AT_GPU), + pMulticastFabricDesc->alignment, + flags, pFabricMemDesc->_pteArray[0], + pMulticastFabricDesc->allocSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Fabric VA space alloc failed for GPU %d\n", + pGpuInfo->pGpu->gpuInstance); + goto cleanup; + } + + pGpuInfo->bMcflaAlloc = NV_TRUE; + } + + return NV_OK; + +cleanup: + for (pGpuInfo = listHead(&pMulticastFabricDesc->gpuInfoList); + pGpuInfo != NULL; + pGpuInfo = listNext(&pMulticastFabricDesc->gpuInfoList, pGpuInfo)) + { + if (pGpuInfo->bMcflaAlloc) + { + pFabricVAS = dynamicCast(pGpuInfo->pGpu->pFabricVAS, FABRIC_VASPACE); + + fabricvaspaceBatchFree(pFabricVAS, &pFabricMemDesc->_pteArray[0], + 1, 1); + + pGpuInfo->bMcflaAlloc = NV_FALSE; + } + } + + return status; +} + NV_STATUS _memMulticastFabricAttachGpuPostProcessorUnderLock ( @@ -768,6 +844,21 @@ _memMulticastFabricAttachGpuPostProcessorUnderLock status = _memMulticastFabricCreateMemDescUnderLock(pMulticastFabricDesc, mcAddressBase, &pMemDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate fabric memdesc\n"); + goto installMemDesc; + } + + status = _memorymulticastFabricAllocVasUnderLock(pMulticastFabricDesc, + pMemDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate fabric VAS\n"); + memdescDestroy(pMemDesc); + pMemDesc = NULL; + goto installMemDesc; + } installMemDesc: _memMulticastFabricInstallMemDescUnderLock(pMulticastFabricDesc, @@ -800,7 +891,8 @@ _memorymulticastfabricDestructUnderLock _memMulticastFabricDescriptorFreeUnderLock(pMulticastFabricDesc); } -void memorymulticastfabricTeamSetupResponseCallback +NV_STATUS +memorymulticastfabricTeamSetupResponseCallback ( NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams @@ -816,16 +908,15 @@ void memorymulticastfabricTeamSetupResponseCallback NvU64 mcAddressBase = 0; NvU64 mcAddressSize = 0; NvU8 *pRsvd = NULL; - NvU32 unused; OBJGPU *pGpu; NV_ASSERT(pInbandRcvParams != NULL); - NV_ASSERT(rmGpuGroupLockIsOwner(gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &unused)); + NV_ASSERT(rmGpuLockIsOwner()); if ((pGpu = gpumgrGetGpu(gpuInstance)) == NULL) { NV_ASSERT_FAILED("Invalid GPU instance"); - return; + return NV_ERR_INVALID_ARGUMENT; } pMcTeamSetupRspMsg = \ @@ -900,6 +991,8 @@ void memorymulticastfabricTeamSetupResponseCallback } fabricMulticastFabricOpsMutexRelease(pFabric); + + return NV_OK; } NV_STATUS @@ -972,6 +1065,7 @@ memorymulticastfabricCtrlAttachGpu_IMPL pGpu = GPU_RES_GET_GPU(pSubdevice); if (RMCFG_FEATURE_PLATFORM_WINDOWS || + gpuIsCCFeatureEnabled(pGpu) || IS_VIRTUAL(pGpu)) { NV_PRINTF(LEVEL_ERROR, @@ -980,7 +1074,7 @@ memorymulticastfabricCtrlAttachGpu_IMPL goto fail; } - status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfo, + status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfoKernel, &gpuProbeHandle); if (status != NV_OK) { @@ -1106,7 +1200,7 @@ _memorymulticastfabricValidatePhysMem { RsResourceRef *pPhysmemRef; MEMORY_DESCRIPTOR *pPhysMemDesc; - NvU32 physPageSize; + NvU64 physPageSize; NV_STATUS status; status = serverutilGetResourceRef(RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), @@ -1185,28 +1279,7 @@ memorymulticastfabricCtrlAttachMem_IMPL pFabricMemDesc = pMulticastFabricDesc->pMemDesc; NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_STATE); - // - // No need to cleanup this MCFLA state on any further failure. We expect - // to get this cleaned up on object destruction only. - // - if (!pGpuInfo->bMcflaAlloc) - { - VAS_ALLOC_FLAGS flags = { 0 }; - - status = fabricvaspaceAllocMulticast(pFabricVAS, - memdescGetPageSize(pFabricMemDesc, AT_GPU), - pMulticastFabricDesc->alignment, - flags, pFabricMemDesc->_pteArray[0], - pMulticastFabricDesc->allocSize); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Fabric VA space alloc failed! for GPU\n"); - return status; - } - - pGpuInfo->bMcflaAlloc = NV_TRUE; - } + NV_ASSERT_OR_RETURN(pGpuInfo->bMcflaAlloc, NV_ERR_INVALID_STATE); status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, &hDupedPhysMem, diff --git a/src/nvidia/src/kernel/mem_mgr/phys_mem.c b/src/nvidia/src/kernel/mem_mgr/phys_mem.c index c43d0aaab8..a011309b1c 100644 --- a/src/nvidia/src/kernel/mem_mgr/phys_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/phys_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/heap.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/bus/kern_bus.h" #include "gpu/device/device.h" #include "rmapi/client.h" #include "virtualization/hypervisor/hypervisor.h" @@ -67,6 +68,7 @@ physmemConstruct_IMPL NvU32 attr2 = 0; const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); @@ -106,7 +108,17 @@ physmemConstruct_IMPL attr2 |= DRF_DEF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _2MB); break; default: - attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _BIG); + if (bCompressedKind && + pKernelBus->bar1[GPU_GFID_PF].bStaticBar1Enabled) + { + NV_ASSERT_OR_RETURN(kgmmuIsHugePageSupported(pKernelGmmu), NV_ERR_INVALID_ARGUMENT); + attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _HUGE); + attr2 |= DRF_DEF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _2MB); + } + else + { + attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _BIG); + } break; } diff --git a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c index 0874c1e5f0..93133ab73e 100644 --- a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c +++ b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c @@ -82,21 +82,23 @@ */ typedef enum { - RM_POOL_IDX_512M = 0, - RM_POOL_IDX_2M = 1, - RM_POOL_IDX_256K = 2, - RM_POOL_IDX_128K = 3, - RM_POOL_IDX_64K = 4, - RM_POOL_IDX_8K = 5, - RM_POOL_IDX_4K = 6, - RM_POOL_IDX_256B = 7, + RM_POOL_IDX_512M, + RM_POOL_IDX_2M, + RM_POOL_IDX_256K, + RM_POOL_IDX_128K, + RM_POOL_IDX_64K, + RM_POOL_IDX_8K, + RM_POOL_IDX_4K, + RM_POOL_IDX_256B, NUM_POOLS // This should always be the last entry! }POOL_IDX; /*! * This array contains the alloction sizes (in bytes) of each pool. */ -static const NvU64 poolAllocSizes[] = {0x20000000, 0x200000, 0x40000, 0x20000, 0x10000, 0x2000, 0x1000, 0x100}; +static const NvU64 poolAllocSizes[] = { + 0x20000000, 0x200000, 0x40000, 0x20000, 0x10000, 0x2000, 0x1000, 0x100 +}; #define POOL_CONFIG_POOL_IDX 0 #define POOL_CONFIG_CHUNKSIZE_IDX 1 @@ -178,7 +180,7 @@ struct RM_POOL_ALLOC_MEM_RESERVE_INFO */ NvBool bTrimOnFree; - /*! + /*! * Allocate pool in protected memory */ NvBool bProtected; @@ -227,11 +229,14 @@ allocUpstreamTopPool } status = pmaAllocatePages(pMemReserveInfo->pPma, - (NvU32)(pMemReserveInfo->pmaChunkSize/PMA_CHUNK_SIZE_64K), + pMemReserveInfo->pmaChunkSize/PMA_CHUNK_SIZE_64K, PMA_CHUNK_SIZE_64K, &allocOptions, &pPage->address); - NV_ASSERT_OR_RETURN((NV_OK == status), status); + if (status != NV_OK) + { + return status; + } pPage->pMetadata = NULL; @@ -693,8 +698,7 @@ rmMemPoolAllocate if (status != NV_OK) { listRemove(pPageHandleList, pPageHandle); - NV_ASSERT_OR_GOTO((NV_OK == status), done); - pPageHandle = NULL; + goto done; } memdescDescribe(pMemDesc, ADDR_FBMEM, pPageHandle->address, pMemDesc->Size); diff --git a/src/nvidia/src/kernel/mem_mgr/standard_mem.c b/src/nvidia/src/kernel/mem_mgr/standard_mem.c index 6c0e67fafd..cca4241c94 100644 --- a/src/nvidia/src/kernel/mem_mgr/standard_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/standard_mem.c @@ -146,7 +146,7 @@ NV_STATUS stdmemValidateParams { NV_PRINTF(LEVEL_ERROR, "Encryption requested for video memory on a non-0FB chip;\n"); - return NV_ERR_INVALID_ARGUMENT; + return NV_ERR_INVALID_ARGUMENT; } if (FLD_TEST_DRF(OS32, _ATTR2, _ALLOCATE_FROM_SUBHEAP, _YES, pAllocData->attr2)) @@ -256,7 +256,7 @@ stdmemQueryPageSize // Control calls for system memory objects maintained outside the heap. // -NvU32 stdmemGetSysmemPageSize_IMPL(OBJGPU * pGpu, StandardMemory *pStdMemory) +NvU64 stdmemGetSysmemPageSize_IMPL(OBJGPU * pGpu, StandardMemory *pStdMemory) { return GPU_GET_MEMORY_MANAGER(pGpu)->sysmemPageSize; } diff --git a/src/nvidia/src/kernel/mem_mgr/system_mem.c b/src/nvidia/src/kernel/mem_mgr/system_mem.c index 6c44fe41bd..84b4ba763a 100644 --- a/src/nvidia/src/kernel/mem_mgr/system_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/system_mem.c @@ -209,6 +209,15 @@ sysmemConstruct_IMPL memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT, NV_TRUE); + if ((sysGetStaticConfig(SYS_GET_INSTANCE()))->bOsSevEnabled && + gpuIsCCorApmFeatureEnabled(pGpu) && + FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, + pAllocData->attr2)) + { + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, + NV_TRUE); + } + memdescSetGpuCacheAttrib(pMemDesc, gpuCacheAttrib); rmStatus = memdescAlloc(pMemDesc); @@ -476,7 +485,7 @@ sysmemAllocResources // While replaying a trace, it is possible for the playback OS to have a smaller page size // than the capture OS so if we're running a replay where the requested page size is larger, // assume this is a contiguous piece of memory, if contiguity is not specified. - // + // if (FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, _DEFAULT, pVidHeapAlloc->attr)) { if ((FLD_TEST_DRF(OS32, _ATTR, _PAGE_SIZE, _BIG, pVidHeapAlloc->attr) || diff --git a/src/nvidia/src/kernel/mem_mgr/vaddr_list.c b/src/nvidia/src/kernel/mem_mgr/vaddr_list.c index 6a4be2396f..1c6705fde9 100644 --- a/src/nvidia/src/kernel/mem_mgr/vaddr_list.c +++ b/src/nvidia/src/kernel/mem_mgr/vaddr_list.c @@ -561,7 +561,7 @@ vaListFindVa(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 *pVaddr) * * @return NV_ERR_OBJECT_NOT_FOUND if VAS not in list */ -NV_STATUS +NV_STATUS vaListGetRefCount(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 *pRefCount) { NV_STATUS status = NV_OK; @@ -620,7 +620,7 @@ vaListGetRefCount(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 *pRefCount) * * @return NV_ERR_OBJECT_NOT_FOUND if VAS not in list */ -NV_STATUS +NV_STATUS vaListSetRefCount(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 refCount) { NV_STATUS status = NV_OK; diff --git a/src/nvidia/src/kernel/mem_mgr/video_mem.c b/src/nvidia/src/kernel/mem_mgr/video_mem.c index 3ca0ef634c..a122a24558 100644 --- a/src/nvidia/src/kernel/mem_mgr/video_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/video_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -34,6 +34,7 @@ #include "diagnostics/gpu_acct.h" #include "Nvcm.h" #include "gpu/bus/third_party_p2p.h" +#include "gpu/bus/kern_bus.h" #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER @@ -64,7 +65,7 @@ _vidmemQueryAlignment MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_STATUS rmStatus = NV_OK; NvU64 size = pAllocData->size; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvU64 align = 0; NvU32 retAttr = pAllocData->attr; NvU32 retAttr2 = pAllocData->attr2; @@ -126,7 +127,7 @@ _vidmemPmaAllocate NvU64 size = 0; NvU32 pageCount; NvU32 pmaInfoSize; - NvU32 pageSize; + NvU64 pageSize; NV_STATUS status; NvU64 sizeAlign = 0; PMA_ALLOCATION_OPTIONS allocOptions = {0}; @@ -134,12 +135,27 @@ _vidmemPmaAllocate _PHYSICALITY, _NONCONTIGUOUS, pAllocData->attr); NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + NvBool bCompressed = !FLD_TEST_DRF(OS32, _ATTR, _COMPR, + _NONE, pAllocData->attr); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 gfid; // LOCK: acquire device lock status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM_PMA); NV_ASSERT_OR_RETURN(status == NV_OK, status); + if (bCompressed && + (vgpuGetCallingContextGfid(pGpu, &gfid) == NV_OK) && + pKernelBus->bar1[gfid].bStaticBar1Enabled) + { + // Override the attr to use 2MB page size + pAllocData->attr = FLD_SET_DRF(OS32, _ATTR, _PAGE_SIZE, _HUGE, pAllocData->attr); + + NV_PRINTF(LEVEL_INFO, + "Overrode the page size to 2MB on this compressed vidmem for the static bar1\n"); + } + NV_PRINTF(LEVEL_INFO, "PMA input\n"); NV_PRINTF(LEVEL_INFO, " Owner: 0x%x\n", pAllocData->owner); NV_PRINTF(LEVEL_INFO, " hMemory: 0x%x\n", pAllocRequest->hMemory); @@ -278,7 +294,7 @@ _vidmemPmaAllocate pAllocRequest->pPmaAllocInfo[subdevInst]->flags = allocOptions.flags; NV_PRINTF(LEVEL_INFO, "\nNVRM: Size requested: 0x%llx bytes\n", size); - NV_PRINTF(LEVEL_INFO, " PageSize: 0x%x bytes\n", pageSize); + NV_PRINTF(LEVEL_INFO, " PageSize: 0x%llx bytes\n", pageSize); NV_PRINTF(LEVEL_INFO, " PageCount: 0x%x\n", pageCount); NV_PRINTF(LEVEL_INFO, " Actual Size: 0x%llx\n", pAllocRequest->pPmaAllocInfo[subdevInst]->allocSize); @@ -380,7 +396,7 @@ Heap* vidmemGetHeap ( OBJGPU *pGpu, - NvHandle hClient, + Device *pDevice, NvBool bSubheap ) { @@ -400,7 +416,8 @@ vidmemGetHeap KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); Heap *pMemoryPartitionHeap = NULL; - status = kmigmgrGetMemoryPartitionHeapFromClient(pGpu, pKernelMIGManager, hClient, &pMemoryPartitionHeap); + status = kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, pKernelMIGManager, pDevice, + &pMemoryPartitionHeap); if (status == NV_OK) { if (pMemoryPartitionHeap != NULL) @@ -409,8 +426,8 @@ vidmemGetHeap else { NV_PRINTF(LEVEL_ERROR, - "failed to get memory partition heap for hClient = 0x%x\n", - hClient); + "failed to get memory partition heap for hClient = 0x%x, hDevice = 0x%x\n", + RES_GET_CLIENT_HANDLE(pDevice), RES_GET_HANDLE(pDevice)); return NULL; } } @@ -488,6 +505,8 @@ vidmemConstruct_IMPL HWRESOURCE_INFO hwResource; RsClient *pRsClient = pCallContext->pClient; RsResourceRef *pResourceRef = pCallContext->pResourceRef; + RsResourceRef *pDeviceRef; + Device *pDevice; NvU32 gpuCacheAttrib; NvBool bIsPmaAlloc = NV_FALSE; NvU64 sizeOut; @@ -500,6 +519,11 @@ vidmemConstruct_IMPL FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; NV_STATUS rmStatus = NV_OK; + NV_ASSERT_OK_OR_RETURN( + refFindAncestorOfType(pResourceRef, classId(Device), &pDeviceRef)); + + pDevice = dynamicCast(pDeviceRef->pResource, Device); + if (RS_IS_COPY_CTOR(pParams)) { if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance) && !rmGpuLockIsOwner()) @@ -524,9 +548,28 @@ vidmemConstruct_IMPL stdmemDumpInputAllocParams(pAllocData, pCallContext); bSubheap = FLD_TEST_DRF(OS32, _ATTR2, _ALLOCATE_FROM_SUBHEAP, _YES, pAllocData->attr2); - pHeap = vidmemGetHeap(pGpu, hClient, bSubheap); + pHeap = vidmemGetHeap(pGpu, pDevice, bSubheap); NV_CHECK_OR_RETURN(LEVEL_INFO, pHeap != NULL, NV_ERR_INVALID_STATE); + if (gpuIsCCorApmFeatureEnabled(pGpu) && + !FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, pAllocData->attr2)) + { + pAllocData->flags |= NVOS32_ALLOC_FLAGS_PROTECTED; + } + else if (gpuIsCCFeatureEnabled(pGpu) && + FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, pAllocData->attr2)) + { + // CC-TODO: Remove this once non-CPR regions are created + NV_PRINTF(LEVEL_ERROR, "Non-CPR region not yet created\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + else if (!gpuIsCCorApmFeatureEnabled(pGpu) && + FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _PROTECTED, pAllocData->attr2)) + { + NV_PRINTF(LEVEL_ERROR, "Protected memory not enabled but PROTECTED flag is set by client"); + return NV_ERR_INVALID_ARGUMENT; + } + pAllocRequest->classNum = NV01_MEMORY_LOCAL_USER; pAllocRequest->pUserParams = pAllocData; pAllocRequest->hMemory = pResourceRef->hResource; @@ -557,7 +600,7 @@ vidmemConstruct_IMPL { SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) pAllocRequest->pGpu = pGpu; - rmStatus = _vidmemPmaAllocate(vidmemGetHeap(pGpu, hClient, NV_FALSE), pAllocRequest); + rmStatus = _vidmemPmaAllocate(vidmemGetHeap(pGpu, pDevice, NV_FALSE), pAllocRequest); if (NV_OK != rmStatus) SLI_LOOP_GOTO(done); SLI_LOOP_END; @@ -659,7 +702,7 @@ vidmemConstruct_IMPL SLI_LOOP_GOTO(done); rmStatus = vidmemAllocResources(pGpu, pMemoryManager, pAllocRequest, pFbAllocInfo, - vidmemGetHeap(pGpu, hClient, NV_FALSE)); + vidmemGetHeap(pGpu, pDevice, NV_FALSE)); if (rmStatus != NV_OK) SLI_LOOP_GOTO(done); @@ -740,6 +783,21 @@ vidmemConstruct_IMPL SLI_LOOP_END; } + // + // Set the unprotected flag in memdesc. Some control calls will use + // this flag to determine if this memory lies in the protected or + // unprotected region and use that to gather statistics like total + // protected and unprotected memory usage by different clients, etc + // + if (gpuIsCCorApmFeatureEnabled(pGpu) && + FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, pAllocData->attr2)) + { + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) + memdescSetFlag(memdescGetMemDescFromGpu(pTopLevelMemDesc, pGpu), + MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY, NV_TRUE); + SLI_LOOP_END; + } + // // Video memory is always locally transparently cached. It does not require // any cache managment. Marked cached unconditionally. Non-coherent peer @@ -871,9 +929,8 @@ vidmemConstruct_IMPL if (bSmcGpuPartitioningEnabled) { NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &partitionRef), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &partitionRef), done); bGlobalInfo = NV_FALSE; } @@ -919,7 +976,7 @@ vidmemConstruct_IMPL SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) if (pAllocRequest->pPmaAllocInfo[gpumgrGetSubDeviceInstanceFromGpu(pGpu)]) - vidmemPmaFree(pGpu, vidmemGetHeap(pGpu, hClient, NV_FALSE), + vidmemPmaFree(pGpu, vidmemGetHeap(pGpu, pDevice, NV_FALSE), pAllocRequest->pPmaAllocInfo[gpumgrGetSubDeviceInstanceFromGpu(pGpu)], 0); SLI_LOOP_END; } @@ -1288,12 +1345,13 @@ vidmemCheckCopyPermissions_IMPL ( VideoMemory *pVideoMemory, OBJGPU *pDstGpu, - NvHandle hDstClient + Device *pDstDevice ) { Memory *pMemory = staticCast(pVideoMemory, Memory); OBJGPU *pSrcGpu = pMemory->pGpu; NvHandle hSrcClient = RES_GET_CLIENT_HANDLE(pVideoMemory); + NvHandle hDstClient = RES_GET_CLIENT_HANDLE(pDstDevice); KernelMIGManager *pSrcKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pSrcGpu); KernelMIGManager *pDstKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pDstGpu); NvBool bSrcClientKernel = (rmclientGetCachedPrivilegeByHandle(hSrcClient) >= RS_PRIV_LEVEL_KERNEL); @@ -1322,8 +1380,8 @@ vidmemCheckCopyPermissions_IMPL // Get memory partition heap from both clients and compare Heap *pDstClientHeap = NULL; NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, - kmigmgrGetMemoryPartitionHeapFromClient(pDstGpu, pDstKernelMIGManager, hDstClient, - &pDstClientHeap)); + kmigmgrGetMemoryPartitionHeapFromDevice(pDstGpu, pDstKernelMIGManager, + pDstDevice, &pDstClientHeap)); // Make sure memory is coming from same heaps if (pDstClientHeap != pMemory->pHeap) @@ -1341,14 +1399,21 @@ vidmemCheckCopyPermissions_IMPL // MIG_INSTANCE_REF srcInstRef; MIG_INSTANCE_REF dstInstRef; + RsResourceRef *pSrcDeviceRef; + Device *pSrcDevice; + + NV_ASSERT_OK_OR_RETURN( + refFindAncestorOfType(RES_GET_REF(pMemory), classId(Device), &pSrcDeviceRef)); + + pSrcDevice = dynamicCast(pSrcDeviceRef->pResource, Device); // Check instance subscription of source and destination clients NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, - kmigmgrGetInstanceRefFromClient(pSrcGpu, pSrcKernelMIGManager, hSrcClient, - &srcInstRef)); + kmigmgrGetInstanceRefFromDevice(pSrcGpu, pSrcKernelMIGManager, + pSrcDevice, &srcInstRef)); NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, - kmigmgrGetInstanceRefFromClient(pDstGpu, pDstKernelMIGManager, hDstClient, - &dstInstRef)); + kmigmgrGetInstanceRefFromDevice(pDstGpu, pDstKernelMIGManager, + pDstDevice, &dstInstRef)); // // Memory duping is allowed accross compute instances. so ignore diff --git a/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c b/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c index 7026b93d8d..6fed7cfa53 100644 --- a/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c +++ b/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c @@ -126,7 +126,7 @@ vmrangeConstruct_IMPL if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { NV_RM_RPC_ALLOC_OBJECT(pGpu, hClient, hParent, hMemory, class, - pAllocData, status); + pAllocData, sizeof(*pAllocData), status); if (status != NV_OK) { memdescDestroy(pMemDesc); diff --git a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c index 66b8a45cb2..6c33a5e6ca 100644 --- a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c @@ -1088,18 +1088,25 @@ _virtmemAllocKernelMapping else { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NvHandle hClient = NV01_NULL_OBJECT; + Device *pDevice = NULL; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); if ((pCallContext != NULL) && (pCallContext->pClient != NULL)) { - hClient = pCallContext->pClient->hClient; + RsResourceRef *pDeviceRef = NULL; + + status = refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef); + if (status == NV_OK) + { + pDevice = dynamicCast(pDeviceRef->pResource, Device); + } } status = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemoryInfo->pMemDesc, offset, &pDmaMappingInfo->FbAperture[gpuSubDevInst], &pDmaMappingInfo->FbApertureLen[gpuSubDevInst], - BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient); + BUS_MAP_FB_FLAGS_MAP_UNICAST, pDevice); if (status != NV_OK) { @@ -1321,6 +1328,7 @@ virtmemMapTo_IMPL // Different cases for vidmem & system memory/fabric memory. bIsSysmem = (tgtAddressSpace == ADDR_SYSMEM); + bIsSysmem = bIsSysmem || (tgtAddressSpace == ADDR_EGM); if (bIsSysmem || (tgtAddressSpace == ADDR_FABRIC_MC) || diff --git a/src/nvidia/src/kernel/os/os_init.c b/src/nvidia/src/kernel/os/os_init.c index 4af4173757..88c1fd9ec6 100644 --- a/src/nvidia/src/kernel/os/os_init.c +++ b/src/nvidia/src/kernel/os/os_init.c @@ -128,22 +128,13 @@ initWinNTStubOSFunctionPointers(OBJOS *pOS) pOS->osQueueWorkItem = stubOsQueueWorkItem; pOS->osQueueWorkItemWithFlags = stubOsQueueWorkItemWithFlags; pOS->osQueueSystemWorkItem = stubOsQueueSystemWorkItem; - pOS->osCallACPI_BCL = stubOsCallACPI_BCL; - pOS->osCallACPI_ON = stubOsCallACPI_ON; - pOS->osCallACPI_OFF = stubOsCallACPI_OFF; - pOS->osCallACPI_NVHG_GPUON = stubOsCallWMI_NVHG_GPUON; - pOS->osCallACPI_NVHG_GPUOFF = stubOsCallWMI_NVHG_GPUOFF; pOS->osCallACPI_NVHG_GPUSTA = stubOsCallWMI_NVHG_GPUSTA; pOS->osCallACPI_NVHG_MXDS = stubOsCallWMI_NVHG_MXDS; pOS->osCallACPI_NVHG_MXMX = stubOsCallWMI_NVHG_MXMX; pOS->osCallACPI_NVHG_DOS = stubOsCallWMI_NVHG_DOS; pOS->osCallACPI_NVHG_DCS = stubOsCallWMI_NVHG_DCS; pOS->osSetupVBlank = stubOsSetupVBlank; - pOS->osCallACPI_NBPS = stubOsCallACPI_NBPS; - pOS->osCallACPI_NBSL = stubOsCallACPI_NBSL; - pOS->osCallACPI_OPTM_GPUON = stubOsCallWMI_OPTM_GPUON; pOS->osGetUefiVariable = stubOsGetUefiVariable; - pOS->osCallACPI_LRST = stubOsCallACPI_LRST; } static void @@ -155,7 +146,6 @@ initMacOSCoreOSFunctionPointers(OBJOS *pOS) pOS->osNv_rdmsr = stubOsnv_rdmsr; pOS->osNv_wrmsr = stubOsnv_wrmsr; pOS->osRobustChannelsDefaultState = stubOsRobustChannelsDefaultState; - pOS->osCallACPI_BCL = stubOsCallACPI_BCL; pOS->osGetUefiVariable = stubOsGetUefiVariable; } @@ -461,7 +451,7 @@ NvU32 osGetCpuVaAddrShift(void) { NvU64 maxUserVa = osGetMaxUserVa(); - + // // Add 1 to account for kernel VA space, on the assumption // that kernel VA space is the top half of the address space. diff --git a/src/nvidia/src/kernel/os/os_stubs.c b/src/nvidia/src/kernel/os/os_stubs.c index 5b1f42445d..1d8045543e 100644 --- a/src/nvidia/src/kernel/os/os_stubs.c +++ b/src/nvidia/src/kernel/os/os_stubs.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -145,49 +145,36 @@ NV_STATUS osCallACPI_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU8 *pInOut) return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_BCL(OBJGPU *pGpu, NvU32 acpiId, NvU32 *pOut, NvU16 *size) +NV_STATUS osCallACPI_BCL(OBJGPU *pGpu, NvU32 acpiId, NvU32 *pOut, NvU16 *size) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_ON(OBJGPU *pGpu, NvU32 uAcpiId) +NV_STATUS osCallACPI_ON(OBJGPU *pGpu, NvU32 uAcpiId) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_OFF(OBJGPU *pGpu, NvU32 uAcpiId) +NV_STATUS osCallACPI_OFF(OBJGPU *pGpu, NvU32 uAcpiId) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_NBPS(OBJGPU *pGpu, NvU8 *pOut, NvU32 *pOutSize) +NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *pGpu) { - *pOutSize = 0; return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_NBSL(OBJGPU *pGpu, NvU32 val) +NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *pGpu, NvU32 *pInOut) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_OPTM_GPUON(OBJGPU *pGpu) +NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *pGpu, NvU32 *pInOut) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_NVHG_GPUON(OBJGPU *pGpu, NvU32 *pInOut) -{ - //STUB_CHECK(225); - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallWMI_NVHG_GPUOFF(OBJGPU *pGpu, NvU32 *pInOut) -{ - //STUB_CHECK(226); - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS stubOsCallWMI_NVHG_GPUSTA(OBJGPU *pGpu, NvU32 *pInOut) { //STUB_CHECK(227); @@ -223,7 +210,7 @@ NV_STATUS osCallACPI_MXID(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallACPI_LRST(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) +NV_STATUS osCallACPI_LRST(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) { return NV_ERR_NOT_SUPPORTED; } @@ -425,6 +412,23 @@ osTegraSocDsiPanelCleanup { return; } + +NV_STATUS +osTegraSocHspSemaphoreAcquire +( + NvU32 ownerId, + NvBool bAcquire, + NvU64 timeout +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NvBool +osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo) +{ + return NV_TRUE; +} #endif NV_STATUS @@ -438,7 +442,6 @@ osTegraSocParseFixedModeTimings return NV_OK; } - NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection) { return NV_OK; @@ -659,28 +662,6 @@ osGetNvGlobalRegistryDword return NV_ERR_NOT_SUPPORTED; } -NvU32 osGetDynamicPowerSupportMask(void) -{ - return 0; -} - -void osUnrefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo) -{ - return; -} - -NV_STATUS osRefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo) -{ - return NV_OK; -} - -void osClientGcoffDisallowRefcount( - OS_GPU_INFO *pArg1, - NvBool arg2 -) -{ -} - #if !RMCFG_FEATURE_PLATFORM_DCE /* dce_core_rm_clk_reset.c */ && \ (!RMCFG_FEATURE_PLATFORM_UNIX || !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY || \ RMCFG_FEATURE_DCE_CLIENT_RM /* osSocNvDisp.c */ ) @@ -796,22 +777,16 @@ osTegraSocPmUnpowergate { return NV_ERR_NOT_SUPPORTED; } -#endif -#if !(RMCFG_FEATURE_PLATFORM_UNIX) || \ - (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) NvU32 osTegraSocFuseRegRead(NvU32 addr) { return 0; } +#endif -NV_STATUS -osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout) -{ - return NV_ERR_NOT_SUPPORTED; -} - +#if !(RMCFG_FEATURE_PLATFORM_UNIX) || \ + (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pOsGpuInfo, NvU32 link_rate, NvU32 lanes) { diff --git a/src/nvidia/src/kernel/platform/acpi_common.c b/src/nvidia/src/kernel/platform/acpi_common.c index 2c2de63970..1459d86383 100644 --- a/src/nvidia/src/kernel/platform/acpi_common.c +++ b/src/nvidia/src/kernel/platform/acpi_common.c @@ -358,13 +358,13 @@ _getRemappedDsmSubfunction // Use NV_ASSERT_OR_ELSE_STR for embedded %. // NV_ASSERT_OR_ELSE_STR( - !(NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) % (ACPI_DSM_FUNCTION_COUNT + 1)), - "!(NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) %% (ACPI_DSM_FUNCTION_COUNT + 1))", + !(NV_ARRAY_ELEMENTS(genDsmSubFuncRemapTable) % (ACPI_DSM_FUNCTION_COUNT + 1)), + "!(NV_ARRAY_ELEMENTS(genDsmSubFuncRemapTable) %% (ACPI_DSM_FUNCTION_COUNT + 1))", return NV_ERR_INVALID_ARGUMENT); // find the event in the table i = 0; - while (i <= (NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) - ACPI_DSM_FUNCTION_COUNT - 1)) + while (i <= (NV_ARRAY_ELEMENTS(genDsmSubFuncRemapTable) - ACPI_DSM_FUNCTION_COUNT - 1)) { if (acpiDsmSubFunction == genDsmSubFuncRemapTable[i]) { @@ -857,7 +857,7 @@ _acpiDsmSupportedFuncCacheInit } } -static void +static void _acpiDsmCallbackInit ( OBJGPU *pGpu @@ -963,7 +963,7 @@ _acpiDsmCallbackInit * * @returns */ -static void +static void _acpiDsmCapsInit ( OBJGPU *pGpu diff --git a/src/nvidia/src/kernel/platform/chipset/chipset.c b/src/nvidia/src/kernel/platform/chipset/chipset.c index 0878531f13..315aedb1b7 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset.c @@ -191,7 +191,7 @@ clInitMappingPciBusDevice_IMPL if (gpuGetDBDF(pGpu) == 0) { - if (!(IS_SIMULATION(pGpu)|| IS_SIM_MODS(GPU_GET_OS(pGpu))) + if (!(IS_SIMULATION(pGpu)|| IS_SIM_MODS(GPU_GET_OS(pGpu))) || (bFoundDevice == NV_FALSE)) { NV_PRINTF(LEVEL_ERROR, @@ -210,7 +210,7 @@ clInitMappingPciBusDevice_IMPL static void getSubsystemFromPCIECapabilities ( NvU32 domain, - NvU8 bus, + NvU8 bus, NvU8 device, NvU8 func, NvU16 *subvendorID, @@ -605,6 +605,65 @@ clIsL1MaskEnabledForUpstreamPort_IMPL return bEnable; } +/*! + * @brief Check if L0s mask is enabled for upstream component + * + * @param[in] pGpu GPU object pointer + * @param[in] pCl CL object pointer + * + * @return NV_TRUE if mask is enabled (implies L0s is disabled) + */ +NvBool +clIsL0sMaskEnabledForUpstreamPort_IMPL +( + OBJGPU *pGpu, + OBJCL *pCl +) +{ + NvU32 linkCtrl; + NvBool bEnable = NV_FALSE; + + if (!pGpu->gpuClData.upstreamPort.addr.valid) + { + if (!pGpu->gpuClData.rootPort.addr.valid) + { + bEnable = NV_TRUE; + } + else + { + if (clPcieReadPortConfigReg(pGpu, pCl, &pGpu->gpuClData.rootPort, + CL_PCIE_LINK_CTRL_STATUS, &linkCtrl) != NV_OK) + { + bEnable = NV_TRUE; + } + else + { + if (!(linkCtrl & CL_PCIE_LINK_CTRL_STATUS_ASPM_L0S_BIT)) + { + bEnable = NV_TRUE; + } + } + } + } + else + { + if (clPcieReadPortConfigReg(pGpu, pCl, &pGpu->gpuClData.upstreamPort, + CL_PCIE_LINK_CTRL_STATUS, &linkCtrl) != NV_OK) + { + bEnable = NV_TRUE; + } + else + { + if (!(linkCtrl & CL_PCIE_LINK_CTRL_STATUS_ASPM_L0S_BIT)) + { + bEnable = NV_TRUE; + } + } + } + + return bEnable; +} + NV_STATUS clInit_IMPL( OBJGPU *pGpu, @@ -753,6 +812,7 @@ void clSyncWithGsp_IMPL(OBJCL *pCl, GspSystemInfo *pGSI) CL_SYNC_PDB(PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE); CL_SYNC_PDB(PDB_PROP_CL_IS_EXTERNAL_GPU); CL_SYNC_PDB(PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR); + CL_SYNC_PDB(PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS); #undef CL_SYNC_PDB diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_info.c b/src/nvidia/src/kernel/platform/chipset/chipset_info.c index fcd531cd33..f0021559f0 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_info.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_info.c @@ -857,25 +857,6 @@ Intel_0685_setupFunc return NV_OK; } -// Intel Ice Lake platform -static NV_STATUS -Intel_IceLake_setupFunc -( - OBJCL *pCl -) -{ - OBJSYS *pSys = SYS_GET_INSTANCE(); - - // Intel IceLake - if ((pSys->cpuInfo.family == 0x6) && - (pSys->cpuInfo.model == 0x6a) && - (pSys->cpuInfo.stepping == 0x6)) - { - pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); - } - return NV_OK; -} - // Intel Z590 platform (Rocket Lake) static NV_STATUS Intel_4381_setupFunc @@ -966,6 +947,30 @@ Nvidia_T194_setupFunc return NV_OK; } +static NV_STATUS +Nvidia_TH500_setupFunc +( + OBJCL *pCl +) +{ + if (!pCl->FHBAddr.valid) + return NV_ERR_GENERIC; + + if (clInsertPcieConfigSpaceBase(pCl, 0, 0, 0, (NvU8)(PCI_MAX_BUSES - 1)) == NV_OK) + pCl->setProperty(pCl, PDB_PROP_CL_PCIE_CONFIG_ACCESSIBLE, NV_TRUE); + + // Enable Gen2 ASLM + pCl->setProperty(pCl, PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE, NV_TRUE); + + pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); + + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); + + _Set_ASPM_L0S_L1(pCl, NV_FALSE, NV_FALSE); + + return NV_OK; +} + static NV_STATUS SiS_656_setupFunc ( @@ -1118,15 +1123,6 @@ AMD_X370_setupFunc OBJCL *pCl ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - - // AMD Milan - if (pSys->cpuInfo.family == 0x19 && - pSys->cpuInfo.model == 0x1 && - pSys->cpuInfo.stepping == 0x1) - { - pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); - } // Set ASPM L0S\L1 properties _Set_ASPM_L0S_L1(pCl, NV_FALSE, NV_FALSE); diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c index 65c802ad70..f27711aeab 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c @@ -57,6 +57,7 @@ // static NV_STATUS objClInitPcieChipset(OBJGPU *, OBJCL *); +static void objClBuildPcieAtomicsAllowList(OBJGPU *, OBJCL *); static NvBool objClInitGpuPortData(OBJGPU *, OBJCL *pCl); static NV_STATUS objClSetPortCapsOffsets(OBJCL *, PORTDATA *); static NV_STATUS objClSetPortPcieEnhancedCapsOffsets(OBJCL *, PORTDATA *); @@ -193,6 +194,55 @@ addHwbcToList (OBJGPU *pGpu, OBJHWBC *pHWBC) return NV_OK; } +/*! @brief Build PCIe atomics allow list for x86 CPUs + * using CPU model and family. + * + * Building allow list using only CPU model and family helps with + * passthrough virtualization where the host and passthrough VM + * has the same CPU model and family unlike the chipset. + * For non-x86 CPUs, allow list is built only during chipset discovery. + * + * @param[in] pGpu GPU object pointer + * @param[in] pCl Core logic object pointer + * @return None + */ +static +void +objClBuildPcieAtomicsAllowList(OBJGPU *pGpu, OBJCL *pCl) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + + // For non-x86 CPUs, allow list is built during chipset discovery. + + // Intel IceLake + if ((pSys->cpuInfo.family == 0x6) && + (pSys->cpuInfo.model == 0x6a) && + (pSys->cpuInfo.stepping == 0x6)) + { + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); + } + // Intel SapphireRapids + else if ((pSys->cpuInfo.family == 0x6) && + (pSys->cpuInfo.model == 0x8f)) + { + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); + } + // AMD Milan + else if (pSys->cpuInfo.family == 0x19 && + pSys->cpuInfo.model == 0x1 && + pSys->cpuInfo.stepping == 0x1) + { + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); + } + // AMD Genoa + else if (pSys->cpuInfo.family == 0x19 && + pSys->cpuInfo.model == 0x11) + { + pCl->setProperty(pCl, PDB_PROP_CL_BUG_3562968_WAR_ALLOW_PCIE_ATOMICS, NV_TRUE); + } + return; +} + // // Determine which chipset we're using (from available options) // and initialize chipset-specific functions @@ -911,6 +961,8 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl) pCl->setProperty(pCl, PDB_PROP_CL_NOSNOOP_NOT_CAPABLE, NV_TRUE); } + objClBuildPcieAtomicsAllowList(pGpu, pCl); + objClInitPcieChipset(pGpu, pCl); // @@ -920,7 +972,7 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl) // kbifInitPcieDeviceControlStatus(pGpu, pKernelBif); - // + // // Probe root port PCIe atomic capabilities. // kbifProbePcieReqAtomicCaps_HAL should be called from here instead of // kbif construct because of the dependency on the chipset @@ -4476,6 +4528,37 @@ clPcieGetRootGenSpeed_IMPL return NV_OK; } +/*! + * @brief: Returns the support for CPM of the root node + */ +NvU32 +clGetChipsetL1ClockPMSupport_IMPL +( + OBJGPU *pGpu, + OBJCL *pCl +) +{ + void *handle; + NvU32 PCIECapPtr; + NvU32 linkCaps; + NvU32 clockPmSupport; + + handle = pGpu->gpuClData.rootPort.addr.handle; + if (handle == NULL) + { + return 0; + } + + PCIECapPtr = pGpu->gpuClData.rootPort.PCIECapPtr; + + linkCaps = osPciReadDword(handle, CL_PCIE_LINK_CAP - CL_PCIE_BEGIN + PCIECapPtr); + + // Read field 18:18 to get clock PM support + clockPmSupport = (linkCaps & CL_PCIE_LINK_CAP_CLOCK_PM_BIT); + + return clockPmSupport; +} + /*! * @brief: Returns the value of link_capabilities_2 of the downstream port * @@ -4617,7 +4700,7 @@ static NvU16 _clPcieGetPcieCapSize(void *deviceHandle, NvU16 capType, NvU16 capI { tempDword = osPciReadDword(deviceHandle, capOffset + capSize + PCI_ENHANCED_ALLOCATION_ENTRY_HEADER); tempDword = REF_VAL(PCI_ENHANCED_ALLOCATION_ENTRY_HEADER_ENTRY_SIZE, tempDword); - capSize += (NvU16)((tempDword + 1) * NV_SIZEOF32(NvU32)); + capSize += (NvU16)((tempDword + 1) * sizeof(NvU32)); } } break; @@ -4875,7 +4958,7 @@ static NvU16 _clPciePopulateCapMap(void * pDeviceHandle, NvU16 type, CL_PCIE_DC_ return 0; } // clear the capability map. - portMemSet(pCapMap, 0, NV_SIZEOF32(*pCapMap)); + portMemSet(pCapMap, 0, sizeof(*pCapMap)); // if there is not a valid device handle, we are done. if (pDeviceHandle == NULL) @@ -4996,14 +5079,14 @@ static NvU16 _clPcieCopyConfigSpaceDiagData(NvU8* pBuffer, NvU32 bufferSz, void } // do all the full dword reads - for (; (blockSz - dataSz) >= sizeof(NvU32); dataSz += NV_SIZEOF32(NvU32)) + for (; (blockSz - dataSz) >= sizeof(NvU32); dataSz += sizeof(NvU32)) { // read a dword of data *((NvU32*)pBuffer) = osPciReadDword(pDeviceHandle, offset); // update the references to the next data to be read/written. - pBuffer += NV_SIZEOF32(NvU32); - offset += NV_SIZEOF32(NvU32); + pBuffer += sizeof(NvU32); + offset += sizeof(NvU32); } // we are at the nearest dword boundary to the end of the block. @@ -5058,8 +5141,8 @@ NvU16 _clPcieSavePcieDiagnosticBlock(void *pDeviceHandle, CL_PCIE_DC_DIAGNOSTIC_ // do some parameter checks if ((pBuffer == NULL) - || ((blkOffset + NV_SIZEOF32(*pBlkHeader) + blkSize) > PCI_EXTENDED_CONFIG_SPACE_LENGTH) - || ((NV_SIZEOF32(*pBlkHeader) + blkSize) > size)) + || ((blkOffset + sizeof(*pBlkHeader) + blkSize) > PCI_EXTENDED_CONFIG_SPACE_LENGTH) + || ((sizeof(*pBlkHeader) + blkSize) > size)) { return 0; } @@ -5068,7 +5151,7 @@ NvU16 _clPcieSavePcieDiagnosticBlock(void *pDeviceHandle, CL_PCIE_DC_DIAGNOSTIC_ // copy the block header & update the size pBlkHeader = (CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY*)pBuffer; *pBlkHeader = *pScriptEntry; - collectedDataSize += NV_SIZEOF32(*pBlkHeader); + collectedDataSize += sizeof(*pBlkHeader); } if((pDeviceHandle != NULL) && (0 < blkSize) @@ -5119,7 +5202,7 @@ NvU16 _clPcieGetDiagnosticData(OBJGPU *pGpu, CL_PCIE_DC_DIAGNOSTIC_COLLECTION_EN { return 0; } - portMemSet(pPCIeHandles, 0, NV_SIZEOF32(pPCIeHandles)); + portMemSet(pPCIeHandles, 0, sizeof(pPCIeHandles)); // get PCIE Handles. pUpstreamPort = &pGpu->gpuClData.upstreamPort.addr; @@ -5142,7 +5225,7 @@ NvU16 _clPcieGetDiagnosticData(OBJGPU *pGpu, CL_PCIE_DC_DIAGNOSTIC_COLLECTION_EN { blkHeader = pScript[idx]; // verify there is space, & we can access the device. - if ((size - collectedDataSize) < (NV_SIZEOF32(blkHeader) + blkHeader.length)) + if ((size - collectedDataSize) < (sizeof(blkHeader) + blkHeader.length)) { // if this block doesn't fit, skip it but continue because another block might. continue; @@ -5300,6 +5383,6 @@ NvU16 clPcieGetGpuLostDiagnosticData_IMPL(OBJGPU *pGpu, OBJCL *pCl, NvU8 * pBuff }; return _clPcieGetDiagnosticData(pGpu, - gpuLostCollectionScript, NV_ARRAY_ELEMENTS32(gpuLostCollectionScript), + gpuLostCollectionScript, NV_ARRAY_ELEMENTS(gpuLostCollectionScript), pBuffer, size); } diff --git a/src/nvidia/src/kernel/platform/chipset/pci_pbi.c b/src/nvidia/src/kernel/platform/chipset/pci_pbi.c index 864ee939d2..998f728240 100644 --- a/src/nvidia/src/kernel/platform/chipset/pci_pbi.c +++ b/src/nvidia/src/kernel/platform/chipset/pci_pbi.c @@ -60,9 +60,9 @@ // Check to see if Post-box interface is found in PCI config space at the // specified base address // -// If the PBI capability was found in the PCI cap list then cap_base is the +// If the PBI capability was found in the PCI cap list then cap_base is the // PCI config offset of the capability. -// If the capability was not found in the PCI cap list then cap_base is zero, but +// If the capability was not found in the PCI cap list then cap_base is zero, but // we still check for PBI at a static location to support certain GPUs in the field. // static NV_STATUS pciPbiCheck(void *handle, NvU32 cap_base) @@ -76,7 +76,7 @@ static NV_STATUS pciPbiCheck(void *handle, NvU32 cap_base) } // -// Find the base of the PCI PBI capability and return the base. +// Find the base of the PCI PBI capability and return the base. // Returns 0 if PBI is not found in the PCI cap list. // static NvU32 pciPbiFindCapability(void *handle) @@ -87,7 +87,7 @@ static NvU32 pciPbiFindCapability(void *handle) // Walk the PCI capability list looking for a match for PBI while (cap_base != 0 && pciPbiCheck(handle, cap_base) != NV_OK) cap_base = osPciReadByte(handle, cap_base + 1); - + return cap_base; } @@ -183,7 +183,7 @@ static NV_STATUS pciPbiCheckStatusWait(void *handle, NvU32 cap_base) { poll_limit = PCI_PBI_POLL_STATIC; - // WAR for 2844918, extra delay is needed for early Ampere GA100 devices + // WAR for 2844918, extra delay is needed for early Ampere GA100 devices // which do not have PBI correctly linked in the PCI Capability list devid = osPciReadWord(handle, 0x2); for (i = 0; ampere_devid[i] != 0; i++) diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index ce8854d264..88747d5971 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -172,6 +172,7 @@ void RmInitCpuInfo(void) case AARCH64_VENDOR_PART(MARVELL, THUNDER_X2): case AARCH64_VENDOR_PART(HUAWEI, KUNPENG_920): case AARCH64_VENDOR_PART(ARM, BLUEFIELD): + case AARCH64_VENDOR_PART(ARM, BLUEFIELD3): // The Neoverse N1 is the same as Gravitron case AARCH64_VENDOR_PART(ARM, GRAVITRON2): case AARCH64_VENDOR_PART(FUJITSU, A64FX): @@ -183,6 +184,10 @@ void RmInitCpuInfo(void) case AARCH64_VENDOR_PART(ARM, CORTEX_A57): pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; break; + case AARCH64_VENDOR_PART(ARM, NEOVERSE_N2): + case AARCH64_VENDOR_PART(ARM, NEOVERSE_V2): + pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC; + break; default: pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; portDbgPrintf( diff --git a/src/nvidia/src/kernel/platform/cpu_arm_def.h b/src/nvidia/src/kernel/platform/cpu_arm_def.h index dfa8da2a50..185777505d 100644 --- a/src/nvidia/src/kernel/platform/cpu_arm_def.h +++ b/src/nvidia/src/kernel/platform/cpu_arm_def.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -78,9 +78,11 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_PRIMARY_PART_NUM_XGENE 0x0 #define CP_MIDR_PRIMARY_PART_NUM_CORTEX_A57 0xd07 #define CP_MIDR_PRIMARY_PART_NUM_CORTEX_A76 0xd0b +#define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_V2 0xd4f #define CP_MIDR_PRIMARY_PART_NUM_THUNDER_X2 0x0af #define CP_MIDR_PRIMARY_PART_NUM_KUNPENG_920 0xd01 #define CP_MIDR_PRIMARY_PART_NUM_BLUEFIELD 0xd08 +#define CP_MIDR_PRIMARY_PART_NUM_BLUEFIELD3 0xd42 #define CP_MIDR_PRIMARY_PART_NUM_GRAVITRON2 0xd0c #define CP_MIDR_PRIMARY_PART_NUM_A64FX 0x001 #define CP_MIDR_PRIMARY_PART_NUM_FT2000 0x662 @@ -88,6 +90,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_PRIMARY_PART_NUM_ALTRA 0x000 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1 +#define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49 // Cache Size Identification Register #define CP_CCSIDR "ccsidr_el1" diff --git a/src/nvidia/src/kernel/platform/hwbc.c b/src/nvidia/src/kernel/platform/hwbc.c index 15b126363c..0967f08a99 100644 --- a/src/nvidia/src/kernel/platform/hwbc.c +++ b/src/nvidia/src/kernel/platform/hwbc.c @@ -160,7 +160,7 @@ static NV_STATUS Plx_Pex8747_GetUpstreamBusSpeed(OBJHWBC *pPlx, OBJCL *pCl, NvU3 static RmPhysAddr Plx_Pex8747_GetBar0(OBJCL *pCl, OBJHWBC *pPlx); // -// static functions +// static functions // static OBJHWBC *objClFindUpperHWBC(OBJCL *, NBADDR, OBJHWBC *, RmPhysAddr); diff --git a/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c b/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c index bee90fa3ea..587c235223 100644 --- a/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c +++ b/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c @@ -728,7 +728,7 @@ static NvU8 checkUidMatch } //---------------------------------------------------------------------------- -// NV_STATUS extractNBSIObjFromDir(pGpu, idx, +// NV_STATUS extractNBSIObjFromDir(pGpu, idx, // pNbsiDir, nbsiDirSize, tableLoc, // wantedGlobType, wantedGlobIndex, // * pActualGlobIdx, @@ -1159,7 +1159,7 @@ static NV_STATUS freeNbsiCache } //---------------------------------------------------------------------------- -// NV_STATUS getNbsiCacheInfoForGlobType(pGpu, idx, +// NV_STATUS getNbsiCacheInfoForGlobType(pGpu, idx, // globType, // *pWantedGlobSource, *pWantedGlobIndex, // *pNbsiDir, *pNbsiDirSize, *pCurTbl) @@ -1384,7 +1384,7 @@ static NV_STATUS getNbsiObjFromCache //---------------------------------------------------------------------------- -// NV_STATUS getNbsiDirFromRegistry(pGpu, idx, +// NV_STATUS getNbsiDirFromRegistry(pGpu, idx, // pNbsiDir, pNbsiDirSize) // // This function determines if an emulated NBSI table exists in the registry @@ -1544,7 +1544,7 @@ static NV_STATUS determineACPIAccess } //---------------------------------------------------------------------------- -// NV_STATUS getNbsiDirectory(pGpu, idx, +// NV_STATUS getNbsiDirectory(pGpu, idx, // searchDir, *pNbsiDir, *pNbsiDirSize, // curSource, // *pbFreeDirMemRequired, @@ -2575,7 +2575,7 @@ static NV_STATUS getTableUsingAllObjectCall } //---------------------------------------------------------------------------- -// NV_STATUS _extractNBSIObjFromACPIDir(pGpu, idx, +// NV_STATUS _extractNBSIObjFromACPIDir(pGpu, idx, // curDir, // acpiFunction, validationOption, acpiMethod, // wantedGlobType, wantedGlobIdx, diff --git a/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c b/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c index b74fe39362..a536b06615 100644 --- a/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c +++ b/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c @@ -137,7 +137,7 @@ NV_STATUS nbsiReadRegistryDword if (errorCode == NV2080_CTRL_BIOS_GET_NBSI_SUCCESS) { *pData = nbsiDword; - } + } else { // diff --git a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c index 2b9e7d4103..9591e74d30 100644 --- a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c +++ b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,9 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED + #include "core/system.h" #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -706,7 +709,7 @@ p2pGetCapsStatus // If any of the GPU has MIG enabled, return with no P2P support if (!bSmcNvLinkP2PSupported) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "P2P is marked unsupported with MIG for GPU instance = 0x%x\n", gpuInstance); return NV_OK; @@ -836,7 +839,7 @@ subdeviceCtrlCmdInternalSetP2pCaps_IMPL return NV_ERR_NOT_SUPPORTED; NV_CHECK_OR_RETURN(LEVEL_ERROR, - pParams->peerGpuCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + pParams->peerGpuCount <= NV_ARRAY_ELEMENTS(pGpu->P2PPeerGpuCaps), NV_ERR_INVALID_ARGUMENT); for (i = 0; i < pParams->peerGpuCount; i++) @@ -851,7 +854,7 @@ subdeviceCtrlCmdInternalSetP2pCaps_IMPL if (pLocalPeerCaps == NULL) { NV_CHECK_OR_ELSE(LEVEL_ERROR, - pGpu->P2PPeerGpuCount < NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + pGpu->P2PPeerGpuCount < NV_ARRAY_ELEMENTS(pGpu->P2PPeerGpuCaps), status = NV_ERR_INSUFFICIENT_RESOURCES; goto fail); pLocalPeerCaps = &pGpu->P2PPeerGpuCaps[pGpu->P2PPeerGpuCount]; @@ -905,7 +908,7 @@ subdeviceCtrlCmdInternalRemoveP2pCaps_IMPL return NV_ERR_NOT_SUPPORTED; NV_CHECK_OR_RETURN(LEVEL_ERROR, - pParams->peerGpuIdCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + pParams->peerGpuIdCount <= NV_ARRAY_ELEMENTS(pGpu->P2PPeerGpuCaps), NV_ERR_INVALID_ARGUMENT); for (i = 0; i < pParams->peerGpuIdCount; i++) @@ -1028,7 +1031,7 @@ subdeviceCtrlCmdGetP2pCaps_IMPL NV_CHECK_OR_RETURN(LEVEL_ERROR, (pParams->bAllCaps || - (pParams->peerGpuCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps))), + (pParams->peerGpuCount <= NV_ARRAY_ELEMENTS(pGpu->P2PPeerGpuCaps))), NV_ERR_INVALID_ARGUMENT); NV_CHECK_OR_RETURN(LEVEL_ERROR, (pParams->bUseUuid == NV_FALSE), NV_ERR_NOT_SUPPORTED); diff --git a/src/nvidia/src/kernel/platform/platform_request_handler.c b/src/nvidia/src/kernel/platform/platform_request_handler.c new file mode 100644 index 0000000000..e2f5edaa80 --- /dev/null +++ b/src/nvidia/src/kernel/platform/platform_request_handler.c @@ -0,0 +1,1031 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "nvRmReg.h" +#include "objtmr.h" +#include "platform/platform_request_handler.h" +#include "core/locks.h" +#include "diagnostics/tracer.h" +#include "gps.h" +#include "platform/platform.h" +#include "rmapi/client_resource.h" + +/* ------------------------ Datatypes -------------------------------------- */ +/* ------------------------ Macros ----------------------------------------- */ +/* ------------------------ Defines ---------------------------------------- */ +/* ---------------------- Static Function Prototypes ----------------------- */ +static NV_STATUS _pfmreqhndlrSupportExists (PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +static NvBool _pfmreqhndlrCheckAndGetPM1ForcedOffState(PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +static GpuPrereqCallback _pfmreqhndlrPmgrPmuPostLoadPrereqCallback; +static GpuPrereqCallback _pfmreqhndlrThermPmuPostInitPrereqCallback; + +/* ---------------------- Extern Function Prototypes ----------------------- */ +extern NV_STATUS pfmreqhndlrCallback(OBJGPU *pGpu, OBJTMR *pTmr, void *pVoid); + +/* ------------------------ Public Functions ------------------------------ */ + +// Constructor +NV_STATUS +pfmreqhndlrConstruct_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_PRINTF(LEVEL_INFO, "\n"); + return NV_OK; +} + +/*! + * @brief Stores the index of first GPU which supports PLATFORM_REQUEST_HANDLER + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + * @return NV_OK always succeeds + */ +NV_STATUS +pfmreqhndlrInitGpu +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + pPlatformRequestHandler->dsmVersion = ACPI_DSM_FUNCTION_INVALID; + + OBJGPU *pGpu = NULL; + NvU32 gpuIndex = 0; + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + NvU32 gpuCount; + NvU32 gpuMask; + + // Initialize index to default (invalid) value. + pPlatformRequestHandler->pfmreqhndlrSupportedGpuIdx = PFM_REQ_HNDLR_MAX_GPU_SUPPORTED; + gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); + + // Invalid GPU configuration + if (gpuCount < 1 || gpuCount > PFM_REQ_HNDLR_MAX_GPU_SUPPORTED) + { + NV_PRINTF(LEVEL_ERROR, "PLATFORM_REQUEST_HANDLER: Cannot support %u GPUs yet\n", gpuCount); + } + else + { + while (((pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex)) != NULL) && + (pGpu->pPrereqTracker != NULL)) + { + // get pfmreqhndlr support option. + if(testIfDsmSubFunctionEnabled(pGpu, ACPI_DSM_FUNCTION_GPS_2X, GPS_FUNC_SUPPORT) == NV_OK) + { + pPlatformRequestHandler->dsmVersion = ACPI_DSM_FUNCTION_GPS_2X; + status = NV_OK; + } + else if(testIfDsmSubFunctionEnabled(pGpu, ACPI_DSM_FUNCTION_GPS, GPS_FUNC_SUPPORT) == NV_OK) + { + pPlatformRequestHandler->dsmVersion = ACPI_DSM_FUNCTION_GPS; + status = NV_OK; + } + + if (status == NV_OK) + { + // + // Store the GPU index of the current GPU. + // gpumgrGetNextGpu() increments gpuIndex to point to the next + // GPU, so need to subtract 1 to get the current GPU index. + // + pPlatformRequestHandler->pfmreqhndlrSupportedGpuIdx = gpuIndex - 1; + break; + } + } + } + + return NV_OK; +} + +/*! + * @brief Returns the GPU which supports PLATFORM_REQUEST_HANDLER + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + * @return pGpu if at least one GPU supports ACPI_DSM_FUNCTION_PFM_REQ_HNDLR + * @return NULL if no GPU supports ACPI_DSM_FUNCTION_PFM_REQ_HNDLR + */ +POBJGPU +pfmreqhndlrGetGpu +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + OBJGPU *pGpu = NULL; + NvU32 gpuIndex; + NvU32 gpuCount; + NvU32 gpuMask; + + gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); + + // gpumgrGetNextGpu() increments the index, so pass a copy to it. + gpuIndex = pPlatformRequestHandler->pfmreqhndlrSupportedGpuIdx; + + if (gpuIndex < PFM_REQ_HNDLR_MAX_GPU_SUPPORTED) + { + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + return pGpu; +} + +/*! + * Acquire/release all locks/semaphores before executing passive mode code. + * + * @param[in] bEnter specify if this call was invoked prior (NV_TRUE) or + * after (NV_FALSE) executing passive mode code + * @param[in] APILockFlag flag for the RM API lock + * @param[in] GPULockFlag flag for RM GPU lock + * + * @return NV_ERR_INVALID_OBJECT failed to look-up system object + * @return propagates an error code of other interfaces called within + */ +NV_STATUS +pfmreqhndlrPassiveModeTransition +( + NvBool bEnter, + NvU32 apiLockFlag, + NvU32 gpuLockFlag +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvBool bReleaseRmSema = NV_FALSE; + NvBool bReleaseApiLock = NV_FALSE; + NvBool bReleaseGpuLock = NV_FALSE; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pSys != NULL, NV_ERR_INVALID_OBJECT); + + if (bEnter) + { + if (status == NV_OK) + { + status = osCondAcquireRmSema(pSys->pSema); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error acquiring semaphore!\n"); + DBG_BREAKPOINT(); + } + } + + if (status == NV_OK) + { + status = rmapiLockAcquire(apiLockFlag, RM_LOCK_MODULES_PFM_REQ_HNDLR); + + if (status != NV_OK) + { + bReleaseRmSema = NV_TRUE; + + NV_PRINTF(LEVEL_ERROR, "Error acquiring API lock!\n"); + DBG_BREAKPOINT(); + } + } + + if (status == NV_OK) + { + status = rmGpuLocksAcquire(gpuLockFlag, RM_LOCK_MODULES_PFM_REQ_HNDLR); + + if (status != NV_OK) + { + bReleaseApiLock = NV_TRUE; + bReleaseRmSema = NV_TRUE; + + NV_PRINTF(LEVEL_ERROR, "Error acquiring GPUs lock!\n"); + DBG_BREAKPOINT(); + } + } + } + else + { + bReleaseRmSema = NV_TRUE; + bReleaseApiLock = NV_TRUE; + bReleaseGpuLock = NV_TRUE; + } + + if (bReleaseGpuLock) + { + rmGpuLocksRelease(gpuLockFlag, NULL); + } + + if (bReleaseApiLock) + { + rmapiLockRelease(); + } + + if (bReleaseRmSema) + { + osReleaseRmSema(pSys->pSema, NULL); + } + + return status; +} + +/*! + * @brief Handle PFM_REQ_HNDLR_EVENT_STATUS_CHANGE event. + * + * This function is called for PlatformRequestHandler when SBIOS triggers + * PFM_REQ_HNDLR_EVENT_STATUS_CHANGE event and also when v-Pstate change heppen in RM + * to update it to SBIOS. This control call will send ACK back to SBIOS if + * get a call from SBIOS and do further processing required. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] input Data used to send in Pcontrol ACPI call + * @param[in] bSbiosCall True if we get a call from SBIOS, false if get + * call to update SBIOS about new v-Pstate + * + * @return 'NV_OK' + * If the command successfully completes. + * @return 'NV_ERR_NOT_SUPPORTED' + * If invalid type of command is requested. + */ +NV_STATUS +pfmreqhndlrPcontrol_IMPL(PlatformRequestHandler *pPlatformRequestHandler, NvU32 input, NvBool bSbiosCall) +{ + OBJGPU *pGpu = NULL; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = NULL; + NvU32 indexPstate = 0; // Pstate index received by SBIOS + NvU32 maxVPstate = 0; // Max v-Pstate corresponding to Pstate index + NvU32 inputData = 0; // Input data sent to SBIOS + NvU32 vpStateMapping = 0; // v-Pstate mapping corresponding Pstate index + NvU32 responseData = 0; // Responce data received from SBIOS + NvU32 requestData = 0; // Request data send to SBIOS + NV_STATUS status = NV_OK; + RM_API *pRmApi = NULL; + NvBool bDone = NV_FALSE; + + if (NULL == pPlatformRequestHandler) + { + NV_PRINTF(LEVEL_ERROR, "PlatformRequestHandler pointer is NULL\n"); + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; + } + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (NULL == pGpu) + { + NV_PRINTF(LEVEL_ERROR, "Gpu pointer is NULL\n"); + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; + } + pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + // + // Setup the initial PFM_REQ_HNDLR_FUNC_PCONTROL call + // + + //Updating input data before sending request for Pcontrol call + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RES, NV_PB_PFM_REQ_HNDLR_PCTRL_RES_CHANGE_EVENT, inputData); + // Setting reserved bit equal to zero + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RESERVED, NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED_BITS, inputData); + // Last received v-Pstate limit in input data designated by bits [15:8]. + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _LAST_VPSTATE_LIMIT, pPfmreqhndlrData->PFMREQHNDLRACPIData.prevSbiosVPStateLimit, inputData); + // Send slowest externally available v-Pstate number in [23:16] of input data. + // NOTE: Notion of a "Slow" vpstate is not applicable in PSTATES 3.0+, this usage is broken for non pstates 2.x environments. + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _SLOW_EXT_VPSTATE, pPlatformRequestHandler->vPstateCache.vPstateIdxHighest, inputData); + // Setting fastest available v-Pstate to 0 + inputData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _FAST_VPSTATE, 0, inputData); + + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams = {0}; + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL; + acpiParams.ctrl.input = inputData; + acpiParams.output.pBuffer = (NvU8*)&(requestData); + acpiParams.output.bufferSz = sizeof(requestData); + + bDone = NV_FALSE; + + while (!bDone) + { + // make the previously setup PFM_REQ_HNDLR_FUNC_PCONTROL call + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + + if (NV_OK != status) + { + NV_PRINTF(LEVEL_ERROR, "ACPI call failed. Error : 0x%x\n", status); + DBG_BREAKPOINT(); + + break; + } + requestData = acpiParams.output.result[0]; + + switch(DRF_VAL(_PB, _PFM_REQ_HNDLR_PCTRL, _REQ, requestData)) + { + case NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_NO_ACTION: + { + // No action is needed, exit the function + NV_PRINTF(LEVEL_INFO, + "No action is required in response to SBIOS event PCONTROL\n"); + bDone = NV_TRUE; + + break; + } + case NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_INFO: + { + // + // Setup a response PFM_REQ_HNDLR_FUNC_PCONTROL call to return the VP-State range + // + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS params = {0}; + params.pStateIdx = DRF_VAL(_PB, _PFM_REQ_HNDLR_PCTRL, _INDEX_PSTATE, requestData);; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING, + ¶ms, + sizeof(params)); + if (status == NV_OK) + { + vpStateMapping = params.vPstateIdxMapping; + } + + + // Send response for v-Pstate information in response type. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RES, NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_INFO, responseData); + // Setting reserved bit equal to zero + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RESERVED, NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED_BITS, responseData); + // Send Pstate index received from previous return value of Pstate index in [15:8] of input data. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _INDEX_PSTATE, indexPstate, responseData); + // Send slowest externally available v-Pstate number in [23:16] of input data. + // NOTE: Notion of a "Slow" vpstate is not applicable in PSTATES 3.0+, this usage is broken for non pstates 2.x environments. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _SLOW_EXT_VPSTATE, pPlatformRequestHandler->vPstateCache.vPstateIdxHighest, responseData); + // Send v-Pstate mapping for indexPstate in [31:24] of input data. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _MAPPING_VPSTATE, vpStateMapping, responseData); + + acpiParams.ctrl.input = responseData; + requestData = 0; + acpiParams.output.pBuffer = (NvU8*)&(requestData); + acpiParams.output.bufferSz = sizeof(requestData); + + // call will actually be made at the top of the while loop in the next pass. + break; + } + case NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_SET: + { + maxVPstate = DRF_VAL(_PB, _PFM_REQ_HNDLR_PCTRL, _MAX_VPSTATE_LEVEL, requestData); + + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS params = {0}; + params.vPstateIdx = maxVPstate; + + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE, + ¶ms, + sizeof(params)); + + // + // Setup a response PFM_REQ_HNDLR_FUNC_PCONTROL call to indicate we have changed the current VP-State + // + + // Send response for v-Pstate information in response type + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RES, NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_SET, responseData); + // Setting reserved bit equal to zero + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _RESERVED, NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED_BITS, responseData); + // Last received v-Pstate limit in input data designated by bits [15:8]. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _LAST_VPSTATE_LIMIT, pPfmreqhndlrData->PFMREQHNDLRACPIData.prevSbiosVPStateLimit, responseData); + // Return slowest of input data designated by bits [23:16]. + // NOTE: Notion of a "Slow" vpstate is not applicable in PSTATES 3.0+, this usage is broken for non pstates 2.x environments. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _SLOW_EXT_VPSTATE, pPlatformRequestHandler->vPstateCache.vPstateIdxHighest, responseData); + // Fastest available v-Pstate of input data designated by bits [31:24] which is 0. + responseData = FLD_SET_DRF_NUM (_PB, _PFM_REQ_HNDLR_PCTRL, _FAST_VPSTATE, 0, responseData); + + pPfmreqhndlrData->PFMREQHNDLRACPIData.prevSbiosVPStateLimit + = maxVPstate; + acpiParams.ctrl.input = responseData; + requestData = 0; + acpiParams.output.pBuffer = (NvU8*)&(requestData); + acpiParams.output.bufferSz = sizeof(requestData); + + // call will actually be made at the top of the while loop in the next pass. + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, + "Received a wrong request type from SBIOS, which is not supported\n"); + status = NV_ERR_NOT_SUPPORTED; + + bDone = NV_TRUE; + + break; + } + } + } + + return status; +} +/* ---------------------- Static Functions --------------------------------- */ + +NvBool +pfmreqhndlrIsInitialized_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_ASSERT(pPlatformRequestHandler); + + return pPlatformRequestHandler->controlData.bStateInitialized; +} + +/*! + * @brief Initializes the PlatformRequestHandler control SW state. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + * @return NV_ERR_INVALID_STATE failed to look-up required object pointers + * @return NV_ERR_NOT_SUPPORTED system doesn't support requested PlatformRequestHandler variant + * @return NV_OK PlatformRequestHandler was successfully initialized + */ +NV_STATUS +pfmreqhndlrStateInit_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_STATUS status = NV_ERR_INVALID_STATE; + OBJGPU *pGpu = NULL; + RM_API *pRmApi = NULL; + + if (pPlatformRequestHandler == NULL) + { + NV_PRINTF(LEVEL_ERROR, "PlatformRequestHandler pointer is NULL\n"); + DBG_BREAKPOINT(); + return NV_ERR_NOT_SUPPORTED; + } + + if (pfmreqhndlrIsInitialized(pPlatformRequestHandler)) + { + // Skip if it has been intialized already + status = NV_OK; + goto pfmreqhndlrStateInit_IMPL_exit; + } + + status = pfmreqhndlrInitGpu(pPlatformRequestHandler); + if (status != NV_OK) + { + goto pfmreqhndlrStateInit_IMPL_exit; + } + + // Validate we have everything. + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + + if (pGpu == NULL) + { + status = NV_ERR_INVALID_STATE; + goto pfmreqhndlrStateInit_IMPL_exit; + } + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // Init state varibles. + pPlatformRequestHandler->controlData.bTGPUOverrideRequired = NV_TRUE; + pPlatformRequestHandler->controlData.bEDPpeakUpdateEnabled = NV_FALSE; + pPlatformRequestHandler->controlData.bUserConfigTGPmodeEnabled = NV_FALSE; + pPlatformRequestHandler->controlData.bPlatformUserConfigTGPmodeEnabled = NV_FALSE; + + // Initialize FRL reporting data + pPlatformRequestHandler->frmData.nextSampleNumber = 0; + + // Check if PlatformRequestHandler is supported through ACPI + if (_pfmreqhndlrSupportExists(pPlatformRequestHandler, pGpu) == NV_OK) + { + NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS ctrlParams = { 0 }; + + pPlatformRequestHandler->setProperty(pPlatformRequestHandler, + PDB_PROP_PFMREQHNDLR_SUPPORTED, NV_TRUE); + + ctrlParams.bIsSysCtrlSupported = NV_TRUE; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE, + &ctrlParams, + sizeof(ctrlParams)); + if (status == NV_OK) + { + pPlatformRequestHandler->setProperty(pPlatformRequestHandler, + PDB_PROP_PFMREQHNDLR_SYS_CONTROL_SUPPORTED, NV_TRUE); + + pPlatformRequestHandler->setProperty(pPlatformRequestHandler, + PDB_PROP_PFMREQHNDLR_IS_PLATFORM_LEGACY, ctrlParams.bIsPlatformLegacy); + } + } + else + { + status = NV_ERR_NOT_SUPPORTED; + goto pfmreqhndlrStateInit_IMPL_exit; + } + + // Initialize the sensors based on ACPI + pfmreqhndlrInitSensors(pPlatformRequestHandler); + + pPlatformRequestHandler->controlData.bStateInitialized = NV_TRUE; + + // Check and get PM1ForcedOff state + pPlatformRequestHandler->controlData.bPM1ForcedOff = + _pfmreqhndlrCheckAndGetPM1ForcedOffState(pPlatformRequestHandler, pGpu); + + // Cache VPstate PS 20 Support and Highest VPstate Idx + // Set the load sync with PMGR + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS params = { 0 }; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO, + ¶ms, + sizeof(params)); + if (status == NV_OK) + { + pPlatformRequestHandler->vPstateCache.bVpsPs20Supported = params.bVpsPs20Supported; + pPlatformRequestHandler->vPstateCache.vPstateIdxHighest = params.vPstateIdxHighest; + } + else + { + // Set the index to invalid incase of error + pPlatformRequestHandler->vPstateCache.bVpsPs20Supported = NV_FALSE; + pPlatformRequestHandler->vPstateCache.vPstateIdxHighest = PFM_REQ_HNDLR_VPSTATE_INDEX_INVALID; + } + + // Set the load sync with PMGR + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS ctrlParams = { 0 }; + + ctrlParams.flags = NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC, + &ctrlParams, + sizeof(ctrlParams)); + if (status != NV_OK) + { + goto pfmreqhndlrStateInit_IMPL_exit; + } + + // 2X only set the init sync with THERM + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + ctrlParams.flags = NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC, + &ctrlParams, + sizeof(ctrlParams)); + if (status != NV_OK) + { + goto pfmreqhndlrStateInit_IMPL_exit; + } + } + +pfmreqhndlrStateInit_IMPL_exit: + return status; +} + +/*! + * @brief deallocates PlatformRequestHandler data. + * + * frees up the memory from PlatformRequestHandler global data + * dynamically allocated during init. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + */ +void +pfmreqhndlrStateDestroy_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_ASSERT(pPlatformRequestHandler); + + pPlatformRequestHandler->controlData.bStateInitialized = NV_FALSE; +} + +NV_STATUS +pfmreqhndlrStateLoad_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + OBJGPU *pGpu = NULL; + NvBool bPM1Available = NV_FALSE; + NvTemp targetTemp = PFM_REQ_HNDLR_TEMP_0_C; + NvU32 data32 = 0; + RM_API *pRmApi = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT(pPlatformRequestHandler); + + // Validate we have everything. + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (pGpu == NULL) + { + return NV_ERR_INVALID_STATE; + } + if (!pPlatformRequestHandler->getProperty(pPlatformRequestHandler, PDB_PROP_PFMREQHNDLR_SUPPORTED)) + { + return NV_OK; + } + + if (!PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // Find default Temp for Thermal Controller from SBIOS. + if (NV_OK == pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), + &data32)) + { + targetTemp = NV_TYPES_CELSIUS_TO_NV_TEMP(data32); + } + + if (targetTemp != PFM_REQ_HNDLR_TEMP_0_C) + { + if (pPlatformRequestHandler->controlData.bTGPUOverrideRequired) + { + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS params = { 0 }; + params.targetTemp = targetTemp; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + pPlatformRequestHandler->controlData.bTGPUOverrideRequired = NV_FALSE; + } + else + { + NV_ASSERT_FAILED("PRH failed to update thermal limit!"); + + } + } + + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + if (pfmreqhndlrHandleCheckPM1Available(pPlatformRequestHandler, pGpu, &bPM1Available) == NV_OK) + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, bPM1Available); + } + } + else + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_FALSE); + } + } + } + + return NV_OK; +} + +NV_STATUS +pfmreqhndlrStateUnload_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + return NV_OK; +} + +NV_STATUS +pfmreqhndlrStateSync_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS + *pParams +) +{ + NV_STATUS status = NV_OK; + + switch(pParams->flags) + { + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD: + { + status = _pfmreqhndlrPmgrPmuPostLoadPrereqCallback(pGpu, NV_TRUE); + break; + } + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT: + { + status = _pfmreqhndlrThermPmuPostInitPrereqCallback(pGpu, NV_TRUE); + break; + } + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR: + { + status = pfmreqhndlrOperatingLimitUpdate(pPlatformRequestHandler, pParams->syncData.data.smbpbi.sensorId, + 0, NV_FALSE); + break; + } + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET: + { + status = pfmreqhndlrOperatingLimitUpdate(pPlatformRequestHandler, pParams->syncData.data.smbpbi.sensorId, + pParams->syncData.data.smbpbi.limit, NV_TRUE); + break; + } + default: + { + return NV_ERR_NOT_SUPPORTED; + } + } + + return status; +} + +/*! + * @brief Checks if ACPI supports calls necessary for the PLATFORM_REQUEST_HANDLER + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] pGpu OBJGPU pointer + * + * @return NV_ERR_NOT_SUPPORTED ACPI does not provide support for PLATFORM_REQUEST_HANDLER + * @return NV_OK otherwise + */ +static NV_STATUS +_pfmreqhndlrSupportExists +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + NvU64 supportedFunction = 0; + NvU16 outDataSize = 0; + + if (pPlatformRequestHandler->dsmVersion == ACPI_DSM_FUNCTION_INVALID) + { + return NV_ERR_NOT_SUPPORTED; + } + + outDataSize = sizeof(supportedFunction); + + + if (osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_SUPPORT, + (NvU32 *)&supportedFunction, + &outDataSize) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GPS FUNC_SUPPORT is not supported on this Platform, Failing ACPI-GPS subfunction 0x%x.\n", + GPS_FUNC_SUPPORT); + return NV_ERR_NOT_SUPPORTED; + } + else + { + if (supportedFunction == 0) + { + NV_PRINTF(LEVEL_INFO, + "PRH : This system doesn't support any ACPI-GPS-subfunctions.\n"); + return NV_ERR_NOT_SUPPORTED; + } + } + + return NV_OK; +} + +/*! + * @brief Check and get PM1ForcedOff state + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] pGpu OBJGPU pointer + * + * @return NV_TRUE if PM1ForcedOff state is set + * @return NV_FALSE if PM1ForcedOff state is not set + */ +NvBool +_pfmreqhndlrCheckAndGetPM1ForcedOffState +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvBool bForcedOff = NV_FALSE; // Return NV_FALSE to match Legacy return values + NV_STATUS status = NV_ERR_GENERIC; + + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS params = { 0 }; + params.flag = NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + bForcedOff = params.bStatus; + } + + return bForcedOff; + +} + +/*! + * @copydoc GpuPrereqCallback + */ +static NV_STATUS +_pfmreqhndlrThermPmuPostInitPrereqCallback +( + OBJGPU *pGpu, + NvBool bSatisfied +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NV_STATUS status = NV_OK; + NvU32 data32 = 0; + NvTemp targetTemp; + NvBool bPM1Available = NV_FALSE; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + // + // bSatisfied handling: + // Only needs to be applied after THERM post pmu init bSatisfied = NV_TRUE + // No need to revert the settings since it is a client applied limit + // so the bSatisfied = NV_FALSE is not required to be handled. + // + // satisfy()/retract () handling: is not supported for this callback since it + // depends on prereq _THERM_PMU_LOADED. + // + if (bSatisfied) + { + // Find default Temp for Thermal Controller from SBIOS. + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), + &data32); + if (status == NV_OK) + { + // Overrride with system Temp + targetTemp = NV_TYPES_CELSIUS_TO_NV_TEMP(data32); + } + else + { + // Override value is set to 0C + targetTemp = PFM_REQ_HNDLR_TEMP_0_C; + + // Fall back to legacy implementation + status = NV_OK; + } + if (targetTemp != PFM_REQ_HNDLR_TEMP_0_C) + { + if (pPlatformRequestHandler->controlData.bTGPUOverrideRequired) + { + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS params = { 0 }; + params.targetTemp = targetTemp; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + pPlatformRequestHandler->controlData.bTGPUOverrideRequired = NV_FALSE; + } + else + { + NV_ASSERT_FAILED("PRH failed to update thermal limit!"); + + // Fall back to legacy implementation + status = NV_OK; + } + } + + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + if (pfmreqhndlrHandleCheckPM1Available(pPlatformRequestHandler, pGpu, &bPM1Available) == NV_OK) + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, bPM1Available); + } + else + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_FALSE); + } + } + else + { + pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_FALSE); + } + } + } + + return status; +} + +/*! + * @copydoc GpuPrereqCallback + */ +NV_STATUS +_pfmreqhndlrPmgrPmuPostLoadPrereqCallback +( + OBJGPU *pGpu, + NvBool bSatisfied +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler + *pPlatformRequestHandler + = SYS_GET_PFM_REQ_HNDLR(pSys); + NV_STATUS status = NV_OK; + NV_STATUS lcstatus; + + // + // bSatisfied handling: + // Only needs to be applied after PMGR post load bSatisfied = NV_TRUE + // No need to revert the settings since it is a client applied limit + // so the bSatisfied = NV_FALSE is not required to be handled. + // + // satisfy()/retract () handling: is not supported for this callback since it + // depends on prereq _PMGR_PMU_LOADED . + // + if (bSatisfied) + { + // + // EDPpeak event update, at this point SBIOS requested state should match + // with current control state if not trigger an update. + // + if (pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest != + pPlatformRequestHandler->controlData.bEDPpeakUpdateEnabled) + { + // Update or Reset the EDPp limit if needed + lcstatus = pfmreqhndlrHandleEdppeakLimitUpdate(pPlatformRequestHandler, pGpu, + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest); + if ((lcstatus != NV_OK) && (lcstatus != NV_ERR_NOT_SUPPORTED)) + { + NV_ASSERT_OK_FAILED("Failed to apply the EDPpeak limit from system", status); + status = lcstatus; + goto _pfmreqhndlrPmgrPmuPostLoadPrereqCallback_exit; + } + } + + // + // User configurable TGP mode (Turbo) event update, at this point SBIOS requested + // state should match with current control state if not trigger an update. + // + if (pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest != + pPlatformRequestHandler->controlData.bUserConfigTGPmodeEnabled) + { + // Enable or Reset the use configurable TGP mode (TGP Turbo mode) if needed. + lcstatus = pfmreqhndlrHandleUserConfigurableTgpMode(pPlatformRequestHandler, pGpu, + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest); + if ((lcstatus != NV_OK) && (lcstatus != NV_ERR_NOT_SUPPORTED)) + { + NV_ASSERT_OK_FAILED("Failed to update user configurable TGP (Turbo) mode from system", + status); + status = lcstatus; + goto _pfmreqhndlrPmgrPmuPostLoadPrereqCallback_exit; + } + } + + // + // Platform EDPp limit if differed apply it after prereq is satisfied + // + if (pPlatformRequestHandler->controlData.edppLimit.bDifferPlatformEdppLimit) + { + lcstatus = pfmreqhndlrHandlePlatformEdppLimitUpdate(pPlatformRequestHandler, pGpu, + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.platformEdppLimit); + if ((NV_OK != lcstatus) && + (NV_ERR_NOT_SUPPORTED != lcstatus)) + { + NV_ASSERT_OK_FAILED("Failed to update platform EDPpeak limit", + status); + status = lcstatus; + goto _pfmreqhndlrPmgrPmuPostLoadPrereqCallback_exit; + } + + // Reset the differ update flag + pPlatformRequestHandler->controlData.edppLimit.bDifferPlatformEdppLimit = NV_FALSE; + } + } + +_pfmreqhndlrPmgrPmuPostLoadPrereqCallback_exit: + return status; +} + diff --git a/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c b/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c new file mode 100644 index 0000000000..af913ef15d --- /dev/null +++ b/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c @@ -0,0 +1,2932 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************************************************************\ +* * +* This module contains the Platform Request Handler control interface * +* * +\***************************************************************************/ + +/* ------------------------ Includes --------------------------------------- */ +#include "nvRmReg.h" +#include "platform/platform_request_handler.h" +#include "platform/platform_request_handler_utils.h" +#include "platform/acpi_common.h" +#include "diagnostics/tracer.h" +#include "os/os.h" +#include "objtmr.h" +#include "core/locks.h" +#include "gps.h" +#include "rmapi/client_resource.h" + +/* ------------------------ Datatypes -------------------------------------- */ +// private typedef for this source file. +typedef NV_STATUS PfmreqhndlrControlHandler(PlatformRequestHandler *pPlatformRequestHandler, NvU16 locale, NvU32 *pData); + +// prototypes, to be used inside _PfmreqhndlrControlHandlerTable[] +static PfmreqhndlrControlHandler _handleCmdSystemPfmreqhndlrGetSupportedFunctions; +static PfmreqhndlrControlHandler _handleCmdSystemPfmreqhndlrDataInitUsingSbiosAndAck; + +typedef struct +{ + NvU16 command; + PfmreqhndlrControlHandler *handler; +} PFM_REQ_HNDLR_CONTROL_ENTRY; + +PFM_REQ_HNDLR_CONTROL_ENTRY _PfmreqhndlrControlTable[] = +{ + { NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS , _handleCmdSystemPfmreqhndlrGetSupportedFunctions }, + { NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK, _handleCmdSystemPfmreqhndlrDataInitUsingSbiosAndAck }, + + // always end with a NULL record + { NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID, NULL } +}; + +NvU16 PerfSensorBlockMap[][32] = { + { + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 0, 1 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 2, 3 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 4, 5 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 6, 7 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 8, 9 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 10, 11 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 12, 13 + PFM_REQ_HNDLR_TC_ENABLE, PFM_REQ_HNDLR_RESERVED_COUNTER, // 14, 15 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 16, 17 + PFM_REQ_HNDLR_PSR_PUB_ENTRY(PFM_REQ_HNDLR_PM1_STATE_AVAIL), PFM_REQ_HNDLR_RESERVED_COUNTER, // 18, 19 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 20, 21 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 22, 23 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 24, 25 + PFM_REQ_HNDLR_CURR_VALUE_PUB_ENTRY(PFM_REQ_HNDLR_TGPU_SENSOR), PFM_REQ_HNDLR_RESERVED_COUNTER, // 26, 27 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 28, 29 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER // 30, 31 + }, + { + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 0, 1 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 2, 3 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 4, 5 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 6, 7 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 8, 9 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 10, 11 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 12, 13 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 14, 15 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 16, 17 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_VPS_PS20_SUPPORT, // 18, 19 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 20, 21 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 22, 23 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 24, 25 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 26, 27 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 28, 29 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER // 30, 31 + }, + { + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 0, 1 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 2, 3 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 4, 5 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 6, 7 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 8, 9 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 10, 11 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 12, 13 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 14, 15 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 16, 17 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 18, 19 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 20, 21 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 22, 23 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 24, 25 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 26, 27 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 28, 29 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER // 30, 31 + }, + { + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 0, 1 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 2, 3 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 4, 5 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 6, 7 + PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), PFM_REQ_HNDLR_RESERVED_COUNTER, // 8, 9 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 10, 11 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 12, 13 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 14, 15 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 16, 17 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 18, 19 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 20, 21 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 22, 23 + PFM_REQ_HNDLR_AVAIL_SENSOR_MSK, PFM_REQ_HNDLR_RESERVED_COUNTER, // 24, 25 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 26, 27 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER, // 28, 29 + PFM_REQ_HNDLR_RESERVED_COUNTER, PFM_REQ_HNDLR_RESERVED_COUNTER // 30, 31 + } +}; + +/* ------------------------ Macros ----------------------------------------- */ +/*! + * Macro to detect and request a new update if it is necessary. + * If system has already applied the update or reset to EDPpeak limit + * the subsequent requests to do the same are ignored unless its different request. + */ +#define PFM_REQ_HNDLR_IS_EDPPEAK_UPDATE_REQUIRED(bUpdateAcpiRequest, bEnabled) \ + ((bUpdateAcpiRequest && !bEnabled) || (!bUpdateAcpiRequest && bEnabled)) + +/*! + * Macro to detect and request to enable user configurable TGP mode if it is necessary. + * If system has already applied the update or reset to user configurable TGP mode + * the subsequent requests to do the same are ignored unless its different request. + */ +#define PFM_REQ_HNDLR_IS_USER_CONFIG_TGP_MODE_UPDATE_REQUIRED(bUpdateAcpiRequest, bEnabled) \ + ((bUpdateAcpiRequest && !bEnabled) || (!bUpdateAcpiRequest && bEnabled)) + +/*! + * Macro to detect if a PLATFORM REQUEST HANDLER counter value is valid, the counter is valid if + * the counter is supported and its value updated with a valid bit set. + */ +#define PFM_REQ_HNDLR_IS_COUNTER_VALID(pPlatformRequestHandler, counterId) \ + ((&(pPlatformRequestHandler->sensorData))->PFMREQHNDLRSensorCache[counterId].bSupported && \ + (!(&(pPlatformRequestHandler->sensorData))->PFMREQHNDLRSensorCache[counterId].bInvalid)) + + /* ------------------------ Defines ---------------------------------------- */ +#define PFM_REQ_HNDLR_USE_SBIOS_LIMIT (0U) +#define PFM_REQ_HNDLR_DISABLE_LIMIT (255U) +#define PFM_REQ_HNDLR_AVAILABLE_SENSOR_BLOCKS (4U) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_USER_LIMITED (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_LIMITED (2) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_UNLIMITED (3) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_NOT_SUPPORTED (4) +#define NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_USER_DISABLED (5) + +/* ---------------------- Static Function Prototypes ----------------------- */ +static NV_STATUS _pfmreqhndlrSampleSensorLimit (PlatformRequestHandler *pPlatformRequestHandler, NvU32 id, NvU32 timeStamp); +static NV_STATUS _pfmreqhndlrSampleSensorLimit_ACPI (PlatformRequestHandler *pPlatformRequestHandler, NvU32 id, NvU32 timeStamp); +static NV_STATUS _pfmreqhndlrUpdateSystemParamLimit (PlatformRequestHandler *pPlatformRequestHandler, NvU32 id); +static void _pfmreqhndlrUpdateSystemParamLimitWorkItem (NvU32 gpuInstance, void *pParams); +static void _pfmreqhndlrResetCounter (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvU32 timeStamp); +static void _pfmreqhndlrUpdateCounter (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvBool bValid, NvU32 value, NvU32 timeStamp); +static void _pfmreqhndlrOverrideCounter (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvU32 value, NvU32 timeStamp); +static void _pfmreqhndlrCancelCounterOverride (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvU32 timeStamp); +static void _pfmreqhndlrInitSupportedCounter (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 id, NvBool bVolatile, NvU32 timeStamp); +static NvBool _pfmreqhndlrIsCacheEntryStale (PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, NvU32 counterId, NvU32 timeStamp); +static NV_STATUS _pfmreqhndlrCallPshareStatus (PlatformRequestHandler *pPlatformRequestHandler, NvBool bInit); +static NvU32 _pfmreqhndlrGetTimeStamp (PlatformRequestHandler *pPlatformRequestHandler); +static NV_STATUS _pfmreqhndlrEnablePM1 (OBJGPU *pGpu, NvBool bEnable); +static NV_STATUS _pfmreqhndlrSetSupportedStatesFromAcpiParams(OBJGPU *pGpu, PlatformRequestHandler *pPlatformRequestHandler, NvU32 supportedSubfuncs); +static NV_STATUS _pfmreqhndlrHandleUserConfigurableTgpModePlatformCustomization(PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +static void _pfmreqhndlrUpdatePlatformPowerModeWorkItem (NvU32 gpuInstance, void *pParams); +static void _pfmreqhndlrPlatformPowerModeStateReset (PlatformRequestHandler *pPlatformRequestHandler); +static NV_STATUS _pfmreqhndlrUpdatePpmdLimit (PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool bInit); +static NV_STATUS _pfmreqhndlrUpdateTgpuLimit (PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +static void _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem(NvU32 gpuInstance, void *pParams); + +/* ------------------------ Public Functions ------------------------------ */ +NV_STATUS +pfmreqhndlrControl_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU16 command, + NvU16 locale, + NvU32 *pData +) +{ + PFM_REQ_HNDLR_CONTROL_ENTRY *pPfmreqhndlrCtrlTableEntry = NULL; + + if (!pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + + for (pPfmreqhndlrCtrlTableEntry = _PfmreqhndlrControlTable; + pPfmreqhndlrCtrlTableEntry->handler; + pPfmreqhndlrCtrlTableEntry++) + { + if (command == pPfmreqhndlrCtrlTableEntry->command) + { + return pPfmreqhndlrCtrlTableEntry->handler(pPlatformRequestHandler, locale, pData); + } + } + + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * Set/Remove the operating limit of a specific system-parameter (denoted by + * id) using a deferred workitem. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] id Identifier of parameter (PFM_REQ_HNDLR_*_SENSOR) to update + * @param[in] limit + * New operating-limit to set for the parameter. All limits are accepted as + * unsigned integers, but internally they should be formatted based on the + * type of id/sensor they correspond to. Limits for temperature-sensors for + * instance should be stored in NvTemp format. + * @param[in] bSet Indicates we are setting or removing the limit + * + * @return NV_OK Upon successful update + * @return NV_ERR_INVALID_ARGUMENT Invalid parameter type/id + * @return NV_ERR_INVALID_REQUEST + * Returned if the provided PlatformRequestHandler pointer was NULL or if the corresponding + * OBJGPU object could not be found. + */ +NV_STATUS +pfmreqhndlrOperatingLimitUpdate_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 limit, + NvBool bSet +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + OBJOS *pOs = GPU_GET_OS(pGpu); + + if (id >= PFM_REQ_HNDLR_PSHAREPARAMS_COUNT) + { + return NV_ERR_INVALID_ARGUMENT; + } + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + if (bSet) + { + // + // Temperature limits arrive in NvTemp format but are stored in NvU32 + // format. Perform the converstion. The limits will be transformed back to + // NvTemp values before they are used. Once the analogous ACPI code is + // changed to perform an immediate conversion from NvS32 to NvTemp, the + // limits can be stored in NvTemp format directly and double-conversion can + // be removed. + // + switch (id) + { + case PFM_REQ_HNDLR_TGPU_SENSOR: + limit = NV_TYPES_NV_TEMP_TO_CELSIUS_ROUNDED((NvTemp)limit); + break; + } + + status = pfmreqhndlrUpdatePerfCounter(pPlatformRequestHandler, PFM_REQ_HNDLR_LIMIT(id), limit); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Update perf counter failed.\n"); + DBG_BREAKPOINT(); + return status; + } + } + else + { + _pfmreqhndlrResetCounter(&pPlatformRequestHandler->sensorData, PFM_REQ_HNDLR_LIMIT(id), + _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler)); + } + + // Record which counter needs to be updated + pPlatformRequestHandler->sysControlData.queuedCounterMask |= NVBIT(id); + + // + // Don't submit the workitem again if there is already a pending workitem, + // all the touched counters will be updated once the workitem is executed. + // + if (!pPlatformRequestHandler->sysControlData.bWorkItemPending) + { + status = pOs->osQueueWorkItem(pGpu, + _pfmreqhndlrUpdateSystemParamLimitWorkItem, NULL); + + if (status != NV_OK) + { + // + // It is not a real failure if the OS doesn't support workitem, + // thus setting the status to NV_OK so that we will update the + // limit directly in this situation. But if the error code is + // not NV_ERR_NOT_SUPPORTED, then we treat it as real failure + // and will not do any update. The queued ID will be kept in + // this situation so that we can still handle it if we get any + // chance to queue another workitem later. + // + if (status == NV_ERR_NOT_SUPPORTED) + { + // + // Reset the queued id if the workitem is not supported (we + // will update the limit directly) + // + pPlatformRequestHandler->sysControlData.queuedCounterMask &= ~(NVBIT(id)); + status = NV_OK; + } + } + else + { + pPlatformRequestHandler->sysControlData.bWorkItemPending = NV_TRUE; + } + } + + if (status == NV_OK) + { + if (!pPlatformRequestHandler->sysControlData.bWorkItemPending) + { + // + // Update the limit directly if nothing wrong and no workitem is + // queued + // + return _pfmreqhndlrUpdateSystemParamLimit(pPlatformRequestHandler, id); + } + else + { + // + // Let the client knows that more processing is needed since + // workitem is queued + // + return NV_WARN_MORE_PROCESSING_REQUIRED; + } + } + + return status; +} + +// +// cliresCtrlCmdSystemPfmreqhndlrCtrl +// +// This function process control request for the PLATFORM REQUEST HANDLER object. +// +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + OBJGPU *pGpu = NULL; + PPFM_REQ_HNDLR_SENSOR_DATA pPfmreqhndlrData = NULL; + NV_STATUS status = NV_OK; + NvU32 timeStamp; + NvU32 newLimit; + NvU32 counterVal; + NvU16 counterId; + RM_API *pRmApi = NULL; + + if (NULL == pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + + if (NULL == pGpu) + { + return NV_ERR_NOT_SUPPORTED; + } + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + + switch (pParams->cmd) + { + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT: + { + counterId = (NvU16)pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX]; + + if (PFM_REQ_HNDLR_VALID_LIMIT_ID(counterId)) + { + if (NV_OK == pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + counterId, + &counterVal)) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT] = counterVal; + if (pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bOverridden) + { + // the Thermal limit is from a user specified limit. + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE] = + NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_USER_LIMITED; + } + else + { + // the thermal limit is from the SBIOS. + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE] = + NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_LIMITED; + } + } + else + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT] = 0; + if (pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bSupported) + { + // the SBIOS is not limiting the thermal sensor. + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE] = + NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_UNLIMITED; + } + else + { + // the SBIOS is not supporting this thermal limit. + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE] = + NV0000_CTRL_PFM_REQ_HNDLR_THERM_LIMIT_SRC_SBIOS_NOT_SUPPORTED; + } + } + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT] = 1; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT] = 100; + + status = NV_OK; + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT: + { + newLimit = pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT]; + counterId = (NvU16)pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX]; + + if (PFM_REQ_HNDLR_VALID_LIMIT_ID(counterId)) + { + if (PFM_REQ_HNDLR_USE_SBIOS_LIMIT == newLimit) + { + // clear any override & invalidate the cached limit. + _pfmreqhndlrCancelCounterOverride(pPfmreqhndlrData, counterId, timeStamp); + } + else + { + // push the new limit into the sensor cache & mark it as overridden. + _pfmreqhndlrOverrideCounter(pPfmreqhndlrData, counterId, pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT], timeStamp); + } + + if (PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR) == counterId) + { + // get & apply the new limit. + if (NV_OK == pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + counterId, + &counterVal)) + { + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS params = { 0 }; + params.targetTemp = NV_TYPES_CELSIUS_TO_NV_TEMP(newLimit);; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT, + ¶ms, + sizeof(params)); + + if (status != NV_OK) + { + status = NV_ERR_NOT_SUPPORTED; + break; + } + } + } + status = NV_OK; + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS: + { + // + // No longer able to turn on/off the temperature controller, so + // getting status is no longer needed. + // + status = NV_ERR_NOT_SUPPORTED; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS: + { + // No longer able to turn on/off the temperature controller + status = NV_ERR_NOT_SUPPORTED; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA: + { + status = NV_ERR_INVALID_ARGUMENT; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR: + { + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + (NvU16)pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX], + &counterVal); + if (NV_OK == status) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE] = counterVal; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE] = NV_TRUE; + } + else + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE] = 0; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE] = NV_FALSE; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS: + { + status = NV_ERR_NOT_SUPPORTED; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE: + { + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + status = _pfmreqhndlrEnablePM1(pGpu, + pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE]); + } + else + { + status = NV_ERR_NOT_SUPPORTED; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE: + { + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_PM1_STATE_AVAIL, + &counterVal); + if (NV_OK == status) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE] = counterVal; + } + else + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE] = 0; + } + } + else + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE] = 0; + status = NV_ERR_NOT_SUPPORTED; + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS: + { + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX acpiParamsEx = {0}; + + // Use EX type struct -- three NvU32s for both input and output for input + acpiParamsEx.inSize = NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT * sizeof(NvU32); + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX] = + FLD_SET_DRF(0000_CTRL_PFM_REQ_HNDLR, _PPL_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX]); + acpiParamsEx.outSize = NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT * sizeof(NvU32); + + if (pParams->cmd == NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS) + { + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_SETPPL; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT1_IDX] = + pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1]; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT2_IDX] = + pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1] * 2; + } + else + { + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_GETPPL; + } + + status = pfmreqhndlrCallACPI_EX(pGpu, &acpiParamsEx); + if (NV_OK == status) + { + // Check for major version 1 + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PPL_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX])) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1] = + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT1_IDX]; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2] = + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT2_IDX]; + } + else + { + status = NV_ERR_INVALID_DATA; + } + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT: + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT: + { + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX acpiParamsEx = {0}; + + // Use EX type struct -- two NvU32s for both input and output for input + acpiParamsEx.inSize = NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_COUNT * sizeof(NvU32); + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX] = + FLD_SET_DRF(0000_CTRL_PFM_REQ_HNDLR, _TRL_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX]); + acpiParamsEx.outSize = NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_COUNT * sizeof(NvU32); + + if (pParams->cmd == NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT) + { + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_SETTRL; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX] = + pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ]; + } + else + { + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_GETTRL; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX] = 0; + } + + status = pfmreqhndlrCallACPI_EX(pGpu, &acpiParamsEx); + if (NV_OK == status) + { + // Check for major version 1 + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _TRL_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX])) + { + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ] = + acpiParamsEx.output[NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX]; + } + else + { + status = NV_ERR_INVALID_DATA; + } + } + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM: + { + // + // Mask is cached in pfmreqhndlrStateLoad and when we recieve SBIOS notification on battery transitions in AC. + // Index is cached in pfmreqhndlrStateLoad, SBIOS notification and in the workItem to set the Platform power mode. + // Return the cached values instead of making ACPI calls. + // + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX] = + (NvS32) pPlatformRequestHandler->ppmData.ppmIdxCurrent; + pParams->result[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK] = + (NvS32) pPlatformRequestHandler->ppmData.ppmMaskCurrent; + + status = NV_OK; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM: + { + + // Return error if platform power modes are not supported + if (pPlatformRequestHandler->ppmData.ppmMaskCurrent == NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID) + { + status = NV_ERR_INVALID_DATA; + break; + } + NvU8 clientPpmIdx = (NvU8) pParams->input[NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX]; + + // If requested mode is same as current mode, return success + if (pPlatformRequestHandler->ppmData.ppmIdxCurrent == clientPpmIdx) + { + status = NV_OK; + break; + } + + // Return error for invalid mask or if index requested is not present in the mask + if ((clientPpmIdx == NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID) || + !(pPlatformRequestHandler->ppmData.ppmMaskCurrent & NVBIT(clientPpmIdx))) + { + status = NV_ERR_INVALID_DATA; + break; + } + + status = NV_ERR_BUSY_RETRY; + if (!pPlatformRequestHandler->ppmData.bWorkItemPending) + { + OBJOS *pOS = GPU_GET_OS(pGpu); + pPlatformRequestHandler->ppmData.ppmIdxRequested = clientPpmIdx; + // Create a workItem to change Platform Power Mode + status = pOS->osQueueWorkItem(pGpu, _pfmreqhndlrUpdatePlatformPowerModeWorkItem, NULL); + if (status == NV_OK) + { + // Queing workitem succeeded, mark it as pending. + pPlatformRequestHandler->ppmData.bWorkItemPending = NV_TRUE; + } + } + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, "Unknown request %x\n", pParams->cmd); + status = NV_ERR_NOT_SUPPORTED; + break; + } + } + return status; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrGetFrmData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NvU8 logicalBufferStart; + NvU8 block0Size; + + if (NULL==pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + + pParams->nextSampleNumber = pPlatformRequestHandler->frmData.nextSampleNumber; + + // logical buffer starts at the oldest entry + logicalBufferStart = ((pPlatformRequestHandler->frmData.nextSampleNumber) % NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE); + + // Block0 goes from the logical start of the buffer to the physical end of the buffer + block0Size = (NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE - logicalBufferStart); + + portMemCopy(&(pParams->samples[0]), (sizeof(pPlatformRequestHandler->frmData.samples[0]) * block0Size), &(pPlatformRequestHandler->frmData.samples[logicalBufferStart]), (sizeof(pPlatformRequestHandler->frmData.samples[0]) * block0Size)); + + // + // if the logical buffer is wrapping from the physical end of the buffer back to the beginning, + // copy the logical end block to the end of the output buffer + // + if (0 != logicalBufferStart) + { + portMemCopy(&(pParams->samples[block0Size]), (sizeof(pPlatformRequestHandler->frmData.samples[0]) * (logicalBufferStart)), &(pPlatformRequestHandler->frmData.samples[0]), (sizeof(pPlatformRequestHandler->frmData.samples[0]) * (logicalBufferStart))); + } + + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrSetFrmData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NvU8 sampleNumber = 0; + + if (NULL == pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + + sampleNumber = ((pPlatformRequestHandler->frmData.nextSampleNumber) % NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE); + pPlatformRequestHandler->frmData.samples[sampleNumber] = pParams->sampleData; + pPlatformRequestHandler->frmData.samples[sampleNumber].sampleNumber = pPlatformRequestHandler->frmData.nextSampleNumber; + pPlatformRequestHandler->frmData.nextSampleNumber++; + + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrCallAcpi_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams +) +{ + NV_STATUS status; + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + OBJGPU *pGpu; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams; + + if (NULL == pPlatformRequestHandler) + { + return NV_ERR_NOT_SUPPORTED; + } + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (NULL == pGpu) + { + return NV_ERR_NOT_SUPPORTED; + } + + portMemSet((void *) &acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + acpiParams.ctrl.cmd = pParams->cmd; + acpiParams.ctrl.input = pParams->input; + acpiParams.output.pBuffer = (NvU8*)&(pParams->result); + acpiParams.output.bufferSz = sizeof(pParams->result); + + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + + if (NV_OK != status) + { + return status; + } + if (0 == acpiParams.output.bufferSz) + { + // we used the result field, not the buffer, copy the results to the buffer + // based on the command type. + switch(acpiParams.ctrl.cmd) + { + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT: + { + pParams->result[0] = acpiParams.output.result[0]; + pParams->result[1] = acpiParams.output.result[1]; + pParams->resultSz = sizeof(acpiParams.output.result[0]) * 2; + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL: + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS: + { + pParams->result[0] = acpiParams.output.result[0]; + pParams->resultSz = sizeof(acpiParams.output.result[0]); + break; + } + // anything left is either a command that should have used a buffer, or something we don't recognize. + default: + { + pParams->resultSz = 0; + break; + } + } + } + else + { + pParams->resultSz = acpiParams.output.bufferSz; + } + return status; +} + +NV_STATUS +pfmreqhndlrCallACPI +( + OBJGPU *pGpu, + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NV_STATUS status = NV_OK; + NvU32 rc; + NvU16 paramSize; + + switch (pParams->ctrl.cmd) + { + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT: + { + // no input parameters + pParams->output.result[0] = 0; + pParams->output.result[1] = 0; + pParams->output.bufferSz = 0; + paramSize = sizeof(pParams->output.result); + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_SUPPORT, + pParams->output.result, + ¶mSize)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_SUPPORT. Possibly not supported/enabled by " + "CPU/ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SUPPORT, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SUPPORT, pParams->output.result[0], pParams->output.result[1], 0, 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL: + { + pParams->output.result[0] = pParams->ctrl.input; + paramSize = sizeof(pParams->output.result[0]); + pParams->output.bufferSz = 0; + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_PCONTROL, + (NvU32 *) &pParams->output.result[0], + ¶mSize)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_PCONTROL. Possibly not supported/enabled by " + "CPU/ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PCONTROL, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PCONTROL, pParams->ctrl.input, pParams->output.result[0], 0, 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS: + { + pParams->output.result[0] = pParams->ctrl.input; + paramSize = sizeof(pParams->output.result[0]); + pParams->output.bufferSz = 0; + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_PSHARESTATUS, + &pParams->output.result[0], + ¶mSize)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_PSHARESTATUS. Possibly not supported/enabled by" + " CPU/ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PSHARESTATUS, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PSHARESTATUS, pParams->ctrl.input, pParams->output.result[0], 0, 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS: + { + if (sizeof(PFM_REQ_HNDLR_PSHAREDATA) > pParams->output.bufferSz) + { + NV_PRINTF(LEVEL_ERROR, "buffer to small to hold output.\n"); + status = NV_ERR_NOT_SUPPORTED; + break; + } + *((NvU32*)(pParams->output.pBuffer)) = pParams->ctrl.input; + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_PSHAREPARAMS, + (NvU32 *) pParams->output.pBuffer, + &pParams->output.bufferSz)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_PSHAREPARAMS. Possibly not supported/enabled by" + " CPU/ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PSHAREPARAMS, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_PSHAREPARAMS, ((NvU32 *) pParams->output.pBuffer)[0], ((NvU32 *) pParams->output.pBuffer)[3], ((NvU32 *) pParams->output.pBuffer)[6], 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETEDPPLIMIT: + { + pParams->output.result[0] = pParams->ctrl.input; + paramSize = sizeof(pParams->output.result[0]); + + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_GETEDPPLIMIT, + &pParams->output.result[0], + ¶mSize)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_FUNC_GETEDPPLIMIT. Possibly not supported/enabled by " + "ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_GETEDPPLIMIT, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_GETEDPPLIMIT, pParams->output.result[0], pParams->output.result[1], 0, 0, 0); + break; + } + case NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETEDPPLIMITINFO: + { + if ((rc = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + GPS_FUNC_SETEDPPLIMITINFO, + (NvU32 *) pParams->output.pBuffer, + &pParams->output.bufferSz)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to retrieve PFM_REQ_HNDLR_FUNC_SETEDPPLIMITINFO. Possibly not supported/enabled by " + "ACPI? rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SETEDPPLIMITINFO, 0, 0, 0, 0, 0); + break; + } + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SETEDPPLIMITINFO, pParams->output.result[0], pParams->output.result[1], 0, 0, 0); + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, "Unknown request %x\n", + DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _CALL_ACPI, _CMD_TYPE, pParams->ctrl.cmd)); + status = NV_ERR_NOT_SUPPORTED; + break; + } + } + return status; +} + +/*! + * EX version of pfmreqhndlrCallACPI used only for PPL and TRL calls, which require + * a greater number of input args. + * + * @param[in] pGpu GPU object pointer + * @param[in, out] pParams Call parameters + * + * Returns NV_OK if handled successfully; otherwise propogates errors. + */ +NV_STATUS +pfmreqhndlrCallACPI_EX +( + OBJGPU *pGpu, + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX *pParams +) +{ + NvU32 idx; + NvU16 paramSize; + NV_STATUS status; + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + for (idx = 0; idx < NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ; ++idx) + { + pParams->output[idx] = pParams->input[idx]; + } + paramSize = pParams->outSize; + + if ((status = osCallACPI_DSM(pGpu, + pPlatformRequestHandler->dsmVersion, + pParams->pfmreqhndlrFunc, + pParams->output, + ¶mSize)) != NV_OK) + { + status = NV_ERR_NOT_SUPPORTED; + } + return status; +} + +// +// pfmreqhndlrInitSensors +// +// This function initialises the PLATFORM REQUEST HANDLER sensor data. +// it initializes all the data, and determines which sensors are available for sampling. +// +NV_STATUS +pfmreqhndlrInitSensors +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = NULL; + NvU32 timeStamp = 0; + PFM_REQ_HNDLR_PSHAREDATA *pPShareParams = NULL; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS + acpiParams; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + NV_ASSERT_OR_RETURN(NULL != pGpu, NV_ERR_INVALID_REQUEST); + + pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + + // init the PLATFORM REQUEST HANDLER data cache. + portMemSet((void *)pPfmreqhndlrData, 0, sizeof(PFM_REQ_HNDLR_SENSOR_DATA)); + + // + // Initialize a logical sw version based of ACPI dsm version + // + if ((pPlatformRequestHandler->getProperty(pPlatformRequestHandler, PDB_PROP_PFMREQHNDLR_IS_PLATFORM_LEGACY)) || + (pPlatformRequestHandler->dsmVersion == ACPI_DSM_FUNCTION_GPS_2X)) + { + pPfmreqhndlrData->PFMREQHNDLRACPIData.acpiVersionSw = + NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_2X; + } + + // Cache the current timestamp + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + + pPfmreqhndlrData->counterHoldPeriod = + PFM_REQ_HNDLR_DEFAULT_COUNTER_HOLD_PERIOD_MS; + + // + // init the PSHARESTATUS ACPI cache. + // set up the defaults + // + pPfmreqhndlrData->PFMREQHNDLRACPIData.bPfmReqHndlrSupported = NV_FALSE; + + // + // Check if PLATFORM REQUEST HANDLER is supported on this platform + // determine if we can call the PLATFORM REQUEST HANDLER ACPI call. + // + portMemSet((void *) &acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT; + acpiParams.ctrl.input = 0; + acpiParams.output.pBuffer = NULL; + acpiParams.output.bufferSz = 0; + if (NV_OK == pfmreqhndlrCallACPI(pGpu, &acpiParams)) + { + // Set up all the control flags based on all the supported subfunctions + status = _pfmreqhndlrSetSupportedStatesFromAcpiParams(pGpu, + pPlatformRequestHandler, acpiParams.output.result[1]); + if (NV_OK != status) + { + NV_ASSERT_FAILED("Get all the supported PlatformRequestHandler subfunctions"); + return status; + } + } + if (pPfmreqhndlrData->PFMREQHNDLRACPIData.bPfmReqHndlrSupported) + { + // call PSHARESTATUS to get the initial values. + _pfmreqhndlrCallPshareStatus(pPlatformRequestHandler, NV_TRUE); + + // PShare param is available, determine which sensors it is reporting. + pPShareParams = portMemAllocNonPaged(sizeof(PFM_REQ_HNDLR_PSHAREDATA)); + if (NULL != pPShareParams) + { + portMemSet((void *)pPShareParams, 0, sizeof(PFM_REQ_HNDLR_PSHAREDATA)); + portMemSet((void *)&acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS; + acpiParams.ctrl.input = + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_QUERY_TYPE, _SUPPORTED_FIELDS) | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_TGPU, _TRUE) | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_PPMD, _TRUE); + acpiParams.output.pBuffer = (void *) pPShareParams; + acpiParams.output.bufferSz = sizeof(PFM_REQ_HNDLR_PSHAREDATA); + + if (NV_OK == pfmreqhndlrCallACPI(pGpu, &acpiParams)) + { + // Determine the SBP(PFMREQHNDLR) version on this platform + // save the version number + pPfmreqhndlrData->version = pPShareParams->ulVersion; + + // save a mask of available counters + pPfmreqhndlrData->PFMREQHNDLRShareParamsAvailMask = pPShareParams->status & + (DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_TGPU, _TRUE) | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_PPMD, _TRUE)); + + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_AVAIL_SENSOR_MSK, NV_FALSE, timeStamp); + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_AVAIL_SENSOR_MSK, NV_TRUE, pPfmreqhndlrData->PFMREQHNDLRShareParamsAvailMask, timeStamp); + + // check each counter & if available, flag current value, limit, & period as available. + if (0 != (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _TGPU, pPShareParams->status))) + { + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), NV_TRUE, timeStamp); + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_PERIOD(PFM_REQ_HNDLR_TGPU_SENSOR), NV_FALSE, timeStamp); + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_PERIOD(PFM_REQ_HNDLR_TGPU_SENSOR), NV_TRUE, pPShareParams->tGpu, timeStamp); + } + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler) && + (0 != (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _PPMD, pPShareParams->status)))) + { + // Invalidate Platform Power Mode cache on boot + _pfmreqhndlrPlatformPowerModeStateReset(pPlatformRequestHandler); + + // Init PPMD sensor if this is enabled + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR), NV_TRUE, timeStamp); + + // Sample the PPMD counter from init time + _pfmreqhndlrUpdatePpmdLimit(pPlatformRequestHandler, pGpu, NV_TRUE); + } + } + portMemFree(pPShareParams); + } + + } + + // as long as there is an PlatformRequestHandler object, these counters should always be available. + // The following counters are non-Volatile, they are being updated as the corresponding functions change, + // so they do not need to be sampled on request for a current value. + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_VPS_PS20_SUPPORT, NV_TRUE, timeStamp); + + // The following counters are volatile, and need to be sampled on request for a current value. + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_TRUE, timeStamp); + + // The following counters are dynamically controlled by the Thermal controller. + // they are currently handled as volatile counters, but could be changed to non-volatile counters + // if TC is modified to push the new values to PFMREQHNDLR when they change. + // (note with the current policy of seperating TC & PFMREQHNDLR this is unlikely) + _pfmreqhndlrInitSupportedCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_TC_ENABLE, NV_TRUE, timeStamp); + + return status; +} + +/*! + * Set/update the value of a specific perf-counter (denoted by id). + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] id Identifier of counter to update + * @param[in] value New value to set for the counter + * + * @return NV_OK Upon successful update + * @return NV_ERR_INVALID_ARGUMENT Invalid counter id + * @return NV_ERR_INVALID_REQUEST + * Returned if the provided PlatformRequestHandler pointer was NULL or if the corresponding + * OBJGPU object could not be found. + */ +NV_STATUS +pfmreqhndlrUpdatePerfCounter +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 value +) +{ + OBJGPU *pGpu = NULL; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData; + NvU32 timeStamp; + + // is the Id within range? + if (id >= PFM_REQ_HNDLR_NUM_COUNTERS) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (NULL == pPlatformRequestHandler) + { + NV_ASSERT(pPlatformRequestHandler); + return NV_ERR_INVALID_REQUEST; + } + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (NULL == pGpu) + { + return NV_ERR_INVALID_REQUEST; + } + // determine the current ms timestamp. + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + + pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, id, NV_TRUE, value, timeStamp); + + return NV_OK; +} + +// +// PfmreqhndlrSampleCounter +// +// This function determines if it is appropriate to update the specified counter & does so if it is. +// Note that this function contains all the code specific to the sampling of each counter. +// +NV_STATUS +pfmreqhndlrSampleCounter +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 timeStamp +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + PFM_REQ_HNDLR_SENSOR_COUNTER *pCounter = &(pPfmreqhndlrData->PFMREQHNDLRSensorCache[id]); + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + NvBool bPM1Available = NV_TRUE; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + if (0 == timeStamp) + { + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + } + + // check if we can sample the counter. + // (marked available & can be sampled now.) + if (pCounter->bSupported + && (pCounter->bInvalid || ((timeStamp - pCounter->lastSampled) >= pCounter->minInterval))) + { + // Sample the requested counter. + switch (id) + { + case PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR): + case PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR): + { + status = _pfmreqhndlrSampleSensorLimit(pPlatformRequestHandler, id, timeStamp); + break; + } + case PFM_REQ_HNDLR_PM1_STATE_AVAIL: + { + if (!pPlatformRequestHandler->controlData.bPM1ForcedOff) + { + if (pfmreqhndlrHandleCheckPM1Available(pPlatformRequestHandler, pGpu, &bPM1Available) == NV_OK) + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_PM1_STATE_AVAIL, NV_TRUE, (NvU32)bPM1Available, timeStamp); + status = NV_OK; + } + } + //If PM1 is forced off or Boost Clocks not available + else + { + status = NV_ERR_NOT_SUPPORTED; + } + break; + } + case PFM_REQ_HNDLR_VPS_PS20_SUPPORT: + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_VPS_PS20_SUPPORT, NV_TRUE, pPlatformRequestHandler->vPstateCache.bVpsPs20Supported, timeStamp); + } + case PFM_REQ_HNDLR_TC_ENABLE: + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_TC_ENABLE, NV_TRUE, NV_TRUE, timeStamp); + break; + } + default: + { + break; + } + } + } + return status; +} + +/*! + * @brief Retrieves the requested counter and returns it if available. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] counterId ID of the requested counter + * @param[out] pCounterVal buffer to hold value of requested counter + * + * @return NV_ERR_INVALID_POINTER NULL pointer passed + * @return NV_ERR_NOT_SUPPORTED various failures (TODO) + * @return NV_ERR_INVALID_DATA counter is not available + * @return NV_OK counter successfully retrieved + */ +NV_STATUS +pfmreqhndlrGetPerfSensorCounterById_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU16 counterId, + NvU32 *pCounterVal +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = NULL; + OBJOS *pOs = NULL; + PPFM_REQ_HNDLR_SENSOR_DATA pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + NV_STATUS status = NV_ERR_INVALID_DATA; + NvU32 timeStamp; + + NV_ASSERT_OR_RETURN(NULL != pCounterVal, NV_ERR_INVALID_POINTER); + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_NOT_SUPPORTED); + + *pCounterVal = 0; + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if(pGpu == NULL){ + return NV_ERR_NOT_SUPPORTED; + } + + pOs = SYS_GET_OS(pSys); + if(pOs == NULL){ + return NV_ERR_NOT_SUPPORTED; + } + + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + + // Is the Id within range? + if (counterId >= PFM_REQ_HNDLR_NUM_COUNTERS) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid counter Id specified = %d.\n", + counterId); + DBG_BREAKPOINT(); + status = NV_ERR_NOT_SUPPORTED; + goto pfmreqhndlrGetPerfSensorCounterById_IMPL_exit; + } + // is the counter available? + if ((!pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bSupported) && + (!pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bVolatile)) + { + goto pfmreqhndlrGetPerfSensorCounterById_IMPL_exit; + } + + // Has the counter gone stale since the last sampling? + if (_pfmreqhndlrIsCacheEntryStale(pPfmreqhndlrData, counterId, timeStamp)) + { + // sample the counter + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // 2X path + status = pfmreqhndlrSampleCounter(pPlatformRequestHandler, counterId, timeStamp); + if (status != NV_OK) + { + if (status == NV_ERR_NOT_SUPPORTED) + { + // OK to sample unsupported counters (and fall through). + status = NV_OK; + } + else + { + // Fail for any other error code (and bail) + NV_PRINTF(LEVEL_ERROR, + "Sampling counter failed for counter id = %d.\n", + counterId); + DBG_BREAKPOINT(); + goto pfmreqhndlrGetPerfSensorCounterById_IMPL_exit; + } + } + } + else + { + // 1X path + pfmreqhndlrSampleCounter(pPlatformRequestHandler, counterId, timeStamp); + } + } + // + // NOTE per spec, some counters may be reported as available, + // but may not be available under some conditions. + // I.E. pshare params may report a counter as available when supported fields are queried, + // but the limits are only available if the SBIOS wants that particular sensor limited. + // so these sensors may be intermittently available. + // to check for this case, check to see if the counter is still stale. + // + if (!_pfmreqhndlrIsCacheEntryStale(pPfmreqhndlrData, counterId, timeStamp) && + !pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bInvalid) + { + // the counter is not stale, + // copy it to the output + *pCounterVal = pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].value; + status = NV_OK; + goto pfmreqhndlrGetPerfSensorCounterById_IMPL_exit; + } + +pfmreqhndlrGetPerfSensorCounterById_IMPL_exit: + return status; +} + +NV_STATUS +pfmreqhndlrHandleStatusChangeEvent +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + NvU32 data = 0; + NvBool bIsPctrlSupported = NV_TRUE; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + // get the latest pshare status + status = _pfmreqhndlrCallPshareStatus(pPlatformRequestHandler, NV_FALSE); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("PshareStatus", status); + } + + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // Additionally if PCONTROL subfunction is supported call it + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams; + + portMemSet((void *) &acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT; + acpiParams.ctrl.input = 0; + acpiParams.output.pBuffer = NULL; + acpiParams.output.bufferSz = 0; + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("supported subfunction", status); + goto pfmreqhndlrHandleStatusChangeEvent_exit; + } + if (0 == (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _SUPPORTED, _PCONTROL_AVAIL, acpiParams.output.result[1]))) + { + // PCONTTOL is not supported on 2X, can be hard coded + bIsPctrlSupported = NV_FALSE; + } + } + + if (bIsPctrlSupported) + { + status = pfmreqhndlrPcontrol(pPlatformRequestHandler, data, NV_TRUE); + if (status != NV_OK) + { + NV_ASSERT_FAILED("Pcontrol command"); + goto pfmreqhndlrHandleStatusChangeEvent_exit; + } + } + +pfmreqhndlrHandleStatusChangeEvent_exit: + return status; +} + +/*! + * Helper routine to check PM1 Available Status + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[out] bIsPm1Available Status of PM1 Availability + * + * @return NV_OK if RMAPI call was succesful. + * @return bubble up errors from called RMAPI + */ + +NV_STATUS +pfmreqhndlrHandleCheckPM1Available_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvBool *pbPM1Available +) +{ + NV_STATUS status = NV_ERR_GENERIC; + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.flag = NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + *pbPM1Available = params.bStatus; + } + + return status; +} + +/*! + * Handler routine to Update or Reset EDPpeak limit of GPU + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[in] bEnable Enable or Reset the settings. + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return NV_ERR_INVALID_STATE for invalid PMU state + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandleEdppeakLimitUpdate_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvBool bEnable +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = NV_OK; + + if (gpuIsGpuFullPower(pGpu)) + { + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS params = { 0 }; + + params.bEnable = bEnable; + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT, + ¶ms, + sizeof(params)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error updating EDPpeak Limit State: 0x%08x\n", status); + DBG_BREAKPOINT(); + } + else + { + // Update the cached enable bit, if everything went well + pPlatformRequestHandler->controlData.bEDPpeakUpdateEnabled = bEnable; + } + } + + return status; +} + +/*! + * Handler routine to Update or Reset EDPpeak limit from platform + * + * @param[in] pPlatformRequestHandler PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[in] platformEdppLimit Platform EDPpeak limit value + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return NV_ERR_INVALID_STATE for invalid PMU state + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandlePlatformEdppLimitUpdate_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvU32 platformEdppLimit +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = NV_OK; + + if (gpuIsGpuFullPower(pGpu)) + { + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS params = { 0 }; + + params.clientLimit = platformEdppLimit; + params.bEnable = NV_TRUE; + + // Platform can remove its EDPp and fall back to GPU default by setting a limit of value 0 + if (platformEdppLimit == 0) + { + params.bEnable = NV_FALSE; + } + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT, + ¶ms, + sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error updating EDPpeak Limit State: 0x%08x\n", status); + DBG_BREAKPOINT(); + } + } + + return status; +} + +/*! + * Handle EDPpeak new limit query from platform + * + * @param[in] pPlatformRequestHandler PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[in] pPlatformEdppLimit Pointer to Platform EDPpeak limit value + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandlePlatformGetEdppLimit_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvU32 *pPlatformEdppLimit +) +{ + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams; + NV_STATUS status = NV_OK; + + portMemSet((void*)&acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETEDPPLIMIT; + + // Input is V1 + acpiParams.ctrl.input = NV0000_CTRL_PFM_REQ_HNDLR_EDPP_VERSION_V10; + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error querying EDPpeak Limit from platform: 0x%08x\n", status); + DBG_BREAKPOINT(); + status = NV_ERR_NOT_SUPPORTED; + goto _pfmreqhndlrHandlePlatformGetEdppLimit_IMPL_IMPL_exit; + } + + *pPlatformEdppLimit = acpiParams.output.result[0]; + +_pfmreqhndlrHandlePlatformGetEdppLimit_IMPL_IMPL_exit: + return status; +} + +/*! + * Handle send GPU EDPpeak limit info to platform + * + * @param[in] pPlatformRequestHandler PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * + * @return NV_OK if the update was successful. + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandlePlatformSetEdppLimitInfo_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = NV_OK; + PFM_REQ_HNDLR_EDPP_DATA *pEdppLimit = + &pPlatformRequestHandler->controlData.edppLimit; + + if (gpuIsGpuFullPower(pGpu)) + { + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS params = { 0 }; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO, + ¶ms, + sizeof(params)); + if (status == NV_OK) + { + pEdppLimit->edppLimitInfo.limitMin = params.limitMin; + pEdppLimit->edppLimitInfo.limitRated = params.limitRated; + pEdppLimit->edppLimitInfo.limitMax = params.limitMax; + pEdppLimit->edppLimitInfo.limitCurr = params.limitCurr; + pEdppLimit->edppLimitInfo.limitBattRated = params.limitBattRated; + pEdppLimit->edppLimitInfo.limitBattMax = params.limitBattMax; + pEdppLimit->edppLimitInfo.rsvd = 0; + pEdppLimit->status = NV_OK; + } + else + { + pEdppLimit->status = NV_ERR_INVALID_ARGUMENT; + } + } + else + { + pEdppLimit->status = NV_ERR_GPU_NOT_FULL_POWER; + } + + if (!pEdppLimit->bWorkItemPending) + { + OBJOS *pOS = GPU_GET_OS(pGpu); + + // Queue workitem to send the EDP limit info to platform + status = pOS->osQueueWorkItem(pGpu, + _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem, NULL); + if(status == NV_OK) + { + pEdppLimit->bWorkItemPending = NV_TRUE; + } + } + + return status; +} + +/*! + * Handler routine to enable or Reset GPU User Configurable TGP mode + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] pGpu GPU object pointer + * @param[in] bEnable Enable or Reset the settings. + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return NV_ERR_INVALID_STATE for invalid PMU state + * @return bubble up errors triggered by called code + */ +NV_STATUS +pfmreqhndlrHandleUserConfigurableTgpMode_IMPL +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvBool bEnable +) +{ + NV_STATUS status = NV_ERR_GENERIC; + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.bEnable = bEnable; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE, + ¶ms, + sizeof(params)); + if (status == NV_OK) + { + // Update the cached enable bit, if everything went well + pPlatformRequestHandler->controlData.bUserConfigTGPmodeEnabled = bEnable; + } + + return status; +} + +/* ---------------------- Static Functions --------------------------------- */ + +static NV_STATUS +_handleCmdSystemPfmreqhndlrGetSupportedFunctions +( + PlatformRequestHandler + *pPlatformRequestHandler, + NvU16 locale, + NvU32 *pData +) +{ + OBJGPU* pGpu = NULL; + + *pData = 0; + + + if (locale != NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM) + { + return NV_ERR_INVALID_COMMAND; + } + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + if (pGpu == NULL) + { + return NV_ERR_INVALID_STATE; + } + + *pData |= (NV_OK == testIfDsmSubFunctionEnabled(pGpu, pPlatformRequestHandler->dsmVersion, + NV_ACPI_ALL_FUNC_SUPPORT)) ? + NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT : 0; + + return NV_OK; +} + +static NV_STATUS +_handleCmdSystemPfmreqhndlrDataInitUsingSbiosAndAck +( + PlatformRequestHandler + *pPlatformRequestHandler, + NvU16 locale, + NvU32 *pData +) +{ + OBJGPU *pGpu; + NV_STATUS status = NV_OK; + + if (locale != NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM) + { + return NV_ERR_INVALID_COMMAND; + } + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + + /* Full GPU check to ensure device is on */ + NV_ASSERT_OR_RETURN(FULL_GPU_SANITY_CHECK(pGpu), NV_ERR_INVALID_STATE); + + if (pPlatformRequestHandler->getProperty(pPlatformRequestHandler, PDB_PROP_PFMREQHNDLR_SUPPORTED)) + { + status = pfmreqhndlrHandleStatusChangeEvent(pPlatformRequestHandler, pGpu); + } + else + { + status = NV_ERR_NOT_SUPPORTED; + } + + return status; +} + +/*! + * Get a current 32 bit timestamp in MS + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + * @return 32 bit MS timestamp. + */ +static NvU32 +_pfmreqhndlrGetTimeStamp +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU32 timeStamp = 0; + + timeStamp = (NvU32)(tmrGetTime_HAL(pGpu, pTmr) / 1000000L); + + return timeStamp; +} + +/*! + * Configure a counter with an override value. + * + * @param[in] pPfmreqhndlrData pointer to the PlatformRequestHandler data structure + * @param[in] id identifier of counter to whose Override should be canceled. + * @param[in] value new value for the specified counter. All values are accepted as + * unsigned integers, but internally they should be formatted based on the + * type of id/sensor they correspond to. + * @param[in] timeStamp current time stamp in MS used to indicate when the counter was last updated + * + */ +static void +_pfmreqhndlrOverrideCounter +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvU32 value, + NvU32 timeStamp +) +{ + // update the counter with the new value. + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, id, NV_TRUE, value, timeStamp); + + // lock it in as an overriden value. + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden = NV_TRUE; +} + +/*! + * Cancel an override of a specified counter. + * + * @param[in] pPfmreqhndlrData pointer to the PlatformRequestHandler data structure + * @param[in] id Identifier of counter to whose Override should be canceled. + * @param[in] timeStamp current time stamp in MSused to indicate when the caounter was last updated + * + * @note if a non-volatile counter has its override canceled, it may not be refreshed as part of a query, + * it is up to the calling function to ensure that the counter is placed in a valid (I.E. updated) state. + */ +static void +_pfmreqhndlrCancelCounterOverride +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvU32 timeStamp +) +{ + if (pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden) + { + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden = NV_FALSE; + _pfmreqhndlrResetCounter(pPfmreqhndlrData, id, timeStamp); + } +} + +/*! + * place the counter into a reset state where it does not contain a valid value, and the sample is expired. + * it updates the counter so that the value is marked as invalid & the timestamp + * is set so that the counter can be updated + * + * @param[in] pPfmreqhndlrData Pointer to the PlatformRequestHandler data structure + * @param[in] id Identifier of counter to which should be marked invalid. + * + * @note if a non-volatile counter is marked as invalid, it may not be refreshed as part of a query, + * it is up to the calling function to ensure that the counter is placed in a valid (I.E. updated) state. + */ +static void +_pfmreqhndlrResetCounter +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvU32 timeStamp +) +{ + if (!pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden) + { + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bInvalid = NV_TRUE; + + // use a timestamp that marks the value as stale in order to ensure that + // volatile counters are refreshed prior to being reported. + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].lastSampled = timeStamp - NV_MAX(pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].minInterval, pPfmreqhndlrData->counterHoldPeriod) - 1; + } +} + +/*! + * Update a counter to a specified state (valid/invalid) & value. + * it updates the specified counter based on the result of the sampling + * (as reported in bValid) and the value provided. + * + * @param[in] pPfmreqhndlrData pointer to the PlatformRequestHandler data structure + * @param[in] id identifier of counter to be updated. + * @param[in] bValid a bool indicating a valid value is being provided for the counter. + * @param[in] value new value for the specified counter. All values are accepted as + * unsigned integers, but internally they should be formatted based on the + * type of id/sensor they correspond to. + * @param[in] timeStamp current time stamp in MS used to indicate when the counter was last updated + * + */ +static void +_pfmreqhndlrUpdateCounter +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvBool bValid, + NvU32 value, + NvU32 timeStamp +) +{ + if (bValid || pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden) + { + // only update the value if the current value is not an override. + if (!pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bOverridden) + { + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].value = value; + } + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].lastSampled = timeStamp; + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bInvalid = NV_FALSE; + } + else + { + // The counter is not valid or overridden, mark it as invalid. + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bInvalid = NV_TRUE; + } +} + +/*! + * Enables/disables PM1 (boost clocks). + * + * @param[in] pGpu OBJGPU pointer + * @param[in] bEnable Boolean value to turn on/off PM1 (boost clocks) + * + * @return NV_OK PM1 (boost clocks) successfully enabled/disabled + * @return NV_ERR_NOT_SUPPORTED PM1 (boost clocks) not supported + * @return NV_ERR_INVALID_STATE Could not enable/disable PM1 + */ +static NV_STATUS +_pfmreqhndlrEnablePM1 +( + OBJGPU *pGpu, + NvBool bEnable +) +{ + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.bEnable = bEnable; + + return pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE, + ¶ms, + sizeof(params)); +} + +/*! + * Sample and update the Platform Power Mode data. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object poiner + * @param[in] pGpu OBJGPU object pointer + * @param[in] If called from PlatformRequestHandler init sequence + * + * @return NV_OK on success + * @return Bubble up error otherwise + */ + +static NV_STATUS +_pfmreqhndlrUpdatePpmdLimit +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu, + NvBool bInit +) +{ + NV_STATUS status = NV_OK; + PFM_REQ_HNDLR_PPM_DATA *pPpmData = NULL; + NvU32 counterVal = 0; + NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS params = { 0 }; + NvU32 info32 = 0; + + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR), + &counterVal); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("PlatformRequestHandler failed to get platform power mode from SBIOS", status); + goto _pfmreqhndlrUpdatePpmdLimit_exit; + } + + if (PFM_REQ_HNDLR_IS_COUNTER_VALID(pPlatformRequestHandler, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR))) + { + pPpmData = &(pPlatformRequestHandler->ppmData); + + // Update the power mode mask as received from the platform + pPpmData->ppmMaskCurrent = + DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PPM, _MASK, counterVal); + + // + // Cache the platform requested power mode during init time only. + // Runtime, the system request should result in a client notification only. + // + if (bInit) + { + pPpmData->ppmIdxCurrent = + DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PPM, _INDEX, counterVal); + } + + // Notify clients with the new limits + params.platformPowerModeIndex = DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _PPM, _INDEX, counterVal); + params.platformPowerModeMask = pPpmData->ppmMaskCurrent; + params.eventReason = NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION; + + info32 = (params.platformPowerModeIndex << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX)) | + (params.platformPowerModeMask << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK)) | + (params.eventReason << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON)); + + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE, ¶ms, sizeof(params), info32, 0); + } + +_pfmreqhndlrUpdatePpmdLimit_exit: + return status; +} + +static NV_STATUS +_pfmreqhndlrUpdateTgpuLimit +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + NvU32 counterVal; + NvTemp targetTemp = PFM_REQ_HNDLR_TEMP_0_C; + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + // note -- we need to go through the call to ensure any override is honored. + status = pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), + &counterVal); + + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("PlatformRequestHandler failed to get target temp from SBIOS", status); + return status; + } + + targetTemp = NV_TYPES_CELSIUS_TO_NV_TEMP(counterVal); + + // 2x operation + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // 2X operation Will not allow a 0C default value from SBIOS to SWTC interface + if (targetTemp == PFM_REQ_HNDLR_TEMP_0_C) + { + // The VBIOS default limit takes effect + status = NV_OK; + return status; + } + } + + + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS params = { 0 }; + params.targetTemp = targetTemp; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT, + ¶ms, + sizeof(params)); + + return status; +} + +/*! + * @brief helper function to update each system control parameter. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] id Identifier of counter to update + */ +static NV_STATUS +_pfmreqhndlrUpdateSystemParamLimit(PlatformRequestHandler *pPlatformRequestHandler, NvU32 id) +{ + NV_STATUS status; + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + + switch (id) + { + case PFM_REQ_HNDLR_TGPU_SENSOR: + { + status = _pfmreqhndlrUpdateTgpuLimit(pPlatformRequestHandler, pGpu); + break; + } + default: + { + status = NV_ERR_NOT_SUPPORTED; + break; + } + } + + return status; +} + +/*! + * @brief passive worker thread to platform power mode. + * + * @param[in] gpuInstance GPU instance ID + * @param[in] newIndex requested Platform Power Mode Index + */ +static void +_pfmreqhndlrUpdatePlatformPowerModeWorkItem +( + NvU32 gpuInstance, + void *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + NvU32 status = NV_OK; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX acpiParamsEx = {0}; + NvU32 gpuLockFlag = GPUS_LOCK_FLAGS_NONE; + + if (FULL_GPU_SANITY_CHECK(pGpu)) + { + // Attempt to acquire locks/semaphore + if (pfmreqhndlrPassiveModeTransition(NV_TRUE, API_LOCK_FLAGS_NONE, + gpuLockFlag) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to acquire the locks/semaphore!\n"); + goto pfmreqhndlrUpdatePlatformPowerModeWorkItemExit; + } + + // Call ACPI to set the new platform power mode + acpiParamsEx.inSize = NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_COUNT * sizeof(NvU32); + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_VERSION_IDX] = + FLD_SET_DRF(0000_CTRL_PFM_REQ_HNDLR, _PPM_ARG0_VERSION, _MAJOR, _V1, + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_VERSION_IDX]); + acpiParamsEx.outSize = NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_COUNT * sizeof(NvU32); + acpiParamsEx.pfmreqhndlrFunc = GPS_FUNC_SETPPM; + acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_IDX] = + FLD_SET_DRF_NUM(0000_CTRL_PFM_REQ_HNDLR, _PPM_ARGS, _INDEX, + pPlatformRequestHandler->ppmData.ppmIdxRequested, acpiParamsEx.input[NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_IDX]); + + status = pfmreqhndlrCallACPI_EX(pGpu, &acpiParamsEx); + + // + // If ACPI call is successful, cache the new Index for future Get PPM calls + // and notify NvCPL + // + if (NV_OK == status) + { + NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS params = {0}; + NvU32 info32 = 0; + pPlatformRequestHandler->ppmData.ppmIdxCurrent = pPlatformRequestHandler->ppmData.ppmIdxRequested; + params.platformPowerModeIndex = pPlatformRequestHandler->ppmData.ppmIdxCurrent; + params.platformPowerModeMask = pPlatformRequestHandler->ppmData.ppmMaskCurrent; + params.eventReason = NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION; + + info32 = (params.platformPowerModeIndex << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX)) | + (params.platformPowerModeMask << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK)) | + (params.eventReason << DRF_SHIFT(NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON)); + + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE, ¶ms, sizeof(params), info32, 0); + } + + // Release locks/semaphore + pfmreqhndlrPassiveModeTransition(NV_FALSE, API_LOCK_FLAGS_NONE, gpuLockFlag); + } + +pfmreqhndlrUpdatePlatformPowerModeWorkItemExit: + // Reset on exit + pPlatformRequestHandler->ppmData.ppmIdxRequested = NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID; + pPlatformRequestHandler->ppmData.bWorkItemPending = NV_FALSE; +} + +/*! + * @brief passive worker thread to update the system control parameters. + * + * @param[in] gpuInstance GPU instance ID + * @param[in] pParam unused + */ +static void +_pfmreqhndlrUpdateSystemParamLimitWorkItem +( + NvU32 gpuInstance, + void *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NvU32 id; + + // Attempt to acquire locks/semaphore + if (pfmreqhndlrPassiveModeTransition(NV_TRUE, API_LOCK_FLAGS_NONE, GPUS_LOCK_FLAGS_NONE) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to acquire the locks/semaphore!\n"); + + pPlatformRequestHandler->sysControlData.bWorkItemPending = NV_FALSE; + return; + } + + FOR_EACH_INDEX_IN_MASK(32, id, pPlatformRequestHandler->sysControlData.queuedCounterMask) + { + _pfmreqhndlrUpdateSystemParamLimit(pPlatformRequestHandler, id); + } + FOR_EACH_INDEX_IN_MASK_END; + + pPlatformRequestHandler->sysControlData.bWorkItemPending = NV_FALSE; + pPlatformRequestHandler->sysControlData.queuedCounterMask = 0; + + // Release locks/semaphore + pfmreqhndlrPassiveModeTransition(NV_FALSE, API_LOCK_FLAGS_NONE, GPUS_LOCK_FLAGS_NONE); +} + +/*! + * + * _pfmreqhndlrCallPshareStatus + * + * This function makes the PSHARESTATUS ACPI call. It sets up the call based on + * the ACPI cache & updates the cache with the results. + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * @param[in] bInit If called from PlatformRequestHandler init sequence + * + * @return NV_OK if the update was successful. + * @return NV_ERR_INVALID_STATE for invalid PMU state + * @return bubble up errors triggered by called code + */ +static NV_STATUS +_pfmreqhndlrCallPshareStatus +( + PlatformRequestHandler *pPlatformRequestHandler, + NvBool bInit +) +{ + OBJGPU *pGpu = NULL; + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = NULL; + NV_STATUS status = NV_OK; + NV_STATUS lclStatus = NV_OK; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS + acpiParams; + NvU32 timeStamp; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_INVALID_REQUEST); + + pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + pPfmreqhndlrData = &pPlatformRequestHandler->sensorData; + + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS; + acpiParams.ctrl.input = 0; + acpiParams.output.pBuffer = NULL; + acpiParams.output.bufferSz = 0; + + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + + if (NV_OK == status) + { + NvBool bQueryEdppRequired = NV_FALSE; + NvBool bPlatformEdpUpdate = NV_FALSE; + + // Platform EDPp limit handling check + bQueryEdppRequired = FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _PLATFORM_GETEDPPEAKLIMIT_SET, _TRUE, acpiParams.output.result[0]); + bPlatformEdpUpdate = FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _PLATFORM_SETEDPPEAKLIMITINFO_SET, _TRUE, acpiParams.output.result[0]); + + // update the cache values + pPfmreqhndlrData->PFMREQHNDLRACPIData.bSystemParamLimitUpdate = FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _UPDATE_LIMIT, _PENDING, acpiParams.output.result[0]); + + pPfmreqhndlrData->PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest = + FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _EDPPEAK_LIMIT_UPDATE, _TRUE, acpiParams.output.result[0]); + pPfmreqhndlrData->PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest = + FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _USER_CONFIG_TGP_MODE, _ENABLE, acpiParams.output.result[0]); + pPfmreqhndlrData->PFMREQHNDLRACPIData.bPlatformUserConfigTGPSupport = + FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARESTATUS, _PLAT_USER_CONFIG_TGP_MODE_SUPPORT, _ENABLE, acpiParams.output.result[0]); + + // + // 1.A. EDPpeak limit update: Handle the legacy way where a VBIOS static limit is applied + // Update only if in reset state and Reset only if is in enabled state + // + if (PFM_REQ_HNDLR_IS_EDPPEAK_UPDATE_REQUIRED(pPfmreqhndlrData->PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest, + pPlatformRequestHandler->controlData.bEDPpeakUpdateEnabled) && !bInit) + { + // Update or Reset the EDPp limit if needed + lclStatus = pfmreqhndlrHandleEdppeakLimitUpdate(pPlatformRequestHandler, pGpu, + pPfmreqhndlrData->PFMREQHNDLRACPIData.bEDPpeakLimitUpdateRequest); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + + // + // 1.B. EDPpeak limit update : Handle platform supplied limit + // + if (bQueryEdppRequired) + { + NvU32 platformEdppLimit = 0; + + // Query platform for the new EDPp value + lclStatus = pfmreqhndlrHandlePlatformGetEdppLimit(pPlatformRequestHandler, pGpu, &platformEdppLimit); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + else + { + // Cache the EDPp limit from platform request + pPfmreqhndlrData->PFMREQHNDLRACPIData.platformEdppLimit = platformEdppLimit; + } + + if (bInit) + { + // Defer init time EDPp update after prereq is satisfied + pPlatformRequestHandler->controlData.edppLimit.bDifferPlatformEdppLimit = NV_TRUE; + } + else + { + // Followed by apply the platform limit on the GPU + lclStatus = pfmreqhndlrHandlePlatformEdppLimitUpdate(pPlatformRequestHandler, pGpu, + pPfmreqhndlrData->PFMREQHNDLRACPIData.platformEdppLimit); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + } + + // + // 2. User configurable TGP mode (Turbo) Update + // Enable only if in reset state and Reset only if in enabled state + // + if (PFM_REQ_HNDLR_IS_USER_CONFIG_TGP_MODE_UPDATE_REQUIRED(pPfmreqhndlrData->PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest, + pPlatformRequestHandler->controlData.bUserConfigTGPmodeEnabled) && !bInit) + { + // Enable or Reset the configurable TGP mode if needed + lclStatus = pfmreqhndlrHandleUserConfigurableTgpMode(pPlatformRequestHandler, pGpu, + pPfmreqhndlrData->PFMREQHNDLRACPIData.bUserConfigTGPmodeRequest); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + + // 3. Platform static customization for user config TGP can be handled here one time + if ((pPfmreqhndlrData->PFMREQHNDLRACPIData.bPlatformUserConfigTGPSupport) && + (!pPlatformRequestHandler->controlData.bPlatformUserConfigTGPmodeEnabled) && + (bInit)) + { + lclStatus = _pfmreqhndlrHandleUserConfigurableTgpModePlatformCustomization(pPlatformRequestHandler, pGpu); + if ((NV_OK != lclStatus) && + (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + + if (pPfmreqhndlrData->PFMREQHNDLRACPIData.bSystemParamLimitUpdate) + { + timeStamp = _pfmreqhndlrGetTimeStamp(pPlatformRequestHandler); + _pfmreqhndlrResetCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), timeStamp); + _pfmreqhndlrResetCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR), timeStamp); + + lclStatus = _pfmreqhndlrUpdateTgpuLimit(pPlatformRequestHandler, pGpu); + if ((NV_OK == status) && (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + + if (PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler)) + { + // Run time PPMD update from the system + lclStatus = _pfmreqhndlrUpdatePpmdLimit(pPlatformRequestHandler, pGpu, NV_FALSE); + if ((NV_OK == status) && (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + + // Reset the system parameter update flag + pPfmreqhndlrData->PFMREQHNDLRACPIData.bSystemParamLimitUpdate = NV_FALSE; + } + + if (bPlatformEdpUpdate) + { + lclStatus = pfmreqhndlrHandlePlatformSetEdppLimitInfo(pPlatformRequestHandler, pGpu); + if ((NV_OK != lclStatus) && (NV_ERR_NOT_SUPPORTED != lclStatus)) + { + status = lclStatus; + } + } + } + + return status; +} + +/*! + * Setup the initial state for the given counter as a supported counter. + * + * @param[in] pPfmreqhndlrData Pointer to the Sensor Data cache. + * @param[in] id Identifier of counter to be updated. + * @param[in] bVolatile bool indicating if the counter is volatile or not. + * Volatile counters can go stale & will be sampled + * on request for a sampling, whereas it is the + * responsability of the code associated with controlling + * the counter value to update a non-volatile counter. + * @param[in] timeStamp current time stamp in MS used to create a stale + * timestamp if needed to ensure that the first time + * the counter is querried we try to sample it. + * + */ +static void +_pfmreqhndlrInitSupportedCounter +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 id, + NvBool bVolatile, + NvU32 timeStamp +) +{ + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bSupported = NV_TRUE; + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].bVolatile = bVolatile; + pPfmreqhndlrData->PFMREQHNDLRSensorCache[id].minInterval = PFM_REQ_HNDLR_DEFAULT_COUNTER_HOLD_PERIOD_MS; + _pfmreqhndlrResetCounter(pPfmreqhndlrData, id, timeStamp); +} + +// +// _pfmreqhndlrGetPerfSensorCounters +// +// This function collects the requested counters and returns those that are actually available. +// +NV_STATUS +pfmreqhndlrGetPerfSensorCounters +( + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams, + NvU16 mapFlags +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + NvU32 counterMask; + NvU32 counterVal; + NvU16 idx; + + NV_ASSERT_OR_RETURN(NULL != pPlatformRequestHandler, NV_ERR_NOT_SUPPORTED); + + // is the block Id within range? + if (pParams->blockId >= PFM_REQ_HNDLR_AVAILABLE_SENSOR_BLOCKS) + { + return NV_ERR_NOT_SUPPORTED; + } + + // run thru & get each counter specified in the request mask. + for (idx = 0; idx < PFM_REQ_HNDLR_MAX_SENSORS_IN_BLOCK; ++idx) + { + pParams->counterBlock[idx] = 0; + counterMask = (1 << idx); + + // are we interested in this counter? + if (((pParams->countersReq & counterMask) != 0) && + ((PerfSensorBlockMap[pParams->blockId][idx] & mapFlags) == mapFlags)) + { + if (NV_OK == pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, + PFM_REQ_HNDLR_PSR_ID(PerfSensorBlockMap[pParams->blockId][idx]), + &counterVal)) + { + pParams->counterBlock[idx] = counterVal; + pParams->countersReturned |= counterMask; + } + } + } + + return NV_OK; +} + +// +// _pfmreqhndlrIsCacheEntryStale +// +// This function returns a bool indicating if the specified cache entry is stale. +// +static NvBool +_pfmreqhndlrIsCacheEntryStale +( + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData, + NvU32 counterId, + NvU32 timeStamp +) +{ + NvU32 age; + NvBool bStale = NV_FALSE; + + // if the counter is Volatile, check to see if it has aged out. + if ((pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bVolatile) && + (!pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].bOverridden)) + { + // calculate the age allowing for wrap. + age = timeStamp - pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].lastSampled; + + // if the age went negitive, make the age 0. + if ((NvS32)age < 0) + { + age = 0; + } + bStale = ((pPfmreqhndlrData->counterHoldPeriod < age) && (pPfmreqhndlrData->PFMREQHNDLRSensorCache[counterId].minInterval < age)); + } + return bStale; +} + +static NV_STATUS +_pfmreqhndlrSampleSensorLimit +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 timeStamp +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (!PFM_REQ_HNDLR_VALID_LIMIT_ID(id)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // Use ACPI only + status = _pfmreqhndlrSampleSensorLimit_ACPI(pPlatformRequestHandler, id, timeStamp); + + return status; +} + +static NV_STATUS +_pfmreqhndlrSampleSensorLimit_ACPI +( + PlatformRequestHandler *pPlatformRequestHandler, + NvU32 id, + NvU32 timeStamp +) +{ + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = &pPlatformRequestHandler->sensorData; + OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams = {{ 0 }}; + PFM_REQ_HNDLR_PSHAREDATA pshareParams = { 0 }; + NV_STATUS status; + NvU8 i; + + // all the counters for this case are read in a single block + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS; + acpiParams.ctrl.input = pPfmreqhndlrData->PFMREQHNDLRShareParamsAvailMask | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_QUERY_TYPE, _CURRENT_LIMITS); + + // exclude counters that are up-to-date or have forced overrides + for (i = 0; i < PFM_REQ_HNDLR_PSHAREPARAMS_COUNT; i++) + { + if (((timeStamp - pPfmreqhndlrData->PFMREQHNDLRSensorCache[PFM_REQ_HNDLR_LIMIT(i)].lastSampled) < + pPfmreqhndlrData->PFMREQHNDLRSensorCache[PFM_REQ_HNDLR_LIMIT(i)].minInterval) || + pPfmreqhndlrData->PFMREQHNDLRSensorCache[PFM_REQ_HNDLR_LIMIT(i)].bOverridden) + { + acpiParams.ctrl.input &= ~NVBIT(i + DRF_BASE(NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU)); + } + } + + // bail-out if everything is already up-to-date + if (acpiParams.ctrl.input == 0) + { + return NV_OK; + } + + acpiParams.output.pBuffer = (NvU8 *)&pshareParams; + acpiParams.output.bufferSz = sizeof(pshareParams); + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status == NV_OK) + { + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _TGPU, _TRUE, acpiParams.ctrl.input)) + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_TGPU_SENSOR), FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _TGPU, _TRUE, pshareParams.status), pshareParams.tGpu, timeStamp); + } + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _PPMD, _TRUE, acpiParams.ctrl.input)) + { + _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_LIMIT(PFM_REQ_HNDLR_PPMD_SENSOR), FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _PPMD, _TRUE, pshareParams.status), pshareParams.ppmd, timeStamp); + } + } + return status; +} + +/*! + * Set up PlatformRequestHandler control flags based on the ACPI supported subfunction lists. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * @param[in] supportedSubfuncs NvU32 supported subfunctions list from SBIOS + * + * @return NV_OK always succeeds + * + */ +static NV_STATUS +_pfmreqhndlrSetSupportedStatesFromAcpiParams +( + OBJGPU *pGpu, + PlatformRequestHandler + *pPlatformRequestHandler, + NvU32 supportedSubfuncs + +) +{ + PFM_REQ_HNDLR_SENSOR_DATA *pPfmreqhndlrData = &(pPlatformRequestHandler->sensorData); + + pPfmreqhndlrData->PFMREQHNDLRACPIData.bPfmReqHndlrSupported = + ((0 != (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _SUPPORTED, _PSHARESTATUS_AVAIL, supportedSubfuncs))) && + (0 != (DRF_VAL(0000_CTRL_PFM_REQ_HNDLR, _SUPPORTED, _PSHAREPARAMS_AVAIL, supportedSubfuncs)))); + + return NV_OK; +} + +/*! + * Handler routine to platform costumization to user mode TGP + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler object pointer + * + * @return NV_OK if the update was successful. + * @return NV_ERR_NOT_SUPPORTED if the POR support is not present + * @return bubble up errors triggered by called code + */ +static NV_STATUS +_pfmreqhndlrHandleUserConfigurableTgpModePlatformCustomization +( + PlatformRequestHandler *pPlatformRequestHandler, + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS acpiParams; + PFM_REQ_HNDLR_PSHAREDATA pshareParams; + + portMemSet((void *) &acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + portMemSet((void *) &pshareParams, 0, sizeof(PFM_REQ_HNDLR_PSHAREDATA)); + + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS; + acpiParams.ctrl.input = DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_CTGP, _TRUE) | + DRF_DEF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS, _STATUS_QUERY_TYPE, _CURRENT_LIMITS); + acpiParams.output.pBuffer = (NvU8*)&pshareParams; + acpiParams.output.bufferSz = sizeof(pshareParams); + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + status = NV_ERR_NOT_SUPPORTED; + goto _pfmreqhndlrHandleUserConfigurableTgpModePlatfromCustomization_exit; + } + + //Set the customization config tgp delta + if (FLD_TEST_DRF(0000_CTRL_PFM_REQ_HNDLR, _PSHARE_PARAMS_STATUS, _CTGP, _TRUE, pshareParams.status)) + { + // Cached the platform limit delta in the PlatformRequestHandler ACPI cache + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.platformLimitDeltamW = pshareParams.ctgp; + + // Config TGP from platform is enabled + pPlatformRequestHandler->controlData.bPlatformUserConfigTGPmodeEnabled = NV_TRUE; + + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS params = { 0 }; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.ctgpOffsetmW = pshareParams.ctgp; + + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2, + ¶ms, + sizeof(params)); + } + +_pfmreqhndlrHandleUserConfigurableTgpModePlatfromCustomization_exit: + return status; +} + +/*! + * Reset Platform Power Mode cache on PlatformRequestHandler init and PlatformRequestHandler state unload + * + * @param[in] pPlatformRequestHandler *PlatformRequestHandler pointer + * + */ +static void +_pfmreqhndlrPlatformPowerModeStateReset +( + PlatformRequestHandler *pPlatformRequestHandler +) +{ + PFM_REQ_HNDLR_PPM_DATA *pPpmData = NULL; + + pPpmData = &(pPlatformRequestHandler->ppmData); + + // Init the PPM Cache Data + pPpmData->ppmMaskCurrent = NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID; + pPpmData->ppmIdxCurrent = NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID; + pPpmData->bWorkItemPending = NV_FALSE; + pPpmData->ppmIdxRequested = NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID; +} + +/*! + * @brief passive worker thread to communcate EDPpeak info to platform. + * + * @param[in] gpuInstance GPU instance ID + * @param[in] pParams unused +*/ +static void +_pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem +( + NvU32 gpuInstance, + void *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + OBJGPU *pGpu = + pfmreqhndlrGetGpu(pPlatformRequestHandler); + PFM_REQ_HNDLR_EDPP_DATA *pEdppLimit = + &pPlatformRequestHandler->controlData.edppLimit; + NvU32 status = NV_OK; + NvU32 gpuLockFlag = GPUS_LOCK_FLAGS_NONE; + NvBool lockAcquired = NV_FALSE; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS + acpiParams; + NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1 + edppLimitInfo; + + if (FULL_GPU_SANITY_CHECK(pGpu)) + { + // Attempt to acquire locks/semaphore + if (pfmreqhndlrPassiveModeTransition(NV_TRUE, API_LOCK_FLAGS_NONE, + gpuLockFlag) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to acquire the locks/semaphore!\n"); + goto _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem_exit; + } + lockAcquired = NV_TRUE; + + portMemSet((void*)&acpiParams, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS)); + portMemSet((void*)&edppLimitInfo, 0, sizeof(NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1)); + + edppLimitInfo.ulVersion = NV0000_CTRL_PFM_REQ_HNDLR_EDPP_VERSION_V10; + edppLimitInfo.limitLast = + pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.platformEdppLimit; + + // Fill in the other EDPpeak data if we received them from GPU successfully + if (pEdppLimit->status == NV_OK) + { + edppLimitInfo.limitMin = pEdppLimit->edppLimitInfo.limitMin; + edppLimitInfo.limitRated = pEdppLimit->edppLimitInfo.limitRated; + edppLimitInfo.limitMax = pEdppLimit->edppLimitInfo.limitMax; + edppLimitInfo.limitCurr = pEdppLimit->edppLimitInfo.limitCurr; + edppLimitInfo.limitBattRated = pEdppLimit->edppLimitInfo.limitBattRated; + edppLimitInfo.limitBattMax = pEdppLimit->edppLimitInfo.limitBattMax; + } + + // Call the platform and communicate the EDPp info + acpiParams.ctrl.cmd = NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETEDPPLIMITINFO; + + acpiParams.output.pBuffer = (NvU8*)&edppLimitInfo; + acpiParams.output.bufferSz = sizeof(edppLimitInfo); + + status = pfmreqhndlrCallACPI(pGpu, &acpiParams); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + goto _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem_exit; + } + + } + +_pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem_exit: + + // Make workitem available + pEdppLimit->bWorkItemPending = NV_FALSE; + if (lockAcquired) + { + // Release locks/semaphore + pfmreqhndlrPassiveModeTransition(NV_FALSE, API_LOCK_FLAGS_NONE, gpuLockFlag); + } + return; +} + +/* + * NOTE. HOSUNGK. These functions are for backwards compatibility with KMD and NvAPI + * These will be removed after promotion from bugfix_main + */ +NV_STATUS +cliresCtrlCmdSystemGpsCtrl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemGpsGetFrmData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemGpsSetFrmData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS *pParams +) +{ + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemGpsCallAcpi_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *pParams +) +{ + return NV_OK; +} diff --git a/src/nvidia/src/kernel/power/gpu_boost_mgr.c b/src/nvidia/src/kernel/power/gpu_boost_mgr.c index 14f222feee..1d881dee24 100644 --- a/src/nvidia/src/kernel/power/gpu_boost_mgr.c +++ b/src/nvidia/src/kernel/power/gpu_boost_mgr.c @@ -643,6 +643,8 @@ _gpuboostmgrApplyPolicyFilters(NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *pBoostConfig) for (i = 1; i < pBoostConfig->gpuCount; i++) { pGpuItr = gpumgrGetGpuFromId(pBoostConfig->gpuIds[i]); + NV_ASSERT_OR_RETURN(NULL != pGpuItr, NV_ERR_OBJECT_NOT_FOUND); + if (pGpuGrp == gpumgrGetGpuGrpFromGpu(pGpuItr)) { continue; diff --git a/src/nvidia/src/kernel/rmapi/alloc_free.c b/src/nvidia/src/kernel/rmapi/alloc_free.c index 1d2e0913d7..0dd98174fd 100644 --- a/src/nvidia/src/kernel/rmapi/alloc_free.c +++ b/src/nvidia/src/kernel/rmapi/alloc_free.c @@ -547,6 +547,7 @@ _rmAlloc NvHandle *phObject, NvU32 hClass, NvP64 pUserAllocParams, + NvU32 paramsSize, NvU32 allocFlags, NvU32 allocInitStates, RS_LOCK_INFO *pLockInfo, @@ -569,6 +570,7 @@ _rmAlloc rmAllocParams.pSecInfo = &secInfo; rmAllocParams.pResourceRef = NULL; rmAllocParams.pAllocParams = NvP64_VALUE(pUserAllocParams); + rmAllocParams.paramsSize = paramsSize; rmAllocParams.pLockInfo = pLockInfo; rmAllocParams.pRightsRequested = NvP64_VALUE(pRightsRequested); rmAllocParams.pRightsRequired = NULL; @@ -624,6 +626,7 @@ static NV_STATUS _serverAllocValidatePrivilege ( + RsServer *pServer, RS_RESOURCE_DESC *pResDesc, RS_RES_ALLOC_PARAMS *pParams ) @@ -715,7 +718,7 @@ serverAllocResourceUnderLock NV_ASSERT_OK_OR_RETURN(_fixupAllocParams(&pResDesc, pRmAllocParams)); rmapiResourceDescToLegacyFlags(pResDesc, &pLockInfo->flags, NULL); - status = _serverAllocValidatePrivilege(pResDesc, pRmAllocParams); + status = _serverAllocValidatePrivilege(pServer, pResDesc, pRmAllocParams); if (status != NV_OK) goto done; @@ -917,6 +920,7 @@ serverAllocResourceUnderLock pRmAllocParams->hResource, pRmAllocParams->externalClassId, pRmAllocParams->pAllocParams, + pRmAllocParams->paramsSize, status); resservRestoreTlsCallContext(pOldContext); @@ -996,10 +1000,6 @@ serverResLock_Epilogue NvU32 *pReleaseFlags ) { - NvU32 gpuLockFlags = GPUS_LOCK_FLAGS_NONE; - if (access == LOCK_ACCESS_READ) - gpuLockFlags |= GPU_LOCK_FLAGS_READ; - if (*pReleaseFlags & RM_LOCK_RELEASE_GPU_GROUP_LOCK) { // UNLOCK: release GPU group lock @@ -1109,13 +1109,14 @@ rmapiAlloc NvHandle hParent, NvHandle *phObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ) { if (!pRmApi->bHasDefaultSecInfo) return NV_ERR_NOT_SUPPORTED; - return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, phObject, hClass, NV_PTR_TO_NvP64(pAllocParams), + return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, phObject, hClass, NV_PTR_TO_NvP64(pAllocParams), paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &pRmApi->defaultSecInfo); } @@ -1127,13 +1128,14 @@ rmapiAllocWithHandle NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ) { if (!pRmApi->bHasDefaultSecInfo) return NV_ERR_NOT_SUPPORTED; - return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, &hObject, hClass, NV_PTR_TO_NvP64(pAllocParams), + return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, &hObject, hClass, NV_PTR_TO_NvP64(pAllocParams), paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &pRmApi->defaultSecInfo); } @@ -1146,6 +1148,7 @@ rmapiAllocWithSecInfo NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequested, API_SECURITY_INFO *pSecInfo @@ -1204,6 +1207,7 @@ rmapiAllocWithSecInfo phObject, hClass, pAllocParams, + paramsSize, flags, allocInitStates, pLockInfo, @@ -1335,6 +1339,7 @@ rmapiAllocWithSecInfoTls NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequested, API_SECURITY_INFO *pSecInfo @@ -1346,7 +1351,7 @@ rmapiAllocWithSecInfoTls threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = rmapiAllocWithSecInfo(pRmApi, hClient, hParent, phObject, hClass, - pAllocParams, flags, pRightsRequested, pSecInfo); + pAllocParams, paramsSize, flags, pRightsRequested, pSecInfo); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); diff --git a/src/nvidia/src/kernel/rmapi/binary_api.c b/src/nvidia/src/kernel/rmapi/binary_api.c index 661922bdda..eb91a42420 100644 --- a/src/nvidia/src/kernel/rmapi/binary_api.c +++ b/src/nvidia/src/kernel/rmapi/binary_api.c @@ -56,7 +56,7 @@ binapiprivConstruct_IMPL return NV_OK; } -NV_STATUS +NV_STATUS binapiControl_IMPL ( BinaryApi *pResource, @@ -93,9 +93,9 @@ binapiControl_IMPL rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); } return status; -} +} -NV_STATUS +NV_STATUS binapiprivControl_IMPL ( BinaryApiPrivileged *pResource, @@ -106,15 +106,15 @@ binapiprivControl_IMPL // check if CMD is NULL, return early if (RMCTRL_IS_NULL_CMD(pParams->cmd)) return NV_OK; - + // Add check if privileged client if (pParams->secInfo.privLevel >= RS_PRIV_LEVEL_USER_ROOT) { return binapiControl_IMPL(staticCast(pResource, BinaryApi), pCallContext, pParams); } - else + else { return NV_ERR_INSUFFICIENT_PERMISSIONS; } -} +} diff --git a/src/nvidia/src/kernel/rmapi/client.c b/src/nvidia/src/kernel/rmapi/client.c index 88b34609ca..8d07b94a76 100644 --- a/src/nvidia/src/kernel/rmapi/client.c +++ b/src/nvidia/src/kernel/rmapi/client.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -554,27 +554,21 @@ rmclientPostProcessPendingFreeList_IMPL return NV_OK; } -static RmClient *handleToObject(NvHandle hClient) -{ - RmClient *pClient; - return (NV_OK == serverutilGetClientUnderLock(hClient, &pClient)) ? pClient : NULL; -} - RS_PRIV_LEVEL rmclientGetCachedPrivilegeByHandle(NvHandle hClient) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); return pClient ? rmclientGetCachedPrivilege(pClient) : RS_PRIV_LEVEL_USER; } NvBool rmclientIsAdminByHandle(NvHandle hClient, RS_PRIV_LEVEL privLevel) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); return pClient ? rmclientIsAdmin(pClient, privLevel) : NV_FALSE; } NvBool rmclientSetClientFlagsByHandle(NvHandle hClient, NvU32 clientFlags) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); if (pClient) rmclientSetClientFlags(pClient, clientFlags); return !!pClient; @@ -582,20 +576,20 @@ NvBool rmclientSetClientFlagsByHandle(NvHandle hClient, NvU32 clientFlags) void rmclientPromoteDebuggerStateByHandle(NvHandle hClient, NvU32 newMinimumState) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); if (pClient) _rmclientPromoteDebuggerState(pClient, newMinimumState); } void *rmclientGetSecurityTokenByHandle(NvHandle hClient) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); return pClient ? rmclientGetSecurityToken(pClient) : NULL; } NV_STATUS rmclientUserClientSecurityCheckByHandle(NvHandle hClient, const API_SECURITY_INFO *pSecInfo) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); // // Return early if it's a null object. This is probably the allocation of @@ -857,7 +851,7 @@ NvBool rmclientIsCapableOrAdminByHandle RS_PRIV_LEVEL privLevel ) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); if (pClient == NULL) { return NV_FALSE; @@ -888,7 +882,7 @@ NvBool rmclientIsCapableByHandle NvU32 capability ) { - RmClient *pClient = handleToObject(hClient); + RmClient *pClient = serverutilGetClientUnderLock(hClient); if (pClient == NULL) { return NV_FALSE; @@ -957,7 +951,7 @@ _unregisterOSInfo NvU64 key2 = (NvU64)(staticCast(pClient, RsClient))->hClient; OsInfoMapSubmap *pSubmap = NULL; RmClient **pFind = NULL; - + pFind = multimapFindItem(&g_osInfoList, key1, key2); if (pFind != NULL) multimapRemoveItem(&g_osInfoList, pFind); @@ -965,8 +959,8 @@ _unregisterOSInfo pSubmap = multimapFindSubmap(&g_osInfoList, key1); if (pSubmap == NULL || multimapCountSubmapItems(&g_osInfoList, pSubmap) > 0) return NV_OK; - + multimapRemoveSubmap(&g_osInfoList, pSubmap); - + return NV_OK; } diff --git a/src/nvidia/src/kernel/rmapi/client_resource.c b/src/nvidia/src/kernel/rmapi/client_resource.c index 2d55a722bc..03c6149be6 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource.c +++ b/src/nvidia/src/kernel/rmapi/client_resource.c @@ -61,6 +61,7 @@ #include "jt.h" #include "nvop.h" #include "diagnostics/gpu_acct.h" +#include "platform/platform_request_handler.h" #include "gpu/external_device/gsync.h" #include "mem_mgr/virt_mem_mgr.h" #include "diagnostics/journal.h" @@ -218,7 +219,7 @@ cliresControl_Prologue_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { - NV_STATUS status = serverDeserializeCtrlDown(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags); + NV_STATUS status = serverDeserializeCtrlDown(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags); return status; } @@ -231,7 +232,7 @@ cliresControl_Epilogue_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { - NV_ASSERT_OK(serverSerializeCtrlUp(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags)); + NV_ASSERT_OK(serverSerializeCtrlUp(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags)); serverFreeSerializeStructures(pCallContext, pParams->pParams); } @@ -257,7 +258,8 @@ CliControlSystemEvent return NV_ERR_INVALID_ARGUMENT; } - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + pClient = serverutilGetClientUnderLock(hClient); + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; CliGetEventNotificationList(hClient, hClient, NULL, &pEventNotification); @@ -308,9 +310,9 @@ CliGetSystemEventStatus ) { NvU32 Head, Tail; - RmClient *pClient; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; Head = pClient->CliSysEventInfo.systemEventsQueue.Head; @@ -1941,6 +1943,99 @@ cliresCtrlCmdGpuAcctGetAccountingPids_IMPL } +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrControl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *controlParams +) +{ + OBJSYS *pSys = NULL; + PlatformRequestHandler *pPlatformRequestHandler = NULL; + NV_STATUS ret = NV_OK; + NvU32 data = 0; + + pSys = SYS_GET_INSTANCE(); + if (!pSys) + { + return NV_ERR_INVALID_REQUEST; + } + + data = controlParams->data; + + pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + if (!pPlatformRequestHandler) + { + return NV_ERR_INVALID_REQUEST; + } + + ret = pfmreqhndlrControl(pPlatformRequestHandler, controlParams->command, controlParams->locale, &data); + + if (NV_OK == ret) + { + controlParams->data = data; + } + else + { + controlParams->data = NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID; + } + + return ret; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrBatchControl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS *controlParams +) +{ + OBJSYS *pSys = NULL; + PlatformRequestHandler *pPlatformRequestHandler = NULL; + NvU32 data = 0; + NvU32 i = 0; + NvU32 cnt = 0; + + if (controlParams->cmdCount > NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX) + { + return NV_ERR_INVALID_REQUEST; + } + + pSys = SYS_GET_INSTANCE(); + if (!pSys) + { + NV_ASSERT(pSys); + return NV_ERR_INVALID_REQUEST; + } + + pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + if (!pPlatformRequestHandler) + { + NV_ASSERT(pPlatformRequestHandler); + return NV_ERR_INVALID_REQUEST; + } + + for (i = 0; i < controlParams->cmdCount; i++) + { + data = controlParams->cmdData[i].data; + if (pfmreqhndlrControl(pPlatformRequestHandler, + controlParams->cmdData[i].command, + controlParams->cmdData[i].locale, &data) == NV_OK) + { + controlParams->cmdData[i].data = data; + cnt++; + } + else + { + controlParams->cmdData[i].data = NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID; + } + } + + controlParams->succeeded = cnt; + + return NV_OK; +} + /*! * Helper to build config data from unpacked table data, * static config v2.0/2.1. @@ -3619,9 +3714,9 @@ cliresCtrlCmdSetSubProcessID_IMPL ) { NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); - RmClient *pClient; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; pClient->SubProcessID = pParams->subProcessID; @@ -3643,9 +3738,9 @@ cliresCtrlCmdDisableSubProcessUserdIsolation_IMPL ) { NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); - RmClient *pClient; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; pClient->bIsSubProcessDisabled = pParams->bIsSubProcessDisabled; @@ -3879,6 +3974,7 @@ cliresCtrlCmdClientGetAddrSpaceType_IMPL switch (memType) { case ADDR_SYSMEM: + case ADDR_EGM: pParams->addrSpaceType = NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM; break; case ADDR_FBMEM: @@ -4432,7 +4528,7 @@ cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL ) { NV_STATUS status = NV_OK; - portMemSet(pParams, 0, sizeof(*pParams)); + status = pfmreqhndlrGetPerfSensorCounters(pParams, PFM_REQ_HNDLR_PSR_PUB_TAG); return status; } @@ -4444,11 +4540,30 @@ cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_IMPL ) { NV_STATUS status = NV_OK; - portMemSet(pParams, 0, sizeof(*pParams)); + status = pfmreqhndlrGetPerfSensorCounters(pParams, 0); return status; } // GPS HOSUNGK DELETE after KMD, NvAPI changes are made +NV_STATUS +cliresCtrlCmdSystemGpsControl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS *controlParams +) +{ + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemGpsBatchControl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS *controlParams +) +{ + return NV_OK; +} NV_STATUS cliresCtrlCmdSystemGetPerfSensorCounters_IMPL @@ -4469,3 +4584,4 @@ cliresCtrlCmdSystemGetExtendedPerfSensorCounters_IMPL { return NV_OK; } + diff --git a/src/nvidia/src/kernel/rmapi/control.c b/src/nvidia/src/kernel/rmapi/control.c index c22d5c6b76..48c7ddc179 100644 --- a/src/nvidia/src/kernel/rmapi/control.c +++ b/src/nvidia/src/kernel/rmapi/control.c @@ -69,7 +69,6 @@ NV_STATUS rmControl_Deferred(RmCtrlDeferredCmd* pRmCtrlDeferredCmd) { RmCtrlParams rmCtrlParams; - RmClient *pClient; NvU8 paramBuffer[RMCTRL_DEFERRED_MAX_PARAM_SIZE]; NV_STATUS status; RS_LOCK_INFO lockInfo = {0}; @@ -108,7 +107,7 @@ rmControl_Deferred(RmCtrlDeferredCmd* pRmCtrlDeferredCmd) // client was checked when we came in through rmControl() // but check again to make sure it's still good - if (serverutilGetClientUnderLock(rmCtrlParams.hClient, &pClient) != NV_OK) + if (serverutilGetClientUnderLock(rmCtrlParams.hClient) == NULL) { status = NV_ERR_INVALID_CLIENT; goto exit; @@ -391,7 +390,6 @@ static NV_STATUS _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams, NvU32 paramsSize, NvU32 flags, RM_API *pRmApi, API_SECURITY_INFO *pSecInfo) { OBJSYS *pSys = SYS_GET_INSTANCE(); - RmClient *pClient; RmCtrlParams rmCtrlParams; RS_CONTROL_COOKIE rmCtrlExecuteCookie = {0}; NvBool bIsRaisedIrqlCmd; @@ -470,7 +468,7 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams } // Potential race condition if run lockless? - if (serverutilGetClientUnderLock(hClient, &pClient) != NV_OK) + if (serverutilGetClientUnderLock(hClient) == NULL) { rmStatus = NV_ERR_INVALID_CLIENT; goto done; @@ -686,6 +684,12 @@ NV_STATUS serverControl_ValidateCookie OBJGPU *pGpu; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + if (pCallContext == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Calling context is NULL!\n"); + return NV_ERR_INVALID_PARAMETER; + } + if (RMCFG_FEATURE_PLATFORM_GSP) { pGpu = gpumgrGetSomeGpu(); diff --git a/src/nvidia/src/kernel/rmapi/deprecated_context.c b/src/nvidia/src/kernel/rmapi/deprecated_context.c index cbdfd443b4..3752e21da2 100644 --- a/src/nvidia/src/kernel/rmapi/deprecated_context.c +++ b/src/nvidia/src/kernel/rmapi/deprecated_context.c @@ -29,13 +29,13 @@ static NV_STATUS _rmAllocForDeprecatedApi(DEPRECATED_CONTEXT *_pContext, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, void *pAllocParams) + NvHandle *phObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize) { DEPRECATED_CONTEXT_EXT *pContext = (DEPRECATED_CONTEXT_EXT *)_pContext; RM_API *pRmApi = pContext->pRmApi; return pRmApi->AllocWithSecInfo(pRmApi, hClient, hParent, phObject, - hClass, NV_PTR_TO_NvP64(pAllocParams), + hClass, NV_PTR_TO_NvP64(pAllocParams), paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &pContext->secInfo); } diff --git a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c index 695ee517d4..fb7d35996c 100644 --- a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c +++ b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c @@ -888,7 +888,7 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC case NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS); - + status = rmapiParamsRelease(¶mCopies[0]); ((NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS*)pRmCtrlParams->pParams)->buffer = paramCopies[0].pUserParams; break; diff --git a/src/nvidia/src/kernel/rmapi/entry_points.c b/src/nvidia/src/kernel/rmapi/entry_points.c index 43414c877e..decf23a53f 100644 --- a/src/nvidia/src/kernel/rmapi/entry_points.c +++ b/src/nvidia/src/kernel/rmapi/entry_points.c @@ -217,7 +217,7 @@ static void _nv04Alloc XlateUserModeArgsToSecInfo(bUserModeArgs, NV_FALSE, &secInfo); pArgs->status = pRmApi->AllocWithSecInfo(pRmApi, pArgs->hRoot, pArgs->hObjectParent, &pArgs->hObjectNew, - pArgs->hClass, pArgs->pAllocParms, RMAPI_ALLOC_FLAGS_NONE, + pArgs->hClass, pArgs->pAllocParms, pArgs->paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &secInfo); } // end of Nv04Alloc() @@ -241,7 +241,7 @@ static void _nv04AllocWithSecInfo RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); pArgs->status = pRmApi->AllocWithSecInfo(pRmApi, pArgs->hRoot, pArgs->hObjectParent, &pArgs->hObjectNew, - pArgs->hClass, pArgs->pAllocParms, RMAPI_ALLOC_FLAGS_NONE, + pArgs->hClass, pArgs->pAllocParms, pArgs->paramsSize, RMAPI_ALLOC_FLAGS_NONE, NvP64_NULL, &secInfo); } // end of _nv04AllocWithSecInfo() @@ -264,12 +264,16 @@ static void _nv04AllocWithAccess ) { RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); + NvU32 flags = RMAPI_ALLOC_FLAGS_NONE; API_SECURITY_INFO secInfo; XlateUserModeArgsToSecInfo(bUserModeArgs, NV_FALSE, &secInfo); + if (pArgs->flags & NVOS64_FLAGS_FINN_SERIALIZED) + flags |= RMAPI_ALLOC_FLAGS_SERIALIZED; + pArgs->status = pRmApi->AllocWithSecInfo(pRmApi, pArgs->hRoot, pArgs->hObjectParent, &pArgs->hObjectNew, - pArgs->hClass, pArgs->pAllocParms, RMAPI_ALLOC_FLAGS_NONE, + pArgs->hClass, pArgs->pAllocParms, pArgs->paramsSize, flags, pArgs->pRightsRequested, &secInfo); } // end of _nv04AllocWithAccess() @@ -280,9 +284,13 @@ static void _nv04AllocWithAccessSecInfo ) { RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); + NvU32 flags = RMAPI_ALLOC_FLAGS_NONE; + + if (pArgs->flags & NVOS64_FLAGS_FINN_SERIALIZED) + flags |= RMAPI_ALLOC_FLAGS_SERIALIZED; pArgs->status = pRmApi->AllocWithSecInfo(pRmApi, pArgs->hRoot, pArgs->hObjectParent, &pArgs->hObjectNew, - pArgs->hClass, pArgs->pAllocParms, RMAPI_ALLOC_FLAGS_NONE, + pArgs->hClass, pArgs->pAllocParms, pArgs->paramsSize, flags, pArgs->pRightsRequested, &secInfo); } // end of _nv04AllocWithAccessSecInfo() diff --git a/src/nvidia/src/kernel/rmapi/entry_points.h b/src/nvidia/src/kernel/rmapi/entry_points.h index 156c661f05..9cf33a5f55 100644 --- a/src/nvidia/src/kernel/rmapi/entry_points.h +++ b/src/nvidia/src/kernel/rmapi/entry_points.h @@ -35,7 +35,8 @@ rmapiAlloc NvHandle hParent, NvHandle *phObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ); NV_STATUS @@ -46,7 +47,8 @@ rmapiAllocWithHandle NvHandle hParent, NvHandle hObject, NvU32 hClass, - void *pAllocParams + void *pAllocParams, + NvU32 paramsSize ); NV_STATUS @@ -58,6 +60,7 @@ rmapiAllocWithSecInfo NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequired, API_SECURITY_INFO *pSecInfo @@ -72,6 +75,7 @@ rmapiAllocWithSecInfoTls NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequired, API_SECURITY_INFO *pSecInfo diff --git a/src/nvidia/src/kernel/rmapi/event.c b/src/nvidia/src/kernel/rmapi/event.c index c444b2796c..5ebc0854b1 100644 --- a/src/nvidia/src/kernel/rmapi/event.c +++ b/src/nvidia/src/kernel/rmapi/event.c @@ -188,7 +188,7 @@ eventConstruct_IMPL if (rmStatus == NV_OK) rmStatus = registerEventNotification(ppEventNotification, - pRsClient->hClient, + pRsClient, pEvent->hNotifierResource, pResourceRef->hResource, pNv0050AllocParams->notifyIndex, @@ -494,11 +494,11 @@ CliGetEventInfo Event **ppEvent ) { - RmClient *pClient; RsClient *pRsClient; RsResourceRef *pResourceRef; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + if (pClient == NULL) return NV_FALSE; pRsClient = staticCast(pClient, RsClient); diff --git a/src/nvidia/src/kernel/rmapi/event_buffer.c b/src/nvidia/src/kernel/rmapi/event_buffer.c index 5706501e63..ce4e09147c 100644 --- a/src/nvidia/src/kernel/rmapi/event_buffer.c +++ b/src/nvidia/src/kernel/rmapi/event_buffer.c @@ -619,9 +619,7 @@ eventbuffertBufferCtrlCmdEnableEvent_IMPL // NvTelemetry requires a valid subdevice if (updateTelemetry && pEventBuffer->hSubDevice) { - NvHandle hClient = RES_GET_CLIENT_HANDLE(pEventBuffer); - NvHandle hDevice; - OBJGPU *pGpu; + Subdevice *pSubDevice; status = rmGpuGroupLockAcquire(pEventBuffer->subDeviceInst, GPU_LOCK_GRP_SUBDEVICE, @@ -630,7 +628,12 @@ eventbuffertBufferCtrlCmdEnableEvent_IMPL if (status != NV_OK) return status; - status = CliSetSubDeviceContext(hClient, pEventBuffer->hSubDevice, &hDevice, &pGpu); + status = subdeviceGetByHandle(RES_GET_CLIENT(pEventBuffer), + pEventBuffer->hSubDevice, &pSubDevice); + if (status != NV_OK) + return status; + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); } diff --git a/src/nvidia/src/kernel/rmapi/event_notification.c b/src/nvidia/src/kernel/rmapi/event_notification.c index bb7c18dca5..53b33d62f3 100644 --- a/src/nvidia/src/kernel/rmapi/event_notification.c +++ b/src/nvidia/src/kernel/rmapi/event_notification.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -361,7 +361,7 @@ static NV_STATUS _gpuEngineEventNotificationListNotify // // Iterate through the pending notifications and call the OS to send them. // Note that osNotifyEvent may need to be preemptible, so this is done - // outside of the spinlock-protected critical section. + // outside of the spinlock-protected critical section. // PendingEventNotifyListIter it = listIterAll(pPending); while (listIterNext(&it)) @@ -559,7 +559,7 @@ eventGetEngineTypeFromSubNotifyIndex NV_STATUS registerEventNotification ( PEVENTNOTIFICATION *ppEventNotification, - NvHandle hEventClient, + RsClient *pEventClient, NvHandle hNotifier, NvHandle hEvent, NvU32 NotifyIndex, @@ -568,13 +568,13 @@ NV_STATUS registerEventNotification NvBool bUserOsEventHandle ) { + NvHandle hEventClient = pEventClient->hClient; Subdevice *pSubDevice; PEVENTNOTIFICATION pTargetEvent = NULL; NV_STATUS rmStatus = NV_OK, rmTmpStatus = NV_OK; OBJGPU *pGpu; NvBool bNonStallIntrEvent = NV_FALSE; RM_ENGINE_TYPE rmEngineId; - NvHandle hDevice; RsResourceRef *pResourceRef; Memory *pSemMemory = NULL; @@ -592,7 +592,7 @@ NV_STATUS registerEventNotification // For non-stall interrupt, the event parent type is NV20_SUBDEVICE, so we can locate // the correct OBJGPU and attach to its per-engine non-stall event list. // - if ((serverutilGetResourceRef(hEventClient, hNotifier, &pResourceRef) != NV_OK) || + if ((clientGetResourceRef(pEventClient, hNotifier, &pResourceRef) != NV_OK) || (!dynamicCast(pResourceRef->pResource, Subdevice))) { rmStatus = NV_ERR_INVALID_ARGUMENT; @@ -600,13 +600,10 @@ NV_STATUS registerEventNotification } pSubDevice = dynamicCast(pResourceRef->pResource, Subdevice); - hDevice = RES_GET_PARENT_HANDLE(pSubDevice); - if (CliSetSubDeviceContext(hEventClient, RES_GET_HANDLE(pSubDevice), &hDevice, &pGpu) != NV_OK) - { - rmStatus = NV_ERR_INVALID_ARGUMENT; - goto free_entry; - } + pGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); rmStatus = eventGetEngineTypeFromSubNotifyIndex( DRF_VAL(0005, _NOTIFY_INDEX, _INDEX, NotifyIndex), &rmEngineId); @@ -789,7 +786,6 @@ NV_STATUS unregisterEventNotificationWithData PEVENTNOTIFICATION pTargetEvent = NULL; Subdevice *pSubDevice; RsResourceRef *pResourceRef; - NvHandle hDevice; RM_ENGINE_TYPE rmEngineId; OBJGPU *pGpu; @@ -813,13 +809,11 @@ NV_STATUS unregisterEventNotificationWithData } pSubDevice = dynamicCast(pResourceRef->pResource, Subdevice); - hDevice = RES_GET_PARENT_HANDLE(pSubDevice); - if (CliSetSubDeviceContext(hEventClient, RES_GET_HANDLE(pSubDevice), &hDevice, &pGpu) != NV_OK) - { - rmStatus = NV_ERR_INVALID_ARGUMENT; - goto free_entry; - } + // Fetch pGpu and hDevice, set the threadstate to the pGpu + pGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); rmStatus = eventGetEngineTypeFromSubNotifyIndex(pTargetEvent->NotifyIndex, &rmEngineId); diff --git a/src/nvidia/src/kernel/rmapi/mapping.c b/src/nvidia/src/kernel/rmapi/mapping.c index 508a8bcdf1..720c4bf8b4 100644 --- a/src/nvidia/src/kernel/rmapi/mapping.c +++ b/src/nvidia/src/kernel/rmapi/mapping.c @@ -35,7 +35,7 @@ #include "gpu/mem_mgr/mem_desc.h" #include "gpu/mem_mgr/mem_mgr.h" -static NvU32 +static NvU64 _getMappingPageSize ( RsResourceRef *pMappableRef @@ -113,7 +113,7 @@ serverInterMap_Prologue if (pVirtualMemory != NULL) { - NvU32 pageSize = RM_PAGE_SIZE; + NvU64 pageSize = RM_PAGE_SIZE; if (pVirtualMemory->bOptimizePageTableMempoolUsage) { diff --git a/src/nvidia/src/kernel/rmapi/mapping_cpu.c b/src/nvidia/src/kernel/rmapi/mapping_cpu.c index 02bf578206..91c1587887 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_cpu.c +++ b/src/nvidia/src/kernel/rmapi/mapping_cpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,6 +48,8 @@ static void RmUnmapBusAperture (OBJGPU *, NvP64, NvU64, NvBool, NvP64); +#include "gpu/conf_compute/conf_compute.h" + typedef struct RS_CPU_MAP_PARAMS RmMapParams; typedef struct RS_CPU_UNMAP_PARAMS RmUnmapParams; @@ -176,8 +178,7 @@ memMap_IMPL KernelBus *pKernelBus = NULL; MemoryManager *pMemoryManager = NULL; KernelMemorySystem *pKernelMemorySystem = NULL; - RsClient *pRsClient; - RmClient *pRmClient; + RmClient *pClient; RsResourceRef *pContextRef; RsResourceRef *pMemoryRef; Memory *pMemoryInfo; // TODO: rename this field. pMemoryInfo is the legacy name. @@ -206,8 +207,10 @@ memMap_IMPL pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); } - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, pMapParams->hClient, &pRsClient)); - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, pMapParams->hMemory, &pMemoryRef)); + pClient = serverutilGetClientUnderLock(pMapParams->hClient); + NV_ASSERT_OR_ELSE(pClient != NULL, return NV_ERR_INVALID_CLIENT); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(staticCast(pClient, RsClient), + pMapParams->hMemory, &pMemoryRef)); pMemoryInfo = dynamicCast(pMemoryRef->pResource, Memory); NV_ASSERT_OR_RETURN(pMemoryInfo != NULL, NV_ERR_NOT_SUPPORTED); @@ -228,12 +231,32 @@ memMap_IMPL // // CPU to directly access protected memory is allowed on MODS // + // The check below is for VPR and should be skipped for Hopper CC + if ((pGpu != NULL) && !gpuIsCCFeatureEnabled(pGpu)) + { if ((pMemoryInfo->Flags & NVOS32_ALLOC_FLAGS_PROTECTED) && (pMapParams->protect != NV_PROTECT_WRITEABLE) && ! RMCFG_FEATURE_PLATFORM_MODS) { return NV_ERR_NOT_SUPPORTED; } + } + + if ((pGpu != NULL) && (pMemoryInfo->Flags & NVOS32_ALLOC_FLAGS_PROTECTED)) + { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + // + // If neither BAR1 nor PCIE as a whole is trusted, fail the mapping + // for allocations in CPR region. Mapping should still succeed for + // allocations in non-CPR region + // + if ((pCC != NULL) && !pCC->ccStaticInfo.bIsBar1Trusted && + !pCC->ccStaticInfo.bIsPcieTrusted) + { + NV_ASSERT(0); + return NV_ERR_NOT_SUPPORTED; + } + } if (!pMapParams->bKernel && FLD_TEST_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_ONLY, pMemoryInfo->Attr2) && @@ -278,6 +301,7 @@ memMap_IMPL } bIsSysmem = (effectiveAddrSpace == ADDR_SYSMEM); + bIsSysmem = bIsSysmem || (effectiveAddrSpace == ADDR_EGM); if (dynamicCast(pMemoryInfo, FlaMemory) != NULL) { @@ -436,6 +460,8 @@ memMap_IMPL NV_ASSERT(pGpu->busInfo.gpuPhysFbAddr); { + Device *pDevice = NULL; + // Below, we only map one GPU's address for CPU access, so we can use UNICAST here NvU32 busMapFbFlags = BUS_MAP_FB_FLAGS_MAP_UNICAST; if(DRF_VAL(OS33, _FLAGS, _MAPPING, pMapParams->flags) == NVOS33_FLAGS_MAPPING_DIRECT) @@ -457,15 +483,18 @@ memMap_IMPL // WAR for Bug 3564398, need to allocate doorbell for windows differently if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && - memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)) + memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)) { busMapFbFlags |= BUS_MAP_FB_FLAGS_MAP_DOWNWARDS; } + (void) deviceGetByHandle(staticCast(pClient, RsClient), + pMapParams->hDevice, &pDevice); + rmStatus = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, pMapParams->offset, &gpuVirtAddr, &gpuMapLength, - busMapFbFlags, pMapParams->hClient); + busMapFbFlags, pDevice); } if (rmStatus != NV_OK) @@ -583,13 +612,12 @@ memMap_IMPL { RS_PRIV_LEVEL privLevel; - pRmClient = dynamicCast(pRsClient, RmClient); - if (pRmClient == NULL) - return NV_ERR_OPERATING_SYSTEM; - - privLevel = rmclientGetCachedPrivilege(pRmClient); - if (!rmclientIsAdmin(pRmClient, privLevel) && !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK)) + privLevel = rmclientGetCachedPrivilege(pClient); + if (!rmclientIsAdmin(pClient, privLevel) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK)) + { return NV_ERR_PROTECTION_FAULT; + } if (DRF_VAL(OS33, _FLAGS, _MEM_SPACE, pMapParams->flags) == NVOS33_FLAGS_MEM_SPACE_USER) { @@ -815,8 +843,7 @@ serverMap_Prologue ) { NV_STATUS rmStatus; - RsClient *pRsClient; - RmClient *pRmClient; + RmClient *pClient; RsResourceRef *pMemoryRef; NvHandle hClient = pMapParams->hClient; NvHandle hParent = hClient; @@ -830,16 +857,15 @@ serverMap_Prologue return NV_ERR_INVALID_FLAGS; // Populate Resource Server information - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + pClient = serverutilGetClientUnderLock(hClient); + NV_ASSERT_OR_ELSE(pClient != NULL, return NV_ERR_INVALID_CLIENT); // Validate hClient - pRmClient = dynamicCast(pRsClient, RmClient); - if (pRmClient == NULL) - return NV_ERR_OPERATING_SYSTEM; - privLevel = rmclientGetCachedPrivilege(pRmClient); + privLevel = rmclientGetCachedPrivilege(pClient); // RS-TODO: Assert if this fails after all objects are converted - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, pMapParams->hMemory, &pMemoryRef)); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(staticCast(pClient, RsClient), + pMapParams->hMemory, &pMemoryRef)); if (pMemoryRef->pParentRef != NULL) hParent = pMemoryRef->pParentRef->hResource; @@ -859,7 +885,9 @@ serverMap_Prologue NV_ASSERT_OR_RETURN(hParent != hClient, NV_ERR_INVALID_OBJECT_PARENT); RsResourceRef *pContextRef; - rmStatus = clientGetResourceRef(pRsClient, pMapParams->hDevice, &pContextRef); + rmStatus = clientGetResourceRef(staticCast(pClient, RsClient), + pMapParams->hDevice, &pContextRef); + if (rmStatus != NV_OK) return rmStatus; @@ -917,8 +945,7 @@ serverUnmap_Prologue { OBJGPU *pGpu = NULL; NV_STATUS rmStatus; - RsClient *pRsClient; - RmClient *pRmClient; + RmClient *pClient; RsResourceRef *pMemoryRef; NvHandle hClient = pUnmapParams->hClient; NvHandle hParent = hClient; @@ -931,16 +958,15 @@ serverUnmap_Prologue void *pProcessHandle = NULL; // Populate Resource Server information - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + pClient = serverutilGetClientUnderLock(hClient); + NV_ASSERT_OR_ELSE(pClient != NULL, return NV_ERR_INVALID_CLIENT); // check if we have a user or kernel RM client - pRmClient = dynamicCast(pRsClient, RmClient); - if (pRmClient == NULL) - return NV_ERR_OPERATING_SYSTEM; - privLevel = rmclientGetCachedPrivilege(pRmClient); + privLevel = rmclientGetCachedPrivilege(pClient); // RS-TODO: Assert if this fails after all objects are converted - NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, hMemory, &pMemoryRef)); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(staticCast(pClient, RsClient), + hMemory, &pMemoryRef)); if (pMemoryRef->pParentRef != NULL) hParent = pMemoryRef->pParentRef->hResource; @@ -955,7 +981,9 @@ serverUnmap_Prologue NV_ASSERT_OR_RETURN(hParent != hClient, NV_ERR_INVALID_OBJECT_PARENT); RsResourceRef *pContextRef; - rmStatus = clientGetResourceRef(pRsClient, pUnmapParams->hDevice, &pContextRef); + rmStatus = clientGetResourceRef(staticCast(pClient, RsClient), + pUnmapParams->hDevice, &pContextRef); + if (rmStatus != NV_OK) return rmStatus; @@ -1184,8 +1212,8 @@ rmapiMapToCpuWithSecInfo API_SECURITY_INFO *pSecInfo ) { - return rmapiMapToCpuWithSecInfoV2(pRmApi, hClient, - hDevice, hMemory, offset, length, ppCpuVirtAddr, + return rmapiMapToCpuWithSecInfoV2(pRmApi, hClient, + hDevice, hMemory, offset, length, ppCpuVirtAddr, &flags, pSecInfo); } diff --git a/src/nvidia/src/kernel/rmapi/mapping_list.c b/src/nvidia/src/kernel/rmapi/mapping_list.c index 3335a14029..94c055f1b4 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_list.c +++ b/src/nvidia/src/kernel/rmapi/mapping_list.c @@ -217,7 +217,7 @@ intermapRegisterDmaMapping // if (IS_VIRTUAL_WITH_SRIOV(pGpu) && RMCFG_FEATURE_PLATFORM_MODS - && FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _4KB, pDmaMapping->Flags) + && FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _4KB, pDmaMapping->Flags) && kgmmuIsVaspaceInteropSupported(GPU_GET_KERNEL_GMMU(pGpu)) ) { @@ -225,7 +225,7 @@ intermapRegisterDmaMapping } else { - alignment = memdescGetPageSize64(memdescGetMemDescFromGpu(pDmaMapping->pMemDesc, pGpu), + alignment = memdescGetPageSize(memdescGetMemDescFromGpu(pDmaMapping->pMemDesc, pGpu), pDmaMapping->addressTranslation); } } @@ -388,7 +388,7 @@ intermapGetDmaMapping NvBool CliGetDmaMappingInfo ( - NvHandle hClient, + RsClient *pClient, NvHandle hDevice, NvHandle hMemCtx, NvU64 dmaOffset, @@ -397,15 +397,10 @@ CliGetDmaMappingInfo ) { VirtualMemory *pVirtualMemory; - RsClient *pClient; Device *pDevice; NODE *pNode; NV_STATUS status; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return NV_FALSE; - // Try a non-zero handle as a NVxx_MEMORY_VIRTUAL object if (hMemCtx != NV01_NULL_OBJECT) { @@ -437,7 +432,7 @@ CliGetDmaMappingInfo btreeEnumNext(&pNode, pDevice->DevMemoryTable); if ((pVirtualMemory != NULL) && - virtmemMatchesVASpace(pVirtualMemory, hClient, hMemCtx)) + virtmemMatchesVASpace(pVirtualMemory, pClient->hClient, hMemCtx)) { *ppDmaMappingInfo = intermapGetDmaMapping(pVirtualMemory, dmaOffset, gpuMask); diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c index d0c979dd25..c5394fa19a 100644 --- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c +++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,9 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +// FIXME XXX +#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED + #include "core/prelude.h" +// FIXME XXX +#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED + #include #include #include // NV01_MEMORY_SYSTEM @@ -33,6 +39,7 @@ #include // NV50_MEMORY_VIRTUAL #include #include +#include // KEPLER_CHANNEL_GROUP_A #include #include #include @@ -65,9 +72,12 @@ #include #include #include +#include // NV_CONFIDENTIAL_COMPUTE #include // HOPPER_USERMODE_A #include // HOPPER_DMA_COPY_A #include // HOPPER_COMPUTE_A +#include // HOPPER_SEC2_WORK_LAUNCH_A +#include #include #include @@ -84,6 +94,7 @@ #include #include #include +#include #include #include @@ -98,7 +109,6 @@ #include #include #include -#include #include #include #include @@ -123,8 +133,11 @@ #include #include +#include #include +#include + #define NV_GPU_OPS_NUM_GPFIFO_ENTRIES_DEFAULT 1024 #define NV_GPU_SMALL_PAGESIZE (4 * 1024) @@ -221,6 +234,9 @@ struct gpuDevice NvU32 deviceInstance; NvU32 subdeviceInstance; NvU32 gpuId; + + // TODO: Bug 3906861: The info struct contains many of these fields. Find + // and remove the redundant fields from this top level. NvU32 hostClass; NvU32 ceClass; NvU32 sec2Class; @@ -232,9 +248,7 @@ struct gpuDevice struct gpuSession *session; NvU8 gpuUUID[NV_GPU_UUID_LEN]; gpuFbInfo fbInfo; - UVM_LINK_TYPE sysmemLink; - NvU32 sysmemLinkRateMBps; - NvBool connectedToSwitch; + gpuInfo info; MemdescMap kern2PhysDescrMap; @@ -263,25 +277,34 @@ struct gpuAddressSpace } dummyGpuAlloc; }; +struct gpuTsg +{ + NvHandle tsgHandle; + struct gpuAddressSpace *vaSpace; + UVM_GPU_CHANNEL_ENGINE_TYPE engineType; + + // Index of the engine the TSG is bound to. + // Ignored if engineType is anything other than + // UVM_GPU_CHANNEL_ENGINE_TYPE_CE. + NvU32 engineIndex; + + // True when the GPU does not support TSG for the engineType. + NvBool isFakeTsg; +}; + struct gpuChannel { + const struct gpuTsg *tsg; NvHandle channelHandle; + NvHandle engineHandle; NvU32 hwRunlistId; NvU32 hwChannelId; - UVM_GPU_CHANNEL_ENGINE_TYPE engineType; - - // If engineType is CE, engineIndex is a zero-based offset from - // RM_ENGINE_TYPE_COPY0. If engineType is GR, engineIndex is a - // zero-based offset from NV2080_ENGINE_TYPE_GR0. - NvU32 engineIndex; - struct gpuAddressSpace *vaSpace; NvU64 gpFifo; NvNotification *errorNotifier; NvU64 errorNotifierOffset; NvU64 *gpFifoEntries; NvU32 fifoEntries; KeplerAControlGPFifo *controlPage; - struct gpuObject *nextAttachedEngine; NvHandle hFaultCancelSwMethodClass; volatile unsigned *workSubmissionOffset; NvU32 workSubmissionToken; @@ -291,6 +314,8 @@ struct gpuChannel UVM_BUFFER_LOCATION gpFifoLoc; UVM_BUFFER_LOCATION gpPutLoc; NvBool retainedDummyAlloc; + NvBool bClientRegionGpuMappingNeeded; + NvU64 clientRegionGpuAddr; }; // Add 3 to include local ctx buffer, patch context buffer and PM ctxsw buffer @@ -323,13 +348,6 @@ struct gpuRetainedChannel_struct NvHandle hChannelRetainer; }; -struct gpuObject -{ - NvHandle handle; - NvU32 type; - struct gpuObject *next; -}; - struct allocFlags { NvBool bGetKernelVA; @@ -398,8 +416,9 @@ static void gpuDeviceUnmapCpuFreeHandle(struct gpuDevice *device, NvHandle handle, void *ptr, NvU32 flags); -static NV_STATUS allocNvlinkStatusForSubdevice(struct gpuDevice *device, - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut); +static NV_STATUS allocNvlinkStatus(NvHandle hClient, + NvHandle hSubDevice, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut); static NvU32 getNvlinkConnectionToNpu(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus, NvBool *atomicSupported, NvU32 *linkBandwidthMBps); @@ -414,6 +433,10 @@ static NV_STATUS _nvGpuOpsRetainChannelResources(struct gpuDevice *device, gpuChannelInstanceInfo *channelInstanceInfo); static void _nvGpuOpsReleaseChannelResources(gpuRetainedChannel *retainedChannel); +static NV_STATUS +nvGpuOpsQueryGpuConfidentialComputeCaps(NvHandle hClient, + UvmGpuConfComputeCaps *pGpuConfComputeCaps); + /* * This function will lock the RM API lock according to rmApiLockFlags, and then * examine numLocksNeeded. If this is 0, no GPU locks will be acquired. If it @@ -600,7 +623,7 @@ static NV_STATUS nvGpuOpsCreateClient(RM_API *pRmApi, NvHandle *hClient) *hClient = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, - hClient, NV01_ROOT, hClient); + hClient, NV01_ROOT, hClient, sizeof(*hClient)); if (status != NV_OK) { return status; @@ -690,7 +713,7 @@ static NvBool deviceNeedsDummyAlloc(struct gpuDevice *device) // any CPU BAR1 PCIE writes prior to updating GPPUT. This is only needed // when the bus is non-coherent and when not in ZeroFB (where there can't be // any BAR1 mappings). - return device->sysmemLink < UVM_LINK_TYPE_NVLINK_2 && !device->fbInfo.bZeroFb; + return device->info.sysmemLink < UVM_LINK_TYPE_NVLINK_2 && !device->fbInfo.bZeroFb; } static NV_STATUS nvGpuOpsVaSpaceRetainDummyAlloc(struct gpuAddressSpace *vaSpace) @@ -707,6 +730,12 @@ static NV_STATUS nvGpuOpsVaSpaceRetainDummyAlloc(struct gpuAddressSpace *vaSpace if (vaSpace->dummyGpuAlloc.refCount > 0) goto done; + // When HCC is enabled the allocation happens in CPR vidmem + // The dummy BAR1 pointer read mechanism won't work when + // BAR1 access to CPR vidmem is sealed off as part of HCC + // production settings. Creating dummy BAR1 mapping can + // also be avoided when doorbell is in BAR1. + flags.bGetKernelVA = NV_FALSE; status = nvGpuOpsGpuMalloc(vaSpace, NV_FALSE, @@ -908,7 +937,8 @@ static NV_STATUS nvGpuOpsRmDeviceCreate(struct gpuDevice *device) session->handle, &device->handle, NV01_DEVICE_0, - &nv0080AllocParams); + &nv0080AllocParams, + sizeof(nv0080AllocParams)); if (status != NV_OK) goto cleanup_device_desc; @@ -1111,7 +1141,8 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) device->subhandle, &rmSubDevice->eccMasterHandle, GF100_SUBDEVICE_MASTER, - &tempPtr); + &tempPtr, + sizeof(tempPtr)); if (status != NV_OK) goto done; @@ -1173,7 +1204,8 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) device->subhandle, &rmSubDevice->eccCallbackHandle, NV01_EVENT_KERNEL_CALLBACK_EX, - &pParams->allocDbe); + &pParams->allocDbe, + sizeof(pParams->allocDbe)); if (status != NV_OK) goto done; @@ -1431,7 +1463,8 @@ static NV_STATUS nvGpuOpsRmSubDeviceCreate(struct gpuDevice *device) device->handle, &device->subhandle, NV20_SUBDEVICE_0, - &nv2080AllocParams); + &nv2080AllocParams, + sizeof(nv2080AllocParams)); if (status != NV_OK) goto cleanup_subdevice_desc; rmSubDevice->subDeviceHandle = device->subhandle; @@ -1479,6 +1512,13 @@ static NvBool isDeviceAmperePlus(const struct gpuDevice *device) return device->rmDevice->arch >= GPU_ARCHITECTURE_AMPERE; } +// Assume ...->Ampere->Ada->Hopper->... +static NvBool isDeviceHopperPlus(const struct gpuDevice *device) +{ + NV_ASSERT(device->rmDevice); + return (device->rmDevice->arch >= GPU_ARCHITECTURE_HOPPER) && (device->rmDevice->arch != GPU_ARCHITECTURE_ADA); +} + static UVM_LINK_TYPE rmControlToUvmNvlinkVersion(NvU32 nvlinkVersion) { if (nvlinkVersion == NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID) @@ -1564,9 +1604,9 @@ static NV_STATUS queryFbInfo(struct gpuDevice *device) return nvStatus; } -// Return the PCIE link cap max speed associated with the given GPU in -// megabytes per seconds.. -static NV_STATUS getPCIELinkRateMBps(struct gpuDevice *device, NvU32 *pcieLinkRate) +// Return the PCIE link cap max speed associated with the given subdevice in +// megabytes per second. +static NV_STATUS getPCIELinkRateMBps(NvHandle hClient, NvHandle hSubDevice, NvU32 *pcieLinkRate) { // PCI Express Base Specification: https://www.pcisig.com/specifications/pciexpress const NvU32 PCIE_1_ENCODING_RATIO_TOTAL = 10; @@ -1593,8 +1633,8 @@ static NV_STATUS getPCIELinkRateMBps(struct gpuDevice *device, NvU32 *pcieLinkRa busInfoParams.busInfoList = NV_PTR_TO_NvP64(&busInfo); NV_STATUS status = pRmApi->Control(pRmApi, - device->session->handle, - device->subhandle, + hClient, + hSubDevice, NV2080_CTRL_CMD_BUS_GET_INFO, &busInfoParams, sizeof(busInfoParams)); @@ -1653,13 +1693,6 @@ NV_STATUS nvGpuOpsDeviceCreate(struct gpuSession *session, NV_STATUS status; struct gpuDevice *device = NULL; NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS gpuIdInfoParams = {{0}}; - NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *busInfoParams; - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus; - NvU32 nvlinkVersion; - NvU32 sysmemLink; - NvU32 linkBandwidthMBps; - NvU32 sysmemConnType; - NvBool atomicSupported; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); OBJGPU *pGpu; @@ -1684,6 +1717,8 @@ NV_STATUS nvGpuOpsDeviceCreate(struct gpuSession *session, device->subdeviceInstance = gpuIdInfoParams.subdeviceInstance; device->gpuId = gpuIdInfoParams.gpuId; + portMemCopy(&device->info, sizeof(device->info), pGpuInfo, sizeof(*pGpuInfo)); + status = nvGpuOpsRmDeviceCreate(device); if (status != NV_OK) goto cleanup_device_obj; @@ -1734,91 +1769,6 @@ NV_STATUS nvGpuOpsDeviceCreate(struct gpuSession *session, if (status != NV_OK) goto cleanup_ecc; - busInfoParams = portMemAllocNonPaged(sizeof(*busInfoParams)); - if (busInfoParams == NULL) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto cleanup_ecc; - } - portMemSet(busInfoParams, 0, sizeof(*busInfoParams)); - busInfoParams->busInfoListSize = 1; - busInfoParams->busInfoList[0].index = NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE; - status = pRmApi->Control(pRmApi, - device->session->handle, - device->subhandle, - NV2080_CTRL_CMD_BUS_GET_INFO_V2, - busInfoParams, - sizeof(*busInfoParams)); - if (status != NV_OK) - { - portMemFree(busInfoParams); - goto cleanup_ecc; - } - - sysmemConnType = busInfoParams->busInfoList[0].data; - portMemFree(busInfoParams); - - sysmemLink = UVM_LINK_TYPE_NONE; - switch (sysmemConnType) - { - case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK: - { - status = allocNvlinkStatusForSubdevice(device, &nvlinkStatus); - if (status != NV_OK) - goto cleanup_ecc; - - nvlinkVersion = getNvlinkConnectionToNpu(nvlinkStatus, - &atomicSupported, - &linkBandwidthMBps); - - sysmemLink = rmControlToUvmNvlinkVersion(nvlinkVersion); - - portMemFree(nvlinkStatus); - nvlinkStatus = NULL; - break; - } - case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE: - { - sysmemLink = UVM_LINK_TYPE_PCIE; - status = getPCIELinkRateMBps(device, &linkBandwidthMBps); - if (status != NV_OK) - goto cleanup_ecc; - break; - } - default: - { - NV_PRINTF(LEVEL_ERROR, "Unsupported sysmem connection type: %d\n", - sysmemConnType); - NV_ASSERT(0); - break; - } - } - - NV_PRINTF(LEVEL_INFO, "sysmem link type: %d bw: %u\n", sysmemLink, linkBandwidthMBps); - - NV_ASSERT(sysmemLink != UVM_LINK_TYPE_NONE); - device->sysmemLink = sysmemLink; - device->sysmemLinkRateMBps = linkBandwidthMBps; - - status = allocNvlinkStatusForSubdevice(device, &nvlinkStatus); - if (status != NV_OK) - goto cleanup_ecc; - nvlinkVersion = getNvlinkConnectionToSwitch(nvlinkStatus, - &linkBandwidthMBps); - - if (rmControlToUvmNvlinkVersion(nvlinkVersion) != UVM_LINK_TYPE_NONE) - { - NV_ASSERT(rmControlToUvmNvlinkVersion(nvlinkVersion) != UVM_LINK_TYPE_NVLINK_1); - - // If the GPU is ever connected to the CPU via a switch, sysmemLink - // and sysmemLinkRateMBps need to be updated accordingly. - NV_ASSERT(sysmemConnType != NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK); - - device->connectedToSwitch = NV_TRUE; - } - - portMemFree(nvlinkStatus); - mapInit(&device->kern2PhysDescrMap, portMemAllocatorGetGlobalNonPaged()); status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); @@ -2072,7 +2022,8 @@ NV_STATUS nvGpuOpsAddressSpaceCreate(struct gpuDevice *device, device->session->handle, device->handle, &gpuVaSpace->handle, FERMI_VASPACE_A, - &vaParams); + &vaParams, + sizeof(vaParams)); if (status != NV_OK) { goto cleanup_struct; @@ -2222,8 +2173,9 @@ NV_STATUS nvGpuOpsDupAddressSpace(struct gpuDevice *device, // Get the NVLink connection status for the given device. On success, caller is // responsible of freeing the memory. -static NV_STATUS allocNvlinkStatusForSubdevice(struct gpuDevice *device, - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut) +static NV_STATUS allocNvlinkStatus(NvHandle hClient, + NvHandle hSubDevice, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS **nvlinkStatusOut) { NV_STATUS status; NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus; @@ -2237,8 +2189,8 @@ static NV_STATUS allocNvlinkStatusForSubdevice(struct gpuDevice *device, portMemSet(nvlinkStatus, 0, sizeof(*nvlinkStatus)); status = pRmApi->Control(pRmApi, - device->session->handle, - device->subhandle, + hClient, + hSubDevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS, nvlinkStatus, sizeof(*nvlinkStatus)); @@ -2321,6 +2273,34 @@ static NvU32 getNvlinkConnectionToGpu(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ST return version; } +static NV_STATUS getC2CConnectionToCpu(NvHandle hClient, + NvHandle hSubDevice, + NvBool *connectedToCpu, + NvU32 *linkBandwidthMBps) +{ + NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS params = {0}; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + + *connectedToCpu = NV_FALSE; + *linkBandwidthMBps = 0; + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + hClient, + hSubDevice, + NV2080_CTRL_CMD_BUS_GET_C2C_INFO, + ¶ms, + sizeof(params))); + + if (params.bIsLinkUp == NV_TRUE && + (params.remoteType == NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU)) + { + *connectedToCpu = NV_TRUE; + *linkBandwidthMBps = params.nrLinks * params.perLinkBwMBps; + } + + return NV_OK; +} + // If the given NvLink connection has a NPU device as an endpoint, return the // version of the NvLink connection with that NPU , and the maximum // unidirectional bandwidth in megabytes per second. Otherwise, return @@ -2414,8 +2394,7 @@ static NvU32 getNvlinkConnectionToSwitch(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK // communicate through P9 NPUs static NV_STATUS gpusHaveNpuNvlink(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus1, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus2, - NvU32 *nvlinkVersion, - NvU32 *linkBandwidthMBps) + NvU32 *nvlinkVersion) { NvU32 nvlinkVersion1, nvlinkVersion2; NvU32 tmpLinkBandwidthMBps; @@ -2454,11 +2433,6 @@ static NV_STATUS gpusHaveNpuNvlink(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARA // access B. *nvlinkVersion = NV_MIN(nvlinkVersion1, nvlinkVersion2); - // Link bandwidth not provided because the intermediate link rate could - // vary a lot with system topologies & current load, making this bandwidth - // obsolete. - *linkBandwidthMBps = 0; - return NV_OK; } @@ -2566,7 +2540,7 @@ static NV_STATUS getNvlinkP2PCaps(struct gpuDevice *device1, *nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID; - if (device1->connectedToSwitch && device2->connectedToSwitch) + if (device1->info.connectedToSwitch && device2->info.connectedToSwitch) { nvlinkVersion1 = getNvlinkConnectionToSwitch(nvlinkStatus1, &linkBandwidthMBps1); @@ -2636,11 +2610,15 @@ NV_STATUS nvGpuOpsGetP2PCaps(struct gpuDevice *device1, if (!p2pCapsParams) return NV_ERR_INVALID_ARGUMENT; - status = allocNvlinkStatusForSubdevice(device1, &nvlinkStatus1); + status = allocNvlinkStatus(device1->session->handle, + device1->subhandle, + &nvlinkStatus1); if (status != NV_OK) goto cleanup; - status = allocNvlinkStatusForSubdevice(device2, &nvlinkStatus2); + status = allocNvlinkStatus(device2->session->handle, + device2->subhandle, + &nvlinkStatus2); if (status != NV_OK) goto cleanup; @@ -2657,26 +2635,27 @@ NV_STATUS nvGpuOpsGetP2PCaps(struct gpuDevice *device1, if (p2pCaps.indirectAccessSupported) { NvU32 nvlinkVersion; - NvU32 linkBandwidthMBps; NvU32 p2pLink; status = gpusHaveNpuNvlink(nvlinkStatus1, nvlinkStatus2, - &nvlinkVersion, - &linkBandwidthMBps); + &nvlinkVersion); if (status != NV_OK) goto cleanup; p2pLink = rmControlToUvmNvlinkVersion(nvlinkVersion); NV_ASSERT(p2pLink >= UVM_LINK_TYPE_NVLINK_2); - NV_ASSERT(linkBandwidthMBps == 0); p2pCapsParams->indirectAccess = NV_TRUE; p2pCapsParams->p2pLink = p2pLink; p2pCapsParams->optimalNvlinkWriteCEs[0] = p2pCaps.optimalNvlinkWriteCEs[0]; p2pCapsParams->optimalNvlinkWriteCEs[1] = p2pCaps.optimalNvlinkWriteCEs[1]; - p2pCapsParams->totalLinkLineRateMBps = linkBandwidthMBps; + + // Link bandwidth not provided because the intermediate link rate could + // vary a lot with system topologies & current load, making this bandwidth + // obsolete. + p2pCapsParams->totalLinkLineRateMBps = 0; } else if (p2pCaps.accessSupported) { @@ -2712,11 +2691,15 @@ NV_STATUS nvGpuOpsGetP2PCaps(struct gpuDevice *device1, { NvU32 linkBandwidthMBps1, linkBandwidthMBps2; - status = getPCIELinkRateMBps(device1, &linkBandwidthMBps1); + status = getPCIELinkRateMBps(device1->session->handle, + device1->subhandle, + &linkBandwidthMBps1); if (status != NV_OK) goto cleanup; - status = getPCIELinkRateMBps(device2, &linkBandwidthMBps2); + status = getPCIELinkRateMBps(device2->session->handle, + device2->subhandle, + &linkBandwidthMBps2); if (status != NV_OK) goto cleanup; @@ -3687,6 +3670,17 @@ static NV_STATUS nvGpuOpsAllocPhysical(struct gpuDevice *device, if (!isSystemMemory && allocInfo->bPersistentVidmem) memAllocParams.flags |= NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM; + // + // Indicate to the RM that the allocation should be in unprotected memory. + // If the Confidential Computing feature is not enabled on the system, this + // flag has no effect. + // + if (allocInfo->bUnprotected) + { + memAllocParams.attr2 = FLD_SET_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, + _UNPROTECTED, memAllocParams.attr2); + } + // // vid heap ctrl has a different policy as compared to other internal APIS // it expects the gpu lock to not be held. This means we have to drop the gpu lock @@ -3700,7 +3694,8 @@ static NV_STATUS nvGpuOpsAllocPhysical(struct gpuDevice *device, isSystemMemory ? device->handle : device->subhandle, &physHandle, isSystemMemory ? NV01_MEMORY_SYSTEM : NV01_MEMORY_LOCAL_USER, - &memAllocParams), done); + &memAllocParams, + sizeof(memAllocParams)), done); if (allocInfo->bContiguousPhysAlloc) allocInfo->gpuPhysOffset = memAllocParams.offset; @@ -3778,7 +3773,8 @@ static NV_STATUS nvGpuOpsAllocVirtual(struct gpuAddressSpace *vaSpace, vaSpace->device->handle, &memDesc->handle, NV50_MEMORY_VIRTUAL, - &memAllocParams), done); + &memAllocParams, + sizeof(memAllocParams)), done); memDesc->address = (NvU64)memAllocParams.offset; memDesc->size = length; memDesc->childHandle = physHandle; @@ -3929,6 +3925,38 @@ static NV_STATUS nvGpuOpsGpuMalloc(struct gpuAddressSpace *vaSpace, return status; } +// This function is generic and can be used outside CC as well. +// As of today the only caller of this function is under CC checks +// Hence this is also protected under the same checks. Otherwise, +// builds will fail. +static void nvGpuOpsUnmapGpuMemory(struct gpuAddressSpace *vaSpace, + NvU64 gpuOffset) +{ + gpuMemDesc *memDescVa = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + + NV_ASSERT(vaSpace != NULL); + + portSyncRwLockAcquireRead(vaSpace->allocationsLock); + NV_ASSERT_OK(findDescriptor(vaSpace->allocations, gpuOffset, (void**)&memDescVa)); + portSyncRwLockReleaseRead(vaSpace->allocationsLock); + + NV_ASSERT(memDescVa != NULL); + NV_ASSERT(memDescVa->handle != 0); + NV_ASSERT(memDescVa->childHandle != 0); + NV_ASSERT(memDescVa->address == gpuOffset); + + NV_ASSERT_OK(pRmApi->Unmap(pRmApi, + vaSpace->device->session->handle, + vaSpace->device->handle, + memDescVa->handle, + memDescVa->childHandle, + NV04_MAP_MEMORY_FLAGS_NONE, + gpuOffset)); + + return; +} + static void nvGpuOpsFreeVirtual(struct gpuAddressSpace *vaSpace, NvU64 vaOffset) { RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); @@ -4213,8 +4241,8 @@ static NV_STATUS nvGpuOpsChannelGetHwChannelId(struct gpuChannel *channel, params.pChannelList = NV_PTR_TO_NvP64(hwChannelId); return pRmApi->Control(pRmApi, - channel->vaSpace->device->session->handle, - channel->vaSpace->device->handle, + channel->tsg->vaSpace->device->session->handle, + channel->tsg->vaSpace->device->handle, NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST, ¶ms, sizeof(params)); @@ -4262,16 +4290,18 @@ static NV_STATUS gpuDeviceMapUsermodeRegion(struct gpuDevice *device) subDeviceDesc *rmSubDevice = device->rmSubDevice; NvU32 usermodeClass = VOLTA_USERMODE_A; void *pParams = NULL; + NvU32 paramsSize = 0; NV_HOPPER_USERMODE_A_PARAMS hopperParams = { .bBar1Mapping = NV_TRUE, .bPriv = NV_FALSE }; - if (device->rmDevice->arch >= GPU_ARCHITECTURE_HOPPER) + if (isDeviceHopperPlus(device)) { usermodeClass = HOPPER_USERMODE_A; pParams = &hopperParams; + paramsSize = sizeof(hopperParams); } NV_ASSERT(isDeviceVoltaPlus(device)); @@ -4283,7 +4313,9 @@ static NV_STATUS gpuDeviceMapUsermodeRegion(struct gpuDevice *device) device->subhandle, ®ionHandle, usermodeClass, - pParams); + pParams, + paramsSize); + if (NV_OK != status) return status; @@ -4350,17 +4382,68 @@ static NV_STATUS nvGpuOpsGetWorkSubmissionInfo(struct gpuAddressSpace *vaSpace, (NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN * sizeof(NvNotification)) + NV_OFFSETOF(NvNotification, info32)); + { + OBJGPU *pGpu; + RsClient *pClient; + Device *pDevice; + + status = serverGetClientUnderLock(&g_resServ, session->handle, &pClient); + if (status != NV_OK) + return status; + + status = deviceGetByHandle(pClient, device->handle, &pDevice); + if (status != NV_OK) + return status; + + pGpu = GPU_RES_GET_GPU(pDevice); + + // Map the usermode region in channel's vaspace + if (gpuIsCCFeatureEnabled(pGpu)) + { + NvU64 vaOffset = 0; + NvU64 gpuOffset = 0; + gpuVaAllocInfo vaAllocInfo = {0}; + struct allocFlags flags = {0}; + + NV_ASSERT(isDeviceHopperPlus(device)); + + status = nvGpuOpsAllocVirtual(vaSpace, NVC361_NV_USERMODE__SIZE, &vaOffset, + rmSubDevice->clientRegionHandle, + flags, &vaAllocInfo); + if (status != NV_OK) + return status; + + status = nvGpuOpsMapGpuMemory(vaSpace, vaOffset, NVC361_NV_USERMODE__SIZE, + vaAllocInfo.pageSize, &gpuOffset, flags); + if (status != NV_OK) + { + nvGpuOpsFreeVirtual(vaSpace, vaOffset); + return status; + } + + channel->bClientRegionGpuMappingNeeded = NV_TRUE; + channel->clientRegionGpuAddr = gpuOffset; + } + } + return status; } static NvBool channelNeedsDummyAlloc(struct gpuChannel *channel) { - return channel->gpPutLoc == UVM_BUFFER_LOCATION_SYS && deviceNeedsDummyAlloc(channel->vaSpace->device); + if (deviceNeedsDummyAlloc(channel->tsg->vaSpace->device)) + { + return isDeviceHopperPlus(channel->tsg->vaSpace->device) ? + channel->gpPutLoc == UVM_BUFFER_LOCATION_VID : + channel->gpPutLoc == UVM_BUFFER_LOCATION_SYS; + } + + return NV_FALSE; } static NV_STATUS channelRetainDummyAlloc(struct gpuChannel *channel, gpuChannelInfo *channelInfo) { - struct gpuAddressSpace *vaSpace = channel->vaSpace; + struct gpuAddressSpace *vaSpace = channel->tsg->vaSpace; NV_STATUS status; if (!channelNeedsDummyAlloc(channel)) @@ -4381,32 +4464,34 @@ static void channelReleaseDummyAlloc(struct gpuChannel *channel) if (channel != NULL && channel->retainedDummyAlloc) { NV_ASSERT(channelNeedsDummyAlloc(channel)); - nvGpuOpsVaSpaceReleaseDummyAlloc(channel->vaSpace); + nvGpuOpsVaSpaceReleaseDummyAlloc(channel->tsg->vaSpace); } } -static RM_ENGINE_TYPE channelEngineType(const struct gpuChannel *channel) +static RM_ENGINE_TYPE tsgEngineType(const struct gpuTsg *tsg) { - if (channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE) - return RM_ENGINE_TYPE_COPY(channel->engineIndex); - else if (channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) + NV_ASSERT(tsg->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || tsg->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2); + + if (tsg->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) return RM_ENGINE_TYPE_SEC2; else - return RM_ENGINE_TYPE_GR(channel->engineIndex); + return RM_ENGINE_TYPE_COPY(tsg->engineIndex); } -static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, - UVM_GPU_CHANNEL_ENGINE_TYPE engineType, +static NV_STATUS channelAllocate(const gpuTsgHandle tsg, const gpuChannelAllocParams *params, struct gpuChannel **channelHandle, gpuChannelInfo *channelInfo) { NV_STATUS status; + nvGpuOpsLockSet acquiredLocks; + struct gpuAddressSpace *vaSpace = NULL; struct gpuChannel *channel = NULL; struct gpuDevice *device = NULL; struct gpuSession *session = NULL; void *cpuMap = NULL; NvHandle hErrorNotifier; + NvHandle hTsg; struct ChannelAllocInfo *pAllocInfo = NULL; void *gpfifoCtrl = NULL; PCLI_DMA_MAPPING_INFO pDmaMappingInfo = NULL; @@ -4419,20 +4504,12 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, UVM_BUFFER_LOCATION gpPutLoc; NvLength gpFifoSize, errorNotifierSize; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); - - if (!vaSpace || !channelHandle || !params || !channelInfo) - return NV_ERR_INVALID_ARGUMENT; + RsClient *pClient; if (params->numGpFifoEntries == 0) return NV_ERR_INVALID_ARGUMENT; - if (engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_CE && - engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_GR && - engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) - return NV_ERR_INVALID_ARGUMENT; - - // TODO: Bug 2458492: Ampere-SMC Verify GR/CE indices within partition/SMC Engine - + vaSpace = tsg->vaSpace; device = vaSpace->device; NV_ASSERT(device); session = device->session; @@ -4491,21 +4568,32 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, portMemSet(channel, 0, sizeof(*channel)); - channel->vaSpace = vaSpace; + channel->tsg = tsg; channel->fifoEntries = params->numGpFifoEntries; channel->gpFifoLoc = gpFifoLoc; channel->gpPutLoc = gpPutLoc; - // Remember which engine we are using, so that RC recovery can reset it if - // it hangs: - channel->engineType = engineType; - channel->engineIndex = params->engineIndex; - gpFifoSize = (NvLength)params->numGpFifoEntries * NVA06F_GP_ENTRY__SIZE; // If the allocation is vidmem ask RM to allocate persistent vidmem pAllocInfo->gpuAllocInfo.bPersistentVidmem = NV_TRUE; + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + // Gpfifo can be placed in one of the following locations + // 1. Unprotected sysmem in case of both APM and HCC + // 2. Unprotected vidmem in case of APM + // 3. Protected vidmem in case of HCC + if ((gpFifoLoc == UVM_BUFFER_LOCATION_SYS) || gpuIsApmFeatureEnabled(pGpu)) + { + pAllocInfo->gpuAllocInfo.bUnprotected = NV_TRUE; + } + else + { + pAllocInfo->gpuAllocInfo.bUnprotected = NV_FALSE; + } + } + // 1. Allocate the GPFIFO entries. Dont pass any special flags. flags.bGetKernelVA = NV_FALSE; status = nvGpuOpsGpuMalloc(vaSpace, @@ -4533,6 +4621,11 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, // sufficiently large to also accommodate any other channel // notifiers, and request a kernel VA and CPU caching. // + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + // Put notifier in unprotected sysmem + pAllocInfo->gpuAllocInfo.bUnprotected = NV_TRUE; + } flags.bGetKernelVA = NV_TRUE; errorNotifierSize = sizeof(NvNotification) * @@ -4558,23 +4651,24 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, // 4. Find and share the VA with UVM driver // TODO: Acquired because CliGetDmaMappingInfo expects RMAPI lock. Necessary? - status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); + status = _nvGpuOpsLocksAcquire(RMAPI_LOCK_FLAGS_READ, session->handle, &pClient, 0, + 0, 0, &acquiredLocks); if (status != NV_OK) goto cleanup_free_virtual; - if (!CliGetDmaMappingInfo(session->handle, + if (!CliGetDmaMappingInfo(pClient, device->handle, hErrorNotifier, channel->errorNotifierOffset, gpumgrGetDeviceGpuMask(device->deviceInstance), &pDmaMappingInfo)) { - rmapiLockRelease(); + _nvGpuOpsLocksRelease(&acquiredLocks); status = NV_ERR_GENERIC; goto cleanup_free_virtual; } - rmapiLockRelease(); + _nvGpuOpsLocksRelease(&acquiredLocks); // // RM uses the parent subdevice index to fill the notifier on SYSMEM. So use the same. @@ -4598,12 +4692,27 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, pAllocInfo->gpFifoAllocParams.gpFifoOffset = channel->gpFifo; pAllocInfo->gpFifoAllocParams.gpFifoEntries = channel->fifoEntries; - // If zero then it will attach to the device address space - pAllocInfo->gpFifoAllocParams.hVASpace = vaSpace->handle; - pAllocInfo->gpFifoAllocParams.engineType = gpuGetNv2080EngineType(channelEngineType(channel)); + + if (params->secure) + pAllocInfo->gpFifoAllocParams.flags = FLD_SET_DRF(OS04, _FLAGS, _CC_SECURE, _TRUE, pAllocInfo->gpFifoAllocParams.flags); if (isDeviceVoltaPlus(device)) { + if (gpuIsCCorApmFeatureEnabled(pGpu)) + { + // USERD can be placed in one of the following locations + // 1. Unprotected sysmem in case of both APM and HCC + // 2. Unprotected vidmem in case of APM + // 3. Protected vidmem in case of HCC + if ((gpPutLoc == UVM_BUFFER_LOCATION_SYS) || gpuIsApmFeatureEnabled(pGpu)) + { + pAllocInfo->gpuAllocInfo.bUnprotected = NV_TRUE; + } + else + { + pAllocInfo->gpuAllocInfo.bUnprotected = NV_FALSE; + } + } flags.bGetKernelVA = NV_FALSE; status = nvGpuOpsGpuMalloc(vaSpace, @@ -4631,12 +4740,32 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, goto cleanup_free_virtual; } + pAllocInfo->gpFifoAllocParams.engineType = gpuGetNv2080EngineType(tsgEngineType(channel->tsg)); + + if (channel->tsg->isFakeTsg) + { + // The internal RM TSG requires a valid vaSpace object. + pAllocInfo->gpFifoAllocParams.hVASpace = vaSpace->handle; + + // Not a Tsg, device handle parents a channel when RM internal TSG is + // used. + hTsg = device->handle; + } + else + { + // If zero then it will attach to the TSG address space. + pAllocInfo->gpFifoAllocParams.hVASpace = NV01_NULL_OBJECT; + hTsg = channel->tsg->tsgHandle; + } + channel->channelHandle = NV01_NULL_OBJECT; - status = pRmApi->Alloc(pRmApi, session->handle, - device->handle, + status = pRmApi->Alloc(pRmApi, + session->handle, + hTsg, &channel->channelHandle, device->hostClass, - &pAllocInfo->gpFifoAllocParams); + &pAllocInfo->gpFifoAllocParams, + sizeof(pAllocInfo->gpFifoAllocParams)); if (status != NV_OK) { goto cleanup_free_virtual; @@ -4647,7 +4776,7 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, - (NvU32)channelEngineType(channel), + (NvU32)tsgEngineType(channel->tsg), ENGINE_INFO_TYPE_RUNLIST, &channel->hwRunlistId); if (status != NV_OK) @@ -4680,7 +4809,7 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, goto cleanup_free_controlpage; // Allocate the SW method class for fault cancel - if (isDevicePascalPlus(device) && (engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2)) + if (isDevicePascalPlus(device) && (channel->tsg->engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2)) { channel->hFaultCancelSwMethodClass = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, @@ -4688,7 +4817,8 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, channel->channelHandle, &channel->hFaultCancelSwMethodClass, GP100_UVM_SW, - NULL); + NULL, + 0); if (status != NV_OK) goto cleanup_free_controlpage; } @@ -4705,6 +4835,15 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, channelInfo->hwRunlistId = channel->hwRunlistId; channelInfo->hwChannelId = channel->hwChannelId; + channelInfo->gpFifoGpuVa = channel->gpFifo; + channelInfo->gpPutGpuVa = channel->userdGpuAddr + NV_OFFSETOF(KeplerAControlGPFifo, GPPut); + if (gpuIsCCFeatureEnabled(pGpu) && (channel->tsg->engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2)) + { + channelInfo->gpGet = NULL; + channelInfo->gpPut = NULL; + channelInfo->gpFifoEntries = NULL; + } + return NV_OK; cleanup_free_controlpage: @@ -4738,7 +4877,6 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, static NV_STATUS engineAllocate(struct gpuChannel *channel, gpuChannelInfo *channelInfo, UVM_GPU_CHANNEL_ENGINE_TYPE engineType) { NV_STATUS status = NV_OK; - struct gpuObject *object = NULL; NVB0B5_ALLOCATION_PARAMETERS ceAllocParams = {0}; NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS channelGrpParams = {0}; struct gpuAddressSpace *vaSpace = NULL; @@ -4746,49 +4884,45 @@ static NV_STATUS engineAllocate(struct gpuChannel *channel, gpuChannelInfo *chan struct gpuSession *session = NULL; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); NvU32 class; + NvU32 paramsSize; void *params; NV_ASSERT(channel); NV_ASSERT(channelInfo); - NV_ASSERT(channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || - channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2); - - // TODO: Bug 2458492: Ampere-SMC Verify GR/CE indices within partition + NV_ASSERT(engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2); - vaSpace = channel->vaSpace; + vaSpace = channel->tsg->vaSpace; NV_ASSERT(vaSpace); device = vaSpace->device; NV_ASSERT(device); session = device->session; NV_ASSERT(session); - object = portMemAllocNonPaged(sizeof(*object)); - if (object == NULL) - return NV_ERR_NO_MEMORY; - - object->handle = NV01_NULL_OBJECT; - if (engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE) { ceAllocParams.version = NVB0B5_ALLOCATION_PARAMETERS_VERSION_1; - ceAllocParams.engineType = NV2080_ENGINE_TYPE_COPY(channel->engineIndex); + ceAllocParams.engineType = NV2080_ENGINE_TYPE_COPY(channel->tsg->engineIndex); params = &ceAllocParams; + paramsSize = sizeof(ceAllocParams); class = device->ceClass; } else { params = NULL; + paramsSize = 0; class = device->sec2Class; } + channel->engineHandle = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, session->handle, channel->channelHandle, - &object->handle, + &channel->engineHandle, class, - params); + params, + paramsSize); if (status != NV_OK) - goto cleanup_free_memory; + return status; // In volta+ gpus, the channel has a submission offset used as doorbell. if (isDeviceVoltaPlus(device)) @@ -4800,6 +4934,11 @@ static NV_STATUS engineAllocate(struct gpuChannel *channel, gpuChannelInfo *chan channelInfo->workSubmissionOffset = channel->workSubmissionOffset; channelInfo->workSubmissionToken = channel->workSubmissionToken; channelInfo->pWorkSubmissionToken = channel->pWorkSubmissionToken; + if (channel->bClientRegionGpuMappingNeeded) + { + channelInfo->workSubmissionOffsetGpuVa = channel->clientRegionGpuAddr + + NVC361_NOTIFY_CHANNEL_PENDING; + } } // Schedule the channel @@ -4814,45 +4953,47 @@ static NV_STATUS engineAllocate(struct gpuChannel *channel, gpuChannelInfo *chan if (status != NV_OK) goto cleanup_free_engine; - object->next = channel->nextAttachedEngine; - channel->nextAttachedEngine = object; - object->type = class; - return NV_OK; cleanup_free_engine: - pRmApi->Free(pRmApi, session->handle, object->handle); -cleanup_free_memory: - portMemFree(object); + pRmApi->Free(pRmApi, session->handle, channel->engineHandle); + channel->engineHandle = NV01_NULL_OBJECT; return status; } -NV_STATUS nvGpuOpsChannelAllocate(struct gpuAddressSpace *vaSpace, +NV_STATUS nvGpuOpsChannelAllocate(const gpuTsgHandle tsg, const gpuChannelAllocParams *params, struct gpuChannel **channelHandle, gpuChannelInfo *channelInfo) { NV_STATUS status; - UVM_GPU_CHANNEL_ENGINE_TYPE channelType = params->engineType; + UVM_GPU_CHANNEL_ENGINE_TYPE channelType; + + if (!tsg || !channelHandle || !params || !channelInfo) + return NV_ERR_INVALID_ARGUMENT; - NV_ASSERT_OR_RETURN((channelType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || channelType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2), NV_ERR_NOT_SUPPORTED); + channelType = tsg->engineType; + NV_ASSERT(channelType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE || channelType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2); - status = channelAllocate(vaSpace, channelType, params, - channelHandle, channelInfo); + status = channelAllocate(tsg, params, channelHandle, channelInfo); if (status != NV_OK) return status; status = engineAllocate(*channelHandle, channelInfo, channelType); if (status != NV_OK) - nvGpuOpsChannelDestroy(*channelHandle); + goto cleanup_free_channel; + return NV_OK; + +cleanup_free_channel: + nvGpuOpsChannelDestroy(*channelHandle); + *channelHandle = NULL; return status; + } void nvGpuOpsChannelDestroy(struct gpuChannel *channel) { - struct gpuObject *nextEngine; - struct gpuObject *currEngine; NvU32 pid = osGetCurrentProcess(); struct gpuAddressSpace *vaSpace = NULL; struct gpuDevice *device = NULL; @@ -4862,26 +5003,17 @@ void nvGpuOpsChannelDestroy(struct gpuChannel *channel) if (!channel) return; - vaSpace = channel->vaSpace; + NV_ASSERT(channel->tsg); + vaSpace = channel->tsg->vaSpace; NV_ASSERT(vaSpace); device = vaSpace->device; NV_ASSERT(device); session = device->session; NV_ASSERT(session); - // destroy the engines under this channel - if (channel->nextAttachedEngine) - { - currEngine = channel->nextAttachedEngine; - nextEngine = currEngine; - do - { - currEngine = nextEngine; - nextEngine = currEngine->next; - pRmApi->Free(pRmApi, session->handle, currEngine->handle); - portMemFree(currEngine); - } while (nextEngine != NULL); - } + // destroy the engine associated with the channel. + if (channel->engineHandle != NV01_NULL_OBJECT) + pRmApi->Free(pRmApi, session->handle, channel->engineHandle); // Tear down the channel if (isDevicePascalPlus(device)) @@ -4903,6 +5035,13 @@ void nvGpuOpsChannelDestroy(struct gpuChannel *channel) pid); } + if (channel->bClientRegionGpuMappingNeeded) + { + NV_ASSERT(isDeviceHopperPlus(device)); + nvGpuOpsUnmapGpuMemory(vaSpace, channel->clientRegionGpuAddr); + nvGpuOpsFreeVirtual(vaSpace, channel->clientRegionGpuAddr); + } + // Free the channel pRmApi->Free(pRmApi, session->handle, channel->channelHandle); @@ -4917,34 +5056,133 @@ void nvGpuOpsChannelDestroy(struct gpuChannel *channel) portMemFree(channel); } -static NV_STATUS trackDescriptor(PNODE *pRoot, NvU64 key, void *desc) +NV_STATUS nvGpuOpsTsgAllocate(struct gpuAddressSpace *vaSpace, + const gpuTsgAllocParams *params, + struct gpuTsg **tsgHandle) { - PNODE btreeNode; - NV_ASSERT(desc); - NV_ASSERT(pRoot); + NV_STATUS status; + struct gpuDevice *device = NULL; + struct gpuSession *session = NULL; + struct gpuTsg *tsg = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS tsgParams = { 0 }; + UVM_GPU_CHANNEL_ENGINE_TYPE engineType; - btreeNode = (PNODE)desc; + if (!vaSpace || !params || !tsgHandle) + return NV_ERR_INVALID_ARGUMENT; - btreeNode->keyStart = key; - btreeNode->keyEnd = key; - btreeNode->Data = desc; - return btreeInsert(btreeNode, pRoot); -} + engineType = params->engineType; -static NV_STATUS findDescriptor(PNODE pRoot, NvU64 key, void **desc) -{ - PNODE btreeNode = NULL; - NV_STATUS status = NV_OK; + if (engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_CE && + engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) + return NV_ERR_INVALID_ARGUMENT; - NV_ASSERT(desc); + tsg = portMemAllocNonPaged(sizeof(*tsg)); + if (tsg == NULL) + return NV_ERR_NO_MEMORY; - status = btreeSearch(key, &btreeNode, pRoot); - if (status != NV_OK) - return status; + portMemSet(tsg, 0, sizeof(*tsg)); - *desc = btreeNode->Data; - return NV_OK; -} + device = vaSpace->device; + NV_ASSERT(device); + session = device->session; + NV_ASSERT(session); + + tsg->vaSpace = vaSpace; + tsg->engineType = engineType; + tsg->engineIndex = params->engineIndex; + + // TSG is supported for any engine type starting on Volta. Prior to Volta + // only GR/compute channels use TSGs. nvGpuOps only allocates channels/TSGs + // for CE and SEC2 engine types. + tsg->isFakeTsg = !isDeviceVoltaPlus(device); + tsg->tsgHandle = NV01_NULL_OBJECT; + + if (tsg->isFakeTsg) + { + *tsgHandle = tsg; + return NV_OK; + } + + tsgParams.hVASpace = vaSpace->handle; + tsgParams.engineType = gpuGetNv2080EngineType(tsgEngineType(tsg)); + + status = pRmApi->Alloc(pRmApi, + session->handle, + device->handle, + &tsg->tsgHandle, + KEPLER_CHANNEL_GROUP_A, + &tsgParams, + sizeof(tsgParams)); + if (status != NV_OK) + goto cleanup_free_tsg; + + *tsgHandle = tsg; + + return NV_OK; + +cleanup_free_tsg: + portMemFree(tsg); + + return status; +} + +void nvGpuOpsTsgDestroy(struct gpuTsg *tsg) +{ + if (!tsg) + return; + + // RM takes care of freeing its internal TSG in the channel destruction + // path. + if (!tsg->isFakeTsg) + { + struct gpuAddressSpace *vaSpace = NULL; + struct gpuDevice *device = NULL; + struct gpuSession *session = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + + vaSpace = tsg->vaSpace; + NV_ASSERT(vaSpace); + device = vaSpace->device; + NV_ASSERT(device); + session = device->session; + NV_ASSERT(session); + + // Free the TSG + pRmApi->Free(pRmApi, session->handle, tsg->tsgHandle); + } + + portMemFree(tsg); +} + +static NV_STATUS trackDescriptor(PNODE *pRoot, NvU64 key, void *desc) +{ + PNODE btreeNode; + NV_ASSERT(desc); + NV_ASSERT(pRoot); + + btreeNode = (PNODE)desc; + + btreeNode->keyStart = key; + btreeNode->keyEnd = key; + btreeNode->Data = desc; + return btreeInsert(btreeNode, pRoot); +} + +static NV_STATUS findDescriptor(PNODE pRoot, NvU64 key, void **desc) +{ + PNODE btreeNode = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT(desc); + + status = btreeSearch(key, &btreeNode, pRoot); + if (status != NV_OK) + return status; + + *desc = btreeNode->Data; + return NV_OK; +} static NV_STATUS deleteDescriptor(PNODE *pRoot, NvU64 key, void **desc) { @@ -5206,8 +5444,6 @@ NV_STATUS nvGpuOpsQueryCaps(struct gpuDevice *device, gpuCaps *caps) NV_STATUS status; nvGpuOpsLockSet acquiredLocks; THREAD_STATE_NODE threadState; - OBJGPU *pGpu = NULL; - KernelMemorySystem *pKernelMemorySystem; NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS infoParams = {0}; struct gpuSession *session = device->session; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); @@ -5220,10 +5456,6 @@ NV_STATUS nvGpuOpsQueryCaps(struct gpuDevice *device, gpuCaps *caps) return status; } - caps->sysmemLink = device->sysmemLink; - caps->sysmemLinkRateMBps = device->sysmemLinkRateMBps; - caps->connectedToSwitch = device->connectedToSwitch; - infoParams.gpuId = device->gpuId; status = pRmApi->Control(pRmApi, session->handle, @@ -5232,11 +5464,7 @@ NV_STATUS nvGpuOpsQueryCaps(struct gpuDevice *device, gpuCaps *caps) &infoParams, sizeof(infoParams)); if (status != NV_OK) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return status; - } + goto cleanup; if (infoParams.numaId != NV0000_CTRL_NO_NUMA_NODE) { @@ -5244,51 +5472,10 @@ NV_STATUS nvGpuOpsQueryCaps(struct gpuDevice *device, gpuCaps *caps) caps->numaNodeId = infoParams.numaId; } - status = CliSetGpuContext(session->handle, device->handle, &pGpu, NULL); - if (status != NV_OK) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return status; - } - - pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - if (!pKernelMemorySystem) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } - - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)) - { - caps->systemMemoryWindowStart = pKernelMemorySystem->coherentCpuFbBase; - caps->systemMemoryWindowSize = pKernelMemorySystem->coherentCpuFbEnd - - pKernelMemorySystem->coherentCpuFbBase; - } - else - { - caps->systemMemoryWindowStart = 0; - caps->systemMemoryWindowSize = 0; - } - - if (device->connectedToSwitch) - { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - if (pKernelNvlink == NULL) - { - caps->nvswitchMemoryWindowStart = NVLINK_INVALID_FABRIC_ADDR; - } - else - { - caps->nvswitchMemoryWindowStart = knvlinkGetUniqueFabricBaseAddress( - pGpu, pKernelNvlink); - } - } - +cleanup: _nvGpuOpsLocksRelease(&acquiredLocks); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_OK; + return status; } static NV_STATUS findVaspaceFromPid(unsigned pid, unsigned gpuId, @@ -5323,8 +5510,12 @@ static NV_STATUS findVaspaceFromPid(unsigned pid, unsigned gpuId, if (!pGpu) return NV_ERR_INVALID_ARGUMENT; - pSubDevice = CliGetSubDeviceInfoFromGpu(pRsClient->hClient, - pGpu); + status = subdeviceGetByGpu(pRsClient, pGpu, &pSubDevice); + + if (status != NV_OK) + continue; + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); status = deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice); if (status == NV_OK) @@ -5458,6 +5649,211 @@ static NV_STATUS queryVirtMode(NvHandle hClient, NvHandle hDevice, NvU32 *virtMo return status; } +static NV_STATUS +nvGpuOpsQueryGpuConfidentialComputeCaps(NvHandle hClient, + UvmGpuConfComputeCaps *pGpuConfComputeCaps) +{ + NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS confComputeAllocParams = {0}; + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS confComputeParams = {0}; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NvHandle hConfCompute = 0; + NV_STATUS status = NV_OK; + + confComputeAllocParams.hClient = hClient; + status = pRmApi->Alloc(pRmApi, + hClient, + hClient, + &hConfCompute, + NV_CONFIDENTIAL_COMPUTE, + &confComputeAllocParams, + sizeof(confComputeAllocParams)); + if (status == NV_ERR_INVALID_CLASS) + { + pGpuConfComputeCaps->mode = UVM_GPU_CONF_COMPUTE_MODE_NONE; + return NV_OK; + } + else + { + NV_ASSERT_OK_OR_RETURN(status); + } + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + hClient, + hConfCompute, + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES, + &confComputeParams, + sizeof(confComputeParams)), + cleanup); + + if (confComputeParams.ccFeature == NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED) + { + pGpuConfComputeCaps->mode = UVM_GPU_CONF_COMPUTE_MODE_APM; + } + else if (confComputeParams.ccFeature == NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED) + { + pGpuConfComputeCaps->mode = UVM_GPU_CONF_COMPUTE_MODE_HCC; + } + +cleanup: + pRmApi->Free(pRmApi, hClient, hConfCompute); + return status; +} + +static NV_STATUS getSysmemLinkInfo(NvHandle hClient, + NvHandle hSubDevice, + gpuInfo *pGpuInfo) +{ + NvU32 sysmemConnType; + NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *busInfoParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NV_STATUS status; + + pGpuInfo->sysmemLink = UVM_LINK_TYPE_NONE; + + busInfoParams = portMemAllocNonPaged(sizeof(*busInfoParams)); + if (busInfoParams == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + portMemSet(busInfoParams, 0, sizeof(*busInfoParams)); + busInfoParams->busInfoListSize = 1; + busInfoParams->busInfoList[0].index = NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE; + status = pRmApi->Control(pRmApi, + hClient, + hSubDevice, + NV2080_CTRL_CMD_BUS_GET_INFO_V2, + busInfoParams, + sizeof(*busInfoParams)); + sysmemConnType = busInfoParams->busInfoList[0].data; + portMemFree(busInfoParams); + + if (status != NV_OK) + return status; + + switch (sysmemConnType) + { + case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK: + { + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus; + NvU32 nvlinkVersion; + NvBool atomicSupported; + + status = allocNvlinkStatus(hClient, hSubDevice, &nvlinkStatus); + if (status != NV_OK) + return status; + + nvlinkVersion = getNvlinkConnectionToNpu(nvlinkStatus, + &atomicSupported, + &pGpuInfo->sysmemLinkRateMBps); + + pGpuInfo->sysmemLink = rmControlToUvmNvlinkVersion(nvlinkVersion); + + portMemFree(nvlinkStatus); + break; + } + case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C: + { + NvBool c2cConnectedToCpu = NV_FALSE; + + status = getC2CConnectionToCpu(hClient, + hSubDevice, + &c2cConnectedToCpu, + &pGpuInfo->sysmemLinkRateMBps); + if (status != NV_OK) + return status; + + if (c2cConnectedToCpu == NV_FALSE) + { + NV_ASSERT(0); + return NV_ERR_INVALID_STATE; + } + + pGpuInfo->sysmemLink = UVM_LINK_TYPE_C2C; + break; + } + case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE: + { + pGpuInfo->sysmemLink = UVM_LINK_TYPE_PCIE; + status = getPCIELinkRateMBps(hClient, hSubDevice, &pGpuInfo->sysmemLinkRateMBps); + if (status != NV_OK) + return status; + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, "Unsupported sysmem connection type: %d\n", + sysmemConnType); + break; + } + } + + NV_PRINTF(LEVEL_INFO, "sysmem link type: %d bw: %u\n", pGpuInfo->sysmemLink, pGpuInfo->sysmemLinkRateMBps); + NV_ASSERT(pGpuInfo->sysmemLink != UVM_LINK_TYPE_NONE); + return NV_OK; +} + +static NV_STATUS getSystemMemoryWindow(OBJGPU *pGpu, gpuInfo *pGpuInfo) +{ + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + + if (!pKernelMemorySystem) + return NV_ERR_OBJECT_NOT_FOUND; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)) + { + pGpuInfo->systemMemoryWindowStart = pKernelMemorySystem->coherentCpuFbBase; + pGpuInfo->systemMemoryWindowSize = pKernelMemorySystem->coherentCpuFbEnd - + pKernelMemorySystem->coherentCpuFbBase; + } + else + { + pGpuInfo->systemMemoryWindowStart = 0; + pGpuInfo->systemMemoryWindowSize = 0; + } + + return NV_OK; +} + +static NV_STATUS getNvswitchInfo(OBJGPU *pGpu, + NvHandle hClient, + NvHandle hSubDevice, + gpuInfo *pGpuInfo) +{ + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus; + NvU32 nvlinkVersion; + NvU32 linkBandwidthMBps; + NV_STATUS status; + + pGpuInfo->connectedToSwitch = NV_FALSE; + + status = allocNvlinkStatus(hClient, hSubDevice, &nvlinkStatus); + if (status != NV_OK) + return status; + + nvlinkVersion = getNvlinkConnectionToSwitch(nvlinkStatus, &linkBandwidthMBps); + + if (rmControlToUvmNvlinkVersion(nvlinkVersion) != UVM_LINK_TYPE_NONE) + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV_ASSERT(rmControlToUvmNvlinkVersion(nvlinkVersion) != UVM_LINK_TYPE_NVLINK_1); + pGpuInfo->connectedToSwitch = NV_TRUE; + + if (pKernelNvlink == NULL) + { + pGpuInfo->nvswitchMemoryWindowStart = NVLINK_INVALID_FABRIC_ADDR; + } + else + { + pGpuInfo->nvswitchMemoryWindowStart = knvlinkGetUniqueFabricBaseAddress(pGpu, pKernelNvlink); + } + } + + portMemFree(nvlinkStatus); + + return NV_OK; +} + NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, const gpuClientInfo *pGpuClientInfo, gpuInfo *pGpuInfo) @@ -5520,7 +5916,8 @@ NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, clientHandle, &deviceHandle, NV01_DEVICE_0, - &nv0080AllocParams); + &nv0080AllocParams, + sizeof(nv0080AllocParams)); if (NV_OK != status) goto cleanup; @@ -5532,7 +5929,8 @@ NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, deviceHandle, &subDeviceHandle, NV20_SUBDEVICE_0, - &nv2080AllocParams); + &nv2080AllocParams, + sizeof(nv2080AllocParams)); if (NV_OK != status) goto cleanup; @@ -5629,6 +6027,24 @@ NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, pGpuInfo->isSimulated = (simulationInfoParams.type != NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE); + portMemSet(&pGpuInfo->gpuConfComputeCaps, 0, sizeof(pGpuInfo->gpuConfComputeCaps)); + + status = nvGpuOpsQueryGpuConfidentialComputeCaps(clientHandle, &pGpuInfo->gpuConfComputeCaps); + if (status != NV_OK) + goto cleanup; + + status = getSysmemLinkInfo(clientHandle, subDeviceHandle, pGpuInfo); + if (status != NV_OK) + goto cleanup; + + status = getSystemMemoryWindow(pGpu, pGpuInfo); + if (status != NV_OK) + goto cleanup; + + status = getNvswitchInfo(pGpu, clientHandle, subDeviceHandle, pGpuInfo); + if (status != NV_OK) + goto cleanup; + cleanup: if (isSubdeviceAllocated) pRmApi->Free(pRmApi, clientHandle, subDeviceHandle); @@ -5738,7 +6154,7 @@ NV_STATUS nvGpuOpsCheckEccErrorSlowpath(struct gpuChannel *channel, threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_READ, - channel->vaSpace->device->session->handle, + channel->tsg->vaSpace->device->session->handle, NULL, &acquiredLocks); if (status != NV_OK) @@ -5750,13 +6166,13 @@ NV_STATUS nvGpuOpsCheckEccErrorSlowpath(struct gpuChannel *channel, *bEccDbeSet = NV_FALSE; // Do anything only if ECC is enabled on this device - if (channel->vaSpace->device->rmSubDevice->bEccEnabled) + if (channel->tsg->vaSpace->device->rmSubDevice->bEccEnabled) { portMemSet(&eccStatus, 0, sizeof(eccStatus)); status = pRmApi->Control(pRmApi, - channel->vaSpace->device->session->handle, - channel->vaSpace->device->subhandle, + channel->tsg->vaSpace->device->session->handle, + channel->tsg->vaSpace->device->subhandle, NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS, &eccStatus, sizeof(eccStatus)); @@ -5838,7 +6254,8 @@ static NV_STATUS nvGpuOpsFillGpuMemoryInfo(PMEMORY_DESCRIPTOR pMemDesc, static NvBool memdescIsSysmem(PMEMORY_DESCRIPTOR pMemDesc) { - return memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM; + return (memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) && + !(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)); } static NV_STATUS dupMemory(struct gpuDevice *device, @@ -5858,11 +6275,12 @@ static NV_STATUS dupMemory(struct gpuDevice *device, FABRIC_VASPACE *pFabricVAS = NULL; OBJGPU *pMappingGpu; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RsClient *pSessionClient; RsResourceRef *pResourceRef; RsResourceRef *pParentRef; + Subdevice *pSubdevice; struct gpuSession *session; NvHandle hParent; - NvHandle hSubDevice; NvBool bIsIndirectPeer = NV_FALSE; if (!device || !hDupMemory) @@ -5873,21 +6291,22 @@ static NV_STATUS dupMemory(struct gpuDevice *device, threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // RS-TODO use dual client locking - status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_NONE, NV01_NULL_OBJECT, NULL, &acquiredLocks); + status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_NONE, device->session->handle, + &pSessionClient, &acquiredLocks); if (status != NV_OK) { threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); return status; } - status = CliSetSubDeviceContext(device->session->handle, - device->subhandle, - &hSubDevice, - &pMappingGpu); - + status = subdeviceGetByHandle(pSessionClient, device->subhandle, &pSubdevice); if (status != NV_OK) goto done; + pMappingGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + // Get all the necessary information about the memory status = nvGpuOpsGetMemoryByHandle(hClient, hPhysMemory, @@ -6155,6 +6574,7 @@ static void setCeCaps(const NvU8 *rmCeCaps, gpuCeCaps *ceCaps) ceCaps->nvlinkP2p = !!NV2080_CTRL_CE_GET_CAP(rmCeCaps, NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P); ceCaps->sysmem = !!NV2080_CTRL_CE_GET_CAP(rmCeCaps, NV2080_CTRL_CE_CAPS_CE_SYSMEM); ceCaps->p2p = !!NV2080_CTRL_CE_GET_CAP(rmCeCaps, NV2080_CTRL_CE_CAPS_CE_P2P); + ceCaps->secure = !!NV2080_CTRL_CE_GET_CAP(rmCeCaps, NV2080_CTRL_CE_CAPS_CE_CC_SECURE); } static NV_STATUS queryCopyEngines(struct gpuDevice *gpu, gpuCesCaps *cesCaps) @@ -6283,7 +6703,8 @@ static NvBool isClassSec2(NvU32 class) { switch (class) { - + case HOPPER_SEC2_WORK_LAUNCH_A: + return NV_TRUE; default: return NV_FALSE; } @@ -6797,8 +7218,9 @@ NV_STATUS nvGpuOpsFreeDupedHandle(struct gpuDevice *device, Memory *pMemory = NULL; OBJGPU *pMappingGpu = NULL; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RsClient *pClient; + Subdevice *pSubdevice; NvHandle hClient; - NvHandle hSubDevice; if (!device) return NV_ERR_INVALID_ARGUMENT; @@ -6806,20 +7228,21 @@ NV_STATUS nvGpuOpsFreeDupedHandle(struct gpuDevice *device, hClient = device->session->handle; threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - status = _nvGpuOpsLocksAcquire(RMAPI_LOCK_FLAGS_READ, hClient, NULL, 0, 0, 0, &acquiredLocks); + status = _nvGpuOpsLocksAcquire(RMAPI_LOCK_FLAGS_READ, hClient, &pClient, 0, 0, 0, &acquiredLocks); if (status != NV_OK) { threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); return status; } - status = CliSetSubDeviceContext(device->session->handle, - device->subhandle, - &hSubDevice, - &pMappingGpu); + status = subdeviceGetByHandle(pClient, device->subhandle, &pSubdevice); if (status != NV_OK) goto out; + pMappingGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + status = nvGpuOpsGetMemoryByHandle(device->session->handle, hPhysHandle, &pMemory); @@ -6852,6 +7275,21 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, void *bufferAddress = NULL; NvU32 faultBufferSize = 0; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + RsClient *pClient; + Device *pDevice; + NvHandle hClient = device->session->handle; + NvHandle hDevice = device->handle; + UvmFaultMetadataPacket *bufferMetadata = NULL; + + status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); + if (status != NV_OK) + return status; + + status = deviceGetByHandle(pClient, hDevice, &pDevice); + if (status != NV_OK) + return status; + + pFaultInfo->pDevice = pDevice; pFaultInfo->faultBufferHandle = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, @@ -6859,11 +7297,22 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, device->subhandle, &pFaultInfo->faultBufferHandle, device->faultBufferClass, - &faultBufferAllocParams); + &faultBufferAllocParams, + sizeof(faultBufferAllocParams)); if (status != NV_OK) goto cleanup; + OBJGPU *pGpu; + + pGpu = GPU_RES_GET_GPU(pDevice); + // + // When Hopper CC is enabled, UVM won't have direct access to the replayable + // HW fault buffer. Instead, it will be using a shadow fault buffer in + // unprotected sysmem and GSP-RM will be copying encrypted fault packets from the + // HW fault buffer to this shadow buffer + // + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { // Get the Size of the fault buffer status = pRmApi->Control(pRmApi, @@ -6906,6 +7355,44 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, pFaultInfo->nonReplayable.shadowBufferAddress = (void *)NvP64_VALUE(nonReplayableFaultsParams.pShadowBuffer); pFaultInfo->nonReplayable.shadowBufferContext = (void *)NvP64_VALUE(nonReplayableFaultsParams.pShadowBufferContext); pFaultInfo->nonReplayable.bufferSize = nonReplayableFaultsParams.bufferSize; + pFaultInfo->nonReplayable.shadowBufferMetadata = (UvmFaultMetadataPacket *)NvP64_VALUE(nonReplayableFaultsParams.pShadowBufferMetadata); + } + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS replayableFaultsParams = {0}; + + // Allocate a shadow buffer for replayable faults in case Hopper CC is enabled + status = pRmApi->Control(pRmApi, + session->handle, + pFaultInfo->faultBufferHandle, + NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF, + &replayableFaultsParams, + sizeof(replayableFaultsParams)); + if (status != NV_OK) + goto cleanup_fault_buffer; + + bufferAddress = (void *)NvP64_VALUE(replayableFaultsParams.pShadowBuffer); + faultBufferSize = replayableFaultsParams.bufferSize; + + // Make sure that the UVM and RM sizes of the metadata packet are equal. + ct_assert(sizeof(GMMU_FAULT_PACKET_METADATA) == sizeof(UvmFaultMetadataPacket)); + bufferMetadata = (UvmFaultMetadataPacket *)NvP64_VALUE(replayableFaultsParams.pShadowBufferMetadata); + + // Get the register mappings for non-replayable fault buffer + portMemSet(®istermappingsParams, 0, sizeof(registermappingsParams)); + + registermappingsParams.faultBufferType = NVB069_CTRL_FAULT_BUFFER_NON_REPLAYABLE; + status = pRmApi->Control(pRmApi, + session->handle, + pFaultInfo->faultBufferHandle, + NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS, + ®istermappingsParams, + sizeof(registermappingsParams)); + if (status != NV_OK) + goto cleanup_fault_buffer; + + pFaultInfo->nonReplayable.pFaultBufferPut = (NvU32*)(NvUPtr)registermappingsParams.pFaultBufferPut; } registermappingsParams.faultBufferType = NVB069_CTRL_FAULT_BUFFER_REPLAYABLE; @@ -6928,10 +7415,21 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, pFaultInfo->replayable.pPrefetchCtrl = (NvU32*)(NvUPtr)registermappingsParams.pPrefetchCtrl; pFaultInfo->replayable.bufferSize = faultBufferSize; pFaultInfo->replayable.bufferAddress = bufferAddress; + pFaultInfo->replayable.bufferMetadata = bufferMetadata; + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + pFaultInfo->replayable.bUvmOwnsHwFaultBuffer = NV_FALSE; + } + else + { + pFaultInfo->replayable.bUvmOwnsHwFaultBuffer = NV_TRUE; + } return NV_OK; cleanup_fault_buffer: + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { gpuDeviceUnmapCpuFreeHandle(device, pFaultInfo->faultBufferHandle, @@ -6944,15 +7442,15 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, } NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, - gpuAccessCntrInfo *pAccessCntrInfo) + gpuAccessCntrInfo *pAccessCntrInfo, + NvU32 accessCntrIndex) { struct gpuSession *session = device->session; NV_STATUS status = NV_OK; - NvU32 accessCntrBufferAllocParams = {0}; + NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS accessCntrBufferAllocParams = {0}; NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_SIZE_PARAMS sizeParams = {0}; NVC365_CTRL_ACCESS_CNTR_BUFFER_GET_REGISTER_MAPPINGS_PARAMS registermappings; void *bufferAddress; - NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS getDmaBaseSysmemAddrParams = {0}; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); OBJGPU *pGpu = NULL; @@ -6965,13 +7463,15 @@ NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, if (status != NV_OK) return status; + accessCntrBufferAllocParams.accessCounterIndex = accessCntrIndex; pAccessCntrInfo->accessCntrBufferHandle = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, session->handle, device->subhandle, &pAccessCntrInfo->accessCntrBufferHandle, device->accessCounterBufferClass, - &accessCntrBufferAllocParams); + &accessCntrBufferAllocParams, + sizeof(accessCntrBufferAllocParams)); if (status != NV_OK) goto cleanup; @@ -7005,15 +7505,6 @@ NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, if (status != NV_OK) goto cleanup_access_ctr_buffer; - status = pRmApi->Control(pRmApi, - session->handle, - device->handle, - NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR, - &getDmaBaseSysmemAddrParams, - sizeof(getDmaBaseSysmemAddrParams)); - if (status != NV_OK) - goto cleanup_access_ctr_buffer; - pAccessCntrInfo->pAccessCntrBufferGet = (NvU32*)(NvUPtr)registermappings.pAccessCntrBufferGet; pAccessCntrInfo->pAccessCntrBufferPut = (NvU32*)(NvUPtr)registermappings.pAccessCntrBufferPut; pAccessCntrInfo->pAccessCntrBufferFull = (NvU32*)(NvUPtr)registermappings.pAccessCntrBufferFull; @@ -7021,7 +7512,6 @@ NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, pAccessCntrInfo->pHubIntrEnSet = (NvU32*)(NvUPtr)registermappings.pHubIntrEnSet; pAccessCntrInfo->pHubIntrEnClear = (NvU32*)(NvUPtr)registermappings.pHubIntrEnClear; pAccessCntrInfo->accessCounterMask = registermappings.accessCntrMask; - pAccessCntrInfo->baseDmaSysmemAddr = getDmaBaseSysmemAddrParams.baseDmaSysmemAddr; return NV_OK; @@ -7175,6 +7665,14 @@ NV_STATUS nvGpuOpsDestroyFaultInfo(struct gpuDevice *device, NV_STATUS status = NV_OK; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + OBJGPU *pGpu; + + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); + NV_ASSERT(status == NV_OK); + status = CliSetGpuContext(device->session->handle, device->handle, &pGpu, NULL); + NV_ASSERT(status == NV_OK); + rmapiLockRelease(); + if (pFaultInfo->faultBufferHandle && isDeviceVoltaPlus(device)) { NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS params = {0}; @@ -7190,6 +7688,21 @@ NV_STATUS nvGpuOpsDestroyFaultInfo(struct gpuDevice *device, NV_ASSERT(status == NV_OK); } + if (pFaultInfo->faultBufferHandle && gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS params = {0}; + + params.pShadowBuffer = NV_PTR_TO_NvP64(pFaultInfo->replayable.bufferAddress); + + status = pRmApi->Control(pRmApi, + device->session->handle, + pFaultInfo->faultBufferHandle, + NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF, + ¶ms, + sizeof(params)); + NV_ASSERT(status == NV_OK); + } + else { gpuDeviceUnmapCpuFreeHandle(device, pFaultInfo->faultBufferHandle, @@ -7204,39 +7717,134 @@ NV_STATUS nvGpuOpsDestroyFaultInfo(struct gpuDevice *device, NV_STATUS nvGpuOpsHasPendingNonReplayableFaults(gpuFaultInfo *pFaultInfo, NvBool *hasPendingFaults) { - GMMU_SHADOW_FAULT_BUF *pQueue = - (GMMU_SHADOW_FAULT_BUF *) pFaultInfo->nonReplayable.shadowBufferAddress; + NV_STATUS status = NV_OK; - if (!pQueue || !hasPendingFaults) + if (hasPendingFaults == NULL) return NV_ERR_INVALID_ARGUMENT; - *hasPendingFaults = !queueIsEmpty(pQueue); + if (pFaultInfo->pDevice == NULL) + return NV_ERR_INVALID_ARGUMENT; - return NV_OK; + OBJGPU *pGpu; + + pGpu = GPU_RES_GET_GPU(pFaultInfo->pDevice); + + // + // In case of GSP owned HW fault buffers, CPU-RM maintains the get pointer. + // The PUT pointer is updated by GSP in a PRI and CPU-RM just reads the same. + // GET != PUT implies pending faults in the shadow buffer + // + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + *hasPendingFaults = (pFaultInfo->nonReplayable.shadowBufferGet != + kgmmuReadShadowBufPutIndex_HAL(pGpu, + pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER)); + + } + else + { + GMMU_SHADOW_FAULT_BUF *pQueue = + (GMMU_SHADOW_FAULT_BUF *) pFaultInfo->nonReplayable.shadowBufferAddress; + + if (pQueue == NULL) + return NV_ERR_INVALID_ARGUMENT; + + *hasPendingFaults = !queueIsEmpty(pQueue); + } + + return status; } NV_STATUS nvGpuOpsGetNonReplayableFaults(gpuFaultInfo *pFaultInfo, void *faultBuffer, NvU32 *numFaults) { - GMMU_SHADOW_FAULT_BUF *pQueue = - (GMMU_SHADOW_FAULT_BUF *) pFaultInfo->nonReplayable.shadowBufferAddress; - QueueContext *pQueueCtx = - (QueueContext *) pFaultInfo->nonReplayable.shadowBufferContext; + NV_STATUS status = NV_OK; + + if (faultBuffer == NULL || numFaults == NULL) + return NV_ERR_INVALID_ARGUMENT; - if (!pQueue || !faultBuffer || !numFaults) + if (pFaultInfo->pDevice == NULL) return NV_ERR_INVALID_ARGUMENT; *numFaults = 0; - // Copy all faults in the client shadow fault buffer to the given buffer - while (queuePopAndCopyNonManaged(pQueue, pQueueCtx, faultBuffer)) + OBJGPU *pGpu; + + pGpu = GPU_RES_GET_GPU(pFaultInfo->pDevice); + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { - ++(*numFaults); - faultBuffer = (char *)faultBuffer + NVC369_BUF_SIZE; + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 shadowBufferPutIndex; + NvU32 shadowBufferGetIndex; + NvU32 maxFaultBufferEntries; + + maxFaultBufferEntries = pFaultInfo->nonReplayable.bufferSize / NVC369_BUF_SIZE; + shadowBufferGetIndex = pFaultInfo->nonReplayable.shadowBufferGet; + shadowBufferPutIndex = kgmmuReadShadowBufPutIndex_HAL(pGpu, + pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER); + // Copy the fault packets as long as GET != PUT + while (shadowBufferGetIndex != shadowBufferPutIndex) + { + UvmFaultMetadataPacket metadata; + NvU8 *pShadowBuffer = (NvU8 *)pFaultInfo->nonReplayable.shadowBufferAddress; + UvmFaultMetadataPacket *pShadowBufferMetadata = pFaultInfo->nonReplayable.shadowBufferMetadata; + + ++(*numFaults); + + // TODO: Revisit this while adding encryption/decryption support + // Once encryption/decryption is enabled, CPU-RM will have to decrypt + // the fault packet before copying it to the UVM provided buffer. For + // now a plain text copy should suffice. + portMemCopy(faultBuffer, NVC369_BUF_SIZE, + pShadowBuffer + (shadowBufferGetIndex * NVC369_BUF_SIZE), + NVC369_BUF_SIZE); + + portMemCopy(&metadata, sizeof(UvmFaultMetadataPacket), + pShadowBufferMetadata + shadowBufferGetIndex, + sizeof(UvmFaultMetadataPacket)); + + // CC-TODO: Packet decryption should go here. + if (metadata.valid != GMMU_FAULT_PACKET_METADATA_VALID_YES) + { + return NV_ERR_INVALID_STATE; + } + + // Clear the plaintext valid bit and authTag. + portMemSet(pShadowBufferMetadata + shadowBufferGetIndex, + 0x0, + sizeof(UvmFaultMetadataPacket)); + + shadowBufferGetIndex = (shadowBufferGetIndex + 1) % maxFaultBufferEntries; + faultBuffer = (NvU8 *)faultBuffer + NVC369_BUF_SIZE; + } + // Update the GET pointer + pFaultInfo->nonReplayable.shadowBufferGet = shadowBufferGetIndex; } + else + { + GMMU_SHADOW_FAULT_BUF *pQueue = + (GMMU_SHADOW_FAULT_BUF *) pFaultInfo->nonReplayable.shadowBufferAddress; + QueueContext *pQueueCtx = + (QueueContext *) pFaultInfo->nonReplayable.shadowBufferContext; - return NV_OK; + if (pQueue == NULL) + return NV_ERR_INVALID_ARGUMENT; + + // Copy all faults in the client shadow fault buffer to the given buffer + while (queuePopAndCopyNonManaged(pQueue, pQueueCtx, faultBuffer)) + { + ++(*numFaults); + faultBuffer = (char *)faultBuffer + NVC369_BUF_SIZE; + } + } + + return status; } NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device) @@ -7265,36 +7873,38 @@ NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device) } static NV_STATUS nvGpuOpsVerifyChannel(struct gpuAddressSpace *vaSpace, - NvHandle hClient, + RsClient *pClient, NvHandle hKernelChannel, OBJGPU **pGpu, KernelChannel **ppKernelChannel) { NV_STATUS status = NV_OK; - NvHandle hDevice, hSubDevice; + NvHandle hDevice; OBJVASPACE *pVAS = NULL; OBJGPU *pVaSpaceGpu; - RsClient *pClient; + RsClient *pSessionClient; + Subdevice *pSubdevice; NV_ASSERT_OR_RETURN(ppKernelChannel != NULL, NV_ERR_INVALID_ARGUMENT); - status = serverGetClientUnderLock(&g_resServ, vaSpace->device->session->handle, &pClient); + status = serverGetClientUnderLock(&g_resServ, vaSpace->device->session->handle, + &pSessionClient); if (status != NV_OK) return status; - status = vaspaceGetByHandleOrDeviceDefault(pClient, + status = vaspaceGetByHandleOrDeviceDefault(pSessionClient, vaSpace->device->handle, vaSpace->handle, &pVAS); if (status != NV_OK) return status; - status = CliGetKernelChannel(hClient, hKernelChannel, ppKernelChannel); + status = CliGetKernelChannel(pClient, hKernelChannel, ppKernelChannel); if (status != NV_OK) return NV_ERR_INVALID_OBJECT_HANDLE; hDevice = RES_GET_HANDLE(GPU_RES_GET_DEVICE(*ppKernelChannel)); - status = CliSetGpuContext(hClient, hDevice, pGpu, NULL); + status = CliSetGpuContext(pClient->hClient, hDevice, pGpu, NULL); if (status != NV_OK) return status; @@ -7311,13 +7921,15 @@ static NV_STATUS nvGpuOpsVerifyChannel(struct gpuAddressSpace *vaSpace, // In SLI config, RM's internal allocations such as channel instance // are tracked with a memdesc per subdevice. Hence, Get the correct pGpu. - status = CliSetSubDeviceContext(vaSpace->device->session->handle, - vaSpace->device->subhandle, - &hSubDevice, - pGpu); + status = subdeviceGetByHandle(pSessionClient, vaSpace->device->subhandle, + &pSubdevice); if (status != NV_OK) return status; + *pGpu = GPU_RES_GET_GPU(pSubdevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + return NV_OK; } @@ -7618,6 +8230,7 @@ NV_STATUS nvGpuOpsRetainChannel(struct gpuAddressSpace *vaSpace, { nvGpuOpsLockSet acquiredLocks; THREAD_STATE_NODE threadState; + RsClient *pClient; KernelChannel *pKernelChannel = NULL; OBJGPU *pGpu = NULL; gpuRetainedChannel *channel = NULL; @@ -7635,7 +8248,7 @@ NV_STATUS nvGpuOpsRetainChannel(struct gpuAddressSpace *vaSpace, threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_READ, hClient, - NULL, + &pClient, &acquiredLocks); if (status != NV_OK) { @@ -7646,7 +8259,7 @@ NV_STATUS nvGpuOpsRetainChannel(struct gpuAddressSpace *vaSpace, device = vaSpace->device; rmSubDevice = device->rmSubDevice; - status = nvGpuOpsVerifyChannel(vaSpace, hClient, hKernelChannel, &pGpu, + status = nvGpuOpsVerifyChannel(vaSpace, pClient, hKernelChannel, &pGpu, &pKernelChannel); if (status != NV_OK) { @@ -7716,7 +8329,8 @@ NV_STATUS nvGpuOpsRetainChannel(struct gpuAddressSpace *vaSpace, hChannelParent, &channel->hChannelRetainer, UVM_CHANNEL_RETAINER, - &channelRetainerParams); + &channelRetainerParams, + sizeof(channelRetainerParams)); if (status != NV_OK) goto error; @@ -8228,11 +8842,11 @@ NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace, NV_STATUS status = NV_OK; nvGpuOpsLockSet acquiredLocks; THREAD_STATE_NODE threadState; - NvHandle hSubDevice; PMEMORY_DESCRIPTOR pMemDesc = NULL; OBJGPU *pMappingGpu = NULL; OBJVASPACE *pVAS = NULL; RsClient *pClient; + Subdevice *pSubDevice; if (!vaSpace || !resourceDescriptor || !pGpuExternalMappingInfo) return NV_ERR_INVALID_ARGUMENT; @@ -8245,7 +8859,7 @@ NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace, threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_READ, vaSpace->device->session->handle, - NULL, + &pClient, &acquiredLocks); if (status != NV_OK) { @@ -8255,10 +8869,7 @@ NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace, pMemDesc = (MEMORY_DESCRIPTOR *) NvP64_VALUE(resourceDescriptor); - status = CliSetSubDeviceContext(vaSpace->device->session->handle, - vaSpace->device->subhandle, - &hSubDevice, - &pMappingGpu); + status = subdeviceGetByHandle(pClient, vaSpace->device->subhandle, &pSubDevice); if (status != NV_OK) { _nvGpuOpsLocksRelease(&acquiredLocks); @@ -8266,6 +8877,10 @@ NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace, return status; } + pMappingGpu = GPU_RES_GET_GPU(pSubDevice); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + if (pMemDesc->pGpu != pMappingGpu) { _nvGpuOpsLocksRelease(&acquiredLocks); @@ -8282,14 +8897,6 @@ NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace, return NV_ERR_NOT_SUPPORTED; } - status = serverGetClientUnderLock(&g_resServ, vaSpace->device->session->handle, &pClient); - if (status != NV_OK) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return status; - } - status = vaspaceGetByHandleOrDeviceDefault(pClient, vaSpace->device->handle, vaSpace->handle, @@ -8484,6 +9091,9 @@ ct_assert(sizeof(UvmPmaStatistics) == sizeof(PMA_STATS)); ct_assert(NV_OFFSETOF(UvmPmaStatistics, numPages2m) == NV_OFFSETOF(PMA_STATS, num2mbPages)); ct_assert(NV_OFFSETOF(UvmPmaStatistics, numFreePages64k) == NV_OFFSETOF(PMA_STATS, numFreeFrames)); ct_assert(NV_OFFSETOF(UvmPmaStatistics, numFreePages2m) == NV_OFFSETOF(PMA_STATS, numFree2mbPages)); +ct_assert(NV_OFFSETOF(UvmPmaStatistics, numPages2mProtected) == NV_OFFSETOF(PMA_STATS, num2mbPagesProtected)); +ct_assert(NV_OFFSETOF(UvmPmaStatistics, numFreePages64kProtected) == NV_OFFSETOF(PMA_STATS, numFreeFramesProtected)); +ct_assert(NV_OFFSETOF(UvmPmaStatistics, numFreePages2mProtected) == NV_OFFSETOF(PMA_STATS, numFree2mbPagesProtected)); /*! * Retrieve the PMA (Physical Memory Allocator) object initialized by RM @@ -8522,53 +9132,51 @@ NV_STATUS nvGpuOpsGetPmaObject(struct gpuDevice *device, return status; } - status = CliSetGpuContext(session->handle, device->handle, &pGpu, NULL); - if (status != NV_OK) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + CliSetGpuContext(session->handle, device->handle, &pGpu, NULL), + done); pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - if (pMemoryManager == NULL) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pMemoryManager != NULL, + status = NV_ERR_OBJECT_NOT_FOUND; goto done; ); if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + RsClient *pClient; + Device *pDevice; - status = kmigmgrGetMemoryPartitionHeapFromClient(pGpu, pKernelMIGManager, session->handle, &pHeap); - if (status != NV_OK) - return status; + NV_ASSERT_OK_OR_GOTO(status, + serverGetClientUnderLock(&g_resServ, session->handle, &pClient), + done); + + NV_ASSERT_OK_OR_GOTO(status, + deviceGetByHandle(pClient, device->handle, &pDevice), + done); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, pKernelMIGManager, pDevice, &pHeap), + done); } else pHeap = GPU_GET_HEAP(pGpu); - if (pHeap == NULL) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pHeap != NULL, + status = NV_ERR_OBJECT_NOT_FOUND; goto done; ); - if (!memmgrIsPmaInitialized(pMemoryManager)) - { - _nvGpuOpsLocksRelease(&acquiredLocks); - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_ERR_OBJECT_NOT_FOUND; - } + NV_CHECK_OR_ELSE(LEVEL_ERROR, + memmgrIsPmaInitialized(pMemoryManager), + status = NV_ERR_OBJECT_NOT_FOUND; goto done; ); *pPmaObject = (void *)&pHeap->pmaObject; *pPmaStats = (const UvmPmaStatistics *)&pHeap->pmaObject.pmaStats; +done: _nvGpuOpsLocksRelease(&acquiredLocks); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return NV_OK; + return status; } NV_STATUS nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, @@ -8600,7 +9208,7 @@ NV_STATUS nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, session = device1->session; hTemp = NV01_NULL_OBJECT; - status = pRmApi->Alloc(pRmApi, session->handle, session->handle, &hTemp, NV50_P2P, &p2pAllocParams); + status = pRmApi->Alloc(pRmApi, session->handle, session->handle, &hTemp, NV50_P2P, &p2pAllocParams, sizeof(p2pAllocParams)); if (status == NV_OK) *hP2pObject = hTemp; @@ -9004,3 +9612,131 @@ static NV_STATUS nvGpuOpsGetMemoryByHandle(NvHandle hClient, NvHandle hMemory, M ppMemory); } +NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx, + struct gpuChannel *channel) +{ + if ((ctx == NULL) || (channel == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslContextInitViaChannel(ctx, channel->tsg->vaSpace->device->session->handle, channel->channelHandle); +} + +NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + ccslContextClear(ctx); + return NV_OK; +} + +NV_STATUS nvGpuOpsCcslAcquireEncryptionIv(struct ccslContext_t *ctx, NvU8 *encryptIv) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslAcquireEncryptionIv(ctx, encryptIv); +} + +NV_STATUS nvGpuOpsCcslLogDeviceEncryption(struct ccslContext_t *ctx, NvU8 *decryptIv) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslLogDeviceEncryption(ctx, decryptIv); +} + +NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, NvU8 direction) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslRotateIv(ctx, direction); +} + +NV_STATUS nvGpuOpsCcslEncryptWithIv(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *encryptIv, + NvU8 *outputBuffer, + NvU8 *authTagBuffer) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslEncryptWithIv(ctx, bufferSize, inputBuffer, encryptIv, outputBuffer, authTagBuffer); +} + +NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *outputBuffer, + NvU8 *authTagBuffer) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslEncrypt(ctx, bufferSize, inputBuffer, outputBuffer, authTagBuffer); +} + +NV_STATUS nvGpuOpsCcslDecrypt(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 const *decryptIv, + NvU8 *outputBuffer, + NvU8 const *authTagBuffer) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslDecrypt(ctx, bufferSize, inputBuffer, decryptIv, outputBuffer, authTagBuffer); +} + +NV_STATUS nvGpuOpsCcslSign(struct ccslContext_t *ctx, + NvU32 bufferSize, + NvU8 const *inputBuffer, + NvU8 *authTagBuffer) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslSign(ctx, bufferSize, inputBuffer, authTagBuffer); +} + +NV_STATUS nvGpuOpsQueryMessagePool(struct ccslContext_t *ctx, + NvU8 direction, + NvU64 *messageNum) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + switch (direction) + { + case UVM_CSL_DIR_CPU_TO_GPU: + return ccslQueryMessagePool(ctx, CCSL_DIR_HOST_TO_DEVICE, messageNum); + case UVM_CSL_DIR_GPU_TO_CPU: + return ccslQueryMessagePool(ctx, CCSL_DIR_DEVICE_TO_HOST, messageNum); + default: + return NV_ERR_INVALID_ARGUMENT; + } +} diff --git a/src/nvidia/src/kernel/rmapi/resource.c b/src/nvidia/src/kernel/rmapi/resource.c index 3fc137430f..a2accf5d81 100644 --- a/src/nvidia/src/kernel/rmapi/resource.c +++ b/src/nvidia/src/kernel/rmapi/resource.c @@ -238,18 +238,11 @@ rmresControlSerialization_Prologue_IMPL ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) { - return serverSerializeCtrlDown(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags); + return serverSerializeCtrlDown(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags); } else { - // Deserialize and replace the pParams->pParams if necessary - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, serverDeserializeCtrlDown(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags)); - - if (pParams->flags & NVOS54_FLAGS_FINN_SERIALIZED) - { - pParams->pParams = pCallContext->pDeserializedParams; - pCallContext->bRestoreParams = NV_TRUE; - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, serverDeserializeCtrlDown(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags)); } return NV_OK; @@ -269,22 +262,18 @@ rmresControlSerialization_Epilogue_IMPL ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) { - NV_ASSERT_OK(serverDeserializeCtrlUp(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags)); - } - else if (pCallContext->bRestoreParams) - { - pParams->pParams = pCallContext->pSerializedParams; + NV_ASSERT_OK(serverDeserializeCtrlUp(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags)); } - NV_ASSERT_OK(serverSerializeCtrlUp(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags)); + NV_ASSERT_OK(serverSerializeCtrlUp(pCallContext, pParams->cmd, &pParams->pParams, &pParams->paramsSize, &pParams->flags)); serverFreeSerializeStructures(pCallContext, pParams->pParams); } NV_STATUS rmresControl_Prologue_IMPL ( - RmResource *pResource, - CALL_CONTEXT *pCallContext, + RmResource *pResource, + CALL_CONTEXT *pCallContext, RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { @@ -296,7 +285,7 @@ rmresControl_Prologue_IMPL (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) { // - // GPU lock is required to protect the RPC buffers. + // GPU lock is required to protect the RPC buffers. // However, some controls have ROUTE_TO_PHYSICAL + NO_GPUS_LOCK flags set. // This is not valid in offload mode, but is in monolithic. // In those cases, just acquire the lock for the RPC diff --git a/src/nvidia/src/kernel/rmapi/resource_desc.c b/src/nvidia/src/kernel/rmapi/resource_desc.c index e4230a9854..bd92ef45f1 100644 --- a/src/nvidia/src/kernel/rmapi/resource_desc.c +++ b/src/nvidia/src/kernel/rmapi/resource_desc.c @@ -109,7 +109,7 @@ g_RsResourceDescList[] = #undef RS_OPTIONAL #undef RS_NONE -#define NUM_ENTRIES_DESC_LIST NV_ARRAY_ELEMENTS32(g_RsResourceDescList) +#define NUM_ENTRIES_DESC_LIST NV_ARRAY_ELEMENTS(g_RsResourceDescList) void RsResInfoInitialize(void) { diff --git a/src/nvidia/src/kernel/rmapi/resource_list.h b/src/nvidia/src/kernel/rmapi/resource_list.h index 28152ae6a5..b4809d5c11 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list.h +++ b/src/nvidia/src/kernel/rmapi/resource_list.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -130,6 +130,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV_SEMAPHORE_SURFACE, + /* Internal Class */ SemaphoreSurface, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV50_P2P, /* Internal Class */ P2PApi, @@ -402,6 +412,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV_MEMORY_EXTENDED_USER, + /* Internal Class */ ExtendedGpuMemory, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV01_MEMORY_LOCAL_PHYSICAL, /* Internal Class */ PhysicalMemory, @@ -746,9 +766,9 @@ RS_ENTRY( RS_ENTRY( /* External Class */ ACCESS_COUNTER_NOTIFY_BUFFER, /* Internal Class */ AccessCounterBuffer, - /* Multi-Instance */ NV_FALSE, + /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Subdevice)), - /* Alloc Param Info */ RS_NONE, + /* Alloc Param Info */ RS_REQUIRED(NV_ACCESS_COUNTER_NOTIFY_BUFFER_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE @@ -1275,6 +1295,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ HOPPER_SEC2_WORK_LAUNCH_A, + /* Internal Class */ Sec2Context, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(KernelChannel)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ AMPERE_A, /* Internal Class */ KernelGraphicsObject, @@ -1445,6 +1475,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV_CONFIDENTIAL_COMPUTE, + /* Internal Class */ ConfidentialComputeApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(RmClientResource)), + /* Alloc Param Info */ RS_OPTIONAL(NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV_COUNTER_COLLECTION_UNIT, /* Internal Class */ KernelCcuApi, @@ -1455,6 +1495,18 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +#if RMCFG_CLASS_NV_CE_UTILS && (defined(DEBUG) || defined(DEVELOP)) +RS_ENTRY( + /* External Class */ NV_CE_UTILS, + /* Internal Class */ CeUtilsApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV0050_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_PRIVILEGED, + /* Required Access Rights */ RS_ACCESS_NONE +) +#endif // Undefine the entry macro to simplify call sites #undef RS_ENTRY diff --git a/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h b/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h index de4aef8b0b..2703e8a275 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h +++ b/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h @@ -45,28 +45,10 @@ #include "nvos.h" -#if RMCFG_CLASS_GF100_CHANNEL_GPFIFO || \ - RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_B || \ - RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_C || \ - RMCFG_CLASS_MAXWELL_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_PASCAL_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_VOLTA_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_TURING_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_AMPERE_CHANNEL_GPFIFO_A || \ - RMCFG_CLASS_HOPPER_CHANNEL_GPFIFO_A #include "alloc/alloc_channel.h" -#endif -#if RMCFG_CLASS_MAXWELL_DMA_COPY_A || \ - RMCFG_CLASS_PASCAL_DMA_COPY_A || \ - RMCFG_CLASS_PASCAL_DMA_COPY_B || \ - RMCFG_CLASS_VOLTA_DMA_COPY_A || \ - RMCFG_CLASS_TURING_DMA_COPY_A || \ - RMCFG_CLASS_AMPERE_DMA_COPY_A || \ - RMCFG_CLASS_AMPERE_DMA_COPY_B || \ - RMCFG_CLASS_HOPPER_DMA_COPY_A #include "class/clb0b5sw.h" -#endif + +#include "alloc/alloc_access_counter_buffer.h" #endif /* ifndef RESOURCE_LIST_REQUIRED_INCLUDES_H */ diff --git a/src/nvidia/src/kernel/rmapi/rmapi.c b/src/nvidia/src/kernel/rmapi/rmapi.c index 2ca7d11234..6ecccf1716 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi.c +++ b/src/nvidia/src/kernel/rmapi/rmapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -217,6 +217,65 @@ rmapiGetInterface return &g_RmApiList[rmapiType]; } +static void +_rmapiUnrefGpuAccessNeeded +( + NvU32 gpuMask +) +{ + NvU32 gpuInstance = 0; + OBJGPU *pGpu = NULL; + + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + osUnrefGpuAccessNeeded(pGpu->pOsGpuInfo); + } +} + +static NV_STATUS +_rmapiRefGpuAccessNeeded +( + NvU32 *pGpuMask +) +{ + NV_STATUS status = NV_OK; + NvU32 mask = 0; + NvU32 gpuInstance = 0; + OBJGPU *pGpu = NULL; + + status = gpumgrGetGpuAttachInfo(NULL, &mask); + if (status != NV_OK) + { + return status; + } + + while ((pGpu = gpumgrGetNextGpu(mask, &gpuInstance)) != NULL) + { + status = osRefGpuAccessNeeded(pGpu->pOsGpuInfo); + if (status != NV_OK) + { + goto unref; + } + + /* + *_rmapiRefGpuAccessNeeded records the gpuMask + * during ref up and this is used to unref exact same + * GPUs in _rmapiUnrefGpuAccessNeeded. This is done + * to protect against obtaining incorrect pGpu if the mask + * changes due to a RM_API called between ref/unref + * sequence. + */ + *pGpuMask |= (1 << pGpu->gpuInstance); + } + +unref: + if (status != NV_OK) + { + _rmapiUnrefGpuAccessNeeded(*pGpuMask); + } + return status; +} + NV_STATUS rmapiPrologue ( @@ -225,6 +284,49 @@ rmapiPrologue ) { NV_STATUS status = NV_OK; + NvBool bApiLockTaken = NV_FALSE; + NvU32 mask; + + NV_ASSERT_OR_RETURN(pRmApi != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pContext != NULL, NV_ERR_INVALID_ARGUMENT); + + /* + * Check for external clients. This condition is checked here + * in order to avoid a check at all caller sites of + * rmapiPrologue. Effectively rmapiprologue is a no-op for + * internal clients. + */ + if (!pRmApi->bTlsInternal) + { + mask = osGetDynamicPowerSupportMask(); + if (!mask) + return status; + /* + * NOTE1: Callers of rmapiPro{Epi}logue function call may call + * it with or without API lock taken. Hence, we check here + * whether API lock has been taken. We take API lock if + * it not taken already. + * We obtain the pGPU by using the gpuMask in + * _rmapiRef{Unref}GpuAccessNeeded. This needs API lock to be + * safe against init/teardown of GPUs while we ref/unref + * the GPUs. We release the lock after we have finished + * with ref/unref, if we had taken it. + */ + if (!rmapiLockIsOwner()) + { + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_CLIENT); + if (status != NV_OK) + { + return status; + } + bApiLockTaken = NV_TRUE; + } + status = _rmapiRefGpuAccessNeeded(&pContext->gpuMask); + if (bApiLockTaken == NV_TRUE) + { + rmapiLockRelease(); + } + } return status; } @@ -235,6 +337,43 @@ rmapiEpilogue RM_API_CONTEXT *pContext ) { + NV_STATUS status = NV_OK; + NvBool bApiLockTaken = NV_FALSE; + NvU32 mask; + + NV_ASSERT_OR_RETURN_VOID(pRmApi != NULL); + NV_ASSERT_OR_RETURN_VOID(pContext != NULL); + + /* + * Check for external clients. This condition is checked here + * in order to avoid a check at all caller sites of + * rmapiEpilogue. Effectively rmapiEpilogue is a no-op for + * internal clients. + */ + if (!pRmApi->bTlsInternal) + { + mask = osGetDynamicPowerSupportMask(); + if (!mask) + return; + + /* Please see NOTE1 */ + if (!rmapiLockIsOwner()) + { + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_CLIENT); + if (status != NV_OK) + { + return; + } + bApiLockTaken = NV_TRUE; + } + + _rmapiUnrefGpuAccessNeeded(pContext->gpuMask); + + if (bApiLockTaken == NV_TRUE) + { + rmapiLockRelease(); + } + } } void @@ -767,7 +906,7 @@ rmapiGetClientHandlesFromOSInfo { pClient = *it.pValue; pRsClient = staticCast(pClient, RsClient); - + NV_CHECK_OR_ELSE_STR(LEVEL_ERROR, pClient->pOSInfo == pOSInfo, "*** OS info mismatch", continue); pClientHandleList[k++] = pRsClient->hClient; diff --git a/src/nvidia/src/kernel/rmapi/rmapi_cache.c b/src/nvidia/src/kernel/rmapi/rmapi_cache.c index a9fab785e3..6746e87432 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_cache.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_cache.c @@ -51,7 +51,7 @@ MAKE_MAP(ObjectToGpuInstMap, NvU64); // Stores the cached control value. // Each submap in the multimap stores the cached control value for one GPU. // The key to find a submap is GPU Instance stored in ObjectToGpuInstMap -// +// // The key inside the submap is the control command // The value inside the submap is the cached control value for the command // @@ -375,7 +375,7 @@ static NV_STATUS _rmapiControlCacheSet // // A succeeded getOrInit call without params allocated implies - // duplicated cache insertion that should be skipped. + // duplicated cache insertion that should be skipped. // Duplicated cache set happens when // 1. Parallel controls call into RM before first cache set. // All threads will attempt cache set after the control calls. @@ -453,13 +453,13 @@ _getOrInitCacheEntry if (entry == NULL) goto failed_free_submap; - + if (entry->params == NULL) { entry->params = portMemAllocNonPaged(allocSize); if (entry->params == NULL) goto failed_free_entry; - + portMemSet(entry->params, 0, allocSize); if (pbParamsAllocated != NULL) @@ -739,7 +739,7 @@ NV_STATUS _gpuNameStringGet cachedParams->ascii, sizeof(pParams->gpuNameString.ascii)); break; - + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE: if (!cachedParams->bUnicodeValid) { @@ -816,7 +816,7 @@ NV_STATUS _gpuNameStringSet cachedParams->bAsciiValid = NV_TRUE; } break; - + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE: if (cachedParams->bUnicodeValid) { diff --git a/src/nvidia/src/kernel/rmapi/rmapi_finn.c b/src/nvidia/src/kernel/rmapi/rmapi_finn.c index abb1bf6258..f2df6c6288 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_finn.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_finn.c @@ -22,6 +22,7 @@ */ #include "resserv/resserv.h" +#include "rmapi/rmapi.h" #include "ctrl/ctrlxxxx.h" @@ -32,14 +33,16 @@ * * If unserialized params are passed in, try to serialize into CALL_CONTEXT. * If serialized params are passed in, set CALL_CONTEXT variables. + * + * Caller's parameters pointer and size will be overridden and restored on *CtrlUp call */ NV_STATUS serverSerializeCtrlDown ( CALL_CONTEXT *pCallContext, NvU32 cmd, - void *pParams, - NvU32 paramsSize, + void **ppParams, + NvU32 *pParamsSize, NvU32 *flags ) { @@ -50,10 +53,10 @@ serverSerializeCtrlDown const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); - NvU32 serializedSize = (NvU32)FinnRmApiGetSerializedSize(interface_id, message_id, pParams); + NvU32 serializedSize = (NvU32)FinnRmApiGetSerializedSize(interface_id, message_id, *ppParams); - pCallContext->pDeserializedParams = pParams; - pCallContext->deserializedSize = paramsSize; + pCallContext->pDeserializedParams = *ppParams; + pCallContext->deserializedSize = *pParamsSize; // Nothing to do if FINN doesn't support serializing this control if (serializedSize == 0) @@ -74,14 +77,13 @@ serverSerializeCtrlDown pCallContext->pSerializedParams = (FINN_RM_API *)pSerBuffer; } - status = FinnRmApiSerializeDown(interface_id, message_id, pParams, &pSerBuffer, serializedSize); + status = FinnRmApiSerializeDown(interface_id, message_id, *ppParams, pSerBuffer, serializedSize); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Serialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", - cmd, nvAssertStatusToString(status), status, - (NvUPtr)(pSerBuffer - (NvU8 *)pCallContext->pSerializedParams)); + "Serialization failed for cmd 0x%06x with status %s (0x%02x)\n", + cmd, nvAssertStatusToString(status), status); portMemFree(pCallContext->pSerializedParams); pCallContext->pSerializedParams = NULL; return status; @@ -89,12 +91,17 @@ serverSerializeCtrlDown pCallContext->serializedSize = serializedSize; *flags |= NVOS54_FLAGS_FINN_SERIALIZED; + + // Override passed in parameters + *ppParams = pCallContext->pSerializedParams; + *pParamsSize = pCallContext->serializedSize; + pCallContext->bLocalSerialization = NV_TRUE; } else { // Params are already serialized, just copy them in - pCallContext->pSerializedParams = pParams; - pCallContext->serializedSize = paramsSize; + pCallContext->pSerializedParams = *ppParams; + pCallContext->serializedSize = *pParamsSize; } return NV_OK; @@ -105,14 +112,16 @@ serverSerializeCtrlDown * * If serialized params are passed in, deserialize them into CALL_CONTEXT. * If deserialized params are passed in, set CALL_CONTEXT variables. + * + * Caller's parameters pointer and size will be overridden and restored on *CtrlUp call */ NV_STATUS serverDeserializeCtrlDown ( CALL_CONTEXT *pCallContext, NvU32 cmd, - void *pParams, - NvU32 paramsSize, + void **ppParams, + NvU32 *pParamsSize, NvU32 *flags ) { @@ -145,30 +154,33 @@ serverDeserializeCtrlDown pCallContext->pDeserializedParams = pDeserParams; } - pSerBuffer = (NvU8 *)pParams; + pSerBuffer = (NvU8 *)*ppParams; - status = FinnRmApiDeserializeDown(&pSerBuffer, paramsSize, pDeserParams, unserializedSize); + status = FinnRmApiDeserializeDown(pSerBuffer, *pParamsSize, pDeserParams, unserializedSize); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Deserialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", - cmd, nvAssertStatusToString(status), status, - (NvUPtr)(pSerBuffer - (NvU8 *)pParams)); + "Deserialization failed for cmd 0x%06x with status %s (0x%02x)\n", + cmd, nvAssertStatusToString(status), status); portMemFree(pCallContext->pDeserializedParams); pCallContext->pDeserializedParams = NULL; return status; } pCallContext->deserializedSize = unserializedSize; - pCallContext->pSerializedParams = pParams; - pCallContext->serializedSize = paramsSize; + pCallContext->pSerializedParams = *ppParams; + pCallContext->serializedSize = *pParamsSize; + + // Override passed in parameters + *ppParams = pCallContext->pDeserializedParams; + *pParamsSize = pCallContext->deserializedSize; } else { // Not serialized, copy into deser params - pCallContext->pDeserializedParams = pParams; - pCallContext->deserializedSize = paramsSize; + pCallContext->pDeserializedParams = *ppParams; + pCallContext->deserializedSize = *pParamsSize; } // Automatically request reserialization in case the control goes to GSP @@ -183,24 +195,24 @@ serverDeserializeCtrlDown * If serialized params are passed in, serialize into them from CALL_CONTEXT deserialized params. * If deserialized params are passed in, unset the serialized flag. We expect that this means that * the parameters were serialized locally and not by the caller. + * + * Caller's parameters pointer and size will be restored from *CtrlDown call */ NV_STATUS serverSerializeCtrlUp ( CALL_CONTEXT *pCallContext, NvU32 cmd, - void *pParams, - NvU32 paramsSize, + void **ppParams, + NvU32 *pParamsSize, NvU32 *flags ) { // // We add NVOS54_FLAGS_FINN_SERIALIZED if the control can be serialized but wasn't in serverSerializeCtrlDown // We don't want to return a serialized buffer if one wasn't given to us in the first place - // Check if pSerializedParams matches pParams to make sure the caller expects serialized info returned // - if ((*flags & NVOS54_FLAGS_FINN_SERIALIZED) && - (pCallContext->pSerializedParams == pParams)) + if ((*flags & NVOS54_FLAGS_FINN_SERIALIZED) && !pCallContext->bLocalSerialization) { NV_STATUS status; NvU8 *pSerBuffer; @@ -223,15 +235,17 @@ serverSerializeCtrlUp if (pDeserBuffer == NULL) return NV_OK; - status = FinnRmApiSerializeUp(interface_id, message_id, pDeserBuffer, &pSerBuffer, pCallContext->serializedSize); + status = FinnRmApiSerializeUp(interface_id, message_id, pDeserBuffer, pSerBuffer, pCallContext->serializedSize); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Serialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", - cmd, nvAssertStatusToString(status), status, - (NvUPtr)(pSerBuffer - (NvU8 *)pCallContext->pSerializedParams)); + "Serialization failed for cmd 0x%06x with status %s (0x%02x)\n", + cmd, nvAssertStatusToString(status), status); return status; } + + *ppParams = pCallContext->pSerializedParams; + *pParamsSize = pCallContext->serializedSize; } else if (*flags & NVOS54_FLAGS_FINN_SERIALIZED) { @@ -250,14 +264,16 @@ serverSerializeCtrlUp * If deserialized params are passed in with the serialized flag set, unset flag and deserialize into params. * We expect that this means that the parameters were serialized locally and not by the caller. * If deserialized params are passed in without the flag set just copy to CALL_CONTEXT + * + * Caller's parameters pointer and size will be restored from *CtrlDown call */ NV_STATUS serverDeserializeCtrlUp ( CALL_CONTEXT *pCallContext, NvU32 cmd, - void *pParams, - NvU32 paramsSize, + void **ppParams, + NvU32 *pParamsSize, NvU32 *flags ) { @@ -265,14 +281,15 @@ serverDeserializeCtrlUp { NV_STATUS status; NvU8 *pSerBuffer; + void *pDeserBuffer; const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); - if (pParams == pCallContext->pSerializedParams) + if (!pCallContext->bLocalSerialization) { - // Received serialized params from caller, no reason to deserialize up + // We didn't serialize down, so don't deserialize up return NV_OK; } else @@ -285,31 +302,289 @@ serverDeserializeCtrlUp if (unserializedSize == 0) return NV_ERR_LIB_RM_VERSION_MISMATCH; - pCallContext->pDeserializedParams = pParams; - // DeserializeUp expects pointers to be set up already + pDeserBuffer = pCallContext->pDeserializedParams; + if (pDeserBuffer == NULL) + return NV_ERR_INVALID_STATE; + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; if (pSerBuffer == NULL) return NV_ERR_INVALID_STATE; - status = FinnRmApiDeserializeUp(&pSerBuffer, pCallContext->serializedSize, pParams, unserializedSize); + status = FinnRmApiDeserializeUp(pSerBuffer, pCallContext->serializedSize, pDeserBuffer, unserializedSize); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Deserialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", - cmd, nvAssertStatusToString(status), status, - (NvUPtr)(pSerBuffer - (NvU8 *)pCallContext->pSerializedParams)); + "Deserialization failed for cmd 0x%06x with status %s (0x%02x)\n", + cmd, nvAssertStatusToString(status), status); return status; } pCallContext->deserializedSize = unserializedSize; + + *ppParams = pCallContext->pDeserializedParams; + *pParamsSize = pCallContext->deserializedSize; + } + + return NV_OK; +} + +NV_STATUS +serverSerializeAllocDown +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + const NvU32 interface_id = NV_RM_ALLOC_INTERFACE_INTERFACE_ID; + const NvU32 message_id = classId; + if (!(*flags & RMAPI_ALLOC_FLAGS_SERIALIZED)) + { + NV_STATUS status; + NvU8 *pSerBuffer; + NvU32 serializedSize = (NvU32)FinnRmApiGetSerializedSize(interface_id, message_id, *ppParams); + + pCallContext->pDeserializedParams = *ppParams; + pCallContext->deserializedSize = *pParamsSize; + + // Nothing to do if FINN doesn't support serializing this allocation + if (serializedSize == 0) + return NV_OK; + + // Assume we've already serialized if it exists + if (pCallContext->pSerializedParams != NULL) + { + NV_ASSERT_OR_RETURN(pCallContext->serializedSize == serializedSize, NV_ERR_INVALID_STATE); + return NV_OK; + } + else + { + pSerBuffer = portMemAllocNonPaged(serializedSize); + if (pSerBuffer == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + pCallContext->pSerializedParams = (FINN_RM_API *)pSerBuffer; + } + + status = FinnRmApiSerializeDown(interface_id, message_id, *ppParams, pSerBuffer, serializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Serialization failed for classId 0x%06x with status %s (0x%02x)\n", + classId, nvAssertStatusToString(status), status); + portMemFree(pCallContext->pSerializedParams); + pCallContext->pSerializedParams = NULL; + return status; + } + + pCallContext->serializedSize = serializedSize; + *flags |= RMAPI_ALLOC_FLAGS_SERIALIZED; + *ppParams = pCallContext->pSerializedParams; + *pParamsSize = serializedSize; + pCallContext->bLocalSerialization = NV_TRUE; } else { - // already in deserialized state - pCallContext->pDeserializedParams = pParams; - pCallContext->deserializedSize = paramsSize; + // Params are already serialized, just copy them in + pCallContext->pSerializedParams = *ppParams; + pCallContext->serializedSize = *pParamsSize; + } + + return NV_OK; +} + + +NV_STATUS +serverDeserializeAllocDown +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + const NvU32 interface_id = NV_RM_ALLOC_INTERFACE_INTERFACE_ID; + const NvU32 message_id = classId; + if (*flags & RMAPI_ALLOC_FLAGS_SERIALIZED) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserParams; + NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); + + // Report error if FINN can't deserialize but RM is reporting the alloc as serialized + if (unserializedSize == 0) + return NV_ERR_LIB_RM_VERSION_MISMATCH; + + // Assume we've already deserialized if it exists + if (pCallContext->pDeserializedParams != NULL) + { + NV_ASSERT_OR_RETURN(pCallContext->deserializedSize == unserializedSize, NV_ERR_INVALID_STATE); + return NV_OK; + } + else + { + pDeserParams = portMemAllocNonPaged(unserializedSize); + if (pDeserParams == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + pCallContext->pDeserializedParams = pDeserParams; + } + + pSerBuffer = (NvU8 *)*ppParams; + + status = FinnRmApiDeserializeDown(pSerBuffer, *pParamsSize, pDeserParams, unserializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Deserialization failed for classId 0x%06x with status %s (0x%02x)\n", + classId, nvAssertStatusToString(status), status); + portMemFree(pCallContext->pDeserializedParams); + pCallContext->pDeserializedParams = NULL; + return status; + } + + pCallContext->serializedSize = *pParamsSize; + pCallContext->deserializedSize = unserializedSize; + pCallContext->pSerializedParams = *ppParams; + + *ppParams = pCallContext->pDeserializedParams; + *pParamsSize = pCallContext->deserializedSize; + } + else + { + // Not serialized, copy into deser params + pCallContext->pDeserializedParams = *ppParams; + pCallContext->deserializedSize = *pParamsSize; + } + + // Automatically request reserialization in case the alloc goes to GSP + pCallContext->bReserialize = NV_TRUE; + + return NV_OK; +} + +NV_STATUS +serverSerializeAllocUp +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + // + // We add RMAPI_ALLOC_FLAGS_SERIALIZED if the alloc can be serialized but wasn't in serverSerializeAllocDown + // We don't want to return a serialized buffer if one wasn't given to us in the first place + // Check if pSerializedParams matches pParams to make sure the caller expects serialized info returned + // + if ((*flags & RMAPI_ALLOC_FLAGS_SERIALIZED) && !pCallContext->bLocalSerialization) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserBuffer; + const NvU32 interface_id = NV_RM_ALLOC_INTERFACE_INTERFACE_ID; + const NvU32 message_id = classId; + + // Should be serialized at this point. Expect that serializedSize is set otherwise something is wrong + if (pCallContext->serializedSize == 0) + return NV_ERR_INVALID_STATE; + + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; + pDeserBuffer = (NvU8 *) pCallContext->pDeserializedParams; + + if (pSerBuffer == NULL) + return NV_ERR_INVALID_STATE; + + // It's possible that we have nothing to do if we're just passing parameters along + if (pDeserBuffer == NULL) + return NV_OK; + + status = FinnRmApiSerializeUp(interface_id, message_id, pDeserBuffer, pSerBuffer, pCallContext->serializedSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Serialization failed for classId 0x%06x with status %s (0x%02x)\n", + classId, nvAssertStatusToString(status), status); + return status; + } + + *ppParams = pCallContext->pSerializedParams; + *pParamsSize = pCallContext->serializedSize; + } + else if (*flags & RMAPI_ALLOC_FLAGS_SERIALIZED) + { + // We serialized the alloc. Unset the flag + *flags &= ~RMAPI_ALLOC_FLAGS_SERIALIZED; + } + + return NV_OK; +} + +NV_STATUS +serverDeserializeAllocUp +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + const NvU32 interface_id = NV_RM_ALLOC_INTERFACE_INTERFACE_ID; + const NvU32 message_id = classId; + if (*flags & RMAPI_ALLOC_FLAGS_SERIALIZED) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserBuffer; + NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); + + if (!pCallContext->bLocalSerialization) + { + // We didn't serialize down, so don't deserialize up + return NV_OK; + } + else + { + // Serialized, but not passing back up serialized params, clear flag + *flags &= ~RMAPI_ALLOC_FLAGS_SERIALIZED; + } + + // Report error if FINN can't deserialize but RM is reporting the alloc as serialized + if (unserializedSize == 0) + return NV_ERR_LIB_RM_VERSION_MISMATCH; + + // DeserializeUp expects pointers to be set up already + pDeserBuffer = pCallContext->pDeserializedParams; + if (pDeserBuffer == NULL) + return NV_ERR_INVALID_STATE; + + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; + if (pSerBuffer == NULL) + return NV_ERR_INVALID_STATE; + + status = FinnRmApiDeserializeUp(pSerBuffer, pCallContext->serializedSize, pDeserBuffer, unserializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Deserialization failed for classId 0x%06x with status %s (0x%02x)\n", + classId, nvAssertStatusToString(status), status); + return status; + } + + pCallContext->deserializedSize = unserializedSize; + *ppParams = pCallContext->pDeserializedParams; + *pParamsSize = unserializedSize; } return NV_OK; diff --git a/src/nvidia/src/kernel/rmapi/rmapi_stubs.c b/src/nvidia/src/kernel/rmapi/rmapi_stubs.c index 06834def96..240ffa8f80 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_stubs.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_stubs.c @@ -24,19 +24,19 @@ static NV_STATUS _rmapiAlloc_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, void *pAllocParams) + NvHandle *phObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize) { return NV_ERR_NOT_SUPPORTED; } static NV_STATUS _rmapiAllocWithHandle_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle hObject, NvU32 hClass, void *pAllocParams) + NvHandle hObject, NvU32 hClass, void *pAllocParams, NvU32 paramsSize) { return NV_ERR_NOT_SUPPORTED; } static NV_STATUS _rmapiAllocWithSecInfo_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hParent, - NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, + NvHandle *phObject, NvU32 hClass, NvP64 pAllocParams, NvU32 paramsSize, NvU32 flags, NvP64 pRightsRequested, API_SECURITY_INFO *pSecInfo) { return NV_ERR_NOT_SUPPORTED; diff --git a/src/nvidia/src/kernel/rmapi/rmapi_utils.c b/src/nvidia/src/kernel/rmapi/rmapi_utils.c index 7505335087..8eda73e617 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_utils.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_utils.c @@ -57,7 +57,8 @@ rmapiutilAllocClientAndDeviceHandles NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_ROOT, - &hClient), + &hClient, + sizeof(hClient)), cleanup); // Allocate a device @@ -75,7 +76,8 @@ rmapiutilAllocClientAndDeviceHandles hClient, hDevice, NV01_DEVICE_0, - &nv0080AllocParams), + &nv0080AllocParams, + sizeof(nv0080AllocParams)), cleanup); // Allocate a subDevice @@ -92,7 +94,8 @@ rmapiutilAllocClientAndDeviceHandles hDevice, hSubDevice, NV20_SUBDEVICE_0, - &nv2080AllocParams), + &nv2080AllocParams, + sizeof(nv2080AllocParams)), cleanup); *phClient = hClient; diff --git a/src/nvidia/src/kernel/rmapi/rpc_common.c b/src/nvidia/src/kernel/rmapi/rpc_common.c index f88b5c9b5d..6d337004ee 100644 --- a/src/nvidia/src/kernel/rmapi/rpc_common.c +++ b/src/nvidia/src/kernel/rmapi/rpc_common.c @@ -83,6 +83,8 @@ OBJRPC *initRpcObject(OBJGPU *pGpu) gpuGetInstance(pGpu)); return NULL; } + pRpc->timeoutCount = 0; + pRpc->bQuietPrints = NV_FALSE; // VIRTUALIZATION is disabled on DCE. Only run the below code on VGPU and GSP. rpcSetIpVersion(pGpu, pRpc, diff --git a/src/nvidia/src/kernel/rmapi/rs_utils.c b/src/nvidia/src/kernel/rmapi/rs_utils.c index 533601adf3..96de03fce6 100644 --- a/src/nvidia/src/kernel/rmapi/rs_utils.c +++ b/src/nvidia/src/kernel/rmapi/rs_utils.c @@ -101,28 +101,20 @@ serverutilGetResourceRefWithParent return NV_OK; } -NV_STATUS -serverutilGetClientUnderLock +RmClient +*serverutilGetClientUnderLock ( - NvHandle hClient, - RmClient **ppClient + NvHandle hClient ) { NV_STATUS status; RsClient *pRsClient; - RmClient *pClient; status = serverGetClientUnderLock(&g_resServ, hClient, &pRsClient); if (status != NV_OK) - return status; - - pClient = dynamicCast(pRsClient, RmClient); - NV_ASSERT(pClient != NULL); - - if (ppClient) - *ppClient = pClient; + return NULL; - return NV_OK; + return dynamicCast(pRsClient, RmClient); } RmClient @@ -238,9 +230,9 @@ serverutilValidateNewResourceHandle NvHandle hObject ) { - RmClient *pClient; + RmClient *pClient = serverutilGetClientUnderLock(hClient); - return ((NV_OK == serverutilGetClientUnderLock(hClient, &pClient)) && + return ((pClient != NULL) && (NV_OK == clientValidateNewResourceHandle(staticCast(pClient, RsClient), hObject, NV_TRUE))); } @@ -257,7 +249,9 @@ serverutilGenResourceHandle // LOCK TEST: we should have the API lock here LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); - if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) + pClient = serverutilGetClientUnderLock(hClient); + + if (pClient == NULL) return NV_ERR_INVALID_CLIENT; status = clientGenResourceHandle(staticCast(pClient, RsClient), returnHandle); diff --git a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c index d87c3a3811..23eb740ad0 100644 --- a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c +++ b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c @@ -22,6 +22,8 @@ */ #include "virtualization/common_vgpu_mgr.h" +#include "virtualization/hypervisor/hypervisor.h" + #include "ctrl/ctrl2080/ctrl2080gpu.h" void diff --git a/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c index 4181985648..0a898c46e9 100644 --- a/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c +++ b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c @@ -33,7 +33,7 @@ static HYPERVISOR_OPS _hypervisorOps[OS_HYPERVISOR_UNKNOWN]; -static NV_STATUS _hypervisorDetection_HVM(OBJHYPERVISOR *, OBJOS *, NvU32 *); +static NV_STATUS _hypervisorDetection_HVM(OBJHYPERVISOR *, OBJOS *); static NvBool _hypervisorCheckVirtualPcieP2PApproval(OBJHYPERVISOR *, NvU32); // Because M$ compiler doesn't support C99 we have to initialize @@ -63,8 +63,6 @@ NV_STATUS hypervisorConstruct_IMPL(OBJHYPERVISOR *pHypervisor) return NV_OK; } -static NvU32 _leaf; - NvBool hypervisorPcieP2pDetection_IMPL ( OBJHYPERVISOR *pHypervisor, @@ -91,7 +89,7 @@ NV_STATUS hypervisorDetection_IMPL if (hypervisorIsVgxHyper()) goto found_one; - if ((rmStatus = _hypervisorDetection_HVM(pHypervisor, pOS, &_leaf)) != NV_OK) + if ((rmStatus = _hypervisorDetection_HVM(pHypervisor, pOS)) != NV_OK) return rmStatus; if ((rmStatus = _hypervisorOps[pHypervisor->type].hypervisorPostDetection(pOS, &pHypervisor->bIsHVMGuest)) != NV_OK) @@ -123,15 +121,13 @@ NV_STATUS hypervisorDetection_IMPL static NV_STATUS _hypervisorDetection_HVM ( OBJHYPERVISOR *pHypervisor, - OBJOS *pOS, - NvU32 *pLeaf + OBJOS *pOS ) { +#if defined(NVCPU_X86_64) NvU32 i = 0, base, eax = 0; NvU32 vmmSignature[3]; - - NV_ASSERT_OR_RETURN(pLeaf, NV_ERR_INVALID_ARGUMENT); - *pLeaf = 0; + NvU32 leaf = 0; for (base = 0x40000000; base < 0x40001000; base += 0x100) { @@ -153,16 +149,103 @@ static NV_STATUS _hypervisorDetection_HVM if (!portMemCmp(_hypervisorOps[i].hypervisorSig, vmmSignature, sizeof(vmmSignature))) { - if (base > *pLeaf) + if (base > leaf) { - *pLeaf = base; + leaf = base; pHypervisor->type = i; } } } } - return *pLeaf ? NV_OK : NV_ERR_NOT_SUPPORTED; + return leaf ? NV_OK : NV_ERR_NOT_SUPPORTED; +#elif defined(NVCPU_AARCH64) + void *pSmbiosTable = NULL; + NvU8 *tableStart = NULL; + NvU64 i = 0; + NvU64 totalLength = 0; + NvU64 numSubTypes; + NvU32 version; + NvBool bIsVM = NV_FALSE; + + if (osGetSmbiosTable(&pSmbiosTable, &totalLength, &numSubTypes, &version) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, "SMBIOS is NOT supported!\n"); + return NV_ERR_NOT_SUPPORTED; + } + + NV_ASSERT_OR_RETURN(pSmbiosTable, NV_ERR_INVALID_POINTER); + tableStart = (NvU8 *)pSmbiosTable; + + // Traverse SMBIOS table to locate 'BIOS Information (Type 0)' struct + while (i < totalLength) + { + NvU8 *structStart; + NvU8 structType; + NvU8 structLength; + + // SMBIOS Spec: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.4.0.pdf + // Each SMBIOS struct has a formatted section followed by optional strings section. + // type of struct is at byte offset 0. + // length of formatted section is at byte offset 1. + // optional strings section starts at byte offset structLength. + // struct end is marked with two null bytes. + + if ((i + 2ULL) <= totalLength) + { + structStart = &tableStart[i]; + structType = structStart[0]; + structLength = structStart[1]; + } + else + { + break; + } + + if (structType == 0x7f) + { + // 'End-of-Table (Type 127)' struct reached, stop traversing further. + break; + } + + // traverse formatted section + i += structLength; + + // traverse optional strings section until start of two null bytes + while (((i + 2ULL) <= totalLength) && (tableStart[i] || tableStart[i + 1])) + i++; + + // ensure that entire struct (including last two null bytes) is within tableLength + if ((i + 2ULL) <= totalLength) + { + if (structType == 0x0) + { + // found 'BIOS Information (Type 0)' struct. + // check Bit 4 of 'BIOS Characteristics Extention Byte 2' - offset 0x13 + if ((structLength > 0x13) && (structStart[0x13] & NVBIT(4))) + { + bIsVM = NV_TRUE; + } + break; + } + } + + // traverse over two null bytes at end of a struct + i += 2; + } + + osPutSmbiosTable(pSmbiosTable, totalLength); + + if (bIsVM) + { + pHypervisor->type = OS_HYPERVISOR_KVM; + return NV_OK; + } + + return NV_ERR_NOT_SUPPORTED; +#else + return NV_ERR_NOT_SUPPORTED; +#endif } HYPERVISOR_TYPE hypervisorGetHypervisorType_IMPL(OBJHYPERVISOR *pHypervisor) @@ -172,6 +255,12 @@ HYPERVISOR_TYPE hypervisorGetHypervisorType_IMPL(OBJHYPERVISOR *pHypervisor) return OS_HYPERVISOR_UNKNOWN; } +void hypervisorSetHypervisorType_IMPL(OBJHYPERVISOR *pHypervisor, HYPERVISOR_TYPE type) +{ + pHypervisor->type = type; + pHypervisor->bDetected = type != OS_HYPERVISOR_UNKNOWN; +} + static NvBool _hypervisorCheckVirtualPcieP2PApproval ( OBJHYPERVISOR *pHypervisor, diff --git a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c index 446775720d..05e4c8f3cf 100644 --- a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c +++ b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -179,30 +179,19 @@ kernelhostvgpudeviceapiCtrlCmdEventSetNotification_IMPL } NV_STATUS -kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL -( - KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, - NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pSetSriovStateParams -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS -kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL +kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL ( KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, - NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams ) { return NV_ERR_NOT_SUPPORTED; } NV_STATUS -kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL +kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL ( - KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, - NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi ) { return NV_ERR_NOT_SUPPORTED; diff --git a/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c index 4d61456105..429ca15211 100644 --- a/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c +++ b/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -111,14 +111,14 @@ kvgpumgrDetachGpu(NvU32 gpuPciId) /* * @brief Sets Guest(VM) ID for the requested hostvgpudevice * - * @param pParams NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS Pointer + * @param pParams SET_GUEST_ID_PARAMS Pointer * @param pKernelHostVgpuDevice Device for which Vm ID need to be set * @param pGpu OBJGPU pointer * * @return NV_STATUS */ NV_STATUS -kvgpumgrRegisterGuestId(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams, +kvgpumgrRegisterGuestId(SET_GUEST_ID_PARAMS *pParams, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; @@ -318,3 +318,14 @@ kvgpumgrGetConfigEventInfoFromDb(NvHandle hClient, { return NV_ERR_OBJECT_NOT_FOUND; } + +NV_STATUS +kvgpuMgrRestoreSmcExecPart +( + OBJGPU *pGpu, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance +) +{ + return NV_ERR_NOT_SUPPORTED; +} diff --git a/src/nvidia/src/lib/base_utils.c b/src/nvidia/src/lib/base_utils.c index 27c4158f16..5af3a9d414 100644 --- a/src/nvidia/src/lib/base_utils.c +++ b/src/nvidia/src/lib/base_utils.c @@ -336,7 +336,7 @@ char * nvU32ToStr(NvU32 value, char *string, NvU32 radix) * @param[in] value to be converted to string * @param[in] targetStrLen Denoted the converted string Length * @param[out] *string is the char array to be have the converted data - * + * * @return the converted string */ char * @@ -356,9 +356,9 @@ nvU64ToStr { rem = value % base; value = value / base; - tempBuffer[inx] = (rem > 9)? (rem - 10) + 'a' : rem + '0'; + tempBuffer[inx] = (rem > 9)? (rem - 10) + 'a' : rem + '0'; } - + for(inx = 0; inx < targetStrLen; inx++) { string[inx] = tempBuffer[targetStrLen - inx - 1]; diff --git a/src/nvidia/src/lib/ref_count.c b/src/nvidia/src/lib/ref_count.c index ab42899b9e..de41892c4e 100644 --- a/src/nvidia/src/lib/ref_count.c +++ b/src/nvidia/src/lib/ref_count.c @@ -415,7 +415,7 @@ refcntReset_IMPL * PDB property enabled * @param[in] bSuppressStateChange - Indicates whether the state change (and * its callback) should be suppressed - * @param[out] bNodeIsRemoved - Whether the requester is removed from + * @param[out] bNodeIsRemoved - Whether the requester is removed from * requesterTree. * * @returns NV_OK if the requester's references are successfully removed from diff --git a/src/nvidia/src/libraries/containers/btree/btree.c b/src/nvidia/src/libraries/containers/btree/btree.c index 6dd9de8147..a7b8c68a4f 100644 --- a/src/nvidia/src/libraries/containers/btree/btree.c +++ b/src/nvidia/src/libraries/containers/btree/btree.c @@ -114,7 +114,7 @@ _btreeNodeValidate ) { NV_STATUS status; - + status = NV_OK; if (pNode == NULL) { @@ -157,7 +157,7 @@ _btreeNodeValidate } } - // red black tree property: Every red node that is not a leaf has only black children. + // red black tree property: Every red node that is not a leaf has only black children. if (pNode->isRed) { if (pNode->left && pNode->left->isRed) @@ -182,7 +182,7 @@ _btreeBranchValidate NODE *pNode ) { - NV_STATUS status; + NV_STATUS status; status = NV_OK; if (pNode) { @@ -206,7 +206,7 @@ _btreeTreeValidate ) { NV_STATUS status; - + status = NV_OK; if (pRoot) { @@ -227,7 +227,7 @@ _btreeTreeValidate } return (status); } - + #else // // Validate nothing. @@ -460,7 +460,7 @@ static void _deleteFixup(NODE **pRoot, NODE *parentOfX, NODE *x) { NV_ASSERT (!(x == NULL && parentOfX == NULL)); // NULL nodes are sentinel nodes. If we delete a sentinel node (x==NULL) it - // must have a parent node (or be the root). Hence, parentOfX == NULL with + // must have a parent node (or be the root). Hence, parentOfX == NULL with // x==NULL is never possible (tree invariant) if ((parentOfX != NULL) && (x == parentOfX->left)) @@ -755,7 +755,7 @@ btreeEnumNext PNODE *pNode, PNODE root ) -{ +{ // no nodes ? NODE *current = NULL; VALIDATE_NODE(*pNode); @@ -821,7 +821,7 @@ btreeDestroyData // // Frees all the nodes and data stored in them. -// Don't use if the nodes were allocated within other structs +// Don't use if the nodes were allocated within other structs // (e.g. if the Node is embedded within the struct pointed by its "Data" field) // NV_STATUS diff --git a/src/nvidia/src/libraries/containers/eheap/eheap_old.c b/src/nvidia/src/libraries/containers/eheap/eheap_old.c index 4a03dc639b..351aba6489 100644 --- a/src/nvidia/src/libraries/containers/eheap/eheap_old.c +++ b/src/nvidia/src/libraries/containers/eheap/eheap_old.c @@ -376,19 +376,19 @@ eheapAlloc if (blockFree == NULL) goto failed; - do + do { - desiredOffset = NV_ALIGN_DOWN(blockFree->begin, pHeap->ownerGranularity) + offsetAlign; + desiredOffset = NV_ALIGN_DOWN(blockFree->begin, pHeap->ownerGranularity) + offsetAlign; while (desiredOffset + allocSize - 1 <= blockFree->end) { desiredOffsetLo = NV_ALIGN_DOWN(desiredOffset, pHeap->ownerGranularity); - desiredOffsetHi = (((desiredOffset % pHeap->ownerGranularity) == 0) ? + desiredOffsetHi = (((desiredOffset % pHeap->ownerGranularity) == 0) ? NV_ALIGN_UP((desiredOffset + 1), pHeap->ownerGranularity) : NV_ALIGN_UP(desiredOffset, pHeap->ownerGranularity)); if ((desiredOffset >= blockFree->begin) && - ((desiredOffsetLo >= blockFree->begin) && + ((desiredOffsetLo >= blockFree->begin) && (desiredOffsetHi <= blockFree->end))) { if (_eheapCheckOwnership(pHeap, pIsolationID, desiredOffset, @@ -403,8 +403,8 @@ eheapAlloc desiredOffset += pHeap->ownerGranularity; } - - blockFree = blockFree->nextFree; + + blockFree = blockFree->nextFree; } while (blockFree != pHeap->pFreeBlockList); @@ -456,7 +456,7 @@ eheapAlloc desiredOffset + allocSize - 1, blockFree, checker)) { break; - } + } } // we have a match, now remove it from the pool @@ -571,7 +571,7 @@ eheapAlloc allocLo = allocAl; allocHi = allocAl + allocSize - 1; - if (_eheapCheckOwnership(pHeap, pIsolationID, allocLo, allocHi, blockFree, checker)) + if (_eheapCheckOwnership(pHeap, pIsolationID, allocLo, allocHi, blockFree, checker)) { goto alloc_done; } @@ -1075,8 +1075,8 @@ eheapInfo { NV_RANGE range = rangeMake(pHeap->rangeLo, pHeap->rangeHi); - if (pBytesFree) - { + if (pBytesFree) + { *pBytesFree = pHeap->free; } if (pBytesTotal) @@ -1100,14 +1100,14 @@ eheapInfoForRange PEMEMBLOCK blockFirstFree, blockFree; NvU64 freeBlockSize = 0; NvU64 largestFreeOffset = 0; - NvU64 largestFreeSize = 0; + NvU64 largestFreeSize = 0; NvU32 numFreeBlocks = 0; if (pUsableBytesFree) *pUsableBytesFree = 0; blockFirstFree = pHeap->pFreeBlockList; - if (blockFirstFree) + if (blockFirstFree) { NV_ASSERT( range.lo <= range.hi ); @@ -1385,7 +1385,7 @@ _eheapCheckOwnership { EMEMBLOCK *pTmpBlock; NvU64 checkLo = NV_ALIGN_DOWN(allocLo, pHeap->ownerGranularity); - NvU64 checkHi = (((allocHi % pHeap->ownerGranularity) == 0) ? + NvU64 checkHi = (((allocHi % pHeap->ownerGranularity) == 0) ? NV_ALIGN_UP((allocHi + 1), pHeap->ownerGranularity) : NV_ALIGN_UP(allocHi, pHeap->ownerGranularity)); NvU64 check; @@ -1407,7 +1407,7 @@ _eheapCheckOwnership if (!pComparator(pIsolationID, pTmpBlock->pData)) { return NV_FALSE; - } + } } check = pTmpBlock->end + 1; diff --git a/src/nvidia/src/libraries/containers/list.c b/src/nvidia/src/libraries/containers/list.c index 6471471235..250f59e72a 100644 --- a/src/nvidia/src/libraries/containers/list.c +++ b/src/nvidia/src/libraries/containers/list.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -122,7 +122,12 @@ void *listPrependNew_IMPL(NonIntrusiveList *pList) return listInsertNew_IMPL(pList, listHead_IMPL(&(pList->base))); } -void *listInsertValue_IMPL(NonIntrusiveList *pList, void *pNext, void *pValue) +void *listInsertValue_IMPL +( + NonIntrusiveList *pList, + void *pNext, + const void *pValue +) { void *pCurrent; @@ -135,12 +140,12 @@ void *listInsertValue_IMPL(NonIntrusiveList *pList, void *pNext, void *pValue) return portMemCopy(pCurrent, pList->valueSize, pValue, pList->valueSize); } -void *listAppendValue_IMPL(NonIntrusiveList *pList, void *pValue) +void *listAppendValue_IMPL(NonIntrusiveList *pList, const void *pValue) { return listInsertValue_IMPL(pList, NULL, pValue); } -void *listPrependValue_IMPL(NonIntrusiveList *pList, void *pValue) +void *listPrependValue_IMPL(NonIntrusiveList *pList, const void *pValue) { return listInsertValue_IMPL(pList, listHead_IMPL(&(pList->base)), pValue); } diff --git a/src/nvidia/src/libraries/containers/map.c b/src/nvidia/src/libraries/containers/map.c index 8c1c92b43e..db339e6250 100644 --- a/src/nvidia/src/libraries/containers/map.c +++ b/src/nvidia/src/libraries/containers/map.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -191,7 +191,7 @@ void *mapInsertValue_IMPL ( NonIntrusiveMap *pMap, NvU64 key, - void *pValue + const void *pValue ) { void *pCurrent; @@ -202,8 +202,7 @@ void *mapInsertValue_IMPL if (NULL == pCurrent) return NULL; - return portMemCopy(pCurrent, pMap->valueSize, pValue, - pMap->valueSize); + return portMemCopy(pCurrent, pMap->valueSize, pValue, pMap->valueSize); } NvBool mapInsertExisting_IMPL diff --git a/src/nvidia/src/libraries/containers/multimap.c b/src/nvidia/src/libraries/containers/multimap.c index a314af6543..ae19915b18 100644 --- a/src/nvidia/src/libraries/containers/multimap.c +++ b/src/nvidia/src/libraries/containers/multimap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -161,9 +161,9 @@ void *multimapInsertItemNew_IMPL void *multimapInsertItemValue_IMPL ( MultimapBase *pBase, - NvU64 submapKey, - NvU64 itemKey, - void *pValue + NvU64 submapKey, + NvU64 itemKey, + const void *pValue ) { void *pLeaf; @@ -299,7 +299,7 @@ void *multimapFirstItem_IMPL(MultimapBase *pBase) void *pItem = mapFindGEQ_IMPL(&pSubmap->base, 0); if (NULL != pItem) return pItem; - + pSubmap = mapNext_IMPL(&pBase->map.base, pSubmap); } @@ -317,7 +317,7 @@ void *multimapLastItem_IMPL(MultimapBase *pBase) void *pItem = mapFindLEQ_IMPL(&pSubmap->base, NV_U64_MAX); if (NULL != pItem) return pItem; - + pSubmap = mapPrev_IMPL(&pBase->map.base, pSubmap); } @@ -335,7 +335,7 @@ MultimapIterBase multimapItemIterRange_IMPL portMemSet(&it, 0, sizeof(it)); it.pMultimap = pBase; - + NV_ASSERT_OR_RETURN(NULL != pBase, it); if (pBase->itemCount == 0 || pFirst == NULL || pLast == NULL) diff --git a/src/nvidia/src/libraries/containers/ringbuf.c b/src/nvidia/src/libraries/containers/ringbuf.c new file mode 100644 index 0000000000..e12c2b9b63 --- /dev/null +++ b/src/nvidia/src/libraries/containers/ringbuf.c @@ -0,0 +1,233 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "containers/ringbuf.h" + +/* + * @brief Initialize ring buffer given pre-allocated array for storage + * + * @param pBase + * Pointer to RingBufBase structure + * @param logSz + * Log base 2 of total size of storage, in # of elements + * @param arr + * Storage for ring buffer + * + * @returns NvBool + * NV_TRUE if unable to construct, NV_FALSE otherwise + */ +NvBool +ringbufConstruct_IMPL +( + RingBufBase *pBase, + NvU64 logSz, + void *arr +) +{ + pBase->head = 0; + pBase->tail = 0; + pBase->logSz = logSz; + pBase->arr = arr; + return pBase->arr == NULL; +} + +/* + * @brief Initialize dynamic ring buffer given a PORT_MEM_ALLOCATOR + * + * @param pBase + * Pointer to RingBufBase structure + * @param logSz + * Log base 2 of total size of storage, in # of elements + * @param eleSz + * Size per element + * @param pAlloc + * Pointer to PORT_MEM_ALLOCATOR + * + * @returns NvBool + * NV_TRUE if unable to construct, NV_FALSE otherwise + */ +NvBool +ringbufConstructDynamic_IMPL +( + RingBufBase *pBase, + NvU64 logSz, + NvU64 eleSz, + PORT_MEM_ALLOCATOR *pAlloc +) +{ + NV_ASSERT_OR_RETURN(logSz < 64, NV_TRUE); + return ringbufConstruct_IMPL(pBase, logSz, PORT_ALLOC(pAlloc, eleSz << logSz)); +} + +/* + * @brief Destroy a dynamic ring buffer + * + * @param pBase + * Pointer to RingBufBase structure + * @param pAlloc + * Pointer to PORT_MEM_ALLOCATOR used to construct Ring Buffer + * + * @returns void + */ +void +ringbufDestruct_IMPL +( + RingBufBase *pBase, + void *pAlloc +) +{ + if ((pAlloc != NULL) && (pBase->arr != NULL)) + { + PORT_FREE((PORT_MEM_ALLOCATOR *) pAlloc, pBase->arr); + pBase->arr = 0; + pBase->logSz = 0; + } +} + +/* + * @brief Peek up to *pMax elements from a ring buffer + * + * @param pBase + * Pointer to RingBufBase structure + * @param eleSz + * Size per element + * @param pMax + * Initially a pointer to number of elements to try to fetch. Returns number of elements actually gotten + * + * @returns void * + * Pointer to the start of the ringbuffer area containing pMax elements, NULL if *pMax == 0, initially or finally + */ +void * +ringbufPeekN_IMPL +( + RingBufBase *pBase, + NvU64 eleSz, + NvU64 *pMax +) +{ + NvU64 mask = RINGBUF_ARRAY_MASK(pBase); + NvU8 *ret = &pBase->arr[(pBase->tail & mask)*eleSz]; + NvU64 max = NV_ALIGN_UP64(pBase->tail + 1llu, RINGBUF_ARRAY_SIZE(pBase)); + max = max > pBase->head ? pBase->head : max; + max -= pBase->tail; + + NV_ASSERT_OR_RETURN(pMax != NULL, NULL); + + max = (max > *pMax) ? *pMax : max; + *pMax = max; + return max == 0 ? NULL : ret; +} + +/* + * @brief Pop up to *pMax elements from a ring buffer + * + * @param pBase + * Pointer to RingBufBase structure + * @param eleSz + * Size per element + * @param pMax + * Initially a pointer to number of elements to try to fetch. Returns number of elements actually gotten + * + * @returns void * + * Pointer to the start of the ringbuffer area containing pMax elements, NULL if *pMax == 0, initially or finally + */ +void * +ringbufPopN_IMPL +( + RingBufBase *pBase, + NvU64 eleSz, + NvU64 *pMax +) +{ + void *ret = ringbufPeekN_IMPL(pBase, eleSz, pMax); + + NV_CHECK_OR_RETURN(LEVEL_INFO, ret != NULL, NULL); + + pBase->tail += *pMax; + return ret; +} + +/* + * @brief Append num elements to the ringbuffer + * + * @param pBase + * Pointer to RingBufBase structure + * @param eleSz + * Size per element + * @param pEle + * Pointer to buffer with num elements + * @param num + * Number of elements + * @param bOverwrite + * Whether to overwrite existing elements in ring buffer + * + * @returns NvBool + * NV_TRUE if success, NV_FALSE otherwise + */ +NvBool +ringbufAppendN_IMPL +( + RingBufBase *pBase, + NvU64 eleSz, + NvU8 *pEle, + NvU64 num, + NvBool bOverwrite +) +{ + if ((RINGBUF_ARRAY_SIZE(pBase) - (bOverwrite ? 0llu : (pBase->head - pBase->tail))) < num) + { + return NV_FALSE; + } + + while (num != 0) + { + NvU64 mask = RINGBUF_ARRAY_MASK(pBase); + NvU8 *pPtr = &pBase->arr[(pBase->head & mask) * eleSz]; + NvU64 max = NV_ALIGN_UP64(pBase->head + 1llu, RINGBUF_ARRAY_SIZE(pBase)); + max -= pBase->head; + max = (max > num) ? num : max; + portMemCopy(pPtr, max * eleSz, pEle, max * eleSz); + pBase->head += max; + pEle = &pEle[max * eleSz]; + num -= max; + } + pBase->tail = (pBase->head - pBase->tail) > (1llu<logSz) ? (pBase->head - (1llu<logSz)) : pBase->tail; + return NV_TRUE; +} + +/* + * @brief Get current size of ring buffer + * + * @param pBase + * Pointer to RingBufBase structure + * + * @returns NvU64 + * Number of elements currently in ring buffer + */ +NvU64 +ringbufCurrentSize_IMPL +( + RingBufBase *pBase +) +{ + return pBase->head - pBase->tail; +} \ No newline at end of file diff --git a/src/nvidia/src/libraries/containers/vector.c b/src/nvidia/src/libraries/containers/vector.c new file mode 100644 index 0000000000..a2ae403f9b --- /dev/null +++ b/src/nvidia/src/libraries/containers/vector.c @@ -0,0 +1,450 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + #include "containers/vector.h" + +CONT_VTABLE_DEFN(Vector, vectIterRange_IMPL, NULL); + +/** + * Check if the given index is contained in vector, that is if + * ((index >= 0) && (index < pVector->size)) + */ +static NvBool _vectIndexCheck(Vector *pVector, NvU32 index); + +/** + * Reallocates container. + * + * Allocate a memory of 'newSize' bytes, then copy 'copySize' bytes from the old + * vector memory to the new one. + */ +static NvBool _vectReallocHelper(Vector *pVector, NvU32 newSize, NvU32 copySize); + +NV_STATUS vectInit_IMPL +( + Vector *pVector, + PORT_MEM_ALLOCATOR *pAllocator, + NvU32 capacity, + NvU32 valueSize +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pAllocator != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECKED_ONLY(pVector->versionNumber++); + + portMemSet(pVector, 0, sizeof(*pVector)); + CONT_VTABLE_INIT(Vector, pVector); + pVector->pAllocator = pAllocator; + pVector->valueSize = valueSize; + pVector->capacity = capacity; + pVector->size = 0; + + if (capacity > 0) + { + pVector->pHead = PORT_ALLOC(pVector->pAllocator, + capacity * pVector->valueSize); + if (NULL == pVector->pHead) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pVector->pHead, 0, capacity * pVector->valueSize); + } + return NV_OK; +} + +void vectDestroy_IMPL(Vector *pVector) +{ + NV_ASSERT_OR_RETURN_VOID(pVector != NULL); + NV_CHECKED_ONLY(pVector->versionNumber++); + + PORT_FREE(pVector->pAllocator, pVector->pHead); + pVector->pHead = NULL; + pVector->capacity = 0; + pVector->size = 0; +} + +void *vectAt_IMPL +( + Vector *pVector, + NvU32 index +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, NULL); + if ((pVector->size == 0) || !_vectIndexCheck(pVector, index)) + { + return NULL; + } + return (void *)((NvU8 *)pVector->pHead + index * pVector->valueSize); +} + +NvU32 vectCapacity_IMPL +( + Vector *pVector +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, 0); + return pVector->capacity; +} + +NvU32 vectCount_IMPL +( + Vector *pVector +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, 0); + return pVector->size; +} + +NvBool vectIsEmpty_IMPL +( + Vector *pVector +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, 0); + + return pVector->size == 0; +} + +NV_STATUS vectTrim_IMPL +( + Vector *pVector, + NvU32 n +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECKED_ONLY(pVector->versionNumber++); + + if (n > pVector->capacity) + { + return NV_OK; + } + + if (n < pVector->size) + { + n = pVector->size; + } + + if (!_vectReallocHelper(pVector, + n * pVector->valueSize, + pVector->size * pVector->valueSize)) + { + return NV_ERR_NO_MEMORY; + } + return NV_OK; +} + +NV_STATUS vectReserve_IMPL +( + Vector *pVector, + NvU32 n +) +{ + NV_ASSERT_OR_RETURN(pVector != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(n > 0, NV_ERR_INVALID_ARGUMENT); + NV_CHECKED_ONLY(pVector->versionNumber++); + + if (n > pVector->capacity) + { + if (!_vectReallocHelper(pVector, + n * pVector->valueSize, + pVector->size * pVector->valueSize)) + { + return NV_ERR_NO_MEMORY; + } + } + return NV_OK; +} + +void *vectInsert_IMPL +( + Vector *pVector, + NvU32 index, + const void *pData +) +{ + void *dst; + void *src; + NvU32 i; + NV_ASSERT_OR_RETURN(pVector != NULL, NULL); + NV_CHECKED_ONLY(pVector->versionNumber++); + if (pVector->size != index) + { + NV_ASSERT_OR_RETURN(_vectIndexCheck(pVector, index), NULL); + } + if (pVector->size + 1 > pVector->capacity) + { + // resize the container by the factor of 2, newcapacity = capacity * 2 + NvU32 newCapacity = pVector->capacity == 0 ? 10 : pVector->capacity * 2; + + if (!_vectReallocHelper(pVector, + newCapacity * pVector->valueSize, + pVector->size * pVector->valueSize)) + return NULL; + } + + for (i = pVector->size; i > index; i--) + { + dst = (void *)((NvU8 *)pVector->pHead + i * pVector->valueSize); + src = (void *)((NvU8 *)pVector->pHead + (i - 1) * pVector->valueSize); + portMemCopy(dst, pVector->valueSize, src, pVector->valueSize); + } + pVector->size++; + dst = (void *)((NvU8 *)pVector->pHead + index * pVector->valueSize); + portMemCopy(dst, pVector->valueSize, pData, pVector->valueSize); + + return dst; +} + +void vectRemove_IMPL +( + Vector *pVector, + NvU32 index +) +{ + void *src; + void *dst; + NvU32 i; + NV_ASSERT_OR_RETURN_VOID(pVector != NULL); + NV_CHECKED_ONLY(pVector->versionNumber++); + NV_ASSERT_OR_RETURN_VOID(_vectIndexCheck(pVector, index)); + + for (i = index; i < pVector->size - 1; i++) + { + dst = (void *)((NvU8 *)pVector->pHead + i * pVector->valueSize); + src = (void *)((NvU8 *)pVector->pHead + (i + 1) * pVector->valueSize); + portMemCopy(dst, pVector->valueSize, src, pVector->valueSize); + } + + pVector->size--; +} + +void *vectAppend_IMPL +( + Vector *pVector, + const void *pData +) +{ + return vectInsert_IMPL(pVector, pVector->size, pData); +} + +void *vectPrepend_IMPL +( + Vector *pVector, + const void *pData +) +{ + return vectInsert_IMPL(pVector, 0, pData); +} + +VectorIterBase vectIterRange_IMPL +( + Vector *pVector, + void *pFirst, + void *pLast +) +{ + VectorIterBase it; + NvU32 first = ~0U; + NvU32 last = ~0U; + NV_ASSERT(pVector != NULL); + + if (pFirst != NULL) + { + first = (NvU32)(((NvU8 *)pFirst - (NvU8 *)pVector->pHead) / + pVector->valueSize); + } + if (pLast != NULL) + { + last = (NvU32)(((NvU8 *)pLast - (NvU8 *)pVector->pHead) / + pVector->valueSize); + } + + NV_CHECKED_ONLY(it.versionNumber = pVector->versionNumber); + if ((pVector->size == 0) || (pFirst == NULL) || (first >= pVector->size) || + (pLast == NULL) || (last >= pVector->size)) + { + it.pVector = pVector; + it.nextIndex = -1; + it.prevIndex = -1; + it.firstIndex = -1; + it.lastIndex = -1; + it.bForward = NV_TRUE; + it.pValue = NULL; + return it; + } + it.pVector = pVector; + it.nextIndex = first; + it.prevIndex = last; + it.firstIndex = first; + it.lastIndex = last; + it.bForward = (first <= last); + it.pValue = NULL; + return it; +} + +NvBool vectIterNext_IMPL +( + VectorIterBase *pIter, + void **ppValue +) +{ + NV_ASSERT_OR_RETURN(pIter != NULL, NV_FALSE); + NV_ASSERT_OR_RETURN(ppValue != NULL, NV_FALSE); + + if (pIter->nextIndex == -1) + { + return NV_FALSE; + } + + NV_ASSERT_CHECKED(pIter->versionNumber == pIter->pVector->versionNumber); + + *ppValue = (void *)((NvU8 *)pIter->pVector->pHead + + pIter->nextIndex * pIter->pVector->valueSize); + + pIter->prevIndex = pIter->bForward ? pIter->nextIndex - 1 : + pIter->nextIndex + 1; + + if (pIter->nextIndex == pIter->lastIndex) + { + pIter->nextIndex = -1; + } + else + { + pIter->nextIndex = pIter->bForward ? pIter->nextIndex + 1 : + pIter->nextIndex - 1; + } + + return NV_TRUE; +} + +NvBool vectIterPrev_IMPL +( + VectorIterBase *pIter, + void **ppValue +) +{ + NV_ASSERT_OR_RETURN(pIter != NULL, NV_FALSE); + NV_ASSERT_OR_RETURN(ppValue != NULL, NV_FALSE); + + if (pIter->prevIndex == -1) + { + return NV_FALSE; + } + + NV_ASSERT_CHECKED(pIter->versionNumber == pIter->pVector->versionNumber); + + *ppValue = (void *)((NvU8 *)pIter->pVector->pHead + + pIter->prevIndex * pIter->pVector->valueSize); + + pIter->nextIndex = pIter->bForward ? pIter->prevIndex + 1 : + pIter->prevIndex - 1; + + if (pIter->prevIndex == pIter->firstIndex) + { + pIter->prevIndex = -1; + } + else + { + pIter->prevIndex = pIter->bForward ? pIter->prevIndex - 1 : + pIter->prevIndex + 1; + } + + return NV_TRUE; +} + +static NvBool _vectReallocHelper +( + Vector *pVector, + NvU32 newSize, + NvU32 copySize +) +{ + void *pNewArray; + void *pCopiedArray; + + NV_ASSERT_OR_RETURN(newSize >= copySize, NV_FALSE); + + pNewArray = PORT_ALLOC(pVector->pAllocator, newSize); + if (pNewArray == NULL && newSize > 0) + { + return NV_FALSE; + } + portMemSet(pNewArray, 0, newSize); + + if (copySize > 0) + { + pCopiedArray = portMemCopy(pNewArray, newSize, + pVector->pHead, copySize); + if (NULL == pCopiedArray) + { + NV_ASSERT(pCopiedArray); + PORT_FREE(pVector->pAllocator, pNewArray); + return NV_FALSE; + } + + PORT_FREE(pVector->pAllocator, pVector->pHead); + pNewArray = pCopiedArray; + } + + pVector->pHead = pNewArray; + pVector->capacity = newSize / pVector->valueSize; + pVector->size = copySize / pVector->valueSize; + + return NV_TRUE; +} + +static NvBool _vectIndexCheck +( + Vector *pVector, + NvU32 index +) +{ + void *pActualOffset, *pLastElem; + + if (pVector->size == 0) + { + return NV_FALSE; + } + + pActualOffset = (void *)((NvU8 *)pVector->pHead + + index * pVector->valueSize); + + pLastElem = (void *)((NvU8 *)pVector->pHead + + (pVector->size - 1) * pVector->valueSize); + + return ((void *)pVector->pHead <= pActualOffset && + pActualOffset <= (void *)pLastElem); +} + +NvBool vectIsValid_IMPL(void *pVect) +{ +#if NV_TYPEOF_SUPPORTED + return NV_TRUE; +#else + if (CONT_VTABLE_VALID((Vector*)pVect)) + return NV_TRUE; + + NV_ASSERT_FAILED("vtable not valid!"); + CONT_VTABLE_INIT(Vector, (Vector*)pVect); + return NV_FALSE; +#endif +} diff --git a/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c b/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c index 45d776fc5f..0876ba2a94 100644 --- a/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c +++ b/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c @@ -26,7 +26,7 @@ // // This file contains generic event buffer producer implementation for adding variable length data -// +// // Data format: // // Event Record buffer holds fixed size records @@ -112,7 +112,7 @@ eventBufferUpdateRecordBufferGet(EVENT_BUFFER_PRODUCER_INFO *info, NvU32 get) RECORD_BUFFER_INFO* pRecordBuffer = &info->recordBuffer; pRecordBuffer->pHeader->recordGet = get; - // used for notification + // used for notification _eventBufferUpdateRecordBufferCount(info); // dropCounts get reset on every updateGet call @@ -192,7 +192,7 @@ eventBufferProducerAddEvent } } -NV_EVENT_BUFFER_RECORD* +NV_EVENT_BUFFER_RECORD* _eventBufferGetFreeRecord(EVENT_BUFFER_PRODUCER_INFO *info) { RECORD_BUFFER_INFO* pRecInfo = &info->recordBuffer; diff --git a/src/nvidia/src/libraries/ioaccess/ioaccess.c b/src/nvidia/src/libraries/ioaccess/ioaccess.c index ea16ebe188..33d5bf79d3 100644 --- a/src/nvidia/src/libraries/ioaccess/ioaccess.c +++ b/src/nvidia/src/libraries/ioaccess/ioaccess.c @@ -29,17 +29,17 @@ /*! * Initialize an IO_APERTURE instance. This enables initialization for derived IO_APERTURE instances * that are not allocated via CreateIOAperture. - * + * * @param[in,out] pAperture pointer to IO_APERTURE instance to be initialized. * @param[in] pParentAperture pointer to parent of the new IO_APERTURE. * @param[in] pDevice pointer to IO_DEVICE of the APERTURE. * @param[in] offset offset from the parent APERTURE's baseAddress. * @param[in] length length of the APERTURE. - * + * * @return NV_OK when inputs are valid. */ NV_STATUS -ioaccessInitIOAperture +ioaccessInitIOAperture ( IO_APERTURE *pAperture, IO_APERTURE *pParentAperture, @@ -75,7 +75,7 @@ ioaccessInitIOAperture // Check if the child Aperture strides beyond the parent's boundary. if ((length + offset) > pParentAperture->length) { - NV_PRINTF(LEVEL_WARNING, + NV_PRINTF(LEVEL_WARNING, "Child aperture crosses parent's boundary, length %u offset %u, Parent's length %u\n", length, offset, pParentAperture->length); } diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h new file mode 100644 index 0000000000..096d172853 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h @@ -0,0 +1,87 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef BASE_H +#define BASE_H + +#ifndef LIBSPDM_STDINT_ALT + +#include + +/* LIBSPDM_OPENSSL_STDINT_WORKAROUND */ + +/* This is a workaround for OpenSSL compilation problems when used with + * on Windows platforms built with Visual Studio. Including pulls in + * , which causes the type size_t to be defined. The size_t type + * depends on if _WIN32 or _WIN64 is defined. The default if neither is defined + * is the 32-bit version of size_t. */ + +/* Our OpenSSL compilation requires _WIN32 and _WIN64 to NOT be defined. + * This will force the to use the wrong 32-bit definition of size_t + * if we are compiling as 64-bit. This 32-bit definition then does not agree with + * the 64-bit definition defined in libspdm and generates compile errors. */ + +/* To workaround this issue, LIBSPDM_OPENSSL_STDINT_WORKAROUND was created + * that is only defined for compilation via tha makefile of the OpenSSL library + * portion of libspdm. */ + +/* This will lead to _WIN32 and _WIN64 to be NOT defined when reaching the OpenSSL + * portions of a compilation unit (header files + c file), thus meeting the + * no Win32/Win64 requirement for OpenSSL, but will still be defined when compiling + * the file in the compilation unit (and getting the right size_t). */ + +/* In the future libspdm intends to use the Windows native compilation flags and defines, + * in place of the UEFI profile / personality. */ + +#ifdef LIBSPDM_OPENSSL_STDINT_WORKAROUND +#undef _WIN32 +#undef _WIN64 +#endif + +#else /* LIBSPDM_STDINT_ALT */ +#include LIBSPDM_STDINT_ALT +#endif /* LIBSPDM_STDINT_ALT */ + +#ifndef LIBSPDM_STDBOOL_ALT +#include +#else +#include LIBSPDM_STDBOOL_ALT +#endif + +#ifndef LIBSPDM_STDDEF_ALT +#include +#else +#include LIBSPDM_STDDEF_ALT +#endif + +/** + * Return the minimum of two operands. + * + * This macro returns the minimal of two operand specified by a and b. + * Both a and b must be the same numerical types, signed or unsigned. + * + * @param a The first operand with any numerical type. + * @param b The second operand. It should be the same any numerical type with a. + * + * @return Minimum of two operands. + * + **/ +#define LIBSPDM_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +/** + * Return the number of elements in an array. + * + * @param array An object of array type. Array is only used as an argument to + * the sizeof operator, therefore Array is never evaluated. The + * caller is responsible for ensuring that Array's type is not + * incomplete; that is, Array must have known constant size. + * + * @return The number of elements in Array. The result has type size_t. + * + **/ +#define LIBSPDM_ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) + +#endif /* BASE_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h new file mode 100644 index 0000000000..4566a3f501 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h @@ -0,0 +1,109 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Defines base cryptographic library APIs. + * The Base Cryptographic Library provides implementations of basic cryptography + * primitives (hash Serials, HMAC, AES, RSA, Diffie-Hellman, Elliptic Curve, etc) for security + * functionality enabling. + **/ + +#ifndef CRYPTLIB_H +#define CRYPTLIB_H + +#include "internal/libspdm_lib_config.h" + +#define LIBSPDM_CRYPTO_NID_NULL 0x0000 + +/* Hash */ +#define LIBSPDM_CRYPTO_NID_SHA256 0x0001 +#define LIBSPDM_CRYPTO_NID_SHA384 0x0002 +#define LIBSPDM_CRYPTO_NID_SHA512 0x0003 +#define LIBSPDM_CRYPTO_NID_SHA3_256 0x0004 +#define LIBSPDM_CRYPTO_NID_SHA3_384 0x0005 +#define LIBSPDM_CRYPTO_NID_SHA3_512 0x0006 +#define LIBSPDM_CRYPTO_NID_SM3_256 0x0007 + +/* Signing */ +#define LIBSPDM_CRYPTO_NID_RSASSA2048 0x0101 +#define LIBSPDM_CRYPTO_NID_RSASSA3072 0x0102 +#define LIBSPDM_CRYPTO_NID_RSASSA4096 0x0103 +#define LIBSPDM_CRYPTO_NID_RSAPSS2048 0x0104 +#define LIBSPDM_CRYPTO_NID_RSAPSS3072 0x0105 +#define LIBSPDM_CRYPTO_NID_RSAPSS4096 0x0106 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P256 0x0107 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P384 0x0108 +#define LIBSPDM_CRYPTO_NID_ECDSA_NIST_P521 0x0109 +#define LIBSPDM_CRYPTO_NID_SM2_DSA_P256 0x010A +#define LIBSPDM_CRYPTO_NID_EDDSA_ED25519 0x010B +#define LIBSPDM_CRYPTO_NID_EDDSA_ED448 0x010C + +/* Key Exchange */ +#define LIBSPDM_CRYPTO_NID_FFDHE2048 0x0201 +#define LIBSPDM_CRYPTO_NID_FFDHE3072 0x0202 +#define LIBSPDM_CRYPTO_NID_FFDHE4096 0x0203 +#define LIBSPDM_CRYPTO_NID_SECP256R1 0x0204 +#define LIBSPDM_CRYPTO_NID_SECP384R1 0x0205 +#define LIBSPDM_CRYPTO_NID_SECP521R1 0x0206 +#define LIBSPDM_CRYPTO_NID_SM2_KEY_EXCHANGE_P256 0x0207 +#define LIBSPDM_CRYPTO_NID_CURVE_X25519 0x0208 +#define LIBSPDM_CRYPTO_NID_CURVE_X448 0x0209 + +/* AEAD */ +#define LIBSPDM_CRYPTO_NID_AES_128_GCM 0x0301 +#define LIBSPDM_CRYPTO_NID_AES_256_GCM 0x0302 +#define LIBSPDM_CRYPTO_NID_CHACHA20_POLY1305 0x0303 +#define LIBSPDM_CRYPTO_NID_SM4_128_GCM 0x0304 + +/* X.509 v3 key usage extension flags. */ +#define LIBSPDM_CRYPTO_X509_KU_DIGITAL_SIGNATURE 0x80 /* bit 0 */ +#define LIBSPDM_CRYPTO_X509_KU_NON_REPUDIATION 0x40 /* bit 1 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_ENCIPHERMENT 0x20 /* bit 2 */ +#define LIBSPDM_CRYPTO_X509_KU_DATA_ENCIPHERMENT 0x10 /* bit 3 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_AGREEMENT 0x08 /* bit 4 */ +#define LIBSPDM_CRYPTO_X509_KU_KEY_CERT_SIGN 0x04 /* bit 5 */ +#define LIBSPDM_CRYPTO_X509_KU_CRL_SIGN 0x02 /* bit 6 */ +#define LIBSPDM_CRYPTO_X509_KU_ENCIPHER_ONLY 0x01 /* bit 7 */ +#define LIBSPDM_CRYPTO_X509_KU_DECIPHER_ONLY 0x8000 /* bit 8 */ + +/* These constants comply with the DER encoded ASN.1 type tags. */ +#define LIBSPDM_CRYPTO_ASN1_BOOLEAN 0x01 +#define LIBSPDM_CRYPTO_ASN1_INTEGER 0x02 +#define LIBSPDM_CRYPTO_ASN1_BIT_STRING 0x03 +#define LIBSPDM_CRYPTO_ASN1_OCTET_STRING 0x04 +#define LIBSPDM_CRYPTO_ASN1_NULL 0x05 +#define LIBSPDM_CRYPTO_ASN1_OID 0x06 +#define LIBSPDM_CRYPTO_ASN1_UTF8_STRING 0x0C +#define LIBSPDM_CRYPTO_ASN1_SEQUENCE 0x10 +#define LIBSPDM_CRYPTO_ASN1_SET 0x11 +#define LIBSPDM_CRYPTO_ASN1_PRINTABLE_STRING 0x13 +#define LIBSPDM_CRYPTO_ASN1_T61_STRING 0x14 +#define LIBSPDM_CRYPTO_ASN1_IA5_STRING 0x16 +#define LIBSPDM_CRYPTO_ASN1_UTC_TIME 0x17 +#define LIBSPDM_CRYPTO_ASN1_GENERALIZED_TIME 0x18 +#define LIBSPDM_CRYPTO_ASN1_UNIVERSAL_STRING 0x1C +#define LIBSPDM_CRYPTO_ASN1_BMP_STRING 0x1E +#define LIBSPDM_CRYPTO_ASN1_PRIMITIVE 0x00 +#define LIBSPDM_CRYPTO_ASN1_CONSTRUCTED 0x20 +#define LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC 0x80 + +#define LIBSPDM_CRYPTO_ASN1_TAG_CLASS_MASK 0xC0 +#define LIBSPDM_CRYPTO_ASN1_TAG_PC_MASK 0x20 +#define LIBSPDM_CRYPTO_ASN1_TAG_VALUE_MASK 0x1F + +#include "hal/library/cryptlib/cryptlib_hash.h" +#include "hal/library/cryptlib/cryptlib_mac.h" +#include "hal/library/cryptlib/cryptlib_aead.h" +#include "hal/library/cryptlib/cryptlib_cert.h" +#include "hal/library/cryptlib/cryptlib_hkdf.h" +#include "hal/library/cryptlib/cryptlib_rsa.h" +#include "hal/library/cryptlib/cryptlib_ec.h" +#include "hal/library/cryptlib/cryptlib_dh.h" +#include "hal/library/cryptlib/cryptlib_ecd.h" +#include "hal/library/cryptlib/cryptlib_sm2.h" +#include "hal/library/cryptlib/cryptlib_rng.h" + +#endif /* CRYPTLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h new file mode 100644 index 0000000000..3d8f64535b --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h @@ -0,0 +1,211 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_AEAD_H +#define CRYPTLIB_AEAD_H + +/*===================================================================================== + * Authenticated Encryption with Associated data (AEAD) Cryptography Primitives + *===================================================================================== + */ + +#if LIBSPDM_AEAD_GCM_SUPPORT +/** + * Performs AEAD AES-GCM authenticated encryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16 or 32, otherwise false is returned. + * tag_size must be 12, 13, 14, 15, 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD AES-GCM authenticated encryption succeeded. + * @retval false AEAD AES-GCM authenticated encryption failed. + **/ +extern bool libspdm_aead_aes_gcm_encrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD AES-GCM authenticated decryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16 or 32, otherwise false is returned. + * tag_size must be 12, 13, 14, 15, 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD AES-GCM authenticated decryption succeeded. + * @retval false AEAD AES-GCM authenticated decryption failed. + **/ +extern bool libspdm_aead_aes_gcm_decrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_GCM_SUPPORT */ + +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT +/** + * Performs AEAD ChaCha20Poly1305 authenticated encryption on a data buffer and additional + * authenticated data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 32, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD ChaCha20Poly1305 authenticated encryption succeeded. + * @retval false AEAD ChaCha20Poly1305 authenticated encryption failed. + **/ +extern bool libspdm_aead_chacha20_poly1305_encrypt( + const uint8_t *key, size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, uint8_t *tag_out, + size_t tag_size, uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD ChaCha20Poly1305 authenticated decryption on a data buffer and additional authenticated data (AAD). + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 32, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD ChaCha20Poly1305 authenticated decryption succeeded. + * @retval false AEAD ChaCha20Poly1305 authenticated decryption failed. + * + **/ +extern bool libspdm_aead_chacha20_poly1305_decrypt( + const uint8_t *key, size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, const uint8_t *tag, + size_t tag_size, uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT */ + +#if LIBSPDM_AEAD_SM4_SUPPORT +/** + * Performs AEAD SM4-GCM authenticated encryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD SM4-GCM authenticated encryption succeeded. + * @retval false AEAD SM4-GCM authenticated encryption failed. + **/ +extern bool libspdm_aead_sm4_gcm_encrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); + +/** + * Performs AEAD SM4-GCM authenticated decryption on a data buffer and additional authenticated + * data. + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16, otherwise false is returned. + * tag_size must be 16, otherwise false is returned. + * + * If data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size Size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size Size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data. + * @param[in] a_data_size Size of the additional authenticated data in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size Size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size Size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD SM4-GCM authenticated decryption succeeded. + * @retval false AEAD SM4-GCM authenticated decryption failed. + **/ +extern bool libspdm_aead_sm4_gcm_decrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size); +#endif /* LIBSPDM_AEAD_SM4_SUPPORT */ + +#endif /* CRYPTLIB_AEAD_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h new file mode 100644 index 0000000000..0f0b5bca08 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h @@ -0,0 +1,416 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_CERT_H +#define CRYPTLIB_CERT_H + +/** + * Retrieve the tag and length of the tag. + * + * @param ptr The position in the ASN.1 data. + * @param end End of data. + * @param length The variable that will receive the length. + * @param tag The expected tag. + * + * @retval true Get tag successful. + * @retval false Failed to get tag or tag not match. + **/ +extern bool libspdm_asn1_get_tag(uint8_t **ptr, const uint8_t *end, size_t *length, uint32_t tag); + +/** + * Retrieve the subject bytes from one X.509 certificate. + * + * If cert is NULL, then return false. + * If subject_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] cert_subject Pointer to the retrieved certificate subject bytes. + * @param[in, out] subject_size The size in bytes of the cert_subject buffer on input, + * and the size of buffer returned cert_subject on output. + * + * @retval true The certificate subject retrieved successfully. + * @retval false Invalid certificate, or the subject_size is too small for the result. + * The subject_size will be updated with the required size. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_subject_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_subject, + size_t *subject_size); + +/** + * Retrieve the version from one X.509 certificate. + * + * If cert is NULL, then return false. + * If cert_size is 0, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] version Pointer to the retrieved version integer. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_version(const uint8_t *cert, size_t cert_size, size_t *version); + +/** + * Retrieve the serialNumber from one X.509 certificate. + * + * If cert is NULL, then return false. + * If cert_size is 0, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] serial_number Pointer to the retrieved certificate serial_number bytes. + * @param[in, out] serial_number_size The size in bytes of the serial_number buffer on input, + * and the size of buffer returned serial_number on output. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_serial_number(const uint8_t *cert, size_t cert_size, + uint8_t *serial_number, + size_t *serial_number_size); + +/** + * Retrieve the issuer bytes from one X.509 certificate. + * + * If cert is NULL, then return false. + * If issuer_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] cert_issuer Pointer to the retrieved certificate subject bytes. + * @param[in, out] issuer_size The size in bytes of the cert_issuer buffer on input, + * and the size of buffer returned cert_issuer on output. + * + * @retval true The certificate issuer retrieved successfully. + * @retval false Invalid certificate, or the issuer_size is too small for the result. + * The issuer_size will be updated with the required size. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_issuer_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_issuer, + size_t *issuer_size); + +/** + * Retrieve Extension data from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[in] oid Object identifier buffer + * @param[in] oid_size Object identifier buffer size + * @param[out] extension_data Extension bytes. + * @param[in, out] extension_data_size Extension bytes size. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extension_data(const uint8_t *cert, size_t cert_size, + const uint8_t *oid, size_t oid_size, + uint8_t *extension_data, + size_t *extension_data_size); + +/** + * Retrieve the Validity from one X.509 certificate + * + * If cert is NULL, then return false. + * If CertIssuerSize is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] from notBefore Pointer to date_time object. + * @param[in,out] from_size notBefore date_time object size. + * @param[out] to notAfter Pointer to date_time object. + * @param[in,out] to_size notAfter date_time object size. + * + * Note: libspdm_x509_compare_date_time to compare date_time oject + * x509SetDateTime to get a date_time object from a date_time_str + * + * @retval true The certificate Validity retrieved successfully. + * @retval false Invalid certificate, or Validity retrieve failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_validity(const uint8_t *cert, size_t cert_size, + uint8_t *from, size_t *from_size, uint8_t *to, + size_t *to_size); + +/** + * Format a date_time object into DataTime buffer + * + * If date_time_str is NULL, then return false. + * If date_time_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] date_time_str date_time string like YYYYMMDDhhmmssZ + * Ref: https://www.w3.org/TR/NOTE-datetime + * Z stand for UTC time + * @param[out] date_time Pointer to a date_time object. + * @param[in,out] date_time_size date_time object buffer size. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_set_date_time(const char *date_time_str, void *date_time, + size_t *date_time_size); + +/** + * Compare date_time1 object and date_time2 object. + * + * If date_time1 is NULL, then return -2. + * If date_time2 is NULL, then return -2. + * If date_time1 == date_time2, then return 0 + * If date_time1 > date_time2, then return 1 + * If date_time1 < date_time2, then return -1 + * + * @param[in] date_time1 Pointer to a date_time Ojbect + * @param[in] date_time2 Pointer to a date_time Object + * + * @retval 0 If date_time1 == date_time2 + * @retval 1 If date_time1 > date_time2 + * @retval -1 If date_time1 < date_time2 + **/ +extern int32_t libspdm_x509_compare_date_time(const void *date_time1, const void *date_time2); + +/** + * Retrieve the key usage from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] usage Key usage (LIBSPDM_CRYPTO_X509_KU_*) + * + * @retval true The certificate key usage retrieved successfully. + * @retval false Invalid certificate, or usage is NULL + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_get_key_usage(const uint8_t *cert, size_t cert_size, size_t *usage); + +/** + * Retrieve the Extended key usage from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] usage Key usage bytes. + * @param[in, out] usage_size Key usage buffer sizs in bytes. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extended_key_usage(const uint8_t *cert, + size_t cert_size, uint8_t *usage, + size_t *usage_size); + +/** + * Retrieve the basic constraints from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] basic_constraints Basic constraints bytes. + * @param[in, out] basic_constraints_size Basic constraints buffer sizs in bytes. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_extended_basic_constraints(const uint8_t *cert, + size_t cert_size, + uint8_t *basic_constraints, + size_t *basic_constraints_size); + +/** + * Verify one X509 certificate was issued by the trusted CA. + * + * If cert is NULL, then return false. + * If ca_cert is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate to be verified. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[in] ca_cert Pointer to the DER-encoded trusted CA certificate. + * @param[in] ca_cert_size Size of the CA Certificate in bytes. + * + * @retval true The certificate was issued by the trusted CA. + * @retval false Invalid certificate or the certificate was not issued by the given + * trusted CA. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_x509_verify_cert(const uint8_t *cert, size_t cert_size, + const uint8_t *ca_cert, size_t ca_cert_size); + +/** + * Verify one X509 certificate was issued by the trusted CA. + * + * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates + * where the first certificate is signed by the Root + * Certificate or is the Root Cerificate itself. and + * subsequent cerificate is signed by the preceding + * cerificate. + * @param[in] cert_chain_length Total length of the certificate chain, in bytes. + * + * @param[in] root_cert Trusted Root Certificate buffer. + * + * @param[in] root_cert_length Trusted Root Certificate buffer length. + * + * @retval true All cerificates were issued by the first certificate in X509Certchain. + * @retval false Invalid certificate or the certificate was not issued by the given + * trusted CA. + **/ +extern bool libspdm_x509_verify_cert_chain(const uint8_t *root_cert, size_t root_cert_length, + const uint8_t *cert_chain, + size_t cert_chain_length); + +/** + * Get one X509 certificate from cert_chain. + * + * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates + * where the first certificate is signed by the Root + * Certificate or is the Root Cerificate itself. and + * subsequent cerificate is signed by the preceding + * cerificate. + * @param[in] cert_chain_length Total length of the certificate chain, in bytes. + * + * @param[in] cert_index Index of certificate. If index is -1 indecate the + * last certificate in cert_chain. + * + * @param[out] cert The certificate at the index of cert_chain. + * @param[out] cert_length The length certificate at the index of cert_chain. + * + * @retval true Success. + * @retval false Failed to get certificate from certificate chain. + **/ +extern bool libspdm_x509_get_cert_from_cert_chain(const uint8_t *cert_chain, + size_t cert_chain_length, + const int32_t cert_index, const uint8_t **cert, + size_t *cert_length); + +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +/** + * Retrieve the RSA public key from one DER-encoded X509 certificate. + * + * If cert is NULL, then return false. + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * RSA public key component. Use libspdm_rsa_free() function to free the + * resource. + * + * @retval true RSA public key was retrieved successfully. + * @retval false Fail to retrieve RSA public key from X509 certificate. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **rsa_context); +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + +#if LIBSPDM_ECDSA_SUPPORT +/** + * Retrieve the EC public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * EC public key component. Use libspdm_ec_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ec_context is NULL, then return false. + * + * @retval true EC public key was retrieved successfully. + * @retval false Fail to retrieve EC public key from X509 certificate. + * + **/ +extern bool libspdm_ec_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ec_context); +#endif /* LIBSPDM_ECDSA_SUPPORT */ + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +/** + * Retrieve the Ed public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * Ed public key component. Use libspdm_ecd_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true Ed public key was retrieved successfully. + * @retval false Fail to retrieve Ed public key from X509 certificate. + * + **/ +extern bool libspdm_ecd_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ecd_context); +#endif /* (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) */ + +#if LIBSPDM_SM2_DSA_SUPPORT +/** + * Retrieve the sm2 public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * sm2 public key component. Use sm2_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If sm2_context is NULL, then return false. + * + * @retval true sm2 public key was retrieved successfully. + * @retval false Fail to retrieve sm2 public key from X509 certificate. + * + **/ +extern bool libspdm_sm2_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **sm2_context); +#endif /* LIBSPDM_SM2_DSA_SUPPORT */ + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * Generate a CSR. + * + * @param[in] hash_nid hash algo for sign + * @param[in] asym_nid asym algo for sign + * + * @param[in] requester_info requester info to gen CSR + * @param[in] requester_info_length The len of requester info + * + * @param[in] context Pointer to asymmetric context + * @param[in] subject_name Subject name: should be break with ',' in the middle + * example: "C=AA,CN=BB" + * + * Subject names should contain a comma-separated list of OID types and values: + * The valid OID type name is in: + * {"CN", "commonName", "C", "countryName", "O", "organizationName","L", + * "OU", "organizationalUnitName", "ST", "stateOrProvinceName", "emailAddress", + * "serialNumber", "postalAddress", "postalCode", "dnQualifier", "title", + * "SN","givenName","GN", "initials", "pseudonym", "generationQualifier", "domainComponent", "DC"}. + * Note: The object of C and countryName should be CSR Supported Country Codes + * + * @param[in] csr_len For input, csr_len is the size of store CSR buffer. + * For output, csr_len is CSR len for DER format + * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. + * For output, csr_pointer is address for stored CSR. + * The csr_pointer address will be changed. + * + * @retval true Success. + * @retval false Failed to gen CSR. + **/ +extern bool libspdm_gen_x509_csr(size_t hash_nid, size_t asym_nid, + uint8_t *requester_info, size_t requester_info_length, + void *context, char *subject_name, + size_t *csr_len, uint8_t **csr_pointer); +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ + +#endif /* CRYPTLIB_CERT_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h new file mode 100644 index 0000000000..779c470153 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h @@ -0,0 +1,98 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_DH_H +#define CRYPTLIB_DH_H + +/*===================================================================================== + * Diffie-Hellman Key Exchange Primitives + *===================================================================================== + */ + +#if LIBSPDM_FFDHE_SUPPORT +/** + * Allocates and initializes one Diffie-Hellman context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + * If the allocations fails, libspdm_dh_new_by_nid() returns NULL. + * If the interface is not supported, libspdm_dh_new_by_nid() returns NULL. + **/ +extern void *libspdm_dh_new_by_nid(size_t nid); + +/** + * Release the specified DH context. + * + * @param[in] dh_context Pointer to the DH context to be released. + **/ +void libspdm_dh_free(void *dh_context); + +/** + * Generates DH public key. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * If dh_context is NULL, then return false. + * If public_key_size is NULL, then return false. + * If public_key_size is large enough but public_key is NULL, then return false. + * If this interface is not supported, then return false. + * + * For FFDHE2048, the public_size is 256. + * For FFDHE3072, the public_size is 384. + * For FFDHE4096, the public_size is 512. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[out] public_key Pointer to the buffer to receive generated public key. + * @param[in, out] public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in + * bytes. + * + * @retval true DH public key generation succeeded. + * @retval false DH public key generation failed. + * @retval false public_key_size is not large enough. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_generate_key(void *dh_context, uint8_t *public_key, size_t *public_key_size); + +/** + * Computes exchanged common key. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * If dh_context is NULL, then return false. + * If peer_public_key is NULL, then return false. + * If key_size is NULL, then return false. + * If key is NULL, then return false. + * If key_size is not large enough, then return false. + * If this interface is not supported, then return false. + * + * For FFDHE2048, the peer_public_size and key_size is 256. + * For FFDHE3072, the peer_public_size and key_size is 384. + * For FFDHE4096, the peer_public_size and key_size is 512. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[in] peer_public_key Pointer to the peer's public key. + * @param[in] peer_public_key_size size of peer's public key in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in, out] key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in + * bytes. + * + * @retval true DH exchanged key generation succeeded. + * @retval false DH exchanged key generation failed. + * @retval false key_size is not large enough. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_compute_key(void *dh_context, const uint8_t *peer_public_key, + size_t peer_public_key_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_FFDHE_SUPPORT */ +#endif /* CRYPTLIB_DH_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h new file mode 100644 index 0000000000..1b42da7037 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h @@ -0,0 +1,162 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_EC_H +#define CRYPTLIB_EC_H + +/*===================================================================================== + * Elliptic Curve Primitives + *=====================================================================================*/ + +#if (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) +/** + * Allocates and Initializes one Elliptic Curve context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Elliptic Curve context that has been initialized. + * If the allocations fails, libspdm_ec_new_by_nid() returns NULL. + **/ +extern void *libspdm_ec_new_by_nid(size_t nid); + +/** + * Release the specified EC context. + * + * @param[in] ec_context Pointer to the EC context to be released. + **/ +extern void libspdm_ec_free(void *ec_context); +#endif /* (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) */ + +#if LIBSPDM_ECDHE_SUPPORT +/** + * Generates EC key and returns EC public key (X, Y). + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * EC context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * If ec_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] ec_context Pointer to the EC context. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true EC public X,Y generation succeeded. + * @retval false EC public X,Y generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_ec_generate_key(void *ec_context, uint8_t *public_key, size_t *public_key_size); + +/** + * Computes exchanged common key. + * + * Given peer's public key (X, Y), this function computes the exchanged common key, + * based on its own context including value of curve parameter and random secret. + * X is the first half of peer_public with size being peer_public_size / 2, + * Y is the second half of peer_public with size being peer_public_size / 2. + * + * If ec_context is NULL, then return false. + * If peer_public is NULL, then return false. + * If peer_public_size is 0, then return false. + * If key is NULL, then return false. + * If key_size is not large enough, then return false. + * + * For P-256, the peer_public_size is 64. first 32-byte is X, second 32-byte is Y. + * The key_size is 32. + * For P-384, the peer_public_size is 96. first 48-byte is X, second 48-byte is Y. + * The key_size is 48. + * For P-521, the peer_public_size is 132. first 66-byte is X, second 66-byte is Y. + * The key_size is 66. + * + * @param[in, out] ec_context Pointer to the EC context. + * @param[in] peer_public Pointer to the peer's public X,Y. + * @param[in] peer_public_size Size of peer's public X,Y in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in, out] key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in bytes. + * + * @retval true EC exchanged key generation succeeded. + * @retval false EC exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +extern bool libspdm_ec_compute_key(void *ec_context, const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_ECDHE_SUPPORT */ + +#if LIBSPDM_ECDSA_SUPPORT +/** + * Carries out the EC-DSA signature. + * + * This function carries out the EC-DSA signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If ec_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * For P-256, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For P-384, the sig_size is 96. first 48-byte is R, second 48-byte is S. + * For P-521, the sig_size is 132. first 66-byte is R, second 66-byte is S. + * + * @param[in] ec_context Pointer to EC context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive EC-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in EC-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_ecdsa_sign(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the EC-DSA signature. + * + * If ec_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * + * For P-256, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For P-384, the sig_size is 96. first 48-byte is R, second 48-byte is S. + * For P-521, the sig_size is 132. first 66-byte is R, second 66-byte is S. + * + * @param[in] ec_context Pointer to EC context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to EC-DSA signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in EC-DSA. + * @retval false Invalid signature or invalid EC context. + **/ +extern bool libspdm_ecdsa_verify(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_ECDSA_SUPPORT */ +#endif /* CRYPTLIB_EC_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h new file mode 100644 index 0000000000..10cbbfb2ce --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h @@ -0,0 +1,100 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_ECD_H +#define CRYPTLIB_ECD_H + +/*===================================================================================== + * Edwards-Curve Primitives + *=====================================================================================*/ + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +/** + * Allocates and Initializes one Edwards-Curve context for subsequent use with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Edwards-Curve context that has been initialized. + * If the allocations fails, libspdm_ecd_new_by_nid() returns NULL. + **/ +extern void *libspdm_ecd_new_by_nid(size_t nid); + +/** + * Release the specified Ed context. + * + * @param[in] ecd_context Pointer to the Ed context to be released. + **/ +extern void libspdm_ecd_free(void *ecd_context); + +/** + * Carries out the Ed-DSA signature. + * + * This function carries out the Ed-DSA signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If ecd_context is NULL, then return false. + * If message is NULL, then return false. + * hash_nid must be NULL. + * If sig_size is large enough but signature is NULL, then return false. + * + * For ed25519, context must be NULL and context_size must be 0. + * For ed448, context must be maximum of 255 octets. + * + * For ed25519, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For ed448, the sig_size is 114. first 57-byte is R, second 57-byte is S. + * + * @param[in] ecd_context Pointer to Ed context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] context The EDDSA signing context. + * @param[in] context_size Size of EDDSA signing context. + * @param[in] message Pointer to octet message to be signed (before hash). + * @param[in] size size of the message in bytes. + * @param[out] signature Pointer to buffer to receive Ed-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in Ed-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_eddsa_sign(const void *ecd_context, size_t hash_nid, + const uint8_t *context, size_t context_size, + const uint8_t *message, size_t size, uint8_t *signature, + size_t *sig_size); + +/** + * Verifies the Ed-DSA signature. + * + * If ecd_context is NULL, then return false. + * If message is NULL, then return false. + * If signature is NULL, then return false. + * hash_nid must be NULL. + * + * For ed25519, context must be NULL and context_size must be 0. + * For ed448, context must be maximum of 255 octets. + * + * For ed25519, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For ed448, the sig_size is 114. first 57-byte is R, second 57-byte is S. + * + * @param[in] ecd_context Pointer to Ed context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] context The EDDSA signing context. + * @param[in] context_size Size of EDDSA signing context. + * @param[in] message Pointer to octet message to be checked (before hash). + * @param[in] size Size of the message in bytes. + * @param[in] signature Pointer to Ed-DSA signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in Ed-DSA. + * @retval false Invalid signature or invalid Ed context. + **/ +extern bool libspdm_eddsa_verify(const void *ecd_context, size_t hash_nid, + const uint8_t *context, size_t context_size, + const uint8_t *message, size_t size, + const uint8_t *signature, size_t sig_size); +#endif /* (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) */ +#endif /* CRYPTLIB_ECD_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h new file mode 100644 index 0000000000..e59c5671c7 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h @@ -0,0 +1,772 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_HASH_H +#define CRYPTLIB_HASH_H + +/* SHA-256 digest size in bytes. */ +#define LIBSPDM_SHA256_DIGEST_SIZE 32 + +/* SHA-384 digest size in bytes. */ +#define LIBSPDM_SHA384_DIGEST_SIZE 48 + +/* SHA-512 digest size in bytes. */ +#define LIBSPDM_SHA512_DIGEST_SIZE 64 + +/* SHA3-256 digest size in bytes. */ +#define LIBSPDM_SHA3_256_DIGEST_SIZE 32 + +/* SHA3-384 digest size in bytes. */ +#define LIBSPDM_SHA3_384_DIGEST_SIZE 48 + +/* SHA3-512 digest size in bytes. */ +#define LIBSPDM_SHA3_512_DIGEST_SIZE 64 + +/* SM3_256 digest size in bytes. */ +#define LIBSPDM_SM3_256_DIGEST_SIZE 32 + +/*===================================================================================== + * One-way cryptographic hash SHA2 primitives. + *===================================================================================== + */ +#if LIBSPDM_SHA256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, sha256_new() returns NULL. * + **/ +extern void *libspdm_sha256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha256_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha256_free(void *sha256_context); + +/** + * Initializes user-supplied memory pointed to by sha256_context as SHA-256 hash context for + * subsequent use. + * + * If sha256_context is NULL, then return false. + * + * @param[out] sha256_context Pointer to SHA-256 context being initialized. + * + * @retval true SHA-256 context initialization succeeded. + * @retval false SHA-256 context initialization failed. + **/ +extern bool libspdm_sha256_init(void *sha256_context); + +/** + * Makes a copy of an existing SHA-256 context. + * + * If sha256_context is NULL, then return false. + * If new_sha256_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha256_context Pointer to SHA-256 context being copied. + * @param[out] new_sha256_context Pointer to new SHA-256 context. + * + * @retval true SHA-256 context copy succeeded. + * @retval false SHA-256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha256_duplicate(const void *sha256_context, void *new_sha256_context); + +/** + * Digests the input data and updates SHA-256 context. + * + * This function performs SHA-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-256 context should be already correctly initialized by libspdm_sha256_init(), and must not + * have been finalized by libspdm_sha256_final(). Behavior with invalid context is undefined. + * + * If sha256_context is NULL, then return false. + * + * @param[in, out] sha256_context Pointer to the SHA-256 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-256 data digest succeeded. + * @retval false SHA-256 data digest failed. + **/ +extern bool libspdm_sha256_update(void *sha256_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-256 digest value. + * + * This function completes SHA-256 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-256 context cannot + * be used again. SHA-256 context should be already correctly initialized by libspdm_sha256_init(), + * and must not have been finalized by libspdm_sha256_final(). Behavior with invalid SHA-256 context + * is undefined. + * + * If sha256_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha256_context Pointer to the SHA-256 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-256 digest + * value (32 bytes). + * + * @retval true SHA-256 digest computation succeeded. + * @retval false SHA-256 digest computation failed. + **/ +extern bool libspdm_sha256_final(void *sha256_context, uint8_t *hash_value); + +/** + * Computes the SHA-256 message digest of an input data buffer. + * + * This function performs the SHA-256 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-256 digest value (32 bytes). + * + * @retval true SHA-256 digest computation succeeded. + * @retval false SHA-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-384 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha384_new() returns NULL. + **/ +extern void *libspdm_sha384_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha384_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha384_free(void *sha384_context); + +/** + * Initializes user-supplied memory pointed to by sha384_context as SHA-384 hash context for + * subsequent use. + * + * If sha384_context is NULL, then return false. + * + * @param[out] sha384_context Pointer to SHA-384 context being initialized. + * + * @retval true SHA-384 context initialization succeeded. + * @retval false SHA-384 context initialization failed. + **/ +extern bool libspdm_sha384_init(void *sha384_context); + +/** + * Makes a copy of an existing SHA-384 context. + * + * If sha384_context is NULL, then return false. + * If new_sha384_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha384_context Pointer to SHA-384 context being copied. + * @param[out] new_sha384_context Pointer to new SHA-384 context. + * + * @retval true SHA-384 context copy succeeded. + * @retval false SHA-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha384_duplicate(const void *sha384_context, void *new_sha384_context); + +/** + * Digests the input data and updates SHA-384 context. + * + * This function performs SHA-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-384 context should be already correctly initialized by libspdm_sha384_init(), and must not + * have been finalized by libspdm_sha384_final(). Behavior with invalid context is undefined. + * + * If sha384_context is NULL, then return false. + * + * @param[in, out] sha384_context Pointer to the SHA-384 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-384 data digest succeeded. + * @retval false SHA-384 data digest failed. + **/ +extern bool libspdm_sha384_update(void *sha384_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-384 digest value. + * + * This function completes SHA-384 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-384 context cannot + * be used again. SHA-384 context should be already correctly initialized by libspdm_sha384_init(), + * and must not have been finalized by libspdm_sha384_final(). Behavior with invalid SHA-384 context + * is undefined. + * + * If sha384_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha384_context Pointer to the SHA-384 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-384 digest + * value (48 bytes). + * + * @retval true SHA-384 digest computation succeeded. + * @retval false SHA-384 digest computation failed. + **/ +extern bool libspdm_sha384_final(void *sha384_context, uint8_t *hash_value); + +/** + * Computes the SHA-384 message digest of an input data buffer. + * + * This function performs the SHA-384 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-384 digest value (48 bytes). + * + * @retval true SHA-384 digest computation succeeded. + * @retval false SHA-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha384_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA-512 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha512_new() returns NULL. + **/ +extern void *libspdm_sha512_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha512_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha512_free(void *sha512_context); + +/** + * Initializes user-supplied memory pointed by sha512_context as SHA-512 hash context for + * subsequent use. + * + * If sha512_context is NULL, then return false. + * + * @param[out] sha512_context Pointer to SHA-512 context being initialized. + * + * @retval true SHA-512 context initialization succeeded. + * @retval false SHA-512 context initialization failed. + **/ +extern bool libspdm_sha512_init(void *sha512_context); + +/** + * Makes a copy of an existing SHA-512 context. + * + * If sha512_context is NULL, then return false. + * If new_sha512_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha512_context Pointer to SHA-512 context being copied. + * @param[out] new_sha512_context Pointer to new SHA-512 context. + * + * @retval true SHA-512 context copy succeeded. + * @retval false SHA-512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha512_duplicate(const void *sha512_context, void *new_sha512_context); + +/** + * Digests the input data and updates SHA-512 context. + * + * This function performs SHA-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-512 context should be already correctly initialized by libspdm_sha512_init(), and must not + * have been finalized by libspdm_sha512_final(). Behavior with invalid context is undefined. + * + * If sha512_context is NULL, then return false. + * + * @param[in, out] sha512_context Pointer to the SHA-512 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA-512 data digest succeeded. + * @retval false SHA-512 data digest failed. + **/ +extern bool libspdm_sha512_update(void *sha512_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA-512 digest value. + * + * This function completes SHA-512 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA-512 context cannot + * be used again. SHA-512 context should be already correctly initialized by libspdm_sha512_init(), + * and must not have been finalized by libspdm_sha512_final(). Behavior with invalid SHA-512 context + * is undefined. + * + * If sha512_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha512_context Pointer to the SHA-512 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-512 digest + * value (64 bytes). + * + * @retval true SHA-512 digest computation succeeded. + * @retval false SHA-512 digest computation failed. + **/ +extern bool libspdm_sha512_final(void *sha512_context, uint8_t *hash_value); + +/** + * Computes the SHA-512 message digest of an input data buffer. + * + * This function performs the SHA-512 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-512 digest value (64 bytes). + * + * @retval true SHA-512 digest computation succeeded. + * @retval false SHA-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha512_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +/*===================================================================================== + * One-way cryptographic hash SHA3 primitives. + *===================================================================================== + */ +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_256_new() returns NULL. + **/ +extern void *libspdm_sha3_256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_256_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_256_free(void *sha3_256_context); + +/** + * Initializes user-supplied memory pointed by sha3_256_context as SHA3-256 hash context for + * subsequent use. + * + * If sha3_256_context is NULL, then return false. + * + * @param[out] sha3_256_context Pointer to SHA3-256 context being initialized. + * + * @retval true SHA3-256 context initialization succeeded. + * @retval false SHA3-256 context initialization failed. + **/ +extern bool libspdm_sha3_256_init(void *sha3_256_context); + +/** + * Makes a copy of an existing SHA3-256 context. + * + * If sha3_256_context is NULL, then return false. + * If new_sha3_256_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_256_context Pointer to SHA3-256 context being copied. + * @param[out] new_sha3_256_context Pointer to new SHA3-256 context. + * + * @retval true SHA3-256 context copy succeeded. + * @retval false SHA3-256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_256_duplicate(const void *sha3_256_context, void *new_sha3_256_context); + +/** + * Digests the input data and updates SHA3-256 context. + * + * This function performs SHA3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-256 context should be already correctly initialized by libspdm_sha3_256_init(), and must not + * have been finalized by libspdm_sha3_256_final(). Behavior with invalid context is undefined. + * + * If sha3_256_context is NULL, then return false. + * + * @param[in, out] sha3_256_context Pointer to the SHA3-256 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true SHA3-256 data digest succeeded. + * @retval false SHA3-256 data digest failed. + **/ +extern bool libspdm_sha3_256_update(void *sha3_256_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-256 digest value. + * + * This function completes SHA3-256 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-512 context cannot + * be used again. SHA3-256 context should be already correctly initialized by + * libspdm_sha3_256_init(), and must not have been finalized by libspdm_sha3_256_final(). + * Behavior with invalid SHA3-256 context is undefined. + * + * If sha3_256_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_256_context Pointer to the SHA3-256 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-256 digest + * value (32 bytes). + * + * @retval true SHA3-256 digest computation succeeded. + * @retval false SHA3-256 digest computation failed. + **/ +extern bool libspdm_sha3_256_final(void *sha3_256_context, uint8_t *hash_value); + +/** + * Computes the SHA3-256 message digest of an input data buffer. + * + * This function performs the SHA3-256 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-256 digest value (32 bytes). + * + * @retval true SHA3-256 digest computation succeeded. + * @retval false SHA3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-384 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_384_new() returns NULL. + **/ +extern void *libspdm_sha3_384_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_384_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_384_free(void *sha3_384_context); + +/** + * Initializes user-supplied memory pointed by sha3_384_context as SHA3-384 hash context for + * subsequent use. + * + * If sha3_384_context is NULL, then return false. + * + * @param[out] sha3_384_context Pointer to SHA3-384 context being initialized. + * + * @retval true SHA3-384 context initialization succeeded. + * @retval false SHA3-384 context initialization failed. + **/ +extern bool libspdm_sha3_384_init(void *sha3_384_context); + +/** + * Makes a copy of an existing SHA3-384 context. + * + * If sha3_384_context is NULL, then return false. + * If new_sha3_384_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_384_context Pointer to SHA3-384 context being copied. + * @param[out] new_sha3_384_context Pointer to new SHA3-384 context. + * + * @retval true SHA3-384 context copy succeeded. + * @retval false SHA3-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_384_duplicate(const void *sha3_384_context, void *new_sha3_384_context); + +/** + * Digests the input data and updates SHA3-384 context. + * + * This function performs SHA3-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-384 context should be already correctly initialized by libspdm_sha3_384_init(), and must not + * have been finalized by libspdm_sha3_384_final(). Behavior with invalid context is undefined. + * + * If sha3_384_context is NULL, then return false. + * + * @param[in, out] sha3_384_context Pointer to the SHA3-384 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA3-384 data digest succeeded. + * @retval false SHA3-384 data digest failed. + **/ +extern bool libspdm_sha3_384_update(void *sha3_384_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-384 digest value. + * + * This function completes SHA3-384 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-384 context cannot + * be used again. SHA3-384 context should be already correctly initialized by + * libspdm_sha3_384_init(), and must not have been finalized by libspdm_sha3_384_final(). + * Behavior with invalid SHA3-384 context is undefined. + * + * If sha3_384_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_384_context Pointer to the SHA3-384 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-384 digest + * value (48 bytes). + * + * @retval true SHA3-384 digest computation succeeded. + * @retval false SHA3-384 digest computation failed. + * + **/ +extern bool libspdm_sha3_384_final(void *sha3_384_context, uint8_t *hash_value); + +/** + * Computes the SHA3-384 message digest of an input data buffer. + * + * This function performs the SHA3-384 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-384 digest value (48 bytes). + * + * @retval true SHA3-384 digest computation succeeded. + * @retval false SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_384_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA3-512 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha3_512_new() returns NULL. + **/ +extern void *libspdm_sha3_512_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha3_512_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sha3_512_free(void *sha3_512_context); + +/** + * Initializes user-supplied memory pointed by sha3_512_context as SHA3-512 hash context for + * subsequent use. + * + * If sha3_512_context is NULL, then return false. + * + * @param[out] sha3_512_context Pointer to SHA3-512 context being initialized. + * + * @retval true SHA3-512 context initialization succeeded. + * @retval false SHA3-512 context initialization failed. + **/ +extern bool libspdm_sha3_512_init(void *sha3_512_context); + +/** + * Makes a copy of an existing SHA3-512 context. + * + * If sha3_512_context is NULL, then return false. + * If new_sha3_512_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha3_512_context Pointer to SHA3-512 context being copied. + * @param[out] new_sha3_512_context Pointer to new SHA3-512 context. + * + * @retval true SHA3-512 context copy succeeded. + * @retval false SHA3-512 context copy failed. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_sha3_512_duplicate(const void *sha3_512_context, void *new_sha3_512_context); + +/** + * Digests the input data and updates SHA3-512 context. + * + * This function performs SHA3-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA3-512 context should be already correctly initialized by libspdm_sha3_512_init(), and must not + * have been finalized by libspdm_sha3_512_final(). Behavior with invalid context is undefined. + * + * If sha3_512_context is NULL, then return false. + * + * @param[in, out] sha3_512_context Pointer to the SHA3-512 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SHA3-512 data digest succeeded. + * @retval false SHA3-512 data digest failed. + **/ +extern bool libspdm_sha3_512_update(void *sha3_512_context, const void *data, size_t data_size); + +/** + * Completes computation of the SHA3-512 digest value. + * + * This function completes SHA3-512 hash computation and populates the digest value into + * the specified memory. After this function has been called, the SHA3-512 context cannot + * be used again. SHA3-512 context should be already correctly initialized by + * libspdm_sha3_512_init(), and must not have been finalized by libspdm_sha3_512_final(). + * Behavior with invalid SHA3-512 context is undefined. + * + * If sha3_512_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha3_512_context Pointer to the SHA3-512 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-512 digest + * value (64 bytes). + * + * @retval true SHA3-512 digest computation succeeded. + * @retval false SHA3-512 digest computation failed. + **/ +extern bool libspdm_sha3_512_final(void *sha3_512_context, uint8_t *hash_value); + +/** + * Computes the SHA3-512 message digest of an input data buffer. + * + * This function performs the SHA3-512 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA3-512 digest value (64 bytes). + * + * @retval true SHA3-512 digest computation succeeded. + * @retval false SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sha3_512_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +/*===================================================================================== + * One-Way Cryptographic hash SM3 Primitives + *===================================================================================== + */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Allocates and initializes one HASH_CTX context for subsequent SM3-256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sm3_256_new() returns NULL. + **/ +extern void *libspdm_sm3_256_new(void); + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sm3_context Pointer to the HASH_CTX context to be released. + **/ +extern void libspdm_sm3_256_free(void *sm3_context); + +/** + * Initializes user-supplied memory pointed by sm3_context as SM3 hash context for + * subsequent use. + * + * If sm3_context is NULL, then return false. + * + * @param[out] sm3_context Pointer to SM3 context being initialized. + * + * @retval true SM3 context initialization succeeded. + * @retval false SM3 context initialization failed. + **/ +extern bool libspdm_sm3_256_init(void *sm3_context); + +/** + * Makes a copy of an existing SM3 context. + * + * If sm3_context is NULL, then return false. + * If new_sm3_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sm3_context Pointer to SM3 context being copied. + * @param[out] new_sm3_context Pointer to new SM3 context. + * + * @retval true SM3 context copy succeeded. + * @retval false SM3 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sm3_256_duplicate(const void *sm3_context, void *new_sm3_context); + +/** + * Digests the input data and updates SM3 context. + * + * This function performs SM3 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SM3 context should be already correctly initialized by sm3_init(), and should not be finalized + * by sm3_final(). Behavior with invalid context is undefined. + * + * If sm3_context is NULL, then return false. + * + * @param[in, out] sm3_context Pointer to the SM3 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true SM3 data digest succeeded. + * @retval false SM3 data digest failed. + **/ +extern bool libspdm_sm3_256_update(void *sm3_context, const void *data, size_t data_size); + +/** + * Completes computation of the SM3 digest value. + * + * This function completes SM3 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the SM3 context cannot + * be used again. SM3 context should be already correctly initialized by sm3_init(), and should not + * be finalized by sm3_final(). Behavior with invalid SM3 context is undefined. + * + * If sm3_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sm3_context Pointer to the SM3 context. + * @param[out] hash_value Pointer to a buffer that receives the SM3 digest value (32 bytes). + * + * @retval true SM3 digest computation succeeded. + * @retval false SM3 digest computation failed. + **/ +extern bool libspdm_sm3_256_final(void *sm3_context, uint8_t *hash_value); + +/** + * Computes the SM3 message digest of an input data buffer. + * + * This function performs the SM3 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SM3 digest value (32 bytes). + * + * @retval true SM3 digest computation succeeded. + * @retval false SM3 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_sm3_256_hash_all(const void *data, size_t data_size, uint8_t *hash_value); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_HASH_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h new file mode 100644 index 0000000000..5ed5ce0c3e --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h @@ -0,0 +1,266 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_HKDF_H +#define CRYPTLIB_HKDF_H + +/*===================================================================================== + * Key Derivation Function Primitives + *=====================================================================================*/ + +#if LIBSPDM_SHA256_SUPPORT +/** + * Derive SHA-256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive prk value. + * @param[in] prk_out_size Size of prk bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Derive SHA384 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha384_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA384 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha384_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Derive SHA512 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha512_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA512 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha512_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Derive SHA3_256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Derive SHA3_384 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_384_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_384 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_384_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Derive SHA3_512 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_512_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SHA3_512 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_512_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Derive SM3_256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sm3_256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive SM3_256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size Key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sm3_256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_HKDF_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h new file mode 100644 index 0000000000..d9d8bc3553 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h @@ -0,0 +1,833 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_MAC_H +#define CRYPTLIB_MAC_H + +/*===================================================================================== + * Message Authentication Code (MAC) Primitives + *===================================================================================== + */ + +#if LIBSPDM_SHA256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha256_new() returns NULL. + **/ +extern void *libspdm_hmac_sha256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha256_free(void *hmac_sha256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha256_update(). + * + * If hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha256_ctx Pointer to HMAC-SHA256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_set_key(void *hmac_sha256_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA256 context. + * + * If hmac_sha256_ctx is NULL, then return false. + * If new_hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha256_ctx Pointer to HMAC-SHA256 context being copied. + * @param[out] new_hmac_sha256_ctx Pointer to new HMAC-SHA256 context. + * + * @retval true HMAC-SHA256 context copy succeeded. + * @retval false HMAC-SHA256 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_duplicate(const void *hmac_sha256_ctx, void *new_hmac_sha256_ctx); + +/** + * Digests the input data and updates HMAC-SHA256 context. + * + * This function performs HMAC-SHA256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA256 context should be initialized by libspdm_hmac_sha256_new(), and should not be + * finalized by libspdm_hmac_sha256_final(). Behavior with invalid context is undefined. + * + * If hmac_sha256_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha256_ctx Pointer to the HMAC-SHA256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA256 data digest succeeded. + * @retval false HMAC-SHA256 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_update(void *hmac_sha256_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA256 digest value. + * + * This function completes HMAC-SHA256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA256 context cannot + * be used again. HMAC-SHA256 context should be initialized by libspdm_hmac_sha256_new(), and should + * not be finalized by libspdm_hmac_sha256_final(). Behavior with invalid HMAC-SHA256 context is + * undefined. + * + * If hmac_sha256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha256_ctx Pointer to the HMAC-SHA256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA256 digest computation succeeded. + * @retval false HMAC-SHA256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_final(void *hmac_sha256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA256 digest of a input data buffer. + * + * This function performs the HMAC-SHA256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA256 digest computation succeeded. + * @retval false HMAC-SHA256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA256_SUPPORT */ + +#if LIBSPDM_SHA384_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA384 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha384_new() returns NULL. + **/ +extern void *libspdm_hmac_sha384_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha384_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha384_free(void *hmac_sha384_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha384_update(). + * + * If hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha384_ctx Pointer to HMAC-SHA384 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_set_key(void *hmac_sha384_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA384 context. + * + * If hmac_sha384_ctx is NULL, then return false. + * If new_hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha384_ctx Pointer to HMAC-SHA384 context being copied. + * @param[out] new_hmac_sha384_ctx Pointer to new HMAC-SHA384 context. + * + * @retval true HMAC-SHA384 context copy succeeded. + * @retval false HMAC-SHA384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_duplicate(const void *hmac_sha384_ctx, void *new_hmac_sha384_ctx); + +/** + * Digests the input data and updates HMAC-SHA384 context. + * + * This function performs HMAC-SHA384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA384 context should be initialized by libspdm_hmac_sha384_new(), and should not be + * finalized by libspdm_hmac_sha384_final(). Behavior with invalid context is undefined. + * + * If hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha384_ctx Pointer to the HMAC-SHA384 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA384 data digest succeeded. + * @retval false HMAC-SHA384 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_update(void *hmac_sha384_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA384 digest value. + * + * This function completes HMAC-SHA384 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA384 context cannot + * be used again. HMAC-SHA384 context should be initialized by libspdm_hmac_sha384_new(), and should + * not be finalized by libspdm_hmac_sha384_final(). Behavior with invalid HMAC-SHA384 context is + * undefined. + * + * If hmac_sha384_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha384_ctx Pointer to the HMAC-SHA384 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA384 digest computation succeeded. + * @retval false HMAC-SHA384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_final(void *hmac_sha384_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA384 digest of a input data buffer. + * + * This function performs the HMAC-SHA384 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA384 digest computation succeeded. + * @retval false HMAC-SHA384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha384_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA384_SUPPORT */ + +#if LIBSPDM_SHA512_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA512 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha512_new() returns NULL. + **/ +extern void *libspdm_hmac_sha512_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha512_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha512_free(void *hmac_sha512_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha512_update(). + * + * If hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha512_ctx Pointer to HMAC-SHA512 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_set_key(void *hmac_sha512_ctx, const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA512 context. + * + * If hmac_sha512_ctx is NULL, then return false. + * If new_hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha512_ctx Pointer to HMAC-SHA512 context being copied. + * @param[out] new_hmac_sha512_ctx Pointer to new HMAC-SHA512 context. + * + * @retval true HMAC-SHA512 context copy succeeded. + * @retval false HMAC-SHA512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_duplicate(const void *hmac_sha512_ctx, void *new_hmac_sha512_ctx); + +/** + * Digests the input data and updates HMAC-SHA512 context. + * + * This function performs HMAC-SHA512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA512 context should be initialized by libspdm_hmac_sha512_new(), and should not be + * finalized by libspdm_hmac_sha512_final(). Behavior with invalid context is undefined. + * + * If hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha512_ctx Pointer to the HMAC-SHA512 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA512 data digest succeeded. + * @retval false HMAC-SHA512 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_update(void *hmac_sha512_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA512 digest value. + * + * This function completes HMAC-SHA512 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA512 context cannot + * be used again. HMAC-SHA512 context should be initialized by libspdm_hmac_sha512_new(), and should + * not be finalized by libspdm_hmac_sha512_final(). Behavior with invalid HMAC-SHA512 context is + * undefined. + * + * If hmac_sha512_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha512_ctx Pointer to the HMAC-SHA512 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA512 digest computation succeeded. + * @retval false HMAC-SHA512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha512_final(void *hmac_sha512_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA512 digest of a input data buffer. + * + * This function performs the HMAC-SHA512 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA512 digest computation succeeded. + * @retval false HMAC-SHA512 digest computation failed. + * @retval false This interface is not supported. + * + **/ +extern bool libspdm_hmac_sha512_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA512_SUPPORT */ + +#if LIBSPDM_SHA3_256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_256_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_256_free(void *hmac_sha3_256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_256_update(). + * + * If hmac_sha3_256_ctx is NULL, then return false. + * + * @param[out] hmac_sha3_256_ctx Pointer to HMAC-SHA3-256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +extern bool libspdm_hmac_sha3_256_set_key(void *hmac_sha3_256_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-256 context. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * If new_hmac_sha3_256_ctx is NULL, then return false. + * + * @param[in] hmac_sha3_256_ctx Pointer to HMAC-SHA3-256 context being copied. + * @param[out] new_hmac_sha3_256_ctx Pointer to new HMAC-SHA3-256 context. + * + * @retval true HMAC-SHA3-256 context copy succeeded. + * @retval false HMAC-SHA3-256 context copy failed. + **/ +extern bool libspdm_hmac_sha3_256_duplicate(const void *hmac_sha3_256_ctx, + void *new_hmac_sha3_256_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-256 context. + * + * This function performs HMAC-SHA3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-256 context should be initialized by libspdm_hmac_sha3_256_new(), and should not be + * finalized by libspdm_hmac_sha3_256_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * + * @param[in, out] hmac_sha3_256_ctx Pointer to the HMAC-SHA3-256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-256 data digest succeeded. + * @retval false HMAC-SHA3-256 data digest failed. + **/ +extern bool libspdm_hmac_sha3_256_update(void *hmac_sha3_256_ctx, + const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-256 digest value. + * + * This function completes HMAC-SHA3-256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-256 context cannot + * be used again. HMAC-SHA3-256 context should be initialized by libspdm_hmac_sha3_256_new(), and + * should not be finalized by libspdm_hmac_sha3_256_final(). Behavior with invalid HMAC-SHA3-256 + * context is undefined. + * + * If hmac_sha3_256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_sha3_256_ctx Pointer to the HMAC-SHA3-256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA3-256 digest computation succeeded. + * @retval false HMAC-SHA3-256 digest computation failed. + **/ +extern bool libspdm_hmac_sha3_256_final(void *hmac_sha3_256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-256 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA3-256 digest computation succeeded. + * @retval false HMAC-SHA3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_256_SUPPORT */ + +#if LIBSPDM_SHA3_384_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-384 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_384_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_384_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_384_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_384_free(void *hmac_sha3_384_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_384_update(). + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha3_384_ctx Pointer to HMAC-SHA3-384 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_set_key(void *hmac_sha3_384_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-384 context. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If new_hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha3_384_ctx Pointer to HMAC-SHA3-384 context being copied. + * @param[out] new_hmac_sha3_384_ctx Pointer to new HMAC-SHA3-384 context. + * + * @retval true HMAC-SHA3-384 context copy succeeded. + * @retval false HMAC-SHA3-384 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_duplicate(const void *hmac_sha3_384_ctx, + void *new_hmac_sha3_384_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-384 context. + * + * This function performs HMAC-SHA3-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-384 context should be initialized by libspdm_hmac_sha3_384_new(), and should not be + * finalized by libspdm_hmac_sha3_384_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_384_ctx Pointer to the HMAC-SHA3-384 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-384 data digest succeeded. + * @retval false HMAC-SHA3-384 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_update(void *hmac_sha3_384_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-384 digest value. + * + * This function completes HMAC-SHA3-384 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-384 context cannot + * be used again. HMAC-SHA3-384 context should be initialized by libspdm_hmac_sha3_384_new(), and + * should not be finalized by libspdm_hmac_sha3_384_final(). Behavior with invalid HMAC-SHA3-384 + * context is undefined. + * + * If hmac_sha3_384_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_384_ctx Pointer to the HMAC-SHA3-384 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA3-384 digest computation succeeded. + * @retval false HMAC-SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_final(void *hmac_sha3_384_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-384 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-384 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA3-384 digest computation succeeded. + * @retval false HMAC-SHA3-384 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_384_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_384_SUPPORT */ + +#if LIBSPDM_SHA3_512_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA3-512 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha3_512_new() returns NULL. + **/ +extern void *libspdm_hmac_sha3_512_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha3_512_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sha3_512_free(void *hmac_sha3_512_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha3_512_update(). + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha3_512_ctx Pointer to HMAC-SHA3-512 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_set_key(void *hmac_sha3_512_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC-SHA3-512 context. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If new_hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha3_512_ctx Pointer to HMAC-SHA3-512 context being copied. + * @param[out] new_hmac_sha3_512_ctx Pointer to new HMAC-SHA3-512 context. + * + * @retval true HMAC-SHA3-512 context copy succeeded. + * @retval false HMAC-SHA3-512 context copy failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_duplicate(const void *hmac_sha3_512_ctx, + void *new_hmac_sha3_512_ctx); + +/** + * Digests the input data and updates HMAC-SHA3-512 context. + * + * This function performs HMAC-SHA3-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA3-512 context should be initialized by libspdm_hmac_sha3_512_new(), and should not be + * finalized by libspdm_hmac_sha3_512_final(). Behavior with invalid context is undefined. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_512_ctx Pointer to the HMAC-SHA3-512 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SHA3-512 data digest succeeded. + * @retval false HMAC-SHA3-512 data digest failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_update(void *hmac_sha3_512_ctx, + const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SHA3-512 digest value. + * + * This function completes HMAC-SHA3-512 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA3-512 context cannot + * be used again. HMAC-SHA3-512 context should be initialized by libspdm_hmac_sha3_512_new(), and + * should not be finalized by libspdm_hmac_sha3_512_final(). Behavior with invalid HMAC-SHA3-512 + * context is undefined. + * + * If hmac_sha3_512_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha3_512_ctx Pointer to the HMAC-SHA3-512 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA3-512 digest computation succeeded. + * @retval false HMAC-SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_final(void *hmac_sha3_512_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SHA3-512 digest of a input data buffer. + * + * This function performs the HMAC-SHA3-512 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA3-512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA3-512 digest computation succeeded. + * @retval false HMAC-SHA3-512 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sha3_512_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SHA3_512_SUPPORT */ + +#if LIBSPDM_SM3_256_SUPPORT +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SM3-256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sm3_256_new() returns NULL. + **/ +extern void *libspdm_hmac_sm3_256_new(void); + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sm3_256_ctx Pointer to the HMAC_CTX context to be released. + **/ +extern void libspdm_hmac_sm3_256_free(void *hmac_sm3_256_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sm3_256_update(). + * + * If hmac_sm3_256_ctx is NULL, then return false. + * + * @param[out] hmac_sm3_256_ctx Pointer to HMAC-SM3-256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +extern bool libspdm_hmac_sm3_256_set_key(void *hmac_sm3_256_ctx, + const uint8_t *key, size_t key_size); + +/** + * Makes a copy of an existing HMAC-SM3-256 context. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * If new_hmac_sm3_256_ctx is NULL, then return false. + * + * @param[in] hmac_sm3_256_ctx Pointer to HMAC-SM3-256 context being copied. + * @param[out] new_hmac_sm3_256_ctx Pointer to new HMAC-SM3-256 context. + * + * @retval true HMAC-SM3-256 context copy succeeded. + * @retval false HMAC-SM3-256 context copy failed. + **/ +extern bool libspdm_hmac_sm3_256_duplicate(const void *hmac_sm3_256_ctx, + void *new_hmac_sm3_256_ctx); + +/** + * Digests the input data and updates HMAC-SM3-256 context. + * + * This function performs HMAC-SM3-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SM3-256 context should be initialized by libspdm_hmac_sm3_256_new(), and should not be + * finalized by libspdm_hmac_sm3_256_final(). Behavior with invalid context is undefined. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * + * @param[in, out] hmac_sm3_256_ctx Pointer to the HMAC-SM3-256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC-SM3-256 data digest succeeded. + * @retval false HMAC-SM3-256 data digest failed. + **/ +extern bool libspdm_hmac_sm3_256_update(void *hmac_sm3_256_ctx, const void *data, size_t data_size); + +/** + * Completes computation of the HMAC-SM3-256 digest value. + * + * This function completes HMAC-SM3-256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SM3-256 context cannot + * be used again. HMAC-SM3-256 context should be initialized by libspdm_hmac_sm3_256_new(), and + * should not be finalized by libspdm_hmac_sm3_256_final(). Behavior with invalid HMAC-SM3-256 + * context is undefined. + * + * If hmac_sm3_256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_sm3_256_ctx Pointer to the HMAC-SM3-256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SM3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SM3-256 digest computation succeeded. + * @retval false HMAC-SM3-256 digest computation failed. + **/ +extern bool libspdm_hmac_sm3_256_final(void *hmac_sm3_256_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC-SM3-256 digest of a input data buffer. + * + * This function performs the HMAC-SM3-256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SM3-256 digest + * value (32 bytes). + * + * @retval true HMAC-SM3-256 digest computation succeeded. + * @retval false HMAC-SM3-256 digest computation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_hmac_sm3_256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value); +#endif /* LIBSPDM_SM3_256_SUPPORT */ + +#endif /* CRYPTLIB_MAC_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h new file mode 100644 index 0000000000..7da2bbb4cc --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h @@ -0,0 +1,30 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_RNG_H +#define CRYPTLIB_RNG_H + +/*===================================================================================== + * Random Number Generation Primitive + *=====================================================================================*/ + +/** + * Generates a random byte stream of the specified size. If initialization, testing, or seeding of + * the (pseudo)random number generator is required it should be done before this function is called. + * + * If output is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] output Pointer to buffer to receive random value. + * @param[in] size Size of random bytes to generate. + * + * @retval true Random byte stream generated successfully. + * @retval false Generation of random byte stream failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_random_bytes(uint8_t *output, size_t size); + +#endif /* CRYPTLIB_RNG_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h new file mode 100644 index 0000000000..6135575b3b --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h @@ -0,0 +1,264 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_RSA_H +#define CRYPTLIB_RSA_H + +/*===================================================================================== + * RSA Cryptography Primitives + *===================================================================================== + */ + +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +/* RSA key Tags Definition used in libspdm_rsa_set_key() function for key component + * identification. + */ +typedef enum { + LIBSPDM_RSA_KEY_N, /*< RSA public Modulus (N)*/ + LIBSPDM_RSA_KEY_E, /*< RSA public exponent (e)*/ + LIBSPDM_RSA_KEY_D, /*< RSA Private exponent (d)*/ + LIBSPDM_RSA_KEY_P, /*< RSA secret prime factor of Modulus (p)*/ + LIBSPDM_RSA_KEY_Q, /*< RSA secret prime factor of Modules (q)*/ + LIBSPDM_RSA_KEY_DP, /*< p's CRT exponent (== d mod (p - 1))*/ + LIBSPDM_RSA_KEY_DQ, /*< q's CRT exponent (== d mod (q - 1))*/ + LIBSPDM_RSA_KEY_Q_INV /*< The CRT coefficient (== 1/q mod p)*/ +} libspdm_rsa_key_tag_t; + +/** + * Allocates and initializes one RSA context for subsequent use. + * + * @return Pointer to the RSA context that has been initialized. + * If the allocations fails, libspdm_rsa_new() returns NULL. + **/ +extern void *libspdm_rsa_new(void); + +/** + * Release the specified RSA context. + * + * If rsa_context is NULL, then return false. + * + * @param[in] rsa_context Pointer to the RSA context to be released. + **/ +extern void libspdm_rsa_free(void *rsa_context); + +/** + * Sets the tag-designated key component into the established RSA context. + * + * This function sets the tag-designated RSA key component into the established + * RSA context from the user-specified non-negative integer (octet string format + * represented in RSA PKCS#1). + * If big_number is NULL, then the specified key component in RSA context is cleared. + * If rsa_context is NULL, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] key_tag tag of RSA key component being set. + * @param[in] big_number Pointer to octet integer buffer. + * If NULL, then the specified key component in RSA + * context is cleared. + * @param[in] bn_size Size of big number buffer in bytes. + * If big_number is NULL, then it is ignored. + * + * @retval true RSA key component was set successfully. + * @retval false Invalid RSA key component tag. + **/ +extern bool libspdm_rsa_set_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, + const uint8_t *big_number, size_t bn_size); + +/** + * Gets the tag-designated RSA key component from the established RSA context. + * + * This function retrieves the tag-designated RSA key component from the + * established RSA context as a non-negative integer (octet string format + * represented in RSA PKCS#1). + * If specified key component has not been set or has been cleared, then returned + * bn_size is set to 0. + * If the big_number buffer is too small to hold the contents of the key, false + * is returned and bn_size is set to the required buffer size to obtain the key. + * + * If rsa_context is NULL, then return false. + * If bn_size is NULL, then return false. + * If bn_size is large enough but big_number is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] key_tag Tag of RSA key component being set. + * @param[out] big_number Pointer to octet integer buffer. + * @param[in, out] bn_size On input, the size of big number buffer in bytes. + * On output, the size of data returned in big number buffer in bytes. + * + * @retval true RSA key component was retrieved successfully. + * @retval false Invalid RSA key component tag. + * @retval false bn_size is too small. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, + uint8_t *big_number, size_t *bn_size); + +/** + * Generates RSA key components. + * + * This function generates RSA key components. It takes RSA public exponent E and + * length in bits of RSA modulus N as input, and generates all key components. + * If public_exponent is NULL, the default RSA public exponent (0x10001) will be used. + * + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] modulus_length Length of RSA modulus N in bits. + * @param[in] public_exponent Pointer to RSA public exponent. + * @param[in] public_exponent_size Size of RSA public exponent buffer in bytes. + * + * @retval true RSA key component was generated successfully. + * @retval false Invalid RSA key component tag. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_generate_key(void *rsa_context, size_t modulus_length, + const uint8_t *public_exponent, + size_t public_exponent_size); + +/** + * Validates key components of RSA context. + * NOTE: This function performs integrity checks on all the RSA key material, so + * the RSA key structure must contain all the private key data. + * + * This function validates key components of RSA context in following aspects: + * - Whether p is a prime + * - Whether q is a prime + * - Whether n = p * q + * - Whether d*e = 1 mod lcm(p-1,q-1) + * + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] rsa_context Pointer to RSA context to check. + * + * @retval true RSA key components are valid. + * @retval false RSA key components are not valid. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_check_key(void *rsa_context); +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + +#if LIBSPDM_RSA_SSA_SUPPORT +/** + * Carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme. + * + * This function carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme + * defined in RSA PKCS#1. If the signature buffer is too small to hold the contents of signature, + * false is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] rsa_context Pointer to RSA context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive RSA PKCS1-v1_5 signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in PKCS1-v1_5. + * @retval false signature generation failed. + * @retval false sig_size is too small. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_pkcs1_sign_with_nid(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, + size_t hash_size, uint8_t *signature, + size_t *sig_size); + +/** + * Verifies the RSA-SSA signature with EMSA-PKCS1-v1_5 encoding scheme defined in RSA PKCS#1. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, + * SHA3_384, SHA3_512. + * + * @param[in] rsa_context Pointer to RSA context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to RSA PKCS1-v1_5 signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in PKCS1-v1_5. + * @retval false Invalid signature or invalid RSA context. + **/ +extern bool libspdm_rsa_pkcs1_verify_with_nid(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, + size_t hash_size, const uint8_t *signature, + size_t sig_size); +#endif /* LIBSPDM_RSA_SSA_SUPPORT */ + +#if LIBSPDM_RSA_PSS_SUPPORT +/** + * Carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme. + * + * This function carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme defined + * in RSA PKCS#1 v2.2. + * + * The salt length is same as digest length. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, + * SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * @param[in] rsa_context Pointer to RSA context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive RSA-SSA PSS signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in RSA-SSA PSS. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_rsa_pss_sign(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the RSA-SSA signature with EMSA-PSS encoding scheme defined in + * RSA PKCS#1 v2.2. + * + * The salt length is same as digest length. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, + * SHA3_512. + * + * @param[in] rsa_context Pointer to RSA context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size Size of the message hash in bytes. + * @param[in] signature Pointer to RSA-SSA PSS signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in RSA-SSA PSS. + * @retval false Invalid signature or invalid RSA context. + **/ +extern bool libspdm_rsa_pss_verify(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_RSA_PSS_SUPPORT */ +#endif /* CRYPTLIB_RSA_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h new file mode 100644 index 0000000000..2b382b9394 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h @@ -0,0 +1,194 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_SM2_H +#define CRYPTLIB_SM2_H + +/*===================================================================================== + * Shang-Mi2 Primitives + *=====================================================================================*/ + +#if LIBSPDM_SM2_DSA_SUPPORT +/** + * Allocates and Initializes one Shang-Mi2 context for subsequent use. + * + * @param nid cipher NID + * + * @return Pointer to the Shang-Mi2 context that has been initialized. + * If the allocations fails, sm2_new_by_nid() returns NULL. + **/ +extern void *libspdm_sm2_dsa_new_by_nid(size_t nid); + +/** + * Release the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + **/ +extern void libspdm_sm2_dsa_free(void *sm2_context); + +/** + * Carries out the SM2 signature, based upon GB/T 32918.2-2016: SM2 - Part2. + * + * This function carries out the SM2 signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If sm2_context is NULL, then return false. + * If message is NULL, then return false. + * hash_nid must be SM3_256. + * If sig_size is large enough but signature is NULL, then return false. + * + * The id_a_size must be smaller than 2^16-1. + * The sig_size is 64. first 32-byte is R, second 32-byte is S. + * + * @param[in] sm2_context Pointer to sm2 context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] id_a The ID-A of the signing context. + * @param[in] id_a_size Size of ID-A signing context. + * @param[in] message Pointer to octet message to be signed (before hash). + * @param[in] size Size of the message in bytes. + * @param[out] signature Pointer to buffer to receive SM2 signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in SM2. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_sm2_dsa_sign(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *message, size_t size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the SM2 signature, based upon GB/T 32918.2-2016: SM2 - Part2. + * + * If sm2_context is NULL, then return false. + * If message is NULL, then return false. + * If signature is NULL, then return false. + * hash_nid must be SM3_256. + * + * The id_a_size must be smaller than 2^16-1. + * The sig_size is 64. first 32-byte is R, second 32-byte is S. + * + * @param[in] sm2_context Pointer to SM2 context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] id_a The ID-A of the signing context. + * @param[in] id_a_size Size of ID-A signing context. + * @param[in] message Pointer to octet message to be checked (before hash). + * @param[in] size Size of the message in bytes. + * @param[in] signature Pointer to SM2 signature to be verified. + * @param[in] sig_size Size of signature in bytes. + * + * @retval true Valid signature encoded in SM2. + * @retval false Invalid signature or invalid sm2 context. + * + **/ +extern bool libspdm_sm2_dsa_verify(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *message, size_t size, + const uint8_t *signature, size_t sig_size); +#endif /* LIBSPDM_SM2_DSA_SUPPORT */ + +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT +/** + * Allocates and Initializes one Shang-Mi2 context for subsequent use. + * + * @param nid cipher NID + * + * @return Pointer to the Shang-Mi2 context that has been initialized. + * If the allocations fails, sm2_new_by_nid() returns NULL. + **/ +extern void *libspdm_sm2_key_exchange_new_by_nid(size_t nid); + +/** + * Release the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + * + **/ +extern void libspdm_sm2_key_exchange_free(void *sm2_context); + +/** + * Initialize the specified sm2 context. + * + * @param[in] sm2_context Pointer to the sm2 context to be released. + * @param[in] hash_nid hash NID, only SM3 is valid. + * @param[in] id_a The ID-A of the key exchange context. + * @param[in] id_a_size Size of ID-A key exchange context. + * @param[in] id_b The ID-B of the key exchange context. + * @param[in] id_b_size Size of ID-B key exchange context. + * @param[in] is_initiator If the caller is initiator. + * + * @retval true sm2 context is initialized. + * @retval false sm2 context is not initialized. + **/ +extern bool libspdm_sm2_key_exchange_init(const void *sm2_context, size_t hash_nid, + const uint8_t *id_a, size_t id_a_size, + const uint8_t *id_b, size_t id_b_size, + bool is_initiator); + +/** + * Generates sm2 key and returns sm2 public key (X, Y), based upon GB/T 32918.3-2016: SM2 - Part3. + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * sm2 context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * If sm2_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] sm2_context Pointer to the sm2 context. + * @param[out] public_data Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true sm2 public X,Y generation succeeded. + * @retval false sm2 public X,Y generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_sm2_key_exchange_generate_key(void *sm2_context, uint8_t *public_data, + size_t *public_size); + +/** + * Computes exchanged common key, based upon GB/T 32918.3-2016: SM2 - Part3. + * + * Given peer's public key (X, Y), this function computes the exchanged common key, + * based on its own context including value of curve parameter and random secret. + * X is the first half of peer_public with size being peer_public_size / 2, + * Y is the second half of peer_public with size being peer_public_size / 2. + * + * If sm2_context is NULL, then return false. + * If peer_public is NULL, then return false. + * If peer_public_size is 0, then return false. + * If key is NULL, then return false. + * + * The id_a_size and id_b_size must be smaller than 2^16-1. + * The peer_public_size is 64. first 32-byte is X, second 32-byte is Y. + * The key_size must be smaller than 2^32-1, limited by KDF function. + * + * @param[in, out] sm2_context Pointer to the sm2 context. + * @param[in] peer_public Pointer to the peer's public X,Y. + * @param[in] peer_public_size Size of peer's public X,Y in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in] key_size On input, the size of key buffer in bytes. + * + * @retval true sm2 exchanged key generation succeeded. + * @retval false sm2 exchanged key generation failed. + **/ +extern bool libspdm_sm2_key_exchange_compute_key(void *sm2_context, + const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); +#endif /* LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT */ +#endif /* CRYPTLIB_SM2_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h new file mode 100644 index 0000000000..9f638beb65 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h @@ -0,0 +1,116 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef DEBUG_LIB_H +#define DEBUG_LIB_H + +/** @file + * Provides services to print debug and assert messages to a debug output device. + * + * The debug library supports debug print and asserts based on a combination of macros and code. + * The debug library can be turned on and off so that the debug code does not increase the size of + * an image. + **/ + +#include "internal/libspdm_lib_config.h" + +#if LIBSPDM_DEBUG_PRINT_ENABLE + +/* Declare bits for the error_level parameter of libspdm_debug_print(). */ +#define LIBSPDM_DEBUG_INFO 0x00000040 +#define LIBSPDM_DEBUG_ERROR 0x80000000 + +/** + * Prints a debug message to the debug output device if the specified error level is enabled. + * + * @param error_level The error level of the debug message, either LIBSPDM_DEBUG_INFO or + * LIBSPDM_DEBUG_ERROR. + * @param format The format string for the debug message to print. + * @param ... The variable argument list whose contents are accessed + * based on the format string specified by format. + **/ +extern void libspdm_debug_print(size_t error_level, const char *format, ...); +#endif /* LIBSPDM_DEBUG_PRINT_ENABLE */ + +#if LIBSPDM_DEBUG_ASSERT_ENABLE +/** + * Prints an assert message containing a filename, line number, and description. + * This may be followed by a breakpoint or a dead loop. + * + * @param file_name The pointer to the name of the source file that generated the assert + * condition. + * @param line_number The line number in the source file that generated the assert condition + * @param description The pointer to the description of the assert condition. + * + **/ +extern void libspdm_debug_assert(const char *file_name, size_t line_number, + const char *description); +#endif /* LIBSPDM_DEBUG_ASSERT_ENABLE */ + +/** + * LIBSPDM_ASSERT(expression) - Macro that calls libspdm_debug_assert() if an expression evaluates + * to false. It is enabled through the LIBSPDM_DEBUG_ASSERT_ENABLE + * macro. + * + * @param expression Boolean expression. + **/ +#if LIBSPDM_DEBUG_ASSERT_ENABLE +#define LIBSPDM_ASSERT(expression) \ + do { \ + if (!(expression)) { \ + libspdm_debug_assert(__FILE__, __LINE__, #expression); \ + } \ + } while (false) +#else +#define LIBSPDM_ASSERT(expression) +#endif + +/** + * LIBSPDM_DEBUG(level, format_string, argument_list...) - Macro that calls libspdm_debug_print(). + * It is enabled through the + * LIBSPDM_PRINT_ENABLE macro. + * @param print_level Either LIBSPDM_DEBUG_INFO or LIBSPDM_DEBUG_ERROR. + * @param format_string Formatted string. + * @param argument_list List of arguments. + * + * Note that format_string and argument_list are the same as those defined by the C printf function. + **/ +#if LIBSPDM_DEBUG_PRINT_ENABLE +#define LIBSPDM_DEBUG(expression) \ + do { \ + LIBSPDM_DEBUG_INTERNAL(expression); \ + } while (false) + +#define LIBSPDM_DEBUG_PRINT_INTERNAL(print_level, ...) \ + do { \ + libspdm_debug_print(print_level, ## __VA_ARGS__); \ + } while (false) + +#define LIBSPDM_DEBUG_INTERNAL(expression) LIBSPDM_DEBUG_PRINT_INTERNAL expression +#else +#define LIBSPDM_DEBUG(expression) +#endif + +/** + * LIBSPDM_DEBUG_CODE(expression) - Macro that defines a section of debug source code. + * It is enabled through the LIBSPDM_BLOCK_ENABLE macro. + * + * @param expression One or more lines of expressions that are used for debugging and should not + * affect the behavior of functional code. + **/ +#if LIBSPDM_DEBUG_BLOCK_ENABLE +#define LIBSPDM_DEBUG_CODE(expression) \ + do { \ + uint8_t __debug_code_local; \ + expression \ + __debug_code_local = 0; \ + __debug_code_local++; \ + } while (false) +#else +#define LIBSPDM_DEBUG_CODE(expression) +#endif + +#endif /* DEBUG_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h new file mode 100644 index 0000000000..9e8396eabe --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h @@ -0,0 +1,113 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Provides copy memory, fill memory, zero memory, and GUID functions. + * + * The Base Memory Library provides optimized implementations for common memory-based operations. + * These functions should be used in place of coding your own loops to do equivalent common functions. + * This allows optimized library implementations to help increase performance. + **/ + +#ifndef BASE_MEMORY_LIB +#define BASE_MEMORY_LIB + +/** + * Copies bytes from a source buffer to a destination buffer. + * + * This function copies "src_len" bytes from "src_buf" to "dst_buf". + * + * Asserts and returns a non-zero value if any of the following are true: + * 1) "src_buf" or "dst_buf" are NULL. + * 2) "src_len" or "dst_len" is greater than (SIZE_MAX >> 1). + * 3) "src_len" is greater than "dst_len". + * 4) "src_buf" and "dst_buf" overlap. + * + * If any of these cases fail, a non-zero value is returned. Additionally if + * "dst_buf" points to a non-NULL value and "dst_len" is valid, then "dst_len" + * bytes of "dst_buf" are zeroed. + * + * This function follows the C11 cppreference description of memcpy_s. + * https://en.cppreference.com/w/c/string/byte/memcpy + * The cppreferece description does NOT allow the source or destination + * buffers to be NULL. + * + * This function differs from the Microsoft and Safeclib memcpy_s implementations + * in that the Microsoft and Safeclib implementations allow for NULL source and + * destinations pointers when the number of bytes to copy (src_len) is zero. + * + * In addition the Microsoft and Safeclib memcpy_s functions return different + * negative values on error. For best support, clients should generally check + * against zero for success or failure. + * + * @param dst_buf Destination buffer to copy to. + * @param dst_len Maximum length in bytes of the destination buffer. + * @param src_buf Source buffer to copy from. + * @param src_len The number of bytes to copy from the source buffer. + * + * @return 0 on success. non-zero on error. + * + **/ +int libspdm_copy_mem(void *dst_buf, size_t dst_len, + const void *src_buf, size_t src_len); + +/** + * Fills a target buffer with a byte value, and returns the target buffer. + * + * This function fills length bytes of buffer with value, and returns buffer. + * + * If length is greater than (MAX_ADDRESS - buffer + 1), then ASSERT(). + * + * @param buffer The memory to set. + * @param length The number of bytes to set. + * @param value The value with which to fill length bytes of buffer. + * + * @return buffer. + * + **/ +void *libspdm_set_mem(void *buffer, size_t length, uint8_t value); + +/** + * Fills a target buffer with zeros, and returns the target buffer. + * + * This function fills length bytes of buffer with zeros, and returns buffer. + * + * If length > 0 and buffer is NULL, then ASSERT(). + * If length is greater than (MAX_ADDRESS - buffer + 1), then ASSERT(). + * + * @param buffer The pointer to the target buffer to fill with zeros. + * @param length The number of bytes in buffer to fill with zeros. + * + * @return buffer. + * + **/ +void *libspdm_zero_mem(void *buffer, size_t length); + +/** + * Compares the contents of two buffers in const time. + * + * This function compares length bytes of source_buffer to length bytes of destination_buffer. + * If all length bytes of the two buffers are identical, then 0 is returned. Otherwise, the + * value returned is the first mismatched byte in source_buffer subtracted from the first + * mismatched byte in destination_buffer. + * + * If length > 0 and destination_buffer is NULL, then ASSERT(). + * If length > 0 and source_buffer is NULL, then ASSERT(). + * If length is greater than (MAX_ADDRESS - destination_buffer + 1), then ASSERT(). + * If length is greater than (MAX_ADDRESS - source_buffer + 1), then ASSERT(). + * + * @param destination_buffer A pointer to the destination buffer to compare. + * @param source_buffer A pointer to the source buffer to compare. + * @param length The number of bytes to compare. + * + * @return 0 All length bytes of the two buffers are identical. + * @retval Non-zero There is mismatched between source_buffer and destination_buffer. + * + **/ +int32_t libspdm_const_compare_mem(const void *destination_buffer, + const void *source_buffer, size_t length); + +#endif /* BASE_MEMORY_LIB */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h new file mode 100644 index 0000000000..b1d3f28c6a --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h @@ -0,0 +1,57 @@ +/** + * Copyright Notice: + * Copyright 2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ +#ifndef PLATFORM_LIB_H +#define PLATFORM_LIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" + +/** + * Suspends the execution of the current thread until the time-out interval elapses. + * This API is deprecated. Please use libspdm_sleep_in_us(). + * + * @param milliseconds The time interval for which execution is to be suspended, in milliseconds. + * + **/ +void libspdm_sleep(uint64_t milliseconds); + +/** + * Suspends the execution of the current thread until the time-out interval elapses. + * + * @param microseconds The time interval for which execution is to be suspended, in milliseconds. + * + **/ +void libspdm_sleep_in_us(uint64_t microseconds); + +#if LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP +/** + * If no heartbeat arrives in seconds, the watchdog timeout event + * should terminate the session. + * + * @param session_id Indicate the SPDM session ID. + * @param seconds heartbeat period, in seconds. + * + **/ +bool libspdm_start_watchdog(uint32_t session_id, uint16_t seconds); + +/** + * stop watchdog. + * + * @param session_id Indicate the SPDM session ID. + * + **/ +bool libspdm_stop_watchdog(uint32_t session_id); + +/** + * Reset the watchdog in heartbeat response. + * + * @param session_id Indicate the SPDM session ID. + * + **/ +bool libspdm_reset_watchdog(uint32_t session_id); +#endif /* LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP */ + +#endif /* PLATFORM_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h new file mode 100644 index 0000000000..fd599c8bf3 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h @@ -0,0 +1,992 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Definitions of DSP0274 Security Protocol & data Model Specification (SPDM) + * version 1.2.0 in Distributed Management Task Force (DMTF). + **/ + +#ifndef SPDM_H +#define SPDM_H + +#pragma pack(1) + +/* 3 means SPDM spec 1.0, 1.1, 1.2 */ +#define SPDM_MAX_VERSION_COUNT 3 +#define SPDM_MAX_SLOT_COUNT 8 +#define SPDM_MAX_OPAQUE_DATA_SIZE 1024 + +#define SPDM_NONCE_SIZE 32 +#define SPDM_RANDOM_DATA_SIZE 32 + +/* SPDM response code (1.0) */ +#define SPDM_DIGESTS 0x01 +#define SPDM_CERTIFICATE 0x02 +#define SPDM_CHALLENGE_AUTH 0x03 +#define SPDM_VERSION 0x04 +#define SPDM_MEASUREMENTS 0x60 +#define SPDM_CAPABILITIES 0x61 +#define SPDM_ALGORITHMS 0x63 +#define SPDM_VENDOR_DEFINED_RESPONSE 0x7E +#define SPDM_ERROR 0x7F + +/* SPDM response code (1.1) */ +#define SPDM_KEY_EXCHANGE_RSP 0x64 +#define SPDM_FINISH_RSP 0x65 +#define SPDM_PSK_EXCHANGE_RSP 0x66 +#define SPDM_PSK_FINISH_RSP 0x67 +#define SPDM_HEARTBEAT_ACK 0x68 +#define SPDM_KEY_UPDATE_ACK 0x69 +#define SPDM_ENCAPSULATED_REQUEST 0x6A +#define SPDM_ENCAPSULATED_RESPONSE_ACK 0x6B +#define SPDM_END_SESSION_ACK 0x6C + +/* SPDM response code (1.2) */ +#define SPDM_CSR 0x6D +#define SPDM_SET_CERTIFICATE_RSP 0x6E +#define SPDM_CHUNK_SEND_ACK 0x05 +#define SPDM_CHUNK_RESPONSE 0x06 + +/* SPDM request code (1.0) */ +#define SPDM_GET_DIGESTS 0x81 +#define SPDM_GET_CERTIFICATE 0x82 +#define SPDM_CHALLENGE 0x83 +#define SPDM_GET_VERSION 0x84 +#define SPDM_GET_MEASUREMENTS 0xE0 +#define SPDM_GET_CAPABILITIES 0xE1 +#define SPDM_NEGOTIATE_ALGORITHMS 0xE3 +#define SPDM_VENDOR_DEFINED_REQUEST 0xFE +#define SPDM_RESPOND_IF_READY 0xFF + +/* SPDM request code (1.1) */ +#define SPDM_KEY_EXCHANGE 0xE4 +#define SPDM_FINISH 0xE5 +#define SPDM_PSK_EXCHANGE 0xE6 +#define SPDM_PSK_FINISH 0xE7 +#define SPDM_HEARTBEAT 0xE8 +#define SPDM_KEY_UPDATE 0xE9 +#define SPDM_GET_ENCAPSULATED_REQUEST 0xEA +#define SPDM_DELIVER_ENCAPSULATED_RESPONSE 0xEB +#define SPDM_END_SESSION 0xEC + +/* SPDM request code (1.2) */ +#define SPDM_GET_CSR 0xED +#define SPDM_SET_CERTIFICATE 0xEE +#define SPDM_CHUNK_SEND 0x85 +#define SPDM_CHUNK_GET 0x86 + +/* SPDM message header*/ +typedef struct { + uint8_t spdm_version; + uint8_t request_response_code; + uint8_t param1; + uint8_t param2; +} spdm_message_header_t; + +#define SPDM_MESSAGE_VERSION_10 0x10 +#define SPDM_MESSAGE_VERSION_11 0x11 +#define SPDM_MESSAGE_VERSION_12 0x12 +#define SPDM_MESSAGE_VERSION SPDM_MESSAGE_VERSION_10 + +/* SPDM GET_VERSION request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_get_version_request_t; + + +/* SPDM GET_VERSION response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint8_t reserved; + uint8_t version_number_entry_count; + /*spdm_version_number_t version_number_entry[version_number_entry_count];*/ +} spdm_version_response_t; + +/* SPDM VERSION structure + * bit[15:12] major_version + * bit[11:8] minor_version + * bit[7:4] update_version_number + * bit[3:0] alpha*/ +typedef uint16_t spdm_version_number_t; +#define SPDM_VERSION_NUMBER_SHIFT_BIT 8 + +#define SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT "dmtf-spdm-v1.2.*" +#define SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT_SIZE \ + (sizeof(SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT) - 1) +#define SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE 100 + +/* SPDM GET_CAPABILITIES request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD + * Below field is added in 1.1.*/ + uint8_t reserved; + uint8_t ct_exponent; + uint16_t reserved2; + uint32_t flags; + /* Below field is added in 1.2.*/ + uint32_t data_transfer_size; + uint32_t max_spdm_msg_size; +} spdm_get_capabilities_request_t; + +/* SPDM GET_CAPABILITIES response*/ + +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint8_t reserved; + uint8_t ct_exponent; + uint16_t reserved2; + uint32_t flags; + /* Below field is added in 1.2.*/ + uint32_t data_transfer_size; + uint32_t max_spdm_msg_size; +} spdm_capabilities_response_t; + +#define SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12 42 + +/* SPDM GET_CAPABILITIES request flags (1.1) */ +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP 0x00000002 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHAL_CAP 0x00000004 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP 0x00000040 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP 0x00000080 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MUT_AUTH_CAP 0x00000100 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP 0x00000200 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP (0x00000400 | 0x00000800) +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP_REQUESTER 0x00000400 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCAP_CAP 0x00001000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HBEAT_CAP 0x00002000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP 0x00004000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP 0x00008000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PUB_KEY_ID_CAP 0x00010000 + +/* SPDM GET_CAPABILITIES request flags (1.2) */ +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP 0x00020000 + +/* SPDM GET_CAPABILITIES response flags (1.0) */ +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP 0x00000001 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP 0x00000002 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP 0x00000004 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (0x00000008 | 0x00000010) +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG 0x00000008 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG 0x00000010 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP 0x00000020 + +/* SPDM GET_CAPABILITIES response flags (1.1) */ +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP 0x00000040 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MAC_CAP 0x00000080 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MUT_AUTH_CAP 0x00000100 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP 0x00000200 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP (0x00000400 | 0x00000800) +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER 0x00000400 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER_WITH_CONTEXT 0x00000800 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCAP_CAP 0x00001000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HBEAT_CAP 0x00002000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP 0x00004000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP 0x00008000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PUB_KEY_ID_CAP 0x00010000 + +/* SPDM GET_CAPABILITIES request flags (1.2) */ +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP 0x00020000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ALIAS_CERT_CAP 0x00040000 + +/* SPDM GET_CAPABILITIES response flags (1.2.1)*/ +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_SET_CERT_CAP 0x00080000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CSR_CAP 0x00100000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_INSTALL_RESET_CAP 0x00200000 + +/* SPDM NEGOTIATE_ALGORITHMS request */ +typedef struct { + spdm_message_header_t header; + /* param1 == Number of Algorithms Structure Tables + * param2 == RSVD*/ + uint16_t length; + uint8_t measurement_specification; + /* other_params_support is added in 1.2. + * BIT[0:3]=opaque_data_format support, BIT[4:7]=reserved*/ + uint8_t other_params_support; + uint32_t base_asym_algo; + uint32_t base_hash_algo; + uint8_t reserved2[12]; + uint8_t ext_asym_count; + uint8_t ext_hash_count; + uint16_t reserved3; + /*spdm_extended_algorithm_t ext_asym[ext_asym_count]; + * spdm_extended_algorithm_t ext_hash[ext_hash_count]; + * Below field is added in 1.1. + * spdm_negotiate_algorithms_struct_table_t alg_struct[param1];*/ +} spdm_negotiate_algorithms_request_t; + +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_LENGTH_VERSION_10 0x40 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_LENGTH_VERSION_11 0x80 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_LENGTH_VERSION_12 0x80 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_EXT_ALG_COUNT_VERSION_10 0x08 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_EXT_ALG_COUNT_VERSION_11 0x14 +#define SPDM_NEGOTIATE_ALGORITHMS_REQUEST_MAX_EXT_ALG_COUNT_VERSION_12 0x14 + +typedef struct { + uint8_t alg_type; + uint8_t alg_count; /* BIT[0:3]=ext_alg_count, BIT[4:7]=fixed_alg_byte_count*/ + /*uint8_t alg_supported[fixed_alg_byte_count]; + * uint32_t alg_external[ext_alg_count];*/ +} spdm_negotiate_algorithms_struct_table_t; + +#define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE 2 +#define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD 3 +#define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG 4 +#define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE 5 + +typedef struct { + uint8_t alg_type; + uint8_t alg_count; + uint16_t alg_supported; +} spdm_negotiate_algorithms_common_struct_table_t; + + +/* SPDM NEGOTIATE_ALGORITHMS request base_asym_algo/REQ_BASE_ASYM_ALG */ +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 0x00000001 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 0x00000002 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 0x00000004 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 0x00000008 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 0x00000010 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 0x00000020 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096 0x00000040 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 0x00000080 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521 0x00000100 + +/* SPDM NEGOTIATE_ALGORITHMS request base_asym_algo/REQ_BASE_ASYM_ALG (1.2) */ +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256 0x00000200 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519 0x00000400 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448 0x00000800 + +/* SPDM NEGOTIATE_ALGORITHMS request base_hash_algo */ +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256 0x00000001 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 0x00000002 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512 0x00000004 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256 0x00000008 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 0x00000010 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512 0x00000020 + +/* SPDM NEGOTIATE_ALGORITHMS request base_hash_algo (1.2) */ +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256 0x00000040 + +/* SPDM NEGOTIATE_ALGORITHMS request DHE */ +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048 0x00000001 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072 0x00000002 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096 0x00000004 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1 0x00000008 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1 0x00000010 +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1 0x00000020 + +/* SPDM NEGOTIATE_ALGORITHMS request DHE (1.2) */ +#define SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256 0x00000040 + +/* SPDM NEGOTIATE_ALGORITHMS request AEAD */ +#define SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM 0x00000001 +#define SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM 0x00000002 +#define SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305 0x00000004 + +/* SPDM NEGOTIATE_ALGORITHMS request AEAD (1.2) */ +#define SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM 0x00000008 + +/* SPDM NEGOTIATE_ALGORITHMS request KEY_SCHEDULE */ +#define SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH 0x00000001 + +/* SPDM NEGOTIATE_ALGORITHMS response */ +typedef struct { + spdm_message_header_t header; + /* param1 == Number of Algorithms Structure Tables + * param2 == RSVD*/ + uint16_t length; + uint8_t measurement_specification_sel; + /* other_params_selection is added in 1.2. + * BIT[0:3]=opaque_data_format select, BIT[4:7]=reserved*/ + uint8_t other_params_selection; + uint32_t measurement_hash_algo; + uint32_t base_asym_sel; + uint32_t base_hash_sel; + uint8_t reserved2[12]; + uint8_t ext_asym_sel_count; + uint8_t ext_hash_sel_count; + uint16_t reserved3; + /*spdm_extended_algorithm_t ext_asym_sel[ext_asym_sel_count]; + * spdm_extended_algorithm_t ext_hash_sel[ext_hash_sel_count]; + * Below field is added in 1.1. + * spdm_negotiate_algorithms_struct_table_t alg_struct[param1];*/ +} spdm_algorithms_response_t; + +/* SPDM NEGOTIATE_ALGORITHMS response measurement_hash_algo */ +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY 0x00000001 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256 0x00000002 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 0x00000004 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512 0x00000008 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 0x00000010 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384 0x00000020 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512 0x00000040 + +/* SPDM NEGOTIATE_ALGORITHMS response measurement_hash_algo (1.2) */ +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SM3_256 0x00000080 + +/* SPDM Opaque Data Format (1.2) */ +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_0 0x00000001 +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_1 0x00000002 +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_MASK 0xF + +/* SPDM Opaque Data Format 1 (1.2) */ +typedef struct { + uint8_t total_elements; + uint8_t reserved[3]; + /*opaque_element_table_t opaque_list[];*/ +} spdm_general_opaque_data_table_header_t; + +/* SPDM extended algorithm */ +typedef struct { + uint8_t registry_id; + uint8_t reserved; + uint16_t algorithm_id; +} spdm_extended_algorithm_t; + +/* SPDM registry_id */ +#define SPDM_REGISTRY_ID_DMTF 0 +#define SPDM_REGISTRY_ID_TCG 1 +#define SPDM_REGISTRY_ID_USB 2 +#define SPDM_REGISTRY_ID_PCISIG 3 +#define SPDM_REGISTRY_ID_IANA 4 +#define SPDM_REGISTRY_ID_HDBASET 5 +#define SPDM_REGISTRY_ID_MIPI 6 +#define SPDM_REGISTRY_ID_CXL 7 +#define SPDM_REGISTRY_ID_JEDEC 8 + +/* SPDM GET_DIGESTS request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_get_digest_request_t; + +/* SPDM GET_DIGESTS response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == slot_mask + * uint8_t digest[digest_size][slot_count];*/ +} spdm_digest_response_t; + + +/* SPDM GET_CERTIFICATE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == BIT[0:3]=slot_id, BIT[4:7]=RSVD + * param2 == RSVD*/ + uint16_t offset; + uint16_t length; +} spdm_get_certificate_request_t; + +#define SPDM_GET_CERTIFICATE_REQUEST_SLOT_ID_MASK 0xF + +/* SPDM GET_CERTIFICATE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == BIT[0:3]=slot_id, BIT[4:7]=RSVD + * param2 == RSVD*/ + uint16_t portion_length; + uint16_t remainder_length; + /*uint8_t cert_chain[portion_length];*/ +} spdm_certificate_response_t; + +#define SPDM_CERTIFICATE_RESPONSE_SLOT_ID_MASK 0xF +typedef struct { + /* Total length of the certificate chain, in bytes, + * including all fields in this table.*/ + + uint16_t length; + uint16_t reserved; + + /* digest of the Root Certificate. + * Note that Root Certificate is ASN.1 DER-encoded for this digest. + * The hash size is determined by the SPDM device.*/ + + /*uint8_t root_hash[hash_size];*/ + + /* One or more ASN.1 DER-encoded X509v3 certificates where the first certificate is signed by the Root + * Certificate or is the Root Certificate itself and each subsequent certificate is signed by the preceding + * certificate. The last certificate is the Leaf Certificate.*/ + + /*uint8_t certificates[length - 4 - hash_size];*/ +} spdm_cert_chain_t; + +/* SPDM CHALLENGE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == slot_id + * param2 == HashType*/ + uint8_t nonce[32]; +} spdm_challenge_request_t; + +/* SPDM CHALLENGE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == ResponseAttribute, BIT[0:3]=slot_id, BIT[4:6]=RSVD, BIT[7]=basic_mut_auth(deprecated in 1.2) + * param2 == slot_mask + * uint8_t cert_chain_hash[digest_size]; + * uint8_t nonce[32]; + * uint8_t measurement_summary_hash[digest_size]; + * uint16_t opaque_length; + * uint8_t opaque_data[opaque_length]; + * uint8_t signature[key_size];*/ +} spdm_challenge_auth_response_t; + +/* SPDM CHALLENGE request HashType */ +#define SPDM_CHALLENGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH 0 +#define SPDM_CHALLENGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH 1 +#define SPDM_CHALLENGE_REQUEST_ALL_MEASUREMENTS_HASH 0xFF + +#define SPDM_CHALLENGE_AUTH_RESPONSE_ATTRIBUTE_SLOT_ID_MASK 0xF +#define SPDM_CHALLENGE_AUTH_RESPONSE_ATTRIBUTE_BASIC_MUT_AUTH_REQ 0x00000080 /* Deprecated in SPDM 1.2*/ + +#define SPDM_CHALLENGE_AUTH_SIGN_CONTEXT "responder-challenge_auth signing" +#define SPDM_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE (sizeof(SPDM_CHALLENGE_AUTH_SIGN_CONTEXT) - 1) +#define SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT "requester-challenge_auth signing" +#define SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE (sizeof(SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT) - 1) + +/* SPDM GET_MEASUREMENTS request */ +typedef struct { + spdm_message_header_t header; + /* param1 == Attributes + * param2 == measurement_operation*/ + uint8_t nonce[32]; + /* Below field is added in 1.1.*/ + uint8_t slot_id_param; /* BIT[0:3]=slot_id, BIT[4:7]=RSVD*/ +} spdm_get_measurements_request_t; + +#define SPDM_GET_MEASUREMENTS_REQUEST_SLOT_ID_MASK 0xF + +/* SPDM GET_MEASUREMENTS request Attributes */ +#define SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE 0x00000001 +#define SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_RAW_BIT_STREAM_REQUESTED 0x00000002 + +/* SPDM GET_MEASUREMENTS request measurement_operation */ +#define SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS 0 + +/*SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_INDEX */ +#define SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS 0xFF + + +/* SPDM MEASUREMENTS block common header */ +typedef struct { + uint8_t index; + uint8_t measurement_specification; + uint16_t measurement_size; + /*uint8_t measurement[measurement_size];*/ +} spdm_measurement_block_common_header_t; + +#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF 0x00000001 + +/* SPDM MEASUREMENTS block DMTF header */ +typedef struct { + uint8_t dmtf_spec_measurement_value_type; + uint16_t dmtf_spec_measurement_value_size; + /*uint8_t Dmtf_spec_measurement_value[dmtf_spec_measurement_value_size];*/ +} spdm_measurement_block_dmtf_header_t; + +typedef struct { + spdm_measurement_block_common_header_t measurement_block_common_header; + spdm_measurement_block_dmtf_header_t measurement_block_dmtf_header; + /*uint8_t hash_value[hash_size];*/ +} spdm_measurement_block_dmtf_t; + +/* SPDM MEASUREMENTS block MeasurementValueType */ +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_IMMUTABLE_ROM 0 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MUTABLE_FIRMWARE 1 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_HARDWARE_CONFIGURATION 2 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_FIRMWARE_CONFIGURATION 3 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MEASUREMENT_MANIFEST 4 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_DEVICE_MODE 5 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_VERSION 6 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_SECURE_VERSION_NUMBER 7 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MASK 0x7 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_RAW_BIT_STREAM 0x00000080 + +/* SPDM MEASUREMENTS block index */ +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_INDEX_MEASUREMENT_MANIFEST 0xFD +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_INDEX_DEVICE_MODE 0xFE + +/* SPDM MEASUREMENTS device mode */ +typedef struct { + uint32_t operational_mode_capabilties; + uint32_t operational_mode_state; + uint32_t device_mode_capabilties; + uint32_t device_mode_state; +} spdm_measurements_device_mode_t; + +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_MANUFACTURING_MODE 0x00000001 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_VALIDATION_MODE 0x00000002 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_NORMAL_MODE 0x00000004 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_RECOVERY_MODE 0x00000008 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_RMA_MODE 0x00000010 +#define SPDM_MEASUREMENT_DEVICE_OPERATION_MODE_DECOMMISSIONED_MODE 0x00000020 + +#define SPDM_MEASUREMENT_DEVICE_MODE_NON_INVASIVE_DEBUG_MODE_IS_ACTIVE 0x00000001 +#define SPDM_MEASUREMENT_DEVICE_MODE_INVASIVE_DEBUG_MODE_IS_ACTIVE 0x00000002 +#define SPDM_MEASUREMENT_DEVICE_MODE_NON_INVASIVE_DEBUG_MODE_HAS_BEEN_ACTIVE 0x00000004 +#define SPDM_MEASUREMENT_DEVICE_MODE_INVASIVE_DEBUG_MODE_HAS_BEEN_ACTIVE 0x00000008 +#define SPDM_MEASUREMENT_DEVICE_MODE_INVASIVE_DEBUG_MODE_HAS_BEEN_ACTIVE_AFTER_MFG 0x00000010 + +/* SPDM MEASUREMENTS SVN */ +typedef uint64_t spdm_measurements_secure_version_number_t; + +/* SPDM GET_MEASUREMENTS response */ +typedef struct { + spdm_message_header_t header; + /* param1 == TotalNumberOfMeasurement/RSVD + * param2 == BIT[0:3]=slot_id, BIT[4:5]=content changed, BIT[6:7]=RSVD*/ + uint8_t number_of_blocks; + uint8_t measurement_record_length[3]; + /*uint8_t measurement_record[measurement_record_length]; + * uint8_t nonce[32]; + * uint16_t opaque_length; + * uint8_t opaque_data[opaque_length]; + * uint8_t signature[key_size];*/ +} spdm_measurements_response_t; + +#define SPDM_MEASUREMENTS_RESPONSE_SLOT_ID_MASK 0xF + +/* SPDM MEASUREMENTS content changed */ +#define SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_MASK 0x30 +#define SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_NO_DETECTION 0x00 +#define SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_DETECTED 0x10 +#define SPDM_MEASUREMENTS_RESPONSE_CONTENT_NO_CHANGE_DETECTED 0x20 + +#define SPDM_MEASUREMENTS_SIGN_CONTEXT "responder-measurements signing" +#define SPDM_MEASUREMENTS_SIGN_CONTEXT_SIZE (sizeof(SPDM_MEASUREMENTS_SIGN_CONTEXT) - 1) + +/* SPDM ERROR response */ +typedef struct { + spdm_message_header_t header; + /* param1 == Error Code + * param2 == Error data + * uint8_t extended_error_data[32];*/ +} spdm_error_response_t; + +#define SPDM_EXTENDED_ERROR_DATA_MAX_SIZE 32 + +/* SPDM error code */ +#define SPDM_ERROR_CODE_INVALID_REQUEST 0x01 +#define SPDM_ERROR_CODE_BUSY 0x03 +#define SPDM_ERROR_CODE_UNEXPECTED_REQUEST 0x04 +#define SPDM_ERROR_CODE_UNSPECIFIED 0x05 +#define SPDM_ERROR_CODE_UNSUPPORTED_REQUEST 0x07 +#define SPDM_ERROR_CODE_VERSION_MISMATCH 0x41 +#define SPDM_ERROR_CODE_RESPONSE_NOT_READY 0x42 +#define SPDM_ERROR_CODE_REQUEST_RESYNCH 0x43 +#define SPDM_ERROR_CODE_VENDOR_DEFINED 0xFF + +/* SPDM error code (1.1) */ +#define SPDM_ERROR_CODE_INVALID_SESSION 0x02 /* Deprecated in SPDM 1.2*/ +#define SPDM_ERROR_CODE_DECRYPT_ERROR 0x06 +#define SPDM_ERROR_CODE_REQUEST_IN_FLIGHT 0x08 +#define SPDM_ERROR_CODE_INVALID_RESPONSE_CODE 0x09 +#define SPDM_ERROR_CODE_SESSION_LIMIT_EXCEEDED 0x0A + +/* SPDM error code (1.2) */ +#define SPDM_ERROR_CODE_SESSION_REQUIRED 0x0B +#define SPDM_ERROR_CODE_RESET_REQUIRED 0x0C +#define SPDM_ERROR_CODE_RESPONSE_TOO_LARGE 0x0D +#define SPDM_ERROR_CODE_REQUEST_TOO_LARGE 0x0E +#define SPDM_ERROR_CODE_LARGE_RESPONSE 0x0F +#define SPDM_ERROR_CODE_MESSAGE_LOST 0x10 + +/* SPDM ResponseNotReady extended data */ +typedef struct { + uint8_t rd_exponent; + uint8_t request_code; + uint8_t token; + uint8_t rd_tm; +} spdm_error_data_response_not_ready_t; + +typedef struct { + spdm_message_header_t header; + /* param1 == Error Code + * param2 == Error data*/ + spdm_error_data_response_not_ready_t extend_error_data; +} spdm_error_response_data_response_not_ready_t; + +/* SPDM LargeResponse extended data */ +typedef struct { + uint8_t handle; +} spdm_error_data_large_response_t; + +typedef struct { + spdm_message_header_t header; + /* param1 == Error Code + * param2 == Error data*/ + spdm_error_data_large_response_t extend_error_data; +} spdm_error_response_large_response_t; + +/* SPDM RESPONSE_IF_READY request */ +typedef struct { + spdm_message_header_t header; + /* param1 == request_code + * param2 == token*/ +} spdm_response_if_ready_request_t; + +/* SPDM VENDOR_DEFINED request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint16_t standard_id; + uint8_t len; + /*uint8_t vendor_id[len]; + * uint16_t payload_length; + * uint8_t vendor_defined_payload[payload_length];*/ +} spdm_vendor_defined_request_msg_t; + +/* SPDM VENDOR_DEFINED response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint16_t standard_id; + uint8_t len; + /*uint8_t vendor_id[len]; + * uint16_t payload_length; + * uint8_t vendor_defined_payload[payload_length];*/ +} spdm_vendor_defined_response_msg_t; + +/* Below command is defined in SPDM 1.1 */ + +/* SPDM KEY_EXCHANGE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == HashType + * param2 == slot_id*/ + uint16_t req_session_id; + /* session_policy is added in 1.2.*/ + uint8_t session_policy; + uint8_t reserved; + uint8_t random_data[32]; + /*uint8_t exchange_data[D]; + * uint16_t opaque_length; + * uint8_t opaque_data[opaque_length];*/ +} spdm_key_exchange_request_t; + +/* SPDM KEY_EXCHANGE request session_policy */ +#define SPDM_KEY_EXCHANGE_REQUEST_SESSION_POLICY_TERMINATION_POLICY_RUNTIME_UPDATE 0x00000001 + +/* SPDM KEY_EXCHANGE request HashType */ +#define SPDM_KEY_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH 0 +#define SPDM_KEY_EXCHANGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH 1 +#define SPDM_KEY_EXCHANGE_REQUEST_ALL_MEASUREMENTS_HASH 0xFF + +/* SPDM KEY_EXCHANGE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == heartbeat_period + * param2 == RSVD*/ + uint16_t rsp_session_id; + uint8_t mut_auth_requested; + uint8_t req_slot_id_param; + uint8_t random_data[32]; + /*uint8_t exchange_data[D]; + * uint8_t measurement_summary_hash[digest_size]; + * uint16_t opaque_length; + * uint8_t opaque_data[opaque_length]; + * uint8_t signature[S]; + * uint8_t verify_data[H];*/ +} spdm_key_exchange_response_t; + +/* SPDM KEY_EXCHANGE response mut_auth_requested */ +#define SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED 0x00000001 +#define SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST 0x00000002 +#define SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS 0x00000004 + +#define SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT "responder-key_exchange_rsp signing" +#define SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT_SIZE \ + (sizeof(SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT) - 1) + +#define SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT "Requester-KEP-dmtf-spdm-v1.2" +#define SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE \ + (sizeof(SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT) - 1) + +#define SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT "Responder-KEP-dmtf-spdm-v1.2" +#define SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE \ + (sizeof(SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT) - 1) + +/* SPDM FINISH request */ +typedef struct { + spdm_message_header_t header; + /* param1 == signature_included + * param2 == req_slot_id + * uint8_t signature[S]; + * uint8_t verify_data[H];*/ +} spdm_finish_request_t; + +/* SPDM FINISH request signature_included */ +#define SPDM_FINISH_REQUEST_ATTRIBUTES_SIGNATURE_INCLUDED 0x00000001 + +/* SPDM FINISH response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD + * uint8_t verify_data[H];*/ +} spdm_finish_response_t; + +#define SPDM_FINISH_SIGN_CONTEXT "requester-finish signing" +#define SPDM_FINISH_SIGN_CONTEXT_SIZE (sizeof(SPDM_FINISH_SIGN_CONTEXT) - 1) + +/* SPDM PSK_EXCHANGE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == HashType + * param2 == RSVD/session_policy (1.2)*/ + uint16_t req_session_id; + uint16_t psk_hint_length; + uint16_t context_length; + uint16_t opaque_length; + /*uint8_t psk_hint[psk_hint_length]; + * uint8_t context[context_length]; + * uint8_t opaque_data[opaque_length];*/ +} spdm_psk_exchange_request_t; + +/* SPDM PSK_EXCHANGE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == heartbeat_period + * param2 == RSVD*/ + uint16_t rsp_session_id; + uint16_t reserved; + uint16_t context_length; + uint16_t opaque_length; + /*uint8_t measurement_summary_hash[digest_size]; + * uint8_t context[context_length]; + * uint8_t opaque_data[opaque_length]; + * uint8_t verify_data[H];*/ +} spdm_psk_exchange_response_t; + +/* SPDM PSK_FINISH request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD + * uint8_t verify_data[H];*/ +} spdm_psk_finish_request_t; + +/* SPDM PSK_FINISH response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_psk_finish_response_t; + + +/* SPDM HEARTBEAT request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_heartbeat_request_t; + +/* SPDM HEARTBEAT response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_heartbeat_response_t; + +/* SPDM KEY_UPDATE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == key_operation + * param2 == tag*/ +} spdm_key_update_request_t; + +/* SPDM KEY_UPDATE Operations table */ +#define SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_KEY 1 +#define SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_ALL_KEYS 2 +#define SPDM_KEY_UPDATE_OPERATIONS_TABLE_VERIFY_NEW_KEY 3 + +/* SPDM KEY_UPDATE response */ +typedef struct { + spdm_message_header_t header; + /* param1 == key_operation + * param2 == tag*/ +} spdm_key_update_response_t; + +/* SPDM GET_ENCAPSULATED_REQUEST request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_get_encapsulated_request_request_t; + +/* SPDM ENCAPSULATED_REQUEST response */ +typedef struct { + spdm_message_header_t header; + /* param1 == request_id + * param2 == RSVD + * uint8_t encapsulated_request[];*/ +} spdm_encapsulated_request_response_t; + +/* SPDM DELIVER_ENCAPSULATED_RESPONSE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == request_id + * param2 == RSVD + * uint8_t encapsulated_response[];*/ +} spdm_deliver_encapsulated_response_request_t; + +/* SPDM ENCAPSULATED_RESPONSE_ACK response */ +typedef struct { + spdm_message_header_t header; + /* param1 == request_id + * param2 == payload_type*/ + + /* below 4 bytes are added in 1.2.*/ + uint8_t ack_request_id; + uint8_t reserved[3]; + + /*uint8_t encapsulated_request[];*/ +} spdm_encapsulated_response_ack_response_t; + +/* SPDM ENCAPSULATED_RESPONSE_ACK_RESPONSE payload Type */ +#define SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_ABSENT 0 +#define SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_PRESENT 1 +#define SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_REQ_SLOT_NUMBER 2 + +/* SPDM END_SESSION request */ +typedef struct { + spdm_message_header_t header; + /* param1 == end_session_request_attributes + * param2 == RSVD*/ +} spdm_end_session_request_t; + +/* SPDM END_SESSION request Attributes */ +#define SPDM_END_SESSION_REQUEST_ATTRIBUTES_PRESERVE_NEGOTIATED_STATE_CLEAR 0x00000001 + +/* SPDM END_SESSION response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ +} spdm_end_session_response_t; + +/* SPDM SET_CERTIFICATE request */ +typedef struct { + spdm_message_header_t header; + /* param1 == BIT[0:3]=slot_id, BIT[4:7]=RSVD + * param2 == RSVD + * void * cert_chain*/ +} spdm_set_certificate_request_t; + +/* SPDM SET_CERTIFICATE_RSP response */ +typedef struct { + spdm_message_header_t header; + /* param1 == BIT[0:3]=slot_id, BIT[4:7]=RSVD + * param2 == RSVD*/ +} spdm_set_certificate_response_t; + +/* SPDM GET_CSR request */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint16_t requester_info_length; + uint16_t opaque_data_length; + /* uint8_t RequesterInfo[requester_info_length]; + * uint8_t opaque_data[opaque_data_length]; */ +} spdm_get_csr_request_t; + +/* SPDM CSR response */ +typedef struct { + spdm_message_header_t header; + /* param1 == RSVD + * param2 == RSVD*/ + uint16_t csr_length; + uint16_t reserved; +} spdm_csr_response_t; + +/* SPDM CHUNK_SEND request */ +typedef struct { + spdm_message_header_t header; + /* param1 - Request Attributes + * param2 - Handle */ + uint16_t chunk_seq_no; + uint16_t reserved; + uint32_t chunk_size; + + /* uint32_t large_message_size; + * uint8_t spdm_chunk[chunk_size]; */ +} spdm_chunk_send_request_t; + +#define SPDM_CHUNK_SEND_REQUEST_ATTRIBUTE_LAST_CHUNK (1 << 0) + +/* SPDM CHUNK_SEND_ACK response */ +typedef struct { + spdm_message_header_t header; + /* param1 - Response Attributes + * param2 - Handle */ + uint16_t chunk_seq_no; + /* uint8_t response_to_large_request[variable] */ +} spdm_chunk_send_ack_response_t; + +#define SPDM_CHUNK_SEND_ACK_RESPONSE_ATTRIBUTE_EARLY_ERROR_DETECTED (1 << 0) + +/* SPDM CHUNK_GET request */ +typedef struct { + spdm_message_header_t header; + /* param1 - Reserved + * param2 - Handle */ + uint16_t chunk_seq_no; +} spdm_chunk_get_request_t; + +/* SPDM CHUNK_RESPONSE response */ +typedef struct { + spdm_message_header_t header; + /* param1 - Response Attributes + * param2 - Handle */ + uint16_t chunk_seq_no; + uint16_t reserved; + uint32_t chunk_size; + + /* uint32_t large_message_size; + * uint8_t spdm_chunk[chunk_size]; */ +} spdm_chunk_response_response_t; + +#define SPDM_CHUNK_GET_RESPONSE_ATTRIBUTE_LAST_CHUNK (1 << 0) + +#pragma pack() + +#define SPDM_VERSION_1_1_BIN_CONCAT_LABEL "spdm1.1 " +#define SPDM_VERSION_1_2_BIN_CONCAT_LABEL "spdm1.2 " +#define SPDM_BIN_STR_0_LABEL "derived" +#define SPDM_BIN_STR_1_LABEL "req hs data" +#define SPDM_BIN_STR_2_LABEL "rsp hs data" +#define SPDM_BIN_STR_3_LABEL "req app data" +#define SPDM_BIN_STR_4_LABEL "rsp app data" +#define SPDM_BIN_STR_5_LABEL "key" +#define SPDM_BIN_STR_6_LABEL "iv" +#define SPDM_BIN_STR_7_LABEL "finished" +#define SPDM_BIN_STR_8_LABEL "exp master" +#define SPDM_BIN_STR_9_LABEL "traffic upd" + +/** + * The maximum amount of time in microseconds the Responder has to provide a response + * to requests that do not require cryptographic processing. + **/ +#define SPDM_ST1_VALUE_US 100000 + +#define SPDM_OID_EXTENSION {0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x06} +#define SPDM_OID_HARDWARE_IDENTITY {0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x02} + +#endif /* SPDM_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h new file mode 100644 index 0000000000..70869e4cf5 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h @@ -0,0 +1,127 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Definitions of DSP0277 Secured Messages using SPDM Specification + * version 1.0.0 in Distributed Management Task Force (DMTF). + **/ + +#ifndef SPDM_SECURED_MESSAGE_H +#define SPDM_SECURED_MESSAGE_H + +#pragma pack(1) + + +/* ENC+AUTH session:*/ + +/* +-----------------+ + * | ApplicationData |----------------------------------------------------- + * +-----------------+ | + * V + * +---------------------------------+----------------------------------+-------+------+---+ + * |SPDM_SECURED_MESSAGE_ADATA_HEADER|SPDM_SECURED_MESSAGE_CIPHER_HEADER|AppData|Random|MAC| + * | SessionId | SeqNum (O) | Length | ApplicationDataLength | | (O) | | + * +---------------------------------+----------------------------------+-------+------+---+ + * | | | | + * --------------------------------- ------------------------------------------------- --- + * | | | + * V V V + * AssociatedData EncryptedData AeadTag + */ + +/* (O) means Optional or Transport Layer Specific.*/ + +/* AUTH session:*/ + +/* +-----------------+ + * | ApplicationData |------------------ + * +-----------------+ | + * V + * +---------------------------------+-------+---+ + * |SPDM_SECURED_MESSAGE_ADATA_HEADER|AppData|MAC| + * | SessionId | SeqNum (T) | length | | | + * +---------------------------------+-------+---+ + * | | | + * ----------------------------------------- --- + * | | + * V V + * AssociatedData AeadTag + */ + + +typedef struct { + uint32_t session_id; +} spdm_secured_message_a_data_header1_t; + +/* The length of sequence_number between HEADER_1 and HEADER_2 is transport specific.*/ + +typedef struct { + uint16_t length; /* The length of the remaining data, including application_data_length(O), payload, Random(O) and MAC.*/ +} spdm_secured_message_a_data_header2_t; + +typedef struct { + uint16_t application_data_length; /* The length of the payload*/ +} spdm_secured_message_cipher_header_t; + + +/* Secured Messages opaque data format*/ + +#define SECURED_MESSAGE_OPAQUE_DATA_SPEC_ID 0x444D5446 +#define SECURED_MESSAGE_OPAQUE_VERSION 0x1 + +typedef struct { + uint32_t spec_id; /* SECURED_MESSAGE_OPAQUE_DATA_SPEC_ID*/ + uint8_t opaque_version; /* SECURED_MESSAGE_OPAQUE_VERSION*/ + uint8_t total_elements; + uint16_t reserved; + /*opaque_element_table_t opaque_list[];*/ +} secured_message_general_opaque_data_table_header_t; + +typedef struct { + uint8_t id; + uint8_t vendor_len; + /*uint8_t vendor_id[vendor_len]; + * uint16_t opaque_element_data_len; + * uint8_t opaque_element_data[opaque_element_data_len]; + * uint8_t align_padding[];*/ +} opaque_element_table_header_t; + +#define SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION 0x1 + +typedef struct { + uint8_t id; /* SPDM_REGISTRY_ID_DMTF*/ + uint8_t vendor_len; + uint16_t opaque_element_data_len; + /*uint8_t sm_data_version; + * uint8_t sm_data_id; + * uint8_t sm_data[];*/ +} secured_message_opaque_element_table_header_t; + +typedef struct { + uint8_t sm_data_version; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION*/ + uint8_t sm_data_id; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_VERSION_SELECTION*/ +} secured_message_opaque_element_header_t; + +#define SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_VERSION_SELECTION 0x0 + +typedef struct { + uint8_t sm_data_version; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION*/ + uint8_t sm_data_id; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_VERSION_SELECTION*/ + spdm_version_number_t selected_version; +} secured_message_opaque_element_version_selection_t; + +#define SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_SUPPORTED_VERSION 0x1 + +typedef struct { + uint8_t sm_data_version; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION*/ + uint8_t sm_data_id; /* SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_SUPPORTED_VERSION*/ + uint8_t version_count; + /*spdm_version_number_t versions_list[version_count];*/ +} secured_message_opaque_element_supported_version_t; + +#pragma pack() + +#endif /* SPDM_SECURED_MESSAGE_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h new file mode 100644 index 0000000000..f33d915985 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h @@ -0,0 +1,1298 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_COMMON_LIB_INTERNAL_H +#define SPDM_COMMON_LIB_INTERNAL_H + +#include "library/spdm_common_lib.h" +#include "library/spdm_secured_message_lib.h" +#include "library/spdm_return_status.h" +#include "library/spdm_crypt_lib.h" +#include "library/spdm_device_secret_lib.h" + +#define INVALID_SESSION_ID 0 + +typedef struct { + uint8_t spdm_version_count; + spdm_version_number_t spdm_version[SPDM_MAX_VERSION_COUNT]; +} libspdm_device_version_t; + +typedef struct { + uint8_t ct_exponent; + uint64_t rtt; + uint32_t st1; + uint32_t flags; + uint32_t data_transfer_size; + uint32_t max_spdm_msg_size; +} libspdm_device_capability_t; + +typedef struct { + uint8_t measurement_spec; + uint8_t other_params_support; + uint32_t measurement_hash_algo; + uint32_t base_asym_algo; + uint32_t base_hash_algo; + uint16_t dhe_named_group; + uint16_t aead_cipher_suite; + uint16_t req_base_asym_alg; + uint16_t key_schedule; +} libspdm_device_algorithm_t; + +typedef struct { +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t buffer[LIBSPDM_MAX_CERT_CHAIN_SIZE]; + size_t buffer_size; +#else + uint8_t buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t buffer_hash_size; + /* leaf cert public key of the peer */ + void *leaf_cert_public_key; +#endif +} libspdm_peer_used_cert_chain_t; + +typedef struct { + /* Local device info */ + libspdm_device_version_t version; + libspdm_device_capability_t capability; + libspdm_device_algorithm_t algorithm; + libspdm_device_version_t secured_message_version; + + /* My Certificate */ + const void *local_cert_chain_provision[SPDM_MAX_SLOT_COUNT]; + size_t local_cert_chain_provision_size[SPDM_MAX_SLOT_COUNT]; + /* My provisioned certificate (for slot_id - 0xFF, default 0)*/ + uint8_t provisioned_slot_id; + + /* Peer Root Certificate */ + const void *peer_root_cert_provision[LIBSPDM_MAX_ROOT_CERT_SUPPORT]; + size_t peer_root_cert_provision_size[LIBSPDM_MAX_ROOT_CERT_SUPPORT]; + + /* Peer CertificateChain + * Whether it contains the root certificate or not, + * it should be equal to the one returned from peer by get_certificate*/ + const void *peer_cert_chain_provision; + size_t peer_cert_chain_provision_size; + + /* Peer Cert verify*/ + libspdm_verify_spdm_cert_chain_func verify_peer_spdm_cert_chain; + + /* PSK provision locally*/ + size_t psk_hint_size; + const void *psk_hint; + + /* opaque_data provision locally*/ + size_t opaque_challenge_auth_rsp_size; + uint8_t *opaque_challenge_auth_rsp; + size_t opaque_measurement_rsp_size; + uint8_t *opaque_measurement_rsp; + + /* Responder policy*/ + bool basic_mut_auth_requested; + uint8_t mut_auth_requested; + uint8_t heartbeat_period; + + /*The device role*/ + bool is_requester; +} libspdm_local_context_t; + +typedef struct { + /* Connection State */ + libspdm_connection_state_t connection_state; + + /* Peer device info (negotiated) */ + spdm_version_number_t version; + libspdm_device_capability_t capability; + libspdm_device_algorithm_t algorithm; + spdm_version_number_t secured_message_version; + + /* Peer digests buffer */ + uint8_t peer_digest_slot_mask; + uint8_t peer_total_digest_buffer[LIBSPDM_MAX_HASH_SIZE * SPDM_MAX_SLOT_COUNT]; + + /* Peer CertificateChain */ + libspdm_peer_used_cert_chain_t peer_used_cert_chain[SPDM_MAX_SLOT_COUNT]; + uint8_t peer_used_cert_chain_slot_id; + + /* Local Used CertificateChain (for responder, or requester in mut auth) */ + const uint8_t *local_used_cert_chain_buffer; + size_t local_used_cert_chain_buffer_size; +} libspdm_connection_info_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + /*uint8_t buffer[max_buffer_size];*/ +} libspdm_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; +} libspdm_large_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE]; +} libspdm_medium_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; +} libspdm_small_managed_buffer_t; + +/* signature = Sign(SK, hash(M1)) + * Verify(PK, hash(M2), signature)*/ + +/* M1/M2 = Concatenate (A, B, C) + * A = Concatenate (GET_VERSION, VERSION, GET_CAPABILITIES, CAPABILITIES, NEGOTIATE_ALGORITHMS, ALGORITHMS) + * B = Concatenate (GET_DIGEST, DIGEST, GET_CERTFICATE, CERTIFICATE) + * C = Concatenate (CHALLENGE, CHALLENGE_AUTH\signature)*/ + +/* Mut M1/M2 = Concatenate (MutB, MutC) + * MutB = Concatenate (GET_DIGEST, DIGEST, GET_CERTFICATE, CERTIFICATE) + * MutC = Concatenate (CHALLENGE, CHALLENGE_AUTH\signature)*/ + +/* signature = Sign(SK, hash(L1)) + * Verify(PK, hash(L2), signature)*/ + +/* L1/L2 = Concatenate (M) + * M = Concatenate (GET_MEASUREMENT, MEASUREMENT\signature)*/ + +typedef struct { + /* the message_a must be plan text because we do not know the algorithm yet.*/ + libspdm_small_managed_buffer_t message_a; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t message_b; + libspdm_small_managed_buffer_t message_c; + libspdm_large_managed_buffer_t message_mut_b; + libspdm_small_managed_buffer_t message_mut_c; + libspdm_large_managed_buffer_t message_m; +#else + void *digest_context_m1m2; + void *digest_context_mut_m1m2; + void *digest_context_l1l2; +#endif +} libspdm_transcript_t; + +/* TH for KEY_EXCHANGE response signature: Concatenate (A, Ct, K) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response\signature+verify_data)*/ + +/* TH for KEY_EXCHANGE response HMAC: Concatenate (A, Ct, K) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response\verify_data)*/ + +/* TH for FINISH request signature: Concatenate (A, Ct, K, CM, F) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response)*/ +/* CM = mutual certificate chain * + * F = Concatenate (FINISH request\signature+verify_data)*/ + +/* TH for FINISH response HMAC: Concatenate (A, Ct, K, CM, F) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response)*/ +/* CM = mutual certificate chain * + * F = Concatenate (FINISH request\verify_data)*/ + +/* th1: Concatenate (A, Ct, K) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response)*/ + +/* th2: Concatenate (A, Ct, K, CM, F) + * Ct = certificate chain + * K = Concatenate (KEY_EXCHANGE request, KEY_EXCHANGE response)*/ +/* CM = mutual certificate chain * + * F = Concatenate (FINISH request, FINISH response)*/ + +/* TH for PSK_EXCHANGE response HMAC: Concatenate (A, K) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response\verify_data)*/ + +/* TH for PSK_FINISH response HMAC: Concatenate (A, K, F) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response) + * F = Concatenate (PSK_FINISH request\verify_data)*/ + +/* TH1_PSK1: Concatenate (A, K) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response\verify_data)*/ + +/* TH1_PSK2: Concatenate (A, K, F) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response) + * F = Concatenate (PSK_FINISH request\verify_data)*/ + +/* TH2_PSK: Concatenate (A, K, F) + * K = Concatenate (PSK_EXCHANGE request, PSK_EXCHANGE response) + * F = Concatenate (PSK_FINISH request, PSK_FINISH response)*/ + +typedef struct { +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t message_k; + libspdm_large_managed_buffer_t message_f; + libspdm_large_managed_buffer_t message_m; +#else + bool message_f_initialized; + void *digest_context_th; + void *digest_context_l1l2; + /* this is back up for message F reset.*/ + void *digest_context_th_backup; +#endif +} libspdm_session_transcript_t; + +typedef struct { + uint32_t session_id; + bool use_psk; + uint8_t mut_auth_requested; + uint8_t end_session_attributes; + uint8_t session_policy; + uint8_t heartbeat_period; + libspdm_session_transcript_t session_transcript; + /* Register for the last KEY_UPDATE token and operation (responder only)*/ + spdm_key_update_request_t last_key_update_request; + void *secured_message_context; +} libspdm_session_info_t; + +#define LIBSPDM_MAX_ENCAP_REQUEST_OP_CODE_SEQUENCE_COUNT 3 +typedef struct { + /* Valid OpCode: GET_DIEGST/GET_CERTIFICATE/CHALLENGE/KEY_UPDATE + * The last one is 0x00, as terminator.*/ + uint8_t request_op_code_sequence[LIBSPDM_MAX_ENCAP_REQUEST_OP_CODE_SEQUENCE_COUNT + 1]; + uint8_t request_op_code_count; + uint8_t current_request_op_code; + uint8_t request_id; + uint8_t req_slot_id; + spdm_message_header_t last_encap_request_header; + size_t last_encap_request_size; + uint16_t cert_chain_total_len; + libspdm_large_managed_buffer_t certificate_chain_buffer; +} libspdm_encap_context_t; + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP +typedef struct { + bool chunk_in_use; + uint8_t chunk_handle; + uint16_t chunk_seq_no; + size_t chunk_bytes_transferred; + + void* large_message; + size_t large_message_size; + size_t large_message_capacity; +} libspdm_chunk_info_t; + +typedef struct { + libspdm_chunk_info_t send; + libspdm_chunk_info_t get; +} libspdm_chunk_context_t; +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +#if LIBSPDM_ENABLE_MSG_LOG +typedef struct { + void *buffer; + size_t max_buffer_size; + uint32_t mode; + size_t buffer_size; + uint32_t status; +} libspdm_msg_log_t; +#endif /* LIBSPDM_ENABLE_MSG_LOG */ + +#define libspdm_context_struct_version 0x2 + +typedef struct { + uint32_t version; + + /* IO information */ + libspdm_device_send_message_func send_message; + libspdm_device_receive_message_func receive_message; + + /* + * reserved for request and response in the main dispatch function in SPDM responder. + * this buffer is the transport message recived from spdm_context->receive_message() + * or sent to spdm_context->send_message(). + * This message may be SPDM transport message or secured SPDM transport message. + **/ + libspdm_device_acquire_sender_buffer_func acquire_sender_buffer; + libspdm_device_release_sender_buffer_func release_sender_buffer; + libspdm_device_acquire_receiver_buffer_func acquire_receiver_buffer; + libspdm_device_release_receiver_buffer_func release_receiver_buffer; + + /* Transport Layer information */ + libspdm_transport_encode_message_func transport_encode_message; + libspdm_transport_decode_message_func transport_decode_message; + libspdm_transport_get_header_size_func transport_get_header_size; + + /* Cached plain text command + * If the command is cipher text, decrypt then cache it. */ + uint8_t last_spdm_request[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t last_spdm_request_size; + + /* scratch buffer */ + uint8_t *scratch_buffer; + size_t scratch_buffer_size; + /* sender buffer */ + uint8_t *sender_buffer; + size_t sender_buffer_size; + /* receiver buffer */ + uint8_t *receiver_buffer; + size_t receiver_buffer_size; + + /* Cache session_id in this spdm_message, only valid for secured message. */ + uint32_t last_spdm_request_session_id; + bool last_spdm_request_session_id_valid; + + /* Cache the error in libspdm_process_request. It is handled in libspdm_build_response. */ + libspdm_error_struct_t last_spdm_error; + + /* Register GetResponse function (responder only) */ + size_t get_response_func; + + /* Register GetEncapResponse function (requester only) */ + size_t get_encap_response_func; + libspdm_encap_context_t encap_context; + + /* Register spdm_session_state_callback function (responder only) + * Register can know the state after StartSession / EndSession. */ + size_t spdm_session_state_callback[LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM]; + + /* Register spdm_connection_state_callback function (responder only) + * Register can know the connection state such as negotiated. */ + size_t spdm_connection_state_callback[LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM]; + + /* Register libspdm_key_update_callback function (responder only) + * Register can know when session keys are updated during KEY_UPDATE operations. */ + size_t spdm_key_update_callback[LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM]; + + libspdm_local_context_t local_context; + + libspdm_connection_info_t connection_info; + libspdm_transcript_t transcript; + + libspdm_session_info_t session_info[LIBSPDM_MAX_SESSION_COUNT]; + + /* Cache lastest session ID for HANDSHAKE_IN_THE_CLEAR */ + uint32_t latest_session_id; + + /* Register for Responder state, be initial to Normal (responder only) */ + libspdm_response_state_t response_state; + + /* Cached data for SPDM_ERROR_CODE_RESPONSE_NOT_READY/SPDM_RESPOND_IF_READY */ + spdm_error_data_response_not_ready_t error_data; + uint8_t cache_spdm_request[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t cache_spdm_request_size; + uint8_t current_token; + + /* Register for the retry times when receive "BUSY" Error response (requester only) */ + uint8_t retry_times; + bool crypto_request; + + /* App context data for use by application */ + void *app_context_data_ptr; + + /* See LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY_*. */ + uint8_t handle_error_return_policy; + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* Chunk specific context */ + libspdm_chunk_context_t chunk_context; +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +#if LIBSPDM_ENABLE_MSG_LOG + libspdm_msg_log_t msg_log; +#endif /* LIBSPDM_ENABLE_MSG_LOG */ +} libspdm_context_t; + +#define LIBSPDM_CONTEXT_SIZE_WITHOUT_SECURED_CONTEXT (sizeof(libspdm_context_t)) +#define LIBSPDM_CONTEXT_SIZE_ALL (LIBSPDM_CONTEXT_SIZE_WITHOUT_SECURED_CONTEXT + \ + LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE * LIBSPDM_MAX_SESSION_COUNT) + +#if LIBSPDM_DEBUG_PRINT_ENABLE +/** + * This function dump raw data. + * + * @param data raw data + * @param size raw data size + **/ +void libspdm_internal_dump_hex_str(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_HEX_STR(data, size) libspdm_internal_dump_hex_str(data, size) + +/** + * This function dump raw data. + * + * @param data raw data + * @param size raw data size + **/ +void libspdm_internal_dump_data(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_DATA(data, size) libspdm_internal_dump_data(data, size) + +/** + * This function dump raw data with colume format. + * + * @param data raw data + * @param size raw data size + **/ +void libspdm_internal_dump_hex(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_HEX(data, size) libspdm_internal_dump_hex(data, size) + +#else /* LIBSPDM_DEBUG_PRINT_ENABLE */ +#define LIBSPDM_INTERNAL_DUMP_HEX(data, size) +#define LIBSPDM_INTERNAL_DUMP_HEX_STR(data, size) +#define LIBSPDM_INTERNAL_DUMP_DATA(data, size) +#endif /* LIBSPDM_DEBUG_PRINT_ENABLE */ + +/** + * Append a new data buffer to the managed buffer. + * + * @param managed_buffer The managed buffer to be appended. + * @param buffer The address of the data buffer to be appended to the managed buffer. + * @param buffer_size The size in bytes of the data buffer to be appended to the managed buffer. + * + * @retval RETURN_SUCCESS The new data buffer is appended to the managed buffer. + * @retval RETURN_BUFFER_TOO_SMALL The managed buffer is too small to be appended. + **/ +libspdm_return_t libspdm_append_managed_buffer(void *managed_buffer, + const void *buffer, size_t buffer_size); + +/** + * Reset the managed buffer. + * The buffer_size is reset to 0. + * The max_buffer_size is unchanged. + * The buffer is not freed. + * + * @param managed_buffer The managed buffer to be shrinked. + **/ +void libspdm_reset_managed_buffer(void *managed_buffer); + +/** + * Return the size of managed buffer. + * + * @param managed_buffer The managed buffer. + * + * @return the size of managed buffer. + **/ +size_t libspdm_get_managed_buffer_size(void *managed_buffer); + +/** + * Return the address of managed buffer. + * + * @param managed_buffer The managed buffer. + * + * @return the address of managed buffer. + **/ +void *libspdm_get_managed_buffer(void *managed_buffer); + +/** + * Init the managed buffer. + * + * @param managed_buffer The managed buffer. + * @param max_buffer_size The maximum size in bytes of the managed buffer. + **/ +void libspdm_init_managed_buffer(void *managed_buffer, size_t max_buffer_size); + +/** + * Reset message buffer in SPDM context according to request code. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param spdm_request The SPDM request code. + */ +void libspdm_reset_message_buffer_via_request_code(void *context, void *session_info, + uint8_t request_code); + +/** + * This function initializes the session info. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + **/ +void libspdm_session_info_init(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint32_t session_id, bool use_psk); + +/** + * Set the psk_hint to a session info. + * + * @param session_info A pointer to a session info. + * @param psk_hint Indicate the PSK hint. + * @param psk_hint_size The size in bytes of the PSK hint. + */ +void libspdm_session_info_set_psk_hint(libspdm_session_info_t *session_info, + const void *psk_hint, + size_t psk_hint_size); + +/** + * This function returns if a given version is supported based upon the GET_VERSION/VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * @param version The SPDM version. + * + * @retval true the version is supported. + * @retval false the version is not supported. + **/ +bool libspdm_is_version_supported(const libspdm_context_t *spdm_context, uint8_t version); + +/** + * This function returns connection version negotiated by GET_VERSION/VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * + * @return the connection version. + **/ +uint8_t libspdm_get_connection_version(const libspdm_context_t *spdm_context); + +/** + * This function returns if a capablities flag is supported in current SPDM connection. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Is the function called from a requester. + * @param requester_capabilities_flag The requester capabilities flag to be checked + * @param responder_capabilities_flag The responder capabilities flag to be checked + * + * @retval true the capablities flag is supported. + * @retval false the capablities flag is not supported. + **/ +bool libspdm_is_capabilities_flag_supported(const libspdm_context_t *spdm_context, + bool is_requester, + uint32_t requester_capabilities_flag, + uint32_t responder_capabilities_flag); + +/** + * This function generates the certificate chain hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The slot index of the certificate chain. + * @param signature The buffer to store the certificate chain hash. + * + * @retval true certificate chain hash is generated. + * @retval false certificate chain hash is not generated. + **/ +bool libspdm_generate_cert_chain_hash(libspdm_context_t *spdm_context, + size_t slot_id, uint8_t *hash); + +/** + * This function verifies the digest. + * + * @param spdm_context A pointer to the SPDM context. + * @param digest The digest data buffer. + * @param digest_count size of the digest data buffer. + * + * @retval true digest verification pass. + * @retval false digest verification fail. + **/ +bool libspdm_verify_peer_digests(libspdm_context_t *spdm_context, + const void *digest, size_t digest_count); + +/** + * This function verifies peer certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * @param is_requester Indicates if it is a requester message. + * + * @retval true Peer certificate chain buffer verification passed. + * @retval false Peer certificate chain buffer verification failed. + **/ +bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + const void **trust_anchor, + size_t *trust_anchor_size, + bool is_requester); + +/** + * This function generates the challenge signature based upon m1m2 for authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Indicate of the signature generation for a requester or a responder. + * @param signature The buffer to store the challenge signature. + * + * @retval true challenge signature is generated. + * @retval false challenge signature is not generated. + **/ +bool libspdm_generate_challenge_auth_signature(libspdm_context_t *spdm_context, + bool is_requester, + uint8_t *signature); + +/** + * This function verifies the certificate chain hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param certificate_chain_hash The certificate chain hash data buffer. + * @param certificate_chain_hash_size size in bytes of the certificate chain hash data buffer. + * + * @retval true hash verification pass. + * @retval false hash verification fail. + **/ +bool libspdm_verify_certificate_chain_hash(libspdm_context_t *spdm_context, + const void *certificate_chain_hash, + size_t certificate_chain_hash_size); + +/** + * This function verifies the challenge signature based upon m1m2. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Indicate of the signature verification for a requester or a responder. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_challenge_auth_signature(libspdm_context_t *spdm_context, + bool is_requester, + const void *sign_data, + size_t sign_data_size); + +/** + * This function calculate the measurement summary hash size. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Is the function called from a requester. + * @param measurement_summary_hash_type The type of the measurement summary hash. + * + * @return 0 measurement summary hash type is invalid, NO_MEAS hash type or no MEAS capabilities. + * @return measurement summary hash size according to type. + **/ +uint32_t libspdm_get_measurement_summary_hash_size(libspdm_context_t *spdm_context, + bool is_requester, + uint8_t measurement_summary_hash_type); + +/* + * This function calculates l1l2. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param l1l2 The buffer to store the l1l2. + * + * @retval RETURN_SUCCESS l1l2 is calculated. + */ +bool libspdm_calculate_l1l2(void *context, void *session_info, + libspdm_large_managed_buffer_t *l1l2); + +/* + * This function calculates l1l2 hash. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param l1l2_hash_size size in bytes of the l1l2 hash + * @param l1l2_hash The buffer to store the l1l2 hash + * + * @retval RETURN_SUCCESS l1l2 is calculated. + */ +bool libspdm_calculate_l1l2_hash(void *context, void *session_info, + size_t *l1l2_hash_size, void *l1l2_hash); + +/** + * Get element from multi element opaque data by element id. + * + * This function should be called in + * libspdm_process_opaque_data_supported_version_data/libspdm_process_opaque_data_version_selection_data. + * + * @param[in] data_in_size Size of multi element opaque data. + * @param[in] data_in A pointer to the multi element opaque data. + * @param[in] element_id Element id. + * @param[in] sm_data_id ID for the Secured Message data type. + * @param[out] get_element_ptr Pointer to store finded element. + * + * @retval true Get element successfully + * @retval false Get element failed + **/ +bool libspdm_get_element_from_opaque_data(libspdm_context_t *spdm_context, + size_t data_in_size, const void *data_in, + uint8_t element_id, uint8_t sm_data_id, + const void **get_element_ptr, size_t *get_element_len); + +/** + * Return the size in bytes of opaque data supported version. + * + * This function should be called in libspdm_process_opaque_data_supported_version_data. + * + * @param version_count Secure version count. + * + * @return The size in bytes of opaque data supported version. + **/ +size_t libspdm_get_untrusted_opaque_data_supported_version_data_size( + libspdm_context_t *spdm_context, uint8_t version_count); + +/** + * Return the size in bytes of opaque data supproted version. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request generation. + * + * @return the size in bytes of opaque data supproted version. + **/ +size_t libspdm_get_opaque_data_supported_version_data_size(libspdm_context_t *spdm_context); + +/** + * Return the size in bytes of opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response generation. + * + * @return the size in bytes of opaque data version selection. + **/ +size_t libspdm_get_opaque_data_version_selection_data_size(const libspdm_context_t *spdm_context); + +/** + * Return the SPDMversion field of the version number struct. + * + * @param ver Spdm version number struct. + * + * @return the SPDMversion of the version number struct. + **/ +uint8_t libspdm_get_version_from_version_number(const spdm_version_number_t ver); + +/** + * Sort SPDMversion in descending order. + * + * @param spdm_context A pointer to the SPDM context. + * @param ver_set A pointer to the version set. + * @param ver_num Version number. + */ +void libspdm_version_number_sort(spdm_version_number_t *ver_set, size_t ver_num); + +/** + * Negotiate SPDMversion for connection. + * ver_set is the local version set of requester, res_ver_set is the version set of responder. + * + * @param common_version A pointer to store the common version. + * @param req_ver_set A pointer to the requester version set. + * @param req_ver_num Version number of requester. + * @param res_ver_set A pointer to the responder version set. + * @param res_ver_num Version number of responder. + * + * @retval true Negotiation successfully, connect version be saved to common_version. + * @retval false Negotiation failed. + */ +bool libspdm_negotiate_connection_version(spdm_version_number_t *common_version, + spdm_version_number_t *req_ver_set, + size_t req_ver_num, + const spdm_version_number_t *res_ver_set, + size_t res_ver_num); + +/** + * Acquire a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param max_msg_size size in bytes of the maximum size of sender buffer. + * @param msg_buf_ptr A pointer to a sender buffer. + * + * @retval RETURN_SUCCESS The sender buffer is acquired. + **/ +libspdm_return_t libspdm_acquire_sender_buffer ( + libspdm_context_t *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + +/** + * Release a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The sender buffer is Released. + **/ +void libspdm_release_sender_buffer (libspdm_context_t *spdm_context); + +/** + * Get the sender buffer. + * + * @param context A pointer to the SPDM context. + * @param sender_buffer Buffer address of the sender buffer. + * @param sender_buffer_size Size of the sender buffer. + * + **/ +void libspdm_get_sender_buffer ( + libspdm_context_t *spdm_context, + void **sender_buffer, + size_t *sender_buffer_size); + +/** + * Acquire a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param max_msg_size size in bytes of the maximum size of receiver buffer. + * @param msg_buf_pt A pointer to a receiver buffer. + * + * @retval RETURN_SUCCESS The receiver buffer is acquired. + **/ +libspdm_return_t libspdm_acquire_receiver_buffer ( + libspdm_context_t *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + +/** + * Release a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The receiver buffer is Released. + **/ +void libspdm_release_receiver_buffer (libspdm_context_t *spdm_context); + +/** + * Get the receiver buffer. + * + * @param context A pointer to the SPDM context. + * @param receiver_buffer Buffer address of the receiver buffer. + * @param receiver_buffer_size Size of the receiver buffer. + * + **/ +void libspdm_get_receiver_buffer ( + libspdm_context_t *spdm_context, + void **receiver_buffer, + size_t *receiver_buffer_size); + +/** + * Get the certificate slot mask + * + * @param[in] context A pointer to the SPDM context. + * + * @retval slot_mask get slot mask + **/ +uint8_t libspdm_get_cert_slot_mask (libspdm_context_t *spdm_context); + +/** + * Get the certificate slot count + * + * @param[in] context A pointer to the SPDM context. + * + * @retval slot_count get slot count + **/ +uint8_t libspdm_get_cert_slot_count(libspdm_context_t *spdm_context); + +#if LIBSPDM_ENABLE_MSG_LOG +void libspdm_append_msg_log(void *context, void *message, size_t message_size); +#endif + +/** + * Reset message A cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_a(void *spdm_context); + +/** + * Reset message B cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_b(void *spdm_context); + +/** + * Reset message C cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_c(void *spdm_context); + +/** + * Reset message MutB cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_mut_b(void *spdm_context); + +/** + * Reset message MutC cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_mut_c(void *spdm_context); + +/** + * Reset message M cache in SPDM context. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_m(void *context, void *session_info); + +/** + * Reset message K cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_k(void *context, void *spdm_session_info); + +/** + * Reset message F cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_f(void *context, void *spdm_session_info); + +/** + * Append message A cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_a(void *spdm_context, const void *message, + size_t message_size); +/** + * Append message B cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_b(void *spdm_context, const void *message, + size_t message_size); + +/** + * Append message C cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_c(void *spdm_context, const void *message, + size_t message_size); + +/** + * Append message MutB cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_mut_b(void *spdm_context, const void *message, + size_t message_size); + +/** + * Append message MutC cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_mut_c(void *spdm_context, const void *message, + size_t message_size); + +/** + * Append message M cache in SPDM context. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_m(void *context, void *session_info, + const void *message, size_t message_size); + +/** + * Append message K cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_k(void *context, void *spdm_session_info, + bool is_requester, const void *message, + size_t message_size); + +/** + * Append message F cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param message Message buffer. + * @param message_size Size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_f(void *context, void *spdm_session_info, + bool is_requester, const void *message, + size_t message_size); + +/** + * This function generates a session ID by concatenating req_session_id and rsp_session_id. + * + * @param[in] req_session_id + * @param[in] rsp_session_id + * + * @return Session ID. + **/ +uint32_t libspdm_generate_session_id(uint16_t req_session_id, uint16_t rsp_session_id); + +/** + * This function assigns a new session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return session info associated with this new session ID. + **/ +void *libspdm_assign_session_id(void *spdm_context, uint32_t session_id, bool use_psk); + +/** + * This function frees a session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + **/ +void libspdm_free_session_id(void *spdm_context, uint32_t session_id); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates current TH data with message A and message K. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * @param th_data_buffer_size Size in bytes of the th_data_buffer + * @param th_data_buffer The buffer to store the th_data_buffer + * + * @retval RETURN_SUCCESS current TH data is calculated. + */ +bool libspdm_calculate_th_for_exchange( + void *spdm_context, void *spdm_session_info, + const uint8_t *cert_chain_buffer, size_t cert_chain_buffer_size, + size_t *th_data_buffer_size, void *th_data_buffer); +#else +/* + * This function calculates current TH hash with message A and message K. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hash_buffer_size Size in bytes of the th_hash_buffer + * @param th_hash_buffer The buffer to store the th_hash_buffer + * + * @retval RETURN_SUCCESS current TH hash is calculated. + */ +bool libspdm_calculate_th_hash_for_exchange( + void *context, void *spdm_session_info, + size_t *th_hash_buffer_size, void *th_hash_buffer); + +/* + * This function calculates current TH hmac with message A and message K, with response finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size Size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_exchange_rsp( + void *context, void *spdm_session_info, bool is_requester, + size_t *th_hmac_buffer_size, void *th_hmac_buffer); +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates current TH data with message A, message K and message F. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * @param mut_cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header in mutual authentication. + * @param mut_cert_chain_buffer_size Size in bytes of the certitiface chain buffer in mutual authentication. + * @param th_data_buffer_size Size in bytes of the th_data_buffer. + * @param th_data_buffer The buffer to store the th_data_buffer + * + * @retval RETURN_SUCCESS current TH data is calculated. + */ +bool libspdm_calculate_th_for_finish(void *spdm_context, + void *spdm_session_info, + const uint8_t *cert_chain_buffer, + size_t cert_chain_buffer_size, + const uint8_t *mut_cert_chain_buffer, + size_t mut_cert_chain_buffer_size, + size_t *th_data_buffer_size, + void *th_data_buffer); +#else +/* + * This function calculates current TH hash with message A, message K and message F. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hash_buffer_size Size in bytes of the th_hash_buffer + * @param th_hash_buffer The buffer to store the th_hash_buffer + * + * @retval RETURN_SUCCESS current TH hash is calculated. + */ +bool libspdm_calculate_th_hash_for_finish(void *spdm_context, + void *spdm_session_info, + size_t *th_hash_buffer_size, + void *th_hash_buffer); + +/* + * This function calculates current TH hmac with message A, message K and message F, with response finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size Size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_finish_rsp(void *spdm_context, + void *spdm_session_info, + size_t *th_hmac_buffer_size, + void *th_hmac_buffer); + +/* + * This function calculates current TH hmac with message A, message K and message F, with request finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size Size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_finish_req(void *spdm_context, + void *spdm_session_info, + size_t *th_hmac_buffer_size, + void *th_hmac_buffer); +#endif + +/* + * This function calculates th1 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param th1_hash_data Th1 hash. + * + * @retval RETURN_SUCCESS th1 hash is calculated. + */ +bool libspdm_calculate_th1_hash(void *spdm_context, + void *spdm_session_info, + bool is_requester, + uint8_t *th1_hash_data); + +/* + * This function calculates th2 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param th1_hash_data Th2 hash + * + * @retval RETURN_SUCCESS th2 hash is calculated. + */ +bool libspdm_calculate_th2_hash(void *spdm_context, + void *spdm_session_info, + bool is_requester, + uint8_t *th2_hash_data); + +/** + * Reads a 24-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 24-bit value that may be unaligned. + * + * @return The 24-bit value read from buffer. + **/ +uint32_t libspdm_read_uint24(const uint8_t *buffer); + +/** + * Writes a 24-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 24-bit value that may be unaligned. + * @param value 24-bit value to write to buffer. + **/ +void libspdm_write_uint24(uint8_t *buffer, uint32_t value); + +/** + * Reads a 16-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 16-bit value that may be unaligned. + * + * @return The 16-bit value read from buffer. + **/ +uint16_t libspdm_read_uint16(const uint8_t *buffer); + +/** + * Writes a 16-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 16-bit value that may be unaligned. + * @param value 16-bit value to write to buffer. + **/ +void libspdm_write_uint16(uint8_t *buffer, uint16_t value); + +/** + * Reads a 32-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 32-bit value that may be unaligned. + * + * @return The 32-bit value read from buffer. + **/ +uint32_t libspdm_read_uint32(const uint8_t *buffer); + +/** + * Writes a 32-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 32-bit value that may be unaligned. + * @param value 32-bit value to write to buffer. + **/ +void libspdm_write_uint32(uint8_t *buffer, uint32_t value); + +/** + * Reads a 64-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 64-bit value that may be unaligned. + * + * @return The 64-bit value read from buffer. + **/ +uint64_t libspdm_read_uint64(const uint8_t *buffer); + +/** + * Writes a 64-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 64-bit value that may be unaligned. + * @param value 64-bit value to write to buffer. + **/ +void libspdm_write_uint64(uint8_t *buffer, uint64_t value); + +/** + * Determine if bitmask has at most one bit set. + * + * @param mask The bitmask to be tested. + * + * @return true At most one bit is set. + * @return false More than one bit is set. + */ +static inline bool libspdm_onehot0(uint32_t mask) +{ + return !mask || !(mask & (mask - 1)); +} + +#endif /* SPDM_COMMON_LIB_INTERNAL_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h new file mode 100644 index 0000000000..ee72761a29 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h @@ -0,0 +1,10 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "library/spdm_crypt_lib.h" +#include "hal/library/cryptlib.h" +#include "hal/library/debuglib.h" +#include "hal/library/memlib.h" diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h new file mode 100644 index 0000000000..69be506b04 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h @@ -0,0 +1,55 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef LIBSPDM_LIB_CONFIG_H +#define LIBSPDM_LIB_CONFIG_H + +#ifndef LIBSPDM_CONFIG +#include "library/spdm_lib_config.h" +#else +#include LIBSPDM_CONFIG +#endif + +#if defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) && \ + !defined(LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP) +#warning LIBSPDM_ENABLE_SET_CERTIFICATE_CAP is deprecated. Use \ + LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP instead. This warning will be removed in a \ + future release. +#endif /* defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) */ + +#if defined(LIBSPDM_ENABLE_CHUNK_CAP) && !defined(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) +#warning LIBSPDM_ENABLE_CHUNK_CAP is deprecated. Use LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP \ + instead. This warning will be removed in a future release. +#endif /* defined(LIBSPDM_ENABLE_CHUNK_CAP) */ + +#if defined(MDEPKG_NDEBUG) && !defined(LIBSPDM_DEBUG_ENABLE) +#warning MDEPKG_NDEBUG is deprecated. Use LIBSPDM_DEBUG_ENABLE \ + instead. This warning will be removed in a future release. +#endif /* defined(MDEPKG_NDEBUG) */ + +#if defined(LIBSPDM_DEBUG_ENABLE) +#undef LIBSPDM_DEBUG_ASSERT_ENABLE +#undef LIBSPDM_DEBUG_PRINT_ENABLE +#undef LIBSPDM_DEBUG_BLOCK_ENABLE + +#define LIBSPDM_DEBUG_ASSERT_ENABLE (LIBSPDM_DEBUG_ENABLE) +#define LIBSPDM_DEBUG_PRINT_ENABLE (LIBSPDM_DEBUG_ENABLE) +#define LIBSPDM_DEBUG_BLOCK_ENABLE (LIBSPDM_DEBUG_ENABLE) +#elif defined(MDEPKG_NDEBUG) +#undef LIBSPDM_DEBUG_ASSERT_ENABLE +#undef LIBSPDM_DEBUG_PRINT_ENABLE +#undef LIBSPDM_DEBUG_BLOCK_ENABLE + +#define LIBSPDM_DEBUG_ASSERT_ENABLE 0 +#define LIBSPDM_DEBUG_PRINT_ENABLE 0 +#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 +#endif /* defined(LIBSPDM_DEBUG_ENABLE) */ + +#if LIBSPDM_CHECK_MACRO +#include "internal/libspdm_macro_check.h" +#endif /* LIBSPDM_CHECK_MACRO */ + +#endif /* LIBSPDM_LIB_CONFIG_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h new file mode 100644 index 0000000000..93311336c5 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h @@ -0,0 +1,44 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef LIBSPDM_MACRO_CHECK_H +#define LIBSPDM_MACRO_CHECK_H + +#define LIBSPDM_ASYM_ALGO_SUPPORT \ + ((LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) || \ + (LIBSPDM_SM2_DSA_SUPPORT) || (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT)) + +#define LIBSPDM_DHE_ALGO_SUPPORT \ + ((LIBSPDM_FFDHE_SUPPORT) || (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT)) + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If KEY_EX_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If CERT_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If CHAL_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_DHE_ALGO_SUPPORT + #error If KEY_EX_CAP is enabled then at least one DHE algorithm must also be enabled. +#endif + +#if ((LIBSPDM_MAX_VERSION_COUNT) == 0) || ((LIBSPDM_MAX_VERSION_COUNT) > 255) + #error LIBSPDM_MAX_VERSION_COUNT must be between 1 and 255 inclusive. +#endif + +#if (LIBSPDM_MAX_SESSION_COUNT) > 65535 + #error LIBSPDM_MAX_SESSION_COUNT must be less than 65536. +#endif + +#undef LIBSPDM_ASYM_ALGO_SUPPORT +#undef LIBSPDM_DHE_ALGO_SUPPORT + +#endif /* LIBSPDM_MACRO_CHECK_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h new file mode 100644 index 0000000000..92bb147408 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h @@ -0,0 +1,555 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_REQUESTER_LIB_INTERNAL_H +#define SPDM_REQUESTER_LIB_INTERNAL_H + +#include "library/spdm_requester_lib.h" +#include "library/spdm_secured_message_lib.h" +#include "internal/libspdm_common_lib.h" + +/** + * This function handles simple error code. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code Indicate the error code. + * + * @retval RETURN_NO_RESPONSE If the error code is BUSY. + * @retval RETURN_DEVICE_ERROR If the error code is REQUEST_RESYNCH or others. + **/ +libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t error_code); + +/** + * This function handles the error response. + * + * The SPDM response code must be SPDM_ERROR. + * For error code RESPONSE_NOT_READY, this function sends RESPOND_IF_READY and receives an expected SPDM response. + * For error code BUSY, this function shrinks the managed buffer, and return RETURN_NO_RESPONSE. + * For error code REQUEST_RESYNCH, this function shrinks the managed buffer, clears connection_state, and return RETURN_DEVICE_ERROR. + * For error code DECRYPT_ERROR, end the session: free session id and session key, return RETURN_SECURITY_VIOLATION. + * For any other error code, this function shrinks the managed buffer, and return RETURN_DEVICE_ERROR. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param response_size The size of the response. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned. + * @param response The SPDM response message. + * @param original_request_code Indicate the original request code. + * @param expected_response_code Indicate the expected response code. + * @param expected_response_size Indicate the expected response size. + * + * @retval RETURN_SUCCESS The error code is RESPONSE_NOT_READY. The RESPOND_IF_READY is sent and an expected SPDM response is received. + * @retval RETURN_NO_RESPONSE The error code is BUSY. + * @retval RETURN_DEVICE_ERROR The error code is REQUEST_RESYNCH or others. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION The error code is DECRYPT_ERROR and session_id is NOT NULL. + **/ +libspdm_return_t libspdm_handle_error_response_main( + libspdm_context_t *spdm_context, const uint32_t *session_id, + size_t *response_size, void **response, + uint8_t original_request_code, uint8_t expected_response_code, + size_t expected_response_size); + +/** + * This function handles the error response handling for large responses. + * Will retrieve the large response in chunks if supported and necessary. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param inout_response_size The size of the response. + * On input, expected to be the size of an error response. + * On output, the large response size after being retrieved in chunks. + * @param response The error response on input. Large response on output. + * @param response_capacity The maximum capacity of the response buffer. + * + * @retval libspdm_return_t An error value or success. + **/ +libspdm_return_t libspdm_handle_error_large_response( + libspdm_context_t* spdm_context, + const uint32_t* session_id, + size_t* inout_response_size, + void* inout_response, + size_t response_capacity); + +/** + * This function sends GET_VERSION and receives VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The GET_VERSION is sent and the VERSION is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_get_version(libspdm_context_t *spdm_context, + uint8_t *version_number_entry_count, + spdm_version_number_t *version_number_entry); + +/** + * This function sends GET_CAPABILITIES and receives CAPABILITIES. + * + * @param spdm_context A pointer to the SPDM context. + * @param RequesterCTExponent RequesterCTExponent to the GET_CAPABILITIES request. + * @param RequesterFlags RequesterFlags to the GET_CAPABILITIES request. + * @param ResponderCTExponent ResponderCTExponent from the CAPABILITIES response. + * @param ResponderFlags ResponderFlags from the CAPABILITIES response. + * + * @retval RETURN_SUCCESS The GET_CAPABILITIES is sent and the CAPABILITIES is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_get_capabilities(libspdm_context_t *spdm_context); + +/** + * This function sends NEGOTIATE_ALGORITHMS and receives ALGORITHMS. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The NEGOTIATE_ALGORITHMS is sent and the ALGORITHMS is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_negotiate_algorithms(libspdm_context_t *spdm_context); + +#if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP +/** + * This function sends KEY_EXCHANGE and receives KEY_EXCHANGE_RSP for SPDM key exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type measurement_hash_type to the KEY_EXCHANGE request. + * @param slot_id slot_id to the KEY_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the KEY_EXCHANGE_RSP response. + * @param heartbeat_period heartbeat_period from the KEY_EXCHANGE_RSP response. + * @param req_slot_id_param req_slot_id_param from the KEY_EXCHANGE_RSP response. + * @param measurement_hash measurement_hash from the KEY_EXCHANGE_RSP response. + * + * @retval RETURN_SUCCESS The KEY_EXCHANGE is sent and the KEY_EXCHANGE_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_key_exchange( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash); + +/** + * This function sends KEY_EXCHANGE and receives KEY_EXCHANGE_RSP for SPDM key exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type measurement_hash_type to the KEY_EXCHANGE request. + * @param slot_id slot_id to the KEY_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the KEY_EXCHANGE_RSP response. + * @param heartbeat_period heartbeat_period from the KEY_EXCHANGE_RSP response. + * @param req_slot_id_param req_slot_id_param from the KEY_EXCHANGE_RSP response. + * @param measurement_hash measurement_hash from the KEY_EXCHANGE_RSP response. + * @param requester_random_in A buffer to hold the requester random (32 bytes) as input, if not NULL. + * @param requester_random A buffer to hold the requester random (32 bytes), if not NULL. + * @param responder_random A buffer to hold the responder random (32 bytes), if not NULL. + * + * @retval RETURN_SUCCESS The KEY_EXCHANGE is sent and the KEY_EXCHANGE_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_key_exchange_ex( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash, + const void *requester_random_in, + void *requester_random, + void *responder_random); + +/** + * This function sends FINISH and receives FINISH_RSP for SPDM finish. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the FINISH request. + * @param req_slot_id_param req_slot_id_param to the FINISH request. + * + * @retval RETURN_SUCCESS The FINISH is sent and the FINISH_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_finish(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t req_slot_id_param); +#endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +/** + * This function sends PSK_EXCHANGE and receives PSK_EXCHANGE_RSP for SPDM PSK exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type measurement_hash_type to the PSK_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the PSK_EXCHANGE_RSP response. + * @param heartbeat_period heartbeat_period from the PSK_EXCHANGE_RSP response. + * @param measurement_hash measurement_hash from the PSK_EXCHANGE_RSP response. + * + * @retval RETURN_SUCCESS The PSK_EXCHANGE is sent and the PSK_EXCHANGE_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_psk_exchange(libspdm_context_t *spdm_context, + uint8_t measurement_hash_type, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash); + +/** + * This function sends PSK_EXCHANGE and receives PSK_EXCHANGE_RSP for SPDM PSK exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type measurement_hash_type to the PSK_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the PSK_EXCHANGE_RSP response. + * @param heartbeat_period heartbeat_period from the PSK_EXCHANGE_RSP response. + * @param measurement_hash measurement_hash from the PSK_EXCHANGE_RSP response. + * @param requester_context_in A buffer to hold the requester context as input, if not NULL. + * @param requester_context_in_size The size of requester_context_in. + * It must be 32 bytes at least, but not exceed LIBSPDM_PSK_CONTEXT_LENGTH. + * @param requester_context A buffer to hold the requester context, if not NULL. + * @param requester_context_size On input, the size of requester_context buffer. + * On output, the size of data returned in requester_context buffer. + * It must be 32 bytes at least. + * @param responder_context A buffer to hold the responder context, if not NULL. + * @param responder_context_size On input, the size of requester_context buffer. + * On output, the size of data returned in requester_context buffer. + * It could be 0 if device does not support context. + * + * @retval RETURN_SUCCESS The PSK_EXCHANGE is sent and the PSK_EXCHANGE_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_psk_exchange_ex(libspdm_context_t *spdm_context, + uint8_t measurement_hash_type, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash, + const void *requester_context_in, + size_t requester_context_in_size, + void *requester_context, + size_t *requester_context_size, + void *responder_context, + size_t *responder_context_size); + +/** + * This function sends PSK_FINISH and receives PSK_FINISH_RSP for SPDM PSK finish. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the PSK_FINISH request. + * + * @retval RETURN_SUCCESS The PSK_FINISH is sent and the PSK_FINISH_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_psk_finish(libspdm_context_t *spdm_context, + uint32_t session_id); +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +/** + * This function sends END_SESSION and receives END_SESSION_ACK for SPDM session end. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the END_SESSION request. + * @param end_session_attributes end_session_attributes to the END_SESSION_ACK request. + * + * @retval RETURN_SUCCESS The END_SESSION is sent and the END_SESSION_ACK is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_end_session(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t end_session_attributes); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ + +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +/** + * This function executes a series of SPDM encapsulated requests and receives SPDM encapsulated responses. + * + * This function starts with the first encapsulated request (such as GET_ENCAPSULATED_REQUEST) + * and ends with last encapsulated response (such as RESPONSE_PAYLOAD_TYPE_ABSENT or RESPONSE_PAYLOAD_TYPE_SLOT_NUMBER). + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicate if the encapsulated request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param mut_auth_requested Indicate of the mut_auth_requested through KEY_EXCHANGE or CHALLENG response. + * @param req_slot_id_param req_slot_id_param from the RESPONSE_PAYLOAD_TYPE_REQ_SLOT_NUMBER. + * + * @retval RETURN_SUCCESS The SPDM Encapsulated requests are sent and the responses are received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_encapsulated_request(libspdm_context_t *spdm_context, + const uint32_t *session_id, + uint8_t mut_auth_requested, + uint8_t *req_slot_id_param); + +/** + * Process the SPDM encapsulated GET_DIGESTS request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_encap_response_digest(void *context, + size_t request_size, + void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM encapsulated GET_CERTIFICATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_encap_response_certificate(void *context, + size_t request_size, + void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM encapsulated CHALLENGE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_encap_response_challenge_auth( + void *context, size_t request_size, void *request, + size_t *response_size, void *response); + +/** + * Process the SPDM encapsulated KEY_UPDATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_encap_response_key_update(void *context, + size_t request_size, + void *request, + size_t *response_size, + void *response); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ + +/** + * Send an SPDM request to a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param request_size size in bytes of the request data buffer. + * @param request A pointer to a destination buffer to store the request. + * The caller is responsible for having + * either implicit or explicit ownership of the buffer. + * For normal message, requester pointer point to transport_message + transport header size + * For secured message, requester pointer will point to the scratch buffer + transport header size in spdm_context. + * + * @retval RETURN_SUCCESS The SPDM request is sent successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM request is sent to the device. + **/ +libspdm_return_t libspdm_send_spdm_request(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t request_size, void *request); + +/** + * Receive an SPDM response from a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the response is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param response_size size in bytes of the response data buffer. + * @param response A pointer to a destination buffer to store the response. + * The caller is responsible for having + * either implicit or explicit ownership of the buffer. + * For normal message, response pointer still point to original transport_message. + * For secured message, response pointer will point to the scratch buffer in spdm_context. + * + * @retval RETURN_SUCCESS The SPDM response is received successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM response is received from the device. + **/ +libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *response_size, + void **response); + +/** + * This function allocates half of session ID for a requester. + * + * @param spdm_context A pointer to the SPDM context. + * + * @return half of session ID for a requester. + **/ +uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context); + +/** + * Build opaque data supported version. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request generation. + * + * @param data_out_size Size in bytes of the data_out. + * On input, it means the size in bytes of data_out buffer. + * On output, it means the size in bytes of copied data_out buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired data_out buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param data_out A pointer to the desination buffer to store the opaque data supported version. + **/ +libspdm_return_t libspdm_build_opaque_data_supported_version_data(libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out); + +/** + * Process opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response parsing in requester. + * + * @param data_in_size Size in bytes of the data_in. + * @param data_in A pointer to the buffer to store the opaque data version selection. + **/ +libspdm_return_t libspdm_process_opaque_data_version_selection_data(libspdm_context_t *spdm_context, + size_t data_in_size, + void *data_in); + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +/** + * This function generates the finish signature based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param signature The buffer to store the finish signature. + * + * @retval true finish signature is generated. + * @retval false finish signature is not generated. + **/ +bool libspdm_generate_finish_req_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *signature); +#endif + +/** + * This function generates the finish HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac The buffer to store the finish HMAC. + * + * @retval true finish HMAC is generated. + * @retval false finish HMAC is not generated. + **/ +bool libspdm_generate_finish_req_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + void *hmac); + +/** + * This function verifies the finish HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac_data The HMAC data buffer. + * @param hmac_data_size Size in bytes of the HMAC data buffer. + * + * @retval true HMAC verification pass. + * @retval false HMAC verification fail. + **/ +bool libspdm_verify_finish_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *hmac_data, size_t hmac_data_size); + +/** + * This function verifies the key exchange HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac_data The HMAC data buffer. + * @param hmac_data_size Size in bytes of the HMAC data buffer. + * + * @retval true HMAC verification pass. + * @retval false HMAC verification fail. + **/ +bool libspdm_verify_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *hmac_data, + size_t hmac_data_size); + +/** + * This function verifies the key exchange signature based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_key_exchange_rsp_signature( + libspdm_context_t *spdm_context, libspdm_session_info_t *session_info, + const void *sign_data, const size_t sign_data_size); + +/** + * This function verifies the measurement signature based upon l1l2. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_measurement_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *sign_data, + size_t sign_data_size); + +#endif /* SPDM_REQUESTER_LIB_INTERNAL_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h new file mode 100644 index 0000000000..4aa211ead8 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h @@ -0,0 +1,870 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_RESPONDER_LIB_INTERNAL_H +#define SPDM_RESPONDER_LIB_INTERNAL_H + +#include "library/spdm_responder_lib.h" +#include "library/spdm_secured_message_lib.h" +#include "internal/libspdm_common_lib.h" + +/** + * Process the SPDM request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +typedef libspdm_return_t (*libspdm_get_spdm_response_func)( + void *spdm_context, size_t request_size, const void *request, + size_t *response_size, void *response); + +/** + * Build the response when the response state is incorrect. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_code The SPDM request code. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_responder_handle_response_state(void *spdm_context, + uint8_t request_code, + size_t *response_size, + void *response); + +/** + * Process the SPDM RESPONSE_IF_READY request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_respond_if_ready(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM GET_VERSION request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_version(void *spdm_context, + size_t request_size, const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM GET_CAPABILITIES request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_capabilities(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM NEGOTIATE_ALGORITHMS request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_algorithms(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP +/** + * Process the SPDM GET_DIGESTS request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_digests(void *spdm_context, + size_t request_size, const void *request, + size_t *response_size, + void *response); +/** + * Process the SPDM GET_CERTIFICATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ + +libspdm_return_t libspdm_get_response_certificate(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP +/** + * Process the SPDM CHALLENGE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_challenge_auth(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +/** + * Process the SPDM GET_MEASUREMENT request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_measurements(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP +/** + * Process the SPDM KEY_EXCHANGE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_key_exchange(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM FINISH request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_finish(void *spdm_context, + size_t request_size, const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +/** + * Process the SPDM PSK_EXCHANGE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_psk_exchange(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM PSK_FINISH request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_psk_finish(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +/** + * Process the SPDM END_SESSION request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_end_session(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM KEY_UPDATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_key_update(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); + +/** + * Process the SPDM HEARTBEAT request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_heartbeat(void *spdm_context, + size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ + +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +/** + * Process the SPDM ENCAPSULATED_REQUEST request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_encapsulated_request( + void *spdm_context, size_t request_size, const void *request, + size_t *response_size, void *response); + +/** + * Process the SPDM ENCAPSULATED_RESPONSE_ACK request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_encapsulated_response_ack( + void *spdm_context, size_t request_size, const void *request, + size_t *response_size, void *response); + +/** + * Get the SPDM encapsulated GET_DIGESTS request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the encapsulated request data. + * On input, it means the size in bytes of encapsulated request data buffer. + * On output, it means the size in bytes of copied encapsulated request data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired encapsulated request data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param encap_request A pointer to the encapsulated request data. + * + * @retval RETURN_SUCCESS The encapsulated request is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_encap_request_get_digest(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); + +/** + * Process the SPDM encapsulated DIGESTS response. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_response_size size in bytes of the encapsulated response data. + * @param encap_response A pointer to the encapsulated response data. + * @param need_continue Indicate if encapsulated communication need continue. + * + * @retval RETURN_SUCCESS The encapsulated response is processed. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_process_encap_response_digest( + libspdm_context_t *spdm_context, size_t encap_response_size, + const void *encap_response, bool *need_continue); + + +/** + * Get the SPDM encapsulated GET_CERTIFICATE request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the encapsulated request data. + * On input, it means the size in bytes of encapsulated request data buffer. + * On output, it means the size in bytes of copied encapsulated request data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired encapsulated request data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param encap_request A pointer to the encapsulated request data. + * + * @retval RETURN_SUCCESS The encapsulated request is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_encap_request_get_certificate(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); + +/** + * Process the SPDM encapsulated CERTIFICATE response. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_response_size size in bytes of the encapsulated response data. + * @param encap_response A pointer to the encapsulated response data. + * @param need_continue Indicate if encapsulated communication need continue. + * + * @retval RETURN_SUCCESS The encapsulated response is processed. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_process_encap_response_certificate( + libspdm_context_t *spdm_context, size_t encap_response_size, + const void *encap_response, bool *need_continue); + +/** + * Get the SPDM encapsulated CHALLENGE request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the encapsulated request data. + * On input, it means the size in bytes of encapsulated request data buffer. + * On output, it means the size in bytes of copied encapsulated request data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired encapsulated request data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param encap_request A pointer to the encapsulated request data. + * + * @retval RETURN_SUCCESS The encapsulated request is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_encap_request_challenge(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); + +/** + * Process the SPDM encapsulated CHALLENGE_AUTH response. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_response_size size in bytes of the encapsulated response data. + * @param encap_response A pointer to the encapsulated response data. + * @param need_continue Indicate if encapsulated communication need continue. + * + * @retval RETURN_SUCCESS The encapsulated response is processed. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_process_encap_response_challenge_auth( + libspdm_context_t *spdm_context, size_t encap_response_size, + const void *encap_response, bool *need_continue); + +/** + * Get the SPDM encapsulated KEY_UPDATE request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the encapsulated request data. + * On input, it means the size in bytes of encapsulated request data buffer. + * On output, it means the size in bytes of copied encapsulated request data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired encapsulated request data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param encap_request A pointer to the encapsulated request data. + * + * @retval RETURN_SUCCESS The encapsulated request is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t +libspdm_get_encap_request_key_update(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); + +/** + * Process the SPDM encapsulated KEY_UPDATE response. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_response_size size in bytes of the encapsulated response data. + * @param encap_response A pointer to the encapsulated response data. + * @param need_continue Indicate if encapsulated communication need continue. + * + * @retval RETURN_SUCCESS The encapsulated response is processed. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_process_encap_response_key_update( + libspdm_context_t *spdm_context, size_t encap_response_size, + const void *encap_response, bool *need_continue); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ + +/** + * Return the GET_SPDM_RESPONSE function via request code. + * + * @param request_code The SPDM request code. + * + * @return GET_SPDM_RESPONSE function according to the request code. + **/ +libspdm_get_spdm_response_func libspdm_get_response_func_via_request_code(uint8_t request_code); + +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +/** + * This function initializes the mut_auth encapsulated state. + * + * @param spdm_context A pointer to the SPDM context. + * @param mut_auth_requested Indicate of the mut_auth_requested through KEY_EXCHANGE response. + **/ +void libspdm_init_mut_auth_encap_state(libspdm_context_t *spdm_context, uint8_t mut_auth_requested); + +/** + * This function initializes the basic_mut_auth encapsulated state. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_init_basic_mut_auth_encap_state(libspdm_context_t *spdm_context); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ + +/** + * This function handles the encap error response. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code Indicate the error code. + * + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_handle_encap_error_response_main( + libspdm_context_t *spdm_context, uint8_t error_code); + +/** + * Set session_state to an SPDM secured message context and trigger callback. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicate the SPDM session ID. + * @param session_state Indicate the SPDM session state. + */ +void libspdm_set_session_state(libspdm_context_t *spdm_context, + uint32_t session_id, + libspdm_session_state_t session_state); + +/** + * Set connection_state to an SPDM context and trigger callback. + * + * @param spdm_context A pointer to the SPDM context. + * @param connection_state Indicate the SPDM connection state. + */ +void libspdm_set_connection_state(libspdm_context_t *spdm_context, + libspdm_connection_state_t connection_state); + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * Process the SPDM GET_CSR request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_csr(void *context, size_t request_size, + const void *request, size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP || LIBSPDM_ENABLE_SET_CERTIFICATE_CAP +/** + * Process the SPDM SET_CERTIFICATE request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_set_certificate(void *context, size_t request_size, + const void *request, + size_t *response_size, + void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP +/** + * Process the SPDM CHUNK_GET request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_chunk_get(void* context, + size_t request_size, + const void* request, + size_t* response_size, + void* response); + +/** + * Process the SPDM CHUNK_SEND request and return the response. + * + * @param spdm_context A pointer to the SPDM context. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_response_chunk_send(void* context, + size_t request_size, + const void* request, + size_t* response_size, + void* response); + +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +/** + * This function allocates half of session ID for a responder. + * + * @param spdm_context A pointer to the SPDM context. + * + * @return half of session ID for a responder. + **/ +uint16_t libspdm_allocate_rsp_session_id(const libspdm_context_t *spdm_context); + +/** + * Build opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response generation. + * + * @param data_out_size Size in bytes of the data_out. + * On input, it means the size in bytes of data_out buffer. + * On output, it means the size in bytes of copied data_out buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired data_out buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param data_out A pointer to the desination buffer to store the opaque data version selection. + **/ +libspdm_return_t +libspdm_build_opaque_data_version_selection_data(const libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out); + +/** + * Process opaque data supported version. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request parsing in responder. + * + * @param data_in_size Size in bytes of the data_in. + * @param data_in A pointer to the buffer to store the opaque data supported version. + **/ +libspdm_return_t +libspdm_process_opaque_data_supported_version_data(libspdm_context_t *spdm_context, + size_t data_in_size, + const void *data_in); + +/** + * This function verifies the finish HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac_data The HMAC data buffer. + * @param hmac_data_size Size in bytes of the HMAC data buffer. + * + * @retval true HMAC verification pass. + * @retval false HMAC verification fail. + **/ +bool libspdm_verify_finish_req_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const uint8_t *hmac, size_t hmac_size); + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +/** + * This function verifies the finish signature based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_finish_req_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *sign_data, + const size_t sign_data_size); +#endif + +/** + * This function generates the finish HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac The buffer to store the finish HMAC. + * + * @retval true finish HMAC is generated. + * @retval false finish HMAC is not generated. + **/ +bool libspdm_generate_finish_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *hmac); + +/** + * This function generates the key exchange HMAC based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param hmac The buffer to store the key exchange HMAC. + * + * @retval true key exchange HMAC is generated. + * @retval false key exchange HMAC is not generated. + **/ +bool libspdm_generate_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *hmac); + +/** + * This function generates the key exchange signature based upon TH. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The session info of an SPDM session. + * @param signature The buffer to store the key exchange signature. + * + * @retval true key exchange signature is generated. + * @retval false key exchange signature is not generated. + **/ +bool libspdm_generate_key_exchange_rsp_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *signature); + +/** + * This function generates the measurement signature to response message based upon l1l2. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param signature The buffer to store the signature. + * + * @retval true measurement signature is generated. + * @retval false measurement signature is not generated. + **/ +bool libspdm_generate_measurement_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *signature); + +#endif /* SPDM_RESPONDER_LIB_INTERNAL_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h new file mode 100644 index 0000000000..97d95f8411 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h @@ -0,0 +1,79 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_SECURED_MESSAGE_LIB_INTERNAL_H +#define SPDM_SECURED_MESSAGE_LIB_INTERNAL_H + +#include "library/spdm_secured_message_lib.h" +#include "library/spdm_crypt_lib.h" +#include "library/spdm_device_secret_lib.h" +#include "internal/libspdm_common_lib.h" +#include "hal/library/memlib.h" +#include "hal/library/cryptlib.h" + +typedef struct { + uint8_t dhe_secret[LIBSPDM_MAX_DHE_KEY_SIZE]; + uint8_t handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t master_secret[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_session_info_struct_master_secret_t; + +typedef struct { + uint8_t request_handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_finished_key[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_finished_key[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_handshake_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t request_handshake_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t request_handshake_sequence_number; + uint8_t response_handshake_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t response_handshake_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t response_handshake_sequence_number; +} libspdm_session_info_struct_handshake_secret_t; + +typedef struct { + uint8_t request_data_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_data_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_data_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t request_data_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t request_data_sequence_number; + uint8_t response_data_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t response_data_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t response_data_sequence_number; +} libspdm_session_info_struct_application_secret_t; + +typedef struct { + libspdm_session_type_t session_type; + spdm_version_number_t version; + spdm_version_number_t secured_message_version; + uint32_t base_hash_algo; + uint16_t dhe_named_group; + uint16_t aead_cipher_suite; + uint16_t key_schedule; + size_t hash_size; + size_t dhe_key_size; + size_t aead_key_size; + size_t aead_iv_size; + size_t aead_tag_size; + bool use_psk; + libspdm_session_state_t session_state; + libspdm_session_info_struct_master_secret_t master_secret; + libspdm_session_info_struct_handshake_secret_t handshake_secret; + libspdm_session_info_struct_application_secret_t application_secret; + libspdm_session_info_struct_application_secret_t application_secret_backup; + bool requester_backup_valid; + bool responder_backup_valid; + size_t psk_hint_size; + uint8_t psk_hint[LIBSPDM_PSK_MAX_HINT_LENGTH]; + uint8_t export_master_secret[LIBSPDM_MAX_HASH_SIZE]; + + /* Cache the error in libspdm_decode_secured_message. + * It is handled in libspdm_build_response. */ + libspdm_error_struct_t last_spdm_error; +} libspdm_secured_message_context_t; + +#define LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE (sizeof(libspdm_secured_message_context_t)) + +#endif /* SPDM_SECURED_MESSAGE_LIB_INTERNAL_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h new file mode 100644 index 0000000000..a72b696816 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h @@ -0,0 +1,795 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_COMMON_LIB_H +#define SPDM_COMMON_LIB_H + +#include "internal/libspdm_lib_config.h" +#include "hal/base.h" +#include "library/spdm_secured_message_lib.h" +#include "library/spdm_return_status.h" + +/* Connection: When a host sends messgages to a device, they create a connection. + * The host can and only can create one connection with one device. + * The host may create multiple connections with multiple devices at same time. + * A connection can be unique identified by the connected device. + * The message exchange in a connection is plain text.*/ + +/* Session: In one connection with one device, a host may create multiple sessions. + * The session starts with via KEY_EXCHANGE or PSK_EXCHANGE, and step with END_SESSION. + * A session can be unique identified by a session ID, returned from the device. + * The message exchange in a session is cipher text.*/ + +typedef enum { + /* SPDM parameter */ + LIBSPDM_DATA_SPDM_VERSION, + LIBSPDM_DATA_SECURED_MESSAGE_VERSION, + + /* SPDM capability */ + LIBSPDM_DATA_CAPABILITY_FLAGS, + LIBSPDM_DATA_CAPABILITY_CT_EXPONENT, + LIBSPDM_DATA_CAPABILITY_RTT_US, + LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE, + LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE, + + /* SPDM algorithm setting */ + LIBSPDM_DATA_MEASUREMENT_SPEC, + LIBSPDM_DATA_MEASUREMENT_HASH_ALGO, + LIBSPDM_DATA_BASE_ASYM_ALGO, + LIBSPDM_DATA_BASE_HASH_ALGO, + LIBSPDM_DATA_DHE_NAME_GROUP, + LIBSPDM_DATA_AEAD_CIPHER_SUITE, + LIBSPDM_DATA_REQ_BASE_ASYM_ALG, + LIBSPDM_DATA_KEY_SCHEDULE, + LIBSPDM_DATA_OTHER_PARAMS_SUPPORT, + + /* Connection State */ + LIBSPDM_DATA_CONNECTION_STATE, + + /* response_state */ + LIBSPDM_DATA_RESPONSE_STATE, + + /* Certificate info */ + LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN, + /* LIBSPDM_DATA_LOCAL_SLOT_COUNT is deprecated. Do not use it. Reserved only. */ + LIBSPDM_DATA_LOCAL_SLOT_COUNT, + LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT, + LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN, + LIBSPDM_DATA_BASIC_MUT_AUTH_REQUESTED, + LIBSPDM_DATA_MUT_AUTH_REQUESTED, + LIBSPDM_DATA_HEARTBEAT_PERIOD, + + /* Negotiated result */ + LIBSPDM_DATA_LOCAL_USED_CERT_CHAIN_BUFFER, + LIBSPDM_DATA_PEER_USED_CERT_CHAIN_BUFFER, + LIBSPDM_DATA_PEER_SLOT_MASK, + LIBSPDM_DATA_PEER_TOTAL_DIGEST_BUFFER, + + /* Pre-shared key Hint + * If PSK is present, then PSK_EXCHANGE is used. + * Otherwise, the KEY_EXCHANGE is used. */ + LIBSPDM_DATA_PSK_HINT, + + /* SessionData */ + LIBSPDM_DATA_SESSION_USE_PSK, + LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED, + LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES, + LIBSPDM_DATA_SESSION_POLICY, + + /* App context data that can be used by the application + * during callback functions such libspdm_device_send_message_func. */ + LIBSPDM_DATA_APP_CONTEXT_DATA, + + /** + * The LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY 0x00000001 control to generate SPDM_ERROR_CODE_DECRYPT_ERROR response or drop the request silently. + * If the 0x00000001 is not set, generate SPDM_ERROR_CODE_DECRYPT_ERROR response. + * If the 0x00000001 set, drop the request silently. + **/ + LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY, + + /* VCA cached for CACHE_CAP in 1.2 for transcript. */ + LIBSPDM_DATA_VCA_CACHE, + + /* My provisioned certificate slot_id (for slot_id - 0xFF, default 0)*/ + LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN_DEFAULT_SLOT_ID, + + /* if the context is for a requester. It only needs to be set in VCA cache. + * In normal flow, the value is set in GET_VERSION or VERSION automatically. + * false means responder + * true means requester + **/ + LIBSPDM_DATA_IS_REQUESTER, + + /* MAX */ + LIBSPDM_DATA_MAX +} libspdm_data_type_t; + +/** + * It controls to generate SPDM_ERROR_CODE_DECRYPT_ERROR response or drop the request silently. + * If the 0x1 is not set, generate SPDM_ERROR_CODE_DECRYPT_ERROR response. + * If the 0x1 set, drop the request silently. + **/ +#define LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY_DROP_ON_DECRYPT_ERROR 0x1 + +#define LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL 1 +#define LIBSPDM_MSG_LOG_MODE_ENABLE 1 + +typedef enum { + LIBSPDM_DATA_LOCATION_LOCAL, + LIBSPDM_DATA_LOCATION_CONNECTION, + LIBSPDM_DATA_LOCATION_SESSION, + LIBSPDM_DATA_LOCATION_MAX +} libspdm_data_location_t; + +typedef struct { + libspdm_data_location_t location; + /* data_type specific: + * session_id for the negoatiated key. + * SlotId for the certificate. + * req_slot_id + measurement_hash_type for LIBSPDM_DATA_MUT_AUTH_REQUESTED*/ + uint8_t additional_data[4]; +} libspdm_data_parameter_t; + +typedef enum { + /* Before GET_VERSION/VERSION */ + LIBSPDM_CONNECTION_STATE_NOT_STARTED, + + /* After GET_VERSION/VERSION */ + LIBSPDM_CONNECTION_STATE_AFTER_VERSION, + + /* After GET_CAPABILITIES/CAPABILITIES */ + LIBSPDM_CONNECTION_STATE_AFTER_CAPABILITIES, + + /* After NEGOTIATE_ALGORITHMS/ALGORITHMS */ + LIBSPDM_CONNECTION_STATE_NEGOTIATED, + + /* After GET_DIGESTS/DIGESTS */ + LIBSPDM_CONNECTION_STATE_AFTER_DIGESTS, + + /* After GET_CERTIFICATE/CERTIFICATE */ + LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE, + + /* After CHALLENGE/CHALLENGE_AUTH, and ENCAP CALLENGE/CHALLENG_AUTH if MUT_AUTH is enabled. */ + LIBSPDM_CONNECTION_STATE_AUTHENTICATED, + + /* MAX */ + LIBSPDM_CONNECTION_STATE_MAX +} libspdm_connection_state_t; + +typedef enum { + /* Normal response. */ + LIBSPDM_RESPONSE_STATE_NORMAL, + + /* Other component is busy. */ + LIBSPDM_RESPONSE_STATE_BUSY, + + /* Hardware is not ready. */ + LIBSPDM_RESPONSE_STATE_NOT_READY, + + /* Firmware Update is done. Need resync. */ + LIBSPDM_RESPONSE_STATE_NEED_RESYNC, + + /* Processing Encapsulated message. */ + LIBSPDM_RESPONSE_STATE_PROCESSING_ENCAP, + + /* MAX */ + LIBSPDM_RESPONSE_STATE_MAX +} libspdm_response_state_t; + +/** + * Set an SPDM context data. + * + * @param spdm_context A pointer to the SPDM context. + * @param data_type Type of the SPDM context data. + * @param parameter Type specific parameter of the SPDM context data. + * @param data A pointer to the SPDM context data. + * @param data_size Size in bytes of the SPDM context data. + * + * @retval RETURN_SUCCESS The SPDM context data is set successfully. + * @retval RETURN_INVALID_PARAMETER The data is NULL or the data_type is zero. + * @retval RETURN_UNSUPPORTED The data_type is unsupported. + * @retval RETURN_ACCESS_DENIED The data_type cannot be set. + * @retval RETURN_NOT_READY data is not ready to set. + **/ +libspdm_return_t libspdm_set_data(void *spdm_context, + libspdm_data_type_t data_type, + const libspdm_data_parameter_t *parameter, void *data, + size_t data_size); + +/** + * Get an SPDM context data. + * + * @param spdm_context A pointer to the SPDM context. + * @param data_type Type of the SPDM context data. + * @param parameter Type specific parameter of the SPDM context data. + * @param data A pointer to the SPDM context data. + * @param data_size Size in bytes of the SPDM context data. + * On input, it means the size in bytes of data buffer. + * On output, it means the size in bytes of copied data buffer if RETURN_SUCCESS, + * and means the size in bytes of desired data buffer if RETURN_BUFFER_TOO_SMALL. + * + * @retval RETURN_SUCCESS The SPDM context data is set successfully. + * @retval RETURN_INVALID_PARAMETER The data_size is NULL or the data is NULL and *data_size is not zero. + * @retval RETURN_UNSUPPORTED The data_type is unsupported. + * @retval RETURN_NOT_FOUND The data_type cannot be found. + * @retval RETURN_NOT_READY The data is not ready to return. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_data(void *spdm_context, + libspdm_data_type_t data_type, + const libspdm_data_parameter_t *parameter, + void *data, size_t *data_size); + +/** + * Get the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_get_last_spdm_error_struct(void *spdm_context, + libspdm_error_struct_t *last_spdm_error); + +/** + * Set the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_set_last_spdm_error_struct(void *spdm_context, + libspdm_error_struct_t *last_spdm_error); + +/** + * Initialize an SPDM context, as well as all secured message contexts, + * in the specified locations. + * + * The size in bytes of the spdm_context can be returned by + * libspdm_get_context_size_without_secured_context. + * + * The size in bytes of a single secured message context can be returned by + * libspdm_secured_message_get_context_size. + * + * @param spdm_context A pointer to the SPDM context. + * @param secured_contexts An array of pointers, with each entry containing + * the location of a secured message context. + * @param num_secured_contexts Number of secured message contexts to initialize. + * Currently, only LIBSPDM_MAX_SESSION_COUNT is supported. + * In future releases, lesser values may be supported. + * + * @retval RETURN_SUCCESS Contexts are initialized. + * @retval RETURN_DEVICE_ERROR Context initialization failed. + */ +libspdm_return_t libspdm_init_context_with_secured_context(void *spdm_context, + void **secured_contexts, + size_t num_secured_contexts); + +/** + * Initialize an SPDM context, as well as secured message contexts. + * The secured message contexts are appended to the context structure. + * + * The total size in bytes of the spdm_context and all secured message + * contexts can be returned by libspdm_get_context_size(). + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS context is initialized. + * @retval RETURN_DEVICE_ERROR context initialization failed. + */ +libspdm_return_t libspdm_init_context(void *spdm_context); + +/** + * Reset an SPDM context. + * + * The size in bytes of the spdm_context can be returned by libspdm_get_context_size. + * + * @param spdm_context A pointer to the SPDM context. + */ +void libspdm_reset_context(void *spdm_context); + +/** + * Free the memory of contexts within the SPDM context. + * These are typically contexts whose memory has been allocated by the cryptography library. + * This function does not free the SPDM context itself. + * + * @param[in] spdm_context A pointer to the SPDM context. + * + */ +void libspdm_deinit_context(void *spdm_context); + +/** + * Return the size in bytes of the SPDM context. This includes all + * secured message context data as well. + * + * For just the SPDM context size, use libspdm_get_context_size_without_secured_context. + * + * @return the size in bytes of the SPDM context and secured message contexts. + **/ +size_t libspdm_get_context_size(void); + +/** + * Return the size in bytes of just the SPDM context, without secured message context. + * + * For the complete context size, use libspdm_get_context_size. + * + * @return the size in bytes of the SPDM context. + **/ +size_t libspdm_get_context_size_without_secured_context(void); + +/** + * Send an SPDM transport layer message to a device. + * + * The message is an SPDM message with transport layer wrapper, + * or a secured SPDM message with transport layer wrapper. + * + * For requester, the message is a transport layer SPDM request. + * For responder, the message is a transport layer SPDM response. + * + * @param spdm_context A pointer to the SPDM context. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a destination buffer to store the message. + * The caller is responsible for having either implicit or explicit ownership + * of the buffer. The message pointer shall be inside of + * [msg_buf_ptr, msg_buf_ptr + max_msg_size] from acquired sender_buffer. + * @param timeout The timeout, in us units, to use for the execution of the message. A + * timeout value of 0 means that this function will wait indefinitely for the + * message to execute. If timeout is greater than zero, then this function + * will return RETURN_TIMEOUT if the time required to execute the message is + * greater than timeout. + * + * @retval RETURN_SUCCESS The SPDM message is sent successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM message is sent to the device. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_TIMEOUT A timeout occurred while waiting for the SPDM message + * to execute. + **/ +typedef libspdm_return_t (*libspdm_device_send_message_func)(void *spdm_context, + size_t message_size, + const void *message, + uint64_t timeout); + +/** + * Receive an SPDM transport layer message from a device. + * + * The message is an SPDM message with transport layer wrapper, + * or a secured SPDM message with transport layer wrapper. + * + * For requester, the message is a transport layer SPDM response. + * For responder, the message is a transport layer SPDM request. + * + * @param spdm_context A pointer to the SPDM context. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a destination buffer to store the message. + * The caller is responsible for having either implicit or explicit ownership + * of the buffer. On input, the message pointer shall be msg_buf_ptr from + * acquired receiver_buffer. On output, the message pointer shall be inside of + * [msg_buf_ptr, msg_buf_ptr + max_msg_size] from acquired receiver_buffer. + * @param timeout The timeout, in us units, to use for the execution of the message. A + * timeout value of 0 means that this function will wait indefinitely for the + * message to execute. If timeout is greater than zero, then this function + * will return RETURN_TIMEOUT if the time required to execute the message is + * greater than timeout. + * + * @retval RETURN_SUCCESS The SPDM message is received successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM message is received from the device. + * @retval RETURN_INVALID_PARAMETER The message is NULL, message_size is NULL or + * the *message_size is zero. + * @retval RETURN_TIMEOUT A timeout occurred while waiting for the SPDM message + * to execute. + **/ +typedef libspdm_return_t (*libspdm_device_receive_message_func)( + void *spdm_context, size_t *message_size, void **message, + uint64_t timeout); + +/** + * Register SPDM device input/output functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param send_message The fuction to send an SPDM transport layer message. + * @param receive_message The fuction to receive an SPDM transport layer message. + **/ +void libspdm_register_device_io_func( + void *spdm_context, libspdm_device_send_message_func send_message, + libspdm_device_receive_message_func receive_message); + +/** + * Acquire a device sender buffer for transport layer message. + * + * The max_msg_size must be larger than + * MAX (non-secure Transport Message Header Size + + * SPDM_CAPABILITIES.DataTransferSize + + * max alignment pad size (transport specific), + * secure Transport Message Header Size + + * sizeof(spdm_secured_message_a_data_header1_t) + + * length of sequence_number (transport specific) + + * sizeof(spdm_secured_message_a_data_header2_t) + + * sizeof(spdm_secured_message_cipher_header_t) + + * App Message Header Size (transport specific) + + * SPDM_CAPABILITIES.DataTransferSize + + * maximum random data size (transport specific) + + * AEAD MAC size (16) + + * max alignment pad size (transport specific)) + * + * For MCTP, + * Transport Message Header Size = sizeof(mctp_message_header_t) + * length of sequence_number = 2 + * App Message Header Size = sizeof(mctp_message_header_t) + * maximum random data size = MCTP_MAX_RANDOM_NUMBER_COUNT + * max alignment pad size = 0 + * For PCI_DOE, + * Transport Message Header Size = sizeof(pci_doe_data_object_header_t) + * length of sequence_number = 0 + * App Message Header Size = 0 + * maximum random data size = 0 + * max alignment pad size = 3 + * + * @param context A pointer to the SPDM context. + * @param max_msg_size Size in bytes of the maximum size of sender buffer. + * @param msg_buf_ptr A pointer to a sender buffer. + * + * @retval LIBSPDM_STATUS_SUCCESS The sender buffer has been acquired. + * @retval LIBSPDM_STATUS_ACQUIRE_FAIL Unable to acquire sender buffer. + **/ +typedef libspdm_return_t (*libspdm_device_acquire_sender_buffer_func)( + void *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + +/** + * Release a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param msg_buf_ptr A pointer to a sender buffer. + * + * @retval RETURN_SUCCESS The sender buffer is Released. + **/ +typedef void (*libspdm_device_release_sender_buffer_func)(void *spdm_context, + const void *msg_buf_ptr); + +/** + * Acquire a device receiver buffer for transport layer message. + * + * The max_msg_size must be larger than + * MAX (non-secure Transport Message Header Size + + * SPDM_CAPABILITIES.DataTransferSize + + * max alignment pad size (transport specific), + * secure Transport Message Header Size + + * sizeof(spdm_secured_message_a_data_header1_t) + + * length of sequence_number (transport specific) + + * sizeof(spdm_secured_message_a_data_header2_t) + + * sizeof(spdm_secured_message_cipher_header_t) + + * App Message Header Size (transport specific) + + * SPDM_CAPABILITIES.DataTransferSize + + * maximum random data size (transport specific) + + * AEAD MAC size (16) + + * max alignment pad size (transport specific)) + * + * For MCTP, + * Transport Message Header Size = sizeof(mctp_message_header_t) + * length of sequence_number = 2 + * App Message Header Size = sizeof(mctp_message_header_t) + * maximum random data size = MCTP_MAX_RANDOM_NUMBER_COUNT + * max alignment pad size = 0 + * For PCI_DOE, + * Transport Message Header Size = sizeof(pci_doe_data_object_header_t) + * length of sequence_number = 0 + * App Message Header Size = 0 + * maximum random data size = 0 + * max alignment pad size = 3 + * + * @param context A pointer to the SPDM context. + * @param max_msg_size Size in bytes of the maximum size of receiver buffer. + * @param msg_buf_pt A pointer to a receiver buffer. + * + * @retval LIBSPDM_STATUS_SUCCESS The receiver buffer has been acquired. + * @retval LIBSPDM_STATUS_ACQUIRE_FAIL Unable to acquire receiver buffer. + **/ +typedef libspdm_return_t (*libspdm_device_acquire_receiver_buffer_func)( + void *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + +/** + * Release a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param msg_buf_ptr A pointer to a receiver buffer. + * + * @retval RETURN_SUCCESS The receiver buffer is Released. + **/ +typedef void (*libspdm_device_release_receiver_buffer_func)(void *spdm_context, + const void *msg_buf_ptr); + +/** + * Register SPDM device buffer management functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param acquire_sender_buffer The fuction to acquire transport layer sender buffer. + * @param release_sender_buffer The fuction to release transport layer sender buffer. + * @param acquire_receiver_buffer The fuction to acquire transport layer receiver buffer. + * @param release_receiver_buffer The fuction to release transport layer receiver buffer. + **/ +void libspdm_register_device_buffer_func( + void *spdm_context, + libspdm_device_acquire_sender_buffer_func acquire_sender_buffer, + libspdm_device_release_sender_buffer_func release_sender_buffer, + libspdm_device_acquire_receiver_buffer_func acquire_receiver_buffer, + libspdm_device_release_receiver_buffer_func release_receiver_buffer); + +/** + * Encode an SPDM or APP message to a transport layer message. + * + * For normal SPDM message, it adds the transport layer wrapper. + * For secured SPDM message, it encrypts a secured message then adds the transport layer wrapper. + * For secured APP message, it encrypts a secured message then adds the transport layer wrapper. + * + * The APP message is encoded to a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param is_requester Indicates if it is a requester message. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a source buffer to store the message. + * For normal message, it shall point to the acquired sender buffer. + * For secured message, it shall point to the scratch buffer in spdm_context. + * @param transport_message_size Size in bytes of the transport message data buffer. + * @param transport_message A pointer to a destination buffer to store the transport message. + * On input, it shall be msg_buf_ptr from sender buffer. + * On output, it will point to acquired sender buffer. + * + * @retval RETURN_SUCCESS The message is encoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + **/ +typedef libspdm_return_t (*libspdm_transport_encode_message_func)( + void *spdm_context, const uint32_t *session_id, bool is_app_message, + bool is_requester, size_t message_size, + void *message, size_t *transport_message_size, + void **transport_message); + +/** + * Decode an SPDM or APP message from a transport layer message. + * + * For normal SPDM message, it removes the transport layer wrapper, + * For secured SPDM message, it removes the transport layer wrapper, then decrypts and verifies a secured message. + * For secured APP message, it removes the transport layer wrapper, then decrypts and verifies a secured message. + * + * The APP message is decoded from a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param is_requester Indicates if it is a requester message. + * @param transport_message_size Size in bytes of the transport message data buffer. + * @param transport_message A pointer to a source buffer to store the transport message. + * For normal message or secured message, it shall point to acquired receiver buffer. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a destination buffer to store the message. + * On input, it shall point to the scratch buffer in spdm_context. + * On output, for normal message, it will point to the original receiver buffer. + * On output, for secured message, it will point to the scratch buffer in spdm_context. + * + * @retval RETURN_SUCCESS The message is decoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_UNSUPPORTED The transport_message is unsupported. + **/ +typedef libspdm_return_t (*libspdm_transport_decode_message_func)( + void *spdm_context, uint32_t **session_id, + bool *is_app_message, bool is_requester, + size_t transport_message_size, void *transport_message, + size_t *message_size, void **message); + +/** + * Return the maximum transport layer message header size. + * Transport Message Header Size + sizeof(spdm_secured_message_cipher_header_t)) + * + * For MCTP, Transport Message Header Size = sizeof(mctp_message_header_t) + * For PCI_DOE, Transport Message Header Size = sizeof(pci_doe_data_object_header_t) + * + * @param spdm_context A pointer to the SPDM context. + * + * @return size of maximum transport layer message header size + **/ +typedef uint32_t (*libspdm_transport_get_header_size_func)(void *spdm_context); + +/** + * Register SPDM transport layer encode/decode functions for SPDM or APP messages. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param transport_encode_message The fuction to encode an SPDM or APP message to a transport layer message. + * @param transport_decode_message The fuction to decode an SPDM or APP message from a transport layer message. + * @param transport_get_header_size The fuction to get the maximum transport layer message header size. + **/ +void libspdm_register_transport_layer_func( + void *spdm_context, + libspdm_transport_encode_message_func transport_encode_message, + libspdm_transport_decode_message_func transport_decode_message, + libspdm_transport_get_header_size_func transport_get_header_size); + +/** + * Get the size of required scratch buffer. + * + * The SPDM Integrator must call libspdm_get_sizeof_required_scratch_buffer to get the size, + * then allocate enough scratch buffer and call libspdm_set_scratch_buffer(). + * + * @param context A pointer to the SPDM context. + * + * @return the size of required scratch buffer. + **/ +size_t libspdm_get_sizeof_required_scratch_buffer (void *spdm_context); + +/** + * Set the scratch buffer. + * + * The size of scratch buffer must be larger than the value returned in + * libspdm_get_sizeof_required_scratch_buffer(). + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param scratch_buffer Buffer address of the scratch buffer. + * @param scratch_buffer_size Size of the scratch buffer. + * + **/ +void libspdm_set_scratch_buffer ( + void *spdm_context, + void *scratch_buffer, + size_t scratch_buffer_size); + +/** + * Get the scratch buffer. + * + * @param spdm_context A pointer to the SPDM context. + * @param scratch_buffer Buffer address of the scratch buffer. + * @param scratch_buffer_size Size of the scratch buffer. + * + **/ +void libspdm_get_scratch_buffer ( + void *spdm_context, + void **scratch_buffer, + size_t *scratch_buffer_size); + +/** + * Verify a SPDM cert chain in a slot. + * + * This function shall verify: + * 1) The integrity of the certificate chain. (Root Cert Hash->Root Cert->Cert Chain) + * 2) The trust anchor. (Root Cert Hash/Root cert matches the trust anchor) + * + * The function shall check the negotiated hash algorithm to check root cert hash. + * The function shall check the negotiated (req) asym algorithm to determine if it is right cert chain. + * + * The function returns error if either of above is not satisfied. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size Indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to the buffer storing the certificate chain + * returned from GET_CERTIFICATE. It starts with spdm_cert_chain_t. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval RETURN_SUCCESS The cert chain verification pass. + * @retval RETURN_SECURIY_VIOLATION The cert chain verification fail. + **/ +typedef bool (*libspdm_verify_spdm_cert_chain_func)( + void *spdm_context, uint8_t slot_id, + size_t cert_chain_size, const void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * Register SPDM certificate verification functions for SPDM GET_CERTIFICATE in requester or responder. + * It is called after GET_CERTIFICATE gets a full certificate chain from peer. + * + * If it is NOT registered, the default verification in SPDM lib will be used. It verifies: + * 1) The integrity of the certificate chain, (Root Cert Hash->Root Cert->Cert Chain), according to X.509. + * 2) The trust anchor, according LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT or LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN. + * If it is registered, SPDM lib will use this function to verify the certificate. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param verify_certificate The fuction to verify an SPDM certificate after GET_CERTIFICATE. + **/ +void libspdm_register_verify_spdm_cert_chain_func( + void *spdm_context, + const libspdm_verify_spdm_cert_chain_func verify_spdm_cert_chain); + +/** + * This function gets the session info via session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return session info. + **/ +void *libspdm_get_session_info_via_session_id(void *spdm_context, uint32_t session_id); + +/** + * This function gets the secured message context via session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return secured message context. + **/ +void *libspdm_get_secured_message_context_via_session_id(void *spdm_context, uint32_t session_id); + +/** + * This function gets the secured message context via session ID. + * + * @param spdm_session_info A pointer to the SPDM context. + * + * @return secured message context. + **/ +void *libspdm_get_secured_message_context_via_session_info(void *spdm_session_info); + +/** + * This function returns peer certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * + * @retval true Peer certificate chain buffer including spdm_cert_chain_t header is returned. + * @retval false Peer certificate chain buffer including spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_peer_cert_chain_buffer(void *spdm_context, + const void **cert_chain_buffer, + size_t *cert_chain_buffer_size); + +/** + * This function returns peer certificate chain data without spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certitiface chain data. + * + * @retval true Peer certificate chain data without spdm_cert_chain_t header is returned. + * @retval false Peer certificate chain data without spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_peer_cert_chain_data(void *spdm_context, + const void **cert_chain_data, + size_t *cert_chain_data_size); + +/** + * This function returns local used certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * + * @retval true Local used certificate chain buffer including spdm_cert_chain_t header is returned. + * @retval false Local used certificate chain buffer including spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_local_cert_chain_buffer(void *spdm_context, + const void **cert_chain_buffer, + size_t *cert_chain_buffer_size); + +/** + * This function returns local used certificate chain data without spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certitiface chain data. + * + * @retval true Local used certificate chain data without spdm_cert_chain_t header is returned. + * @retval false Local used certificate chain data without spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_local_cert_chain_data(void *spdm_context, + const void **cert_chain_data, + size_t *cert_chain_data_size); + +#endif /* SPDM_COMMON_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h new file mode 100644 index 0000000000..de177ea0b1 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h @@ -0,0 +1,877 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_CRYPT_LIB_H +#define SPDM_CRYPT_LIB_H + +#include "internal/libspdm_lib_config.h" + +#include "hal/base.h" +#include "industry_standard/spdm.h" + +#define LIBSPDM_MAX_DHE_KEY_SIZE 512 +#define LIBSPDM_MAX_ASYM_KEY_SIZE 512 +#define LIBSPDM_MAX_HASH_SIZE 64 +#define LIBSPDM_MAX_AEAD_KEY_SIZE 32 +#define LIBSPDM_MAX_AEAD_IV_SIZE 12 +#define LIBSPDM_MAX_AEAD_TAG_SIZE 16 + +/** + * This function returns the SPDM hash algorithm size. + * + * @param base_hash_algo SPDM base_hash_algo + * + * @return SPDM hash algorithm size. + **/ +uint32_t libspdm_get_hash_size(uint32_t base_hash_algo); + +/** + * Return cipher ID, based upon the negotiated hash algorithm. + * + * @param base_hash_algo SPDM base_hash_algo + * + * @return hash cipher ID + **/ +size_t libspdm_get_hash_nid(uint32_t base_hash_algo); + +/** + * Allocates and initializes one HASH_CTX context for subsequent hash use. + * + * @param base_hash_algo SPDM base_hash_algo + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_hash_new() returns NULL. + **/ +void *libspdm_hash_new(uint32_t base_hash_algo); + +/** + * Release the specified HASH_CTX context. + * + * @param base_hash_algo SPDM base_hash_algo + * @param hash_context Pointer to the HASH_CTX context to be released. + **/ +void libspdm_hash_free(uint32_t base_hash_algo, void *hash_context); + +/** + * Initializes user-supplied memory pointed by hash_context as hash context for + * subsequent use. + * + * @param base_hash_algo SPDM base_hash_algo + * @param hash_context Pointer to hash context being initialized. + * + * @retval true Hash context initialization succeeded. + * @retval false Hash context initialization failed. + **/ +bool libspdm_hash_init(uint32_t base_hash_algo, void *hash_context); + +/** + * Makes a copy of an existing hash context. + * + * If hash_ctx is NULL, then return false. + * If new_hash_ctx is NULL, then return false. + * + * @param[in] hash_ctx Pointer to hash context being copied. + * @param[out] new_hash_ctx Pointer to new hash context. + * + * @retval true Hash context copy succeeded. + * @retval false Hash context copy failed. + **/ +bool libspdm_hash_duplicate(uint32_t base_hash_algo, const void *hash_ctx, void *new_hash_ctx); + +/** + * Digests the input data and updates hash context. + * + * This function performs hash digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * Hash context should be already correctly initialized by hash_init(), and should not be finalized + * by hash_final(). Behavior with invalid context is undefined. + * + * If hash_context is NULL, then return false. + * + * @param[in, out] hash_context Pointer to the MD context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true Hash data digest succeeded. + * @retval false Hash data digest failed. + **/ +bool libspdm_hash_update(uint32_t base_hash_algo, void *hash_context, + const void *data, size_t data_size); + +/** + * Completes computation of the hash digest value. + * + * This function completes hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the hash context cannot + * be used again. + * hash context should be already correctly initialized by hash_init(), and should not be + * finalized by hash_final(). Behavior with invalid hash context is undefined. + * + * If hash_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] hash_context Pointer to the hash context. + * @param[out] hash_value Pointer to a buffer that receives the hash digest value. + * + * @retval true Hash digest computation succeeded. + * @retval false Hash digest computation failed. + **/ +bool libspdm_hash_final(uint32_t base_hash_algo, void *hash_context, uint8_t *hash_value); + +/** + * Allocates and initializes one HMAC context for subsequent use. + * + * @param base_hash_algo SPDM base_hash_algo + * + * @return Pointer to the HMAC context that has been initialized. + * If the allocations fails, libspdm_hash_new() returns NULL. + **/ +void *libspdm_hmac_new(uint32_t base_hash_algo); + +/** + * Release the specified HMAC context. + * + * @param base_hash_algo SPDM base_hash_algo + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free(uint32_t base_hash_algo, void *hmac_ctx); + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * If hmac_ctx is NULL, then return false. + * + * @param[out] hmac_ctx Pointer to HMAC context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * + **/ +bool libspdm_hmac_init(uint32_t base_hash_algo, + void *hmac_ctx, + const uint8_t *key, + size_t key_size); + +/** + * Makes a copy of an existing HMAC context. + * + * If hmac_ctx is NULL, then return false. + * If new_hmac_ctx is NULL, then return false. + * + * @param[in] hmac_ctx Pointer to HMAC context being copied. + * @param[out] new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + * + **/ +bool libspdm_hmac_duplicate(uint32_t base_hash_algo, const void *hmac_ctx, void *new_hmac_ctx); + +/** + * Digests the input data and updates HMAC context. + * + * This function performs HMAC digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC context should be initialized by hmac_new(), and should not be finalized + * by hmac_final(). Behavior with invalid context is undefined. + * + * If hmac_ctx is NULL, then return false. + * + * @param[in, out] hmac_ctx Pointer to the HMAC context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size Size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + * + **/ +bool libspdm_hmac_update(uint32_t base_hash_algo, + void *hmac_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC digest value. + * + * This function completes HMAC hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC context cannot + * be used again. + * + * If hmac_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_ctx Pointer to the HMAC context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC digest value. + * + * @retval true HMAC digest computation succeeded. + * @retval false HMAC digest computation failed. + * + **/ +bool libspdm_hmac_final(uint32_t base_hash_algo, void *hmac_ctx, uint8_t *hmac_value); + +/** + * Computes the hash of a input data buffer, based upon the negotiated hash algorithm. + * + * This function performs the hash of a given data buffer, and return the hash value. + * + * @param base_hash_algo SPDM base_hash_algo + * @param data Pointer to the buffer containing the data to be hashed. + * @param data_size Size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the hash value. + * + * @retval true Hash computation succeeded. + * @retval false Hash computation failed. + **/ +bool libspdm_hash_all(uint32_t base_hash_algo, const void *data, + size_t data_size, uint8_t *hash_value); + +/** + * This function returns the SPDM measurement hash algorithm size. + * + * @param measurement_hash_algo SPDM measurement_hash_algo. + * + * @return SPDM measurement hash algorithm size. + * @return 0xFFFFFFFF for RAW_BIT_STREAM_ONLY. + **/ +uint32_t libspdm_get_measurement_hash_size(uint32_t measurement_hash_algo); + +/** + * Computes the HMAC of a input data buffer, based upon the negotiated HMAC algorithm. + * + * This function performs the HMAC of a given data buffer, and return the hash value. + * + * @param base_hash_algo SPDM base_hash_algo + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size Size of data buffer in bytes. + * @param key Pointer to the user-supplied key. + * @param key_size Key size in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all(uint32_t base_hash_algo, const void *data, + size_t data_size, const uint8_t *key, + size_t key_size, uint8_t *hmac_value); + +/** + * Derive HMAC-based Extract key Derivation Function (HKDF) Extract, based upon the negotiated HKDF + * algorithm. + * + * @param ikm Pointer to the input key material. + * @param ikm_size Key size in bytes. + * @param salt Pointer to the salt value. + * @param salt_size Salt size in bytes. + * @param prk_out Pointer to buffer to receive hkdf value. + * @param prk_out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +bool libspdm_hkdf_extract(uint32_t base_hash_algo, const uint8_t *ikm, size_t ikm_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size); + +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF + * algorithm. + * + * @param base_hash_algo SPDM base_hash_algo + * @param prk Pointer to the user-supplied key. + * @param prk_size Key size in bytes. + * @param info Pointer to the application specific info. + * @param info_size Info size in bytes. + * @param out Pointer to buffer to receive hkdf value. + * @param out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +bool libspdm_hkdf_expand(uint32_t base_hash_algo, const uint8_t *prk, + size_t prk_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size); + +/** + * This function returns the SPDM asymmetric algorithm size. + * + * @param base_asym_algo SPDM base_hash_algo + * + * @return SPDM asymmetric algorithm size. + **/ +uint32_t libspdm_get_asym_signature_size(uint32_t base_asym_algo); + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size Size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the retrieved + * public key component. Use libspdm_asym_free() function to free the + * resource. + * + * @retval true Public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_asym_get_public_key_from_x509(uint32_t base_asym_algo, + const uint8_t *cert, + size_t cert_size, + void **context); + +/** + * Release the specified asymmetric context, based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param context Pointer to the asymmetric context to be released. + **/ +void libspdm_asym_free(uint32_t base_asym_algo, void *context); + +/** + * Verifies the asymmetric signature, based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature verification. + * @param message Pointer to octet message to be checked (before hash). + * @param message_size Size of the message in bytes. + * @param signature Pointer to asymmetric signature to be verified. + * @param sig_size Size of signature in bytes. + * + * @retval true Valid asymmetric signature. + * @retval false Invalid asymmetric signature or invalid asymmetric context. + **/ +bool libspdm_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message, + size_t message_size, const uint8_t *signature, + size_t sig_size); + +/** + * Verifies the asymmetric signature, based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature verification. + * @param message_hash Pointer to octet message hash to be checked (after hash). + * @param hash_size Size of the hash in bytes. + * @param signature Pointer to asymmetric signature to be verified. + * @param sig_size Size of signature in bytes. + * + * @retval true Valid asymmetric signature. + * @retval false Invalid asymmetric signature or invalid asymmetric context. + **/ +bool libspdm_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message_hash, + size_t hash_size, const uint8_t *signature, + size_t sig_size); + +/** + * Carries out the signature generation. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature generation. + * @param message Pointer to octet message to be signed (before hash). + * @param message_size Size of the message in bytes. + * @param signature Pointer to buffer to receive signature. + * @param sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true Signature successfully generated. + * @retval false Signature generation failed. + * @retval false sig_size is too small. + **/ +bool libspdm_asym_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size); + +/** + * Carries out the signature generation. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature generation. + * @param message_hash Pointer to octet message hash to be signed (after hash). + * @param hash_size Size of the hash in bytes. + * @param signature Pointer to buffer to receive signature. + * @param sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true Signature successfully generated. + * @retval false Signature generation failed. + * @retval false sig_size is too small. + **/ +bool libspdm_asym_sign_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message_hash, + size_t hash_size, uint8_t *signature, + size_t *sig_size); + +/** + * This function returns the SPDM requester asymmetric algorithm size. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * + * @return SPDM requester asymmetric algorithm size. + **/ +uint32_t libspdm_get_req_asym_signature_size(uint16_t req_base_asym_alg); + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size Size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the + * retrieved public key component. Use libspdm_asym_free() function to + * free the resource. + * + * @retval true Public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_req_asym_get_public_key_from_x509(uint16_t req_base_asym_alg, + const uint8_t *cert, + size_t cert_size, + void **context); + +/** + * Release the specified asymmetric context, based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param context Pointer to the asymmetric context to be released. + **/ +void libspdm_req_asym_free(uint16_t req_base_asym_alg, void *context); + +/** + * Verifies the asymmetric signature, based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature verification. + * @param message Pointer to octet message to be checked (before hash). + * @param message_size Size of the message in bytes. + * @param signature Pointer to asymmetric signature to be verified. + * @param sig_size Size of signature in bytes. + * + * @retval true Valid asymmetric signature. + * @retval false Invalid asymmetric signature or invalid asymmetric context. + **/ +bool libspdm_req_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message, size_t message_size, + const uint8_t *signature, size_t sig_size); + +/** + * Verifies the asymmetric signature, based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature verification. + * @param message_hash Pointer to octet message hash to be checked (after hash). + * @param hash_size Size of the hash in bytes. + * @param signature Pointer to asymmetric signature to be verified. + * @param sig_size Size of signature in bytes. + * + * @retval true Valid asymmetric signature. + * @retval false Invalid asymmetric signature or invalid asymmetric context. + **/ +bool libspdm_req_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); + +/** + * Carries out the signature generation. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature generation. + * @param message Pointer to octet message to be signed (before hash). + * @param message_size Size of the message in bytes. + * @param signature Pointer to buffer to receive signature. + * @param sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true Signature successfully generated. + * @retval false Signature generation failed. + * @retval false sig_size is too small. + **/ +bool libspdm_req_asym_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size); + +/** + * Carries out the signature generation. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param base_hash_algo SPDM base_hash_algo + * @param context Pointer to asymmetric context for signature generation. + * @param message_hash Pointer to octet message hash to be signed (after hash). + * @param hash_size Size of the hash in bytes. + * @param signature Pointer to buffer to receive signature. + * @param sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true Signature successfully generated. + * @retval false Signature generation failed. + * @retval false sig_size is too small. + **/ +bool libspdm_req_asym_sign_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * This function returns the SPDM DHE algorithm key size. + * + * @param dhe_named_group SPDM dhe_named_group + * + * @return SPDM DHE algorithm key size. + **/ +uint32_t libspdm_get_dhe_pub_key_size(uint16_t dhe_named_group); + +/** + * Allocates and Initializes one Diffie-Hellman Ephemeral (DHE) context for subsequent use, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param is_initiator If the caller is initiator. + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + **/ +void *libspdm_dhe_new(spdm_version_number_t spdm_version, + uint16_t dhe_named_group, bool is_initiator); + +/** + * Release the specified DHE context, based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param context Pointer to the DHE context to be released. + **/ +void libspdm_dhe_free(uint16_t dhe_named_group, void *context); + +/** + * Generates DHE public key, based upon negotiated DHE algorithm. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * @param dhe_named_group SPDM dhe_named_group + * @param context Pointer to the DHE context. + * @param public_key Pointer to the buffer to receive generated public key. + * @param public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in bytes. + * + * @retval true DHE public key generation succeeded. + * @retval false DHE public key generation failed. + * @retval false public_key_size is not large enough. + **/ +bool libspdm_dhe_generate_key(uint16_t dhe_named_group, void *context, + uint8_t *public_key, + size_t *public_key_size); + +/** + * Computes exchanged common key, based upon negotiated DHE algorithm. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * @param dhe_named_group SPDM dhe_named_group + * @param context Pointer to the DHE context. + * @param peer_public_key Pointer to the peer's public key. + * @param peer_public_key_size Size of peer's public key in bytes. + * @param key Pointer to the buffer to receive generated key. + * @param key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in bytes. + * + * @retval true DHE exchanged key generation succeeded. + * @retval false DHE exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +bool libspdm_dhe_compute_key(uint16_t dhe_named_group, void *context, + const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size); + +/** + * This function returns the SPDM AEAD algorithm key size. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * + * @return SPDM AEAD algorithm key size. + **/ +uint32_t libspdm_get_aead_key_size(uint16_t aead_cipher_suite); + +/** + * This function returns the SPDM AEAD algorithm iv size. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * + * @return SPDM AEAD algorithm iv size. + **/ +uint32_t libspdm_get_aead_iv_size(uint16_t aead_cipher_suite); + +/** + * This function returns the SPDM AEAD algorithm tag size. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * + * @return SPDM AEAD algorithm tag size. + **/ +uint32_t libspdm_get_aead_tag_size(uint16_t aead_cipher_suite); + +/** + * Performs AEAD authenticated encryption on a data buffer and additional authenticated data (AAD), + * based upon negotiated AEAD algorithm. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * @param key Pointer to the encryption key. + * @param key_size Size of the encryption key in bytes. + * @param iv Pointer to the IV value. + * @param iv_size Size of the IV value in bytes. + * @param a_data Pointer to the additional authenticated data (AAD). + * @param a_data_size Size of the additional authenticated data (AAD) in bytes. + * @param data_in Pointer to the input data buffer to be encrypted. + * @param data_in_size Size of the input data buffer in bytes. + * @param tag_out Pointer to a buffer that receives the authentication tag output. + * @param tag_size Size of the authentication tag in bytes. + * @param data_out Pointer to a buffer that receives the encryption output. + * @param data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD authenticated encryption succeeded. + * @retval false AEAD authenticated encryption failed. + **/ +bool libspdm_aead_encryption(const spdm_version_number_t secured_message_version, + uint16_t aead_cipher_suite, const uint8_t *key, + size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, + size_t a_data_size, const uint8_t *data_in, + size_t data_in_size, uint8_t *tag_out, + size_t tag_size, uint8_t *data_out, + size_t *data_out_size); + +/** + * Performs AEAD authenticated decryption on a data buffer and additional authenticated data (AAD), + * based upon negotiated AEAD algorithm. + * + * @param aead_cipher_suite SPDM aead_cipher_suite + * @param key Pointer to the encryption key. + * @param key_size Size of the encryption key in bytes. + * @param iv Pointer to the IV value. + * @param iv_size Size of the IV value in bytes. + * @param a_data Pointer to the additional authenticated data (AAD). + * @param a_data_size Size of the additional authenticated data (AAD) in bytes. + * @param data_in Pointer to the input data buffer to be decrypted. + * @param data_in_size Size of the input data buffer in bytes. + * @param tag Pointer to a buffer that contains the authentication tag. + * @param tag_size Size of the authentication tag in bytes. + * @param data_out Pointer to a buffer that receives the decryption output. + * @param data_out_size Size of the output data buffer in bytes. + * + * @retval true AEAD authenticated decryption succeeded. + * @retval false AEAD authenticated decryption failed. + **/ +bool libspdm_aead_decryption(const spdm_version_number_t secured_message_version, + uint16_t aead_cipher_suite, const uint8_t *key, + size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, + size_t a_data_size, const uint8_t *data_in, + size_t data_in_size, const uint8_t *tag, + size_t tag_size, uint8_t *data_out, + size_t *data_out_size); + +/** + * Generates a random byte stream of the specified size. + * + * @param spdm_context A pointer to the SPDM context. + * @param size Size of random bytes to generate. + * @param rand Pointer to buffer to receive random value. + **/ +bool libspdm_get_random_number(size_t size, uint8_t *rand); + +/** + * Certificate Check for SPDM leaf cert. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in] base_hash_algo SPDM base_hash_algo + * @param[in] is_device_cert_model If true, the cert chain is DeviceCert model. + * If false, the cert chain is AliasCert model. + * + * @retval true Success. + * @retval false Certificate is not valid. + **/ +bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_device_cert_model); + +/** + * Return certificate is root cert or not. + * Certificate is considered as a root certificate if the subjectname equal issuername. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true Certificate is self-signed. + * @retval false Certificate is not self-signed. + **/ +bool libspdm_is_root_certificate(const uint8_t *cert, size_t cert_size); + +/** + * Retrieve the SubjectAltName from SubjectAltName Bytes. + * + * @param[in] buffer Pointer to subjectAltName oct bytes. + * @param[in] len Size of buffer in bytes. + * @param[out] name_buffer Buffer to contain the retrieved certificate + * SubjectAltName. At most name_buffer_size bytes will be + * written. Maybe NULL in order to determine the size + * buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * @param[out] oid OID of otherName + * @param[in,out] oid_size The buffersize for required OID + * + * @retval true Get the subjectAltName string successfully + * @retval failed Get the subjectAltName string failed + **/ +bool libspdm_get_dmtf_subject_alt_name_from_bytes( + uint8_t *buffer, const size_t len, char *name_buffer, + size_t *name_buffer_size, uint8_t *oid, + size_t *oid_size); + +/** + * Retrieve the SubjectAltName from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] name_buffer Buffer to contain the retrieved certificate + * SubjectAltName. At most name_buffer_size bytes will be + * written. Maybe NULL in order to determine the size + * buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * @param[out] oid OID of otherName + * @param[in,out] oid_size The buffersize for required OID + * + * @retval true Get the subjectAltName string successfully + * @retval failed Get the subjectAltName string failed + **/ +bool libspdm_get_dmtf_subject_alt_name(const uint8_t *cert, const size_t cert_size, + char *name_buffer, + size_t *name_buffer_size, + uint8_t *oid, size_t *oid_size); + +/** + * This function verifies the integrity of certificate chain data without spdm_cert_chain_t header. + * + * @param cert_chain_data The certificate chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certificate chain data. + * @param base_hash_algo SPDM base_hash_algo + * @param base_asym_algo SPDM base_asym_algo + * @param is_device_cert_model If true, the cert chain is DeviceCert model. + * If false, the cert chain is AliasCert model. + * + * @retval true Certificate chain data integrity verification pass. + * @retval false Certificate chain data integrity verification fail. + **/ +bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_data_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_device_cert_model); + +/** + * This function verifies the integrity of certificate chain buffer including + * spdm_cert_chain_t header. + * + * @param base_hash_algo SPDM base_hash_algo + * @param base_asym_algo SPDM base_asym_algo + * @param cert_chain_buffer The certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certificate chain buffer. + * @param is_device_cert_model If true, the cert chain is DeviceCert model. + * If false, the cert chain is AliasCert model. + * + * @retval true Certificate chain buffer integrity verification pass. + * @retval false Certificate chain buffer integrity verification fail. + **/ +bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t base_asym_algo, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + bool is_device_cert_model); + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated asymmetric or requester asymmetric algorithm. + * + * + * @param base_hash_algo SPDM base_hash_algo. + * @param base_asym_alg SPDM base_asym_algo or req_base_asym_alg. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certitiface chain data. + * @param public_key Pointer to new-generated asymmetric context which contain the + * retrieved public key component. + * + * @retval true Public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_get_leaf_cert_public_key_from_cert_chain(uint32_t base_hash_algo, + uint32_t base_asym_alg, + uint8_t *cert_chain_data, + size_t cert_chain_data_size, + void **public_key); + +/** + * Verify req info format refer to PKCS#10. + * + * @param[in] req_info Requester info to gen CSR. + * @param[in] req_info_len The len of requester info. + * + * @retval true Vaild req info, have three situations: + * 1: no req_info + * 2: good format req_info without attributes + * 3: good format req_info with good format attributes + * @retval false Invaild req info. + **/ +bool libspdm_verify_req_info(uint8_t *req_info, uint16_t req_info_len); + +#endif /* SPDM_CRYPT_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h new file mode 100644 index 0000000000..429d1377e3 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h @@ -0,0 +1,256 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_DEVICE_SECRET_LIB_H +#define SPDM_DEVICE_SECRET_LIB_H + +#include "internal/libspdm_lib_config.h" + +#include "hal/base.h" +#include "industry_standard/spdm.h" +#include "hal/library/debuglib.h" +#include "hal/library/memlib.h" +#include "hal/library/cryptlib.h" +#include "library/spdm_crypt_lib.h" +#include "library/spdm_return_status.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +/** + * Collect the device measurement. + * + * libspdm will call this function to retrieve the measurements for a device. + * The "measurement_index" parameter indicates the measurement requested. + * + * @param measurement_specification Indicates the measurement specification. + * Must be a SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_* value in spdm.h. + * + * @param measurement_hash_algo Indicates the measurement hash algorithm. + * Must be SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_* value in spdm.h. + * + * @param measurement_index The index of the measurement to collect. + * + * A value of [0x0] requests only the total number of measurements to be returned + * in "measurements_count". The parameters "measurements" and + * "measurements_size" will be left unmodified. + * + * A value of [1-0xFE] requests a single measurement for that measurement index + * be returned. On success, "measurements_count" will be set to 1 and the + * "measurements" and "measurements_size" fields will be set based + * on the single measurement. An invalid measurement index will cause + * "measurements_count" to return 0. + * + * A value of [0xFF] requests all measurements be returned. + * On success, "measurements_count", "measurements", and "measurements_size" + * fields will be set with data from all measurements. + * + * @param measurements_count + * + * When "measurement_index" is zero, returns the total count of + * measurements available for the device. None of the actual measurements are + * returned however, and "measurements" and "measurements_size" are unmodified. + * + * When "measurement_index" is non-zero, returns the number of measurements + * returned in "measurements" and "measurements_size". If "measurements_index" + * is an invalid index not supported by the device, "measurements_count" will + * return 0. + * + * @param measurements + * + * A pointer to a destination buffer to store the concatenation of all device + * measurement blocks. This buffer will only be modified if + * "measurement_index" is non-zero. + * + * @param measurements_size + * + * On input, indicates the size in bytes of the destination buffer. + * On output, indicates the total size in bytes of all device measurement + * blocks in the buffer. This field should only be modified if + * "measurement_index" is non-zero. + * + * @retval RETURN_SUCCESS Successfully returned measurement_count, + * measurements, measurements_size. + * @retval RETURN_BUFFER_TOO_SMALL measurements buffer too small for measurements. + * @retval RETURN_INVALID_PARAMETER Invalid parameter passed to function. + * @retval RETURN_NOT_FOUND Unsupported measurement index. + * @retval RETURN_*** Any other RETURN_ error from base.h + * indicating the type of failure + **/ +libspdm_return_t libspdm_measurement_collection( + spdm_version_number_t spdm_version, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_index, + uint8_t request_attribute, + uint8_t *content_changed, + uint8_t *measurements_count, + void *measurements, + size_t *measurements_size); + +/** + * This function calculates the measurement summary hash. + * + * @param spdm_version The spdm version. + * @param base_hash_algo The hash algo to use on summary. + * @param measurement_specification Indicates the measurement specification. + * It must align with measurement_specification + * (SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_*) + * @param measurement_hash_algo Indicates the measurement hash algorithm. + * It must align with measurement_hash_alg + * (SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_*) + * + * @param measurement_summary_hash_type The type of the measurement summary hash. + * @param measurement_summary_hash The buffer to store the measurement summary hash. + * @param measurement_summary_hash_size The size in bytes of the buffer. + * + * @retval true measurement summary hash is generated or skipped. + * @retval false measurement summary hash is not generated. + **/ +bool libspdm_generate_measurement_summary_hash( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_summary_hash_type, + uint8_t *measurement_summary_hash, + size_t *measurement_summary_hash_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +/** + * Sign an SPDM message data. + * + * @param req_base_asym_alg Indicates the signing algorithm. + * @param base_hash_algo Indicates the hash algorithm. + * @param is_data_hash Indicate the message type. true: raw message before hash, false: message hash. + * @param message A pointer to a message to be signed. + * @param message_size The size in bytes of the message to be signed. + * @param signature A pointer to a destination buffer to store the signature. + * @param sig_size On input, indicates the size in bytes of the destination buffer to store the signature. + * On output, indicates the size in bytes of the signature in the buffer. + * + * @retval true signing success. + * @retval false signing fail. + **/ +bool libspdm_requester_data_sign( + spdm_version_number_t spdm_version, + uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + +/** + * Sign an SPDM message data. + * + * @param base_asym_algo Indicates the signing algorithm. + * @param base_hash_algo Indicates the hash algorithm. + * @param is_data_hash Indicate the message type. true: raw message before hash, false: message hash. + * @param message A pointer to a message to be signed. + * @param message_size The size in bytes of the message to be signed. + * @param signature A pointer to a destination buffer to store the signature. + * @param sig_size On input, indicates the size in bytes of the destination buffer to store the signature. + * On output, indicates the size in bytes of the signature in the buffer. + * + * @retval true signing success. + * @retval false signing fail. + **/ +bool libspdm_responder_data_sign( + spdm_version_number_t spdm_version, + uint8_t op_code, + uint32_t base_asym_algo, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size); + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF algorithm. + * + * @param base_hash_algo Indicates the hash algorithm. + * @param psk_hint Pointer to the user-supplied PSK Hint. + * @param psk_hint_size PSK Hint size in bytes. + * @param info Pointer to the application specific info. + * @param info_size info size in bytes. + * @param out Pointer to buffer to receive hkdf value. + * @param out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +bool libspdm_psk_handshake_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, const uint8_t *psk_hint, + size_t psk_hint_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size); + +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF algorithm. + * + * @param base_hash_algo Indicates the hash algorithm. + * @param psk_hint Pointer to the user-supplied PSK Hint. + * @param psk_hint_size PSK Hint size in bytes. + * @param info Pointer to the application specific info. + * @param info_size info size in bytes. + * @param out Pointer to buffer to receive hkdf value. + * @param out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +bool libspdm_psk_master_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + const uint8_t *psk_hint, + size_t psk_hint_size, + const uint8_t *info, + size_t info_size, uint8_t *out, + size_t out_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP +/** + * This function sends SET_CERTIFICATE + * to set certificate from the device. + * + * + * @param[in] slot_id The number of slot for the certificate chain. + * @param[in] cert_chain The pointer for the certificate chain to set. + * @param[in] cert_chain_size The size of the certificate chain to set. + * + * @retval true Set certificate to NV successfully. + * @retval false Set certificate to NV unsuccessfully. + **/ +bool libspdm_write_certificate_to_nvm(uint8_t slot_id, const void * cert_chain, + size_t cert_chain_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * Gen CSR + * + * @param[in] base_hash_algo hash algo for sign + * @param[in] base_asym_algo asym public key to set + * @param[in] need_reset device need reset for gen csr + * + * @param[in] requester_info requester info to gen CSR + * @param[in] requester_info_length The len of requester info + * + * @param[in] csr_len For input, csr_len is the size of store CSR buffer. + * For output, csr_len is CSR len for DER format + * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. + * For output, csr_pointer is address for stored CSR. + * The csr_pointer address will be changed. + * + * @retval true Success. + * @retval false Failed to gen CSR. + **/ +bool libspdm_gen_csr(uint32_t base_hash_algo, uint32_t base_asym_algo, bool *need_reset, + uint8_t *requester_info, size_t requester_info_length, + size_t *csr_len, uint8_t **csr_pointer); +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ + +#endif /* SPDM_DEVICE_SECRET_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h new file mode 100644 index 0000000000..cfff674c5b --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h @@ -0,0 +1,415 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_LIB_CONFIG_H +#define SPDM_LIB_CONFIG_H + +/* Enables assertions and debug printing. When `LIBSPDM_DEBUG_ENABLE` is defined it overrides or + * sets the values of `LIBSPDM_DEBUG_PRINT_ENABLE`, `LIBSPDM_DEBUG_ASSERT_ENABLE`, and + * `LIBSPDM_BLOCK_ENABLE` to the value of `LIBSPDM_DEBUG_ENABLE`. + * + * Note that if this file is used with CMake and `DTARGET=Release` is defined, then all debugging + * is disabled. + */ +#ifndef LIBSPDM_DEBUG_ENABLE +#define LIBSPDM_DEBUG_ENABLE 1 +#endif + +/* The SPDM specification allows a Responder to return up to 256 version entries in the `VERSION` + * response to the Requester, including duplicate entries. For a Requester this value specifies the + * maximum number of entries that libspdm will tolerate in a `VERSION` response before returning an + * error. A similiar macro, `SPDM_MAX_VERSION_COUNT`, exists for the Responder. However this macro + * is not meant to be configured by the Integrator. + */ +#ifndef LIBSPDM_MAX_VERSION_COUNT +#define LIBSPDM_MAX_VERSION_COUNT 5 +#endif + +/* This value specifies the maximum size, in bytes, of the `PSK_EXCHANGE.RequesterContext` and, + * if supported by the Responder, `PSK_EXCHANGE_RSP.ResponderContext` fields. The fields are + * typically random or monotonically increasing numbers. + */ +#ifndef LIBSPDM_PSK_CONTEXT_LENGTH +#define LIBSPDM_PSK_CONTEXT_LENGTH LIBSPDM_MAX_HASH_SIZE +#endif +/* This value specifies the maximum size, in bytes, of the `PSK_EXCHANGE.PSKHint` field.*/ +#ifndef LIBSPDM_PSK_MAX_HINT_LENGTH +#define LIBSPDM_PSK_MAX_HINT_LENGTH 16 +#endif + +/* libspdm allows an Integrator to specify multiple root certificates as trust anchors when + * verifying certificate chains from an endpoint. This value specifies the maximum number of root + * certificates that libspdm can support. + */ +#ifndef LIBSPDM_MAX_ROOT_CERT_SUPPORT +#define LIBSPDM_MAX_ROOT_CERT_SUPPORT 10 +#endif + +/* If the Responder supports it a Requester is allowed to establish multiple secure sessions with + * the Responder. This value specifies the maximum number of sessions libspdm can support. + */ +#ifndef LIBSPDM_MAX_SESSION_COUNT +#define LIBSPDM_MAX_SESSION_COUNT 4 +#endif +/* This value specifies the maximum size, in bytes, of a certificate chain that can be stored in a + * libspdm context. + */ +#ifndef LIBSPDM_MAX_CERT_CHAIN_SIZE +#define LIBSPDM_MAX_CERT_CHAIN_SIZE 0x1000 +#endif +#ifndef LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE +#define LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE 0x1000 +#endif +/* Partial certificates can be retrieved from a Requester or Responder and through multiple messages + * the complete certificate chain can be constructed. This value specifies the maximum size, + * in bytes, of a partial certificate that can be sent or received. + */ +#ifndef LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN +#define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN 1024 +#endif + +#ifndef LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_BUFFER_SIZE 0x1200 +#endif +#ifndef LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE 0x100 /* to hold message_a before negotiate*/ +#endif +#ifndef LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE +#define LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE 0x300 /* to hold message_k before finished_key is ready*/ +#endif + +/* If the Responder replies with a Busy `ERROR` response to a request then the Requester is free to + * retry sending the request. This value specifies the maximum number of times libspdm will retry + * sending the request before returning an error. If its value is 0 then libspdm will not send any + * retry requests. + */ +#ifndef LIBSPDM_MAX_REQUEST_RETRY_TIMES +#define LIBSPDM_MAX_REQUEST_RETRY_TIMES 3 +#endif +#ifndef LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM +#define LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM 4 +#endif +#ifndef LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM +#define LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM 4 +#endif +#ifndef LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM +#define LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM 4 +#endif + +#ifndef LIBSPDM_MAX_CSR_SIZE +#define LIBSPDM_MAX_CSR_SIZE 0x1000 +#endif + +/* To ensure integrity in communication between the Requester and the Responder libspdm calculates + * cryptographic digests and signatures over multiple requests and responses. This value specifies + * whether libspdm will use a running calculation over the transcript, where requests and responses + * are discarded as they are cryptographically consumed, or whether libspdm will buffer the entire + * transcript before calculating the digest or signature. + */ +#ifndef LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +#define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 +#endif + + +/* Cryptography Configuration + * In each category, at least one should be selected. + * NOTE: Not all combination can be supported. E.g. Don't mix NIST algo with SMx.*/ + +#ifndef LIBSPDM_RSA_SSA_SUPPORT +#define LIBSPDM_RSA_SSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_PSS_SUPPORT +#define LIBSPDM_RSA_PSS_SUPPORT 1 +#endif +#ifndef LIBSPDM_ECDSA_SUPPORT +#define LIBSPDM_ECDSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM2_DSA_SUPPORT +#define LIBSPDM_SM2_DSA_SUPPORT 1 +#endif +#ifndef LIBSPDM_EDDSA_ED25519_SUPPORT +#define LIBSPDM_EDDSA_ED25519_SUPPORT 1 +#endif +#ifndef LIBSPDM_EDDSA_ED448_SUPPORT +#define LIBSPDM_EDDSA_ED448_SUPPORT 1 +#endif + +#ifndef LIBSPDM_FFDHE_SUPPORT +#define LIBSPDM_FFDHE_SUPPORT 1 +#endif +#ifndef LIBSPDM_ECDHE_SUPPORT +#define LIBSPDM_ECDHE_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT +#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT 1 +#endif + +#ifndef LIBSPDM_AEAD_GCM_SUPPORT +#define LIBSPDM_AEAD_GCM_SUPPORT 1 +#endif +#ifndef LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT +#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 1 +#endif +#ifndef LIBSPDM_AEAD_SM4_SUPPORT +#define LIBSPDM_AEAD_SM4_SUPPORT 1 +#endif + +#ifndef LIBSPDM_SHA256_SUPPORT +#define LIBSPDM_SHA256_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA384_SUPPORT +#define LIBSPDM_SHA384_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA512_SUPPORT +#define LIBSPDM_SHA512_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_256_SUPPORT +#define LIBSPDM_SHA3_256_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_384_SUPPORT +#define LIBSPDM_SHA3_384_SUPPORT 1 +#endif +#ifndef LIBSPDM_SHA3_512_SUPPORT +#define LIBSPDM_SHA3_512_SUPPORT 1 +#endif +#ifndef LIBSPDM_SM3_256_SUPPORT +#define LIBSPDM_SM3_256_SUPPORT 1 +#endif + +/* Code space optimization for Optional request/response messages.*/ + +/* Consumers of libspdm may wish to not fully implement all of the optional + * SPDM request/response messages. Therefore we have provided these + * SPDM_ENABLE_CAPABILITY_***_CAP compile time switches as an optimization + * disable the code (#if 0) related to said optional capability, thereby + * reducing the code space used in the image.*/ + +/* A single switch may enable/disable a single capability or group of related + * capabilities.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP - Enable/Disable single CERT capability. + * LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP - Enable/Disable single CHAL capability. + * LIBSPDM_ENABLE_CAPABILTIY_MEAS_CAP - Enable/Disables multiple MEAS capabilities: + * (MEAS_CAP_NO_SIG, MEAS_CAP_SIG, MEAS_FRESH_CAP)*/ + +/* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP - Enable/Disable single Key Exchange capability. + * LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP - Enable/Disable PSK_EX and PSK_FINISH.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP - Enable/Disable mutual authentication. +* LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP - Enable/Disable encapsulated message.*/ + +/* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP - Enable/Disable get csr capability. + * LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP - Enable/Disable set certificate capability. */ + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CERT_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +#define LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP +#define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +#define LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP +#define LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +#define LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP +#define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +#define LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP +#define LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP 1 +#endif + +#ifndef LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 1 +#endif + +/* + * MinDataTransferSize = 42 + * + * H = HashLen = HmacLen = [32, 64] + * S = SigLen = [64, 512] + * D = ExchangeDataLen = [64, 512] + * R = RequesterContextLen >= 32 + * R = ResponderContextLen >= 0 + * O = OpaqueDataLen <= 1024 + * + * Max Chunk No = 1, if (message size <= 42) + * Max Chunk No = [(message size + 4) / 30] roundup, if (message size > 42) + * + * +==========================+==========================================+=========+ + * | Command | Size |MaxChunk | + * +==========================+==========================================+=========+ + * | GET_VERSION | 4 | 1 | + * | VERSION {1.0, 1.1, 1.2} | 6 + 2 * 3 = 12 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | GET_CAPABILITIES 1.2 | 20 | 1 | + * | CAPABILITIES 1.2 | 20 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | ERROR | 4 | 1 | + * | ERROR(ResponseTooLarge) | 4 + 4 = 8 | 1 | + * | ERROR(LargeResponse) | 4 + 1 = 5 | 1 | + * | ERROR(ResponseNotReady) | 4 + 4 = 8 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | CHUNK_SEND header | 12 + L0 (0 or 4) | 1 | + * | CHUNK_RESPONSE header | 12 + L0 (0 or 4) | 1 | + * +==========================+==========================================+=========+ + * | NEGOTIATE_ALGORITHMS 1.2 | 32 + 4 * 4 = 48 | 2 | + * | ALGORITHMS 1.2 | 36 + 4 * 4 = 52 | 2 | + * +--------------------------+------------------------------------------+---------+ + * | GET_DIGESTS 1.2 | 4 | 1 | + * | DIGESTS 1.2 | 4 + H * SlotNum = [36, 516] | [1, 18] | + * +--------------------------+------------------------------------------+---------+ + * | GET_CERTIFICATE 1.2 | 8 | 1 | + * | CERTIFICATE 1.2 | 8 + PortionLen | [1, ] | + * +--------------------------+------------------------------------------+---------+ + * | CHALLENGE 1.2 | 40 | 1 | + * | CHALLENGE_AUTH 1.2 | 38 + H * 2 + S [+ O] = [166, 678] | [6, 23] | + * +--------------------------+------------------------------------------+---------+ + * | GET_MEASUREMENTS 1.2 | 5 + Nounce (0 or 32) | 1 | + * | MEASUREMENTS 1.2 | 42 + MeasRecLen (+ S) [+ O] = [106, 554] | [4, 19] | + * +--------------------------+------------------------------------------+---------+ + * | KEY_EXCHANGE 1.2 | 42 + D [+ O] = [106, 554] | [4, 19] | + * | KEY_EXCHANGE_RSP 1.2 | 42 + D + H + S (+ H) [+ O] = [234, 1194] | [8, 40] | + * +--------------------------+------------------------------------------+---------+ + * | FINISH 1.2 | 4 (+ S) + H = [100, 580] | [4, 20] | + * | FINISH_RSP 1.2 | 4 (+ H) = [36, 69] | [1, 3] | + * +--------------------------+------------------------------------------+---------+ + * | PSK_EXCHANGE 1.2 | 12 [+ PSKHint] + R [+ O] = 44 | 2 | + * | PSK_EXCHANGE_RSP 1.2 | 12 + R + H (+ H) [+ O] = [108, 172] | [4, 6] | + * +--------------------------+------------------------------------------+---------+ + * | PSK_FINISH 1.2 | 4 + H = [36, 68] | [1, 3] | + * | PSK_FINISH_RSP 1.2 | 4 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | GET_CSR 1.2 | 8 + RequesterInfoLen [+ O] | [1, ] | + * | CSR 1.2 | 8 + CSRLength | [1, ] | + * +--------------------------+------------------------------------------+---------+ + * | SET_CERTIFICATE 1.2 | 4 + CertChainLen | [1, ] | + * | SET_CERTIFICATE_RSP 1.2 | 4 | 1 | + * +==========================+==========================================+=========+ + */ + +/* Maximum size of a large SPDM message. + * If chunk is unsupported, it must be same as LIBSPDM_DATA_TRANSFER_SIZE. + * If chunk is supported, it must be larger than LIBSPDM_DATA_TRANSFER_SIZE. + * It matches MaxSPDMmsgSize in SPDM specification. */ +#ifndef LIBSPDM_MAX_SPDM_MSG_SIZE +#define LIBSPDM_MAX_SPDM_MSG_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#endif + +/* Maximum size of a single SPDM message. + * It matches DataTransferSize in SPDM specification. */ +#ifndef LIBSPDM_DATA_TRANSFER_SIZE +#define LIBSPDM_DATA_TRANSFER_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#endif + +/* Required sender/receive buffer in device io. + * NOTE: This is transport specific. Below configuration is just an example. + * +-------+--------+---------------------------+------+--+------+---+--------+-----+ + * | TYPE |TransHdr| EncryptionHeader |AppHdr| |Random|MAC|AlignPad|FINAL| + * | | |SessionId|SeqNum|Len|AppLen| | | | | | | + * +-------+--------+---------------------------+------+ +------+---+--------+-----+ + * | MCTP | 1 | 4 | 2 | 2 | 2 | 1 | | 32 | 12| 0 | 56 | + * |PCI_DOE| 8 | 4 | 0 | 2 | 2 | 0 | | 0 | 12| 3 | 31 | + * +-------+--------+---------------------------+------+--+------+---+--------+-----+ + */ +#ifndef LIBSPDM_TRANSPORT_ADDITIONAL_SIZE +#define LIBSPDM_TRANSPORT_ADDITIONAL_SIZE 64 +#endif +#ifndef LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE +#define LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE (LIBSPDM_DATA_TRANSFER_SIZE + \ + LIBSPDM_TRANSPORT_ADDITIONAL_SIZE) +#endif + + +/* Required scratch buffer size for libspdm internal usage. + * It may be used to hold the encrypted/decrypted message and/or last sent/received message. + * It may be used to hold the large request/response and intermediate send/receive buffer + * in case of chunking. + * + * If chunking is not supported, it may be just LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE. + * If chunking is supported, it should be at least below. + * + * +---------------+--------------+--------------------------+------------------------------+ + * |SECURE_MESSAGE |LARGE_MESSAGE | SENDER_RECEIVER | LARGE_SENDER_RECEIVER | + * +---------------+--------------+--------------------------+------------------------------+ + * |<-Secure msg ->|<-Large msg ->|<-Snd/Rcv buf for chunk ->|<-Snd/Rcv buf for large msg ->| + * + * The value is NOT configurable. + * The value MAY be changed in different libspdm version. + * It is exposed here, just in case the libspdm consumer wants to configure the setting at build time. + */ +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + +/* first section */ +#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_OFFSET 0 + +#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* second section */ +#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* third section */ +#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET \ + (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +/* fourth section */ +#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET \ + (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY) + +#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) + +#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY + \ + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY \ + ) + +#else +#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE) +#endif + +/* Enable message logging. + * See https://github.com/DMTF/libspdm/blob/main/doc/user_guide.md#message-logging + * for more information */ +#ifndef LIBSPDM_ENABLE_MSG_LOG +#define LIBSPDM_ENABLE_MSG_LOG 1 +#endif + +/* Enable macro checking during compilation. */ +#ifndef LIBSPDM_CHECK_MACRO +#define LIBSPDM_CHECK_MACRO 0 +#endif + +#endif /* SPDM_LIB_CONFIG_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h new file mode 100644 index 0000000000..eae8635a09 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h @@ -0,0 +1,804 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_REQUESTER_LIB_H +#define SPDM_REQUESTER_LIB_H + +#include "library/spdm_common_lib.h" + +/** + * Send an SPDM or an APP request to a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request_size Size in bytes of the request data buffer. + * @param request A pointer to a destination buffer to store the request. + * The caller is responsible for having either implicit or explicit ownership + * of the buffer. + * For normal message, requester pointer point to transport_message + transport header size + * For secured message, requester pointer will point to the scratch buffer + transport header size in spdm_context. + * + * @retval RETURN_SUCCESS The SPDM request is sent successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM request is sent to the device. + **/ +libspdm_return_t libspdm_send_request(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + size_t request_size, void *request); + +/** + * Receive an SPDM or an APP response from a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the response is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param response_size Size in bytes of the response data buffer. + * @param response A pointer to a destination buffer to store the response. + * The caller is responsible for having either implicit or explicit + * ownership of the buffer. + * For normal message, response pointer still point to original transport_message. + * For secured message, response pointer will point to the scratch buffer in spdm_context. + * + * @retval RETURN_SUCCESS The SPDM response is received successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM response is received from the device. + **/ +libspdm_return_t libspdm_receive_response(void *spdm_context, + const uint32_t *session_id, + bool is_app_message, + size_t *response_size, + void **response); + +/** + * This function sends GET_VERSION, GET_CAPABILITIES, NEGOTIATE_ALGORITHMS + * to initialize the connection with SPDM responder. + * + * Before this function, the requester configuration data can be set via libspdm_set_data. + * After this function, the negotiated configuration data can be got via libspdm_get_data. + * + * @param spdm_context A pointer to the SPDM context. + * @param get_version_only If the requester sends GET_VERSION only or not. + * + * @retval RETURN_SUCCESS The connection is initialized successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_init_connection(void *spdm_context, bool get_version_only); + +/** + * This function sends GET_DIGEST to get all digest of the certificate chains from device. + * + * If the peer certificate chain is deployed, this function also verifies the digest with the + * certificate chain. + * + * TotalDigestSize = sizeof(digest) * count in slot_mask + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_mask The slots which deploy the CertificateChain. + * @param total_digest_buffer A pointer to a destination buffer to store the digest buffer. + * + * @retval RETURN_SUCCESS The digests are got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_digest(void *spdm_context, uint8_t *slot_mask, + void *total_digest_buffer); + +/** + * This function sends GET_DIGESTS and receives DIGESTS. It may retry GET_DIGESTS multiple times + * if the Responder replies with a Busy error. + * + * If the peer certificate chain is deployed, this function also verifies the digest with the + * certificate chain. + * + * TotalDigestSize = sizeof(digest) * count in slot_mask + * + * @param context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param slot_mask Bitmask of the slots that contain certificates. + * @param total_digest_buffer A pointer to a destination buffer to store the digests. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_DIGETS was sent and DIGESTS was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_DIGESTS due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_DIGESTS because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the DIGESTS response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The DIGESTS response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * The digest of the stored certificate chain does not match the digest returned by + * the Responder. + * Note: This return value may be removed in the future. + **/ +libspdm_return_t libspdm_get_digest_in_session(void *context, const uint32_t *session_id, + uint8_t *slot_mask, void *total_digest_buffer); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate(void *spdm_context, uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate_ex(void *context, uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate_in_session(void *context, const uint32_t *session_id, + uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param length LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate_choose_length(void *spdm_context, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param length LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval RETURN_SUCCESS The certificate chain is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_certificate_choose_length_ex(void *context, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * This function sends GET_CERTIFICATE and receives CERTIFICATE. It may retry GET_CERTIFICATE + * multiple times if the Responder replies with a Busy error. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store + * the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer + * certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_CERTIFICATE was sent and CERTIFICATE was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_CERTIFICATE due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_CERTIFICATE because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the CERTIFICATE response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The CERTIFICATE response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * Verification of the certificate chain failed. + * @retval LIBSPDM_STATUS_INVALID_CERT + * The certificate is unable to be parsed or contains invalid field values. + * @retval LIBSPDM_STATUS_CRYPTO_ERROR + * A generic cryptography error occurred. + **/ +libspdm_return_t libspdm_get_certificate_choose_length_in_session(void *context, + const uint32_t *session_id, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + +/** + * This function sends CHALLENGE to authenticate the device based upon the key in one slot. + * + * This function verifies the signature in the challenge auth. + * + * If basic mutual authentication is requested from the responder, + * this function also perform the basic mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the challenge. + * @param measurement_hash_type The type of the measurement hash. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * @param slot_mask A pointer to a destination to store the slot mask. + * + * @retval RETURN_SUCCESS The challenge auth is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_challenge(void *spdm_context, uint8_t slot_id, + uint8_t measurement_hash_type, + void *measurement_hash, + uint8_t *slot_mask); + +/** + * This function sends CHALLENGE to authenticate the device based upon the key in one slot. + * + * This function verifies the signature in the challenge auth. + * + * If basic mutual authentication is requested from the responder, + * this function also perform the basic mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the challenge. + * @param measurement_hash_type The type of the measurement hash. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * @param slot_mask A pointer to a destination to store the slot mask. + * @param requester_nonce_in A buffer to hold the requester nonce (32 bytes) as input, if not NULL. + * @param requester_nonce A buffer to hold the requester nonce (32 bytes), if not NULL. + * @param responder_nonce A buffer to hold the responder nonce (32 bytes), if not NULL. + * + * @retval RETURN_SUCCESS The challenge auth is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_challenge_ex(void *context, uint8_t slot_id, + uint8_t measurement_hash_type, + void *measurement_hash, + uint8_t *slot_mask, + const void *requester_nonce_in, + void *requester_nonce, + void *responder_nonce); + +/** + * This function sends GET_MEASUREMENT + * to get measurement from the device. + * + * If the signature is requested, this function verifies the signature of the measurement. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param request_attribute The request attribute of the request message. + * @param measurement_operation The measurement operation of the request message. + * @param slot_id The number of slot for the certificate chain. + * @param content_changed The measurement content changed output param. + * @param number_of_blocks The number of blocks of the measurement record. + * @param measurement_record_length On input, indicate the size in bytes of the destination buffer to store the measurement record. + * On output, indicate the size in bytes of the measurement record. + * @param measurement_record A pointer to a destination buffer to store the measurement record. + * + * @retval RETURN_SUCCESS The measurement is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_measurement(void *spdm_context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record); + +/** + * This function sends GET_MEASUREMENT to get measurement from the device. + * + * If the signature is requested, this function verifies the signature of the measurement. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param request_attribute The request attribute of the request message. + * @param measurement_operation The measurement operation of the request message. + * @param slot_id The number of slot for the certificate chain. + * @param content_changed The measurement content changed output param. + * @param number_of_blocks The number of blocks of the measurement record. + * @param measurement_record_length On input, indicate the size in bytes of the destination buffer to store the measurement record. + * On output, indicate the size in bytes of the measurement record. + * @param measurement_record A pointer to a destination buffer to store the measurement record. + * @param requester_nonce_in A buffer to hold the requester nonce (32 bytes) as input, if not NULL. + * @param requester_nonce A buffer to hold the requester nonce (32 bytes), if not NULL. + * @param responder_nonce A buffer to hold the responder nonce (32 bytes), if not NULL. + * + * @retval RETURN_SUCCESS The measurement is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record, + const void *requester_nonce_in, + void *requester_nonce, + void *responder_nonce); + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +/** + * This function sends KEY_EXCHANGE/FINISH or PSK_EXCHANGE/PSK_FINISH + * to start an SPDM Session. + * + * If encapsulated mutual authentication is requested from the responder, + * this function also perform the encapsulated mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param use_psk False means to use KEY_EXCHANGE/FINISH to start a session. + * True means to use PSK_EXCHANGE/PSK_FINISH to start a session. + * @param measurement_hash_type The type of the measurement hash. + * @param slot_id The number of slot for the certificate chain. + * @param session_policy The policy for the session. + * @param session_id The session ID of the session. + * @param heartbeat_period The heartbeat period for the session. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * + * @retval RETURN_SUCCESS The SPDM session is started. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_start_session(void *spdm_context, bool use_psk, + uint8_t measurement_hash_type, + uint8_t slot_id, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash); + +/** + * This function sends KEY_EXCHANGE/FINISH or PSK_EXCHANGE/PSK_FINISH to start an SPDM Session. + * + * If encapsulated mutual authentication is requested from the responder, + * this function also perform the encapsulated mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param use_psk False means to use KEY_EXCHANGE/FINISH to start a session. + * True means to use PSK_EXCHANGE/PSK_FINISH to start a session. + * @param measurement_hash_type The type of the measurement hash. + * @param slot_id The number of slot for the certificate chain. + * @param session_policy The policy for the session. + * @param session_id The session ID of the session. + * @param heartbeat_period The heartbeat period for the session. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * @param requester_random_in A buffer to hold the requester random as input, if not NULL. + * @param requester_random_in_size The size of requester_random_in. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context and must be 32 bytes at least, + * but not exceed LIBSPDM_PSK_CONTEXT_LENGTH. + * @param requester_random A buffer to hold the requester random, if not NULL. + * @param requester_random_size On input, the size of requester_random buffer. + * On output, the size of data returned in requester_random buffer. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context and must be 32 bytes at least. + * @param responder_random A buffer to hold the responder random, if not NULL. + * @param responder_random_size On input, the size of requester_random buffer. + * On output, the size of data returned in requester_random buffer. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context. It could be 0 if device does not support context. + * + * @retval RETURN_SUCCESS The SPDM session is started. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_start_session_ex(void *spdm_context, bool use_psk, + uint8_t measurement_hash_type, + uint8_t slot_id, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash, + const void *requester_random_in, + size_t requester_random_in_size, + void *requester_random, + size_t *requester_random_size, + void *responder_random, + size_t *responder_random_size); + +/** + * This function sends END_SESSION to stop an SPDM Session. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * @param end_session_attributes The end session attribute for the session. + * + * @retval RETURN_SUCCESS The SPDM session is stopped. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_stop_session(void *spdm_context, uint32_t session_id, + uint8_t end_session_attributes); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ + +/** + * Send and receive an SPDM or APP message. + * + * The SPDM message can be a normal message or a secured message in SPDM session. + * + * The APP message is encoded to a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request A pointer to the request data. + * @param request_size Size in bytes of the request data. + * @param response A pointer to the response data. + * @param response_size Size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * + * @retval RETURN_SUCCESS The SPDM request is set successfully. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_send_receive_data(void *spdm_context, + const uint32_t *session_id, + bool is_app_message, + const void *request, size_t request_size, + void *response, + size_t *response_size); + +/** + * This function sends HEARTBEAT + * to an SPDM Session. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * + * @retval RETURN_SUCCESS The heartbeat is sent and received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_heartbeat(void *spdm_context, uint32_t session_id); + +/** + * This function sends KEY_UPDATE + * to update keys for an SPDM Session. + * + * After keys are updated, this function also uses VERIFY_NEW_KEY to verify the key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * @param single_direction true means the operation is UPDATE_KEY. + * false means the operation is UPDATE_ALL_KEYS. + * + * @retval RETURN_SUCCESS The keys of the session are updated. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_key_update(void *spdm_context, uint32_t session_id, bool single_direction); + +/** + * This function executes a series of SPDM encapsulated requests and receives SPDM encapsulated responses. + * + * This function starts with the first encapsulated request (such as GET_ENCAPSULATED_REQUEST) + * and ends with last encapsulated response (such as RESPONSE_PAYLOAD_TYPE_ABSENT or RESPONSE_PAYLOAD_TYPE_SLOT_NUMBER). + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicate if the encapsulated request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * + * @retval RETURN_SUCCESS The SPDM Encapsulated requests are sent and the responses are received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +libspdm_return_t libspdm_send_receive_encap_request(void *spdm_context, const uint32_t *session_id); + +/** + * Process the encapsulated request and return the encapsulated response. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_request_size Size in bytes of the request data. + * @param spdm_request A pointer to the request data. + * @param spdm_response_size Size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +typedef libspdm_return_t (*libspdm_get_encap_response_func)( + void *spdm_context, size_t spdm_request_size, + void *spdm_request, size_t *spdm_response_size, + void *spdm_response); + +/** + * Register an SPDM encapsulated message process function. + * + * If the default encapsulated message process function cannot handle the encapsulated message, + * this function will be invoked. + * + * @param spdm_context A pointer to the SPDM context. + * @param get_encap_response_func The function to process the encapsuled message. + **/ +void libspdm_register_get_encap_response_func(void *spdm_context, + const libspdm_get_encap_response_func + get_encap_response_func); + +/** + * Generate encapsulated ERROR message. + * + * This function can be called in libspdm_get_encap_response_func. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code The error code of the message. + * @param error_data The error data of the message. + * @param spdm_response_size Size in bytes of the response data. + * On input, it means the size in bytes of data buffer. + * On output, it means the size in bytes of copied data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The error message is generated. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_generate_encap_error_response( + const void *spdm_context, uint8_t error_code, uint8_t error_data, + size_t *spdm_response_size, void *spdm_response); + +/** + * Generate encapsulated ERROR message with extended error data. + * + * This function can be called in libspdm_get_encap_response_func. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code The error code of the message. + * @param error_data The error data of the message. + * @param extended_error_data_size The size in bytes of the extended error data. + * @param extended_error_data A pointer to the extended error data. + * @param spdm_response_size Size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The error message is generated. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_generate_encap_extended_error_response( + const void *spdm_context, uint8_t error_code, uint8_t error_data, + size_t extended_error_data_size, const uint8_t *extended_error_data, + size_t *spdm_response_size, void *spdm_response); + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +/** + * This function sends GET_CSR + * to get csr from the device. + * + * @param[in] context A pointer to the SPDM context. + * @param[in] requester_info Requester info to gen CSR + * @param[in] requester_info_length The length of requester info + * @param[in] opaque_data opaque data. + * @param[in] opaque_data_length The length of opaque data. + * @param[in] session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param[out] csr Address to store CSR. + * @param[out] csr_len On input, *csr_len indicates the max csr buffer size. + * On output, *csr_len indicates the actual csr buffer size. + * + * @retval RETURN_SUCCESS The measurement is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_get_csr(void *context, + void *requester_info, uint16_t requester_info_length, + void *opaque_data, uint16_t opaque_data_length, + const uint32_t *session_id, + void *csr, size_t *csr_len); +#endif /*LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP*/ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP || LIBSPDM_ENABLE_SET_CERTIFICATE_CAP +/** + * This function try to send SET_CERTIFICATE + * to set certificate from the device. + * + * @param context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain The pointer for the certificate chain to set. + * The cert chain is a full SPDM certificate chain, including Length and Root Cert Hash. + * @param cert_chain_size The size of the certificate chain to set. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * + * @retval RETURN_SUCCESS The measurement is got successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +libspdm_return_t libspdm_set_certificate(void * context, uint8_t slot_id, + void * cert_chain, size_t cert_chain_size, + const uint32_t *session_id); + +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ + +#if LIBSPDM_ENABLE_MSG_LOG +/* For now these functions are only available to the Requester. They may become available to the + * Responder at a later time. + */ + +/** + * This function initializes message logging. The caller must provide a buffer and the buffer's + * size. + * + * @param context A pointer to the SPDM context. + * @param msg_buffer A pointer to a caller-provided buffer. + * @param msg_buffer_size The size of the buffer in bytes. It must be greater than zero. + **/ +void libspdm_init_msg_log (void *context, void *msg_buffer, size_t msg_buffer_size); + +/** + * This function sets the mode in which the message logger operates. + * + * @param context A pointer to the SPDM context. + * @param mode A bitmask specifying the mode in which the message logger operates. + * LIBSPDM_MSG_LOG_MODE_ENABLE - when set the message logger is active. + */ +void libspdm_set_msg_log_mode (void *context, uint32_t mode); + +/** + * This function returns the status of the message logger. + * + * @param context A pointer to the SPDM context. + * + * @retval uint32_t A bitmask giving the status of the message logger. + * LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL - if set the message logging buffer has + * reached capacity. + */ +uint32_t libspdm_get_msg_log_status (void *context); + +/** + * This function returns the size of the message log. + * + * @param context A pointer to the SPDM context. + * @retval size_t The size of the message log in bytes. + */ +size_t libspdm_get_msg_log_size (void *context); + +/** + * This function resets the message log while retaining the message buffer and maximum size given in + * libspdm_init_msg_log. + * + * @param context A pointer to the SPDM context. + */ +void libspdm_reset_msg_log (void *context); +#endif /* LIBSPDM_ENABLE_MSG_LOG */ + +#endif /* SPDM_REQUESTER_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h new file mode 100644 index 0000000000..f4bf958f26 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h @@ -0,0 +1,257 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_RESPONDER_LIB_H +#define SPDM_RESPONDER_LIB_H + +#include "library/spdm_common_lib.h" + +/** + * Process the SPDM or APP request and return the response. + * + * The APP message is encoded to a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request_size size in bytes of the request data. + * @param request A pointer to the request data. + * @param response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param response A pointer to the response data. + * + * @retval RETURN_SUCCESS The request is processed and the response is returned. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + * @retval RETURN_UNSUPPORTED Just ignore this message: return UNSUPPORTED and clear response_size. + * Continue the dispatch without send response. + **/ +typedef libspdm_return_t (*libspdm_get_response_func)( + void *spdm_context, const uint32_t *session_id, bool is_app_message, + size_t request_size, const void *request, size_t *response_size, + void *response); + +/** + * Register an SPDM or APP message process function. + * + * If the default message process function cannot handle the message, + * this function will be invoked. + * + * @param spdm_context A pointer to the SPDM context. + * @param get_response_func The function to process the encapsuled message. + **/ +void libspdm_register_get_response_func( + void *spdm_context, libspdm_get_response_func get_response_func); + +/** + * Process a SPDM request from a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request_size size in bytes of the request data buffer. + * @param request A pointer to a destination buffer to store the request. + * The caller is responsible for having + * either implicit or explicit ownership of the buffer. + * + * @retval RETURN_SUCCESS The SPDM request is received successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM request is received from the device. + **/ +libspdm_return_t libspdm_process_request(void *spdm_context, + uint32_t **session_id, + bool *is_app_message, + size_t request_size, void *request); + +/** + * Build a SPDM response to a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the response is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param response_size size in bytes of the response data buffer. + * @param response A pointer to a destination buffer to store the response. + * The caller is responsible for having + * either implicit or explicit ownership of the buffer. + * + * @retval RETURN_SUCCESS The SPDM response is sent successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM response is sent to the device. + * @retval RETURN_UNSUPPORTED Just ignore this message: return UNSUPPORTED and clear response_size. + * Continue the dispatch without send response. + **/ +libspdm_return_t libspdm_build_response(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + size_t *response_size, + void **response); + +/** + * This is the main dispatch function in SPDM responder. + * + * It receives one request message, processes it and sends the response message. + * + * It should be called in a while loop or an timer/interrupt handler. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS One SPDM request message is processed. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_UNSUPPORTED One request message is not supported. + **/ +libspdm_return_t libspdm_responder_dispatch_message(void *spdm_context); + +/** + * Generate ERROR message. + * + * This function can be called in libspdm_get_response_func. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code The error code of the message. + * @param error_data The error data of the message. + * @param spdm_response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The error message is generated. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_generate_error_response(const void *spdm_context, + uint8_t error_code, + uint8_t error_data, + size_t *spdm_response_size, + void *spdm_response); + +/** + * Generate ERROR message with extended error data. + * + * This function can be called in libspdm_get_response_func. + * + * @param spdm_context A pointer to the SPDM context. + * @param error_code The error code of the message. + * @param error_data The error data of the message. + * @param extended_error_data_size The size in bytes of the extended error data. + * @param extended_error_data A pointer to the extended error data. + * @param spdm_response_size size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, + * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * @param spdm_response A pointer to the response data. + * + * @retval RETURN_SUCCESS The error message is generated. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_generate_extended_error_response( + const void *context, uint8_t error_code, uint8_t error_data, + size_t extended_error_data_size, const uint8_t *extended_error_data, + size_t *spdm_response_size, void *spdm_response); + +/** + * Notify the session state to a session APP. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session_id of a session. + * @param session_state The state of a session. + **/ +typedef void (*libspdm_session_state_callback_func)( + void *spdm_context, uint32_t session_id, + libspdm_session_state_t session_state); + +/** + * Register an SPDM state callback function. + * + * This function can be called multiple times to let different session APPs register its own callback. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_state_callback The function to be called in SPDM session state change. + * + * @retval RETURN_SUCCESS The callback is registered. + * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. + **/ +libspdm_return_t libspdm_register_session_state_callback_func( + void *spdm_context, + libspdm_session_state_callback_func spdm_session_state_callback); + +/** + * Notify the connection state to an SPDM context register. + * + * @param spdm_context A pointer to the SPDM context. + * @param connection_state Indicate the SPDM connection state. + **/ +typedef void (*libspdm_connection_state_callback_func)( + void *spdm_context, libspdm_connection_state_t connection_state); + +/** + * Register an SPDM connection state callback function. + * + * This function can be called multiple times to let different register its own callback. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_connection_state_callback The function to be called in SPDM connection state change. + * + * @retval RETURN_SUCCESS The callback is registered. + * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. + **/ +libspdm_return_t libspdm_register_connection_state_callback_func( + void *spdm_context, + libspdm_connection_state_callback_func spdm_connection_state_callback); + +/** + * Notify the key update operation to an SPDM context register. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Session ID for the keys being updated. + * @param key_update_operation Indicate the key update operation. + * @param key_update_action Indicate the direction of the key update. + **/ +typedef void (*libspdm_key_update_callback_func)( + void *spdm_context, uint32_t session_id, libspdm_key_update_operation_t key_update_op, + libspdm_key_update_action_t key_update_action); + +/** + * Notify the key update operation to an SPDM context register. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Session ID for the keys being updated. + * @param key_update_operation Indicate the key update operation. + * @param key_update_action Indicate the direction of the key update. + **/ +void libspdm_trigger_key_update_callback( + void *spdm_context, uint32_t session_id, libspdm_key_update_operation_t key_update_op, + libspdm_key_update_action_t key_update_action); + +/** + * Register a key update callback function. + * + * This function can be called multiple times to register multiple callbacks. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_key_update_callback The function to be called in key update operation. + * + * @retval RETURN_SUCCESS The callback is registered. + * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. + **/ +libspdm_return_t libspdm_register_key_update_callback_func( + void *spdm_context, libspdm_key_update_callback_func spdm_key_update_callback); + +/** + * This function initializes the key_update encapsulated state. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_init_key_update_encap_state(void *spdm_context); + +#endif /*SPDM_RESPONDER_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h new file mode 100644 index 0000000000..eebb0f3de9 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h @@ -0,0 +1,185 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_RETURN_STATUS_H +#define SPDM_RETURN_STATUS_H + +#ifndef LIBSPDM_STDINT_ALT +#include +#else +#include LIBSPDM_STDINT_ALT +#endif + +/* The layout of libspdm_return_t is + * [31:28] - Severity + * [27:24] - Reserved + * [23:16] - Source + * [15:00] - Code + */ +typedef uint32_t libspdm_return_t; + +/* Returns 1 if severity is LIBSPDM_SEVERITY_SUCCESS else it returns 0. */ +#define LIBSPDM_STATUS_IS_SUCCESS(status) \ + (LIBSPDM_STATUS_SEVERITY(status) == LIBSPDM_SEVERITY_SUCCESS) + +/* Returns 1 if severity is LIBSPDM_SEVERITY_ERROR else it returns 0. */ +#define LIBSPDM_STATUS_IS_ERROR(status) \ + (LIBSPDM_STATUS_SEVERITY(status) == LIBSPDM_SEVERITY_ERROR) + +/* Returns the severity of the status. */ +#define LIBSPDM_STATUS_SEVERITY(status) (((status) >> 28) & 0xf) + +/* Returns the source of the status. */ +#define LIBSPDM_STATUS_SOURCE(status) (((status) >> 16) & 0xff) + +#define LIBSPDM_SEVERITY_SUCCESS 0x0 +#define LIBSPDM_SEVERITY_ERROR 0x8 + +#define LIBSPDM_SOURCE_SUCCESS 0x00 +#define LIBSPDM_SOURCE_CORE 0x01 +#define LIBSPDM_SOURCE_CRYPTO 0x02 +#define LIBSPDM_SOURCE_CERT_PARSE 0x03 + +/*LIBSPSM_SOURCE_TRANSPORT is deprecated. Do not use it. Reserved only.*/ +#define LIBSPSM_SOURCE_TRANSPORT 0x04 + +#define LIBSPDM_SOURCE_TRANSPORT 0x04 +#define LIBSPDM_SOURCE_MEAS_COLLECT 0x05 +#define LIBSPDM_SOURCE_RNG 0x06 + +#define LIBSPDM_STATUS_CONSTRUCT(severity, source, code) \ + ((libspdm_return_t)(((severity) << 28) | ((source) << 16) | (code))) + +/* Success status is always 0x00000000. */ +#define LIBSPDM_STATUS_SUCCESS \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_SUCCESS, LIBSPDM_SOURCE_SUCCESS, 0x0000) + +#define LIBSPDM_RET_ON_ERR(status) \ + do { \ + if (LIBSPDM_STATUS_IS_ERROR(status)) { \ + return (status); \ + } \ + } \ + while (0) + +/* - Core Errors - */ + +/* The function input parameter is invalid. */ +#define LIBSPDM_STATUS_INVALID_PARAMETER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0001) + +/* Unable to complete operation due to unsupported capabilities by either the caller, the peer, + * or both. */ +#define LIBSPDM_STATUS_UNSUPPORTED_CAP \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0002) + +/* Unable to complete operation due to caller's state. */ +#define LIBSPDM_STATUS_INVALID_STATE_LOCAL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0003) + +/* Unable to complete operation due to peer's state. */ +#define LIBSPDM_STATUS_INVALID_STATE_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0004) + +/* The received message contains one or more invalid message fields. */ +#define LIBSPDM_STATUS_INVALID_MSG_FIELD \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0005) + +/* The received message's size is invalid. */ +#define LIBSPDM_STATUS_INVALID_MSG_SIZE \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0006) + +/* Unable to derive a common set of versions, algorithms, etc. */ +#define LIBSPDM_STATUS_NEGOTIATION_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0007) + +/* Received a Busy error message. */ +#define LIBSPDM_STATUS_BUSY_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0008) + +/* Received a NotReady error message. */ +#define LIBSPDM_STATUS_NOT_READY_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0009) + +/* Received an unexpected error message. */ +#define LIBSPDM_STATUS_ERROR_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000a) + +/* Received a RequestResynch error message. */ +#define LIBSPDM_STATUS_RESYNCH_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000b) + +/* Unable to append new data to buffer due to resource exhaustion. */ +#define LIBSPDM_STATUS_BUFFER_FULL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000c) + +/* Unable to return data because caller does not provide big enough buffer. */ +#define LIBSPDM_STATUS_BUFFER_TOO_SMALL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000d) + +/* Unable to allocate more session. */ +#define LIBSPDM_STATUS_SESSION_NUMBER_EXCEED \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000e) + +/* Decrypt error from peer. */ +#define LIBSPDM_STATUS_SESSION_MSG_ERROR \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x000f) + +/* Unable to acquire resource. */ +#define LIBSPDM_STATUS_ACQUIRE_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0010) + +/* Re-triable decrypt error from peer - must rollback to backup keys. */ +#define LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0011) + +/* - Cryptography Errors - */ + +/* Generic failure originating from the cryptography module. */ +#define LIBSPDM_STATUS_CRYPTO_ERROR \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CRYPTO, 0x0000) + +/* Verification of the provided signature digest, signature, or AEAD tag failed. */ +#define LIBSPDM_STATUS_VERIF_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CRYPTO, 0x0001) + +/* AEAD sequence number overflow. */ +#define LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CRYPTO, 0x0002) + +/* - Certificate Parsing Errors - */ + +/* Certificate is malformed or does not comply to x.509 standard. */ +#define LIBSPDM_STATUS_INVALID_CERT \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CERT_PARSE, 0x0000) + +/* - Transport Errors - */ + +/* Unable to send message to peer. */ +#define LIBSPDM_STATUS_SEND_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_TRANSPORT, 0x0000) + +/* Unable to receive message from peer. */ +#define LIBSPDM_STATUS_RECEIVE_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_TRANSPORT, 0x0001) + +/* - Measurement Collection Errors - */ + +/* Unable to collect measurement because of invalid index. */ +#define LIBSPDM_STATUS_MEAS_INVALID_INDEX \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_MEAS_COLLECT, 0x0000) + +/* Unable to collect measurement because of internal error. */ +#define LIBSPDM_STATUS_MEAS_INTERNAL_ERROR \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_MEAS_COLLECT, 0x0001) + +/* - Random Number Generation Errors - */ + +/* Unable to produce random number due to lack of entropy. */ +#define LIBSPDM_STATUS_LOW_ENTROPY \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_RNG, 0x0000) + +#endif diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h new file mode 100644 index 0000000000..6f7d2d0804 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h @@ -0,0 +1,650 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_SECURED_MESSAGE_LIB_H +#define SPDM_SECURED_MESSAGE_LIB_H + +#include "hal/base.h" +#include "industry_standard/spdm.h" +#include "industry_standard/spdm_secured_message.h" +#include "library/spdm_return_status.h" + +typedef enum { + LIBSPDM_SESSION_TYPE_NONE, + LIBSPDM_SESSION_TYPE_MAC_ONLY, + LIBSPDM_SESSION_TYPE_ENC_MAC, + LIBSPDM_SESSION_TYPE_MAX +} libspdm_session_type_t; + +typedef enum { + /* Before send KEY_EXCHANGE/PSK_EXCHANGE or after END_SESSION */ + LIBSPDM_SESSION_STATE_NOT_STARTED, + + /* After send KEY_EXHCNAGE, before send FINISH */ + LIBSPDM_SESSION_STATE_HANDSHAKING, + + /* After send FINISH, before END_SESSION */ + LIBSPDM_SESSION_STATE_ESTABLISHED, + + /* MAX */ + LIBSPDM_SESSION_STATE_MAX +} libspdm_session_state_t; + +/** + * Return the size in bytes of a single SPDM secured message context. + * + * @return the size in bytes of a single SPDM secured message context. + **/ +size_t libspdm_secured_message_get_context_size(void); + +/** + * Initialize an SPDM secured message context. + * + * The size in bytes of the spdm_secured_message_context can be returned by libspdm_secured_message_get_context_size. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + */ +void libspdm_secured_message_init_context(void *spdm_secured_message_context); + +/** + * Set use_psk to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param use_psk Indicate if the SPDM session use PSK. + */ +void libspdm_secured_message_set_use_psk(void *spdm_secured_message_context, bool use_psk); + +/** + * Set session_state to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_state Indicate the SPDM session state. + */ +void libspdm_secured_message_set_session_state( + void *spdm_secured_message_context, + libspdm_session_state_t session_state); + +/** + * Return session_state of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return the SPDM session state. + */ +libspdm_session_state_t +libspdm_secured_message_get_session_state(void *spdm_secured_message_context); + +/** + * Set session_type to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_type Indicate the SPDM session type. + */ +void libspdm_secured_message_set_session_type(void *spdm_secured_message_context, + libspdm_session_type_t session_type); + +/** + * Set algorithm to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param base_hash_algo Indicate the negotiated base_hash_algo for the SPDM session. + * @param dhe_named_group Indicate the negotiated dhe_named_group for the SPDM session. + * @param aead_cipher_suite Indicate the negotiated aead_cipher_suite for the SPDM session. + * @param key_schedule Indicate the negotiated key_schedule for the SPDM session. + */ +void libspdm_secured_message_set_algorithms(void *spdm_secured_message_context, + const spdm_version_number_t version, + const spdm_version_number_t secured_message_version, + uint32_t base_hash_algo, + uint16_t dhe_named_group, + uint16_t aead_cipher_suite, + uint16_t key_schedule); + +/** + * Set the psk_hint to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param psk_hint Indicate the PSK hint. + * @param psk_hint_size The size in bytes of the PSK hint. + */ +void libspdm_secured_message_set_psk_hint(void *spdm_secured_message_context, + const void *psk_hint, + size_t psk_hint_size); + +/** + * Import the DHE Secret to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param dhe_secret Indicate the DHE secret. + * @param dhe_secret_size The size in bytes of the DHE secret. + * + * @retval RETURN_SUCCESS DHE Secret is imported. + */ +bool +libspdm_secured_message_import_dhe_secret(void *spdm_secured_message_context, + const void *dhe_secret, + size_t dhe_secret_size); + +/** + * Export the Export Master Secret from an SPDM secured message context. + * + * The size of the Export Master Secret is the size of the digest of the negotiated hash algorithm. + * If the size of the destination buffer is less than the size of the Export Master Secret then + * the first export_master_secret_size bytes are copied. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param export_master_secret A pointer to the buffer to store the export_master_secret. + * @param export_master_secret_size On input, the size of the destination buffer. + * On output, the lesser of either the size of the destination + * buffer or the size of the Export Master Secret. + */ +bool libspdm_secured_message_export_master_secret( + void *spdm_secured_message_context, void *export_master_secret, + size_t *export_master_secret_size); + +/** + * Erase the Export Master Secret from an SPDM secured message context. This is typically called + * after libspdm_secured_message_export_master_secret(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + */ +void libspdm_secured_message_clear_export_master_secret(void *spdm_secured_message_context); + +#define LIBSPDM_SECURE_SESSION_KEYS_STRUCT_VERSION 1 + +#pragma pack(1) +typedef struct { + uint32_t version; + uint32_t aead_key_size; + uint32_t aead_iv_size; + /* uint8_t request_data_encryption_key[aead_key_size]; + * uint8_t request_data_salt[aead_iv_size]; + * uint64_t request_data_sequence_number; + * uint8_t response_data_encryption_key[aead_key_size]; + * uint8_t response_data_salt[aead_iv_size]; + * uint64_t response_data_sequence_number;*/ +} libspdm_secure_session_keys_struct_t; +#pragma pack() + +/** + * Export the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * + * @retval RETURN_SUCCESS session_keys are exported. + */ +bool libspdm_secured_message_export_session_keys(void *spdm_secured_message_context, + void *session_keys, + size_t *session_keys_size); + +/** + * Import the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * + * @retval RETURN_SUCCESS session_keys are imported. + */ +bool libspdm_secured_message_import_session_keys(void *spdm_secured_message_context, + const void *session_keys, + size_t session_keys_size); + +/** + * Allocates and Initializes one Diffie-Hellman Ephemeral (DHE) context for subsequent use, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param is_initiator if the caller is initiator. + * true: initiator + * false: not an initiator + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + **/ +void *libspdm_secured_message_dhe_new(spdm_version_number_t spdm_version, + uint16_t dhe_named_group, bool is_initiator); + +/** + * Release the specified DHE context, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context to be released. + **/ +void libspdm_secured_message_dhe_free(uint16_t dhe_named_group, void *dhe_context); + +/** + * Generates DHE public key, + * based upon negotiated DHE algorithm. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context. + * @param public_key Pointer to the buffer to receive generated public key. + * @param public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in bytes. + * + * @retval true DHE public key generation succeeded. + * @retval false DHE public key generation failed. + * @retval false public_key_size is not large enough. + **/ +bool libspdm_secured_message_dhe_generate_key(uint16_t dhe_named_group, + void *dhe_context, + uint8_t *public_key, + size_t *public_key_size); + +/** + * Computes exchanged common key, + * based upon negotiated DHE algorithm. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context. + * @param peer_public_key Pointer to the peer's public key. + * @param peer_public_key_size size of peer's public key in bytes. + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @retval true DHE exchanged key generation succeeded. + * @retval false DHE exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +bool libspdm_secured_message_dhe_compute_key( + uint16_t dhe_named_group, void *dhe_context, + const uint8_t *peer_public, size_t peer_public_size, + void *spdm_secured_message_context); + +/** + * This function is used to clear handshake secret. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + **/ +void libspdm_clear_handshake_secret(void *spdm_secured_message_context); + +/** + * This function is used to clear the master secret; + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + **/ +void libspdm_clear_master_secret(void *spdm_secured_message_context); + +/** + * Allocates and initializes one HMAC context for subsequent use, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return Pointer to the HMAC context that has been initialized. + **/ +void *libspdm_hmac_new_with_request_finished_key(void *spdm_secured_message_context); + +/** + * Release the specified HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free_with_request_finished_key( + void *spdm_secured_message_context, void *hmac_ctx); + +/** + * Set request_finished_key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +bool libspdm_hmac_init_with_request_finished_key( + void *spdm_secured_message_context, void *hmac_ctx); + +/** + * Makes a copy of an existing HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + **/ +bool libspdm_hmac_duplicate_with_request_finished_key( + void *spdm_secured_message_context, + const void *hmac_ctx, void *new_hmac_ctx); + +/** + * Digests the input data and updates HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param data Pointer to the buffer containing the data to be digested. + * @param data_size size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_update_with_request_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC digest value, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param hmac_value Pointer to a buffer that receives the HMAC digest value + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_final_with_request_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC of a input data buffer, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all_with_request_finished_key(void *spdm_secured_message_context, + const void *data, size_t data_size, + uint8_t *hmac_value); + +/** + * Allocates and initializes one HMAC context for subsequent use, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return Pointer to the HMAC context that has been initialized. + **/ +void *libspdm_hmac_new_with_response_finished_key(void *spdm_secured_message_context); + +/** + * Release the specified HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free_with_response_finished_key( + void *spdm_secured_message_context, void *hmac_ctx); + +/** + * Set response_finished_key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +bool libspdm_hmac_init_with_response_finished_key( + void *spdm_secured_message_context, void *hmac_ctx); + +/** + * Makes a copy of an existing HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + **/ +bool libspdm_hmac_duplicate_with_response_finished_key( + void *spdm_secured_message_context, + const void *hmac_ctx, void *new_hmac_ctx); + +/** + * Digests the input data and updates HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param data Pointer to the buffer containing the data to be digested. + * @param data_size size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_update_with_response_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, const void *data, + size_t data_size); + +/** + * Completes computation of the HMAC digest value, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param hmac_value Pointer to a buffer that receives the HMAC digest value + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_final_with_response_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, uint8_t *hmac_value); + +/** + * Computes the HMAC of a input data buffer, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all_with_response_finished_key( + void *spdm_secured_message_context, const void *data, + size_t data_size, uint8_t *hmac_value); + +/** + * This function concatenates binary data, which is used as info in HKDF expand later. + * + * @param label An ascii string label for the libspdm_bin_concat. + * @param label_size The size in bytes of the ASCII string label, not including NULL terminator. + * @param context A pre-defined hash value as the context for the libspdm_bin_concat. + * @param length 16 bits length for the libspdm_bin_concat. + * @param hash_size The size in bytes of the context hash. + * @param out_bin The buffer to store the output binary. + * @param out_bin_size The size in bytes for the out_bin. + **/ +void libspdm_bin_concat(spdm_version_number_t spdm_version, + const char *label, size_t label_size, + const uint8_t *context, uint16_t length, + size_t hash_size, uint8_t *out_bin, + size_t *out_bin_size); + +/** + * This function generates SPDM HandshakeKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param th1_hash_data th1 hash + * + * @retval RETURN_SUCCESS SPDM HandshakeKey for a session is generated. + **/ +bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, + const uint8_t *th1_hash_data); + +/** + * This function generates SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param th2_hash_data th2 hash + * + * @retval RETURN_SUCCESS SPDM DataKey for a session is generated. + **/ +bool libspdm_generate_session_data_key(void *spdm_secured_message_context, + const uint8_t *th2_hash_data); + +typedef enum { + LIBSPDM_KEY_UPDATE_OPERATION_CREATE_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_COMMIT_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_DISCARD_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_MAX +} libspdm_key_update_operation_t; + +typedef enum { + LIBSPDM_KEY_UPDATE_ACTION_REQUESTER, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, + LIBSPDM_KEY_UPDATE_ACTION_MAX +} libspdm_key_update_action_t; + +/** + * This function creates the updates of SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param action Indicate of the key update action. + * + * @retval RETURN_SUCCESS SPDM DataKey update is created. + **/ +bool libspdm_create_update_session_data_key(void *spdm_secured_message_context, + libspdm_key_update_action_t action); + +/** + * This function activates the update of SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param action Indicate of the key update action. + * @param use_new_key Indicate if the new key should be used. + * + * @retval RETURN_SUCCESS SPDM DataKey update is activated. + **/ +bool libspdm_activate_update_session_data_key(void *spdm_secured_message_context, + libspdm_key_update_action_t action, + bool use_new_key); + +/** + * Get sequence number in an SPDM secure message. + * + * This value is transport layer specific. + * + * @param sequence_number The current sequence number used to encode or decode message. + * @param sequence_number_buffer A buffer to hold the sequence number output used in the secured message. + * The size in byte of the output buffer shall be 8. + * + * @return size in byte of the sequence_number_buffer. + * It shall be no greater than 8. + * 0 means no sequence number is required. + **/ +typedef uint8_t (*libspdm_secured_message_get_sequence_number_func)( + uint64_t sequence_number, uint8_t *sequence_number_buffer); + +/** + * Return max random number count in an SPDM secure message. + * + * This value is transport layer specific. + * + * @return Max random number count in an SPDM secured message. + * 0 means no randum number is required. + **/ +typedef uint32_t (*libspdm_secured_message_get_max_random_number_count_func)(void); + +#define SPDM_SECURED_MESSAGE_CALLBACKS_VERSION 1 + +typedef struct { + uint32_t version; + libspdm_secured_message_get_sequence_number_func get_sequence_number; + libspdm_secured_message_get_max_random_number_count_func get_max_random_number_count; +} libspdm_secured_message_callbacks_t; + +typedef struct { + uint8_t error_code; + uint32_t session_id; +} libspdm_error_struct_t; + +/** + * Encode an application message to a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_requester Indicates if it is a requester message. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a source buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer. + * Before app_message, there is room for spdm_secured_message_cipher_header_t. + * After (app_message + app_message_size), there is room for random bytes. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a destination buffer to store the secured message. + * It shall point to the acquired sender buffer. + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is encoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + **/ +libspdm_return_t libspdm_encode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_requester, size_t app_message_size, + void *app_message, size_t *secured_message_size, + void *secured_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks); + +/** + * Decode an application message from a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_requester Indicates if it is a requester message. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a source buffer to store the secured message. + * It shall point to the acquired receiver buffer. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a destination buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer to hold the decrypted message + * On output, the app_message pointer shall be inside of [app_message, app_message + app_message_size] + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is decoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_UNSUPPORTED The secured_message is unsupported. + **/ +libspdm_return_t libspdm_decode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_requester, size_t secured_message_size, + void *secured_message, size_t *app_message_size, + void **app_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks); + +/** + * Get the last SPDM error struct of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param last_spdm_error Last SPDM error struct of an SPDM secured message context. + */ +void libspdm_secured_message_get_last_spdm_error_struct( + void *spdm_secured_message_context, + libspdm_error_struct_t *last_spdm_error); + +/** + * Set the last SPDM error struct of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param last_spdm_error Last SPDM error struct of an SPDM secured message context. + */ +void libspdm_secured_message_set_last_spdm_error_struct( + void *spdm_secured_message_context, + const libspdm_error_struct_t *last_spdm_error); + +#endif /* SPDM_SECURED_MESSAGE_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c new file mode 100644 index 0000000000..b93f13ba61 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c @@ -0,0 +1,2420 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" +#include "internal/libspdm_secured_message_lib.h" + +/** + * Returns if an SPDM data_type requires session info. + * + * @param data_type SPDM data type. + * + * @retval true session info is required. + * @retval false session info is not required. + **/ +static bool need_session_info_for_data(libspdm_data_type_t data_type) +{ + switch (data_type) { + case LIBSPDM_DATA_SESSION_USE_PSK: + case LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED: + case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: + case LIBSPDM_DATA_SESSION_POLICY: + return true; + default: + return false; + } +} + +/** + * Set an SPDM context data. + * + * @param spdm_context A pointer to the SPDM context. + * @param data_type Type of the SPDM context data. + * @param parameter Type specific parameter of the SPDM context data. + * @param data A pointer to the SPDM context data. + * @param data_size size in bytes of the SPDM context data. + * + * @retval RETURN_SUCCESS The SPDM context data is set successfully. + * @retval RETURN_INVALID_PARAMETER The data is NULL or the data_type is zero. + * @retval RETURN_UNSUPPORTED The data_type is unsupported. + * @retval RETURN_ACCESS_DENIED The data_type cannot be set. + * @retval RETURN_NOT_READY data is not ready to set. + **/ +libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, + const libspdm_data_parameter_t *parameter, void *data, + size_t data_size) +{ + libspdm_context_t *spdm_context; + uint32_t session_id; + libspdm_session_info_t *session_info; + uint8_t slot_id; + uint8_t mut_auth_requested; + uint8_t root_cert_index; +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + bool status; +#endif + + if (context == NULL || data == NULL || data_type >= LIBSPDM_DATA_MAX) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + spdm_context = context; + + if (need_session_info_for_data(data_type)) { + if (parameter->location != LIBSPDM_DATA_LOCATION_SESSION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_id = *(const uint32_t *)parameter->additional_data; + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + } else { + session_info = NULL; + } + + switch (data_type) { + case LIBSPDM_DATA_SPDM_VERSION: + LIBSPDM_ASSERT (data_size <= sizeof(spdm_version_number_t) * SPDM_MAX_VERSION_COUNT); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + /* Only have one connected version */ + LIBSPDM_ASSERT (data_size == sizeof(spdm_version_number_t)); + libspdm_copy_mem(&(spdm_context->connection_info.version), + sizeof(spdm_context->connection_info.version), + data, + sizeof(spdm_version_number_t)); + } else { + spdm_context->local_context.version.spdm_version_count = + (uint8_t)(data_size / sizeof(spdm_version_number_t)); + libspdm_copy_mem(spdm_context->local_context.version.spdm_version, + sizeof(spdm_context->local_context.version.spdm_version), + data, + spdm_context->local_context.version.spdm_version_count * + sizeof(spdm_version_number_t)); + } + break; + case LIBSPDM_DATA_SECURED_MESSAGE_VERSION: + LIBSPDM_ASSERT (data_size <= sizeof(spdm_version_number_t) * SPDM_MAX_VERSION_COUNT); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + /* Only have one connected version */ + LIBSPDM_ASSERT (data_size == sizeof(spdm_version_number_t)); + libspdm_copy_mem(&(spdm_context->connection_info.secured_message_version), + sizeof(spdm_context->connection_info.secured_message_version), + data, + sizeof(spdm_version_number_t)); + } else { + spdm_context->local_context.secured_message_version + .spdm_version_count = (uint8_t)(data_size / sizeof(spdm_version_number_t)); + libspdm_copy_mem(spdm_context->local_context + .secured_message_version.spdm_version, + sizeof(spdm_context->local_context + .secured_message_version.spdm_version), + data, + spdm_context->local_context.secured_message_version. + spdm_version_count * sizeof(spdm_version_number_t)); + } + break; + case LIBSPDM_DATA_CAPABILITY_FLAGS: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + #if !(LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_CERT_CAP */ + + #if !(LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP */ + + #if !(LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + + #if !(LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP) == + 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + + #if !(LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) + LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.capability.flags = *(uint32_t *)data; + } else { + spdm_context->local_context.capability.flags = *(uint32_t *)data; + } + break; + case LIBSPDM_DATA_CAPABILITY_CT_EXPONENT: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.capability.ct_exponent = *(uint8_t *)data; + break; + case LIBSPDM_DATA_CAPABILITY_RTT_US: + if (data_size != sizeof(uint64_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.capability.rtt = *(uint64_t *)data; + break; + case LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + /* Only allow set smaller value*/ + LIBSPDM_ASSERT (*(uint32_t *)data <= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + spdm_context->local_context.capability.data_transfer_size = *(uint32_t *)data; + break; + case LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + /* Only allow set smaller value. Need different value for CHUNK - TBD*/ + LIBSPDM_ASSERT (*(uint32_t *)data <= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + spdm_context->local_context.capability.max_spdm_msg_size = *(uint32_t *)data; + break; + case LIBSPDM_DATA_MEASUREMENT_SPEC: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.measurement_spec = *(uint8_t *)data; + } else { + spdm_context->local_context.algorithm.measurement_spec = *(uint8_t *)data; + } + break; + case LIBSPDM_DATA_MEASUREMENT_HASH_ALGO: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.measurement_hash_algo = *(uint32_t *)data; + } else { + spdm_context->local_context.algorithm.measurement_hash_algo = *(uint32_t *)data; + } + break; + case LIBSPDM_DATA_BASE_ASYM_ALGO: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.base_asym_algo = *(uint32_t *)data; + } else { + spdm_context->local_context.algorithm.base_asym_algo = *(uint32_t *)data; + } + break; + case LIBSPDM_DATA_BASE_HASH_ALGO: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.base_hash_algo = *(uint32_t *)data; + } else { + spdm_context->local_context.algorithm.base_hash_algo = *(uint32_t *)data; + } + break; + case LIBSPDM_DATA_DHE_NAME_GROUP: + if (data_size != sizeof(uint16_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.dhe_named_group = *(uint16_t *)data; + } else { + spdm_context->local_context.algorithm.dhe_named_group = *(uint16_t *)data; + } + break; + case LIBSPDM_DATA_AEAD_CIPHER_SUITE: + if (data_size != sizeof(uint16_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.aead_cipher_suite = *(uint16_t *)data; + } else { + spdm_context->local_context.algorithm.aead_cipher_suite = *(uint16_t *)data; + } + break; + case LIBSPDM_DATA_REQ_BASE_ASYM_ALG: + if (data_size != sizeof(uint16_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.req_base_asym_alg = *(uint16_t *)data; + } else { + spdm_context->local_context.algorithm.req_base_asym_alg = *(uint16_t *)data; + } + break; + case LIBSPDM_DATA_KEY_SCHEDULE: + if (data_size != sizeof(uint16_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.key_schedule = *(uint16_t *)data; + } else { + spdm_context->local_context.algorithm.key_schedule = *(uint16_t *)data; + } + break; + case LIBSPDM_DATA_OTHER_PARAMS_SUPPORT: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + spdm_context->connection_info.algorithm.other_params_support = *(uint8_t *)data; + } else { + spdm_context->local_context.algorithm.other_params_support = *(uint8_t *)data; + } + break; + case LIBSPDM_DATA_CONNECTION_STATE: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->connection_info.connection_state = *(uint32_t *)data; + break; + case LIBSPDM_DATA_RESPONSE_STATE: + if (data_size != sizeof(uint32_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->response_state = *(uint32_t *)data; + break; + case LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT: + root_cert_index = 0; + while (spdm_context->local_context.peer_root_cert_provision[root_cert_index] != NULL) { + root_cert_index++; + if (root_cert_index >= LIBSPDM_MAX_ROOT_CERT_SUPPORT) { + return LIBSPDM_STATUS_BUFFER_FULL; + } + } + spdm_context->local_context.peer_root_cert_provision_size[root_cert_index] = data_size; + spdm_context->local_context.peer_root_cert_provision[root_cert_index] = data; + break; + case LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN: + spdm_context->local_context.peer_cert_chain_provision_size = data_size; + spdm_context->local_context.peer_cert_chain_provision = data; + break; + case LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN: + slot_id = parameter->additional_data[0]; + if (slot_id >= SPDM_MAX_SLOT_COUNT) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.local_cert_chain_provision_size[slot_id] = data_size; + spdm_context->local_context.local_cert_chain_provision[slot_id] = data; + break; + case LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN_DEFAULT_SLOT_ID: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (*(uint8_t *)data >= SPDM_MAX_SLOT_COUNT) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.provisioned_slot_id = *(uint8_t *)data; + break; + case LIBSPDM_DATA_LOCAL_USED_CERT_CHAIN_BUFFER: + if (data_size > LIBSPDM_MAX_CERT_CHAIN_SIZE) { + return LIBSPDM_STATUS_BUFFER_FULL; + } + spdm_context->connection_info.local_used_cert_chain_buffer_size = data_size; + spdm_context->connection_info.local_used_cert_chain_buffer = data; + break; + case LIBSPDM_DATA_PEER_USED_CERT_CHAIN_BUFFER: + slot_id = parameter->additional_data[0]; + if (slot_id >= SPDM_MAX_SLOT_COUNT) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (data_size > LIBSPDM_MAX_CERT_CHAIN_SIZE) { + return LIBSPDM_STATUS_BUFFER_FULL; + } + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size = data_size; + libspdm_copy_mem(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer, + sizeof(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer), + data, data_size); +#else + status = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + data, data_size, + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash); + if (!status) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size = + libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + status = false; +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) + if (!status) { + status = libspdm_rsa_get_public_key_from_x509( + data, data_size, + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + } +#endif +#if LIBSPDM_ECDSA_SUPPORT + if (!status) { + status = libspdm_ec_get_public_key_from_x509( + data, data_size, + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + } +#endif +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + if (!status) { + status = libspdm_ecd_get_public_key_from_x509( + data, data_size, + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + } +#endif +#if LIBSPDM_SM2_DSA_SUPPORT + if (!status) { + status = libspdm_sm2_get_public_key_from_x509( + data, data_size, + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + } +#endif + if (!status) { + return LIBSPDM_STATUS_INVALID_CERT; + } +#endif + break; + case LIBSPDM_DATA_BASIC_MUT_AUTH_REQUESTED: + if (data_size != sizeof(bool)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + mut_auth_requested = *(uint8_t *)data; + if (((mut_auth_requested != 0) && (mut_auth_requested != 1))) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.basic_mut_auth_requested = mut_auth_requested; + spdm_context->encap_context.request_id = 0; + spdm_context->encap_context.req_slot_id = parameter->additional_data[0]; + break; + case LIBSPDM_DATA_MUT_AUTH_REQUESTED: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + mut_auth_requested = *(uint8_t *)data; + if (((mut_auth_requested != 0) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS))) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.mut_auth_requested = mut_auth_requested; + spdm_context->encap_context.request_id = 0; + spdm_context->encap_context.req_slot_id = parameter->additional_data[0]; + break; + case LIBSPDM_DATA_HEARTBEAT_PERIOD: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.heartbeat_period = *(uint8_t *)data; + break; + case LIBSPDM_DATA_PSK_HINT: + if (data_size > LIBSPDM_PSK_MAX_HINT_LENGTH) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.psk_hint_size = data_size; + spdm_context->local_context.psk_hint = data; + break; + case LIBSPDM_DATA_SESSION_USE_PSK: + if (data_size != sizeof(bool)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_info->use_psk = *(bool *)data; + break; + case LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_info->mut_auth_requested = *(uint8_t *)data; + break; + case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_info->end_session_attributes = *(uint8_t *)data; + break; + case LIBSPDM_DATA_SESSION_POLICY: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_info->session_policy = *(uint8_t *)data; + break; + case LIBSPDM_DATA_APP_CONTEXT_DATA: + if (data_size != sizeof(void *) || *(void **)data == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->app_context_data_ptr = *(void **)data; + break; + case LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->handle_error_return_policy = *(uint8_t *)data; + break; + case LIBSPDM_DATA_VCA_CACHE: + if (data_size > sizeof(spdm_context->transcript.message_a.buffer)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->transcript.message_a.buffer_size = data_size; + libspdm_copy_mem(spdm_context->transcript.message_a.buffer, + sizeof(spdm_context->transcript.message_a.buffer), + data, data_size); + break; + case LIBSPDM_DATA_IS_REQUESTER: + if (data_size != sizeof(bool)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + spdm_context->local_context.is_requester = *(bool *)data; + break; + default: + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + break; + } + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Get an SPDM context data. + * + * @param spdm_context A pointer to the SPDM context. + * @param data_type Type of the SPDM context data. + * @param parameter Type specific parameter of the SPDM context data. + * @param data A pointer to the SPDM context data. + * @param data_size size in bytes of the SPDM context data. + * On input, it means the size in bytes of data buffer. + * On output, it means the size in bytes of copied data buffer if RETURN_SUCCESS, + * and means the size in bytes of desired data buffer if RETURN_BUFFER_TOO_SMALL. + * + * @retval RETURN_SUCCESS The SPDM context data is set successfully. + * @retval RETURN_INVALID_PARAMETER The data_size is NULL or the data is NULL and *data_size is not zero. + * @retval RETURN_UNSUPPORTED The data_type is unsupported. + * @retval RETURN_NOT_FOUND The data_type cannot be found. + * @retval RETURN_NOT_READY The data is not ready to return. + * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. + **/ +libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, + const libspdm_data_parameter_t *parameter, + void *data, size_t *data_size) +{ + libspdm_context_t *spdm_context; + size_t target_data_size; + void *target_data; + uint32_t session_id; + libspdm_session_info_t *session_info; + size_t digest_size; + size_t digest_count; + size_t index; + + if (context == NULL || data == NULL || data_size == NULL || data_type >= LIBSPDM_DATA_MAX) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + spdm_context = context; + + if (need_session_info_for_data(data_type)) { + if (parameter->location != LIBSPDM_DATA_LOCATION_SESSION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + session_id = *(const uint32_t *)parameter->additional_data; + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + } else { + session_info = NULL; + } + + switch (data_type) { + case LIBSPDM_DATA_SPDM_VERSION: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(spdm_version_number_t); + target_data = &(spdm_context->connection_info.version); + break; + case LIBSPDM_DATA_SECURED_MESSAGE_VERSION: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(spdm_version_number_t); + target_data = &(spdm_context->connection_info.secured_message_version); + break; + case LIBSPDM_DATA_CAPABILITY_FLAGS: + target_data_size = sizeof(uint32_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + target_data = &spdm_context->connection_info.capability.flags; + } else { + target_data = &spdm_context->local_context.capability.flags; + } + break; + case LIBSPDM_DATA_CAPABILITY_CT_EXPONENT: + target_data_size = sizeof(uint8_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + target_data = &spdm_context->connection_info.capability.ct_exponent; + } else { + target_data = &spdm_context->local_context.capability.ct_exponent; + } + break; + case LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE: + target_data_size = sizeof(uint32_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + target_data = &spdm_context->connection_info.capability.data_transfer_size; + } else { + target_data = &spdm_context->local_context.capability.data_transfer_size; + } + break; + case LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE: + target_data_size = sizeof(uint32_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + target_data = &spdm_context->connection_info.capability.max_spdm_msg_size; + } else { + target_data = &spdm_context->local_context.capability.max_spdm_msg_size; + } + break; + case LIBSPDM_DATA_MEASUREMENT_SPEC: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint8_t); + target_data = &spdm_context->connection_info.algorithm.measurement_spec; + break; + case LIBSPDM_DATA_MEASUREMENT_HASH_ALGO: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->connection_info.algorithm.measurement_hash_algo; + break; + case LIBSPDM_DATA_BASE_ASYM_ALGO: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->connection_info.algorithm.base_asym_algo; + break; + case LIBSPDM_DATA_BASE_HASH_ALGO: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->connection_info.algorithm.base_hash_algo; + break; + case LIBSPDM_DATA_DHE_NAME_GROUP: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint16_t); + target_data = &spdm_context->connection_info.algorithm.dhe_named_group; + break; + case LIBSPDM_DATA_AEAD_CIPHER_SUITE: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint16_t); + target_data = &spdm_context->connection_info.algorithm.aead_cipher_suite; + break; + case LIBSPDM_DATA_REQ_BASE_ASYM_ALG: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint16_t); + target_data = &spdm_context->connection_info.algorithm.req_base_asym_alg; + break; + case LIBSPDM_DATA_KEY_SCHEDULE: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint16_t); + target_data = &spdm_context->connection_info.algorithm.key_schedule; + break; + case LIBSPDM_DATA_OTHER_PARAMS_SUPPORT: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint8_t); + target_data = &spdm_context->connection_info.algorithm.other_params_support; + break; + case LIBSPDM_DATA_CONNECTION_STATE: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->connection_info.connection_state; + break; + case LIBSPDM_DATA_RESPONSE_STATE: + target_data_size = sizeof(uint32_t); + target_data = &spdm_context->response_state; + break; + case LIBSPDM_DATA_PEER_SLOT_MASK: + target_data_size = sizeof(uint8_t); + target_data = &spdm_context->connection_info.peer_digest_slot_mask; + break; + case LIBSPDM_DATA_PEER_TOTAL_DIGEST_BUFFER: + digest_count = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (spdm_context->connection_info.peer_digest_slot_mask & (1 << index)) { + digest_count++; + } + } + digest_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + target_data_size = digest_size * digest_count; + target_data = spdm_context->connection_info.peer_total_digest_buffer; + break; + case LIBSPDM_DATA_SESSION_USE_PSK: + target_data_size = sizeof(bool); + target_data = &session_info->use_psk; + break; + case LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED: + target_data_size = sizeof(uint8_t); + target_data = &session_info->mut_auth_requested; + break; + case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: + target_data_size = sizeof(uint8_t); + target_data = &session_info->end_session_attributes; + break; + case LIBSPDM_DATA_SESSION_POLICY: + target_data_size = sizeof(uint8_t); + target_data = &session_info->session_policy; + break; + case LIBSPDM_DATA_APP_CONTEXT_DATA: + target_data_size = sizeof(void *); + target_data = &spdm_context->app_context_data_ptr; + break; + case LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY: + target_data_size = sizeof(uint8_t); + target_data = &spdm_context->handle_error_return_policy; + break; + case LIBSPDM_DATA_VCA_CACHE: + target_data_size = spdm_context->transcript.message_a.buffer_size; + target_data = spdm_context->transcript.message_a.buffer; + break; + default: + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + break; + } + + if (*data_size < target_data_size) { + *data_size = target_data_size; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + libspdm_copy_mem(data, *data_size, target_data, target_data_size); + *data_size = target_data_size; + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Reset message A cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_a(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + libspdm_reset_managed_buffer(&spdm_context->transcript.message_a); +} + +/** + * Reset message B cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_b(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_context->transcript.message_b); +#else + if (spdm_context->transcript.digest_context_m1m2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + } +#endif +} + +/** + * Reset message C cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_c(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_context->transcript.message_c); +#else + if (spdm_context->transcript.digest_context_m1m2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + } +#endif +} + +/** + * Reset message MutB cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_mut_b(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_context->transcript.message_mut_b); +#else + if (spdm_context->transcript.digest_context_mut_m1m2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + } +#endif +} + +/** + * Reset message MutC cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + **/ +void libspdm_reset_message_mut_c(void *context) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_context->transcript.message_mut_c); +#else + if (spdm_context->transcript.digest_context_mut_m1m2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + } +#endif +} + +/** + * Reset message M cache in SPDM context. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_m(void *context, void *session_info) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *spdm_session_info; + + spdm_context = context; + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + if (spdm_session_info == NULL) { + libspdm_reset_managed_buffer(&spdm_context->transcript.message_m); + } else { + libspdm_reset_managed_buffer(&spdm_session_info->session_transcript.message_m); + } +#else + if (spdm_session_info == NULL) { + if (spdm_context->transcript.digest_context_l1l2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + spdm_context->transcript.digest_context_l1l2 = NULL; + } + } else { + if (spdm_session_info->session_transcript.digest_context_l1l2 != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + spdm_session_info->session_transcript.digest_context_l1l2 = NULL; + } + } +#endif +} + +/** + * Reset message K cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_k(void *context, void *session_info) +{ + libspdm_session_info_t *spdm_session_info; + + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_session_info->session_transcript.message_k); +#else + { + libspdm_context_t *spdm_context; + + spdm_context = context; + + if (spdm_session_info->session_transcript.digest_context_th != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + spdm_session_info->session_transcript.digest_context_th = NULL; + } + if (spdm_session_info->session_transcript.digest_context_th_backup != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th_backup); + spdm_session_info->session_transcript.digest_context_th_backup = NULL; + } + } +#endif +} + +/** + * Reset message F cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + **/ +void libspdm_reset_message_f(void *context, void *session_info) +{ + libspdm_session_info_t *spdm_session_info; + + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_reset_managed_buffer(&spdm_session_info->session_transcript.message_f); +#else + { + libspdm_context_t *spdm_context; + + spdm_context = context; + + if (spdm_session_info->session_transcript.digest_context_th != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + spdm_session_info->session_transcript.digest_context_th = + spdm_session_info->session_transcript.digest_context_th_backup; + spdm_session_info->session_transcript.digest_context_th_backup = NULL; + } + spdm_session_info->session_transcript.message_f_initialized = false; + } +#endif +} + +/** + * Reset message buffer in SPDM context according to request code. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param spdm_request The SPDM request code. + */ +void libspdm_reset_message_buffer_via_request_code(void *context, void *session_info, + uint8_t request_code) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + /** + * Any request other than SPDM_GET_MEASUREMENTS resets L1/L2 + */ + if (request_code != SPDM_GET_MEASUREMENTS) { + libspdm_reset_message_m(spdm_context, session_info); + } + /** + * If the Requester issued GET_MEASUREMENTS or KEY_EXCHANGE or FINISH or PSK_EXCHANGE + * or PSK_FINISH or KEY_UPDATE or HEARTBEAT or GET_ENCAPSULATED_REQUEST or DELIVER_ENCAPSULATED_RESPONSE + * or END_SESSSION request(s) and skipped CHALLENGE completion, M1 and M2 are reset to null. + */ + switch (request_code) + { + case SPDM_KEY_EXCHANGE: + case SPDM_GET_MEASUREMENTS: + case SPDM_FINISH: + case SPDM_PSK_EXCHANGE: + case SPDM_PSK_FINISH: + case SPDM_KEY_UPDATE: + case SPDM_HEARTBEAT: + case SPDM_GET_ENCAPSULATED_REQUEST: + case SPDM_END_SESSION: + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_AUTHENTICATED) { + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + libspdm_reset_message_mut_b(spdm_context); + libspdm_reset_message_mut_c(spdm_context); + } + break; + case SPDM_DELIVER_ENCAPSULATED_RESPONSE: + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_AUTHENTICATED) { + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + } + break; + case SPDM_GET_DIGESTS: + libspdm_reset_message_b(spdm_context); + break; + default: + break; + } +} +/** + * Append message A cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_a(void *context, const void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + return libspdm_append_managed_buffer(&spdm_context->transcript.message_a, + message, message_size); +} + +/** + * Append message B cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_b(void *context, const void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer(&spdm_context->transcript.message_b, + message, message_size); +#else + { + bool result; + + if (spdm_context->transcript.digest_context_m1m2 == NULL) { + spdm_context->transcript.digest_context_m1m2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_m1m2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript. + message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message C cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_c(void *context, const void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer(&spdm_context->transcript.message_c, + message, message_size); +#else + { + bool result; + + if (spdm_context->transcript.digest_context_m1m2 == NULL) { + spdm_context->transcript.digest_context_m1m2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_m1m2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript. + message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2); + spdm_context->transcript.digest_context_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message MutB cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_mut_b(void *context, const void *message, + size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer(&spdm_context->transcript.message_mut_b, + message, message_size); +#else + { + bool result; + + if (spdm_context->transcript.digest_context_mut_m1m2 == NULL) { + spdm_context->transcript.digest_context_mut_m1m2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_mut_m1m2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script */ + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message MutC cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_mut_c(void *context, const void *message, + size_t message_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer(&spdm_context->transcript.message_mut_c, + message, message_size); +#else + { + bool result; + + if (spdm_context->transcript.digest_context_mut_m1m2 == NULL) { + spdm_context->transcript.digest_context_mut_m1m2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_mut_m1m2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script */ + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2); + spdm_context->transcript.digest_context_mut_m1m2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message M cache in SPDM context. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_m(void *context, void *session_info, + const void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *spdm_session_info; + + spdm_context = context; + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + if (spdm_session_info == NULL) { + return libspdm_append_managed_buffer(&spdm_context->transcript.message_m, + message, message_size); + } else { + return libspdm_append_managed_buffer(&spdm_session_info->session_transcript.message_m, + message, message_size); + } +#else + { + bool result; + + if (spdm_session_info == NULL) { + if (spdm_context->transcript.digest_context_l1l2 == NULL) { + spdm_context->transcript.digest_context_l1l2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_context->transcript.digest_context_l1l2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + spdm_context->transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script */ + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2, + libspdm_get_managed_buffer( + &spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + spdm_context->transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2, message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2); + spdm_context->transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } else { + if (spdm_session_info->session_transcript.digest_context_l1l2 == NULL) { + spdm_session_info->session_transcript.digest_context_l1l2 = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_session_info->session_transcript.digest_context_l1l2 == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + spdm_session_info->session_transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script*/ + + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2, + libspdm_get_managed_buffer( + &spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript. + message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + spdm_session_info->session_transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2, + message, message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2); + spdm_session_info->session_transcript.digest_context_l1l2 = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message K cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_k(void *context, void *session_info, + bool is_requester, const void *message, + size_t message_size) +{ + libspdm_session_info_t *spdm_session_info; + + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer( + &spdm_session_info->session_transcript.message_k, message, + message_size); +#else + { + libspdm_context_t *spdm_context; + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + bool result; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size; + uint8_t slot_id; + + hash_size = 0; + spdm_context = context; + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + + if (spdm_session_info->session_transcript.digest_context_th == NULL) { + if (!spdm_session_info->use_psk) { + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (is_requester) { + if(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size + != 0) { + hash_size = + spdm_context->connection_info.peer_used_cert_chain[slot_id]. + buffer_hash_size; + libspdm_copy_mem(cert_chain_buffer_hash, + sizeof(cert_chain_buffer_hash), + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash, + hash_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_PEER; + } + hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + } + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + } + + + /* prepare digest_context_th*/ + + if (spdm_session_info->session_transcript.digest_context_th == NULL) { + spdm_session_info->session_transcript.digest_context_th = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_session_info->session_transcript.digest_context_th == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_init (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + libspdm_get_managed_buffer(&spdm_context->transcript. + message_a), + libspdm_get_managed_buffer_size( + &spdm_context->transcript.message_a)); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + if (!spdm_session_info->use_psk) { + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + cert_chain_buffer_hash, hash_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * Append message F cache in SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param spdm_session_info A pointer to the SPDM session context. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param message message buffer. + * @param message_size size in bytes of message buffer. + * + * @return RETURN_SUCCESS message is appended. + * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. + **/ +libspdm_return_t libspdm_append_message_f(void *context, void *session_info, + bool is_requester, const void *message, + size_t message_size) +{ + libspdm_session_info_t *spdm_session_info; + + spdm_session_info = session_info; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + return libspdm_append_managed_buffer( + &spdm_session_info->session_transcript.message_f, message, + message_size); +#else + { + libspdm_context_t *spdm_context; + const uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + bool result; + uint8_t mut_cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size; + libspdm_return_t status; + uint8_t slot_id; + + hash_size = 0; + spdm_context = context; + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + + if (!spdm_session_info->session_transcript.message_f_initialized) { + + /* digest_context_th might be NULL in unit test, where message_k is hardcoded. */ + if (spdm_session_info->session_transcript.digest_context_th == NULL) { + status = libspdm_append_message_k (context, session_info, is_requester, NULL, 0); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + } + + if (!spdm_session_info->use_psk && spdm_session_info->mut_auth_requested) { + if (is_requester) { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + mut_cert_chain_buffer, mut_cert_chain_buffer_size, + mut_cert_chain_buffer_hash); + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } else { + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size + != 0) { + hash_size = + spdm_context->connection_info.peer_used_cert_chain[slot_id]. + buffer_hash_size; + libspdm_copy_mem(mut_cert_chain_buffer_hash, + sizeof(mut_cert_chain_buffer_hash), + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash, + hash_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_PEER; + } + hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + mut_cert_chain_buffer, mut_cert_chain_buffer_size, + mut_cert_chain_buffer_hash); + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + } + + /* It is first time call, backup current message_k context + * this backup will be used in reset_message_f.*/ + + LIBSPDM_ASSERT (spdm_session_info->session_transcript.digest_context_th != NULL); + spdm_session_info->session_transcript.digest_context_th_backup = libspdm_hash_new ( + spdm_context->connection_info.algorithm.base_hash_algo); + if (spdm_session_info->session_transcript.digest_context_th_backup == NULL) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + spdm_session_info->session_transcript.digest_context_th_backup); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th_backup); + spdm_session_info->session_transcript.digest_context_th_backup = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + + /* prepare digest_context_th*/ + + LIBSPDM_ASSERT (spdm_session_info->session_transcript.digest_context_th != NULL); + if (!spdm_session_info->session_transcript.message_f_initialized) { + if (!spdm_session_info->use_psk && spdm_session_info->mut_auth_requested) { + result = libspdm_hash_update ( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + mut_cert_chain_buffer_hash, hash_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + spdm_session_info->session_transcript.digest_context_th = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + } + result = libspdm_hash_update (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th, + message, + message_size); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_th); + spdm_session_info->session_transcript.digest_context_th = NULL; + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + spdm_session_info->session_transcript.message_f_initialized = true; + return LIBSPDM_STATUS_SUCCESS; + } +#endif +} + +/** + * This function returns if a given version is supported based upon the GET_VERSION/VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * @param version The SPDM version. + * + * @retval true the version is supported. + * @retval false the version is not supported. + **/ +bool libspdm_is_version_supported(const libspdm_context_t *spdm_context, uint8_t version) +{ + if (version == (spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT)) { + return true; + } + + return false; +} + +/** + * This function returns connection version negotiated by GET_VERSION/VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * + * @return the connection version. + **/ +uint8_t libspdm_get_connection_version(const libspdm_context_t *spdm_context) +{ + return (uint8_t)(spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT); +} + +/** + * This function returns if a capablities flag is supported in current SPDM connection. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Is the function called from a requester. + * @param requester_capabilities_flag The requester capabilities flag to be checked + * @param responder_capabilities_flag The responder capabilities flag to be checked + * + * @retval true the capablities flag is supported. + * @retval false the capablities flag is not supported. + **/ +bool libspdm_is_capabilities_flag_supported(const libspdm_context_t *spdm_context, + bool is_requester, + uint32_t requester_capabilities_flag, + uint32_t responder_capabilities_flag) +{ + uint32_t negotiated_requester_capabilities_flag; + uint32_t negotiated_responder_capabilities_flag; + + if (is_requester) { + negotiated_requester_capabilities_flag = spdm_context->local_context.capability.flags; + negotiated_responder_capabilities_flag = spdm_context->connection_info.capability.flags; + } else { + negotiated_requester_capabilities_flag = spdm_context->connection_info.capability.flags; + negotiated_responder_capabilities_flag = spdm_context->local_context.capability.flags; + } + + if (((requester_capabilities_flag == 0) || + ((negotiated_requester_capabilities_flag & + requester_capabilities_flag) != 0)) && + ((responder_capabilities_flag == 0) || + ((negotiated_responder_capabilities_flag & + responder_capabilities_flag) != 0))) { + return true; + } else { + return false; + } +} + +/** + * Register SPDM device input/output functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param send_message The fuction to send an SPDM transport layer message. + * @param receive_message The fuction to receive an SPDM transport layer message. + **/ +void libspdm_register_device_io_func( + void *context, libspdm_device_send_message_func send_message, + libspdm_device_receive_message_func receive_message) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + spdm_context->send_message = send_message; + spdm_context->receive_message = receive_message; +} + +/** + * Register SPDM device buffer management functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param acquire_sender_buffer The fuction to acquire transport layer sender buffer. + * @param release_sender_buffer The fuction to release transport layer sender buffer. + * @param acquire_receiver_buffer The fuction to acquire transport layer receiver buffer. + * @param release_receiver_buffer The fuction to release transport layer receiver buffer. + **/ +void libspdm_register_device_buffer_func( + void *context, + libspdm_device_acquire_sender_buffer_func acquire_sender_buffer, + libspdm_device_release_sender_buffer_func release_sender_buffer, + libspdm_device_acquire_receiver_buffer_func acquire_receiver_buffer, + libspdm_device_release_receiver_buffer_func release_receiver_buffer) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + spdm_context->acquire_sender_buffer = acquire_sender_buffer; + spdm_context->release_sender_buffer = release_sender_buffer; + spdm_context->acquire_receiver_buffer = acquire_receiver_buffer; + spdm_context->release_receiver_buffer = release_receiver_buffer; +} + +/** + * Register SPDM transport layer encode/decode functions for SPDM or APP messages. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param spdm_context A pointer to the SPDM context. + * @param transport_encode_message The fuction to encode an SPDM or APP message to a transport layer message. + * @param transport_decode_message The fuction to decode an SPDM or APP message from a transport layer message. + * @param transport_get_header_size The fuction to get the maximum transport layer message header size. + **/ +void libspdm_register_transport_layer_func( + void *context, + libspdm_transport_encode_message_func transport_encode_message, + libspdm_transport_decode_message_func transport_decode_message, + libspdm_transport_get_header_size_func transport_get_header_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + spdm_context->transport_encode_message = transport_encode_message; + spdm_context->transport_decode_message = transport_decode_message; + spdm_context->transport_get_header_size = transport_get_header_size; +} + +/** + * Register SPDM certificate verification functions for SPDM GET_CERTIFICATE in requester or responder. + * It is called after GET_CERTIFICATE gets a full certificate chain from peer. + * + * If it is NOT registered, the default verification in SPDM lib will be used. It verifies: + * 1) The integrity of the certificate chain, (Root Cert Hash->Root Cert->Cert Chain), according to X.509. + * 2) The trust anchor, according LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT or LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN. + * If it is registered, SPDM lib will use this function to verify the certificate. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param context A pointer to the SPDM context. + * @param verify_spdm_cert_chain The fuction to verify an SPDM certificate after GET_CERTIFICATE. + **/ +void libspdm_register_verify_spdm_cert_chain_func( + void *context, + const libspdm_verify_spdm_cert_chain_func verify_spdm_cert_chain) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + spdm_context->local_context.verify_peer_spdm_cert_chain = verify_spdm_cert_chain; +} + +/** + * Get the size of required scratch buffer. + * + * The SPDM Integrator must call libspdm_get_sizeof_required_scratch_buffer to get the size, + * then allocate enough scratch buffer and call libspdm_set_scratch_buffer(). + * + * @param context A pointer to the SPDM context. + * + * @return the size of required scratch buffer. + **/ +size_t libspdm_get_sizeof_required_scratch_buffer ( + void *context) +{ + return LIBSPDM_SCRATCH_BUFFER_SIZE; +} + +/** + * Set the scratch buffer. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * @param context A pointer to the SPDM context. + * @param scratch_buffer Buffer address of the scratch buffer. + * @param scratch_buffer_size Size of the scratch buffer. + * + **/ +void libspdm_set_scratch_buffer ( + void *context, + void *scratch_buffer, + size_t scratch_buffer_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + LIBSPDM_ASSERT (scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); + spdm_context->scratch_buffer = scratch_buffer; + spdm_context->scratch_buffer_size = scratch_buffer_size; +} + +/** + * Get the scratch buffer. + * + * @param context A pointer to the SPDM context. + * @param scratch_buffer Buffer address of the scratch buffer. + * @param scratch_buffer_size Size of the scratch buffer. + * + **/ +void libspdm_get_scratch_buffer ( + void *context, + void **scratch_buffer, + size_t *scratch_buffer_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + LIBSPDM_ASSERT (spdm_context->scratch_buffer != NULL); + LIBSPDM_ASSERT (spdm_context->scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); + *scratch_buffer = spdm_context->scratch_buffer; + *scratch_buffer_size = spdm_context->scratch_buffer_size; +} + +/** + * Acquire a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param max_msg_size size in bytes of the maximum size of sender buffer. + * @param msg_buf_ptr A pointer to a sender buffer. + * + * @retval RETURN_SUCCESS The sender buffer is acquired. + **/ +libspdm_return_t libspdm_acquire_sender_buffer ( + libspdm_context_t *spdm_context, size_t *max_msg_size, void **msg_buf_ptr) +{ + libspdm_return_t status; + + LIBSPDM_ASSERT (spdm_context->sender_buffer == NULL); + LIBSPDM_ASSERT (spdm_context->sender_buffer_size == 0); + status = spdm_context->acquire_sender_buffer (spdm_context, max_msg_size, msg_buf_ptr); + if (status != LIBSPDM_STATUS_SUCCESS) { + return status; + } + spdm_context->sender_buffer = *msg_buf_ptr; + spdm_context->sender_buffer_size = *max_msg_size; + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* it return scratch buffer, because the requester need build message there.*/ + *msg_buf_ptr = spdm_context->scratch_buffer + + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; + *max_msg_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + #endif + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Release a device sender buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The sender buffer is Released. + **/ +void libspdm_release_sender_buffer (libspdm_context_t *spdm_context) +{ + LIBSPDM_ASSERT(spdm_context->sender_buffer != NULL); + LIBSPDM_ASSERT(spdm_context->sender_buffer_size != 0); + + spdm_context->release_sender_buffer (spdm_context, spdm_context->sender_buffer); + spdm_context->sender_buffer = NULL; + spdm_context->sender_buffer_size = 0; +} + +/** + * Get the sender buffer. + * + * @param context A pointer to the SPDM context. + * @param receiver_buffer Buffer address of the sender buffer. + * @param receiver_buffer_size Size of the sender buffer. + * + **/ +void libspdm_get_sender_buffer ( + libspdm_context_t *spdm_context, + void **sender_buffer, + size_t *sender_buffer_size) +{ + *sender_buffer = spdm_context->sender_buffer; + *sender_buffer_size = spdm_context->sender_buffer_size; +} + +/** + * Acquire a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param max_msg_size size in bytes of the maximum size of receiver buffer. + * @param msg_buf_pt A pointer to a receiver buffer. + * + * @retval RETURN_SUCCESS The receiver buffer is acquired. + **/ +libspdm_return_t libspdm_acquire_receiver_buffer ( + libspdm_context_t *spdm_context, size_t *max_msg_size, void **msg_buf_ptr) +{ + libspdm_return_t status; + + LIBSPDM_ASSERT (spdm_context->receiver_buffer == NULL); + LIBSPDM_ASSERT (spdm_context->receiver_buffer_size == 0); + status = spdm_context->acquire_receiver_buffer (spdm_context, max_msg_size, msg_buf_ptr); + if (status != LIBSPDM_STATUS_SUCCESS) { + return status; + } + spdm_context->receiver_buffer = *msg_buf_ptr; + spdm_context->receiver_buffer_size = *max_msg_size; + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* it return scratch buffer, because the requester need build message there.*/ + *msg_buf_ptr = spdm_context->scratch_buffer + + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; + *max_msg_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + #endif + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Release a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS The receiver buffer is Released. + **/ +void libspdm_release_receiver_buffer (libspdm_context_t *spdm_context) +{ + LIBSPDM_ASSERT(spdm_context->receiver_buffer != NULL); + LIBSPDM_ASSERT(spdm_context->receiver_buffer_size != 0); + + spdm_context->release_receiver_buffer (spdm_context, spdm_context->receiver_buffer); + spdm_context->receiver_buffer = NULL; + spdm_context->receiver_buffer_size = 0; +} + +/** + * Get the receiver buffer. + * + * @param context A pointer to the SPDM context. + * @param receiver_buffer Buffer address of the receiver buffer. + * @param receiver_buffer_size Size of the receiver buffer. + * + **/ +void libspdm_get_receiver_buffer ( + libspdm_context_t *spdm_context, + void **receiver_buffer, + size_t *receiver_buffer_size) +{ + *receiver_buffer = spdm_context->receiver_buffer; + *receiver_buffer_size = spdm_context->receiver_buffer_size; +} + +/** + * Get the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_get_last_spdm_error_struct(void *context, libspdm_error_struct_t *last_spdm_error) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + libspdm_copy_mem(last_spdm_error, sizeof(libspdm_error_struct_t), + &spdm_context->last_spdm_error,sizeof(libspdm_error_struct_t)); +} + +/** + * Set the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_set_last_spdm_error_struct(void *context, libspdm_error_struct_t *last_spdm_error) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + libspdm_copy_mem(&spdm_context->last_spdm_error, sizeof(spdm_context->last_spdm_error), + last_spdm_error, sizeof(libspdm_error_struct_t)); +} + +/** + * Initialize an SPDM context, as well as all secured message contexts, + * in the specified locations. + * + * The size in bytes of the spdm_context can be returned by + * libspdm_get_context_size_without_secured_context. + * + * The size in bytes of a single secured message context can be returned by + * libspdm_secured_message_get_context_size. + * + * @param spdm_context A pointer to the SPDM context. + * @param secured_contexts An array of pointers, with each entry containing + * the location of a secured message context. + * @param num_secured_contexts Number of secured message contexts to initialize. + * Currently, only LIBSPDM_MAX_SESSION_COUNT is supported. + * + * @retval RETURN_SUCCESS Contexts are initialized. + * @retval RETURN_DEVICE_ERROR Context initialization failed. + */ +libspdm_return_t libspdm_init_context_with_secured_context(void *context, + void **secured_contexts, + size_t num_secured_contexts) +{ + libspdm_context_t *spdm_context; + size_t index; + + LIBSPDM_ASSERT(context != NULL); + LIBSPDM_ASSERT(secured_contexts != NULL); + LIBSPDM_ASSERT(num_secured_contexts == LIBSPDM_MAX_SESSION_COUNT); + + spdm_context = context; + libspdm_zero_mem(spdm_context, sizeof(libspdm_context_t)); + spdm_context->version = libspdm_context_struct_version; + spdm_context->transcript.message_a.max_buffer_size = + sizeof(spdm_context->transcript.message_a.buffer); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + spdm_context->transcript.message_b.max_buffer_size = + sizeof(spdm_context->transcript.message_b.buffer); + spdm_context->transcript.message_c.max_buffer_size = + sizeof(spdm_context->transcript.message_c.buffer); + spdm_context->transcript.message_mut_b.max_buffer_size = + sizeof(spdm_context->transcript.message_mut_b.buffer); + spdm_context->transcript.message_mut_c.max_buffer_size = + sizeof(spdm_context->transcript.message_mut_c.buffer); + spdm_context->transcript.message_m.max_buffer_size = + sizeof(spdm_context->transcript.message_m.buffer); +#endif + spdm_context->retry_times = LIBSPDM_MAX_REQUEST_RETRY_TIMES; + spdm_context->response_state = LIBSPDM_RESPONSE_STATE_NORMAL; + spdm_context->current_token = 0; + spdm_context->local_context.version.spdm_version_count = 3; + spdm_context->local_context.version.spdm_version[0] = SPDM_MESSAGE_VERSION_10 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.version.spdm_version[1] = SPDM_MESSAGE_VERSION_11 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.version.spdm_version[2] = SPDM_MESSAGE_VERSION_12 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.secured_message_version.spdm_version_count = 2; + spdm_context->local_context.secured_message_version.spdm_version[0] = + SPDM_MESSAGE_VERSION_10 << SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.secured_message_version.spdm_version[1] = + SPDM_MESSAGE_VERSION_11 << SPDM_VERSION_NUMBER_SHIFT_BIT; + spdm_context->local_context.capability.st1 = SPDM_ST1_VALUE_US; + + spdm_context->encap_context.certificate_chain_buffer.max_buffer_size = + sizeof(spdm_context->encap_context.certificate_chain_buffer.buffer); + + /* From the config.h, need different value for CHUNK - TBD*/ + spdm_context->local_context.capability.data_transfer_size = LIBSPDM_DATA_TRANSFER_SIZE; + spdm_context->local_context.capability.max_spdm_msg_size = LIBSPDM_MAX_SPDM_MSG_SIZE; + + for (index = 0; index < num_secured_contexts; index++) { + if (secured_contexts[index] == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + spdm_context->session_info[index].secured_message_context = secured_contexts[index]; + libspdm_secured_message_init_context( + spdm_context->session_info[index] + .secured_message_context); + } + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Initialize an SPDM context, as well as secured message contexts. + * The secured message contexts are appended to the context structure. + * + * The total size in bytes of the spdm_context and all secured message + * contexts can be returned by libspdm_get_context_size(). + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS context is initialized. + * @retval RETURN_DEVICE_ERROR context initialization failed. + */ +libspdm_return_t libspdm_init_context(void *context) +{ + libspdm_context_t *spdm_context; + void *secured_context; + void *secured_contexts[LIBSPDM_MAX_SESSION_COUNT]; + size_t secured_context_size; + size_t index; + + LIBSPDM_ASSERT(context != NULL); + + /* libspdm_get_context_size() allocates space for all secured message + * contexts. They are appended to the general SPDM context. */ + spdm_context = context; + secured_context = (void *)((size_t)(spdm_context + 1)); + secured_context_size = libspdm_secured_message_get_context_size(); + + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) + { + secured_contexts[index] = + (uint8_t *)secured_context + secured_context_size * index; + } + + return libspdm_init_context_with_secured_context(context, + secured_contexts, + LIBSPDM_MAX_SESSION_COUNT); +} + +/** + * Reset an SPDM context. + * + * The size in bytes of the spdm_context can be returned by libspdm_get_context_size. + * + * @param spdm_context A pointer to the SPDM context. + */ +void libspdm_reset_context(void *context) +{ + libspdm_context_t *spdm_context; + size_t index; + + spdm_context = context; + + /*Clear all info about last connection*/ + + /*need clear session info to free context before algo is zeroed.*/ + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) + { + libspdm_session_info_init(spdm_context, + &spdm_context->session_info[index], + INVALID_SESSION_ID, + false); + } + + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_NOT_STARTED; + libspdm_zero_mem(&spdm_context->connection_info.version, sizeof(spdm_version_number_t)); + libspdm_zero_mem(&spdm_context->connection_info.capability, + sizeof(libspdm_device_capability_t)); + libspdm_zero_mem(&spdm_context->connection_info.algorithm, sizeof(libspdm_device_algorithm_t)); + libspdm_zero_mem(&spdm_context->last_spdm_error, sizeof(libspdm_error_struct_t)); + libspdm_zero_mem(&spdm_context->encap_context, sizeof(libspdm_encap_context_t)); + spdm_context->connection_info.local_used_cert_chain_buffer_size = 0; + spdm_context->connection_info.local_used_cert_chain_buffer = NULL; + spdm_context->cache_spdm_request_size = 0; + spdm_context->retry_times = LIBSPDM_MAX_REQUEST_RETRY_TIMES; + spdm_context->response_state = LIBSPDM_RESPONSE_STATE_NORMAL; + spdm_context->current_token = 0; + spdm_context->last_spdm_request_session_id = INVALID_SESSION_ID; + spdm_context->last_spdm_request_session_id_valid = false; + spdm_context->last_spdm_request_size = 0; + spdm_context->encap_context.certificate_chain_buffer.max_buffer_size = + sizeof(spdm_context->encap_context.certificate_chain_buffer.buffer); + + #if LIBSPDM_ENABLE_MSG_LOG + spdm_context->msg_log.buffer = NULL; + spdm_context->msg_log.max_buffer_size = 0; + spdm_context->msg_log.buffer_size = 0; + spdm_context->msg_log.mode = 0; + spdm_context->msg_log.status = 0; + #endif /* LIBSPDM_ENABLE_MSG_LOG */ +} + +/** + * Free the memory of contexts within the SPDM context. + * These are typically contexts whose memory has been allocated by the cryptography library. + * This function does not free the SPDM context itself. + * + * @param[in] spdm_context A pointer to the SPDM context. + * + */ +void libspdm_deinit_context(void *context) +{ +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + libspdm_context_t *spdm_context; + void *pubkey_context; + bool is_requester; + uint8_t slot_index; + + spdm_context = context; + is_requester = spdm_context->local_context.is_requester; + + for (slot_index = 0; slot_index < SPDM_MAX_SLOT_COUNT; slot_index++) { + pubkey_context = spdm_context->connection_info.peer_used_cert_chain[slot_index]. + leaf_cert_public_key; + + if (pubkey_context != NULL) { + if (is_requester) { + libspdm_asym_free( + spdm_context->connection_info.algorithm.base_asym_algo, pubkey_context); + } else { + libspdm_req_asym_free( + spdm_context->connection_info.algorithm.req_base_asym_alg, pubkey_context); + } + + pubkey_context = NULL; + spdm_context->connection_info.peer_used_cert_chain[slot_index]. + leaf_cert_public_key = NULL; + } + } + +#endif +} + +/** + * Return the size in bytes of the SPDM context. This includes all + * secured message context data as well. + * + * For just the SPDM context size, use libspdm_get_context_size_without_secured_context. + * + * @return the size in bytes of the SPDM context and secured message contexts. + **/ +size_t libspdm_get_context_size(void) +{ + size_t size; + + size = sizeof(libspdm_context_t) + + libspdm_secured_message_get_context_size() * LIBSPDM_MAX_SESSION_COUNT; + LIBSPDM_ASSERT (size == LIBSPDM_CONTEXT_SIZE_ALL); + return size; +} + +/** + * Return the size in bytes of just the SPDM context, without secured message context. + * + * For the complete context size, use libspdm_get_context_size. + * + * @return the size in bytes of the SPDM context. + **/ +size_t libspdm_get_context_size_without_secured_context(void) +{ + size_t size; + + size = sizeof(libspdm_context_t); + LIBSPDM_ASSERT (size == LIBSPDM_CONTEXT_SIZE_WITHOUT_SECURED_CONTEXT); + return size; +} + +/** + * Return the SPDMversion field of the version number struct. + * + * @param ver Spdm version number struct. + * + * @return the SPDMversion of the version number struct. + **/ +uint8_t libspdm_get_version_from_version_number(const spdm_version_number_t ver) +{ + return (uint8_t)(ver >> SPDM_VERSION_NUMBER_SHIFT_BIT); +} + +/** + * Sort SPDMversion in descending order. + * + * @param spdm_context A pointer to the SPDM context. + * @param ver_set A pointer to the version set. + * @param ver_num Version number. + */ +void libspdm_version_number_sort(spdm_version_number_t *ver_set, size_t ver_num) +{ + size_t index; + size_t index_sort; + size_t index_max; + spdm_version_number_t version; + + /* Select sort */ + if (ver_num > 1) { + for (index_sort = 0; index_sort < ver_num; index_sort++) { + index_max = index_sort; + for (index = index_sort + 1; index < ver_num; index++) { + /* if ver_ser[index] higher than ver_set[index_max] */ + if (ver_set[index] > ver_set[index_max]) { + index_max = index; + } + } + /* swap ver_ser[index_min] and ver_set[index_sort] */ + version = ver_set[index_sort]; + ver_set[index_sort] = ver_set[index_max]; + ver_set[index_max] = version; + } + } +} + +/** + * Negotiate SPDMversion for connection. + * ver_set is the local version set of requester, res_ver_set is the version set of responder. + * + * @param common_version A pointer to store the common version. + * @param req_ver_set A pointer to the requester version set. + * @param req_ver_num Version number of requester. + * @param res_ver_set A pointer to the responder version set. + * @param res_ver_num Version number of responder. + * + * @retval true Negotiation successfully, connect version be saved to common_version. + * @retval false Negotiation failed. + */ +bool libspdm_negotiate_connection_version(spdm_version_number_t *common_version, + spdm_version_number_t *req_ver_set, + size_t req_ver_num, + const spdm_version_number_t *res_ver_set, + size_t res_ver_num) +{ + spdm_version_number_t req_version_list[LIBSPDM_MAX_VERSION_COUNT]; + spdm_version_number_t res_version_list[LIBSPDM_MAX_VERSION_COUNT]; + size_t req_index; + size_t res_index; + + if (req_ver_num > LIBSPDM_MAX_VERSION_COUNT || res_ver_num > LIBSPDM_MAX_VERSION_COUNT) { + return false; + } + + if (req_ver_set == NULL || req_ver_num == 0 || res_ver_set == NULL || res_ver_num == 0) { + return false; + } + + libspdm_zero_mem(req_version_list, sizeof(spdm_version_number_t) * LIBSPDM_MAX_VERSION_COUNT); + libspdm_zero_mem(res_version_list, sizeof(spdm_version_number_t) * LIBSPDM_MAX_VERSION_COUNT); + + libspdm_copy_mem(req_version_list, sizeof(spdm_version_number_t) * LIBSPDM_MAX_VERSION_COUNT, + req_ver_set, sizeof(spdm_version_number_t) * req_ver_num); + libspdm_copy_mem(res_version_list, sizeof(spdm_version_number_t) * LIBSPDM_MAX_VERSION_COUNT, + res_ver_set, sizeof(spdm_version_number_t) * res_ver_num); + + /* Sort SPDMversion in descending order. */ + libspdm_version_number_sort(req_version_list, req_ver_num); + libspdm_version_number_sort(res_version_list, res_ver_num); + + /** + * Find highest same version and make req_index point to it. + * If not found, return false. + **/ + for (res_index = 0; res_index < res_ver_num; res_index++) { + for (req_index = 0; req_index < req_ver_num; req_index++) { + if (libspdm_get_version_from_version_number(req_version_list[req_index]) == + libspdm_get_version_from_version_number(res_version_list[res_index])) { + *common_version = req_version_list[req_index]; + return true; + } + } + } + return false; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c new file mode 100644 index 0000000000..78180423cd --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c @@ -0,0 +1,266 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +/** + * This function initializes the session info. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + **/ +void libspdm_session_info_init(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint32_t session_id, bool use_psk) +{ + libspdm_session_type_t session_type; + uint32_t capabilities_flag; + + capabilities_flag = spdm_context->connection_info.capability.flags & + spdm_context->local_context.capability.flags; + switch (capabilities_flag & + (SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP)) { + case 0: + session_type = LIBSPDM_SESSION_TYPE_NONE; + break; + case (SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP): + session_type = LIBSPDM_SESSION_TYPE_ENC_MAC; + break; + case SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP: + session_type = LIBSPDM_SESSION_TYPE_MAC_ONLY; + break; + default: + LIBSPDM_ASSERT(false); + session_type = LIBSPDM_SESSION_TYPE_MAX; + break; + } + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + if (session_info->session_transcript.digest_context_th != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th); + session_info->session_transcript.digest_context_th = NULL; + } + if (session_info->session_transcript.digest_context_th_backup != NULL) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th_backup); + session_info->session_transcript.digest_context_th_backup = NULL; + } +#endif + + libspdm_zero_mem (&(session_info->last_key_update_request), sizeof(spdm_key_update_request_t)); + libspdm_zero_mem(session_info, offsetof(libspdm_session_info_t, secured_message_context)); + libspdm_secured_message_init_context(session_info->secured_message_context); + session_info->session_id = session_id; + session_info->use_psk = use_psk; + libspdm_secured_message_set_use_psk(session_info->secured_message_context, use_psk); + libspdm_secured_message_set_session_type(session_info->secured_message_context, session_type); + libspdm_secured_message_set_algorithms( + session_info->secured_message_context, + spdm_context->connection_info.version, + spdm_context->connection_info.secured_message_version, + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.dhe_named_group, + spdm_context->connection_info.algorithm.aead_cipher_suite, + spdm_context->connection_info.algorithm.key_schedule); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + session_info->session_transcript.message_k.max_buffer_size = + sizeof(session_info->session_transcript.message_k.buffer); + session_info->session_transcript.message_f.max_buffer_size = + sizeof(session_info->session_transcript.message_f.buffer); + session_info->session_transcript.message_m.max_buffer_size = + sizeof(session_info->session_transcript.message_m.buffer); +#endif +} + +/** + * Set the psk_hint to a session info. + * + * @param session_info A pointer to a session info. + * @param psk_hint Indicate the PSK hint. + * @param psk_hint_size The size in bytes of the PSK hint. + */ +void libspdm_session_info_set_psk_hint(libspdm_session_info_t *session_info, + const void *psk_hint, + size_t psk_hint_size) +{ + libspdm_secured_message_set_psk_hint( + session_info->secured_message_context, + psk_hint, + psk_hint_size); +} + +/** + * This function gets the session info via session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return session info. + **/ +void *libspdm_get_session_info_via_session_id(void *context, uint32_t session_id) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + size_t index; + + if (session_id == INVALID_SESSION_ID) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_get_session_info_via_session_id - Invalid session_id\n")); + LIBSPDM_ASSERT(false); + return NULL; + } + + spdm_context = context; + + session_info = (libspdm_session_info_t *)spdm_context->session_info; + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if (session_info[index].session_id == session_id) { + return &session_info[index]; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_get_session_info_via_session_id - not found session_id\n")); + return NULL; +} + +/** + * This function gets the secured message context via session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return secured message context. + **/ +void *libspdm_get_secured_message_context_via_session_id(void *spdm_context, uint32_t session_id) +{ + libspdm_session_info_t *session_info; + + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + return NULL; + } else { + return session_info->secured_message_context; + } +} + +/** + * This function gets the secured message context via session ID. + * + * @param spdm_session_info A pointer to the SPDM context. + * + * @return secured message context. + **/ +void *libspdm_get_secured_message_context_via_session_info(void *spdm_session_info) +{ + libspdm_session_info_t *session_info; + + session_info = spdm_session_info; + if (session_info == NULL) { + return NULL; + } else { + return session_info->secured_message_context; + } +} + +/** + * This function generate a new session ID by concatnating req_session_id and rsp_session_id. + * + * @param[in] req_session_id + * @param[in] rsp_session_id + * + * @return this new session ID. + **/ +uint32_t libspdm_generate_session_id(uint16_t req_session_id, uint16_t rsp_session_id) +{ + uint32_t session_id; + session_id = (rsp_session_id << 16) | req_session_id; + return session_id; +} + +/** + * This function assigns a new session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + * + * @return session info associated with this new session ID. + **/ +void *libspdm_assign_session_id(void *context, uint32_t session_id, bool use_psk) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + size_t index; + + spdm_context = context; + + if (session_id == INVALID_SESSION_ID) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_assign_session_id - Invalid session_id\n")); + LIBSPDM_ASSERT(false); + return NULL; + } + + session_info = spdm_context->session_info; + + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if (session_info[index].session_id == session_id) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_assign_session_id - Duplicated session_id\n")); + LIBSPDM_ASSERT(false); + return NULL; + } + } + + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if (session_info[index].session_id == INVALID_SESSION_ID) { + libspdm_session_info_init(spdm_context, + &session_info[index], session_id, + use_psk); + spdm_context->latest_session_id = session_id; + return &session_info[index]; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_assign_session_id - MAX session_id\n")); + return NULL; +} + +/** + * This function frees a session ID. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The SPDM session ID. + **/ +void libspdm_free_session_id(void *context, uint32_t session_id) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + size_t index; + + spdm_context = context; + + if (session_id == INVALID_SESSION_ID) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_free_session_id - Invalid session_id\n")); + LIBSPDM_ASSERT(false); + return; + } + + session_info = spdm_context->session_info; + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if (session_info[index].session_id == session_id) { + libspdm_session_info_init(spdm_context, + &session_info[index], + INVALID_SESSION_ID, false); + return; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_free_session_id - MAX session_id\n")); + LIBSPDM_ASSERT(false); +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c new file mode 100644 index 0000000000..b3f86d6a63 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c @@ -0,0 +1,1147 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +/** + * This function returns peer certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * + * @retval true Peer certificate chain buffer including spdm_cert_chain_t header is returned. + * @retval false Peer certificate chain buffer including spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_peer_cert_chain_buffer(void *context, + const void **cert_chain_buffer, + size_t *cert_chain_buffer_size) +{ + libspdm_context_t *spdm_context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t slot_id; +#endif + + spdm_context = context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size != 0) { + *cert_chain_buffer = spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer; + *cert_chain_buffer_size = spdm_context->connection_info + .peer_used_cert_chain[slot_id].buffer_size; + return true; + } +#endif + if (spdm_context->local_context.peer_cert_chain_provision_size != 0) { + *cert_chain_buffer = spdm_context->local_context.peer_cert_chain_provision; + *cert_chain_buffer_size = spdm_context->local_context.peer_cert_chain_provision_size; + return true; + } + return false; +} + +/** + * This function returns peer certificate chain data without spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size size in bytes of the certitiface chain data. + * + * @retval true Peer certificate chain data without spdm_cert_chain_t header is returned. + * @retval false Peer certificate chain data without spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_peer_cert_chain_data(void *context, + const void **cert_chain_data, + size_t *cert_chain_data_size) +{ + libspdm_context_t *spdm_context; + bool result; + size_t hash_size; + + spdm_context = context; + + result = libspdm_get_peer_cert_chain_buffer(spdm_context, cert_chain_data, + cert_chain_data_size); + if (!result) { + return false; + } + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + *cert_chain_data = (const uint8_t *)*cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; + *cert_chain_data_size = *cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); + + return true; +} + +/** + * This function returns local used certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * + * @retval true Local used certificate chain buffer including spdm_cert_chain_t header is returned. + * @retval false Local used certificate chain buffer including spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_local_cert_chain_buffer(void *context, + const void **cert_chain_buffer, + size_t *cert_chain_buffer_size) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + if (spdm_context->connection_info.local_used_cert_chain_buffer_size != 0) { + *cert_chain_buffer = spdm_context->connection_info.local_used_cert_chain_buffer; + *cert_chain_buffer_size = spdm_context->connection_info.local_used_cert_chain_buffer_size; + return true; + } + return false; +} + +/** + * This function returns local used certificate chain data without spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size size in bytes of the certitiface chain data. + * + * @retval true Local used certificate chain data without spdm_cert_chain_t header is returned. + * @retval false Local used certificate chain data without spdm_cert_chain_t header is not found. + **/ +bool libspdm_get_local_cert_chain_data(void *context, + const void **cert_chain_data, + size_t *cert_chain_data_size) +{ + libspdm_context_t *spdm_context; + bool result; + size_t hash_size; + + spdm_context = context; + + result = libspdm_get_local_cert_chain_buffer(spdm_context, cert_chain_data, + cert_chain_data_size); + if (!result) { + return false; + } + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + *cert_chain_data = (const uint8_t *)*cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; + *cert_chain_data_size = *cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); + return true; +} + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates l1l2. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param l1l2 The buffer to store the l1l2. + * + * @retval RETURN_SUCCESS l1l2 is calculated. + */ +bool libspdm_calculate_l1l2(void *context, void *session_info, + libspdm_large_managed_buffer_t *l1l2) +{ + libspdm_context_t *spdm_context; + libspdm_return_t status; + libspdm_session_info_t *spdm_session_info; + + spdm_context = context; + spdm_session_info = session_info; + + libspdm_init_managed_buffer(l1l2, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + + /* Need append VCA since 1.2 script*/ + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + l1l2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + if (spdm_session_info == NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_m data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_m), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_m)); + status = libspdm_append_managed_buffer( + l1l2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_m), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_m)); + } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "use message_m in session :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_session_info->session_transcript.message_m), + libspdm_get_managed_buffer_size(&spdm_session_info->session_transcript.message_m)); + status = libspdm_append_managed_buffer( + l1l2, + libspdm_get_managed_buffer(&spdm_session_info->session_transcript.message_m), + libspdm_get_managed_buffer_size(&spdm_session_info->session_transcript.message_m)); + } + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + /* Debug code only - calculate and print value of l1l2 hash*/ + LIBSPDM_DEBUG_CODE( + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + libspdm_get_managed_buffer(l1l2), + libspdm_get_managed_buffer_size(l1l2), hash_data)) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "l1l2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ); + + return true; +} +#else +/* + * This function calculates l1l2 hash. + * If session_info is NULL, this function will use M cache of SPDM context, + * else will use M cache of SPDM session context. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info A pointer to the SPDM session context. + * @param l1l2_hash_size size in bytes of the l1l2 hash + * @param l1l2_hash The buffer to store the l1l2 hash + * + * @retval RETURN_SUCCESS l1l2 is calculated. + */ +bool libspdm_calculate_l1l2_hash(void *context, void *session_info, + size_t *l1l2_hash_size, void *l1l2_hash) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *spdm_session_info; + bool result; + + uint32_t hash_size; + + spdm_context = context; + spdm_session_info = session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + if (spdm_session_info == NULL) { + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_l1l2, l1l2_hash); + } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "use message_m in session :\n")); + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_session_info->session_transcript.digest_context_l1l2, + l1l2_hash); + } + if (!result) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "l1l2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(l1l2_hash, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + *l1l2_hash_size = hash_size; + + return true; +} +#endif /* LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT */ + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates m1m2. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_mut Indicate if this is from mutual authentication. + * @param m1m2 The buffer to store the m1m2 + * + * @retval RETURN_SUCCESS m1m2 is calculated. + */ +static bool libspdm_calculate_m1m2(void *context, bool is_mut, + libspdm_large_managed_buffer_t *m1m2) +{ + libspdm_context_t *spdm_context; + libspdm_return_t status; + + spdm_context = context; + + libspdm_init_managed_buffer(m1m2, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + if (is_mut) { + if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > + SPDM_MESSAGE_VERSION_11) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_mut_b data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_mut_b), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_mut_b)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_mut_b), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_mut_b)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_mut_c data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_mut_c), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_mut_c)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_mut_c), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_mut_c)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + /* Debug code only - calculate and print value of m1m2 mut hash*/ + LIBSPDM_DEBUG_CODE( + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + libspdm_get_managed_buffer(m1m2), + libspdm_get_managed_buffer_size(m1m2), hash_data)) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "m1m2 Mut hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ); + + } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_b data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_b), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_b)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_b), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_b)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_c data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_c), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_c)); + status = libspdm_append_managed_buffer( + m1m2, + libspdm_get_managed_buffer(&spdm_context->transcript.message_c), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_c)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + /* Debug code only - calculate and print value of m1m2 hash*/ + LIBSPDM_DEBUG_CODE( + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + libspdm_get_managed_buffer(m1m2), + libspdm_get_managed_buffer_size(m1m2), hash_data)) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "m1m2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ); + } + + return true; +} +#else +/* + * This function calculates m1m2 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_mut Indicate if this is from mutual authentication. + * @param m1m2_hash_size size in bytes of the m1m2 hash + * @param m1m2_hash The buffer to store the m1m2 hash + * + * @retval RETURN_SUCCESS m1m2 is calculated. + */ +static bool libspdm_calculate_m1m2_hash(void *context, bool is_mut, + size_t *m1m2_hash_size, + void *m1m2_hash) +{ + libspdm_context_t *spdm_context; + uint32_t hash_size; + bool result; + + spdm_context = context; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + if (is_mut) { + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_mut_m1m2, m1m2_hash); + if (!result) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "m1m2 Mut hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(m1m2_hash, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + } else { + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->transcript.digest_context_m1m2, m1m2_hash); + if (!result) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "m1m2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(m1m2_hash, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + *m1m2_hash_size = hash_size; + + return true; +} +#endif + +/** + * This function generates the certificate chain hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The slot index of the certificate chain. + * @param signature The buffer to store the certificate chain hash. + * + * @retval true certificate chain hash is generated. + * @retval false certificate chain hash is not generated. + **/ +bool libspdm_generate_cert_chain_hash(libspdm_context_t *spdm_context, + size_t slot_id, uint8_t *hash) +{ + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + return libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->local_context.local_cert_chain_provision[slot_id], + spdm_context->local_context.local_cert_chain_provision_size[slot_id], hash); +} + +/** + * Get the certificate slot mask + * + * @param[in] context A pointer to the SPDM context. + * + * @retval slot_mask get slot mask + **/ +uint8_t libspdm_get_cert_slot_mask(libspdm_context_t *spdm_context) +{ + size_t index; + uint8_t slot_mask; + + slot_mask = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (spdm_context->local_context.local_cert_chain_provision[index] != NULL) { + slot_mask |= (1 << index); + } + } + + return slot_mask; +} + +/** + * Get the certificate slot count + * + * @param[in] context A pointer to the SPDM context. + * + * @retval slot_count get slot count + **/ +uint8_t libspdm_get_cert_slot_count(libspdm_context_t *spdm_context) +{ + size_t index; + uint8_t slot_count; + + slot_count = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (spdm_context->local_context.local_cert_chain_provision[index] != NULL) { + slot_count++; + } + } + + return slot_count; +} + +/** + * This function verifies the digest. + * + * @param spdm_context A pointer to the SPDM context. + * @param digest The digest data buffer. + * @param digest_count size of the digest data buffer. + * + * @retval true digest verification pass. + * @retval false digest verification fail. + **/ +bool libspdm_verify_peer_digests(libspdm_context_t *spdm_context, const void *digest, + size_t digest_count) +{ + size_t hash_size; + const uint8_t *hash_buffer; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + const uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + size_t index; + bool result; + + cert_chain_buffer = spdm_context->local_context.peer_cert_chain_provision; + cert_chain_buffer_size = spdm_context->local_context.peer_cert_chain_provision_size; + if ((cert_chain_buffer != NULL) && (cert_chain_buffer_size != 0)) { + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + hash_buffer = digest; + + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_digests - FAIL (hash calculation) !!!\n")); + return false; + } + + for (index = 0; index < digest_count; index++) + { + if (libspdm_const_compare_mem(hash_buffer, cert_chain_buffer_hash, hash_size) == 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - PASS !!!\n")); + return true; + } + hash_buffer += hash_size; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - FAIL !!!\n")); + return false; + } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - PASS !!!\n")); + } + return true; +} + +/** + * This function verifies peer certificate chain buffer including spdm_cert_chain_t header. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * @param is_requester Indicates if it is a requester message. + * + * @retval true Peer certificate chain buffer verification passed. + * @retval false Peer certificate chain buffer verification failed. + **/ +bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + const void **trust_anchor, + size_t *trust_anchor_size, + bool is_requester) +{ + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; + const uint8_t *root_cert; + size_t root_cert_size; + uint8_t root_cert_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t root_cert_hash_size; + const uint8_t *received_root_cert; + size_t received_root_cert_size; + bool result; + uint8_t root_cert_index; + bool is_device_cert_model; + + if((spdm_context->connection_info.capability.flags & + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ALIAS_CERT_CAP) == 0) { + is_device_cert_model = true; + } else { + is_device_cert_model = false; + } + + if (is_requester) { + result = libspdm_verify_certificate_chain_buffer( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.base_asym_algo, + cert_chain_buffer, cert_chain_buffer_size, is_device_cert_model); + } else { + result = libspdm_verify_certificate_chain_buffer( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.req_base_asym_alg, + cert_chain_buffer, cert_chain_buffer_size, is_device_cert_model); + } + if (!result) { + return false; + } + + root_cert_index = 0; + root_cert = spdm_context->local_context.peer_root_cert_provision[root_cert_index]; + root_cert_size = spdm_context->local_context.peer_root_cert_provision_size[root_cert_index]; + cert_chain_data = spdm_context->local_context.peer_cert_chain_provision; + cert_chain_data_size = spdm_context->local_context.peer_cert_chain_provision_size; + + root_cert_hash_size = libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + + if ((root_cert != NULL) && (root_cert_size != 0)) { + while ((root_cert != NULL) && (root_cert_size != 0)) { + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + root_cert, root_cert_size, root_cert_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - FAIL (hash calculation) !!!\n")); + return false; + } + + if (libspdm_const_compare_mem((const uint8_t *)cert_chain_buffer + + sizeof(spdm_cert_chain_t), + root_cert_hash, root_cert_hash_size) == 0) { + break; + } + + #if (LIBSPDM_MAX_ROOT_CERT_SUPPORT) > 1 + if ((root_cert_index < ((LIBSPDM_MAX_ROOT_CERT_SUPPORT) -1)) && + (spdm_context->local_context.peer_root_cert_provision[root_cert_index + 1] != + NULL)) { + root_cert_index++; + root_cert = spdm_context->local_context.peer_root_cert_provision[root_cert_index]; + root_cert_size = + spdm_context->local_context.peer_root_cert_provision_size[root_cert_index]; + } else + #endif /* LIBSPDM_MAX_ROOT_CERT_SUPPORT */ + { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - " + "FAIL (all root cert hash mismatch) !!!\n")); + return false; + } + } + + result = libspdm_x509_get_cert_from_cert_chain( + (const uint8_t *)cert_chain_buffer + sizeof(spdm_cert_chain_t) + root_cert_hash_size, + cert_chain_buffer_size - sizeof(spdm_cert_chain_t) - root_cert_hash_size, + 0, &received_root_cert, &received_root_cert_size); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - FAIL (cert retrieval fail) !!!\n")); + return false; + } + if (libspdm_is_root_certificate(received_root_cert, received_root_cert_size)) { + if ((root_cert != NULL) && + (libspdm_const_compare_mem(received_root_cert, root_cert, root_cert_size) != 0)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - " + "FAIL (root cert mismatch) !!!\n")); + return false; + } + } else { + if (!libspdm_x509_verify_cert(received_root_cert, received_root_cert_size, + root_cert, root_cert_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_peer_cert_chain_buffer - " + "FAIL (received root cert verify failed)!!!\n")); + return false; + } + } + if (trust_anchor != NULL) { + *trust_anchor = root_cert; + } + if (trust_anchor_size != NULL) { + *trust_anchor_size = root_cert_size; + } + } else if ((cert_chain_data != NULL) && (cert_chain_data_size != 0)) { + /* Whether it contains the root certificate or not, + * it should be equal to the one provisioned in trusted environment*/ + if (cert_chain_data_size != cert_chain_buffer_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - FAIL !!!\n")); + return false; + } + if (libspdm_const_compare_mem(cert_chain_buffer, cert_chain_data, + cert_chain_buffer_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - FAIL !!!\n")); + return false; + } + if (trust_anchor != NULL) { + *trust_anchor = cert_chain_data + sizeof(spdm_cert_chain_t) + + libspdm_get_hash_size( + spdm_context->connection_info.algorithm.base_hash_algo); + } + if (trust_anchor_size != NULL) { + *trust_anchor_size = cert_chain_data_size; + } + } + /* + * When there is no root_cert and cert_chain_data in local_context, the return is true too. + * No provision means the caller wants to verify the trust anchor of the cert chain. + */ + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - PASS !!!\n")); + + return true; +} + +/** + * This function generates the challenge signature based upon m1m2 for authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Indicate of the signature generation for a requester or a responder. + * @param signature The buffer to store the challenge signature. + * + * @retval true challenge signature is generated. + * @retval false challenge signature is not generated. + **/ +bool libspdm_generate_challenge_auth_signature(libspdm_context_t *spdm_context, + bool is_requester, + uint8_t *signature) +{ + bool result; + size_t signature_size; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t m1m2; + uint8_t *m1m2_buffer; + size_t m1m2_buffer_size; +#else + uint8_t m1m2_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t m1m2_hash_size; +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_calculate_m1m2(spdm_context, is_requester, &m1m2); + m1m2_buffer = libspdm_get_managed_buffer(&m1m2); + m1m2_buffer_size = libspdm_get_managed_buffer_size(&m1m2); +#else + m1m2_hash_size = sizeof(m1m2_hash); + result = libspdm_calculate_m1m2_hash(spdm_context, is_requester, &m1m2_hash_size, &m1m2_hash); +#endif + if (is_requester) { + libspdm_reset_message_mut_b(spdm_context); + libspdm_reset_message_mut_c(spdm_context); + } else { + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + } + if (!result) { + return false; + } + + if (is_requester) { +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + signature_size = libspdm_get_req_asym_signature_size( + spdm_context->connection_info.algorithm.req_base_asym_alg); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_requester_data_sign( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + false, m1m2_buffer, m1m2_buffer_size, signature, &signature_size); +#else + result = libspdm_requester_data_sign( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + true, m1m2_hash, m1m2_hash_size, signature, &signature_size); +#endif +#else /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + result = false; +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + } else { + signature_size = libspdm_get_asym_signature_size( + spdm_context->connection_info.algorithm.base_asym_algo); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_responder_data_sign( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + false, m1m2_buffer, m1m2_buffer_size, signature, + &signature_size); +#else + result = libspdm_responder_data_sign( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + true, m1m2_hash, m1m2_hash_size, signature, + &signature_size); +#endif + } + + return result; +} + +/** + * This function verifies the certificate chain hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param certificate_chain_hash The certificate chain hash data buffer. + * @param certificate_chain_hash_size size in bytes of the certificate chain hash data buffer. + * + * @retval true hash verification pass. + * @retval false hash verification fail. + **/ +bool libspdm_verify_certificate_chain_hash(libspdm_context_t *spdm_context, + const void *certificate_chain_hash, + size_t certificate_chain_hash_size) +{ + size_t hash_size; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + const uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + bool result; +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + uint8_t slot_id; +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer(spdm_context, + (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + if (!result) { + return false; + } + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_certificate_chain_hash - FAIL (hash calculation) !!!\n")); + return false; + } + + if (hash_size != certificate_chain_hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + if (libspdm_const_compare_mem(certificate_chain_hash, cert_chain_buffer_hash, + certificate_chain_hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } +#else + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size != 0) { + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size != + certificate_chain_hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + + if (libspdm_const_compare_mem(certificate_chain_hash, + spdm_context->connection_info.peer_used_cert_chain[slot_id]. + buffer_hash, certificate_chain_hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + + } else { + result = libspdm_get_peer_cert_chain_buffer(spdm_context, + (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + if (!result) { + return false; + } + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_certificate_chain_hash - FAIL (hash calculation) !!!\n")); + return false; + } + + if (hash_size != certificate_chain_hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + if (libspdm_const_compare_mem(certificate_chain_hash, cert_chain_buffer_hash, + certificate_chain_hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - PASS !!!\n")); + return true; +} + +/** + * This function verifies the challenge signature based upon m1m2. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Indicate of the signature verification for a requester or a responder. + * @param sign_data The signature data buffer. + * @param sign_data_size size in bytes of the signature data buffer. + * + * @retval true signature verification pass. + * @retval false signature verification fail. + **/ +bool libspdm_verify_challenge_auth_signature(libspdm_context_t *spdm_context, + bool is_requester, + const void *sign_data, + size_t sign_data_size) +{ + bool result; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + void *context; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t m1m2; + uint8_t *m1m2_buffer; + size_t m1m2_buffer_size; +#else + uint8_t m1m2_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t m1m2_hash_size; + uint8_t slot_id; +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_calculate_m1m2(spdm_context, !is_requester, &m1m2); +#else + m1m2_hash_size = sizeof(m1m2_hash); + result = libspdm_calculate_m1m2_hash(spdm_context, !is_requester, &m1m2_hash_size, &m1m2_hash); +#endif + if (is_requester) { + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + } else { + libspdm_reset_message_mut_b(spdm_context); + libspdm_reset_message_mut_c(spdm_context); + } + if (!result) { + return false; + } + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + + /* Get leaf cert from cert chain*/ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + m1m2_buffer = libspdm_get_managed_buffer(&m1m2); + m1m2_buffer_size = libspdm_get_managed_buffer_size(&m1m2); + + if (is_requester) { + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_buffer, m1m2_buffer_size, sign_data, sign_data_size); + libspdm_asym_free( + spdm_context->connection_info.algorithm.base_asym_algo, context); + } else { + result = libspdm_req_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.req_base_asym_alg, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_req_asym_verify( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_buffer, m1m2_buffer_size, sign_data, sign_data_size); + libspdm_req_asym_free(spdm_context->connection_info.algorithm.req_base_asym_alg, context); + } +#else + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (is_requester) { + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != + NULL) { + context = + spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_challenge_signature - FAIL !!!\n")); + return false; + } + return true; + } + + } else { + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != + NULL) { + context = + spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; + result = libspdm_req_asym_verify_hash( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_challenge_signature - FAIL !!!\n")); + return false; + } + return true; + } + } + + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + + + /* Get leaf cert from cert chain*/ + + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + if (is_requester) { + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_hash, m1m2_hash_size, sign_data, + sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); + } else { + result = libspdm_req_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.req_base_asym_alg, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_req_asym_verify_hash( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); + libspdm_req_asym_free(spdm_context->connection_info.algorithm.req_base_asym_alg, context); + } +#endif + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! verify_challenge_signature - FAIL !!!\n")); + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_challenge_signature - PASS !!!\n")); + + return true; +} + +/** + * This function calculate the measurement summary hash size. + * + * @param spdm_context A pointer to the SPDM context. + * @param is_requester Is the function called from a requester. + * @param measurement_summary_hash_type The type of the measurement summary hash. + * + * @return 0 measurement summary hash type is invalid, NO_MEAS hash type or no MEAS capabilities. + * @return measurement summary hash size according to type. + **/ +uint32_t +libspdm_get_measurement_summary_hash_size(libspdm_context_t *spdm_context, + bool is_requester, + uint8_t measurement_summary_hash_type) +{ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, is_requester, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP)) { + return 0; + } + + switch (measurement_summary_hash_type) { + case SPDM_CHALLENGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH: + return 0; + break; + + case SPDM_CHALLENGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH: + case SPDM_CHALLENGE_REQUEST_ALL_MEASUREMENTS_HASH: + return libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + break; + default: + return 0; + break; + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c new file mode 100644 index 0000000000..3d3fceaaf8 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c @@ -0,0 +1,686 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates current TH data with message A and message K. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param th_data_buffer_size size in bytes of the th_data_buffer + * @param th_data_buffer The buffer to store the th_data_buffer + * + * @retval RETURN_SUCCESS current TH data is calculated. + */ +bool libspdm_calculate_th_for_exchange( + void *context, void *spdm_session_info, const uint8_t *cert_chain_buffer, + size_t cert_chain_buffer_size, + size_t *th_data_buffer_size, void *th_data_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size; + libspdm_return_t status; + libspdm_large_managed_buffer_t th_curr; + bool result; + size_t th_data_buffer_capacity; + + spdm_context = context; + session_info = spdm_session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_data_buffer_size >= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + libspdm_init_managed_buffer(&th_curr, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + if (cert_chain_buffer != NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_message_ct data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX(cert_chain_buffer, cert_chain_buffer_size); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + return false; + } + status = libspdm_append_managed_buffer(&th_curr, cert_chain_buffer_hash, hash_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_k data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&session_info->session_transcript.message_k), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&session_info->session_transcript.message_k), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + th_data_buffer_capacity = *th_data_buffer_size; + *th_data_buffer_size = libspdm_get_managed_buffer_size(&th_curr); + libspdm_copy_mem(th_data_buffer, th_data_buffer_capacity, + libspdm_get_managed_buffer(&th_curr), *th_data_buffer_size); + + return true; +} +#else +/* + * This function calculates current TH hash with message A and message K. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hash_buffer_size size in bytes of the th_hash_buffer + * @param th_hash_buffer The buffer to store the th_hash_buffer + * + * @retval RETURN_SUCCESS current TH hash is calculated. + */ +bool libspdm_calculate_th_hash_for_exchange( + void *context, void *spdm_session_info, + size_t *th_hash_buffer_size, void *th_hash_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + uint32_t hash_size; + void *digest_context_th; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hash_buffer_size >= hash_size); + + /* duplicate the th context, because we still need use original context to continue.*/ + digest_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (digest_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + digest_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + digest_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + digest_context_th, th_hash_buffer); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, digest_context_th); + if (!result) { + return false; + } + + *th_hash_buffer_size = hash_size; + + return true; +} + +/* + * This function calculates current TH hmac with message A and message K, with response finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_exchange_rsp( + void *context, void *spdm_session_info, bool is_requester, + size_t *th_hmac_buffer_size, void *th_hmac_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + void *secured_message_context; + uint32_t hash_size; + void *hash_context_th; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + secured_message_context = session_info->secured_message_context; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hmac_buffer_size >= hash_size); + + /* duplicate the th context, because we still need use original context to continue.*/ + hash_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (hash_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + hash_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + hash_context_th, hash_data); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_response_finished_key (secured_message_context, + hash_data, hash_size, th_hmac_buffer); + if (!result) { + return false; + } + *th_hmac_buffer_size = hash_size; + + return true; +} +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT +/* + * This function calculates current TH data with message A, message K and message F. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param mut_cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header in mutual authentication. + * @param mut_cert_chain_buffer_size size in bytes of the certitiface chain buffer in mutual authentication. + * @param th_data_buffer_size size in bytes of the th_data_buffer + * @param th_data_buffer The buffer to store the th_data_buffer + * + * @retval RETURN_SUCCESS current TH data is calculated. + */ +bool libspdm_calculate_th_for_finish(void *context, + void *spdm_session_info, + const uint8_t *cert_chain_buffer, + size_t cert_chain_buffer_size, + const uint8_t *mut_cert_chain_buffer, + size_t mut_cert_chain_buffer_size, + size_t *th_data_buffer_size, + void *th_data_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint8_t mut_cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + uint32_t hash_size; + libspdm_return_t status; + libspdm_large_managed_buffer_t th_curr; + bool result; + size_t th_data_buffer_capacity; + + spdm_context = context; + session_info = spdm_session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_data_buffer_size >= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + libspdm_init_managed_buffer(&th_curr, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&spdm_context->transcript.message_a), + libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + if (cert_chain_buffer != NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_message_ct data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX(cert_chain_buffer, cert_chain_buffer_size); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + cert_chain_buffer, cert_chain_buffer_size, + cert_chain_buffer_hash); + if (!result) { + return false; + } + status = libspdm_append_managed_buffer(&th_curr, cert_chain_buffer_hash, hash_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_k data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&session_info->session_transcript.message_k), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&session_info->session_transcript.message_k), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + if (mut_cert_chain_buffer != NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_message_cm data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX(mut_cert_chain_buffer, mut_cert_chain_buffer_size); + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + mut_cert_chain_buffer, mut_cert_chain_buffer_size, + mut_cert_chain_buffer_hash); + if (!result) { + return false; + } + status = libspdm_append_managed_buffer(&th_curr, mut_cert_chain_buffer_hash, hash_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_f data :\n")); + LIBSPDM_INTERNAL_DUMP_HEX( + libspdm_get_managed_buffer(&session_info->session_transcript.message_f), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_f)); + status = libspdm_append_managed_buffer( + &th_curr, + libspdm_get_managed_buffer(&session_info->session_transcript.message_f), + libspdm_get_managed_buffer_size(&session_info->session_transcript.message_f)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return false; + } + + th_data_buffer_capacity = *th_data_buffer_size; + *th_data_buffer_size = libspdm_get_managed_buffer_size(&th_curr); + libspdm_copy_mem(th_data_buffer, th_data_buffer_capacity, + libspdm_get_managed_buffer(&th_curr), *th_data_buffer_size); + + return true; +} +#else +/* + * This function calculates current TH hash with message A, message K and message F. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hash_buffer_size size in bytes of the th_hash_buffer + * @param th_hash_buffer The buffer to store the th_hash_buffer + * + * @retval RETURN_SUCCESS current TH hash is calculated. + */ +bool libspdm_calculate_th_hash_for_finish(void *context, + void *spdm_session_info, + size_t *th_hash_buffer_size, + void *th_hash_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + uint32_t hash_size; + void *digest_context_th; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hash_buffer_size >= hash_size); + + /* duplicate the th context, because we still need use original context to continue.*/ + digest_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (digest_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + digest_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, + digest_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + digest_context_th, th_hash_buffer); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, digest_context_th); + if (!result) { + return false; + } + + *th_hash_buffer_size = hash_size; + + return true; +} + +/* + * This function calculates current TH hmac with message A, message K and message F, with response finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_finish_rsp(void *context, + void *spdm_session_info, + size_t *th_hmac_buffer_size, + void *th_hmac_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + void *secured_message_context; + uint32_t hash_size; + void *hash_context_th; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + secured_message_context = session_info->secured_message_context; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hmac_buffer_size >= hash_size); + LIBSPDM_ASSERT(session_info->session_transcript.digest_context_th != NULL); + + /* duplicate the th context, because we still need use original context to continue.*/ + hash_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (hash_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + hash_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + hash_context_th, hash_data); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_response_finished_key (secured_message_context, + hash_data, hash_size, th_hmac_buffer); + if (!result) { + return false; + } + *th_hmac_buffer_size = hash_size; + + return true; +} + +/* + * This function calculates current TH hmac with message A, message K and message F, with request finished_key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param th_hmac_buffer_size size in bytes of the th_hmac_buffer + * @param th_hmac_buffer The buffer to store the th_hmac_buffer + * + * @retval RETURN_SUCCESS current TH hmac is calculated. + */ +bool libspdm_calculate_th_hmac_for_finish_req(void *context, + void *spdm_session_info, + size_t *th_hmac_buffer_size, + void *th_hmac_buffer) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + void *secured_message_context; + uint32_t hash_size; + void *hash_context_th; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; + + spdm_context = context; + session_info = spdm_session_info; + secured_message_context = session_info->secured_message_context; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + LIBSPDM_ASSERT(*th_hmac_buffer_size >= hash_size); + LIBSPDM_ASSERT(session_info->session_transcript.digest_context_th != NULL); + + /* duplicate the th context, because we still need use original context to continue.*/ + hash_context_th = libspdm_hash_new (spdm_context->connection_info.algorithm.base_hash_algo); + if (hash_context_th == NULL) { + return false; + } + result = libspdm_hash_duplicate (spdm_context->connection_info.algorithm.base_hash_algo, + session_info->session_transcript.digest_context_th, + hash_context_th); + if (!result) { + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + return false; + } + result = libspdm_hash_final (spdm_context->connection_info.algorithm.base_hash_algo, + hash_context_th, hash_data); + libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, hash_context_th); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_request_finished_key (secured_message_context, + hash_data, hash_size, th_hmac_buffer); + if (!result) { + return false; + } + *th_hmac_buffer_size = hash_size; + + return true; +} +#endif + +/* + * This function calculates th1 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param th1_hash_data th1 hash + * + * @retval RETURN_SUCCESS th1 hash is calculated. + */ +bool libspdm_calculate_th1_hash(void *context, + void *spdm_session_info, + bool is_requester, + uint8_t *th1_hash_data) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; +#endif +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + size_t hash_size; +#endif + spdm_context = context; + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Calc th1 hash ...\n")); + + session_info = spdm_session_info; + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); +#endif +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + if (!session_info->use_psk) { + if (is_requester) { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } + if (!result) { + return false; + } + } else { + cert_chain_buffer = NULL; + cert_chain_buffer_size = 0; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_exchange( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, th1_hash_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hash_for_exchange( + spdm_context, session_info, &hash_size, th1_hash_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th1 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(th1_hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + return true; +} + +/* + * This function calculates th2 hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_info The SPDM session ID. + * @param is_requester Indicate of the key generation for a requester or a responder. + * @param th1_hash_data th2 hash + * + * @retval RETURN_SUCCESS th2 hash is calculated. + */ +bool libspdm_calculate_th2_hash(void *context, + void *spdm_session_info, + bool is_requester, + uint8_t *th2_hash_data) +{ + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; +#endif +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + size_t hash_size; +#endif + + spdm_context = context; + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Calc th2 hash ...\n")); + + session_info = spdm_session_info; + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + if (!session_info->use_psk) { + if (is_requester) { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } + if (!result) { + return false; + } + if (session_info->mut_auth_requested) { + if (is_requester) { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } + if (!result) { + return false; + } + } else { + mut_cert_chain_buffer = NULL; + mut_cert_chain_buffer_size = 0; + } + } else { + cert_chain_buffer = NULL; + cert_chain_buffer_size = 0; + mut_cert_chain_buffer = NULL; + mut_cert_chain_buffer_size = 0; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, mut_cert_chain_buffer, + mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, th2_hash_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hash_for_finish( + spdm_context, session_info, &hash_size, th2_hash_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th2 hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(th2_hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + return true; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c new file mode 100644 index 0000000000..5dca6f1311 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c @@ -0,0 +1,102 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +#if LIBSPDM_ENABLE_MSG_LOG +void libspdm_init_msg_log (void *context, void *msg_buffer, size_t msg_buffer_size) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT((context != NULL) && (msg_buffer != NULL)); + LIBSPDM_ASSERT(msg_buffer_size != 0); + + spdm_context = context; + spdm_context->msg_log.buffer = msg_buffer; + spdm_context->msg_log.max_buffer_size = msg_buffer_size; + spdm_context->msg_log.buffer_size = 0; + spdm_context->msg_log.mode = 0; + spdm_context->msg_log.status = 0; +} + +void libspdm_set_msg_log_mode (void *context, uint32_t mode) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT(context != NULL); + + spdm_context = context; + spdm_context->msg_log.mode = mode; +} + +uint32_t libspdm_get_msg_log_status (void *context) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT(context != NULL); + + spdm_context = context; + + return spdm_context->msg_log.status; +} + +size_t libspdm_get_msg_log_size (void *context) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT(context != NULL); + + spdm_context = context; + + return spdm_context->msg_log.buffer_size; +} + +void libspdm_reset_msg_log (void *context) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT(context != NULL); + + spdm_context = context; + + spdm_context->msg_log.buffer_size = 0; + spdm_context->msg_log.mode = 0; + spdm_context->msg_log.status = 0; +} + +void libspdm_append_msg_log(void *context, void *message, size_t message_size) +{ + libspdm_context_t *spdm_context; + + LIBSPDM_ASSERT((context != NULL) && (message != NULL)); + + spdm_context = context; + + if (((spdm_context->msg_log.mode & LIBSPDM_MSG_LOG_MODE_ENABLE) != 0) && + ((spdm_context->msg_log.status & LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL) == 0)) { + if (spdm_context->msg_log.buffer_size + message_size > + spdm_context->msg_log.max_buffer_size) { + libspdm_copy_mem((uint8_t *)spdm_context->msg_log.buffer + + spdm_context->msg_log.buffer_size, + spdm_context->msg_log.max_buffer_size, message, + spdm_context->msg_log.max_buffer_size - + spdm_context->msg_log.buffer_size); + spdm_context->msg_log.status |= LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL; + spdm_context->msg_log.buffer_size = spdm_context->msg_log.max_buffer_size; + } else { + libspdm_copy_mem((uint8_t *)spdm_context->msg_log.buffer + + spdm_context->msg_log.buffer_size, + spdm_context->msg_log.max_buffer_size, message, message_size); + spdm_context->msg_log.buffer_size += message_size; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Message Logging Status = [%x] Buffer Size = [%x] " + "Max Buffer Size = [%x]\n", spdm_context->msg_log.status, + spdm_context->msg_log.buffer_size, spdm_context->msg_log.max_buffer_size)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_context->msg_log.buffer, spdm_context->msg_log.buffer_size); + } +} +#endif /* LIBSPDM_ENABLE_MSG_LOG */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c new file mode 100644 index 0000000000..a43e01575d --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c @@ -0,0 +1,232 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +/** + * Return the size in bytes of opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response generation. + * + * @return the size in bytes of opaque data version selection. + **/ +size_t libspdm_get_opaque_data_version_selection_data_size(const libspdm_context_t *spdm_context) +{ + size_t size; + + if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { + return 0; + } + + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + size = sizeof(spdm_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_version_selection_t); + } else { + size = sizeof(secured_message_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_version_selection_t); + } + /* Add Padding*/ + return (size + 3) & ~3; +} + +/** + * Return the size in bytes of opaque data supported version. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request generation. + * + * @return the size in bytes of opaque data supported version. + **/ +size_t libspdm_get_opaque_data_supported_version_data_size(libspdm_context_t *spdm_context) +{ + size_t size; + + if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { + return 0; + } + + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + size = sizeof(spdm_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * + spdm_context->local_context.secured_message_version.spdm_version_count; + } else { + size = sizeof(secured_message_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * + spdm_context->local_context.secured_message_version.spdm_version_count; + } + /* Add Padding*/ + return (size + 3) & ~3; +} + +/** + * Return the size in bytes of opaque data supported version. + * + * This function should be called in libspdm_process_opaque_data_supported_version_data. + * + * @param version_count Secure version count. + * + * @return the size in bytes of opaque data supported version. + **/ +size_t libspdm_get_untrusted_opaque_data_supported_version_data_size( + libspdm_context_t *spdm_context, uint8_t version_count) +{ + size_t size; + + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + size = sizeof(spdm_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * version_count; + } else { + size = sizeof(secured_message_general_opaque_data_table_header_t) + + sizeof(secured_message_opaque_element_table_header_t) + + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * version_count; + } + /* Add Padding*/ + return (size + 3) & ~3; +} + +/** + * Get element from multi element opaque data by element id. + * + * This function should be called in + * libspdm_process_opaque_data_supported_version_data/libspdm_process_opaque_data_version_selection_data. + * + * @param[in] data_in_size size of multi element opaque data. + * @param[in] data_in A pointer to the multi element opaque data. + * @param[in] element_id element id. + * @param[in] sm_data_id sm_data_id to identifiy for the Secured Message data type. + * @param[out] get_element_ptr pointer to store finded element + * + * @retval true get element successfully + * @retval false get element failed + **/ +bool libspdm_get_element_from_opaque_data(libspdm_context_t *spdm_context, + size_t data_in_size, const void *data_in, + uint8_t element_id, uint8_t sm_data_id, + const void **get_element_ptr, size_t *get_element_len) +{ + const secured_message_general_opaque_data_table_header_t + *general_opaque_data_table_header; + const spdm_general_opaque_data_table_header_t + *spdm_general_opaque_data_table_header; + const secured_message_opaque_element_table_header_t + *opaque_element_table_header; + const secured_message_opaque_element_header_t + * secured_message_element_header; + + bool result; + uint8_t element_num; + uint8_t element_index; + size_t data_element_size; + size_t current_element_len; + size_t total_element_len; + + total_element_len = 0; + result = false; + + /*check parameter in*/ + if (element_id > SPDM_REGISTRY_ID_JEDEC) { + return false; + } + if ((data_in_size == 0) || (data_in == NULL)) { + return false; + } + + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + spdm_general_opaque_data_table_header = data_in; + if (data_in_size < sizeof(spdm_general_opaque_data_table_header_t)) { + return false; + } + if (spdm_general_opaque_data_table_header->total_elements < 1) { + return false; + } + opaque_element_table_header = (const void *)(spdm_general_opaque_data_table_header + 1); + + element_num = spdm_general_opaque_data_table_header->total_elements; + + data_element_size = data_in_size - sizeof(spdm_general_opaque_data_table_header_t); + } else { + general_opaque_data_table_header = data_in; + if (data_in_size < sizeof(secured_message_general_opaque_data_table_header_t)) { + return false; + } + if ((general_opaque_data_table_header->spec_id != + SECURED_MESSAGE_OPAQUE_DATA_SPEC_ID) || + (general_opaque_data_table_header->opaque_version != + SECURED_MESSAGE_OPAQUE_VERSION) || + (general_opaque_data_table_header->total_elements < 1)) { + return false; + } + opaque_element_table_header = (const void *)(general_opaque_data_table_header + 1); + + element_num = general_opaque_data_table_header->total_elements; + + data_element_size = data_in_size - + sizeof(secured_message_general_opaque_data_table_header_t); + } + + for (element_index = 0; element_index < element_num; element_index++) { + /*ensure the opaque_element_table_header is valid*/ + if (total_element_len + sizeof(secured_message_opaque_element_table_header_t) > + data_element_size) { + return false; + } + + /*check element header id*/ + if ((opaque_element_table_header->id > SPDM_REGISTRY_ID_JEDEC) || + (opaque_element_table_header->vendor_len != 0)) { + return false; + } + + current_element_len = sizeof(secured_message_opaque_element_table_header_t) + + opaque_element_table_header->opaque_element_data_len; + /* Add Padding*/ + current_element_len = (current_element_len + 3) & ~3; + + total_element_len += current_element_len; + + if (data_element_size < total_element_len) { + return false; + } + + if (opaque_element_table_header->id == element_id) { + secured_message_element_header = (const void *)(opaque_element_table_header + 1); + if ((const uint8_t *)secured_message_element_header + + sizeof(secured_message_opaque_element_header_t) > + (const uint8_t *)data_in + data_in_size) { + return false; + } + + if ((secured_message_element_header->sm_data_id == sm_data_id) && + (secured_message_element_header->sm_data_version == + SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION)) { + /*get element by element id*/ + *get_element_ptr = opaque_element_table_header; + *get_element_len = current_element_len; + result = true; + } + } + + /*move to next element*/ + opaque_element_table_header = (const secured_message_opaque_element_table_header_t *) + ((const uint8_t *)opaque_element_table_header + + current_element_len); + } + + /*ensure data size is right*/ + if (data_element_size != total_element_len) { + return false; + } + + return result; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c new file mode 100644 index 0000000000..b90dbaa62b --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c @@ -0,0 +1,231 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_common_lib.h" + +#if LIBSPDM_DEBUG_PRINT_ENABLE +void libspdm_internal_dump_hex_str(const uint8_t *data, size_t size) +{ + size_t index; + for (index = 0; index < size; index++) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "%02x", (size_t)data[index])); + } +} + +void libspdm_internal_dump_data(const uint8_t *data, size_t size) +{ + size_t index; + for (index = 0; index < size; index++) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "%02x ", (size_t)data[index])); + } +} + +void libspdm_internal_dump_hex(const uint8_t *data, size_t size) +{ + size_t index; + size_t count; + size_t left; + + #define COLUMN_SIZE (16 * 2) + + count = size / COLUMN_SIZE; + left = size % COLUMN_SIZE; + for (index = 0; index < count; index++) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "%04x: ", index * COLUMN_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(data + index * COLUMN_SIZE, COLUMN_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + if (left != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "%04x: ", index * COLUMN_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(data + index * COLUMN_SIZE, left); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } +} +#endif /* LIBSPDM_DEBUG_PRINT_ENABLE */ + +/** + * Reads a 24-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 24-bit value that may be unaligned. + * + * @return The 24-bit value read from buffer. + **/ +uint32_t libspdm_read_uint24(const uint8_t *buffer) +{ + return (uint32_t)(buffer[0] | buffer[1] << 8 | buffer[2] << 16); +} + +/** + * Writes a 24-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 24-bit value that may be unaligned. + * @param value 24-bit value to write to buffer. + **/ +void libspdm_write_uint24(uint8_t *buffer, uint32_t value) +{ + buffer[0] = (uint8_t)(value & 0xFF); + buffer[1] = (uint8_t)((value >> 8) & 0xFF); + buffer[2] = (uint8_t)((value >> 16) & 0xFF); +} + +/** + * Reads a 16-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 16-bit value that may be unaligned. + * + * @return The 16-bit value read from buffer. + **/ +uint16_t libspdm_read_uint16(const uint8_t *buffer) +{ + return (uint16_t)(buffer[0] | buffer[1] << 8); +} + +/** + * Writes a 16-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 16-bit value that may be unaligned. + * @param value 16-bit value to write to buffer. + **/ +void libspdm_write_uint16(uint8_t *buffer, uint16_t value) +{ + buffer[0] = (uint8_t)(value & 0xFF); + buffer[1] = (uint8_t)((value >> 8) & 0xFF); +} + +/** + * Reads a 32-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 32-bit value that may be unaligned. + * + * @return The 32-bit value read from buffer. + **/ +uint32_t libspdm_read_uint32(const uint8_t *buffer) +{ + return (uint32_t)(buffer[0] | buffer[1] << 8 | buffer[2] << 16 | buffer[3] << 24); +} + +/** + * Writes a 32-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 32-bit value that may be unaligned. + * @param value 32-bit value to write to buffer. + **/ +void libspdm_write_uint32(uint8_t *buffer, uint32_t value) +{ + buffer[0] = (uint8_t)(value & 0xFF); + buffer[1] = (uint8_t)((value >> 8) & 0xFF); + buffer[2] = (uint8_t)((value >> 16) & 0xFF); + buffer[3] = (uint8_t)((value >> 24) & 0xFF); +} + +/** + * Reads a 64-bit value from memory that may be unaligned. + * + * @param buffer The pointer to a 64-bit value that may be unaligned. + * + * @return The 64-bit value read from buffer. + **/ +uint64_t libspdm_read_uint64(const uint8_t *buffer) +{ + return (uint64_t)(buffer[0]) | + ((uint64_t)(buffer[1]) << 8) | + ((uint64_t)(buffer[2]) << 16) | + ((uint64_t)(buffer[3]) << 24) | + ((uint64_t)(buffer[4]) << 32) | + ((uint64_t)(buffer[5]) << 40) | + ((uint64_t)(buffer[6]) << 48) | + ((uint64_t)(buffer[7]) << 56); +} + +/** + * Writes a 64-bit value to memory that may be unaligned. + * + * @param buffer The pointer to a 64-bit value that may be unaligned. + * @param value 64-bit value to write to buffer. + **/ +void libspdm_write_uint64(uint8_t *buffer, uint64_t value) +{ + buffer[0] = (uint8_t)(value & 0xFF); + buffer[1] = (uint8_t)((value >> 8) & 0xFF); + buffer[2] = (uint8_t)((value >> 16) & 0xFF); + buffer[3] = (uint8_t)((value >> 24) & 0xFF); + buffer[4] = (uint8_t)((value >> 32) & 0xFF); + buffer[5] = (uint8_t)((value >> 40) & 0xFF); + buffer[6] = (uint8_t)((value >> 48) & 0xFF); + buffer[7] = (uint8_t)((value >> 56) & 0xFF); +} + +libspdm_return_t libspdm_append_managed_buffer(void *m_buffer, const void *buffer, + size_t buffer_size) +{ + libspdm_managed_buffer_t *managed_buffer; + + LIBSPDM_ASSERT(buffer != NULL); + + if (buffer_size == 0) { + return LIBSPDM_STATUS_SUCCESS; + } + + managed_buffer = m_buffer; + + LIBSPDM_ASSERT(buffer_size != 0); + LIBSPDM_ASSERT(managed_buffer->max_buffer_size >= managed_buffer->buffer_size); + + if (buffer_size > managed_buffer->max_buffer_size - managed_buffer->buffer_size) { + /* Do not LIBSPDM_ASSERT here, because command processor will append message from external.*/ + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_append_managed_buffer 0x%x fail, rest 0x%x only\n", + (uint32_t)buffer_size, + (uint32_t)(managed_buffer->max_buffer_size - managed_buffer->buffer_size))); + return LIBSPDM_STATUS_BUFFER_FULL; + } + LIBSPDM_ASSERT(buffer_size <= managed_buffer->max_buffer_size - managed_buffer->buffer_size); + + libspdm_copy_mem((uint8_t *)(managed_buffer + 1) + managed_buffer->buffer_size, + buffer_size, buffer, buffer_size); + managed_buffer->buffer_size += buffer_size; + + return LIBSPDM_STATUS_SUCCESS; +} + +void libspdm_reset_managed_buffer(void *m_buffer) +{ + libspdm_managed_buffer_t *managed_buffer; + + managed_buffer = m_buffer; + managed_buffer->buffer_size = 0; + + libspdm_zero_mem(managed_buffer + 1, managed_buffer->max_buffer_size); +} + +size_t libspdm_get_managed_buffer_size(void *m_buffer) +{ + libspdm_managed_buffer_t *managed_buffer; + + managed_buffer = m_buffer; + + return managed_buffer->buffer_size; +} + +void *libspdm_get_managed_buffer(void *m_buffer) +{ + libspdm_managed_buffer_t *managed_buffer; + + managed_buffer = m_buffer; + + return (managed_buffer + 1); +} + +void libspdm_init_managed_buffer(void *m_buffer, size_t max_buffer_size) +{ + libspdm_managed_buffer_t *managed_buffer; + + managed_buffer = m_buffer; + managed_buffer->max_buffer_size = max_buffer_size; + + libspdm_reset_managed_buffer(m_buffer); +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c new file mode 100644 index 0000000000..f10cc6bf69 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c @@ -0,0 +1,159 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +uint32_t libspdm_get_aead_key_size(uint16_t aead_cipher_suite) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: + return 16; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: + return 32; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: + return 32; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: + return 16; + default: + return 0; + } +} + +uint32_t libspdm_get_aead_iv_size(uint16_t aead_cipher_suite) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: + return 12; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: + return 12; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: + return 12; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: + return 12; + default: + return 0; + } +} + +uint32_t libspdm_get_aead_tag_size(uint16_t aead_cipher_suite) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: + return 16; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: + return 16; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: + return 16; + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: + return 16; + default: + return 0; + } +} + +bool libspdm_aead_encryption(const spdm_version_number_t secured_message_version, + uint16_t aead_cipher_suite, const uint8_t *key, + size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, + size_t a_data_size, const uint8_t *data_in, + size_t data_in_size, uint8_t *tag_out, + size_t tag_size, uint8_t *data_out, + size_t *data_out_size) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: +#if LIBSPDM_AEAD_GCM_SUPPORT + return libspdm_aead_aes_gcm_encrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag_out, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: +#if LIBSPDM_AEAD_GCM_SUPPORT + return libspdm_aead_aes_gcm_encrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag_out, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT + return libspdm_aead_chacha20_poly1305_encrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag_out, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: +#if LIBSPDM_AEAD_SM4_SUPPORT + return libspdm_aead_sm4_gcm_encrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag_out, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_aead_decryption(const spdm_version_number_t secured_message_version, + uint16_t aead_cipher_suite, const uint8_t *key, + size_t key_size, const uint8_t *iv, + size_t iv_size, const uint8_t *a_data, + size_t a_data_size, const uint8_t *data_in, + size_t data_in_size, const uint8_t *tag, + size_t tag_size, uint8_t *data_out, + size_t *data_out_size) +{ + switch (aead_cipher_suite) { + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: +#if LIBSPDM_AEAD_GCM_SUPPORT + return libspdm_aead_aes_gcm_decrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: +#if LIBSPDM_AEAD_GCM_SUPPORT + return libspdm_aead_aes_gcm_decrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT + return libspdm_aead_chacha20_poly1305_decrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: +#if LIBSPDM_AEAD_SM4_SUPPORT + return libspdm_aead_sm4_gcm_decrypt(key, key_size, iv, iv_size, a_data, + a_data_size, data_in, data_in_size, tag, + tag_size, data_out, data_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c new file mode 100644 index 0000000000..3215821f4e --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c @@ -0,0 +1,1154 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +typedef struct { + bool is_requester; + uint8_t op_code; + const void *context; + size_t context_size; + size_t zero_pad_size; +} libspdm_signing_context_str_t; + +static const libspdm_signing_context_str_t m_libspdm_signing_context_str_table[] = { + {false, SPDM_CHALLENGE_AUTH, SPDM_CHALLENGE_AUTH_SIGN_CONTEXT, + SPDM_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE, 36 - SPDM_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE}, + {true, SPDM_CHALLENGE_AUTH, SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT, + SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE, 36 - SPDM_MUT_CHALLENGE_AUTH_SIGN_CONTEXT_SIZE}, + {false, SPDM_MEASUREMENTS, SPDM_MEASUREMENTS_SIGN_CONTEXT, SPDM_MEASUREMENTS_SIGN_CONTEXT_SIZE, + 36 - SPDM_MEASUREMENTS_SIGN_CONTEXT_SIZE}, + {false, SPDM_KEY_EXCHANGE_RSP, SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT, + SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT_SIZE, + 36 - SPDM_KEY_EXCHANGE_RESPONSE_SIGN_CONTEXT_SIZE}, + {true, SPDM_FINISH, SPDM_FINISH_SIGN_CONTEXT, SPDM_FINISH_SIGN_CONTEXT_SIZE, + 36 - SPDM_FINISH_SIGN_CONTEXT_SIZE}, +}; + +#if LIBSPDM_RSA_SSA_SUPPORT +static bool libspdm_rsa_pkcs1_sign_with_nid_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_rsa_pkcs1_sign_with_nid (context, hash_nid, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_RSA_PSS_SUPPORT +static bool libspdm_rsa_pss_sign_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_rsa_pss_sign (context, hash_nid, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_ECDSA_SUPPORT +static bool libspdm_ecdsa_sign_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_ecdsa_sign (context, hash_nid, + message, message_size, signature, sig_size); +} +#endif + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +static bool libspdm_eddsa_sign_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_eddsa_sign (context, hash_nid, param, param_size, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_SM2_DSA_SUPPORT +static bool libspdm_sm2_dsa_sign_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + return libspdm_sm2_dsa_sign (context, hash_nid, param, param_size, + message, message_size, signature, sig_size); +} +#endif + +/** + * Get the SPDM signing context string, which is required since SPDM 1.2. + * + * @param spdm_version negotiated SPDM version + * @param op_code the SPDM opcode which requires the signing + * @param is_requester indicate if the signing is from a requester + * @param context_size SPDM signing context size + **/ +static const void *libspdm_get_signing_context_string ( + spdm_version_number_t spdm_version, + uint8_t op_code, + bool is_requester, + size_t *context_size) +{ + size_t index; + + /* It is introduced in SPDM 1.2*/ + LIBSPDM_ASSERT((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11); + + for (index = 0; index < LIBSPDM_ARRAY_SIZE(m_libspdm_signing_context_str_table); index++) { + if (m_libspdm_signing_context_str_table[index].is_requester == is_requester && + m_libspdm_signing_context_str_table[index].op_code == op_code) { + *context_size = m_libspdm_signing_context_str_table[index].context_size; + return m_libspdm_signing_context_str_table[index].context; + } + } + LIBSPDM_ASSERT(false); + return NULL; +} + +/** + * Create SPDM signing context, which is required since SPDM 1.2. + * + * @param spdm_version negotiated SPDM version + * @param op_code the SPDM opcode which requires the signing + * @param is_requester indicate if the signing is from a requester + * @param spdm_signing_context SPDM signing context + **/ +static void libspdm_create_signing_context ( + spdm_version_number_t spdm_version, + uint8_t op_code, + bool is_requester, + void *spdm_signing_context) +{ + size_t index; + char *context_str; + + /* It is introduced in SPDM 1.2*/ + LIBSPDM_ASSERT((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11); + + /* So far, it only leaves 1 bytes for version*/ + LIBSPDM_ASSERT((((spdm_version >> 12) & 0xF) < 10) && + (((spdm_version >> 8) & 0xF) < 10)); + + context_str = spdm_signing_context; + for (index = 0; index < 4; index++) { + libspdm_copy_mem(context_str, + SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT_SIZE, + SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT, + SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT_SIZE); + /* patch the version*/ + context_str[11] = (char)('0' + ((spdm_version >> 12) & 0xF)); + context_str[13] = (char)('0' + ((spdm_version >> 8) & 0xF)); + context_str[15] = (char)('*'); + context_str += SPDM_VERSION_1_2_SIGNING_PREFIX_CONTEXT_SIZE; + } + for (index = 0; index < LIBSPDM_ARRAY_SIZE(m_libspdm_signing_context_str_table); index++) { + if (m_libspdm_signing_context_str_table[index].is_requester == is_requester && + m_libspdm_signing_context_str_table[index].op_code == op_code) { + libspdm_zero_mem ( + context_str, + m_libspdm_signing_context_str_table[index].zero_pad_size); + libspdm_copy_mem(context_str + m_libspdm_signing_context_str_table[index].zero_pad_size, + m_libspdm_signing_context_str_table[index].context_size, + m_libspdm_signing_context_str_table[index].context, + m_libspdm_signing_context_str_table[index].context_size); + return; + } + } + LIBSPDM_ASSERT(false); +} + +uint32_t libspdm_get_asym_signature_size(uint32_t base_asym_algo) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + return 256; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + return 384; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: + return 512; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + return 32 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + return 48 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: + return 66 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + return 32 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + return 32 * 2; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + return 57 * 2; + default: + return 0; + } +} + +static bool libspdm_asym_sign_wrap (void *context, size_t hash_nid, uint32_t base_asym_algo, + const uint8_t *param, size_t param_size, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: +#if LIBSPDM_RSA_SSA_SUPPORT + return libspdm_rsa_pkcs1_sign_with_nid_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if LIBSPDM_RSA_PSS_SUPPORT + return libspdm_rsa_pss_sign_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT + return libspdm_ecdsa_sign_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + return libspdm_eddsa_sign_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT + return libspdm_sm2_dsa_sign_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +void libspdm_asym_free(uint32_t base_asym_algo, void *context) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) + libspdm_rsa_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT + libspdm_ec_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + libspdm_ecd_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT + libspdm_sm2_dsa_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + default: + LIBSPDM_ASSERT(false); + break; + } +} + +/** + * Return if asymmetric function need message hash. + * + * @param base_asym_algo SPDM base_asym_algo + * + * @retval true asymmetric function need message hash + * @retval false asymmetric function need raw message + **/ +static bool libspdm_asym_func_need_hash(uint32_t base_asym_algo) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: + return true; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: + return true; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + return false; + default: + LIBSPDM_ASSERT(false); + break; + } + + return false; +} + +#if LIBSPDM_RSA_SSA_SUPPORT +static bool libspdm_rsa_pkcs1_verify_with_nid_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_rsa_pkcs1_verify_with_nid (context, hash_nid, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_RSA_PSS_SUPPORT +static bool libspdm_rsa_pss_verify_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_rsa_pss_verify (context, hash_nid, message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_ECDSA_SUPPORT +bool libspdm_ecdsa_verify_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_ecdsa_verify (context, hash_nid, message, message_size, signature, sig_size); +} +#endif + +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +bool libspdm_eddsa_verify_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_eddsa_verify (context, hash_nid, param, param_size, + message, message_size, signature, sig_size); +} +#endif + +#if LIBSPDM_SM2_DSA_SUPPORT +bool libspdm_sm2_dsa_verify_wrap (void *context, size_t hash_nid, + const uint8_t *param, size_t param_size, + const uint8_t *message, + size_t message_size, + const uint8_t *signature, + size_t sig_size) +{ + return libspdm_sm2_dsa_verify (context, hash_nid, param, param_size, + message, message_size, signature, sig_size); +} +#endif + +static bool libspdm_asym_verify_wrap( + void *context, size_t hash_nid, uint32_t base_asym_algo, + const uint8_t *param, size_t param_size, + const uint8_t *message, size_t message_size, + const uint8_t *signature, size_t sig_size) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: +#if LIBSPDM_RSA_SSA_SUPPORT + return libspdm_rsa_pkcs1_verify_with_nid_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if LIBSPDM_RSA_PSS_SUPPORT + return libspdm_rsa_pss_verify_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT + return libspdm_ecdsa_verify_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + return libspdm_eddsa_verify_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT + return libspdm_sm2_dsa_verify_wrap(context, hash_nid, + param, param_size, + message, message_size, + signature, sig_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message, + size_t message_size, const uint8_t *signature, + size_t sig_size) +{ + bool need_hash; + uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t hash_size; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_asym_func_need_hash(base_asym_algo); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing. */ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, false, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, false, + spdm12_signing_context_with_hash); + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + &spdm12_signing_context_with_hash[ + SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE]); + if (!result) { + return false; + } + + /* re-assign message and message_size for signing */ + hash_size = libspdm_get_hash_size(base_hash_algo); + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + /* Passthru */ + } + + if (need_hash) { + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, message_hash); + if (!result) { + return false; + } + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } +} + +bool libspdm_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message_hash, + size_t hash_size, const uint8_t *signature, + size_t sig_size) +{ + bool need_hash; + uint8_t *message; + size_t message_size; + uint8_t full_message_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_asym_func_need_hash(base_asym_algo); + LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, false, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, false, + spdm12_signing_context_with_hash); + libspdm_copy_mem(&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE], + sizeof(spdm12_signing_context_with_hash) + - (&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE] + - spdm12_signing_context_with_hash), + message_hash, hash_size); + + /* assign message and message_size for signing */ + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + if (need_hash) { + result = libspdm_hash_all(base_hash_algo, message, message_size, full_message_hash); + if (!result) { + return false; + } + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + full_message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } + + /* SPDM 1.2 signing done. */ + } + + if (need_hash) { + return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_asym_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message, + size_t message_size, uint8_t *signature, + size_t *sig_size) +{ + bool need_hash; + uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t hash_size; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_asym_func_need_hash(base_asym_algo); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, false, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, false, + spdm12_signing_context_with_hash); + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + &spdm12_signing_context_with_hash[ + SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE]); + if (!result) { + return false; + } + + /* re-assign message and message_size for signing */ + hash_size = libspdm_get_hash_size(base_hash_algo); + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + /* Passthru*/ + } + + if (need_hash) { + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, message_hash); + if (!result) { + return false; + } + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } +} + +bool libspdm_asym_sign_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void *context, const uint8_t *message_hash, + size_t hash_size, uint8_t *signature, + size_t *sig_size) +{ + bool need_hash; + uint8_t *message; + size_t message_size; + uint8_t full_message_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_asym_func_need_hash(base_asym_algo); + LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, false, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, false, + spdm12_signing_context_with_hash); + libspdm_copy_mem(&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE], + sizeof(spdm12_signing_context_with_hash) + - (&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE] + - spdm12_signing_context_with_hash), + message_hash, hash_size); + + /* assign message and message_size for signing */ + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + if (need_hash) { + result = libspdm_hash_all(base_hash_algo, message, message_size, full_message_hash); + if (!result) { + return false; + } + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + full_message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } + + /* SPDM 1.2 signing done. */ + } + + if (need_hash) { + return libspdm_asym_sign_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + LIBSPDM_ASSERT (false); + return false; + } +} + +uint32_t libspdm_get_req_asym_signature_size(uint16_t req_base_asym_alg) +{ + return libspdm_get_asym_signature_size(req_base_asym_alg); +} + +void libspdm_req_asym_free(uint16_t req_base_asym_alg, void *context) +{ + libspdm_asym_free(req_base_asym_alg, context); +} + +bool libspdm_req_asym_func_need_hash(uint16_t req_base_asym_alg) +{ + return libspdm_asym_func_need_hash(req_base_asym_alg); +} + +bool libspdm_req_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message, size_t message_size, + const uint8_t *signature, size_t sig_size) +{ + bool need_hash; + uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t hash_size; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (req_base_asym_alg) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, true, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, true, + spdm12_signing_context_with_hash); + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + &spdm12_signing_context_with_hash[ + SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE]); + if (!result) { + return false; + } + + /* re-assign message and message_size for signing */ + hash_size = libspdm_get_hash_size(base_hash_algo); + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + /* Passthru */ + } + + if (need_hash) { + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, message_hash); + if (!result) { + return false; + } + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } +} + +bool libspdm_req_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size) +{ + bool need_hash; + uint8_t *message; + size_t message_size; + uint8_t full_message_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); + LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (req_base_asym_alg) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, true, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, true, + spdm12_signing_context_with_hash); + libspdm_copy_mem(&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE], + sizeof(spdm12_signing_context_with_hash) + - (&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE] + - spdm12_signing_context_with_hash), + message_hash, hash_size); + + /* assign message and message_size for signing */ + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + if (need_hash) { + result = libspdm_hash_all(base_hash_algo, message, message_size, + full_message_hash); + if (!result) { + return false; + } + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + full_message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } + /* SPDM 1.2 signing done. */ + } + + if (need_hash) { + return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + LIBSPDM_ASSERT (false); + return false; + } +} + +bool libspdm_req_asym_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + bool need_hash; + uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t hash_size; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (req_base_asym_alg) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, true, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, true, + spdm12_signing_context_with_hash); + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + &spdm12_signing_context_with_hash[ + SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE]); + if (!result) { + return false; + } + + /* re-assign message and message_size for signing */ + hash_size = libspdm_get_hash_size(base_hash_algo); + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + /* Passthru */ + } + + if (need_hash) { + hash_size = libspdm_get_hash_size(base_hash_algo); + result = libspdm_hash_all(base_hash_algo, message, message_size, + message_hash); + if (!result) { + return false; + } + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } +} + +bool libspdm_req_asym_sign_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size) +{ + bool need_hash; + uint8_t *message; + size_t message_size; + uint8_t full_message_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + size_t hash_nid; + uint8_t spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + + LIBSPDM_MAX_HASH_SIZE]; + const void *param; + size_t param_size; + + hash_nid = libspdm_get_hash_nid(base_hash_algo); + need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); + LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); + + param = NULL; + param_size = 0; + + if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { + /* Need use SPDM 1.2 signing */ + switch (req_base_asym_alg) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + param = ""; + param_size = 0; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + hash_nid = LIBSPDM_CRYPTO_NID_NULL; + param = libspdm_get_signing_context_string (spdm_version, op_code, true, ¶m_size); + break; + default: + /* pass thru for rest algorithm */ + break; + } + + libspdm_create_signing_context (spdm_version, op_code, true, + spdm12_signing_context_with_hash); + libspdm_copy_mem(&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE], + sizeof(spdm12_signing_context_with_hash) + - (&spdm12_signing_context_with_hash[SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE] + - spdm12_signing_context_with_hash), + message_hash, hash_size); + + /* assign message and message_size for signing */ + message = spdm12_signing_context_with_hash; + message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; + + if (need_hash) { + result = libspdm_hash_all(base_hash_algo, message, message_size, + full_message_hash); + if (!result) { + return false; + } + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + full_message_hash, hash_size, + signature, sig_size); + } else { + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } + + /* SPDM 1.2 signing done. */ + } + + if (need_hash) { + return libspdm_asym_sign_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } else { + LIBSPDM_ASSERT (false); + return false; + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c new file mode 100644 index 0000000000..539e588d6c --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c @@ -0,0 +1,1325 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +/**pathLenConstraint is optional. + * In https://www.pkisolutions.com/basic-constraints-certificate-extension/: + * pathLenConstraint: How many CAs are allowed in the chain below current CA certificate. + * This setting has no meaning for end entity certificates. + **/ + +/** + * leaf cert spdm extension len + * len > 2 * (spdm id-DMTF-spdm size + 2) + **/ + +#ifndef SPDM_EXTENDSION_LEN +#define SPDM_EXTENDSION_LEN 30 +#endif + +/*max public key encryption algo oid len*/ +#ifndef LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN +#define LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN 10 +#endif + +/*leaf cert basic constraints len,CA = false: 30 03 01 01 00*/ +#ifndef BASIC_CONSTRAINTS_CA_LEN +#define BASIC_CONSTRAINTS_CA_LEN 5 +#endif + +/** + * 0x02 is integer; + * 0x82 indicates that the length is expressed in two bytes; + * 0x01 and 0x01 are rsa key len; + **/ +#define KEY_ENCRY_ALGO_RSA2048_FLAG {0x02, 0x82, 0x01, 0x01} +#define KEY_ENCRY_ALGO_RSA3072_FLAG {0x02, 0x82, 0x01, 0x81} +#define KEY_ENCRY_ALGO_RSA4096_FLAG {0x02, 0x82, 0x02, 0x01} + +/* the other case is ASN1 code different when integer is 1 on highest position*/ +#define KEY_ENCRY_ALGO_RSA2048_FLAG_OTHER {0x02, 0x82, 0x01, 0x00} +#define KEY_ENCRY_ALGO_RSA3072_FLAG_OTHER {0x02, 0x82, 0x01, 0x80} +#define KEY_ENCRY_ALGO_RSA4096_FLAG_OTHER {0x02, 0x82, 0x02, 0x00} + +/** + * https://oidref.com/1.2.840.10045.3.1.7 + * ECC256 curve OID: 1.2.840.10045.3.1.7 + * https://oidref.com/1.3.132.0.34 + * ECC384 curve OID: 1.3.132.0.34 + * https://oidref.com/1.3.132.0.35 + * ECC521 curve OID: 1.3.132.0.35 + **/ +#define KEY_ENCRY_ALGO_ECC256_OID {0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01, 0x07} +#define KEY_ENCRY_ALGO_ECC384_OID {0x2B, 0x81, 0x04, 0x00, 0x22} +#define KEY_ENCRY_ALGO_ECC521_OID {0x2B, 0x81, 0x04, 0x00, 0x23} + +/** + * EDxxx OID: https://datatracker.ietf.org/doc/html/rfc8420 + * ED448 OID: 1.3.101.113 + * ED25519 OID: 1.3.101.112 + **/ +#define ENCRY_ALGO_ED25519_OID {0x2B, 0x65, 0x70} +#define ENCRY_ALGO_ED448_OID {0x2B, 0x65, 0x71} + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate. + * + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size Size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the retrieved public + * key component. Use libspdm_asym_free() function to free the resource. + * + * @retval true public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +typedef bool (*libspdm_asym_get_public_key_from_x509_func)(const uint8_t *cert, + size_t cert_size, + void **context); + +/** + * Return asymmetric GET_PUBLIC_KEY_FROM_X509 function, based upon the negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * + * @return asymmetric GET_PUBLIC_KEY_FROM_X509 function + **/ +libspdm_asym_get_public_key_from_x509_func +static libspdm_get_asym_get_public_key_from_x509(uint32_t base_asym_algo) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) + return libspdm_rsa_get_public_key_from_x509; +#else + LIBSPDM_ASSERT(false); + break; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT + return libspdm_ec_get_public_key_from_x509; +#else + LIBSPDM_ASSERT(false); + break; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + return libspdm_ecd_get_public_key_from_x509; +#else + LIBSPDM_ASSERT(false); + break; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT + return libspdm_sm2_get_public_key_from_x509; +#else + LIBSPDM_ASSERT(false); + break; +#endif + default: + LIBSPDM_ASSERT(false); + break; + } + + return NULL; +} + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the retrieved public key component. + * Use libspdm_asym_free() function to free the resource. + * + * @retval true public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_asym_get_public_key_from_x509(uint32_t base_asym_algo, + const uint8_t *cert, + size_t cert_size, + void **context) +{ + libspdm_asym_get_public_key_from_x509_func get_public_key_from_x509_function; + get_public_key_from_x509_function = libspdm_get_asym_get_public_key_from_x509(base_asym_algo); + if (get_public_key_from_x509_function == NULL) { + return false; + } + return get_public_key_from_x509_function(cert, cert_size, context); +} + +/** + * Return requester asymmetric GET_PUBLIC_KEY_FROM_X509 function, based upon the negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * + * @return requester asymmetric GET_PUBLIC_KEY_FROM_X509 function + **/ +static libspdm_asym_get_public_key_from_x509_func +libspdm_get_req_asym_get_public_key_from_x509(uint16_t req_base_asym_alg) +{ + return libspdm_get_asym_get_public_key_from_x509(req_base_asym_alg); +} + +/** + * Retrieve the asymmetric public key from one DER-encoded X509 certificate, + * based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param cert Pointer to the DER-encoded X509 certificate. + * @param cert_size size of the X509 certificate in bytes. + * @param context Pointer to new-generated asymmetric context which contain the retrieved public key component. + * Use libspdm_asym_free() function to free the resource. + * + * @retval true public key was retrieved successfully. + * @retval false Fail to retrieve public key from X509 certificate. + **/ +bool libspdm_req_asym_get_public_key_from_x509(uint16_t req_base_asym_alg, + const uint8_t *cert, + size_t cert_size, + void **context) +{ + libspdm_asym_get_public_key_from_x509_func get_public_key_from_x509_function; + get_public_key_from_x509_function = + libspdm_get_req_asym_get_public_key_from_x509(req_base_asym_alg); + if (get_public_key_from_x509_function == NULL) { + return false; + } + return get_public_key_from_x509_function(cert, cert_size, context); +} + +/** + * Check the X509 DataTime is within a valid range. + * + * @param spdm_context A pointer to the SPDM context. + * @param from notBefore Pointer to date_time object. + * @param from_size notBefore date_time object size. + * @param to notAfter Pointer to date_time object. + * @param to_size notAfter date_time object size. + * + * @retval true verification pass. + * @retval false verification fail. + **/ +static bool libspdm_internal_x509_date_time_check(const uint8_t *from, + size_t from_size, + const uint8_t *to, + size_t to_size) +{ + int32_t ret; + bool status; + uint8_t f0[64]; + uint8_t t0[64]; + size_t f0_size; + size_t t0_size; + + f0_size = 64; + t0_size = 64; + + status = libspdm_x509_set_date_time("19700101000000Z", f0, &f0_size); + if (!status) { + return false; + } + + status = libspdm_x509_set_date_time("99991231235959Z", t0, &t0_size); + if (!status) { + return false; + } + + /* from >= f0*/ + ret = libspdm_x509_compare_date_time(from, f0); + if (ret < 0) { + return false; + } + + /* to <= t0*/ + ret = libspdm_x509_compare_date_time(t0, to); + if (ret < 0) { + return false; + } + + return true; +} + +/** + * This function returns the SPDM public key encryption algorithm OID len. + * + * @param[in] base_asym_algo SPDM base_asym_algo + * + * @return SPDM public key encryption algorithms OID len. + **/ +static uint32_t libspdm_get_public_key_algo_OID_len(uint32_t base_asym_algo) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: + return 4; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + return 8; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: + return 5; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + return 3; + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +/** + * This function get the SPDM public key encryption algorithm OID. + * + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in,out] oid SPDM public key encryption algorithm OID + * @param[in,out] oid_other Other SPDM public key encryption algorithm OID + * because of ASN1 code for integer + * + * @retval true get OID sucessful. + * @retval false get OID fail. + **/ +static bool libspdm_get_public_key_algo_OID(uint32_t base_asym_algo, uint8_t *oid, + uint8_t *oid_other) +{ + uint32_t oid_len; + oid_len = libspdm_get_public_key_algo_OID_len(base_asym_algo); + + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: { + uint8_t encry_algo_oid_rsa2048[] = KEY_ENCRY_ALGO_RSA2048_FLAG; + uint8_t encry_algo_oid_rsa2048_ohter[] = KEY_ENCRY_ALGO_RSA2048_FLAG_OTHER; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa2048, oid_len); + libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa2048_ohter, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: { + uint8_t encry_algo_oid_rsa3072[] = KEY_ENCRY_ALGO_RSA3072_FLAG; + uint8_t encry_algo_oid_rsa3072_ohter[] = KEY_ENCRY_ALGO_RSA3072_FLAG_OTHER; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa3072, oid_len); + libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa3072_ohter, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: { + uint8_t encry_algo_oid_rsa4096[] = KEY_ENCRY_ALGO_RSA4096_FLAG; + uint8_t encry_algo_oid_rsa4096_ohter[] = KEY_ENCRY_ALGO_RSA4096_FLAG_OTHER; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa4096, oid_len); + libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa4096_ohter, oid_len); + break; + } + + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: { + uint8_t encry_algo_oid_ecc256[] = KEY_ENCRY_ALGO_ECC256_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc256, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: { + uint8_t encry_algo_oid_ecc384[] = KEY_ENCRY_ALGO_ECC384_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc384, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: { + uint8_t encry_algo_oid_ecc521[] = KEY_ENCRY_ALGO_ECC521_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc521, oid_len); + break; + } + + /*sm2 oid TBD*/ + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: + return true; + + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: { + uint8_t encry_algo_oid_ed25519[] = ENCRY_ALGO_ED25519_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ed25519, oid_len); + break; + } + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: { + uint8_t encry_algo_oid_ed448[] = ENCRY_ALGO_ED448_OID; + libspdm_copy_mem(oid, oid_len, encry_algo_oid_ed448, oid_len); + break; + } + + default: + LIBSPDM_ASSERT(false); + return false; + } + + return true; +} + +/** + * Verify cert public key encryption algorithm is matched to negotiated base_aysm algo + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[out] oid cert public key encryption algorithm OID + * @param[in] oid_size the buffer size for required OID + * + * @retval true get public key oid from cert successfully + * @retval false get public key oid from cert fail + **/ +static bool libspdm_get_public_key_oid(const uint8_t *cert, size_t cert_size, + uint8_t *oid, size_t oid_size, uint32_t base_asym_algo) +{ + bool ret; + uint8_t *ptr; + int32_t length; + size_t obj_len; + uint8_t *end; + uint8_t index; + uint8_t sequence_time; + + length = (int32_t)cert_size; + ptr = (uint8_t*)(size_t)cert; + obj_len = 0; + end = ptr + length; + ret = true; + + /* TBSCertificate have 5 sequence before subjectPublicKeyInfo*/ + sequence_time = 5; + + /*all cert sequence*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + /*TBSCertificate sequence*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + end = ptr + obj_len; + /*version*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + ptr += obj_len; + /*serialNumber*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_INTEGER); + if (!ret) { + return false; + } + + /** + * signature AlgorithmIdentifier, + * issuer Name, + * validity Validity, + * subject Name, + * subjectPublicKeyInfo + **/ + for (index = 0; index < sequence_time; index++) { + ptr += obj_len; + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + } + + switch (base_asym_algo) + { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + ptr += obj_len; + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_BIT_STRING); + if (!ret) { + return false; + } + + /*get rsa key len*/ + ptr++; + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + libspdm_copy_mem(oid, oid_size, ptr, oid_size); + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); + if (!ret) { + return false; + } + + /*get ecc second oid*/ + ptr +=obj_len; + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); + if (!ret) { + return false; + } + + if (oid_size != obj_len) { + return false; + } + + libspdm_copy_mem(oid, oid_size, ptr, obj_len); + break; + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + /*get eddsa oid*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); + if (!ret) { + return false; + } + + if (oid_size != obj_len) { + return false; + } + + libspdm_copy_mem(oid, oid_size, ptr, obj_len); + break; + default: + LIBSPDM_ASSERT(false); + return false; + } + + return true; +} + +/** + * Verify cert public key encryption algorithm is matched to negotiated base_aysm algo + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * + * @retval true verify pass + * @retval false verify fail + **/ +static bool libspdm_verify_cert_subject_public_key_info(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo) +{ + size_t oid_len; + bool status; + + /*public key encrypt algo OID from cert*/ + uint8_t cert_public_key_crypt_algo_oid[LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN]; + /*public key encrypt algo OID from libspdm stored*/ + uint8_t libspdm_public_key_crypt_algo_oid[LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN]; + uint8_t libspdm_public_key_crypt_algo_oid_other[LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN]; + + libspdm_zero_mem(libspdm_public_key_crypt_algo_oid, LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN); + libspdm_zero_mem(libspdm_public_key_crypt_algo_oid_other, LIBSPDM_MAX_ENCRYPTION_ALGO_OID_LEN); + + /*work around: skip the sm2*/ + if (base_asym_algo == SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256) { + return true; + } + + oid_len = libspdm_get_public_key_algo_OID_len(base_asym_algo); + if(oid_len == 0) { + return false; + } + /*get public key encrypt algo OID from libspdm stored*/ + status = libspdm_get_public_key_algo_OID(base_asym_algo, + libspdm_public_key_crypt_algo_oid, + libspdm_public_key_crypt_algo_oid_other); + if (!status) { + return status; + } + + /*get public key encrypt algo OID from cert*/ + status = libspdm_get_public_key_oid(cert, cert_size, cert_public_key_crypt_algo_oid, oid_len, + base_asym_algo); + if (!status || (libspdm_const_compare_mem(cert_public_key_crypt_algo_oid, + libspdm_public_key_crypt_algo_oid, oid_len) && + libspdm_const_compare_mem(cert_public_key_crypt_algo_oid, + libspdm_public_key_crypt_algo_oid_other, oid_len))) { + return false; + } + + return status; +} + +/** + * Verify leaf cert basic_constraints CA is false + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true verify pass,two case: 1.basic constraints is not present in cert; + * 2. cert basic_constraints CA is false; + * @retval false verify fail + **/ +static bool libspdm_verify_leaf_cert_basic_constraints(const uint8_t *cert, size_t cert_size) +{ + bool status; + /*basic_constraints from cert*/ + uint8_t cert_basic_constraints[BASIC_CONSTRAINTS_CA_LEN]; + size_t len; + + /*leaf cert basic_constraints case1: CA: false and CA object is excluded */ + #define BASIC_CONSTRAINTS_STRING_CASE1 {0x30, 0x00} + uint8_t basic_constraints_case1[] = BASIC_CONSTRAINTS_STRING_CASE1; + + /*leaf cert basic_constraints case2: CA: false */ + #define BASIC_CONSTRAINTS_STRING_CASE2 {0x30, 0x03, 0x01, 0x01, 0x00} + uint8_t basic_constraints_case2[] = BASIC_CONSTRAINTS_STRING_CASE2; + + len = BASIC_CONSTRAINTS_CA_LEN; + + status = libspdm_x509_get_extended_basic_constraints(cert, cert_size, + cert_basic_constraints, &len); + + if (len == 0) { + /* basic constraints is not present in cert */ + return true; + } else if (!status ) { + return false; + } + + if ((len == sizeof(basic_constraints_case1)) && + (!libspdm_const_compare_mem(cert_basic_constraints, + basic_constraints_case1, + sizeof(basic_constraints_case1)))) { + return true; + } + + if ((len == sizeof(basic_constraints_case2)) && + (!libspdm_const_compare_mem(cert_basic_constraints, + basic_constraints_case2, + sizeof(basic_constraints_case2)))) { + return true; + } + + return false; +} + +/** + * Verify leaf cert extend spdm OID + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true verify pass + * @retval false verify fail,two case: 1. return is not RETURN_SUCCESS or RETURN_NOT_FOUND; + * 2. hardware_identity_oid is found in AliasCert model; + **/ +static bool libspdm_verify_leaf_cert_eku_spdm_OID(const uint8_t *cert, size_t cert_size, + bool is_device_cert_model) +{ + bool status; + bool find_sucessful; + uint8_t spdm_extension[SPDM_EXTENDSION_LEN]; + size_t index; + size_t len; + + /* SPDM defined OID */ + + uint8_t oid_spdm_extension[] = SPDM_OID_EXTENSION; + uint8_t hardware_identity_oid[] = SPDM_OID_HARDWARE_IDENTITY; + + len = SPDM_EXTENDSION_LEN; + + if (cert == NULL || cert_size == 0) { + return false; + } + + status = libspdm_x509_get_extension_data(cert, cert_size, + (const uint8_t *)oid_spdm_extension, + sizeof(oid_spdm_extension), + spdm_extension, + &len); + + if(len == 0) { + return true; + } else if(!status) { + return false; + } + + /*find the spdm hardware identity OID*/ + find_sucessful = false; + for(index = 0; index <= len - sizeof(hardware_identity_oid); index++) { + if (!libspdm_const_compare_mem(spdm_extension + index, hardware_identity_oid, + sizeof(hardware_identity_oid))) { + find_sucessful = true; + break; + } + } + + if ((find_sucessful) && (!is_device_cert_model)) { + /* Hardware_identity_OID is found in alias cert model */ + return false; + } else { + return true; + } +} + +/** + * Certificate Check for SPDM leaf cert. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in] base_hash_algo SPDM base_hash_algo + * @param[in] is_device_cert_model If true, the cert chain is DeviceCert model; + * If false, the cert chain is AliasCert model; + * + * @retval true Success. + * @retval false Certificate is not valid + **/ +bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo, + uint32_t base_hash_algo, + bool is_device_cert_model) +{ + uint8_t end_cert_from[64]; + size_t end_cert_from_len; + uint8_t end_cert_to[64]; + size_t end_cert_to_len; + size_t asn1_buffer_len; + bool status; + size_t cert_version; + size_t value; + void *context; + + if (cert == NULL || cert_size == 0) { + return false; + } + + status = true; + context = NULL; + end_cert_from_len = 64; + end_cert_to_len = 64; + + /* 1. version*/ + cert_version = 0; + status = libspdm_x509_get_version(cert, cert_size, &cert_version); + if (!status) { + goto cleanup; + } + if (cert_version != 2) { + status = false; + goto cleanup; + } + + /* 2. serial_number*/ + asn1_buffer_len = 0; + status = libspdm_x509_get_serial_number(cert, cert_size, NULL, &asn1_buffer_len); + if (asn1_buffer_len == 0) { + status = false; + goto cleanup; + } + + /* 3. Verify public key algorithm. */ + status = libspdm_verify_cert_subject_public_key_info(cert, cert_size, base_asym_algo); + if (!status) { + goto cleanup; + } + + /* 4. issuer_name*/ + asn1_buffer_len = 0; + status = libspdm_x509_get_issuer_name(cert, cert_size, NULL, &asn1_buffer_len); + if (asn1_buffer_len == 0) { + status = false; + goto cleanup; + } + + /* 5. subject_name*/ + asn1_buffer_len = 0; + status = libspdm_x509_get_subject_name(cert, cert_size, NULL, &asn1_buffer_len); + if (asn1_buffer_len == 0) { + status = false; + goto cleanup; + } + + /* 6. validaity*/ + status = libspdm_x509_get_validity(cert, cert_size, end_cert_from, + &end_cert_from_len, end_cert_to, + &end_cert_to_len); + if (!status) { + goto cleanup; + } + + status = libspdm_internal_x509_date_time_check( + end_cert_from, end_cert_from_len, end_cert_to, end_cert_to_len); + if (!status) { + goto cleanup; + } + + /* 7. subject_public_key*/ + status = libspdm_asym_get_public_key_from_x509(base_asym_algo, cert, cert_size, &context); + if (!status) { + goto cleanup; + } + + /* 8. key_usage*/ + value = 0; + status = libspdm_x509_get_key_usage(cert, cert_size, &value); + if (!status) { + goto cleanup; + } + if (LIBSPDM_CRYPTO_X509_KU_DIGITAL_SIGNATURE & value) { + status = true; + } else { + status = false; + goto cleanup; + } + + /* 9. verify SPDM extension OID*/ + status = libspdm_verify_leaf_cert_eku_spdm_OID(cert, cert_size, is_device_cert_model); + if (!status) { + goto cleanup; + } + + /* 10. verify basic constraints*/ + status = libspdm_verify_leaf_cert_basic_constraints(cert, cert_size); + if (!status) { + goto cleanup; + } + + /* 11. extended_key_usage*/ + value = 0; + status = libspdm_x509_get_extended_key_usage(cert, cert_size, NULL, &value); + if (value == 0) { + status = false; + goto cleanup; + } + status = true; + +cleanup: + libspdm_asym_free(base_asym_algo, context); + return status; +} + +/** + * Return certificate is root cert or not. + * Certificate is considered as a root certificate if the subjectname equal issuername. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true Certificate is self-signed. + * @retval false Certificate is not self-signed. + **/ +bool libspdm_is_root_certificate(const uint8_t *cert, size_t cert_size) +{ + uint8_t issuer_name[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; + size_t issuer_name_len; + uint8_t subject_name[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; + size_t subject_name_len; + bool result; + + if (cert == NULL || cert_size == 0) { + return false; + } + + /* 1. issuer_name*/ + issuer_name_len = LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE; + result = libspdm_x509_get_issuer_name(cert, cert_size, issuer_name, &issuer_name_len); + if (!result) { + return false; + } + + /* 2. subject_name*/ + subject_name_len = LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE; + result = libspdm_x509_get_subject_name(cert, cert_size, subject_name, &subject_name_len); + if (!result) { + return false; + } + + if (issuer_name_len != subject_name_len) { + return false; + } + if (libspdm_const_compare_mem(issuer_name, subject_name, issuer_name_len) != 0) { + return false; + } + + return true; +} + +/** + * Retrieve the SubjectAltName from SubjectAltName Bytes. + * + * @param[in] buffer Pointer to subjectAltName oct bytes. + * @param[in] len size of buffer in bytes. + * @param[out] name_buffer buffer to contain the retrieved certificate + * SubjectAltName. At most name_buffer_size bytes will be + * written. Maybe NULL in order to determine the size + * buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * @param[out] oid OID of otherName + * @param[in,out] oid_size the buffersize for required OID + * + * @retval true get the subjectAltName string successfully + * @retval failed get the subjectAltName string failed + **/ +bool libspdm_get_dmtf_subject_alt_name_from_bytes( + uint8_t *buffer, const size_t len, char *name_buffer, + size_t *name_buffer_size, uint8_t *oid, + size_t *oid_size) +{ + uint8_t *ptr; + int32_t length; + size_t obj_len; + int32_t ret; + + /*copy mem variable*/ + volatile uint8_t* dst; + const volatile uint8_t* src; + size_t dst_len; + size_t src_len; + + length = (int32_t)len; + ptr = buffer; + obj_len = 0; + + /* Sequence*/ + ret = libspdm_asn1_get_tag(&ptr, ptr + length, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + ret = libspdm_asn1_get_tag(&ptr, ptr + obj_len, &obj_len, + LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + + ret = libspdm_asn1_get_tag(&ptr, ptr + obj_len, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); + if (!ret) { + return false; + } + /* CopyData to OID*/ + if (*oid_size < (size_t)obj_len) { + *oid_size = (size_t)obj_len; + return false; + } + if (oid != NULL) { + libspdm_copy_mem(oid, *oid_size, ptr, obj_len); + *oid_size = obj_len; + } + + /* Move to next element*/ + ptr += obj_len; + + ret = libspdm_asn1_get_tag(&ptr, (uint8_t *)(buffer + length), &obj_len, + LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + ret = libspdm_asn1_get_tag(&ptr, (uint8_t *)(buffer + length), &obj_len, + LIBSPDM_CRYPTO_ASN1_UTF8_STRING); + if (!ret) { + return false; + } + + if (*name_buffer_size < (size_t)obj_len + 1) { + *name_buffer_size = (size_t)obj_len + 1; + return false; + } + + /* the src and dst adress are overlap, + * When the function is called by libspdm_get_dmtf_subject_alt_name. + * libspdm_copy_mem can not be uesed */ + if ((name_buffer != NULL) && (ptr != NULL)) { + dst = (volatile uint8_t*) name_buffer; + src = (const volatile uint8_t*) ptr; + dst_len = *name_buffer_size; + src_len = obj_len; + + /* Check for case where "dst_len" may be invalid. Do not zero "dst" in this case. */ + if (dst_len > (SIZE_MAX >> 1)) { + LIBSPDM_ASSERT(0); + return false; + } + + /* Guard against invalid lengths. Zero "dst" in these cases. */ + if (src_len > dst_len || + src_len > (SIZE_MAX >> 1)) { + libspdm_zero_mem(name_buffer, dst_len); + LIBSPDM_ASSERT(0); + return false; + } + + while (src_len-- != 0) { + *(dst++) = *(src++); + } + + /*encode name buffer to string*/ + *name_buffer_size = obj_len + 1; + name_buffer[obj_len] = 0; + return true; + } + + return false; +} + +/** + * Retrieve the SubjectAltName from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] name_buffer buffer to contain the retrieved certificate + * SubjectAltName. At most name_buffer_size bytes will be + * written. Maybe NULL in order to determine the size + * buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * @param[out] oid OID of otherName + * @param[in,out] oid_size the buffersize for required OID + * + * @retval true get the subjectAltName string successfully + * @retval failed get the subjectAltName string failed + **/ +bool libspdm_get_dmtf_subject_alt_name(const uint8_t *cert, const size_t cert_size, + char *name_buffer, + size_t *name_buffer_size, + uint8_t *oid, size_t *oid_size) +{ + bool status; + size_t extension_data_size; + uint8_t oid_subject_alt_name[] = { 0x55, 0x1D, 0x11 }; + + extension_data_size = 0; + status = libspdm_x509_get_extension_data(cert, cert_size, + oid_subject_alt_name, + sizeof(oid_subject_alt_name), NULL, + &extension_data_size); + if (status || (extension_data_size == 0)) { + *name_buffer_size = 0; + return false; + } + if (extension_data_size > *name_buffer_size) { + *name_buffer_size = extension_data_size; + return false; + } + status = + libspdm_x509_get_extension_data(cert, cert_size, + oid_subject_alt_name, + sizeof(oid_subject_alt_name), + (uint8_t *)name_buffer, name_buffer_size); + if (!status) { + return status; + } + + return libspdm_get_dmtf_subject_alt_name_from_bytes( + (uint8_t *)name_buffer, *name_buffer_size, name_buffer, + name_buffer_size, oid, oid_size); +} + +/** + * This function verifies the integrity of certificate chain data without spdm_cert_chain_t header. + * + * @param cert_chain_data The certificate chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size size in bytes of the certificate chain data. + * @param base_hash_algo SPDM base_hash_algo + * @param base_asym_algo SPDM base_asym_algo + * @param is_device_cert_model If true, the cert chain is DeviceCert model; + * If false, the cert chain is AliasCert model; + * + * @retval true certificate chain data integrity verification pass. + * @retval false certificate chain data integrity verification fail. + **/ +bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_data_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_device_cert_model) +{ + const uint8_t *root_cert_buffer; + size_t root_cert_buffer_size; + const uint8_t *leaf_cert_buffer; + size_t leaf_cert_buffer_size; + + if (cert_chain_data_size > + 0xFFFF - (sizeof(spdm_cert_chain_t) + LIBSPDM_MAX_HASH_SIZE)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (chain size too large) !!!\n")); + return false; + } + + if (!libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, 0, &root_cert_buffer, + &root_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (get root certificate failed)!!!\n")); + return false; + } + + if (!libspdm_x509_verify_cert_chain(root_cert_buffer, root_cert_buffer_size, + cert_chain_data, cert_chain_data_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (cert chain verify failed)!!!\n")); + return false; + } + + if (!libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, -1, + &leaf_cert_buffer, &leaf_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (get leaf certificate failed)!!!\n")); + return false; + } + + if (!libspdm_x509_certificate_check(leaf_cert_buffer, leaf_cert_buffer_size, + base_asym_algo, base_hash_algo, + is_device_cert_model)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainData - FAIL (leaf certificate check failed)!!!\n")); + return false; + } + + return true; +} + +bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t base_asym_algo, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + bool is_device_cert_model) +{ + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; + const uint8_t *first_cert_buffer; + size_t first_cert_buffer_size; + size_t hash_size; + uint8_t calc_root_cert_hash[LIBSPDM_MAX_HASH_SIZE]; + const uint8_t *leaf_cert_buffer; + size_t leaf_cert_buffer_size; + bool result; + const spdm_cert_chain_t *cert_chain_header; + + hash_size = libspdm_get_hash_size(base_hash_algo); + + if (cert_chain_buffer_size <= sizeof(spdm_cert_chain_t) + hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (buffer too small) !!!\n")); + return false; + } + + cert_chain_header = cert_chain_buffer; + if (cert_chain_header->length != cert_chain_buffer_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (cert_chain->length mismatch) !!!\n")); + return false; + } + + cert_chain_data = (const uint8_t *)cert_chain_buffer + sizeof(spdm_cert_chain_t) + hash_size; + cert_chain_data_size = cert_chain_buffer_size - sizeof(spdm_cert_chain_t) - hash_size; + if (!libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, 0, &first_cert_buffer, + &first_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (get root certificate failed)!!!\n")); + return false; + } + + if (libspdm_is_root_certificate(first_cert_buffer, first_cert_buffer_size)) { + result = libspdm_hash_all(base_hash_algo, first_cert_buffer, first_cert_buffer_size, + calc_root_cert_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (hash calculation fail) !!!\n")); + return false; + } + if (libspdm_const_compare_mem((const uint8_t *)cert_chain_buffer + + sizeof(spdm_cert_chain_t), + calc_root_cert_hash, hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (cert root hash mismatch) !!!\n")); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - PASS (cert root hash match) !!!\n")); + } + + /*If the number of certificates in the certificate chain is more than 1, + * other certificates need to be verified.*/ + if (cert_chain_data_size > first_cert_buffer_size) { + if (!libspdm_x509_verify_cert_chain(first_cert_buffer, first_cert_buffer_size, + cert_chain_data + first_cert_buffer_size, + cert_chain_data_size - first_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (cert chain verify failed)!!!\n")); + return false; + } + } + + if (!libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, -1, + &leaf_cert_buffer, &leaf_cert_buffer_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (get leaf certificate failed)!!!\n")); + return false; + } + + if (!libspdm_x509_certificate_check(leaf_cert_buffer, leaf_cert_buffer_size, + base_asym_algo, base_hash_algo, + is_device_cert_model)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "!!! VerifyCertificateChainBuffer - FAIL (leaf certificate check failed)!!!\n")); + return false; + } + + return true; +} + +bool libspdm_get_leaf_cert_public_key_from_cert_chain(uint32_t base_hash_algo, + uint32_t base_asym_alg, + uint8_t *cert_chain_data, + size_t cert_chain_data_size, + void **public_key) +{ + size_t hash_size; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + bool result; + + hash_size = libspdm_get_hash_size(base_hash_algo); + + cert_chain_data = cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; + cert_chain_data_size = cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); + + /* Get leaf cert from cert chain */ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + base_asym_alg, + cert_buffer, cert_buffer_size, public_key); + if (!result) { + return false; + } + + return true; +} + +bool libspdm_verify_req_info(uint8_t *req_info, uint16_t req_info_len) +{ + bool ret; + uint8_t *ptr; + int32_t length; + size_t obj_len; + uint8_t *end; + + length = (int32_t)req_info_len; + ptr = req_info; + obj_len = 0; + end = ptr + length; + ret = true; + + if (req_info_len == 0) { + return true; + } + + /*req_info sequence*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } + + /*integer:version*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_INTEGER); + if (!ret) { + return false; + } else { + ptr += obj_len; + } + + /*sequence:subject name*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } else { + ptr += obj_len; + } + + /*sequence:subject pkinfo*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (!ret) { + return false; + } else { + ptr += obj_len; + } + + /*[0]: attributes*/ + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + /*req_info format error, don't have attributes tag*/ + if (!ret) { + return false; + } + + /*there is no attributes object*/ + if (ptr == end) { + return true; + } + + /*there is some attributes object: 0,1,2 ...*/ + while (ret) + { + ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, + LIBSPDM_CRYPTO_ASN1_SEQUENCE | + LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); + if (ret) { + ptr += obj_len; + } else { + break; + } + } + + if (ptr == end) { + return true; + } else { + return false; + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c new file mode 100644 index 0000000000..72adf085c8 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c @@ -0,0 +1,270 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +/** + * This function returns the SPDM DHE algorithm key size. + * + * @param dhe_named_group SPDM dhe_named_group + * + * @return SPDM DHE algorithm key size. + **/ +uint32_t libspdm_get_dhe_pub_key_size(uint16_t dhe_named_group) +{ + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + return 256; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + return 384; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: + return 512; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + return 32 * 2; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + return 48 * 2; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: + return 66 * 2; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: + return 32 * 2; + default: + return 0; + } +} + +/** + * Return cipher ID, based upon the negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * + * @return DHE cipher ID + **/ +static size_t libspdm_get_dhe_nid(uint16_t dhe_named_group) +{ + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + return LIBSPDM_CRYPTO_NID_FFDHE2048; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + return LIBSPDM_CRYPTO_NID_FFDHE3072; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: + return LIBSPDM_CRYPTO_NID_FFDHE4096; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + return LIBSPDM_CRYPTO_NID_SECP256R1; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + return LIBSPDM_CRYPTO_NID_SECP384R1; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: + return LIBSPDM_CRYPTO_NID_SECP521R1; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: + return LIBSPDM_CRYPTO_NID_SM2_KEY_EXCHANGE_P256; + default: + return LIBSPDM_CRYPTO_NID_NULL; + } +} + +void *libspdm_dhe_new(spdm_version_number_t spdm_version, + uint16_t dhe_named_group, bool is_initiator) +{ + size_t nid; + void *context; + + nid = libspdm_get_dhe_nid(dhe_named_group); + if (nid == 0) { + return NULL; + } + + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_SUPPORT + context = libspdm_dh_new_by_nid(nid); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + break; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_SUPPORT + context = libspdm_ec_new_by_nid(nid); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + break; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + context = libspdm_sm2_key_exchange_new_by_nid(nid); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + break; + default: + LIBSPDM_ASSERT(false); + return NULL; + } + +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + if (dhe_named_group == SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256) { + bool result; + uint8_t spdm12_key_change_requester_context[ + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE]; + uint8_t spdm12_key_change_responder_context[ + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE]; + + libspdm_copy_mem(spdm12_key_change_requester_context, + sizeof(spdm12_key_change_requester_context), + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT, + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE); + libspdm_copy_mem(spdm12_key_change_responder_context, + sizeof(spdm12_key_change_responder_context), + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT, + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE); + /* patch the version*/ + spdm12_key_change_requester_context[25] = (char)('0' + ((spdm_version >> 12) & 0xF)); + spdm12_key_change_requester_context[27] = (char)('0' + ((spdm_version >> 8) & 0xF)); + spdm12_key_change_responder_context[25] = (char)('0' + ((spdm_version >> 12) & 0xF)); + spdm12_key_change_responder_context[27] = (char)('0' + ((spdm_version >> 8) & 0xF)); + + result = libspdm_sm2_key_exchange_init (context, LIBSPDM_CRYPTO_NID_SM3_256, + spdm12_key_change_requester_context, + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE, + spdm12_key_change_responder_context, + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE, + is_initiator); + if (!result) { + libspdm_sm2_key_exchange_free (context); + return NULL; + } + } +#endif /* LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT */ + + return context; +} + +void libspdm_dhe_free(uint16_t dhe_named_group, void *context) +{ + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_SUPPORT + libspdm_dh_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_SUPPORT + libspdm_ec_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + libspdm_sm2_key_exchange_free(context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + default: + LIBSPDM_ASSERT(false); + break; + } +} + +bool libspdm_dhe_generate_key(uint16_t dhe_named_group, void *context, + uint8_t *public_key, + size_t *public_key_size) +{ + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_SUPPORT + return libspdm_dh_generate_key(context, public_key, public_key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_SUPPORT + return libspdm_ec_generate_key(context, public_key, public_key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + return libspdm_sm2_key_exchange_generate_key(context, public_key, public_key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_dhe_compute_key(uint16_t dhe_named_group, void *context, + const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size) +{ +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + bool ret; +#endif + + switch (dhe_named_group) { + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_SUPPORT + return libspdm_dh_compute_key(context, peer_public, peer_public_size, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_SUPPORT + return libspdm_ec_compute_key(context, peer_public, peer_public_size, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT + ret = libspdm_sm2_key_exchange_compute_key(context, peer_public, + peer_public_size, key, key_size); + if (!ret) { + return false; + } else { + /* SM2 key exchange can generate arbitrary length key_size. + * SPDM requires SM2 key_size to be 16. */ + LIBSPDM_ASSERT (*key_size >= 16); + *key_size = 16; + + return true; + } +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c new file mode 100644 index 0000000000..e5a31fd599 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c @@ -0,0 +1,477 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +uint32_t libspdm_get_hash_size(uint32_t base_hash_algo) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: + return 32; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: + return 48; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: + return 64; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: + return 32; + default: + return 0; + } +} + +size_t libspdm_get_hash_nid(uint32_t base_hash_algo) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: + return LIBSPDM_CRYPTO_NID_SHA256; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: + return LIBSPDM_CRYPTO_NID_SHA384; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: + return LIBSPDM_CRYPTO_NID_SHA512; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: + return LIBSPDM_CRYPTO_NID_SHA3_256; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: + return LIBSPDM_CRYPTO_NID_SHA3_384; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: + return LIBSPDM_CRYPTO_NID_SHA3_512; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: + return LIBSPDM_CRYPTO_NID_SM3_256; + default: + return LIBSPDM_CRYPTO_NID_NULL; + } +} + +void *libspdm_hash_new(uint32_t base_hash_algo) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_new(); +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + default: + LIBSPDM_ASSERT(false); + return NULL; + } +} + +void libspdm_hash_free(uint32_t base_hash_algo, void *hash_context) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + libspdm_sha256_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + libspdm_sha384_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + libspdm_sha512_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + libspdm_sha3_256_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + libspdm_sha3_384_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + libspdm_sha3_512_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + libspdm_sm3_256_free(hash_context); +#else + LIBSPDM_ASSERT(false); +#endif + break; + default: + LIBSPDM_ASSERT(false); + break; + } +} + +bool libspdm_hash_init(uint32_t base_hash_algo, void *hash_context) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_init(hash_context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hash_duplicate(uint32_t base_hash_algo, const void *hash_ctx, void *new_hash_ctx) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_duplicate(hash_ctx, new_hash_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hash_update(uint32_t base_hash_algo, void *hash_context, + const void *data, size_t data_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_update(hash_context, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hash_final(uint32_t base_hash_algo, void *hash_context, uint8_t *hash_value) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_final(hash_context, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hash_all(uint32_t base_hash_algo, const void *data, + size_t data_size, uint8_t *hash_value) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_sha256_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_sha384_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_sha512_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_sha3_256_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_sha3_384_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_sha3_512_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_sm3_256_hash_all(data, data_size, hash_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +uint32_t libspdm_get_measurement_hash_size(uint32_t measurement_hash_algo) +{ + switch (measurement_hash_algo) { + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256: + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256: + return 32; + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384: + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384: + return 48; + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512: + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512: + return 64; + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SM3_256: + return 32; + case SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY: + return 0xFFFFFFFF; + default: + return 0; + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c new file mode 100644 index 0000000000..3f7b22b7c6 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c @@ -0,0 +1,127 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +bool libspdm_hkdf_extract(uint32_t base_hash_algo, const uint8_t *ikm, size_t ikm_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hkdf_sha256_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hkdf_sha384_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hkdf_sha512_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hkdf_sha3_256_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hkdf_sha3_384_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hkdf_sha3_512_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hkdf_sm3_256_extract(ikm, ikm_size, salt, salt_size, prk_out, prk_out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hkdf_expand(uint32_t base_hash_algo, const uint8_t *prk, + size_t prk_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hkdf_sha256_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hkdf_sha384_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hkdf_sha512_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hkdf_sha3_256_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hkdf_sha3_384_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hkdf_sha3_512_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hkdf_sm3_256_expand(prk, prk_size, info, info_size, out, out_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c new file mode 100644 index 0000000000..d68b52b55c --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c @@ -0,0 +1,419 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +void *libspdm_hmac_new(uint32_t base_hash_algo) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_new(); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +void libspdm_hmac_free(uint32_t base_hash_algo, void *hmac_ctx) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + libspdm_hmac_sha256_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + libspdm_hmac_sha384_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + libspdm_hmac_sha512_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + libspdm_hmac_sha3_256_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + libspdm_hmac_sha3_384_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + libspdm_hmac_sha3_512_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + libspdm_hmac_sm3_256_free(hmac_ctx); +#else + LIBSPDM_ASSERT(false); +#endif + break; + default: + LIBSPDM_ASSERT(false); + break; + } +} + +bool libspdm_hmac_init(uint32_t base_hash_algo, + void *hmac_ctx, const uint8_t *key, + size_t key_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_set_key(hmac_ctx, key, key_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hmac_duplicate(uint32_t base_hash_algo, const void *hmac_ctx, void *new_hmac_ctx) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_duplicate(hmac_ctx, new_hmac_ctx); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hmac_update(uint32_t base_hash_algo, + void *hmac_ctx, const void *data, + size_t data_size) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_update(hmac_ctx, data, data_size); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hmac_final(uint32_t base_hash_algo, void *hmac_ctx, uint8_t *hmac_value) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_final(hmac_ctx, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_hmac_all(uint32_t base_hash_algo, const void *data, + size_t data_size, const uint8_t *key, + size_t key_size, uint8_t *hmac_value) +{ + switch (base_hash_algo) { + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return libspdm_hmac_sha256_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return libspdm_hmac_sha384_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return libspdm_hmac_sha512_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT + return libspdm_hmac_sha3_256_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT + return libspdm_hmac_sha3_384_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT + return libspdm_hmac_sha3_512_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT + return libspdm_hmac_sm3_256_all(data, data_size, key, key_size, hmac_value); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c new file mode 100644 index 0000000000..4e35206705 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c @@ -0,0 +1,15 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_crypt_lib.h" + +bool libspdm_get_random_number(size_t size, uint8_t *rand) +{ + if (size == 0) { + return true; + } + return libspdm_random_bytes(rand, size); +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c new file mode 100644 index 0000000000..7400f2bd1b --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c @@ -0,0 +1,174 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context) +{ + uint16_t req_session_id; + libspdm_session_info_t *session_info; + size_t index; + + session_info = spdm_context->session_info; + for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { + if ((session_info[index].session_id & 0xFFFF) == (INVALID_SESSION_ID & 0xFFFF)) { + req_session_id = (uint16_t)(0xFFFF - index); + return req_session_id; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_allocate_req_session_id - MAX session_id\n")); + return (INVALID_SESSION_ID & 0xFFFF); +} + +libspdm_return_t libspdm_build_opaque_data_supported_version_data(libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out) +{ + size_t final_data_size; + secured_message_general_opaque_data_table_header_t + *general_opaque_data_table_header; + spdm_general_opaque_data_table_header_t + *spdm_general_opaque_data_table_header; + secured_message_opaque_element_table_header_t + *opaque_element_table_header; + secured_message_opaque_element_supported_version_t + *opaque_element_support_version; + spdm_version_number_t *versions_list; + void *end; + + if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { + *data_out_size = 0; + return LIBSPDM_STATUS_SUCCESS; + } + + final_data_size = libspdm_get_opaque_data_supported_version_data_size(spdm_context); + if (*data_out_size < final_data_size) { + *data_out_size = final_data_size; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { + spdm_general_opaque_data_table_header = data_out; + spdm_general_opaque_data_table_header->total_elements = 1; + libspdm_write_uint24(spdm_general_opaque_data_table_header->reserved, 0); + opaque_element_table_header = (void *)(spdm_general_opaque_data_table_header + 1); + } else { + general_opaque_data_table_header = data_out; + general_opaque_data_table_header->spec_id = SECURED_MESSAGE_OPAQUE_DATA_SPEC_ID; + general_opaque_data_table_header->opaque_version = SECURED_MESSAGE_OPAQUE_VERSION; + general_opaque_data_table_header->total_elements = 1; + general_opaque_data_table_header->reserved = 0; + opaque_element_table_header = (void *)(general_opaque_data_table_header + 1); + } + + opaque_element_table_header->id = SPDM_REGISTRY_ID_DMTF; + opaque_element_table_header->vendor_len = 0; + opaque_element_table_header->opaque_element_data_len = + sizeof(secured_message_opaque_element_supported_version_t) + + sizeof(spdm_version_number_t) * + spdm_context->local_context.secured_message_version.spdm_version_count; + + opaque_element_support_version = (void *)(opaque_element_table_header + 1); + opaque_element_support_version->sm_data_version = + SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_DATA_VERSION; + opaque_element_support_version->sm_data_id = + SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_SUPPORTED_VERSION; + opaque_element_support_version->version_count = + spdm_context->local_context.secured_message_version.spdm_version_count; + + versions_list = (void *)(opaque_element_support_version + 1); + libspdm_copy_mem(versions_list, + *data_out_size - ((uint8_t*)versions_list - (uint8_t*)data_out), + spdm_context->local_context.secured_message_version.spdm_version, + spdm_context->local_context.secured_message_version.spdm_version_count * + sizeof(spdm_version_number_t)); + + /* Zero Padding. *data_out_size does not need to be changed, because data is 0 padded */ + end = versions_list + spdm_context->local_context.secured_message_version.spdm_version_count; + libspdm_zero_mem(end, (size_t)data_out + final_data_size - (size_t)end); + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Process opaque data version selection. + * + * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE response parsing in requester. + * + * @param data_in_size size in bytes of the data_in. + * @param data_in A pointer to the buffer to store the opaque data version selection. + * + * @retval RETURN_SUCCESS The opaque data version selection is processed successfully. + * @retval RETURN_UNSUPPORTED The data_in is NOT opaque data version selection. + **/ +libspdm_return_t libspdm_process_opaque_data_version_selection_data(libspdm_context_t *spdm_context, + size_t data_in_size, + void *data_in) +{ + const secured_message_opaque_element_table_header_t + *opaque_element_table_header; + const secured_message_opaque_element_version_selection_t + *opaque_element_version_section; + + bool result; + uint8_t secured_message_version_index; + const void *get_element_ptr; + size_t get_element_len; + + result = false; + get_element_ptr = NULL; + + if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { + return LIBSPDM_STATUS_SUCCESS; + } + + result = libspdm_get_element_from_opaque_data( + spdm_context, data_in_size, + data_in, SPDM_REGISTRY_ID_DMTF, + SECURED_MESSAGE_OPAQUE_ELEMENT_SMDATA_ID_VERSION_SELECTION, + &get_element_ptr, &get_element_len); + if ((!result) || (get_element_ptr == NULL)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"get element error!\n")); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + opaque_element_table_header = (const secured_message_opaque_element_table_header_t*) + get_element_ptr; + + /*check for selection vesion data*/ + if ((opaque_element_table_header->vendor_len != 0) || + (opaque_element_table_header->opaque_element_data_len != + sizeof(secured_message_opaque_element_version_selection_t))) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + opaque_element_version_section = (const void *)(opaque_element_table_header + 1); + + if ((const uint8_t *)opaque_element_version_section + + sizeof(secured_message_opaque_element_version_selection_t) > + (const uint8_t *)opaque_element_table_header + get_element_len) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + for (secured_message_version_index = 0; + secured_message_version_index < + spdm_context->local_context.secured_message_version.spdm_version_count; + secured_message_version_index++) { + if (libspdm_get_version_from_version_number(opaque_element_version_section-> + selected_version) + == + libspdm_get_version_from_version_number( + spdm_context->local_context.secured_message_version.spdm_version[ + secured_message_version_index])) { + libspdm_copy_mem(&(spdm_context->connection_info.secured_message_version), + sizeof(spdm_context->connection_info.secured_message_version), + &(opaque_element_version_section->selected_version), + sizeof(spdm_version_number_t)); + return LIBSPDM_STATUS_SUCCESS; + } + } + + return LIBSPDM_STATUS_UNSUPPORTED_CAP; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c new file mode 100644 index 0000000000..f9f1fbbbe8 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c @@ -0,0 +1,368 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +libspdm_return_t libspdm_init_connection(void *context, bool get_version_only) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + + spdm_context = context; + + status = libspdm_get_version(spdm_context, NULL, NULL); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + + if (!get_version_only) { + status = libspdm_get_capabilities(spdm_context); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + status = libspdm_negotiate_algorithms(spdm_context); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + } + return LIBSPDM_STATUS_SUCCESS; +} + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +libspdm_return_t libspdm_start_session(void *context, bool use_psk, + uint8_t measurement_hash_type, + uint8_t slot_id, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + libspdm_session_info_t *session_info; + uint8_t req_slot_id_param; + #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + + spdm_context = context; + status = LIBSPDM_STATUS_UNSUPPORTED_CAP; + + if (!use_psk) { + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + status = libspdm_send_receive_key_exchange( + spdm_context, measurement_hash_type, slot_id, session_policy, + session_id, heartbeat_period, &req_slot_id_param, + measurement_hash); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_key_exchange - %p\n", + status)); + return status; + } + + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + switch (session_info->mut_auth_requested) { + case 0: + break; + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED: +#if !(LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; +#endif + break; + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST: + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS: +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) + status = libspdm_encapsulated_request( + spdm_context, session_id, + session_info->mut_auth_requested, + &req_slot_id_param); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_encapsulated_request - %p\n", status)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } +#else + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; +#endif + break; + default: + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unknown mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + if (req_slot_id_param == 0xF) { + req_slot_id_param = 0xFF; + } + status = libspdm_send_receive_finish(spdm_context, *session_id, req_slot_id_param); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_finish - %p\n", status)); + #else /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + } else { + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + status = libspdm_send_receive_psk_exchange( + spdm_context, measurement_hash_type, session_policy, session_id, + heartbeat_period, measurement_hash); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_psk_exchange - %p\n", + status)); + return status; + } + + /* send PSK_FINISH only if Responder supports context.*/ + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER_WITH_CONTEXT)) { + status = libspdm_send_receive_psk_finish(spdm_context, *session_id); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_psk_finish - %p\n", + status)); + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + } + return status; +} + +libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, + uint8_t measurement_hash_type, + uint8_t slot_id, + uint8_t session_policy, + uint32_t *session_id, + uint8_t *heartbeat_period, + void *measurement_hash, + const void *requester_random_in, + size_t requester_random_in_size, + void *requester_random, + size_t *requester_random_size, + void *responder_random, + size_t *responder_random_size) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + libspdm_session_info_t *session_info; + uint8_t req_slot_id_param; + #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + + spdm_context = context; + status = LIBSPDM_STATUS_UNSUPPORTED_CAP; + + if (!use_psk) { + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + LIBSPDM_ASSERT ( + requester_random_in_size == 0 || requester_random_in_size == SPDM_RANDOM_DATA_SIZE); + LIBSPDM_ASSERT ( + requester_random_size == NULL || *requester_random_size == SPDM_RANDOM_DATA_SIZE); + LIBSPDM_ASSERT ( + responder_random_size == NULL || *responder_random_size == SPDM_RANDOM_DATA_SIZE); + status = libspdm_send_receive_key_exchange_ex( + spdm_context, measurement_hash_type, slot_id, session_policy, + session_id, heartbeat_period, &req_slot_id_param, + measurement_hash, requester_random_in, + requester_random, responder_random); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_key_exchange - %p\n", + status)); + return status; + } + + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + switch (session_info->mut_auth_requested) { + case 0: + break; + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED: +#if !(LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; +#endif + break; + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST: + case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS: +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) + status = libspdm_encapsulated_request( + spdm_context, session_id, + session_info->mut_auth_requested, + &req_slot_id_param); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_encapsulated_request - %p\n", status)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } +#else + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; +#endif + break; + default: + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - unknown mut_auth_requested - 0x%x\n", + session_info->mut_auth_requested)); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + if (req_slot_id_param == 0xF) { + req_slot_id_param = 0xFF; + } + status = libspdm_send_receive_finish(spdm_context, *session_id, req_slot_id_param); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_finish - %p\n", status)); + #else /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ + } else { + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + status = libspdm_send_receive_psk_exchange_ex( + spdm_context, measurement_hash_type, session_policy, session_id, + heartbeat_period, measurement_hash, + requester_random_in, requester_random_in_size, + requester_random, requester_random_size, + responder_random, responder_random_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_psk_exchange - %p\n", + status)); + return status; + } + + /* send PSK_FINISH only if Responder supports context.*/ + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER_WITH_CONTEXT)) { + status = libspdm_send_receive_psk_finish(spdm_context, *session_id); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_start_session - libspdm_send_receive_psk_finish - %p\n", + status)); + } + #else /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + } + + return status; +} + +libspdm_return_t libspdm_stop_session(void *context, uint32_t session_id, + uint8_t end_session_attributes) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + + spdm_context = context; + + status = libspdm_send_receive_end_session(spdm_context, session_id, end_session_attributes); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_stop_session - %p\n", status)); + + return status; +} +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ + +libspdm_return_t libspdm_send_receive_data(void *context, const uint32_t *session_id, + bool is_app_message, + const void *request, size_t request_size, + void *response, + size_t *response_size) +{ + libspdm_return_t status; + libspdm_context_t *spdm_context; + spdm_message_header_t *spdm_request; + size_t spdm_request_size; + spdm_error_response_t *spdm_response; + size_t spdm_response_size; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + spdm_context = context; + spdm_response = response; + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + libspdm_copy_mem (spdm_request, spdm_request_size, request, request_size); + spdm_request_size = request_size; + + status = libspdm_send_request(spdm_context, session_id, is_app_message, + spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + status = libspdm_receive_response(spdm_context, session_id, is_app_message, + &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + return status; + } + + if (spdm_response->header.request_response_code == SPDM_ERROR) { + if ((spdm_response->header.param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) && + (session_id != NULL)) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } + } + + if (*response_size >= spdm_response_size) { + libspdm_copy_mem (response, *response_size, spdm_response, spdm_response_size); + *response_size = spdm_response_size; + } else { + *response_size = spdm_response_size; + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + + libspdm_release_receiver_buffer (spdm_context); + + return LIBSPDM_STATUS_SUCCESS; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c new file mode 100644 index 0000000000..643551e65d --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c @@ -0,0 +1,165 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t dummy_data[sizeof(spdm_error_data_response_not_ready_t)]; +} libspdm_end_session_response_mine_t; +#pragma pack() + +/** + * This function sends END_SESSION and receives END_SESSION_ACK for SPDM session end. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the END_SESSION request. + * @param end_session_attributes end_session_attributes to the END_SESSION_ACK request. + * + * @retval RETURN_SUCCESS The END_SESSION is sent and the END_SESSION_ACK is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +static libspdm_return_t libspdm_try_send_receive_end_session(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t end_session_attributes) +{ + libspdm_return_t status; + spdm_end_session_request_t *spdm_request; + size_t spdm_request_size; + libspdm_end_session_response_mine_t *spdm_response; + size_t spdm_response_size; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP)) { + end_session_attributes = 0; + } + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_END_SESSION; + spdm_request->header.param1 = end_session_attributes; + spdm_request->header.param2 = 0; + + spdm_request_size = sizeof(spdm_end_session_request_t); + status = libspdm_send_spdm_request(spdm_context, &session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_END_SESSION); + + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, &session_id, &spdm_response_size, + (void **)&spdm_response, SPDM_END_SESSION, SPDM_END_SESSION_ACK, + sizeof(libspdm_end_session_response_mine_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_END_SESSION_ACK) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size != sizeof(spdm_end_session_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + session_info->end_session_attributes = end_session_attributes; + + libspdm_secured_message_set_session_state( + session_info->secured_message_context, + LIBSPDM_SESSION_STATE_NOT_STARTED); + libspdm_free_session_id(spdm_context, session_id); + + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_send_receive_end_session(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t end_session_attributes) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_send_receive_end_session( + spdm_context, session_id, end_session_attributes); + if (LIBSPDM_STATUS_BUSY_PEER != status) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c new file mode 100644 index 0000000000..f6e4f9f9cd --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c @@ -0,0 +1,576 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t signature[LIBSPDM_MAX_ASYM_KEY_SIZE]; + uint8_t verify_data[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_finish_request_mine_t; + +typedef struct { + spdm_message_header_t header; + uint8_t verify_data[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_finish_response_mine_t; +#pragma pack() + +bool libspdm_verify_finish_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *hmac_data, size_t hmac_data_size) +{ + size_t hash_size; + uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; +#endif + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + LIBSPDM_ASSERT(hash_size == hmac_data_size); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + if (session_info->mut_auth_requested) { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return false; + } + } else { + mut_cert_chain_buffer = NULL; + mut_cert_chain_buffer_size = 0; + } + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, mut_cert_chain_buffer, + mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_response_finished_key( + session_info->secured_message_context, hash_data, + hash_size, calc_hmac_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hmac_for_finish_rsp( + spdm_context, session_info, &hash_size, calc_hmac_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hmac - ")); + LIBSPDM_INTERNAL_DUMP_DATA(calc_hmac_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + if (libspdm_const_compare_mem(calc_hmac_data, hmac_data, hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_finish_rsp_hmac - FAIL !!!\n")); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_finish_rsp_hmac - PASS !!!\n")); + + return true; +} + +bool libspdm_generate_finish_req_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + void *hmac) +{ + size_t hash_size; + uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; +#endif + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + if (session_info->mut_auth_requested) { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return false; + } + } else { + mut_cert_chain_buffer = NULL; + mut_cert_chain_buffer_size = 0; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, mut_cert_chain_buffer, + mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_request_finished_key( + session_info->secured_message_context, hash_data, + hash_size, calc_hmac_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hmac_for_finish_req( + spdm_context, session_info, &hash_size, calc_hmac_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hmac - ")); + LIBSPDM_INTERNAL_DUMP_DATA(calc_hmac_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + libspdm_copy_mem(hmac, hash_size, calc_hmac_data, hash_size); + + return true; +} + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + +bool libspdm_generate_finish_req_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + uint8_t *signature) +{ + bool result; + size_t signature_size; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t *mut_cert_chain_buffer; + size_t mut_cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; +#endif +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + size_t hash_size; +#endif +#if ((LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) && (LIBSPDM_DEBUG_BLOCK_ENABLE)) || \ + !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; +#endif + + signature_size = libspdm_get_req_asym_signature_size( + spdm_context->connection_info.algorithm.req_base_asym_alg); + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + result = libspdm_get_local_cert_chain_buffer(spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + if (!result) { + return false; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, mut_cert_chain_buffer, + mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + /* Debug code only - required for debug print of th_curr below*/ + LIBSPDM_DEBUG_CODE( + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data)) { + return false; + } + ); +#else + result = libspdm_calculate_th_hash_for_finish( + spdm_context, session_info, &hash_size, hash_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_requester_data_sign( + spdm_context->connection_info.version, SPDM_FINISH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + false, th_curr_data, th_curr_data_size, signature, &signature_size); +#else + result = libspdm_requester_data_sign( + spdm_context->connection_info.version, SPDM_FINISH, + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->connection_info.algorithm.base_hash_algo, + true, hash_data, hash_size, signature, &signature_size); +#endif + if (result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "signature - ")); + LIBSPDM_INTERNAL_DUMP_DATA(signature, signature_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + return result; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + +/** + * This function sends FINISH and receives FINISH_RSP for SPDM finish. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id session_id to the FINISH request. + * @param req_slot_id_param req_slot_id_param to the FINISH request. + * + * @retval RETURN_SUCCESS The FINISH is sent and the FINISH_RSP is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t req_slot_id_param) +{ + libspdm_return_t status; + libspdm_finish_request_mine_t *spdm_request; + size_t spdm_request_size; + size_t signature_size; + size_t hmac_size; + libspdm_finish_response_mine_t *spdm_response; + size_t spdm_response_size; + libspdm_session_info_t *session_info; + uint8_t *ptr; + bool result; + uint8_t th2_hash_data[LIBSPDM_MAX_HASH_SIZE]; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* -=[Check Parameters Phase]=- */ + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + status = LIBSPDM_STATUS_INVALID_PARAMETER; + goto error; + } + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP)) { + status = LIBSPDM_STATUS_UNSUPPORTED_CAP; + goto error; + } + + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto error; + } + + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_HANDSHAKING) { + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto error; + } + if (session_info->mut_auth_requested != 0) { + if ((req_slot_id_param >= SPDM_MAX_SLOT_COUNT) && (req_slot_id_param != 0xFF)) { + status = LIBSPDM_STATUS_INVALID_PARAMETER; + goto error; + } + } else { + if (req_slot_id_param != 0) { + status = LIBSPDM_STATUS_INVALID_PARAMETER; + goto error; + } + } + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto error; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_FINISH; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + signature_size = 0; +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + if (session_info->mut_auth_requested) { + spdm_request->header.param1 = SPDM_FINISH_REQUEST_ATTRIBUTES_SIGNATURE_INCLUDED; + spdm_request->header.param2 = req_slot_id_param; + signature_size = libspdm_get_req_asym_signature_size( + spdm_context->connection_info.algorithm.req_base_asym_alg); + } +#endif + + if (req_slot_id_param == 0xFF) { + req_slot_id_param = spdm_context->local_context.provisioned_slot_id; + } + + if (session_info->mut_auth_requested) { + LIBSPDM_ASSERT(req_slot_id_param < SPDM_MAX_SLOT_COUNT); + spdm_context->connection_info.local_used_cert_chain_buffer = + spdm_context->local_context.local_cert_chain_provision[req_slot_id_param]; + spdm_context->connection_info.local_used_cert_chain_buffer_size = + spdm_context->local_context.local_cert_chain_provision_size[req_slot_id_param]; + } + + hmac_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + spdm_request_size = sizeof(spdm_finish_request_t) + signature_size + hmac_size; + ptr = spdm_request->signature; + + status = libspdm_append_message_f(spdm_context, session_info, true, (uint8_t *)spdm_request, + sizeof(spdm_finish_request_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto error; + } +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + if (session_info->mut_auth_requested) { + result = libspdm_generate_finish_req_signature(spdm_context, session_info, ptr); + if (!result) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto error; + } + status = libspdm_append_message_f(spdm_context, session_info, true, ptr, signature_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto error; + } + ptr += signature_size; + } +#endif + + result = libspdm_generate_finish_req_hmac(spdm_context, session_info, ptr); + if (!result) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto error; + } + + status = libspdm_append_message_f(spdm_context, session_info, true, ptr, hmac_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto error; + } + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, &session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + goto error; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_FINISH); + + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto error; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + if (spdm_response->header.param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) { + status = LIBSPDM_STATUS_SESSION_MSG_ERROR; + goto receive_done; + } + if (spdm_response->header.param1 != SPDM_ERROR_CODE_RESPONSE_NOT_READY) { + libspdm_reset_message_f (spdm_context, session_info); + } + status = libspdm_handle_error_response_main( + spdm_context, &session_id, + &spdm_response_size, (void **)&spdm_response, + SPDM_FINISH, SPDM_FINISH_RSP, + sizeof(libspdm_finish_response_mine_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_FINISH_RSP) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + hmac_size = 0; + } + + if (spdm_response_size != sizeof(spdm_finish_response_t) + hmac_size) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + status = libspdm_append_message_f(spdm_context, session_info, true, spdm_response, + sizeof(spdm_finish_response_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "verify_data (0x%x):\n", hmac_size)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->verify_data, hmac_size); + result = libspdm_verify_finish_rsp_hmac(spdm_context, session_info, + spdm_response->verify_data, + hmac_size); + if (!result) { + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + + status = libspdm_append_message_f( + spdm_context, session_info, true, + (uint8_t *)spdm_response + + sizeof(spdm_finish_response_t), + hmac_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + } + + /* -=[Process Response Phase]=- */ + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_generate_session_data_key[%x]\n", session_id)); + result = libspdm_calculate_th2_hash(spdm_context, session_info, true, th2_hash_data); + if (!result) { + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; + } + result = libspdm_generate_session_data_key( + session_info->secured_message_context, th2_hash_data); + if (!result) { + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; + } + + /* -=[Update State Phase]=- */ + libspdm_secured_message_set_session_state( + session_info->secured_message_context, LIBSPDM_SESSION_STATE_ESTABLISHED); + + libspdm_release_receiver_buffer (spdm_context); + + return LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); +error: + if (status != LIBSPDM_STATUS_BUSY_PEER) { + libspdm_free_session_id(spdm_context, session_id); + } + + return status; +} + +libspdm_return_t libspdm_send_receive_finish(libspdm_context_t *spdm_context, + uint32_t session_id, + uint8_t req_slot_id_param) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_send_receive_finish(spdm_context, session_id, + req_slot_id_param); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c new file mode 100644 index 0000000000..a4722955d9 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c @@ -0,0 +1,337 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +/** + * This function validates the Responder's capabilities. + * + * @param capabilities_flag The Responder's CAPABILITIES.Flags field. + * @param version The SPDM message version. + * + * @retval true The field is valid. + * @retval false The field is invalid. + **/ +static bool validate_responder_capability(uint32_t capabilities_flag, uint8_t version) +{ + /*uint8_t cache_cap = (uint8_t)(capabilities_flag)&0x01;*/ + const uint8_t cert_cap = (uint8_t)(capabilities_flag >> 1) & 0x01; + const uint8_t chal_cap = (uint8_t)(capabilities_flag >> 2) & 0x01; + const uint8_t meas_cap = (uint8_t)(capabilities_flag >> 3) & 0x03; + const uint8_t meas_fresh_cap = (uint8_t)(capabilities_flag >> 5) & 0x01; + const uint8_t encrypt_cap = (uint8_t)(capabilities_flag >> 6) & 0x01; + const uint8_t mac_cap = (uint8_t)(capabilities_flag >> 7) & 0x01; + const uint8_t mut_auth_cap = (uint8_t)(capabilities_flag >> 8) & 0x01; + const uint8_t key_ex_cap = (uint8_t)(capabilities_flag >> 9) & 0x01; + const uint8_t psk_cap = (uint8_t)(capabilities_flag >> 10) & 0x03; + const uint8_t encap_cap = (uint8_t)(capabilities_flag >> 12) & 0x01; + const uint8_t hbeat_cap = (uint8_t)(capabilities_flag >> 13) & 0x01; + const uint8_t key_upd_cap = (uint8_t)(capabilities_flag >> 14) & 0x01; + const uint8_t handshake_in_the_clear_cap = (uint8_t)(capabilities_flag >> 15) & 0x01; + const uint8_t pub_key_id_cap = (uint8_t)(capabilities_flag >> 16) & 0x01; + /* uint8_t chunk_cap = (uint8_t)(capabilities_flag >> 17) & 0x01; */ + const uint8_t alias_cert_cap = (uint8_t)(capabilities_flag >> 18) & 0x01; + const uint8_t set_cert_cap = (uint8_t)(capabilities_flag >> 19) & 0x01; + const uint8_t csr_cap = (uint8_t)(capabilities_flag >> 20) & 0x01; + const uint8_t cert_install_reset_cap = (uint8_t)(capabilities_flag >> 21) & 0x01; + + /* Checks common to all SPDM versions. */ + + /* Illegal to return reserved value. */ + if (meas_cap == 3) { + return false; + } + + /* If MEAS_FRESH_CAP is set then MEAS_CAP must be set. */ + if ((meas_cap == 0) && (meas_fresh_cap == 1)) { + return false; + } + + if (version == SPDM_MESSAGE_VERSION_10) { + /* If measurements are not signed then CERT_CAP must equal CHAL_CAP. + * If measurements are signed then CERT_CAP must be set. */ + if ((meas_cap == 0) || (meas_cap == 1)) { + if (cert_cap != chal_cap) { + return false; + } + } else if (meas_cap == 2) { + if (cert_cap == 0) { + return false; + } + } + return true; + } + + /* Checks common to 1.1 and 1.2. */ + if ((version == SPDM_MESSAGE_VERSION_11) || (version == SPDM_MESSAGE_VERSION_12)) { + /* Illegal to return reserved values. */ + if (psk_cap == 3) { + return false; + } + + /* Checks that originate from key exchange capabilities. */ + if ((key_ex_cap == 1) || (psk_cap != 0)) { + if ((mac_cap == 0) && (encrypt_cap == 0)) { + return false; + } + } else { + if ((mac_cap == 1) || (encrypt_cap == 1) || (handshake_in_the_clear_cap == 1) || + (hbeat_cap == 1) || (key_upd_cap == 1)) { + return false; + } + } + if ((key_ex_cap == 0) && (psk_cap != 0)) { + if (handshake_in_the_clear_cap == 1) { + return false; + } + } + + /* Checks that originate from certificate or public key capabilities. */ + if ((cert_cap == 1) || (pub_key_id_cap == 1)) { + /* Certificate capabilities and public key capabilities cannot both be set. */ + if ((cert_cap == 1) && (pub_key_id_cap == 1)) { + return false; + } + if ((chal_cap == 0) && (key_ex_cap == 0) && ((meas_cap == 0) || (meas_cap == 1))) { + return false; + } + } else { + /* If certificates or public keys are not enabled then these capabilities + * cannot be enabled. */ + if ((chal_cap == 1) || (key_ex_cap == 1) || (meas_cap == 2) || (mut_auth_cap == 1)) { + return false; + } + } + } + + /* Checks specific to 1.1. */ + if (version == SPDM_MESSAGE_VERSION_11) { + if ((mut_auth_cap == 1) && (encap_cap == 0)) { + return false; + } + } + + /* Checks specific to 1.2. */ + if (version == SPDM_MESSAGE_VERSION_12) { + if ((cert_cap == 0) && ((alias_cert_cap == 1) || (set_cert_cap == 1))) { + return false; + } + if ((csr_cap == 1) && (set_cert_cap == 0)) { + return false; + } + if ((cert_install_reset_cap == 1) && (csr_cap == 0) && (set_cert_cap == 0)) { + return false; + } + } + + return true; +} + +/** + * This function sends GET_CAPABILITIES and receives CAPABILITIES. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_CAPABILITIES was sent and CAPABILITIES was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_CAPABILITIES due to Requester's state. Send GET_VERSION first. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the CAPABILITIES response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The CAPABILITIES response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + **/ +static libspdm_return_t libspdm_try_get_capabilities(libspdm_context_t *spdm_context) +{ + libspdm_return_t status; + spdm_get_capabilities_request_t *spdm_request; + size_t spdm_request_size; + spdm_capabilities_response_t *spdm_response; + size_t spdm_response_size; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* -=[Verify State Phase]=- */ + if (spdm_context->connection_info.connection_state != LIBSPDM_CONNECTION_STATE_AFTER_VERSION) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_CAPABILITIES); + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + + libspdm_zero_mem(spdm_request, sizeof(spdm_get_capabilities_request_t)); + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_request_size = sizeof(spdm_get_capabilities_request_t); + } else if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + spdm_request_size = sizeof(spdm_get_capabilities_request_t) - + sizeof(spdm_request->data_transfer_size) - + sizeof(spdm_request->max_spdm_msg_size); + } else { + spdm_request_size = sizeof(spdm_request->header); + } + spdm_request->header.request_response_code = SPDM_GET_CAPABILITIES; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + spdm_request->ct_exponent = spdm_context->local_context.capability.ct_exponent; + spdm_request->flags = spdm_context->local_context.capability.flags; + spdm_request->data_transfer_size = spdm_context->local_context.capability.data_transfer_size; + spdm_request->max_spdm_msg_size = spdm_context->local_context.capability.max_spdm_msg_size; + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, NULL, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response(spdm_context, NULL, &spdm_response_size, + (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response( + spdm_context, spdm_response->header.param1); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_CAPABILITIES) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if (spdm_response_size < sizeof(spdm_capabilities_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + } else { + if (spdm_response_size < sizeof(spdm_capabilities_response_t) - + sizeof(spdm_response->data_transfer_size) - sizeof(spdm_response->max_spdm_msg_size)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + } + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_response_size = sizeof(spdm_capabilities_response_t); + } else { + spdm_response_size = sizeof(spdm_capabilities_response_t) - + sizeof(spdm_response->data_transfer_size) - + sizeof(spdm_response->max_spdm_msg_size); + } + + if (!validate_responder_capability(spdm_response->flags, spdm_response->header.spdm_version)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if ((spdm_response->data_transfer_size < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) || + (spdm_response->data_transfer_size > spdm_response->max_spdm_msg_size)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + if (((spdm_response->flags & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP) == 0) && + (spdm_response->data_transfer_size != spdm_response->max_spdm_msg_size)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_a(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_a(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + spdm_context->connection_info.capability.ct_exponent = spdm_response->ct_exponent; + spdm_context->connection_info.capability.flags = spdm_response->flags; + + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_context->connection_info.capability.data_transfer_size = + spdm_response->data_transfer_size; + spdm_context->connection_info.capability.max_spdm_msg_size = + spdm_response->max_spdm_msg_size; + } else { + spdm_context->connection_info.capability.data_transfer_size = 0; + spdm_context->connection_info.capability.max_spdm_msg_size = 0; + } + + /* -=[Update State Phase]=- */ + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_AFTER_CAPABILITIES; + status = LIBSPDM_STATUS_SUCCESS; + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_get_capabilities(libspdm_context_t *spdm_context) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = false; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_capabilities(spdm_context); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c new file mode 100644 index 0000000000..e1feb22038 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c @@ -0,0 +1,511 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP + +// NVIDIA_EDIT: Include malloclib for dynamic allocation. +#include "library/malloclib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint16_t portion_length; + uint16_t remainder_length; + uint8_t cert_chain[LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN]; +} libspdm_certificate_response_max_t; +#pragma pack() + +/** + * This function sends GET_CERTIFICATE and receives CERTIFICATE. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param slot_id The number of slot for the certificate chain. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store + * the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer + * certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_CERTIFICATE was sent and CERTIFICATE was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_CERTIFICATE due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_CERTIFICATE because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the CERTIFICATE response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The CERTIFICATE response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * Verification of the certificate chain failed. + * @retval LIBSPDM_STATUS_INVALID_CERT + * The certificate is unable to be parsed or contains invalid field values. + * @retval LIBSPDM_STATUS_CRYPTO_ERROR + * A generic cryptography error occurred. + **/ +static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_t *session_id, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + bool result; + libspdm_return_t status; + spdm_get_certificate_request_t *spdm_request; + size_t spdm_request_size; + libspdm_certificate_response_max_t *spdm_response; + size_t spdm_response_size; + libspdm_large_managed_buffer_t *certificate_chain_buffer; + libspdm_context_t *spdm_context; + uint16_t total_responder_cert_chain_buffer_length; + size_t cert_chain_capacity; + uint16_t remainder_length; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + bool chunk_enabled; + + // + // NVIDIA_EDIT: To avoid massive stack usage, changed the certificate buffer from + // allocation on stack to dynamic memory. Changed return patterns where + // necessary to ensure memory is freed. + // + certificate_chain_buffer = (libspdm_large_managed_buffer_t *) + allocate_zero_pool(sizeof(libspdm_large_managed_buffer_t)); + if (certificate_chain_buffer == NULL) { + return LIBSPDM_STATUS_BUFFER_FULL; + } + + /* -=[Check Parameters Phase]=- */ + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + + /* -=[Verify State Phase]=- */ + spdm_context = context; + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP)) { + status = LIBSPDM_STATUS_UNSUPPORTED_CAP; + goto done; + } + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto done; + } + + session_info = NULL; + if (session_id != NULL) { + session_info = libspdm_get_session_info_via_session_id( + spdm_context, *session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto done; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; + goto done; + } + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_GET_CERTIFICATE); + + libspdm_init_managed_buffer(certificate_chain_buffer, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + + chunk_enabled = + libspdm_is_capabilities_flag_supported(spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP); + + if (chunk_enabled) { + length = 0xffff; + } else { + length = LIBSPDM_MIN(length, LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN); + } + + remainder_length = 0; + total_responder_cert_chain_buffer_length = 0; + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + + do { + /* -=[Construct Request Phase]=- */ + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto done; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_GET_CERTIFICATE; + spdm_request->header.param1 = slot_id; + spdm_request->header.param2 = 0; + spdm_request->offset = (uint16_t)libspdm_get_managed_buffer_size(certificate_chain_buffer); + if (spdm_request->offset == 0) { + spdm_request->length = length; + } else { + spdm_request->length = LIBSPDM_MIN(length, remainder_length); + } + spdm_request_size = sizeof(spdm_get_certificate_request_t); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "request (offset 0x%x, size 0x%x):\n", + spdm_request->offset, spdm_request->length)); + + /* -=[Send Request Phase]=- */ + status = + libspdm_send_spdm_request(spdm_context, session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + status = LIBSPDM_STATUS_SEND_FAIL; + goto done; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto done; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response(spdm_context, session_id, + &spdm_response_size, + (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_RECEIVE_FAIL; + goto done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, session_id, + &spdm_response_size, + (void **)&spdm_response, SPDM_GET_CERTIFICATE, + SPDM_CERTIFICATE, + sizeof(libspdm_certificate_response_max_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + goto done; + } + } else if (spdm_response->header.request_response_code != + SPDM_CERTIFICATE) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (spdm_response_size < sizeof(spdm_certificate_response_t)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto done; + } + if ((spdm_response->portion_length > spdm_request->length) || + (spdm_response->portion_length == 0)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if ((spdm_response->header.param1 & SPDM_CERTIFICATE_RESPONSE_SLOT_ID_MASK) != slot_id) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (spdm_response_size < sizeof(spdm_certificate_response_t) + + spdm_response->portion_length) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto done; + } + if (spdm_request->offset == 0) { + total_responder_cert_chain_buffer_length = spdm_response->portion_length + + spdm_response->remainder_length; + } else if (spdm_request->offset + spdm_response->portion_length + + spdm_response->remainder_length != total_responder_cert_chain_buffer_length) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (chunk_enabled && (spdm_response->remainder_length != 0)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + + /* -=[Process Response Phase]=- */ + remainder_length = spdm_response->remainder_length; + spdm_response_size = sizeof(spdm_certificate_response_t) + spdm_response->portion_length; + + if (session_id == NULL) { + status = libspdm_append_message_b(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto done; + } + status = libspdm_append_message_b(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto done; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Certificate (offset 0x%x, size 0x%x):\n", + spdm_request->offset, spdm_response->portion_length)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->cert_chain, spdm_response->portion_length); + + status = libspdm_append_managed_buffer(certificate_chain_buffer, + spdm_response->cert_chain, + spdm_response->portion_length); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto done; + } + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE) { + spdm_context->connection_info.connection_state = + LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE; + } + + libspdm_release_receiver_buffer (spdm_context); + } while (remainder_length != 0); + + if (spdm_context->local_context.verify_peer_spdm_cert_chain != NULL) { + result = spdm_context->local_context.verify_peer_spdm_cert_chain ( + spdm_context, slot_id, libspdm_get_managed_buffer_size(certificate_chain_buffer), + libspdm_get_managed_buffer(certificate_chain_buffer), + trust_anchor, trust_anchor_size); + if (!result) { + status = LIBSPDM_STATUS_VERIF_FAIL; + goto done; + } + } else { + result = libspdm_verify_peer_cert_chain_buffer( + spdm_context, libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer), + trust_anchor, trust_anchor_size, true); + if (!result) { + status = LIBSPDM_STATUS_VERIF_FAIL; + goto done; + } + } + + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size = + libspdm_get_managed_buffer_size(certificate_chain_buffer); + libspdm_copy_mem(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer, + sizeof(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer), + libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer)); +#else + result = libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer), + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash); + if (!result) { + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto done; + } + + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size = + libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + result = libspdm_get_leaf_cert_public_key_from_cert_chain( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.base_asym_algo, + libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer), + &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + if (!result) { + status = LIBSPDM_STATUS_INVALID_CERT; + goto done; + } +#endif + + if (cert_chain_size != NULL) { + if (*cert_chain_size < + libspdm_get_managed_buffer_size(certificate_chain_buffer)) { + *cert_chain_size = libspdm_get_managed_buffer_size( + certificate_chain_buffer); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto done; + } + cert_chain_capacity = *cert_chain_size; + *cert_chain_size = libspdm_get_managed_buffer_size(certificate_chain_buffer); + if (cert_chain != NULL) { + libspdm_copy_mem(cert_chain, + cert_chain_capacity, + libspdm_get_managed_buffer(certificate_chain_buffer), + libspdm_get_managed_buffer_size(certificate_chain_buffer)); + } + } + + status = LIBSPDM_STATUS_SUCCESS; +done: + free_pool(certificate_chain_buffer); + + return status; +} + +libspdm_return_t libspdm_get_certificate(void *context, uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain) +{ + return libspdm_get_certificate_choose_length(context, slot_id, + LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, + cert_chain_size, cert_chain); +} + +libspdm_return_t libspdm_get_certificate_ex(void *context, uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + return libspdm_get_certificate_choose_length_ex(context, slot_id, + LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, + cert_chain_size, cert_chain, + trust_anchor, trust_anchor_size); +} + +libspdm_return_t libspdm_get_certificate_in_session(void *context, const uint32_t *session_id, + uint8_t slot_id, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + return libspdm_get_certificate_choose_length_in_session(context, + session_id, + slot_id, + LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, + cert_chain_size, cert_chain, + trust_anchor, trust_anchor_size); +} + +libspdm_return_t libspdm_get_certificate_choose_length(void *context, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_certificate(spdm_context, NULL, slot_id, length, + cert_chain_size, cert_chain, NULL, NULL); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_get_certificate_choose_length_ex(void *context, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_certificate(spdm_context, NULL, slot_id, length, + cert_chain_size, cert_chain, trust_anchor, + trust_anchor_size); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_get_certificate_choose_length_in_session(void *context, + const uint32_t *session_id, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_certificate(spdm_context, session_id, slot_id, length, + cert_chain_size, cert_chain, trust_anchor, + trust_anchor_size); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c new file mode 100644 index 0000000000..0a307b02a4 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c @@ -0,0 +1,273 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t digest[LIBSPDM_MAX_HASH_SIZE * SPDM_MAX_SLOT_COUNT]; +} libspdm_digests_response_max_t; +#pragma pack() + +/** + * This function sends GET_DIGESTS and receives DIGESTS * + * + * @param context A pointer to the SPDM context. + * @param slot_mask Bitmask of the slots that contain certificates. + * @param total_digest_buffer A pointer to a destination buffer to store the digests. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_DIGETS was sent and DIGESTS was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_DIGESTS due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_DIGESTS because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the DIGESTS response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The DIGESTS response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * The digest of the stored certificate chain does not match the digest returned by + * the Responder. + * Note: This return value may be removed in the future. + **/ +static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *session_id, + uint8_t *slot_mask, + void *total_digest_buffer) +{ + bool result; + libspdm_return_t status; + spdm_get_digest_request_t *spdm_request; + size_t spdm_request_size; + libspdm_digests_response_max_t *spdm_response; + size_t spdm_response_size; + size_t digest_size; + size_t digest_count; + size_t index; + libspdm_context_t *spdm_context; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + + spdm_context = context; + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + session_info = NULL; + if (session_id != NULL) { + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_GET_DIGESTS); + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_GET_DIGESTS; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + spdm_request_size = sizeof(spdm_get_digest_request_t); + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, session_id, + &spdm_response_size, + (void **)&spdm_response, SPDM_GET_DIGESTS, SPDM_DIGESTS, + sizeof(libspdm_digests_response_max_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_DIGESTS) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_digest_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + digest_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + if (slot_mask != NULL) { + *slot_mask = spdm_response->header.param2; + } + + digest_count = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (spdm_response->header.param2 & (1 << index)) { + digest_count++; + } + } + if (digest_count == 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + if (spdm_response_size < sizeof(spdm_digest_response_t) + digest_count * digest_size) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + spdm_response_size = sizeof(spdm_digest_response_t) + digest_count * digest_size; + + /* -=[Process Response Phase]=- */ + if (session_id == NULL) { + status = libspdm_append_message_b(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_b(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + } + + for (index = 0; index < digest_count; index++) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "digest (0x%x) - ", index)); + LIBSPDM_INTERNAL_DUMP_DATA(&spdm_response->digest[digest_size * index], digest_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + result = libspdm_verify_peer_digests(spdm_context, spdm_response->digest, digest_count); + if (!result) { + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + + if (total_digest_buffer != NULL) { + libspdm_copy_mem(total_digest_buffer, digest_size * digest_count, + spdm_response->digest, digest_size * digest_count); + } + + spdm_context->connection_info.peer_digest_slot_mask = spdm_response->header.param2; + libspdm_copy_mem( + spdm_context->connection_info.peer_total_digest_buffer, + sizeof(spdm_context->connection_info.peer_total_digest_buffer), + spdm_response->digest, digest_size * digest_count); + + /* -=[Update State Phase]=- */ + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_AFTER_DIGESTS) { + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_AFTER_DIGESTS; + } + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_get_digest(void *context, uint8_t *slot_mask, void *total_digest_buffer) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_digest(spdm_context, NULL, slot_mask, total_digest_buffer); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_get_digest_in_session(void *context, const uint32_t *session_id, + uint8_t *slot_mask, void *total_digest_buffer) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_digest(spdm_context, session_id, slot_mask, total_digest_buffer); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /*LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c new file mode 100644 index 0000000000..c6bb752214 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c @@ -0,0 +1,679 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP + +bool libspdm_verify_measurement_signature(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *sign_data, + size_t sign_data_size) +{ + bool result; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + void *context; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_large_managed_buffer_t l1l2; + uint8_t *l1l2_buffer; + size_t l1l2_buffer_size; +#else + uint8_t l1l2_hash[LIBSPDM_MAX_HASH_SIZE]; + size_t l1l2_hash_size; + uint8_t slot_id; +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_calculate_l1l2(spdm_context, session_info, &l1l2); +#else + l1l2_hash_size = sizeof(l1l2_hash); + result = libspdm_calculate_l1l2_hash(spdm_context, session_info, &l1l2_hash_size, l1l2_hash); +#endif + libspdm_reset_message_m(spdm_context, session_info); + if (!result) { + return false; + } + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + l1l2_buffer = libspdm_get_managed_buffer(&l1l2); + l1l2_buffer_size = libspdm_get_managed_buffer_size(&l1l2); + + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + + /* Get leaf cert from cert chain*/ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify( + spdm_context->connection_info.version, SPDM_MEASUREMENTS, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, context, + l1l2_buffer, l1l2_buffer_size, sign_data, sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); +#else + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != NULL) { + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_MEASUREMENTS, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key, + l1l2_hash, l1l2_hash_size, sign_data, sign_data_size); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - FAIL !!!\n")); + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - PASS !!!\n")); + return true; + } + + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + + /* Get leaf cert from cert chain */ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_MEASUREMENTS, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, context, + l1l2_hash, l1l2_hash_size, sign_data, sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); +#endif + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - FAIL !!!\n")); + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - PASS !!!\n")); + return true; +} + +/** + * This function sends GET_MEASUREMENT to get measurement from the device. + * If the signature is requested this function verifies the signature of the measurement. + * + * @param context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param request_attribute The request attribute of the request message. + * @param measurement_operation The measurement operation of the request message. + * @param slot_id The number of slot for the certificate chain. + * @param content_changed The measurement content changed output param. + * @param number_of_blocks The number of blocks of the measurement record. + * @param measurement_record_length On input, indicate the size in bytes of the destination buffer + * to store the measurement record. + * On output, indicate the size in bytes of the measurement record. + * @param measurement_record A pointer to a destination buffer to store the measurement record. + * @param requester_nonce_in If not NULL, a buffer that holds the requester nonce (32 bytes) + * @param requester_nonce If not NULL, a buffer to hold the requester nonce (32 bytes). + * @param responder_nonce If not NULL, a buffer to hold the responder nonce (32 bytes). + * + **/ +static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id_param, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record, + const void *requester_nonce_in, + void *requester_nonce, + void *responder_nonce) +{ + bool result; + libspdm_return_t status; + spdm_get_measurements_request_t *spdm_request; + size_t spdm_request_size; + spdm_measurements_response_t *spdm_response; + size_t spdm_response_size; + uint32_t measurement_record_data_length; + uint8_t *measurement_record_data; + spdm_measurement_block_common_header_t *measurement_block_header; + uint32_t measurement_block_size; + uint8_t measurement_block_count; + uint8_t *ptr; + void *nonce; + uint16_t opaque_length; + void *signature; + size_t signature_size; + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + spdm_context = context; + + /* -=[Check Parameters Phase]=- */ + LIBSPDM_ASSERT((slot_id_param < SPDM_MAX_SLOT_COUNT) || (slot_id_param == 0xF)); + LIBSPDM_ASSERT((slot_id_param != 0xf) || + (spdm_context->local_context.peer_cert_chain_provision_size != 0)); + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + LIBSPDM_ASSERT(spdm_context->local_context.algorithm.measurement_spec != 0); + + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + if (session_id == NULL) { + session_info = NULL; + } else { + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG) && + ((request_attribute & SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + if ((request_attribute & SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0) { + signature_size = libspdm_get_asym_signature_size( + spdm_context->connection_info.algorithm.base_asym_algo); + } else { + signature_size = 0; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_MEASUREMENTS); + + /* -=[Construct Request Phase]=- */ + if (slot_id_param != 0xf) { + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id_param; + } else { + spdm_context->connection_info.peer_used_cert_chain_slot_id = + spdm_context->local_context.provisioned_slot_id; + } + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_GET_MEASUREMENTS; + spdm_request->header.param1 = request_attribute; + spdm_request->header.param2 = measurement_operation; + if ((request_attribute & SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0) { + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + spdm_request_size = sizeof(spdm_get_measurements_request_t); + } else { + spdm_request_size = sizeof(spdm_get_measurements_request_t) - + sizeof(spdm_request->slot_id_param); + } + + if (requester_nonce_in == NULL) { + if(!libspdm_get_random_number(SPDM_NONCE_SIZE, spdm_request->nonce)) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_LOW_ENTROPY; + } + } else { + libspdm_copy_mem(spdm_request->nonce, sizeof(spdm_request->nonce), + requester_nonce_in, SPDM_NONCE_SIZE); + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientNonce - ")); + LIBSPDM_INTERNAL_DUMP_DATA(spdm_request->nonce, SPDM_NONCE_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + spdm_request->slot_id_param = slot_id_param; + + if (requester_nonce != NULL) { + libspdm_copy_mem(requester_nonce, SPDM_NONCE_SIZE, + spdm_request->nonce, SPDM_NONCE_SIZE); + } + } else { + spdm_request_size = sizeof(spdm_request->header); + + if (requester_nonce != NULL) { + libspdm_zero_mem (requester_nonce, SPDM_NONCE_SIZE); + } + } + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, session_id, + &spdm_response_size, (void **)&spdm_response, + SPDM_GET_MEASUREMENTS, SPDM_MEASUREMENTS, + message_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_MEASUREMENTS) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_measurements_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (measurement_operation == + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS) { + if (spdm_response->number_of_blocks != 0) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else if (measurement_operation == + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS) { + if (spdm_response->number_of_blocks == 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else { + if (spdm_response->number_of_blocks != 1) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + + measurement_record_data_length = libspdm_read_uint24(spdm_response->measurement_record_length); + if (measurement_operation == + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS) { + if (measurement_record_data_length != 0) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else { + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "measurement_record_length - 0x%06x\n", + measurement_record_data_length)); + } + + measurement_record_data = (void *)(spdm_response + 1); + + if ((request_attribute & SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0) { + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length + SPDM_NONCE_SIZE + sizeof(uint16_t)) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if ((spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_11) && + ((spdm_response->header.param2 & SPDM_MEASUREMENTS_RESPONSE_SLOT_ID_MASK) + != slot_id_param)) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + ptr = measurement_record_data + measurement_record_data_length; + nonce = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "nonce (0x%x) - ", SPDM_NONCE_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(nonce, SPDM_NONCE_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ptr += SPDM_NONCE_SIZE; + if (responder_nonce != NULL) { + libspdm_copy_mem(responder_nonce, SPDM_NONCE_SIZE, nonce, SPDM_NONCE_SIZE); + } + + opaque_length = *(uint16_t *)ptr; + if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + ptr += sizeof(uint16_t); + + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length + SPDM_NONCE_SIZE + + sizeof(uint16_t) + opaque_length + signature_size) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + spdm_response_size = sizeof(spdm_measurements_response_t) + + measurement_record_data_length + + SPDM_NONCE_SIZE + sizeof(uint16_t) + + opaque_length + signature_size; + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_m(spdm_context, session_info, spdm_request, + spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_m(spdm_context, session_info, spdm_response, + spdm_response_size - signature_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + LIBSPDM_DEBUG_CODE( + void *opaque; + opaque = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "opaque (0x%x):\n", opaque_length)); + LIBSPDM_INTERNAL_DUMP_HEX(opaque, opaque_length); + ); + ptr += opaque_length; + + signature = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "signature (0x%x):\n", signature_size)); + LIBSPDM_INTERNAL_DUMP_HEX(signature, signature_size); + + result = libspdm_verify_measurement_signature( + spdm_context, session_info, signature, signature_size); + if (!result) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + + libspdm_reset_message_m(spdm_context, session_info); + } else { + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length + sizeof(uint16_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + ptr = measurement_record_data + measurement_record_data_length; + + nonce = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "nonce (0x%x) - ", SPDM_NONCE_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(nonce, SPDM_NONCE_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + ptr += SPDM_NONCE_SIZE; + if (responder_nonce != NULL) { + libspdm_copy_mem(responder_nonce, SPDM_NONCE_SIZE, nonce, SPDM_NONCE_SIZE); + } + + opaque_length = *(uint16_t *)ptr; + if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + ptr += sizeof(uint16_t); + + if (spdm_response_size < + sizeof(spdm_measurements_response_t) + + measurement_record_data_length + SPDM_NONCE_SIZE + + sizeof(uint16_t) + opaque_length) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + spdm_response_size = sizeof(spdm_measurements_response_t) + + measurement_record_data_length + + SPDM_NONCE_SIZE + sizeof(uint16_t) + + opaque_length; + + status = libspdm_append_message_m(spdm_context, session_info, spdm_request, + spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_m(spdm_context, session_info, spdm_response, + spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_reset_message_m(spdm_context, session_info); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + } + + if (content_changed != NULL) { + *content_changed = 0; + if ((spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) && + ((request_attribute & + SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE) != 0)) { + *content_changed = + (spdm_response->header.param2 & SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_MASK); + } + } + if (measurement_operation == + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS) { + *number_of_blocks = spdm_response->header.param1; + if (*number_of_blocks == 0xFF) { + /* the number of block cannot be 0xFF, because index 0xFF will brings confusing.*/ + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (*number_of_blocks == 0x0) { + /* the number of block cannot be 0x0, because a responder without measurement should clear capability flags.*/ + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else { + *number_of_blocks = spdm_response->number_of_blocks; + if (*measurement_record_length < measurement_record_data_length) { + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + goto receive_done; + } + if (measurement_record_data_length < sizeof(spdm_measurement_block_common_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + measurement_block_size = 0; + measurement_block_count = 1; + while (measurement_block_size < measurement_record_data_length) { + measurement_block_header = + (spdm_measurement_block_common_header_t *)&measurement_record_data + [measurement_block_size]; + if (measurement_block_header->measurement_size > + measurement_record_data_length - + ((uint8_t *)measurement_block_header - + (uint8_t *)measurement_record_data)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (measurement_block_header->measurement_specification == 0 || + (measurement_block_header->measurement_specification & + (measurement_block_header->measurement_specification - 1))) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (measurement_block_header->measurement_specification != + spdm_context->connection_info.algorithm.measurement_spec) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (measurement_block_header->index == 0 || measurement_block_header->index == 0xFF) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (measurement_operation != + SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS) { + if (measurement_block_header->index != measurement_operation) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + if (measurement_block_count > *number_of_blocks) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + measurement_block_count++; + measurement_block_size = (uint32_t)( + measurement_block_size + + sizeof(spdm_measurement_block_common_header_t) + + measurement_block_header->measurement_size); + } + + *measurement_record_length = measurement_record_data_length; + libspdm_copy_mem(measurement_record, + measurement_record_data_length, + measurement_record_data, + measurement_record_data_length); + } + + status = LIBSPDM_STATUS_SUCCESS; + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_get_measurement(void *context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id_param, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_measurement( + spdm_context, session_id, request_attribute, + measurement_operation, slot_id_param, content_changed, number_of_blocks, + measurement_record_length, measurement_record, NULL, NULL, NULL); + if (LIBSPDM_STATUS_BUSY_PEER != status) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *session_id, + uint8_t request_attribute, + uint8_t measurement_operation, + uint8_t slot_id_param, + uint8_t *content_changed, + uint8_t *number_of_blocks, + uint32_t *measurement_record_length, + void *measurement_record, + const void *requester_nonce_in, + void *requester_nonce, + void *responder_nonce) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + + spdm_context = context; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_measurement( + spdm_context, session_id, request_attribute, + measurement_operation, slot_id_param, content_changed, number_of_blocks, + measurement_record_length, measurement_record, + requester_nonce_in, + requester_nonce, responder_nonce); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP*/ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c new file mode 100644 index 0000000000..2a5306af3a --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c @@ -0,0 +1,222 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t reserved; + uint8_t version_number_entry_count; + spdm_version_number_t version_number_entry[LIBSPDM_MAX_VERSION_COUNT]; +} libspdm_version_response_max_t; +#pragma pack() + +/** + * This function sends GET_VERSION and receives VERSION. + * + * @param spdm_context A pointer to the SPDM context. + * @param version_count The number of SPDM versions that the Responder supports. + * @param VersionNumberEntries The list of SPDM versions that the Responder supports. + * + * @retval LIBSPDM_STATUS_SUCCESS + * GET_VERSION was sent and VERSION was received. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the VERSION response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The VERSION response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_NEGOTIATION_FAIL + * The Requester and Responder do not support a common SPDM version. + **/ +static libspdm_return_t libspdm_try_get_version(libspdm_context_t *spdm_context, + uint8_t *version_number_entry_count, + spdm_version_number_t *version_number_entry) +{ + libspdm_return_t status; + bool result; + spdm_get_version_request_t *spdm_request; + size_t spdm_request_size; + libspdm_version_response_max_t *spdm_response; + size_t spdm_response_size; + spdm_version_number_t common_version; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* -=[Set State Phase]=- */ + libspdm_reset_message_a(spdm_context); + libspdm_reset_message_b(spdm_context); + libspdm_reset_message_c(spdm_context); + libspdm_reset_context(spdm_context); + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_VERSION); + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = SPDM_MESSAGE_VERSION_10; + spdm_request->header.request_response_code = SPDM_GET_VERSION; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + spdm_request_size = sizeof(spdm_get_version_request_t); + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, NULL, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response(spdm_context, NULL, &spdm_response_size, + (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != SPDM_MESSAGE_VERSION_10) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response(spdm_context, spdm_response->header.param1); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_VERSION) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_version_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->version_number_entry_count > LIBSPDM_MAX_VERSION_COUNT) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->version_number_entry_count == 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_version_response_t) + + spdm_response->version_number_entry_count * sizeof(spdm_version_number_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + spdm_response_size = sizeof(spdm_version_response_t) + + spdm_response->version_number_entry_count * sizeof(spdm_version_number_t); + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_a(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + status = libspdm_append_message_a(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_reset_message_a(spdm_context); + goto receive_done; + } + + result = libspdm_negotiate_connection_version ( + &common_version, + spdm_context->local_context.version.spdm_version, + spdm_context->local_context.version.spdm_version_count, + spdm_response->version_number_entry, + spdm_response->version_number_entry_count); + if (result == false) { + libspdm_reset_message_a(spdm_context); + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + + libspdm_copy_mem(&(spdm_context->connection_info.version), + sizeof(spdm_context->connection_info.version), + &(common_version), sizeof(spdm_version_number_t)); + + if (version_number_entry_count != NULL && version_number_entry != NULL) { + if (*version_number_entry_count < spdm_response->version_number_entry_count) { + *version_number_entry_count = spdm_response->version_number_entry_count; + libspdm_reset_message_a(spdm_context); + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + goto receive_done; + } else { + *version_number_entry_count = spdm_response->version_number_entry_count; + libspdm_copy_mem(version_number_entry, + spdm_response->version_number_entry_count * + sizeof(spdm_version_number_t), + spdm_response->version_number_entry, + spdm_response->version_number_entry_count * + sizeof(spdm_version_number_t)); + libspdm_version_number_sort (version_number_entry, *version_number_entry_count); + } + } + + /* -=[Update State Phase]=- */ + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_AFTER_VERSION; + status = LIBSPDM_STATUS_SUCCESS; + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + + /*Set the role of device*/ + spdm_context->local_context.is_requester = true; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_get_version(libspdm_context_t *spdm_context, + uint8_t *version_number_entry_count, + spdm_version_number_t *version_number_entry) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = false; + retry = spdm_context->retry_times; + do { + status = libspdm_try_get_version(spdm_context, + version_number_entry_count, version_number_entry); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c new file mode 100644 index 0000000000..542b6884bc --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c @@ -0,0 +1,418 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" +#include "hal/library/platform_lib.h" + +/** + * This function sends RESPOND_IF_READY and receives an expected SPDM response. + * + * @param spdm_context A pointer to the SPDM context. + * @param response_size The size of the response. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned. + * @param response The SPDM response message. + * @param expected_response_code Indicate the expected response code. + * @param expected_response_size Indicate the expected response size. + * + * @retval RETURN_SUCCESS The RESPOND_IF_READY is sent and an expected SPDM response is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +static libspdm_return_t libspdm_requester_respond_if_ready(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *response_size, + void **response, + uint8_t expected_response_code, + size_t expected_response_size) +{ + libspdm_return_t status; + spdm_response_if_ready_request_t *spdm_request; + size_t spdm_request_size; + spdm_message_header_t *spdm_response; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* the response might be in response buffer in normal SPDM message + * or it is in scratch buffer in case of secure SPDM message + * the response buffer is in acquired state, so we release it*/ + libspdm_release_receiver_buffer (spdm_context); + + /* now we can get sender buffer */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_context->crypto_request = true; + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_RESPOND_IF_READY; + spdm_request->header.param1 = spdm_context->error_data.request_code; + spdm_request->header.param2 = spdm_context->error_data.token; + spdm_request_size = sizeof(spdm_response_if_ready_request_t); + status = libspdm_send_spdm_request(spdm_context, session_id, + spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + /* need acquire response buffer, so that the caller can release it */ + status = libspdm_acquire_receiver_buffer (spdm_context, response_size, response); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* receive + * do not release response buffer in case of error, because caller will release it*/ + + status = libspdm_acquire_receiver_buffer (spdm_context, response_size, response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (*response_size >= transport_header_size); + + libspdm_zero_mem(*response, *response_size); + status = libspdm_receive_spdm_response(spdm_context, session_id, + response_size, response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + spdm_response = (void *)(*response); + if (*response_size < sizeof(spdm_message_header_t)) { + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + if (spdm_response->spdm_version != spdm_request->header.spdm_version) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (spdm_response->request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response(spdm_context, spdm_response->param1); + return status; + } + if (spdm_response->request_response_code != expected_response_code) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + /* For response like SPDM_ALGORITHMS, we just can expect the max response size*/ + if (*response_size > expected_response_size) { + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + return LIBSPDM_STATUS_SUCCESS; +} + +libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t error_code) +{ + libspdm_context_t *spdm_context; + + spdm_context = context; + + if (error_code == SPDM_ERROR_CODE_RESPONSE_NOT_READY) { + return LIBSPDM_STATUS_NOT_READY_PEER; + } + + if (error_code == SPDM_ERROR_CODE_BUSY) { + return LIBSPDM_STATUS_BUSY_PEER; + } + + if (error_code == SPDM_ERROR_CODE_REQUEST_RESYNCH) { + spdm_context->connection_info.connection_state = + LIBSPDM_CONNECTION_STATE_NOT_STARTED; + return LIBSPDM_STATUS_RESYNCH_PEER; + } + + return LIBSPDM_STATUS_ERROR_PEER; +} + +/** + * This function handles RESPONSE_NOT_READY error code. + * + * @param spdm_context A pointer to the SPDM context. + * @param response_size The size of the response. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned. + * @param response The SPDM response message. + * @param original_request_code Indicate the orginal request code. + * @param expected_response_code Indicate the expected response code. + * @param expected_response_size Indicate the expected response size. + * + * @retval RETURN_SUCCESS The RESPOND_IF_READY is sent and an expected SPDM response is received. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + **/ +static libspdm_return_t libspdm_handle_response_not_ready(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *response_size, + void **response, + uint8_t original_request_code, + uint8_t expected_response_code, + size_t expected_response_size) +{ + spdm_error_response_t *spdm_response; + spdm_error_data_response_not_ready_t *extend_error_data; + + if(*response_size != sizeof(spdm_error_response_t) + + sizeof(spdm_error_data_response_not_ready_t)) { + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + spdm_response = *response; + extend_error_data = + (spdm_error_data_response_not_ready_t *)(spdm_response + 1); + LIBSPDM_ASSERT(spdm_response->header.request_response_code == SPDM_ERROR); + LIBSPDM_ASSERT(spdm_response->header.param1 == + SPDM_ERROR_CODE_RESPONSE_NOT_READY); + if (extend_error_data->request_code != original_request_code) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + spdm_context->error_data.rd_exponent = extend_error_data->rd_exponent; + spdm_context->error_data.request_code = extend_error_data->request_code; + spdm_context->error_data.token = extend_error_data->token; + spdm_context->error_data.rd_tm = extend_error_data->rd_tm; + + libspdm_sleep_in_us((2 << extend_error_data->rd_exponent)); + return libspdm_requester_respond_if_ready(spdm_context, session_id, + response_size, response, + expected_response_code, + expected_response_size); +} + +#if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) +libspdm_return_t libspdm_handle_error_large_response( + libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *inout_response_size, + void *inout_response, + size_t response_capacity) +{ + libspdm_return_t status; + uint8_t chunk_handle; + spdm_error_response_t* error_response; + spdm_error_data_large_response_t* extend_error_data; + + spdm_chunk_get_request_t* spdm_request; + size_t spdm_request_size; + spdm_chunk_response_response_t* spdm_response; + uint8_t* message; + size_t message_size; + size_t transport_header_size; + + uint8_t* scratch_buffer; + size_t scratch_buffer_size; + uint16_t chunk_seq_no; + uint8_t* chunk_ptr; + uint8_t* large_response; + size_t large_response_capacity; + size_t large_response_size; + size_t large_response_size_so_far; + + /* Fail if requester or responder does not support chunk cap */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP)) { + return LIBSPDM_STATUS_ERROR_PEER; + } + + if (*inout_response_size < sizeof(spdm_error_response_t) + + sizeof(spdm_error_data_large_response_t)) { + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + error_response = inout_response; + extend_error_data = + (spdm_error_data_large_response_t*)(error_response + 1); + chunk_handle = extend_error_data->handle; + + /* now we can get sender buffer */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + + libspdm_get_scratch_buffer(spdm_context, (void**)&scratch_buffer, &scratch_buffer_size); + LIBSPDM_ASSERT(scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); + + /* The first LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE bytes of the scratch + * buffer may be used for other purposes. Use only after that section. */ + large_response = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET; + large_response_capacity = LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY; + + /* Temporary send/receive buffers for chunking are in the scratch space */ + message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; + message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + + libspdm_zero_mem(large_response, large_response_capacity); + large_response_size = 0; + large_response_size_so_far = 0; + chunk_seq_no = 0; + + do { + LIBSPDM_ASSERT(message_size >= transport_header_size); + spdm_request = (spdm_chunk_get_request_t*)(void*) (message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version(spdm_context); + spdm_request->header.request_response_code = SPDM_CHUNK_GET; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = chunk_handle; + spdm_request->chunk_seq_no = chunk_seq_no; + spdm_request_size = sizeof(spdm_chunk_get_request_t); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "CHUNK_GET Handle %d SeqNo %d\n", chunk_handle, chunk_seq_no)); + + status = libspdm_send_spdm_request(spdm_context, session_id, + spdm_request_size, spdm_request); + spdm_request = NULL; + spdm_request_size = 0; + if (LIBSPDM_STATUS_IS_ERROR(status)) { + break; + } + + libspdm_zero_mem(message, message_size); + void* response = message; + size_t response_size = message_size; + + status = libspdm_receive_spdm_response( + spdm_context, session_id, + &response_size, &response); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + break; + } + spdm_response = (void*) (response); + if (spdm_response->header.spdm_version != libspdm_get_connection_version(spdm_context)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response(spdm_context, + spdm_response->header.param1); + break; + } + if (spdm_response->header.request_response_code != SPDM_CHUNK_RESPONSE) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (chunk_seq_no == 0) { + + if (response_size + < (sizeof(spdm_chunk_response_response_t) + sizeof(uint32_t))) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (response_size < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + + if (spdm_response->chunk_size + < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12 + - sizeof(spdm_chunk_response_response_t) + - sizeof(uint32_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + + large_response_size = *(uint32_t*) (spdm_response + 1); + chunk_ptr = (uint8_t*) (((uint32_t*) (spdm_response + 1)) + 1); + + if (spdm_response->chunk_size > large_response_size) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (large_response_size > large_response_capacity) { + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + break; + } + } + else { + if (response_size < sizeof(spdm_chunk_response_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (spdm_response->chunk_size + large_response_size_so_far > large_response_size) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + + if (!(spdm_response->header.param1 & SPDM_CHUNK_GET_RESPONSE_ATTRIBUTE_LAST_CHUNK)) + { + if (response_size < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (spdm_response->chunk_size + < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12 + - sizeof(spdm_chunk_response_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + } + + chunk_ptr = (uint8_t*) (spdm_response + 1); + } + + if (spdm_response->chunk_seq_no != chunk_seq_no) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + + libspdm_copy_mem(large_response + large_response_size_so_far, + large_response_size - large_response_size_so_far, + chunk_ptr, spdm_response->chunk_size); + + large_response_size_so_far += spdm_response->chunk_size; + + chunk_seq_no++; + + } while (LIBSPDM_STATUS_IS_SUCCESS(status) + && large_response_size_so_far < large_response_size + && !(spdm_response->header.param1 & SPDM_CHUNK_GET_RESPONSE_ATTRIBUTE_LAST_CHUNK)); + + + if (LIBSPDM_STATUS_IS_SUCCESS(status)) { + if (large_response_size_so_far != large_response_size) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + else if (large_response_size <= response_capacity) + { + libspdm_copy_mem(inout_response, response_capacity, + large_response, large_response_size); + *inout_response_size = large_response_size; + + LIBSPDM_INTERNAL_DUMP_HEX(large_response, large_response_size); + } + } + + return status; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +libspdm_return_t libspdm_handle_error_response_main( + libspdm_context_t *spdm_context, const uint32_t *session_id, + size_t *response_size, void **response, + uint8_t original_request_code, uint8_t expected_response_code, + size_t expected_response_size) +{ + spdm_message_header_t *spdm_response; + + spdm_response = *response; + LIBSPDM_ASSERT(spdm_response->request_response_code == SPDM_ERROR); + + if ((spdm_response->param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) && + (session_id != NULL)) { + libspdm_free_session_id(spdm_context, *session_id); + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } else if(spdm_response->param1 == SPDM_ERROR_CODE_RESPONSE_NOT_READY) { + return libspdm_handle_response_not_ready(spdm_context, session_id, + response_size, response, + original_request_code, + expected_response_code, + expected_response_size); + } else { + return libspdm_handle_simple_error_response(spdm_context, + spdm_response->param1); + } +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c new file mode 100644 index 0000000000..d00a3294bf --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c @@ -0,0 +1,777 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint16_t req_session_id; + uint8_t session_policy; + uint8_t reserved; + uint8_t random_data[SPDM_RANDOM_DATA_SIZE]; + uint8_t exchange_data[LIBSPDM_MAX_DHE_KEY_SIZE]; + uint16_t opaque_length; + uint8_t opaque_data[SPDM_MAX_OPAQUE_DATA_SIZE]; +} libspdm_key_exchange_request_mine_t; + +typedef struct { + spdm_message_header_t header; + uint16_t rsp_session_id; + uint8_t mut_auth_requested; + uint8_t req_slot_id_param; + uint8_t random_data[SPDM_RANDOM_DATA_SIZE]; + uint8_t exchange_data[LIBSPDM_MAX_DHE_KEY_SIZE]; + uint8_t measurement_summary_hash[LIBSPDM_MAX_HASH_SIZE]; + uint16_t opaque_length; + uint8_t opaque_data[SPDM_MAX_OPAQUE_DATA_SIZE]; + uint8_t signature[LIBSPDM_MAX_ASYM_KEY_SIZE]; + uint8_t verify_data[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_key_exchange_response_max_t; +#pragma pack() + +bool libspdm_verify_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, + libspdm_session_info_t *session_info, + const void *hmac_data, + size_t hmac_data_size) +{ + size_t hash_size; + uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; + bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; +#endif + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + LIBSPDM_ASSERT(hash_size == hmac_data_size); + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_exchange( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data); + if (!result) { + return false; + } + + result = libspdm_hmac_all_with_response_finished_key( + session_info->secured_message_context, hash_data, + hash_size, calc_hmac_data); + if (!result) { + return false; + } +#else + result = libspdm_calculate_th_hmac_for_exchange_rsp( + spdm_context, session_info, true, &hash_size, calc_hmac_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hmac - ")); + LIBSPDM_INTERNAL_DUMP_DATA(calc_hmac_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + if (libspdm_const_compare_mem(calc_hmac_data, hmac_data, hash_size) != 0) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_hmac - FAIL !!!\n")); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_hmac - PASS !!!\n")); + + return true; +} + +bool libspdm_verify_key_exchange_rsp_signature( + libspdm_context_t *spdm_context, libspdm_session_info_t *session_info, + const void *sign_data, const size_t sign_data_size) +{ + bool result; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + void *context; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t *cert_chain_buffer; + size_t cert_chain_buffer_size; + uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + size_t th_curr_data_size; +#else + uint8_t slot_id; +#endif +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) + size_t hash_size; + uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); +#endif + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (!result) { + return false; + } + + th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_exchange( + spdm_context, session_info, cert_chain_buffer, + cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + if (!result) { + return false; + } + + /* Debug code only - required for debug print of th_curr hash below*/ + LIBSPDM_DEBUG_CODE( + if (!libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + th_curr_data, th_curr_data_size, hash_data)) { + return false; + } + ); +#else + result = libspdm_calculate_th_hash_for_exchange( + spdm_context, session_info, &hash_size, hash_data); + if (!result) { + return false; + } +#endif + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "th_curr hash - ")); + LIBSPDM_INTERNAL_DUMP_DATA(hash_data, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "signature - ")); + LIBSPDM_INTERNAL_DUMP_DATA(sign_data, sign_data_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + /* Get leaf cert from cert chain */ + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify( + spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, context, + th_curr_data, th_curr_data_size, sign_data, sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); +#else + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != NULL) { + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key, + hash_data, hash_size, sign_data, sign_data_size); + } else { + /* Get leaf cert from cert chain*/ + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); + if (!result) { + return false; + } + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } + + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } + + result = libspdm_asym_verify_hash( + spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, context, + hash_data, hash_size, sign_data, sign_data_size); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); + } +#endif + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_signature - FAIL !!!\n")); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_signature - PASS !!!\n")); + + return true; +} + +/** + * This function sends KEY_EXCHANGE and receives KEY_EXCHANGE_RSP for SPDM key exchange. + * + * @param spdm_context A pointer to the SPDM context. + * @param measurement_hash_type Measurement_hash_type to the KEY_EXCHANGE request. + * @param slot_id slot_id to the KEY_EXCHANGE request. + * @param session_policy The policy for the session. + * @param session_id session_id from the KEY_EXCHANGE_RSP response. + * @param heartbeat_period Heartbeat_period from the KEY_EXCHANGE_RSP response. + * @param req_slot_id_param req_slot_id_param from the KEY_EXCHANGE_RSP response. + * @param measurement_hash Measurement_hash from the KEY_EXCHANGE_RSP response. + * @param requester_nonce_in If not NULL, a buffer that holds the requester nonce (32 bytes) + * @param requester_nonce If not NULL, a buffer to hold the requester nonce (32 bytes). + * @param responder_nonce If not NULL, a buffer to hold the responder nonce (32 bytes). + **/ +static libspdm_return_t libspdm_try_send_receive_key_exchange( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash, + const void *requester_random_in, + void *requester_random, + void *responder_random) +{ + bool result; + libspdm_return_t status; + libspdm_key_exchange_request_mine_t *spdm_request; + size_t spdm_request_size; + libspdm_key_exchange_response_max_t *spdm_response; + size_t spdm_response_size; + size_t dhe_key_size; + uint32_t measurement_summary_hash_size; + uint32_t signature_size; + uint32_t hmac_size; + uint8_t *ptr; + void *measurement_summary_hash; + uint16_t opaque_length; + uint8_t *signature; + uint8_t *verify_data; + void *dhe_context; + uint16_t req_session_id; + uint16_t rsp_session_id; + libspdm_session_info_t *session_info; + size_t opaque_key_exchange_req_size; + uint8_t th1_hash_data[LIBSPDM_MAX_HASH_SIZE]; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + uint8_t mut_auth_requested; + + /* -=[Check Parameters Phase]=- */ + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xff)); + LIBSPDM_ASSERT((slot_id != 0xff) || + (spdm_context->local_context.peer_cert_chain_provision_size != 0)); + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + req_session_id = libspdm_allocate_req_session_id(spdm_context); + if (req_session_id == ((INVALID_SESSION_ID & 0xFFFF0000) >> 16)) + { + return LIBSPDM_STATUS_SESSION_NUMBER_EXCEED; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_KEY_EXCHANGE); + + /* -=[Construct Request Phase]=- */ + if (slot_id != 0xff) { + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; + } else { + spdm_context->connection_info.peer_used_cert_chain_slot_id = + spdm_context->local_context.provisioned_slot_id; + } + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_KEY_EXCHANGE; + spdm_request->header.param1 = measurement_hash_type; + spdm_request->header.param2 = slot_id; + if (requester_random_in == NULL) { + if(!libspdm_get_random_number(SPDM_RANDOM_DATA_SIZE, spdm_request->random_data)) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_LOW_ENTROPY; + } + } else { + libspdm_copy_mem(spdm_request->random_data, sizeof(spdm_request->random_data), + requester_random_in, SPDM_RANDOM_DATA_SIZE); + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientRandomData (0x%x) - ", + SPDM_RANDOM_DATA_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(spdm_request->random_data, SPDM_RANDOM_DATA_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + if (requester_random != NULL) { + libspdm_copy_mem(requester_random, SPDM_RANDOM_DATA_SIZE, + spdm_request->random_data, SPDM_RANDOM_DATA_SIZE); + } + + spdm_request->req_session_id = req_session_id; + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_request->session_policy = session_policy; + } else { + spdm_request->session_policy = 0; + } + spdm_request->reserved = 0; + + ptr = spdm_request->exchange_data; + dhe_key_size = libspdm_get_dhe_pub_key_size( + spdm_context->connection_info.algorithm.dhe_named_group); + dhe_context = libspdm_secured_message_dhe_new( + spdm_context->connection_info.version, + spdm_context->connection_info.algorithm.dhe_named_group, true); + if (dhe_context == NULL) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + result = libspdm_secured_message_dhe_generate_key( + spdm_context->connection_info.algorithm.dhe_named_group, + dhe_context, ptr, &dhe_key_size); + if (!result) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientKey (0x%x):\n", dhe_key_size)); + LIBSPDM_INTERNAL_DUMP_HEX(ptr, dhe_key_size); + ptr += dhe_key_size; + + opaque_key_exchange_req_size = + libspdm_get_opaque_data_supported_version_data_size(spdm_context); + *(uint16_t *)ptr = (uint16_t)opaque_key_exchange_req_size; + ptr += sizeof(uint16_t); + status = libspdm_build_opaque_data_supported_version_data( + spdm_context, &opaque_key_exchange_req_size, ptr); + LIBSPDM_ASSERT(status == LIBSPDM_STATUS_SUCCESS); + ptr += opaque_key_exchange_req_size; + + spdm_request_size = (size_t)ptr - (size_t)spdm_request; + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, NULL, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, NULL, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, NULL, &spdm_response_size, + (void **)&spdm_response, SPDM_KEY_EXCHANGE, + SPDM_KEY_EXCHANGE_RSP, sizeof(libspdm_key_exchange_response_max_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_KEY_EXCHANGE_RSP) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_key_exchange_response_t)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HBEAT_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HBEAT_CAP)) { + if (spdm_response->header.param1 != 0) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + if (heartbeat_period != NULL) { + *heartbeat_period = spdm_response->header.param1; + } + + *req_slot_id_param = spdm_response->req_slot_id_param & 0xf; + mut_auth_requested = spdm_response->mut_auth_requested & 0x7; + + if (mut_auth_requested != 0) { + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MUT_AUTH_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MUT_AUTH_CAP)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if ((mut_auth_requested != SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST) && + (mut_auth_requested != + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if ((*req_slot_id_param != 0xF) && (*req_slot_id_param >= SPDM_MAX_SLOT_COUNT)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if ((mut_auth_requested != SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED) && + (*req_slot_id_param != 0)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } else if (*req_slot_id_param != 0) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + + signature_size = libspdm_get_asym_signature_size( + spdm_context->connection_info.algorithm.base_asym_algo); + measurement_summary_hash_size = libspdm_get_measurement_summary_hash_size( + spdm_context, true, measurement_hash_type); + hmac_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + hmac_size = 0; + } + + if (spdm_response_size < + sizeof(spdm_key_exchange_response_t) + dhe_key_size + + measurement_summary_hash_size + sizeof(uint16_t) + signature_size + hmac_size) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ServerRandomData (0x%x) - ", SPDM_RANDOM_DATA_SIZE)); + LIBSPDM_INTERNAL_DUMP_DATA(spdm_response->random_data, SPDM_RANDOM_DATA_SIZE); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + if (responder_random != NULL) { + libspdm_copy_mem(responder_random, SPDM_RANDOM_DATA_SIZE, + spdm_response->random_data, SPDM_RANDOM_DATA_SIZE); + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ServerKey (0x%x):\n", dhe_key_size)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->exchange_data, dhe_key_size); + + ptr = spdm_response->exchange_data; + ptr += dhe_key_size; + + measurement_summary_hash = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "measurement_summary_hash (0x%x) - ", + measurement_summary_hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(measurement_summary_hash, measurement_summary_hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + ptr += measurement_summary_hash_size; + + opaque_length = *(uint16_t *)ptr; + if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + ptr += sizeof(uint16_t); + if (spdm_response_size < + sizeof(spdm_key_exchange_response_t) + dhe_key_size + + measurement_summary_hash_size + sizeof(uint16_t) + + opaque_length + signature_size + hmac_size) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (opaque_length != 0) { + status = libspdm_process_opaque_data_version_selection_data( + spdm_context, opaque_length, ptr); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + + ptr += opaque_length; + + spdm_response_size = sizeof(spdm_key_exchange_response_t) + + dhe_key_size + measurement_summary_hash_size + + sizeof(uint16_t) + opaque_length + signature_size + hmac_size; + + rsp_session_id = spdm_response->rsp_session_id; + *session_id = libspdm_generate_session_id(req_session_id, rsp_session_id); + session_info = libspdm_assign_session_id(spdm_context, *session_id, false); + + if (session_info == NULL) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_SESSION_NUMBER_EXCEED; + goto receive_done; + } + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_k(spdm_context, session_info, true, spdm_request, + spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_k(spdm_context, session_info, true, spdm_response, + spdm_response_size - signature_size - hmac_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + signature = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "signature (0x%x):\n", signature_size)); + LIBSPDM_INTERNAL_DUMP_HEX(signature, signature_size); + ptr += signature_size; + result = libspdm_verify_key_exchange_rsp_signature( + spdm_context, session_info, signature, signature_size); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + + status = libspdm_append_message_k(spdm_context, session_info, true, signature, signature_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_free_session_id(spdm_context, *session_id); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + result = libspdm_secured_message_dhe_compute_key( + spdm_context->connection_info.algorithm.dhe_named_group, + dhe_context, spdm_response->exchange_data, dhe_key_size, + session_info->secured_message_context); + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_generate_session_handshake_key[%x]\n", + *session_id)); + result = libspdm_calculate_th1_hash(spdm_context, session_info, true, th1_hash_data); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + result = libspdm_generate_session_handshake_key( + session_info->secured_message_context, th1_hash_data); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + verify_data = ptr; + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "verify_data (0x%x):\n", hmac_size)); + LIBSPDM_INTERNAL_DUMP_HEX(verify_data, hmac_size); + result = libspdm_verify_key_exchange_rsp_hmac( + spdm_context, session_info, verify_data, hmac_size); + if (!result) { + libspdm_free_session_id(spdm_context, *session_id); + status = LIBSPDM_STATUS_VERIF_FAIL; + goto receive_done; + } + ptr += hmac_size; + + status = libspdm_append_message_k(spdm_context, session_info, true, verify_data, hmac_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_free_session_id(spdm_context, *session_id); + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + } + + if (measurement_hash != NULL) { + libspdm_copy_mem(measurement_hash, measurement_summary_hash_size, + measurement_summary_hash, measurement_summary_hash_size); + } + session_info->heartbeat_period = spdm_response->header.param1; + session_info->mut_auth_requested = mut_auth_requested; + session_info->session_policy = session_policy; + + /* -=[Update State Phase]=- */ + libspdm_secured_message_set_session_state( + session_info->secured_message_context, LIBSPDM_SESSION_STATE_HANDSHAKING); + + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_send_receive_key_exchange( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_send_receive_key_exchange( + spdm_context, measurement_hash_type, slot_id, session_policy, + session_id, heartbeat_period, req_slot_id_param, + measurement_hash, NULL, NULL, NULL); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} + +libspdm_return_t libspdm_send_receive_key_exchange_ex( + libspdm_context_t *spdm_context, uint8_t measurement_hash_type, + uint8_t slot_id, uint8_t session_policy, uint32_t *session_id, + uint8_t *heartbeat_period, + uint8_t *req_slot_id_param, void *measurement_hash, + const void *requester_random_in, + void *requester_random, + void *responder_random) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_send_receive_key_exchange( + spdm_context, measurement_hash_type, slot_id, session_policy, + session_id, heartbeat_period, req_slot_id_param, + measurement_hash, requester_random_in, + requester_random, responder_random); + if (LIBSPDM_STATUS_BUSY_PEER != status) { + return status; + } + } while (retry-- != 0); + + return status; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c new file mode 100644 index 0000000000..0679737cbb --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c @@ -0,0 +1,326 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t dummy_data[sizeof(spdm_error_data_response_not_ready_t)]; +} libspdm_key_update_response_mine_t; +#pragma pack() + +/** + * This function sends KEY_UPDATE + * to update keys for an SPDM Session. + * + * After keys are updated, this function also uses VERIFY_NEW_KEY to verify the key. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * @param single_direction true means the operation is UPDATE_KEY. + * false means the operation is UPDATE_ALL_KEYS. + * @param key_updated true means the operation is to verify key(s). + * false means the operation is to update and verify key(s). + * + * @retval RETURN_SUCCESS The keys of the session are updated. + * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. + * @retval RETURN_SECURITY_VIOLATION Any verification fails. + **/ +static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_id, + bool single_direction, bool *key_updated) +{ + libspdm_return_t status; + bool result; + spdm_key_update_request_t *spdm_request; + size_t spdm_request_size; + libspdm_key_update_response_mine_t *spdm_response; + size_t spdm_response_size; + libspdm_context_t *spdm_context; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + spdm_context = context; + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + if (spdm_context->connection_info.connection_state < + LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_info = + libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_KEY_UPDATE); + + if(!(*key_updated)) { + + /* Update key*/ + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_KEY_UPDATE; + if (single_direction) { + spdm_request->header.param1 = SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_KEY; + } else { + spdm_request->header.param1 = SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_ALL_KEYS; + } + spdm_request->header.param2 = 0; + + if(!libspdm_get_random_number(sizeof(spdm_request->header.param2), + &spdm_request->header.param2)) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_LOW_ENTROPY; + } + + spdm_request_size = sizeof(spdm_key_update_request_t); + + /* If updating both, create new responder key*/ + if (!single_direction) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_create_update_session_data_key[%x] Responder\n", + session_id)); + result = libspdm_create_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER); + if (!result) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + status = libspdm_send_spdm_request(spdm_context, &session_id, + spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + + if (!LIBSPDM_STATUS_IS_ERROR(status)) { + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + } else if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + } else if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, &session_id, + &spdm_response_size, (void **)&spdm_response, + SPDM_KEY_UPDATE, SPDM_KEY_UPDATE_ACK, + sizeof(libspdm_key_update_response_mine_t)); + } else if ((spdm_response->header.request_response_code != + SPDM_KEY_UPDATE_ACK) || + (spdm_response->header.param1 != spdm_request->header.param1) || + (spdm_response->header.param2 != spdm_request->header.param2)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + } + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + if (!single_direction) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_activate_update_session_data_key[%x] Responder old\n", + session_id)); + result = libspdm_activate_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, false); + if (!result) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + libspdm_release_receiver_buffer (spdm_context); + return status; + } + + if (!single_direction) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_activate_update_session_data_key[%x] Responder new\n", + session_id, LIBSPDM_KEY_UPDATE_ACTION_RESPONDER)); + result = libspdm_activate_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, true); + if (!result) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_create_update_session_data_key[%x] Requester\n", + session_id)); + result = libspdm_create_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_REQUESTER); + if (!result) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_activate_update_session_data_key[%x] Requester new\n", + session_id)); + result = libspdm_activate_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_REQUESTER, true); + if (!result) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + libspdm_release_receiver_buffer (spdm_context); + } + + *key_updated = true; + + + /* Verify key*/ + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_KEY_UPDATE; + spdm_request->header.param1 = + SPDM_KEY_UPDATE_OPERATIONS_TABLE_VERIFY_NEW_KEY; + spdm_request->header.param2 = 1; + if(!libspdm_get_random_number(sizeof(spdm_request->header.param2), + &spdm_request->header.param2)) { + libspdm_release_sender_buffer (spdm_context); + return LIBSPDM_STATUS_LOW_ENTROPY; + } + spdm_request_size = sizeof(spdm_key_update_request_t); + + status = libspdm_send_spdm_request(spdm_context, &session_id, + spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + return status; + } + if (spdm_response_size < sizeof(spdm_message_header_t)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, &session_id, + &spdm_response_size, (void **)&spdm_response, + SPDM_KEY_UPDATE, SPDM_KEY_UPDATE_ACK, + sizeof(libspdm_key_update_response_mine_t)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); + libspdm_release_receiver_buffer (spdm_context); + return status; + } + } + + if ((spdm_response->header.request_response_code != + SPDM_KEY_UPDATE_ACK) || + (spdm_response->header.param1 != spdm_request->header.param1) || + (spdm_response->header.param2 != spdm_request->header.param2)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Success\n", session_id)); + + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_SUCCESS; +} + +libspdm_return_t libspdm_key_update(void *context, uint32_t session_id, + bool single_direction) +{ + libspdm_context_t *spdm_context; + size_t retry; + libspdm_return_t status; + bool key_updated; + + spdm_context = context; + key_updated = false; + spdm_context->crypto_request = true; + retry = spdm_context->retry_times; + do { + status = libspdm_try_key_update(context, session_id, + single_direction, &key_updated); + if (LIBSPDM_STATUS_BUSY_PEER != status) { + return status; + } + } while (retry-- != 0); + + return status; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c new file mode 100644 index 0000000000..496b97ff1c --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c @@ -0,0 +1,531 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint16_t length; + uint8_t measurement_specification; + uint8_t other_params_support; + uint32_t base_asym_algo; + uint32_t base_hash_algo; + uint8_t reserved2[12]; + uint8_t ext_asym_count; + uint8_t ext_hash_count; + uint16_t reserved3; + spdm_negotiate_algorithms_common_struct_table_t struct_table[4]; +} libspdm_negotiate_algorithms_request_mine_t; + +typedef struct { + spdm_message_header_t header; + uint16_t length; + uint8_t measurement_specification_sel; + uint8_t other_params_selection; + uint32_t measurement_hash_algo; + uint32_t base_asym_sel; + uint32_t base_hash_sel; + uint8_t reserved2[12]; + uint8_t ext_asym_sel_count; + uint8_t ext_hash_sel_count; + uint16_t reserved3; + uint32_t ext_asym_sel; + uint32_t ext_hash_sel; + spdm_negotiate_algorithms_common_struct_table_t struct_table[4]; +} libspdm_algorithms_response_max_t; +#pragma pack() + +/** + * This function sends NEGOTIATE_ALGORITHMS and receives ALGORITHMS. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval LIBSPDM_STATUS_SUCCESS + * NEGOTIATE_ALGORITHMS was sent and ALGORITHMS was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send NEGOTIATE_ALGORITHMS due to Requester's state. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the ALGORITHMS response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The ALGORITHMS response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_NEGOTIATION_FAIL + * The Requester and Responder could not agree on mutual algorithms. + * Note: This return value may be removed in the future. + **/ +static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm_context) +{ + libspdm_return_t status; + libspdm_negotiate_algorithms_request_mine_t *spdm_request; + size_t spdm_request_size; + libspdm_algorithms_response_max_t *spdm_response; + size_t spdm_response_size; + uint32_t algo_size; + size_t index; + spdm_negotiate_algorithms_common_struct_table_t *struct_table; + uint8_t fixed_alg_size; + uint8_t ext_alg_count; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + uint8_t alg_type_pre; + + /* -=[Verify State Phase]=- */ + if (spdm_context->connection_info.connection_state != + LIBSPDM_CONNECTION_STATE_AFTER_CAPABILITIES) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_NEGOTIATE_ALGORITHMS); + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + libspdm_zero_mem(spdm_request, sizeof(libspdm_negotiate_algorithms_request_mine_t)); + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + spdm_request->length = sizeof(libspdm_negotiate_algorithms_request_mine_t); + /* Number of Algorithms Structure Tables*/ + spdm_request->header.param1 = 4; + } else { + spdm_request->length = sizeof(libspdm_negotiate_algorithms_request_mine_t) - + sizeof(spdm_request->struct_table); + spdm_request->header.param1 = 0; + } + spdm_request->header.request_response_code = SPDM_NEGOTIATE_ALGORITHMS; + spdm_request->header.param2 = 0; + spdm_request->measurement_specification = + spdm_context->local_context.algorithm.measurement_spec; + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_request->other_params_support = + spdm_context->local_context.algorithm.other_params_support; + } + spdm_request->base_asym_algo = spdm_context->local_context.algorithm.base_asym_algo; + spdm_request->base_hash_algo = spdm_context->local_context.algorithm.base_hash_algo; + spdm_request->ext_asym_count = 0; + spdm_request->ext_hash_count = 0; + spdm_request->struct_table[0].alg_type = SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE; + spdm_request->struct_table[0].alg_count = 0x20; + spdm_request->struct_table[0].alg_supported = + spdm_context->local_context.algorithm.dhe_named_group; + spdm_request->struct_table[1].alg_type = SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD; + spdm_request->struct_table[1].alg_count = 0x20; + spdm_request->struct_table[1].alg_supported = + spdm_context->local_context.algorithm.aead_cipher_suite; + spdm_request->struct_table[2].alg_type = + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG; + spdm_request->struct_table[2].alg_count = 0x20; + spdm_request->struct_table[2].alg_supported = + spdm_context->local_context.algorithm.req_base_asym_alg; + spdm_request->struct_table[3].alg_type = + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE; + spdm_request->struct_table[3].alg_count = 0x20; + spdm_request->struct_table[3].alg_supported = + spdm_context->local_context.algorithm.key_schedule; + spdm_request_size = spdm_request->length; + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, NULL, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response(spdm_context, NULL, &spdm_response_size, + (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_simple_error_response(spdm_context, spdm_response->header.param1); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_ALGORITHMS) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < sizeof(spdm_algorithms_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (!libspdm_onehot0(spdm_response->measurement_specification_sel)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (!libspdm_onehot0(spdm_response->measurement_hash_algo)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (!libspdm_onehot0(spdm_response->base_asym_sel)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (!libspdm_onehot0(spdm_response->base_hash_sel)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->ext_asym_sel_count > 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->ext_hash_sel_count > 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response_size < + sizeof(spdm_algorithms_response_t) + + sizeof(uint32_t) * spdm_response->ext_asym_sel_count + + sizeof(uint32_t) * spdm_response->ext_hash_sel_count + + sizeof(spdm_negotiate_algorithms_common_struct_table_t) * spdm_response->header.param1) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + struct_table = + (void *)((size_t)spdm_response + + sizeof(spdm_algorithms_response_t) + + sizeof(uint32_t) * spdm_response->ext_asym_sel_count + + sizeof(uint32_t) * spdm_response->ext_hash_sel_count); + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + alg_type_pre = struct_table->alg_type; + /* header.param1 is implictly checked through spdm_response_size. */ + for (index = 0; index < spdm_response->header.param1; index++) { + if ((size_t)spdm_response + spdm_response_size < (size_t)struct_table) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if ((size_t)spdm_response + spdm_response_size - (size_t)struct_table < + sizeof(spdm_negotiate_algorithms_common_struct_table_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if ((struct_table->alg_type < SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE) || + (struct_table->alg_type > + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + /* AlgType shall monotonically increase for subsequent entries. */ + if ((index != 0) && (struct_table->alg_type <= alg_type_pre)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + alg_type_pre = struct_table->alg_type; + fixed_alg_size = (struct_table->alg_count >> 4) & 0xF; + ext_alg_count = struct_table->alg_count & 0xF; + if (fixed_alg_size != 2) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (ext_alg_count > 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (!libspdm_onehot0(struct_table->alg_supported)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if ((size_t)spdm_response + spdm_response_size - + (size_t)struct_table - sizeof(spdm_negotiate_algorithms_common_struct_table_t) < + sizeof(uint32_t) * ext_alg_count) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + struct_table = + (void *)((size_t)struct_table + + sizeof(spdm_negotiate_algorithms_common_struct_table_t) + + sizeof(uint32_t) * ext_alg_count); + } + } + + spdm_response_size = (size_t)struct_table - (size_t)spdm_response; + if (spdm_response_size != spdm_response->length) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + /* -=[Process Response Phase]=- */ + status = libspdm_append_message_a(spdm_context, spdm_request, spdm_request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + status = libspdm_append_message_a(spdm_context, spdm_response, spdm_response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + status = LIBSPDM_STATUS_BUFFER_FULL; + goto receive_done; + } + + spdm_context->connection_info.algorithm.measurement_spec = + spdm_response->measurement_specification_sel; + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + spdm_context->connection_info.algorithm.other_params_support = + spdm_response->other_params_selection; + } + spdm_context->connection_info.algorithm.measurement_hash_algo = + spdm_response->measurement_hash_algo; + spdm_context->connection_info.algorithm.base_asym_algo = spdm_response->base_asym_sel; + spdm_context->connection_info.algorithm.base_hash_algo = spdm_response->base_hash_sel; + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP) && + (spdm_request->measurement_specification != 0)) { + if (spdm_context->connection_info.algorithm.measurement_spec != + SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + algo_size = libspdm_get_measurement_hash_size( + spdm_context->connection_info.algorithm.measurement_hash_algo); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP)) { + algo_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.base_hash_algo & + spdm_context->local_context.algorithm.base_hash_algo) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, 0, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP)) { + algo_size = libspdm_get_asym_signature_size( + spdm_context->connection_info.algorithm.base_asym_algo); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.base_asym_algo & + spdm_context->local_context.algorithm.base_asym_algo) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + struct_table = + (void *)((size_t)spdm_response + + sizeof(spdm_algorithms_response_t) + + sizeof(uint32_t) * spdm_response->ext_asym_sel_count + + sizeof(uint32_t) * spdm_response->ext_hash_sel_count); + for (index = 0; index < spdm_response->header.param1; index++) { + switch (struct_table->alg_type) { + case SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE: + spdm_context->connection_info.algorithm.dhe_named_group = + struct_table->alg_supported; + break; + case SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD: + spdm_context->connection_info.algorithm.aead_cipher_suite = + struct_table->alg_supported; + break; + case SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG: + spdm_context->connection_info.algorithm.req_base_asym_alg = + struct_table->alg_supported; + break; + case SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE: + spdm_context->connection_info.algorithm.key_schedule = + struct_table->alg_supported; + break; + } + ext_alg_count = struct_table->alg_count & 0xF; + struct_table = + (void *)((size_t)struct_table + + sizeof(spdm_negotiate_algorithms_common_struct_table_t) + + sizeof(uint32_t) * ext_alg_count); + } + + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP)) { + algo_size = libspdm_get_dhe_pub_key_size( + spdm_context->connection_info.algorithm.dhe_named_group); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.dhe_named_group & + spdm_context->local_context.algorithm.dhe_named_group) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MAC_CAP)) { + algo_size = libspdm_get_aead_key_size( + spdm_context->connection_info.algorithm.aead_cipher_suite); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.aead_cipher_suite & + spdm_context->local_context.algorithm.aead_cipher_suite) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MUT_AUTH_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MUT_AUTH_CAP)) { + algo_size = libspdm_get_req_asym_signature_size( + spdm_context->connection_info.algorithm.req_base_asym_alg); + if (algo_size == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.req_base_asym_alg & + spdm_context->local_context.algorithm.req_base_asym_alg) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + if (libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP) || + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP)) { + if (spdm_context->connection_info.algorithm.key_schedule != + SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if ((spdm_context->connection_info.algorithm.key_schedule & + spdm_context->local_context.algorithm.key_schedule) == 0) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if ((spdm_context->connection_info.algorithm.other_params_support & + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_MASK) != + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_1) { + status = LIBSPDM_STATUS_NEGOTIATION_FAIL; + goto receive_done; + } + } + } + } else { + spdm_context->connection_info.algorithm.dhe_named_group = 0; + spdm_context->connection_info.algorithm.aead_cipher_suite = 0; + spdm_context->connection_info.algorithm.req_base_asym_alg = 0; + spdm_context->connection_info.algorithm.key_schedule = 0; + } + + /* -=[Update State Phase]=- */ + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_NEGOTIATED; + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_negotiate_algorithms(libspdm_context_t *spdm_context) +{ + size_t retry; + libspdm_return_t status; + + spdm_context->crypto_request = false; + retry = spdm_context->retry_times; + do { + status = libspdm_try_negotiate_algorithms(spdm_context); + if (status != LIBSPDM_STATUS_BUSY_PEER) { + return status; + } + } while (retry-- != 0); + + return status; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c new file mode 100644 index 0000000000..6272dff9ba --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c @@ -0,0 +1,685 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +libspdm_return_t libspdm_send_request(void *context, const uint32_t *session_id, + bool is_app_message, + size_t request_size, void *request) +{ + libspdm_context_t *spdm_context; + libspdm_return_t status; + uint8_t *message; + size_t message_size; + uint64_t timeout; + uint8_t *scratch_buffer; + size_t scratch_buffer_size; + size_t transport_header_size; + uint8_t *sender_buffer; + size_t sender_buffer_size; + + spdm_context = context; + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_send_spdm_request[%x] (0x%x): \n", + (session_id != NULL) ? *session_id : 0x0, request_size)); + LIBSPDM_INTERNAL_DUMP_HEX(request, request_size); + + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + libspdm_get_scratch_buffer(spdm_context, (void**) &scratch_buffer, &scratch_buffer_size); + libspdm_get_sender_buffer(spdm_context, (void**) &sender_buffer, &sender_buffer_size); + + /* This is a problem because original code assumes request is in the sender buffer, + * when it can really be using the scratch space for chunking. + * Did not want to modify ally request handlers to pass this information, + * so just making the determination here by examining scratch/sender buffers. + * This may be something that should be refactored in the future. */ + #if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) + if ((uint8_t*) request >= sender_buffer && + (uint8_t*)request < sender_buffer + sender_buffer_size) { + message = sender_buffer; + message_size = sender_buffer_size; + } + else { + if ((uint8_t*)request >= scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET + && (uint8_t*)request < scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET + + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY) { + message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; + message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + } else if ((uint8_t*)request >= + scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET + && (uint8_t*)request < + scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET + + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY) { + message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; + message_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + } + } + #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + message = sender_buffer; + message_size = sender_buffer_size; + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + + if (session_id != NULL) { + /* For secure message, message is in sender buffer, we need copy it to scratch buffer. + * transport_message is always in sender buffer. */ + + libspdm_copy_mem (scratch_buffer + transport_header_size, + scratch_buffer_size - transport_header_size, + request, request_size); + request = scratch_buffer + transport_header_size; + } + + /* backup it to last_spdm_request, because the caller wants to compare it with response */ + if (((const spdm_message_header_t *)request)->request_response_code != SPDM_RESPOND_IF_READY + && ((const spdm_message_header_t *)request)->request_response_code != SPDM_CHUNK_GET + && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_SEND) { + libspdm_copy_mem (spdm_context->last_spdm_request, + sizeof(spdm_context->last_spdm_request), + request, + request_size + ); + spdm_context->last_spdm_request_size = request_size; + } + + status = spdm_context->transport_encode_message( + spdm_context, session_id, is_app_message, true, request_size, + request, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "transport_encode_message status - %p\n", + status)); + return status; + } + + timeout = spdm_context->local_context.capability.rtt; + + status = spdm_context->send_message(spdm_context, message_size, message, + timeout); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_send_spdm_request[%x] status - %p\n", + (session_id != NULL) ? *session_id : 0x0, status)); + } + + return status; +} + +libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session_id, + bool is_app_message, + size_t *response_size, + void **response) +{ + libspdm_context_t *spdm_context; + void *temp_session_context; + libspdm_return_t status; + uint8_t *message; + size_t message_size; + uint32_t *message_session_id; + bool is_message_app_message; + uint64_t timeout; + size_t transport_header_size; + uint8_t *scratch_buffer; + size_t scratch_buffer_size; + void *backup_response; + size_t backup_response_size; + bool reset_key_update; + bool result; + + spdm_context = context; + + if (spdm_context->crypto_request) { + timeout = spdm_context->local_context.capability.rtt + + ((uint64_t)2 << spdm_context->connection_info.capability.ct_exponent); + } else { + timeout = spdm_context->local_context.capability.rtt + + spdm_context->local_context.capability.st1; + } + + message = *response; + message_size = *response_size; + status = spdm_context->receive_message(spdm_context, &message_size, + (void **)&message, timeout); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] status - %p\n", + (session_id != NULL) ? *session_id : 0x0, status)); + return status; + } + + message_session_id = NULL; + is_message_app_message = false; + + /* always use scratch buffer to response. + * if it is secured message, this scratch buffer will be used. + * if it is normal message, the response ptr will point to receiver buffer. */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + libspdm_get_scratch_buffer (spdm_context, (void **)&scratch_buffer, &scratch_buffer_size); + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + *response = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_OFFSET + + transport_header_size; + *response_size = LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY - transport_header_size; + #else + *response = scratch_buffer + transport_header_size; + *response_size = scratch_buffer_size - transport_header_size; + #endif + + backup_response = *response; + backup_response_size = *response_size; + + status = spdm_context->transport_decode_message( + spdm_context, &message_session_id, &is_message_app_message, + false, message_size, message, response_size, response); + + reset_key_update = false; + temp_session_context = NULL; + + if (status == LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE) { + /* Failed to decode, but have backup keys. Try rolling back before aborting. + * message_session_id must be valid for us to have attempted decryption. */ + if (message_session_id == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + temp_session_context = libspdm_get_secured_message_context_via_session_id( + spdm_context, *message_session_id); + if (temp_session_context == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + result = libspdm_activate_update_session_data_key( + temp_session_context, LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, false); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + /* Retry decoding message with backup Requester key. + * Must reset some of the parameters in case they were modified */ + message_session_id = NULL; + is_message_app_message = false; + *response = backup_response; + *response_size = backup_response_size; + status = spdm_context->transport_decode_message( + spdm_context, &message_session_id, &is_message_app_message, + false, message_size, message, response_size, response); + + reset_key_update = true; + } + + if (session_id != NULL) { + if (message_session_id == NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] GetSessionId - NULL\n", + (session_id != NULL) ? *session_id : 0x0)); + goto error; + } + if (*message_session_id != *session_id) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] GetSessionId - %x\n", + (session_id != NULL) ? *session_id : 0x0, + *message_session_id)); + goto error; + } + } else { + if (message_session_id != NULL) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] GetSessionId - %x\n", + (session_id != NULL) ? *session_id : 0x0, + *message_session_id)); + goto error; + } + } + + if ((is_app_message && !is_message_app_message) || + (!is_app_message && is_message_app_message)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] app_message mismatch\n", + (session_id != NULL) ? *session_id : 0x0)); + goto error; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_receive_spdm_response[%x] (0x%x): \n", + (session_id != NULL) ? *session_id : 0x0, *response_size)); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] status - %p\n", + (session_id != NULL) ? *session_id : 0x0, status)); + } else { + LIBSPDM_INTERNAL_DUMP_HEX(*response, *response_size); + } + + /* Handle special case: + * If the Responder returns RESPONSE_NOT_READY error to KEY_UPDATE, the Requester needs + * to activate backup key to parse the error. Then later the Responder will return SUCCESS, + * the Requester needs new key. So we need to restore the environment by + * libspdm_create_update_session_data_key() again.*/ + if (reset_key_update) + { + /* temp_session_context and message_session_id must necessarily + * be valid for us to reach here. */ + if (temp_session_context == NULL || message_session_id == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + result = libspdm_create_update_session_data_key( + temp_session_context, LIBSPDM_KEY_UPDATE_ACTION_RESPONDER); + if (!result) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + } + + return status; + +error: + if (spdm_context->last_spdm_error.error_code == SPDM_ERROR_CODE_DECRYPT_ERROR) { + return LIBSPDM_STATUS_SESSION_MSG_ERROR; + } else { + return LIBSPDM_STATUS_RECEIVE_FAIL; + } +} + +#if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) +libspdm_return_t libspdm_handle_large_request( + libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t request_size, void *request) +{ + libspdm_return_t status; + + spdm_chunk_send_request_t *spdm_request; + size_t spdm_request_size; + spdm_chunk_send_ack_response_t *spdm_response; + uint8_t *message; + size_t message_size; + void *response; + size_t response_size; + size_t transport_header_size; + + uint8_t *scratch_buffer; + size_t scratch_buffer_size; + + uint8_t *chunk_ptr; + size_t copy_size; + libspdm_chunk_info_t *send_info; + + /* Fail if requester or responder does not support chunk cap */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP)) { + return LIBSPDM_STATUS_ERROR_PEER; + } + + /* now we can get sender buffer */ + transport_header_size = spdm_context->transport_get_header_size(spdm_context); + + libspdm_get_scratch_buffer(spdm_context, (void**) &scratch_buffer, &scratch_buffer_size); + LIBSPDM_ASSERT(scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); + + /* Temporary send/receive buffers for chunking are in the scratch space */ + message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; + message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + + send_info = &spdm_context->chunk_context.send; + send_info->chunk_in_use = true; + + /* The first section of the scratch + * buffer may be used for other purposes. Use only after that section. */ + send_info->large_message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET; + send_info->large_message_capacity = LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY; + + libspdm_zero_mem(send_info->large_message, send_info->large_message_capacity); + libspdm_copy_mem(send_info->large_message, send_info->large_message_capacity, + request, request_size); + + send_info->large_message_size = request_size; + send_info->chunk_bytes_transferred = 0; + send_info->chunk_seq_no = 0; + request = NULL; /* Invalidate to prevent accidental use. */ + request_size = 0; + + do { + LIBSPDM_ASSERT(send_info->large_message_capacity >= transport_header_size); + spdm_request = (spdm_chunk_send_request_t*) ((uint8_t*) message + transport_header_size); + spdm_request_size = message_size - transport_header_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version(spdm_context); + spdm_request->header.request_response_code = SPDM_CHUNK_SEND; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = send_info->chunk_handle; + spdm_request->chunk_seq_no = send_info->chunk_seq_no; + spdm_request->reserved = 0; + chunk_ptr = (uint8_t*) (spdm_request + 1); + + if (spdm_context->connection_info.capability.data_transfer_size + - sizeof(spdm_chunk_send_request_t) + < (send_info->large_message_size - send_info->chunk_bytes_transferred)) { + + copy_size = spdm_context->connection_info.capability.data_transfer_size + - sizeof(spdm_chunk_send_request_t); + } + else { + copy_size = (send_info->large_message_size - send_info->chunk_bytes_transferred); + } + + if (send_info->chunk_seq_no == 0) { + *(uint32_t*) (spdm_request + 1) = (uint32_t) send_info->large_message_size; + chunk_ptr += sizeof(uint32_t); + copy_size -= sizeof(uint32_t); + } + + spdm_request->chunk_size = (uint32_t) copy_size; + + libspdm_copy_mem( + chunk_ptr, spdm_request_size - ((uint8_t*) spdm_request - (uint8_t*) message), + (uint8_t*)send_info->large_message + send_info->chunk_bytes_transferred, copy_size); + + send_info->chunk_bytes_transferred += copy_size; + if (send_info->chunk_bytes_transferred >= send_info->large_message_size) { + spdm_request->header.param1 |= SPDM_CHUNK_SEND_REQUEST_ATTRIBUTE_LAST_CHUNK; + } + + spdm_request_size = (chunk_ptr + copy_size) - (uint8_t*)spdm_request; + status = libspdm_send_request( + spdm_context, session_id, false, + spdm_request_size, spdm_request); + + spdm_request = NULL; + spdm_request_size = 0; + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + break; + } + + response = message; + response_size = message_size; + + libspdm_zero_mem(response, response_size); + + status = libspdm_receive_response( + spdm_context, session_id, false, + &response_size, &response); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + break; + } + spdm_response = (void*) (response); + + if (response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (spdm_response->header.spdm_version != libspdm_get_connection_version(spdm_context)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + + if (spdm_response->header.request_response_code == SPDM_ERROR + && spdm_response->header.param1 == SPDM_ERROR_CODE_LARGE_RESPONSE) { + + /* It is possible that the CHUNK_SEND_ACK + chunk response is larger + * than the DATA_TRANSFER_SIZE. In this case an ERROR_LARGE_RESPONSE + * is returned directly in the response buffer rather than part of + * the CHUNK_SEND_ACK. Store this error response in scratch buffer + * to be handled when reading response. Also note that in this case + * of large response, the CHUNK_SEND_ACK portion is not sent. + * Only the response portion that requires the CHUNK_GET is sent */ + if (response_size < send_info->large_message_capacity) { + libspdm_copy_mem( + send_info->large_message, send_info->large_message_capacity, + spdm_response, response_size); + send_info->large_message_size = response_size; + break; + } + else { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + } else { + if (spdm_response->header.request_response_code != SPDM_CHUNK_SEND_ACK) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + + if (response_size < sizeof(spdm_chunk_send_ack_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if (spdm_response->header.param1 + & SPDM_CHUNK_SEND_ACK_RESPONSE_ATTRIBUTE_EARLY_ERROR_DETECTED) { + + /* Store the error response in scratch buffer to be read by + * libspdm_receive_spdm_response and returned to its caller + * and handled in the error response handling flow */ + libspdm_copy_mem( + send_info->large_message, + send_info->large_message_capacity, + (uint8_t*) (spdm_response + 1), + response_size - sizeof(spdm_chunk_send_ack_response_t)); + + send_info->large_message_size = + (response_size - sizeof(spdm_chunk_send_ack_response_t)); + + status = LIBSPDM_STATUS_SUCCESS; + break; + } + if (spdm_response->header.param2 != send_info->chunk_handle) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (send_info->chunk_seq_no != spdm_response->chunk_seq_no) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + + chunk_ptr = (uint8_t*) (spdm_response + 1); + send_info->chunk_seq_no++; + + if (send_info->chunk_bytes_transferred >= send_info->large_message_size) { + + /* All bytes have been transferred. Store response in scratch buffer + * to be read by libspdm_receive_spdm_response */ + libspdm_copy_mem( + send_info->large_message, send_info->large_message_capacity, + chunk_ptr, response_size - sizeof(spdm_chunk_send_ack_response_t)); + send_info->large_message_size = + (response_size - sizeof(spdm_chunk_send_ack_response_t)); + break; + } + } + + } while (LIBSPDM_STATUS_IS_SUCCESS(status) + && send_info->chunk_bytes_transferred < send_info->large_message_size); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + + send_info->chunk_in_use = false; + send_info->chunk_handle++; /* Implicit wrap-around*/ + send_info->chunk_seq_no = 0; + send_info->chunk_bytes_transferred = 0; + send_info->large_message = NULL; + send_info->large_message_size = 0; + } + + return status; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + +libspdm_return_t libspdm_send_spdm_request(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t request_size, void *request) +{ + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + libspdm_return_t status; + + if ((spdm_context->connection_info.capability.data_transfer_size != 0) && + (request_size > spdm_context->connection_info.capability.data_transfer_size) && + !libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP)) { + return LIBSPDM_STATUS_SEND_FAIL; + } + + if ((session_id != NULL) && + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + session_info = libspdm_get_session_info_via_session_id( + spdm_context, *session_id); + LIBSPDM_ASSERT(session_info != NULL); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if ((session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) && + !session_info->use_psk) { + session_id = NULL; + } + } + + if (((const spdm_message_header_t*) request)->request_response_code != SPDM_GET_VERSION + && ((const spdm_message_header_t*) request)->request_response_code != SPDM_GET_CAPABILITIES + && spdm_context->connection_info.capability.data_transfer_size != 0 + && request_size > spdm_context->connection_info.capability.data_transfer_size) { + + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* libspdm_send_request is not called with the original request in this flow. + * This leads to the last_spdm_request field not having the original request value. + * The caller assumes the request has been copied to last_spdm_request, + * so that it can compare last_spdm_request's fields with response fields + * Therefore the request must be copied to last_spdm_request here. */ + + if (((const spdm_message_header_t*) request)->request_response_code != SPDM_RESPOND_IF_READY + && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_GET + && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_SEND) { + libspdm_copy_mem( + spdm_context->last_spdm_request, sizeof(spdm_context->last_spdm_request), + request, request_size); + spdm_context->last_spdm_request_size = request_size; + } + + status = libspdm_handle_large_request( + spdm_context, session_id, request_size, request); + #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP*/ + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP*/ + } + else + { + status = libspdm_send_request(spdm_context, session_id, false, request_size, request); + } + + #if LIBSPDM_ENABLE_MSG_LOG + if (status == LIBSPDM_STATUS_SUCCESS) { + libspdm_append_msg_log(spdm_context, request, request_size); + } + #endif + + return status; +} + +libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, + const uint32_t *session_id, + size_t *response_size, + void **response) +{ + libspdm_return_t status; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + + #if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) + spdm_message_header_t *spdm_response; + size_t response_capacity; + libspdm_chunk_info_t *send_info; + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + + if ((session_id != NULL) && + libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP)) { + session_info = libspdm_get_session_info_via_session_id( + spdm_context, *session_id); + LIBSPDM_ASSERT(session_info != NULL); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if ((session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) && + !session_info->use_psk) { + session_id = NULL; + } + } + + #if !(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) && !(LIBSPDM_ENABLE_CHUNK_CAP) + status = libspdm_receive_response(spdm_context, session_id, false, response_size, response); + #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + send_info = &spdm_context->chunk_context.send; + if (send_info->chunk_in_use) { + libspdm_copy_mem(*response, *response_size, + send_info->large_message, send_info->large_message_size); + *response_size = send_info->large_message_size; + response_capacity = send_info->large_message_capacity; + + /* This response may either be an actual response or ERROR_LARGE_RESPONSE, + * the latter which should be handled in the large response handler. */ + + send_info->chunk_in_use = false; + send_info->chunk_handle++; /* Implicit wrap-around*/ + send_info->chunk_seq_no = 0; + send_info->chunk_bytes_transferred = 0; + send_info->large_message = NULL; + send_info->large_message_size = 0; + send_info->large_message_capacity = 0; + status = LIBSPDM_STATUS_SUCCESS; + } + else { + response_capacity = *response_size; + status = libspdm_receive_response(spdm_context, session_id, false, + response_size, response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } + + spdm_response = (spdm_message_header_t*) (*response); + + if (*response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + if (spdm_response->request_response_code == SPDM_ERROR + && spdm_response->param1 == SPDM_ERROR_CODE_LARGE_RESPONSE) { + + status = libspdm_handle_error_large_response( + spdm_context, session_id, + response_size, (void*) spdm_response, response_capacity); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + if (*response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + /* Per the spec, SPDM_VERSION and SPDM_CAPABILITIES shall not be chunked + * and should be an unexpected error. */ + if (spdm_response->request_response_code == SPDM_VERSION || + spdm_response->request_response_code == SPDM_CAPABILITIES + ) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + +receive_done: + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ + + return status; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c new file mode 100644 index 0000000000..90c412ece7 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c @@ -0,0 +1,398 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_secured_message_lib.h" + +/** + * Return the size in bytes of a single SPDM secured message context. + * + * @return the size in bytes of a single SPDM secured message context. + **/ +size_t libspdm_secured_message_get_context_size(void) +{ + size_t size; + + size = sizeof(libspdm_secured_message_context_t); + LIBSPDM_ASSERT (size == LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE); + return size; +} + +/** + * Initialize an SPDM secured message context. + * + * The size in bytes of the spdm_secured_message_context can be returned by libspdm_secured_message_get_context_size. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + */ +void libspdm_secured_message_init_context(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_zero_mem(secured_message_context, sizeof(libspdm_secured_message_context_t)); +} + +/** + * Set use_psk to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param use_psk Indicate if the SPDM session use PSK. + */ +void libspdm_secured_message_set_use_psk(void *spdm_secured_message_context, bool use_psk) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->use_psk = use_psk; +} + +/** + * Set session_state to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_state Indicate the SPDM session state. + */ +void libspdm_secured_message_set_session_state( + void *spdm_secured_message_context, + libspdm_session_state_t session_state) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->session_state = session_state; + + if (session_state == LIBSPDM_SESSION_STATE_ESTABLISHED) { + /* session handshake key should be zeroized after handshake phase. */ + libspdm_clear_handshake_secret(secured_message_context); + libspdm_clear_master_secret(secured_message_context); + } +} + +/** + * Return session_state of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return the SPDM session state. + */ +libspdm_session_state_t +libspdm_secured_message_get_session_state(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return secured_message_context->session_state; +} + +/** + * Set session_type to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_type Indicate the SPDM session type. + */ +void libspdm_secured_message_set_session_type(void *spdm_secured_message_context, + libspdm_session_type_t session_type) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->session_type = session_type; +} + +/** + * Set algorithm to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param base_hash_algo Indicate the negotiated base_hash_algo for the SPDM session. + * @param dhe_named_group Indicate the negotiated dhe_named_group for the SPDM session. + * @param aead_cipher_suite Indicate the negotiated aead_cipher_suite for the SPDM session. + * @param key_schedule Indicate the negotiated key_schedule for the SPDM session. + */ +void libspdm_secured_message_set_algorithms(void *spdm_secured_message_context, + const spdm_version_number_t version, + const spdm_version_number_t secured_message_version, + uint32_t base_hash_algo, + uint16_t dhe_named_group, + uint16_t aead_cipher_suite, + uint16_t key_schedule) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->version = version; + secured_message_context->secured_message_version = secured_message_version; + secured_message_context->base_hash_algo = base_hash_algo; + secured_message_context->dhe_named_group = dhe_named_group; + secured_message_context->aead_cipher_suite = aead_cipher_suite; + secured_message_context->key_schedule = key_schedule; + + secured_message_context->hash_size = + libspdm_get_hash_size(secured_message_context->base_hash_algo); + secured_message_context->dhe_key_size = libspdm_get_dhe_pub_key_size( + secured_message_context->dhe_named_group); + secured_message_context->aead_key_size = libspdm_get_aead_key_size( + secured_message_context->aead_cipher_suite); + secured_message_context->aead_iv_size = libspdm_get_aead_iv_size( + secured_message_context->aead_cipher_suite); + secured_message_context->aead_tag_size = libspdm_get_aead_tag_size( + secured_message_context->aead_cipher_suite); +} + +/** + * Set the psk_hint to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param psk_hint Indicate the PSK hint. + * @param psk_hint_size The size in bytes of the PSK hint. + */ +void libspdm_secured_message_set_psk_hint(void *spdm_secured_message_context, + const void *psk_hint, + size_t psk_hint_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + if ((psk_hint != NULL) && (psk_hint_size > 0)) { + secured_message_context->psk_hint_size = psk_hint_size; + libspdm_copy_mem(secured_message_context->psk_hint, + LIBSPDM_PSK_MAX_HINT_LENGTH, + psk_hint, + psk_hint_size); + } +} + +/** + * Import the DHE Secret to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param dhe_secret Indicate the DHE secret. + * @param dhe_secret_size The size in bytes of the DHE secret. + * + * @retval RETURN_SUCCESS DHE Secret is imported. + */ +bool libspdm_secured_message_import_dhe_secret(void *spdm_secured_message_context, + const void *dhe_secret, + size_t dhe_secret_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + if (dhe_secret_size > secured_message_context->dhe_key_size) { + return false; + } + secured_message_context->dhe_key_size = dhe_secret_size; + libspdm_copy_mem(secured_message_context->master_secret.dhe_secret, + sizeof(secured_message_context->master_secret.dhe_secret), + dhe_secret, dhe_secret_size); + return true; +} + +bool libspdm_secured_message_export_master_secret( + void *spdm_secured_message_context, void *export_master_secret, + size_t *export_master_secret_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + if (*export_master_secret_size > secured_message_context->hash_size) { + *export_master_secret_size = secured_message_context->hash_size; + } + + libspdm_copy_mem(export_master_secret, *export_master_secret_size, + secured_message_context->export_master_secret, + *export_master_secret_size); + + return true; +} + +void libspdm_secured_message_clear_export_master_secret(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + LIBSPDM_ASSERT(spdm_secured_message_context != NULL); + + secured_message_context = spdm_secured_message_context; + + libspdm_zero_mem(secured_message_context->export_master_secret, + sizeof(secured_message_context->export_master_secret)); +} + +/** + * Export the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * + * @retval RETURN_SUCCESS session_keys are exported. + */ +bool libspdm_secured_message_export_session_keys(void *spdm_secured_message_context, + void *session_keys, + size_t *session_keys_size) +{ + libspdm_secured_message_context_t *secured_message_context; + size_t struct_size; + libspdm_secure_session_keys_struct_t *session_keys_struct; + uint8_t *ptr; + + secured_message_context = spdm_secured_message_context; + struct_size = sizeof(libspdm_secure_session_keys_struct_t) + + (secured_message_context->aead_key_size + + secured_message_context->aead_iv_size + sizeof(uint64_t)) * 2; + + if (*session_keys_size < struct_size) { + *session_keys_size = struct_size; + return false; + } + + session_keys_struct = session_keys; + session_keys_struct->version = LIBSPDM_SECURE_SESSION_KEYS_STRUCT_VERSION; + session_keys_struct->aead_key_size = (uint32_t)secured_message_context->aead_key_size; + session_keys_struct->aead_iv_size = (uint32_t)secured_message_context->aead_iv_size; + + ptr = (void *)(session_keys_struct + 1); + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + secured_message_context->application_secret.request_data_encryption_key, + secured_message_context->aead_key_size); + ptr += secured_message_context->aead_key_size; + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + secured_message_context->application_secret.request_data_salt, + secured_message_context->aead_iv_size); + ptr += secured_message_context->aead_iv_size; + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + &secured_message_context->application_secret.request_data_sequence_number, + sizeof(uint64_t)); + ptr += sizeof(uint64_t); + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + secured_message_context->application_secret.response_data_encryption_key, + secured_message_context->aead_key_size); + ptr += secured_message_context->aead_key_size; + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + secured_message_context->application_secret.response_data_salt, + secured_message_context->aead_iv_size); + ptr += secured_message_context->aead_iv_size; + libspdm_copy_mem(ptr, + *session_keys_size - (ptr - (uint8_t*)session_keys), + &secured_message_context->application_secret.response_data_sequence_number, + sizeof(uint64_t)); + ptr += sizeof(uint64_t); + return true; +} + +/** + * Import the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * + * @retval RETURN_SUCCESS session_keys are imported. + */ +bool +libspdm_secured_message_import_session_keys(void *spdm_secured_message_context, + const void *session_keys, + size_t session_keys_size) +{ + libspdm_secured_message_context_t *secured_message_context; + size_t struct_size; + const libspdm_secure_session_keys_struct_t *session_keys_struct; + const uint8_t *ptr; + + secured_message_context = spdm_secured_message_context; + struct_size = sizeof(libspdm_secure_session_keys_struct_t) + + (secured_message_context->aead_key_size + + secured_message_context->aead_iv_size + sizeof(uint64_t)) * 2; + + if (session_keys_size != struct_size) { + return false; + } + + session_keys_struct = session_keys; + if ((session_keys_struct->version != + LIBSPDM_SECURE_SESSION_KEYS_STRUCT_VERSION) || + (session_keys_struct->aead_key_size != + secured_message_context->aead_key_size) || + (session_keys_struct->aead_iv_size != + secured_message_context->aead_iv_size)) { + return false; + } + + ptr = (const void *)(session_keys_struct + 1); + libspdm_copy_mem(secured_message_context->application_secret.request_data_encryption_key, + sizeof(secured_message_context->application_secret + .request_data_encryption_key), + ptr, secured_message_context->aead_key_size); + ptr += secured_message_context->aead_key_size; + libspdm_copy_mem(secured_message_context->application_secret.request_data_salt, + sizeof(secured_message_context->application_secret + .request_data_salt), + ptr, secured_message_context->aead_iv_size); + ptr += secured_message_context->aead_iv_size; + libspdm_copy_mem(&secured_message_context->application_secret.request_data_sequence_number, + sizeof(secured_message_context->application_secret + .request_data_sequence_number), + ptr, sizeof(uint64_t)); + ptr += sizeof(uint64_t); + libspdm_copy_mem(secured_message_context->application_secret + .response_data_encryption_key, + sizeof(secured_message_context->application_secret + .response_data_encryption_key), + ptr, secured_message_context->aead_key_size); + ptr += secured_message_context->aead_key_size; + libspdm_copy_mem(secured_message_context->application_secret.response_data_salt, + sizeof(secured_message_context->application_secret.response_data_salt), + ptr, secured_message_context->aead_iv_size); + ptr += secured_message_context->aead_iv_size; + libspdm_copy_mem(&secured_message_context->application_secret.response_data_sequence_number, + sizeof(secured_message_context->application_secret + .response_data_sequence_number), + ptr, sizeof(uint64_t)); + ptr += sizeof(uint64_t); + return true; +} + +/** + * Get the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_secured_message_get_last_spdm_error_struct( + void *spdm_secured_message_context, + libspdm_error_struct_t *last_spdm_error) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_copy_mem(last_spdm_error, sizeof(libspdm_error_struct_t), + &secured_message_context->last_spdm_error, + sizeof(libspdm_error_struct_t)); +} + +/** + * Set the last SPDM error struct of an SPDM context. + * + * @param spdm_context A pointer to the SPDM context. + * @param last_spdm_error Last SPDM error struct of an SPDM context. + */ +void libspdm_secured_message_set_last_spdm_error_struct( + void *spdm_secured_message_context, + const libspdm_error_struct_t *last_spdm_error) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_copy_mem(&secured_message_context->last_spdm_error, + sizeof(secured_message_context->last_spdm_error), + last_spdm_error, + sizeof(libspdm_error_struct_t)); +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c new file mode 100644 index 0000000000..0b15bba414 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c @@ -0,0 +1,580 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_secured_message_lib.h" + +/** + * Encode an application message to a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_requester Indicates if it is a requester message. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a source buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * Before app_message, there is room for spdm_secured_message_cipher_header_t. + * After (app_message + app_message_size), there is room for random bytes. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a destination buffer to store the secured message. + * It shall point to the acquired sender buffer. + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is encoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + **/ +libspdm_return_t libspdm_encode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_requester, size_t app_message_size, + void *app_message, size_t *secured_message_size, + void *secured_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks) +{ + libspdm_secured_message_context_t *secured_message_context; + size_t total_secured_message_size; + size_t plain_text_size; + size_t cipher_text_size; + size_t aead_pad_size; + size_t aead_tag_size; + size_t aead_key_size; + size_t aead_iv_size; + uint8_t *a_data; + uint8_t *enc_msg; + uint8_t *dec_msg; + uint8_t *tag; + spdm_secured_message_a_data_header1_t *record_header1; + spdm_secured_message_a_data_header2_t *record_header2; + size_t record_header_size; + spdm_secured_message_cipher_header_t *enc_msg_header; + bool result; + uint8_t key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t sequence_number; + uint64_t sequence_num_in_header; + uint8_t sequence_num_in_header_size; + libspdm_session_type_t session_type; + uint32_t rand_count; + uint32_t max_rand_count; + libspdm_session_state_t session_state; + + secured_message_context = spdm_secured_message_context; + + session_type = secured_message_context->session_type; + LIBSPDM_ASSERT((session_type == LIBSPDM_SESSION_TYPE_MAC_ONLY) || + (session_type == LIBSPDM_SESSION_TYPE_ENC_MAC)); + session_state = secured_message_context->session_state; + LIBSPDM_ASSERT((session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) || + (session_state == LIBSPDM_SESSION_STATE_ESTABLISHED)); + + aead_tag_size = secured_message_context->aead_tag_size; + aead_key_size = secured_message_context->aead_key_size; + aead_iv_size = secured_message_context->aead_iv_size; + + switch (session_state) { + case LIBSPDM_SESSION_STATE_HANDSHAKING: + if (is_requester) { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->handshake_secret + .request_handshake_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->handshake_secret.request_handshake_salt, + secured_message_context->aead_iv_size); + sequence_number = secured_message_context->handshake_secret + .request_handshake_sequence_number; + } else { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->handshake_secret + .response_handshake_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->handshake_secret.response_handshake_salt, + secured_message_context->aead_iv_size); + sequence_number = secured_message_context->handshake_secret + .response_handshake_sequence_number; + } + break; + case LIBSPDM_SESSION_STATE_ESTABLISHED: + if (is_requester) { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->application_secret + .request_data_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->application_secret.request_data_salt, + secured_message_context->aead_iv_size); + sequence_number = secured_message_context->application_secret + .request_data_sequence_number; + } else { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->application_secret + .response_data_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->application_secret.response_data_salt, + secured_message_context->aead_iv_size); + sequence_number = secured_message_context->application_secret + .response_data_sequence_number; + } + break; + default: + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + break; + } + + if (sequence_number == (uint64_t)-1) { + return LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW; + } + + *(uint64_t *)salt = *(uint64_t *)salt ^ sequence_number; + + sequence_num_in_header = 0; + sequence_num_in_header_size = spdm_secured_message_callbacks->get_sequence_number( + sequence_number, (uint8_t *)&sequence_num_in_header); + LIBSPDM_ASSERT(sequence_num_in_header_size <= sizeof(sequence_num_in_header)); + + sequence_number++; + if (session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) { + if (is_requester) { + secured_message_context->handshake_secret.request_handshake_sequence_number = + sequence_number; + } else { + secured_message_context->handshake_secret.response_handshake_sequence_number = + sequence_number; + } + } + else { + if (is_requester) { + secured_message_context->application_secret.request_data_sequence_number = + sequence_number; + } else { + secured_message_context->application_secret.response_data_sequence_number = + sequence_number; + } + } + + record_header_size = sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size + + sizeof(spdm_secured_message_a_data_header2_t); + + switch (session_type) { + case LIBSPDM_SESSION_TYPE_ENC_MAC: + max_rand_count = spdm_secured_message_callbacks->get_max_random_number_count(); + if (max_rand_count != 0) { + rand_count = 0; + result = libspdm_get_random_number(sizeof(rand_count), (uint8_t *)&rand_count); + if (!result) { + return LIBSPDM_STATUS_LOW_ENTROPY; + } + rand_count = (uint8_t)((rand_count % max_rand_count) + 1); + } else { + rand_count = 0; + } + + plain_text_size = sizeof(spdm_secured_message_cipher_header_t) + app_message_size + + rand_count; + cipher_text_size = plain_text_size; + aead_pad_size = cipher_text_size - plain_text_size; + total_secured_message_size = record_header_size + cipher_text_size + aead_tag_size; + + LIBSPDM_ASSERT(*secured_message_size >= total_secured_message_size); + if (*secured_message_size < total_secured_message_size) { + *secured_message_size = total_secured_message_size; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + *secured_message_size = total_secured_message_size; + record_header1 = (void *)secured_message; + record_header2 = (void *)((uint8_t *)record_header1 + + sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size); + record_header1->session_id = session_id; + libspdm_copy_mem(record_header1 + 1, + *secured_message_size + - ((uint8_t*)(record_header1 + 1) - (uint8_t*)secured_message), + &sequence_num_in_header, + sequence_num_in_header_size); + record_header2->length = (uint16_t)(cipher_text_size + aead_tag_size); + + enc_msg_header = + (void *)((uint8_t *)app_message - sizeof(spdm_secured_message_cipher_header_t)); + enc_msg_header->application_data_length = (uint16_t)app_message_size; + result = libspdm_get_random_number(rand_count, + (uint8_t *)enc_msg_header + + sizeof(spdm_secured_message_cipher_header_t) + + app_message_size); + if (!result) { + return LIBSPDM_STATUS_LOW_ENTROPY; + } + libspdm_zero_mem((uint8_t *)enc_msg_header + plain_text_size, aead_pad_size); + + a_data = (uint8_t *)record_header1; + enc_msg = (uint8_t *)(record_header2 + 1); + dec_msg = (uint8_t *)enc_msg_header; + tag = (uint8_t *)record_header1 + record_header_size + + cipher_text_size; + + result = libspdm_aead_encryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, salt, aead_iv_size, (uint8_t *)a_data, + record_header_size, dec_msg, cipher_text_size, tag, + aead_tag_size, enc_msg, &cipher_text_size); + break; + + case LIBSPDM_SESSION_TYPE_MAC_ONLY: + total_secured_message_size = + record_header_size + app_message_size + aead_tag_size; + + LIBSPDM_ASSERT(*secured_message_size >= total_secured_message_size); + if (*secured_message_size < total_secured_message_size) { + *secured_message_size = total_secured_message_size; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + *secured_message_size = total_secured_message_size; + record_header1 = (void *)secured_message; + record_header2 = + (void *)((uint8_t *)record_header1 + + sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size); + record_header1->session_id = session_id; + libspdm_copy_mem(record_header1 + 1, + *secured_message_size + - ((uint8_t*)(record_header1 + 1) - (uint8_t*)secured_message), + &sequence_num_in_header, + sequence_num_in_header_size); + record_header2->length = + (uint16_t)(app_message_size + aead_tag_size); + libspdm_copy_mem(record_header2 + 1, + *secured_message_size + - ((uint8_t*)(record_header2 + 1) - (uint8_t*)secured_message), + app_message, app_message_size); + a_data = (uint8_t *)record_header1; + tag = (uint8_t *)record_header1 + record_header_size + app_message_size; + + result = libspdm_aead_encryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, salt, aead_iv_size, (uint8_t *)a_data, + record_header_size + app_message_size, NULL, 0, tag, + aead_tag_size, NULL, NULL); + break; + + default: + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (!result) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Decode an application message from a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_requester Indicates if it is a requester message. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a source buffer to store the secured message. + * It shall point to the acquired receiver buffer. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a destination buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer to hold the decrypted message + * On output, the app_message pointer shall be inside of [app_message, app_message + app_message_size] + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is decoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_UNSUPPORTED The secured_message is unsupported. + **/ +libspdm_return_t libspdm_decode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_requester, size_t secured_message_size, + void *secured_message, size_t *app_message_size, + void **app_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks) +{ + libspdm_secured_message_context_t *secured_message_context; + size_t plain_text_size; + size_t cipher_text_size; + size_t aead_tag_size; + size_t aead_key_size; + size_t aead_iv_size; + const uint8_t *a_data; + const uint8_t *enc_msg; + uint8_t *dec_msg; + const uint8_t *tag; + spdm_secured_message_a_data_header1_t *record_header1; + spdm_secured_message_a_data_header2_t *record_header2; + size_t record_header_size; + spdm_secured_message_cipher_header_t *enc_msg_header; + bool result; + uint8_t key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t sequence_number; + uint64_t sequence_num_in_header; + uint8_t sequence_num_in_header_size; + libspdm_session_type_t session_type; + libspdm_session_state_t session_state; + libspdm_error_struct_t spdm_error; + + spdm_error.error_code = 0; + spdm_error.session_id = 0; + libspdm_secured_message_set_last_spdm_error_struct(spdm_secured_message_context, &spdm_error); + + spdm_error.error_code = SPDM_ERROR_CODE_DECRYPT_ERROR; + spdm_error.session_id = session_id; + + secured_message_context = spdm_secured_message_context; + + session_type = secured_message_context->session_type; + LIBSPDM_ASSERT((session_type == LIBSPDM_SESSION_TYPE_MAC_ONLY) || + (session_type == LIBSPDM_SESSION_TYPE_ENC_MAC)); + session_state = secured_message_context->session_state; + LIBSPDM_ASSERT((session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) || + (session_state == LIBSPDM_SESSION_STATE_ESTABLISHED)); + + aead_tag_size = secured_message_context->aead_tag_size; + aead_key_size = secured_message_context->aead_key_size; + aead_iv_size = secured_message_context->aead_iv_size; + + switch (session_state) { + case LIBSPDM_SESSION_STATE_HANDSHAKING: + if (is_requester) { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->handshake_secret + .request_handshake_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->handshake_secret + .request_handshake_salt, + secured_message_context->aead_iv_size); + sequence_number = + secured_message_context->handshake_secret.request_handshake_sequence_number; + } else { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->handshake_secret + .response_handshake_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->handshake_secret + .response_handshake_salt, + secured_message_context->aead_iv_size); + sequence_number = + secured_message_context->handshake_secret.response_handshake_sequence_number; + } + break; + case LIBSPDM_SESSION_STATE_ESTABLISHED: + if (is_requester) { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->application_secret + .request_data_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->application_secret + .request_data_salt, + secured_message_context->aead_iv_size); + sequence_number = + secured_message_context->application_secret.request_data_sequence_number; + } else { + libspdm_copy_mem(key, sizeof(key), + secured_message_context->application_secret + .response_data_encryption_key, + secured_message_context->aead_key_size); + libspdm_copy_mem(salt, sizeof(salt), + secured_message_context->application_secret + .response_data_salt, + secured_message_context->aead_iv_size); + sequence_number = + secured_message_context->application_secret.response_data_sequence_number; + } + break; + default: + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + if (sequence_number == (uint64_t)-1) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW; + } + + *(uint64_t *)salt = *(uint64_t *)salt ^ sequence_number; + + sequence_num_in_header = 0; + sequence_num_in_header_size = + spdm_secured_message_callbacks->get_sequence_number( + sequence_number, (uint8_t *)&sequence_num_in_header); + LIBSPDM_ASSERT(sequence_num_in_header_size <= sizeof(sequence_num_in_header)); + + sequence_number++; + if (session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) { + if (is_requester) { + secured_message_context->handshake_secret.request_handshake_sequence_number = + sequence_number; + } else { + secured_message_context->handshake_secret.response_handshake_sequence_number = + sequence_number; + } + } + else { + if (is_requester) { + secured_message_context->application_secret.request_data_sequence_number = + sequence_number; + } else { + secured_message_context->application_secret.response_data_sequence_number = + sequence_number; + } + } + + record_header_size = sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size + + sizeof(spdm_secured_message_a_data_header2_t); + + switch (session_type) { + case LIBSPDM_SESSION_TYPE_ENC_MAC: + if (secured_message_size < record_header_size + aead_tag_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + record_header1 = secured_message; + record_header2 = + (void *)((uint8_t *)record_header1 + + sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size); + if (record_header1->session_id != session_id) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (libspdm_const_compare_mem(record_header1 + 1, &sequence_num_in_header, + sequence_num_in_header_size) != 0) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (record_header2->length > secured_message_size - record_header_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + if (record_header2->length < aead_tag_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + cipher_text_size = (record_header2->length - aead_tag_size); + if (cipher_text_size > *app_message_size) { + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; + } + libspdm_zero_mem(*app_message, *app_message_size); + enc_msg_header = (void *)(record_header2 + 1); + a_data = (const uint8_t *)record_header1; + enc_msg = (const uint8_t *)enc_msg_header; + dec_msg = (uint8_t *)*app_message; + enc_msg_header = (void *)dec_msg; + tag = (const uint8_t *)record_header1 + record_header_size + cipher_text_size; + result = libspdm_aead_decryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, salt, aead_iv_size, a_data, + record_header_size, enc_msg, cipher_text_size, tag, + aead_tag_size, dec_msg, &cipher_text_size); + if (!result) { + /* Backup keys are valid, fail and alert rollback and retry is possible. */ + if ((is_requester && secured_message_context->requester_backup_valid) || + ((!is_requester) && secured_message_context->responder_backup_valid)) { + return LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE; + } + + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + plain_text_size = enc_msg_header->application_data_length; + if (plain_text_size > cipher_text_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + LIBSPDM_ASSERT(*app_message_size >= plain_text_size); + *app_message = enc_msg_header + 1; + *app_message_size = plain_text_size; + break; + + case LIBSPDM_SESSION_TYPE_MAC_ONLY: + if (secured_message_size < record_header_size + aead_tag_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + record_header1 = secured_message; + record_header2 = + (void *)((uint8_t *)record_header1 + + sizeof(spdm_secured_message_a_data_header1_t) + + sequence_num_in_header_size); + if (record_header1->session_id != session_id) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (libspdm_const_compare_mem(record_header1 + 1, &sequence_num_in_header, + sequence_num_in_header_size) != 0) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (record_header2->length > + secured_message_size - record_header_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + if (record_header2->length < aead_tag_size) { + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + a_data = (uint8_t *)record_header1; + tag = (uint8_t *)record_header1 + record_header_size + + record_header2->length - aead_tag_size; + result = libspdm_aead_decryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, salt, aead_iv_size, a_data, + record_header_size + record_header2->length - + aead_tag_size, + NULL, 0, tag, aead_tag_size, NULL, NULL); + if (!result) { + /* Backup keys are valid, fail and alert rollback and retry is possible. */ + if ((is_requester && secured_message_context->requester_backup_valid) || + ((!is_requester) && secured_message_context->responder_backup_valid)) { + return LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE; + } + + libspdm_secured_message_set_last_spdm_error_struct( + spdm_secured_message_context, &spdm_error); + return LIBSPDM_STATUS_CRYPTO_ERROR; + } + + plain_text_size = record_header2->length - aead_tag_size; + LIBSPDM_ASSERT(*app_message_size >= plain_text_size); + *app_message = record_header2 + 1; + *app_message_size = plain_text_size; + break; + + default: + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + return LIBSPDM_STATUS_SUCCESS; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c new file mode 100644 index 0000000000..c902317d66 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c @@ -0,0 +1,108 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_secured_message_lib.h" + +/** + * Allocates and Initializes one Diffie-Hellman Ephemeral (DHE) context for subsequent use, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param is_initiator if the caller is initiator. + * true: initiator + * false: not an initiator + * + * @return Pointer to the Diffie-Hellman context that has been initialized. + **/ +void *libspdm_secured_message_dhe_new(spdm_version_number_t spdm_version, + uint16_t dhe_named_group, bool is_initiator) +{ + return libspdm_dhe_new(spdm_version, dhe_named_group, is_initiator); +} + +/** + * Release the specified DHE context, + * based upon negotiated DHE algorithm. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context to be released. + **/ +void libspdm_secured_message_dhe_free(uint16_t dhe_named_group, void *dhe_context) +{ + libspdm_dhe_free(dhe_named_group, dhe_context); +} + +/** + * Generates DHE public key, + * based upon negotiated DHE algorithm. + * + * This function generates random secret exponent, and computes the public key, which is + * returned via parameter public_key and public_key_size. DH context is updated accordingly. + * If the public_key buffer is too small to hold the public key, false is returned and + * public_key_size is set to the required buffer size to obtain the public key. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context. + * @param public_key Pointer to the buffer to receive generated public key. + * @param public_key_size On input, the size of public_key buffer in bytes. + * On output, the size of data returned in public_key buffer in bytes. + * + * @retval true DHE public key generation succeeded. + * @retval false DHE public key generation failed. + * @retval false public_key_size is not large enough. + **/ +bool libspdm_secured_message_dhe_generate_key(uint16_t dhe_named_group, + void *dhe_context, + uint8_t *public_key, + size_t *public_key_size) +{ + return libspdm_dhe_generate_key(dhe_named_group, dhe_context, public_key, public_key_size); +} + +/** + * Computes exchanged common key, + * based upon negotiated DHE algorithm. + * + * Given peer's public key, this function computes the exchanged common key, based on its own + * context including value of prime modulus and random secret exponent. + * + * @param dhe_named_group SPDM dhe_named_group + * @param dhe_context Pointer to the DHE context. + * @param peer_public_key Pointer to the peer's public key. + * @param peer_public_key_size size of peer's public key in bytes. + * @param key Pointer to the buffer to receive generated key. + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @retval true DHE exchanged key generation succeeded. + * @retval false DHE exchanged key generation failed. + * @retval false key_size is not large enough. + **/ +bool libspdm_secured_message_dhe_compute_key( + uint16_t dhe_named_group, void *dhe_context, + const uint8_t *peer_public, size_t peer_public_size, + void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + uint8_t final_key[LIBSPDM_MAX_DHE_KEY_SIZE]; + size_t final_key_size; + bool ret; + + secured_message_context = spdm_secured_message_context; + + final_key_size = sizeof(final_key); + ret = libspdm_dhe_compute_key(dhe_named_group, dhe_context, peer_public, + peer_public_size, final_key, + &final_key_size); + if (!ret) { + return ret; + } + libspdm_copy_mem(secured_message_context->master_secret.dhe_secret, + sizeof(secured_message_context->master_secret.dhe_secret), + final_key, final_key_size); + libspdm_zero_mem(final_key, final_key_size); + secured_message_context->dhe_key_size = final_key_size; + return true; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c new file mode 100644 index 0000000000..b4bf707d5e --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c @@ -0,0 +1,1113 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_secured_message_lib.h" + +/** + * This function concatenates binary data, which is used as info in HKDF expand later. + * + * @param label An ascii string label for the libspdm_bin_concat. + * @param label_size The size in bytes of the ASCII string label, not including NULL terminator. + * @param context A pre-defined hash value as the context for the libspdm_bin_concat. + * @param length 16 bits length for the libspdm_bin_concat. + * @param hash_size The size in bytes of the context hash. + * @param out_bin The buffer to store the output binary. + * @param out_bin_size The size in bytes for the out_bin. + **/ +void libspdm_bin_concat(spdm_version_number_t spdm_version, + const char *label, size_t label_size, + const uint8_t *context, uint16_t length, + size_t hash_size, uint8_t *out_bin, + size_t *out_bin_size) +{ + size_t final_size; + + /* The correct version characters (1.1 or 1.2) will replace the x.x. */ + #define LIBSPDM_BIN_CONCAT_LABEL "spdmx.x " + + final_size = sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - 1 + label_size; + if (context != NULL) { + final_size += hash_size; + } + + LIBSPDM_ASSERT(*out_bin_size >= final_size); + + *out_bin_size = final_size; + + libspdm_copy_mem(out_bin, *out_bin_size, &length, sizeof(uint16_t)); + libspdm_copy_mem(out_bin + sizeof(uint16_t), *out_bin_size - sizeof(uint16_t), + LIBSPDM_BIN_CONCAT_LABEL, sizeof(LIBSPDM_BIN_CONCAT_LABEL) - 1); + + /* Patch the version. */ + out_bin[6] = (char)('0' + ((spdm_version >> 12) & 0xF)); + out_bin[8] = (char)('0' + ((spdm_version >> 8) & 0xF)); + libspdm_copy_mem(out_bin + sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - 1, + *out_bin_size - (sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - 1), + label, label_size); + + if (context != NULL) { + libspdm_copy_mem(out_bin + sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - + 1 + label_size, + *out_bin_size - (sizeof(uint16_t) + sizeof(LIBSPDM_BIN_CONCAT_LABEL) - + 1 + label_size), context, hash_size); + } + + #undef LIBSPDM_BIN_CONCAT_LABEL +} + +/** + * This function generates SPDM AEAD key and IV for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param major_secret The major secret. + * @param key The buffer to store the AEAD key. + * @param iv The buffer to store the AEAD IV. + * + * @retval RETURN_SUCCESS SPDM AEAD key and IV for a session is generated. + **/ +bool libspdm_generate_aead_key_and_iv( + libspdm_secured_message_context_t *secured_message_context, + const uint8_t *major_secret, uint8_t *key, uint8_t *iv) +{ + bool status; + size_t hash_size; + size_t key_length; + size_t iv_length; + uint8_t bin_str5[128]; + size_t bin_str5_size; + uint8_t bin_str6[128]; + size_t bin_str6_size; + + hash_size = secured_message_context->hash_size; + key_length = secured_message_context->aead_key_size; + iv_length = secured_message_context->aead_iv_size; + + bin_str5_size = sizeof(bin_str5); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_5_LABEL, sizeof(SPDM_BIN_STR_5_LABEL) - 1, + NULL, (uint16_t)key_length, hash_size, bin_str5, + &bin_str5_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str5 (0x%x):\n", bin_str5_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str5, bin_str5_size); + status = libspdm_hkdf_expand(secured_message_context->base_hash_algo, + major_secret, hash_size, bin_str5, + bin_str5_size, key, key_length); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "key (0x%x) - ", key_length)); + LIBSPDM_INTERNAL_DUMP_DATA(key, key_length); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + bin_str6_size = sizeof(bin_str6); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_6_LABEL, sizeof(SPDM_BIN_STR_6_LABEL) - 1, + NULL, (uint16_t)iv_length, hash_size, bin_str6, + &bin_str6_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str6 (0x%x):\n", bin_str6_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str6, bin_str6_size); + status = libspdm_hkdf_expand(secured_message_context->base_hash_algo, + major_secret, hash_size, bin_str6, + bin_str6_size, iv, iv_length); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "iv (0x%x) - ", iv_length)); + LIBSPDM_INTERNAL_DUMP_DATA(iv, iv_length); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + return true; +} + +/** + * This function generates SPDM finished_key for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param handshake_secret The handshake secret. + * @param finished_key The buffer to store the finished key. + * + * @retval RETURN_SUCCESS SPDM finished_key for a session is generated. + **/ +bool libspdm_generate_finished_key( + libspdm_secured_message_context_t *secured_message_context, + const uint8_t *handshake_secret, uint8_t *finished_key) +{ + bool status; + size_t hash_size; + uint8_t bin_str7[128]; + size_t bin_str7_size; + + hash_size = secured_message_context->hash_size; + + bin_str7_size = sizeof(bin_str7); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_7_LABEL, sizeof(SPDM_BIN_STR_7_LABEL) - 1, + NULL, (uint16_t)hash_size, hash_size, bin_str7, + &bin_str7_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str7 (0x%x):\n", bin_str7_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str7, bin_str7_size); + status = libspdm_hkdf_expand(secured_message_context->base_hash_algo, + handshake_secret, hash_size, bin_str7, + bin_str7_size, finished_key, hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "finished_key (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(finished_key, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + return true; +} + +/** + * This function generates SPDM HandshakeKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param th1_hash_data th1 hash + * + * @retval RETURN_SUCCESS SPDM HandshakeKey for a session is generated. + **/ +bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, + const uint8_t *th1_hash_data) +{ + bool status; + size_t hash_size; + uint8_t bin_str0[128]; + size_t bin_str0_size; + uint8_t bin_str1[128]; + size_t bin_str1_size; + uint8_t bin_str2[128]; + size_t bin_str2_size; + libspdm_secured_message_context_t *secured_message_context; + uint8_t zero_filled_buffer[LIBSPDM_MAX_HASH_SIZE]; + + secured_message_context = spdm_secured_message_context; + + hash_size = secured_message_context->hash_size; + + bin_str0_size = sizeof(bin_str0); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_0_LABEL, sizeof(SPDM_BIN_STR_0_LABEL) - 1, + NULL, (uint16_t)hash_size, hash_size, bin_str0, + &bin_str0_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str0 (0x%x):\n", bin_str0_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str0, bin_str0_size); + + if (!(secured_message_context->use_psk)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "[DHE Secret]: ")); + LIBSPDM_INTERNAL_DUMP_HEX_STR( + secured_message_context->master_secret.dhe_secret, + secured_message_context->dhe_key_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + libspdm_zero_mem(zero_filled_buffer, sizeof(zero_filled_buffer)); + status = libspdm_hkdf_extract( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.dhe_secret, + secured_message_context->dhe_key_size, + zero_filled_buffer, hash_size, + secured_message_context->master_secret.handshake_secret, hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "handshake_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->master_secret.handshake_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + bin_str1_size = sizeof(bin_str1); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_1_LABEL, sizeof(SPDM_BIN_STR_1_LABEL) - 1, + th1_hash_data, (uint16_t)hash_size, hash_size, + bin_str1, &bin_str1_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str1 (0x%x):\n", bin_str1_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str1, bin_str1_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_handshake_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str1, + bin_str1_size, + secured_message_context->handshake_secret.request_handshake_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.handshake_secret, + hash_size, bin_str1, bin_str1_size, + secured_message_context->handshake_secret.request_handshake_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "request_handshake_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(secured_message_context->handshake_secret + .request_handshake_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + bin_str2_size = sizeof(bin_str2); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_2_LABEL, sizeof(SPDM_BIN_STR_2_LABEL) - 1, + th1_hash_data, (uint16_t)hash_size, hash_size, + bin_str2, &bin_str2_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str2 (0x%x):\n", bin_str2_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str2, bin_str2_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_handshake_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str2, + bin_str2_size, + secured_message_context->handshake_secret.response_handshake_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.handshake_secret, + hash_size, bin_str2, bin_str2_size, + secured_message_context->handshake_secret.response_handshake_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "response_handshake_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(secured_message_context->handshake_secret.response_handshake_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + status = libspdm_generate_finished_key( + secured_message_context, + secured_message_context->handshake_secret + .request_handshake_secret, + secured_message_context->handshake_secret.request_finished_key); + if (!status) { + return status; + } + + status = libspdm_generate_finished_key( + secured_message_context, + secured_message_context->handshake_secret.response_handshake_secret, + secured_message_context->handshake_secret.response_finished_key); + if (!status) { + return status; + } + + status = libspdm_generate_aead_key_and_iv(secured_message_context, + secured_message_context->handshake_secret + .request_handshake_secret, + secured_message_context->handshake_secret + .request_handshake_encryption_key, + secured_message_context->handshake_secret + .request_handshake_salt); + if (!status) { + return status; + } + secured_message_context->handshake_secret.request_handshake_sequence_number = 0; + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->handshake_secret.response_handshake_secret, + secured_message_context->handshake_secret.response_handshake_encryption_key, + secured_message_context->handshake_secret.response_handshake_salt); + if (!status) { + return status; + } + + secured_message_context->handshake_secret.response_handshake_sequence_number = 0; + libspdm_zero_mem(secured_message_context->master_secret.dhe_secret, LIBSPDM_MAX_DHE_KEY_SIZE); + + return true; +} + +/** + * This function generates SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param th2_hash_data th2 hash + * + * @retval RETURN_SUCCESS SPDM DataKey for a session is generated. + **/ +bool libspdm_generate_session_data_key(void *spdm_secured_message_context, + const uint8_t *th2_hash_data) +{ + bool status; + size_t hash_size; + uint8_t salt1[64]; + uint8_t bin_str0[128]; + size_t bin_str0_size; + uint8_t bin_str3[128]; + size_t bin_str3_size; + uint8_t bin_str4[128]; + size_t bin_str4_size; + uint8_t bin_str8[128]; + size_t bin_str8_size; + libspdm_secured_message_context_t *secured_message_context; + uint8_t zero_filled_buffer[LIBSPDM_MAX_HASH_SIZE]; + + secured_message_context = spdm_secured_message_context; + + hash_size = secured_message_context->hash_size; + + if (!(secured_message_context->use_psk)) { + bin_str0_size = sizeof(bin_str0); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_0_LABEL, + sizeof(SPDM_BIN_STR_0_LABEL) - 1, NULL, + (uint16_t)hash_size, hash_size, bin_str0, + &bin_str0_size); + + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.handshake_secret, + hash_size, bin_str0, bin_str0_size, salt1, hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "salt1 (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(salt1, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + libspdm_zero_mem(zero_filled_buffer, sizeof(zero_filled_buffer)); + status = libspdm_hkdf_extract( + secured_message_context->base_hash_algo, + zero_filled_buffer, hash_size, salt1, hash_size, + secured_message_context->master_secret.master_secret, hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "master_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->master_secret.master_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + } + + bin_str3_size = sizeof(bin_str3); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_3_LABEL, sizeof(SPDM_BIN_STR_3_LABEL) - 1, + th2_hash_data, (uint16_t)hash_size, hash_size, + bin_str3, &bin_str3_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str3 (0x%x):\n", bin_str3_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str3, bin_str3_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_master_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str3, + bin_str3_size, + secured_message_context->application_secret.request_data_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.master_secret, + hash_size, bin_str3, bin_str3_size, + secured_message_context->application_secret.request_data_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "request_data_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->application_secret.request_data_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + bin_str4_size = sizeof(bin_str4); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_4_LABEL, sizeof(SPDM_BIN_STR_4_LABEL) - 1, + th2_hash_data, (uint16_t)hash_size, hash_size, + bin_str4, &bin_str4_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str4 (0x%x):\n", bin_str4_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str4, bin_str4_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_master_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str4, + bin_str4_size, + secured_message_context->application_secret.response_data_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.master_secret, + hash_size, bin_str4, bin_str4_size, + secured_message_context->application_secret.response_data_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "response_data_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->application_secret.response_data_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + bin_str8_size = sizeof(bin_str8); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_8_LABEL, sizeof(SPDM_BIN_STR_8_LABEL) - 1, + th2_hash_data, (uint16_t)hash_size, hash_size, + bin_str8, &bin_str8_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str8 (0x%x):\n", bin_str8_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str8, bin_str8_size); + + #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + if (secured_message_context->use_psk) { + status = libspdm_psk_master_secret_hkdf_expand( + secured_message_context->version, + secured_message_context->base_hash_algo, + secured_message_context->psk_hint, + secured_message_context->psk_hint_size, bin_str8, + bin_str8_size, + secured_message_context->export_master_secret, + hash_size); + + if (!status) { + return false; + } + } + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + if (!(secured_message_context->use_psk)) { + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->master_secret.master_secret, + hash_size, bin_str8, bin_str8_size, + secured_message_context->export_master_secret, + hash_size); + + if (!status) { + return false; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "export_master_secret (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA( + secured_message_context->export_master_secret, hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->application_secret.request_data_secret, + secured_message_context->application_secret.request_data_encryption_key, + secured_message_context->application_secret.request_data_salt); + if (!status) { + return status; + } + secured_message_context->application_secret.request_data_sequence_number = 0; + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->application_secret.response_data_secret, + secured_message_context->application_secret.response_data_encryption_key, + secured_message_context->application_secret.response_data_salt); + if (!status) { + return status; + } + secured_message_context->application_secret.response_data_sequence_number = 0; + + return true; +} + +/** + * This function creates the updates of SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param action Indicate of the key update action. + * + * @retval RETURN_SUCCESS SPDM DataKey update is created. + **/ +bool libspdm_create_update_session_data_key(void *spdm_secured_message_context, + libspdm_key_update_action_t action) +{ + bool status; + size_t hash_size; + uint8_t bin_str9[128]; + size_t bin_str9_size; + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + hash_size = secured_message_context->hash_size; + + bin_str9_size = sizeof(bin_str9); + libspdm_bin_concat(secured_message_context->version, + SPDM_BIN_STR_9_LABEL, sizeof(SPDM_BIN_STR_9_LABEL) - 1, + NULL, (uint16_t)hash_size, hash_size, bin_str9, + &bin_str9_size); + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str9 (0x%x):\n", bin_str9_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str9, bin_str9_size); + + if (action == LIBSPDM_KEY_UPDATE_ACTION_REQUESTER) { + libspdm_copy_mem(&secured_message_context->application_secret_backup + .request_data_secret, + sizeof(secured_message_context->application_secret_backup + .request_data_secret), + &secured_message_context->application_secret + .request_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret_backup + .request_data_encryption_key, + sizeof(secured_message_context->application_secret_backup + .request_data_encryption_key), + &secured_message_context->application_secret + .request_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret_backup + .request_data_salt, + sizeof(secured_message_context->application_secret_backup + .request_data_salt), + &secured_message_context->application_secret + .request_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret_backup + .request_data_sequence_number = + secured_message_context->application_secret.request_data_sequence_number; + + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->application_secret.request_data_secret, + hash_size, bin_str9, bin_str9_size, + secured_message_context->application_secret.request_data_secret, + hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "RequestDataSecretUpdate (0x%x) - ", hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(secured_message_context->application_secret.request_data_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->application_secret.request_data_secret, + secured_message_context->application_secret.request_data_encryption_key, + secured_message_context->application_secret.request_data_salt); + if (!status) { + return status; + } + secured_message_context->application_secret.request_data_sequence_number = 0; + + secured_message_context->requester_backup_valid = true; + } else if (action == LIBSPDM_KEY_UPDATE_ACTION_RESPONDER) { + libspdm_copy_mem(&secured_message_context->application_secret_backup + .response_data_secret, + sizeof(secured_message_context->application_secret_backup + .response_data_secret), + &secured_message_context->application_secret + .response_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret_backup + .response_data_encryption_key, + sizeof(secured_message_context->application_secret_backup + .response_data_encryption_key), + &secured_message_context->application_secret + .response_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret_backup + .response_data_salt, + sizeof(secured_message_context->application_secret_backup + .response_data_salt), + &secured_message_context->application_secret + .response_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret_backup + .response_data_sequence_number = + secured_message_context->application_secret.response_data_sequence_number; + + status = libspdm_hkdf_expand( + secured_message_context->base_hash_algo, + secured_message_context->application_secret.response_data_secret, + hash_size, bin_str9, bin_str9_size, + secured_message_context->application_secret.response_data_secret, + hash_size); + if (!status) { + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ResponseDataSecretUpdate (0x%x) - ", + hash_size)); + LIBSPDM_INTERNAL_DUMP_DATA(secured_message_context->application_secret.response_data_secret, + hash_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); + + status = libspdm_generate_aead_key_and_iv( + secured_message_context, + secured_message_context->application_secret.response_data_secret, + secured_message_context->application_secret.response_data_encryption_key, + secured_message_context->application_secret.response_data_salt); + if (!status) { + return status; + } + secured_message_context->application_secret.response_data_sequence_number = 0; + + secured_message_context->responder_backup_valid = true; + } else { + return false; + } + + return true; +} + +void libspdm_clear_handshake_secret(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + libspdm_zero_mem(secured_message_context->master_secret.handshake_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_zero_mem(&(secured_message_context->handshake_secret), + sizeof(libspdm_session_info_struct_handshake_secret_t)); + + secured_message_context->requester_backup_valid = false; + secured_message_context->responder_backup_valid = false; +} + +void libspdm_clear_master_secret(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + libspdm_zero_mem(secured_message_context->master_secret.master_secret, LIBSPDM_MAX_HASH_SIZE); +} + +/** + * This function activates the update of SPDM DataKey for a session. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param action Indicate of the key update action. + * @param use_new_key Indicate if the new key should be used. + * + * @retval RETURN_SUCCESS SPDM DataKey update is activated. + **/ +bool libspdm_activate_update_session_data_key(void *spdm_secured_message_context, + libspdm_key_update_action_t action, + bool use_new_key) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + + if (!use_new_key) { + if ((action == LIBSPDM_KEY_UPDATE_ACTION_REQUESTER) && + secured_message_context->requester_backup_valid) { + libspdm_copy_mem(&secured_message_context->application_secret + .request_data_secret, + sizeof(secured_message_context->application_secret + .request_data_secret), + &secured_message_context + ->application_secret_backup + .request_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret + .request_data_encryption_key, + sizeof(secured_message_context->application_secret + .request_data_encryption_key), + &secured_message_context + ->application_secret_backup + .request_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret + .request_data_salt, + sizeof(secured_message_context->application_secret + .request_data_salt), + &secured_message_context + ->application_secret_backup + .request_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret + .request_data_sequence_number = + secured_message_context->application_secret_backup.request_data_sequence_number; + } else if ((action == LIBSPDM_KEY_UPDATE_ACTION_RESPONDER) && + secured_message_context->responder_backup_valid) { + libspdm_copy_mem(&secured_message_context->application_secret + .response_data_secret, + sizeof(secured_message_context->application_secret + .response_data_secret), + &secured_message_context + ->application_secret_backup + .response_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret + .response_data_encryption_key, + sizeof(secured_message_context->application_secret + .response_data_encryption_key), + &secured_message_context + ->application_secret_backup + .response_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_copy_mem(&secured_message_context->application_secret + .response_data_salt, + sizeof(secured_message_context->application_secret + .response_data_salt), + &secured_message_context + ->application_secret_backup + .response_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret.response_data_sequence_number = + secured_message_context->application_secret_backup.response_data_sequence_number; + } + } + + if (action == LIBSPDM_KEY_UPDATE_ACTION_REQUESTER) { + libspdm_zero_mem(&secured_message_context->application_secret_backup.request_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_zero_mem(&secured_message_context->application_secret_backup + .request_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_zero_mem(&secured_message_context->application_secret_backup.request_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret_backup.request_data_sequence_number = 0; + secured_message_context->requester_backup_valid = false; + } else if (action == LIBSPDM_KEY_UPDATE_ACTION_RESPONDER) { + libspdm_zero_mem(&secured_message_context->application_secret_backup.response_data_secret, + LIBSPDM_MAX_HASH_SIZE); + libspdm_zero_mem(&secured_message_context->application_secret_backup + .response_data_encryption_key, + LIBSPDM_MAX_AEAD_KEY_SIZE); + libspdm_zero_mem(&secured_message_context->application_secret_backup.response_data_salt, + LIBSPDM_MAX_AEAD_IV_SIZE); + secured_message_context->application_secret_backup.response_data_sequence_number = 0; + secured_message_context->responder_backup_valid = false; + } + + return true; +} + +/** + * Allocates and initializes one HMAC context for subsequent use, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return Pointer to the HMAC context that has been initialized. + **/ +void *libspdm_hmac_new_with_request_finished_key(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_new(secured_message_context->base_hash_algo); +} + +/** + * Release the specified HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free_with_request_finished_key( + void *spdm_secured_message_context, void *hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_hmac_free(secured_message_context->base_hash_algo, hmac_ctx); +} + +/** + * Set request_finished_key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +bool libspdm_hmac_init_with_request_finished_key( + void *spdm_secured_message_context, void *hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_init( + secured_message_context->base_hash_algo, hmac_ctx, + secured_message_context->handshake_secret.request_finished_key, + secured_message_context->hash_size); +} + +/** + * Makes a copy of an existing HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + **/ +bool libspdm_hmac_duplicate_with_request_finished_key( + void *spdm_secured_message_context, + const void *hmac_ctx, void *new_hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_duplicate(secured_message_context->base_hash_algo, hmac_ctx, new_hmac_ctx); +} + +/** + * Digests the input data and updates HMAC context, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param data Pointer to the buffer containing the data to be digested. + * @param data_size size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_update_with_request_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, const void *data, + size_t data_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_update(secured_message_context->base_hash_algo, hmac_ctx, data, data_size); +} + +/** + * Completes computation of the HMAC digest value, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param hmac_value Pointer to a buffer that receives the HMAC digest value + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_final_with_request_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, uint8_t *hmac_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_final(secured_message_context->base_hash_algo, hmac_ctx, hmac_value); +} + +/** + * Computes the HMAC of a input data buffer, with request_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all_with_request_finished_key(void *spdm_secured_message_context, + const void *data, size_t data_size, + uint8_t *hmac_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_all( + secured_message_context->base_hash_algo, data, data_size, + secured_message_context->handshake_secret.request_finished_key, + secured_message_context->hash_size, hmac_value); +} + +/** + * Allocates and initializes one HMAC context for subsequent use, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return Pointer to the HMAC context that has been initialized. + **/ +void *libspdm_hmac_new_with_response_finished_key(void *spdm_secured_message_context) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_new(secured_message_context->base_hash_algo); +} + +/** + * Release the specified HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to the HMAC context to be released. + **/ +void libspdm_hmac_free_with_response_finished_key( + void *spdm_secured_message_context, void *hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + libspdm_hmac_free(secured_message_context->base_hash_algo, hmac_ctx); +} + +/** + * Set response_finished_key for subsequent use. It must be done before any + * calling to hmac_update(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + **/ +bool libspdm_hmac_init_with_response_finished_key( + void *spdm_secured_message_context, void *hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_init( + secured_message_context->base_hash_algo, hmac_ctx, + secured_message_context->handshake_secret.response_finished_key, + secured_message_context->hash_size); +} + +/** + * Makes a copy of an existing HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param new_hmac_ctx Pointer to new HMAC context. + * + * @retval true HMAC context copy succeeded. + * @retval false HMAC context copy failed. + **/ +bool libspdm_hmac_duplicate_with_response_finished_key( + void *spdm_secured_message_context, + const void *hmac_ctx, void *new_hmac_ctx) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_duplicate(secured_message_context->base_hash_algo, hmac_ctx, new_hmac_ctx); +} + +/** + * Digests the input data and updates HMAC context, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param data Pointer to the buffer containing the data to be digested. + * @param data_size size of data buffer in bytes. + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_update_with_response_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, const void *data, + size_t data_size) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_update(secured_message_context->base_hash_algo, hmac_ctx, data, data_size); +} + +/** + * Completes computation of the HMAC digest value, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param hmac_ctx Pointer to HMAC context being copied. + * @param hmac_value Pointer to a buffer that receives the HMAC digest value + * + * @retval true HMAC data digest succeeded. + * @retval false HMAC data digest failed. + **/ +bool libspdm_hmac_final_with_response_finished_key( + void *spdm_secured_message_context, + void *hmac_ctx, uint8_t *hmac_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_final(secured_message_context->base_hash_algo, hmac_ctx, hmac_value); +} + +/** + * Computes the HMAC of a input data buffer, with response_finished_key. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param data Pointer to the buffer containing the data to be HMACed. + * @param data_size size of data buffer in bytes. + * @param hash_value Pointer to a buffer that receives the HMAC value. + * + * @retval true HMAC computation succeeded. + * @retval false HMAC computation failed. + **/ +bool libspdm_hmac_all_with_response_finished_key( + void *spdm_secured_message_context, const void *data, + size_t data_size, uint8_t *hmac_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + return libspdm_hmac_all( + secured_message_context->base_hash_algo, data, data_size, + secured_message_context->handshake_secret.response_finished_key, + secured_message_context->hash_size, hmac_value); +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/cipher/libspdm_aead_aes_gcm.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/cipher/libspdm_aead_aes_gcm.c new file mode 100644 index 0000000000..8f4198a97d --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/cipher/libspdm_aead_aes_gcm.c @@ -0,0 +1,187 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * AEAD (AES-GCM) Wrapper Implementation. + * + * RFC 5116 - An Interface and Algorithms for Authenticated Encryption + * NIST SP800-38d - Cipher Modes of Operation: Galois / Counter Mode(GCM) and GMAC + **/ + +#include "internal_crypt_lib.h" +#include + +/** + * Performs AEAD AES-GCM authenticated encryption on a data buffer and additional authenticated data (AAD). + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16, 24 or 32, otherwise false is returned. + * tag_size must be 12, 13, 14, 15, 16, otherwise false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data (AAD). + * @param[in] a_data_size size of the additional authenticated data (AAD) in bytes. + * @param[in] data_in Pointer to the input data buffer to be encrypted. + * @param[in] data_in_size size of the input data buffer in bytes. + * @param[out] tag_out Pointer to a buffer that receives the authentication tag output. + * @param[in] tag_size size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the encryption output. + * @param[out] data_out_size size of the output data buffer in bytes. + * + * @retval true AEAD AES-GCM authenticated encryption succeeded. + * @retval false AEAD AES-GCM authenticated encryption failed. + * + **/ +bool libspdm_aead_aes_gcm_encrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + uint8_t *tag_out, size_t tag_size, + uint8_t *data_out, size_t *data_out_size) +{ + mbedtls_gcm_context ctx; + int32_t ret; + + if (data_in_size > INT_MAX) { + return false; + } + if (a_data_size > INT_MAX) { + return false; + } + if (iv_size != 12) { + return false; + } + switch (key_size) { + case 16: + case 24: + case 32: + break; + default: + return false; + } + if ((tag_size != 12) && (tag_size != 13) && (tag_size != 14) && + (tag_size != 15) && (tag_size != 16)) { + return false; + } + if (data_out_size != NULL) { + if ((*data_out_size > INT_MAX) || + (*data_out_size < data_in_size)) { + return false; + } + } + + mbedtls_gcm_init(&ctx); + + ret = mbedtls_gcm_setkey(&ctx, MBEDTLS_CIPHER_ID_AES, key, + (uint32_t)(key_size * 8)); + if (ret != 0) { + return false; + } + + ret = mbedtls_gcm_crypt_and_tag(&ctx, MBEDTLS_GCM_ENCRYPT, + (uint32_t)data_in_size, iv, + (uint32_t)iv_size, a_data, + (uint32_t)a_data_size, data_in, data_out, + tag_size, tag_out); + mbedtls_gcm_free(&ctx); + if (ret != 0) { + return false; + } + if (data_out_size != NULL) { + *data_out_size = data_in_size; + } + + return true; +} + +/** + * Performs AEAD AES-GCM authenticated decryption on a data buffer and additional authenticated data (AAD). + * + * iv_size must be 12, otherwise false is returned. + * key_size must be 16, 24 or 32, otherwise false is returned. + * tag_size must be 12, 13, 14, 15, 16, otherwise false is returned. + * If additional authenticated data verification fails, false is returned. + * + * @param[in] key Pointer to the encryption key. + * @param[in] key_size size of the encryption key in bytes. + * @param[in] iv Pointer to the IV value. + * @param[in] iv_size size of the IV value in bytes. + * @param[in] a_data Pointer to the additional authenticated data (AAD). + * @param[in] a_data_size size of the additional authenticated data (AAD) in bytes. + * @param[in] data_in Pointer to the input data buffer to be decrypted. + * @param[in] data_in_size size of the input data buffer in bytes. + * @param[in] tag Pointer to a buffer that contains the authentication tag. + * @param[in] tag_size size of the authentication tag in bytes. + * @param[out] data_out Pointer to a buffer that receives the decryption output. + * @param[out] data_out_size size of the output data buffer in bytes. + * + * @retval true AEAD AES-GCM authenticated decryption succeeded. + * @retval false AEAD AES-GCM authenticated decryption failed. + * + **/ +bool libspdm_aead_aes_gcm_decrypt(const uint8_t *key, size_t key_size, + const uint8_t *iv, size_t iv_size, + const uint8_t *a_data, size_t a_data_size, + const uint8_t *data_in, size_t data_in_size, + const uint8_t *tag, size_t tag_size, + uint8_t *data_out, size_t *data_out_size) +{ + mbedtls_gcm_context ctx; + int32_t ret; + + if (data_in_size > INT_MAX) { + return false; + } + if (a_data_size > INT_MAX) { + return false; + } + if (iv_size != 12) { + return false; + } + switch (key_size) { + case 16: + case 24: + case 32: + break; + default: + return false; + } + if ((tag_size != 12) && (tag_size != 13) && (tag_size != 14) && + (tag_size != 15) && (tag_size != 16)) { + return false; + } + if (data_out_size != NULL) { + if ((*data_out_size > INT_MAX) || + (*data_out_size < data_in_size)) { + return false; + } + } + + mbedtls_gcm_init(&ctx); + + ret = mbedtls_gcm_setkey(&ctx, MBEDTLS_CIPHER_ID_AES, key, + (uint32_t)(key_size * 8)); + if (ret != 0) { + return false; + } + + ret = mbedtls_gcm_auth_decrypt(&ctx, (uint32_t)data_in_size, iv, + (uint32_t)iv_size, a_data, + (uint32_t)a_data_size, tag, + (uint32_t)tag_size, data_in, data_out); + mbedtls_gcm_free(&ctx); + if (ret != 0) { + return false; + } + if (data_out_size != NULL) { + *data_out_size = data_in_size; + } + + return true; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hash/libspdm_sha.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hash/libspdm_sha.c new file mode 100644 index 0000000000..34bc4c42f9 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hash/libspdm_sha.c @@ -0,0 +1,623 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * SHA-256/384/512 digest Wrapper Implementation. + **/ + +#include "internal_crypt_lib.h" +#include +#include + +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA256 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha256_new() returns NULL. + * + **/ +void *libspdm_sha256_new(void) +{ + void *hmac_md_ctx; + + hmac_md_ctx = allocate_zero_pool(sizeof(mbedtls_sha256_context)); + if (hmac_md_ctx == NULL) { + return NULL; + } + + return hmac_md_ctx; +} + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha256_ctx Pointer to the HASH_CTX context to be released. + * + **/ +void libspdm_sha256_free(void *sha256_ctx) +{ + mbedtls_sha256_free(sha256_ctx); + free_pool (sha256_ctx); +} + +/** + * Initializes user-supplied memory pointed by sha256_context as SHA-256 hash context for + * subsequent use. + * + * If sha256_context is NULL, then return false. + * + * @param[out] sha256_context Pointer to SHA-256 context being initialized. + * + * @retval true SHA-256 context initialization succeeded. + * @retval false SHA-256 context initialization failed. + * + **/ +bool libspdm_sha256_init(void *sha256_context) +{ + int32_t ret; + + if (sha256_context == NULL) { + return false; + } + + mbedtls_sha256_init(sha256_context); + + ret = mbedtls_sha256_starts_ret(sha256_context, false); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Makes a copy of an existing SHA-256 context. + * + * If sha256_context is NULL, then return false. + * If new_sha256_context is NULL, then return false. + * + * @param[in] sha256_context Pointer to SHA-256 context being copied. + * @param[out] new_sha256_context Pointer to new SHA-256 context. + * + * @retval true SHA-256 context copy succeeded. + * @retval false SHA-256 context copy failed. + * + **/ +bool libspdm_sha256_duplicate(const void *sha256_context, + void *new_sha256_context) +{ + if (sha256_context == NULL || new_sha256_context == NULL) { + return false; + } + + mbedtls_sha256_clone(new_sha256_context, sha256_context); + + return true; +} + +/** + * Digests the input data and updates SHA-256 context. + * + * This function performs SHA-256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-256 context should be already correctly initialized by libspdm_sha256_init(), and should not be finalized + * by libspdm_sha256_final(). Behavior with invalid context is undefined. + * + * If sha256_context is NULL, then return false. + * + * @param[in, out] sha256_context Pointer to the SHA-256 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true SHA-256 data digest succeeded. + * @retval false SHA-256 data digest failed. + * + **/ +bool libspdm_sha256_update(void *sha256_context, const void *data, + size_t data_size) +{ + int32_t ret; + + if (sha256_context == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = mbedtls_sha256_update_ret(sha256_context, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Completes computation of the SHA-256 digest value. + * + * This function completes SHA-256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the SHA-256 context cannot + * be used again. + * SHA-256 context should be already correctly initialized by libspdm_sha256_init(), and should not be + * finalized by libspdm_sha256_final(). Behavior with invalid SHA-256 context is undefined. + * + * If sha256_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha256_context Pointer to the SHA-256 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-256 digest + * value (32 bytes). + * + * @retval true SHA-256 digest computation succeeded. + * @retval false SHA-256 digest computation failed. + * + **/ +bool libspdm_sha256_final(void *sha256_context, uint8_t *hash_value) +{ + int32_t ret; + + if (sha256_context == NULL || hash_value == NULL) { + return false; + } + + ret = mbedtls_sha256_finish_ret(sha256_context, hash_value); + mbedtls_sha256_free(sha256_context); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Computes the SHA-256 message digest of a input data buffer. + * + * This function performs the SHA-256 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-256 digest + * value (32 bytes). + * + * @retval true SHA-256 digest computation succeeded. + * @retval false SHA-256 digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_sha256_hash_all(const void *data, size_t data_size, + uint8_t *hash_value) +{ + int32_t ret; + + if (hash_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = mbedtls_sha256_ret(data, data_size, hash_value, false); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA384 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha384_new() returns NULL. + * + **/ +void *libspdm_sha384_new(void) +{ + void *hmac_md_ctx; + + hmac_md_ctx = allocate_zero_pool(sizeof(mbedtls_sha512_context)); + if (hmac_md_ctx == NULL) { + return NULL; + } + + return hmac_md_ctx; +} + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha384_ctx Pointer to the HASH_CTX context to be released. + * + **/ +void libspdm_sha384_free(void *sha384_ctx) +{ + mbedtls_sha512_free(sha384_ctx); + free_pool (sha384_ctx); +} + +/** + * Initializes user-supplied memory pointed by sha384_context as SHA-384 hash context for + * subsequent use. + * + * If sha384_context is NULL, then return false. + * + * @param[out] sha384_context Pointer to SHA-384 context being initialized. + * + * @retval true SHA-384 context initialization succeeded. + * @retval false SHA-384 context initialization failed. + * + **/ +bool libspdm_sha384_init(void *sha384_context) +{ + int32_t ret; + + if (sha384_context == NULL) { + return false; + } + + mbedtls_sha512_init(sha384_context); + + ret = mbedtls_sha512_starts_ret(sha384_context, true); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Makes a copy of an existing SHA-384 context. + * + * If sha384_context is NULL, then return false. + * If new_sha384_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha384_context Pointer to SHA-384 context being copied. + * @param[out] new_sha384_context Pointer to new SHA-384 context. + * + * @retval true SHA-384 context copy succeeded. + * @retval false SHA-384 context copy failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_sha384_duplicate(const void *sha384_context, + void *new_sha384_context) +{ + if (sha384_context == NULL || new_sha384_context == NULL) { + return false; + } + + mbedtls_sha512_clone(new_sha384_context, sha384_context); + + return true; +} + +/** + * Digests the input data and updates SHA-384 context. + * + * This function performs SHA-384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-384 context should be already correctly initialized by libspdm_sha384_init(), and should not be finalized + * by libspdm_sha384_final(). Behavior with invalid context is undefined. + * + * If sha384_context is NULL, then return false. + * + * @param[in, out] sha384_context Pointer to the SHA-384 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true SHA-384 data digest succeeded. + * @retval false SHA-384 data digest failed. + * + **/ +bool libspdm_sha384_update(void *sha384_context, const void *data, + size_t data_size) +{ + int32_t ret; + + if (sha384_context == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = mbedtls_sha512_update_ret(sha384_context, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Completes computation of the SHA-384 digest value. + * + * This function completes SHA-384 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the SHA-384 context cannot + * be used again. + * SHA-384 context should be already correctly initialized by libspdm_sha384_init(), and should not be + * finalized by libspdm_sha384_final(). Behavior with invalid SHA-384 context is undefined. + * + * If sha384_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha384_context Pointer to the SHA-384 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-384 digest + * value (48 bytes). + * + * @retval true SHA-384 digest computation succeeded. + * @retval false SHA-384 digest computation failed. + * + **/ +bool libspdm_sha384_final(void *sha384_context, uint8_t *hash_value) +{ + int32_t ret; + + if (sha384_context == NULL || hash_value == NULL) { + return false; + } + + ret = mbedtls_sha512_finish_ret(sha384_context, hash_value); + mbedtls_sha512_free(sha384_context); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Computes the SHA-384 message digest of a input data buffer. + * + * This function performs the SHA-384 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-384 digest + * value (48 bytes). + * + * @retval true SHA-384 digest computation succeeded. + * @retval false SHA-384 digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_sha384_hash_all(const void *data, size_t data_size, + uint8_t *hash_value) +{ + int32_t ret; + + if (hash_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = mbedtls_sha512_ret(data, data_size, hash_value, true); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Allocates and initializes one HASH_CTX context for subsequent SHA512 use. + * + * @return Pointer to the HASH_CTX context that has been initialized. + * If the allocations fails, libspdm_sha512_new() returns NULL. + * + **/ +void *libspdm_sha512_new(void) +{ + void *hmac_md_ctx; + + hmac_md_ctx = allocate_zero_pool(sizeof(mbedtls_sha512_context)); + if (hmac_md_ctx == NULL) { + return NULL; + } + + return hmac_md_ctx; +} + +/** + * Release the specified HASH_CTX context. + * + * @param[in] sha512_ctx Pointer to the HASH_CTX context to be released. + * + **/ +void libspdm_sha512_free(void *sha512_ctx) +{ + mbedtls_sha512_free(sha512_ctx); + free_pool (sha512_ctx); +} + +/** + * Initializes user-supplied memory pointed by sha512_context as SHA-512 hash context for + * subsequent use. + * + * If sha512_context is NULL, then return false. + * + * @param[out] sha512_context Pointer to SHA-512 context being initialized. + * + * @retval true SHA-512 context initialization succeeded. + * @retval false SHA-512 context initialization failed. + * + **/ +bool libspdm_sha512_init(void *sha512_context) +{ + int32_t ret; + + if (sha512_context == NULL) { + return false; + } + + mbedtls_sha512_init(sha512_context); + + ret = mbedtls_sha512_starts_ret(sha512_context, false); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Makes a copy of an existing SHA-512 context. + * + * If sha512_context is NULL, then return false. + * If new_sha512_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] sha512_context Pointer to SHA-512 context being copied. + * @param[out] new_sha512_context Pointer to new SHA-512 context. + * + * @retval true SHA-512 context copy succeeded. + * @retval false SHA-512 context copy failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_sha512_duplicate(const void *sha512_context, + void *new_sha512_context) +{ + if (sha512_context == NULL || new_sha512_context == NULL) { + return false; + } + + mbedtls_sha512_clone(new_sha512_context, sha512_context); + + return true; +} + +/** + * Digests the input data and updates SHA-512 context. + * + * This function performs SHA-512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * SHA-512 context should be already correctly initialized by libspdm_sha512_init(), and should not be finalized + * by libspdm_sha512_final(). Behavior with invalid context is undefined. + * + * If sha512_context is NULL, then return false. + * + * @param[in, out] sha512_context Pointer to the SHA-512 context. + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true SHA-512 data digest succeeded. + * @retval false SHA-512 data digest failed. + * + **/ +bool libspdm_sha512_update(void *sha512_context, const void *data, + size_t data_size) +{ + int32_t ret; + + if (sha512_context == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = mbedtls_sha512_update_ret(sha512_context, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Completes computation of the SHA-512 digest value. + * + * This function completes SHA-512 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the SHA-512 context cannot + * be used again. + * SHA-512 context should be already correctly initialized by libspdm_sha512_init(), and should not be + * finalized by libspdm_sha512_final(). Behavior with invalid SHA-512 context is undefined. + * + * If sha512_context is NULL, then return false. + * If hash_value is NULL, then return false. + * + * @param[in, out] sha512_context Pointer to the SHA-512 context. + * @param[out] hash_value Pointer to a buffer that receives the SHA-512 digest + * value (64 bytes). + * + * @retval true SHA-512 digest computation succeeded. + * @retval false SHA-512 digest computation failed. + * + **/ +bool libspdm_sha512_final(void *sha512_context, uint8_t *hash_value) +{ + int32_t ret; + + if (sha512_context == NULL || hash_value == NULL) { + return false; + } + + ret = mbedtls_sha512_finish_ret(sha512_context, hash_value); + mbedtls_sha512_free(sha512_context); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Computes the SHA-512 message digest of a input data buffer. + * + * This function performs the SHA-512 message digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be hashed. + * @param[in] data_size size of data buffer in bytes. + * @param[out] hash_value Pointer to a buffer that receives the SHA-512 digest + * value (64 bytes). + * + * @retval true SHA-512 digest computation succeeded. + * @retval false SHA-512 digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_sha512_hash_all(const void *data, size_t data_size, + uint8_t *hash_value) +{ + int32_t ret; + + if (hash_value == NULL) { + return false; + } + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = mbedtls_sha512_ret(data, data_size, hash_value, false); + if (ret != 0) { + return false; + } + return true; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hmac/libspdm_hmac_sha.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hmac/libspdm_hmac_sha.c new file mode 100644 index 0000000000..2948e0f288 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hmac/libspdm_hmac_sha.c @@ -0,0 +1,709 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * HMAC-SHA256/384/512 Wrapper Implementation. + **/ + +#include "internal_crypt_lib.h" +#include + +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-MD use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, hmac_md_new() returns NULL. + * + **/ +void *hmac_md_new(void) +{ + void *hmac_md_ctx; + + hmac_md_ctx = allocate_zero_pool(sizeof(mbedtls_md_context_t)); + if (hmac_md_ctx == NULL) { + return NULL; + } + + return hmac_md_ctx; +} + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_md_ctx Pointer to the HMAC_CTX context to be released. + * + **/ +void hmac_md_free(void *hmac_md_ctx) +{ + mbedtls_md_free(hmac_md_ctx); + free_pool (hmac_md_ctx); +} + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to hmac_md_update(). + * + * If hmac_md_ctx is NULL, then return false. + * + * @param[in] md_type message digest Type. + * @param[out] hmac_md_ctx Pointer to HMAC-MD context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * + **/ +bool hmac_md_set_key(const mbedtls_md_type_t md_type, void *hmac_md_ctx, + const uint8_t *key, size_t key_size) +{ + const mbedtls_md_info_t *md_info; + int32_t ret; + + if (hmac_md_ctx == NULL || key_size > INT_MAX) { + return false; + } + + libspdm_zero_mem(hmac_md_ctx, sizeof(mbedtls_md_context_t)); + mbedtls_md_init(hmac_md_ctx); + + md_info = mbedtls_md_info_from_type(md_type); + LIBSPDM_ASSERT(md_info != NULL); + + ret = mbedtls_md_setup(hmac_md_ctx, md_info, 1); + if (ret != 0) { + return false; + } + + ret = mbedtls_md_hmac_starts(hmac_md_ctx, key, key_size); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Return block size in md_type. + * This function is use to enable hmac_duplicate. + * + * @param[in] md_type mbedtls Type. + * + * @retval blocksize in md_type + **/ +int hmac_md_get_blocksize( mbedtls_md_type_t md_type ) +{ + switch( md_type ) + { + case MBEDTLS_MD_SHA256: + return 64; + case MBEDTLS_MD_SHA384: + return 128; + case MBEDTLS_MD_SHA512: + return 128; + default: + LIBSPDM_ASSERT(false); + return 0; + } +} + +/** + * Makes a copy of an existing HMAC-MD context. + * + * If hmac_md_ctx is NULL, then return false. + * If new_hmac_md_ctx is NULL, then return false. + * + * @param[in] md_type message digest Type. + * @param[in] hmac_md_ctx Pointer to HMAC-MD context being copied. + * @param[out] new_hmac_md_ctx Pointer to new HMAC-MD context. + * + * @retval true HMAC-MD context copy succeeded. + * @retval false HMAC-MD context copy failed. + * + **/ +bool hmac_md_duplicate(const mbedtls_md_type_t md_type, const void *hmac_md_ctx, + void *new_hmac_md_ctx) +{ + int32_t ret; + const mbedtls_md_info_t *md_info; + + if (hmac_md_ctx == NULL || new_hmac_md_ctx == NULL) { + return false; + } + + libspdm_zero_mem(new_hmac_md_ctx, sizeof(mbedtls_md_context_t)); + mbedtls_md_init(new_hmac_md_ctx); + + md_info = mbedtls_md_info_from_type(md_type); + LIBSPDM_ASSERT(md_info != NULL); + + ret = mbedtls_md_setup(new_hmac_md_ctx, md_info, 1); + if (ret != 0) { + return false; + } + ret = mbedtls_md_clone(new_hmac_md_ctx, hmac_md_ctx); + if (ret != 0) { + return false; + } + /*Temporary solution to the problem of context clone. + * There are not any standard function in mbedtls to clone a complete hmac context.*/ + libspdm_copy_mem(((mbedtls_md_context_t *)new_hmac_md_ctx)->hmac_ctx, + hmac_md_get_blocksize(md_type) * 2, + ((const mbedtls_md_context_t *)hmac_md_ctx)->hmac_ctx, + hmac_md_get_blocksize(md_type) * 2); + return true; +} + +/** + * Digests the input data and updates HMAC-MD context. + * + * This function performs HMAC-MD digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-MD context should be initialized by hmac_md_new(), and should not be finalized + * by hmac_md_final(). Behavior with invalid context is undefined. + * + * If hmac_md_ctx is NULL, then return false. + * + * @param[in, out] hmac_md_ctx Pointer to the HMAC-MD context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true HMAC-MD data digest succeeded. + * @retval false HMAC-MD data digest failed. + * + **/ +bool hmac_md_update(void *hmac_md_ctx, const void *data, + size_t data_size) +{ + int32_t ret; + + if (hmac_md_ctx == NULL) { + return false; + } + + if (data == NULL && data_size != 0) { + return false; + } + if (data_size > INT_MAX) { + return false; + } + + ret = mbedtls_md_hmac_update(hmac_md_ctx, data, data_size); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Completes computation of the HMAC-MD digest value. + * + * This function completes HMAC-MD hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-MD context cannot + * be used again. + * HMAC-MD context should be initialized by hmac_md_new(), and should not be finalized + * by hmac_md_final(). Behavior with invalid HMAC-MD context is undefined. + * + * If hmac_md_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_md_ctx Pointer to the HMAC-MD context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-MD digest + * value. + * + * @retval true HMAC-MD digest computation succeeded. + * @retval false HMAC-MD digest computation failed. + * + **/ +bool hmac_md_final(void *hmac_md_ctx, uint8_t *hmac_value) +{ + int32_t ret; + + if (hmac_md_ctx == NULL || hmac_value == NULL) { + return false; + } + + ret = mbedtls_md_hmac_finish(hmac_md_ctx, hmac_value); + mbedtls_md_free(hmac_md_ctx); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Computes the HMAC-MD digest of a input data buffer. + * + * This function performs the HMAC-MD digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] md_type message digest Type. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[out] hash_value Pointer to a buffer that receives the HMAC-MD digest + * value. + * + * @retval true HMAC-MD digest computation succeeded. + * @retval false HMAC-MD digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool hmac_md_all(const mbedtls_md_type_t md_type, const void *data, + size_t data_size, const uint8_t *key, size_t key_size, + uint8_t *hmac_value) +{ + const mbedtls_md_info_t *md_info; + int32_t ret; + + md_info = mbedtls_md_info_from_type(md_type); + LIBSPDM_ASSERT(md_info != NULL); + + ret = mbedtls_md_hmac(md_info, key, key_size, data, data_size, + hmac_value); + if (ret != 0) { + return false; + } + return true; +} + +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA256 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha256_new() returns NULL. + * + **/ +void *libspdm_hmac_sha256_new(void) +{ + return hmac_md_new(); +} + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha256_ctx Pointer to the HMAC_CTX context to be released. + * + **/ +void libspdm_hmac_sha256_free(void *hmac_sha256_ctx) +{ + hmac_md_free(hmac_sha256_ctx); +} + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha256_update(). + * + * If hmac_sha256_ctx is NULL, then return false. + * + * @param[out] hmac_sha256_ctx Pointer to HMAC-SHA256 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * + **/ +bool libspdm_hmac_sha256_set_key(void *hmac_sha256_ctx, const uint8_t *key, + size_t key_size) +{ + return hmac_md_set_key(MBEDTLS_MD_SHA256, hmac_sha256_ctx, key, + key_size); +} + +/** + * Makes a copy of an existing HMAC-SHA256 context. + * + * If hmac_sha256_ctx is NULL, then return false. + * If new_hmac_sha256_ctx is NULL, then return false. + * + * @param[in] hmac_sha256_ctx Pointer to HMAC-SHA256 context being copied. + * @param[out] new_hmac_sha256_ctx Pointer to new HMAC-SHA256 context. + * + * @retval true HMAC-SHA256 context copy succeeded. + * @retval false HMAC-SHA256 context copy failed. + * + **/ +bool libspdm_hmac_sha256_duplicate(const void *hmac_sha256_ctx, + void *new_hmac_sha256_ctx) +{ + return hmac_md_duplicate(MBEDTLS_MD_SHA256, hmac_sha256_ctx, new_hmac_sha256_ctx); +} + +/** + * Digests the input data and updates HMAC-SHA256 context. + * + * This function performs HMAC-SHA256 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA256 context should be initialized by libspdm_hmac_sha256_new(), and should not be finalized + * by libspdm_hmac_sha256_final(). Behavior with invalid context is undefined. + * + * If hmac_sha256_ctx is NULL, then return false. + * + * @param[in, out] hmac_sha256_ctx Pointer to the HMAC-SHA256 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true HMAC-SHA256 data digest succeeded. + * @retval false HMAC-SHA256 data digest failed. + * + **/ +bool libspdm_hmac_sha256_update(void *hmac_sha256_ctx, const void *data, + size_t data_size) +{ + return hmac_md_update(hmac_sha256_ctx, data, data_size); +} + +/** + * Completes computation of the HMAC-SHA256 digest value. + * + * This function completes HMAC-SHA256 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA256 context cannot + * be used again. + * HMAC-SHA256 context should be initialized by libspdm_hmac_sha256_new(), and should not be finalized + * by libspdm_hmac_sha256_final(). Behavior with invalid HMAC-SHA256 context is undefined. + * + * If hmac_sha256_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * + * @param[in, out] hmac_sha256_ctx Pointer to the HMAC-SHA256 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA256 digest computation succeeded. + * @retval false HMAC-SHA256 digest computation failed. + * + **/ +bool libspdm_hmac_sha256_final(void *hmac_sha256_ctx, uint8_t *hmac_value) +{ + return hmac_md_final(hmac_sha256_ctx, hmac_value); +} + +/** + * Computes the HMAC-SHA256 digest of a input data buffer. + * + * This function performs the HMAC-SHA256 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[out] hash_value Pointer to a buffer that receives the HMAC-SHA256 digest + * value (32 bytes). + * + * @retval true HMAC-SHA256 digest computation succeeded. + * @retval false HMAC-SHA256 digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha256_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value) +{ + return hmac_md_all(MBEDTLS_MD_SHA256, data, data_size, key, key_size, + hmac_value); +} + +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA384 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha384_new() returns NULL. + * + **/ +void *libspdm_hmac_sha384_new(void) +{ + return hmac_md_new(); +} + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha384_ctx Pointer to the HMAC_CTX context to be released. + * + **/ +void libspdm_hmac_sha384_free(void *hmac_sha384_ctx) +{ + hmac_md_free(hmac_sha384_ctx); +} + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha384_update(). + * + * If hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha384_ctx Pointer to HMAC-SHA384 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha384_set_key(void *hmac_sha384_ctx, const uint8_t *key, + size_t key_size) +{ + return hmac_md_set_key(MBEDTLS_MD_SHA384, hmac_sha384_ctx, key, + key_size); +} + +/** + * Makes a copy of an existing HMAC-SHA384 context. + * + * If hmac_sha384_ctx is NULL, then return false. + * If new_hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha384_ctx Pointer to HMAC-SHA384 context being copied. + * @param[out] new_hmac_sha384_ctx Pointer to new HMAC-SHA384 context. + * + * @retval true HMAC-SHA384 context copy succeeded. + * @retval false HMAC-SHA384 context copy failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha384_duplicate(const void *hmac_sha384_ctx, + void *new_hmac_sha384_ctx) +{ + return hmac_md_duplicate(MBEDTLS_MD_SHA384, hmac_sha384_ctx, new_hmac_sha384_ctx); +} + +/** + * Digests the input data and updates HMAC-SHA384 context. + * + * This function performs HMAC-SHA384 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA384 context should be initialized by libspdm_hmac_sha384_new(), and should not be finalized + * by libspdm_hmac_sha384_final(). Behavior with invalid context is undefined. + * + * If hmac_sha384_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha384_ctx Pointer to the HMAC-SHA384 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true HMAC-SHA384 data digest succeeded. + * @retval false HMAC-SHA384 data digest failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha384_update(void *hmac_sha384_ctx, const void *data, + size_t data_size) +{ + return hmac_md_update(hmac_sha384_ctx, data, data_size); +} + +/** + * Completes computation of the HMAC-SHA384 digest value. + * + * This function completes HMAC-SHA384 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA384 context cannot + * be used again. + * HMAC-SHA384 context should be initialized by libspdm_hmac_sha384_new(), and should not be finalized + * by libspdm_hmac_sha384_final(). Behavior with invalid HMAC-SHA384 context is undefined. + * + * If hmac_sha384_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha384_ctx Pointer to the HMAC-SHA384 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA384 digest computation succeeded. + * @retval false HMAC-SHA384 digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha384_final(void *hmac_sha384_ctx, uint8_t *hmac_value) +{ + return hmac_md_final(hmac_sha384_ctx, hmac_value); +} + +/** + * Computes the HMAC-SHA384 digest of a input data buffer. + * + * This function performs the HMAC-SHA384 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[out] hash_value Pointer to a buffer that receives the HMAC-SHA384 digest + * value (48 bytes). + * + * @retval true HMAC-SHA384 digest computation succeeded. + * @retval false HMAC-SHA384 digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha384_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value) +{ + return hmac_md_all(MBEDTLS_MD_SHA384, data, data_size, key, key_size, + hmac_value); +} + +/** + * Allocates and initializes one HMAC_CTX context for subsequent HMAC-SHA512 use. + * + * @return Pointer to the HMAC_CTX context that has been initialized. + * If the allocations fails, libspdm_hmac_sha512_new() returns NULL. + * + **/ +void *libspdm_hmac_sha512_new(void) +{ + return hmac_md_new(); +} + +/** + * Release the specified HMAC_CTX context. + * + * @param[in] hmac_sha512_ctx Pointer to the HMAC_CTX context to be released. + * + **/ +void libspdm_hmac_sha512_free(void *hmac_sha512_ctx) +{ + hmac_md_free(hmac_sha512_ctx); +} + +/** + * Set user-supplied key for subsequent use. It must be done before any + * calling to libspdm_hmac_sha512_update(). + * + * If hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] hmac_sha512_ctx Pointer to HMAC-SHA512 context. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * + * @retval true The key is set successfully. + * @retval false The key is set unsuccessfully. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha512_set_key(void *hmac_sha512_ctx, const uint8_t *key, + size_t key_size) +{ + return hmac_md_set_key(MBEDTLS_MD_SHA512, hmac_sha512_ctx, key, + key_size); +} + +/** + * Makes a copy of an existing HMAC-SHA512 context. + * + * If hmac_sha512_ctx is NULL, then return false. + * If new_hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] hmac_sha512_ctx Pointer to HMAC-SHA512 context being copied. + * @param[out] new_hmac_sha512_ctx Pointer to new HMAC-SHA512 context. + * + * @retval true HMAC-SHA512 context copy succeeded. + * @retval false HMAC-SHA512 context copy failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha512_duplicate(const void *hmac_sha512_ctx, + void *new_hmac_sha512_ctx) +{ + return hmac_md_duplicate(MBEDTLS_MD_SHA512, hmac_sha512_ctx, new_hmac_sha512_ctx); +} + +/** + * Digests the input data and updates HMAC-SHA512 context. + * + * This function performs HMAC-SHA512 digest on a data buffer of the specified size. + * It can be called multiple times to compute the digest of long or discontinuous data streams. + * HMAC-SHA512 context should be initialized by libspdm_hmac_sha512_new(), and should not be finalized + * by libspdm_hmac_sha512_final(). Behavior with invalid context is undefined. + * + * If hmac_sha512_ctx is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha512_ctx Pointer to the HMAC-SHA512 context. + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size size of data buffer in bytes. + * + * @retval true HMAC-SHA512 data digest succeeded. + * @retval false HMAC-SHA512 data digest failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha512_update(void *hmac_sha512_ctx, const void *data, + size_t data_size) +{ + return hmac_md_update(hmac_sha512_ctx, data, data_size); +} + +/** + * Completes computation of the HMAC-SHA512 digest value. + * + * This function completes HMAC-SHA512 hash computation and retrieves the digest value into + * the specified memory. After this function has been called, the HMAC-SHA512 context cannot + * be used again. + * HMAC-SHA512 context should be initialized by libspdm_hmac_sha512_new(), and should not be finalized + * by libspdm_hmac_sha512_final(). Behavior with invalid HMAC-SHA512 context is undefined. + * + * If hmac_sha512_ctx is NULL, then return false. + * If hmac_value is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] hmac_sha512_ctx Pointer to the HMAC-SHA512 context. + * @param[out] hmac_value Pointer to a buffer that receives the HMAC-SHA512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA512 digest computation succeeded. + * @retval false HMAC-SHA512 digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha512_final(void *hmac_sha512_ctx, uint8_t *hmac_value) +{ + return hmac_md_final(hmac_sha512_ctx, hmac_value); +} + +/** + * Computes the HMAC-SHA512 digest of a input data buffer. + * + * This function performs the HMAC-SHA512 digest of a given data buffer, and places + * the digest value into the specified memory. + * + * If this interface is not supported, then return false. + * + * @param[in] data Pointer to the buffer containing the data to be digested. + * @param[in] data_size size of data buffer in bytes. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[out] hash_value Pointer to a buffer that receives the HMAC-SHA512 digest + * value (64 bytes). + * + * @retval true HMAC-SHA512 digest computation succeeded. + * @retval false HMAC-SHA512 digest computation failed. + * @retval false This interface is not supported. + * + **/ +bool libspdm_hmac_sha512_all(const void *data, size_t data_size, + const uint8_t *key, size_t key_size, + uint8_t *hmac_value) +{ + return hmac_md_all(MBEDTLS_MD_SHA512, data, data_size, key, key_size, + hmac_value); +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/internal_crypt_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/internal_crypt_lib.h new file mode 100644 index 0000000000..5fd6035f44 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/internal_crypt_lib.h @@ -0,0 +1,28 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Internal include file for cryptlib. + **/ + +#ifndef __INTERNAL_CRYPT_LIB_H__ +#define __INTERNAL_CRYPT_LIB_H__ + +#include +#include "library/memlib.h" +#include "library/malloclib.h" +#include "library/debuglib.h" +#include "library/cryptlib.h" +#include "spdm_crypt_ext_lib/cryptlib_ext.h" + +/* We should alwasy add mbedtls/config.h here + * to ensure the config override takes effect.*/ + +#include + +int libspdm_myrand(void *rng_state, unsigned char *output, size_t len); + +#endif diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/kdf/libspdm_hkdf_sha.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/kdf/libspdm_hkdf_sha.c new file mode 100644 index 0000000000..71411cbc39 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/kdf/libspdm_hkdf_sha.c @@ -0,0 +1,386 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * HMAC-SHA256/384/512 KDF Wrapper Implementation. + * + * RFC 5869: HMAC-based Extract-and-Expand key Derivation Function (HKDF) + **/ + +#include "internal_crypt_lib.h" +#include + +/** + * Derive HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] md_type message digest Type. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[in] salt Pointer to the salt(non-secret) value. + * @param[in] salt_size salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool hkdf_md_extract_and_expand(const mbedtls_md_type_t md_type, + const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + const mbedtls_md_info_t *md; + int32_t ret; + + if (key == NULL || salt == NULL || info == NULL || out == NULL || + key_size > INT_MAX || salt_size > INT_MAX || info_size > INT_MAX || + out_size > INT_MAX) { + return false; + } + + md = mbedtls_md_info_from_type(md_type); + LIBSPDM_ASSERT(md != NULL); + + ret = mbedtls_hkdf(md, salt, (uint32_t)salt_size, key, (uint32_t)key_size, + info, (uint32_t)info_size, out, (uint32_t)out_size); + if (ret != 0) { + return false; + } + + return true; +} + +/** + * Derive HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] md_type message digest Type. + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[in] salt Pointer to the salt(non-secret) value. + * @param[in] salt_size salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool hkdf_md_extract(const mbedtls_md_type_t md_type, const uint8_t *key, + size_t key_size, const uint8_t *salt, + size_t salt_size, uint8_t *prk_out, + size_t prk_out_size) +{ + const mbedtls_md_info_t *md; + int32_t ret; + size_t md_size; + + if (key == NULL || salt == NULL || prk_out == NULL || + key_size > INT_MAX || salt_size > INT_MAX || + prk_out_size > INT_MAX) { + return false; + } + + md_size = 0; + switch (md_type) { + case MBEDTLS_MD_SHA256: + md_size = LIBSPDM_SHA256_DIGEST_SIZE; + break; + case MBEDTLS_MD_SHA384: + md_size = LIBSPDM_SHA384_DIGEST_SIZE; + break; + case MBEDTLS_MD_SHA512: + md_size = LIBSPDM_SHA512_DIGEST_SIZE; + break; + default: + return false; + } + if (prk_out_size != md_size) { + return false; + } + + md = mbedtls_md_info_from_type(md_type); + LIBSPDM_ASSERT(md != NULL); + + ret = mbedtls_hkdf_extract(md, salt, (uint32_t)salt_size, key, + (uint32_t)key_size, prk_out); + if (ret != 0) { + return false; + } + + return true; +} + +/** + * Derive HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] md_type message digest Type. + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool hkdf_md_expand(const mbedtls_md_type_t md_type, const uint8_t *prk, + size_t prk_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size) +{ + const mbedtls_md_info_t *md; + int32_t ret; + size_t md_size; + + if (prk == NULL || info == NULL || out == NULL || prk_size > INT_MAX || + info_size > INT_MAX || out_size > INT_MAX) { + return false; + } + + switch (md_type) { + case MBEDTLS_MD_SHA256: + md_size = LIBSPDM_SHA256_DIGEST_SIZE; + break; + case MBEDTLS_MD_SHA384: + md_size = LIBSPDM_SHA384_DIGEST_SIZE; + break; + case MBEDTLS_MD_SHA512: + md_size = LIBSPDM_SHA512_DIGEST_SIZE; + break; + default: + LIBSPDM_ASSERT(false); + return false; + } + if (prk_size != md_size) { + return false; + } + + md = mbedtls_md_info_from_type(md_type); + LIBSPDM_ASSERT(md != NULL); + + ret = mbedtls_hkdf_expand(md, prk, (uint32_t)prk_size, info, + (uint32_t)info_size, out, (uint32_t)out_size); + if (ret != 0) { + return false; + } + + return true; +} + +/** + * Derive SHA256 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[in] salt Pointer to the salt(non-secret) value. + * @param[in] salt_size salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha256_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return hkdf_md_extract_and_expand(MBEDTLS_MD_SHA256, key, key_size, + salt, salt_size, info, info_size, out, + out_size); +} + +/** + * Derive SHA256 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[in] salt Pointer to the salt(non-secret) value. + * @param[in] salt_size salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha256_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size) +{ + return hkdf_md_extract(MBEDTLS_MD_SHA256, key, key_size, salt, + salt_size, prk_out, prk_out_size); +} + +/** + * Derive SHA256 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha256_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return hkdf_md_expand(MBEDTLS_MD_SHA256, prk, prk_size, info, info_size, + out, out_size); +} + +/** + * Derive SHA384 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[in] salt Pointer to the salt(non-secret) value. + * @param[in] salt_size salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha384_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return hkdf_md_extract_and_expand(MBEDTLS_MD_SHA384, key, key_size, + salt, salt_size, info, info_size, out, + out_size); +} + +/** + * Derive SHA384 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[in] salt Pointer to the salt(non-secret) value. + * @param[in] salt_size salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha384_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size) +{ + return hkdf_md_extract(MBEDTLS_MD_SHA384, key, key_size, salt, + salt_size, prk_out, prk_out_size); +} + +/** + * Derive SHA384 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha384_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return hkdf_md_expand(MBEDTLS_MD_SHA384, prk, prk_size, info, info_size, + out, out_size); +} + +/** + * Derive SHA512 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[in] salt Pointer to the salt(non-secret) value. + * @param[in] salt_size salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha512_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return hkdf_md_extract_and_expand(MBEDTLS_MD_SHA512, key, key_size, + salt, salt_size, info, info_size, out, + out_size); +} + +/** + * Derive SHA512 HMAC-based Extract key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size key size in bytes. + * @param[in] salt Pointer to the salt(non-secret) value. + * @param[in] salt_size salt size in bytes. + * @param[out] prk_out Pointer to buffer to receive hkdf value. + * @param[in] prk_out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha512_extract(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + uint8_t *prk_out, size_t prk_out_size) +{ + return hkdf_md_extract(MBEDTLS_MD_SHA512, key, key_size, salt, + salt_size, prk_out, prk_out_size); +} + +/** + * Derive SHA512 HMAC-based Expand key Derivation Function (HKDF). + * + * @param[in] prk Pointer to the user-supplied key. + * @param[in] prk_size key size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + * + **/ +bool libspdm_hkdf_sha512_expand(const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size) +{ + return hkdf_md_expand(MBEDTLS_MD_SHA512, prk, prk_size, info, info_size, + out, out_size); +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_ec.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_ec.c new file mode 100644 index 0000000000..531c9550d1 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_ec.c @@ -0,0 +1,708 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Elliptic Curve Wrapper Implementation. + * + * RFC 8422 - Elliptic Curve Cryptography (ECC) Cipher Suites + * FIPS 186-4 - Digital signature Standard (DSS) + **/ + +#include "internal_crypt_lib.h" +#include +#include +#include +#include + +/** + * Allocates and Initializes one Elliptic Curve context for subsequent use + * with the NID. + * + * @param nid cipher NID + * + * @return Pointer to the Elliptic Curve context that has been initialized. + * If the allocations fails, libspdm_ec_new_by_nid() returns NULL. + * + **/ +void *libspdm_ec_new_by_nid(size_t nid) +{ + mbedtls_ecdh_context *ctx; + mbedtls_ecp_group_id grp_id; + int32_t ret; + + ctx = allocate_zero_pool(sizeof(mbedtls_ecdh_context)); + if (ctx == NULL) { + return NULL; + } + switch (nid) { + case LIBSPDM_CRYPTO_NID_SECP256R1: + case LIBSPDM_CRYPTO_NID_ECDSA_NIST_P256: + grp_id = MBEDTLS_ECP_DP_SECP256R1; + break; + case LIBSPDM_CRYPTO_NID_SECP384R1: + case LIBSPDM_CRYPTO_NID_ECDSA_NIST_P384: + grp_id = MBEDTLS_ECP_DP_SECP384R1; + break; + case LIBSPDM_CRYPTO_NID_SECP521R1: + case LIBSPDM_CRYPTO_NID_ECDSA_NIST_P521: + grp_id = MBEDTLS_ECP_DP_SECP521R1; + break; + default: + goto error; + } + + mbedtls_ecdh_init(ctx); + ret = mbedtls_ecdh_setup(ctx, grp_id); + if (ret != 0) { + goto error; + } + return ctx; +error: + free_pool(ctx); + return NULL; +} + +/** + * Release the specified EC context. + * + * @param[in] ec_context Pointer to the EC context to be released. + * + **/ +void libspdm_ec_free(void *ec_context) +{ + mbedtls_ecdh_free(ec_context); + free_pool(ec_context); +} + +/** + * Sets the public key component into the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] public Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true EC public key component was set successfully. + * @retval false Invalid EC public key component. + * + **/ +bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size) +{ + mbedtls_ecdh_context *ctx; + int32_t ret; + size_t half_size; + + if (ec_context == NULL || public_key == NULL) { + return false; + } + + ctx = ec_context; + switch (ctx->grp.id) { + case MBEDTLS_ECP_DP_SECP256R1: + half_size = 32; + break; + case MBEDTLS_ECP_DP_SECP384R1: + half_size = 48; + break; + case MBEDTLS_ECP_DP_SECP521R1: + half_size = 66; + break; + default: + return false; + } + if (public_key_size != half_size * 2) { + return false; + } + + ret = mbedtls_mpi_read_binary(&ctx->Q.X, public_key, half_size); + if (ret != 0) { + return false; + } + ret = mbedtls_mpi_read_binary(&ctx->Q.Y, public_key + half_size, + half_size); + if (ret != 0) { + return false; + } + ret = mbedtls_mpi_lset(&ctx->Q.Z, 1); + if (ret != 0) { + return false; + } + + return true; +} + +/** + * Sets the private key component into the established EC context. + * + * For P-256, the private_key_size is 32 byte. + * For P-384, the private_key_size is 48 byte. + * For P-521, the private_key_size is 66 byte. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] private_key Pointer to the private key buffer. + * @param[in] private_key_size The size of private key buffer in bytes. + * + * @retval true EC private key component was set successfully. + * @retval false Invalid EC private key component. + * + **/ +bool libspdm_ec_set_priv_key(void *ec_context, const uint8_t *private_key, + size_t private_key_size) +{ + mbedtls_ecdh_context *ctx; + int32_t ret; + size_t half_size; + + if (ec_context == NULL || private_key == NULL) { + return false; + } + + ctx = ec_context; + switch (ctx->grp.id) { + case MBEDTLS_ECP_DP_SECP256R1: + half_size = 32; + break; + case MBEDTLS_ECP_DP_SECP384R1: + half_size = 48; + break; + case MBEDTLS_ECP_DP_SECP521R1: + half_size = 66; + break; + default: + return false; + } + if (private_key_size != half_size) { + return false; + } + + ret = mbedtls_mpi_read_binary(&ctx->d, private_key, private_key_size); + if (ret != 0) { + return false; + } + + return true; +} + +/** + * Gets the public key component from the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true EC key component was retrieved successfully. + * @retval false Invalid EC key component. + * + **/ +bool libspdm_ec_get_pub_key(void *ec_context, uint8_t *public_key, + size_t *public_key_size) +{ + mbedtls_ecdh_context *ctx; + int32_t ret; + size_t half_size; + size_t x_size; + size_t y_size; + + if (ec_context == NULL || public_key_size == NULL) { + return false; + } + + if (public_key == NULL && *public_key_size != 0) { + return false; + } + + ctx = ec_context; + switch (ctx->grp.id) { + case MBEDTLS_ECP_DP_SECP256R1: + half_size = 32; + break; + case MBEDTLS_ECP_DP_SECP384R1: + half_size = 48; + break; + case MBEDTLS_ECP_DP_SECP521R1: + half_size = 66; + break; + default: + return false; + } + if (*public_key_size < half_size * 2) { + *public_key_size = half_size * 2; + return false; + } + *public_key_size = half_size * 2; + libspdm_zero_mem(public_key, *public_key_size); + + x_size = mbedtls_mpi_size(&ctx->Q.X); + y_size = mbedtls_mpi_size(&ctx->Q.Y); + LIBSPDM_ASSERT(x_size <= half_size && y_size <= half_size); + + ret = mbedtls_mpi_write_binary( + &ctx->Q.X, &public_key[0 + half_size - x_size], x_size); + if (ret != 0) { + return false; + } + ret = mbedtls_mpi_write_binary( + &ctx->Q.Y, &public_key[half_size + half_size - y_size], y_size); + if (ret != 0) { + return false; + } + + return true; +} + +/** + * Validates key components of EC context. + * NOTE: This function performs integrity checks on all the EC key material, so + * the EC key structure must contain all the private key data. + * + * If ec_context is NULL, then return false. + * + * @param[in] ec_context Pointer to EC context to check. + * + * @retval true EC key components are valid. + * @retval false EC key components are not valid. + * + **/ +bool libspdm_ec_check_key(const void *ec_context) +{ + /* TBD*/ + return true; +} + +/** + * Generates EC key and returns EC public key (X, Y). + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * EC context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * If ec_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] ec_context Pointer to the EC context. + * @param[out] public_data Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true EC public X,Y generation succeeded. + * @retval false EC public X,Y generation failed. + * @retval false public_size is not large enough. + * + **/ +bool libspdm_ec_generate_key(void *ec_context, uint8_t *public_data, + size_t *public_size) +{ + mbedtls_ecdh_context *ctx; + int32_t ret; + size_t half_size; + size_t x_size; + size_t y_size; + + if (ec_context == NULL || public_size == NULL) { + return false; + } + + if (public_data == NULL && *public_size != 0) { + return false; + } + + ctx = ec_context; + ret = mbedtls_ecdh_gen_public(&ctx->grp, &ctx->d, &ctx->Q, libspdm_myrand, + NULL); + if (ret != 0) { + return false; + } + + switch (ctx->grp.id) { + case MBEDTLS_ECP_DP_SECP256R1: + half_size = 32; + break; + case MBEDTLS_ECP_DP_SECP384R1: + half_size = 48; + break; + case MBEDTLS_ECP_DP_SECP521R1: + half_size = 66; + break; + default: + return false; + } + if (*public_size < half_size * 2) { + *public_size = half_size * 2; + return false; + } + *public_size = half_size * 2; + libspdm_zero_mem(public_data, *public_size); + + x_size = mbedtls_mpi_size(&ctx->Q.X); + y_size = mbedtls_mpi_size(&ctx->Q.Y); + LIBSPDM_ASSERT(x_size <= half_size && y_size <= half_size); + + ret = mbedtls_mpi_write_binary(&ctx->Q.X, + &public_data[0 + half_size - x_size], x_size); + if (ret != 0) { + return false; + } + ret = mbedtls_mpi_write_binary( + &ctx->Q.Y, &public_data[half_size + half_size - y_size], y_size); + if (ret != 0) { + return false; + } + + return true; +} + +/** + * Computes exchanged common key. + * + * Given peer's public key (X, Y), this function computes the exchanged common key, + * based on its own context including value of curve parameter and random secret. + * X is the first half of peer_public with size being peer_public_size / 2, + * Y is the second half of peer_public with size being peer_public_size / 2. + * + * If ec_context is NULL, then return false. + * If peer_public is NULL, then return false. + * If peer_public_size is 0, then return false. + * If key is NULL, then return false. + * If key_size is not large enough, then return false. + * + * For P-256, the peer_public_size is 64. first 32-byte is X, second 32-byte is Y. The key_size is 32. + * For P-384, the peer_public_size is 96. first 48-byte is X, second 48-byte is Y. The key_size is 48. + * For P-521, the peer_public_size is 132. first 66-byte is X, second 66-byte is Y. The key_size is 66. + * + * @param[in, out] ec_context Pointer to the EC context. + * @param[in] peer_public Pointer to the peer's public X,Y. + * @param[in] peer_public_size size of peer's public X,Y in bytes. + * @param[out] key Pointer to the buffer to receive generated key. + * @param[in, out] key_size On input, the size of key buffer in bytes. + * On output, the size of data returned in key buffer in bytes. + * + * @retval true EC exchanged key generation succeeded. + * @retval false EC exchanged key generation failed. + * @retval false key_size is not large enough. + * + **/ +bool libspdm_ec_compute_key(void *ec_context, const uint8_t *peer_public, + size_t peer_public_size, uint8_t *key, + size_t *key_size) +{ + mbedtls_ecdh_context *ctx; + size_t half_size; + int32_t ret; + + if (ec_context == NULL || peer_public == NULL || key_size == NULL || + key == NULL) { + return false; + } + + if (peer_public_size > INT_MAX) { + return false; + } + + ctx = ec_context; + switch (ctx->grp.id) { + case MBEDTLS_ECP_DP_SECP256R1: + half_size = 32; + break; + case MBEDTLS_ECP_DP_SECP384R1: + half_size = 48; + break; + case MBEDTLS_ECP_DP_SECP521R1: + half_size = 66; + break; + default: + return false; + } + if (peer_public_size != half_size * 2) { + return false; + } + + ret = mbedtls_mpi_read_binary(&ctx->Qp.X, peer_public, half_size); + if (ret != 0) { + return false; + } + ret = mbedtls_mpi_read_binary(&ctx->Qp.Y, peer_public + half_size, + half_size); + if (ret != 0) { + return false; + } + ret = mbedtls_mpi_lset(&ctx->Qp.Z, 1); + if (ret != 0) { + return false; + } + + ret = mbedtls_ecdh_compute_shared(&ctx->grp, &ctx->z, &ctx->Qp, &ctx->d, + libspdm_myrand, NULL); + if (ret != 0) { + return false; + } + + if (mbedtls_mpi_size(&ctx->z) > *key_size) { + return false; + } + + *key_size = ctx->grp.pbits / 8 + ((ctx->grp.pbits % 8) != 0); + ret = mbedtls_mpi_write_binary(&ctx->z, key, *key_size); + if (ret != 0) { + return false; + } + + return true; +} + +/** + * Carries out the EC-DSA signature. + * + * This function carries out the EC-DSA signature. + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If ec_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * For P-256, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For P-384, the sig_size is 96. first 48-byte is R, second 48-byte is S. + * For P-521, the sig_size is 132. first 66-byte is R, second 66-byte is S. + * + * @param[in] ec_context Pointer to EC context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive EC-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in EC-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + * + **/ +bool libspdm_ecdsa_sign(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size) +{ + int32_t ret; + mbedtls_ecdh_context *ctx; + mbedtls_mpi bn_r; + mbedtls_mpi bn_s; + size_t r_size; + size_t s_size; + size_t half_size; + + if (ec_context == NULL || message_hash == NULL) { + return false; + } + + if (signature == NULL) { + return false; + } + + ctx = ec_context; + switch (ctx->grp.id) { + case MBEDTLS_ECP_DP_SECP256R1: + half_size = 32; + break; + case MBEDTLS_ECP_DP_SECP384R1: + half_size = 48; + break; + case MBEDTLS_ECP_DP_SECP521R1: + half_size = 66; + break; + default: + return false; + } + if (*sig_size < (size_t)(half_size * 2)) { + *sig_size = half_size * 2; + return false; + } + *sig_size = half_size * 2; + libspdm_zero_mem(signature, *sig_size); + + switch (hash_nid) { + case LIBSPDM_CRYPTO_NID_SHA256: + if (hash_size != LIBSPDM_SHA256_DIGEST_SIZE) { + return false; + } + break; + + case LIBSPDM_CRYPTO_NID_SHA384: + if (hash_size != LIBSPDM_SHA384_DIGEST_SIZE) { + return false; + } + break; + + case LIBSPDM_CRYPTO_NID_SHA512: + if (hash_size != LIBSPDM_SHA512_DIGEST_SIZE) { + return false; + } + break; + + default: + return false; + } + + mbedtls_mpi_init(&bn_r); + mbedtls_mpi_init(&bn_s); + + ret = mbedtls_ecdsa_sign(&ctx->grp, &bn_r, &bn_s, &ctx->d, message_hash, + hash_size, libspdm_myrand, NULL); + if (ret != 0) { + return false; + } + + r_size = mbedtls_mpi_size(&bn_r); + s_size = mbedtls_mpi_size(&bn_s); + LIBSPDM_ASSERT(r_size <= half_size && s_size <= half_size); + + ret = mbedtls_mpi_write_binary( + &bn_r, &signature[0 + half_size - r_size], r_size); + if (ret != 0) { + mbedtls_mpi_free(&bn_r); + mbedtls_mpi_free(&bn_s); + return false; + } + ret = mbedtls_mpi_write_binary( + &bn_s, &signature[half_size + half_size - s_size], s_size); + if (ret != 0) { + mbedtls_mpi_free(&bn_r); + mbedtls_mpi_free(&bn_s); + return false; + } + + mbedtls_mpi_free(&bn_r); + mbedtls_mpi_free(&bn_s); + + return true; +} + +/** + * Verifies the EC-DSA signature. + * + * If ec_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. hash_nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, SHA3_512. + * + * For P-256, the sig_size is 64. first 32-byte is R, second 32-byte is S. + * For P-384, the sig_size is 96. first 48-byte is R, second 48-byte is S. + * For P-521, the sig_size is 132. first 66-byte is R, second 66-byte is S. + * + * @param[in] ec_context Pointer to EC context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size size of the message hash in bytes. + * @param[in] signature Pointer to EC-DSA signature to be verified. + * @param[in] sig_size size of signature in bytes. + * + * @retval true Valid signature encoded in EC-DSA. + * @retval false Invalid signature or invalid EC context. + * + **/ +bool libspdm_ecdsa_verify(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size) +{ + int32_t ret; + mbedtls_ecdh_context *ctx; + mbedtls_mpi bn_r; + mbedtls_mpi bn_s; + size_t half_size; + + if (ec_context == NULL || message_hash == NULL || signature == NULL) { + return false; + } + + if (sig_size > INT_MAX || sig_size == 0) { + return false; + } + + ctx = ec_context; + switch (ctx->grp.id) { + case MBEDTLS_ECP_DP_SECP256R1: + half_size = 32; + break; + case MBEDTLS_ECP_DP_SECP384R1: + half_size = 48; + break; + case MBEDTLS_ECP_DP_SECP521R1: + half_size = 66; + break; + default: + return false; + } + if (sig_size != (size_t)(half_size * 2)) { + return false; + } + + switch (hash_nid) { + case LIBSPDM_CRYPTO_NID_SHA256: + if (hash_size != LIBSPDM_SHA256_DIGEST_SIZE) { + return false; + } + break; + + case LIBSPDM_CRYPTO_NID_SHA384: + if (hash_size != LIBSPDM_SHA384_DIGEST_SIZE) { + return false; + } + break; + + case LIBSPDM_CRYPTO_NID_SHA512: + if (hash_size != LIBSPDM_SHA512_DIGEST_SIZE) { + return false; + } + break; + + default: + return false; + } + + mbedtls_mpi_init(&bn_r); + mbedtls_mpi_init(&bn_s); + + ret = mbedtls_mpi_read_binary(&bn_r, signature, half_size); + if (ret != 0) { + mbedtls_mpi_free(&bn_r); + mbedtls_mpi_free(&bn_s); + return false; + } + ret = mbedtls_mpi_read_binary(&bn_s, signature + half_size, half_size); + if (ret != 0) { + mbedtls_mpi_free(&bn_r); + mbedtls_mpi_free(&bn_s); + return false; + } + + ret = mbedtls_ecdsa_verify(&ctx->grp, message_hash, hash_size, &ctx->Q, + &bn_r, &bn_s); + mbedtls_mpi_free(&bn_r); + mbedtls_mpi_free(&bn_s); + + if (ret != 0) { + return false; + } + + return true; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_x509.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_x509.c new file mode 100644 index 0000000000..6b761f0dbd --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_x509.c @@ -0,0 +1,1845 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * X.509 Certificate Handler Wrapper Implementation. + **/ + +#include +#include "internal_crypt_lib.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* OID*/ + +#define OID_COMMON_NAME { 0x55, 0x04, 0x03 } +#define OID_ORGANIZATION_NAME { 0x55, 0x04, 0x0A } +#define OID_EXT_KEY_USAGE { 0x55, 0x1D, 0x25 } +#define OID_BASIC_CONSTRAINTS { 0x55, 0x1D, 0x13 } + +static const uint8_t m_libspdm_oid_common_name[] = OID_COMMON_NAME; +static const uint8_t m_libspdm_oid_organization_name[] = OID_ORGANIZATION_NAME; +static const uint8_t m_libspdm_oid_ext_key_usage[] = OID_EXT_KEY_USAGE; +static const uint8_t m_libspdm_oid_basic_constraints[] = OID_BASIC_CONSTRAINTS; + +/** + * Construct a X509 object from DER-encoded certificate data. + * + * If cert is NULL, then return false. + * If single_x509_cert is NULL, then return false. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[out] single_x509_cert The generated X509 object. + * + * @retval true The X509 object generation succeeded. + * @retval false The operation failed. + * + **/ +bool libspdm_x509_construct_certificate(const uint8_t *cert, size_t cert_size, + uint8_t **single_x509_cert) +{ + mbedtls_x509_crt *mbedtls_cert; + int32_t ret; + + if (cert == NULL || single_x509_cert == NULL || cert_size == 0) { + return false; + } + + mbedtls_cert = allocate_pool(sizeof(mbedtls_x509_crt)); + if (mbedtls_cert == NULL) { + return false; + } + + mbedtls_x509_crt_init(mbedtls_cert); + + *single_x509_cert = (uint8_t *)(void *)mbedtls_cert; + ret = mbedtls_x509_crt_parse_der(mbedtls_cert, cert, cert_size); + + return ret == 0; +} + +static bool libspdm_x509_construct_certificate_stack_v(uint8_t **x509_stack, + va_list args) +{ + uint8_t *cert; + size_t cert_size; + int32_t index; + int32_t ret; + + if (x509_stack == NULL) { + return false; + } + + ret = 0; + mbedtls_x509_crt *crt = (mbedtls_x509_crt *)*x509_stack; + if (crt == NULL) { + crt = allocate_pool(sizeof(mbedtls_x509_crt)); + if (crt == NULL) { + return false; + } + mbedtls_x509_crt_init(crt); + *x509_stack = (uint8_t *)crt; + } + + for (index = 0;; index++) { + + /* If cert is NULL, then it is the end of the list.*/ + + cert = va_arg(args, uint8_t *); + if (cert == NULL) { + break; + } + + cert_size = va_arg(args, size_t); + if (cert_size == 0) { + break; + } + + ret = mbedtls_x509_crt_parse_der(crt, cert, cert_size); + + if (ret != 0) { + break; + } + } + return ret == 0; +} + +/** + * Construct a X509 stack object from a list of DER-encoded certificate data. + * + * If x509_stack is NULL, then return false. + * + * @param[in, out] x509_stack On input, pointer to an existing or NULL X509 stack object. + * On output, pointer to the X509 stack object with new + * inserted X509 certificate. + * @param ... A list of DER-encoded single certificate data followed + * by certificate size. A NULL terminates the list. The + * pairs are the arguments to libspdm_x509_construct_certificate(). + * + * @retval true The X509 stack construction succeeded. + * @retval false The construction operation failed. + * + **/ +bool libspdm_x509_construct_certificate_stack(uint8_t **x509_stack, ...) +{ + va_list args; + bool result; + + va_start(args, x509_stack); + result = libspdm_x509_construct_certificate_stack_v(x509_stack, args); + va_end(args); + return result; +} + +/** + * Release the specified X509 object. + * + * If x509_cert is NULL, then return false. + * + * @param[in] x509_cert Pointer to the X509 object to be released. + * + **/ +void libspdm_x509_free(void *x509_cert) +{ + if (x509_cert) { + mbedtls_x509_crt_free(x509_cert); + free_pool(x509_cert); + } +} + +/** + * Release the specified X509 stack object. + * + * If x509_stack is NULL, then return false. + * + * @param[in] x509_stack Pointer to the X509 stack object to be released. + * + **/ +void libspdm_x509_stack_free(void *x509_stack) +{ + if (x509_stack == NULL) { + return; + } + + mbedtls_x509_crt_free(x509_stack); +} + +/** + * Retrieve the tag and length of the tag. + * + * @param ptr The position in the ASN.1 data + * @param end end of data + * @param length The variable that will receive the length + * @param tag The expected tag + * + * @retval true Get tag successful + * @retval FALSe Failed to get tag or tag not match + **/ +bool libspdm_asn1_get_tag(uint8_t **ptr, const uint8_t *end, size_t *length, + uint32_t tag) +{ + if (mbedtls_asn1_get_tag(ptr, end, length, (int32_t)tag) == 0) { + return true; + } else { + return false; + } +} + +/** + * Retrieve the subject bytes from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] cert_subject Pointer to the retrieved certificate subject bytes. + * @param[in, out] subject_size The size in bytes of the cert_subject buffer on input, + * and the size of buffer returned cert_subject on output. + * + * If cert is NULL, then return false. + * If subject_size is NULL, then return false. + * + * @retval true The certificate subject retrieved successfully. + * @retval false Invalid certificate, or the subject_size is too small for the result. + * The subject_size will be updated with the required size. + * + **/ +bool libspdm_x509_get_subject_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_subject, + size_t *subject_size) +{ + mbedtls_x509_crt crt; + int32_t ret; + bool status; + + if (cert == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + if (*subject_size < crt.subject_raw.len) { + *subject_size = crt.subject_raw.len; + status = false; + goto cleanup; + } + if (cert_subject != NULL) { + libspdm_copy_mem(cert_subject, *subject_size, + crt.subject_raw.p, crt.subject_raw.len); + } + *subject_size = crt.subject_raw.len; + status = true; + } + +cleanup: + mbedtls_x509_crt_free(&crt); + + return status; +} + +bool +libspdm_internal_x509_get_nid_name(mbedtls_x509_name *name, const uint8_t *oid, + size_t oid_size, char *common_name, + size_t *common_name_size) +{ + mbedtls_asn1_named_data *data; + + data = mbedtls_asn1_find_named_data(name, (const char *)oid, oid_size); + if (data != NULL) { + if (*common_name_size <= data->val.len) { + *common_name_size = data->val.len + 1; + return false; + } + if (common_name != NULL) { + libspdm_copy_mem(common_name, *common_name_size, data->val.p, data->val.len); + common_name[data->val.len] = '\0'; + } + *common_name_size = data->val.len + 1; + return true; + } else { + *common_name_size = 0; + return false; + } +} + +bool +libspdm_internal_x509_get_subject_nid_name(const uint8_t *cert, size_t cert_size, + const uint8_t *oid, size_t oid_size, + char *common_name, + size_t *common_name_size) +{ + mbedtls_x509_crt crt; + int32_t ret; + mbedtls_x509_name *name; + bool status; + + if (cert == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + name = &(crt.subject); + status = libspdm_internal_x509_get_nid_name( + name, oid, oid_size, common_name, common_name_size); + } + + mbedtls_x509_crt_free(&crt); + + return status; +} + +bool +libspdm_internal_x509_get_issuer_nid_name(const uint8_t *cert, size_t cert_size, + const uint8_t *oid, size_t oid_size, + char *common_name, + size_t *common_name_size) +{ + mbedtls_x509_crt crt; + int32_t ret; + mbedtls_x509_name *name; + bool status; + + if (cert == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + name = &(crt.issuer); + status = libspdm_internal_x509_get_nid_name( + name, oid, oid_size, common_name, common_name_size); + } + + mbedtls_x509_crt_free(&crt); + + return status; +} + +/** + * Retrieve the common name (CN) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] common_name buffer to contain the retrieved certificate common + * name string. At most common_name_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] common_name_size The size in bytes of the common_name buffer on input, + * and the size of buffer returned common_name on output. + * If common_name is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval RETURN_SUCCESS The certificate common_name retrieved successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL. + * If common_name_size is NULL. + * If common_name is not NULL and *common_name_size is 0. + * If Certificate is invalid. + * @retval RETURN_NOT_FOUND If no common_name entry exists. + * @retval RETURN_BUFFER_TOO_SMALL If the common_name is NULL. The required buffer size + * (including the final null) is returned in the + * common_name_size parameter. + * @retval RETURN_UNSUPPORTED The operation is not supported. + * + **/ +bool libspdm_x509_get_common_name(const uint8_t *cert, size_t cert_size, + char *common_name, + size_t *common_name_size) +{ + return libspdm_internal_x509_get_subject_nid_name( + cert, cert_size, (const uint8_t *)m_libspdm_oid_common_name, + sizeof(m_libspdm_oid_common_name), common_name, common_name_size); +} + +/** + * Retrieve the organization name (O) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] name_buffer buffer to contain the retrieved certificate organization + * name string. At most name_buffer_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval RETURN_SUCCESS The certificate Organization name retrieved successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL. + * If name_buffer_size is NULL. + * If name_buffer is not NULL and *common_name_size is 0. + * If Certificate is invalid. + * @retval RETURN_NOT_FOUND If no Organization name entry exists. + * @retval RETURN_BUFFER_TOO_SMALL If the name_buffer is NULL. The required buffer size + * (including the final null) is returned in the + * common_name_size parameter. + * @retval RETURN_UNSUPPORTED The operation is not supported. + * + **/ +bool +libspdm_x509_get_organization_name(const uint8_t *cert, size_t cert_size, + char *name_buffer, + size_t *name_buffer_size) +{ + return libspdm_internal_x509_get_subject_nid_name( + cert, cert_size, m_libspdm_oid_organization_name, + sizeof(m_libspdm_oid_organization_name), name_buffer, name_buffer_size); +} + +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +/** + * Retrieve the RSA public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * RSA public key component. Use libspdm_rsa_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If rsa_context is NULL, then return false. + * + * @retval true RSA public key was retrieved successfully. + * @retval false Fail to retrieve RSA public key from X509 certificate. + * + **/ +bool libspdm_rsa_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **rsa_context) +{ + mbedtls_x509_crt crt; + mbedtls_rsa_context *rsa; + int32_t ret; + + mbedtls_x509_crt_init(&crt); + + if (mbedtls_x509_crt_parse_der(&crt, cert, cert_size) != 0) { + return false; + } + + if (mbedtls_pk_get_type(&crt.pk) != MBEDTLS_PK_RSA) { + mbedtls_x509_crt_free(&crt); + return false; + } + + rsa = libspdm_rsa_new(); + if (rsa == NULL) { + mbedtls_x509_crt_free(&crt); + return false; + } + ret = mbedtls_rsa_copy(rsa, mbedtls_pk_rsa(crt.pk)); + if (ret != 0) { + libspdm_rsa_free(rsa); + mbedtls_x509_crt_free(&crt); + return false; + } + mbedtls_x509_crt_free(&crt); + + *rsa_context = rsa; + return true; +} +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + +/** + * Retrieve the EC public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * EC public key component. Use libspdm_ec_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ec_context is NULL, then return false. + * + * @retval true EC public key was retrieved successfully. + * @retval false Fail to retrieve EC public key from X509 certificate. + * + **/ +bool libspdm_ec_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ec_context) +{ + mbedtls_x509_crt crt; + mbedtls_ecdh_context *ecdh; + int32_t ret; + + mbedtls_x509_crt_init(&crt); + + if (mbedtls_x509_crt_parse_der(&crt, cert, cert_size) != 0) { + return false; + } + + if (mbedtls_pk_get_type(&crt.pk) != MBEDTLS_PK_ECKEY) { + mbedtls_x509_crt_free(&crt); + return false; + } + + ecdh = allocate_zero_pool(sizeof(mbedtls_ecdh_context)); + if (ecdh == NULL) { + mbedtls_x509_crt_free(&crt); + return false; + } + mbedtls_ecdh_init(ecdh); + + ret = mbedtls_ecdh_get_params(ecdh, mbedtls_pk_ec(crt.pk), + MBEDTLS_ECDH_OURS); + if (ret != 0) { + mbedtls_ecdh_free(ecdh); + free_pool(ecdh); + mbedtls_x509_crt_free(&crt); + return false; + } + mbedtls_x509_crt_free(&crt); + + *ec_context = ecdh; + return true; +} + +/** + * Retrieve the Ed public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * Ed public key component. Use libspdm_ecd_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true Ed public key was retrieved successfully. + * @retval false Fail to retrieve Ed public key from X509 certificate. + * + **/ +bool libspdm_ecd_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **ecd_context) +{ + return false; +} + +/** + * Retrieve the sm2 public key from one DER-encoded X509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * sm2 public key component. Use sm2_free() function to free the + * resource. + * + * If cert is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true sm2 public key was retrieved successfully. + * @retval false Fail to retrieve sm2 public key from X509 certificate. + * + **/ +bool libspdm_sm2_get_public_key_from_x509(const uint8_t *cert, size_t cert_size, + void **sm2_context) +{ + return false; +} + +/** + * Verify one X509 certificate was issued by the trusted CA. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate to be verified. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[in] ca_cert Pointer to the DER-encoded trusted CA certificate. + * @param[in] ca_cert_size size of the CA Certificate in bytes. + * + * If cert is NULL, then return false. + * If ca_cert is NULL, then return false. + * + * @retval true The certificate was issued by the trusted CA. + * @retval false Invalid certificate or the certificate was not issued by the given + * trusted CA. + * + **/ +bool libspdm_x509_verify_cert(const uint8_t *cert, size_t cert_size, + const uint8_t *ca_cert, size_t ca_cert_size) +{ + int32_t ret; + mbedtls_x509_crt ca, end; + uint32_t v_flag = 0; + mbedtls_x509_crt_profile profile = { 0 }; + + if (cert == NULL || ca_cert == NULL) { + return false; + } + + libspdm_copy_mem(&profile, sizeof(profile), + &mbedtls_x509_crt_profile_default, + sizeof(mbedtls_x509_crt_profile)); + + mbedtls_x509_crt_init(&ca); + mbedtls_x509_crt_init(&end); + + ret = mbedtls_x509_crt_parse_der(&ca, ca_cert, ca_cert_size); + + if (ret == 0) { + ret = mbedtls_x509_crt_parse_der(&end, cert, cert_size); + } + + if (ret == 0) { + ret = mbedtls_x509_crt_verify_with_profile( + &end, &ca, NULL, &profile, NULL, &v_flag, NULL, NULL); + } + + mbedtls_x509_crt_free(&ca); + mbedtls_x509_crt_free(&end); + + return ret == 0; +} + +/** + * Verify one X509 certificate was issued by the trusted CA. + * + * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates + * where the first certificate is signed by the Root + * Certificate or is the Root Cerificate itself. and + * subsequent cerificate is signed by the preceding + * cerificate. + * @param[in] cert_chain_length Total length of the certificate chain, in bytes. + * + * @param[in] root_cert Trusted Root Certificate buffer + * + * @param[in] root_cert_length Trusted Root Certificate buffer length + * + * @retval true All cerificates was issued by the first certificate in X509Certchain. + * @retval false Invalid certificate or the certificate was not issued by the given + * trusted CA. + **/ +bool libspdm_x509_verify_cert_chain(const uint8_t *root_cert, size_t root_cert_length, + const uint8_t *cert_chain, size_t cert_chain_length) +{ + size_t asn1_len; + size_t preceding_cert_len; + const uint8_t *preceding_cert; + size_t current_cert_len; + const uint8_t *current_cert; + const uint8_t *tmp_ptr; + uint32_t ret; + bool verify_flag; + + verify_flag = false; + preceding_cert = root_cert; + preceding_cert_len = root_cert_length; + + current_cert = cert_chain; + + + /* Get Current certificate from certificates buffer and Verify with preciding cert*/ + + do { + tmp_ptr = current_cert; + ret = mbedtls_asn1_get_tag( + (unsigned char **)&tmp_ptr, cert_chain + cert_chain_length, &asn1_len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + break; + } + + current_cert_len = asn1_len + (tmp_ptr - current_cert); + + if (libspdm_x509_verify_cert(current_cert, current_cert_len, + preceding_cert, + preceding_cert_len) == false) { + verify_flag = false; + break; + } else { + verify_flag = true; + } + + + /* Save preceding certificate*/ + + preceding_cert = current_cert; + preceding_cert_len = current_cert_len; + + + /* Move current certificate to next;*/ + + current_cert = current_cert + current_cert_len; + } while (true); + + return verify_flag; +} + +/** + * Get one X509 certificate from cert_chain. + * + * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates + * where the first certificate is signed by the Root + * Certificate or is the Root Cerificate itself. and + * subsequent cerificate is signed by the preceding + * cerificate. + * @param[in] cert_chain_length Total length of the certificate chain, in bytes. + * + * @param[in] cert_index index of certificate. + * + * @param[out] cert The certificate at the index of cert_chain. + * @param[out] cert_length The length certificate at the index of cert_chain. + * + * @retval true Success. + * @retval false Failed to get certificate from certificate chain. + **/ +bool libspdm_x509_get_cert_from_cert_chain(const uint8_t *cert_chain, + size_t cert_chain_length, + const int32_t cert_index, const uint8_t **cert, + size_t *cert_length) +{ + size_t asn1_len; + int32_t current_index; + size_t current_cert_len; + const uint8_t *current_cert; + const uint8_t *tmp_ptr; + int32_t ret; + + current_cert_len = 0; + + /* Check input parameters.*/ + + if ((cert_chain == NULL) || (cert == NULL) || (cert_index < -1) || + (cert_length == NULL)) { + return false; + } + + current_cert = cert_chain; + current_index = -1; + + + /* Traverse the certificate chain*/ + + while (true) { + + /* Get asn1 tag len*/ + + tmp_ptr = current_cert; + ret = mbedtls_asn1_get_tag( + (unsigned char **)&tmp_ptr, cert_chain + cert_chain_length, &asn1_len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + break; + } + + current_cert_len = asn1_len + (tmp_ptr - current_cert); + current_index++; + + if (current_index == cert_index) { + *cert = current_cert; + *cert_length = current_cert_len; + return true; + } + + + /* Move to next*/ + + current_cert = current_cert + current_cert_len; + } + + + /* If cert_index is -1, Return the last certificate*/ + + if (cert_index == -1 && current_index >= 0) { + *cert = current_cert - current_cert_len; + *cert_length = current_cert_len; + return true; + } + + return false; +} + +/** + * Retrieve the TBSCertificate from one given X.509 certificate. + * + * @param[in] cert Pointer to the given DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] tbs_cert DER-Encoded to-Be-Signed certificate. + * @param[out] tbs_cert_size size of the TBS certificate in bytes. + * + * If cert is NULL, then return false. + * If tbs_cert is NULL, then return false. + * If tbs_cert_size is NULL, then return false. + * + * @retval true The TBSCertificate was retrieved successfully. + * @retval false Invalid X.509 certificate. + * + **/ +bool libspdm_x509_get_tbs_cert(const uint8_t *cert, size_t cert_size, + uint8_t **tbs_cert, size_t *tbs_cert_size) +{ + return false; +} + +/** + * Retrieve the version from one X.509 certificate. + * + * If cert is NULL, then return false. + * If cert_size is 0, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] version Pointer to the retrieved version integer. + * + * @retval RETURN_SUCCESS The certificate version retrieved successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL or cert_size is Zero. + * @retval RETURN_UNSUPPORTED The operation is not supported. + * + **/ +bool libspdm_x509_get_version(const uint8_t *cert, size_t cert_size, + size_t *version) +{ + mbedtls_x509_crt crt; + int32_t ret; + bool status; + + if (cert == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + *version = crt.version - 1; + status = true; + } + + mbedtls_x509_crt_free(&crt); + + return status; +} + +/** + * Retrieve the serialNumber from one X.509 certificate. + * + * If cert is NULL, then return false. + * If cert_size is 0, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] serial_number Pointer to the retrieved certificate serial_number bytes. + * @param[in, out] serial_number_size The size in bytes of the serial_number buffer on input, + * and the size of buffer returned serial_number on output. + * + * @retval RETURN_SUCCESS The certificate serialNumber retrieved successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL or cert_size is Zero. + * If serial_number_size is NULL. + * If Certificate is invalid. + * @retval RETURN_NOT_FOUND If no serial_number exists. + * @retval RETURN_BUFFER_TOO_SMALL If the serial_number is NULL. The required buffer size + * (including the final null) is returned in the + * serial_number_size parameter. + * @retval RETURN_UNSUPPORTED The operation is not supported. + **/ +bool libspdm_x509_get_serial_number(const uint8_t *cert, size_t cert_size, + uint8_t *serial_number, + size_t *serial_number_size) +{ + mbedtls_x509_crt crt; + int32_t ret; + bool status; + + if (cert == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + if (*serial_number_size <= crt.serial.len) { + *serial_number_size = crt.serial.len + 1; + status = false; + goto cleanup; + } + if (serial_number != NULL) { + libspdm_copy_mem(serial_number, *serial_number_size, crt.serial.p, crt.serial.len); + serial_number[crt.serial.len] = '\0'; + } + *serial_number_size = crt.serial.len + 1; + status = true; + } +cleanup: + mbedtls_x509_crt_free(&crt); + + return status; +} + +/** + * Retrieve the issuer bytes from one X.509 certificate. + * + * If cert is NULL, then return false. + * If issuer_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] cert_issuer Pointer to the retrieved certificate subject bytes. + * @param[in, out] issuer_size The size in bytes of the cert_issuer buffer on input, + * and the size of buffer returned cert_issuer on output. + * + * @retval true The certificate issuer retrieved successfully. + * @retval false Invalid certificate, or the issuer_size is too small for the result. + * The issuer_size will be updated with the required size. + * @retval false This interface is not supported. + * + **/ +bool libspdm_x509_get_issuer_name(const uint8_t *cert, size_t cert_size, + uint8_t *cert_issuer, + size_t *issuer_size) +{ + mbedtls_x509_crt crt; + int32_t ret; + bool status; + + if (cert == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + if (*issuer_size < crt.issuer_raw.len) { + *issuer_size = crt.issuer_raw.len; + status = false; + goto cleanup; + } + if (cert_issuer != NULL) { + libspdm_copy_mem(cert_issuer, *issuer_size, crt.issuer_raw.p, crt.issuer_raw.len); + } + *issuer_size = crt.issuer_raw.len; + status = true; + } + +cleanup: + mbedtls_x509_crt_free(&crt); + + return status; +} + +/** + * Retrieve the issuer common name (CN) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] common_name buffer to contain the retrieved certificate issuer common + * name string. At most common_name_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] common_name_size The size in bytes of the common_name buffer on input, + * and the size of buffer returned common_name on output. + * If common_name is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval RETURN_SUCCESS The certificate Issuer common_name retrieved successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL. + * If common_name_size is NULL. + * If common_name is not NULL and *common_name_size is 0. + * If Certificate is invalid. + * @retval RETURN_NOT_FOUND If no common_name entry exists. + * @retval RETURN_BUFFER_TOO_SMALL If the common_name is NULL. The required buffer size + * (including the final null) is returned in the + * common_name_size parameter. + * @retval RETURN_UNSUPPORTED The operation is not supported. + * + **/ +bool +libspdm_x509_get_issuer_common_name(const uint8_t *cert, size_t cert_size, + char *common_name, + size_t *common_name_size) +{ + return libspdm_internal_x509_get_issuer_nid_name(cert, cert_size, + m_libspdm_oid_common_name, + sizeof(m_libspdm_oid_common_name), + common_name, common_name_size); +} + +/** + * Retrieve the issuer organization name (O) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] name_buffer buffer to contain the retrieved certificate issuer organization + * name string. At most name_buffer_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval RETURN_SUCCESS The certificate issuer Organization name retrieved successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL. + * If name_buffer_size is NULL. + * If name_buffer is not NULL and *common_name_size is 0. + * If Certificate is invalid. + * @retval RETURN_NOT_FOUND If no Organization name entry exists. + * @retval RETURN_BUFFER_TOO_SMALL If the name_buffer is NULL. The required buffer size + * (including the final null) is returned in the + * common_name_size parameter. + * @retval RETURN_UNSUPPORTED The operation is not supported. + * + **/ +bool +libspdm_x509_get_issuer_orgnization_name(const uint8_t *cert, size_t cert_size, + char *name_buffer, + size_t *name_buffer_size) +{ + return libspdm_internal_x509_get_issuer_nid_name( + cert, cert_size, m_libspdm_oid_organization_name, + sizeof(m_libspdm_oid_organization_name), name_buffer, name_buffer_size); +} + +/** + * Retrieve the signature algorithm from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] oid signature algorithm Object identifier buffer. + * @param[in,out] oid_size signature algorithm Object identifier buffer size + * + * @retval RETURN_SUCCESS The certificate Extension data retrieved successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL. + * If oid_size is NULL. + * If oid is not NULL and *oid_size is 0. + * If Certificate is invalid. + * @retval RETURN_NOT_FOUND If no SignatureType. + * @retval RETURN_BUFFER_TOO_SMALL If the oid is NULL. The required buffer size + * is returned in the oid_size. + * @retval RETURN_UNSUPPORTED The operation is not supported. + **/ +bool libspdm_x509_get_signature_algorithm(const uint8_t *cert, + size_t cert_size, uint8_t *oid, + size_t *oid_size) +{ + mbedtls_x509_crt crt; + int32_t ret; + bool status; + + if (cert == NULL || cert_size == 0 || oid_size == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + if (*oid_size < crt.sig_oid.len) { + *oid_size = crt.serial.len; + status = false; + goto cleanup; + } + if (oid != NULL) { + libspdm_copy_mem(oid, *oid_size, crt.sig_oid.p, crt.sig_oid.len); + } + *oid_size = crt.sig_oid.len; + status = true; + } + +cleanup: + mbedtls_x509_crt_free(&crt); + + return status; +} + +/** + * Find first Extension data match with given OID + * + * @param[in] start Pointer to the DER-encoded extensions data + * @param[in] end extensions data size in bytes + * @param[in ] oid OID for match + * @param[in ] oid_size OID size in bytes + * @param[out] find_extension_data output matched extension data. + * @param[out] find_extension_data_len matched extension data size. + * + **/ +static bool +libspdm_internal_x509_find_extension_data(uint8_t *start, uint8_t *end, const uint8_t *oid, + size_t oid_size, uint8_t **find_extension_data, + size_t *find_extension_data_len) +{ + uint8_t *ptr; + uint8_t *extension_ptr; + size_t obj_len; + int32_t ret; + bool status; + size_t find_extension_len; + size_t header_len; + + /*If no Extension entry match oid*/ + status = false; + ptr = start; + + ret = 0; + + while (true) { + /* + * Extension ::= SEQUENCE { + * extnID OBJECT IDENTIFIER, + * critical bool DEFAULT false, + * extnValue OCTET STRING } + */ + extension_ptr = ptr; + ret = mbedtls_asn1_get_tag(&ptr, end, &obj_len, + MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret == 0) { + header_len = (size_t)(ptr - extension_ptr); + find_extension_len = obj_len; + /* Get Object Identifier*/ + ret = mbedtls_asn1_get_tag(&ptr, end, &obj_len, + MBEDTLS_ASN1_OID); + } else { + break; + } + + if (ret == 0 && libspdm_const_compare_mem(ptr, oid, oid_size) == 0) { + ptr += obj_len; + + ret = mbedtls_asn1_get_tag(&ptr, end, &obj_len, + MBEDTLS_ASN1_BOOLEAN); + if (ret == 0) { + ptr += obj_len; + } + + ret = mbedtls_asn1_get_tag(&ptr, end, &obj_len, + MBEDTLS_ASN1_OCTET_STRING); + } else { + ret = 1; + } + + if (ret == 0) { + *find_extension_data = ptr; + *find_extension_data_len = obj_len; + status = true; + break; + } + + /* move to next*/ + ptr = extension_ptr + header_len + find_extension_len; + ret = 0; + } + + return status; +} + +/** + * Retrieve Extension data from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[in] oid Object identifier buffer + * @param[in] oid_size Object identifier buffer size + * @param[out] extension_data Extension bytes. + * @param[in, out] extension_data_size Extension bytes size. + * + * @retval RETURN_SUCCESS The certificate Extension data retrieved successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL. + * If extension_data_size is NULL. + * If extension_data is not NULL and *extension_data_size is 0. + * If Certificate is invalid. + * @retval RETURN_NOT_FOUND If no Extension entry match oid. + * @retval RETURN_BUFFER_TOO_SMALL If the extension_data is NULL. The required buffer size + * is returned in the extension_data_size parameter. + * @retval RETURN_UNSUPPORTED The operation is not supported. + **/ +bool libspdm_x509_get_extension_data(const uint8_t *cert, size_t cert_size, + const uint8_t *oid, size_t oid_size, + uint8_t *extension_data, + size_t *extension_data_size) +{ + mbedtls_x509_crt crt; + int32_t ret; + bool status; + uint8_t *ptr; + uint8_t *end; + size_t obj_len; + + ptr = NULL; + end = NULL; + obj_len = 0; + + if (cert == NULL || cert_size == 0 || oid == NULL || oid_size == 0 || + extension_data_size == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + ptr = crt.v3_ext.p; + end = crt.v3_ext.p + crt.v3_ext.len; + ret = mbedtls_asn1_get_tag(&ptr, end, &obj_len, + MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + } + + if (ret == 0) { + status = libspdm_internal_x509_find_extension_data( + ptr, end, oid, oid_size, &ptr, &obj_len); + } + + if (status) { + if (*extension_data_size < obj_len) { + *extension_data_size = obj_len; + status = false; + goto cleanup; + } + if (oid != NULL) { + libspdm_copy_mem(extension_data, *extension_data_size, ptr, obj_len); + } + *extension_data_size = obj_len; + } else { + *extension_data_size = 0; + } + +cleanup: + mbedtls_x509_crt_free(&crt); + + return status; +} + +/** + * Retrieve the Validity from one X.509 certificate + * + * If cert is NULL, then return false. + * If CertIssuerSize is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] from notBefore Pointer to date_time object. + * @param[in,out] from_size notBefore date_time object size. + * @param[out] to notAfter Pointer to date_time object. + * @param[in,out] to_size notAfter date_time object size. + * + * Note: libspdm_x509_compare_date_time to compare date_time oject + * x509SetDateTime to get a date_time object from a date_time_str + * + * @retval true The certificate Validity retrieved successfully. + * @retval false Invalid certificate, or Validity retrieve failed. + * @retval false This interface is not supported. + **/ +bool libspdm_x509_get_validity(const uint8_t *cert, size_t cert_size, + uint8_t *from, size_t *from_size, uint8_t *to, + size_t *to_size) +{ + mbedtls_x509_crt crt; + int32_t ret; + bool status; + size_t t_size; + size_t f_size; + + if (cert == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + f_size = sizeof(mbedtls_x509_time); + if (*from_size < f_size) { + *from_size = f_size; + goto done; + } + if (from != NULL) { + libspdm_copy_mem(from, *from_size, &(crt.valid_from), f_size); + } + *from_size = f_size; + + t_size = sizeof(mbedtls_x509_time); + if (*to_size < t_size) { + *to_size = t_size; + goto done; + } + if (to != NULL) { + libspdm_copy_mem(to, *to_size, &(crt.valid_to), + sizeof(mbedtls_x509_time)); + } + *to_size = t_size; + status = true; + } + +done: + mbedtls_x509_crt_free(&crt); + + return status; +} + +/** + * Retrieve the key usage from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] usage key usage (LIBSPDM_CRYPTO_X509_KU_*) + * + * @retval true The certificate key usage retrieved successfully. + * @retval false Invalid certificate, or usage is NULL + * @retval false This interface is not supported. + **/ +bool libspdm_x509_get_key_usage(const uint8_t *cert, size_t cert_size, + size_t *usage) +{ + mbedtls_x509_crt crt; + int32_t ret; + bool status; + + if (cert == NULL) { + return false; + } + + status = false; + + mbedtls_x509_crt_init(&crt); + + ret = mbedtls_x509_crt_parse_der(&crt, cert, cert_size); + + if (ret == 0) { + *usage = crt.key_usage; + status = true; + } + mbedtls_x509_crt_free(&crt); + + return status; +} + +/** + * Retrieve the Extended key usage from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] usage key usage bytes. + * @param[in, out] usage_size key usage buffer sizs in bytes. + * + * @retval RETURN_SUCCESS The usage bytes retrieve successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL. + * If cert_size is NULL. + * If usage is not NULL and *usage_size is 0. + * If cert is invalid. + * @retval RETURN_BUFFER_TOO_SMALL If the usage is NULL. The required buffer size + * is returned in the usage_size parameter. + * @retval RETURN_UNSUPPORTED The operation is not supported. + **/ +bool libspdm_x509_get_extended_key_usage(const uint8_t *cert, + size_t cert_size, uint8_t *usage, + size_t *usage_size) +{ + bool status; + + if (cert == NULL || cert_size == 0 || usage_size == NULL) { + return false; + } + + status = libspdm_x509_get_extension_data(cert, cert_size, + m_libspdm_oid_ext_key_usage, + sizeof(m_libspdm_oid_ext_key_usage), usage, + usage_size); + + return status; +} + +/** + * Retrieve the basic constraints from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] basic_constraints basic constraints bytes. + * @param[in, out] basic_constraints_size basic constraints buffer sizs in bytes. + * + * @retval RETURN_SUCCESS The basic constraints retrieve successfully. + * @retval RETURN_INVALID_PARAMETER If cert is NULL. + * If cert_size is NULL. + * If basic_constraints is not NULL and *basic_constraints_size is 0. + * If cert is invalid. + * @retval RETURN_BUFFER_TOO_SMALL The required buffer size is small. + * The return buffer size is basic_constraints_size parameter. + * @retval RETURN_NOT_FOUND If no Extension entry match oid. + * @retval RETURN_UNSUPPORTED The operation is not supported. + **/ +bool libspdm_x509_get_extended_basic_constraints(const uint8_t *cert, + size_t cert_size, + uint8_t *basic_constraints, + size_t *basic_constraints_size) +{ + bool status; + + if (cert == NULL || cert_size == 0 || basic_constraints_size == NULL) { + return false; + } + + status = libspdm_x509_get_extension_data(cert, cert_size, + m_libspdm_oid_basic_constraints, + sizeof(m_libspdm_oid_basic_constraints), + basic_constraints, + basic_constraints_size); + return status; +} + +/** + * Return 0 if before <= after, 1 otherwise + **/ +static int32_t libspdm_internal_x509_check_time(const mbedtls_x509_time *before, + const mbedtls_x509_time *after) +{ + if (before->year > after->year) + return (1); + + if (before->year == after->year && before->mon > after->mon) + return (1); + + if (before->year == after->year && before->mon == after->mon && + before->day > after->day) + return (1); + + if (before->year == after->year && before->mon == after->mon && + before->day == after->day && before->hour > after->hour) + return (1); + + if (before->year == after->year && before->mon == after->mon && + before->day == after->day && before->hour == after->hour && + before->min > after->min) + return (1); + + if (before->year == after->year && before->mon == after->mon && + before->day == after->day && before->hour == after->hour && + before->min == after->min && before->sec > after->sec) + return (1); + + return (0); +} + +static int32_t libspdm_internal_atoi(const char *p_start, char const *p_end) +{ + const char *p = p_start; + int32_t k = 0; + while (p < p_end) { + + /* k = k * 2³ + k * 2¹ = k * 8 + k * 2 = k * 10*/ + + k = (k << 3) + (k << 1) + (*p) - '0'; + p++; + } + return k; +} + +/** + * format a date_time object into DataTime buffer + * + * If date_time_str is NULL, then return false. + * If date_time_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] date_time_str date_time string like YYYYMMDDhhmmssZ + * Ref: https://www.w3.org/TR/NOTE-datetime + * Z stand for UTC time + * @param[out] date_time Pointer to a date_time object. + * @param[in,out] date_time_size date_time object buffer size. + * + * @retval RETURN_SUCCESS The date_time object create successfully. + * @retval RETURN_INVALID_PARAMETER If date_time_str is NULL. + * If date_time_size is NULL. + * If date_time is not NULL and *date_time_size is 0. + * If year month day hour minute second combination is invalid datetime. + * @retval RETURN_BUFFER_TOO_SMALL If the date_time is NULL. The required buffer size + * (including the final null) is returned in the + * date_time_size parameter. + * @retval RETURN_UNSUPPORTED The operation is not supported. + **/ +bool libspdm_x509_set_date_time(const char *date_time_str, void *date_time, size_t *date_time_size) +{ + mbedtls_x509_time dt; + + int32_t year; + int32_t month; + int32_t day; + int32_t hour; + int32_t minute; + int32_t second; + bool status; + const char *p; + + p = date_time_str; + + year = libspdm_internal_atoi(p, p + 4); + p += 4; + month = libspdm_internal_atoi(p, p + 2); + p += 2; + day = libspdm_internal_atoi(p, p + 2); + p += 2; + hour = libspdm_internal_atoi(p, p + 2); + p += 2; + minute = libspdm_internal_atoi(p, p + 2); + p += 2; + second = libspdm_internal_atoi(p, p + 2); + p += 2; + dt.year = (int)year; + dt.mon = (int)month; + dt.day = (int)day; + dt.hour = (int)hour; + dt.min = (int)minute; + dt.sec = (int)second; + + if (*date_time_size < sizeof(mbedtls_x509_time)) { + *date_time_size = sizeof(mbedtls_x509_time); + status = false; + goto cleanup; + } + if (date_time != NULL) { + libspdm_copy_mem(date_time, *date_time_size, &dt, sizeof(mbedtls_x509_time)); + } + *date_time_size = sizeof(mbedtls_x509_time); + status = true; +cleanup: + return status; +} + +/** + * Compare date_time1 object and date_time2 object. + * + * If date_time1 is NULL, then return -2. + * If date_time2 is NULL, then return -2. + * If date_time1 == date_time2, then return 0 + * If date_time1 > date_time2, then return 1 + * If date_time1 < date_time2, then return -1 + * + * @param[in] date_time1 Pointer to a date_time Ojbect + * @param[in] date_time2 Pointer to a date_time Object + * + * @retval 0 If date_time1 == date_time2 + * @retval 1 If date_time1 > date_time2 + * @retval -1 If date_time1 < date_time2 + **/ +int32_t libspdm_x509_compare_date_time(const void *date_time1, const void *date_time2) +{ + if (date_time1 == NULL || date_time2 == NULL) { + return -2; + } + if (libspdm_const_compare_mem(date_time2, date_time1, sizeof(mbedtls_x509_time)) == + 0) { + return 0; + } + if (libspdm_internal_x509_check_time((const mbedtls_x509_time *)date_time1, + (const mbedtls_x509_time *)date_time2) == 0) { + return -1; + } else { + return 1; + } +} + +// NVIDIA_EDIT: These functions are all unneeded, uncomment for compilation purposes. +// /** +// * Set all attributes object form req_info to CSR +// * +// * @param[in] req CSR to set attributes +// * @param[in] req_info requester info to gen CSR +// * @param[in] req_info_len The len of requester info +// * +// * @retval true Success Set. +// * @retval false Set failed. +// **/ +// bool libspdm_set_attribute_for_req(mbedtls_x509write_csr *req, uint8_t *req_info, +// size_t req_info_len) +// { +// uint8_t *ptr; +// int32_t length; +// size_t obj_len; +// bool ret; +// uint8_t *end; +// uint8_t *ptr_old; +// +// uint8_t *oid; +// size_t oid_len; +// uint8_t *val; +// size_t val_len; +// +// length = (int32_t)req_info_len; +// ptr = req_info; +// obj_len = 0; +// end = ptr + length; +// ret = false; +// +// if (req_info == NULL) { +// return false; +// } +// +// /*req_info sequence, all ret is ok because the req_info has been verified before*/ +// ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, +// LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); +// +// /*integer:version*/ +// ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, LIBSPDM_CRYPTO_ASN1_INTEGER); +// ptr += obj_len; +// +// /*sequence:subject name*/ +// ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, +// LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); +// ptr += obj_len; +// +// /*sequence:subject pkinfo*/ +// ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, +// LIBSPDM_CRYPTO_ASN1_SEQUENCE | LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); +// ptr += obj_len; +// +// +// /*[0]: attributes*/ +// ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, +// LIBSPDM_CRYPTO_ASN1_CONTEXT_SPECIFIC | +// LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); +// /*there is no attributes*/ +// if (ptr == end) { +// return true; +// } +// +// /*there is some attributes object: 1,2 ...*/ +// while (ret) +// { +// ret = libspdm_asn1_get_tag(&ptr, end, &obj_len, +// LIBSPDM_CRYPTO_ASN1_SEQUENCE | +// LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); +// if (ret) { +// /*save old positon*/ +// ptr_old = ptr; +// +// /*move to the next sequence*/ +// ptr += obj_len; +// +// /*get attributes oid*/ +// ret = libspdm_asn1_get_tag(&ptr_old, end, &obj_len, LIBSPDM_CRYPTO_ASN1_OID); +// if (!ret) { +// return false; +// } +// oid = ptr_old; +// oid_len = obj_len; +// +// ptr_old += obj_len; +// /*get attributes val*/ +// ret = libspdm_asn1_get_tag(&ptr_old, end, &obj_len, +// LIBSPDM_CRYPTO_ASN1_SET | +// LIBSPDM_CRYPTO_ASN1_CONSTRUCTED); +// if (!ret) { +// return false; +// } +// ret = libspdm_asn1_get_tag(&ptr_old, end, &obj_len, LIBSPDM_CRYPTO_ASN1_UTF8_STRING); +// if (!ret) { +// return false; +// } +// val = ptr_old; +// val_len = obj_len; +// +// /*set attributes*/ +// ret = mbedtls_x509write_csr_set_extension(req, oid, oid_len, val, val_len); +// if (ret) { +// return false; +// } +// +// } else { +// break; +// } +// } +// +// if (ptr == end) { +// return true; +// } else { +// return false; +// } +// } +// +// /** +// * Gen CSR +// * +// * @param[in] hash_nid hash algo for sign +// * @param[in] asym_nid asym algo for sign +// * +// * @param[in] requester_info requester info to gen CSR +// * @param[in] requester_info_length The len of requester info +// * +// * @param[in] context Pointer to asymmetric context +// * @param[in] subject_name Subject name: should be break with ',' in the middle +// * example: "C=AA,CN=BB" +// * Subject names should contain a comma-separated list of OID types and values: +// * The valid OID type name is in: +// * {"CN", "commonName", "C", "countryName", "O", "organizationName","L", +// * "OU", "organizationalUnitName", "ST", "stateOrProvinceName", "emailAddress", +// * "serialNumber", "postalAddress", "postalCode", "dnQualifier", "title", +// * "SN","givenName","GN", "initials", "pseudonym", "generationQualifier", "domainComponent", "DC"}. +// * Note: The object of C and countryName should be CSR Supported Country Codes +// * +// * @param[in] csr_len For input, csr_len is the size of store CSR buffer. +// * For output, csr_len is CSR len for DER format +// * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. +// * For output, csr_pointer is address for stored CSR. +// * The csr_pointer address will be changed. +// * +// * @retval true Success. +// * @retval false Failed to gen CSR. +// **/ +// bool libspdm_gen_x509_csr(size_t hash_nid, size_t asym_nid, +// uint8_t *requester_info, size_t requester_info_length, +// void *context, char *subject_name, +// size_t *csr_len, uint8_t **csr_pointer) +// { +// int ret; +// bool result; +// size_t csr_buffer_size; +// +// mbedtls_x509write_csr req; +// mbedtls_md_type_t md_alg; +// mbedtls_pk_context key; +// +// /* Init */ +// mbedtls_x509write_csr_init(&req); +// mbedtls_pk_init(&key); +// csr_buffer_size = *csr_len; +// +// ret = 1; +// switch (asym_nid) +// { +// case LIBSPDM_CRYPTO_NID_RSASSA2048: +// case LIBSPDM_CRYPTO_NID_RSAPSS2048: +// case LIBSPDM_CRYPTO_NID_RSASSA3072: +// case LIBSPDM_CRYPTO_NID_RSAPSS3072: +// case LIBSPDM_CRYPTO_NID_RSASSA4096: +// case LIBSPDM_CRYPTO_NID_RSAPSS4096: +// ret = mbedtls_pk_setup(&key, mbedtls_pk_info_from_type(MBEDTLS_PK_RSA)); +// if (ret != 0) { +// LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"failed\n ! mbedtls_pk_setup %d", ret)); +// goto free_all; +// } +// ret = mbedtls_rsa_copy(mbedtls_pk_rsa(key), (mbedtls_rsa_context *)context); +// if (ret != 0) { +// LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"failed\n ! mbedtls_rsa_copy %d", ret)); +// goto free_all; +// } +// ret = mbedtls_rsa_complete(mbedtls_pk_rsa(key)); +// if (ret != 0) { +// LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"failed\n ! mbedtls_rsa_complete %d", ret)); +// goto free_all; +// } +// break; +// case LIBSPDM_CRYPTO_NID_ECDSA_NIST_P256: +// case LIBSPDM_CRYPTO_NID_ECDSA_NIST_P384: +// case LIBSPDM_CRYPTO_NID_ECDSA_NIST_P521: +// ret = mbedtls_pk_setup(&key, mbedtls_pk_info_from_type(MBEDTLS_PK_ECKEY)); +// if (ret != 0) { +// LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"failed\n ! mbedtls_pk_setup %d", ret)); +// goto free_all; +// } +// /*mbedtls_ecdh_context include mbedtls_ecdsa_context,can be treated as mbedtls_ecdsa_context*/ +// ret = mbedtls_ecdsa_from_keypair(mbedtls_pk_ec(key), (mbedtls_ecdsa_context *)context); +// if (ret != 0) { +// LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"failed\n ! mbedtls_ecdsa_from_keypair %d", ret)); +// goto free_all; +// } +// break; +// default: +// return false; +// } +// +// switch (hash_nid) +// { +// case LIBSPDM_CRYPTO_NID_SHA256: +// md_alg = MBEDTLS_MD_SHA256; +// break; +// case LIBSPDM_CRYPTO_NID_SHA384: +// md_alg = MBEDTLS_MD_SHA384; +// break; +// case LIBSPDM_CRYPTO_NID_SHA512: +// md_alg = MBEDTLS_MD_SHA512; +// break; +// default: +// ret = 1; +// goto free_all; +// } +// +// /* requester info parse*/ +// if (requester_info_length != 0) { +// result = libspdm_set_attribute_for_req(&req, requester_info, requester_info_length); +// if (!result) { +// LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"set_attribute failed !\n")); +// goto free_all; +// } +// } +// +// /* Set the md alg */ +// mbedtls_x509write_csr_set_md_alg(&req, md_alg); +// +// /* Set the subject name */ +// if (subject_name != NULL) { +// ret = mbedtls_x509write_csr_set_subject_name(&req, subject_name); +// if (ret != 0) { +// LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, +// "failed\n ! mbedtls_x509write_csr_set_subject_name returned %d", ret)); +// goto free_all; +// } +// } +// +// /* Set key */ +// mbedtls_x509write_csr_set_key(&req, &key); +// +// /*data is written at the end of the buffer*/ +// ret = mbedtls_x509write_csr_der(&req, *csr_pointer, csr_buffer_size, libspdm_myrand, NULL); +// if (ret <= 0) { +// ret = 1; +// LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO,"mbedtls_x509write_csr_der failed \n")); +// goto free_all; +// } +// +// *csr_len = (size_t)ret; +// /*change csr_pointer to start location*/ +// *csr_pointer = *csr_pointer + csr_buffer_size - *csr_len; +// +// ret = 0; +// free_all: +// mbedtls_x509write_csr_free(&req); +// mbedtls_pk_free(&key); +// +// return(ret == 0); +// } diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/rand/libspdm_rand.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/rand/libspdm_rand.c new file mode 100644 index 0000000000..4228dd3edc --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/rand/libspdm_rand.c @@ -0,0 +1,65 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Pseudorandom Number generator Wrapper Implementation. + **/ + +#include "internal_crypt_lib.h" +#include "library/rnglib.h" + +/** + * Generates a random byte stream of the specified size. + * + * If output is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[out] output Pointer to buffer to receive random value. + * @param[in] size Size of random bytes to generate. + * + * @retval true Random byte stream generated successfully. + * @retval false Generation of random byte stream failed. + **/ +bool libspdm_random_bytes(uint8_t *output, size_t size) +{ + bool ret; + uint64_t temp_rand; + size_t dst_size = size; + + ret = false; + + while (size > 0) { + /* Use rnglib to get random number*/ + ret = libspdm_get_random_number_64(&temp_rand); + + if (!ret) { + return ret; + } + + if (size >= sizeof(uint64_t)) { + libspdm_copy_mem(output, dst_size, &temp_rand, sizeof(uint64_t)); + output += sizeof(uint64_t); + size -= sizeof(uint64_t); + } else { + libspdm_copy_mem(output, dst_size, &temp_rand, size); + size = 0; + } + } + + return ret; +} + +int libspdm_myrand(void *rng_state, unsigned char *output, size_t len) +{ + bool result = libspdm_random_bytes(output, len); + + + /* The MbedTLS function f_rng, which myrand implements, is not + * documented well. From looking at code: zero is considered success, + * while non-zero return value is considered failure.*/ + + return result ? 0 : -1; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h new file mode 100644 index 0000000000..851e64b50a --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h @@ -0,0 +1,64 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Provides services to allocate and free memory buffers of various memory types and alignments. + * + * The Memory Allocation Library abstracts various common memory allocation operations. This library + * allows code to be written in a phase-independent manner because the allocation of memory in PEI, DXE, + * and SMM (for example) is done via a different mechanism. Using a common library interface makes it + * much easier to port algorithms from phase to phase. + **/ + +#ifndef __MEMORY_ALLOCATION_LIB_H__ +#define __MEMORY_ALLOCATION_LIB_H__ + +/** + * Allocates a buffer of type EfiBootServicesData. + * + * Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a + * pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is + * returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. + * + * @param AllocationSize The number of bytes to allocate. + * + * @return A pointer to the allocated buffer or NULL if allocation fails. + * + **/ +void *allocate_pool(size_t AllocationSize); + +/** + * Allocates and zeros a buffer of type EfiBootServicesData. + * + * Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, clears the + * buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a + * valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the + * request, then NULL is returned. + * + * @param AllocationSize The number of bytes to allocate and zero. + * + * @return A pointer to the allocated buffer or NULL if allocation fails. + * + **/ +void *allocate_zero_pool(size_t AllocationSize); + +/** + * Frees a buffer that was previously allocated with one of the pool allocation functions in the + * Memory Allocation Library. + * + * Frees the buffer specified by buffer. buffer must have been allocated on a previous call to the + * pool allocation services of the Memory Allocation Library. If it is not possible to free pool + * resources, then this function will perform no actions. + * + * If buffer was not allocated with a pool allocation function in the Memory Allocation Library, + * then ASSERT(). + * + * @param buffer Pointer to the buffer to free. + * + **/ +void free_pool(void *buffer); + +#endif diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h new file mode 100644 index 0000000000..b538cd00c6 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h @@ -0,0 +1,27 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * Provides random number generator services. + **/ + +#ifndef __RNG_LIB_H__ +#define __RNG_LIB_H__ + +/** + * Generates a 64-bit random number. + * + * if rand is NULL, then ASSERT(). + * + * @param[out] rand_data buffer pointer to store the 64-bit random value. + * + * @retval true Random number generated successfully. + * @retval false Failed to generate the random number. + * + **/ +bool libspdm_get_random_number_64(uint64_t *rand_data); + +#endif /* __RNG_LIB_H__*/ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c new file mode 100644 index 0000000000..25e25bea3a --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c @@ -0,0 +1,49 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * libspdm_const_compare_mem() implementation. + **/ + +#include "base.h" + +/** + * Compares the contents of two buffers in const time. + * + * This function compares length bytes of source_buffer to length bytes of destination_buffer. + * If all length bytes of the two buffers are identical, then 0 is returned. Otherwise, the + * value returned is the first mismatched byte in source_buffer subtracted from the first + * mismatched byte in destination_buffer. + * + * If length > 0 and destination_buffer is NULL, then LIBSPDM_ASSERT(). + * If length > 0 and source_buffer is NULL, then LIBSPDM_ASSERT(). + * If length is greater than (MAX_ADDRESS - destination_buffer + 1), then LIBSPDM_ASSERT(). + * If length is greater than (MAX_ADDRESS - source_buffer + 1), then LIBSPDM_ASSERT(). + * + * @param destination_buffer A pointer to the destination buffer to compare. + * @param source_buffer A pointer to the source buffer to compare. + * @param length The number of bytes to compare. + * + * @return 0 All length bytes of the two buffers are identical. + * @retval Non-zero There is mismatched between source_buffer and destination_buffer. + * + **/ +int32_t libspdm_const_compare_mem(const void *destination_buffer, + const void *source_buffer, size_t length) +{ + const volatile uint8_t *pointer_dst; + const volatile uint8_t *pointer_src; + uint8_t delta; + + pointer_dst = (const uint8_t *)destination_buffer; + pointer_src = (const uint8_t *)source_buffer; + delta = 0; + while ((length-- != 0)) { + delta |= *(pointer_dst++) ^ *(pointer_src++); + } + + return delta; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c new file mode 100644 index 0000000000..f14676386a --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c @@ -0,0 +1,17 @@ +/** + * Copyright Notice: + * Copyright 2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include + +/** + * Suspends the execution of the current thread until the time-out interval elapses. + * + * @param microseconds The time interval for which execution is to be suspended, in milliseconds. + * + **/ +void libspdm_sleep_in_us(uint64_t microseconds) +{ +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c new file mode 100644 index 0000000000..a533135006 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c @@ -0,0 +1,45 @@ +/** + * Copyright Notice: + * Copyright 2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "base.h" +#include "internal/libspdm_lib_config.h" + +#if LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP +/** + * If no heartbeat arrives in seconds, the watchdog timeout event + * should terminate the session. + * + * @param session_id Indicate the SPDM session ID. + * @param seconds heartbeat period, in seconds. + * + **/ +bool libspdm_start_watchdog(uint32_t session_id, uint16_t seconds) +{ + return true; +} + +/** + * stop watchdog. + * + * @param session_id Indicate the SPDM session ID. + * + **/ +bool libspdm_stop_watchdog(uint32_t session_id) +{ + return true; +} + +/** + * Reset the watchdog in heartbeat response. + * + * @param session_id Indicate the SPDM session ID. + * + **/ +bool libspdm_reset_watchdog(uint32_t session_id) +{ + return true; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h new file mode 100644 index 0000000000..5a6555415d --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h @@ -0,0 +1,668 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef CRYPTLIB_EXT_H +#define CRYPTLIB_EXT_H + +#include "hal/base.h" + +/** + * Retrieve the common name (CN) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] common_name Buffer to contain the retrieved certificate common + * name string (UTF8). At most common_name_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] common_name_size The size in bytes of the common_name buffer on input, + * and the size of buffer returned common_name on output. + * If common_name is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_common_name(const uint8_t *cert, size_t cert_size, + char *common_name, + size_t *common_name_size); + +/** + * Retrieve the organization name (O) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] name_buffer Buffer to contain the retrieved certificate organization + * name string. At most name_buffer_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_organization_name(const uint8_t *cert, size_t cert_size, + char *name_buffer, + size_t *name_buffer_size); + +/** + * Retrieve the issuer common name (CN) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] common_name Buffer to contain the retrieved certificate issuer common + * name string. At most common_name_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] common_name_size The size in bytes of the common_name buffer on input, + * and the size of buffer returned common_name on output. + * If common_name is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_issuer_common_name(const uint8_t *cert, size_t cert_size, + char *common_name, + size_t *common_name_size); + +/** + * Retrieve the issuer organization name (O) string from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] name_buffer Buffer to contain the retrieved certificate issuer organization + * name string. At most name_buffer_size bytes will be + * written and the string will be null terminated. May be + * NULL in order to determine the size buffer needed. + * @param[in,out] name_buffer_size The size in bytes of the name buffer on input, + * and the size of buffer returned name on output. + * If name_buffer is NULL then the amount of space needed + * in buffer (including the final null) is returned. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_issuer_orgnization_name(const uint8_t *cert, size_t cert_size, + char *name_buffer, + size_t *name_buffer_size); + +/** + * Retrieve the signature algorithm from one X.509 certificate. + * + * @param[in] cert Pointer to the DER-encoded X509 certificate. + * @param[in] cert_size Size of the X509 certificate in bytes. + * @param[out] oid Signature algorithm Object identifier buffer. + * @param[in,out] oid_size Signature algorithm Object identifier buffer size. + * + * @retval true + * @retval false + **/ +extern bool libspdm_x509_get_signature_algorithm(const uint8_t *cert, + size_t cert_size, uint8_t *oid, + size_t *oid_size); + +/** + * Construct a X509 object from DER-encoded certificate data. + * + * If cert is NULL, then return false. + * If single_x509_cert is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[out] single_x509_cert The generated X509 object. + * + * @retval true The X509 object generation succeeded. + * @retval false The operation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_construct_certificate(const uint8_t *cert, size_t cert_size, + uint8_t **single_x509_cert); + +/** + * Construct a X509 stack object from a list of DER-encoded certificate data. + * + * If x509_stack is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] x509_stack On input, pointer to an existing or NULL X509 stack object. + * On output, pointer to the X509 stack object with new + * inserted X509 certificate. + * @param ... A list of DER-encoded single certificate data followed + * by certificate size. A NULL terminates the list. The + * pairs are the arguments to libspdm_x509_construct_certificate(). + * + * @retval true The X509 stack construction succeeded. + * @retval false The construction operation failed. + * @retval false This interface is not supported. + **/ +extern bool libspdm_x509_construct_certificate_stack(uint8_t **x509_stack, ...); + +/** + * Release the specified X509 object. + * + * If the interface is not supported, then ASSERT(). + * + * @param[in] x509_cert Pointer to the X509 object to be released. + **/ +extern void libspdm_x509_free(void *x509_cert); + +/** + * Release the specified X509 stack object. + * + * If the interface is not supported, then ASSERT(). + * + * @param[in] x509_stack Pointer to the X509 stack object to be released. + **/ +extern void libspdm_x509_stack_free(void *x509_stack); + +/** + * Retrieve the TBSCertificate from one given X.509 certificate. + * + * @param[in] cert Pointer to the given DER-encoded X509 certificate. + * @param[in] cert_size size of the X509 certificate in bytes. + * @param[out] tbs_cert DER-Encoded to-Be-Signed certificate. + * @param[out] tbs_cert_size size of the TBS certificate in bytes. + * + * If cert is NULL, then return false. + * If tbs_cert is NULL, then return false. + * If tbs_cert_size is NULL, then return false. + * If this interface is not supported, then return false. + * + * @retval true The TBSCertificate was retrieved successfully. + * @retval false Invalid X.509 certificate. + **/ +extern bool libspdm_x509_get_tbs_cert(const uint8_t *cert, size_t cert_size, + uint8_t **tbs_cert, size_t *tbs_cert_size); + +/** + * Retrieve the RSA Private key from the password-protected PEM key data. + * + * If pem_data is NULL, then return false. + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. + * @param[in] pem_size Size of the PEM key data in bytes. + * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. + * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * RSA private key component. Use libspdm_rsa_free() function to free the + * resource. + * + * @retval true RSA Private key was retrieved successfully. + * @retval false Invalid PEM key data or incorrect password. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_private_key_from_pem(const uint8_t *pem_data, + size_t pem_size, + const char *password, + void **rsa_context); + +/** + * Retrieve the EC Private key from the password-protected PEM key data. + * + * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. + * @param[in] pem_size Size of the PEM key data in bytes. + * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. + * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * EC private key component. Use libspdm_ec_free() function to free the + * resource. + * + * If pem_data is NULL, then return false. + * If ec_context is NULL, then return false. + * + * @retval true EC Private key was retrieved successfully. + * @retval false Invalid PEM key data or incorrect password. + * + **/ +extern bool libspdm_ec_get_private_key_from_pem(const uint8_t *pem_data, size_t pem_size, + const char *password, + void **ec_context); + +/** + * Retrieve the Ed Private key from the password-protected PEM key data. + * + * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. + * @param[in] pem_size Size of the PEM key data in bytes. + * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. + * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * Ed private key component. Use libspdm_ecd_free() function to free the + * resource. + * + * If pem_data is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true Ed Private key was retrieved successfully. + * @retval false Invalid PEM key data or incorrect password. + **/ +extern bool libspdm_ecd_get_private_key_from_pem(const uint8_t *pem_data, + size_t pem_size, + const char *password, + void **ecd_context); + +/** + * Retrieve the sm2 Private key from the password-protected PEM key data. + * + * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. + * @param[in] pem_size Size of the PEM key data in bytes. + * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. + * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * sm2 private key component. Use sm2_free() function to free the + * resource. + * + * If pem_data is NULL, then return false. + * If sm2_context is NULL, then return false. + * + * @retval true sm2 Private key was retrieved successfully. + * @retval false Invalid PEM key data or incorrect password. + * + **/ +extern bool libspdm_sm2_get_private_key_from_pem(const uint8_t *pem_data, + size_t pem_size, + const char *password, + void **sm2_context); + +/** + * Derive key data using HMAC-SHA256 based KDF. + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha256_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive key data using HMAC-SHA384 based KDF. + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha384_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive key data using HMAC-SHA512 based KDF. + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha512_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive SHA3_256 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_256_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive SHA3_384 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_384_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive SHA3_512 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sha3_512_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Derive SM3_256 HMAC-based Extract-and-Expand key Derivation Function (HKDF). + * + * @param[in] key Pointer to the user-supplied key. + * @param[in] key_size Key size in bytes. + * @param[in] salt Pointer to the salt value. + * @param[in] salt_size Salt size in bytes. + * @param[in] info Pointer to the application specific info. + * @param[in] info_size Info size in bytes. + * @param[out] out Pointer to buffer to receive hkdf value. + * @param[in] out_size Size of hkdf bytes to generate. + * + * @retval true Hkdf generated successfully. + * @retval false Hkdf generation failed. + **/ +extern bool libspdm_hkdf_sm3_256_extract_and_expand(const uint8_t *key, size_t key_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); + +/** + * Sets the public key component into the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] public Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true EC public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size); + +/** + * Sets the private key component into the established EC context. + * + * For P-256, the private_key_size is 32 byte. + * For P-384, the private_key_size is 48 byte. + * For P-521, the private_key_size is 66 byte. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] private_key Pointer to the private key buffer. + * @param[in] private_key_size The size of private key buffer in bytes. + * + * @retval true EC private key component was set successfully. + * @retval false Invalid EC private key component. + * + **/ +extern bool libspdm_ec_set_priv_key(void *ec_context, const uint8_t *private_key, + size_t private_key_size); + +/** + * Gets the public key component from the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true EC key component was retrieved successfully. + * @retval false Invalid EC key component. + **/ +extern bool libspdm_ec_get_pub_key(void *ec_context, uint8_t *public_key, size_t *public_key_size); + +/** + * Validates key components of EC context. + * NOTE: This function performs integrity checks on all the EC key material, so + * the EC key structure must contain all the private key data. + * + * If ec_context is NULL, then return false. + * + * @param[in] ec_context Pointer to EC context to check. + * + * @retval true EC key components are valid. + * @retval false EC key components are not valid. + **/ +extern bool libspdm_ec_check_key(const void *ec_context); + +/** + * Sets the public key component into the established Ed context. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[in] public_key Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true Ed public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ecd_set_pub_key(void *ecd_context, const uint8_t *public_key, + size_t public_key_size); + +/** + * Gets the public key component from the established Ed context. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true Ed key component was retrieved successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ecd_get_pub_key(void *ecd_context, uint8_t *public_key, + size_t *public_key_size); + +/** + * Validates key components of Ed context. + * NOTE: This function performs integrity checks on all the Ed key material, so + * the Ed key structure must contain all the private key data. + * + * If ecd_context is NULL, then return false. + * + * @param[in] ecd_context Pointer to Ed context to check. + * + * @retval true Ed key components are valid. + * @retval false Ed key components are not valid. + **/ +extern bool libspdm_ecd_check_key(const void *ecd_context); + +/** + * Generates Ed key and returns Ed public key. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * If ecd_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] ecd_context Pointer to the Ed context. + * @param[out] public_key Pointer to the buffer to receive generated public key. + * @param[in, out] public_key_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true Ed public key generation succeeded. + * @retval false Ed public key generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_ecd_generate_key(void *ecd_context, uint8_t *public_key, + size_t *public_key_size); + +/** + * Generates DH parameter. + * + * Given generator g, and length of prime number p in bits, this function generates p, + * and sets DH context according to value of g and p. + * + * If dh_context is NULL, then return false. + * If prime is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[in] generator Value of generator. + * @param[in] prime_length Length in bits of prime to be generated. + * @param[out] prime Pointer to the buffer to receive the generated prime number. + * + * @retval true DH parameter generation succeeded. + * @retval false Value of generator is not supported. + * @retval false Random number generator fails to generate random prime number with prime_length. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_generate_parameter(void *dh_context, size_t generator, + size_t prime_length, uint8_t *prime); + +/** + * Sets generator and prime parameters for DH. + * + * Given generator g, and prime number p, this function and sets DH context accordingly. + * + * If dh_context is NULL, then return false. + * If prime is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] dh_context Pointer to the DH context. + * @param[in] generator Value of generator. + * @param[in] prime_length Length in bits of prime to be generated. + * @param[in] prime Pointer to the prime number. + * + * @retval true DH parameter setting succeeded. + * @retval false Value of generator is not supported. + * @retval false Value of generator is not suitable for the prime. + * @retval false Value of prime is not a prime number. + * @retval false Value of prime is not a safe prime number. + * @retval false This interface is not supported. + **/ +extern bool libspdm_dh_set_parameter(void *dh_context, size_t generator, + size_t prime_length, const uint8_t *prime); + +/** + * Sets the public key component into the established sm2 context. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * @param[in, out] ec_context Pointer to sm2 context being set. + * @param[in] public_key Pointer to the buffer to receive generated public X,Y. + * @param[in] public_key_size The size of public buffer in bytes. + * + * @retval true sm2 public key component was set successfully. + * @retval false Invalid sm2 public key component. + **/ +extern bool libspdm_sm2_dsa_set_pub_key(void *sm2_context, const uint8_t *public_key, + size_t public_key_size); + +/** + * Gets the public key component from the established sm2 context. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * @param[in, out] sm2_context Pointer to sm2 context being set. + * @param[out] public_key Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_key_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true sm2 key component was retrieved successfully. + * @retval false Invalid sm2 key component. + **/ +extern bool libspdm_sm2_dsa_get_pub_key(void *sm2_context, uint8_t *public_key, + size_t *public_key_size); + +/** + * Validates key components of sm2 context. + * NOTE: This function performs integrity checks on all the sm2 key material, so + * the sm2 key structure must contain all the private key data. + * + * If sm2_context is NULL, then return false. + * + * @param[in] sm2_context Pointer to sm2 context to check. + * + * @retval true sm2 key components are valid. + * @retval false sm2 key components are not valid. + **/ +extern bool libspdm_sm2_dsa_check_key(const void *sm2_context); + +/** + * Generates sm2 key and returns sm2 public key (X, Y), based upon GB/T 32918.3-2016: SM2 - Part3. + * + * This function generates random secret, and computes the public key (X, Y), which is + * returned via parameter public, public_size. + * X is the first half of public with size being public_size / 2, + * Y is the second half of public with size being public_size / 2. + * sm2 context is updated accordingly. + * If the public buffer is too small to hold the public X, Y, false is returned and + * public_size is set to the required buffer size to obtain the public X, Y. + * + * The public_size is 64. first 32-byte is X, second 32-byte is Y. + * + * If sm2_context is NULL, then return false. + * If public_size is NULL, then return false. + * If public_size is large enough but public is NULL, then return false. + * + * @param[in, out] sm2_context Pointer to the sm2 context. + * @param[out] public_data Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true sm2 public X,Y generation succeeded. + * @retval false sm2 public X,Y generation failed. + * @retval false public_size is not large enough. + **/ +extern bool libspdm_sm2_dsa_generate_key(void *sm2_context, uint8_t *public_data, + size_t *public_size); + +#endif /* CRYPTLIB_EXT_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c new file mode 100644 index 0000000000..b2369f2da7 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c @@ -0,0 +1,105 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** @file + * SPDM common library. + * It follows the SPDM Specification. + **/ + +#include "library/spdm_device_secret_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +libspdm_return_t libspdm_measurement_collection( + spdm_version_number_t spdm_version, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t mesurements_index, + uint8_t request_attribute, + uint8_t *content_changed, + uint8_t *device_measurement_count, + void *device_measurement, + size_t *device_measurement_size) +{ + return LIBSPDM_STATUS_UNSUPPORTED_CAP; +} + +bool libspdm_generate_measurement_summary_hash( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_summary_hash_type, + uint8_t *measurement_summary_hash, + size_t *measurement_summary_hash_size) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +bool libspdm_requester_data_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + +bool libspdm_responder_data_sign( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + return false; +} + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +bool libspdm_psk_handshake_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + const uint8_t *psk_hint, + size_t psk_hint_size, + const uint8_t *info, + size_t info_size, + uint8_t *out, size_t out_size) +{ + return false; +} + +bool libspdm_psk_master_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + const uint8_t *psk_hint, + size_t psk_hint_size, + const uint8_t *info, + size_t info_size, uint8_t *out, + size_t out_size) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP +bool libspdm_write_certificate_to_nvm(uint8_t slot_id, const void * cert_chain, + size_t cert_chain_size) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +bool libspdm_gen_csr(uint32_t base_hash_algo, uint32_t base_asym_algo, bool *need_reset, + uint8_t *requester_info, size_t requester_info_length, + size_t *csr_len, uint8_t **csr_pointer) +{ + return false; +} +#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c new file mode 100644 index 0000000000..35ac287322 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +// +// Included libspdm copyright alongside NVIDIA copyright, as these functions +// are copied from libspdm cryptlib_null files. Meant to more easily stub out +// cryptography functions when not needed. +// + +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + + +// Use headers directly so we don't rely on internal_crypt_lib.h +#include +#include "library/debuglib.h" +#include "library/memlib.h" +#include "library/cryptlib.h" + +// Stub out all crypto functions that we do not support. + +bool libspdm_ec_get_private_key_from_pem(const uint8_t *pem_data, size_t pem_size, + const char *password, + void **ec_context) +{ + LIBSPDM_ASSERT(false); + return false; +} + + diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c new file mode 100644 index 0000000000..0ac0766eb8 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu.h" +#include "base.h" +#include "libraries/utils/nvprintf.h" + +static bool g_libspdmAssertHit = false; + +/* + * Checking and clear libspdm assert status. + * Any assert in libspdm we need to return error and stop processing. + * Returns true if no assert detected, false if assert detected. + */ +bool +nvspdm_check_and_clear_libspdm_assert(void) +{ + bool bAssertHit = g_libspdmAssertHit; + + // Clear assert status before returning. + g_libspdmAssertHit = false; + + // Function is successful on no assert, failing on assert. + return !bAssertHit; +} + +void +libspdm_debug_assert +( + const char *file_name, + size_t line_number, + const char *description +) +{ + NV_PRINTF (LEVEL_ERROR, "libspdm assertion hit!\n"); + g_libspdmAssertHit = NV_TRUE; + DBG_BREAKPOINT(); +} diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c new file mode 100644 index 0000000000..87d21c99c1 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_malloclib.c @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvport/nvport.h" +#include + +void *allocate_pool(size_t AllocationSize) +{ + return portMemAllocNonPaged((NvLength)AllocationSize); +} + +void *allocate_zero_pool(size_t AllocationSize) +{ + void * ptr = portMemAllocNonPaged((NvLength)AllocationSize); + + if (ptr == NULL) + { + return ptr; + } + + portMemSet(ptr, 0, AllocationSize); + + return ptr; +} + +void free_pool(void *buffer) +{ + portMemFree(buffer); +} diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c new file mode 100644 index 0000000000..7e97113adf --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c @@ -0,0 +1,147 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +// Included libSPDM copyright, as file is NV-authored but uses libSPDM code. + +#include "base.h" +#include "library/debuglib.h" +#include "hal/library/memlib.h" +#include "nvport/nvport.h" // NvPort Header + +/** + * Fills a target buffer with a byte value, and returns the target buffer. + * + * This function fills length bytes of buffer with value, and returns buffer. + * + * If length is greater than (MAX_ADDRESS - buffer + 1), then LIBSPDM_ASSERT(). + * + * @param buffer The memory to set. + * @param length The number of bytes to set. + * @param value The value with which to fill length bytes of buffer. + * + * @return buffer. + * + **/ +void *libspdm_set_mem(void *buffer, size_t length, uint8_t value) +{ + return portMemSet(buffer, value, length); +} + + +/** + * Copies bytes from a source buffer to a destination buffer. + * + * This function copies "src_len" bytes from "src_buf" to "dst_buf". + * + * Asserts and returns a non-zero value if any of the following are true: + * 1) "src_buf" or "dst_buf" are NULL. + * 2) "src_len" or "dst_len" is greater than (SIZE_MAX >> 1). + * 3) "src_len" is greater than "dst_len". + * 4) "src_buf" and "dst_buf" overlap. + * + * If any of these cases fail, a non-zero value is returned. Additionally if + * "dst_buf" points to a non-NULL value and "dst_len" is valid, then "dst_len" + * bytes of "dst_buf" are zeroed. + * + * This function follows the C11 cppreference description of memcpy_s. + * https://en.cppreference.com/w/c/string/byte/memcpy + * The cppreferece description does NOT allow the source or destination + * buffers to be NULL. + * + * This function differs from the Microsoft and Safeclib memcpy_s implementations + * in that the Microsoft and Safeclib implementations allow for NULL source and + * destinations pointers when the number of bytes to copy (src_len) is zero. + * + * In addition the Microsoft and Safeclib memcpy_s functions return different + * negative values on error. For best support, clients should generally check + * against zero for success or failure. + * + * @param dst_buf Destination buffer to copy to. + * @param dst_len Maximum length in bytes of the destination buffer. + * @param src_buf Source buffer to copy from. + * @param src_len The number of bytes to copy from the source buffer. + * + * @return 0 on success. non-zero on error. + * + **/ +int libspdm_copy_mem(void *dst_buf, size_t dst_len, + const void *src_buf, size_t src_len) +{ + volatile void *pRet = NULL; + + /* Check for case where "dst" or "dst_len" may be invalid. + * Do not zero "dst" in this case. */ + if (dst_buf == NULL || dst_len > (SIZE_MAX >> 1)) { + LIBSPDM_ASSERT(0); + return -1; + } + + /* Gaurd against invalid source. Zero "dst" in this case. */ + if (src_buf == NULL) { + LIBSPDM_ASSERT(0); + return -1; + } + + /* Guard against invalid lengths. Zero "dst" in these cases. */ + if (src_len > dst_len || + src_len > (SIZE_MAX >> 1)) { + + LIBSPDM_ASSERT(0); + return -1; + } + + pRet = portMemCopy(dst_buf, dst_len, src_buf, src_len); + + if (pRet == NULL) + { + LIBSPDM_ASSERT(0); + return -1; + } + + return 0; +} + +/** + * Fills a target buffer with zeros, and returns the target buffer. + * + * This function fills length bytes of buffer with zeros, and returns buffer. + * + * If length > 0 and buffer is NULL, then LIBSPDM_ASSERT(). + * If length is greater than (MAX_ADDRESS - buffer + 1), then LIBSPDM_ASSERT(). + * + * @param buffer The pointer to the target buffer to fill with zeros. + * @param length The number of bytes in buffer to fill with zeros. + * + * @return buffer. + * + **/ +void *libspdm_zero_mem(void *buffer, size_t length) +{ + return portMemSet(buffer, 0, length); +} diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h new file mode 100644 index 0000000000..c6b40af48f --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h @@ -0,0 +1,129 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVSPDM_RMCONFIG_H_ +#define _NVSPDM_RMCONFIG_H_ + +// +// NOTE: Any updates to macros must first test a local build with LIBSPDM_CHECK_MACRO +// set to 1! This ensures the macro combination is valid. Kept at 0 since adds +// overhead to build otherwise. +// +#define LIBSPDM_CHECK_MACRO 0 + +// +// RM's configuration values for libspdm. Replaces default values in spdm_lib_config.h. +// Must define LIBSPDM_CONFIG in CFLAGS during build in order to successfully replace. +// +#define LIBSPDM_MAX_VERSION_COUNT 5 +#define LIBSPDM_MAX_SESSION_COUNT 1 + +#define LIBSPDM_PSK_CONTEXT_LENGTH LIBSPDM_MAX_HASH_SIZE +#define LIBSPDM_PSK_MAX_HINT_LENGTH 16 + +#define LIBSPDM_MAX_ROOT_CERT_SUPPORT 1 + +#define LIBSPDM_MAX_MEASUREMENT_BLOCK_COUNT 64 +#define LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE 0x1000 + +#define LIBSPDM_MAX_CERT_CHAIN_SIZE 0x1000 +#define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN 1024 + +#define LIBSPDM_MAX_MESSAGE_BUFFER_SIZE 0x1200 +#define LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE 0x100 +#define LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE 0x300 + +// Do not retry messages. +#define LIBSPDM_MAX_REQUEST_RETRY_TIMES 0 + +// We don't expect to use callbacks, nonzero value is required for compilation. +#define LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM 1 +#define LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM 1 +#define LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM 1 + +// CSR's are not supported. +#define LIBSPDM_MAX_CSR_SIZE 0x0 + +// Use running hash over recording all transcript data. +#define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 + +#define LIBSPDM_ECDSA_SUPPORT 1 +#define LIBSPDM_RSA_SSA_SUPPORT 0 +#define LIBSPDM_RSA_PSS_SUPPORT 0 +#define LIBSPDM_SM2_DSA_SUPPORT 0 +#define LIBSPDM_EDDSA_ED25519_SUPPORT 0 +#define LIBSPDM_EDDSA_ED448_SUPPORT 0 + +#define LIBSPDM_ECDHE_SUPPORT 1 +#define LIBSPDM_FFDHE_SUPPORT 0 +#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT 0 + +#define LIBSPDM_AEAD_GCM_SUPPORT 1 +#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 0 +#define LIBSPDM_AEAD_SM4_SUPPORT 0 + +#define LIBSPDM_SHA256_SUPPORT 1 +#define LIBSPDM_SHA384_SUPPORT 1 +#define LIBSPDM_SHA512_SUPPORT 0 +#define LIBSPDM_SHA3_256_SUPPORT 0 +#define LIBSPDM_SHA3_384_SUPPORT 0 +#define LIBSPDM_SHA3_512_SUPPORT 0 +#define LIBSPDM_SM3_256_SUPPORT 0 + +#define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 0 + +// Compiler will complain if these deprecated aliases of above macros are not defined. +#define LIBSPDM_ENABLE_CHUNK_CAP 0 +#define LIBSPDM_ENABLE_SET_CERTIFICATE_CAP 0 + +#define LIBSPDM_MAX_SPDM_MSG_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE +#define LIBSPDM_DATA_TRANSFER_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE + +#define LIBSPDM_TRANSPORT_ADDITIONAL_SIZE 64 +#define LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE (LIBSPDM_DATA_TRANSFER_SIZE + \ + LIBSPDM_TRANSPORT_ADDITIONAL_SIZE) + +#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE) + +// +// We want debug asserts enabled, but we don't care about debug prints or the debug blocks. +// Don't define LIBSPDM_DEBUG_ENABLE, as it will override these settings below. +// +#define LIBSPDM_DEBUG_ASSERT_ENABLE 1 +#define LIBSPDM_DEBUG_PRINT_ENABLE 0 +#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 + +// Enable in version 3.0 when we can use to replace transcript WAR. +#define LIBSPDM_ENABLE_MSG_LOG 0 + +#endif // _NVSPDM_RMCONFIG_H_ diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c new file mode 100644 index 0000000000..f4706963e0 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rng.c @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "os/os.h" +#include + +/** + * Generates a 64-bit random number. + * + * if rand is NULL, then LIBSPDM_ASSERT(). + * + * @param[out] rand_data buffer pointer to store the 64-bit random value. + * + * @retval true Random number generated successfully. + * @retval false Failed to generate the random number. + * + **/ +bool libspdm_get_random_number_64(uint64_t *rand_data) +{ + NV_STATUS status = NV_ERR_GENERIC; + + if (rand_data == NULL) + { + return false; + } + status = osGetRandomBytes((uint8_t *)rand_data, sizeof(uint64_t)); + return (status == NV_OK); +} diff --git a/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk b/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk new file mode 100644 index 0000000000..9de6d2f551 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk @@ -0,0 +1,110 @@ +# SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: MIT +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +# +# Description: This makefile allows for the compilation of the libspdm +# open-source library, in order to implement an SPDM Requester in RM. +# + +LIBSPDM_SOURCES := +LIBSPDM_INCLUDES := +LIBSPDM_DEFINES := +NV_USE_LIBSPDM := 0 + +# Set some common path defines for readability. +LIBSPDM_SOURCE_DIR := src/libraries/libspdm +LIBSPDM_VERSION := 2.3.1 + +# List all files which depend on libspdm headers under LIBSPDM_SOURCES. + +# NVIDIA-authored module code which depends on libspdm headers. +LIBSPDM_SOURCES += src/kernel/gpu/spdm/spdm.c +LIBSPDM_SOURCES += src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c +LIBSPDM_SOURCES += src/kernel/gpu/conf_compute/ccsl.c +LIBSPDM_SOURCES += src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c + +# NVIDIA-authored platform code +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_crypt_null.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_debuglib.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_malloclib.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_rng.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_memlib.c + +# libspdm source files +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_context_data.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_context_data_session.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_crypto_service.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_crypto_service_session.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_msg_log.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_opaque_data.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_support.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_aead.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_asym.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_cert.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_dhe.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_hash.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_hkdf.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_hmac.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_crypt_lib/libspdm_crypt_rng.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_common.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_communication.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_end_session.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_finish.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_capabilities.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_certificate.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_digests.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_measurements.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_version.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_handle_error_response.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_key_exchange.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_key_update.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_send_receive.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_secured_message_lib/libspdm_secmes_context_data.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_secured_message_lib/libspdm_secmes_session.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/memlib/compare_mem.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/spdm_device_secret_lib_null/lib.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/platform_lib_null/watchdog.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/platform_lib_null/time_linux.c + +#if NV_USE_MBEDTLS +# libspdm source providing hooks to MbedTLS. These are dependent on MbedTLS being enabled in RM build. +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_mbedtls/cipher/libspdm_aead_aes_gcm.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_mbedtls/hash/libspdm_sha.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_mbedtls/hmac/libspdm_hmac_sha.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_mbedtls/kdf/libspdm_hkdf_sha.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_mbedtls/pk/libspdm_ec.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_mbedtls/pk/libspdm_x509.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_mbedtls/rand/libspdm_rand.c +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_mbedtls +#endif + +# Add all libspdm include paths required for the above LIBSPDM_SOURCES to LIBSPDM_INCLUDES. +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/include +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/include/hal +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/include +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/nvidia + +# Override the default libspdm configuration with our own. +LIBSPDM_DEFINES += LIBSPDM_CONFIG=\"nvspdm_rmconfig.h\" diff --git a/src/nvidia/src/libraries/mmu/mmu_walk.c b/src/nvidia/src/libraries/mmu/mmu_walk.c index 6086ef2c54..75cc12d6db 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk.c +++ b/src/nvidia/src/libraries/mmu/mmu_walk.c @@ -914,10 +914,10 @@ mmuWalkRootAcquire // Acquire root level instance memory. NV_ASSERT_OK_OR_RETURN( _mmuWalkLevelInstAcquire(pWalk, &pWalk->root, vaLo, vaHi, - NV_TRUE, NV_FALSE, bCommit, &bChanged, + NV_TRUE, NV_FALSE, bCommit, &bChanged, &pLevelInst, NV_FALSE /*bInitNv4k*/)); - // We check pLevelInst to catch the corner case, where Commit() is called before PDB allocation. + // We check pLevelInst to catch the corner case, where Commit() is called before PDB allocation. if (bChanged || (bCommit && pLevelInst)) { NvBool bDone; @@ -1062,12 +1062,12 @@ mmuWalkSetEntryHybrid } /** - * @brief Calculate target entry indices that covers VA range for + * @brief Calculate target entry indices that covers VA range for * source entries - * - * @details For example, entry 1 in 64K PT is aligned to 4K PT entry 0 to + * + * @details For example, entry 1 in 64K PT is aligned to 4K PT entry 0 to * 15. 4K PTE 1 to 18 will be covered by 64K PTE 0 to 1. - * + * * It is introduced by NV4K encoding. Updating big page table * according to small page table requires index transfering * @@ -1084,7 +1084,7 @@ mmuFmtCalcAlignedEntryIndices const MMU_FMT_LEVEL *pPageFmtIn, const NvU32 indexLoIn, const NvU32 indexHiIn, - const MMU_FMT_LEVEL *pPageFmtOut, + const MMU_FMT_LEVEL *pPageFmtOut, NvU32 *pIndexLoOut, NvU32 *pIndexHiOut ) @@ -1178,29 +1178,29 @@ _mmuWalkLevelDestroy /** * @brief Resolve upcoming state conflicts before mmu walk operations - * + * * @example Say we are to mmuWalkMap VA range [vaLo, vaHi] on small PT. - * Assume we have 4K PT and 64K PT as our small PT and big PT, and [vaLo, vaHi] + * Assume we have 4K PT and 64K PT as our small PT and big PT, and [vaLo, vaHi] * is a strict subset of VA range covered by BigPTE[1, 3] and SmallPTE[18, 61]. * Let's say BigPTE[1, 3] are sparse right now. - * + * * To resolve the conflict, we need to preserve sparse state for part of the * VA range that is not going to be mapped. We need to move those states from * BigPT to SmallPT. - * + * * Before: * BigPTE[1, 3]: sparse, SmallPTE[16 - 63]: invalid * (BigPTE[1, 3] and SmallPTE[16 - 63] are VA aligned) * After: * BigPTE[1, 3]: invalid, SmallPTE[16 - 17]: sparse * SmallPTE[18 - 61]: invalid, will later be mapped - * SmallPTE[62 - 63]: sparse + * SmallPTE[62 - 63]: sparse * * @example If we are to mmuWalkMap on big PT instead of samll PT, * and sparse state was on small PT, we just need to invalidate the small PTEs. - * + * * Before: - * BigPTE[1, 3]: invalid, + * BigPTE[1, 3]: invalid, * SmallPTE[16 - 63]: sparse * After: * BigPTE[1, 3]: invalid, will later be mapped @@ -1247,7 +1247,7 @@ _mmuWalkResolveSubLevelConflicts { entryIndexLo = mmuFmtVirtAddrToEntryIndex(pLevelFmtSmall, clippedVaLo); entryIndexHi = mmuFmtVirtAddrToEntryIndex(pLevelFmtSmall, clippedVaHi); - mmuFmtCalcAlignedEntryIndices(pLevelFmtSmall, entryIndexLo, + mmuFmtCalcAlignedEntryIndices(pLevelFmtSmall, entryIndexLo, entryIndexHi, pLevelFmtBig, &indexLo_Big, &indexHi_Big); mmuFmtCalcAlignedEntryIndices(pLevelFmtBig, indexLo_Big, indexHi_Big, pLevelFmtSmall, &indexLo_Small, &indexHi_Small); @@ -1425,11 +1425,11 @@ _mmuWalkLevelInstAcquire const NvU32 entryIndexHi = (pLevelInst->memSize / pLevel->pFmt->entrySize) - 1; NvU32 progress = 0; - // + // // default state for new entries // NV4K for big page table if ATS is enabled - // - MMU_WALK_FILL_STATE newEntryState = bInitNv4k ? MMU_WALK_FILL_NV4K : + // + MMU_WALK_FILL_STATE newEntryState = bInitNv4k ? MMU_WALK_FILL_NV4K : MMU_WALK_FILL_INVALID; NV_ASSERT(NULL != pLevelInst->pMemDesc); @@ -1571,10 +1571,10 @@ _mmuWalkPdeAcquire } } - // + // // the loop was reversed for NV4K, if there are multiple sublevels // handling small PT first, then the big PT - // + // for (i = numSubLevels; i > 0; --i) { NvBool bChanged = NV_FALSE; @@ -1582,12 +1582,12 @@ _mmuWalkPdeAcquire NvBool bTarget = (subLevelIdx == subLevel); NvBool bInitNv4k = NV_FALSE; - // + // // If NV4K is required (when ATS is enabled), acquire 64K PT // whenever the 4K PT has been acquired and 64K PT was not // there - // - if (pWalk->flags.bAtsEnabled && subLevelIdx == 0 && + // + if (pWalk->flags.bAtsEnabled && subLevelIdx == 0 && numSubLevels > 1 && !pOpParams->bRelease) { if (pSubLevelInsts[1] != NULL) @@ -1605,7 +1605,7 @@ _mmuWalkPdeAcquire _mmuWalkLevelInstAcquire(pWalk, pLevel->subLevels + subLevelIdx, vaLo, vaLimit, bTarget, pOpParams->bRelease, pOpParams->bCommit, - &bChanged, &pSubLevelInsts[subLevelIdx], + &bChanged, &pSubLevelInsts[subLevelIdx], bInitNv4k)); if (NULL == pSubLevelInsts[subLevelIdx]) { @@ -1692,7 +1692,7 @@ _mmuWalkPdeRelease { if (pWalk->flags.bAtsEnabled) { - if (pSubLevelInsts[0]->numNv4k == + if (pSubLevelInsts[0]->numNv4k == mmuFmtLevelEntryCount(pLevel->subLevels[0].pFmt) && (0 == pSubLevelInsts[0]->numReserved) && (pSubMemDescs[1] == NULL || bChanged == NV_TRUE)) @@ -1700,7 +1700,7 @@ _mmuWalkPdeRelease bChanged = NV_TRUE; continue; } - else + else { state = MMU_ENTRY_STATE_IS_PDE; pSubMemDescs[subLevel] = pSubLevelInst->pMemDesc; diff --git a/src/nvidia/src/libraries/mmu/mmu_walk_fill.c b/src/nvidia/src/libraries/mmu/mmu_walk_fill.c index 6701071004..8d62903206 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk_fill.c +++ b/src/nvidia/src/libraries/mmu/mmu_walk_fill.c @@ -29,9 +29,9 @@ static NV_STATUS _mmuWalkPostFillPTETasks ( - const MMU_WALK *pWalk, - MMU_WALK_LEVEL *pLevel, - const NvU32 entryIndexLo, + const MMU_WALK *pWalk, + MMU_WALK_LEVEL *pLevel, + const NvU32 entryIndexLo, const NvU32 entryIndexHi, const MMU_WALK_FILL_STATE fillState, const NvU64 vaLo @@ -41,17 +41,17 @@ static NV_STATUS _mmuWalkPostFillPTETasks /** * @brief Fill a VA range to a constant state for levels below the root. * - * @details This function is of MmuWalkOp function type. Used by + * @details This function is of MmuWalkOp function type. Used by * mmuWalkUnmap and mmuWalkSparsify, which fills INVALID and SPARSE - * states to the target page levels respectively. - * With NV4K introduced with VOLTA ATS, cross PT inconsistency - * during unmapping and sparsifying is handled here. - * - * @todo Recover from failure. It is difficult to do because rollbacks + * states to the target page levels respectively. + * With NV4K introduced with VOLTA ATS, cross PT inconsistency + * during unmapping and sparsifying is handled here. + * + * @todo Recover from failure. It is difficult to do because rollbacks * are costly and complex. Do we really want recovery or asserts? * If the later one, we can replace those recovery codes with * asserts. - * + * * @copydoc MmuWalkCBOpFunc * * @return NV_OK on success @@ -114,7 +114,7 @@ NV_STATUS mmuWalkFill // Clear out the PTEs modulo number of entries in table // We do a modulo of number of entries in the table so that // we do not exceed the allocated sysmem page. - // + // pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel->pFmt, pWalk->pStagingBuffer, @@ -127,7 +127,7 @@ NV_STATUS mmuWalkFill pWalk->pCb->WriteBuffer(pWalk->pUserCtx, pWalk->pStagingBuffer, pLevelInst->pMemDesc, - entryIndexLo, + entryIndexLo, entryIndexHi, numEntries, pLevel->pFmt->entrySize); @@ -212,14 +212,14 @@ mmuWalkFillSelectSubLevel } /** - * @brief Determines if entries indexLo to indexHi (inclusive) are + * @brief Determines if entries indexLo to indexHi (inclusive) are * all invalid. * * @param pLevelInst The level instance * @param[in] indexLo The index lower * @param[in] indexHi The index higher * - * @return True if no level instance or all entries are invalid, + * @return True if no level instance or all entries are invalid, * False otherwise. */ static NvBool @@ -247,13 +247,13 @@ _isRangeAllInvalid /** * @brief Post PTE filling tasks to handle cross PTs inconsistency - * + * * @details Helper function inside mmuWalkFill PT level to update 64K PTEs - * after mmuWalkFill operation complete. It gathers mmuWalkFill + * after mmuWalkFill operation complete. It gathers mmuWalkFill * target entry index range and fillState as input and update * 64K PTEs accordingly. The function doesn't handle extra page - * table allocations and deallocations. It relies on - * _mmuWalkPdeAcquire and _mmuWalkPdeRelease to prepare and + * table allocations and deallocations. It relies on + * _mmuWalkPdeAcquire and _mmuWalkPdeRelease to prepare and * cleanup page levels accordingly. * * @todo Recovery on failure. Same discussion as in mmuWalkFill. @@ -269,9 +269,9 @@ _isRangeAllInvalid */ static NV_STATUS _mmuWalkPostFillPTETasks ( - const MMU_WALK *pWalk, - MMU_WALK_LEVEL *pLevel, - const NvU32 entryIndexLo, + const MMU_WALK *pWalk, + MMU_WALK_LEVEL *pLevel, + const NvU32 entryIndexLo, const NvU32 entryIndexHi, const MMU_WALK_FILL_STATE fillState, const NvU64 virtAddr @@ -279,10 +279,10 @@ static NV_STATUS _mmuWalkPostFillPTETasks { const MMU_FMT_LEVEL *pFmtLevel = pLevel->pFmt; - // + // // NV4K is only necessary for ATS // Only update 64K PTEs on invalidation, not on sparsifying - // + // if (pWalk->flags.bAtsEnabled && fillState == MMU_WALK_FILL_INVALID) { const NvU64 pageSize = mmuFmtLevelPageSize(pFmtLevel); @@ -304,10 +304,10 @@ static NV_STATUS _mmuWalkPostFillPTETasks btreeSearch(vaLevelBase, (NODE**)&pLevel4KInst, (NODE*)pLevel4K->pInstances); - // + // // if 4K page table was modified in mmuWalkFill // check the range and update 64K PTEs accordingly - // + // if (pageSize == 0x1000) { // get involved 64K PTEs and 4K PTEs @@ -327,14 +327,14 @@ static NV_STATUS _mmuWalkPostFillPTETasks // otherwise check the head and tail groups else { - if (indexLo_4K < entryIndexLo && + if (indexLo_4K < entryIndexLo && !_isRangeAllInvalid(pLevel4KInst, indexLo_4K, entryIndexLo - 1)) { indexLo_64K++; } if (indexHi_4K > entryIndexHi && - !_isRangeAllInvalid(pLevel4KInst, entryIndexHi + 1, + !_isRangeAllInvalid(pLevel4KInst, entryIndexHi + 1, indexHi_4K)) { indexHi_64K--; @@ -344,8 +344,8 @@ static NV_STATUS _mmuWalkPostFillPTETasks // update 64K PT given the indexes calculated above if (indexLo_64K <= indexHi_64K) { - pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel64K->pFmt, - pLevel64KInst->pMemDesc, indexLo_64K, indexHi_64K, + pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel64K->pFmt, + pLevel64KInst->pMemDesc, indexLo_64K, indexHi_64K, MMU_WALK_FILL_NV4K, &progress); NV_ASSERT_OR_RETURN(progress == indexHi_64K - indexLo_64K + 1, NV_ERR_INVALID_STATE); @@ -353,28 +353,28 @@ static NV_STATUS _mmuWalkPostFillPTETasks for (entryIndex = indexLo_64K; entryIndex <= indexHi_64K; entryIndex++) { - mmuWalkSetEntryState(pLevel64KInst, entryIndex, + mmuWalkSetEntryState(pLevel64KInst, entryIndex, MMU_ENTRY_STATE_NV4K); } } } - // + // // if 64K page table is invalidated in mmuWalkFill // correct the state as NV4K // @todo move this portion to mmuWalkFill - // + // else if (pageSize == 0x10000) { - mmuFmtCalcAlignedEntryIndices(pLevel64K->pFmt, entryIndexLo, + mmuFmtCalcAlignedEntryIndices(pLevel64K->pFmt, entryIndexLo, entryIndexHi, pLevel4K->pFmt, &indexLo_4K, &indexHi_4K); // the 4K PTE should have already been invalid - NV_ASSERT_OR_RETURN(_isRangeAllInvalid(pLevel4KInst, indexLo_4K, + NV_ASSERT_OR_RETURN(_isRangeAllInvalid(pLevel4KInst, indexLo_4K, indexHi_4K), NV_ERR_INVALID_STATE); // Set 64K PTEs NV4K - pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel64K->pFmt, - pLevel64KInst->pMemDesc, entryIndexLo, entryIndexHi, + pWalk->pCb->FillEntries(pWalk->pUserCtx, pLevel64K->pFmt, + pLevel64KInst->pMemDesc, entryIndexLo, entryIndexHi, MMU_WALK_FILL_NV4K, &progress); NV_ASSERT_OR_RETURN(progress == entryIndexHi - entryIndexLo + 1, NV_ERR_INVALID_STATE); diff --git a/src/nvidia/src/libraries/mmu/mmu_walk_private.h b/src/nvidia/src/libraries/mmu/mmu_walk_private.h index 96b918f769..fb2fa5b23f 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk_private.h +++ b/src/nvidia/src/libraries/mmu/mmu_walk_private.h @@ -357,7 +357,7 @@ void mmuFmtCalcAlignedEntryIndices(const MMU_FMT_LEVEL *pPageFmtIn, const NvU32 indexLoIn, const NvU32 indexHiIn, - const MMU_FMT_LEVEL *pPageFmtOut, + const MMU_FMT_LEVEL *pPageFmtOut, NvU32 *pIndexLoOut, NvU32 *pIndexHiOut); diff --git a/src/nvidia/src/libraries/nvport/cpu/cpu_common.c b/src/nvidia/src/libraries/nvport/cpu/cpu_common.c index 11c4ab9b36..0d9c9f1e84 100644 --- a/src/nvidia/src/libraries/nvport/cpu/cpu_common.c +++ b/src/nvidia/src/libraries/nvport/cpu/cpu_common.c @@ -46,7 +46,7 @@ portCpuShutdown(void) if (PORT_CPU_GET_IMC_BAR_DESC_INIT_STATE() == NV_TRUE) { // - // If PORT_CPU_GET_IMC_BAR_DESC_INIT_STATE is true then + // If PORT_CPU_GET_IMC_BAR_DESC_INIT_STATE is true then // portCpuExFreeImcBarDesc will be supported. Adding following check // to avoid compile time issues // diff --git a/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c b/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c index 0a2e2cdf9c..60140bc2ba 100644 --- a/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c +++ b/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.c @@ -53,18 +53,18 @@ static NV_INLINE NV_STATUS portCpuCheckStdFunSupport(NvU32 function_id) portMemSet(cpuInfo, 0, sizeof(cpuInfo)); status = portCpuCpuId(cpuInfo, PORT_CPU_CPUID_STD_FUN_BASIC, PORT_CPU_CPUID_STD_SUBFUN_0); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; } - if (function_id > cpuInfo[0]) + if (function_id > cpuInfo[0]) { PORT_BREAKPOINT_DEBUG(); return NV_ERR_NOT_SUPPORTED; } - + return NV_OK; } @@ -74,15 +74,15 @@ static NV_INLINE NV_STATUS portCpuIntelGetVersion(PORT_CPU_INTEL *pCpuVersion) NvU32 cpuInfo[4]; NvU32 model; NvU32 family; - - if (pCpuVersion == NULL) + + if (pCpuVersion == NULL) { PORT_BREAKPOINT_DEBUG(); return NV_ERR_INVALID_ARGUMENT; } status = portCpuCheckStdFunSupport(PORT_CPU_CPUID_STD_FUN_VERSION); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -91,7 +91,7 @@ static NV_INLINE NV_STATUS portCpuIntelGetVersion(PORT_CPU_INTEL *pCpuVersion) portMemSet(cpuInfo, 0U, sizeof(cpuInfo)); status = portCpuCpuId(cpuInfo, PORT_CPU_CPUID_STD_FUN_VERSION, PORT_CPU_CPUID_STD_SUBFUN_0); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -100,17 +100,17 @@ static NV_INLINE NV_STATUS portCpuIntelGetVersion(PORT_CPU_INTEL *pCpuVersion) pCpuVersion->steppingId = PORT_CPU_CPUID_GET_STEPPING_ID(cpuInfo[0]); family = PORT_CPU_CPUID_GET_FAMILY(cpuInfo[0]); model = PORT_CPU_CPUID_GET_MODEL(cpuInfo[0]); - if ((family == 0x0FU) || (family == 0x06U)) + if ((family == 0x0FU) || (family == 0x06U)) { model |= PORT_CPU_CPUID_GET_EXT_MODEL(cpuInfo[0]) << PORT_CPU_CPUID_MODEL_SHIFT; } - - if (family == 0x0FU) + + if (family == 0x0FU) { family += PORT_CPU_CPUID_GET_EXT_FAMILY(cpuInfo[0]); } - + pCpuVersion->family = family; switch (pCpuVersion->family) { @@ -121,7 +121,7 @@ static NV_INLINE NV_STATUS portCpuIntelGetVersion(PORT_CPU_INTEL *pCpuVersion) // Unknown famliy, ignore model. break; } - + pCpuVersion->brandIndex = PORT_CPU_CPUID_GET_BRAND_INDEX(cpuInfo[1]); pCpuVersion->localApicId = PORT_CPU_CPUID_GET_LOCAL_APIC_ID(cpuInfo[1]); pCpuVersion->processorType = PORT_CPU_CPUID_GET_PROCESSOR_TYPE(cpuInfo[1]); @@ -135,14 +135,14 @@ static NV_INLINE NV_STATUS portCpuGetIntelFeatures(PORT_CPU_INTEL_X86_FEATURES NV_STATUS status; NvU32 cpuInfo[4]; - if (pCpuFeatures == NULL) + if (pCpuFeatures == NULL) { PORT_BREAKPOINT_DEBUG(); return NV_ERR_INVALID_ARGUMENT; } status = portCpuCheckStdFunSupport(PORT_CPU_CPUID_STD_FUN_VERSION); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -151,7 +151,7 @@ static NV_INLINE NV_STATUS portCpuGetIntelFeatures(PORT_CPU_INTEL_X86_FEATURES portMemSet(cpuInfo, 0U, sizeof(cpuInfo)); status = portCpuCpuId(cpuInfo, PORT_CPU_CPUID_STD_FUN_VERSION, PORT_CPU_CPUID_STD_SUBFUN_0); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -276,7 +276,7 @@ static NV_INLINE NV_STATUS portCpuGetIntelFeatures(PORT_CPU_INTEL_X86_FEATURES pCpuFeatures->TM = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[3], PORT_CPU_CPUID_FEATURE_TM_BIT); pCpuFeatures->PBE = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[3], - PORT_CPU_CPUID_FEATURE_PBE_BIT); + PORT_CPU_CPUID_FEATURE_PBE_BIT); return NV_OK; } @@ -286,14 +286,14 @@ static NV_INLINE NV_STATUS portCpuGetIntelArchPerfMonitor( NV_STATUS status; NvU32 cpuInfo[4]; - if (pCpuArchPerfMonitor == NULL) + if (pCpuArchPerfMonitor == NULL) { PORT_BREAKPOINT_DEBUG(); return NV_ERR_INVALID_ARGUMENT; } status = portCpuCheckStdFunSupport(PORT_CPU_CPUID_STD_FUN_TPM); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -302,7 +302,7 @@ static NV_INLINE NV_STATUS portCpuGetIntelArchPerfMonitor( portMemSet(cpuInfo, 0U, sizeof(cpuInfo)); status = portCpuCpuId(cpuInfo, PORT_CPU_CPUID_STD_FUN_ARCH_PERF_MONITOR, PORT_CPU_CPUID_STD_SUBFUN_0); - if (status != NV_OK) + if (status != NV_OK) { PORT_BREAKPOINT_DEBUG(); return status; @@ -371,13 +371,13 @@ static NV_INLINE NV_STATUS portCpuGetIntelTPMFeatures( return status; } - pCpuTPMFeatures->DTS = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->DTS = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_DTS_BIT); pCpuTPMFeatures->IntelTurboBoost = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_ITB_BIT); - pCpuTPMFeatures->ARAT = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->ARAT = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_ARAT_BIT); - pCpuTPMFeatures->PLN = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->PLN = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_PLN_BIT); pCpuTPMFeatures->ECMD = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_ECMD_BIT); @@ -399,21 +399,21 @@ static NV_INLINE NV_STATUS portCpuGetIntelTPMFeatures( PORT_CPU_CPUID_TPM_FEATURE_ITBMT30_BIT); pCpuTPMFeatures->HWPCapabilities = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_HWP_CAPABILITIES_BIT); - pCpuTPMFeatures->HWPPECI = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->HWPPECI = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_HWPPECI_BIT); - pCpuTPMFeatures->FLEXHWP = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->FLEXHWP = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_FLEXHWP_BIT); - pCpuTPMFeatures->FAM = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->FAM = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_FAM_BIT); - pCpuTPMFeatures->ILPHWPRequest = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], + pCpuTPMFeatures->ILPHWPRequest = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[0], PORT_CPU_CPUID_TPM_FEATURE_ILPHWP_REQUEST_BIT); - pCpuTPMFeatures->NoOfInterruptThresholdsInDTS = + pCpuTPMFeatures->NoOfInterruptThresholdsInDTS = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[1], PORT_CPU_CPUID_TPM_FEATURE_NFITI_DTS_BIT); - pCpuTPMFeatures->HCFC = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[2], + pCpuTPMFeatures->HCFC = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[2], PORT_CPU_CPUID_TPM_FEATURE_HCFC_BIT); - pCpuTPMFeatures->PEBP = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[2], + pCpuTPMFeatures->PEBP = PORT_CPU_CPUID_FEATURE_GET_BIT(cpuInfo[2], PORT_CPU_CPUID_TPM_FEATURE_PEBP_BIT); return NV_OK; @@ -444,7 +444,7 @@ static NV_INLINE NV_STATUS portCpuGetIntelTopology(PORT_CPU_INTEL* pCpuInfo) PORT_BREAKPOINT_DEBUG(); return status; } - + switch (PORT_CPU_EXT_TOPOLOGY_ENUM_GET_LEVEL_TYPE(cpuInfo[2])) { case PORT_CPU_EXT_TOPOLOGY_ENUM_LEVEL_TYPE_SMT: @@ -459,11 +459,11 @@ static NV_INLINE NV_STATUS portCpuGetIntelTopology(PORT_CPU_INTEL* pCpuInfo) cond = NV_FALSE; break; } - + pCpuInfo->physicalCoreCount = pCpuInfo->logicalCoreCount / pCpuInfo->threadCountPerCore; sub++; } while (cond == NV_TRUE); - + return NV_OK; } diff --git a/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h b/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h index ec99a53f3f..a852f284d1 100644 --- a/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h +++ b/src/nvidia/src/libraries/nvport/cpu/cpu_x86_amd64.h @@ -86,7 +86,7 @@ #define PORT_CPU_CPUID_STEPPING_ID_SHIFT 0U #define PORT_CPU_CPUID_GET_STEPPING_ID(a) ((a) \ & 0x0000000FU) - + #define PORT_CPU_CPUID_MODEL_MASK 0x000000F0U #define PORT_CPU_CPUID_MODEL_SHIFT 4U #define PORT_CPU_CPUID_GET_MODEL(a) (((a) \ @@ -131,30 +131,30 @@ & 0xFF000000U)\ >> 24U) -#define PORT_CPU_CPUID_FEATURE_SSE3_BIT (1U << 0U) -#define PORT_CPU_CPUID_FEATURE_PCLMULQDQ_BIT (1U << 1U) +#define PORT_CPU_CPUID_FEATURE_SSE3_BIT (1U << 0U) +#define PORT_CPU_CPUID_FEATURE_PCLMULQDQ_BIT (1U << 1U) #define PORT_CPU_CPUID_FEATURE_DTES64_BIT (1U << 2U) -#define PORT_CPU_CPUID_FEATURE_MONITOR_BIT (1U << 3U) -#define PORT_CPU_CPUID_FEATURE_DSCPL_BIT (1U << 4U) +#define PORT_CPU_CPUID_FEATURE_MONITOR_BIT (1U << 3U) +#define PORT_CPU_CPUID_FEATURE_DSCPL_BIT (1U << 4U) #define PORT_CPU_CPUID_FEATURE_VMX_BIT (1U << 5U) #define PORT_CPU_CPUID_FEATURE_SMX_BIT (1U << 6U) -#define PORT_CPU_CPUID_FEATURE_EIST_BIT (1U << 7U) +#define PORT_CPU_CPUID_FEATURE_EIST_BIT (1U << 7U) #define PORT_CPU_CPUID_FEATURE_TM2_BIT (1U << 8U) #define PORT_CPU_CPUID_FEATURE_SSSE3_BIT (1U << 9U) -#define PORT_CPU_CPUID_FEATURE_CNXTID_BIT (1U << 10U) +#define PORT_CPU_CPUID_FEATURE_CNXTID_BIT (1U << 10U) #define PORT_CPU_CPUID_FEATURE_SDBG_BIT (1U << 11U) #define PORT_CPU_CPUID_FEATURE_FMA_BIT (1U << 12U) -#define PORT_CPU_CPUID_FEATURE_CMPXCHG16B_BIT (1U << 13U) -#define PORT_CPU_CPUID_FEATURE_XTPRUPDATECONTROL_BIT (1U << 14U) -#define PORT_CPU_CPUID_FEATURE_PDCM_BIT (1U << 15U) +#define PORT_CPU_CPUID_FEATURE_CMPXCHG16B_BIT (1U << 13U) +#define PORT_CPU_CPUID_FEATURE_XTPRUPDATECONTROL_BIT (1U << 14U) +#define PORT_CPU_CPUID_FEATURE_PDCM_BIT (1U << 15U) #define PORT_CPU_CPUID_FEATURE_PCID_BIT (1U << 17U) -#define PORT_CPU_CPUID_FEATURE_DCA_BIT (1U << 18U) +#define PORT_CPU_CPUID_FEATURE_DCA_BIT (1U << 18U) #define PORT_CPU_CPUID_FEATURE_SSE41_BIT (1U << 19U) -#define PORT_CPU_CPUID_FEATURE_SSE42_BIT (1U << 20U) -#define PORT_CPU_CPUID_FEATURE_x2APIC_BIT (1U << 21U) +#define PORT_CPU_CPUID_FEATURE_SSE42_BIT (1U << 20U) +#define PORT_CPU_CPUID_FEATURE_x2APIC_BIT (1U << 21U) #define PORT_CPU_CPUID_FEATURE_MOVBE_BIT (1U << 22U) #define PORT_CPU_CPUID_FEATURE_POPCNT_BIT (1U << 23U) -#define PORT_CPU_CPUID_FEATURE_TSCDEADLINE_BIT (1U << 24U) +#define PORT_CPU_CPUID_FEATURE_TSCDEADLINE_BIT (1U << 24U) #define PORT_CPU_CPUID_FEATURE_AES_BIT (1U << 25U) #define PORT_CPU_CPUID_FEATURE_XSAVE_BIT (1U << 26U) #define PORT_CPU_CPUID_FEATURE_OSXSAVE_BIT (1U << 27U) @@ -164,30 +164,30 @@ #define PORT_CPU_CPUID_FEATURE_FPU_BIT (1U << 0U) #define PORT_CPU_CPUID_FEATURE_VME_BIT (1U << 1U) -#define PORT_CPU_CPUID_FEATURE_DE_BIT (1U << 2U) -#define PORT_CPU_CPUID_FEATURE_PSE_BIT (1U << 3U) +#define PORT_CPU_CPUID_FEATURE_DE_BIT (1U << 2U) +#define PORT_CPU_CPUID_FEATURE_PSE_BIT (1U << 3U) #define PORT_CPU_CPUID_FEATURE_TSC_BIT (1U << 4U) -#define PORT_CPU_CPUID_FEATURE_MSR_BIT (1U << 5U) +#define PORT_CPU_CPUID_FEATURE_MSR_BIT (1U << 5U) #define PORT_CPU_CPUID_FEATURE_PAE_BIT (1U << 6U) #define PORT_CPU_CPUID_FEATURE_MCE_BIT (1U << 7U) #define PORT_CPU_CPUID_FEATURE_CX8_BIT (1U << 8U) -#define PORT_CPU_CPUID_FEATURE_APIC_BIT (1U << 9U) +#define PORT_CPU_CPUID_FEATURE_APIC_BIT (1U << 9U) #define PORT_CPU_CPUID_FEATURE_SEP_BIT (1U << 11U) -#define PORT_CPU_CPUID_FEATURE_MTRR_BIT (1U << 12U) -#define PORT_CPU_CPUID_FEATURE_PGE_BIT (1U << 13U) +#define PORT_CPU_CPUID_FEATURE_MTRR_BIT (1U << 12U) +#define PORT_CPU_CPUID_FEATURE_PGE_BIT (1U << 13U) #define PORT_CPU_CPUID_FEATURE_MCA_BIT (1U << 14U) -#define PORT_CPU_CPUID_FEATURE_CMOV_BIT (1U << 15U) +#define PORT_CPU_CPUID_FEATURE_CMOV_BIT (1U << 15U) #define PORT_CPU_CPUID_FEATURE_PAT_BIT (1U << 16U) -#define PORT_CPU_CPUID_FEATURE_PSE36_BIT (1U << 17U) -#define PORT_CPU_CPUID_FEATURE_PSN_BIT (1U << 18U) +#define PORT_CPU_CPUID_FEATURE_PSE36_BIT (1U << 17U) +#define PORT_CPU_CPUID_FEATURE_PSN_BIT (1U << 18U) #define PORT_CPU_CPUID_FEATURE_CLFSH_BIT (1U << 19U) -#define PORT_CPU_CPUID_FEATURE_DS_BIT (1U << 21U) +#define PORT_CPU_CPUID_FEATURE_DS_BIT (1U << 21U) #define PORT_CPU_CPUID_FEATURE_ACPI_BIT (1U << 22U) -#define PORT_CPU_CPUID_FEATURE_MMX_BIT (1U << 23U) -#define PORT_CPU_CPUID_FEATURE_FXSR_BIT (1U << 24U) -#define PORT_CPU_CPUID_FEATURE_SSE_BIT (1U << 25U) +#define PORT_CPU_CPUID_FEATURE_MMX_BIT (1U << 23U) +#define PORT_CPU_CPUID_FEATURE_FXSR_BIT (1U << 24U) +#define PORT_CPU_CPUID_FEATURE_SSE_BIT (1U << 25U) #define PORT_CPU_CPUID_FEATURE_SSE2_BIT (1U << 26U) -#define PORT_CPU_CPUID_FEATURE_SS_BIT (1U << 27U) +#define PORT_CPU_CPUID_FEATURE_SS_BIT (1U << 27U) #define PORT_CPU_CPUID_FEATURE_HTT_BIT (1U << 28U) #define PORT_CPU_CPUID_FEATURE_TM_BIT (1U << 29U) #define PORT_CPU_CPUID_FEATURE_PBE_BIT (1U << 31U) @@ -209,7 +209,7 @@ #define PORT_CPU_CPUID_TPM_FEATURE_HWPPECI_BIT (1U << 15U) #define PORT_CPU_CPUID_TPM_FEATURE_FLEXHWP_BIT (1U << 16U) #define PORT_CPU_CPUID_TPM_FEATURE_FAM_BIT (1U << 17U) -#define PORT_CPU_CPUID_TPM_FEATURE_ILPHWP_REQUEST_BIT (1U << 18U) +#define PORT_CPU_CPUID_TPM_FEATURE_ILPHWP_REQUEST_BIT (1U << 18U) #define PORT_CPU_CPUID_TPM_FEATURE_NFITI_DTS_BIT (1U << 0U) @@ -223,7 +223,7 @@ // Bits 7:0 of CPUID.0AH.EAX indicate the version of the Performance Monitor #define PORT_CPU_ARCH_PERF_MONITOR_VERSION_ID(a) ((a) & 0xFFU) // -// Bits 15:8 of CPUID.0AH.EAX indicate the number of performance +// Bits 15:8 of CPUID.0AH.EAX indicate the number of performance // counters available on the logical processor // #define PORT_CPU_ARCH_PERF_MONITOR_COUNTERS(a) (((a) & 0xFF00U)\ diff --git a/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c b/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c index 3ed2c93c18..f2d34cc81b 100644 --- a/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c +++ b/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c @@ -47,9 +47,9 @@ */ #define XORSHIFT_STATE_QWORDS 2 -struct PORT_CRYPTO_PRNG -{ - NvU64 state[XORSHIFT_STATE_QWORDS]; +struct PORT_CRYPTO_PRNG +{ + NvU64 state[XORSHIFT_STATE_QWORDS]; }; PORT_CRYPTO_PRNG *portCryptoDefaultGenerator; @@ -83,10 +83,10 @@ void portCryptoShutdown(void) /** * @brief Initializes a xorshift state from a 64bit seed. Performed using a * splitmix64 PRNG. - * + * * Adapted from: https://xorshift.di.unimi.it/splitmix64.c */ -static void _initState(NvU64 seed64, NvU64 state[XORSHIFT_STATE_QWORDS]) +static void _initState(NvU64 seed64, NvU64 state[XORSHIFT_STATE_QWORDS]) { NvU32 i; for (i = 0; i < XORSHIFT_STATE_QWORDS; i++) @@ -103,14 +103,14 @@ static void _initState(NvU64 seed64, NvU64 state[XORSHIFT_STATE_QWORDS]) * * Adapted from: https://xorshift.di.unimi.it/xorshift128plus.c */ -static NvU64 _xorshift128plus_GetU64(NvU64 state[2]) +static NvU64 _xorshift128plus_GetU64(NvU64 state[2]) { NvU64 s1 = state[0]; const NvU64 s0 = state[1]; state[0] = s0; s1 ^= s1 << 23; // a state[1] = s1 ^ s0 ^ (s1 >> 18) ^ (s0 >> 5); // b, c - return state[1] + s0; + return state[1] + s0; } PORT_CRYPTO_PRNG *portCryptoPseudoRandomGeneratorCreate(NvU64 seed) @@ -124,7 +124,7 @@ PORT_CRYPTO_PRNG *portCryptoPseudoRandomGeneratorCreate(NvU64 seed) return pPrng; } -void portCryptoPseudoRandomGeneratorDestroy(PORT_CRYPTO_PRNG *pPrng) +void portCryptoPseudoRandomGeneratorDestroy(PORT_CRYPTO_PRNG *pPrng) { portMemFree(pPrng); } @@ -150,7 +150,7 @@ NV_STATUS portCryptoPseudoRandomGeneratorFillBuffer(PORT_CRYPTO_PRNG *pPrng, NvU * we cannot fill the misaligned section first, then copy aligned qwords, * and then fill the remainder - That way we lose some bytes */ - + // Maybe require 64bit alignment for buffers: // PORT_ASSERT_CHECKED(portUtilCheckAlignment(pBuffer, sizeof(NvU64))); diff --git a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c index b0a880d3ee..4ff892230a 100644 --- a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c +++ b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -60,17 +60,17 @@ #else // // We can just stub out the atomic operations for non-atomic ones and not waste -// waste cycles on synchronization +// cycles on synchronization // -#define PORT_MEM_ATOMIC_ADD_SIZE(pVal, val) (*((NvSPtr *)pVal) += val) -#define PORT_MEM_ATOMIC_SUB_SIZE(pVal, val) (*((NvSPtr *)pVal) -= val) -#define PORT_MEM_ATOMIC_DEC_U32(pVal) (--(*((NvU32 *)pVal))) -#define PORT_MEM_ATOMIC_INC_U32(pVal) (++(*((NvU32 *)pVal))) -#define PORT_MEM_ATOMIC_SET_U32(pVal, val) (*((NvU32 *)pVal) = val) +#define PORT_MEM_ATOMIC_ADD_SIZE(pVal, val) (*((volatile NvSPtr *)pVal) += val) +#define PORT_MEM_ATOMIC_SUB_SIZE(pVal, val) (*((volatile NvSPtr *)pVal) -= val) +#define PORT_MEM_ATOMIC_DEC_U32(pVal) (--(*((volatile NvU32 *)pVal))) +#define PORT_MEM_ATOMIC_INC_U32(pVal) (++(*((volatile NvU32 *)pVal))) +#define PORT_MEM_ATOMIC_SET_U32(pVal, val) (*((volatile NvU32 *)pVal) = val) #define PORT_MEM_ATOMIC_CAS_SIZE(pVal, newVal, oldVal) \ - ((*pVal == oldVal) ? ((*((NvSPtr *)pVal) = newVal), NV_TRUE) : NV_FALSE) + ((*pVal == oldVal) ? ((*((volatile NvSPtr *)pVal) = newVal), NV_TRUE) : NV_FALSE) #define PORT_MEM_ATOMIC_CAS_U32(pVal, newVal, oldVal) \ - ((*pVal == oldVal) ? ((*((NvU32 *)pVal) = newVal), NV_TRUE) : NV_FALSE) + ((*pVal == oldVal) ? ((*((volatile NvU32 *)pVal) = newVal), NV_TRUE) : NV_FALSE) #endif // !PORT_MEM_THREAD_SAFE_ALLOCATIONS struct PORT_MEM_ALLOCATOR_IMPL @@ -156,12 +156,67 @@ static void portSyncSpinlockDestroy(PORT_SPINLOCK *pSpinlock) PORT_MEM_LOCK_RELEASE(lock); \ } while (0) - +// +// All memory tracking globals are contained in this structure +// +static struct PORT_MEM_GLOBALS +{ + PORT_MEM_ALLOCATOR_TRACKING mainTracking; + void *trackingLock; + struct + { + PORT_MEM_ALLOCATOR paged; + PORT_MEM_ALLOCATOR nonPaged; + PORT_MEM_ALLOCATOR_IMPL pagedImpl; + PORT_MEM_ALLOCATOR_IMPL nonPagedImpl; + } alloc; + NvU32 initCount; + NvU32 totalAllocators; +#if PORT_MEM_TRACK_USE_LIMIT + NvBool bLimitEnabled; + NvLength limitPid[PORT_MEM_LIMIT_MAX_PIDS]; + NvLength counterPid[PORT_MEM_LIMIT_MAX_PIDS]; +#endif +} portMemGlobals; // // Memory counter implementation // #if PORT_MEM_TRACK_USE_COUNTER +#if PORT_MEM_TRACK_ALLOC_SIZE +static NV_INLINE NvLength +_portMemExTrackingGetAllocUsableSizeWrapper +( + void *pMem +) +{ +#if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetAllocUsableSize) + // + // blockSize in PORT_MEM_HEADER does not include the size of the header/ + // footer, but the underlying malloc implementation doesn't know about + // those. Account for them here. + // + NvLength allocSize = portMemExTrackingGetAllocUsableSize(PORT_MEM_SUB_HEADER_PTR(pMem)); + PORT_ASSERT_CHECKED(allocSize > PORT_MEM_STAGING_SIZE); + return allocSize - PORT_MEM_STAGING_SIZE; +#elif PORT_MEM_HEADER_HAS_BLOCK_SIZE + return PORT_MEM_SUB_HEADER_PTR(pMem)->blockSize; +#endif +} +static NV_INLINE void +_portMemExTrackingSetOrGetAllocUsableSize +( + void *pMem, + NvLength *pSize +) +{ +#if PORT_MEM_HEADER_HAS_BLOCK_SIZE + PORT_MEM_SUB_HEADER_PTR(pMem)->blockSize = *pSize; +#else + *pSize = _portMemExTrackingGetAllocUsableSizeWrapper(pMem); +#endif +} +#endif // PORT_MEM_TRACK_ALLOC_SIZE static NV_INLINE void _portMemCounterInit ( @@ -182,50 +237,72 @@ _portMemCounterInc activeAllocs = PORT_MEM_ATOMIC_INC_U32(&pCounter->activeAllocs); PORT_MEM_ATOMIC_INC_U32(&pCounter->totalAllocs); - if (PORT_MEM_TRACK_USE_FENCEPOSTS) - { - activeSize = PORT_MEM_ATOMIC_ADD_SIZE(&pCounter->activeSize, size); - } +#if PORT_MEM_TRACK_ALLOC_SIZE + // + // activeSize is only tracked on configurations where we can retrieve the + // allocation size from allocation metadata in _portMemCounterDec. + // + activeSize = PORT_MEM_ATOMIC_ADD_SIZE(&pCounter->activeSize, size); +#endif + + // + // Note: this can overflow on 32-bit platforms if we exceed 4GB cumulative + // allocations. It's not trivial to fix, since NvPort doesn't emulate 64-bit + // atomics on 32-bit platforms, so just assume this doesn't happen (or + // doesn't matter too much if it does, since it's only for reporting). + // PORT_MEM_ATOMIC_ADD_SIZE(&pCounter->totalSize, size); - // Atomically compare the peak value with the active, and update if greater. - while (1) - { - NvU32 peakAllocs = pCounter->peakAllocs; - if (activeAllocs <= peakAllocs) - break; - PORT_MEM_ATOMIC_CAS_U32(&pCounter->peakAllocs, activeAllocs, peakAllocs); - } - while (1) + // Update the peak stats, if we're updating the peakSize { + NvU32 peakAllocs; NvLength peakSize = pCounter->peakSize; - if (activeSize <= peakSize) - break; - PORT_MEM_ATOMIC_CAS_SIZE(&pCounter->peakSize, activeSize, peakSize); + while (activeSize > peakSize) + { + PORT_MEM_ATOMIC_CAS_SIZE(&pCounter->peakSize, activeSize, peakSize); + peakSize = pCounter->peakSize; + } + + // + // Ensure peakAllocs stays (approximately) in sync with peakSize, rather + // than always taking the greatest peakAllocs, so that the peak stats + // report is consistent. + // + do + { + peakAllocs = pCounter->peakAllocs; + + // + // Only attempt to update the peakAllocs if activeSize is still the + // peakSize. + // + if (activeSize != pCounter->peakSize) + break; + } while (!PORT_MEM_ATOMIC_CAS_U32(&pCounter->peakAllocs, activeAllocs, peakAllocs)); } } static NV_INLINE void _portMemCounterDec ( PORT_MEM_COUNTER *pCounter, - void *pMem + NvLength size ) { PORT_MEM_ATOMIC_DEC_U32(&pCounter->activeAllocs); - if (PORT_MEM_TRACK_USE_FENCEPOSTS) - { - PORT_MEM_ATOMIC_SUB_SIZE(&pCounter->activeSize, - ((PORT_MEM_FENCE_HEAD *)pMem-1)->blockSize); - } +#if PORT_MEM_TRACK_ALLOC_SIZE + PORT_MEM_ATOMIC_SUB_SIZE(&pCounter->activeSize, size); +#else + PORT_UNREFERENCED_VARIABLE(size); +#endif } #define PORT_MEM_COUNTER_INIT(pCounter) _portMemCounterInit(pCounter) #define PORT_MEM_COUNTER_INC(pCounter, size) _portMemCounterInc(pCounter, size) -#define PORT_MEM_COUNTER_DEC(pCounter, pMem) _portMemCounterDec(pCounter, pMem) +#define PORT_MEM_COUNTER_DEC(pCounter, size) _portMemCounterDec(pCounter, size) #else #define PORT_MEM_COUNTER_INIT(x) -#define PORT_MEM_COUNTER_INC(x, y) -#define PORT_MEM_COUNTER_DEC(x, y) +#define PORT_MEM_COUNTER_INC(x, y) PORT_UNREFERENCED_VARIABLE(y) +#define PORT_MEM_COUNTER_DEC(x, y) PORT_UNREFERENCED_VARIABLE(y) #endif // COUNTER @@ -248,7 +325,6 @@ _portMemFenceInit PORT_MEM_FOOTER *pTail = (PORT_MEM_FOOTER*)((NvU8*)pMem + size); pHead->fence.pAllocator = pAlloc; - pHead->fence.blockSize = size; pHead->fence.magic = PORT_MEM_FENCE_HEAD_MAGIC; pTail->fence.magic = PORT_MEM_FENCE_TAIL_MAGIC; } @@ -257,12 +333,12 @@ static NV_INLINE void _portMemFenceCheck ( PORT_MEM_ALLOCATOR *pAlloc, - void *pMem + void *pMem, + NvLength size ) { PORT_MEM_HEADER *pHead = (PORT_MEM_HEADER*)pMem - 1; - PORT_MEM_FOOTER *pTail = (PORT_MEM_FOOTER*) - ((NvU8*)pMem + pHead->fence.blockSize); + PORT_MEM_FOOTER *pTail = (PORT_MEM_FOOTER*)((NvU8*)pMem + size); if (pHead->fence.magic != PORT_MEM_FENCE_HEAD_MAGIC || pTail->fence.magic != PORT_MEM_FENCE_TAIL_MAGIC) @@ -280,11 +356,11 @@ _portMemFenceCheck } } -#define PORT_MEM_FENCE_CHECK(pAlloc, pMem) _portMemFenceCheck(pAlloc, pMem) -#define PORT_MEM_FENCE_INIT(pAlloc, pMem, size) _portMemFenceInit(pAlloc, pMem, size) +#define PORT_MEM_FENCE_CHECK(pAlloc, pMem, size) _portMemFenceCheck(pAlloc, pMem, size) +#define PORT_MEM_FENCE_INIT(pAlloc, pMem, size) _portMemFenceInit(pAlloc, pMem, size) #else #define PORT_MEM_FENCE_INIT(x, y, z) -#define PORT_MEM_FENCE_CHECK(x, y) +#define PORT_MEM_FENCE_CHECK(x, y, z) #endif // FENCEPOSTS @@ -410,7 +486,7 @@ typedef struct PORT_MEM_LOG_ENTRY { NvP64 address; NvP64 allocator; - NvU64 size; // if size is 0, it is a free() call, not alloc() + NvLength size; // if size is 0, it is a free() call, not alloc() } PORT_MEM_LOG_ENTRY; #define PORT_MEM_TRACK_LOG_TAG 0x70726d74 @@ -482,8 +558,8 @@ static PORT_MEM_ALLOCATOR *_portMemAllocatorCreateOnExistingBlock(void *pAlloc, static void *_portMemAllocatorAllocExistingWrapper(PORT_MEM_ALLOCATOR *pAlloc, NvLength length); static void _portMemAllocatorFreeExistingWrapper(PORT_MEM_ALLOCATOR *pAlloc, void *pMem); -static void _portMemTrackingRelease(PORT_MEM_ALLOCATOR_TRACKING *pTracking); -static void _portMemTrackAlloc(PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem, NvLength size PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM); +static void _portMemTrackingRelease(PORT_MEM_ALLOCATOR_TRACKING *pTracking, NvBool bReportLeaks); +static void _portMemTrackAlloc(PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem, NvLength size, NvU32 pid PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM); static void _portMemTrackFree(PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem); @@ -508,52 +584,27 @@ static void _portMemTrackFree(PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem #define portMemExAllocatorCreateLockedOnExistingBlock portMemExAllocatorCreateLockedOnExistingBlock_CallerInfo #endif -// -// All memory tracking globals are contained in this structure -// -static struct PORT_MEM_GLOBALS -{ - PORT_MEM_ALLOCATOR_TRACKING mainTracking; - void *trackingLock; - struct - { - PORT_MEM_ALLOCATOR paged; - PORT_MEM_ALLOCATOR nonPaged; - PORT_MEM_ALLOCATOR_IMPL pagedImpl; - PORT_MEM_ALLOCATOR_IMPL nonPagedImpl; - } alloc; - NvU32 initCount; - NvU32 totalAllocators; -#if PORT_MEM_TRACK_USE_LIMIT - NvBool bLimitEnabled; - NvU64 limitPid[PORT_MEM_LIMIT_MAX_PIDS]; - NvU64 counterPid[PORT_MEM_LIMIT_MAX_PIDS]; -#endif -} portMemGlobals; - // // Per-process heap limiting implementation // #if PORT_MEM_TRACK_USE_LIMIT static NV_INLINE void -_portMemLimitInc(NvU32 pid, void *pMem, NvU64 size) +_portMemLimitInc(NvU32 pid, void *pMem, NvLength size) { + PORT_MEM_HEADER *pMemHeader = PORT_MEM_SUB_HEADER_PTR(pMem); + pMemHeader->pid = pid; if (portMemGlobals.bLimitEnabled) { - PORT_MEM_HEADER *pMemHeader = PORT_MEM_SUB_HEADER_PTR(pMem); - pMemHeader->pid = pid; - if ((pid > 0) && (pid <= PORT_MEM_LIMIT_MAX_PIDS)) { NvU32 pidIdx = pid - 1; - pMemHeader->blockSize = size; PORT_MEM_ATOMIC_ADD_SIZE(&portMemGlobals.counterPid[pidIdx], size); } } } static NV_INLINE void -_portMemLimitDec(void *pMem) +_portMemLimitDec(void *pMem, NvLength size) { if (portMemGlobals.bLimitEnabled) { @@ -563,22 +614,21 @@ _portMemLimitDec(void *pMem) if ((pid > 0) && (pid <= PORT_MEM_LIMIT_MAX_PIDS)) { NvU32 pidIdx = pid - 1; - if (portMemGlobals.counterPid[pidIdx] < pMemHeader->blockSize) + if (portMemGlobals.counterPid[pidIdx] < size) { - // TODO: How do we protect against double frees? PORT_MEM_PRINT_ERROR("memory free error: counter underflow\n"); PORT_BREAKPOINT_CHECKED(); } else { - PORT_MEM_ATOMIC_SUB_SIZE(&portMemGlobals.counterPid[pidIdx], pMemHeader->blockSize); + PORT_MEM_ATOMIC_SUB_SIZE(&portMemGlobals.counterPid[pidIdx], size); } } } } static NV_INLINE NvBool -_portMemLimitExceeded(NvU32 pid, NvU64 size) +_portMemLimitExceeded(NvU32 pid, NvLength size) { NvBool bExceeded = NV_FALSE; @@ -589,7 +639,7 @@ _portMemLimitExceeded(NvU32 pid, NvU64 size) NvU32 pidIdx = pid - 1; if ((size + portMemGlobals.counterPid[pidIdx]) > portMemGlobals.limitPid[pidIdx]) { - PORT_MEM_PRINT_ERROR("memory allocation denied; PID %d exceeded per-process heap limit of 0x%llx\n", + PORT_MEM_PRINT_ERROR("memory allocation denied; PID %d exceeded per-process heap limit of %"NvUPtr_fmtu"\n", pid, portMemGlobals.limitPid[pidIdx]); bExceeded = NV_TRUE; } @@ -599,11 +649,20 @@ _portMemLimitExceeded(NvU32 pid, NvU64 size) } #define PORT_MEM_LIMIT_INC(pid, pMem, size) _portMemLimitInc(pid, pMem, size) -#define PORT_MEM_LIMIT_DEC(pMem) _portMemLimitDec(pMem) +#define PORT_MEM_LIMIT_DEC(pMem, size) _portMemLimitDec(pMem, size) #define PORT_MEM_LIMIT_EXCEEDED(pid, size) _portMemLimitExceeded(pid, size) #else -#define PORT_MEM_LIMIT_INC(pid, pMem, size) -#define PORT_MEM_LIMIT_DEC(pMem) +#define PORT_MEM_LIMIT_INC(pid, pMem, size) \ + do { \ + PORT_UNREFERENCED_VARIABLE(pid); \ + PORT_UNREFERENCED_VARIABLE(pMem); \ + PORT_UNREFERENCED_VARIABLE(size); \ + } while (0) +#define PORT_MEM_LIMIT_DEC(pMem, size) \ + do { \ + PORT_UNREFERENCED_VARIABLE(pMem); \ + PORT_UNREFERENCED_VARIABLE(size); \ + } while (0) #define PORT_MEM_LIMIT_EXCEEDED(pid, size) (NV_FALSE) #endif // PORT_MEM_TRACK_USE_LIMIT @@ -652,6 +711,11 @@ portMemInitialize(void) if (PORT_MEM_TRACK_USE_FENCEPOSTS) { + // + // Distinct paged and non-paged allocators require PORT_MEM_TRACK_USE_FENCEPOSTS + // so that the correct allocator can be looked up from the fenceposts in the + // portMemFree path. + // portMemGlobals.alloc.paged.pImpl = &portMemGlobals.alloc.pagedImpl; portMemGlobals.alloc.nonPaged.pImpl = &portMemGlobals.alloc.nonPagedImpl; @@ -685,19 +749,19 @@ portMemShutdown(NvBool bForceSilent) #if (PORT_MEM_TRACK_PRINT_LEVEL > PORT_MEM_TRACK_PRINT_LEVEL_SILENT) if (!bForceSilent) { - portMemPrintTrackingInfo(NULL); + portMemPrintAllTrackingInfo(); } #endif PORT_MEM_LOG_DESTROY(); if (PORT_MEM_TRACK_USE_FENCEPOSTS) { - _portMemTrackingRelease(&portMemGlobals.alloc.nonPaged.pImpl->tracking); - _portMemTrackingRelease(&portMemGlobals.alloc.paged.pImpl->tracking); + _portMemTrackingRelease(&portMemGlobals.alloc.nonPaged.pImpl->tracking, NV_FALSE); + _portMemTrackingRelease(&portMemGlobals.alloc.paged.pImpl->tracking, NV_FALSE); } else { - _portMemTrackingRelease(&portMemGlobals.alloc.pagedImpl.tracking); + _portMemTrackingRelease(&portMemGlobals.alloc.pagedImpl.tracking, NV_FALSE); } PORT_MEM_LOCK_DESTROY(portMemGlobals.trackingLock); @@ -705,7 +769,6 @@ portMemShutdown(NvBool bForceSilent) portMemSet(&portMemGlobals, 0, sizeof(portMemGlobals)); } - void * portMemAllocPaged ( @@ -838,7 +901,7 @@ portMemAllocatorRelease PORT_BREAKPOINT_CHECKED(); return; } - _portMemTrackingRelease(pAllocator->pTracking); + _portMemTrackingRelease(pAllocator->pTracking, NV_TRUE); PORT_MEM_PRINT_INFO("Released allocator %p\n", pAllocator); if (pAllocator->_portRelease != NULL) @@ -885,7 +948,7 @@ portMemInitializeAllocatorTracking #if PORT_MEM_TRACK_USE_LIMIT void -portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvU64 limit, NvBool bLimitEnabled) +portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvLength limit, NvBool bLimitEnabled) { NvU32 pidIdx = pid - 1; portMemGlobals.limitPid[pidIdx] = limit; @@ -901,9 +964,7 @@ _portMemAllocatorAlloc PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { -#if PORT_MEM_TRACK_USE_LIMIT NvU32 pid = 0; -#endif void *pMem = NULL; if (pAlloc == NULL) { @@ -948,9 +1009,8 @@ _portMemAllocatorAlloc if (pMem != NULL) { pMem = PORT_MEM_ADD_HEADER_PTR(pMem); - _portMemTrackAlloc(_portMemGetTracking(pAlloc), pMem, length + _portMemTrackAlloc(_portMemGetTracking(pAlloc), pMem, length, pid PORT_MEM_CALLERINFO_COMMA_PARAM); - PORT_MEM_LIMIT_INC(pid, pMem, length); } return pMem; } @@ -968,7 +1028,6 @@ _portMemAllocatorFree } if (pMem != NULL) { - PORT_MEM_LIMIT_DEC(pMem); _portMemTrackFree(_portMemGetTracking(pAlloc), pMem); pMem = PORT_MEM_SUB_HEADER_PTR(pMem); pAlloc->_portFree(pAlloc, pMem); @@ -978,128 +1037,133 @@ _portMemAllocatorFree void portMemPrintTrackingInfo ( - const PORT_MEM_ALLOCATOR *pAllocator + const PORT_MEM_ALLOCATOR_TRACKING *pTracking ) { - PORT_MEM_ALLOCATOR_TRACKING *pTracking = _portMemGetTracking(pAllocator); + if (pTracking == NULL) + pTracking = &portMemGlobals.mainTracking; + + if (pTracking == &portMemGlobals.mainTracking) + portDbgPrintf("[NvPort] ******** Aggregate Memory Tracking ********\n"); + else if ((pTracking == portMemGlobals.alloc.nonPaged.pTracking) && + (pTracking == portMemGlobals.alloc.paged.pTracking)) + portDbgPrintf("[NvPort] ******** Global Allocator Tracking ********\n"); + else if (pTracking == portMemGlobals.alloc.nonPaged.pTracking) + portDbgPrintf("[NvPort] ******** Global Non-Paged Memory Allocator Tracking ********\n"); + else if (pTracking == portMemGlobals.alloc.paged.pTracking) + portDbgPrintf("[NvPort] ******** Global Paged Memory Allocator Tracking ********\n"); + else + portDbgPrintf("[NvPort] ******** Memory Allocator %p Tracking ******** \n", pTracking->pAllocator); - portDbgPrintf("[NvPort] *************************************************\n"); + if (pTracking->counter.activeAllocs != 0) + portDbgPrintf(" !!! MEMORY LEAK DETECTED (%u blocks) !!!\n", + pTracking->counter.activeAllocs); - if (pAllocator == NULL) +#if PORT_MEM_TRACK_USE_CALLERINFO { - portDbgPrintf("NvPort memory tracking information for all allocations:\n"); + portDbgPrintf(" Allocator acquired " + PORT_MEM_CALLERINFO_PRINT_ARGS(pTracking->callerInfo)); } +#endif - if (pTracking == NULL) - { - portDbgPrintf("Allocator %p initialized before portMemInitialize(); no tracking info.\n", pAllocator); - return; - } - - for (;;) - { - if (pTracking->pAllocator == NULL) - { - portDbgPrintf("NULL allocator for tracker %p:\n", pTracking); - goto next_tracking; - } - - portDbgPrintf("NvPort memory tracking information for allocator %p:\n", - pTracking->pAllocator); - -#if PORT_MEM_TRACK_USE_CALLERINFO - { - portDbgPrintf(" Allocator acquired " - PORT_MEM_CALLERINFO_PRINT_ARGS(pTracking->callerInfo)); - } +#if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetHeapSize) + // + // Heap is shared across all allocators, so only print it with the + // aggregate stats. + // + if (pTracking == _portMemGetTracking(NULL)) + portDbgPrintf(" HEAP: %"NvUPtr_fmtu" bytes\n", portMemExTrackingGetHeapSize()); #endif #if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetActiveStats) - { - PORT_MEM_TRACK_ALLOCATOR_STATS stats; + { + PORT_MEM_TRACK_ALLOCATOR_STATS stats; - portMemSet(&stats, 0, sizeof(stats)); + portMemSet(&stats, 0, sizeof(stats)); - portMemExTrackingGetActiveStats(pTracking->pAllocator, &stats); + portMemExTrackingGetActiveStats(pTracking->pAllocator, &stats); - // - // rmtest_gsp test script (dvs_gsp_sanity.sh) depends on this print, so do not change - // format without updating script! - // - portDbgPrintf("ACTIVE: %u allocations, %llu bytes allocated (%llu useful, %llu meta)\n", - stats.numAllocations, - (NvU64) stats.allocatedSize, - (NvU64) stats.usefulSize, - (NvU64) stats.metaSize); - } + // + // rmtest_gsp test script (dvs_gsp_sanity.sh) depends on this print, so do not change + // format without updating script! + // + portDbgPrintf(" ACTIVE: %u allocations, %"NvUPtr_fmtu" bytes allocated (%"NvUPtr_fmtu" useful, %"NvUPtr_fmtu" meta)\n", + stats.numAllocations, + stats.allocatedSize, + stats.usefulSize, + stats.metaSize); + } #endif #if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetTotalStats) - { - PORT_MEM_TRACK_ALLOCATOR_STATS stats; + { + PORT_MEM_TRACK_ALLOCATOR_STATS stats; - portMemSet(&stats, 0, sizeof(stats)); + portMemSet(&stats, 0, sizeof(stats)); - portMemExTrackingGetTotalStats(pTracking->pAllocator, &stats); - portDbgPrintf("TOTAL: %u allocations, %llu bytes allocated (%llu useful, %llu meta)\n", - stats.numAllocations, - (NvU64) stats.allocatedSize, - (NvU64) stats.usefulSize, - (NvU64) stats.metaSize); - } + portMemExTrackingGetTotalStats(pTracking->pAllocator, &stats); + portDbgPrintf(" TOTAL: %u allocations, %"NvUPtr_fmtu" bytes allocated (%"NvUPtr_fmtu" useful, %"NvUPtr_fmtu" meta)\n", + stats.numAllocations, + stats.allocatedSize, + stats.usefulSize, + stats.metaSize); + } #endif #if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetPeakStats) - { - PORT_MEM_TRACK_ALLOCATOR_STATS stats; + { + PORT_MEM_TRACK_ALLOCATOR_STATS stats; - portMemSet(&stats, 0, sizeof(stats)); + portMemSet(&stats, 0, sizeof(stats)); - portMemExTrackingGetPeakStats(pTracking->pAllocator, &stats); - portDbgPrintf("PEAK: %u allocations, %llu bytes allocated (%llu useful, %llu meta)\n", - stats.numAllocations, - (NvU64) stats.allocatedSize, - (NvU64) stats.usefulSize, - (NvU64) stats.metaSize); - } + portMemExTrackingGetPeakStats(pTracking->pAllocator, &stats); + portDbgPrintf(" PEAK: %u allocations, %"NvUPtr_fmtu" bytes allocated (%"NvUPtr_fmtu" useful, %"NvUPtr_fmtu" meta)\n", + stats.numAllocations, + stats.allocatedSize, + stats.usefulSize, + stats.metaSize); + } #endif #if PORT_IS_FUNC_SUPPORTED(portMemExTrackingGetNext) - { - PORT_MEM_TRACK_ALLOC_INFO info; - NvBool bPrinted = NV_FALSE; - void *iterator = NULL; + { + PORT_MEM_TRACK_ALLOC_INFO info; + NvBool bPrinted = NV_FALSE; + void *iterator = NULL; - do + do + { + if (portMemExTrackingGetNext(pTracking->pAllocator, &info, &iterator) != NV_OK) { - if (portMemExTrackingGetNext(pTracking->pAllocator, &info, &iterator) != NV_OK) - { - portDbgPrintf("(no active allocations)\n"); - break; - } - else if (!bPrinted) - { - portDbgPrintf("Currently active allocations:\n"); - bPrinted = NV_TRUE; - } - portDbgPrintf(" - A:%p - 0x%p [%8llu bytes] T=%llu ", - info.pAllocator, - info.pMemory, - (NvU64)info.size, - info.timestamp); - portDbgPrintf(PORT_MEM_CALLERINFO_PRINT_ARGS(info.callerInfo)); - } while (iterator != NULL); - } + portDbgPrintf(" (no active allocations)\n"); + break; + } + else if (!bPrinted) + { + portDbgPrintf(" Currently active allocations:\n"); + bPrinted = NV_TRUE; + } + portDbgPrintf(" - A:%p - 0x%p [%8"NvUPtr_fmtu" bytes] T=%llu ", + info.pAllocator, + info.pMemory, + info.size, + info.timestamp); + portDbgPrintf(PORT_MEM_CALLERINFO_PRINT_ARGS(info.callerInfo)); + } while (iterator != NULL); + } #endif +} -next_tracking: - portDbgPrintf("[NvPort] *************************************************\n"); - - if ((pAllocator != NULL) || (pTracking->pNext == &portMemGlobals.mainTracking)) - break; - - pTracking = pTracking->pNext; - } +void +portMemPrintAllTrackingInfo(void) +{ + const PORT_MEM_ALLOCATOR_TRACKING *pTracking = &portMemGlobals.mainTracking; + PORT_MEM_LOCK_ACQUIRE(portMemGlobals.trackingLock); + do + { + portMemPrintTrackingInfo(pTracking); + } while ((pTracking = pTracking->pNext) != &portMemGlobals.mainTracking); + PORT_MEM_LOCK_RELEASE(portMemGlobals.trackingLock); } #if portMemExTrackingGetActiveStats_SUPPORTED @@ -1201,7 +1265,7 @@ portMemExTrackingGetNext // Populate pInfo pInfo->pMemory = pHead + 1; - pInfo->size = pHead->fence.blockSize; + pInfo->size = _portMemExTrackingGetAllocUsableSizeWrapper(pInfo->pMemory); pInfo->pAllocator = pHead->fence.pAllocator; pInfo->timestamp = 0; @@ -1216,18 +1280,18 @@ portMemExTrackingGetNext static void _portMemTrackingRelease ( - PORT_MEM_ALLOCATOR_TRACKING *pTracking + PORT_MEM_ALLOCATOR_TRACKING *pTracking, + NvBool bReportLeaks ) { if (pTracking == NULL) return; - if (pTracking->counter.activeAllocs != 0) - { - PORT_MEM_PRINT_ERROR("Allocator %p released with memory allocations\n", pTracking->pAllocator); #if (PORT_MEM_TRACK_PRINT_LEVEL > PORT_MEM_TRACK_PRINT_LEVEL_SILENT) - portMemPrintTrackingInfo(pTracking->pAllocator); + if (bReportLeaks && (pTracking->counter.activeAllocs != 0)) + portMemPrintTrackingInfo(pTracking); +#else + PORT_UNREFERENCED_VARIABLE(bReportLeaks); #endif - } PORT_LOCKED_LIST_UNLINK(&portMemGlobals.mainTracking, pTracking, portMemGlobals.trackingLock); PORT_MEM_LIST_DESTROY(pTracking); @@ -1239,17 +1303,29 @@ _portMemTrackAlloc ( PORT_MEM_ALLOCATOR_TRACKING *pTracking, void *pMem, - NvLength size + NvLength size, + NvU32 pid PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { PORT_UNREFERENCED_VARIABLE(pMem); if (pTracking == NULL) return; - PORT_MEM_PRINT_INFO("Allocating %u bytes at address %p", size, pMem); + +#if PORT_MEM_TRACK_ALLOC_SIZE + // + // Either set the block size in the header, or override it with the value + // from the underlying allocator (which may be bigger than what was + // requested). This keeps the counters consistent with the free path. + // + _portMemExTrackingSetOrGetAllocUsableSize(pMem, &size); +#endif + + PORT_MEM_PRINT_INFO("Allocated %"NvUPtr_fmtu" bytes at address %p", size, pMem); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); PORT_MEM_COUNTER_INC(&pTracking->counter, size); PORT_MEM_COUNTER_INC(&portMemGlobals.mainTracking.counter, size); + PORT_MEM_LIMIT_INC(pid, pMem, size); PORT_MEM_FENCE_INIT(pTracking->pAllocator, pMem, size); PORT_MEM_LIST_ADD(pTracking, pMem); @@ -1264,13 +1340,22 @@ _portMemTrackFree void *pMem ) { + NvLength size = 0; + if (pTracking == NULL) return; + +#if PORT_MEM_TRACK_ALLOC_SIZE + size = _portMemExTrackingGetAllocUsableSizeWrapper(pMem); + PORT_MEM_PRINT_INFO("Freeing %"NvUPtr_fmtu"-byte block at address %p\n", size, pMem); +#else PORT_MEM_PRINT_INFO("Freeing block at address %p\n", pMem); +#endif - PORT_MEM_COUNTER_DEC(&pTracking->counter, pMem); - PORT_MEM_COUNTER_DEC(&portMemGlobals.mainTracking.counter, pMem); + PORT_MEM_COUNTER_DEC(&pTracking->counter, size); + PORT_MEM_COUNTER_DEC(&portMemGlobals.mainTracking.counter, size); + PORT_MEM_LIMIT_DEC(pMem, size); - PORT_MEM_FENCE_CHECK(pTracking->pAllocator, pMem); + PORT_MEM_FENCE_CHECK(pTracking->pAllocator, pMem, size); PORT_MEM_LIST_REMOVE(pTracking, pMem); PORT_MEM_LOG_FREE(pTracking->pAllocator, pMem); } @@ -1390,7 +1475,7 @@ _portMemAllocatorCreateOnExistingBlock } portMemSet(pBitVector->bits, 0, bitVectorSize); - PORT_MEM_PRINT_INFO("Acquired preallocated block allocator %p (%llu bytes) ", pAllocator, (NvU64)blockSizeBytes); + PORT_MEM_PRINT_INFO("Acquired preallocated block allocator %p (%"NvUPtr_fmtu" bytes) ", pAllocator, blockSizeBytes); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); return pAllocator; } diff --git a/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c b/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c index 70fb5ca349..b7445e64a2 100644 --- a/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c +++ b/src/nvidia/src/libraries/nvport/memory/memory_unix_kernel_os.c @@ -194,12 +194,12 @@ portMemExGetPageSize(void) } // Large allocations (>KMALLOC_LIMIT) will fail, but it is safe to call -NvBool +NvBool portMemExSafeForPagedAlloc(void) { return NV_TRUE; } -NvBool +NvBool portMemExSafeForNonPagedAlloc(void) { return NV_TRUE; diff --git a/src/nvidia/src/libraries/poolalloc/poolalloc.c b/src/nvidia/src/libraries/poolalloc/poolalloc.c index 6db3cd2d86..ff80779ad4 100644 --- a/src/nvidia/src/libraries/poolalloc/poolalloc.c +++ b/src/nvidia/src/libraries/poolalloc/poolalloc.c @@ -26,10 +26,6 @@ #include "utils/nvprintf.h" #include "utils/nvassert.h" -// Local defines -#define LOG_ENTER NV_PRINTF(LEVEL_INFO, "--> %s at line %d\n", __FUNCTION__, __LINE__) -#define LOG_EXIT NV_PRINTF(LEVEL_INFO, "<-- %s at line %d\n", __FUNCTION__, __LINE__) - // Local function declarations. static NvU32 ntz_64 (NvU64 bits); static NvU32 countZeros(NvU64 bits); @@ -56,10 +52,10 @@ ntz_64 return ((NvU32)(bz + b5 + b4 + b3 + b2 + b1 + b0)); } -static void +static void _setBitmap ( - NvU64 *bitmap, + NvU64 *bitmap, NvU32 index ) { @@ -126,8 +122,8 @@ poolListPrint it = listIterAll(pList); while (listIterNext(&it)) { - NV_PRINTF_EX(POOLALLOC, LEVEL_NOTICE, - "=> [pageAddr: 0x%llx, bitmap: 0x%llx]", + NV_PRINTF_EX(POOLALLOC, LEVEL_NOTICE, + "=> [pageAddr: 0x%llx, bitmap: 0x%llx]", it.pValue->pageAddr, it.pValue->bitmap); } NV_PRINTF_EX(POOLALLOC, LEVEL_NOTICE, "\n"); @@ -137,7 +133,7 @@ poolListPrint static void allocFreeList ( - POOLALLOC *pPool, + POOLALLOC *pPool, POOLALLOC_HANDLE *pPageHandle ) { @@ -167,7 +163,7 @@ allocFreeList static void allocPartialList ( - POOLALLOC *pPool, + POOLALLOC *pPool, POOLALLOC_HANDLE *pPageHandle ) { @@ -202,9 +198,9 @@ poolAllocPrint ) { #if defined(DEBUG_VERBOSE) - NV_PRINTF(LEVEL_NOTICE, "upstreamPageSize = %dKB, allocPageSize = %d%s\n", - (pPool->upstreamPageSize >> 10), - (pPool->allocPageSize >> 10) ? pPool->allocPageSize >> 10 : + NV_PRINTF(LEVEL_NOTICE, "upstreamPageSize = %lldKB, allocPageSize = %lld%s\n", + (pPool->upstreamPageSize >> 10), + (pPool->allocPageSize >> 10) ? pPool->allocPageSize >> 10 : pPool->allocPageSize, (pPool->allocPageSize >> 10) ? "KB" : "B"); NV_PRINTF_EX(POOLALLOC, LEVEL_NOTICE, "freeList => "); @@ -220,8 +216,8 @@ poolAllocPrint POOLALLOC * poolInitialize ( - NvU32 upstreamPageSize, - NvU32 allocPageSize, + NvU64 upstreamPageSize, + NvU64 allocPageSize, allocCallback_t allocCb, freeCallback_t freeCb, void *ctxPtr, @@ -230,7 +226,6 @@ poolInitialize ) { POOLALLOC *pPool; - LOG_ENTER; pPool = PORT_ALLOC(pAllocator, sizeof(*pPool)); if (pPool == NULL) @@ -240,7 +235,7 @@ poolInitialize pPool->upstreamPageSize = upstreamPageSize; pPool->allocPageSize = allocPageSize; - pPool->ratio = upstreamPageSize / allocPageSize; + pPool->ratio = (NvU32)(upstreamPageSize / allocPageSize); pPool->flags = flags; (pPool->callBackInfo).allocCb = allocCb; @@ -253,10 +248,9 @@ poolInitialize listInitIntrusive(&pPool->fullList); listInitIntrusive(&pPool->partialList); - NV_PRINTF(LEVEL_INFO, "Initialized pool with upstreamPageSize = %dB, allocPageSize = %dB and autoPopulate %s\n", + NV_PRINTF(LEVEL_INFO, "Initialized pool with upstreamPageSize = %lldB, allocPageSize = %lldB and autoPopulate %s\n", pPool->upstreamPageSize, pPool->allocPageSize, ((pPool->flags & NV_RMPOOL_FLAGS_AUTO_POPULATE_ENABLE) ? "enabled" : "disabled")); - LOG_EXIT; return pPool; } @@ -272,18 +266,14 @@ poolReserve allocCallback_t allocCb; POOLALLOC_HANDLE pageHandle; - LOG_ENTER; - if (pPool == NULL || (pPool->callBackInfo).allocCb == NULL) { - LOG_EXIT; return NV_ERR_INVALID_ARGUMENT; } freeLength = listCount(&pPool->freeList); if (freeLength >= numPages) { - LOG_EXIT; return NV_OK; } @@ -305,7 +295,6 @@ poolReserve } else { - LOG_EXIT; return NV_ERR_NO_MEMORY; } } @@ -313,7 +302,6 @@ poolReserve freeLength = listCount(&pPool->freeList); NV_ASSERT(freeLength == numPages); - LOG_EXIT; return NV_OK; } @@ -328,17 +316,14 @@ poolTrim NvU64 i, freeLength; freeCallback_t freeCb; - LOG_ENTER; if (pPool == NULL || (pPool->callBackInfo).freeCb == NULL) { - LOG_EXIT; return; } freeLength = listCount(&pPool->freeList); if (freeLength <= preserveNum) { - LOG_EXIT; return; } @@ -362,7 +347,6 @@ poolTrim freeLength = listCount(&pPool->freeList); NV_ASSERT(freeLength == preserveNum); - LOG_EXIT; } @@ -377,13 +361,10 @@ poolAllocate { allocCallback_t allocCb; - LOG_ENTER; - // Trying allocating from the partial list first. if (listCount(&pPool->partialList) > 0) { allocPartialList(pPool, pPageHandle); - LOG_EXIT; return NV_OK; } @@ -391,14 +372,13 @@ poolAllocate if (listCount(&pPool->freeList) > 0) { allocFreeList(pPool, pPageHandle); - LOG_EXIT; return NV_OK; } allocCb = (pPool->callBackInfo).allocCb; // - // Nothing left in free list as well!! Populate the pool if it is configured to be auto-populated + // Nothing left in free list as well!! Populate the pool if it is configured to be auto-populated // Once we have free list then allocate from free list. // if (FLD_TEST_DRF(_RMPOOL, _FLAGS, _AUTO_POPULATE, _ENABLE, pPool->flags)) @@ -416,18 +396,15 @@ poolAllocate allocFreeList(pPool, pPageHandle); - LOG_EXIT; return NV_OK; } } - LOG_EXIT; - return NV_ERR_NO_MEMORY; } -NV_STATUS +NV_STATUS poolAllocateContig ( POOLALLOC *pPool, @@ -442,8 +419,6 @@ poolAllocateContig PoolPageHandleListIter it; NvU64 prevAddr, curAddr; - LOG_ENTER; - // can't allocate more than one upstream chunk NV_ASSERT_OR_RETURN(numPages <= pPool->ratio, NV_ERR_INVALID_ARGUMENT); @@ -510,8 +485,6 @@ poolFree NvU32 freeIdx; NvU64 address, baseAddr; - LOG_ENTER; - address = pPageHandle->address; pNode = (POOLNODE *) (pPageHandle->pMetadata); baseAddr = pNode->pageAddr; @@ -548,8 +521,6 @@ poolFree listPrependExisting(&pPool->freeList, pNode); } } - - LOG_EXIT; } @@ -559,15 +530,12 @@ poolDestroy POOLALLOC *pPool ) { - LOG_ENTER; - // call back to free all the pages poolListDestroy(&pPool->fullList, pPool); poolListDestroy(&pPool->partialList, pPool); poolListDestroy(&pPool->freeList, pPool); PORT_FREE(pPool->pAllocator, pPool); - LOG_EXIT; } void diff --git a/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c b/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c index e787b9571c..444928eb28 100644 --- a/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c +++ b/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c @@ -107,7 +107,7 @@ _prereqArm // Put together a mask of PREREQ_IDs which are both satisfied and requested // We do not keep track of satisfied prereqs until armed, so we have no existing // state to worry about here. - // + // NV_ASSERT_OK_OR_RETURN(bitVectorAnd(&requestedAndSatisfied, &pPrereq->requested, &pTracker->satisfied)); diff --git a/src/nvidia/src/libraries/resserv/src/rs_client.c b/src/nvidia/src/libraries/resserv/src/rs_client.c index 5d5b20210d..358061c164 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_client.c +++ b/src/nvidia/src/libraries/resserv/src/rs_client.c @@ -102,7 +102,7 @@ clientConstruct_IMPL status = clientSetHandleGenerator(pClient, 0, 0); if (status != NV_OK) return status; - + pClient->bActive = NV_TRUE; status = clientSetRestrictedRange(pClient, 0, 0); @@ -281,10 +281,10 @@ clientShareResourceTargetClient_IMPL return NV_OK; } -NV_STATUS +NV_STATUS clientSetRestrictedRange_IMPL ( - RsClient *pClient, + RsClient *pClient, NvHandle handleRangeStart, NvU32 handleRangeSize ) @@ -535,7 +535,7 @@ clientCopyResource_IMPL (pServer->bRsAccessEnabled || (pParams->pSrcClient->hClient != pClient->hClient))) { RS_ACCESS_MASK rightsRequired; - + portMemSet(&rightsRequired, 0, sizeof(rightsRequired)); RS_ACCESS_MASK_ADD(&rightsRequired, RS_ACCESS_DUP_OBJECT); @@ -582,6 +582,50 @@ clientCopyResource_IMPL return _clientAllocResourceHelper(pClient, pServer, ¶ms, &pParams->hResourceDst); } +static +void +_refCleanupDependencies +( + RsResourceRef *pResourceRef +) +{ + RsResourceRef **ppIndepRef; + while (NULL != (ppIndepRef = multimapFirstItem(&pResourceRef->depBackRefMap))) + { + refRemoveDependant(*ppIndepRef, pResourceRef); + } +} + +static +void +_refCleanupDependants +( + RsResourceRef *pResourceRef +) +{ + RsResourceRef **ppDepRef; + while (NULL != (ppDepRef = multimapFirstItem(&pResourceRef->depRefMap))) + { + refRemoveDependant(pResourceRef, *ppDepRef); + } +} + +static +void +_refRemoveAllDependencies +( + RsResourceRef *pResourceRef +) +{ + _refCleanupDependencies(pResourceRef); + + if (pResourceRef->pDependantSession != NULL) + sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef); + + if (pResourceRef->pSession != NULL) + sessionRemoveDependant(pResourceRef->pSession, pResourceRef); +} + static NV_STATUS _clientAllocResourceHelper @@ -684,11 +728,7 @@ _clientAllocResourceHelper pOldContext = NULL; // First undo dependency tracking since it might access the resource - if (pResourceRef->pDependantSession != NULL) - sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef); - - if (pResourceRef->pSession != NULL) - sessionRemoveDependant(pResourceRef->pSession, pResourceRef); + _refRemoveAllDependencies(pResourceRef); portMemSet(¶ms, 0, sizeof(params)); portMemSet(&callContext, 0, sizeof(callContext)); @@ -718,38 +758,6 @@ _clientAllocResourceHelper return status; } -static -NV_STATUS -_refCleanupDependencies -( - RsResourceRef *pResourceRef -) -{ - RsResourceRef **ppIndepRef; - while (NULL != (ppIndepRef = multimapFirstItem(&pResourceRef->depBackRefMap))) - { - refRemoveDependant(*ppIndepRef, pResourceRef); - } - - return NV_OK; -} - -static -NV_STATUS -_refCleanupDependants -( - RsResourceRef *pResourceRef -) -{ - RsResourceRef **ppDepRef; - while (NULL != (ppDepRef = multimapFirstItem(&pResourceRef->depRefMap))) - { - refRemoveDependant(pResourceRef, *ppDepRef); - } - - return NV_OK; -} - NV_STATUS clientFreeResource_IMPL ( @@ -805,13 +813,7 @@ clientFreeResource_IMPL // Remove this resource as a dependency from other resources pResourceRef->bInvalidated = NV_TRUE; - _refCleanupDependencies(pResourceRef); - - if (pResourceRef->pDependantSession != NULL) - sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef); - - if (pResourceRef->pSession != NULL) - sessionRemoveDependant(pResourceRef->pSession, pResourceRef); + _refRemoveAllDependencies(pResourceRef); status = serverFreeResourceRpcUnderLock(pServer, pParams); NV_ASSERT(status == NV_OK); @@ -876,8 +878,8 @@ clientUnmapMemory_IMPL if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "hClient %x: Failed to unmap cpu mapping: hResource: %x error: 0x%x\n", - pClient->hClient, + NV_PRINTF(LEVEL_ERROR, "hClient %x: Failed to unmap cpu mapping: hResource: %x error: 0x%x\n", + pClient->hClient, pResourceRef->hResource, status); @@ -939,7 +941,7 @@ clientGenResourceHandle_IMPL } hFirst = hResource; - do + do { hResource = pClient->handleRangeStart + ((pClient->handleGenIdx++) % pClient->handleRangeSize); status = clientValidateNewResourceHandle(pClient, hResource, NV_FALSE); @@ -1091,8 +1093,8 @@ clientUnmapResourceRefMappings portMemSet(&lockInfo, 0, sizeof(lockInfo)); params.hClient = pClient->hClient; - params.hDevice = (pCpuMapping->pContextRef == NULL) - ? pClient->hClient + params.hDevice = (pCpuMapping->pContextRef == NULL) + ? pClient->hClient : pCpuMapping->pContextRef->hResource; params.hMemory = pResourceRef->hResource; params.pLinearAddress = pCpuMapping->pLinearAddress; @@ -1245,7 +1247,7 @@ _clientUnmapInterMappings pMapping = listHead(&pMapperRef->interMappings); while (pMapping != NULL) { - status = _unmapInterMapping(pCallContext->pServer, pClient, pMapperRef, + status = _unmapInterMapping(pCallContext->pServer, pClient, pMapperRef, pMapping, pLockInfo, &pCallContext->secInfo); if (status != NV_OK) { @@ -1284,7 +1286,7 @@ _clientUnmapInterBackRefMappings RsResourceRef *pMapperRef = pBackRefItem->pMapperRef; RsInterMapping *pMapping = pBackRefItem->pMapping; - status = _unmapInterMapping(pCallContext->pServer, pClient, pMapperRef, + status = _unmapInterMapping(pCallContext->pServer, pClient, pMapperRef, pMapping, pLockInfo, &pCallContext->secInfo); if (status != NV_OK) { @@ -1353,7 +1355,7 @@ clientValidateNewResourceHandle_IMPL ( RsClient *pClient, NvHandle hResource, - NvBool bRestrict + NvBool bRestrict ) { // @@ -1656,7 +1658,7 @@ clientRefIterNext pResourceRef = bUseIdx ? *pIt->idxIt.pValue : pIt->mapIt.pValue; if (bUseIdx || - ((pResourceRef == pIt->pScopeRef) || + ((pResourceRef == pIt->pScopeRef) || (refHasAncestor(pResourceRef, pIt->pScopeRef)))) { NvBool bMatch = NV_TRUE; diff --git a/src/nvidia/src/libraries/resserv/src/rs_resource.c b/src/nvidia/src/libraries/resserv/src/rs_resource.c index f8234a3dde..78402eeda3 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_resource.c +++ b/src/nvidia/src/libraries/resserv/src/rs_resource.c @@ -121,10 +121,10 @@ NV_STATUS resControlLookup_IMPL const struct NVOC_EXPORTED_METHOD_DEF **ppEntry ) { - const struct NVOC_EXPORTED_METHOD_DEF *pEntry; - NvU32 cmd = pRsParams->cmd; + const struct NVOC_EXPORTED_METHOD_DEF *pEntry; + NvU32 cmd = pRsParams->cmd; - *ppEntry = NULL; + *ppEntry = NULL; pEntry = objGetExportedMethodDef(staticCast(objFullyDerive(pResource), Dynamic), cmd); if (pEntry == NULL) @@ -212,14 +212,7 @@ resControl_IMPL { CONTROL_EXPORT_FNPTR pFunc = ((CONTROL_EXPORT_FNPTR) pEntry->pFunc); - if (pRsParams->flags & NVOS54_FLAGS_FINN_SERIALIZED) - { - status = pFunc(pDynamicObj, pCallContext->pDeserializedParams); - } - else - { - status = pFunc(pDynamicObj, pRsParams->pParams); - } + status = pFunc(pDynamicObj, pRsParams->pParams); } } @@ -801,15 +794,20 @@ refAddDependant RsResourceRef *pDependantRef ) { + NV_STATUS status; + // dependencies are implicit between a parent resource reference and child resource reference if (refHasAncestor(pDependantRef, pResourceRef)) return NV_OK; - indexAdd(&pDependantRef->depBackRefMap, pResourceRef->internalClassId, pResourceRef); + status = indexAdd(&pDependantRef->depBackRefMap, pResourceRef->internalClassId, pResourceRef); + if (status != NV_OK) + return status; + return indexAdd(&pResourceRef->depRefMap, pDependantRef->internalClassId, pDependantRef); } -NV_STATUS +void refRemoveDependant ( RsResourceRef *pResourceRef, @@ -817,7 +815,7 @@ refRemoveDependant ) { indexRemove(&pDependantRef->depBackRefMap, pResourceRef->internalClassId, pResourceRef); - return indexRemove(&pResourceRef->depRefMap, pDependantRef->internalClassId, pDependantRef); + indexRemove(&pResourceRef->depRefMap, pDependantRef->internalClassId, pDependantRef); } NvBool diff --git a/src/nvidia/src/libraries/resserv/src/rs_server.c b/src/nvidia/src/libraries/resserv/src/rs_server.c index 18dc2b62bb..7e51ea0630 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_server.c +++ b/src/nvidia/src/libraries/resserv/src/rs_server.c @@ -20,7 +20,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - + #define NVOC_RS_SERVER_H_PRIVATE_ACCESS_ALLOWED #include "nvlog_inc.h" #include "resserv/resserv.h" @@ -639,6 +639,7 @@ serverAllocResource RS_LOCK_INFO *pLockInfo; RsClient *pSecondClient = NULL; NvHandle hSecondClient; + CALL_CONTEXT callContext = {0}; if (!pServer->bConstructed) return NV_ERR_NOT_READY; @@ -661,6 +662,10 @@ serverAllocResource if (status == NV_OK) { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + serverDeserializeAllocDown(&callContext, pParams->externalClassId, &pParams->pAllocParams, &pParams->paramsSize, &pParams->allocFlags), + done); + if (bClientAlloc) { status = serverAllocClient(pServer, pParams); @@ -742,6 +747,10 @@ serverAllocResource } } + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, + serverSerializeAllocUp(&callContext, pParams->externalClassId, &pParams->pAllocParams, &pParams->paramsSize, &pParams->allocFlags)); + serverFreeSerializeStructures(&callContext, pParams->pAllocParams); + serverTopLock_Epilogue(pServer, topLockAccess, pLockInfo, &releaseFlags); // copyout as needed, being careful not to overwrite a useful status value @@ -3019,7 +3028,7 @@ serverAllocShareWithHalspecParent status = objCreateDynamicWithFlags(&pDynamic, pHalspecParent, (const NVOC_CLASS_INFO*)(const void*)pClassInfo, - flags); + flags); if (status != NV_OK) return status; @@ -3152,8 +3161,8 @@ serverSerializeCtrlDown ( CALL_CONTEXT *pCallContext, NvU32 cmd, - void *pParams, - NvU32 paramsSize, + void **ppParams, + NvU32 *pParamsSize, NvU32 *flags ) { @@ -3165,8 +3174,8 @@ serverDeserializeCtrlDown ( CALL_CONTEXT *pCallContext, NvU32 cmd, - void *pParams, - NvU32 paramsSize, + void **ppParams, + NvU32 *pParamsSize, NvU32 *flags ) { @@ -3178,8 +3187,8 @@ serverSerializeCtrlUp ( CALL_CONTEXT *pCallContext, NvU32 cmd, - void *pParams, - NvU32 paramsSize, + void **ppParams, + NvU32 *pParamsSize, NvU32 *flags ) { @@ -3191,8 +3200,60 @@ serverDeserializeCtrlUp ( CALL_CONTEXT *pCallContext, NvU32 cmd, - void *pParams, - NvU32 paramsSize, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverSerializeAllocDown +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverDeserializeAllocDown +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverSerializeAllocUp +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **ppParams, + NvU32 *pParamsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverDeserializeAllocUp +( + CALL_CONTEXT *pCallContext, + NvU32 classId, + void **pParams, + NvU32 *pParamsSize, NvU32 *flags ) { diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index 7677009732..376f5cd3ef 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -5,12 +5,15 @@ SRCS += generated/g_access_cntr_buffer_nvoc.c SRCS += generated/g_all_dcl_pb.c SRCS += generated/g_binary_api_nvoc.c SRCS += generated/g_bindata.c +SRCS += generated/g_ce_utils_nvoc.c SRCS += generated/g_channel_descendant_nvoc.c SRCS += generated/g_chips2halspec_nvoc.c SRCS += generated/g_chipset_nvoc.c SRCS += generated/g_client_nvoc.c SRCS += generated/g_client_resource_nvoc.c SRCS += generated/g_compute_instance_subscription_nvoc.c +SRCS += generated/g_conf_compute_api_nvoc.c +SRCS += generated/g_conf_compute_nvoc.c SRCS += generated/g_console_mem_nvoc.c SRCS += generated/g_context_dma_nvoc.c SRCS += generated/g_dbgbuffer_nvoc.c @@ -22,6 +25,7 @@ SRCS += generated/g_disp_inst_mem_nvoc.c SRCS += generated/g_disp_objs_nvoc.c SRCS += generated/g_disp_sf_user_nvoc.c SRCS += generated/g_dispsw_nvoc.c +SRCS += generated/g_egm_mem_nvoc.c SRCS += generated/g_eng_state_nvoc.c SRCS += generated/g_engines_pb.c SRCS += generated/g_event_buffer_nvoc.c @@ -124,6 +128,7 @@ SRCS += generated/g_os_nvoc.c SRCS += generated/g_p2p_api_nvoc.c SRCS += generated/g_phys_mem_nvoc.c SRCS += generated/g_platform_nvoc.c +SRCS += generated/g_platform_request_handler_nvoc.c SRCS += generated/g_prereq_tracker_nvoc.c SRCS += generated/g_profiler_v1_nvoc.c SRCS += generated/g_profiler_v2_nvoc.c @@ -138,6 +143,9 @@ SRCS += generated/g_rpc_iom.c SRCS += generated/g_rs_client_nvoc.c SRCS += generated/g_rs_resource_nvoc.c SRCS += generated/g_rs_server_nvoc.c +SRCS += generated/g_sec2_context_nvoc.c +SRCS += generated/g_sem_surf_nvoc.c +SRCS += generated/g_spdm_nvoc.c SRCS += generated/g_standard_mem_nvoc.c SRCS += generated/g_subdevice_diag_nvoc.c SRCS += generated/g_subdevice_nvoc.c @@ -165,6 +173,31 @@ SRCS += generated/g_virt_mem_mgr_nvoc.c SRCS += generated/g_virt_mem_range_nvoc.c SRCS += generated/g_virtual_mem_nvoc.c SRCS += generated/g_zbc_api_nvoc.c +SRCS += ../common/mbedtls/library/mbedtls_aes.c +SRCS += ../common/mbedtls/library/mbedtls_asn1parse.c +SRCS += ../common/mbedtls/library/mbedtls_asn1write.c +SRCS += ../common/mbedtls/library/mbedtls_base64.c +SRCS += ../common/mbedtls/library/mbedtls_bignum.c +SRCS += ../common/mbedtls/library/mbedtls_cipher.c +SRCS += ../common/mbedtls/library/mbedtls_cipher_wrap.c +SRCS += ../common/mbedtls/library/mbedtls_ecdh.c +SRCS += ../common/mbedtls/library/mbedtls_ecdsa.c +SRCS += ../common/mbedtls/library/mbedtls_ecp.c +SRCS += ../common/mbedtls/library/mbedtls_ecp_curves.c +SRCS += ../common/mbedtls/library/mbedtls_gcm.c +SRCS += ../common/mbedtls/library/mbedtls_hkdf.c +SRCS += ../common/mbedtls/library/mbedtls_md.c +SRCS += ../common/mbedtls/library/mbedtls_md_wrap.c +SRCS += ../common/mbedtls/library/mbedtls_oid.c +SRCS += ../common/mbedtls/library/mbedtls_pem.c +SRCS += ../common/mbedtls/library/mbedtls_pk.c +SRCS += ../common/mbedtls/library/mbedtls_pk_wrap.c +SRCS += ../common/mbedtls/library/mbedtls_pkparse.c +SRCS += ../common/mbedtls/library/mbedtls_sha256.c +SRCS += ../common/mbedtls/library/mbedtls_sha512.c +SRCS += ../common/mbedtls/library/mbedtls_x509.c +SRCS += ../common/mbedtls/library/mbedtls_x509_crt.c +SRCS += ../common/mbedtls/nvidia/nvrm_platform.c SRCS += ../common/shared/msgq/msgq.c SRCS += ../common/shared/nvstatus/nvstatus.c SRCS += ../common/src/nvSha256.c @@ -262,6 +295,14 @@ SRCS += arch/nvalloc/unix/src/rmobjexportimport.c SRCS += arch/nvalloc/unix/src/subdevice_ctrl_os_unix.c SRCS += arch/nvalloc/unix/src/unix_console.c SRCS += arch/nvalloc/unix/src/unix_intr.c +SRCS += arch/nvalloc/unix/src/vbioscall.c +SRCS += arch/nvalloc/unix/x86emu/debug.c +SRCS += arch/nvalloc/unix/x86emu/decode.c +SRCS += arch/nvalloc/unix/x86emu/fpu.c +SRCS += arch/nvalloc/unix/x86emu/ops.c +SRCS += arch/nvalloc/unix/x86emu/ops2.c +SRCS += arch/nvalloc/unix/x86emu/prim_ops.c +SRCS += arch/nvalloc/unix/x86emu/sys.c SRCS += interface/deprecated/rmapi_deprecated_allocmemory.c SRCS += interface/deprecated/rmapi_deprecated_control.c SRCS += interface/deprecated/rmapi_deprecated_misc.c @@ -333,6 +374,12 @@ SRCS += src/kernel/gpu/ce/kernel_ce.c SRCS += src/kernel/gpu/ce/kernel_ce_context.c SRCS += src/kernel/gpu/ce/kernel_ce_ctrl.c SRCS += src/kernel/gpu/ce/kernel_ce_shared.c +SRCS += src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c +SRCS += src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c +SRCS += src/kernel/gpu/conf_compute/ccsl.c +SRCS += src/kernel/gpu/conf_compute/conf_compute.c +SRCS += src/kernel/gpu/conf_compute/conf_compute_api.c +SRCS += src/kernel/gpu/conf_compute/conf_compute_keystore.c SRCS += src/kernel/gpu/deferred_api.c SRCS += src/kernel/gpu/device.c SRCS += src/kernel/gpu/device_ctrl.c @@ -347,7 +394,7 @@ SRCS += src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c SRCS += src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c SRCS += src/kernel/gpu/disp/disp_objs.c SRCS += src/kernel/gpu/disp/disp_sf_user.c -SRCS += src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c +SRCS += src/kernel/gpu/disp/head/arch/v04/kernel_head_0400.c SRCS += src/kernel/gpu/disp/head/kernel_head.c SRCS += src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c SRCS += src/kernel/gpu/disp/inst_mem/disp_inst_mem.c @@ -366,13 +413,13 @@ SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga100.c SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c SRCS += src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c SRCS += src/kernel/gpu/falcon/kernel_falcon.c +SRCS += src/kernel/gpu/falcon/kernel_falcon_ctrl.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga100.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga10b.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga102.c SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c -SRCS += src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c SRCS += src/kernel/gpu/fifo/arch/pascal/kernel_fifo_gp102.c @@ -380,7 +427,6 @@ SRCS += src/kernel/gpu/fifo/arch/turing/kernel_fifo_tu102.c SRCS += src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c SRCS += src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c SRCS += src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c -SRCS += src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c SRCS += src/kernel/gpu/fifo/channel_descendant.c SRCS += src/kernel/gpu/fifo/kernel_channel.c SRCS += src/kernel/gpu/fifo/kernel_channel_group.c @@ -454,6 +500,7 @@ SRCS += src/kernel/gpu/intr/arch/turing/intr_tu102.c SRCS += src/kernel/gpu/intr/intr.c SRCS += src/kernel/gpu/intr/intr_service.c SRCS += src/kernel/gpu/intr/swintr.c +SRCS += src/kernel/gpu/kern_gpu_power.c SRCS += src/kernel/gpu/mc/arch/ampere/kernel_mc_ga100.c SRCS += src/kernel/gpu/mc/arch/maxwell/kernel_mc_gm107.c SRCS += src/kernel/gpu/mc/kernel_mc.c @@ -473,6 +520,8 @@ SRCS += src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c SRCS += src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c SRCS += src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102_base.c SRCS += src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c +SRCS += src/kernel/gpu/mem_mgr/ce_utils.c +SRCS += src/kernel/gpu/mem_mgr/channel_utils.c SRCS += src/kernel/gpu/mem_mgr/context_dma.c SRCS += src/kernel/gpu/mem_mgr/dma.c SRCS += src/kernel/gpu/mem_mgr/fbsr.c @@ -494,6 +543,7 @@ SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c +SRCS += src/kernel/gpu/mem_mgr/sem_surf.c SRCS += src/kernel/gpu/mem_mgr/vaspace_api.c SRCS += src/kernel/gpu/mem_mgr/virt_mem_allocator.c SRCS += src/kernel/gpu/mem_mgr/virt_mem_allocator_vgpu.c @@ -579,6 +629,10 @@ SRCS += src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga100.c SRCS += src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga102.c SRCS += src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c SRCS += src/kernel/gpu/sec2/kernel_sec2.c +SRCS += src/kernel/gpu/sec2/sec2_context.c +SRCS += src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c +SRCS += src/kernel/gpu/spdm/arch/hopper/spdm_module.c +SRCS += src/kernel/gpu/spdm/spdm.c SRCS += src/kernel/gpu/subdevice/generic_engine.c SRCS += src/kernel/gpu/subdevice/subdevice.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c @@ -612,6 +666,7 @@ SRCS += src/kernel/gpu_mgr/gpu_mgr.c SRCS += src/kernel/gpu_mgr/gpu_mgr_sli.c SRCS += src/kernel/mem_mgr/console_mem.c SRCS += src/kernel/mem_mgr/ctx_buf_pool.c +SRCS += src/kernel/mem_mgr/egm_mem.c SRCS += src/kernel/mem_mgr/fabric_vaspace.c SRCS += src/kernel/mem_mgr/fla_mem.c SRCS += src/kernel/mem_mgr/gpu_vaspace.c @@ -651,6 +706,8 @@ SRCS += src/kernel/platform/nbsi/nbsi_init.c SRCS += src/kernel/platform/nbsi/nbsi_osrg.c SRCS += src/kernel/platform/p2p/p2p_caps.c SRCS += src/kernel/platform/platform.c +SRCS += src/kernel/platform/platform_request_handler.c +SRCS += src/kernel/platform/platform_request_handler_ctrl.c SRCS += src/kernel/platform/sli/sli.c SRCS += src/kernel/power/gpu_boost_mgr.c SRCS += src/kernel/rmapi/alloc_free.c @@ -701,9 +758,60 @@ SRCS += src/libraries/containers/list.c SRCS += src/libraries/containers/map.c SRCS += src/libraries/containers/multimap.c SRCS += src/libraries/containers/queue.c +SRCS += src/libraries/containers/ringbuf.c +SRCS += src/libraries/containers/vector.c SRCS += src/libraries/eventbuffer/eventbufferproducer.c SRCS += src/libraries/fnv_hash/fnv_hash.c SRCS += src/libraries/ioaccess/ioaccess.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c +SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/cipher/libspdm_aead_aes_gcm.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hash/libspdm_sha.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/hmac/libspdm_hmac_sha.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/kdf/libspdm_hkdf_sha.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_ec.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/pk/libspdm_x509.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/cryptlib_mbedtls/rand/libspdm_rand.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c +SRCS += src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_crypt_null.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_debuglib.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_malloclib.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_memlib.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_rng.c SRCS += src/libraries/mmu/gmmu_fmt.c SRCS += src/libraries/mmu/mmu_fmt.c SRCS += src/libraries/mmu/mmu_walk.c diff --git a/version.mk b/version.mk index 805758cc20..e6665a1191 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 530.41.03 +NVIDIA_VERSION = 535.43.02 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))